From 32fd4a9ca52b51ab28abdd389ba9c74dd9bd1d6b Mon Sep 17 00:00:00 2001 From: Gerardo Marx Date: Thu, 16 Jul 2026 13:06:31 -0600 Subject: [PATCH] Code working with ti functions --- Readme.md | 152 + gpio_bitfield_cpu1/.ccsproject | 12 + gpio_bitfield_cpu1/.clangd | 8 + gpio_bitfield_cpu1/.cproject | 190 + gpio_bitfield_cpu1/.project | 41 + .../org.eclipse.cdt.codan.core.prefs | 3 + .../org.eclipse.core.resources.prefs | 9 + gpio_bitfield_cpu1/2837xD_FLASH_lnk_cpu1.cmd | 176 + gpio_bitfield_cpu1/2837xD_RAM_lnk_cpu1.cmd | 141 + ...D_CodeStartBranch.asm.FFF74FBFA9E1DF65.idx | Bin 0 -> 1020 bytes ..._GlobalVariableDefs.c.9475B106EEC7EB3C.idx | Bin 0 -> 11210 bytes .../index/F2837xD_Gpio.c.9A61E7A409D5CE6F.idx | Bin 0 -> 4690 bytes .../F2837xD_SysCtrl.c.56FB42F36D55397C.idx | Bin 0 -> 22762 bytes .../F2837xD_usDelay.asm.7C96C1CDAC6C975F.idx | Bin 0 -> 1032 bytes .../index/device.c.54B6CFC62F397228.idx | Bin 0 -> 11800 bytes .../index/device.h.41952FC88751F598.idx | Bin 0 -> 3206 bytes .../index/driverlib.h.0FB4C8ADA96DE950.idx | Bin 0 -> 856 bytes ...driverlib_main_cpu1.c.F4B0E06E433FAC03.idx | Bin 0 -> 580 bytes ..._bitfield_main_cpu1.c.676B95E1C3FBD8C5.idx | Bin 0 -> 1628 bytes .../CPU1_RAM/.clangd/compile_commands.json | 37 + .../CPU1_RAM/F2837xD_GlobalVariableDefs.d | 156 + .../CPU1_RAM/F2837xD_GlobalVariableDefs.obj | Bin 0 -> 536432 bytes gpio_bitfield_cpu1/CPU1_RAM/F2837xD_Gpio.d | 201 + gpio_bitfield_cpu1/CPU1_RAM/F2837xD_Gpio.obj | Bin 0 -> 131832 bytes gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.d | 201 + .../CPU1_RAM/F2837xD_SysCtrl.obj | Bin 0 -> 88864 bytes .../CPU1_RAM/F2837xD_usDelay.obj | Bin 0 -> 2488 bytes gpio_bitfield_cpu1/CPU1_RAM/ccsObjs.opt | 11 + .../device/F2837xD_CodeStartBranch.obj | Bin 0 -> 3800 bytes gpio_bitfield_cpu1/CPU1_RAM/device/device.d | 267 + gpio_bitfield_cpu1/CPU1_RAM/device/device.obj | Bin 0 -> 28492 bytes .../CPU1_RAM/device/subdir_rules.mk | 18 + .../CPU1_RAM/device/subdir_vars.mk | 38 + .../CPU1_RAM/gpio_bitfield_cpu1.map | 556 ++ .../CPU1_RAM/gpio_bitfield_cpu1.out | Bin 0 -> 442712 bytes .../CPU1_RAM/gpio_bitfield_cpu1_linkInfo.xml | 6138 ++++++++++++++ .../CPU1_RAM/gpio_bitfield_main_cpu1.d | 435 + .../CPU1_RAM/gpio_bitfield_main_cpu1.obj | Bin 0 -> 100584 bytes gpio_bitfield_cpu1/CPU1_RAM/makefile | 154 + gpio_bitfield_cpu1/CPU1_RAM/objects.mk | 8 + gpio_bitfield_cpu1/CPU1_RAM/sources.mk | 110 + gpio_bitfield_cpu1/CPU1_RAM/subdir_rules.mk | 18 + gpio_bitfield_cpu1/CPU1_RAM/subdir_vars.mk | 63 + .../F2837xD_GlobalVariableDefs.c | 961 +++ gpio_bitfield_cpu1/F2837xD_Gpio.c | 506 ++ .../F2837xD_Headers_nonBIOS_cpu1.cmd | 247 + gpio_bitfield_cpu1/F2837xD_SysCtrl.c | 1363 +++ gpio_bitfield_cpu1/F2837xD_usDelay.asm | 109 + .../device/F2837xD_CodeStartBranch.asm | 112 + gpio_bitfield_cpu1/device/device.c | 706 ++ gpio_bitfield_cpu1/device/device.h | 394 + gpio_bitfield_cpu1/device/driverlib.h | 87 + gpio_bitfield_cpu1/device/driverlib/adc.c | 342 + gpio_bitfield_cpu1/device/driverlib/adc.h | 2098 +++++ gpio_bitfield_cpu1/device/driverlib/asysctl.c | 43 + gpio_bitfield_cpu1/device/driverlib/asysctl.h | 160 + gpio_bitfield_cpu1/device/driverlib/can.c | 1122 +++ gpio_bitfield_cpu1/device/driverlib/can.h | 1924 +++++ .../device/driverlib/ccs/Debug/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Debug/driverlib_coff.lib | Bin 0 -> 575952 bytes .../driverlib/ccs/Debug/driverlib_eabi.lib | Bin 0 -> 1003104 bytes .../driverlib/ccs/Release/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Release/driverlib_coff.lib | Bin 0 -> 375766 bytes .../driverlib/ccs/Release/driverlib_eabi.lib | Bin 0 -> 654036 bytes .../driverlib/ccs/driverlib.projectspec | 46 + gpio_bitfield_cpu1/device/driverlib/cla.c | 89 + gpio_bitfield_cpu1/device/driverlib/cla.h | 984 +++ gpio_bitfield_cpu1/device/driverlib/clb.c | 145 + gpio_bitfield_cpu1/device/driverlib/clb.h | 1290 +++ gpio_bitfield_cpu1/device/driverlib/cmpss.c | 223 + gpio_bitfield_cpu1/device/driverlib/cmpss.h | 1325 +++ gpio_bitfield_cpu1/device/driverlib/cpu.h | 172 + .../device/driverlib/cputimer.c | 61 + .../device/driverlib/cputimer.h | 509 ++ gpio_bitfield_cpu1/device/driverlib/dac.c | 93 + gpio_bitfield_cpu1/device/driverlib/dac.h | 604 ++ gpio_bitfield_cpu1/device/driverlib/dcsm.c | 377 + gpio_bitfield_cpu1/device/driverlib/dcsm.h | 669 ++ gpio_bitfield_cpu1/device/driverlib/debug.h | 91 + gpio_bitfield_cpu1/device/driverlib/dma.c | 370 + gpio_bitfield_cpu1/device/driverlib/dma.h | 1171 +++ .../driver_inclusive_terminology_mapping.h | 109 + gpio_bitfield_cpu1/device/driverlib/ecap.c | 61 + gpio_bitfield_cpu1/device/driverlib/ecap.h | 1164 +++ gpio_bitfield_cpu1/device/driverlib/emif.c | 46 + gpio_bitfield_cpu1/device/driverlib/emif.h | 1369 +++ gpio_bitfield_cpu1/device/driverlib/epwm.c | 363 + gpio_bitfield_cpu1/device/driverlib/epwm.h | 7496 +++++++++++++++++ gpio_bitfield_cpu1/device/driverlib/eqep.c | 149 + gpio_bitfield_cpu1/device/driverlib/eqep.h | 1691 ++++ gpio_bitfield_cpu1/device/driverlib/flash.c | 175 + gpio_bitfield_cpu1/device/driverlib/flash.h | 1671 ++++ gpio_bitfield_cpu1/device/driverlib/gpio.c | 489 ++ gpio_bitfield_cpu1/device/driverlib/gpio.h | 1047 +++ gpio_bitfield_cpu1/device/driverlib/hrpwm.c | 47 + gpio_bitfield_cpu1/device/driverlib/hrpwm.h | 1657 ++++ .../driverlib/hw_reg_inclusive_terminology.h | 29 + gpio_bitfield_cpu1/device/driverlib/i2c.c | 351 + gpio_bitfield_cpu1/device/driverlib/i2c.h | 1386 +++ .../device/driverlib/inc/hw_adc.h | 911 ++ .../device/driverlib/inc/hw_asysctl.h | 145 + .../device/driverlib/inc/hw_can.h | 514 ++ .../device/driverlib/inc/hw_cla.h | 241 + .../device/driverlib/inc/hw_clb.h | 661 ++ .../device/driverlib/inc/hw_clbxbar.h | 1272 +++ .../device/driverlib/inc/hw_cmpss.h | 235 + .../device/driverlib/inc/hw_cputimer.h | 112 + .../device/driverlib/inc/hw_dac.h | 122 + .../device/driverlib/inc/hw_dcsm.h | 442 + .../device/driverlib/inc/hw_dma.h | 165 + .../device/driverlib/inc/hw_ecap.h | 157 + .../device/driverlib/inc/hw_emif.h | 259 + .../device/driverlib/inc/hw_epwm.h | 1050 +++ .../device/driverlib/inc/hw_epwmxbar.h | 1192 +++ .../device/driverlib/inc/hw_eqep.h | 225 + .../device/driverlib/inc/hw_flash.h | 286 + .../device/driverlib/inc/hw_gpio.h | 4018 +++++++++ .../device/driverlib/inc/hw_hic.h | 344 + .../device/driverlib/inc/hw_hrpwm.h | 1058 +++ .../device/driverlib/inc/hw_i2c.h | 208 + .../device/driverlib/inc/hw_inputxbar.h | 92 + .../device/driverlib/inc/hw_ints.h | 212 + .../device/driverlib/inc/hw_ipc.h | 323 + .../device/driverlib/inc/hw_mcbsp.h | 286 + .../device/driverlib/inc/hw_memcfg.h | 870 ++ .../device/driverlib/inc/hw_memmap.h | 208 + .../device/driverlib/inc/hw_nmi.h | 134 + .../device/driverlib/inc/hw_otp.h | 63 + .../device/driverlib/inc/hw_outputxbar.h | 1340 +++ .../device/driverlib/inc/hw_pie.h | 636 ++ .../device/driverlib/inc/hw_sci.h | 209 + .../device/driverlib/inc/hw_sdfm.h | 431 + .../device/driverlib/inc/hw_spi.h | 157 + .../device/driverlib/inc/hw_sysctl.h | 1428 ++++ .../device/driverlib/inc/hw_types.h | 166 + .../device/driverlib/inc/hw_upp.h | 306 + .../device/driverlib/inc/hw_usb.h | 4614 ++++++++++ .../device/driverlib/inc/hw_xbar.h | 271 + .../device/driverlib/inc/hw_xint.h | 108 + .../device/driverlib/interrupt.c | 425 + .../device/driverlib/interrupt.h | 497 ++ gpio_bitfield_cpu1/device/driverlib/ipc.c | 445 + gpio_bitfield_cpu1/device/driverlib/ipc.h | 880 ++ gpio_bitfield_cpu1/device/driverlib/mcbsp.c | 1621 ++++ gpio_bitfield_cpu1/device/driverlib/mcbsp.h | 3340 ++++++++ gpio_bitfield_cpu1/device/driverlib/memcfg.c | 701 ++ gpio_bitfield_cpu1/device/driverlib/memcfg.h | 1266 +++ gpio_bitfield_cpu1/device/driverlib/pin_map.h | 894 ++ .../device/driverlib/pin_map_legacy.h | 95 + gpio_bitfield_cpu1/device/driverlib/sci.c | 421 + gpio_bitfield_cpu1/device/driverlib/sci.h | 1646 ++++ gpio_bitfield_cpu1/device/driverlib/sdfm.c | 188 + gpio_bitfield_cpu1/device/driverlib/sdfm.h | 1178 +++ gpio_bitfield_cpu1/device/driverlib/spi.c | 661 ++ gpio_bitfield_cpu1/device/driverlib/spi.h | 1743 ++++ gpio_bitfield_cpu1/device/driverlib/sysctl.c | 1469 ++++ gpio_bitfield_cpu1/device/driverlib/sysctl.h | 3531 ++++++++ gpio_bitfield_cpu1/device/driverlib/upp.c | 298 + gpio_bitfield_cpu1/device/driverlib/upp.h | 1574 ++++ gpio_bitfield_cpu1/device/driverlib/usb.c | 4018 +++++++++ gpio_bitfield_cpu1/device/driverlib/usb.h | 560 ++ gpio_bitfield_cpu1/device/driverlib/version.c | 54 + gpio_bitfield_cpu1/device/driverlib/version.h | 101 + gpio_bitfield_cpu1/device/driverlib/xbar.c | 255 + gpio_bitfield_cpu1/device/driverlib/xbar.h | 1294 +++ gpio_bitfield_cpu1/gpio_bitfield_main_cpu1.c | 57 + .../targetConfigs/TMS320F28377D.ccxml | 22 + gpio_bitfield_cpu1/targetConfigs/readme.txt | 9 + gpio_driverlib_cpu2/.ccsproject | 12 + gpio_driverlib_cpu2/.clangd | 8 + gpio_driverlib_cpu2/.cproject | 185 + gpio_driverlib_cpu2/.project | 33 + .../org.eclipse.cdt.codan.core.prefs | 3 + .../org.eclipse.core.resources.prefs | 9 + gpio_driverlib_cpu2/2837xD_FLASH_lnk_cpu2.cmd | 148 + gpio_driverlib_cpu2/2837xD_RAM_lnk_cpu2.cmd | 104 + ...D_CodeStartBranch.asm.12FC8C33CB659405.idx | Bin 0 -> 1016 bytes .../index/_stdint.h.269335DDD01ACAF0.idx | Bin 0 -> 1424 bytes .../index/_stdint.h.7734A66F203095C8.idx | Bin 0 -> 1564 bytes .../index/_stdint40.h.867E57579EB83AFB.idx | Bin 0 -> 248 bytes .../index/_ti_config.h.B258754A245C49A8.idx | Bin 0 -> 436 bytes .../index/_types.h.CAEEFA4995D439EF.idx | Bin 0 -> 3434 bytes .../index/_types.h.DA467FFD6DBAEA91.idx | Bin 0 -> 3554 bytes .../clangd/index/adc.h.E519F935EB5F4CE6.idx | Bin 0 -> 32078 bytes .../index/asysctl.h.738EE6FD4747F368.idx | Bin 0 -> 1178 bytes .../clangd/index/can.h.4CBCD3766571473F.idx | Bin 0 -> 184 bytes .../clangd/index/cdefs.h.EC7EB816822D7001.idx | Bin 0 -> 3218 bytes .../clangd/index/cla.h.ACD16ADC58C2BB7D.idx | Bin 0 -> 1484 bytes .../clangd/index/clb.h.0A665CC508A5A036.idx | Bin 0 -> 26596 bytes .../clangd/index/cmpss.h.44349D1312E625EE.idx | Bin 0 -> 12618 bytes .../clangd/index/cpu.h.F8701109AD01AD40.idx | Bin 0 -> 824 bytes .../index/cputimer.h.1F7F79EE0F170D39.idx | Bin 0 -> 188 bytes .../clangd/index/dac.h.4D3384276E2A5C5E.idx | Bin 0 -> 6428 bytes .../clangd/index/dcsm.h.095A7773A0730C87.idx | Bin 0 -> 8958 bytes .../clangd/index/debug.h.D983B7242F0626AB.idx | Bin 0 -> 556 bytes .../index/device.c.A7AA6765925BA603.idx | Bin 0 -> 5964 bytes .../index/device.h.7B29A1EE1F525C86.idx | Bin 0 -> 2576 bytes .../clangd/index/dma.h.9D5A0793FF04031F.idx | Bin 0 -> 18698 bytes ...terminology_mapping.h.39CC836B6A3C1A3E.idx | Bin 0 -> 1450 bytes .../index/driverlib.h.5241F9368A7F4655.idx | Bin 0 -> 852 bytes .../clangd/index/ecap.h.961EB755953DA208.idx | Bin 0 -> 12910 bytes .../clangd/index/emif.h.BA5BDF1658E44C3E.idx | Bin 0 -> 16942 bytes .../clangd/index/epwm.h.3D2DFB06B4DF194C.idx | Bin 0 -> 94600 bytes .../clangd/index/eqep.h.02C8CE3D990E0050.idx | Bin 0 -> 18694 bytes .../clangd/index/flash.h.647D30F719902AE3.idx | Bin 0 -> 18684 bytes .../clangd/index/gpio.h.1092B3E5A67E50D1.idx | Bin 0 -> 12160 bytes ...driverlib_main_cpu2.c.67C6948D8AC654E7.idx | Bin 0 -> 604 bytes .../clangd/index/hrpwm.h.C1A2624C7809837C.idx | Bin 0 -> 19702 bytes .../index/hw_adc.h.98EA396AAD9DB0F8.idx | Bin 0 -> 11686 bytes .../index/hw_asysctl.h.6BEC768D9E461FA5.idx | Bin 0 -> 1174 bytes .../index/hw_cla.h.3FB6A75742A9F921.idx | Bin 0 -> 2400 bytes .../index/hw_clb.h.53C8F7671D564C31.idx | Bin 0 -> 8768 bytes .../index/hw_clbxbar.h.BAC502BD359E2501.idx | Bin 0 -> 20206 bytes .../index/hw_cmpss.h.1F121378400A79E1.idx | Bin 0 -> 2198 bytes .../index/hw_dac.h.8340D93FCBD6285D.idx | Bin 0 -> 764 bytes .../index/hw_dcsm.h.7004B82899E7F76A.idx | Bin 0 -> 6710 bytes .../index/hw_dma.h.03CAC36E53F7B443.idx | Bin 0 -> 1600 bytes .../index/hw_ecap.h.AA1FA7CD26AE7175.idx | Bin 0 -> 1740 bytes .../index/hw_emif.h.7360F5A77CD3542C.idx | Bin 0 -> 3224 bytes .../index/hw_epwm.h.91B42B1E43EC138A.idx | Bin 0 -> 14692 bytes .../index/hw_epwmxbar.h.1DB61B86D667E2D6.idx | Bin 0 -> 20194 bytes .../index/hw_eqep.h.4B417234E5F1F8A7.idx | Bin 0 -> 2980 bytes .../index/hw_flash.h.0D3F6EA09BE0112A.idx | Bin 0 -> 2538 bytes .../index/hw_gpio.h.25BC6F0CEA046CD8.idx | Bin 0 -> 80286 bytes .../index/hw_hrpwm.h.5207EFB2BD1D4354.idx | Bin 0 -> 14692 bytes .../index/hw_i2c.h.7F6CC3FCBEA2F327.idx | Bin 0 -> 2132 bytes .../index/hw_inputxbar.h.AE44D51A98000428.idx | Bin 0 -> 908 bytes .../index/hw_ints.h.12E7A906946E97E9.idx | Bin 0 -> 3626 bytes .../index/hw_ipc.h.F1C28A8A3F99F2C6.idx | Bin 0 -> 4558 bytes .../index/hw_mcbsp.h.4696A07EEAA97272.idx | Bin 0 -> 3470 bytes .../index/hw_memcfg.h.68C2AA9BEEF9C297.idx | Bin 0 -> 10302 bytes .../index/hw_memmap.h.6954F579A4F9153D.idx | Bin 0 -> 3940 bytes .../index/hw_nmi.h.A8AF2163556B90D0.idx | Bin 0 -> 1320 bytes .../index/hw_otp.h.79F263D4926CA8B4.idx | Bin 0 -> 374 bytes .../hw_outputxbar.h.36517E226CC8DA79.idx | Bin 0 -> 21104 bytes ...clusive_terminology.h.4A63738FFC69C437.idx | Bin 0 -> 412 bytes .../index/hw_sci.h.8A0443B5BC315791.idx | Bin 0 -> 2008 bytes .../index/hw_sdfm.h.2985C998AC8213E9.idx | Bin 0 -> 4462 bytes .../index/hw_spi.h.AC453C0F657BE042.idx | Bin 0 -> 1458 bytes .../index/hw_sysctl.h.CCCF1E1CE0DE5ADE.idx | Bin 0 -> 17292 bytes .../index/hw_types.h.4E48A9852A3C6224.idx | Bin 0 -> 920 bytes .../index/hw_upp.h.D52237F873383366.idx | Bin 0 -> 3116 bytes .../index/hw_xbar.h.58F56177FA3F16EF.idx | Bin 0 -> 4562 bytes .../index/hw_xint.h.9C59935F074A8FD1.idx | Bin 0 -> 720 bytes .../clangd/index/i2c.h.5F2551596C1F8E5A.idx | Bin 0 -> 18658 bytes .../index/interrupt.h.45051B5A4426F075.idx | Bin 0 -> 190 bytes .../clangd/index/ipc.h.03A3F16C4A72C88B.idx | Bin 0 -> 13496 bytes .../index/linkage.h.13BB6EDDE8E2FF5F.idx | Bin 0 -> 334 bytes .../clangd/index/mcbsp.h.61C109C74F5CFF8C.idx | Bin 0 -> 42164 bytes .../index/memcfg.h.39A2E88995CA1A21.idx | Bin 0 -> 13270 bytes .../index/pin_map.h.F7B7C0A83F9D6974.idx | Bin 0 -> 16836 bytes .../pin_map_legacy.h.A4E8FABDF32673B0.idx | Bin 0 -> 694 bytes .../clangd/index/sci.h.E64424C04B59AFEC.idx | Bin 0 -> 19952 bytes .../clangd/index/sdfm.h.F6782F71CD95D796.idx | Bin 0 -> 14168 bytes .../clangd/index/spi.h.B44947D573F24C04.idx | Bin 0 -> 19926 bytes .../index/stdbool.h.3E82B883304EF4F5.idx | Bin 0 -> 358 bytes .../index/stdint.h.9A63194999B11C70.idx | Bin 0 -> 1902 bytes .../index/stdint.h.F1B42414AC7C7BEF.idx | Bin 0 -> 326 bytes .../index/sysctl.h.FBC41315038F0015.idx | Bin 0 -> 57974 bytes .../clangd/index/upp.h.87E2CC02B09631C6.idx | Bin 0 -> 18484 bytes .../index/version.h.53889B59D65786E6.idx | Bin 0 -> 592 bytes .../clangd/index/xbar.h.219917B2A4786F17.idx | Bin 0 -> 37832 bytes .../CPU2_RAM/.clangd/compile_commands.json | 17 + gpio_driverlib_cpu2/CPU2_RAM/ccsObjs.opt | 6 + .../device/F2837xD_CodeStartBranch.obj | Bin 0 -> 3804 bytes gpio_driverlib_cpu2/CPU2_RAM/device/device.d | 267 + .../CPU2_RAM/device/device.obj | Bin 0 -> 16916 bytes .../CPU2_RAM/device/subdir_rules.mk | 18 + .../CPU2_RAM/device/subdir_vars.mk | 38 + .../CPU2_RAM/gpio_driverlib_cpu2.map | 273 + .../CPU2_RAM/gpio_driverlib_cpu2.out | Bin 0 -> 26304 bytes .../CPU2_RAM/gpio_driverlib_cpu2_linkInfo.xml | 2585 ++++++ .../CPU2_RAM/gpio_driverlib_main_cpu2.d | 267 + .../CPU2_RAM/gpio_driverlib_main_cpu2.obj | Bin 0 -> 6784 bytes gpio_driverlib_cpu2/CPU2_RAM/makefile | 149 + gpio_driverlib_cpu2/CPU2_RAM/objects.mk | 8 + gpio_driverlib_cpu2/CPU2_RAM/sources.mk | 110 + gpio_driverlib_cpu2/CPU2_RAM/subdir_rules.mk | 12 + gpio_driverlib_cpu2/CPU2_RAM/subdir_vars.mk | 30 + .../device/F2837xD_CodeStartBranch.asm | 112 + gpio_driverlib_cpu2/device/device.c | 706 ++ gpio_driverlib_cpu2/device/device.h | 394 + gpio_driverlib_cpu2/device/driverlib.h | 87 + gpio_driverlib_cpu2/device/driverlib/adc.c | 342 + gpio_driverlib_cpu2/device/driverlib/adc.h | 2098 +++++ .../device/driverlib/asysctl.c | 43 + .../device/driverlib/asysctl.h | 160 + gpio_driverlib_cpu2/device/driverlib/can.c | 1122 +++ gpio_driverlib_cpu2/device/driverlib/can.h | 1924 +++++ .../device/driverlib/ccs/Debug/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Debug/driverlib_coff.lib | Bin 0 -> 575952 bytes .../driverlib/ccs/Debug/driverlib_eabi.lib | Bin 0 -> 1003104 bytes .../driverlib/ccs/Release/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Release/driverlib_coff.lib | Bin 0 -> 375766 bytes .../driverlib/ccs/Release/driverlib_eabi.lib | Bin 0 -> 654036 bytes .../driverlib/ccs/driverlib.projectspec | 46 + gpio_driverlib_cpu2/device/driverlib/cla.c | 89 + gpio_driverlib_cpu2/device/driverlib/cla.h | 984 +++ gpio_driverlib_cpu2/device/driverlib/clb.c | 145 + gpio_driverlib_cpu2/device/driverlib/clb.h | 1290 +++ gpio_driverlib_cpu2/device/driverlib/cmpss.c | 223 + gpio_driverlib_cpu2/device/driverlib/cmpss.h | 1325 +++ gpio_driverlib_cpu2/device/driverlib/cpu.h | 172 + .../device/driverlib/cputimer.c | 61 + .../device/driverlib/cputimer.h | 509 ++ gpio_driverlib_cpu2/device/driverlib/dac.c | 93 + gpio_driverlib_cpu2/device/driverlib/dac.h | 604 ++ gpio_driverlib_cpu2/device/driverlib/dcsm.c | 377 + gpio_driverlib_cpu2/device/driverlib/dcsm.h | 669 ++ gpio_driverlib_cpu2/device/driverlib/debug.h | 91 + gpio_driverlib_cpu2/device/driverlib/dma.c | 370 + gpio_driverlib_cpu2/device/driverlib/dma.h | 1171 +++ .../driver_inclusive_terminology_mapping.h | 109 + gpio_driverlib_cpu2/device/driverlib/ecap.c | 61 + gpio_driverlib_cpu2/device/driverlib/ecap.h | 1164 +++ gpio_driverlib_cpu2/device/driverlib/emif.c | 46 + gpio_driverlib_cpu2/device/driverlib/emif.h | 1369 +++ gpio_driverlib_cpu2/device/driverlib/epwm.c | 363 + gpio_driverlib_cpu2/device/driverlib/epwm.h | 7496 +++++++++++++++++ gpio_driverlib_cpu2/device/driverlib/eqep.c | 149 + gpio_driverlib_cpu2/device/driverlib/eqep.h | 1691 ++++ gpio_driverlib_cpu2/device/driverlib/flash.c | 175 + gpio_driverlib_cpu2/device/driverlib/flash.h | 1671 ++++ gpio_driverlib_cpu2/device/driverlib/gpio.c | 489 ++ gpio_driverlib_cpu2/device/driverlib/gpio.h | 1047 +++ gpio_driverlib_cpu2/device/driverlib/hrpwm.c | 47 + gpio_driverlib_cpu2/device/driverlib/hrpwm.h | 1657 ++++ .../driverlib/hw_reg_inclusive_terminology.h | 29 + gpio_driverlib_cpu2/device/driverlib/i2c.c | 351 + gpio_driverlib_cpu2/device/driverlib/i2c.h | 1386 +++ .../device/driverlib/inc/hw_adc.h | 911 ++ .../device/driverlib/inc/hw_asysctl.h | 145 + .../device/driverlib/inc/hw_can.h | 514 ++ .../device/driverlib/inc/hw_cla.h | 241 + .../device/driverlib/inc/hw_clb.h | 661 ++ .../device/driverlib/inc/hw_clbxbar.h | 1272 +++ .../device/driverlib/inc/hw_cmpss.h | 235 + .../device/driverlib/inc/hw_cputimer.h | 112 + .../device/driverlib/inc/hw_dac.h | 122 + .../device/driverlib/inc/hw_dcsm.h | 442 + .../device/driverlib/inc/hw_dma.h | 165 + .../device/driverlib/inc/hw_ecap.h | 157 + .../device/driverlib/inc/hw_emif.h | 259 + .../device/driverlib/inc/hw_epwm.h | 1050 +++ .../device/driverlib/inc/hw_epwmxbar.h | 1192 +++ .../device/driverlib/inc/hw_eqep.h | 225 + .../device/driverlib/inc/hw_flash.h | 286 + .../device/driverlib/inc/hw_gpio.h | 4018 +++++++++ .../device/driverlib/inc/hw_hic.h | 344 + .../device/driverlib/inc/hw_hrpwm.h | 1058 +++ .../device/driverlib/inc/hw_i2c.h | 208 + .../device/driverlib/inc/hw_inputxbar.h | 92 + .../device/driverlib/inc/hw_ints.h | 212 + .../device/driverlib/inc/hw_ipc.h | 323 + .../device/driverlib/inc/hw_mcbsp.h | 286 + .../device/driverlib/inc/hw_memcfg.h | 870 ++ .../device/driverlib/inc/hw_memmap.h | 208 + .../device/driverlib/inc/hw_nmi.h | 134 + .../device/driverlib/inc/hw_otp.h | 63 + .../device/driverlib/inc/hw_outputxbar.h | 1340 +++ .../device/driverlib/inc/hw_pie.h | 636 ++ .../device/driverlib/inc/hw_sci.h | 209 + .../device/driverlib/inc/hw_sdfm.h | 431 + .../device/driverlib/inc/hw_spi.h | 157 + .../device/driverlib/inc/hw_sysctl.h | 1428 ++++ .../device/driverlib/inc/hw_types.h | 166 + .../device/driverlib/inc/hw_upp.h | 306 + .../device/driverlib/inc/hw_usb.h | 4614 ++++++++++ .../device/driverlib/inc/hw_xbar.h | 271 + .../device/driverlib/inc/hw_xint.h | 108 + .../device/driverlib/interrupt.c | 425 + .../device/driverlib/interrupt.h | 497 ++ gpio_driverlib_cpu2/device/driverlib/ipc.c | 445 + gpio_driverlib_cpu2/device/driverlib/ipc.h | 880 ++ gpio_driverlib_cpu2/device/driverlib/mcbsp.c | 1621 ++++ gpio_driverlib_cpu2/device/driverlib/mcbsp.h | 3340 ++++++++ gpio_driverlib_cpu2/device/driverlib/memcfg.c | 701 ++ gpio_driverlib_cpu2/device/driverlib/memcfg.h | 1266 +++ .../device/driverlib/pin_map.h | 894 ++ .../device/driverlib/pin_map_legacy.h | 95 + gpio_driverlib_cpu2/device/driverlib/sci.c | 421 + gpio_driverlib_cpu2/device/driverlib/sci.h | 1646 ++++ gpio_driverlib_cpu2/device/driverlib/sdfm.c | 188 + gpio_driverlib_cpu2/device/driverlib/sdfm.h | 1178 +++ gpio_driverlib_cpu2/device/driverlib/spi.c | 661 ++ gpio_driverlib_cpu2/device/driverlib/spi.h | 1743 ++++ gpio_driverlib_cpu2/device/driverlib/sysctl.c | 1469 ++++ gpio_driverlib_cpu2/device/driverlib/sysctl.h | 3531 ++++++++ gpio_driverlib_cpu2/device/driverlib/upp.c | 298 + gpio_driverlib_cpu2/device/driverlib/upp.h | 1574 ++++ gpio_driverlib_cpu2/device/driverlib/usb.c | 4018 +++++++++ gpio_driverlib_cpu2/device/driverlib/usb.h | 560 ++ .../device/driverlib/version.c | 54 + .../device/driverlib/version.h | 101 + gpio_driverlib_cpu2/device/driverlib/xbar.c | 255 + gpio_driverlib_cpu2/device/driverlib/xbar.h | 1294 +++ .../gpio_driverlib_main_cpu2.c | 40 + .../targetConfigs/TMS320F28377D.ccxml | 22 + gpio_driverlib_cpu2/targetConfigs/readme.txt | 9 + 399 files changed, 195036 insertions(+) create mode 100644 Readme.md create mode 100644 gpio_bitfield_cpu1/.ccsproject create mode 100644 gpio_bitfield_cpu1/.clangd create mode 100644 gpio_bitfield_cpu1/.cproject create mode 100644 gpio_bitfield_cpu1/.project create mode 100644 gpio_bitfield_cpu1/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 gpio_bitfield_cpu1/.settings/org.eclipse.core.resources.prefs create mode 100644 gpio_bitfield_cpu1/2837xD_FLASH_lnk_cpu1.cmd create mode 100644 gpio_bitfield_cpu1/2837xD_RAM_lnk_cpu1.cmd create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.FFF74FBFA9E1DF65.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_GlobalVariableDefs.c.9475B106EEC7EB3C.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_Gpio.c.9A61E7A409D5CE6F.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_SysCtrl.c.56FB42F36D55397C.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_usDelay.asm.7C96C1CDAC6C975F.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/device.c.54B6CFC62F397228.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/device.h.41952FC88751F598.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/driverlib.h.0FB4C8ADA96DE950.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/empty_driverlib_main_cpu1.c.F4B0E06E433FAC03.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/gpio_bitfield_main_cpu1.c.676B95E1C3FBD8C5.idx create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/.clangd/compile_commands.json create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.d create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_Gpio.d create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_Gpio.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.d create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/F2837xD_usDelay.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/ccsObjs.opt create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/device/F2837xD_CodeStartBranch.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/device/device.d create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/device/device.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/device/subdir_rules.mk create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/device/subdir_vars.mk create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1.map create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1.out create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1_linkInfo.xml create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.d create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.obj create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/makefile create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/objects.mk create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/sources.mk create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/subdir_rules.mk create mode 100644 gpio_bitfield_cpu1/CPU1_RAM/subdir_vars.mk create mode 100644 gpio_bitfield_cpu1/F2837xD_GlobalVariableDefs.c create mode 100644 gpio_bitfield_cpu1/F2837xD_Gpio.c create mode 100644 gpio_bitfield_cpu1/F2837xD_Headers_nonBIOS_cpu1.cmd create mode 100644 gpio_bitfield_cpu1/F2837xD_SysCtrl.c create mode 100644 gpio_bitfield_cpu1/F2837xD_usDelay.asm create mode 100644 gpio_bitfield_cpu1/device/F2837xD_CodeStartBranch.asm create mode 100644 gpio_bitfield_cpu1/device/device.c create mode 100644 gpio_bitfield_cpu1/device/device.h create mode 100644 gpio_bitfield_cpu1/device/driverlib.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/adc.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/adc.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/asysctl.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/asysctl.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/can.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/can.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib.lib create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib_coff.lib create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib_eabi.lib create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib.lib create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib_coff.lib create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib_eabi.lib create mode 100644 gpio_bitfield_cpu1/device/driverlib/ccs/driverlib.projectspec create mode 100644 gpio_bitfield_cpu1/device/driverlib/cla.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/cla.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/clb.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/clb.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/cmpss.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/cmpss.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/cpu.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/cputimer.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/cputimer.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/dac.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/dac.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/dcsm.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/dcsm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/debug.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/dma.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/dma.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/ecap.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/ecap.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/emif.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/emif.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/epwm.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/epwm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/eqep.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/eqep.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/flash.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/flash.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/gpio.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/gpio.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/hrpwm.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/hrpwm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/hw_reg_inclusive_terminology.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/i2c.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/i2c.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_adc.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_asysctl.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_can.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_cla.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_clb.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_clbxbar.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_cmpss.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_cputimer.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_dac.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_dcsm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_dma.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_ecap.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_emif.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_epwm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_epwmxbar.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_eqep.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_flash.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_gpio.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_hic.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_hrpwm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_i2c.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_inputxbar.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_ints.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_ipc.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_mcbsp.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_memcfg.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_memmap.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_nmi.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_otp.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_outputxbar.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_pie.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_sci.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_sdfm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_spi.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_sysctl.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_types.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_upp.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_usb.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_xbar.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/inc/hw_xint.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/interrupt.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/interrupt.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/ipc.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/ipc.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/mcbsp.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/mcbsp.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/memcfg.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/memcfg.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/pin_map.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/pin_map_legacy.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/sci.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/sci.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/sdfm.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/sdfm.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/spi.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/spi.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/sysctl.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/sysctl.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/upp.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/upp.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/usb.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/usb.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/version.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/version.h create mode 100644 gpio_bitfield_cpu1/device/driverlib/xbar.c create mode 100644 gpio_bitfield_cpu1/device/driverlib/xbar.h create mode 100644 gpio_bitfield_cpu1/gpio_bitfield_main_cpu1.c create mode 100644 gpio_bitfield_cpu1/targetConfigs/TMS320F28377D.ccxml create mode 100644 gpio_bitfield_cpu1/targetConfigs/readme.txt create mode 100644 gpio_driverlib_cpu2/.ccsproject create mode 100644 gpio_driverlib_cpu2/.clangd create mode 100644 gpio_driverlib_cpu2/.cproject create mode 100644 gpio_driverlib_cpu2/.project create mode 100644 gpio_driverlib_cpu2/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 gpio_driverlib_cpu2/.settings/org.eclipse.core.resources.prefs create mode 100644 gpio_driverlib_cpu2/2837xD_FLASH_lnk_cpu2.cmd create mode 100644 gpio_driverlib_cpu2/2837xD_RAM_lnk_cpu2.cmd create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.12FC8C33CB659405.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint.h.269335DDD01ACAF0.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint.h.7734A66F203095C8.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint40.h.867E57579EB83AFB.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_ti_config.h.B258754A245C49A8.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_types.h.CAEEFA4995D439EF.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_types.h.DA467FFD6DBAEA91.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/adc.h.E519F935EB5F4CE6.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/asysctl.h.738EE6FD4747F368.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/can.h.4CBCD3766571473F.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cdefs.h.EC7EB816822D7001.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cla.h.ACD16ADC58C2BB7D.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/clb.h.0A665CC508A5A036.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cmpss.h.44349D1312E625EE.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cpu.h.F8701109AD01AD40.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cputimer.h.1F7F79EE0F170D39.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dac.h.4D3384276E2A5C5E.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dcsm.h.095A7773A0730C87.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/debug.h.D983B7242F0626AB.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.c.A7AA6765925BA603.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.h.7B29A1EE1F525C86.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dma.h.9D5A0793FF04031F.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/driver_inclusive_terminology_mapping.h.39CC836B6A3C1A3E.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/driverlib.h.5241F9368A7F4655.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/ecap.h.961EB755953DA208.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/emif.h.BA5BDF1658E44C3E.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/epwm.h.3D2DFB06B4DF194C.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/eqep.h.02C8CE3D990E0050.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/flash.h.647D30F719902AE3.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio.h.1092B3E5A67E50D1.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio_driverlib_main_cpu2.c.67C6948D8AC654E7.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hrpwm.h.C1A2624C7809837C.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_adc.h.98EA396AAD9DB0F8.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_asysctl.h.6BEC768D9E461FA5.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_cla.h.3FB6A75742A9F921.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_clb.h.53C8F7671D564C31.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_clbxbar.h.BAC502BD359E2501.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_cmpss.h.1F121378400A79E1.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_dac.h.8340D93FCBD6285D.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_dcsm.h.7004B82899E7F76A.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_dma.h.03CAC36E53F7B443.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ecap.h.AA1FA7CD26AE7175.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_emif.h.7360F5A77CD3542C.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_epwm.h.91B42B1E43EC138A.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_epwmxbar.h.1DB61B86D667E2D6.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_eqep.h.4B417234E5F1F8A7.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_flash.h.0D3F6EA09BE0112A.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_gpio.h.25BC6F0CEA046CD8.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_hrpwm.h.5207EFB2BD1D4354.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_i2c.h.7F6CC3FCBEA2F327.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_inputxbar.h.AE44D51A98000428.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ints.h.12E7A906946E97E9.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ipc.h.F1C28A8A3F99F2C6.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_mcbsp.h.4696A07EEAA97272.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_memcfg.h.68C2AA9BEEF9C297.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_memmap.h.6954F579A4F9153D.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_nmi.h.A8AF2163556B90D0.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_otp.h.79F263D4926CA8B4.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_outputxbar.h.36517E226CC8DA79.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_reg_inclusive_terminology.h.4A63738FFC69C437.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sci.h.8A0443B5BC315791.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sdfm.h.2985C998AC8213E9.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_spi.h.AC453C0F657BE042.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sysctl.h.CCCF1E1CE0DE5ADE.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_types.h.4E48A9852A3C6224.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_upp.h.D52237F873383366.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_xbar.h.58F56177FA3F16EF.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_xint.h.9C59935F074A8FD1.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/i2c.h.5F2551596C1F8E5A.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/interrupt.h.45051B5A4426F075.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/ipc.h.03A3F16C4A72C88B.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/linkage.h.13BB6EDDE8E2FF5F.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/mcbsp.h.61C109C74F5CFF8C.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/memcfg.h.39A2E88995CA1A21.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/pin_map.h.F7B7C0A83F9D6974.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/pin_map_legacy.h.A4E8FABDF32673B0.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sci.h.E64424C04B59AFEC.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sdfm.h.F6782F71CD95D796.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/spi.h.B44947D573F24C04.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdbool.h.3E82B883304EF4F5.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdint.h.9A63194999B11C70.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdint.h.F1B42414AC7C7BEF.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sysctl.h.FBC41315038F0015.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/upp.h.87E2CC02B09631C6.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/version.h.53889B59D65786E6.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/xbar.h.219917B2A4786F17.idx create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/.clangd/compile_commands.json create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/ccsObjs.opt create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/device/F2837xD_CodeStartBranch.obj create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/device/device.d create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/device/device.obj create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/device/subdir_rules.mk create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/device/subdir_vars.mk create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2.map create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2.out create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2_linkInfo.xml create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.d create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.obj create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/makefile create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/objects.mk create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/sources.mk create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/subdir_rules.mk create mode 100644 gpio_driverlib_cpu2/CPU2_RAM/subdir_vars.mk create mode 100644 gpio_driverlib_cpu2/device/F2837xD_CodeStartBranch.asm create mode 100644 gpio_driverlib_cpu2/device/device.c create mode 100644 gpio_driverlib_cpu2/device/device.h create mode 100644 gpio_driverlib_cpu2/device/driverlib.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/adc.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/adc.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/asysctl.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/asysctl.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/can.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/can.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib.lib create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib_coff.lib create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib_eabi.lib create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib.lib create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib_coff.lib create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib_eabi.lib create mode 100644 gpio_driverlib_cpu2/device/driverlib/ccs/driverlib.projectspec create mode 100644 gpio_driverlib_cpu2/device/driverlib/cla.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/cla.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/clb.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/clb.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/cmpss.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/cmpss.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/cpu.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/cputimer.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/cputimer.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/dac.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/dac.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/dcsm.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/dcsm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/debug.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/dma.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/dma.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/ecap.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/ecap.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/emif.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/emif.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/epwm.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/epwm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/eqep.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/eqep.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/flash.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/flash.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/gpio.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/gpio.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/hrpwm.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/hrpwm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/hw_reg_inclusive_terminology.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/i2c.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/i2c.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_adc.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_asysctl.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_can.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_cla.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_clb.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_clbxbar.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_cmpss.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_cputimer.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_dac.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_dcsm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_dma.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_ecap.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_emif.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_epwm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_epwmxbar.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_eqep.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_flash.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_gpio.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_hic.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_hrpwm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_i2c.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_inputxbar.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_ints.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_ipc.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_mcbsp.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_memcfg.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_memmap.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_nmi.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_otp.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_outputxbar.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_pie.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_sci.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_sdfm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_spi.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_sysctl.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_types.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_upp.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_usb.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_xbar.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/inc/hw_xint.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/interrupt.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/interrupt.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/ipc.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/ipc.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/mcbsp.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/mcbsp.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/memcfg.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/memcfg.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/pin_map.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/pin_map_legacy.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/sci.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/sci.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/sdfm.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/sdfm.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/spi.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/spi.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/sysctl.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/sysctl.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/upp.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/upp.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/usb.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/usb.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/version.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/version.h create mode 100644 gpio_driverlib_cpu2/device/driverlib/xbar.c create mode 100644 gpio_driverlib_cpu2/device/driverlib/xbar.h create mode 100644 gpio_driverlib_cpu2/gpio_driverlib_main_cpu2.c create mode 100644 gpio_driverlib_cpu2/targetConfigs/TMS320F28377D.ccxml create mode 100644 gpio_driverlib_cpu2/targetConfigs/readme.txt diff --git a/Readme.md b/Readme.md new file mode 100644 index 0000000..bae5800 --- /dev/null +++ b/Readme.md @@ -0,0 +1,152 @@ +# Creating a dual CPU project +- Open a new folder; not workspace +- Import project from `C2000Ware_26_01_00_00`: `driverlib/f2837xd/examples/dual/empty_projects/css` +- Change project names + - `gpio_bitfield_cpu1` + - `gpio_driverlib_cpu2` +- Change the `.c` files also +- Driverlib project does not require changes for compiling +- Bitfield project needs some additional compilation variables + - Path type var named `C2000_Common` point to `/Users/gmarx/ti/C2000Ware_26_01_00_00/device_support/f2837xd/common/include` + - Path type var named `C2000_Headers` pointing to `/Users/gmarx/ti/C2000Ware_26_01_00_00/device_support/f2837xd/headers/include` +- Also at `C2000 Compiler` and `Include Options` we should add the previous created vars as: + - `${C2000_Common}` + - `${C2000_HEaders}` +- Additionally at `C2000 Compiler` and `Predefined Symbols` add the entry: + - `_DUAL_HEADERS` +- Additional source files must be added from `/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/source`: + - `F2837xD_SysCtrl.c` + - `F2837xD_usDelay.asm` +- Adding the file `F2837xD_GlobalVariableDefs.c`-data structure to map all peripherals- that is at `/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/source/F2837xD_GlobalVariableDefs.c` +- Adding the GPIO file ... +- One last file must be included the `F2837xD_Headers_nonBIOS_cpu1.cmd` from the path `/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd` **we are using the nonBIOS option because the code will run in debug mode** +- However, the CPU2 has an issue at the `Predefined symbols`, we must change the name `CPU1` to `CPU2` + + +# GPIOs example +## CPU1 - Bitfield + +```c +/* +Example project to handle GPIOs from both CPUs using +bitfield and driverlib approaches, respectively on each CPU. +------------- +CPU1: GPIO22 and GPIO97 using bitfield +CPU2: GPIO52 using driverlib +*/ + + +// Included Files +#include "driverlib.h" +#include "device.h" +#include "F28x_Project.h" + + +// Main +void main(void) +{ + // 1: init system + InitSysCtrl(); + + // 2: configure gpios + EALLOW; + //2.1: GPIO22: + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // pin as gpio + GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; // configured as output + GpioCtrlRegs.GPACSEL3.bit.GPIO22 = 0; // cpu1 by default + + //2.2: GPIO52: + GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 0; // pin as gpio + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1; // as output + GpioCtrlRegs.GPBCSEL3.bit.GPIO52 = 2; //cpu2 + + //2.3 GPIO 97: + GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 0; // pin as gpio + GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1; // output + EDIS; + + // 3: Change the gpios state + // 3.1: gpioo22: + GpioDataRegs.GPASET.bit.GPIO22 = 1; // set a logic 1 in the output + // 3.2: gpio97: + GpioDataRegs.GPDSET.bit.GPIO97 = 1; // set a logic 1 in the output + // 4: Infinite loop + +} + + +// End of file +``` + + +## CPU2 - driverlib + +The main code is: + +```c +/*Gerardo Marx +16th July 2026 +GPIOs management with dual CPUs +---------------- +CPU1: GPIO22 and GPIO97 using bitfield approach +CPU2: GPIO52 using driverlib approach + + |-----------| + | | + |GPIO22 | + | | + | ---- | + |GPIO97 | + | | + |GPIO52 | + |-----------| +*/ + +// Libraries and includes +#include "driverlib.h" +#include "device.h" + +void main(void){ + // 1: init uc does not required for CPU2 + // 2: config gpios + //GPIO_setPadConfig(52, GPIO_PIN_TYPE_STD); + //GPIO_setDirectionMode(52, GPIO_DIR_MODE_OUT); + //GPIO_setControllerCore() + + // 3: change state + GPIO_writePin(52, 1); + + // 4: finite loop + for(;;) + { + // control task + + } + +} +``` + + +Pin type at `gpio.h` file +```c +//***************************************************************************** +// +// Values that can be passed to GPIO_setPadConfig() as the pinType parameter +// and returned by GPIO_getPadConfig(). +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x0000U //!< Push-pull output or floating input +#define GPIO_PIN_TYPE_PULLUP 0x0001U //!< Pull-up enable for input +#define GPIO_PIN_TYPE_INVERT 0x0002U //!< Invert polarity on input +#define GPIO_PIN_TYPE_OD 0x0004U //!< Open-drain on output +#endif +``` + +Files to explore and use with a second approach instead of `GPIO_writePin` you can use`HWREG` function: +- `hw_memmap.h` +- `hw_gpio.h` + +Compilation error `GPIO_EnableUnbondedIOPullups` + +- /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_GlobalPrototypes.h +- `F2837xD_Gpio.c` diff --git a/gpio_bitfield_cpu1/.ccsproject b/gpio_bitfield_cpu1/.ccsproject new file mode 100644 index 0000000..f062ad6 --- /dev/null +++ b/gpio_bitfield_cpu1/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu1/.clangd b/gpio_bitfield_cpu1/.clangd new file mode 100644 index 0000000..c9859d6 --- /dev/null +++ b/gpio_bitfield_cpu1/.clangd @@ -0,0 +1,8 @@ +# This is an auto-generated file - do not add it to source-control + +CompileFlags: + CompilationDatabase: CPU1_RAM/.clangd + +Diagnostics: + Suppress: '*' + diff --git a/gpio_bitfield_cpu1/.cproject b/gpio_bitfield_cpu1/.cproject new file mode 100644 index 0000000..330d1fc --- /dev/null +++ b/gpio_bitfield_cpu1/.cproject @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu1/.project b/gpio_bitfield_cpu1/.project new file mode 100644 index 0000000..d78ffcd --- /dev/null +++ b/gpio_bitfield_cpu1/.project @@ -0,0 +1,41 @@ + + + gpio_bitfield_cpu1 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + + + + driverlib.lib + 1 + COM_TI_C2000WARE_INSTALL_DIR/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_INSTALL_DIR%7D/driverlib/f2837xd/driverlib + + + C2000_Common + file:/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include + + + C2000_Headers + file:/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include + + + diff --git a/gpio_bitfield_cpu1/.settings/org.eclipse.cdt.codan.core.prefs b/gpio_bitfield_cpu1/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/gpio_bitfield_cpu1/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/gpio_bitfield_cpu1/.settings/org.eclipse.core.resources.prefs b/gpio_bitfield_cpu1/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..1e8c9e0 --- /dev/null +++ b/gpio_bitfield_cpu1/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,9 @@ +eclipse.preferences.version=1 +encoding//CPU1_RAM/device/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM/device/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM/makefile=UTF-8 +encoding//CPU1_RAM/objects.mk=UTF-8 +encoding//CPU1_RAM/sources.mk=UTF-8 +encoding//CPU1_RAM/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM/subdir_vars.mk=UTF-8 +encoding/=UTF-8 diff --git a/gpio_bitfield_cpu1/2837xD_FLASH_lnk_cpu1.cmd b/gpio_bitfield_cpu1/2837xD_FLASH_lnk_cpu1.cmd new file mode 100644 index 0000000..0c4b505 --- /dev/null +++ b/gpio_bitfield_cpu1/2837xD_FLASH_lnk_cpu1.cmd @@ -0,0 +1,176 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000123, length = 0x0002DD + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + +// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */ + +// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(8) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8) + codestart : > BEGIN PAGE = 0, ALIGN(8) + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .switch : > FLASHB PAGE = 0, ALIGN(8) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + +#if defined(__TI_EABI__) + .init_array : > FLASHB, PAGE = 0, ALIGN(8) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : > FLASHF, PAGE = 0, ALIGN(8) +#else + .pinit : > FLASHB, PAGE = 0, ALIGN(8) + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .econst : >> FLASHF PAGE = 0, ALIGN(8) +#endif + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #if defined(__TI_EABI__) + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #else + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif + +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/gpio_bitfield_cpu1/2837xD_RAM_lnk_cpu1.cmd b/gpio_bitfield_cpu1/2837xD_RAM_lnk_cpu1.cmd new file mode 100644 index 0000000..5d5167a --- /dev/null +++ b/gpio_bitfield_cpu1/2837xD_RAM_lnk_cpu1.cmd @@ -0,0 +1,141 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000123, length = 0x0002DD + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + +// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */ + +// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + /* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .stack : > RAMM1, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .init_array : > RAMM0, PAGE = 0 + .const : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 +#endif + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.FFF74FBFA9E1DF65.idx b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.FFF74FBFA9E1DF65.idx new file mode 100644 index 0000000000000000000000000000000000000000..5942e5eeef3d3473092969a85b7429e7c42e6fa7 GIT binary patch literal 1020 zcmWIYbaVT{%)sEB;#rZKT9U}Zz`!63#Kk2=nHv}x81#Sw6?2XT2WH z*eH3|A-eAGm!}HxssB!@ZaB04lZawOwm{35;&5*0PvgKljQ+Camyo7g|xyz>mp3?S* z%p3T#%px{T_sM$F8~B9Zb!PF5;>z5lAHeuaPu1?5^l6tEFM|*RgQx?80~eS8%76j) z=P!L7?Vgsr3}PT@83#Eq0h89wzMeBxFR_!CK?EqBB%7oNCScO(cV%UsZ3^won#dK#vSOEf?wKn=kQQVBxhr7ENxZevq=KSjMn$zpv{S$GZNBAh`y-&Z^?)=zq>9sQ3 zVGl{3r@_0wf?5lAK2Cqp@R3>(X?E2nuv@{PfHzy7Mm))X-6^o)Oo*!RgJGeKi}LW! z@0Wg=jUIL7Nn*{+$>|a7nxIPO=|QW)7Eg};J^aBo*Wue|-rKmxlUkwCTuM>3@X_*i8zFwZDsIg_pY8dd^=C_ z+VgqoG3rwJBTL%tPWY-VZ(80g>1jT?`yY2bxjR<553e0^2)|r^=fRAB!p`m9{_}_N zf8H(hX6C7fZHct2IN#-X+lUQbSFd=uJ>6-eaeQ0%fnI@bJB$-10+v$e8}kREqho4i=-7wCJlvTuJA#ju*qXfA)w#{e;%>2CP!S~&I`mDLUd)~5l zck+6NKXBe#K6R_t>Ac?VVZB*lGuleU(W*c50CeXDa$#*dGz@ZAFxFE zEiItdZg|N0X=9hSS{it6(zUVuC+;hgRo$CAW6H*b14j=xj9vSE>8Fe3IV;wD9)J7B zC~C@x-#0pK`)61~N~=NRLwbgscDzveIw*GG@v!faiOJk?zEoM@_Tu96*Ws}pLc(u7 zUH&;F_N&RqFUi?4eyv+AFp0WrwL0OPdr|A!4iT24XB;p4WL$hr@zj3bf~bF{Pk!G` z?KFb&9o1v}1*4h`pW1JBTXel7saL_^)R6iBlNCxM$a(8R; z3(uu2%ovfht{~a+m}_n0f%J=WjDB;9{`AVKqeoZEE~6iBpXOTkY1z#BfjQ?7ZOjbc zX3#D1avGP!-HW)g)2Ax6^IsEsA1Zw}{7FdZJCD}IV>)H_U3FF+x3(Y;ZLyd-C5F*Zt1!DE|9QW&Lvtqt(?%hdVuf>v8{U-=39EoJ{W5w!Za5mgeaj z*rjddjJHuO4g}RExjDL~yB__1(e7eO$c;w3);GLACw1Igt2n%*^Pk7(Ob&YQv*=p% ziGlfcKgwDEYd*E6*W0&Tum#UFZF16f|Go{euM%UR17ne=#-EG*a+A@!MmyJ$m zh56Yr7#PCY&Nrts|0 z2(Ppqj~-T6k1pQ-B(?Jbht0K}`j4F%^VH!~^4%%@YZ51|=+yOn`Q^>OJkmE78+?u# zr+J#xKfZ6ReMGI#n)c?+(FW_iqT z%8u#bGBfpg>6o77d-HDCg&OC6>3Hz~q*E^g2_qVe-$nn$(uFr?lBy;N*3(OXB|dpSy3}9h#i2_wIK~hptoI ztLHd$@r_O0x;^p2mrqmus}sJ5I(8dd{L=4@bCltN(|27q#XN9XJM5z2q)GYJTQf3) zCl^K!cTpZPRvlY6YmocbYR@SxVus(CJY)K%#1`ASO*IeIJKc7~_BF>`h7D{x>9pmD zO=}M4d^J)|b(kO9r>W&{)90ZrU%b1T$WcOy2zzks^dd#~R}4?Nf-_F0jFVaBl0*9HL;7}F=LfQ%kX*v{b>9Ax z`m%%LDMxTt&}J2Mr;B8*_1f-Q-wU#hkc))m~UVbBo2)RaBw~Qs5Cz=`>^3-f_-eFaD z*v`Ek&k&tMz?s1)G8ok*a*L>L5$(KF z)npGLmk9eu`t+yX{k%K^%*QT@wE&aHG3A@>M7F+aEE4%WwNp+ebMqy>56auw@RS0ab5(O4 zQc1X;CS0$VcI4$GfRI$e_9(r+oeOvG$WtA`_nBxu6UPj4nRU3#{;qXCB|+MGKfY}G zujqi*wmj7foVVx>w_uK9Xp0z~Ir8&~_e`6{IPjD`I5*Q~n`ztgB$cyH<)nFkMz#>~ zi?Ici*`@HK={oSz5hJrJPQRcv|JV(^$bav%yuX}Ar z4Rid1r-p;`HKTkD&UB(q*KzLgA6lH6@mX{(0q1$n>O9x;1_{&a6sFf-JED#BaqZZ1 zEnOZ9hx~@~RA+F8(54}JX>}}ZtL+9qMZGED-=|=ISC)Ww9Xn)uC&B)uLb3QohS<`w}bA#;Fv)ZdC z9Z5e(tajR4#BTLU7`k=>PdR`yjP4Ky!#PM>9Ml=k?W({rGk5Qp$WvC}EFv~VusE~W z&RIH(bLFb)P_rjj-Fd15I2WrHi`z0nPZOcDEjv!*d~-(hnZZ*%z?V&T$cDC~X^Uu` zwr6?!S;@Rlc=FWm;EZNWqZv&WImK9=Vx;lBCOZkqB5XzDFy)Y!7IS#Y44nR!{yoyf zgVrvS^wUoIBN9kR8exUMe=>)TotVc{e}gZCRfe#Zd8Co38=IGK9XUuyo_Ga$&AcC# zp}&Zyx`H#F?hp^XjG!$dbb8rXXaDo(zNjTUwN~qt8^_DdO38i$^Zf?a+Sa$xXSGXM zR(SeYjNHzfr}}}jo>tV;>P)hmsCGAh^H*d$5&O-KO|ja)x4WeePt5~o5Z57y6EC(D z+9IX7b-dVy1`gsbXv|mfls7n^bIRwOWeM3VQ*V|@8+|itN zd4@GV!*;q#BFt~UZLQYW# zX~I{c`r15pOcT<}O)C?AM*PcDW5JmxQ|7_;jn!Aj>TKWMzYW|_70|eqr%b`=qw*0~ zT%?{RQfI|c?#0SVqu+P%)FALBFs2ENc*sN;SVc4+GH=K(?H8JT*Y~Q|VzQH`7K1a1 zvq<8^LwmoT?f&LNJCHu6-9hcs$6d;9tk}a-Zs5$6DKnv$NA%T4bb4vu>Cwnb#ofbr zYAQH`Wy)YUilb?Dw9Zj%wA4Uv)uNh%JSEbH6!L>;e!zv5$2#QcTv#?)Pb_*d?%_P8 z1gERQRh=sKQng=CO1U1A4caR(?&hrCJw}g@;wd%w@`z0y?A{A(=LX)vVZudO$<-{0nP$OSpe5SGEpb%Tmyo!+1W(Z_M<#y z3C@#5a}pAtORU2sox~@}e(dmGm2DDu$_ShuDi85X9@Ntu)cKM}Ov^vH99^5pQyTD< z5}Q&OPY&BTM`t|2%M<1l?o1S&qrn*|Q%1t~iPl#~>wKS>plomwwCCxP<=WAT9z zzxe?@+XKzt{2d9^e)BO89L~*N_Dyt71ZR^>*(4KBk8ec%P3QC&uy%5Fk=@#3JT(lQ z&lu%1n4>hJPScsAq}$dLEHvSw(*&Fo6%)lTc|cEfK<7(#51Hl8Rdh|_DP!GmWc{5(%h0bc`S(Ey`4sAqeyc{K0IKJ94YXJkbgr1j3^sgdBUktu6r zR=FfmU!ADmNxOIPDRB0BKt`m|_-vjM$yW+_Ni;8EU0!4zF6ykyyt|&U8%p2h@l+ph zmeFQq@Mu_Lz2<)(4MQqEZD0QU%r&0s3BIdzhpTY99-=J{>71@LSxZkBPRJCU=HQGZ zib%*eVrW$iEv@y(WFrxi5Z2D9%e?JX{}u7nba2MAcJb_>eDa#^_L?519nTlBIGjao z{hxfVF4it}oTV#X0;|96(1p7teiI_~YgJu^EJQh_aI-S57#+Zh|t#*>J zI@x@yRgn( z_YV3Q8*(S@Kb~3-&J4LSLvC?j%u~Ves~@6s8aTsPRhaln73WG*NlTBbPb6Hshi*l^IMGmR{hg;)g7Yn>d<%I;kW3w< zlXvu2x@k6KD4KX`DL8XEMK0X@^+Z*#bMyZ-(WjG7s)^`a4$cxzQ3B3yMDBP20acq}1PfieSriph(08m9MMGQ?D4Ib1SjWp)w&JY!kun9QcVZw; zCdA1UxHZMVNttj`roiEeffSjLB2(a9E(S7XLZ(cCDZCiSlL>h;1-?AQK#@!+k|}T^ z#6YP`C>1Mhz7@s5W0~++roiJ`47`*HFJ%fmZ^S^2OsJ75FwH`81jCiE5f1nMO2=8g z*S~dz$qSVWp>ku~y2y~Aj0BLd4DJ_DBw&O}RbbbGi5<&&L2d6@;XSLyTD(5~U3>G^ zyuP4h$b}5K0G~wm9RGCNT5g%36+ZV#w}X*wI8gljS(^!V_fSP|unm06|s+Wh799WpE*ZB7q@P zkOhGvfgn_n{eU8YA5=D5TI%igMDv$#~ zT!KKTAol@9fP0hm4x0_FgfT)GV}kiH zwg+VZ=wJzCI1rZr4l3Sjo=2`Uk6#FNoneJDtQj&7)1&r=Xa7i8$cRcAEtJuw_)-xA z6|_)6o8k>F1}bTxk~YPB5lIlVCt)CLZ$a9PXpa*Uy`a5lR)}WJkcS`>(w5NzAuNLo z2ownbp@J&~6bbmCf>%5!65v7Q)YFW*+_ZOVpa&lq;RB<_*DQ`4%1EdO%Vm?Ch5*vJ2ih&v;)DRndpNN6aMEFc>@cIw~KZx*y*dQZ$ecrn&w0-+P7424@cx2`{0N?sq2Wm5V$aYJ0>A zk62SYe~>jn830XK0<%1bOJE5VWJ#b%APE&@N1#aH2$kjXb|(&|T{!~nXRtyBYliO| z>-JT48&|hI3d_br@GwVKB>tQ$%r(c9MEto}SZt1`nfTL3@G-~FhbRgfmN*nPjMaex z+zI0i6Kl4YIh7|shrY;!FETUS4Vb(_35h^q8O%yRk%$v2xGh1E2oov@l|Ye*5-JFh zK#>R%DhQ200b+#l7b(wseEzNXap-dcBQ!8-#6gIUpaifZEP*=2C02yW09pIM9j1FO zLS0dEAxdtHdFiyq4+V4dO)^0VVT2Gyg->S8b)YthCt+>4(?OB=5h{2PgCg-FRGbS| zIy0j!^5LKglnH?{1!f~+AXp{@%M`fMktabV5=_EMFsTMbf=8$zF9Jn^MW}2J>QWgy z&FnVZ7ImCZ#~I^$Qw%h6LL+C4OB}i;7XszR_|z~@o^#=0=ImlvtxkfIF_Ibar?cQ} zjNd{0=_xyTEc-9sN zIKuyF!<%7a%V0Q7GNDPPz%?fZf>@p}4b3&!krFe1So378aGa(n^|8rJcTfIvsI9lq+XfT4+heYUCAsOyCy5Q7f?^bhBtj;! z!B;lEUtvBZriSx@X%Q$ALqi2m0Z=4rh6*+VibTm!nQ5?R%kfjzZ#l6CIgF6QDDd?l z1_~IVfKlL`AqI*Wp_ox19T5W$7~uhS)E07b%Ws32hjMZ#;S*jIkA zGLZ}Q(6>9RaECQV=2Gc9(ANLqt_D!v)53e&1ThJ+9;i)1a9G><+Q9eitX#iCnJ`ue zW6iPUej~4jWl%?cz;RGd3-z=y=A>evi58k@W85cVAczry7-Kw;5H~=363D~$5Ho-x zfjd<2>;y#ub*SK5859Z3p(3)lMKj^Yishaw#6NLSR5pSCYyUARF;p*phV@k?ZpRywYvS*iF@>-ppDOqz< z)%w$;AE&d2k1M1#iyYnewP%$?m>-M{$UPkG zA8<;oPPN+bBs%0`-pBaH-!_}3G_>DHTQ@~x?33DH5IIWheY(K2MtG#AH@;@L>PUkW_`A&eILFA2Wt&m5c9eDHFxvwQmG z`QT>Q{@|~VCO)n@==8wY>FSDrdq#&M!BXF_6FCmHdWU|$apLx@Yu$CGok15Ywq5#9 zQ%%r@QoHv0=+Qxq%9)G(Tc2G!wqfna^OG-xH~x6va?Oshy+=&ur$_9M(BGA|*zo6B zTgA6d*?hIJ5lkw)<#9cx_)*IBEXH}QM-{E%9m)jeCc_mTIdOUiV-@%ADvCN^`gD}8 zeSOp-*QhMX|43-PQ~FZn)*#c|jiuk5UUtX5FZYw#fzXf3omy7Sdwe{1mA7@w&CHxw z)h}}SojEyS+duAjz=S8(J9s{oclQ6%7WKVU>b`JBL*(tyndkWJk|t+qac70F@anX` zKYPq>p7r^SqXUfFwKL*$|HKD%6CeB`*f>7l{>0(_ERA7_Pu`AzzIT~Z1XB(N5bsB{ zez)q`>tTwpqaQmCdNiE;m-W-JE6%k1`h0WO-J-9p7NuNX*kqZh+MDgA$nJJg{SdjF zKsueLBu0+8bi{xrWCX#~L4!Idkf#8H6d)jY6d=YslXCq>d;Z*UL|G=G2|GlJ;ze1= zw*h(^kPti`B-~sO#Y9=UkkNR{Xu=Uu`T(yFNaRU?P68u`{0xyCf)|cou>F=jP1qum z8t~M>T)qR)JAfs@Gt|?1n!dzyx7m!lb7;aIk)8nF6XYoo(1~16-w-bneB&Dt=~B#e z0jdj#bQNZL0o4mcx~wq$fa(V#R&YyaoxFTd=_Eq&3ZSR}TCtf)c%Nroq1BoP|y&{&^ zcb8|)9gQO11=e=~sE#NNF85jOcpgwdF~+J1SW^6s1Ee zT(V*)D#rTTawAT2=hLLgkY?hh#|5&EX{MT-UQKdvC750bbXXa<^=b_E!Ls33XSNnG*F84DQ%}0jUQ1}{3*gFbL&i=F~v3bytOj;-7 zg#6w%(I@Q8%EidwC-u_}pwLyF|DONMeF<9jmU`=!@1;!gzSD9z6fLWvhZ;_12b_N; z)3!A(b_Fuz0sB0_uz}yUEb!mdUAr0?@}VRjXQ6&TFpHu7S~GNqI1ivFr}jE|EM?T& zpT|ZZLjjZ&;5%lYPObBr6B3CGy}+y&>zgeV%9HjX#=5e)k(|b_pB#%aod!i|T$vR? zQ4!7?dko}3`-EdXypOe9cXz>sSQOJ&wa=Ny+gQ!t8?#W~~oQ%%aMNoPD? zDuJvLIOBPe3aL~m#7&n5sWdK5hg3QjXFw{0i}N9s4~6Vp9V`@8z{Q1-D&*oKNELB$ zF{FyQxCBxq7|&Q^IACCRZp&bHr3#(+G{Y>ustr234K3G`(t12i*g1r%r+xKctH(As zGH72nSOc-3#!cK z1XLpzw*jh+i(dfh1sA^o)Eh2-52*KCJOHQxF5VBR{g4x{6jG%aTba1oljCAep!4{N z{B(L`3k(eZ?-hz>u0#4dbY+kIcSc!#TSYTE5t9lfsodFB2qlHM2b;6CSDUl!(V*cWDSe0y?YkUm zHxzb5OP1(&W}PVM;>o+npp+_ga%lOOkg5Ey$zMZz7Nv5VyAX;BadW@exWrTwpr}Rn zw*s?PAYq0pF?ukM@iG8TzeJCuOiKHcmGN9|K#Fp zBz286#`bDbTuoYITn6}Mz#LD5D}aB6i^~C34vewA5{N6gZzm7o@P|-<-wqm~q!G$6 zZimC$p@8j5n(2Ug9ncVC4U}l0jKw)d@$JN(JsMP=c++^@W1uu?@hSEEJCI2q<_@SjJJE6`5NG0t<@Tv`%WdB=J$f_~A`9Wn$xxS2&YWz7_Ki@E_o{*R8YpM? zVj8aDy$`tAGZ<9rqmx>$=tR?jZ(BZ~sW6k8Y0L@}$%dpdNDgiysU|MI2dI01V{ZXe z3m0nurQzaEKy`BQJ3zhT;!lA3#KkF)N`V~zd63G(n5{S(f7-7kcH<4_Md#B3NBZ)Q8OckW7@El=#0eKkwP-1E8odw;tp-Voacuml< z3EHp*B4*{<&_SSz2~!Qd_e{{42v^;okh%AMiBVGYF(H`XN`ytOSUdP%A}L>DEEJgv R%*{+j@GULGR>Q4{{{gv~#W(-} literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_SysCtrl.c.56FB42F36D55397C.idx b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_SysCtrl.c.56FB42F36D55397C.idx new file mode 100644 index 0000000000000000000000000000000000000000..94ff6211957960504173f7a41449146c6cded095 GIT binary patch literal 22762 zcmYkE30PFs9>6(w&Rw~3S!afsVPtXNolvvVG|e*WS=wghYcVz7OEa~y<(Y|yfb1w( zf(V2NsAwu6ps0*Hpd^AUf*?=|E`X>A`p#gN^PdmD&)@eybM9IH+c|gU%$zZ!{(U>U zX`jzry>#KKPqCeyoeTN5a@C3@jv6~Vi(qHBdRzY6v%ac&*0E{g(RBgl4-Pnw{I05o z`)g`M^~v{h$9uaM#p7QMXQmH{@Em&TO5&6M&Ag)BHfZFV2j=-{C+_{qY;t(+MD63q z)thJQwihoya*ca${<#q`Bjfk(H|<3y9Nu5Nqj3Kp@4x$CSbV_h(r3Q^aKW;Y(8!mM z4Cs%?8GkzGU+|r2dSLFmONLDRW7SBz|Bi{v69v>)4iEYI5iIcB=7aqAzpN|RJ*R!-UkMQd^Y(sxWct)!N4ytNReHvHBdIEQm0L;B zxtZJkwa4Q6`pk^zx=o$#F6TsJ*bJY@2e%ie?a&_`IU}jZ`^Qzs%9C&0oD;v?Z2fG} z3qL&5_WZs%(zMtwU3Cd@zMmZI_rq7#2XE+KzBXiAqx-dyF7rk6vV~KOb0)lfdt>&( z>+jw${tuJg5$Z((V2}c zQ%~=)s~x&v@4sXJHFQ_&o3q~gZN{P6;RPj$OV@6>`or3Wrs6M#j+8#iz2E8<{n61U z*M1+kCv18Bt=A8~x_nV?akjsJHGdmpE=QrH)`S_WDZ)(T; zj}&%&G+_jLaPy@Qua#%DSH4Mg*yIv7qUT4)-`biM*R3r7@ylrs-x}>7ba=4qt=LJg zy}H5{^jySYd>LEJnp`h8k8INVPN)|DXTxLtn~l1LG#VhUCWbqespHo zzrQoIJ^ZG6j@QkP+PQ%#^A4^t?T9wMIArd;{$aB&e6)1R+=$iv{JNZSQ-`f`FIll_ zV*ZprSB;LW@;t{&e|Y8o&3V(Gpt<+X8diS4^s}L4Ul?S!plv^m zw3F>T$tJlevNuK1cP(PqBGFF7*lzq-)VtKKi*0TF$c1_alZ>Gw2{YjDS8g{#;pYKX}r7JD6 zt!9DSU6-k^$aX_XkvfsB6J_6@*`H-vyze&W{)gdB-@Q5MRtkoE>dKHyZ{uze=Zwy zHteUxvfXe}q*B9Hk_XL~=fek8zHsou!*`a*c0)*!VhvlYar6CN{@z5}@<%AT(DB#G zK-tbriX<>>0%P)hQ-0Hj7OC&>pR^e(E>A+mXO?1MJhZV)LlpPldM`>y=%)3)>$ICOG4^VKBn zW7*D&6!=AAe~|>=Ul98X66k~MRxDh!a?BjMW03UEb|F@#_cLZh_1XK+thdw1mNMSE zj33;$CoI=^?`x2c3EszqKDlr0tddP1DhSJ#2!2!qKbC$mM>OP!9({|*QYabL?-)FS za-^t4itc^8%n~gs(U9XsC0=yzTLhK_QAvQDC@P7NGejjrbnjc^mOY}f2XeNkWQ*>! zhbKhkgy^pJuqf>P%)0o!wjQlzOluh*wMS}$8QGGIa58dGXIc73KdG~l#~<*1HF^O< zYS_i-b}9mCqjg#1lbtCY!@jE%vQC`XFsNO2e)lLXP6AP%ErutzlS z5r?ULod4HnFD-p0Ttn7DH18YDPomRV!h4qRLn+q?o;5-r51N>J#r|4{hBP%4xr8Ev z+Nb9hA9S=AKy$5YAP$++ZDVupab@H(AG2x=z;v06&^#52R6(>PB;kVhdAL7*_10rNg2b-p4dh>j4_2V z-s%FcTrI3QI^-3R2<{`}edMVM(g);}9V**yPZmQDYwlsaXj7v&a})=72WQ>^Ih7lj z$_=6AQ@NR`-0PJ6g@OLU5V{zGgh4@cc`nDBD^@?$_aiOZ&FFVCMs+7SzjnKL_0Z28 z$X={s+^ZN;Qp4ZK_&4p-&r?7CgZpHJLNwqt#^oC0 zNo%NQTq~&XjDiB5Z|x65*4OPa%8?@@a%mLq3P_ImpEb7el^?@I}a_2$w=GL%0m`WrQz7 zE=RZ=as|Q_kgp(o1#%_Am5{3tu7X^Ra5dx_gliyQMffV@T7+vM*CAX7xgOzq$PEZL zK)#Ofb;ykfH$rYgxCwGI!p)HXM)+^YHxRx7`6j|QA-5vj3i%eow;T*%KIDf8KZM+ca2Momgu5a4Alw7_3BpexuVwIB2CQE{ z2KzzwXRtryjSSuhIgr7Dkb@W;1UZ<&!H`2390EC%!J&}D7#s#UoWbFcBN!Y3Ig-JV zkfRtJ1v#3*(U7+=cnjnh2FE~-WpFIyWCkZQ4yxXhEx$APcgQIWPJz6W!8;+RGB_3T zE(Y&{oW|fZ$mtADhn&IS49L3~yc_Z!2JeBqm%)1>XEHbw@;(OdgS?-?`ytq zd3>CApnQVICm`1gxLyGA1_3uft`KpB=+GB4SQ zNpSr1Q}E!;gsEQ^c=iU8B$k{?+ms`kbHtG}%qkSkh2lsx%#ukUX)YE=s)3~Hev#>U znx|2ppxrv_Y~j+yUgXhT$k;{Oq}D{-s3cxa;@#CpOaG*C)Ea94C_8hec9svRAsP83 zqrS#Z#$K_p2bK;Xf^uXmr&S+ZcWC;SFsFfJ*>7Y_8{x7~kW2}5nah?U$y7x7-m$9u z8y&(RQe!1DR?-@i^6lQuf39FK5nMsWD^&1c(eJli=f@2rj|yVlgIE(?RN<^sIO|He znsch=`Z#TFYwIP}VT3dBA~pS*H7uBG_;)T{icj77(kLQ0jf|(!0M)&|a&v8bBy)5$5frck3aCb~e)_Sg>c@A- z5(PJ5SQy+qfm_&+(+s@uE3i970n|*`hgH9HQ!Nk2_1gS>A8XL{h_k zM!%niw_E>hJ+|uAl!>H<->}nfm?WE@eux?6ocy^y#;*VAH#Oz!=SU6B$k4W1YsP6$x+@kR2?dhA_~!L})5z02q}b2#|-{^wd}zDR1wklZpP zPu0^=7XvX=Pm}m+)#HQn{+#|&=~S|?L$FT>%y@=kpHRqY*q8<%osNy^kn6Fo9)qk( z8LKO!S(hQlHorf^f80wplfjsR=y1rEM9Gv$t&wagkxV6&-(N8yCG2_KH1frK&7geE z*uHGH<*3HzsAd%9iyGra&7e*HWcZhUb*5_0dhTVielvJO2J|$_cyk$47T0+5HOTF} zxgBzrV9pYNaycfLk3lXK%%zlFes(f^`LEG0lUa!3$=?KZiQHZ`f8wPtTV@bJy5yEl zrzh*}AFGrU`&URG|3Nm+Ht$-F*2c~R%}%kreTsjaWQLLSwL zjGc7-R^FIa`t?U;wnsJdKFv@??i2d&6TH>N5-&mUDH8fr=zERFr&;~KdzIAa$C&)+ z1RnR9S?##}hgYAsC5ZK#us7Y;Ay^**ITY(dA%|go7~~kNi-Aih4Lhb`5LcyR$8^YN zv2YfHIOzfwEako8xfwe*W8l1WVzCpu(Drv>u?uo4i&I(PLlm&~1u%zd zWo0W1e3%keE`eOe%4Lu%S?5aVJk_#tEtFe1y_EywY2{{Gxw)Wy9PZ*kdm?y!1P^8~ zlGjHYVt@VEqW884La&UA%T^FlS`YrJp`ax?GHOf{rzY3GG@ zC{GlGL;=*dPmuNruC)FvLCAvgV}fuD@@YXh4Y^2gC=&WKvTP|8giTXayZlx)cn zaSr4YB0eEHs4)V`lZvu z$va=|b!wbyG_KI8ak>gQf^~|3UVS9%6bZSUb1J7^zHF)BoGK`DgU){~eap`zI_C+} zKOr_lsUdi_PI-kd^* za-ZO~PcYNrEE3#{sQuKm|FCX-edSyd3zZ?I435%eq+Etvj+Ao96-cRod<7|2AXg%# z5^@z%svuV*r5bV#QfeSyMaoskwMeOjT!)l8$SI7HLT6PC*~v=(41Wd=l%HPgP(6@U z{zGrHzuECNnVKz(vV{RbWDKLkK#paUSjhVsWj_rn(bi>;5(;$hkf}*$bm=rq{n+&8 z&Xjko?~o@{i0&1l2_`Jv8$^@p9g&?Sy5AK|ba@3x?g5fXU0#;Lp|dJK*S|}8bP?$; zQum5j5Tq-mY#woZbYN~m2HB>x_f;o}; ziX>PU%%>?2_xYyw`lUbTk5M5zsmAj%V z?5q+XxvHI2tqGImUcDU7F= zw$yc`x*Lr2&s8l|K%#aQ@28G-;P$nbesZ4w1*x%=(U&qtI%+8zeTv4Yj+z?!k#Okg z%`UaZ_=>Ttao=Z4$S6D!lqWQ6HnL~%R&m;${}MqoV~VD0dGN@+<}Y&jrNs5jiM+_?J>-~mOGyj-8NEMsezNBp=T#l~ zXc-Z-GR9WMtoFLAZA4Gc=D4q%Y{@8Gqmk5slu0rQUxnPNv2WElsT!Lc325*wjYN4P zYrm0oq8>&dYaa+Xh?Rp_5MYI~IGhDZ)(93yK#pW_B;;)@-Ud02#c`0!Ib6`Jom zk|~KM8)VA`$#j8o%ct>))3R6CYOFxU3R+{BcU|6MP2BR{jqF{`3{@wG7%7c+x@M@l zB)yO2T*)8$!q=o=BtI$=URsOdM@3O~UcF*V&%Bpy1%t3L2$Kt!Pd~Ed2;2V%OYVz4 z{lxzDY3Yrl(O;7`RUu;)Z4)=?m#@73Q@er)8abhnlhtpm-E@DM?%lsuknZotp8GMl z7nQ`iC&37`lyfiT`XXW%w>REP{$c$pQez;(fyh(U5!<}ptV*jZUqu=lipk#ux`fj4 zuyj0HV00POc&GF<`PQu1^Boa9M8=1-7cqnUJ!a+}unAK5ekr`0 z+KYGI3y~U%LDvv!+Gew0rLh zo8Tleo}@|my=P17PR`^0M+7~{)I%Hpfo}gFb+Yom-XP4aMq_}R+3hOi2-YnEo-#+W zZjq47Ik$3nid@0DRZt%9=X$N+=72S%bFE0%N_`cg6_D;0<(G;J%7flIw1zY_k}*Y6 zm1uZ7VMU1Z#I;1=r@?+2Cv|w9pO)%0+wh@Ha1R;p(YYLy|7UW}R||h3f@)-}rhF&`1x25QGosjP% z-F?dM&%Jo8RoUWCx)#CvM8GHHh)NE;6yt^Ob8Z6Je} zuOWZq)YNHSKuum<*yN2w(29($$gBqFb)#kv-8RKDu-Bt=IZJK1Euzy^Lk};NRZ?NF zYGrj+Xf;b%T?yn`R#yx8zNp+6-JwUPJb)Y~DPfYk>c!eTIwhR4dT2p>iKiE~>GX$4 zI7Bk4UwqCdWy+Gl0fD_MZ%j1*44tkL-c$nbeAWo28lmqF=#%TuU0pMMd@vcKG)9+3 zHJLhAWMdsd_z-oZ$dPXE#c;JLcJEy1vc!+URFkJq9MnNhIr8f zChrUhkP}5iBIFFwkRf`g-m5KnXV?QdTQp?DJLV@u!wGuFJge#S^5zuRrN+p5xc9k-AK!bV2f2m|Cm zMhS!*#3(_KgBc|lawel>(tuhf_j8m4NvA%@b}dHP0Xb1p5+Nr^N)qHENhyL{EGfm1 zOC+TP@&!q`K)Gnt)KM3H_t-*u9L|`+se$=VM~42dmaG`ElOC~#M=(B&;S4b}o!4Dc zy}kJd&sb7JAu<-C{^}k)KQ^HB+b>qw1Zk328Xe64yja;%`=-k_GCe`8OAwrnaMnH? z9?({E_SN)2c9v=Picw#AY$G+MOJ3=;#tDUAOsYAN8*e5i4B=?<4#Ynn+43uce`Nq4 zVDJIR{u=DB0rLGCydUx@4L$|ARD(+)*J^Mr?yE#z*ZXWOE0bk(p1<3Wh zP|x>yi?U^_AZ!%?Cka9lMSK{t zRm4`vB_b|?d_}}pAYT{pb;xZZZiD<##1A2Fl<-Cgv^PS+5tIj-jR~%gj&ASW*#q`t zaAPWo^+;mD`AjM2QA*Eimi*YgT*Y}pRctpn!Rf+TGaO}Xs- zcxHKY#wJ_AQpTl}(W%ZOaq~4UDH@&XTdNA26imR53Do6~{&|T?9Yq7X-Z`quIgJcf zfYd)gB5y4{{ivxDk_CABPL(S7K4^VZzh|xK#I?JFlshmGxQmp#klT>b2Du$6?U2(L zC5;9S`-=~!{ML9no!HSrq${MZo9$}5&I77kkjy>G`OhK@t}0dwVAUg zRX+~iOP+8M886bcn$)JfXFpiXB!X7PrIj(L6Z*xmaf?dM&#?(gk+GD1<8b-Tvu983 z+ec=$nlV>1Ug|e&F|#>co87fYh*0@YzRSwNNb$m9oef1WVq*(oog8`#G;x z`=iES6SN^?8y()_X-}5Sx;QzTtnOBgu2o~8X`Wje$6N5OT_CFqgpp$$>lnv^bMGq7 zv5M>Cw%GyukFA-KO`h0@jE(e(uPn=YcHQ_HHo+Fgw1uWsKAmCzs^Rs`*+gY-WOWsbKb;HqQ?SJDe*bu%sx`+Ua3 z9MY6n#uQ7Nl2vuy$J_VxVK3VeqWK2Yly_M39mo$^?L(+JyIE~Fa zyLfFEOvOLqwT~eC3m*Q0Cym#F1alBQIU(1q1Z@mG(j_@S!TCD1RK#)$&MlM|+4CcQ zYBuGPop_BIc#W}8ZPd*S?54c=esGqo>z_xK))QoUg8JUAd@XsO*?q*Ae8Hw<^dU5J zYrEK`4}~1Y=))j~Gx~7I5sW?pawMaVgdD}_qaa5!`e@3pZ68`(-s*jXw6K-w-%3w4 z|NZlT5OzY@5z@k2?66xbNYe#y!vZ+K!Q8N5$YI>DFvvNacMjK=){`w+{GcotJRj%H z$Kmzadcj;T^j)Xj9>_IUM15XB3}ii0>Y*iVKuQDT>qxl{xe+OikeiUw1i2Y0&5(C8 z%1&yTm;SK%){Eb)J<+R)oHxSDHQQMGZLC6!eJte}aa|XWoN+uuR=S_Y%TF^{-Lw^N9JIe( zcG@OLlibqi)w&n$2amEW9DbGvP9ftdnvuPmaIpLA)tAna#?~_f>zOfXRU|{p4D6x& zX=ZA_+^LPWf?>!#3=M$2a@$28wQ|;@wVkgyp6|Wc;e8WM$X(X^F61uO&;`TWEu3Ks zoS;LT;Sl6J&X5QBFmFB#C-5Y%JqahUQP4Kh2^^*yy?9gewew`S^EFDoW}uq)lgSlI z`KZR5@&ZQF>Z#h^Y|%A9zK(R)AvYpjBjhHeYl7U2bj_6W-7Kk1pG>_-5=9SL z^FwIIH*@CA@cb=~Gsi)W=gjet6FGAtf?KVA7=K(T_i)-!U!$&4ciYxhd1PXIJ}gsvns};3Z6b>YCJOO>BF&2T;9De zg+ECR`I_0DrT8EHn7xPNE|Xqu z#CRioBO{E*Vf2lNy7pft-xzhHg4AF|Mk|edr+j{X(yq9+3ev{M0)8xjqwpsJegb)| zh}Y7iZ`%<8{)KYC1>V(~m0&W2f!#^dXRQ3WTQ*@qE8{div1+ z^?&81yfd}h))a1RCg-c#r#0f@)$fPQvHDu6D55j@%Bz+0w z3zGf<<-vb`vGwzNtFMx^7=p+6CFl`B8y>|6Av9b;N^fq-uZ0Q6;3R~5KFKULV)*z+nr&s04zg#CZL@=fZnzwaroW0?l+1nb4 z;4(5^rkj7z%+Y(druPcgi^_Vs<09k#*LKr0yOHdVX6(_72dM*Kdq+uI0N}s(G;ODyicg zXpHZ&j&~uqv5sw!+gYb}_{$tooDfBSse+_~IUySIW=_})c?&0OfgHmLF_2?9Ar^8x zC&WWe;DiLoJ2+tnrBwIKk9m;b#As2EUC*(oS=Y)L7M>ydK{(|B!nCSC@1jitHAIBC)3NbWJw8fG5x&YeODBwoOO#*I$+$`W`$SneHp}exd z&3to!@;BKmPv7iQH>j$&$x;GL!4Oj4X{xIJ)!ju-nAh zI*Yx}!fZ(@Yfh!RhL}`#kQKiBTgwirg?wK$-xmi_(-0<^!=yo~X_!28O0u%yjoYLJ zb;wvpZ!esEXz;AcU37;Cb~3u1)G9T(ugM$RHR>)A>|^x%s7bYan~*f_z_B(WxQUE6 zsjg7HYSMk%Z%?V6H*TF>{_HCY+sTH1f|Mul-NUtvvKD6A{20X#@*YOnLo;uMMHhPh z@ZZ}`9vq7Lhaw;Kfjj?x!}rS%4s?(pxezIZFaWb6#R~Z(QcglXg_Ki}Pb1|tls`Rxs}1K zkh>Y&4Y`NGJ&;p0I7Q>E=3{O7S)2|zQ-d=p-`jd=!mm@vPjJ}oIFY};7oJ>xoqPTR z&F`IL^8Q9-$%A(fZy@CcUEc25Op$*WNum=F<5GMq6NEcnB4L zH*4sI+`}4rAU|dek0D2KhA0@dMRSH|$eTICX2`LeAr^8RXNZFw&l%z&Z|4l#At!K# z1jsu$!w$%aoFNf%5@$$)oXUBna^Q?Vm3ujrdzG5zG|rF)%cpaObjVg-YlVvb46i){ zxr;Y+Q6HIPz=!ke^}j8OS>{c!vhab2T^@@&ygP z0J&O&t0A{&a0}#J81KTMzAzStv4HbgoDVsj$LTzfALH>c$d`EG67N9!*TxHNkaq~e z4gtvj5QIMxCe5Ch$BQGj}vhmW;lr`iSVM zXwe)k4y3nA5=C>OI8Z&5BwnXz&JYLETOub!^9gaF`pQ<_bGsJLpa0h*k~NIveInsi zttj$yAdsthmuk5969tzyWOFvg%S0Gyn7#B-O>b zV&Rvc+Wxb_@+mwdHLrPyKD8$byJZEwJ zV4lwd*{tG=^X3`FO$|S-G&Ad4{uG0xPjOFvK5S&ZdsEb8a{qg~H(xeS-oHu2_tWN@EdqkFjfc)fr#pQry6U#? zyqa2iWME3A+5UA0zn$W})w4r&ro)9Yqc;a~MRN@AT$Hkvy)-|&py=pXzp{IhO-&X!q6V>$1cDwzBP+ zy3H)8fBXD`Y40=@+>SLX$}}0p+%EWde&JM4clFd+lFPjOURh*x&-`L%`77g>$A*do z!5*amzi+xC&)=wibyGcex_atOiFP~9ho?^7NO-}axAa%!{gi(XA4K}Z{;epQysw)3 zpVdphwM%PzR{JQki*KIW)h{QZaX{;4?a$2YzJ(JD`Hv=5Rf_zW{`Z2mVLbdwA{J=(Nt#Al4MYo7aw+ z{^sq;Uc|;wT$!8n0~pI~iqcP)eSOKv%OK9cAd<+Q$O$HZGGNdb{pIkalY4l18Ki*H zq3WU9U;-vBx=h4mo$`HYUItO1bP{_KH<*A)bASHQ*U|22$;%)Kl=heQmjx3r={RZa zMXR69wdG}y07|E^rE!A^nDh*7j`|4=&H=m(VnFF+)?_{~0h4~c_~cs7`O_nLL8(SH zW(LgnK)oQZ!-QeJ1`30`3=@X=7AOqzDohyWOQ0~wi!foB?|{M}ufc?2z5==n)i#|Hig9uir8-BHF??ukl@Ly=%{(K6R>wsYEhq{q%j?Htbph z5{X0;|7X9;&c>;OM6#^AM6&PF`^DRK^tI4X-W6F<;3p%095=;G}}5EsZA z=5$T)wM(^&TD@w|+oFn~1$8Au&lEbo9oba(%>LKih_0^lFWURWnL3Oux9M0jazc2= zs?r0sm+QVB();_e(UWUC=YJ^N>2t*E)L*mvAD)nEuW@?imhnG7MU2Z++cH;UO1GVT z?2oEFn03AGfA7bAD!;tp`u4gXXH*ckAmPH0Db8 zK6PbSH-m$I-Rm2crM5b0Hhf8ZW%DcVrP|W)rClvX%XMO2rcSWe-@13L5cgX4F6&;5 zPF&*Hx_Jhk(Hk;5Kb-SyNOOno&4xLpk0+%k9{;K};!fk?Sf8zFEf*HoE}d6WvckYt ztF^^7t*!K>r^7sz=+$vf+vhl6a+>FW?4)JiPM(VFImf5f>-_RtyF-J#KHQ9Wy#M8d z%g=l}Uzz6JW8{LUfs1-fo1QAKy0Yq5wqBa`6E(xbZI4Pi+HP)Qp4k&SOwO5M-Fa?sZ=LHGYrA+&+WTUM#Ixc>>b5BvhRr9+sbCzJe4_aeyLlId(PF~hu&(M#>Uw@`_A^Ni}$%^ zykN%vhK5%(r==%mw0s>D82mmH4y1<}U3W@ItA|^IC!Y4aK4{nMMU6UnT%bc%zQf3h zU9G#dBO)prKHkW<{bc!~%C2T3?e@>Qwfvsr(m&(_k8P;fVzs%(A-w6cSM%KrHAAhP zLA%%A-jZ3QJ7U+KE~fDnqj#50))>2LSor(RFEU$(SJvi=!7ifP9R^>p(qbxYi|Wt(ix2J9_5e#HFm+bc&(OS&BT z*!f^ya(Am^dpunRbPCj+aopvL^@q8yR$IOQxBSMzm!5xx4DM~=+{tS7z9g;32Tr)W z+tW6E;2-;=2aMV?#luB+o* zsZ)%-+oy?A&6E(;@9$Qg?)C0cL3-+H2g?zo_KYjgG||~(7Qbmz=BAVLGlDGV?D#Qa z?ETEZ?+0FcSbgeasu%2PBecBRAw38?cDeCIzXpA=@$2W@qkrxQmCP?2-BqnpMxM*r zUjA_OXQ}(tEoBDzrvgvce<}ZSpvsqX#&AzsHSq6?iT~7cRw}98lb0Jb9RB;o>$59$ zb$S)_a}S8vH13}%vXDoA>r5#!xsjl1sT%TV!tLF@+ot#WK4o{8>M0GQht8MkzRT)l zdLiwN6P#EyV!waeT9%PWk}iZ*Rn8DNnZ!UMk+&hP4RtjSWMqL%Pl+nab{K9d8FKTa z_LH}I-DDCIY;uR=?r=KhM_AbrwvWO@f=xVr%=;3wB2r%_F~%lI9GArL<}R$vh3zhy z_+2<*yk+lGQ<5c#ce>hYe~Ou9oR*Uc$&q7-NM=Cv0+dm4(->UEWJ&l7ZMHjN`&M zb+e(ep;{7EKx)HHkr}rpmWj3A{O=l>L?4^@F`OS`Y97VNqL^U{FH-Df<&UgCl24{? zRFm|_CYGv}TITggqaFzoRlJH18zkv*kGD%;B7lw<&C3(om9x6+s zic3;|Q5d)ROl+o_#1NZ|RUNBi{vBz2N4V*gB}phP)qV8sN0Cg@2OB(QxW|lvc>yCU zUWS2sA_#T2mtu#~t1SSa^ekH)yCRh{Fm=e~&5gU6))Mm+kR& zQDJ2A07fSOcmD66OrFB%q!2c!tnQ)a_FWabeuji+$Xs-7Yd>B$KzFVbd-%X=ePD+Y z4;8FX!HyQW_c8yS=+$zWnoNEQ_){>Ty+`EdfImm`4d8Fk90`0R&C$R|(;N?cJk3vm ze@gQU;9t;O23locO5Xnw_>Z(+4SY4tEx@Rx1CqRP2&r^FUZ9j z4-K~|KJ(_1LP$eG8tEsOm-VaC%3rEu;VTlpl72e-*9(_n4qZF5xXanTIjouJN+vI4 z%?sIagx|CM-?KwR&eAzxkhYNJvByHtFNF37)gOB;Zu>PyA*3TAos?l}!P!qg#;no8 zLJa7~fVt@E%$hlG-dRYyVIdC*d8DVsz=H>oGU|v=$S37HyIbcfo`^+4EP2OjYahsa z8P&ayOg=_3MnxR>GWl4^SQT+9$>f$2OBHd7gWR71e@0b|3LwAAz*U+97zm&_kbyv& z6BtNfRK>Xr@ncSH(aOMV!{BVhhR`3#Dw}VXX z0oopbL$vZI!!^|Qq&XC{Luq~j+D~ZC1?^m#-8pS{uHE0uZVh)dmk!g#qxm5c9+J`Q zclTk+s&kTFSh$CTdqfc8+r}8Q4AjFR@FbX=gfU{7u_2h;Bb*hbwp72~p*QwW4En`n zmWm5Do?6P)TC7}zb*MVyx1+yICieo~3;Gh*-oSg)91eUq%~8Nd(HsMO49y9^C(v97 zd?C%nz!%f}3HVPm*8pEbb2ISGG&^#qCY5_bDfQoV6lZL1L$yty9UT>C00E^@eM&mcI1^u#@p z^!JuYEXYuN9D8&^qnywzv2eMruFEe5 z$%l3X`4tAPFj5j+;~9u&q$F52GtkUP#kL2zJMiwHEe<-6hX5Z!a}Mx1G`n%U8`p0C zOZqP9^~Pbtafzal5KUEn=01jd+(E(}BJ{bc-fY>wd=wV0BjGw}mB7`GQTMz$ zjln`2qu0i?Z!_Wz_r~cyTBHyjA>k2m6<*iibzJYLLP$bF5^<3fVgt^rSvu4@QZ2$4vLBrkVb zx3@mH`p6_KG$5gYbmHt+)_!LXL`=rL>j4HH&|VLjJQNHMG6q9BtirwU=^R3WUKDuk6&g|Kp}5LQkVk;N&8 zBh6Notp;LErN56=qS>u~UBd0Wo#%5hxvh$=y7*_AyoG@lMoPGqfmWK^7-*x}kp)M# z-CjO9J-6&oz6Q!deynD~MQLMUO!q zBNMkn@Vj7Q^+2vH7-40>2rCOFGTu3}k~CIDj6gDZ1`8QvJ0+86vXDu5_MI<6!-e2P)uDVyk}5Hi3l115;I5H~}3 z94n8+;yVvt_DyY0%Tzqk%ILL{D3{WjRXTH8<#H^9A|aH#Jg~lFeq-9@l~@QyLNKY< z#(oJZ#anx=#`W@Nbo|Ll4u?ZVCyDTa#anGOM;u&@J%l4699f8qp14Xd(%+|Yv6M1- zDWg)#$i+^MKh!s`ZvWG@*h2;qGDsBM@=&+zMrUr_e@8yEQ(!4JfD9k`%+Aq#1I%vF z90_KTG)IG3G|ll~7Ekk2Fndb#3ov^@a~TXRgGuE5AHnP+tyhCtHO(zx)fV<3%YKNkF0NoEX{EU;%L5y;2zEK2;yl@K#)LlB7#Jk zlMp1)oQxou=2Qf!G^Zg*qd6TxI?eYH+^6{gf(JBbAjqKkA%cfAKSJ<`<}3tRG-o5o zra1>e4$Zj;a%s*(kVkVqf_$0_5ERf{h@g<>A_PS=KSS`0<`)QF&|Hk5nC4dqUeR2F zpoHc(2;R_KilCI{cL?6mT#lfe<_ZKAG=D_!k>*bbKG9r>ppxb)1XVOwBdDgi20;zY zwFqiy{(|5O&0i6GrMV749nIeme51J@K|Re42pVW^M9@g{cLu&QJ;_2_&pl_);tDsN)0W2gUA(1>0VC3jNrLo&VEYyI04SB*=eV)l@b>qLW;D|ao zA{{ZD`R=H!xfbnA+pN=yXth;)Dfv&cK}; zAqvC%8;>{WA3KbNTqNWYS22I5o%77mJ%WVZG@hT;jku6FIG&{dJBxp%+KE_f-w%II7rZ@^8;=p+-4+A+BxFYDV; z{QL_fydY(4UR_=?zCgtdaGIBe09GK~9>_u<%|R>#(HzV|FySMcE{*l~mb>9MRI?`4 zY{px2`jUUgp>cvE)rH|7YQq~i-eWgMZ(H# zAz@{9kgzg4NLZO2B&^I15>{ph2`jUMgq7Jr!piI*VP$rZurfPHSeYFptjrD)R%Qo9 z7NZBA3CbH8QFs&7K(5^Hitz>H%Kfg`(I8jucL^)^yM&ed zU6I*Iu+-*;<#k;2Vk8ukI@jzsKN)f0{&gG^9Z^q5G>8=43F$kbVImj3$_or1yXYqN zkk9nXC&`4`4`=W7Uv=sh_V5Y`uZU}z{5WTPoEs;WAxK55O4ds&0()@e^c}hO`<-E> zi)`<#ym(g)Rb&V%qJFPx!g~T|M{S=y zD*-o62@*<38>Vbtsnz4NSu*zE2?m}djfGcFFvunBSRB+Z(mx{wd$@*#Yh->jWb7=+ z&}~k|!d_wTP;nx&H=9fctp1XY|LnmH^x$TS{p{K?OR)U0@BtRw7#%lq3K#F0aEwvh z*NXNryCQaU_-k;M!awZoDf-`@XmPra=3>R4eYqaKTzfj8rq>m_5fj|A6q%RKw!K9+ zip)!=7Dgc4%5-X_xsB=6MzbT^$&qchKi{>irpd`aOI4ASGdT;R#XiIrCtwmra|D<~ z(0mt6?$TTUCIvJ<2b1SCzk|W=U_9|(0VWl+UIivqgm?e>;CX-b?b)~?Y*cL8bELl# zrnTh`n3RK$^ryk-Gz=&H&V$i;ns0*9O`30m(QTSz!6=sIL@-LExd@DkXnqMsFKI4^ zLFJ^p_+9~wDrvnIjB06a0;49H+rX%e@L{mL>M*xF2iG@|(Mcqms+JKyt|S{9KfyvO z5>iR@%ywFrcy#S1h2YHSIFk_B(j)ZbDuLfTntmXSSMj_0CS?&AWW!KJH?wY;)>3_YVh(u&K zDkBkLWh5f3j6{T$k%+J|5)oELBErf@L|7S#2rDBIVPzyDtc*m2m61r~XwUrN8!{&p z;reDFA&WG=n0vxad4hoxOh0i!m;V0fLiF(R#2Vvx>(kG%VIZRuNct6bC!>=}xYD@B zBx#s&34T=#5^Bh?Bk^7#PdVhoh+5pH+Ga`|5Zq+ zA|)PSXu-X?GwQvH;xhv692S3`qx>mun+*%;&kEkNJ>Rp`aH(Q7tJt2zzM9pnrrDcQ z_vX40-Ir7MrP-fT_b1$B`f6h1hf5W>gmFlSBi%QC^qB2A4wGx8iXFMsAAeKy`={8E zORv%#z(@mV4rHW(G$%091ey~WX(G)@j5LYnWJa1ya|$C(p*fY2rV^gHrgnQk>+@Pg z8?z==tc6(6?srDPF{{yEv5*RUD(PH#pr7GQ!%1~mXl40Uwtc%W@9nr{z6<}V$3iI* zN=bJut#7!fW_Dg76e6LJ%=Tu(8}cni|7*a)7bJWkPt*kr56$j1yb%jwNC+eC>OEn= zr4SFNpIC6_cxSGk7@k{BmG!DxJpUIK!a+ZrT#AnHA80W;;)g;w#^@X)QOsoE=+vuM zo;G2@k=1h~ANK4lZT#udDY_L41x$|uru}|(@$xp8=|xGcc&gdz+qNGK6-%UE3&~|q z`Z}QI!o*u``1w4hcOHX3V^jXReJIE;Y5A-Wyg}ca+~e47*t$kxVsE$3{=Y9<+FvP= z4F3Hv{-^yD76~h79kySbRdRMRYd&PKWZky)TNSrOf_hI4t!|oKyYM}_YwL8@{XfFr BRWbko literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/device.h.41952FC88751F598.idx b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/device.h.41952FC88751F598.idx new file mode 100644 index 0000000000000000000000000000000000000000..d35843421059da992bd9e31a0bba1d77f4129759 GIT binary patch literal 3206 zcmYLLc|4S99Dkp89PjWts!gLIN4eIRkaBIiIdau1N+Y?~ZKP1HbPPGRB#K;VLrs@6 zF|C&5R-|SX5@M;f?s9Ck+dkU&9na@8e>}hM_jf$M=llHLvA4FcIF2KTnU{4$kaw7e z5P~49;4d^R#J>Y>KCVEJh};oJm*Ckg-;5g74mt01GG1YdYN@a&PDT}#=342MH&^N= zf!nGbY|%E?iP|Xxx6Y)4&cCo?s&3fL{9PK87drla+r)VF#^NjGj#UqC#$Q}G-MOHg zeizn{05(+^k|=$SJbu6@dqn38M~9qIh7^mRs6>?hitR~CO%_HNG?TihsB_hrE7EIa+s zulZ&1t~+^-Co|Z>o{|?nxhduc%Gl3oB{(;(wYqw`UsW}i&kX79VMHj|6*ijwtf!%? ztwJ^Hu01w?S>aYmroV;3r&u3RgB0$m9(PS;*?~z}MX7G(Q;sI;o?62ClMS4gj%?4} z*@^|3LE`c5eo0xuW?{Uu4f&Ek2Lu&j*>>Ok^HGoYDf07or|uWla`hyuj%W^RuP)N@ z@vxl?F}?fLdM7`oXLSt4GTLEavCrF0b!ap>{-zRJNTe>5fBU@F$vh?QD93#7v3XQ7c!ot+How^W-^$hmT3UOSxrups*!k6RSSA%1~HR96Rlk&*}@4nvt^e{`n3R3t2IR$*Z#_+rO`$E)IVca>`1~>qpvCqi@eFl-`-o zwDK{!^YHyj%SH|D6-E1evRouLxotO;*xWQ*vs?8>)YWR!*0K0(=QQm?8d@0`5Y_UD zT}0ib%;uaO{U7i!^11>C^(TrOMZf@)ixHtKj?k*l=s{8;j!I{+?M@KLM319b5=cE_qJ|wKBgp^ z$@@hq+N5LEmo9hp!oSBJ4izv`_f0Z>wCw%DW(VpAH)vn`Q~Fu42(SxKoZh=H4b!Y$ z>%JqZ@Y|7(m-nb_?!VWm@TR)BU6xxjZ17a9*2GwxeJ)sXAg;rrh4ncqSKW8g<(|>& zmO6eA{}^+GH?Qnr+GA(KOJ3WIb2nX|=^uTjx6}S*YxKdHlCsZhcUV98YlH75=l0KW z!>+bRiau*`D`gnB{t+H3sL>6L4Du`j2vU=Idwk4BP8k0>>)^OU=mjWVfYK2viV7*L zMK%?utmzn3kiik!5(*bRmV(Dpl$HnxB%E2an=W)ITaP0$|KkY#GzC9Rp^=2knddYD z!}&}ckt7LOD4vC?EfIuagj9xBgT3*XHIA$#31?CKEV^ciAO;CJ#`3J3e>t`|B0&=R zP`nS-SRzm%!GnkLSblFja0CwNuZv!e;^pY(B?1Nsu8VEEYE$ZbB#>`N!W@vE19Auz z?$^m8>xzGHe5?}_ha+o9LL3E;TRx`WiL-3e>tPu<0>2So7kvShUO*KPDg}tk%OZwf z(gJ?d;1%GAG)ZVd@s|H<5QR0&Wy}5GcY)U|fvhG8AAs}+06Piyu!aW%1M;o!7rSso ziX=Qo@#iRG=@cR`0utiw6Iw2eAp0&Kq8uHr5dva#HpZ4C*n-OhRPquDBp`H~e7^i{ zG01-buopm$^f-lVdNL7oNdf|`0BZ&6B+$oi;F_P_x*7s3jHN)DNj1O>gbD~`U-+Fy z7qyQvkROhP3o3GFWeIimmeYiA`UfET0Z5Te!0B^9bPh<77lXrYDlVYvf;Q7R6b6T) zchOBhwInRVDe<^OP1?0HN-+KtfIV3*l$0N=h>#soQJJs7(^m=2s?g&(z@7sY@(eiz z^LL}P6B!VH7+k}`#X2ze3?v0c1M>8|{ZkpB{3F9DMbq?x(dsFLNW3jrR$cmQ6| z|LeQ;HVa#=q_#t#1Yjl00I77CgHSl(G1JY>XvmZJ5qj_e#s`LEC{p^+gOEIdlnuwt z8EnvJfu+ugE}&9m=Z0z}Mwsz6jxba^z}msLWGJgdS4|t8j{Okm2UtH?`g8Mjkv)bv zI24>iA?1nO51eIQH&tn}f8)A790E?5lR$loKj>3pA4Eq(vm@pxFmJv<F6R{?f)S;VSt zjLP7X+=mdb!E6MncV(JLV?VuagytjI5rLU}@Gvnk?T7@^E4A>M@-NRJ-xu>0h>IM8 zkWUOhf}b6nHmz=m_dvcs<}cufJo;4P!3iFKW-H7}kTy|#7!33J2BG;ez#cDa;?@Rd z|7l&yI|%q;eu6N0fkUYIpNE&sL0FI=46VXQDACe*2AbOd*0vl*r{J<$v6|T|1X=*r xvJ9BLD^xC;7+8cr7#1c76ynYHSUN~($WNhPwIe_flzu}uUMBEBYBT&C{RcY#BOCw# literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/driverlib.h.0FB4C8ADA96DE950.idx b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/driverlib.h.0FB4C8ADA96DE950.idx new file mode 100644 index 0000000000000000000000000000000000000000..3386a98e68658c5a6bcb8ff4ecafd2b244b2586a GIT binary patch literal 856 zcmWIYbaM+}W?*nm@vO*AElFfyU|9;>PK(WJG2m(W?qs4f z_1E{XuRNjh%9B|(%xaKsZ{1tF`L5Sp<`NYa!H)BZ68$w27H#6mXI6WpxVKJ^^i6!c zYg_Kw+fV;ETHbhfaNFCj26mq{pPbk$xoi3F<9F}hQGEYy+2Q@cU)QX2VYqp*XMtN& zKsAeLr&g1;c3YH1E0069Q^a*^Uyhs?*98yyay*X&MoM%>MO6{ci60 z)CU54*B-vJ(a%V|?BV*9wcmJiCQAG(uFOpW1}{TVYFe>4kiIPx$S5!N?-(POiWY|! zDC8laC^aV$#40XIE?y6e2L^tKIEdszFhNE@0XvMrz@Ug=@*$Yq2qq|&p+F4AU|?W{ zGnrJp79ZQ={Hpn_vKS*1GYcylI|nBhHxD1bfS{1Dh^V-Pq?ELbtem`pqLMN%gCJZZ zg9w5tgkVY|m~sdvFxkO?1dPGJAdg@of`dT;Au5GnDj}Gh2qqhXDT-hM6EY0Qz!(e+ dk_e_Og2{_ug2EmOIA9D024w_O0KsHJFaZdtzDNK7 literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/empty_driverlib_main_cpu1.c.F4B0E06E433FAC03.idx b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/empty_driverlib_main_cpu1.c.F4B0E06E433FAC03.idx new file mode 100644 index 0000000000000000000000000000000000000000..4518408cfc7f775ce47b0c697f27f40ef95544aa GIT binary patch literal 580 zcmWIYbaS&|VqkDi@vO*AElFfyU|f{wwfFJ*G0BcU4Brc>&&pna?eCmi=7M6*7JPYn%K0 zH#SFZZd>-}*UQr@;^+LC&b{-@`A?coCFhJ5yxy}>L`Z96Z_)I%dgnJSI`Qev_q#$q z{bd(SF0P%yL z;ZpuK9#CuvnX{U6f(f7u1QeyF6^jFzFm;Sv=<+#R1#7%JxM4av>EZ6I*X|K)e3 z`EM_-mHpx@mae}hRWUDOKj%{w>!?(3kD^z9f1j*eocLOShrfmI{@i(&ZL7|;1UaoN z$WoTg?U}Is>r>T*M@#mdS)`dJKW+Y^)T2d3$L-Fm9nA?8`o*etEvwZ=<8l=Tmx2Ff zk!6Sf&9y%HX}gYZId|EMsI?1Dt-rtL^-=Eg@*6Kae;H~O!Er2uKSOHumJ&m+jeI51 zy-&kEr>SNZeGh2L3M_ZxEAZBz+rI1JI`+RkA9C(Yj+cI2{xqK@W8b1p&wH<4a(2sJ z-Lrhr<5|Zzc;@FUby~Vaj3;+`Z!?!up2)wlryd8iP4X_!e80w2PiAM&9g}6Xy$!_| zuTAQH_(jm~=lpw;!W^ZSW}jQQ#A)a4{dTuZUcE??x_{=#?3gJFg-@y6xh0X&oYUNX zRPOX)1*R)|)++8++~Qu;^`}Gd^_Lt)^B`&Is|MF?LXMfry|b*-mKWY#zUPEy_xj@- z#QmQiuy=X;aMo()I7RJyFDHDF;1hhYr#W=XZLvpBdKOMj6uX&JWY6_uE2z6wm(Iezn#quevNL8_&+WMRU7HrrWU4f!%iwrCdODf?69x*a%c;XvpZu`9>G$DNia=pQ zDMPrG3EdwfS_A*80)_-G}F%eA-?K6gH7DfvZkV3$zk$W~$=^h6#(R0L+&_U$Cel z@zhz=k$74xT1Y%?7HuS+4vP*FPoG5}iD$rKfW$LoF@*DOwwzPW_>k5Jbe)=n8r+L8 z=P+`iq{JIFF-(yw{`LS>8_F5NBU1d>{fC)~N_`+NN|?Y6Q7ZnL^y>91kg%zYDct8z zA8D!TT{$)pD6B7~4-cn17h3&3AD=cGD6A@|3Xg+p*)d-vCu+|D2}`NMRY$I$SXk^8 zxCkh$EvOBT$lcX$MQQCjb^wKS1a;ts{EuxpJ?HZ=u&|U4+z{`oQ!_srnVko!Rufc% z8)9+0?$9mPTc1FN$mzg+c}asuu42Xykgy_)B0nsMn(TO!949)3n41^~m` Bk@x@r literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/.clangd/compile_commands.json b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/compile_commands.json new file mode 100644 index 0000000..276cd4f --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/.clangd/compile_commands.json @@ -0,0 +1,37 @@ +[ + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device/F2837xD_CodeStartBranch.asm" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device/device.c" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/gpio_bitfield_main_cpu1.c" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/F2837xD_SysCtrl.c" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/F2837xD_usDelay.asm" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/F2837xD_GlobalVariableDefs.c" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include\" -I\"/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include\" -DDEBUG -DCPU1 -D_DUAL_HEADERS -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/F2837xD_Gpio.c" + } +] diff --git a/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.d b/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.d new file mode 100644 index 0000000..f4433c5 --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.d @@ -0,0 +1,156 @@ +# FIXED + +F2837xD_GlobalVariableDefs.obj: ../F2837xD_GlobalVariableDefs.c +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_device.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/assert.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdarg.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h +F2837xD_GlobalVariableDefs.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stddef.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_adc.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_analogsubsys.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cla.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clb.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clbxbar.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cmpss.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cputimer.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dac.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dcsm.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dma.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ecap.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_emif.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm_xbar.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_eqep.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_flash.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_gpio.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_i2c.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_input_xbar.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ipc.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_mcbsp.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_memconfig.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_nmiintrupt.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_otp.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_output_xbar.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_piectrl.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_pievect.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sci.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sdfm.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_spi.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sysctrl.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_upp.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xbar.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xint.h +F2837xD_GlobalVariableDefs.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_can.h + +../F2837xD_GlobalVariableDefs.c: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_device.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/assert.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdarg.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stddef.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_adc.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_analogsubsys.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cla.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clb.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clbxbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cmpss.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cputimer.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dac.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dcsm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dma.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ecap.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_emif.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_eqep.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_flash.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_gpio.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_i2c.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_input_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ipc.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_mcbsp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_memconfig.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_nmiintrupt.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_otp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_output_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_piectrl.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_pievect.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sci.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sdfm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_spi.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sysctrl.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_upp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xint.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_can.h: + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.obj b/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_GlobalVariableDefs.obj new file mode 100644 index 0000000000000000000000000000000000000000..d3068410c8591cff21b6e3bad0937d7c002132b9 GIT binary patch literal 536432 zcma%k2bdH^w{}nW%gJshIGus;+aYP7mJazt4l;-S_lV)p_gGd8@0dtEYvsGd&)U z0srSQ<{RoS!+3sIgfOKT3G9Cx8a~TwaUj<;3@`tG3~y=SsYCO|wa7|fe^liN|9xy1 zc0p=-dZ@6lEWaSHD3o55m6uyq5b989*a5SH6`7lp+BGw~gW<8wj#lu+M^ksq_@z$- zM+-wmhR3XH+Gdtju5Mhv&A-;&B@F4=1>E4Z%}&;u*rknTq>fl73|YBFpn>-T`EI-Z`&(?Yi`%Z%9&eik$~QprDoj(+bpsk{^f&Vxl2>Ga9omF$2N)B>ktHrgq zaxO27_=Mv~X?@!)v6hykpUfEBJ3oRms8!Sz1<6q2UQwMScMl6=ZcN3}qWpeou^5TsBp01q;zBv78WTy zsc9`Xq1A?QQ5C;<%)quCkEhKg#m8Ni#TR8Kq94s=&&BedYXKhkSrq3NXBUR@^9qe1 z?~j&fa{4ZkJJ$+97BKlG8M)n!0Kd4kj;9rNOYfNLM8I8W;H4xR7Qea;f;{XByBQ`& z??#kgnqn|C#%c?oVH7KGZ<}=J*!Zu{TqNGcmulWhCQ~6I(x4nCBC1*Gz?fmYrV935 z>h|iN@1@wJ;J7!j;3T9m)1O}uDojt!4jD0=nGR5aq&JGUz9WL{+Pv&yp4p8^?rauX z3bQ)ore^2lWrQ3mJE6tl-SV-^I}XGcVvJ;k zn^+}cpmd@pQ3;!wuqaUmUI`mQ9L+}5FuJoymfg9((bK`0rE6(stP0+qQ#~r z6)jDaL5r5A3Ux#SC5f6;v?MEo7A+}=lIiip=Mwi+TJ=sE=}(v*Gc^+ZDZ`}& zhD%E<45r7eOo$A_*koYxT6uW;Z|~d{UxySQx0PMMk{8Qd?Dkrpz6|p_aH2DH84eR9 z2`4$zmJu#E*_pJAbipaktYs9!PVg`^#u^PE89L1yR2`ZzWLOeuZM>9b)mll%12B&p z2ZcHFxCCoFxNR646c?37kBB_8F1j8mJ&u!wT;Ry*ONrKY& z#2^3-qeL~;KcezSO*+6N_dwpOIIT13d!N-mxN zE*3yx5D^Q(Z4wcqLpdFnl-6+F^{9worDH@)qC`xF8YmG{T(Bf!stcAxOhZ^B;z0mO zM3nA6bmyh3_(^x z60c1xtSm>EUn_5`S0Ko*4H@EQVI=`YZQ@>G72>=Ed8@D*KoWf2ninnGmHV<-O~O?p zE%;cgI5Cp;XMy&$P#6T?I$)U4-lJ3V_GF~}d8kCEeItVW zT1opR0xH@!Bd*cD1wmFq3evt6VU6}}2=Z$s?Jp2e(f%Uh8tvNwB(!gBv;B{i$1bcQ z#8BEfF_QM3K>N#37|^~87&eR(1}fq`GvbcbAN=a8r1ZFN*ac2%EzC>j{ffN5?Po|+ zL#!IT166R0-IVjCj(2q|$q>sQ2X!pj5Nn0+=~#;4=f6FqW6caN$KKbm=7!0!!#dW& zSs?lVFfyGO_w}Z~yFa|`cH&*UTy10B1l~#VJ_hnWfzllEYFnQIPloXw<3`>K-CDHn z`C;#!&LPFeonaT~Uj!<)rx7!48FanVD=YBnN}#@NCN;s- z5^9oxumPu*&tqXQwcKbzn+=1vQ^vv@PyW8_?+YLIBE`oJm5vlWz2sYAXVmPsnBQ0A&kIx`2InTw@4&eXEznb2;- zcu1AMcF5#Ujo0YGgz{*5TgQb7&C<_d>xQmXyAtI0=hChn6`%SC|I*mUZc?(hE&GNK?1KS>0 zF`Cp>LGwn|CB1nUy*Y^Gfj94&&~U@JpEX_b_494-3`|Lzzn#<&JAz%n@)7rjEk74$ z%P2Gh)=`V!^*W$olw(c*%z|NS@darPnspg|3~}O8!_G60gdRNgIH^!~Nmj^RG9#?x z7Cg}S5}#v%OD8O7JsDO#)|Bn~}~>c9?tAR?x2VG zD*awW$=X)u*_$_2eR%T6q%v6BQkBULdIdY^RV>c&Cc!#jLc!_>Q zdFblr(p9#eAYA1mot&tSX5GU-`m(lY5e zM2VxxR~KA+rqmfmPuu0GTeT_4!VZL zK_>m52@NNiwARJ9?wMSEN(8Au%cSygAf^|OMKh_1-QdckmNL*x>O}+TxX&)N-IG0N z)qkcCXoyT95!i8ou#Stgz$=nTJ6}jyKlQHBW2vhulZqO&Od2Cyg-ja6hPyIptTNC{ z8mA0lnY0|*2o3KYuC=UEYVG?;BlY;@f}%2M1*9Q9jE0I9cuX?s-DfuTzxRo=LrD!< zCQWu_(kd32lirH$4$Gufl}XE_)et3)*32tEu0 z6Un3le(JiT=K6z6NDW#hO?G9{J1u@!gmY3G>w$5~GiehECcS`F(M4wA%GX$W_Lp(= zhE;coX3`(grORQFc*TO&lT6y>`^a;Xu76#Nc96=X$uyJJwOn)3df0I2A)ZNZLzHCF zTYmT@Ye)Om2B}QTq_Q#@ZVl0!+p##vq<2`*aFR)X`~HJA|4jP)0I5LBq;k`d} zOxhAFa%Iw1%0M$|Yc!CKTX_A%m}#2_G$aktJC4pt??zYKhIL#!3%nwkbp8GbH9r38 z;y6-+HYXLXYMC_6l}XdF;jT=Yp$s&WhLj;JlV+lg(D2c)*CQrwdig(ZdZCe0P_mGQ zPGK~3w!mYONe{JszWYl<+tSqoEt96WGHEW&qkrLo?~U=*?g(54^e0f`*e!+BiRSq{iRtT(`n%PMYG%q*uc- z=`UCn&7{{5CoYYe^TgghU$^Nvh4>iT&J$8IjL|}%cSF7nREg++?7cuDg(`=lawJWlTJn( zp`ph!HG<2oZGM9^(oKV!lTJe#9t@*lx&)KBA0j*nequqS*m)-uG%bIyLZtjh7nzp|B7P@%i3Kt}6Iyn|YW z1v$}L)mm*rGY#V)`=yutWB=WE=fS((h%JBG7)4Svs z8WEAKu^|tv63Suc;fXO*q3Ip@v$7x`j2%3%U}W(QP2#&C#F9)$yxd~pD7KbI_#9J~ zGV$NAeXbFXp%WU&(*ARYCw6&vcwh}O7hC2qRnyAz04av? z9_NVtWB>iS!;;wEyAM`NV1Hoov4`1T4pWJQs!s@2pJI!3s*WgBqv|L&$VJs>czGCA z$CQau^*I{IlY>4BCsxc(?CZLHkxvd7RgN!`t1pqO6WBC|t6J7q9-xJARr#myqWUzS z)BQiWO4P&ZB;o2?Y_iVPcM8?GI)x2#adjFm598{LGEuJ1qJePLtE5YnKSI^MCBDE@ z7S5IMMRIi>xw?Q&1FnAX04;>8_j=xX=F*j&+e!I)TqWsT{YbdFj7`?Lx}s2xtDmqz zF0OvY%fq<3s!WutU(i6fTD1S2(CjbfeL#HCxe~reu6{+Xe#52#SHF9J7Q)rlx{C_m zyV`d?DPQL*S?B6c!qs2cWSy(O6{>Od4>rif)eXEnjH`c@iE?FNE+$;Hd*{q|@9gVN zZ$oshgfEgS3p2adwdP#Q@|i#j;mRNVfj4gD;QIf`Rf^74z|>QFBsN*+DoUXmSJBuY z7gsTOc^FqgWujcgqJeNVDDAIl)oZ`mj`*T;C47-wl}D~_!KOi6RWN}T!qrD_pSyp0 zhV3Ke>v7dg=c*FnsxmfN=cFSJlx#xT<&{wrZaamrIB* zI#dtDe|0hpC!YFAtDHm|EQT zo_l}FJTjdWug$GUV(&wk>WdB5nd+xdjj8_F9#>Eez{|s!8mLT^sX=HUOw~@=^5f!$ z&kZN8Xmcw)uMbA1?!%S=Q$svJ3Sp|*Gcm2_RXnwk6t6Kw()uvM)NpLD&eRBnYD|s9 z_PCfDg_nmhHCmY{Q)AFTnCkM?pIsgp9GOR4(U{V+`Z#22Jhlv&n&1Ia2vbk5pYiGX z{d;zh;x(p7QlCtint~11nVPCljj3ta9v4#&;^kpXO;;w$)C@EbrtW_v|4U1fJ1(l~rN}o%ZnuiV6nR-;A8dLMJJuapm z!^^{%dR&<(Q%|6QFjYKgb?l(`znlGEOz9c@Nn~mfwhWkB>;X~;Q+aLP|7zljH$Nf8 zYcbVa7r&*1si(2QI#bIOsxh@3+v8$t1zsM;)JkQdOszr#Vd|%Q_I0k)V&^I1iWXDC z6`9f3AXCp`%Ydo19w3Dd_;h-H#@^deTa?c_Ta?Ay#^+$6%GshUUNin)$C8|vbd+)U`FM&6A`9;`zA- zS_km{WiOQf4qJe)Ls8Ba;F{JS(2s^OS9R_eHL5jS(B$6%r0lr)s&fm{RpczkvDJqK)ia1LK&3vUfcMl-+9*Q1-7yK-s}w0?Hot5m0uqpMcQE5fqi3 z9H6M|@LQa*DZ?Q7o*(iIua=t#Z-dJAzm_(cH?2 z7QY=ytek6ZWn2sEC}QPwb1S1;SVt2pXPjFZi_;#*UeFXc7c0@IC|=x z93h`*c&9|bvleF**7Z(}fB|P1kExWq^~vuiE~{u2&{4PmQ!aabPNm#<4^NRzop)d> z;y~wMqVoo9B?8K5=K-uR_2q^o!DFJ1l zClXNhc@hC-pC=Pg_IU~cWuG@ApzQPJ1cW|sK~dS~Eh#GdycI=dpSPx{?DM-QD*L<* zqU8DXjQy1hr@b_35gCQ>e433e*5{&AWVg4&Zf}p}Io)2{O7%bw8^#QkONMUTl9~3# z&(}x|ar}h@Czs?GWZ^vqdrG~RPox-@SCCcI&4}hF4($V_^%oT6=doAjLIsAO8}_3? z$_jr3{0e~N4aSW5@xOJczo{o_1-!xN)W};Q-FywEkFP^v&h#@AwbBwl&9sSNWxt^(;5}Y-_FsuQDr> z{Gs2r=2`H@x3uziF>^&@BW&wY3tq`pR`x0=FF9aa^DTIDlv|NzZjH39$1La-_^tDz zCpSmg*5ekuI!Vl;=4jh`!h+WVW!d}&jQ=#owiZ}$vj8?WW8}7=Z7sB5dMRx@t#Mnd zZ9Qp04pcTC{@fgATZ=3hF4D{&x^r7O+gfbF4ghK6Pa?SO7Ta24!CJqx@dayci?^+( zELh!^Hoip5ZIx_msRiq~(#97hxvh$AJ#E1XrnK>8IBu(ITgxn1vy(Qy@WgG^ZELv& zt5nj)ms+^3rfsdTU|mMq_~HV$CD_(V3sxeejo(glTOHe4Wx>6-w23G9+*r@HR$K7A zAB@0EecO7*f(P7S1Zo=E)*1_*=z-K_{UgFjDGW}ut@XIMNB%?(k0jgLV8Q8C;uj)1lWpsH_b>Qn6joS@ zZEdvRJR0$fWDYm8txfJ<@OOiqA2qkF%@!PbBz`0YSPR?QLVlDdU-9H6wzRFS7QCa$ zTP+U}h1q%eG#$;Qdw6hGraYV_Vy; zk-zRcGNR$k&ip6*6*Xt?CO5aYtsNG;LJ4NE$BkQ4ZR;fqUU&nmvqzDe(`;*}1#c{B z=7NyOTBZMHt)G{6PuumO?>{niA}J@ zraguiW^lX{ocaV=Y~JI!iA`|DW2G_O>C{Wjm>v_H?gss z0cK>g9skXYf*Cf~iMW|jP{SrWftwixH*B^Oc{8IRhfQ~)Ze|qhu*ps|G4kB%u*ciW z<~uQ7c=1{e82LIPH?t{E&E4+eQ^015~*?b@EcBc%xPYSvch6^;%lKZKW`iGZHkhb zZ~HbMy3aLIx9T-J8hLVp1Ostj_upJ;osVYH_EMR z7jV{Dm^<}s-?kH3^Y?sl=Fs*)QDJVOoHy0CeJ|W{-=Vt>tnE`@TrIk+f$e*7b?zsf zX3t)HDv+I*-kCFE+rI7BQ^%jVXT{{7#igPHo7%n|gDRh!b?L5z*#YJe%XPdZsr(ns zZQo1Te_mhGKliiVnk|jnTH3yyuO7R7Yn?woPta`X+}7Imy*zKv{IiqiotdxMGPtdc z?c3FIR_ObVmA3RE-SXP{u}S0F$8V-Ljiqpg92> z)O`>5(>iob6^T_G`|QJ`#h9TmJ1;*Z==ZVvLEm^7>;5cBhQU_IVtf+-_c|TSc0lvh zFW*FhvsE#PPXe5r{|tPRc01=kEAqu1q#5CxD(@hD(_lHwxr40bdl39L42_iB^LK_; zJh!t6DLjsnl7^%_)oVm0RIhRtbsY@%9;m@jx-ob_Y=g9XBVV) zNiSs2iyT5c0Y7`%&wx~M0FqyO*w4T;aRQQGd)Duy3-;t7#=jfayU0Vy73=!#UHxmu zQsPww@laA$>?|qy_rc1Ue?OMwtejQzzv6-R8^&_w)YiZ2Uis_v$$v=Mv8x=Xin3Gj zP$&NskFO}P*zrl*QdN|g;kYyntMnBm6^k>S{Aw>1!!pE?PJXqCNR52QpJYa6QyE9ZH5BRd2HxAp|sej((H{;eAz3X zlIE${V9k@Uf!m<`&tf|uHr9H;OA;H;Wkp{0-o1S_DO<&cR7p0}*|s{24Q*2$#)iJ7 z4q{_IwnD{*+DoTmLv5l{v7z?Q0Yf}C7GQ}aHomQNxL|6{vMl0-iVa6IS!^uA*jS7O zL2NAX02llSD@=ybA3y%(4`&RzQ6esu&wF{;;n-R0&(28gk}A&o7XxS=ByM3y69#^w zp8q*C6n4xgf#2|F)Bg2na*`!~D(&BZpmV)b6n`r1r>7)3M@#zEDT$&*h23(~ogt`B zO5_GMTW1D-q@14~m6*(YXCNMxXc&bC(ouEhw#u#EJoG+cI-b4rCh3ro_=1!iKc0)| z%-C-AZwEpRW4|gkzw)pBdRAWMdUNK0D3&OW*ojw!nxk#S%M&Qy7~t2o;-#iDIL(OW zZf?Xr_wkF<#BLwI+KA^X$Y$&6nNIdroA4n1_z2Z^;FYN6@4Zs($d6xcu9LtZyp5Of zCz=nmVEny^ZGrgP?g0{r7#}TtX3U%CUN}OEj&sDgsIY(^=7=%4)2|LL_2YSwe&>AA z0PoaY7)w%(xl_9VBxA}5bh=RZdj45bv2#Xm7pPdewGVn5pCLKDUBmwhG~Y04s4-R0 z{M?}9CEd%DqT>?ynBqZMmR^`tmR{hvWdn|uPEGo!L3mF!Bq7^Y6oaK0^s5swwrK0AL$y9kqvs(x z57=~qIQ?cs#9T>##5{09K46P@6qqLT?|L?|m3RG{U;j7#$vXXy>-0YXbohaObz`8@ zukHyb{diA6>0bmbchise1mX1K$-H6oKLw4{>Br-Fy&C;^HZP(7%G#$lq#Ta8hY&>Q z7X(TAR{;Gh!3m&$6);Wcx6hcL9!_uae?)(ZPX8L6e!Lq%`qzT5j8GN*N_;5&N_$B3 zPh$Kq?VS2N{h-$QnQN0+ujiw$hgX(5g`D@Z5=yE z-gE|iCc)VT3W;|hcnZIZ5J{pV!JBa{5_lHDoAcA61>OnqlKiH8zoQxlMcdkF$5Tn{%FS2zU05itHp9l)cjhdZ&Q)PR)oy=m>I@ zNt@&Myk$PVif*BBjxs4OP0#L}k;T5_CKZqEC7kN@r52awXJ<29+_!kAd7;gq+p%l| z+=Gb9Ez|NGOz(6wkaGY^Qkp!qVcG}JlMt-X$6yMjH^Xt#JJSmrwjTC^n~tm}cpveC zONOz8{a&uyjXPNJ?-SAUkCO^wpLQx>{;;W~+`PlQ%=P*h#CE8O&60W8WR5aUm_cln z%vS~(ncVd*h`L-aKm*yhlzw^f#=+~#)AZzQToO!+mPyBp(ebV>$7^~^yx^l@Y*dba z^Ze0rY5P-WP{+5R<2l-Srrz#eUls?9$Oz_14{WgPTCx4Ir$RHuwfyL5Z!d*%F4%es z6Mt`SLMcV9;o|d4m76{{?gP5fMdLy=R&vn~x#%Cp#Q-n3Z5Rs`7r*t{ z_H4p)w~nP;EJiL0iwa>9O^fmpo3VqG!TCUQKS#v?543>s%`xYY@<2-+a}FsFw9+x>kn%ul9diyT z58S0=&LQQ2Hag}UQXWvBv19eN5GQO0+QM~ShKX~)d72Hh(_wKGxPaU1Fnd-dbABL| z;Nn1VaeW%W#hKs&PbauI7F^&N1Q#cR3tVXvXRH}-y1-GJ$adA+_J6i{_r<6^r2FIh zJ3;C0ASVt2Su)E9Izjq#ra<)rouR+khg4M%6ztvDxY53g&yqUgHj^MoY+jU?oTx`Z zuITaRP8j5YvjS`(ZUqAQ1Z*kR<^o*^*h<{q1qyU9sj0X@4iplQ?IC2DBv3@aByrw) zpqPLxkMJwI0?4BwDFx;Lff9l@gE>H;l;F)V9=Z{nZIG1x)t%rid7DK)_8@pG-fV&Q z)bZq|yyXJ#MR2x(T;ja}H;lflyQNa)dB1;n^timfq_5%!unW|HRedD`qAvtQKN=7X z0{x-y4Wpigl@va(yIae{+q;oUVjHjvR3)L@)U@mn=7e1yAEVjX#T-xz${cidF$dI( zV;ppLv1U{jL=I|Oo;8SX7!C%o5lpLXkmN4xO z9HoX36XP?Qtzz%goIV^RL%b2N~_xa-{&O)D2y`htv;3Un~aaUw?|9{Ce+ zANf-+@RbL~9g*lS-f5Jyx7mx^NF{Mfq7zwvhe`AxO``9CM50Oby*ef(da#a3iM~(A zq(l$VF)7hQbxcb1{W>NkdKh3-qVdyT999xNLcdy*=#d0h5I84**Ui`jbmJv!`CaTt+%blW5XGG7cs{MxIDBa{a(0=x-v?d!D#(d+uigE|WSm ziRN{vv@bp_Z3Y5Ub%|CBbNpH<(P~|egHocWgPY>#Qle+*AV@SW$MGwZq(sjoS4xS- zH8^pllxVdE$A7LQdKQ!*q+3b!Y=SF^o$+l;}$ol@k3UMWsY*XMu65q(ooAYlW^ViT;Tiltlkb4N9V~QiGD{Ux-1I z=xfxVB>I2Upd|WNYETmW8#O42{+$|>L|>-{CDDISgOcb!sXEp} zP!fFu4P-E$tdO$&jg_v%sY$dpPUJ}Rz{yPk({*xFy?|xHxFZt%IGJG*qJ11{zj^Cedr4Hhy`cl4x8q7r2sWTsRlFlIV4$93|1XbS|z} z61^U-ClXzh+O=7;rhR`V9i&M#=^z;g8zCcaq8Yhl@_HW zT038mF``MdcDf)pD2Z053-UUWltkAcb+7>lchNPeK}mEiYETlLKn+TwYg2=g=sMJ( zB)Tp&D2c8|44Oo%kA8Cp`B;>9(dv`mWH7dSYCyH?Z$DOzj1x_wwQ(Xx;_WEWcZ5lF zBNN6Qk?3_hzTR?TX8-=A5>29$SyRI#`dyw~r9>Zu!6-7WBhl~an7oTVq+?Q|-`6oI z(T84by(d+f1<;hM1M+fCDBI+t|a;>!IeaRMsOw3 z#|W+@`g6dEMDK6+Lcv?xH+)MvNRw#NK{5`$gp7QGX5{*Tub{t)L=PSM>-wC_ecvN> zXcEoq2$$%SqQ|8~e+!Klpp@wE2q-1`6al3~pVmQ;=raVA5`C6{QlifhP)hXo01By8 zchTnwt|a;b!Ieb+KyW3|7YVK;`VzsFME|JcnnYhFxRU5AfRn6nF=fhUweQ_shxC;u z(X_8*KwO1@_=N^UgTOWDdm_<~%zgUQqyL;~NGj1JnpfhIXj_-)CYS>?iEc_jDba}p zloFjpKq=A51e6k;LO?0e%?KzZx;X)*M7JQIl<1ZO1c`1%Q7O@_DJmuUE{aNtZbMNi z(RWi+N_1O9h2W~Y=yuegB)UB{D2Yy`1|`vH#GpxZIyESX&Y%V*(IIM35}ip6N}@YZ zgOccu)Sx6fiyD+fccKO*(VeM5NpvV7shD_mN?7oZsO_S)~A(3bjeO6n!0zjaJX^glW#CHe+nRHFX{n1{QPXag57#4u0~qdnB1MB1bV zrP3BPD4ABrr-?e0POBr-gh2_lI!4Vf`WyIkaPO}ljhVRZNNv(j6$Y^joTr1NpJX^h z!dBZrl zgu5y=DCMq34NAJJ6N9GR>bxgjxpseD6MtbC{K1!eO#OSkCf93(cBhfft8fpA5!HDz zNNQt{)Nut#gFsym!~+rVX2$uhH6~qufYhT2IFCh_fOpjeyae-|Cg7z6lmgz3fKtG_ z6Hp3x4+2U7?@2%@;JpYa1-v%_rGS?aPzrb-0)l||rKl9}eiW4g-k+jUzz0xN3iv>Z zN&z2)s7M}4!0(|3CE)i`gA(w;)Sv|XK4Q=Wdj19&x0k1EgN{M{k0JDiR9QhkM z0d)!+2c?GJPOg+9eg^@iiZ>#ll<~#{lsc{*#KtO;Laq*C;{mR2wwquH99L4_l;GO! zb|N(>DNmvXCFRM~prky78kCebqXs4A&Cx)l{IQqQ?r(ST>`c;Qnv|0slY!9+vvg}$ zmaZST%L6e$r2PADjvr1u_-QXvjV9&18l?vC^tvsP@^DSr%6my|zF4NA(Npav!73#dU!`9fmQr2I*0 zP*T2#8kCeTrUoVDOQ=Cf`BT)Oqts9jSOR@xMw4=FoXEkr2BrMjFezVa!nh++Uaoj|;+3V7=s_l$ls9LC zF-*$4>QY{U*+i4_QUXdT??yl=<=qJ=rMw3LrIhz1pp^1n1e8+V8$sTiO3KR!uB5yV z!8IxGOASiO`%#0E^8VDIqXPzt)S#q%JT)jOpFj;t$|q8TlJZH^prm{j|GXbTPZy}(R@~s4vQofCVQp#T-pp^0# z2?$cYouX38cTiMH`AZa)QofU-Qp#VZsFdZW zzl#PU<)>bMX4&TAn0{oOXi~0?6FC?Up_IQLCgq1s7*nhJmxywPm^-eV=^$F#w@+e zm8I(kmU|!uh?MVm`@UbhzI*fr4Gguw&Z`NR@>N92SEC2Ils`jJDdlS@Dy95cf`XK< zrKpthbrh9S{v1W6l&?qBCFL8aK}q@Z)S#q%BQ+=~-$V^c$~RMklJYIYph@{wYEV+X z4Gl!f8$J4c(bS|n4wBB(q?~r143g~_Bs*L|(jf4X2jYQ9`MnKKl`g*4B%aixNja~_ zCFLLKQvNY!K26F$A)u7IPZNVCi7P*Q%58kCfOPYp`S&r^ev@(a|Ur2GeJP*Q%88kCe@q6Q`9KN5o`<(H{JN%<8t z5Gfz?z^*l?%O>w5<3y8kZJfx#con7mmoO>6X2Q5LjEM$5RqI}*;gBzT95_KLiJihO zaGt#KSJLr~%z!0cQ5SEh2O=$a@C@fL#Icq2C`7H!p>FW{eIOcP^7{REb0RU~KMbS1dV26o>5+{;wt0@8bPyYlPY>9q ztFm&tqIl0Ez+EN1p%wf%I0Nld8linR->+6;DLu2)UCh65sW6-eIp5ISQI=7z33bts9Li zf8^WtRY~D-_o5&C$SQQBuj7U|#)^N2C9)rk4!`C_e*npGD-XTBxoWQkMK6(x#BnQ* z7osBR#2|12U%_;os2O=Lw3i(JS7T?z>L;GRK8utc_YQL+JvFy1twfyYlw>5tFmNJ(hEdEKDMRYRu1nUQsXb*e@gkm|pa@=Y zdb|-)Qyh9?qNYMQ4n5VPrU4U%aYbc_ciZg?om#T#8YwvLD!YIejK}{mdYb#Qh7BHL z)Z*T>KyR`_O^uoyYKc%`R)`&i#-LURg&0(wL#+{VxT(g$yAaGsEikHbs0~8t=^^7* z4&9AV(ZJDTj4B*!i&$1hp;4Jb?GQ>$%QGr*s69gYIT^++ocdIRcsp3f@$1qMEG#Kt z=cX_y9ign;tfGvx4n`9WX8^hWtWct1b0~xmFEQD;lY^NAOfedBumb^`8I3sDk$}yO zhCGt82-w1Cz_08?z?MdR4t6GBD9V<_<+m!Xsgp_C8h zKqz&As4?^}H{Ex@*W|vQnO~8D;~thV8Y+NOby+Ok<1Y%O8&v|Vk@q6Q1q>=5!Jxqk z%6GcqK17_bNhrrI8v@NT41PMJ94WK*_Iah`#|Ms*R>U(Q76C01XBRD#@V|k_Xu^?~45FYmi0_-h;*1@S^c~L!2?t6|n-2 zi6KyeSSY{m=+Vv~C{{GVDZ(rK6&jp%TXHESyaWh$PSRnSsUOhYABu74t{OD} zm^F-5s@(ERFP8f|*3Kd2#;uX%cF0aEV`uG`u`la562y2v;%7+HGWKC74m+9ZC_2Jy ziD(lk>oc@D9F>b@o*yG1OUgXdK8GfgBed$w>wl@$gdz0tKzyH@v`|Kz+*=*Gt zC!LqCdc{P&3B@_i*NJ)y{3Pdx+4j)gBR4l|O3IJp?C8$(&Ia$_#r}7EKZwpi-#eba zhq&hXAp%Oz--o7>eqVHTR{2gf<~&PU7S`{)WzzKzA@o0j@}S>81~1v?g_&oP+P0ZH zUz+)Id)H~r^QG%qnTe?d^4Mb5=S@7mtPG=W4Hl+NJy5iYQcmzH+=AI%@Jy=7Wu#i!@U^XZwhd@E{UhqBz_97jFkJkV|O9_$t_eB~%A z<-NQ@)5eaT;3&&23d~3?N-axs1ik{c-Y4KxN95xbTvS@nrLf46`HBioA37>)*qHob z101cdq*;a!8#8M7P)F`7D?D{nKjRKge-(x0^c_9KxSfNyDlj9fz-Y*^stV%)oNOd; zA+3fe>AlU1x{fM8Zv%ZvOYc2Suk5{=*n73GFzCGm4|J4aELNd9J@VhLdpy{^kOW8U zQWdHWt1>_3d3+gt$Mh|0>hxZ|Mm~oVjdI+RE-pC9XvpCLY?D)n^t%vYlAe~u{1$g= z!aqGo!zw^}Vqqm3CLQmJj+bC*j^nkWNnR|!tKG>C%?{ZuX(jLzpa4yQ|cz-Mn93S8T z9}T0O8n2bskIuVgO_Nkoer%c=uQ~c%!(Ghr>~y0#pLDlT?m3C~Rz5|#TcM%hX>wk# zu%ht=BiVG{ncFM4;Qle8VRCw}q2t+&hM3i)DzJ!y@qFN@!u?iebSEwAiw{SQ^ z!7NE;vo?sEgph)B2aaRW?BtP51#{n|esn-mNf+(fb=sT0bq~Fp)4NDeC}Xn|c2Q?6 z4Z0}X1HEAwj~b{SrGK^Tap(V%?xtPzIJ-b*?3_Zmro~cfU6xW=wh;nS4{MO=R7l8e z3eDlVA~dAF26AB$3eo^Ul7k+LoxU$;@XL)!d-NQ{+auk*1Kn+eg*ooljB4xw&xl-p zxbN{WwFa+##dmva?{ayd_7x?DbrFmbm2M|s!Qv^r^%)@aU( z)<|a`M`xeF!ob-D9`K9E<>2E3mtL%SW-BRPlglJsF7I*4<-IgY6AdAkgDEQI@;-$s zxg4TET`q@W>xo?6uV6Wh#a;0*1-s;OxMtDia)iQBE=MX%$>k^oqFjzvm?oEF5GB2L z+nv3-_Fu4+9z3P@o+g*$u=mDeVbFUMJkU`@HICL_wEo=RgALkyN-mR#Ts}|ba-&AR zCYPIBu$0Tq*d`*ETM#BGY3Kt9d6izsuSOcCr6i|eGHhQ!$6v(K9LH-#ZTEnW#PKfM z54_Oj(5^A0d`&KS`ARO?S9iobLCWRJE)S(#?sCCWE_Y*_h+OVLm^dC>^iqvx8~*T< zhPfO^x!jMAzk;QKlEw}#>QobgaNklFeX>z$(xu?nH5{05%KBX{S zE|)4;lgphHGdHDNL8k?-3@>jy5l>Z1u&30srN!XpPJ}KcKT0u`qD1BoWy1BD>h7DTXL*0(N0Gy`m-DpJ-A_G{pVM&kDtadsSh2!u>_TTEe}ip_p+0r$Ci(e^sEC zaDP*%o^XFxu%2+QD_Bpse<)Z>xPRg>B3)D|_Hb<8$45RQ6zW~1C)|H+b_CurC+DT9hX=1S zclqj%SiOBi^%|e|ignvJ6_!3`)KKS9+gl10nJU$J)bO?oPII0%yrW=eW>JOTh`+1Q ztjy%X9Os_Vd8!AFTR# z)tx`wx_+dG6fZtlC2p_TQwdm+o*`DG+45{T-r9#iO*op!P_eo*6I4S!Cl`x(4+BUZ z-QAj*()D7$Zfi-!_~?!m3OCWSVZnJ0l;bQoSBshpjVEGp;h9lQ{;4y4KPfm4Z%gvo zBZg9R>NoZvn6Gda47?}NsLA{6cjXvZl8oxyavd#Bpq1l~xc?xaTq^k!T1s{XEGYS` z)#-81Mv{h!odJSsr(v=u{{g3OKv9mG&1s zCeq`bVs`ygYvF@yNW-wlWy7T3@@S%%s9&Hc=<#ddpJ6=4I#fPaIk9_3a<8O42T0j* z3)ls`$Jw(}^(=9fpFC$+jSiIL6=aC#4;6XNd_CvIb+)1#o14tso> zr83nfKijR=)KQ(y*nWnwA#`nI}K>@MKir2kRV@%T(JuZbJ$FX+6}}R#^*ka zoaYuc*_4>}!d1d%%$Mu}QF^FDp)tS{h^lHv^1s;vxZ$y*s+q9YB7&o#LjGBFuN_t0 zglFas&UQv{OTdn*VZ!zWVPU(IxFN=ls%gRwAYovso*T;9QMF7E1z{)(v1d}u5^qN( znAf^BANb?m)?Y+8j54^29aY=xZXP?9vwzlM@dF-W{0G(Ts5&M@qxeA*hZF3mx@K&* zX6Kh2&;CyQ0J@G_+uKp~OdwwTNPLt&!;ZSmO#bchjc@W7jdQ{DSmTyPZH{tOy zv9o8U{DLAos(}elS;+Ha18*UOjX%LFE9J(S%-G00zW>XYBM-E%s*LP}NoJkRtc}%AIhoBkK9}Kl zQa_#a#Enat(KaEOi6Vv3DRKp~Hlal}=f7IT@TRoLETM7SxP=)LO;AKpq%b-~zR0Xe zw8$3xS34MEv#s^J1s+9>3E1fbk6WM(LH_l|n)+Rhf03%zb z;Ktd^c$WzeslmwaP`LF`W^H4_0~fIJn|^M6f?4l2;ZdPx6(uiX*0v@*Pjf~Q`>+M; zTxMuz_W3C|rTd<$d*sjf!aFxU!;I}sSVsn<^kf|~rkb$814ik|^URoL!t(<#f+t&; zHQj`@FtCCrFEVR}39Go8Rd}+KSwki)bvmAi*xthonQl+`^q70{Ix}`KVKObtTA)OkR<5Rp)6wsWKQBtix3#!Kw?T7(c!T1iGZzByts0p*R<5|BYM zI{^V9&f@GuI4fr-PlKK=gMwgovK$yA(@+1Jh0jc=^2kI|GEP68%#1{y^gD|zYWn#t z`hXTW{rnCsavH&JI8G5zP9si3OUd*TM1V95r=PN6(&=;H^!HE{Oh37(L9Q+)t&ncQI~Va&_KGb^qbvlRxe%FojTV;tDpB9^X)kL_NB|W zYUT+G+%OE@blG)V#~leyX?z=9QHY%ZW#cY1=G=DaTxND^2dD3LV0(4YkinacaMjJN*0 zIZOITS?p$M3AWb7(o@RdVri+eXe>QVQOVLWL|rT`M+0H$<-F0GAGmVxHsT4gq>Z>$ z$kOUCmY%VI5W_gj29!*g<-e^p|KHZ5=~I}v^X!83j<`R}3`BSE=j3IC#2F^h9pU95 zIdS5HDLM>Qr<#fZmLPR6eTt zH}0Zy5apM$8`oF|&n0*YoU|XE2e@GrDnB2~Uh>JQNw>a6IE?4-BRGCKqcOU`nJNUM z3+W-+w?-EMQ{?3Kyh&*>bKm}L6e%{YzbG~*2(Pd(3F?@HW{5Vfz;v5?mEgkWb02u>(9{ESC2jm4J9v9U+Z6e^=F?Sb*;1A zqgtN?Y7%|kpPiSP$+bi{pw3ZuqFrXgXgo)qcu;oNs;c|19;HF1dyphGBl<`1;Ii9; zE6`ZO;17Ic`2P5d+4!F&=ko|RaeW;R3fYSU@<6@ls~Y>i+?@Su0F&1yDt>WW%VQ~# z^fajW5>#PF)n>_sSFUph*$alihO^FHHQMh1&&jzDe~v#}ZsmX%_a?ByP%mQ# ziK4sEffVWSsgV?gM+8`8C`BVqW-o!JPwgq&7&(bl<4mkO%4(z!vFJmb%ZKXGQr_Kt0j3^}-i6dudpCrx(>SDjkH!(LF<#*;ceSx7=6OfRC<3ChHe#S40^&Wv3- zlT@Yqfg`F4`f+QRA5}fjWb!`u$UmlDI5V#Mi=^<_0gfN~psJzwggOnG_CzhMC$v}^ zKBe0fV`i7Bq!JlRY{PycWQ01{{<^OASBLlQ{*HujFTh}xNjI0E#%~xcI&@>{py0@gp;@`?1J=;oa#chS3PoUln{B39r-|+ z=lWyD+GVRFm@OH2?iMOY@&9WmW z!28dELjHDPaRFO?DJ%-*bFiYzRvlqSPC+xT8ZUv`19s$8ES}dMc15HeISsGiWt0@8=3@h*>`45M zsBlhLu>sL`FNc`HU;Efa=XGcDaMGMkH z9m-NOG8lCoQ#0~PIP>M~$VVVOi?+M$x7d-hh&>I;V526hYlxQ-Z%581*N8Hdy^ta*eAURqe=m#D0@@RJS7^CD*vxQPYl`4|c;?u9C&V?tQJ;vGq=p zff2ikCkuABSd?1WnXy+G%EqaLH$KA0VRl>+(@<~42sGFtXU? zm8pSETcx228ps5*cwAxsrrr0JBh9NICYY|~IlASo79mfc@K%oihaK&$>#Y$1-ckzA zovzWRb;KZ2$4w}}#OY0NC}`$TP#c>rC}=Jw7v4IE3JTcK5Yp4S)X)+ssD}nZ!Rd>$ z|JQJIn>5nAn@|Ah(c1tiXc$Jp?GX#5w}$Zo>trbzsmB){`eSf5&AhQY*ab8S^ixK> zfBSvZnkbecy#M$yB&a<}Oxe6Ql-*Gk2FG~+MO26d3nXWS!E0!=@Q#;FF8yLmi}dV{ z^C&H1#zZ1RJDS96Av0bVGxfc`2q3{Qel}G#gWmrtetQ15q?)*E>;mSSqa1AmF-M|u zx`xu(=_4LH2EUaR5SVyA$zc3cmII3?kft4jU&?Y|@qEy-WAH;+4$L0paixg)0+@AR z_At(@>$78yQ}XhO&Y(36%#A+Xe4BMSds5Wwo?FGG;`wnMJLbFk2{(SY(dNDshRR2!b?ul_J1^aKtjg?i$qp(D zsb|NWKE5Y4YTJ%!uQCIBah#QWn;mmz%aAGNiiwd&7+6r8%hCFF%-Q?_yFXf4@LD&~ zU_o*NI|jd<6)4Ne7ma9W$KbcK#HE7x+wGY1NKP4BMq`iB%({2jF?hen3P>$r-E7uv zWXIs$o+v@|QDZyi;)$&Jd%iexXgj;Mut*SL+cB3epFCK2<=k_v8R`_<)Qh#Y&ag(t0P zq+!nfP_1E(a0Ks!Gns<6>rAFv!6qj7$i6A39G_z5y}srTi)PKZ&Fq47R=$|2l!dyo zr)Y2+9_;03Qp#Q{ueMdP_j{opvFcKfG#$Q0VnGwjYfU)`OZgP{3U@k4{x{Q#kvXh zoNTP5qZH`qM(L;*><*q2I*$E2rq*3sCO$}Nh`R|LII#+*>vUv5yLCE31eA1SBB;^P z0YDcWxOPeCh*)**&*?Kx?jeo6869w28te>oWV`9e0nf=$>A7ck?GN{Ubt|dCHB<^h z+NyN0xz0ula7SmOB>^QHtq|1MXbqr?jk^FRLnWebX_Nh-5AG&ybqy7#tui*+0vYWn z8Fhp0!EeKuW8j=((tyhMENGoZ7kgqJWf$V%xwC)fp|?P(p#*tujl!iSnNuk&YA zLG=Y5pGb~PnV1%(cXXzO!C{!h!P-4kkZ17K_2BR@oA_m-SYr>W&++&&3v-&56|w}& zf2F?0BXMzvVN6hcjK{&Vi;GyJjY$3*^*tURgHxJvci24&v#1a9$Th?Wj;gQmIIT_u zpZwgaKFI@C;ggTs#<_fwzjV%&431Y;=2If~$>P77;KmaTlj9Rzxb(@xZIhIZ`;;hr zVqfNs2~I|fT%nOq9fDJoL3C9TxW%3+3dx-sb^-L3FsmR4#%W=PW)1Rv%}(!CPC*3qxyD-#rm|V!Mac2>hm2OXEH2t^#u=( zCmF2M#P#YU9vo+9083nb$AjZ3yt~Bp>PsFRZ^pYz;ByrN3}=%+iL0-9@atQ^gPoxI zo(Gxa3>@?Ql*)rT^d-P8oj;mBX8c-G zejH!P=L4Q~5X)6Xp@Lkt4LvJYY5O=meUFDctEcY?1eED}B7$1_o&=yPedE%XVf0fC z-u=U-^*>Z?<|7S`ANXGlmds3p9R489;SGb+fdN9xv7w*Fe0}jkG^ypkXi*wJQ>W!& z@JpxV5dunDW+AB2G8;e_Epq@Tw2Zjxe}k&8+H#mQ_`hgDoqrT)!PO&Y7T7TO7%*TM zn;5rJ9#*vbx#O5$Gf$IR;&?b|(Nd5~LghZ4lOfP}ofCD^B%eM@PVl5j`50Ctv|;db z7bn93H;gjX+BW;5xAiK0asp{>JddUD*2*{;1%!;IadKO54ERn6dFJ}?tIbzEpG&H^ zDIqFI7U+a5gqG`sJV`)F$RY%_AXyBci;yLN6G94)9%!7O_F)NW?M(^62$5Urg282O zLY9N?bs;WoR;!L?05s~fWcGX%W3LM-QXE$wqe|B;Mm>w z#_rU|hjdv_Du^4xE`XlNWvQM$xJWJ1@8bUSv$+X>Djvj-=6Va2Gx*S!JbFKQ_mA%^ z_f#H9>WUYS-leLLx@7PCE7x{|hU>XcLpDo<<{JiYvdl;S9*msad10@ANj=lCWR;t-02=UGAb7jhd0qdnjP@hjV| zz3I8D@9h8o@=FCDJC_XnQs2k5G{4mMamf+8)#B%RB1^W#k?Q`-FATs6=vRDLe^vB= z3uHgejnC5$jvARUh*T7NUJ}UO&&cK*_{+EqsNTBU^bt!|E?Z)Wj9?Mj7Ux)DSFm|A zzoOlLUy)=)^DElpOv!TB!X|$a&SWkXi-8B&UdNDz2J*bW(X=a1?7Esjmj}dm9(bUT zdN52vIC;y&COMBb>IXZRz#O6TKJQCccgI)0`2Rtt3X)FYbf!3Tc1CBy=w$O+PFD7R zU(wv5GY8uqMkhPXUDBD0#klCqLj$4nlMNI8*R$}(QsU>$>BQ(PKspPtNkC_j3CtPB zBo=&fcsKdHd4An#h% zU;g`FN6tm1P%nGa>Sd~IiQctxc~>*o+5|@o<89?#=Kd+mCtbd@k`y0%P!``YJ6$ej z^1&zf6$O`jd}4)@-E@bton_4xYA=8=v3pl$5{sKFT_$$h$4p|0bCt`KEKD(c^>Z~Q z4+w@BXKbl&jgXmcw{cJItM02ZocK`zZUCqsk}WumB^X?Xl{v9+Tkts#5MvkzJs1l& z+JA82y-J6ug2leiF5n|LD>t9dVzRQ?tr3!S%Hzvq_ef$FVeqtan1SrZ*krDrA)xbR zo#0slI$zcao+F_1Wu4&n1a!Wv6Fg5q=gT_53j}00nY{KN5VQ)r<)(`R_QkF0MQRX- z>H>oAcI6Pv>T$tq3^O17rZmJXE{=r z_#%Z9n_6AmAx}iGC#H*DSfn!m>IHk7(00SfQ3Ie`)5;ZVymsGEQb}w+4geHtwJ7i> zn|`q5(IKCW4<^xKQSdM96V2v)#v%Ck&1}xs9D@Jc%;tR5A$a3vHs{+8!GCXNb3XA9 zG|+dgEzXx7f}We%oDV((O=ZJ?iwRnYy3)HB4W!pb-Q91+g^TU}B7|zarV%Q`Famom z;7aoKf{`Y4kYRjnVA^`_jtw(+P5Iwlq>|Wg*#$f_veR!izlt$^xqy8 z{=C#$Q}oLfMKPT!Ay6zS3PThloCuh5Tj|o(?3H0hZ!A(iE27`O>ecU; z2>8W;`Y7?iFRohE>FBB!`&A|9*h|1GXVB#zCyue8H@|Wga6*U;Gw#$l*klC`xz`hL zQgSjfQ`6Wv$tg+XpaekD(}Jq(9RKmG#pA)P!#69EiJfCE2AR^50RrRC1O%KFxv}ak z7I4miN^06CpctPmuT1T`!*PGaH%k53@^@$#gi+(CWAYRyllGg}~9>Y6rSvxJdeV@}dq%LoOG< zycSOC);RD8(w2Z8M^n!e!wOjIz$07l6x3tIv;x*S@QmA*g3ibJN#S}2x&+V!d?TN2 z&5|T}tbh#;+#t0l5qte4mA@6R(SbYexuv2Kd#r#>4%~pYr=rEtBtcfdW(RIR(j?>r zhwKxRV)DU(r{n5`7unH&%{^`B(r-iH+|#jZ{N6G9hAiuB=fWW4j0l6HPe-9<$>VQ0 z-|1%OQYV-KR=`(|4%ZJ>o%4S88uTcYeiUv6e63cK++c&9Ns@12D`2|=w-{-@G6~J2 zs1>lofxC9HV7j$QGAM2Z>~yS8YQO8#etlQj`Sk0OR=_uo0i*U@8MJWEV3ECjSB&IQ z$_m)!z|FMWQc-|PTLHTr^ZDLXZmDRAWvzfc4&3RXsTwC|P)kM+=yF!TUPtQ-cReH8 z-uZ>5fD=gI6qE{9z&^*mm7mXi{mldjZ2{(OOF?C^tbqNFA?KTJu07xpt1Mdz zDn}(N;DBT2KZlL9B6&7==Rqqi$_hB>XgF@=z%n<(2Y9ETo?J0jz#+%XrH{wyE3V~` zlzM7au>uY|?yTHdA}!+2Io^3tSFCDQz_*U8Mas;{epMjaI|cQ?s$m5jarpEq^XTt~ zO|xhUWpzm^sFoFQ)PXBf<>3AG_C9&UM-=FLW;n6emu>?HutS&{-A7v?%~`pb&2Pee%)=#J(&adMX<3AG#O zi{?9V=0cNj-!t+(bU_Q8=nzJkunM7L8*y|DSm?yf70LsXBm*sc2R+Z1s(R|?97zNH z&mt%8=&`)*8g!Z*2Cl59iKtyO+Yjfez@}Nzv%Y{eFgT}NzCl4x%WLgIXEGM3ZD=n>kQrzb8 zgXbMqTN*Yf*3vq`w1f}upZgD4x$%?rUnngtuqz~>!#f$4)Z?k&+>tQ2NEw# zQ5$x@gN639(=SmE``PItg$Q=#1GCG;g2?C1WQx56iC$-?OOdX?fYTF2P!$FuD6h;F z2*XNm7*?Ui3JeiL6IxH&v96AiyEhE-NMx-YhIJ^f9ftJ^k;AY-5N$AQM4}fAn~<)+ zfb%d#P;VH-+IuU)u+1BWuTWzJhF$|t-MTs9lV?iq-Y`g;-eHGfC(3Jw;Twg>Vb~>z zHW+pz(F=w>NLOIM38x~cHw>at>_-?5c*AfIHCA9auU$;-9ND3VlDjty(PHEITRRL# zP+mI>M-?K6;X6UJ!Eg+TUN9U-x&i~vtQA4MVTi^?!5^Rs2srHx!}q8$Tw8I9z9FdI z=t&JPW>-^k_ke38?HlZ~R{=!<2lK=uI}30ZEV(|JxYCWtf?{3EQ^3m%z@v-paBm)S z>yFP%C*IuDMX``~5?KIuQ!MPAf)o(RTosFW^K1ohuSI#mG=~QC4QBrUdDYaWK@{^| zEdGBK5Ji09`~ymOC&@@mPmWE2*HZ}&)St2B|B)n;c*yw&MEoB~qKLDce?TdjL@qmF zW4IC&L!BJo`X33%%8PnCmi`|JDgmC<<+05FNDv7LsH2d)?@Bxgi4PmBMX3x?#2n~3 zg1r8!rila>B=m!nmtk>djm2jOkXK@rOl8BZVdQoGN8-qEbk1a8wa+470&8T!=2=7-6SzI7Uhu z!ZAvS=mp1Ukye2NH|`WkbAzJ_!ZA+3F21iwdW2S&(mM9D1nC(E#HSLMq zqnxuhar3p;rOPXYc>d;llr7?7(@ExJYtkL8`^GkFk&)b>68Q5~%1n){9A6&}nk;vS z{?@MZYq#Iav%@75L{`a6jgF)#$cCglR8KX28`YkWQb`MEK_*e;$Z$}1zcomqDbQQIG(7oS4JV0yQn_ttGFI@@7)?{OQU2IX1R;$t(N!| zz43V89G<9(S4IUacX54Y#cQ<(m%Qq4OQU2IZn;b7eX4Z&bI9sVlX#-4UKtg(+$Ht1 zL&nYReBt3DTN)*!qLw>CFaP;(nS-Os9p#CL5hXT>jZ2|HIf`5EQu^0N=2yz!EbJ0b zK@3EuC~3Lh(tin#nRj48r-wWRsd<^Al;tk1*PYd=(2K*93h@-AN@a@Dmb;9;=Jtvm zm+SSf%u|rMk}1ks?y~yyA1;I+`e*1to`O_@Oi|8qzpanG5^Z@d6z|GY5OigV3YNQ^ zetrL)AJFKPo%25igA%%+mc;cSZfzalU8%otV5y*m`3m&y{$v9AIcj3sQ)S$i9gRcaJnZX16}D$9nJK$h9YUy=pd0741L&51K5 zSzsGaBon@qOtQE(o=PS})t5}Nur{7aCXo(y@(J~CNli)3NQ+OSYiQ%SAk#4jg1PXJ z9WMk!+3@zc=PG!xaKm(^;<>|tta!HUHC|&dN8=x_V2;I%e|5AW<-wZ))lyP?KhWwb z`Fn^*0(w|I~fRSFuXgp1Y8M=)_uu&`UFXQZwQi zgBXLy392|C5>D*%sgFZyas|nDmEn|BIB|lnq97g{y-sWBlGP$Jmc(geO~H`#tc0Z4 zl+0w-4tyk?*bGE&0Z$ym6jW*)(ZV=ff}uD!M;}g`c`3VL3q?`(kc?E6}( z)F~#U#zqHzN=9)(rAo>WKqUl2QL^udtphg}KBy^Ds7m5W*eE5Gd@F~Nr47^v0)@-n z<+p0IeEZI!RcDp#Jwxd3a-(b*sMusS%55Aq;BG$YVPFDld}m;H0H>^?TO)(6(=v`3 z*a^y!+OUk{h8T27Mtrb?Pu!Mq!oa3M@?$($7my=yh`xw`Fx+3}K!TgC;W=~pX8Y9ZQ(Lo>#Tgoyn8CfwE zXRRD^a+OON_u$*omhq#}DeL}&F0SydE^e$c>#~;dldN|tfe z*ccX^{BgcgNy@aUOxp(6|N3(C6LngJR>`JS?V-u>90nnlKi%==L_*G`ZizHwSC zjuGZFH~@j)N$K>?p82;}F6xAgy|npU(3Pj%K40JPw9njVb%+gafrYUC*?fgdNAtDU z(y@T~j{^l&)~7>{EG@ogEnd-(pg)P-k9cS&}CS{ z*GeHMJ$ua4=`s!U2sC|!vjH1j3Yex71=S#4guwnuqhiA%e8Ofa83+190uT%4nS5w* zxXpeLNH{hjo(7sE!?XD@j?R>kKpEsNh}mB-GLjOq*cW6Cz%n=Bvrqz%r|1-YlnxV}L4^=V_tSwMxHVzJ^#n zo81&f9A%K>HS>MJAVv}^t3}?5CyY2*E%Ii(ty;v*cqNka-D=~44i+(QDCn_B&a_(S zz7N#OM_4PpP#RV%;bw2F08M)-hskrFZ+iNoXV6k5-@t#!FxfaQBZCc+h1{MOdE!%P zK`=;qUQWDt-?{Ct?l&O7YU8vd=*!7FNO0|_ifp;Tlx1Wi}(Fb%k$bZW$I3! zUprkzI*%NuTb_S@^661=S)E>WDJvnCtQARahUNL!VP3xVU|ql^8e)xl82MNp5g^(P ziId<7MLLw3mgmji0nG{&h+9>~#ToGa5(%2;(Hu=1od4rQ!LlhXcv>v2acqn9#QK!! zw%{xfp_0R?uLaFpkmWbDq&${KmrPc5P>!GFF(jFMlaLq>($RAKEswm5EJvXL%Ofu% zQ`y)zv>cD+amfrxIn?(t(DJw?nUup}4zfJHl0ni_PsqHMCyyipGARgIKFj0hDAn6> z=hBNaw+Lp0L&XiYJpPXJ4>vv>-sIv+CRa*J$_cSN0gkQp#&?>s>BK4IP;o;okH-;| zSf-4t;_%8YI9*RpOMyFdyf(uuPoN`U{_yT`=7aZbT$p6B>dtR@f*jlXG+SA-LI!vV zlh2dn=LIZJUdNdS=|fNSxf5^Wiq8vLo_vlMr4u3=h9?(x5xc~#k8sNq>=?AYFFzm@PLr2G`Mt#l$i7;78Yg?Xx&v|(hV zHcO9Bqz(!m83c>6$W9J%PVmS$SWIOy%O)d;N5;aU448l?5gu8Rctl7nlXf#n;O$6y zGEYr3Ssqn`>{)nf2_i*>3q|@ePi>V&gd$y;r;eo4Y9s}d5yn$jWq?pAghvJ$Pd&k- zLcs%6bpOE5x-$M?*P?*T#vcwc8-F~Byr=Vs5Ndq<@if4S(zNTc zvKz%DpX|`I%myXnz*~@jiv@NlDzKLca@wn}HwtUg2FEJa4}#Ns`Unmn0o@8+R(tvi zDoIcJeS#CMq<(^xk%bIeQF1at+Adsihqa?eP9*B5Cnjd3)`v$72-;#Ep}e+%{iUKL zds&KMPn6^Ueu@B!X#)eWsOK}pO1Y-p{l&g1d%`xhSMm;|F)`$ z-f<{72hxj$kTZ-g;`t(grUUO?C@^wzmXt!`!I5#D;vy$!No2+Ybm$N$HtOsQ{FjKG z%h_3q$cOeta(0#?^C7#a9yvuLaKc^-_=0-G^h_}-oMI^Y38Uiraii*v*om1K8r6pg zlcpWigi#gmyD;K>N`{v^-?xx}7!~9#8bu}_7GUj7u@m7f8J+6Qz-x}xh8;P9C`%Bj zwUSYv_Tnv6I?IM)*HUl@LSS1Yn^s6v`dyr#sR+@vA=iS#(-z@rhxssg3VE^-2~Ard zN6lJVlYi>(8gN(1IB*diHEDEygvU48B%y!_GQRTR9kNwPG4Yjs2y7 zVQT>PL+is+x8!8Nw=qh{8N@b8oAYfV7_1?ZMVPO6dxv7qyz+cS$6~TKyr@5(uMBs} zON1w7NmcmDkf+QfNiF!QAx~qdr=4%65CMbsllmkF0KU>J=xYLmPWJwNrBMJ*gi1F3 zeWg{THcy9Fr|6*TD{X=ZQkjmpzQP=on#WfWlnUY_E~_9`^S*6(&HJ`R*?G8b(^PD5yX(81d_&MrR!YZjf7ar2dUAVyhmv7~vM7(N$2D zef{?YS=nIRIPLd(b3QD-MJb+bFv{YIYEGB&f!N#c?zOjH)aaq3BAT{Y+I8gek52FH zF#EQWy=NP-YY6j6{2@`bB~G8jw5-Pb{A;PW_(7@s=u2J)p;UhAwOmab!?yTWsMN}A zgMXz;t-`kVSE1+D0m5>~Lb;YuX;LW>{2^|7)}eIOT2=IlnmkkiJ*@;TJQANO>$8 zt;1dD_-y)4n7_QrM`YBM=(A;4aV^*|lHkd@~-kQPC+bnoFcS zz=?%JW3u_c8%&&#mXUdjiT5J&CX?Vr=4~d?i_9BMeJ?U^H4VJTyxAmqk$JmGmSm1T zd0V5Qpn9R-NH7%icOF<8zr5HnWyM+_sID zDuXr#%4nrBXnUZH){;TsuR@vxWwcQlRY}Q|(N-{&8YuC7??Qk1>R<6Th$ z?Q_&X2OYuIv=CVXn|H>R`+481hDzq1{IUkbaIp)9i}=_yZvDGOM@Ff<0`{m>UIBYm zDzAWjDwSLQewE4%|A3@2Qzk1`GP;9~2MMW6GX=#h`*=#h^*5nfH(t%*LT;Ez#a$xhL6Ja3532Zh$Y0+x>H+NbodBa8-Vk0|*pPfD#3EUd52tk3yak(mK z3<2t*@QX@~BCXQjxTaF0+0^A%l^VmQF4t9RWj1xWp;D``smo233Qe8Z;w?d?cvlm6 z-xdr7?@OyTE*<86x>~`+hPP<{cLm7cmDLZm#lHmAYj}Dh7z#F%reF5`u*GmS^pFi3 z^h-AW7T7$`fz1mi!k}rydxOuMV#Z(U|6{8Ok5p{_gaoXe3U_4VHDHq_u=z)bN~s*1 ze^n~S=08cbwbM5$mA6w(j1Rn>!ca&D4u{H!Au~0~aH|8#_ao>;LU=P9e!5R`l$eJ4 z3sEVRqZuHn+T;K@h6$}NT#c>C(g;f1)f}({DA@p=M zLIgsgIS>ld5e%g*&Kvyjc%MO?$0&K*+F~^^78iu6XlxT~i{V04O63R@l2lv&S6HR; z{;!Big%N;^3q=K$qAADBVuGPy)9|B?gWA35dq$DphD|k`rz{N_!MX5-}@Z+Z+HG4FcQE3@VP@80w(%$xO| zH@zy|$1?7F)2lHr)(777>U0y!c<4=s4F&4F`X~p3-3B%O$iaYanyCC(F!VGEU1T)b zJ)#}*pE-E4v;HdwuQFL&)9;?-;K}vGQ_0InjBiX1bYM4;e)deVQqmfO%MjEFW&AA} z4bqZRfl0Q8NYzmG^W50*I3s7jkZj&`_%nnr1w--C{q;fE`HUV<)+vU}d~|Jw%op+h z2&cM#y`1Wb8UGpBCX{y*S|4s6{?jMByv|R+pPV$5%;d&!*BCO-fUvoNJ@deCa25#s zsQX`K+h5J@z1E$Uo-|Wpd3Wiy z0FHwTOs#KFvmN~+KXtK2L1VUnf89cJK!tjJ=kMA6J7-V{!L{y7v*V}POG?c-agQ^o zehC`}y25iMSBfy_-vDveDK;dVP`WE91^r%~6o_W*jbi~m*uc%Bk zJvh`YHHD)clZpBzfJ@ynQ_uMC>YOoUF7u3NU?y;?TWcJin^7-?*-=+S3oHb4P+@Y&0M48?d3oj1K?0 zu$uuz`dY>&Gaz8w^$F)T>~yhC2FM><#%A-TyLf1yvptr%>|G2nKe3E0X5R@Vc9!_O zTTdI4>OasjwwiT2F0NNIY;=MvvvGP9=|h<>#vsesX1-YO`e%0g564sCsLX>c<148R z*}$jIQ-Se+ZQeS6f6*7^w!pcV&B3D5-S_)${d|C_Ha~1-toe0^-h+?Bqbr=;S;+(D>}Yz_iPk-wTCbQ+N)7H$uj;JWU)j)xQc=!~9u-9V!9C+MsOW0V2{*C++x83<@|j*AR# z|Nb8FDu$T>9t2s*O*9ud-@Je&o0&ZM; z)~pCpVz1c~D1cJ4=trb#^DY8!E05RgX;kQY%nxh!49c$5Y?;`}_pk2$7`yHH)HhAPyrC-(qH1vqw;8 zP5TCb#%ql7>9T_UbWs$pdL!%#0Z~=;Dz*5jN zL6IFCWk^@>IT96b5Oir&%AnpLkRdCB*Xb8nr;{-wCVgSg6ckjEe&ZKwFOBJcy{wXR zpiO$|(lAt!ei-JDEtE(<9Epnb=&GrdVV9oHwMeHs3Z);78KLxJP*6=u?8kC&H57bN^}l{5ERO^2*{x99Dxij4Hk9cAQ(*B1>>c#SdT3k7|QdMZ_SBg=JW z#-3jWDj8$dQTI-4ke-F8CpA17ZH?(e4NpW{Q>qUALX|SG>R1`v@RnlLEkj_i>XxIR ziu4t47M=7{`))6lobA#}!<(*1KLhi(8{SMLD$=9Bt5SwtdSQ6@IF@HFW`xquLqV0e z+aYbM>`r*u`>~R9U}udQ9yJ}rKB$AVCTe>fu>_PK+#P~CAyJWk@yetAQxE;5cDN`% zD}~!mSF|1BD8=Ou>V~2!4impF_A6h$*PW-T{Oy?h>50vS^i@pwMc+mVs){nA;IQu= zR1JwrUpu^W*wwn@f9|Ygk9{r4o{L=*#TJgMOziNW+9;u>4FIY52;@08Xu_6e=PxPw z1`c9k!`y}69EJ8iz=Z3NREa3T0GJwbn7HqH~Z6Qc_Nh%GwZ(hGse^fpY zrWB41nHJ8q!Y2xYh9Wpjt3pA;PywYWeD0X}a>CS=y_JlyDcA>)peDQ}#L^KYNOfak zBS?^NV^W0wq1Jnk&b=BuNGSt_r)6;AGq6g8*Afcf4CPdWzxF|scVCSjvPsF=kBo9Ygm(8dHQuKp_E}09-DCxI;;hGJFEp|qnw&{UK93I zviR|-n{O2^qhuU-2@*ix%r*dA?x2x*;1_8I4l8IBnl`zRz?V=!9*wgLLMCvM1*y{t z8iTlVdIq8ER?t{fiO|_l0}R6o8i#G3Fwm{t#|j#c!w8{Mn}+nJ6*K{@Qdx}cThJn9 z-sR~0>S7GFWs9-l5{5npvc6cdF1@k}!zcnn9Ox)7Ma^cnjR;ZR*_ne@Zj$RW^b0YW zGev)jwG7_C<~;mD=`(mP%dU>20sEf(p-T(8R<|-yA2%#LqiD zkzMQ}*N4sV3adV6kvqhuoB}fF@H^u3YKo~K#}&UMj)UezktqnBkrkUp9rMjef}D_; z5Xa;r3qYr(<6cG#)QeFhFsNcjzPx;Ce6TYB%*MV{>b=5Su-HXM?>(5ql z=5+;jYOAY#N?q+2g4*lqfJ)_cbx=|h;%KI#{JxiqOO`MQTvSI*BX zw`sd>L5M0ot1D6j7ygV8{s%AN3z}ygD5vs*$BL%@g9pYOt*GQ2NM7(rh?mZ(JgxRE9j&mSJb{gbRp7uB z!OAv@df&h{ia8JlP1`B4adp_~NHf+wP%`!qUns~}I-Zt<8`$zZJ3^>sKhL%WcxBko zb4puOS3>3I*|t!wgv!seW&Bn|h5I?lxUC8*8|P2idvfr8Rd_^2IDnNGs8q;-$~z7O zK+_IMRMxnDIeYcXsNE_mM;I#7`>T>eJ;{!gxUds$ev%y}={Bp07F4}iMjV`m!_`rG zxF;jAa&v;Y0%gc>tdv1fql_vdD+QlxowIgMt2h0Yq6Xq4oWQCJd}`#tr=|m;(6osX zpNiiF|30O|+b$(z4;-NptBGdao6~L7arpF06X*POg^+wGqG#OoR4N?Nk`^VSucD^h z65>R1Mbn+yxuR$Ot8rZs2sMqSogs7_i9*x*IW%qHK&6!S(V@|R%MowNsB2qnAJW&Y zA$g=qc*HakLfRd(Q&cMVFKVn(x$l)N+$y&i;_o2?u5!abKR_9ERY4`=kMU-e@J>r} zMMXHJWe8LWELDBDLv9!(6|l4A-knimHKIO zKfqRAWbPno3$aR5bFWlelvPURZmG6FtCY0sCUVMdRGSmthmA#J2e0NsE1jqo1ure!UO8k zJL`S>49fUG2+3zqwAIPrs+7th@1dsUh<~V3D>L7to`UM-i2aeupj{yCq4@E1 zG6?L_aiWjPs45(>`wE7F{P1&YU$1aD+87K@eG$#Zo4EN*9bxNvRxT#RY7oK@Q8E6cKxpIVPHQh+{4BQ1jpvE z-Ej^COF?kXE3I$63bX6yilFoj`%)|^uQAAKUo6Qmk z&d!1090!7>X;oyOduVBD+`f7HRRja8v(_($+<_*zmqcdQ2e*^V#?6=^%56#DMF}1? zN3lD}zH1)ejKL`*ztC?8odP--*Uo$khDJIYB8ar`_>|a4=0qm;ENN=)|3A#0Ix3r{ zb`irC2R<})H1i)DAySh{iD7}!Mk0|eDxgQ=vx8AcR~8kW8YP8&YBYOCsS>`Z5VORw zxTqNCy{H(E$ZOgZSsl;w4SC*VxW{YvVLGjjD7mPZ@9=4m!QPrM76^+08t)Dk+G*UB zzqHfX{kJB>YRYb>_Y*kiWF5<87OVrwk5)7ay+#xgst8gt=WZl_ge@UO7bz%_=3 zp_11nb3#%N**xuEn{%Raj48Lng;I35xt#LM-- zL^H8*a(&+Y%iS|VKW-+Iqj@CTG z+nQ&hDw;M=T65JBd9Q3Jkmrt)Y2ZR?&2m0J$F$u?m7B4I$n_JOu{0&0R?J5|D3Q-9 z7AQnMi(9A=`5aE{%+k;K3{IRdQX-$fEml6~_fVH8M7)N&RHgD;sN%Sh<{HT_p)MC` zS*6iCs4EmAzk<3_A%g1{Z5Rp>dN4vs+pEwwQ_XQrT9NjuLsDZ&Qf8&c9NKyw1N? zh`i3XD@0!BI|PwIPOp>gRET^u`9>kal9)`{cOj9Y3y||}V>i+jbjP1fJX_>vpM?q# z99^+W+K1@w_eS>s0twf=HGyvClE$@f&MeSK$uw{qBuI#tE2P7w?fRJToS{UH?hzE3 z5;?j@1(Cr+hvx4TA}plIlJOW4DG~q=M?&~SDM%dlDZXt-p4aNuA4fv0T=2an!|T1K z{KogFG_i4k#Nl|KCx2~v++9V&pmrv2=$tj-l^Wi4o}MoWWUB~duOMAP*3>_3Q(5nN zPyvA>D=zI^LmT_m+s3XVhzhd3n`u2>e`ZE0nFcas<$CazDX!t&M%jSGas5q@m?_c8 z^c{uB=hAl-BEN$7yF%nQ@a`!@egW^kLge@FWDp!uIxO%AvJWvOMYfti_7Tz*WD|Zp zpVsxqA?+0qII?2R_a`Fzmp8Ic5JaW*)_C>%hi2O?hm}lu>y_)hzfIePyXPn!CGwrW z7YdPY`Mgw!e8=aNAhLR(t@kw&DH716dF%ZL>B>3VoYHlyf)m~?uL#Y~+2Y08?F|M| z*1YCE`C%4^YHQj(O|;*xGlw;qd1k)qIO2H-2@>Mv%FS@tZ`jG0b@m%}GGra4ayVRK zF30x;X>TS&)$x4`3W$tTM<;~x-iC}+M;Y?chM<GNAGDopyi0P!5hWzj|wY?46YF z6%d27xVC%-87O9uK{-&&>p;NB@smLD`;e?&1*%=6{<5MG23Ge6UP5}Rj6 zLdakAcr*v=Sl^Tdaca1Wuo@A+A;Fb}iKLmIhAeP!Nnfr2KvGK^^JeUiM&3w&6xv<#$*F2mHi_L<~ zZ*yVsxv+U8Hy)c2n@4lwv3ario#ZhiA`@ftn50T@W9Z7yJf0g5?k|wGgjpto7->w0*XcKkxO4ACl;b zCg$w*Cy7FG?e)J<*|OK4?8T71{uIe!K+|4-s-$}N`qNaFcdtKPvN_bG*PkJ%O0WMz z=~C{WUfdp~K*4)`3I#`bwm^A~$OwD=xjF)>wAPObPbgCB=!eIYta)pV6TJcV-ZmfP zY^}COU4*UiUf=epi(v8AYJ1d0uy|{=z3d`bytUe%cM&Y!T5Zp}2o`Uxw#Quri?>$W z(=LL=TkA7{psm&M)@pm+MSO;>Rlf0J`;NC(`OFKSuF+oqWo{+$*7_+b+>YeiD3ZnP$Sp*dEN(}>xv;n$<;jJ`?Z__| z7Plk+Tv*(W0&-#D?7@>8kN5h4x$(Fi*`8Hloe{Mo+k+|s!ANdLwg*)tkK0j>XI029 zn<<}FQS7Mb#mRfp^;y-GdPX}E^~~)kKVEk>3kYq{jtUxRGMctu6Lb9!el2*qYpnw6 zQH_WAmn6i)W}3a<-#`LIq%j97bE7bOAL7Evyhn*1ngci$W%` zE9v}dt3sxEQ;fC=x)Rjt*?^RK=)`T?Y=(cG1vwh^!buh0UEhVxa`J`Y$`F z_9Y*`XG-QYs8vFIeLFl0;LRqs5Tef}EEEO!#HGYGX~fq#UwV;AJZiFtG#5!mS~GCF zB`YfGVY^r|5)&FE!fiPEObyurGM7jm1Dga{HkV2&`GVp{-ENnu3~<1PCq8r?K3T4E zGBRT`n`LNlFye2n5G-Yk9MX8tw#TV;izvA8F_PlKAzv*ZUn4TYF>^)F$MFBttXZd6znT>jPfoB7WXwjwNeTj?Q0m zc^tV{oJrJR4(WN9J8D#V*0#ym&DTgkcVrk=-W85DyGLv`_xco7JjrKtE;*>x6yFJ| zCpk)1pg0lqtX#}Z8`sq@pnXlR>tq+`Vh%)ZMbGXsw36<;`|`jKxT@MHEfwOpCW6IV zdG|Zs6g;(H;lAd^t6~ZMkIlvE|zaEhHV1>MS`(CTN zu@d3ga)tOCL~+x~dkA-tWXu7#mG>|{yhpwRP~k2Yy-OZs<^5KCAXxM=bv`Tak(?~J zhf7}H$$K;>i(V%Wv+{l?SZvsY4+>a$#cnT^fJ$4?%6ok0(m{>3tsnM+P#dJj#*u2I z%y293iM!1!wkomX!*yJtxK? zT&g{{g%QvrFKPs>9KNlh?Da*gpta-YF9&^HD|+q;7cg^}K^w<~5jS7nAAY_YVSCv@ zTgQNgr>9kaaOyc>=4uG?F=u+)oz^K>Lbd}H|bxtXD5$ z4%AU+#nF6ghZ^+@eid*+$vu!>3P_A=)_`Uxp6qeVS0GWuG?degbPg}m_2)#n};@!sjV(?xxR z3ObwYkU61IABkS)4h@j5Ocm=?pFZ%vk*nvZ7DA_rwrV6c0zSA6@g$}Zj$q72iWw6?l0oaIqkI!T+*o9vz;w$60DOa9wq z?$<0n)|D2Uo|&9LM}7#LGehsuyv2-1#qO`=3>qZ}g67QBD}4TJ*8SGnITzgBOQ!LN zAZX4k5h+aeyYSH7Y+b~yfh!YaFo$RM=ID62!39o(gqRNk`RM4J1VrA`8}oGZ@c<(4 z;*I$_IspKYhK_-E_7>=Pb`3;W2{|L+mA!>J9^(R$#$PE6!FqH&fdnFrmIH6@Ez`1B_#QRyJ zqcbSUg6amre%9*f;7F)cISBN#PDiIbphi*UAjr>p9leQYaa1;l@Uua0usrqQH%TwX z&<6#ZfV&TX@h*hl(F<-GQ88fmqi!@kmAV52-_hGWuKzNtZnbl+`Viio&mkcy&t|>< zjDJ(ttUj;N^t7TND$f>uQ=b7TyZvHnxX5z_Bt{KLq(=+~bKa`Iml0X(QCLbj!GqHE zh>^hCrUxCH7rZoh-x64Eup0&HzDGp_Z1srGfxbgRjxvJydc-8)?bMs*JK4Vb!Z2TvAN_7J z@V?Q%uRC>G{11`vnk3f^YDSNk3cOuO5$ zLBE*^^gTJ{AXcbH%m(IOz3snaTa=x;Z#VsjW;Pe-`*Qh+qA?$s`}Lg%%C1XjdZe0= zf>@;~s-x~Mq!ZDg7X$E@4B48ZMB})p(5?~(EwYNU2*6~%l3G6E>;4)ww z);k_LSaQ;vCAtd-HpuTHaK6o!<3~W}9_!T(Ebqw3eIaHe)z&W8~2vW|Wm3s>~Cv^k-R*?A&lOTE`aXxv+g>xLBfewUb37Q_C6iw363k?B!;dM<=dN zRtlicrr4C0&Z^aj(v_Lg)rH7F16L-ZbPYkH)fp+APihK=qTi7}Ui{L2(Sd$S@!t9g z2h}=4zq&c}tLH*hG;Iao!z=Zh#hDMEySfii3h=Ck1UCI-oF2G;=63nmSlqeHSBP(C zvR!&3k7RPoCJwrOf~s1!;V&3U7>mYVuWKC}RZzXf8r(4#NqKDt3N(Ve(1N#A#GjUxw3-e)f{zAU9Q4Q$b z<-14Q$2HrHKCO_T80-2tYSQE#KW( z)o!uoCt5lz-#xfJAa_EYmhWCf7h<J0vPK(dufcu_f>1 zDWui}0?ulpCA1daqgA{9alN#Gg;YBaqzmWtbUr*e-1+L6DOo9Tw5QG|w*ykLlHzDj zolk59Xj;0=Ja68L7aU)I^0rdVAN%0zBqLpjriax=6=pdrf5k*0_|ID2RCx4%tMyJ03W$(*Cy zl6QdlT45$Aa%+@M5jo_yIzK$W=X#l|$P(p-Hk2D-&Ok$v#RGSW$kz|lDjl$^lzMXs zMHVRI6PfwaFk=+CDN3hlFEnAxZ}pn6D0pZu^~^KyH6%#*1cDo-rKe_!TT#w599)7N z{?4XYfKfjY9)ct(vlHkhADK=$#nX5OOvAI%kqv_tWoL-5*+GcgWONa6%ARW^x#&bc z6E$qlHIm$UqHIywbOS7!xHD3E7M7-j5=mV3{7lKpm!~S#MPG@u=}t_+>2kK>rr>Oi z(>jK0QD+;3P}9hyhW8O!sSnG{O+9;C$vbcz#g!b|C1j`&ru~urB2&^A4>(0 z5~on7-0ekj*`XEl6M~YM3JB+?mMdcrp{qlx?(m_Lr%^K&iiDdq7ye8 zQ69%@B;qwn#jB`uG(w|1Rnhai@xQ;>+9XBEJ8+-COJLQ50+Nk5$*`3~f^2wvkjx65 zJy8Lc8u5`4UubHyBoXrkn>oQo1bp$rrVnPVxM6>iP@~be6E*~Q< z{Z(ATou42Cnzj_w#^%)H;>j&FF6>hB4J50Kgiq{i2WJ&~W0FG{O@r!-Q4AuP!5g}$ zzC3GST@r0b;-tZ=A&H{~Mg3p%pZU4N$ltmuVsiCqSzP@(sD52<_3LGEO%<~^UUHoC ztLyPkm3+BbWWw_k!Yr~)`V-88_9pLQC2=w|0@BH}SIK}2@vd-o@FK&~nvgpRGH)`l z%yf1_qL*28M!JH_*s^0{-d@m84a~xEp#pPU-a}lvdE@dvLZE3Wa!$PIag`!h?lmZ= z;*tsp$n7^=W(0qk2VOKLN9R`XBFxwggtVj#GW~Q~!HXrCJjDh?!wOzvC(=o&X$3E} z6X~qfZ3Qp06Jc6PBK8L_7es~|Q2njo6?nw#P9(7dX;~pw@X9-d5A^DNqtqlurlo~i z!K>0Dk8eGA?b#C`CxVXz$vVsmUOlvSOU-+*;SV`^lkCAG?9^=X7zJ??3LdGDA?OI~ngDr}AWI_; z9*sohz7FE47#+Q@!?Y&0>~IB-^HTldCDg@<3Gt^e3_H zgX)=)~@HeMYGSRG;_#i}DbxIQAUX(T8Mua2JU zC+({;p=FkmZ(syghnUR=C&O#rO)|4#B9oECjl7{y0bT}5%g#!N(2QgUHdxN~;k}^r z#&iM~ET;P=?WM>k41M{YHMuvGoDIm4h!??4WcEN$B|9p#rw&e)j4bjA16r&ENNr`u z!mV!_BOq8z;7vj!wMbn4gT=%hX91*A#B^Q39y=!mBZ)mON`jjs_F^86*tbBKHEp0K zu;2W&lIu|8>%S`b27U$!piTjX*fv?|xFCQaYXA*-B>vR>&HzS;$)K?D?`FWF0D@X=F9Ut?EtcrEVo}jr5w| z{YNz;{kv%7tvUK6Bu#J|l#}*)yn(k>h`iHmrx1CknXM3crzxif_D)mI41k)Q*i`nL za&o{qqU%)W2W;;>Sj-O;gTY}-g*Hp7&l@X-vJQR^MMs0_h6rk!Z6IoX;?=zDQVqkD zeEC2GeyBvsQ_;=etB&X4~fk;lGZ3B^$6+*g z@;Dxj?$`1|Czf#JlUYxRg zZmC0scEdzo+>6sW+=+@P_eBCmufAKXf)T9bPVbA*+`&1&N&RHn4QFV1+|H>^UrHyK z!cx>Z&57WB~*j{M6y5d94*otor)E6HcUYFl+zxL%~b zjD?7EZkBbZc4q8A*SSUVd1nRZna-_(>Sf&91VibpPQ{=7YhuLZ-ioxMvy#$s6WA_H zV276plyL5JqUuU#_57K&JGTF>Or-?TSw(quR?C&nibJtN$Zl`PD+Sd{)m4I_bXE&D z%pH)Jy0DHSi0G_P5U%K2q3Aj{y5~kIq!911<5uGO?jVFycVgnAKqs7 zJJEubHf!zfd2DX;)`itJi{i63TgWN&+PY|L-aiw+tf1;u6cUg!*(O<8@VRjK!Vx^# zBy*XLJNf^5oOjTr0yEoq*_Dw1Hw3crMNgO8Q7h<+ zW}EZ$MNT?nnU>4fG2zmL?Y}j9e>KlAJ_GJo&>bqb<;vsm(`Owkb}Fuj;6`(99?RwD zc(ioR%9sr7~)d+Fr_Dz6>hom%8MSP%c5I@g)LV;MH0As z0ngDiZUQ?*&WNIxE7+0$PUeEsQKNde$m%aWHj6NdTdoj?@BRN~OzAnQAZ0YpfFZ*f zQPOgSI?i@J9rOLE*+r27>wmg0SjuvRIYuYGy8Ye8TO|aOZv>XMT=^Zv-fqcNnc#8ZH60zOxDE_a204s1<@F}o>%+we=7DE+mLD}pfg3?7 zQJ5k9u8UwRgTm{jr(NMq3r$vZW^+8DGlSFYhAxTb`=YVpO`Q)M2%e^u@fU~&4Sjp^ zt!WL0DY^TXg9HRo)_H0Uw+RnkW|D9S(0!Ukj7!BDzTLdj@|iA5iy}=I=tYe}^A6N_ zu;A27*;hF&vzQ_JDw3S`Cx&GfHxNR|h1?Q`OnfY}gfXbz6|K>Wi(ktA%e2grG80l0 zL=ZCVGb4<<)y4%KEMnepF*+5-*D^~Pj?JI#Nc$`Pl_jPcQy^3(R-YWD!LA=y(n%UEV*W66fKwQrPmw4oW%n+|0y zvx?Dk*XkwRBUe==#d5XYvCOJQnJNcM)-8KwmJ2rA$+cf+gk_o4jMWo9D)fWTmr*nq zcJHI2WmcEju=YjL$5>_!BlV9i`8FkV8|NZ)rfp@*tZ5{5d^UGqyUrC@KJ=`rie=W4 zl_I(ol2tX!tZiU(WS>yQYFK6+2`DuP`ZiWQ%dBf?<>yAG{5miYECLjZr60svW<8^O zh0n)Et{e84G2%!8ah4ftTnjsqKDcOhGN;oI;w>}IC{X!8Vo3JxA6UuMpc5=JUfM)# z(+qw9*1$3ojGd1Poqh1r+LA0iHQgl3Oq9(IB*G7pEwjEce_4l}Up`Bi%|4(e+R!o^ zNY(KD8W1(jGLsB^s|MN(c`XLWO)WFoz&Buk%-$vfM!ID-H1HiF#vti4EVGe;@B6TF zsj+8TW{M#^5}_YwCz0+h?bJ(eYRobQ{pUC#92oI#^~CsTgGta!1Qdm1H^$ z(7zT{CGNa5^a6zAa0(XGSc1ER6*XFHBU)Pv@0_LVii~vTq z{S(@>>BS)PUBl68k|(xd{vV-ipo2_$#3=Zny^;D(>VIo@7x|ts;3h0#!G$5SgHiru z(ca;smUKWC)Q}!A23Q@9!#B@0e6`{6yR3ZbCJ7gb%ucdX$ZW-qnDvN>!02pLUfpa? z;RfXzvM;C)C0rFUyV$>=r_XxCG@y4iy5C&l>G#XMU{ZP z#>e&#xXx>U-rv}EIKI;H_?GM02h>d00^<|=2VCcMKp$ZIKE7r@Pn)xk*ay@|*8^jq z{R5cgGc7g%=ToCf?b;8L%Jpo`KB0EC5g3E)pFor=_Q@vTd}c)7sc`q2e(f9f2{o+E zz!+@*1cqtiFvMHL7GMuC#;^GDuWzbH8SFc1DO-UtG?(uPnA?Ci%-C`w@L087n{Ts^ zXuW?0jN!)D$A_-Dv?jAV+#V!xX?SDZ54;fuUjJqv(YikXjFGYrfo8{LI|PhT21ZAO z+}J!&k2nmB(FO+4qFKdItN0ceW9(Vg=UE*E##jTxi9l93i_sJ*bL!@B^hK6~7h zD0&Qd<0S}!2N)9eabQnS*zml3LTVP_odDkFx$yX>CxJatvPlmdLk;y5Fecem07*%H z-vj*%uMeo9o&m;W`v)T4ANlMoaHkj;9uTyP#dto1dk(l$4Gj855XR_WgnJ&i(+mtU zMY#5FF93JCfuVy~CD4WdH}=dKMwQ7S|N0f^``DEv#{@m%U*OG@T97#-9WC^T|9~?~ zaFm5~zUI+?2d7SMq%Nd!0l^m1$8@o>7@cxsw);R+m$I_(oP-2)WzixoHk~am>bXOM zbzfqlF^!wGsFax+S((n!tk4j>ZrTU_e-{ZD1@k|~j;xZI8Xd{!a84^UR5zdJIk)o9 z@F1F`vXTSYP7V#zyBS$cukWw+RHRTcF|E-2`t8}*#~R%k)JX`7eJCVpG&8BJ2nD-(Y!G+dt(v!zq`sojl53MCVd6x^Bd+ey>31 zBa~07Px4D!p=I=^Jv)s*|G|$%D4*1f>18uQ1y9)&#$>hwfy``E-;+ixScWSb3I{-({s2K$t@ADB(HWSb^( zzr~X7u*-Rxrln@kuGk9u8MlDkgh<9lBCOL2yP_}}$F?AJ!wS2q&|ykV=%y9+i$YIM zVR50{R@gO#k--^xtS}MRoEFXL{#Mv^`9ZTx7JkTMh25}GiQ65N8f1mtl+>&Qo;aTs zb_+K-+)c9*chKBdu*dZT8?xvE9_4j1Cnz_ zaVzXEWGLo1CbG++%>ynyP|Xpoj+tXeX}x1ktx9lCY?rQ@V;4vOaSyV={&3SU z(Ga&|3|Ct5laGDSJ^c5syXGm`Q$Km0Js7q?;t9S5D|rlwr&xWa4G7XCC=kyC*M`I2 zNc3{CdyaI)#jere(FK2=u`*f_leyTj3L|22V|aze@LDy7q9OmFwwm?|0OWh%^P3zz zk<#*Ftde)&zmR~a30|lo+7CiC++(>5+gob=8=%R=uQUv|zh+vYB;Jm@b=tq&R zw6TPSXM4AJG54IJy=Y@ZR}SlOg!P09YoU;nh@hsu0n|9Ghd1r(erfW5X-dX{PIB%8 zu#h{S%_OoL&HAy)DcO|(DdNBwvI%8nbO_JKOlh;AqoFZ3<&Z6c!EFqDl|r^6(crl! zk=!Xr+f-I$b`mLovc3{5EF+1yLQ~$?g2!txfYG-jUDFE5qp#49F5K_%PmO^p1VvQ{ z>|M?G0tUGKoX(&)gINnGD37+R9|R9YO`%M3G8S@HFl~^WL!y8LOQQOnSJ?my7Dm|@ z1RKj^e1zws;H&UlLb~FD;2gZ=NzE}y{S|mZvcZIG7DC|R7I+ygP|R#tFJCg`3L>p^ z8ouA%ZdLG`q~dD+q;Iw5&-4BU^WLRechQjDXvmt@6F%kE-K={){p#zYy_CEId-J?A zli;R(Qfdl+0o>^h`JHwhg3d-m@qUWeXegdgQAUFI`|G0)ocZBDrN|H*2}IV2)+5yD z4^^WQA&*gbOHm1Y@9 zg?*e@_C`fng&0Q|t4mv`pX|p7*dy4m{6}4-!dhgvc*N&?IwKFv|~(br*{F5P9Jt z@P|6;sI;ZsqxF+-wr{VeRf^)e?7 z%##TH0_=ecW3Nkqr)99 zp10&gp;~>B6H~2_*+54vNX!Y*L$*&ZcVNh_-@FXk4-$|Q3Za(^^`f^)O}EINt3_{< zn!XA-ErV>NliOov9?5_jXAE+I$@G&9h69;soBonY41}zTX{7D|l@4%f21)Nx=;W+Z z`+szud7MtwAIG2B8IQ3&T*kguswc*nv1FSuV`uDHLbfP75fu^=Q7E!Ysc5l;$P%(= zSGJ;Pu`j7;_dEC8?>XQ5{Y<}qdcFF*pSkWm&-tA1=icXj?~QczJW_W*@Ai+y=C!&= z%;r}ZInIv+Xe?-u)fL#s`t=J$?r>h=?|M6tK+y^pS})_na)^gFD&gQGs}UeM9Q{JTKvDbX6~f&PP$ z_fNQgq@R}lClmS#+%M)YR_R{}#JKzPx75{6>7w_KkllY-U5{5E|5xg!Zr!!AaIpE= zOpFsbSZ&g*+mZGgh=OmRNNjYJ8SFq{j{4>(2z+?^?+5Q))LC}wC(PGht)7wgJ7}yP zSntg_vTzgoZ)m_CZYqE~>(q-8Tyr;*K>vll7pl1h!r$gcFnQRXzrCHKsn^mTcq_Xl znSC5O$=Xu)Qd|EwfT~hHqEw-I%z^vc8jea^$DBZ+fI`4NM zq!y}gM7W}nVRZ3ymc@VnF>2G2@u$Q;te?)J|6w|!h9<-}k|DlusIl2|QG(*Xt2N=F zR(GElTg@|CA5LbyrcKo`*&F&o&0^Ekll0rS@_PS6+$Bo2#=Tr+J4E52viP9fm5=TAM>_BM+@asI57QKwuhgdvx6we>tD`p-N)gd8Vrm zWV)v6;8|0BSC7P|saHlQ#XEoQVD^;0s|fe7?DKhIv)VRu|5^v-P$%n)$QXZo($_NZp1~ z_2aW`f(ez0h;cRTPql37izj8RlQdIHqIwU2cm1Rsqxvnn>aD5AqU$rXP{>kZK!h2EK;Q@uO}mG#j1070 zB3+a4r5PHys`QY0S7oE-4OH*1I^p-mrjp%jbIsNpn98izuh*uYzL={neg)KHhJv9a zhVGRE_mZA>L9Yq}8nQU`@noyQkX5xnTnBl-;*Mdxb3*61ZpF|;Mh8WMR?QAtbr`gg zp&Aipd_;Hjn6IDfu(U#j-^5pv@SGVmv9>#UK6$HLVY|B&%k?r>#Hw&~i57?nQ82aM z!_VcrQAGUfJRy8f^9U8U$5sN4t$3(pggJ~rpbTfG>aUglabDxYqr}#8mscOiY+A3i zx;jOVCu|)U7m*`0J3g~j{q*MguG`QX#lK5_eAmD`qy3Mx3(e{O)|T_($&=!8xa+X{ zLr;ltXs%hUm1x#67nKT!=9x85A-#|&xlA}T-z*L}GPCM=j{z?i4lVe5)q`;}bC#LQ zPsFPb4lOjl9p=ciFITA;4lNq;_Q->!_pG_f&%%2k99sO{wE@$2Ge-Z5iW*d4sUME2!}Ev%*9L1)s%8U-f$>0!u)8ZfxRl{;{4%Ig9vjKPhtm+7ug4fTre{$b&8s4*X*hD|L@42PQdpdLKe zaPA)#3x}FUm~<7VR~m!VjBgfUeCr|CNA6##8Q(m@tnqP~>bG&;6*cW!`2ID;cu&;i z&+;*M%6Nn7Zd7@oWrSG;#l-z2=NmOA=Fe9^PFyoTy@}gdOlS;}{nD&nR>KypGQ2sg5<}OBoH_<%v}~&fCmiY)k^XwKbt%gqUnh1aRA>2p z*E7??a(B$X>g~>C-koP>7k=cI==#g$?o8FYqxQlimVEtGol-YryDhBw`rB2M7G1Xj zc{u#*?zmgUQS+4HS!-Nlyk>~R-iy`Y%`4Gp3Uren%r6SiWrTDNVT<<;RKR?N_1 zZgrL!;wK-pYoT7?P^_Oth2CToBp4<*XxzMvi!Ux7e<)dQwajtW zmd9B%RL2}rAh1Xs1}(G`R{lD?@ZeqL#D?=M@s5*Ii9OmW>Jii#`Y9FeLy7da`?5V| z9k|og^V(HTZ|*GvQ!R9ly|Q=f#55zq*_nNmh`4ZIf{@rn{d1WJPUf4QVMbu49D&lI z*UZ6+DgEBnF@LnUF}8r%e1bk5^aP^A*N5nZBy_0J`^^d;eE?SYqR|H<%z=sLGHki^ z;L(?E+#e;jt)I)#KxG*BH(GkSQm!TuF(m1)IagD=v*sj1xj0udtIA``)!YJcY{gnX z@Xwh1T^5LcUmu(K_q~antED-%T&?ifa5;qbjOO;x zs(Ob;6F66j-BtgQrCJq^teOSl?FgGbKYOI&f_H9+e_g*Ff&O(mu$uP39)<%;%vCGG z9E14MR=!xh^61{9>xoUhQeze~4`-Jf%M1b)*41>txi=TZ zwgH^x;WRI?#I_Y!x2fshsN1nlYmZu`V)=z2VzQd{J~8UvWYv9udWBKH8>&|{(vKgV z?B=};nHbwS!hCmuz{r5DC=Zp6e(7epb2>vODmkFO%0R-i>Oa)2Wxvs!kufdQlk=L^ z*K;*C-u_4s(?I?5u4Mf!=3<#kNNmumVy2n~uu|%uv;Vj^Q@y@ob6|PQQzByX+AWz& z>-i$hF$4m~)P|^3&b<8FuG^oU`c-T@;kf#McVPCo9#$qa2UW`so2%)U(B^V~GpNnF zI|dr)2~~%Icer{Y)n!#}MqQo=#JWGX`0VZOgF1PQa%J|ncD;&FuIe{;dp<1F0V)p5 zP6c)5=dN37Dp+sFHn2Nmrb5FAGdO|3!>W&gMl9}w0<}M`G_kzcbV42Vfd(oqHdPNo zG)uBGHCIf7tVS)ohd(>ha+!pnRqwfX&MQ*&o+{?NDpl{XV$O7_de0SeW=Pe0OQ17T zs@_Wio!6x5y(7?hU8>$I0-ae>_1+NZ%$6#>AkcXOWbgfe&K!`v*8@6pLH6Db=*$B- zS)Xb+^Fdb6BT!3u#K#d0MSz?98vN z_x;ZNMylk@Gg2jIo|P&&^INHsGryB6IrE%U$(iS+O3wUVs^rWcq-vb`Bgo{;pFk#O zUI3Y#c@boC<|UBHnU}4M&b$JIop}`qJM$V4cII_Se9pW9gq?X42s`sI8Z#$G;jYkweB>&w}aSn!f)hx^%J1I$l?q!&U9}*a)#PHC1<)f z9y!CL>fN#6JSA0i^}+q@aI5OMnC#xtq?fc25~z2O5qMgH6!&_E{)>?kq`Lor2BRzx zE8Vm`b<(eNP1z}q+OBl^sA))_vqL%>hP0S7Cc=!Kc+<(RvkzRoXW`uuV&e&a@sK9j z7&6Wq(rWr{F6RZivwBFY>wCGJ@lsWbhkKRBnE2Mg#Ko-C1PNI=n=a)J^!vL;@JHI>piMDGR~Q52XP3c5l7Os@8CKuwDbXnm4qsgRHK8x}Tn9Wj(ZN zO*0dAHW2kb0~)3`fM`SLuVW4nZ3<21S|WyabE%`XXAds~KaiX1tmbSLx=!OPutU2r z+t4nGFrz4jc4me95B=L>%l-d%Xp`;GF7bvoN&7YEyk+-R4{efmYtVTcWbM_UvlL|Q z)S&Z@mA#?WhR}oYE)Z=BP2Q74Ew5%ZSO!E}L;uZkOT^H=Hz{;vM8|`5#nJm`ZL%5K z5AD!?lx=8NM3_+w1l)U->8#}N!KiAtb|j^XjptdQKH#q1zI!s9l-QPS>orwpTb1!tGhnECtEpunU|27R)qfhO7Du>agmqa?IiC#)mM7W-qAv6 zuJk&1rPrxrjxZ3Y!Fez4_C{yJtGRoN!%nE>>&rj#Me| z)s-p*zIsxnz?UXf3Vi8OrNCETsucJ#q)LG=Q>qmB8c5XyzJ?%E;A;dj1-`~0Q{Za? zG6lY-AXDILW@WD)@TpjHARPEw0O7!w1%v}%OG$izuN4pue64|S;A;bf17BMp9QfJ+ z;lS4(2nW7LfN?(wdYWYu%s zL$2&*PsARB6R||6doJU_K%fX4v)_HU`xZamN?wxBQ;dw+h|k29#QILe-ZEE6v`AM- z-WDRca;Xr>l>8t>cbnu%eh{K7k|p^`h^|PEkD{brhEBPmBaeV9OS#5^sAq<%Uu5O zS_%`L-Ns*mz#9J9q1>MZUM<@B;19yj37@z>J7m>spq?+mr&(#{G|RoM!{Mu_R1e)J zlRNcoj`2d5eyx_1AyxIAxu4CHYO?NiaQLFC-a=K~>EJY!pH0zy4o)Mfs?6qYx3N`q zWl^^dcumGm6A9GxB)~tOc(q8s4NT`U{^`Uc`h{Sc@DC>*QNK#i*7(;GkEmNGi11G+ z9#J<-5aFLsJfgfwgnv2_$*|1juPdzFHb9}#nAvr0w@uc7r#g6uTM$ZcVb;O$$sk%YN>1;>dldF02;!%)QhIYTeE>c#@ zh1&(=bOl+hi>}-a#sr~*Kw zH;`&}dOQxKx}6?Ry(_=uk z=`k?E%!EMT0WQ=7s;p|6r_||XV&i!p@(Q)ON69AWTmC}*i&@wFh5A<^Qlb7$h*YR= z3y})-9U)So{#}SvsQ(Zm73x2QNQL?@AyT3KTZpDm|07i@)c;DA3iVy1dJdpM9k5@Y zCsU=40GUd4q?Nr@f@^gY5H8lyK)71R0O4{SD~YdO#{uDjodXD0?3_TjWXA*Hnw<*> z7wsSruG+bQaM?}(!gV_j5H8$#CGl16d_cH#=eI;;<^s=uS>c(pcY6rGn9S_@g;wf< z){2F|iiwUBVO$po)MP6*+|;Mj;?|446q`<{?ODvE?M&{ zYt7?e&7#hU2;;&)UX+ zQP42=P;b7?H$5e=QwR|64ttM zrHM=SR$&itn6|eIdw{dFy=B+~9HsfTVLeQoq@Nc%TbYCOI0M8DrSAu}h5jD8M&9*k zE;H(HiDtkAb7D17o>&!iUNqlyAn*Zy{g;|NU8DaqmG{c8e}(<}IYLkN0#S;-UEY~u zcGFWSK=Zw&`fw>f^G&5%rTA>`D%D#s>Dk^>>Zuf-Ulspa5@qMIbZ@FnM& z5^!*SO#;r%uS>wOd6op6nrBPEq4^B~e3^NU1RR;?8XzXZieW9*Ry*8#uK2!u6Tt@N z1!f{F#EG!TeCOhN^H=}usM~o|lNhmKbG^BRYDK0SO`Swhp^MrT%U_|3NtG&eaj8;; zE+JK_&?Tix6}psEsX~{QDplw*Ql$!AR;pB?%SqK#=<*;_g{}ZHRp@&_rV4#8$W)>4 z1DPsxMJr>4z8?rz=m&ssg?w*s&#G(ByFt^b z4Fx*UsS{y5D6Thm_^9XoL*^%cB{prYH)plAkGgX9=_QkH$@{{r9^U%w1?T-jBv&2~ zBAN1_5XqB=gh-a;$E3N7J2{e{kLHSGNPaGwE0Q0NiEWY{zZ9Zz<5yB8Gai>JdGUl) z$%-eXN=`f_RWjmfqk1Ks&tboofNl7V1nj~y60ix+3gGkLw-T@gzmtF+cuoQ~;CTty zf8R^M_OnlV^$IAv???F;Y`&i)VDDX!fUS2?0H5EUM#jxr_dtB;!Jb&S~QoMg=nrc3(;I?7NWV%Y()Kaax88lbdJSM zh3<>R%_QJh+*|^V#VsV@SZtqS;hBqLaZC9Z9E)2SAnxlbU1t2=#!Iet5nofNLqPv5 z;C)Rr0os}g&`wT(VorPWT?Yam@&p*SZsy`1kFS%s? zsZtq!QmRyk`$?4waet{&B_1GED#Zh(YHINykf|6C2AQhy5Rj=H4+WX(@i367AU|bg zOvb~3a7i8kglqECK)5K6l*Ct+M*-oo{0tDT%g+Mg!u%W%uFRu>aA_U`glqFyAY7cE z2g22P91t$gFG%96&*On`fu3NANX7%FkDpL4N2+`-p-INBduV~4WbedyDchYGlXDpl z1_JIKP;_V5S3kd5^k&t+7D!{(^{y(nY0`uatKZ%#(ffuRgx#Lb^S5-kZi9ek!EylB=Q{L!Eq4w#vGn zRX5eTzZ>P3YE|7D>J*TwiZkwK`7x1tyQ%si6;46<*=o8K)F~v@>iS6)jw4m&L)F9- zbPBWVW}f6E{lE&x_q*95KBEyrGTW`elmU}t+zFGvoZZm8Tgy(wx6u5B+9tv z4ytlMD%*at@<7yGy7cex{~VWYti>wJOD(!l8nfMk|^Vvd#U(=+2Zbq6N@en&+KsWj4%-09YF>n zcUCq}o^+C;OsF;eWL2V!5!C|;xOk>c{PFYh(_-Hf8&7DYi)Wf__Ixm?t7H}L74c3u zXf5YX;3`$Ti%SoIoa`C263FW8!kwv=K~C{3ngnvH=g}%4SMyAo46-_ba<^So%IZ~a zZlku70&-=~rl}y4O{;-SHmweFvS-s8AXoKlS`%dT20eFA9tK&Rsk?G5E9)wnT+Q0F zHjwJprgbE#TFKh9E|ALBruBd%S(~N-sbX!K4kX#yv_25kz(5l|14xRsX(o_VYtsfm zs#%*h1fotM>ECH2NlGPa)5bt5TbnikqFyLPTWbnLojnt2W{I%r-;aKEF`RMY9pNNn zQ_o3c)2yJm`r9&yHfh8)T*V+CC3P36CDKYmFz9 zM-PKc9z6mwdGsjA>YcK9_(*oYcHT^o@>f3|h> z7Sz!q&M#5Mi=y-E{ujG6TeA8Gd2a?a)up*F7UnyXds~m{raIpX6{wEtraIs26tt|n z34;#5Pr-AvI`eXy>YlL2tLI}C-LR*F$df?S2_`kw^#h{Y_VnNM2ckRoG#OxtSo_uu z+rMdEX4*kHu3l3e9X$>0U^}!!U}%duL!-gk&FAgVj>|T*FQ}pQMo|py*j@$V&c1i=n_}bsq2*T4i8Qp- zWc#AsTW@I9dhQO^Bq^&kPIuY91hP6Mbw54X%6e$4a+mECAnKf)hUsM>++{lzh_;5F zwbLvSLtAp~jGL3sjQB_#y?;D~E+Y0)o9oi+?hW4!}Gm7HrcUM-9_^U?i`E|s`6P5(L zFywCqjf{+uy`WL{u|Wo?spvL?Mq3b-ts68Z8&k(m?Vz!iiCgtXM^Ea!I;yPvv4C#X zQ?Hv=PY|c|FsFHuR`z%+jSru25(5>3xhX-a2Wg<2#3L2KsXHk z0))fhuRu5q{sx4@;B6or2JZmjF!(zV4ugM4;tPX+0^uSOfUrf!O5(HV^FY|51HNwZ$c?-UiPvLG!kz?@`iQ;}@ZMMBk{SNjhvz->sxceIWXlB~3DbDCg3?@oUmV z#vFK|TECBP^hgrlpo#CIskD*Jn2ob#%qCH0CWz?~uDY}1Klhh7DmLz)9(>Z-+@2Zf z>CwU-hn^nE`j)DolO<)fny5a5pwkj$eLGdq;WtO=ji@st-Bj8dKCM(}M1hZb zqw?D4pBcYOY}^!he^coeS>Qjj>zr9T^n+Qpf=mT|8^~1Pw}VUt{&SG2!0!N=3j9ux zsle}&vMKPpL8bz~2V^SndqJiGzYk<8@LzyT1%5xsRNxPQOa=a+mA$oyGx#AOT;LB& z;w$h+fN+673WN*%F(6#vzXZYs{wp9{;Ex000)GMs7xALw+4cGQ_5H8MZ)d4@%i3nsbGE>r&sN~Sk2G#nuYly!$|@1;9a|(2#>x8GI?|v$mG%GAd^Sm2bnzj0m$Uh4?!l6 zek5h%(G?(*M^}PO9$f`8d2}_%#H`zIa zHvqyRyde+{;f;WB2yYC8LwFM)9KxFd;Sk;o2#4_ImWaubCr`ybnPXqs@t>2!-;vtV zuHda;1uyEfjx_T?OpeDEZmR$8`CO4=+X*~5ID)tHCWpFJLQjtNc3<`6FcJI_DVqr1 z0c48c9YLlD-U(!i;GIFH2>vL@6v4Y#86$XCARNKF0pSS#7!Z!&-6iow@E$-og7*Z% z5xf@=j^Mp55tCzOzR2!V*K9}=U!Ykz)a0-Uysw=cPh^`MPez(~AQJfg#y>aN^1w0q z3xi4E{zlcG?82d|`vtqJX5r8Y{36Iy-7kSm)%`NaRNb$DOx67=$W-00flSr?x|B_I zzX38;_nRP7b^jS;s_wTyrt1C+$W+~b1(~Y*Zy-~3=l5V^b?0|sdxWbyzY5#)0pGU7 zZ^HHnS9g9Bwnwl*CuvqkwRAj|RfkJq8F@_gG6r0xxy`RKL~*E9aCR?HJHMrukY{bK2q_55+yv z$rWYXC@gwo-sf|kYjd}d*tD^zzh!lnwCHR*zQUq!fJ_#h12S23F34ojc_5QT=YvcZ zT>vs!bfJ`uMHhig7F`T7S@cbi$)Za@CX2oWGFkL(kjbJ;K_-j7V`V)(eRmeV3xqBD zo+Q2iz6=OkbU6^V==(s}q8|WZi+%`%E&34omLRR)B zI|pzF2nX=OKsbOG0m1=15eNtHqChx+7X!ipyf_dJ;3X^(mpL1~GcoRRk%YYB8#I?W zMel2AJ3Y$4^eE<(jWjbsOpmw&sSj2BKDmL|xVZ}MZk!`{1sTEbv3n~b_`Om#5&S-o zDS}r7nIic8AX5Z?0Az~b4}we)JZxpJRP$Bvhk$SduLOi6cx50Q!ILEMMer&>ID#hw z;Rs$82uJV~OT_d@>UV5k)b78EiEq$9J!}TAZl_0$Y}2D=q?rk#z|ROxTHo%&;@ic> zO@a5f#Ky?hfmnM7wOKoK29E=o3VaTbslew1nF@S7$W-8SflLKH2r?D;+)_3LJ^^GZ z@OeO{0-qOTD)9M0rUIWIWGe6lK&Ap80+|YYK`Uc{F9d`Oyd#OPz!wI>1-=LnF7Sy! zxWE?$!Uet<5H9e=fpCE@0fY;DNg!O{O99~mUs@7hfiDAu3w&81T;R(A;R0XY5>ens zZ2G?PgRK%92_KmP?`w{|*WQV8U$#3@Dh7=kRdQDsxv4p}*vqS)tnhvRn_|-mjnxNK z;{Y_rwv{ezXLnY(v^~h=(nmlhmv#V|T-p(2a%m@!$)%k^CYL@cW#iH=Ad^eGf=n*$ z1~R$yF_6in-9aXo_5hh&+7o1QX)i0IOM3%hmp(3u&!v5UuuJ;_VV6DugkAb15O!%l zAnelqK-i@NfUrvk0%4a90>UmGEQ!yhLx8YLhXP@j4gKu+=+ z@s5LB#cRYn0dlg}FMASX6{g*7p8`3>Ys5PZa;mynKz;gakgK`vUP0#@kkuK4E1$8l z_GvZ!Of7vg!dW2tMGl&L3q(IXK$Gu)=qCthat?@oihw5Pf#@d*X!1P}{WJkhegLAM zD4@xYK=e}uH2DdLezJfj7bK}($u{C$1friWp#SC)5dDY&O)dk`PZ`kU3K0FE0Zpy~ zQTd(j>%3-(h`iTYHm`T7a`X1WNfde0MI+u#Ytx^>rp26FLE}i#h?ON{J}DB^q;W4tK(ZjLu?zAR60@DZ_PYH3QBjd)4c zqqnH}2Z*@m`7j2T5Sv~~LCyjr2+MEP`2 z|Il(HUMp{CRT|N=wzb_`J+#%-dhQNZ8<45Tu`S3d^tzvJXJu~{|Ipe-yhrWOcF8uhU1Q8BilN={!tXy%$SS#8 zd~g1tyc3_MdMbU`2;?&Z=tJnH6 zRt~M#h?g$j$#^@;^xM%(8SmI%BMngFB|Zb9}&yg#xrHGioQ?@!CbEeMMyzS8>d zo;98kyGXYnc)LjJ;Xn5G&41zd&7#iTD08IZ^5>yf_xCveOT9H>+jRLe-QS4!oIGJ0 zZF8$BH2U)A7?3Fpjs=;*;PW6;7#s&Og~1o3Y{KApkSPpK0GYzzM35;Az6dgf!AT%f z7<>t23WJkDrZ6}KWD0{XgG^y?s+GNEj8E960pT$C3J?y1uL9vPI2{Ow!5Kg}49*0? zVemB|90p$p!eMY05DtU0CGmy9H-K;$oCAcz;9MXa2Im3cFgPEGTBGQMZGk1?^5?wu ze?NKfQbtALBf9*leMA;rY){wTgwwS|XGzewQCRfsxzOU>eIw!VMqVRcy89wJ^I*X4 z(ViFSe62_Hf1a=P1eq+_3uLlrZ;;8NkAqAW?IUGl(Y_#)MV|nfEcztKWYK;glSTW3 zOcosgGFfyW$Yjw$Ad^K0gG?43Vr8`GP#|p4VL;fTPXS?z4hO;(9RY+b`ZN%>=tv-J z(NRFyqR#+fi#{uf&!W!(VT+Ci!WJC^ge^K22wU`dAZ*cbmI#Xm{uw;IOZ|583Cq@^ z+=w?J+MKXWjFu;CiO!4B#*N}P=0Tl)|1e|RffV6>`i(hVHsVFv6E=MdLX?d>rjF`c z5TZfW&npf(F(9k&(Cvnb1zA6LK-9z~5(J`epwNGl8;HJ#LX!j_`Zfwp@&M6yQfQJFh`yOZlYBswb7|l5TOu;% zm}5@{OO9QATYQ5iV~R$+f;M9o%9b&m7&8;Z^w^&Nfs)4_?J3U<{L_O^Iuq@gk)9q! z?cRFvUEk)Ro|y=;zQ;p7GZAEcgGbOQ0kXckBj}U_S*@Jz7hVcvdLVmgkktv1`{^=P z_SQmvD0^8T{8;vKlBl)AysoG`5LGDXYpVc+pUi#_5Pc_wo&@&-;b*ho2SlwM^zT%( zL`;v~TXT)**s1rn|2sYGiSvVYdW5r0kB4H+Ob`V=v;2z@*XPeXEH-X3xW5r^wJh)- z+jY*Y9Xf-r0htQ?T9B#0uLGG1{3jq&fnP6WQ{Xp%Oa=Z^kg33L1epr_CXlJXZw8qP z{1%X@z<&lZ75J?nQ-R+GG8OpkR>lJVIS?-JJAiP3-wA{Z{4O9|;CBPz0>1|c7x=wE zxWMlN!Ug^dAY9=0OX4f=2Y_&aKL~^i{2?G*;12`g0)GSu7x<%=hyp*T{7?HATzF-r z@R2F-zDB&SY=J+Xt-zm%Hf|J+cnf;;x;bp$aY}trc77HVpYgztAyw`0VodtEY zs53jp_)+v)6&Tic@#Gy3!HvLPuT{Ee#7nY;RHv*ec0DmB)ge3?WD4O`L8cI%0y2g0 zRFElzSCg^{;nhK=5MIN|7{Y4;;Sl~X5DwwBfN%(}4TM8@9UvUS>jL2rUJnR|@H9)r z!n;c!E z%{&kZd~ouY6>oNKeUI3-N#OoQywi5!(AE8GyQ^m5&EjkYfTXa4Uw&(&NY|({4*rJPo zutgUGVT-;Age|%R2wU_mAZ*dMCGlBwDG;{kJ3!c??*d_qz6XRYx(o7n?ShIb|bWq&2C|SW$Lg zjY++$;2@i;;2=`~j|JIW1qaz&1(&i3;5k9203L5;4B)wdZ~zYi;Q*c+2nX;4ARNH+ z0O0_h7YGONd_XvW=eI;$=A4_c|MchW!efeJPs){{hHU;6DVJ3j9YPQ-NOrG8OohAX9-~1u_-*)gV)W{}^N{@M}P( z0>9SESm4(I;R62&5H9fRfpCG}0E7$tr$D&CZv?^xeiINb@SA~ff!_jz3;bu2_zL`1 zAY9#$xQHtc2_oEbd5_20*1_Ir=WA>xL z)#LV+-zo1#OX#ILX6wsFy#BehA*-i&jd%m>?s~F*$!X9T2(o^|Y0w!2vPw5@)7fAt zSFTja>%<#^x_-53&>4!lez9rL8HT!wa_;t@LS4VqH0TURUBA*a=!`&JztA-3JdL^v z)$aC3qOMTJT@{&QB>o~>M2KRRFEvoIQwe#3=E zV-V@CWsSxn(w)m1J&#CtFKaXok?vsD=mkW&i&>-bh;%2jMiT(3cVnv86>2mQk?v^L z=tV@jt68H-h;(POMlT`K-OU0sev&Wzl~t${#Sw(y_F{uw(nX~9ck;|Z?E8)Vh@HR<(^6aIZX zPE?@kJ)3_=AY%VMjfnj_5)u1%6e9NTGl=cdtiMH^DRIW9fxy42c+(Rr9xOHaXwEIo#)~bh(^Aj8;!S%0#v1?XR;atN z=wICm6|hI(eVSgJ6#=r!gl;QTq?Nt-sp_wJb5;~06@RH2DjE^LJ1Yi}?zz&-W~@bG zZA@tr{=H=mXMz|3x>Qi#Yhk3}&1r`>9)`D=lPk`Qq2|Q7lgI9^9>~g-bTe4c$%{I*NajOb%_?_@^IM&Un42UEAmT2`5FoYC zm^R6Rh}2p`UrZs3#1NO=G`8o8ZlB8QY5pO$_aqjvL!6jxh>OOV(G)}cPRvV-YTWH0 zA8MZ98)9zeD?vl7QjDI$CGGBdL#*EDt>a@yovt(IB>imHQ zs~jS3mn@G++eOdf3KoeWo^&U5`cK2_!o_k^;gyeVQ{R1dh%06r;``&wXo?}eclnh! zM|Zs5RanG7#N5;urXf}fvL51x?CyF)oTObGbSj}vEt8c|r=H0qt9wJ7#7&b`5NV_6 z!AeHNZIe|IX}jpZO0h@`aq8W_zk2T4m{DRB{Il3L_f@w;TqD~M*NiixDVqD%-q^ag z=ZbOb#m4C^d-X+g-}V^O!$-}1pWFMF3{Zx2oBMWHkiEHYXEw&oeY-3Zw>7-<(!Rr+ zU)Wq+>>}OP;O!!J%c&qD~>Q9O@Jz%cD*qvI6Q9BJV++Lgc-u zQ;56|bqbLcQKt}jKj(`AuU%Z^R z(!y`<6CR_>t@V9x;Hzs-0qemjV4{!`_@6k_N|ME?OP8K+cymn+czB%+qXUU^wr?gNpM4u3 zV*55k#P)53i0#`L5!<&3BDQZ+L~P$?h}gc(EfV(KH=yt*J?a%a{onTGrofi5<|MFH ztUL)!bXvz6rv?K1_$=lAd(wM%8St%qj!D7+?<_?&1s=2p*0)0(vioZ4uf84PFv$AR zt?IF7Agk}v?aVqVW!J#^{cFciSJ%Yd&wq)!eqyV7@)_zX(zu^LZgtN9>I_TmypDP& z5UHt5=p-V2Plx`iQ;76^9U7fRr0?y}=xap!{tk`40i-OgIvq7SgGjlW&{>N_PCc;X zmuHs8mM$qL3Y`jw2ElW7s+@B({tb$W{RCDirJCqd^j>hv7zE2yjW)&2UfqE1h;zJ|Iw$#Oq` z-Rg9z!Oyb3fruYweG?Hs&H86Vs<6;kcnc9f&-xcc`hE{RCw@i5Pqh9Gky=;i-@0v) zm@dIT+dV$u+I=;}H)>96-05OZ&i}B}<<*!&XGej`x`QYz;z6!VABsOkxy}w~_ zv|U$pFc@R^)vPNz7>os(g2D43Q!p4OWg84$K%IiYc+@EvOhBE2!9>(47`%u&1%pYb zQ!sc5bqWTPQKw)q1$7DrFN1D^!Bo^K7)-NzwqWoIA`S+xBH~~$9T5kE8HhL-%tXY& z;59@X3|>dX!C)33Uoe=Bh=ai!h&UL`LBzpeE+P&F^AK?`n2(5q!2(1a3>I1>f7AB~X2RO? z$DKO%5{mF|U69GY^*|>7rb*fQHyw5IZ++CszZs~Le=|`h|29CK{M!(9@^2&5$-j+J zC;v7s|T_kaEEf4hy>+UJV5Ha$Gw*B>$dCyEoRB2Hx+*HQlFX9?A2s*A1-huFzrauDu3m z46L(Sz%D_aOu;?^WD53?QntZ93Uvzh(Wq0fk3pS+eXP~91^YNe9PD!-;$WW>5eNHt zL>%mMA>v>k1mp|$xe;-&Pq0W#l$JS8J(F;vnS218xd5xbOu7J@&#v_OVWltX6o@r* zA`o!T@aT8ISNArVc<_;Kx8+1RY$poG`a%%v9lNu7N>o-qqUfno7-sx^=z@eBqEOWr4VtfFO7&}eHla?>&qhISYHki$NKV!IM!FN zNKBU3r?-Eqaf`kWi!anSS!}Am&rX(#*(S^Vv1VR~RDWdIzLVtsbC8rUn=+v5vPK!h&UB&L&T|IJ0ea6pCjT_umcgNf}Mys73{J|r22yoyw)w@ zO2w1HVq`-$y_u z`*r}C?AuYw*1nxkC;N6ro$UK4>SW(8sFQuWqE7bhhC12zG1SSv-BBm|_CTHN+Y@wS z-(IMbeS2Fyn|&Wg#P;oji0#`K5!?3(L~P$D5wU&yA!7UXN5u9W0LW+Gfr!|?gAlQO z2P0zp4nf5B9g2wUI}8!q_bEhd-{BSs`_6yzPI|YhN6H9~8T=}=XJU<0 z#nt-H7A<=v<;gMsicOoV^|E>KpbYhg{yWqk2H9M#2bn_sQ7PL{e++eVwH|eIwH|eI zwchI4Lj4Iu9O_RZ;!uAI5r_KIh&a@Ljfg}2H-LPh{tO}x^=B;-mtX6>*}VAiKFI~d zw`nfFiblqB_O^=ia9f4CS|4L(g}7QDb@0&(d(ZWqE;eqi)_ZMm=KSv`Z>sRsdb_(a z)?Y;3T&+jlT&+jlT&+i)V*ORr&DDC;&DDCVXN&bW5OJ)(iHKwU&xknI-$KN({ue|X z>wiVWvHmwi9P4jeB&N%K&oBO>araGdv4DQu5si(1*y-|Tw(0U$jF}lC7<8Giy3MW< zHUIl+y}z+BL*9jxX>T|X!Jq-i6bu@IOu?X$lx;9*j5-B_Ca6;|Xo@-ogJ!5xFldfC z1%no-Q!vOvoq|D2)F~LWLY;y^YtT(FXoEThgSJ-B77W@U;$YAo5eI`u5OFZ*fQW-Z zM?@S9Iw9g<&>0a2gGT}RfA6*|_PxEU z_0aVAx^(a?yR*Wg3=zQ6~p4L7g1@7U;&oZ=+5QUTXDh4t@s_JNR8h?BMqhv4fW(Vh1lr#14KR5j*$; zMC{-X0r?#K5h8Z*3PkMSm5A8Es}Qk+S0iEve~gG7yao|Fc&$aEAu{oUdM%FM*f2ua zjNVLGpKL}KV%J*}ZvYb)cRtN+{2B@}aI@WvMy|P}eWA3_1l+*RQb*Iw90m zBy_i55Ow_u%b-&Tb^QX%pyQyfUtbw?3Zt$fy1V@%psQDvM!9+->iWf%L8mC{`n8qn z+1044GZc3_#jWo7I9b2OK;M~B0+D__q(&tX=?-#@N+Hr+PU;XWhe&so>%S_GNOzWNQ~{ChF4yQDM7qOVqk9qQE_03UL!>*+HL8e6cbjW; zKO)_6uF(UC)cFA&@`DzMC_Q%c2d`eA8}q94u@|MuX=LL{3Fel%$_et8x?)aJf^n>< z#clVGI6dxS8|Z8HYH^0IDKaUi^l+7&|Lx&q(2a+yqD~%8L7hCDiaL3?8tUZX>Zp^4 zYoJaZu8BH%_+iw^!?jQ+57!3Wc(@Mgue5 zjghVDKlM-P0yW?#(GCH(ebKcU8MtjuW8iif;bpM)OK95=?*2ph5bojT#{A#_$DA3g@8U-5SuX30nKAuAkaWUsa4l|l! zh=))7di^6OcBYAq`-hl+bUsZ(Tt#=*saFfz-SvjPif*e@?-oX#+E34*u4a}y#AmHe z%K-PEev63vPrpON{io*;sr81wnDZ8iA&&bqeq@e5c?XD5@DH*5rS?ZV#6M*l;tM&< zXo?}OGU@HrL+jU+{_qbmH%DHkAy#Qd&*Cd~cfBD_Rx7_dWLHtA{?luyt03)u{<_s^ zh`Imt1|oG%L4$P@kXrpr|LM<&v|aQpzGaaZ;*I%dcUh4B)Bhi0+Z_3u9pc;BhWJhn zGn!(EyVdz-#4qob>?OWG{}6L?wj$A>uH37!ilbBZxRm9!11q@)#grnEVnEhsm!HahN=gh{NOwL>wkhBH}Q43K56N z(}*}sevOF3oOrEhwT$-J}DlH?>Zq_2 z_AlCGdzYCIb&Q354U&JF{&~8l^Os$2q=o+m-B|b^)XBpCqD~gRi#l02VC#nW?^YoT zN1#p?jzpa-9ECbrI2v`ba182X;aJd(h2u~s3+F(cESwW{vT(fBvspM7BDQc45nDJn zBDQb>BDQcIL~P-_fP5Cthlnkl9}!!)03x<<2oYPjAR@MKAw+Cp2N7GiFe0{a5kzd^ zM2m!ln?<%dRWZ0>(0^N)nllt1m=dKUFvAEJ9sfFLyt`7MBRNpI>5i&jjjh%QQ;9g-A_j>MMI2k-mRKhsC9c^gSdRy#q)YS~Y!Y^e!TOCy7Sy zA<{RKXtWHGayD&nxkVzg=5NsRh0QBJnkT+dlUYThnHgfbOuSoS z^W!~>%dQ;%bm5cR)qLiqr_0B7cfIMN&b;(=S%W$~Wqd8_`UaPvvkrB7&iE&&t2NgB z`qzW5Rv7)h%?+rl2)Vn1ix`}BO-p-_$EaBwDHY|RB@rNa0?=S-uP#T^qnMn zPHaWQPaNNdNUbgOZ*8|oOqT^0-g>D?lY;+$y4Vx-op!qH$~Ikg=P)xv1cbYTnw`5e zX5JHGE}D$*ZZYKZfY1ze3JA?nr-0A`bqWYss8c{_i8=*@ zR;W`zXpK4rgf^&CKxm6P1%!5>n}Es143s+91tEw z!~vlTA`S>$5ph812FMo>9z(uojhC+b@Ff_(2a*3)XBqzQ6~=M)8IECW}q@zuC!hJKJQr6KCdyNccCuOYFR&)Y2_t+a}@rnP!3fkT9XyRXrGt^EQ#u%hI;DeWP^Wb8Eb5dFoEIPaoDN<^#OYu>S3e!os~a{;@TwcfC7e)5gO7#>p~Z;j(sDrG?9ZZY*3Lb+T{; z)XBp4piUOP7j?4meW;U#E22&oz8`h6@B^rmg&#znEF1>iSok5-$-3)e%$7EZHBSU5GSc4$NMEv1CdjD>y8lNr{+nb|DdAct|QxGcNmcFD%Y z)~4LqaW%J}*2>A1CX0RsquHu7k0{#NjDc~zZ4M%{C5EP0{***IN-mBhy(sIL>%y!TO=;aHd#@u@cOBJv&1)QuHuUZ z$`5U5`v^jtx{4oXW`>w9r)H+)Z&Bp6Vq)X|>B13zHAMW6?e5BmzXo-46(4nT6(4nT z6(4nq`0GJ85q|^f<|@9`vqk)kh&bYJLc|e&Ga`=oTM%)?{|pgF{H=&M;%`I55r4Zy zV!EtsyZ!D{4X)tqL3vA`o#vh(yEzAqo)(glI$@5MnG60ipA_ z_-ilS(@Q?E*aQS$6J-wDxRDbYHxixr1mo5~z`YTNuHuj1-tCV)Q8UX+3qRpq#fK)! zs?dOyV)s_MI2Cl`;%caqi>sqfF0O$(xwt0kCl}X3om^ZSb#ieX)XBwlQ70GI z1Kqed4RvyHI_l)&`lyqOGpwG?#hHlM#SIX#iyI$-Qo_VMhb+rnzpNSPrU zDIc*$?f^zE?sQBro(%*t*~qCsdhHVUpnUB8Mn=&VLvzlb#Ge2lt&4QbF>gSv`_?)KNBu3tf_ zZv0?<$k5?Eb1sQ~%92AbR=KWIGVOfNJtN5WR$I zvIB@-L^at7L@%S7>;j?}QcZRP(Mzc&dw}T0RFl1usQzlz&#K8jAbLU7rM+Wz;KzgzTO zVfll6g6rc3S(&~@$yxE_Me^wEc-drSJo*Oeg3S{sFOz* zqD~%N#JbO;i=|2)eN(FB(IrwPkG>^U^61-AC66wZDtYuBtAa=0m4H3^o&-LRE(5|I zT@Hjj`aTf$=m$X9qaOlckA4J%J-Px2dvqlb_UI}g?9tVd_&oYC5ccRAAneh#K-i<} zED?>6L#EWdb9iw(_)WY+z}Sckx*^_l>3te6yYz}U8{>@^-8W~LYR{^*Lp~o+Lmqi2-_Fr&dd%L!(mmTPEIo3XV+;i9b47i+-WO*_IQOKA zZ6`GFDyqL->`{olU2OTccGVZ5x}r`cwHxYGQXfN|N@{o1sigKmol0s?)TyNQLY+!# zZ`OS!^>L|EN$n$5Dye;?N+tCPsZvROQmRx^`$?5bYJaOjNgW^om(+n0_)6*^AY4)h z1L2Z71PGVZp+LB#4gUNr86aFzp9R7t z^*Kw#MW(~GdVReA%N#3&kLV&(rmr1rtPQ=-L+DL(#w8dx3X3)_J8b(Wr3XzGo31?~4NQ=IKx=FpLo79WCNxi6>)Qh@Fy{Mbii@Hg@totmwSgI!VO4X!Z zshZR)Rg-$9YErLM$)fLA6)gI$1Z>gwB=A{u84$MUav*Hc_kplQKLElO{SXLS^dlf_ z(G@`0qAP*0MOOh~i>{W$XVH&=utnDZVT-N>!WLa;iLhwL>&u^RGHwApxYg8o$9Eo#{jtfH8oJzj~fj-HBnbr_1w=tjJkf%Xwa#Jx|;It=WAP?Vs$m! z?p248=Tmh6Iv&@RfFGM$PXc`i`Y+NX;76vWOP~)z|3!TX_;INj66nLwf01c{$d}g_ z<(c2;gSoZDcWCmZXz*%e^JU{~`Lap8nG0eKZ}vy?eOZm-;hm=xv-}-9KfxM)!Omqn zJ#@^vh&rv|mr$oQ{4(mahF?LQ*6^#S(;9vaby~x(qfTr14c2{Y_)V$O8ve6XX$`+6 zRa(P;kt(g>ze<(X@ZY3LYxr%e!Ww=@0$#&^m%z7%{{e*8@IQg@8vYj$Uc>(e!fW_H zKzI%R7YMK6cY*L49g3U)+wggyE)5ccR)Aneg;mWaz0T~kWUDU~_ClrR$A7oX|x zxS4KEIs;5v)R`G?{1^y)#zCu2(GmxPpU#3OC2seEmgu+{&4pAqQH-(6pf#z^Sz}SB zob^2Fl(WX6PC4rZ)G23;N1bxk1k@>KO|*Kpob@6jnX@KIz&YzB2{>m>mVk5C6bU$I zy(|Ietf>-k&YEU{m>$31*b;2_@rq9WIX(P6Hq&hmp8+{sO^=*rCWx4|=}6BTEr)IY zQ*7IuD*M|e5?~3>W2ds69Xe*^MV*%Le5lhBo*#8u!V92IOLz!%TEYvWPD^+p)M*KK zSobaAg{4YMcoC`65}qhkTEdG;m6q^gQl%xlxKwEgFJV>d`oy~AiRW^ z0m4goSs=WGmjl8}czGbagjWEPc@@FZBl6P+sY#*MSWQ+Q74P;K%FeQ6LqraF4W1QyIJ>HbdOZYqI;!E z7TqURvgj95C5!HtDp~Y^RLP&B;b@aR02*} z!zAF8^^^phvW8nAu4cV<>D5lLDSgg}@6cS$5{(Wc?F1PG6Qr2)OinWw#2Wr!k7eT$ zJNG&+Hf~~;|IYOZ@T1{G`{Rk79y(^dh&rv|lTfEM{3XIHpr#1X#)M*W$ ziaM>~(^&Vd;jc)Q*6>%QN^AIZsnQxgL#nif&y*^y;jc-R*6`P@3TyZ*33v^kErD+h ze**}w;d6lS8a@{Yui^86@ESfJ2(RG_fbbf=5D2f~i-7PNz8DCv;crUfTf>(C;Whj% zAiRdZ4TRV5rIv^_e16Bu>&HL#U0C?Ytl_>p)8Df{8ZOKBqv7%d<3{yk17FRGos#3- z%wUeXV$%tYy{lPpXZly*(&Kh-rAtqsPA)x(I=S=|>g3YXsFO>-Mx9*x4eI35GpLhG z&$8}w>9?9v-R*rhjtuuFfI#OKmmK-i_f0AZK@3WQzynx}&R-x%()(g7=bL@3z+Hd+h5(J);KPVj6v~R6UbM-zQbiqR|zl>KQcpeyMu) zjDA3>o;jl*l&WXV=&)2hV@5wD)#`y*cYiBMRZa02SFQ}Q>Iik^B#@Kz>w2QAfLulW zXsJG(405u1&5M$&f~=ZhT{*?dlnUKD{N3LSqf>#TxHyI%LDQrz5d9i7P3i&BFGABK z4TydfnkMN$^vlpRsV|A@a#G)nCK*7~?Q}#kEeQnNJId*f$YE1TZz%n8-+|JgUDXE~ zWU+<3d*q@UnRn<$H->lUmW*x^Yup$JxV;~={g(f>i%TuG{zI|-gr>rxm90gadlpsi z-*7KmM7OZ}tUX#qzpE`6odvRfPg^j$CCK_6ZNcbPAnW(D1*2Potl!NRjBW$6elJ@v zx-H16G27k2c2ZXDS8=Wk@9$3b`a+`N{oTo48I6YbcPD#wG#cLDtsZFPzFR9AUf-=A zS*pznZ|_d_N@+B_ygS*erP2KEZf(|N+a40lZ}0Yqt)|iZ{%%cFqZRdsMDrWGJz}eA zG{3{!Bet4G^IN<Nxt7$a6$6MVjM*Sht@EUK`B%!_*y$A3X?-W~2qv0jqDYlwM^E#u{G+0+WK)tc$Omd*GXhfyrX~!71tk?qbkY zzW_ol1+4>PBXT%f;&V30s^@Bfh_Lfn{EFLgk(b`>^mv?7^+|F-9e-rl*&1KE%=o>H zmt5^)h#G;&ve98@Tl}_BdvCU17gy6I?#~x4hz&d2FLH#P&*N7N zYq7T4;ofsypzb?z{~$i>?1(=D)q`PYXZ)mDhc5lI@7DP^FU=}B zA?)mmKiz2R`V-&pUFCjU{q*gAJa5?99be%2FDpEA_HGYXSJ!G?J%8BQ6W?LR^`$G1 z7p|%|qxU8hcJ{`v96GY;rd-K2+>h(qT--k>6?XQ;m%03Pg_Yapj4(w1O_{LsMSS_1 zpXD#tx@m2_sVeRtlnXoi;|Krt>Cr*=j&I`rfxg+_CHID%1M$=L)Jeb6HD#wEdQ%m{ z&cXN}dc>Q4NZ&K*Uh>i#A>VIC# zmBP*uaU|~VjPB+54*V)-~vfh#&klJDASp3#ftNse?dvlDE)4VwlS+;K2 z`7(ZV^rX(Kqsq2)ft?0vVdty(M(<3FyIdq8uOa$4>W7`<@k#xT?Tgy|S235EX^TQQ?XCx*jIKC(0|b|?3|2WnJ=>Y)HNH@TtL&Hao9N(-(bMkO&+=N%PCi2Cc%*nfOxY zPxWhEuyRgUuji&qcS~);&e`}Ai!Kk(>~Qjo{s+|J8(Fqp*!ea-XWxORPmEvG-u(kR zLAr&V@8SnusMhb}8$FT?(Z|+3?3|0QGVR{j1ucK*uQ!$IZmMV4Iq#n!X?BA22|M4% zuN$_1)4a^IgYKqWqBr$K*!dwo>EeV=q3_xpHAGL4eqraw_>ya9+?;%7#7BncnJ^&i z{1kux@}qP5t}eG#|MRNrG_vfVuyesbLDI|wc{c1^j6d0E=_C8L)|jcc)XM$*=&*As z{re5Li@J!?GU5}F}VWydLWC4O$k{?o_1x9Vk( zI+Cce;}yCZzapd5z=Ee9aE+ht&5@|G6BW4@Kj3<^oym1uB@)qpGf9!_@y?WuTkfR2 zFxn-0mPD1EtiX-IzvvH~~b+YQ;6yrXQ-k^11PyZ`z$rT^@o zDCv5lM3sG2fm`u|%Kx-~!G%{=x?9pSC93QU1%8RoefUu7=MgPO>n*8Vt~T|W0>AnP zGM%PGRN2J}{T4sw*ptDMV^`mHH|8RJC`%N&9p8Ivt`QwO_1@-fPA!yCW#3ldj(=LD z|BtTg4v(t%+IR1kBy319v}CiP3yQkZt01WoNh1kOk$@sLKu|=iDA+q#vFi_eM*#~q zu%coID=G+51baadzA2~7xy$zlJWt+tcJADB&dfXQ&Olg%J3pwXznfio)4bt>cK^9r zX9sZ+?)?mGW} zcb9i7oTKnE43Ae7v$xshm#_Zd#rZE5X@Rl!iE1g|M76vyk@ zHHG2vhGP8q$jr~r$yrw&1IGO3EyaZ6H!c`+#*wur9i|xwkJXBZ#8*$xUw&M1>n}6` z;qk5_qVd~L`Kxqd-w!)k0~n*NQA8~6=t&vG#|MhYi1%v9n$}R)P1nsbh>wpHkr`ie z@C_4lws-%`W@U{0i6XM%j;54Re0-~@X7Ts#{q3BGV;$S;%qTuKC@LP${%7_E$wX>nz~z2?c;dQ zg3gTM<6cE|h~t_1HapX@EmlNFH$Ln=gF3qh71b$@cM|ICC_WxmROdL}rH7PlKNQs^ zj(5NzW!n!$?H|Xx%S<8E$Xz|@Nkw!O?}YKOLNVRqcm%P@&BVt`3O^u@_faamg4z$o z92mzhzBEJeu~Jdpz)dXjyDu@a2$8s*q@l-cuNt7h@W8Np@>u* zx6141W8C)|kJ6vW=skFe@Ws9Qv#qncIq|EzoQ&j&reo|<& zGj;t(MGT0i`WF0nia%7>XtQHYmtePI2F7u7o5{`ia*x6X#qpC`&pSxXJHW)jZT;E} zziIAA*#{~pq5gSlpPE;QBb59O8d~U6^1iz^oq1(s_QM*dz9K5t1EU77 zM`qjqa`ebWL7r-A_TK!VxHi4R^t{w_lM7Kd#YjY#vU4n zhp2H&IQPsI8+#s7pQzM0Jw%OMBDuSd`E*OFeBJ$;;fJWvOEkA&^^W?}Z*P95qDtW* zYV;Dzz3tiEr>xmp-d*GH5H)(q$i2Ds?h{^mEqj#4=^<(WlbO3?WKHqbo;A9ETFMV; zqjV^DmcQl1XE&_vs;Dw}NWK!G+)bBmYtiG*uMX5WJS3qMD0g=2=NfbGI;@+<=^;ra zLAiImcv-(Eiciyn5xBNpo2#9Ypj^D-T~YetFO93=Q%)}45TNGByexp*Ft#_1ty z{L~^BFPYX1ze!i6KDl`OiK6u9Wcnd$V3n7P-<@e39-@X-Epu^cN#pboHLPltiw87l zh99EFRjqSzrdtGYx3P5tW_+~z4;jQ5t2T)D;~>6d@{;)6&lg2y5Vz7n+%TuOw6w0i zwvpzu{S!jbit@(N;Tml^qQTB<`zMCzxCYg=9aB%Np5OLQVz#Wh*kRRNPPTtCvv#hjJnV3Y3928sm!|1vr}IFG-loB^)%De{&Z&b^VG+@`gx}k8g`#&<^=VOia&!B zxQ|qq;@Bw{el;-;p|U=m3HRB(aX!hP#R=SJ(;-3r8Jxg< zc5nU0<`J_wfqr%${nCawlL#^CbI0Cq&)@%{XLgIAu#-McP}mt-|LhPPJK&!alE)6T z_sgX4ZXPUmJ9nFzW=}rG$#0>xZit{$-rNeWbd$ z3;cRHCvcxiXJ7eOZ~_^0S2E$gYkvy5t2lxCY?{mTujT~qv-?xfUBd}v&|OP}2)fgT zwH)!^`2I2|0zro}js8Lky6e+|?uHP?m*=(RmM-(F55E5F``)W$&?Q7mM`tnkH_M>2 zH#YjWP|-!usc-9a&@E!tHHleb%Jy$%)(N`X7kbePT@XRrGV*q|6WcZHJ%}-Zw3h{VabM;^36youwwKsXZ#3^I|zD$G&z+*s1>mZ*0DLWkvF52O7ip-nJ$Gr(OO{}s-$KVg#2W2-i_=EOA*&Pl3;C)bbTZ4btJ}A4l z!5^{@%5HG*hwg)dw)OCRP^y8`TOIsi`{L|=2fuh=Tzp-)11KMw;R}}&A_gxwRv9}?O zfVkV3MnKGcpGH8uZAv2`);6aR5NAK65fEcr(g=vJt!V_t*0yv8;%a+312OeuIs@^v zBb|X*+L_Kk9Q{O0AdY?}LVTc@)iC<#zmHsUn((vzeii%-G4va?XTJy9vqJxm5QdA0 zp~tU2b>XJv1G`v*h@qM<)*jPm%lnrIKVu9Tzd{W4pcv|z7DK&47%n1);uA-=yR74ZKZv|BhV+6y z#ZXNsYW}7es-@B*0WnmUMnDXWOd}wM>eC2_p@uX9VyH2VfEXH;MnDXWP9q?O#-tGt zLu1njjG=Mq48+h;=?uis(di7t(D-x)V(6H324ZLeF@YFrB0|K_!W&;Z@b|ZSZV`UQ z7&3l^7&?|>=(w~PnjFG#@w|#;HhZW)C*7=>7 z$NX|_I;jE+ez}fF5kkMb``?lI1ziG1UYV048|D~uKnQ(7A@pTh2z?d8Xz{#vJQ@P- z3jO`(^B-LrXol9P1jFk~YbuU_sjpCGtW79duGac%%gW12Obo@^QgNfDja8PZFE2B3 z6wBWSS)oW}{Oni(lXlv{S4VBe5)xHQd}^2zE0n0&nwT9+5-Ln}@8gdQ+0ZpKUepLv z+wgU?sX`gC_GqdY%V^fIC(ZIgg|Utyw2J2)!nJMwkzM9gcX~BP`!TSRo)628Z6|nmeN}C7nHSfV`H@g10kxwVOT1<}@eYEEM>W=#)~bzy zSsLF-c*B_Dy5bVE894S6p-_+#HR@NXeKQBx1YJ=AL&P z=X=J2%kvLz{H{^tn={4aTiwuDUPqqD4n>F88%Q79njLFSQ3FTk>LXrbIfRN>nz7`d z>tFhQ!jIxH5KHzkQ2zZWmhvbkjHQ+#EUo9g&989Nkb!qxe!=bEioA2)HLsx7KSBIe zEOpUuP*-ktp~sv~SKXNEhH*7|FNB%ri#gq{#*(_>4c3w6Hq@M+m-VE+svzd{x;VG7 zURGFfPQOe4Lb*9hq1@*ZAHa3%x3bgW2Yhw2cp38noGQA08L-nKWT#ZXPKnr|AvB5S zZD2c19aNWi>8o$|h^%urSv!rXCr9s&*%#B=7W)sw$bhyB6x$;}+x>~{MbLzU?fS$# zDx5)Wzej!JBGRf`tkf~ps#Xb9?XywqhOscCrNvcsW9n;b%%>^pCzxEEe_4Fpm}53c`{{k!mAy*K>dAolC&bix zbg`)=`6pr_!Kk{DRrN-(^4A0zBU$gF0&9&xYgJ)3*uYeyVLb0Tw$^Reof+CS{=Bn9zPZ;!z76%IR8en> zRjMFT-F2_IQuO@WF@I=f^oE-JI|v+8U)fmRbX0kLZG#t4%9ej8QTkm~2S9^&At*v) z`|JhZjQeW0oNB|+sMKYGm%SHX_J5cUhQ?xiFV8FH9`_LoQct}5$S3pU%a*AG%7|`b zda-Uy&1+tQImar>Dy+XRC8$Alr;WQWBdD^z!Mgi$g378&th=uusJ`0Pxhn}7TWpr% z^RFVLv3{)i5;p&8f>bZjbg=WUA*i9T&U^uze=R{amh>le`PUKH&l5C7hMq{ugSvaP}m zjT|L)PU}7r^LASIdcwGMZy=0Y_eR3Fbst3-weF({vei$YzMVgYz~VCd0d4+RhLj5E zFWvLU5j3`;8Y=ivgw;1xjH;@#b^K^TOVp5B|8_hfy5=_2KqWth;0CjUTPK}B7&O2d zY(h{t@797hI(Iy{#oxln@^-wn9ARVy;-rfcfpGnJX$;SwZ(F4 zFZwQDJI}j}o%&1u>=#}?_QEOBsaI;JR+Ls8Vfzn$W_(Pnp|QBWv97kN*z~#LToqKO z)xf&j73b5mt9Kb+c)PeI)C8k9ev?|ZL4vSYPOR>u1DI zf_fW2`SMpj8vpk6wJBR~3*x7sH$86_XIpjF{0)gk6(!QeXPRu4(P(KYK0T)XQau^f zkBy&-B}B2vP~Z#%&FiaPpxs6ipNY6=hfX;++@}7lx|_vwZ97z9o(u0Y3*YAq`96vG zY%IF^!h-jYwCMK8dH*h-@utW(x1CB*SyMNvQB8uWFSFcr*Mfek^Q)MimNM~Mz?~1n z^#V=@aRK!~?C*L5rvtfQAik^R`T(cL5(R@K*B3b5$t)NwxqiUu!9@XeR&1XAfzxxk z1w-WT1^}mzc_2X98he?rquomdGywCwV^lOlE&8L~ z6Q9=Kw6UuQk5&^^0+Y2hgR@*)a3sWE!3Y_DoeQck)YM*hj=!z3Zy#xT>@~SalADR~ z*EF`oc90sp4w(hD&Fl+-^+TzGI<$SJVbHp|AxRZbU&oSYT}Aq-0_yZw60NJqaH@cM zKb9oxYN;%sZjdF>y6TtFQ~~veEQ!&l$XKd?dPbJS@Ka<)s(^Y(mc;l|WM-;>1j3RO zfQrpZ6_8Ex^I9Y+HDByZf>>i@?k^G-@iNtf zK%6Jy)RRY=(QKS&;nb5yn(l6#=isa|>J}sZq5I^Krneja$ib>cS_%G`F#Tiog^7Oh zCkUF_-Iqk=Q^dvO`0~Ax)T&EwkVlQQ8fR)Z7!hRUGnAFjWwlPmzd%oj>4g^4$1Xl* z?|E{l#_mxcVv&2EcHHv}7SnOhQo?s$N|+dMMgYcV#LnYsxk1MY2QLQ5Jmb6g`C% zC8dWR4P56KC6zb0T4lD^JVr_3#lft-BG;d}sriwQ$+y<0S*b}kDw}=r=n#1E=ur9M z?W2d|JBkeuX+TNHEo#e0btFG+uKR%PeKNsR+9PC^`banfM%;t%ZY*s!O? z;=}*H7q?}D7q7$@KQj2@Bk&zP?@?tm@c08G=JkkA%WWny&wavLwW+#+_SI#qj}ladp&QN&8XU&dav}VpnF@rA?=Z}_LYDVAr@T%RpYb=Axk)dEm{RY;Y_ZgaGUfha}B;yCn*$!(x;4q?#Qf<6PI|PP3h{ zolLI3sx>D65$!=H*OW2&4x-THnldKmeHM<%f5P+ulmCpks5zIE|Fh|>C%*3}O5O^Z z3}bR#axlwpXqMllS=wj(ffn$*n?0&I&-&sq*iL4As7zul z!FpW<24J-wQ*Ym!q}r_{q|<@-rj;`h3R&Ct+_>P>iwop?k9CR$@BBHw^B3}+3p2jN z*YmuS_?>U7n05Vm%@@fT;+&~E-;D_1h?@u zQyo7=grn>|y>1Il)0s6-PQUHb0}tz{P=qOdVNl0gr$RiIh3LVA8r#;D+Hb5AEO836yFe49a5|mc{g5Da z)0o}-kRWB#nBDu3aK@~4rFQ2-!Wpa9mDU3%J0oC#7k1FC+e(t`xa zT12O$uWA!Cv@|%K44Rq z&;Lx&7}MZ%`e%ZMmtyAVjaLS=UDLnaVFTLse%S66dsT^@mJg#E|D%BHcN)tCm8xl{t7*wjKTnsAJ5*LF?^|XsYrQ$(^ zdM;Ed9z-Y%Dix0*6b6-w#}EpGO2uOcg<+-QF@y%8Qt=={gHWk>6rn+=R6L5%AXF+I zMraT!6^$dbvzzP5;#|?*96X$>UDv0rFui) zT&dm^I9IB-1kRO;M((=&y|_}*=-uF4sb~OiaIRD|h}XDNsc0Z?aIRD|mKT+3%d8jg z?SFURauKXl+`mhFh?VN2V5RyP>yM~ZSMImt*#qvF5LiI~rK+f+C4|IUr&6s$lR1^@ zGZ%wO^|^~drTW6fpi+J5Vo<5Raxth>U%MDos`V}gm5K)t%H&X~c zMdJqZc2KEk&|pBQRNuSL#!9tGfKaJ6BdDG2RH`2Y&XsD5z`0Uw6*yO_Z7%Lqs_g>j zN<}?q6RcdRsM~CCu2j@#HaJ%*?l!CU>cy3cy3Hm%SE^q`dAL&jDsZk;zX_Zx)$cCu zRH{D&&Xwv<#6_k0b7#fgHM5KE6N-YBN(VnE)h?`5{{$=5zgT}nrP_4m6?1cXomVdM zMWxasgObX|2G7q-T;f!!ORPRQ1|b0Hyu=}D_jgJ)s-#=mFg-NgGzO^i$SHj z#>JpgUF%{{sjhP|tW*mG2$gD~0HIP{FF>eNHwX}v>P7)VrMd}09b`_Wx>?{{scsQC zSE@w<=Sp>}i#wI-Hi2`cx?SL0sqPRsSE@S&&Xwvefpew0Ti{%&?h!aws(S^_mFj;2 z=SsEM#hprZpTN0N-H*7aR8t!7tseSeWUdH)tW-QKPCSH_>fvCedIal_s8r{*>(KP* z{QQ4JzEr6i8>muEa4J<37SX9x6I~3HYLbgVr8?Hdpi&*@Vo<3jyBJie<6R6Y)f5+l zN_B#ZL8Us;#jsMHBtWQCCkqfN)hPmmN;Or0P^qQ~5GvJl1Ot`oRDpA)njvtmR5Jz6 zmFhGXcPiEC0_RFKOW<6o&JZ|Ps@VePN_D2dxl+v$I9IB(1kRP}Y=Lv7I!EAKsm^tA zr&66KaIRG6BQ7e{7ok_bJn@9iCyU^xN~MAyl-r=-`tLNqC#id(4FIUJOzdfMIE2b<&Ve)sxHn5BA|W~uS7%c@N-ezU zbK>=`oJ5qSGtDzBX*L_>q!KYfs_i3X>KqLH!xpJTMjB^kmK2$nN@S*y=F5xj~rg8d1KV8~RsYDAR#WLwPkG=Uqvn$4&Etg3#Zt`{Dcq2HV#%;>p ze)PFpUzY(@qY}7#I-+A?4pL9!M#o{u8_*th6g^6Sz0DTz=+Oi=Hq)z>gX{7v~6{Cf>}9c7WwKksk8kBX8?n2Ax zao94wt=X`oF}6VF#t=i0&RD|S8Da?18cUd4LkvNBV+nPTD?EcV#}dleK#=ZuUcCw_ zXrKNrp0n|U+t2-3gj1_gDuJ^HBsvpXz36GO)yt2bj`8Su=W(u&UB7145$&##U&!QK zU~+9xXSZWlBJ#gTv`PVHf125o9$6g02*R%po2!ZD`v^5N(6qNIaz7E`E4$BHw>oe^ z-R37ds7LY)^if;@+nh%pis01q!x4NnJN2B1JQBgz@Vsx-FTrA+o?pE4xZ|&VNMxO} zL1$f8T}qo2B5h+)1(>f|Bl$6Usga|Ks~Q^1O2&DaYJ+j4fEl}35>h+KA_+#vsDsHH z%guCbq>$inb&u+vrfpFl@#%nwB$?A0^-`aRTB3-F%G%0?+OkTur_RPiq#bc$nR;Vp zht{WmG;OhXMe~WBeMK-{N4lz{Q{bwSf=K5W+R5`yVB^id;kmP_?+D3V1UV;L;(a|sn+q_(|x_>hBEj*@;dU!+2wM$$tW zk$GW^f%%k^je)|*MPV$l=Uu|vLTj4M+x1LI;a$Q&xtFU1RnFm_FbMVEj`1;RRSj_9 z>uP+J7@v@)Nxit{zeA*bPaP`$y9Bz~!FjIl5$R?J$GNT{(uRg=uGA?32u9rO__)>& zh<9`3(^@|yUT3QMhjvq^{}JJCzI+tx$Hcq&@=2_p5U=x9yI>&SPZ1Xjg`J*Gt&eUQ zC0D`CLZRyk8?Zj^dGP~#UfTO#phrD#Cr9gBHH#+>o!ash>E>T_w33_ojMcA&o8gF6 zo;`El)*Qo^?ejF6<7S>mbL|HwsPcT8o1N)wXZt*_=D2wyn$75e+NuF(n|+VCFlUz+ zHZJ}1-oH1AHx8JS4iNnTRKeeZO{ZO7Xzy=D%X!{jHs@1Ix0l{L<;E={^IYH7n$oJ` zx+7?ZivOJ2oooQAFwbLwnSqmBUPx!`sMBAO&e*Z1|6)30yEXnx>5T2$_%9P<-KD;T z%JyGD(AbxR$$u4bp-Y`|>(*afvvZp;K`Wz6>gYK8#t^Kpp>1hwmyjEmQ)|KZIE{ef1b!1(dieUzq!$IVx5eEtem;$cV0VmP5JDq+-k%=z zw+>$($=Yw}IUPm*xw}*X$R9hC{%*BDTpdYA2LBJOhB(-IPY?$)??v2LS>*#3cFs6} z2Y_{*V-A1-%LYz5P?HbZvV77(z_RX12YRmu^fU_>etZ4g&MRe&wmlemDjS`3piYLt zaE2a?pA|v_dY)D;$osjBCtrC#bL>mfs=r&Sx+6*d@|gLPtjbg2fP+x<%V8EJBAug;r;lT^0tR8UagCc~`n(kp; z&!9Dz2Ccaa4JWKw@LKafzk6oOH6mlQrZ}nV$C&w(thoaVia1zvXAlQ#{uIQ)nm-3| zu;wp89IQ#JYq;}ETa%a8w28TAKuc@Fn*F=<9(LG_$qRccI}t z?{QU;p{CE-e%UM6b^k3PGR}EQC8#bQ?d2Py)9EyO-ux5|hwN$D>Z5l%JUNsJ zb9l2R^d5V^2NMuhYVhv&Bs9?O^&&#Zc>mv4Rqt4s@qs9@IU)y247Ic`4&3~HVYCGd z-u?bzd~acl6Z#Y`S{^RAQe=(Ba8~2}mO*2*qOt~z(V7Wqj5bU-#%N1uz!>>N2xDCQ z>$}ryZYh3Llo*Y{OQ?P!86%lyjG{2Ux92^n91oFk_k)WLD}A8gVUcyt(<*_ovz~RR zA!!{HG{;~nZNMCdF(J({gbBwSLkSI-<8UIx0Ogi3rR&Sim{2Fm+){50r7}Zwl#oG6 z0|rU@Wnp}G5giT34BHj$Hu55oIYx)Gtn7CPnxi9?HeilUOh|KdX2LN?7eWK(*q;ay z9UD5{JY&k-9TlR)7#+M8=pR7FI51$0gx@`k@9lZ7DnmkaEE)CN7u!m&$rM@VyrvRV zm#RD8Ff<~MN21kg0#8qZ>&fQG6Eq`daJ?9z=QJWuO1!qB!n7HYrx;h?0%%x&EErkB zFxW?Zr4V_VP-&mYGen4)tpEKswLW|E!j|GC%uJSj2^%XB)y1@@szsg+Oam4~o{OL* zJnwZj&y?MVuj~5LjKJqgZyEE{!=ykcGw-WdeRXNIu}t3Aq#pK-v{~|af}p;%q-um0 zS0DZ4@x(yAI;T#dSxV#ccxIr!u0*41LwR=Ica*DsQn{Xr&d%G{R6yQFOeto7%P#-+ zr{afBm!ons1FU8K^>_G^M*R1uPT9&+E z=?YOGcuhKgE*rnY$sUTCz-wk7j&J07&3RpF^wqPM9Q5wW??kRSEmVSPwQg5GuBp7f zzSevt(clfr^uG>gjVe`;S(8lp>%+@V&r3AyUixZ=fwdLX^tGSzzX@+TW#sse=AQMh zWnghLlJdU|cX%T2`j(fsu2YPf4zoMh_0M7{|2t~t6scNXCNoq12A5Q`EkHzvk4@mhxg~xuq{GPjRxm8VL9i+k<^y9jtKHvJtvF%Pe zP(cax&)x)xVPe-cUkOw4y>IP*^zCOXp4P!lp0i3NQ1R2G&stDzb%QrM(;w<*m6_3+ zS}6Aq_rGoX!I#HgwE2XLGPrv|7fS`sF#m{7$6cTM{h<4Jjax-cu}@d4meJ*G`X?$b zO8oK%|N5X)-!B&0>k&1q0;1F>+n1RmWHsI*<(K)F9dK!%1MfIvg?hH00MK||$}jil zlnom3diScM0M|D*Xs%Vtukd@#eRomI{eHXJJVIS3saLZ7BYe7Y8it~pP{B3a$3bg` zBJ8Z4rc`)U`Z(XEDLvrQgbJ@CeH@yZ-eH_u~%+NY2_Ue3`*FXZzqrz{bkJCx! zDdx&=6?^q;9(D169;xf63`_Y9J{~)sp$IllNy=~Z@tzJ%p?S(u{wN=hnKsWbw|-Zo z{Lwybeo*OM(+p4fV|={NO=kwAG0l-Ff2@!9ZaJi>xK$~CoR2pnIizuWP0Bw?U59RO zt8TCXwXALHYN5a!LyCFG-1{sjNw?oF*9`|g}@ zMs>px^q3hbzsXOuJo$|_Q~&tfF!-F)QvO8$mE&XYeVFskT4L})vr_&ff7GQvJ+fo_ zHdVQuDnG61@vavfJAA6F@>sKNmA^vOZ)hQ=zQO=~B(~WXw-0F2wJsi#B2{$vrsfOTcIGX3qwvFM^+?RL2F~9HXG{1v_ zsJ*gXX z_^R1z!)i@qPxGeP&W6>RM!Rbx+u5*M(`YwsWIG#HYa08Q?sGQJ(y9FVnlIb4d4^75 z{me;j**rU^u>R&Kw``u7Q`i7=m|Hf_%0d4^9qN@$Q*xru{n@j{%^qJe_eJrx<|Ai% zTWiYfh0vACzFzh*lG!()$vp1|w&O=vEtt}~<$X_!oO89IP0nP*GaMt*b~TNG5oxQM z#=wZQO-*B9MB1XJF)-rUSX7OH5ov3h#=wZQElp!!#PjI4juFpCP#kvi%=Z01&A+Tg zZ}F<;up9fTU_soDmOT%1vAwi{?D=Rc&)duvtomr!;}@4bGeTsWyVY2bPmj#LSr;0j z@D|KjV_?8VE(QkV6(p4o49IIo3IhZ3s*%FLfV^I$Ffibq?lZuEX=_9}3Tcf<^l~3P zey=ONQ5P_wb zv&J9-%Ulc$SngtAzzP=w10LaGV8G!n1_rEjF)-kfggFKrfuM-M-a8+?dfMev?h$Va z5vbl2>{o;KtHn$(0_)IJA_Au$cjc!${~1>$a)k(Vg`~kTU?XPj7;uz}fdNOm7#MJj zi-7^hx)>Oc_ZTWCfdP+l(}4kxCd@J5cmzcRR_>@er`cuW1K&B0_H=WvUllCagch8L zxnKlNLSqRFj{Lpsih?808@MkE){lZYPZfd>Iu?8gvvw@VOE>C`!GgSOqcE@_FWD#z zEXd0>3IhxBQjNmEf={^51q;$D4bEujM$lQJX;21&9#-AtZMO|iiHk6c_*_vX$AXL#O!oad;aFSp

}~Ig zJahEuT@N1g5J3+Ftdspr|4^UzB&bOkb>BwaDARrQd-!OHU zsTU`)L8E7f{oWGoWjeTiABpz%6rAn%CDhCrs~u&q1*#tr;)FCD+6V)*oTw}$44_@+ zXZQo@R=q)iTlG5lgMBon=jq-))XMK)J>seS@YQAF0XaWA4YNSO+ttl6Ecc~HQb zN&jFU4JWMG;>!8w9bELmdXYI<)2y80ww(QZdw&yI(=5T~QK4N{ThrX})G|nuHTCU0 zek-P}HO+E-Yl)i6kh1+Y5>?jJ8!_7w8n9+Q5yF}{WEU??)^wMO3(1@>++kTe9xtLl3LlrBRbME0xzKblt*P ztxug5_cI#mkFcd^mda}zI(t!d@9U5G{Wt@g)bUhaerVC5qlTV;-_K3Uyz6{a8CiQ-) zJiZDsLzzxzk(bJAAA0bR*KNE=uL`#XANzsoSOU4&nmZimD3OK9zTHh~|UstdlNy z=TzPyA)F8rQ(QlO^~C7AXCLr{oZ`Y-W2d-Ab5E&g(ArDJ@7md3R;O_)K}}%y#dcq> z9P5P$tDZknPY{c>>CUCLC>gCUpFxMKGX(9g?$=Ijp16TcD znSu6BqrXYCm+7qeze^OZJpV(YN{@9b_$Q&J6;vNff=d5IgxKDHPtGj|%`2X9tFWxu z9EX+#f&PaY!G8mdV4=U;M+d1HEcV*DJ!U*QdFv0eMcz5+HFulHs({yCqrwKf_PQV( zuf4&9^xB(DNUyym3CC-1OUCiqYGxd-y(3ZZ+Pe}3ue~Qx@Y)(e173Td2;sHnPhM5L zWZth6g=NWW&UTiM$ZH>`dF>M)9i;MRuZ_9#;8S1wc(B|ylyfxHH9fN6{VaO}e)DL1 zMZj+%K{$T%nUH=9Ga>yJk%Z&7sAL?!#h7vYmLXB_Tc$+8Z&?xrzcnK?;I}vt;>z=x zA8fm6LF6nsYh$iF*R{>s7V29LZ8gcI^+&raOLaNI=p<3!n&(fy|HKoXksJP~zNsZh z>JP6A`0X(-C^t{u!of!XR*D2G7cK=f3n|p?7Cn{AFq*i2b3Zrn8F1iYDqsfIl zKUS*OAS;U1&0cy-Mj=m<)fZQfs?iJaW(BH{XUZz70N0XS$g^ci^m`5;Q&Op}VpKoU zXQ3DJw3#A%F{uwjFXZ{Ny2|p=>L_>pGp)>pG>HcDLi!B!!eej@uD+TnQSV}exo`rb z>Iq}Y>Kmq;eM5y!f>7x#r;jl%r0KPontU^JD20)cu7P-kMk z@MJKK-l|r}Gvon(@-%tCpEOk-lm48J@2tP(3;Od^mkj!I29ZI3(uBGxaxXJ2R!FBi z2!EbVndpdd{5eYy(w}s|1N)N~%d|h$_*DDzOw2?0GgeyAqt`(TFA_#~{K-oMg=eEb z&%vC~pXZ|Mgg^TXxM}oR%e$T-vUdDQwR4!Loiy>LOe1P%2|hL!@Mb9y(wn@vun%w2 z)SPy8(3`y65cDQ5IfF zN|O3VIzM}fe3Dl|6xQEdP@SYjkch(Q>i8rrgJ@Wt%V7^5NYW~ZhSjkgaAACsnq!00 zUGYh3jSWuM#3!jSHaOi7pQOgv;B+~BlGiG_H&I0;%(*xEQx>o5lNVUc zK29arhl6aNIEg2+Cj%$4cTJ8!e|z4890VJlzG(2?4XNv85IiD+pl83v+TK0gD5%li zP=~AOx#%P<0voWunSoB$Va+t)0COvRlA2!w4m4kZCF|Xk>g*?dk$JK~fa+u`4f2w( zdU~&3p07b(6V{-Te+^QnSKGOl`f?rYOnqL1_oaBCF0aAW+9sr@F0aAWkzIgOZ`a@h zbeZ*m7D?*p8hoHGw!x{Jt8sPSlPbBvsi$l3o)iz%*Y&(f91q`~xpU)m zlJ7}EHShMEmgE{q(4lL|_a#B6t|dQ^1RcAU{7@2f?ppFANzlP-$&V#LC$A+x5rnFW za0XHGQ%R`02=B3$2vHf&c=n!W4<3_{o84N<$_VuYYU1bk9eMJLz!%S5l3#|f-g%xQ z(YIgr`RH{GM;|IGV=hZ{FJ13~5q>P@w}}HDtmq6tqAwIFL85t(qEezn z^9V(QAkjQB(I7}Pk4Q8K5>0~z+3(I5tAiKflPqE-0fmxCTVYS6Y$!dH$&OJ6}iEWm(RCo38{y~5s(OU$F61`QTAko_-3KG3tq9D;fN)#k|heSc5cM=+q=$|CP68*CzSfYQC z1WWX*_EG=uC|W-xAki`38AWIKSawIEGX)3|oh3k!=w<>0iH-{pBsyDw zAkobQ2ojwmK#=HM0fI!g5FkqQei8+Vb~ZBVxCe=L_AhD_B-+`ws8Nt;XWODiL85uv zVnCvuor^j-OEm9XG{0bpE}()Nf+ad32uGp|CBYJ%lmtt3ktA56+ev~Yy1gV=qB}@} zC7O5O>i6KwYm&V8)(|YwyzABwEYZC2Ruhgy^WIxSutf9rTTvOauCCa+B7TFcjE+P* z^#p3-fh5u0())M8E4|Akpu+7)bOQ#H2*O@4_t6AGok1(H{z&CHfME~gGjzsSeI7{?S#6_!6b=iX>=l87~ zC4A*bwDc7O#4jk(zXm1xH}t)b=%df=IN+v+X9kIfIHPF&kbp#|T!}uE+F3`Uo$p7~ z&q1P{FGdsy6775=qCk*n=MxbHfP065Zfqz4N@qybL-1rl&`bIk!z%JS6u4T88YaA|y?s z|8yk!FKkF0iT>NgK%#fK7)bO#E(Q|)uZw|1?{+be=>J>{Bzg~GQlj@Ftizopnonvq z)qoeH`OpYMut@W{5r$xu=CdOV!7|OqM;L;2I!ZGqhG3zN5#f1yIvZ98cT{|Fc8ku# zrV2l`oT3ug)j{DW2!||M_u#uv?B?38$#@7o?|IL0INW{bvNykcyX6bwF*z$lIHZep zj+x}dWohRCV%@xeTstQZYZUa_IdWK|AlS}X!wN;k=Cg)%Ba0K?e9*8#L9<(v6%7ia z-G)$YbZ73ntt42s^CiK$T_6b-?t~;*x%mSg^Kh1K{)9&pj&}1$JceNL=FfOMPcM8y zjNE^4`yJKAtF92vYk7i*5q2H~Nk2h2^R2al3)R!E(sR!QzgLyK0^{L;4>w`0)Cn#Sin!01Pk~qK{x__h9p?PXA>a= z{L5Bt-@EV5w(|TGN5GwW0+sPB67aLr1pFKy>zz7=lw0h`rJs~9X@7p8#eRxf?0zaj z(geIKtV)?}MEo6{t&V1mlE0!e4XE8l#NW_q5Ja56pwl3zIDbE(b94W7s1WS1h5kkt#-(220`pSxh!g-FAOXoq5jHDo`4+KfKWJ3t! zK}h+^lB-_d+PMBd@f=6W^>YGJe!eT^bE)Ms0b)LINnRj8kn#%!2vR;zfFR}b1qf1p zkpMx;FBTw3`6U7bDZf;JAmx_{5T*QbiGq}0AyJU>D^j4ytI8yG^6R3>$kd)t>CguP0vEB(O zzqIC}ap&B4w>(rZho!u~s*Gt;KH8P?G1Qva>S&~VtN>v+K2Crj5~Jkbl2o5A&dbb<-g{f)9U0!T@DhDaim;7CSA&>3n@R9 z-oTae84?94pD9t0^3w#0QhvHbLCR-I6r}tNiGq~RCNv=BXG(&le2yeo%FmJnOZnN7 zU@1RG5-jEC3c``{^CZDiem)UG%2(fY-DCH5UHhnTo+IVbc@QKQQjp9G1WC8#{1C>2 zkn&%z+JD+DeeeH&r`7dy0#bgzE9DPR%jZb>g8~F8e@K8JGL_x}*ktj&{Qi+0;FC#P{<;x|(QvR$Y zSjwN11WWnzf^ek#1xc`!uaE>w`HPZZDSt^4Eafjtf~EWwNwAc^DhZbIm6Bj7UnL2a z^4A36NcroMU@3ot2qER4OuMdpOw*nzvOel*G&_^()Dx(TZXf|P$HQIPVlB??l$p3s1le8$tQn0b4kd?%qwuk&IRhri_mTl_52Q{G3*(YB;Pyn|WN{F;rvfKSg19{y zI9VFRRr{$wWh@Kg_JrVMc@Vd!1ScyPw+BwBj|sDrM-Xbx4^k(#*i+V$!-){*K3#n3 z{EPC-ddka-%(+k2DB4oshY@)0Q?e>}?o+Zlj3!qf*|Q(s?EdQoOA4CFgFbRn>2OONyJcxrca)LNGBR7bHGg>h2 zIAcFT1J1}J!th zLjK?szD*Kva7yoBdB7=s7Q<6a(oKh6T!71&6 zI5?$!5C^Ap2;$%r=fXtmTyTnWU!vm_zAQ1|6uvJ})Re{bd+*sb`H|JaT)~=xClvV^ z$!_G40|FlDlsqtu#`nAfxTZ{=b;H^bHy&k90-@_-a&+Tn-^Wx&QjtG>FuT3dAo&-m zpLECHK^)w%D~N+T{t4pXj(>wVxMOz^2Y37z#K9eV7WsS3G(Uia--?x z#sprjU2<#~-$NNsSq_YM^?qOOKjnobf#GG7Vy*F-#+DSry?VnklShZMEbN{*qfXyR zjt}DzC>fl9hNb!}96yyjCXDA|KqCEFAFfa6G?7$tLKr{PcG8H9VyR?P7{A_yMEc_c zH>1o{a$*=iCv(z>jGCpAlfw9o5hT)EB;Aa%Q^{k)xar+VBQnZKC65c^PH0HvZm-j? z)*_Xh9L7C)P8yL>UMhKf7&m1>BE3-LmZ()KIVFrc0-Q7=qc*AJ31M6khD3Ur%FQT0 zl{_(w>k&>Gkx?R*JSmJ5(vV1ZlHH7wspQFFoDFf(h>Y5$lBa}mI1Gt&5LxZg7V3~n zP7UK(4UmGr`_w5qrIORa_^BwQ;LlEUiY}?-^e}#@0x5Xct4`51l{__!8)YE{Z>!NM z4oD?ugmEVhq~O&$ouYdxIWvq4e2{`C0ddl-qJ}8wuD@>X(qmQM7o!Ihx)6oxW2KnY&bTwk>lVrw@fwgh)l-OQLLi4y0S_&sv12W z(TM(WO|7TW>ce~@Q-~-lA6;2m-lUFXZD?q!EYrU;Dd;o~af|xFSN(DG_M^RzMd{2f z>R3A45JygiFB~GL$S)iUBUAAW#Syg|e;D%9gcIApEi%s4M?%|-tLU|B;kBEqi+m$| zbd#1Bb*X|nG$g`DH)*i98Q(?t=%$gQimS|VP7yx2sjjl7skC;KI*2r?v*pv9bPj#Y zVVn^@y-9<8y|5Cv2%X-fF0N@%mzSuFR0Ju4j&Cx>?Pt!*iSXG?70TYjo6KD&=o3D` zN$0O-3nJDNe1MZRMN>s>eRZ)u18#I>LuGA^QZk#6PIMA3n>KpvjXT?Ke?(Z;aak1% zFe4MtWlcesO+@c_-aRT1K{)?7w($L_qwbh3GR|GB64aGCH}A$?R#(Z?soP9-hamO} z241YTVR+-1#^GLEoq-v9m0*>&qP~2jm#O>^Tj|1OqZ-E<_rz8atSzPHJk;ekvDXk3 zcN|Ua_TP~EzC7$XQAl$`k1eDQ*HA|6O?dYheJW>9=_`o6jj!o>6S#M}apraP0|u1s z5!vQU(&4J^>MpJCLE+ju8r8=go41d&iDDtmg^6|_Z=@}w>d0h!Yj-|l>hQwG%Ifm^ z9`@qyf^?>*IoCFlNN3b~hmO)hX0*lBv_vz7CJ7A>udf?pZqYV%zlaH)ytm$?WQcZ5 zG?wT~$;Z`{>hc=0J(EW;tB&I}YzJm_o_##^Hiqa(gg9CGtb>Qmy8XrFTZM(qN#`YZM*jc`vHKgved`@sLQ<#AlX?ymMYr32fdy*?o^H_Z8PP z65T5s@dU>!;m!mEllG$qWP?34gYPJsC zzV2s6o{vWDwIyJm7pS;^gN0TwZY`t?mmPVL(D0~+5^G}<5-%~KlbiVsL%b{rWxX65 zM6VDb>~vA#72iC&r7R_0#kG^Yf8EcBtRg$TmS(5dqi7P(TflZYbMEB2bIT8HDKgKw zf$ap>uq!*g6^))zSBFvbHWk)w1y)N`)lqGucL+6+q23rG<6R=e8@C_e-!SxosXvNB zxo_MHoBQ|ajXy|x;}4_wa-!ZmQ}f%vew}9)h|Jx3)0>*TPomM{vQm8GPpPm5g{W97 zQPYxSN7hNS%+{OF7=;MZ_2zRzVOZ7p8FwN7ue&evp}^=a1m zCW?meydu_wE*DoW?9(P&wpckGNE3SYA?s{Vtx9!WLj%adMk=j^?Sx+B`v7d`Dk7T# zu$`)iY!1M7rXun~0Jakqku3q(&QnCT24Fi)5!uEtSYP)pw-Xw${*Ocm>#sj})u`cH zXP5uK*6)MX|B0;sbDH&kiK3xBuOnN3-OV4ox$wCsuM?T)bYbiFBkTVjg?guZB#}R; zuyBd7K5;(sr$oW@e@PT9|F=Zdf|!oYU4(|qilHW$M(iI+n95*?eo6ONiBjO50DKlDH-hN|kvq^c$(;TRg*^RDwqH(G7I z^rmJXj6YXoo^!oQ0HQ<=I4~M5S4R{>^mnJS8We*6AVwkNbaQwxp@EP)gb2}#IPRRL zd%G-pXPYRK(~F??zXwHJ&p^Z#MtVi@)jUscEd`w%@NIPMue(+*5_#u5LlMW#e_!>! zs(%IV+mDKBPiJ<3g=#)Tq65uk29co>Rm;oz zLdeMB0l25?g)4Yi0PbZ6PsI#dcbd^tiA2>#37ti$MAc>P8ZDEk>LY2ioKO=Gs_ub4 zRuCZqV$*?NbUppZx&4LHoPZ#CtfYWAGA$rRMA7%2*NOw8DONZC)abkSioA2$Qb4de z)~J9eEv|!rsHLJB6au17q7V=xB?Dr@q`-NaDQzI z5yCbf?47x$^P5Be5i#S~h9vPMvdzh9wmBt=X3*hJwkf&grdBtUtUpWSozs%ykri=z zG}=%G(ReBqRAFG38H`yAm=VrQiNXlyG>P`MW7E?m+Q*JdXGyfLxo9PFhD7_Rpi`Ee zEm5U)Iu_3))Yy9f)&Ds}2z!Sc_I$nQ(r#Y}n>h9+0X&E7eQuh)&x@jIMJ)b3>(2h= zJ#TCy^3LH{>`wxCfwFgLCH9Ulq@o%WddKr53ccg`5{2IJMT}bim{`1+P-7bvq0ly7 zLWHo*XGbo*<=m{fFN^X!w&{0OFQLxPdMxA=PP@+&zuO}4hsp<=wF4YZ^P$$U&aib)Z z(!kjBCL)A2e?2O7$+{8eJ|o`PvE~4@<|4A@t!dW0EsBQoyp?RtiF0ape!RYFgUCDQ zb+YC_vgV!9Xk{-NhuuX*H7Ho~Zbl(`bXV&hLLqw4Lib97XNUeL38f2Qp~XZ93!Ps2 z+ar5gEj>rPg=3+CXrTwlLJy`{=%FYY!}Er6+jst|iH~JWYicF(&Mh`=A6-9{w_V+R zGNQiDOzz~-c|aN*Tc;hLokxcO#VQ(9Lf!7=(Lq28Q|YuCwbTYbto2ZfVHQ#x$Ax+|96e8SU4#Q!UT_FkO0BA{GBto<#1y9aDwE2piCkac~mIN#TR(=I{ z7DrwU>?|&ftPG(+J?}Rakx&nsubBH;_1=+%BJbQkRRV40Mhez=znEIMu-EX#`(u#C z8fq&VO;ZvdKv;cadG#pMmc$1VsB%+_B-)hmK?Lew*EckpK2&@#!PdZ8D)Qrp5vbM< zR7%}fiVq>s+EsUz;zJRPXi(YIhHw0E#KnD8Yd5XDCcbmsC*rlueO2(<)}rweXaVA- z7`3(qNW{y~a-KJsgLd8C?j8R4@vCByZ?0~+)fG_1xQ`^1Su`xB{<3}2qGBwf#%!Oo zsKmu=Prazr#q8LqsLaLe$f&5?#q7AKsKUkUFuCXm7qf%pqTw!PhsZ^hE(QbSq9X-p zhsQ-D1ZW4xMO6e^$LdzOs2V}xmKRn({q)0a&U`|c&$`8$PrD_QQH0ls713fSxTUBb zJs^%XT<~z4%*3qTa`G})pQfbTQrcJ#VXpkrFIHZoFr%489OrO>m#6UTA_{e}64^Cg zljxV2I98T@tn&;gJl;52M8RzfUsyB*%P9`cJiT3;Z%(-WoX#TS9DVhKDph59J+9}d z(ntNMxS`0M)OM~9wJ z6_|$8JJ`rU;QD;rZC+GBS=rURWKqILM+@)&)^q)3U%hbc*Z;5gK?jxh`wH*(qbIoD z?=MmC{s4)B_XkQ8ygx{y;Qhf81@9jwQSkl{iGufsN))|+cmM|P4-3HH{o()&-Y*Hj z;Qi774Bjsbz~KFIf`#`_ij6+^r{Tv1`uUFc?JTTnwT6@TD=91V{*gX9T6q7`zm6O- z>$_QZ{=eRbX;|g`qh-ap$%M|<9t+?yy^^iz0Q{ZAi=%yX~dmfsE~l=DZa4La2BySsK8 z=RmX1J9czR@I39;?pNrQW#z&(B=RFE&O6eZK^AHz4@=QUQXWFB2g6`Emh*pXst5 zlPCC@Zt5{0`1vaFbMW)k0t7$P1wFR#c7>(rT9LFT`1v}Cf}a;i6#TqUqTuK2B?^AN zL89R28xa+LzUPV~uKR256ITg$IDV!oeGB?|5$1z_z7<_6{5-M!jeGa|vg|UEu~VO6 z2}RZCrPfro8@dd0Hz4?Vxd6e>&k7Ly{G0&6&(8}G{QQCd!OtrM2!5uE9!!zI&veU! z@bk;!_vmNdDQ6lk@bjxOE%t{MY+<@R`Iy~Hf z;ODJaI0J&8>DX`sf}iQka07y$d4f>e6a35*gc<}t^9-S}Jk)2NBQz+~XPzW9DEOIY z2@MK<=4nEMf}eSs(4gRFo+mUY_?adOg`XQHpK||M=Nu+y{vAKtRVd}>ztPXT(3I%s zf6%3#cRTBIw=rk8`)>@f~)z!S%ZSF`LtPs zg0uOkS%ZSN`J7pUg1h;US%ZSV`Gi@6g2VZES%acdx0kPhRl7p~2A_8fz~J;w0T{gA zIRJy(y98kH`~C!riL*#)asPJDu9E(-6K6)S`=VeUfD>m$e4?f8n-vyy522fd?>B57 zys-81(kn#ck;A@+gYO#xF!;VP0E6#G z5iES4eb(Xq{{G|Ar0|d9d%F~>D*agUJs*LFzCS92ZWg}Z^+3y}H%>eDFOj$7dsqrp zzCT0wo)5M%Mg!mTsa6IB-}8}H1_j^qc~%Am-}7Ns1_j^qNmd30-}5n61_j^q8CC`b z-}3=h21Vb`C5u}ae1Aaz2H#&8fWi0k0x|agdvM2t&1K$>?_sG|`TjoPdp-%p7!7>S$DkM# ze9vc~7!-WZ2cQ@fe9xz!7!-WZN1qrJe9z~e7!-WZhn^S|e9tGI7!-Z~1X7 zF!=td01Uog5`e+?PX}P|{WAd=e7}@n;rm68cP~Hv^aEG^f4;X1)5`bHlJ9wK2Yvs1 z2;D4vU$Cdm^K;KFXf5(~d=CrL%J-iN->;>j8l!>l*GUw7|CvO=_n%7?eE)?+!S`QE z6ny`cM8Wr8OB8&+UZUvxZvrs*{@VZyzW*)&gYP#4VDSCM01UqWJ^+L7HxVp+zr3Ku z#4}&4yF>WLsrPotUHN_s`F< zNJzL#=o*S5C?E(bf{4-tl_DxADk=zqU_(X30$332pn|<1*ickN1#Iu^J~OjBcm7^J zAO6U9_V(GGnceT!S^k1;{VIu~^{XX{*6%A(w0=~gX#JQ((fTzKMeEl}6s_M+qGbL4 zaWGncKpc$L9~cLt^#{elX#K%)Fj{{|9E{dKpJ8Erx8oaEJ$hB6j>15^4hz=jRrsN7 z{b8IHS%0{n3@xmGdY_&n&KYynZjrfdeX~F}O<4b0{(^1&=@LcjUnfzt{`C??>(7uV zT7RZQ(fYF_iq@YkQMCRXiIVkih=bAkbK_vN{=7ICt$$-2jMl#?4o2(W90#NI=QAv< zU$_2>MfIMj_p30FZGB#{Tg2ACg|i~-FZPq6#cEFf4Z}ulsoX9z=T$p!EuQ6%)$1v^ zIy;Wm5HyIKf0+Q$^5X@FhMyonwEN`(M6*v6AXnbjp<*>>+)G2N`tEKV7PjWq9Aysd=C7mGoa-qcTFse3 zCKYzRWXUI2O&|XD$0B3P&Zd#yW7~N-82jgJ0d1@StMsLWln5w-HoRl|xcmuhY%2PFE9PGs# z@l>rb=R{MrbRXGROw-$4@p1JtzAeuR!}Bz~G-{UR&k)n}2!FsHt+kUV+P=L+(f0Wg zMca3fDB8ZGMA7!0B#O50EK#(57m1SXyT-w2`)+YC+P-@njJEF)2czxJjDykkXT`y2 z`?DDqw(sn3xA)gmOLhtSShnY7`SaNJ1)LMvzR*Wz7PepZz@*aL<*QbRye-?CW%=`k z?JwXD*tV~eDB6CgMA7!cB#O2lE>X1o2#KQYFO(?S{vwH@?MF(KY=3bajJ6*Y2czvr z$H8d(OX6U({iSg*+I~zNjJ6-ku(17ee_ejU*C(FTNZ7}+Jul0TXWLKUoXGZ<`^e0~ z_P34w01?QfAepzTfYa-9}!Zz7j# z6m4(9mTMGkZ(^2f6m7pmevNFuG!91F-w_9+?eC0((e}&YV6^>RaWLBc?l>52e-FdL z_CrqJQM=>F<8je>RV+M@ka=1DKDPb+oDn+yxv_kOKmQS7u-Iq0_9Jul0@!?xeWIg#ym`^e0~ z_AfNr`PDz?-2c@7vb|ZB|54cf5P!h7{ZA4_+y5+4wEZsI>-RoEzfai?K2jrJWo4r!CipE#Hw=_g;gZBiHaDK%_` zh&zq=QeR{KjOWHVf%If5HC%i2b5&Ml%{X;etLGk(Re1#xKvnAWEd|It=Cr7nb-TYl zUZkh@3RgD;l)xX!y2DRL8MOe`Oq3ugl69w_R#)&B z9h4vt$y(;8Lvi>EEl7@J-Q}lwI{pIU8Tj+uNY>qcI$njp(1Mgm);)fj@!>BZ@V-B< zUL0AK*LJJy3vR3+OWP-ows(z6c$$G#~yUF+qEeJ)jR{4p~@E6_GFB(O%R{LoW5`Uou zjU!nP`l%PhUvyW$NRMQ#@zc%~{z40yM6%ZUsqNq|pv}Winnto7^3$yY{D~*Yh-9tv z(@qHeMq4*ClC|DXXVvL9T5>`p>tR2wpVM!&eVawH9`Vx&XZnqnG>>FG>Zes#5fF00 z%|nj28T?h63y>>ScFp z0H9jmiJJX%r3A~!0n*;B>`mQQLUN5>|&85QLoK{*(IDrNBPV5Z065v z5zH=?q7Ec#70m9*qT+&@f{Lo1B+CwFm$58bQw2dil@CC4*1 z5fUyzSup#2mOu%L`8U0S*%z?Hi#bV^tq5koX~sJyA%wK34{_CkYAH zXL2z63L)Y8ObKRR$r43qiF9*KF#9TzB$02f4Q5Z~Bs%nuSHq;d>wprk79y--Qr-*@ zO%WojV^ZEM5KU!~Dpov$CFRY5G}nkU@f?2{h9@kExCw*b;y$7vw0Nx#IFh#mJm5UmsMJgnA9oPH|kgb(6{@Ol}JtSrPx&0tpCuRJ-uR*q6%D7Q}3$ll$jN9b*AbUj0 zkWG{FegN5{Qign*ly?YZkFiV*#kiP1gXnP~;!++4(FP&nLLLFp6D(4lL;Un1Derek z^Q1@<&y-1dMYX?1N~6)XppR#f$;6n{aAr$vg|KE*Q0KagY- zCsC!0Ct{#mm|s34(j*e+3`nzCq)8;sS&-&gktUHi=Rlh0I8AwV5x2a#AbH-Fu>0Kz zk{4_VJKxP9*0^E%9w2eo2bW zxH&0r35Z{2u~K>B*x(LG^NO9OW8&Cg8Kl`R(j>Ca-H_&0ktUISmP48yoW@gyo+1I` zf@r4@(ex=PZw1I+lQOo*10Z`{%Gf5WLG}jAp!yvX+r=74^QK6X*e)J|G;fJCiJrS2 z(!4FwBzo>6kmencCed>rgEYHDnncgt0BLrMG>K+?64JbDr|Fbv){T(nJ&`8SteYUs z`yx%ESvNzPJt9q_o}Ys>dqtW=J-+~HKHxMEW|DfBtswZ&60n6|1i?ov01J0Yw9Lzp z=3|j2(K6d1%_kyFqGfhKnomWVM9aJeX+9Ha5-sxvr1{)V(>c*HZ$X+bI1LQO?LpH! zApBAa%`jv)2=}oNG}1ZIrtd+TuSA+eo9=-$`$d{Wn|=Uk4u~{~HvI_Fd@a%>TIdr< z^NmQ8Xra#_&9@>=qJ_SIG~bCdi5A)iX}%X}5-qeJ(j2tYbV;<(*O2B1ktR{k-$I%n zMVdrCe-CL6i8P6N{sGebB+?}6`4FV}S)@tS^Usjx7m+4W&xaw+VUZ?L&qpB5uOdyN zo_~ilM?{)LJs*WMzu9TJChGY(r1_oG)KFm+$V7?Wv<4Do%0!9Y^bjOEK_*J{ruC4hnM{=EO^-mL<|dJfb6E!)zEx3b zZI3~M7A8Topb}oeibi2iN$n`fv>PC8OOw`n!0LadeiBl*GO1P01w}|+HbIhXlcb<_KthtukR-<>feB{9bmloo5|&94 z<})uqnp{rfIH$qpHEyK8oig^ir+#~MzudQ@?KyAXZlFoN_oh$2JM!^QuGp*&>DyM( zV%l#Ho#$4>`m0cksi6YeQx8;nklJbw6%s0fvmR^F>G+}Ie0g%$3(g9edpqo*50AAHvGi=X3Mk+2-8(>#5vu zl{r+`Xa9kte@qhDhwinqhv(XA=weF!M%+yR1YO4r>v#J*-GC9tcIHN!R?P>kmZ8~kNsHZ-oPv!6| znK=S2naOdr@Qi-uMN}8ZIn|ue4^27H0eW&L(XQJ%QMwQwK`^hrnx#(T~wu` zS7(}5522xT1lmk)^KNyK7q~jpT$zCo&pK>%rgdKiAoYGornxLr3x!ZYt24R9V^dV& zQ8W3XjN?R&J2-E*SU>Q`(tBAwgni@7czCQiH zvi>61P-A6-;u8C>CEm1Dy;UD*TX;s)jH~T z=9vtY_bjL>@zi$~gR%aQQ0wn(#s+{bwEoUvC|0dhuby7XJlB9#;MywIXXbf~^^HY~ z8~{@@3kVbLzVW?tB3E~Kc%0CP=kBNxRCO__x`gr}cP}NaI*#&Y?6^+5xoO$rsnwcI zTY%Xd5ILdtO4TLc;nZJeUV(~Mv8*%A1wHn7b33nZHF~_cn#Ue*?&Yz^n@f4@@#aPz zd%U@h#~#mj@r=h`OLcbHs#{92V12j z`hnIwg`pj0lO5(zE}k8lXWl?6cc5cnJB&JO%xlA5+%i*S8&Z#pz#A%dw_5J@FZO}~ zXZE73-CFQa6-qp_H$%|=D!rbk!eHuIP(`en9PHRtYH6SxuMa0v%F|7y%0T_gy{1yl z5S-t0T=m1g48;HnC@9Jhn5)w9D=fyC3fo<$<8*6}uOWd5yxi@Y%92SBUiP|Bhz`7r z3PDBpCq)mSY&=D`$Q(#Ib)4_OJm~Q0jatk+_h^UaBHz#tkO1<9(Fl9|PVlReQm>1D zjq-L&%PUJgRlm+yQ8A=b;o39bFjy5}TGekd*0;E#)a&NW&Aq;hUiSLsV`Klf%aWCmh zkmQoTcg<^ka>m~xUyme9D|)gDZ!{!%6KjFHjGGNaBsrfU?lKlI#9hWhhPcaEWI;%h zw^$I8ics6L3c{i!saZWcq#^b-2o!@=j;PxWdP&?IQz@yx3gD35d`zgv=`L^fA z8x2HO;4!buR@lU;*b2`u#8%jBL1=|%EeNgfoCTp3o@a=y@B%|@g)I!R6}B>Db==zs z6jqr1%l5J%KWzC^=nJg?`a&zbOjdY>G9fE$Cxt^G28X+ot4$z%$2KXsoOl=Ci6_ z7)z)aIo!42g>~EhYVxfppf_^B0%Fa_Q_Uw(K3>gRW?oK}bR2cI96Qpn{|s7lVEAE2 zWE>g}31IP|y0~Is0r_Cs8n?KlqF|tt)Xu;^UrT543*;c#o%mZl~?85Whl7_~r z@K4e=Md2HjoP2UhyBVGTXW^;$O?#RO&#lbUe57(zN{T6PMg`$_uBp6*;Gk zh6JD%Gt2hZYrM#ptp2WrPZd@%XieXE{(1GVMYcIxG0%*OU%eR>WAGM zTX)5btdkxdG`4Px8ChpNPH1f18#A&ldc4rsx;$oNUG*TjvAIEp7bT!ksnwgt<_=jB z{zyLt4g(M^Hh0PJjU{MhT3~LIiF+asJvZ}l_l4wap=o_jgfy-E&!5tGInAUS-y1iR zZrS)g9~sPX)PqRaetP~<`p-w1Lp~LGhl;fo`@_)NtQQ35xy98mv{Ga5;Em*LZfzA{ zYSb4r;pRy4Ao z>+k=4SC>v#2_<3=flBl&6uc7~S#X(LoNE=li!9+d^Bgu$(dPw!oH9A{bdhuDW=Ie% zG67c7Z?Ptz>89e*{>2p~eexZp%yd)tXlYc#z7&9E^%wEr zpBIJE+@%ZSb%N;>{5kzj@)6{&^kq~V$Ju0ZJ>mFYpKLh0v7A(fp7pB8u|?8nx=}du z4jsDgKhkGW=5DmKyr&-brq4E5QB`GiL7!qL2z^F6PkvlaA@IzlQpgP^xmE~V;7|%N zF~OtNWd*SkPb2dvvCzorfBrP-t55R-|EUqR@1R~~NxvD5p3aU>8d*SUrHflx-Un9oqb2>yW3aOB)Po^-idlZBEa+uRVc4FU(v7MS zfH$FPVX?ow*ztR>ET!<0M4&XP7+!TrDZD5VDAbzJATLV@WqfnO;h!5{vsX^y(LJEp zUJFP$2bGa>u51C#QqH4#JI-X&LEU%ll19tJf4xz$^pyFIK32*=n{y;Sz)=P<>QjjuCjhnSNC427{LMFD#GMjMLMm zz+4M2FI4wRK%yTNn`b20v8mi|G-#}-2-Bx1$xTM$^<~iO!DD8O;v-~ev%q{KP*trP zKYCo<#7V;@T``d?7+7GEs7Iwl8c3uJ8d%6_#Helmdk61Zc^_~7KlaaMq3 zz$VlBMHBj#2O9@OScL`k0IpMAJz?39XgyVc-w6kY%_uq;dM~8{LL!Uzeb)Xy`nJk2s z;rQz1ba53>RuI)&b2*0C)K%qj7}=O-2y>X%+={BI>cZa8Tj+6R4wIT&U7+?dm7oFW zBZr9%1-iS=VPCIqJRs8?UUV1DVM@I_%T8~4b+xFUUhTsAd8*4f z4~Z~`*V?^NL5rM1Qjy~v0JWfhpOJs=M-QLc`cjc^=v&lVjoG2iDRH9%R6SK+nNv!A zh+CsUHB`^($zZIaq{MsRG^dQgngQyrm-d^Saz?$HD;~`0#bB(zW-m{ty%~lAM58c$ zP{mL@m{Y+bl?@Ct;cd;FN&*GzTy*rSS&`fiPY@N=YXwSys-mbtdhIT!FXiKDuw_n^ zlqFtjzGr2xj(=`_=xmX3XbWqQ2b(#gL0MROtwggb5*<+38zowkW@*GzPXkzh%P}h> zp!3S=nt`4UcxeQ3j}{N~JZl`4T@T?wG0L+pBTy)&dPUa6uHD8xF3N8yh6bEDmy>Hv zqXqDSA)%*os>V$KayYr zEax=_i(rpYZ87D%&QL*NF>GL}!AWY)8#bzk**R|#Bq~07#m0G;m9Ob1%10H~npH=Q za;IXJ9yQ*lM%7jOzgdAqiD!MY3aMat$Wv?3EJOkd7k9iSrZs66B-Ib9`oZ(Ls7jg|2eb`2&MtQAH(M_ouXL{cG zDE|a-^%^U{sX31kD%4rrq_XwYacj1TS{nz2TBACjAa(L;9XaSzq&de?r(v+uUl+SH zt+3wgHX`HDFh~G}Dl06g#WO`fm$k0?(`%RgsFbuos2Xd30>#=zR?gq+N(bD(Mtni9 zUGNvM?1QN6gDE4g?5%Q!P%%Z>-z!SFr|7I(gCb`tdxa=_omKXsl)GK_VFZe@zg>1( z;bUbt-X^|4W%s^-WxtThei3CvWgkh!betPOt*G~`TTcIXO!HfA7deOKLjuqW9DZUi zejiJzP7memq0IH0zX2^2$$*>ASrd)hP6EKwR7 zQmE2kEkB`JeoEPRwQP~|8C3`(ewtdgAJ}vH!n@Z0E%FU5@M;N6S6j;UT`_##0*WBFiyK6+wdZ8Uk3u6_Ci$LAdT(=}Tpcpnel{t9T$M(e= z>6^kA%l`d6+VGxMH;XxSPVa5OKrpxK=+~qDUqD-sO8u5dK5tGMRL9;)u`lJ zdn$STNX|jhvl6KBsKOgWa(*Bh_VB32gOQvcX|&_vMY^D=k(@&`uGF8^)oK{Y`RSwb z`J48BwexY68ah{%c_@gzKfQG?=KRi(#w3hRG!NQw(>IHHqOSI>Ng9#=u*wZ3fsn{@;#gP z4c{a(4yoPSSaDHhHQdq1UN`)xTUG&Pfn~ffkFcn{L4CrHlP`#ZpR}b@yAD0`c8L7F zt^)J-${v0an_HNV9$;4y-biH>e9`Q$#~Y4%q|?tL<21Fa>=m46is67SnM-a(B1WaF zqMJy>Vu|JHnZZ{cD)}u=>4U9LVA<=_re4^@9mXY=aL`936~#Zk`MEEgJ*&U`U&ZH0 z-r<2(@dx=x$#n2n6@M_JqWJE!U&I=_KctIK=oKPQL+U<-S|JKwz{NK~W2yKm%V8$m@A(NM65{$|&^y_D}7PUeICNlOki|^%chJ(|pNX@(}CAcAG|w3cWAA z|KPZNTVFdaK4IJjK7o2~!g_DYIg#Eod{k0V{3HD?XxaC?vfoACR`HG3kFbhw1sAq7 zZ-NVp;y*Qb+Vt_qm)s#fVHKafeiRqq#1f|BU*e;ZisCkq>l5b!_+n{ZOjKJpLpLa zk#}eVB!CV9)?O=3XaAC0R27Trm6R|qE5H%ZGCi&g^O+}oDpZXs!`rE6a*Ja5bw#oE zP72Jc!ml!1Sz7L$jt=i&49y9%lQ6GSiQ(F=w876#cw^d6qR8HGjf#xk_y)BkUZ29@ zTKFxhx8tY{S{$;!b=I)~fw}vKik#D)G0HGashKa?XrnpXEt%EP!p6KKvEh~m6AEc% zaHEkd16nG{W>mZw)4P1%gOfI$aafdGzZipNw`HOEx zHoxdxk-4oF(?rMGY8l5LFlxEX#!xNe4JOnw!Qe(MmmAPh%S1+nTK3)2vw7PYj=a`o ztA$(sm8_PlI4e@iWFKijsO9XB$IgAVYEh5>sTR}pU$oU?M@^>2W5-O!1Jq$FVzN++ z6*JkW#fq40sl^0L7HawJ_7~l}D}7IilG|$G9_4jbi;0g+YI)N~8gQKD4mY9(*&VN& zlQL_b$UJmEBmh^esgQlj92X8W=%XQFbFRayfEo~o&8ZFrcF=npVL83;sOP$2p5E*6 zC!7Zg!q0D_UPbh$Cv;!*SdTka%fQ`DaSTT##4cn3bs>DH$?HP0!;7e*qW1Gs-GisC z+$QsuwKtu}$ENn5P)Tw4tZUEfK^nx`e>luU^Oy4luQo|hnf~|%dB#LU7D^XO#Jc*(jZe&!bVg0u3SMzS$aZH#?s)2ig z`K$)>z5uCVp^s`TuKRu6<^FTWy&b+zWUsILX)W_~;1cwCb;37ncIGN!Y@jwz!e(F2 z>jcyiW!UV>DG=6S70A1CU`Q|~()!20&nhi@t520EN7H_gz$*tf^$FzcmrG}F9-c@w zah!`xw#`oHwQ%Q`H(eyM4UN*-syMGWa`M*;?{f9uUG&xA@NUXJpwNyT%F5}SV)$JW ziJ3#|+wW?(^NP6-ix1(PvmXY1N$7P$5dI5Yq+e5^_a#oQIEZ2?u{)OeclrBEvp`0 zzXA2Qj_YxKLOo{qsK}xo1;4hBao{HMHZ8a3s;t`{@|n|r-;09Qc+wgM*z3F#cEce*6qV) zHv;za^ts`%*@-B?nF4P@xG`9}R5!-LOR3qovEtakKI-*F|csW&EXyf0{23GGq>E&1cw>Hd( z;9E-@-%<81YlGKTUDC!uPQ=>y!9YSAKQeA<;}C&D8@r~??D=x&j<_QWwl;W(@C#|< zFy%zr_?0RyM$L13?fW+Uo`0_u+Q7+#r)V=mI2*j2o#Pz#<7C#yxdtPJoM#}`hJPb-jj@s2?)WgFUZHgOEKjvv&b|v@YIHEqBy$zcy z^Qs1Lc3gD`E6GQ7%8p(a!+SXzgo`ICL+TqoV#L66iQo|1tB9Oh59wt%^UW zoEk(`92Fp{;+OzY6~`GQRs6{asp2m}1jnq|IOo~fwH+Q61;(j{Rt5JW|Kjo0uoKr_ zT7`W+s<-1j31&yXc=7TrCtfk3`A(5{+S8B#TBB04=|+0{a5SwQqk_MnQB+5zL{T4o zB#H{DGAL=J+CZd|z6^=E_r{!2e|{dBIZc!s=iXRubdMTtEGD*x*H~JG`}wH;LMcD( z{_u-UeYZ9hncGS+eaL-6Ddu4+TPZ8J3K~VFtduA!hCz8C9$UrIB-#yroJcT7Ju58kRVoETIub=memV? z_PzJh#6C^RlSij`pgymqHeAD>_(nG0bXALH*IWQ1SkO=#je$t` zQy)z;QoJq`;N(d7GcF~hhUFT#!J~fQM#7)_#+HxWc|}^RNdG|ZW2QvHU-;T5Z}KfX zSd7{09z*@4Q6&7OkCrYVGaQvDQR7H>pN~c`O2j`(kA%PSQIDj`tG4gdPntx+`+c+# z=Lx*M=BAPG0UzyEC;{h{5ea|oqs3SC6*b3Ed1Xez-}q>fqAQ~x$7vP`f9tzz(;aU% zSb4lc<>W1`=!%9T;qQF35~1?aqe3mpjfB7V(Evn=Q~|W4btHVyM}3OQ5Gtbud6DoB zKH8b{1Ql9vVkG>dk2Wuqfb(h-2_N#&s;T;lnu4gxoD>QFXP}A(mC=HZk?;{8?bCUJ3N7dq z3IFD!tqdjLygEn1zx!ydQ+-9vD^;nxM8bdgXvU%|qn{M&76~8ykILwZo)-xp^U=b9 z%1c*9iwYv)<33`0B~k^@lEO&%Paid6RWzuK78FIofB9(F&J$E)zS~Oth-q@=|Cq>S#`w&np84jYS>I2}gn3 z;EiGiS&(C=5hkY>(d=WST=B>XUrbgO zk0`fzYu)Z{!&aRrveu6%d!}c*cd_i=l}c&Zy_D*}aE_k=@U5)@~5zOo?f&UY5X zc}b#NVI1$gq$XxEdT%m%g*1ALa3$H-aXxmqy+3sE18=?8@@cu+8~O|q5GC_cYT(etYk<=P z*i~O|4)ZBJG2x(LgjCx=yLvdHyq*-t(TQlnF_U!UIG>x2ve%pE?^=IH(}zUPp?$ie zggfkYbnC}oFQuPbUC^^6R^AihH-VZ`OrPbAhEyk*Vmhtz!h$}%bttzK(`}iFT8ino z;HXhuetuo|x{4}z2~b_OOfg+pQH2vwUo$^3iMupOfkJ!pGw_{rI=1k zCF`uau@u>jby5Al>abEwH>MJIbsBmh08+Rk)9&9*_4zve2r{F_yQ>;&{6c}Nr!P^! z2c5lk1l=(TM)EJJi~C1am#j0o*n(AkG&qVuSXslqHf1z{!g9pOP{LohN0iY;~m&QkC?WZ70@Z=JY*fpd|_IkXHC#EMnUaQU2i+ms0| zTpoq%5@ir-0-{l=jerzhg~ukT7VlE{W{g%3@GWX*5>-y)up7|O)5H~o3xc_6?@dpC zU3$GS&KOS?jEnDO5oiikK!d=f2d}Z>=bj*T_N#ooP~av412uKvF{G+z81~uicy?%s=WV#ONUfCU~2Ux{?9#5MyN@j5Y=R z*LKkRfS5kqlJY7Ql{^o&l2iDA3VI$yfz|c0&Zwvn3V!{BZ))y&tHbQE;_EtKsQ5b8 zjn1j0yeaDzPI-%}0a+U-`|9LDXU@Cq?~uqnElD|9Nl_(4L868gaN&M^X}*e!q=JM7 zQe3JUz#SBGmVdMc!#mAOYytx(Wi>juIAnVREMYr?AM2 zlQZ={g>XFxRMgn)R@vFYwulm%?J8SX>V?X=_CK?QZe9Iy`hN;xjZ+D)VtD%UAtAj zsu=E|#czwEyk=K64-cT=;~yL`6Q~Ib7qLXo;%v&2bxMts2kwk#9N9 zc847bxxtUrGD$i|<74X>VA1f}x^5oDT6G zhWnE%N5Fe_b>5Zgzz9EgejZ-voyEV<;9lx%cq1LOVhl6VnmY62Hnqo}9LC0gWNS(qr%V!hlEm}F4Y zsSaDfD786srYl(>H1y22w(E=gZtwR0Xo$Ak16Q+#rX*-+s-KkMI5~z!w~W3pR9-K) zwa7lLwW3in0Pna5uJtFws#Yw9ZEiZ3*n>NGzI0t2+|g6g^>J_~PfIi6;LdtoC@?b) z?xL550<+@au6lJSFgp(JrWc3;a}10YfF1V04UEQFU@i-U1sdOe+x~gKy)SoJq>p+_ z^AKs}Cbq!M2^N^|CuKWMp0U8i*K~jWosqA~3w~)Q*%s)+?Rk+OyEnBM7r2EBj5`*( z(_1W2RR66KMeW}vQJDEDAHAJXI7)#nLO1UvQlJ}!7A%zl-7d7?4kJ(|=%S3S1$RmT zjCH&Sbb)0o5LR&7OzSq{_yso!N0nAkFH@*#THqeG!tw+w-0LTWJC1d|>HNEQop9js zs`Etl-t{JG2W*7TeaY%&3Ty>mFbQZB8^MOMx}T<)LSzQ9G9rKY#8{HQSB7a29Xi|Vu5gqb9>(3 zx8c%_p9r%Fr|`Cvp&|UsPT|BggsgziPxg15Oyd;M#dT9#KNxpmJFU6p6oxSa{^Sz% z5VJP~OXh~FQFIDdqUaPU5=Ez|CsA~Y`VvK_Xkbv!8tS%1ASh99V>^&4Q5cmd9%#s@ z*1H+jrLjQhy=ln@!%uGYp&XzJy)zLv<_;)5LGMlcq+-W;!Qr9GvWbO5*JscBNLV#( z8zdkiHawgOdWT@!sP_}NxEe*hHt*JH1Knsa>@K~TFqgp?pHT26?ED-t` zzqrBm`HE|%QNf$Z=EwK=CjT_B}OYO~!~KgFP* zYSvE)7gwXGpHhjUetH_zYO`e$#Wq{cD7IN#v=8)>f=+6vuE$}$r2yCmXKWQL5E_jY zRR4Nc`QZOL>4pO(^{kiHXccR;Izgj-{iHm{dD&?6uFaojw*GVTuTrD0S{m)n8m;js z!^`31akX4rjiN^T85F%p4a52~ie5xo8XyH7SxW<@0Js9RG>8R4OE*+x&3u2$3!Owg zgx{%m2(^~ZXDwZjprtxLDa3IU1>>}KTH&#CNzsSrTRj6E`o0>rjK`{D*BI_ zE2K}Li9cWvz)Q^((#`flw6wOOLeJCEd3(W)>T|@=s2a1Urt|iKtD>V->b1Ib-dn(B zVnxE~SMsNdb=)?!WS<_tkqB$$sp)1Tv8bYVtftyYg7vm^vy&L@RjXq&0BCj+iz^EC z230!mBSO8wLr^(mFMh9X+vyvna=e=kS~*JX5ZU%xTuV=%PNnts0h^~^N9t9pf1K^7 zxlcR$M|7Gkb)Jkm=TnF27q}436m@R4)pV2*t#jU0b1}Y};-2(jR0wx~Q2KC#8>RDx zn%h%-O6#0A(;$8iU|Qw8kLIfGNRNcmM{1I?9-SDJhq)t&noZk{%uBLSwTBQcsSZlvELS1NUM`0DWd*6!(jK^>XW6 z)rqS8P`yc}4m0K&jbamr_}c4 zS8>c#pOtIQSkx3$^wxb=ZYfu&vLIGd5`||M3;KBvCgt)$3l}t0=Y_yleOE4@wQzN4 zl3EpnM14gaLCP)X98pEE)s@?eK%t_St}1xq^i4N^DyqUNf~ug3DoI6sC>v5y6=_4n z_c^+JM#=tnhNX&pz4$)WB8p+|JQdytV;JVj`=0rF2$^f$_pAjSqY=)3aL=^Pvk$}> zcYtRED-K~UUG~h4yX@IAcM+9R#377z9KEW1@_>J2(T`HbCJtfl)pi`hT+^Scn1AKU z8rsXbQ}kyj?V1pTx#PJofGb9VBN(Z7k?7tZZZ zKM;!O@Yt;%eRSWT6aG^X=0&bt3i+5jn6e>7452zZ&dp|g*S-ApCx7jJ`pF{S&_X@F z<1l5pD;j`1dtu6QR}x{?Q%*&oSWMFls3!jdAntEq4*F${E6 z;y@(#K^mx-@LtK0+%3_hD+HD!J<0RQg~f_Yvv@J)FXmgtk=(~jc(Q5}o-Frq@@;XR zdGX*Yw%xns&WJqEOjgqV>I?y2#ZL3cqvK+;=U=;4ny(HL#G*Z|DbdSnXwb8`pT2CF z{tDICE$t7_Nhr5V-%gkq_}$DfXC-(Swwe#$JSk)K?n^U8_Gzmjfhu^csz@C;Wm{aIlB{8EA#crp1{YiHlEV+6 zvYrJsX9i{(IciR=zszDZZWV7f3q)A5uFIn*4C>bQ15r%<+=X3CRKr|W!@M{(A)8WEJz_6rNnChyulv{ zEKI4orRUNSul;gzid9B#HlW_;Ro z?*qk!J%NY0o;M^VtCfQGo~zDHimxDqYz)j}G_Ha-vOp~CObia5>^Q@e!+pZom!HoyNNa!*ry0oDSWLG8@ho>R0L z;Vzw;D+f+xgDB&IWkH~i1Ds|ARuep((YSh_!2;0{wQV-&-}xocRib3r5pl_|;_cb2 z`Eh2=4s-}m9UW(_srZ+3s%m$?*(gP1pSGSWURhgVIH7YOxm*E`TK)-i;R55)2sNS% zbTw$HPOAitbmFstBROI7>#p)QWgluzw6&#SB+jeDod1#9A9-O_!uq_Q90MSS6rR50=)xNJ;(U~%!|!> zV4uGZd@%nVY5&m2kf5dzoSp|lZcl3(;+kb0&zfqc<(lQ3s#sZ#>T)5%Qi+~$xxJ_h za7m_DO5NU!tBgA81LbZ7gDR6M=s^eQ!=i2_3#y~V6*_2uJ}Bz)YLA$)w7hFuk00)N z^O(?_p1NV(l&kns+`c%Da``?T&RAUdzNa40hZ#qu{WR;{r7h0BT;v;4C!lq{UN`8g z=XP<6YNA>P>in~7)*P$LV$eyb^=H>CIqE9u6@S+(IFbVNqQ7gcHuf)7B2T$ysj&>U zAvEi#D;=pWFE^^eDR7ax&ynh$ZM0Yh7ti!{j#T#?M%8@UJaX-xO9C-O-J8?vlztbk z`j26`rvp@NA*r^Aa={_0TTEIM>(MuEk9AAEvqWxkrK$DknnKVTF^mhRVl+?|ReeUP zYtF?aX`Ffz*Bp%zNB=)Ou>019BX;%|CTud0zvFcx?$30L!~G@hY)^Cdu#XDsICJ5L z*r4t>j$N9=svGKmMKfJij z)5Rj&(ATPpbgjl$FVqV=47J`KGVQ!31{WQm$|2LrYodjE1tVnIx7V$>>Zjbcz0DLA z4kJ`W1%*u)*i2D3*+SKfd0mM*ULG>HW@{jzmzsx#xRJXx-eu6#5U;Ah+sCGwPxP30 z?XIQmc8h8@g#|TTP0ztY{ZMxywxFlG6G8(>O^)+}$@J{y1Kxf3yA#h9nTCE+nU)om z@|BPvtl1XF$_J@;QlTEfDWY=lIw#O)&|0z8Y2js4mDViRdRkOe8|1~>K+OP^uf8mx zCQU(Ju*KU;khR8nwN~SBt8-`un5pmHrY~Rg@%lY-gzveauCLe7 zg0xf{oJ|ubbiv>p(wI09zy112`7>u0TqxD3mL+P+E2)n>j>GWQG*nR_J;ok@m2OP2VA(AiWt$5~|*F+RQSg{txG#)(YR z)~FI!Mms?NY!9HXbdwQ{Mb*UIn|@#Ak{6Iv9nLQ*s3>vt6nwIgW7nW&5?3=CH{O`S z0x`%s`f$o$cMKaRm)G?m%POd+gupbu-g0f+^_J|wbeF0uhBI&dyyLb{hJ1dX&_n2a zrHAS$zTXJF$3<=pyx3NzSBpX;sorjNtf)+{7KJV*3|`2CA7k(P_<}Rm^_s9?k;q-Y zC#rMDMtcd_j#ubCZ)+ABL&XzU_C8!xbm-g;z1oXhL+ZvAAkk_IwSp#_|rO^77^?buz=LXt1_y1}J_1{Ncu=tedV7nWjCa z1}M?;>iqVVwFBDMRONTJI-Cp$vZr9(-DH>$dkXZP*v>Gq^%Us6t(|d-kE*3W?@{fH zQw6BIj?|3P1n51ZopHJVz4x;-&JbW%J;ck1Fqi}%>PB~fGTI5eJKg=sXfJR$c#4;P zGV-MW`ckiB%P;{y)fe*NHaiMT%ug+VQ7Q^d*iS8hTfQjhEWZJrBnrB)z;T9y|DfBR zJ+Vp6=mBrWwYiHRL88IDrkBy3h9((3;)W(|GS2jo2f(Yz#w}u3H$B*5=f(d@w|Lfe zi~KG%RUPwfzc@$xMSd60F|3$pN=IGwt+EU&?3qHl>CtM275Ge{-Ss`Pj6&9c_98eC z44jowB+-0*b1b7+qHx4lr7e+YN6$Y>8CACE0Ozbw>(!PlNP`hGJf1deR7-;mWLbWyE~s4R9wSi5;=?(?dSKdh=g$%#(H!Bw$B`?ae}XM-wkPWx&-G zsF}CalVM#g>_#=2|6p)Yk_rNMG3kn?Q4N`UquPJDg$VNxv!#2)lJzz3+@ss>Cj!7K@08{ z0%(mGvmoOhDS+09zgW%!#~Er`WB;RPyfR_kshwnNRLwQMnP5}ApUxU)tcW{nn3u8A zPpwXnxKla*!}76LJSe_lNIV~ukwD`8Y!dI!os#xkud5y)KqT>j0z?uYBtRr_^RkP| z6G?oCNQoqVz5tQLFJMra%#gTw=0)L##D|LX7Ksm&0z=}%rNEH*2q`cmexVc?62C|a z42h3qfgtfi2d_F~b>+RQg~6IIi3@|FTa4x&`jWUFx=qHVKJoxT;^Wut2z9-6;au^R zG$wKN6+;BnNskjGZassbQX`354G#3xIEA#rmJUT0-U++2az0z=~F`nwhw5;s@hmB1o#bM0LV42hd7 z?}EgOAKsaM{)m3x3ELSGm$pL}xt?8QMx2YBlrhss-XKW)@RYJU-SaLvB0ghCTzw{v z#8=xS{vh{xUcaH%vNP5Q5J`Nk0FlHW5+IWJIsqbyuNNSa_`?E35`RR1NaBwQ5J~(o z0TPKnE>R@$4H88Xe?p>2;!jExN&G2^B8hKgRJnyk;!jI~A@NO8U`YHKDKI3ySqLl= ze^v?%i9aU=hQyzj0z=|2NP!{oEmB}ee5(`~65l2ThQwc#0z=|2Nr55pmxaJ0@mHk4 zkoa~M2onD>KYFNY!^FEpGikykZZ#8ZiaVLaUrQkI*ZtJ$1c|@WGTZIG>z3x?8-~O? zfPW;A_#B(WO{55m#7&e41tN)Ck1qg-ByQebP$`kbZ{j{vfk@&v3lK?sz5tQL7ci*Y z+mQG|fg2KEByfwwZ;=8+;)|ugkoc`qU`YHnDKI2{yA&7_U%~=G;sd4yAAe=&oEE}h zhQx)z&@Jxd9(q|^58Wo?E+2V-Ao0_W&blf6NZv5<6+`0cD~Tk&T#)#^Tz>5sNaFWN z6iNJki6V)w5GaxON{J$gKOj*g@l_H<5;tLXm48?>@dr7%78nv=BL#-U*GhpQaT9-6 zXJtryo&1F%@%2Jrk@&+>U`YHC76=mGT=h+>)sc4T!ghwlrR~r~9%mQX5a%K%Wjx^{ zZxAHjaQUx0_ubm_D)AXZ;_5STB>t97;%{@Gr`^MwiN7O2B=KDWL=xXEKqT>Z1&Ad6 zo&b@=-xnZ~_#OcwiSHF4lK2M#BohBnqDbN&Nfb%^V~HY(eowr%EK%Y z|6B?TiGLvlhQz;=0z=~aguo*4ucW|`_hX^<+yIz3EU%r!@IZ&_0~*z>q%j_md+bb3PS=nyZ(S7 zf14eDz>vPpc0XXq-e#vCFeGoY&kq=KH}CQX05jChd;AJE%+2?V6l@W90j>FK-0*gx zzzuEl=D$vFSi4xHH>Azik92y&*`<_T+~GO5`qI?jvl`A8=4m?2@fKr*dC&*SaX%%a zm)yHMF{3xx+HqDJ2k5n7VehF^C&_~(p|zF+B(ilMZEajOH~ZB}k;v6%!&-qz)n>z5 zfymTm%Njr;YTmTgE`&U7?f|HiNYmy5fC7=F`Q*RSu|?9nkF9aT(R>&|X;BMv$`_2K z&>4o2GYpr`&?aL9+1+tk!wNX=)udD&JLB0dA8rw!NNWQL=o4|gyb;Iq>Yzu)(>$oK zczKfmk(ZwlAoB8N0U|FyD?sGs=LCqn{Ja2>mtPPd^70k|A}?gDKNaehXtY`77x2%`6pG= z!=jZmu^S?`5^RMZ@(B5(xDj&ejE{ZP<^(ODvZd?vq~2{G7oT8S?hI``ftE+Az7lDf z4-n{%+FKpxyVtr;^|mobQ-`H6q-AsC4=|)2boR6oeyz4P z(lQ@$(jd|@pKsD2((?7T6A&%WutB2bnF2&wo+Ut}WxkcFK18%Uhf*pXTeN(Gzzr?W z6}X}0c>*`Ie51e(E#D+?L(4bYxJAqJ1#W100pX%IIB>`3^HO|s3WTMaQg0wFh0bsb zIm2S<3~e%QCA$k+9&$~)>;D;jP29c+(X#qP94&ul)AHxsi&?b%g#eM3zZ4+S@;(6~ zEq^6Iq~-krL|Q%|K&0ib1&Fl#jR29BzZD?S@^=zNTK-<5NXrK$inRQLM3I(%lqk~j zAx7h9`6nqbwEVLa7+U^C3JfhD76OZwf0Y75%SWWZ(DH9mU}*VwDKNBbg3##|Cqv67 z4xJVlS~j8Rw7}4^iAJXdhL){>bgK0mS~dac)GsVr{#z8cqoL)0SRfkWj*rrxp8m<4 z#iAiHEnBSwTcM9<%l^38a_fvFKeahQ%P%eY^RoR#KMWI}U|Q}9jUg>BvoWOQyKD?;`EDCSTE54|kd~JdraEIo%lF!_q2>E**rMh8 z1#W10g}@ChuN1hUu4K1%GT+njJd30Ivy&3Nd^Dr$7^Pmr`rJnd9*%P0b zv5sslXnEG6s;_@6d~c@s0@JekLLx0cqOFaz{3sP%gGkGd2@q-daRK6Nd4mlSEk7YZ zq~#|Ch_w8a0CBdwk-#`wep=v$mNyC9(DE|^H?+K2;D(l;6}X}0=WN`f<>v)%X!!-g zMQ_k|$gv0JzmoHtuoTm>v=lnSHgbj+r8Bh2c!}&TXgPb`#DbA`zB*Zaf@jO>6LGZc z+N;=w-5r0mRm}Jq2*Rm zU}!l@3Jfi0OM#)~94Rog9F_t@%ehiuXt}i%7+TJg0z=Cu3V}t-ZKS}^@<}WZ4KXQD zxOP;ti?)ka!nAC)5^RO1FfE^&K+C83sm%#m{&+`u+T!YQoy8}Zmb-y>B+&A9izmN_JY`YqD(>vlS%(()GqL|Xn*fJn>xY>;UAD*+-c z?-wA_@&N%NEq_g594&t%a6`-A3f$20cLF!G{Jp>pEguxPq2(WJ+@j?l1#W2h5aFUX zIJWB9Hi5D!?+QyXElW$GGtfim8Hc4aw8{9D>@H||@bneSpIB5eO?-lBS$!gomLoPT zx8q*SqUH7iL|V=lAkuON0U|AT6d=-aCjlZYcNQShau)$2Eq4_l(sDNe5-oR^DAIBd zi6SkZDN&^5vm}bNe6~c9md{}{j+W1r0z=E^Nr9o|0x2-GTqpzj**=2#_40CwTZ)A1R+V7V9bcV1}lM5k% z+Vc}uLRYBI`xy=5_A^e*2>QtCj`Or}g*`XC+3vi~VY#1?w%KxpM1oEeXTm~UdfhK0 zMK_Wta&%*fB1xwUlvuinM3JVON)&lIL!wC3nT#rHTkF~R3dy15h>vTh*- zhOJvlfuZYGLSXTAmJ}Gm&Srr)HMp?psjF)97A%ndK}Y|Ue;CuDgXFSOB57YBKqT!t0U~J+6(EuJFo_~*50@yC_6Uh0XxNMDKMlxK?)3MUoHiP zv?oe|A?-;*V3GC}Qea5?N)`yxo_tQzJ+Cx6c0{xio=aP;1REm1-IWplc310+seWp6 zjx!m0dprU%WI|!*OPY+FEk2Pp6%r^qutT?H)JxKFf^?LRjQUB$g%~jj;M9x;j3)Ii zfe<8K45W-8!y@uQ^Cn-sb6JmVaR-!jz{v0R88Pj7JtRT`Q8=KzvE!<9h!`P42+QxAmC)izl_Sr2pNv0`oYHR?h`xT zu1-F-O_<$_i~y=f?V$3LSowiCag*DP^YI@1 zYwmXUQ8`87>;1iL`rhSd$N*{~UHDj^7{|8o)l2T!F>rH;wvojUbt~zX8%#3_r#6+iU7UWf86Z?^d4PuUlpMD=90TZ zfH3L-XLolRu(+t8q+gBhdv$Ky1|XRyKgWmI+X9vyyn2{&%a(FeL{CA zRC`aa?%OoIam_(;&n;THyZod@q1q2l`DX0+pKtt8WS+*VEv>+aH{jOr!k$s>EnHSh zwTlIas=ZZ!sM^~Eh^oC^fT-Ff1{A7YYU7q_?=ZNf+B+E)s(q~Q%JZ*n`p1W&_WIdY z?O3YzsM@<(wfAsVq}t_v(xT)115Sw~G-vQl%d_u)da=kH?&@i;wOn=syw(B%#&wvf zCpdGZR^3IrPa3QW!iDRoWKS8)(+V70R*tnX9`B$#Y4>RxSK89!lT>$8JdTe0jKMuE z`XQj8yV;;ny6W1BSc#79;6BR&(VG>Vv(WV|o4!zJ!0XKhsYZ*seSvkmh4Z1_Y^$Ht z2oLlb-5%*$S~VhcO|Hl}Z6hQA!`V^s%76n071ZkZJg!;7P++kR%Hx{l3jhmi9TgAP zHA@!?EOt~NT-PjHU{9_>;JRkbBDthy5GX|1!CtTEZ;D-YM%6#-p38b$6uXIzQ{xpI zHNxu@ZZu9KE!>!&D(^UtnXKI><~&%JpPwwUPE#t=8UZiiJ`!df=rpJoYvzFh)QvU! z@B|%DKh_Kc1*juy7J|(WLWH?y8X}tCX>Vj--eUHO;iAmc{Awy7XL6AX*hS3jgPPw^ zKh<3*kUEl!NAN?|B-k!5>8zUFX z(%ypv+Cx|y-F1`ES0mgW?0%{p=;bT-OoO4f=yRB^wZ4izp##de)(R^sQ{P5+%^EAI zOb3;5&o%j5E@akMMHk~6v>>gZ*9jj;jp;anszs5yir9b58Y*=$C4SP3%YP zuL&im9n`9TS0FI{ENB8AiuOvX$;?bX4VjsFXEKwSnQ~IUm-@2Li+~|Azv^G5<#fBs=Ja{IQLD z`qtB_PYjOE39AS0r;G}YeWzKMx~=(bzY(=Zj>X!eYQJFBe#u#Rs%_=&^OF{ZYD2d_ z8cMlts2tH4)!ME6ep|IG_yd+|R|*hS`+xvZwW|b(s$DHWRPBQX6slcg6cS+$RFR;1cT{iH?5xgBOpIDF}`p=9*kGrp2bBWZW& z>6FdJP3>uF2IsC?KDunC08y_e2oUw!On|7@<^n{$wlJWlS8VbvZCvTqTkvvQ8C(V2 z&evhj+$@R04w~YxY>9T%anIZwiFVR)&s=k=3LL4drn8QF=H|+@ut%u!ZEaBU1r_XbxYKuyuQSPYx_54>SCBuX?S`4tBN&Bbp5@B+2Wq~J9fpYv)ji9KaAm5Xy zNwxnPBk_D)F{po6Lle=r;)6uixc!TDv4Ag^t5QitX_++S=CKs zZuAr@;g=Nrm&WU943{@fPh*WBPEX^E#M0Ac5=A|YXEaVv6IdYhbl}pyLv~NU`cF|6 zqbF4r^ruOzrz;ZlbY&8$#DR4s?rNh$e%vtj_{`@-=AlNAptihNaD z7A@#g43YXGtvl1vrg}z@??7Zff24Jn|B!W1vOuJD*Z+{|m$BSP>u&!cgH1qxUcE@` z?*Ad{tYi%$t$PR=JZssv7Q&1B^HL+N&lIAfvJ!YDqP9{A(;}@oShRR`rljb#*RBaI zKJgUCdfTKWsi~RLlhZYc^>=5J{yQd~RxPiir}cmYwbj+0{>thFhx_Wo3uBPa;kV7Z$G4r;JEf=$Q`d_GNBS02 zEP3b4sm-^fl$Sz;SWgqdi+ybmCw+I%U;QosxV&G1&O9{|9Ob+8nxxF=)zwQ=bYyc+ z0m0EeiU^((E$9!EJ6Ljr&o+t#FY*0cfB)~hx^%iKr9?dw>Iu>#!ApH}zn%WTy*-k? zP64>24>+ItNz+JhjPJsdiJwpTEW52IfgW2)G9$sUzNh~UL|(e#wqjj1?F!8z!EwI3 zHr?@NgO$fCplapC5Ih?^%bypH1TQl>LWy>*){)?N-_B`I3~M*B)7A7Fo!g0#-~?aY znaf)|`^&rk$KHE~S5drw|8r7-1j34IbOl7EN|7dr zfYPLhqJp4w1r!7k5D-yRii#9P1qDQY_r3Gp-7}N$c|L!9ukZ6*zl2MCbHDEQ&hE^% znLS$;88b1qsp`RgnGW-FYdk@0Ph%D}gZ;9US#Y2CeQ;Waab5OpNWjQLx`cWhSUYlVHC|$}CWaX2E_>JJO%&_l$VH z`(&O0_ui>)ErR`?aWw2!Byi_Dcl#Q}H)7l>*l)63e5A2XnYRh{o8s8>@ugF>S8n*# zmpL7dIngfIZ>pn8@a*k}i(YDHB(S0*g8iO#RET}*(Uf9?SNhV|S+TWt2=<%i_;S;} z`U%Gl*HQMgJIS37^a=28q3&ts4kh=ruW4^Xr|`956@N@!e0m-4f#vA0{7B=s^pD>3 z88f~BWIR_&mnM$;Fp;0J^s#SRW*FPEZI7PvTDx`UGJp0ml3(oZ$5(EwJD2gvgo5;% zV;}3jWuM*=?K`*a$KUTTzUpD!xa`wDBC>sl=*~T<=3ExPuhz%9ec33B4*&dfpmp!E z@`Kvdy0Pc|Hn*uCNcFL5XZ)aM)((BEbNE5c=e+s*HGWX@`O0h|A&yWfX0uItZeCP` zUj?P$fTLvS9Zp|CH9vDe&34hpXdSMI@nL44Z_GKEO~LK+tpzPNeZE3|LFSTME~cAN zkQZM9weMEuV;gOcT#$XYa%@j&=5mbQ=MQE%N)xqfUHH<&&c!z?H9-@}nxKiUnoVTg zr))OSkFTLMlsn44-2Ys~^f{jWm4b^TQWN!wpf<98ar8Ru<1LBtVtKD4KIU?o*L!I! z>h+05m5WU;H~8sM`17laDKjxHHen`m;k}MoukruPDoFO7%XuC5F&9;c)wFn6#eZL^ z^_uU|LFz+ZMb^mWx0n6`FFkz^sW7#^*Vk6zT&1W^@~Z_G-DyO0tnov>*Ecqm=O!MB zdwr`?+Pb;+mn^ERyU`0S>}?z1cSo&#Uvm*r_aCgfU$%;obuZ&}#mB6s@>}=8fA9Hz zS-gh2-xxpC_lcl8ILu>$*GaBC-_lWlm+}j%c=t7T%A(4kC%W-~uGO|}nyW554|?P* zu<&163xC!s2ZJ83b3W#B3Ne-@#EJ{s|IfmYqtA_3N-i?ND7laQ`4+DqeZ0HScOQ*K z|H&%cy90kynCnC@boTf9*-pr{MA+Z!xbjrKd|^J#~>pD1%St~m9H;5nmCH?2C| zvdS^*blb;Vd?Bvdb=uT!cgnSYR_s$sF2dLK`k+5qr-0WTpMvP+1bhANQ~A{+W9uHC zRmL|qJhlg)WU2;x{o(U>_T{9dfv<=AVwWTC3ikTb$J~*OlbCUC3kvqSYb_qxxk<=f zE!gXxkGb*;H+ltLfBF3MLz%}9de2mj^c@eX;B#>x*R{YhNrY>vhP> ztbh;=Y3s!X>|c0J;XW^Hs-=`1(1fym+qLCEyY-PF5O~dL*nRDOLSkBF>-gk zVOCE`Mj0n)*G4rNYEH=mc-N*}lTpU639ij*GR&Nkzjfr=l4~-`xVyvkrkZSEPRZ9K zU0ZWa(sxlf`Iee&Ximxdrptbc)@TGIql{}lF8gU(BiYEDlDiNt`>9&@WR!6Q$n~x| z&&KAI^zwCom;IEjF(r~w#`PeV{j{x-Y+_Ey7lmB*Q@8HPDC6AhvY);+l31T~!Sg>x5QfT!W7W?sB&0?%%!(u*!6@Z`YQeT( zl!ABgyAD3dVr&#fDIcj8ta_sqyqDkg@sljZ24a+QNVQ-aF-pO^`dx>gWHB}tqm(12 zML8r*JF<6Lh21rGDF==c{rGTb9ysJt$z^^_+I7qv%gfGO1=nZh(MO16dq949&`GEF zKV1$hB?qLC0VRi;$6D9t^l|oXz3`KV%kKCaR9--K**$-Q$}7k&yW4M2c?sENclQk{ zuOYjv{=S@BV|k#lo>cUaAIxnVWAwFL){~0h?PBEN#d=cFC%kjJkT_Zk#=XM+E^8QI zC5(H8{as&~4bO>CIfZdZxsW4450~(M|FwG}Oip1ON-pL|G?a%CdxSvqXdtIB4k7j^ z!A!^-w_Vl{!K*!ge3~cWQ-QImSi=M(XDl+G35=XIS}=0P!kJ&!a9P6zBWElIp9hTT zE}M&P}>A4vHU)|hp)?gDAJ`p z6j{Obhq=cJaoxizIdJ5mxdV>v@K8z)xJd@=#$ncOe2;e(UfNLEsj#2J0uPh@3HwWb}svQEaDMHt@+mgm;Fo@xcn*DWj~h%9wv8b``Ik;26C6SpU;Yo2f0og9s6jXm9d zd`rnj89yPp>}R-;rBk9YE&r6{vLED9vQfMh`Md0=xhNazR$Cs}yX;50Jl(TV)*-;x zy2lv?v&!aipg``1DC=NQP&b$rH;)K~ayLYopWbo#=?1g<=CQ#)cSDqQd?;)iFcd2& z_o5sN%Ya1s7bYt-Za-F`smHnq}oSso@)|)^cHGT z?W4EMHHkiYD>bS1(Oc)5L?6A4npFGfZF5bckKRsAs(tkET$AXdN2p1)kKR7lB>Lzb z%%tpS=GI4#e3HfPqerQh-1_LzPqNs3^p2_}w?2BOCt2)1dS}&=TOYm4lPq>0y{l@; zt&eU!1M%cOy7feawB*)D@2<|sw%C329;zj`K6>nvEOsB=da6P$OKyGiUTP_}#qOi` zHZ4jYeZ;s{J_F0dtyc~l*2&#CaNwxa4;Nfr{q;Wj0Q2ah^wGCz66m9kbWgbV(MRP-ppTy7o^bD@r{+kYkDg{Gj6Sp4M^9IB zY9BpA$*Fzx(MnG3qh~5PwU3^qQ+6MHyq>cA z=o8#iY9D=~p0fMslk}9`M}JyR*?sh9+*4{FeX^NScH^k=$xD`(Tk-c3cVnxM{;ath zPt$kf=gd7;h_CHFde?vVOzbdii?$noi#|H-#&#cly4FXZVJ@o4(MO-DbM(YTHL)Gjz0RlT$AXd&)1S>ht=q#FUU2CF8WJa((I@jJ@kdS zCecA(q$SM`s?k4RoNE%@^CfP{9KG|UX3{J7&iTt)-mI$GH(!=(-tL+&*YakC&7S!y zx#sPT`3fy>R@>~CznW{_?v}5#@@lVqmC4op=I`ISY`gf!#wYGKVYuza^}4y=tkL(I zwdO7&#ARWPZI?`KR3dh6iAqYzMfmPJ_11OJ1?4_G`%s zE1|soYvak(ft|JnX@jx&91DV9O;%aInyl7-HL2qDnwMECA!bnlsH*>l#j|{`Cw(7C z$f|0Qo6VbVSSGwXvKjRkLYU2()4D6s^{ffP1 zVcyc|r&$_&7kk@;%2(PKEX*#Mp6#bzXfeLh-Zz{UhHL5YE%q)p@nY|pg~+S0Wr}S# zYeOH^va49*+OF%Jnj~#gtGHWM5xqOA;!2;s5pDUF31bBovvx$Ez8#_?jjJ=oR+}^Q z>B|=(=ms?5N4I1Yd(GxXgV4>k+#s*p*k};ie7Ql^*tlC%TYi?2TV$ky~yZ^O*nSKvzt1U90TZHbe39*0e4Qk~6 zPD;zQbkBaq^IAdnh#Tvj?q3bEM%v0R@|BNv9F<;q`A}tf zjJqk!<&mpCs3j^IWR0G2H$_luvrbAy3q2QIV*K_i50ruf%!-D(RkWQ_QF|=xR?!Hv zaedT^+QVPBidw^7rJ}b^jww4o__eLd@>mt+uKqP@&DYK{BMiuN(l4cZ{{3FNf@H4I25uGYudLAl*2;5RqXR9duF*jj zcUz-_O{i3~?W&E5#}0RRE%!Cb%Y%xVpOXo)Mtx>Q6U;g(6)pJws0N1*7n`XRY^~9T zZWSG-RMZ~dxmDC2+o=_`hjwliwT5*{MXyZk{O7>oCvPjuV{N*;Jg8`@xkjy_n_1Cx zvrd98DO(4lmp{&UJp1L~WlF&Tg~-603YQuy{0anR7Q(TB`X51A<`JU+L)vfn{s`jP z<_>0X+RT`H1P6^Vw?~81T4C-P95mKkeFmpWF!u@$8fVtFfNVsf-oZiR%{w&=cL?1) z!1e;cLDrbdNQ5F$FgVB>aT$p)BnkxwS>r9Gn{xcbf;wG-PM21@DP{x7Zpu<&wOn{c z`Bgox%vT>N3Rq5t{&XERCZ;FN4|gJZ6mWL&F>g6?b~QI;pLShhBIpD}_aQm0LxC4h z+AX?keZI+ue{gYH2Lv+}!jl*&>zJTiM1IQY%>J(R+v=TACHUPD?n}lSjEAqYCpH*o zFSW~B+1cByp%7Q>YVUc}<3%7LyUX&UEZp8Noc(Z2<9p1U{jDmu?cBM4`yMgI z-5E~%us}GbYkT9h1y1|8(2MRW4)4{Yz45Dx(>^Y=?a`%ugz=M#(>gBTsK`I1IPHr= zya7?~lurCk``S>4m>%Knsbu5S@3gKC2|+g|W`o_;%PPw=!q`1H0we|c`RF6em~6YyhJ!ox%6tc!Z)fdbsRsHdC{ zD<%!w+oJf0bfrDb^C1^*v?o^9d~;3Z)MsWZ{BcP z9YT9P9gKHxIMdaY$@8JE0dGnfIWzQI5obo58M$_NnrI%n8{HE7GQPDC9eG%4B<<_? zR+8>HN7BBKZzbu{E0Xqwd@I?7>t+-?Hs=C$4cXK<8w0n-L<-F8%O#2fm+N zcUuvq^nlT_^v=;;J9Uep-gbMtYtYEYjSA0-v{tN#>aZ`-QPQZtb(KIlfjSD`w0OmN?aG26UZ^p>@qbJFZ*T z41^d!OM}%LeDH;TlJ@-hjk35U2Ip8@94Mm9)`(WuZxv@pv*JRyjTcUS+xO6qeZSeD z6fegMbQw$^FZ^te7p_}1b{jAJVnTCJV2>AW=qY==aMMgF$HxgBKVQ`J=83JQ9n_BJ4&O2remGQ#pov&Q)G3J@MO5p*rG+n#8D~bFN7Y8@lA0#JHhru1O3WVscGlRUCi)*WXtf(Xeyiy=g4 z?pcf>+}=`ZZZcdl1`+n#N|pIy6wxsEk}-^ElzSHAh{m~RF_5s|ZmP@|BZ;QDPm7^M zv)r>7OEk|ti@`*T+_M->w6wEwv*Vi_ovlV8l!?TYguRc4w=kayLTPgD>GC&?jxbvb6 zDk?aRK5LECO?8FtVtUGlQW;)tniOEnGP> z7+eHd8DmY@ql;>G!lZG7-!gb-`Xh*H0=9s?G#2D_8qr&3PTP1URyhbv4-1Sw${Si zgAKP^Y^|(4+OY4l^|Z3~aKrvIgPpa<8}=s}?5sWDus_vcXYCP({mBMwc;=A9{%V7H zqQaQN{&0hGwc$~*t##i%==Hs_?u!o*#<78`B-cF-45h7&tBkgB1v<+*% ze9+x_-kgm&?)b`FcxBwN_H4@_i@KJ<|1q3j&Cilj5{t_ z7)J^ocYJ3;ZQSv_$(3=(+2^j@zcKC0WMy&XxI0#MTWR8u{}GO4^Q}i;M2Kx2jh~Z|A*#s`gHEq!MITAzuQ7xI~Z3d z{r6a;e+T1|r2k%v$TK7j>izxqS+HjZ;}WC)ev8N^^JUus3-;(5(IHH}1k3-RMcFFf zf#v^^1-rE8-wpa07YhA9ws2gJZsEeKD3yB1Y$9VtG~iJokB9van_lIb|E)`(#NNKP zzM0ZeCHR`ZY$>?{{6EDC@IPvnj%)t@$IP}C!bMYITzRePb33=z{9Nt9mmQm)oG3&k z+ZME|e`uyiZlKJ)sHkB(T1HPEFh1;4b-(coG$$0nwl${4g<7>M1Hz zYG@WDs@YRG`>wliZd#M^%Ir%IO;4xciidd0Htrnr)%+d32C6S#D4mr&JS{0PFkwV| zrf~SUFUq6wrM`XcozivHg2$vOQxp(2?Kw=Hx-cbZaaZ-Xm(t_7?6_><;UlWs-Zx7= zo*1&V+YYt#tP$y%*}~y1>e3lEe%>&in{EeFXSW|c_Q<$$U$~lh$))ceg$_qrNo-?R#$PBXWJrtq-IAo{@7N)vYP$aO5_{;NLpj z@6)=;nVeG;v!-w=QzU%+QPp{m*LdcfBGj6KwtcsGl=7~c_*Roc`*KbZY)wHst=kko zefH|!r~GRM=A5FeHANY93cO(==MJ2~LC0CQd8Dr0cR6_WOy8VSRIsKfFNE81 z@%vk8^S+t4F;SVqLBFqwp4LFBBwy=to6E}Z6Fz4r{;Zw`jV-IVHJ4(_6qzw&i&nn) z?TgA>j44W3QxsRG*jziVt2+!z|AI zBtJIl?Jb|jI@KH1N~ff!4Hq8X?rULve345{u7`iA6kggoJIN`O)05d3Ql>CYPt=(U zsaDNl7U@145m7Rt`0d4U%0$MhD`1vaicU6lgmo6Yess+nYb!RHtu~Tbc8*3`_0P`% z^Rs4DQf9!7LHZlHHr2zsK3LU3Sk_3Nm z{BllF)S5y)7Y_Ng@H72)mD`nbiUQUYwDM~UYt1y6=$Dv~ytk|}g|Ybt8e627x8Q>d z9UA%nS4-|aR41Zd!9WVEdu`Nh7?b(B_b9i#(5~Ajw>M^}lMPErkEgz;mwSJFR_aG% zLl(|fpL!{sm_BA`N)r7l<=$y-IsfvZ!{6NeOD&WaI?(q2K?{mycLWF5>k!%`tnv7W zxX6_Bq46ob<1>@vso;pDVOhZm6`4ml8j;ZqoSp)Qps*ta>4Jhi4?GXVpy{6Q5F-GW9r&8=9OwEIBD9F)krvOh`R? zpDx|%-L{M986DWOOKezZ{qWHG_3H;lh6RS#3$IfrFg!gmX?RjvV6U{~@quGQ8wQ7j z1lJGl+%uLk851&-hmXh(teH?NFr;bIMs-8$hcpT7Nehq_7@d}tojE2oDJ`4-osgcH zk)9c!os=jX4QcbvgVpx%rj1*O4k__jBf5=A&4^7(jnANQOHz-d;aQ@N;|-4ztvA=Y z-JxCZ6D*=eo^H4v>8af^lZGW_CyX#!%;gC2>^%I_ckfvQop-Q&ZE^jHasUnD1DURQ2ipFBP1l zr9|aC-B7U;(h_3R6O2}>?0C_0N0UCA!Y+K4;?70cJl#YQ@d@!p`;>ExbL?N)xATgx z!%AB)zj215ai+L8j)eJ*BloOwjv4NaBVistM0ZV1j!vWAWJWd)(E*;3agB;?EZ@4W zmJ+T!ef$Z}7}GO3H7T<`4$^%b?N{tsT>G6X@2i>oW-^*71kDteqnTtTznP3?3Pm#w z&(TaWlg9@p?NgJ7g@mW44ND$wG?dG6$MM#cfT58)%kR{4`Asz}RB5UQj^I7%M_=hZ zpaM6QdoGW62>R01M`Lp;@A$yed{ohbdA)Il#%H2&wt1Sbo9Ju8Jl;653CZRlB;0de zp>of?8CK^*3+6YDISA?G-Z=S#5V|%=8;LmxiFI!r3_|ku*q$0E(KzOma}02A90~LK zZk1sjbFw@a4j6NA_5S6-u_nxK9P^kn$-Qy%k2!qI$*_(&&$%}ajya|C^mx9Pb;w!b zX?~v0WFja}H%;3_zSNpECPns=t2pA4XZsX7*~`~c%jCBc9cSFyX}DWExo7g*i4Hk# z?Ue4;PVSlfcA_4STRV+&YbWrdslSi zNQ&}#`e5EZJU&BSaxL#T=-Bg9kqgT^{uN=<{N~A!ms-m^jw;QA3$XcHPZ%x-ol=@d z()_I_qXC-dg3>&a<~L79Lp0A1O7lpX-#i(O&^*_b=8-gy-xSj=IVn6lQ=Z`~JF0lj zdvV}{Y6Gqmap$69o<6yUr)Fej$+LR}M`_2j8R4H6t9-Pf8_sW_tSosZui&VxHV{tm z`CCwyJeOB+)KD7;r}+E^%93aE3XXbe1K}i}-#}UNd|tuPSZyGj=JOjUOP zgcE&!17$TfIzkm3k!k};oPQR}%4&iJicuR#;yivkRdia$m~87Ng({BI9uLng3;nLe zuOVtCk8ekO(|v#0U99AI*|BTwi!GZD+wzYa&TpX9{<2?K$+6neCDeC9P-^>iMg!$v z52BwG+jmd0t|m_Lm=QAU<98;UziHFFKBA}Qk=sdm#|));^0yvrJ?7QK`AYL(sFAmC zgNY8c9&tJ7@zUO@Z^pDbw9bNg{7w&Q2lGykqwbA^J3aFD%?!~Q@}7>$j&D4^+xp4w zLbLl!G+7=$rFTgfnw24M+N|Js>~Zs(w|l=fw&vSzIKP3iGUQ%V!QtzvG!S;KJpLOP zKZJnG^qwBaUyS>DdB@mSjmHlRn%Db0{BQx9$6sk4^m+33b7RIE2kN&^kO$~M$7+wA z1(!9SUd&ls&4`kD`j?D8@?PJvjyF7yKVR+Rk}Ero1QPZ0bi=ewNJz@c>XwbfMQre{uQpP8ASX`J3%j$b_%^uKU@%g{>6 zdQQ~L(>q+-wD^?t;jv?eW=+U4+A7E~b^nGjq2t<=*peeB%H-*`qFWbbZ?c?YrK7sz z?*~V}{lH>*d^-wH85+_#eRy($d1R{LIQ($-FU`|t)aaWdm)};QT3elPYb!OE-&SE- zTb*@lD>awjRt>ba`qr(j)SRfD$B*Ua@yfhWt)}Bzd{n!4W=~#m$Ub11$^6#BQORtO znvPp;t)(UNTMNe}yS47RwU(C5Z!H{|?AChZ)>>LJkKbBLhbHT8iOLQiM}q}hpFUb9 zV2?Y`>#wNapBtjE~hw@ckFn)rv3$m4Ghiy4#ce&bD5M;Xs`)7IZVGxfD? zS}KoUB#%uTmTLZnklNjNX@2vhn!h28Qkn<9A>{3!cY9@I7*|!wIaYbz zN$z~0Pk?s|ljZTNm~;&@^4rF|rzFy?ZSbpi-o8vp+lc(hvYaEvt!*UB-)`j3mE|0L+}cL6Jbpl?x1q-3 zM}SI>bVvQ4M`pkG;shTzEb{iroL*3XllcdZ{@(`8tol=-@+QmU-9R2%nZ4wa9>scx z-76lmpp#AWo5$)US5%q@z2rQ8pB8OB=H12Bl;*+R#re%+zN?_F(meU^D&Tw5Y3niH zRnSmrp8R(epn1%96|_{E2aho3?_Bax#qy5!O7q|W#{A}y4=R>-bWxfIk1ysoPgA2) zSl-b~X&y=Q_>jWr0Lt$!ly?kL+9yQf{02%5F+0vlY6D4}-$1D$<^|?dwSmxg&f7Qe z@x2Os$87uY_yk-{$NG@ovud|__r8CQT>cF*p;}vQb!#g%m)}-lT3hXKYb!OE-&PH@ zw%Y5~R%$MfAJ8L`#@avoY;=t4*r#dBeIx&J!+HD?b$EQ5d6{wctp=mQTORECrN#2w z#{Ai5v0K~VXP^8>XRNpG1v<8QtY}mzYUz~I{`}~SmB{0_y~ro`tk$UFc-dp&?xBgz zhLq~ArSkYqRP?IG-t^d7PyX7r2z1o)Jn5S{b;sSeuPO;qkuETKi4ydGhr=Nr7iOXR ziun(V!_kKR?YeWCf-{NI=pjoe1R#IkGz2T|xnd9qaC)W!PtzW->pZLtAxX?y%_3O+3>Ln(PO-@LP%NmoB zk)D}dZl@cXa!$Nzm- z{&6Dzh{-3D|GRrf{#Ka373y2ze|IeW-`{fnyXDGvnOpS#WJ~<-ukHU==lDO_s{fN^ z{lD5?`O9VQkN^8E@jtnJ{ZE$l-?ha5{v7|i<#Kb;b&KMD-qC^7jWhn~$N%&!OqUD% z{R;bq`ZXyduL&^r%7G2Hw~cMDj|L5=FGID=0tzx*1tqe}D&z(XhhKmQGydUUoEG1+ zfSOAS%tzuND2XOhXY}T!^yGi3m}yt)pn^YDI)7KlNFM;5HSaXLMlCF0o;u^^NO8 zfstW>;q}7n)CmkvPfQw~lor@4EqQ$4*wBW-AtAx_gFE+(rA)?z%;e!CvIA=-)Cvq~ z+O$#K(E1@w0(&NnkIxE>PRq*99Fv-qmd*c8NYA9}O7YoAiJ}(G%!B7B8q(eNe~}sw zF?1V~nh~3n8lN#DJu}I8IGrt3>8~``fVoF{YPZa!VM*C|a+F;z%T>#E^@&f;j?Jc7 zT7^}yY}H`nFRg~Br>5dNH(XXF%TyVr*a>L~vFUgd8D+~`4*q^5S0ExDUs9xh=bpyH zK2J*9h38zxuBpkYuelxw}F&SI(B}o1A7>E0^@p_)KdaIn%KT$?~Z)TFzYBoznlQ-6?Ii zd#;7!4QsgPDQ{GUyR$b4o9yPqpym@W+ucYrC4jMf>kko;RaW%eRw=R=u3gfJ#TM&x##hE zr6*30_X|BSj~DDbF^@OQP(J6efF2~Wp2H%8@hFj8brn&=@YIZ~EPEH@XN__(*mZn@ z!LH;J40bJ_V6dzC1cP1ACm8T9nI~5hZ&M*dpjA!th@^c9J=a3qzXbkdgWXoSY!B84 zqG|fvwkPWg$xqJPO`Y=~V1Evmrq4BPA7OIt#@07cY2uu1?EX#ACmZbYbE&=csmLeP z&iYm&=L6}l+!W1qqQ@?|X#e;<(dSo5=Z^v@brlE0D1$=tsNM~TXom7i~AtNJZ8 z0y!JR{aavUsA`pAp8Ior28$f_p@?6pVJwvXbtrPVtvi0tD%C zb7o}IK7I2foA%Y0C)ut^nUq6wHZZ4bo^#QWv?$bYV@g$%Ad50(Y^bZ@5 zFXvH`8pV2-JsEP@8u%SMilqwKWF^hMnf^w1GUVI?++Jz^#Jqj{$hn7FueGMBb8e9C zuXQGaz5korko{)kC#CJ(H`l3i>wvfwZubImE}Z)-PHFBr>t?;>ld?Hm&h0gqPt4mb zm;3bgku&$aeU8dKZ=a%a&)a9H-1GJcD)+p7e#$+M*IiNlb2hKrTc9ZaB*T9?(HkY$ zO_=MkLwySl&nQ=$_L7$;*|hhYJjtfL+JkI4tMC453o_)~c9QDC&vb5!@^o$mcQl#E(v$B#>=~2^6QJ`EQe}6}5f(fBb#>Wp$77iK~ z3m-=zhrc}TP~`T9j82<9J8kD|s` zaqZYCS}OTsqN5TQ7k!ktgh*84l47(HmlBhexU`s~#AU=XB`z!0DRDWmQ;ExqV@g~> ze5=G2#cxVnNqD<$1fCw1MR6q#6jhX%uCFL@Rnbz3U80i`2Z?@4Tume^adk0XiED@% zN?cPcRpMG=y%N_J+m*PE_*jXb5~r28uJ}QTgT)_8Tu;y@Z2j@{s4tvK93m^?9ijqnkBV0<{&A6;+`@4%)O1_8aq{OkJuM+nZ zNlM&HWGZoQ@vIW}5p$KeuUMhP{lq3E?k{#K@c?mHi3f@^N<2vXpu~g4uSy&z9x3q< z;pb!4o{#VGqMQ;B6}6N&K{Qd~MA1cwlf+OZ9wx>q@o@2?5|0oolsH*zRN|3hhZ2tx zN0c~4Tu|av@rx3tYjK7akJjQ$EzZ*7Y%Lz6#bdR2oEDGQ;t5(jQHv*O@zYxTj22JU z;wf4@Rg0h1;%Qp^oEAT?#V=^_bS<8t#WS^dmKM*};yGIUq8889;(1y;UyB!L@k?5~ zP>UC7@nS7rqQy(K_+>3#rp3#(_!TW)p~bIi@k%XTrNyhY_%$tlU5nRf@meijr^V~F zc!L(dp~V}uc#{@y*5WN%{H7Lf)#A6b_-!rTrp51Q@w;05o)&M{;vHK2z83G);$2$& zffj$L#k;k5j~4IM;(c1YUyBcD@j)&ANQ*z#;zL?|Sc{Kn@h4jRsTLpA;$vF;nHC?{ z;uBi@xfY+);xDxLlop@X;xk(Or52yn;&WPjUW>od;tN{*wH99#_muP5H(LCy7GKih z@3i=PE&f4^FKh7?ExxM7*R=RYE&fT1f7asbTKtO^-_YWlT6{~3Z)@?dTKt<9-_hdV zwfGM${!@$ZYVkcS{!5Gh*5dnG{6LEzYVki>{78%c)#ArmEF9|g@g zVjnH`)#3tLTu_S(X|bOc`)hGwEiR(P0a{#Ci=A3rOpA+aaS1Ihsl}zVxU?3R(c-dN zTuzJ2YjFiFuBgS8w79Ys2WoK@Ev~A?E-eny;%Zu4U5jgIaZN3*rNyolm4$i@R!Zj23s(;_h19 zLyKdzxThBP(&FA)+((Q1YH>d;?ytoIw0NKv57OenS{$dvL$o+vi-&4)f)*!gagr7f z)8gS;JVJ|;wRof!kJ924El$Ek2~hhqd^K z7Js6}pK9?@Ek35jpK0-NEk2>epKI|+E&f7_PigUKEk2{gUuyALEk38k=e77NExw?| zUu*G2E&fJ}zt!SPTKt_Bf3L+qXz^t&zM{ofwfLGA|ER@3Y4Oimd|iuw(c&9gd{c{W zY4L3>{#A>A)8ac?{JR$ap~Zh{@m(#xr^SD1@!wi}UyC1T@k1^CM~fe6@xNO9Sc`>+ zdi-%{v4<9WYO$9Vduy?e7W-;(0WB`5#f7xkPmBGvxUd!%(c%CtE~>>&EiR_T#kIJE z7MIlGQd(SEi_2(nSuHN7#pSiQf)-cQ;!0XvS&IX;xQZ56)nbI-)6J**;04 zBVsxKULqE8lu>>oF#vI(5tkH+h>IF=VUdYgwtrReG-5fwr^F1zvON;SLc~*z>7&Ft zCGITVQQ}TwuNl*Q2TqSvaSX96Z-DsHjE(##@dIMHJT7qq@d9Ih-NYYCzLM}NND2BQ zm$#M(KzxAigK>KF5v39HjdD&8rwByMw+%QwyhI4%n?~GSv@r9=^u0wSV!1vVh;E4G z@(&dK5zF@U6C)6pGRi9|MkAK>2@;bK4>a;E#R9}~`D=?6h@*^r6R`pDr^fb}EZ#=k z&B!+uA0YNJ+Al?XidZghLvaeRT;4(AB4W9`bpI4$x&5^l4-|i#@G3+zqCax^YKQ>D za(#3aWf9Be8!4(Hmdn>nJcW2FmErX0BAP34r09Zppi#dOqOUT2b1@9DT>il#195$$ zyozFqk{=>wA(qQqQ!GX-*SDuwhgj}^-r_yPvb=KQBPFgNP9c{2+i-Ciu`JI++(#_e zZ#Ch~ci+*U-t^b$(L(qmo@&I=q7q^`zw)9kV%h%Tf*)$*KPBj|)1!#!ia5}S%ZlEJ z<@_p(A&7?<`BoxTnLa=~gSd^64;FI}%lZrxuOgP)TVwGC;y}Y+N^C33h*)l4 zA>uP7t}o6Zmg}pp_#Uxb-azpSVp(2W@er{*p85(eUNQ7XuD|Lc0C6BOr$=c~2C7;|Ax|4f9rt`!3bl51$o-fm3%DnSCOafTFLiB{u=VM-jwC*h5V1mQ#A?dA%7cr+JTk)VB~*Ao*s);@^Q%jhI}b4KLq(Z$kQ#q%JlKb|Biea zEk6|bKai&JJZnM@O-RNqppS#G@ozwhaij_}7{vPrbwEQsS={XN$ z|DpStmFb5gPdl!WryG-%{0QXlBTx5CEBj9}@-(qAeIVUd?Y?{?k*6DkjeHd?KMMJO zkguxcQ;>gzyi3ccBL6S)L0Ucy`Nzmt)AH%a(-Fy7zUtckoq@aq`5Hp-BS=>J(~ZZ* z`k{Ncjp=J@`ApuULN$QM99 zSj&$`z991TwBy4Bm2S>xXVgH`Y%>ZU38sd{N}-1gPwvQ;~Nf-&or}pGCeH@=dh*O+&so@=dk;bI6xK zzL~cC&m&LI&l$_#T+6?Jd@1BxXzOP>@}-e)Ne|_@Z@)8;r>BIB@>>bfz&$?`d78+` z(}M~8M3uGu&qBT&@@=&G%|@OMYR2?!we!Oqs4dwwqR zm5`?niZcB?lz!S2hq5P9k}7}Haa zN69ZjJ_z}aT7EI|)ab_aowWQCw;cJ}$amB7uOMFs`R>~OvjTZqX-4@ywC(3rELcTTfN!tGVHu7zdAExEEA>S7H;adJ3^^6ilyrR8@Z-vRj)ZU25B`AFnbwf%c1@=?gAY14n; z5Y(j=p3x5Dp-<0U4$;?xV&WrNiKnp==Vy$VF9%-<-qcg_PORjQVI}`k@QvVag45+8 zqnr|~N`8Jeg#8=AKLppJ65cv#jJl1bzlkLCJktiGN&(l-l7eEBP<55)bl|yb&w$W~{{j@Ryw4IAm~oQ;@;C zvr;(;;KRYI&=`z)7%P?2n3c+z3ce70DR?lA$=Kh9mHZK`5xk zyRedfA^1A*jo@u)%*Os6tmN;_O8!;g+rYPj^P7X%KY*3|ajfKD2mU_zhv0i@OvnC{ ztmHq#O8)XRmSbL*m3Rm%@dh-8W8Q(4ct=*^3&GccZv@YvF&+D-v66o}EBQ}?{{Vgs z{5{$s*ngOn{6|^IUyR0f%!62o*JLIBH26I5h2R&#Z-L(dk18k2>CZ~#3}&TrHiCZ$ zz7M<}jR|?aZCT0Ro|XJBfv*LB1N;$q0F4#dU!0ZvajaC%Xz(%MUw~f*{}DWt#**xh zV5M@RSgD-V;O~I%0Ou$B*);Q;AA@&v$#Mp=QaM9dshl(5*TAoXHw=>gNLKQ9VkQ6A;5Wg418-4H`n$4{ zzXvP%KL$SwegV8%b?I-+O8(}oAYe|1SR`Q3jl79;LOW;eugKA5EBUbV^V1?Q8~C5#!)Z*<^PRv-u;-T0QBX%1Zv{S;_we_+{`P z!9(gxe>f}oBU#D+BKRusHQ;?hq(7OJ{Hd(ue;@o)@Z;dqLZyE(EBTkPlK(RJpWuIk zzZE9^2Uy8}h?V?B8b}_I8vy#6XEBSpINnVDPcm-DC!@$Rb zKMfw*So$Ma$sff^{)OP{z&C;qZX*2|tmMyTCI3F~FTlS9pVd_QSFnzAYs$%SyZ=EAe6A z4{0U+;jHA3WF`Ls@HOBYzz4LJ{!~`-k7gzRhv3J-zW{%sjr70FO8ynBSc#WmB_7mK@C{{44Np!0Dx(#(E#eO8!Z#%_*w9uz;A$$eOmfwvXcKrR`P!heiQsR z@adDKe;F(JUu7l#4e&?cjwzBCpCE#mHg#rOJ0|icnB-;J#!@goR#=#R^ov# zN*>Beyb&w$<8vjy#7g`!EAfzdl83Vrk7Om@?A%WK{-0UNANHQ)?OBOOvl3qgz72dk z_(Sl*+oj*hO8!Jvs@GWXiQosoPlKNWpT0x-m$A}(UuC6oz5~Alei!`IPU*kGO8%c% z$zOYy z4`C($)8O;K7lN1FBmH$)$zP9^%LktWJ|DdJUg@vKO8#1`3Lv z$v>8r{QJRAfu9BMdqVn0vXVcImHfNFkAZ&<-u-jwPhchga8~la1O74iC*XgclzyKt zq`wd=`FpZb`ws&j34Rs)9{2Vep>P)ti+G85-)y6@@lNaYq1i4 z5quT+8t`l2e}O*)pZujPX8|jfvzV32`5OEt_;29j&r1JnR`SndCI5Nw>)^M*GtNo> zG*mRYhRZB7Ob>9ZCI(C&ER{$4}kkzk^VBQTwhl5&jMcoz8d^T@V~+T0UvQy zmNSu+%9+ecC`{1Le0N6B}vQagOYO8(Eloj*zLVkKUK zmCCsYehd5#c;la?Kbn>NU0BIq`MTsGti&6#5+4gb6Z}Q+ufcDE{|4UR7g zE0yyq_*>xbg5Lu#a6|h2S;^m*mFhbZJPmvs_($MJz!Psu|5#RR`R!CCI55aOTd?d-v$@ArQeH{{GC{N`vi{%-v<5>_z`fwU!}hyE6ukGE0uEy z{2ch#;FW)q{t#C3H)JJ$lRqTy$V$8`EAjK-*THXrH~&-myReeKJ1hCW2EPgZ8+fa` z(%+4h{5@I8e+S(2p5(r)#QU=H`T|b_?|fhK!K_ryP*(C!0-p>15_pLR(qEmG{Iyxh zpA9}8d^ULCL+KA?C4VDU@;?i{2>fO6;D4mQ4J-L0SjoQtd=2;p@RpCHKZce3v8?1@ z4gL=J4)9L@O8+2M^2f81|4s0H;2(iEeJuT*Sjiv5O8ybx6Tv5g-}i7B?d<1CO8x*= z^7mt<_8$eF4qnJh@(Qfv4`d~O2KY4a>EKnor9X_7{Eb=3KLdO@_)74GKGGk_O8!o) z8q4!+XgmzDejS;@Z%d^h-h@Dc^2zd9@VYqOGn9QZ8ox!{+<{{;UVJiMSR zrxz=g(~p(Pc^mv7_+jwUg`~e0Yc$<2z)Jq<;LE^Y1^*S?LHDe(-t~}pnti)Tf5-&jaxH2!tO1u&)@ig$M z;Ln41EiL^+SjnHrO8)KON5GGPH!dUn(X8a}!b<+-;9J1o1`jJM{q0%FAI(bsMd0hf zH-QI~lm05KEBSu_{{#Fl@CsF>KbV#Lp{(TZ1U?8n z9{fGPM5-(gw^2)5lU97}+f*%Dx0bb!L=?`Wle<&;YkAQy#{tbAYy3*g0 zmHcg4$$u97C-58K&4Q)BGb{PKv6BBP_&x9k;L-J@e*i1_<5P}{&}qAU&u=SE#P~>4}!02D*f-XlK(?i@_RLtyc8?(a;(Ik0iO@P2>dJX zU%+pJAEbL;xqZ&CQaR^YshmK%*OhrFEAd9G!~^IaSLRh%iC1GKo(4V@{CV&{!F^gu ze<4=#$Ffp6N#M!gXXqYR=GR!M{Ohdb_h>7530C4|Scwk@p8)<0_yO?K;OD@rwUgyE zW~FkPvr;*e!54rp2A>ly{VQ3?|2ixAuY%tLe*j*!z4SL=C4UoE@=pYR5qtsoxG3qL z#Y+CUtmNMSz6*R0xL-%~(!Ye2 z{L5L%{|)$U@ZZ6o=`Q{AS;@bMmHg+xe+It^-m8c74`(I+C|2@s2R{OS3_Q7~^iN_X z{}fj89|k`Uei3|nFX>;#O8!?_$$tg>F8F{8{i9!0W|Je_K}aw`V2)9PpLkuYo&bIa+;g<_`?8Y1BP;m_f)4?I3;Y21A@Bm3(qE31ma`Hom6HNK8GIV} z5%90TzX5+LOP14$mC9+yO65!kUk3gv_%-mqz#oFQ%$DWEuu?g(tW?g2;K#wg053j9 z`m3>$zZNU`$AQlRp9}s4_+{`P!5fT~<#b@Bayqh7Idj2RgRcco8YlhZSjj($mHdmr zH-K*jFE?KLpJF9{eOB^kfEFdl{ynVZe*_*dQS#!f#22uBK=*-zZveju z{x7)4B95L4{_3pc zPX?a^J_Yr^B@Yto&pTtW3WLENT0pAOL5d8g@rT_|-Sc%_XF1g<;k_WI7@5f5@8U>yX-u6|=V_B)3KCI+_9sE7;o#1b- zl>U9J%Em;xVkWJn`U3;EmTv9?eSSbYUg`%ix>9 zw}KB?EB&dg`lt2)+t@4frka$KdSc zzb~`Wa&BU!a<+m$1TRcE=1x{(lUeES0`SG)=fSUo-vam9E&XL!shkR|R8B+iNbpYJ z3-(C=8dmaeU?u;4@KfMt!7J>Q{$N(}hq97C6a0DbncyeEe*nJ*UTvQ&r!gy))0~yc znFhWXd>Qyx;J<+125-1umJ`WJ<#b}Da^`@q1b-cT#sTSH&Px83tmMA}ei!^c_=1Dd zzlN3k8(7Kz3-~|a;v>oTvC_Kuf|dMVf|vVP@~2pd*Jq`2z6QSu{u_AcA?c4`C4Uqv z`7eOq0RI&{0nO8!f%o&m|9FCElHtcmnuv@W_*r_hY5`4r1l` zf^P%g4!-mY>EFmo{x@04e+&FExaTR!ceB!bPq32z6nMqclGkG;9>z-LYyjT{z6adr zjP#dbC4U80^3MTZ3I00xb?}GakHM3_l;uofrE;dQQaPW1UjY9We9l?vU&%`T*ICK` zA^36dFTh8flm3aUb z1>Xq%CV1-$(%+qx{JmJop9Ve^{CV)X7o~qSEBV*5l7A2Q=isNo`6H{mev7e^zZ5I^ z`+<)FPY3UEN&4eh$)CVV{w?5p!4HC;`$hVHW+nekR`Pq_ki0Z2@$#(1Pv4gODl74y zS&2J-mAp7B@zSisv{{>#~cj+(8O8#!F)DAL?-v<5>_!02#kEB0=mHfk5 z$-f1BFZe<5&i_jPU{>-EWhMUx@Lk}0z^gr${>H52Z_Y~oXTcYNzYIQ?UKYvQ$!b>e zuVp3wkKliU{{vpcL;3?*$sfc@{t@64!6$=zdrE(4R`Qo;C4W447Wg>uhv0?1q~FO( z{{F1AoGIWL;Agge{)uvZ);X6XCwHB;QPS6e5Ah=EBVW@l7A`qM({Vm zZ-Wb8>GxtK{}xu7?_ThO-~|gvUY?c8ugpsROW?nO{|Vlzp!9cRC4Wy=^6vrv9Q-tR zxkA$a6f61bvy#7!pX5DQiT7qDo(}#j_zU3o3roLW5$O+LC4Ws;s#i1cR^T(iUjbhQ zz7zZ?_zCd#0kWJvth77>SgHKg;O~I%03YF${)w#QpUg`B1K_8@&w=+SCjE)5C06oRbxGcUm3R|Y;$?y) zugyw4n3eb#@EPE9z(-e;{^wZ9KZBM0pM!r7eii(9b?LvvO8(2NTeA|c zQB(4!ti)Tg5`P|iDflbkRclFq16J}kVI}`0@VVeGfq(Fn^nb=m{*$caFHu+W>a4_T zvl0)fFL^jC@kmzUv%pt?uLf@$D*dsnAU~FJ~pbl9kH80)7|#KKQJb(!YY0{Hs~Xe;NEw z@V~(qwwC^NtmNOwO8y(*kH8&mB(D`N{mog)-##ti)f7BBgeCmzDhQvl4#*?jJ3AQC8wxI+BuqFDv;EvJ&_1Bzb98;^kS1hj*2{ z7c238ti)G=Zv)>B{#|$Jzr#xYyR77I*+cReR^qX%QXd;u%*#jM0Hg5Lta175A4 z^fzWDe{)vyPXk{Jz6|{6KO<9Ro87z4iEAhsx#3zF<0ACFL zbe#0hV5w^+&FAYSqgti(IA5)U0Jc?2u*C|2V0!Cwbo z4<4ETKP&rL$v+SL|7-8e<7}+^|9^;42_@MTQQ5Z;nncLHgcMmCj3vX2G02`JO9&xL zL-r7gER`i>Es`aKl%gn730czb^*Zm@ajuz8*Z1@L|2~h$eLr2#dHQ^=^SPFDW^VVK z+4A${4|TNu42k|6iM~uH^VLcCS|ohmm&}hL;m4Ek2jzd1|5^UcIO`XY=$De{FUqIy zX8sNmesy;c=jRR*{pTcn)_C)UNch4ee9J`haU^^K$#LX&$bT+>vzPUE_qIM8$#F=` z8z-M2pXX)sB}j~4hD6^-ezg2J`HKCluS=qDNTQ!CzfgXO{PBU-|4O3&gGB$>AoF!d z_y#2W;34KGlJHYV_@naY!LhJ@WhHqsCdElSH4FMBhQaw|qbOMck|g{(`91Rc}6?@V!X*kL7pEe<`1KuJzeS^f^iNt>xq8d&)mB-}*8n`tl_D0rIcQzad{`q4kYP z^vy{0Z^<0NKMB7{e!u)7`P)CTJ~xT} zeiD6q`CjsUuGYrYx@Uz3C{|E2j_Bz!#*{tfy0 z@{8oB?X!LfiGDeW{*ru#{pK^0@Y6`#pO?rlm;X~f>VWlklIWj5Wc^Dd#_vwTe;~h2 zewTcXqt+K8(U&06C&~|(A0=P)xb;m)^vy~1Gv(it|3E(eg!My6^skcWcgvrU|6acI z_trl}qJNr1KSqA0{2ck;PFtV$N9&_V^z})sTO0Xy^105KFGgbgQY89b@+0NP$UptF z_0N;&TaoDJ%CD0DP(JEc>vNLm^OEReB>a^@mCH$4K<~|1e*cgs(ut|9a7U z;7{}ENcegro^NaU82Nmc&6grE&Z8vye)41GC&-_;YW;5{`aenZm9CkuN5VHE;b;GC zekBRNhJ?QxE*+}@#X>JSdXFn4CAQFC?{9*ZH^2O6zUxh^f6p4O>{51Jw`LR*f z&mz&!CDEUizb^le{DlnGr@7tw^d$QFB+noDcJfW`FyDd1_?=1g@5yhL-zLBMPV0A& z=szdXXU%B75D8zHgkLScL;iF5d+xHnAc_7F5`Et+=Esom<4O2~@;}P|EFXQZ^$kh% zO-S@pfP&q%_z&I4kd<4N>A zN%#-tKa>ALzQ6<4KT4v1j6^?Be!To7`Gy6of00DrfkeMVe!cuA`Thm1A4j5}NTNS1 ze^&my{F9GZ{|t%#SrYvW`K9vj%cm`7eKrz(P7-}<`FQ!B@}){xUyVdxlSDsOewO@P z`8K7jPax4Jk?7aS?~&gpU+_`u%aiCUk?04>PmrH1f3|}4*GcsMkmzeYX1)ap-(cS^k=Q)u*g)LZWX@V*F7x&Cej=XOZwf$X}AbDqpOQ z^-qxKtC8qO$WN0`makjS`c@?R7fJN*$bTfiLH

(ex{K0S%PE{W&cO8!OpNlnZz zATj=868#1FG)>K?C*fB%12N8468%mRKJ&BY^ONv}NciT@o9|4*$C2oc~pJ`0Jy8Hss2%D*I^vyJ(pB*rgEqVFX?Qhtp5h8XMjlIRbR=ySF+UzFrHBz*f= z^Swy;z9jr+`2+HY<%5NTOd)qK_JEJ|_vEmxRwV#C!=7 zz6=T9Uw)kYMEN&|S-*%xzm!COS^oCn=I4OtOOWt=kP`lknw8_J`_ z`UUc9<=4p{!UsHXf6kET&yna$PBmYZgs(xuPmzB|{$2UsHNn1QPuR^4sKh$sDI7heW@RM1S80<{u&9i;?gv!ND}=%`5)wek}tZ}`e+h;RTBLv`OEUxuZtd>yhZ^%CD0DP(Izq)@LWt=O)po*L!w_mqQ4-Y=BWAfB>Y(t$LqTMKk_w?nSYMNI4_XsD<3yspM-Br z!cUT4Air3C)Hl}8Akohv(VvvRD1Sx%&w6+qJN4+KSF+*e6oC_)7Hn3=wnIr3*^_zuaj@_qxD@$^zkJ6_vAOrZ93S?fO{(QhEpACf;Ke@=eJdFz*w=-(&N?~*?z|E>IUzgpjg zMBj}>zfyjy{7(7V7pz}NqF+Ozzb1dzZ|3hN;ZKt|j#uQb%SZoiz9ETmnvm!p{=C6`;;Y*V6 zN$JgxAmLvl;rGj*l0PF~JcIRBNc2yU=ts%Vke?-gM*f=oP5G*~+c-@~jMJRNIBV`O zzmtUDO~T)Er}=^;{39g%h>Yf^k?_eR{7LzX@>k@WXR^LCi9U`*zg&Kk{8ssbS*$Nl zqOU}vA0$6PezJV*-PZRZ(f23OPnKUOzeK)#R_kk#=n0^`}VmXGrvq;e#4EP8|}y0SSL3m-(Mb_+Lr*=-lQTlJHGP_%nIT zUnAjflJE`knr}6|VljQF&Vtr{6eK`{SQ2EL7)8tDQv%V^c zz6ObYlKcYs#q#S)TEB-xzmG(pzm)m1Bzy%DerIX(M@je-Bz&nd=BttLHA(n$WzF9t z;nO~9z8Q&i=t#o9BtM{n`PWJKH%N?gQvRa+75PaOtzST*UreIECVy8Y^LLZ*Yb%48 zcNd9%4+;OkD;RbLAJxH>hiUTM~VH z68&oV9rB;cf78JF3ncoBB>JZsnr}wJKTpEPH8MYlgda-6eJq)%@-o!3zP5@rN%W^l^o84)uS~*MA>sGPe=Glke4)11S0K?>Cee?0(fl+LKAD97 zUj9${zvSn|SihP?{}G8k(9V2T5Xje@yXC(-{-qOaK5d|i^` zlkmIcPso2SU$~3)l}YqfNc7*lWc~sPf02Z*)YW`F621`$|4f|u_9T2K5`LNdC-R@l zck5>TU=sZ>68$duWAfk1f79Li3ncf4p4Tab0wh?nAQC(76EWqnH$ zeH#+}V)=FQpU8jE+xl%J`duXYEPc!uAmJY(;iFzQpOb{oOTxF2PmoWNpV`;?_ek^~ zkmxVTXXs}>BMIMv#5#ACkC$I5zg2#xeA5Be$C4Po3yE>wm)|14UH+Lt*0(3ocOua* zm)|76Rld+_N53y|nL$oH1-Cx3CI_31}he+P-aK8ba1Bi~N`+-UPRNsOQNHS24W=v$KT zZRF34F@KGOze!^J8e`2jC*fO?@TbO^zf8hkBjKyQZoUZ#-<*X1ZoK(FNchVneDnnK z4N3SWB>eG-=6@yO{~+NjzG1#D3Ez-}|9X=7Ur6{1Bz%R*=4+Gi^-1`{Q_PnD=vr;zB6$)A`1UB3SU>&KDkCz9w7%b%4$FW=`K>qnF5$C2m{ z$e)%!E8lam^{k~=zy-D=r<>$yR zkk7fx`l2NIk|g?C@-5_B%g>izBmc4dRr!pc**IB9jMIt4b=_Bfp!|0EBl5@PJAQ8c z%Ov(^0Euz7${&(HD&JtY^=(P??Md{@uZtd>yhYRm!B;^Uw-`;)_*~w z-%p~?y4QRm6234AU+7Eo6-fBXB>X`6@$!@8m+!NF6N!E+i9Y>)^EpWPJS2Sf1Lg~p z@Wn~^?((n550`)8p!MBI^gT%QAINW$-z9(YE9)mmpZja;i<9U}ljxJ=N65b>e^~yk{CW8@M{S(y zB*v*lVw|^*nO{c2uOQ*C$lr0?d?pe;`Wq1Eb3+n+6B7PS`9<{F56B;u&wJX& zDM@0SvLwc-C*N8=Mn2Pz);~a^FG!;ABHv$ruza1Ltbc(--u|AnZ zKbu7VgZw4=tMc>CTECh^{}GA)hJ5Cq&1WUylS!=ea`~0=m*g}2Vtqyu{jVhYz&Z2j zNcdVLd<*&3@=u&M--yKiG$ql$DZfa5sr+B^cm8U9W)gi9lIMebXZcm~+vPu#&wRo9 z{3PZrL}Hv|`Q`E}<^PnA`px<~N%X@=%sWMXy8Jit7vwL>SN+}kCM4!2~r-zL$2FaM|fU-C6BTHl;R-;zW>Oa6WNRq_=sSznt(U!O!DE8j=Hzx;Li zOqZ>{heY3u#5#18e@T9o{C4@zPmrH0zfitxTI*|&=xdYcUzeXPKVQDWZPwQ&(bp%@PmzB|{$2Se z(ple#MBkJ|pDe#zex-b&^ww7((N`wX_m>|hKT-aa{AKxT@=rwBIE_foOJbbG^6TV3 zkx!q&`Wz(sJS6%a^26ju%I}f?R{jV1O1IlM^+=4~3@{wj&% zo3ViTEF}E1Bz!0NuJT<9n(t3y-oYgL?ea(DkIPReWc^$c{X!D`ukwM1%%>ya*O8ca zkNiIQ+z*>CPGX$WB>HdUFUVh%kAB4Zh9vqXB>J|6&G#VTdy()P<-e3aD1W+$^;byr z*Gcp>ikfdu!nY*hkIJ8u|4qJPG3)D+=o^ygFBCVQriA(QBzyxB>(Exdy?m#V=KGQu zXCR4woBUz68-1$-^ibopH$BJ1tj{#B>LawZ!2#;0|}qG0*L+0PoghG z!pF+@k?$|x^)c%QlIVw!=(orpls_V0w4(LVB>Ji(`l0fZ<)_Kls$_i&5`AkD{oC>@ zGoK?vMOI`6Kd$9=E;%iM}$4exUq#`APDI3qCZ5U&sD{IF%rHM34codvivpq=qIgjNTP2-qCYSHkNj;_&DSJx9G@f6zaalr zHS<4_@V}54C*4!#vyNd_xB*y7ZVx0HnH_LC6KUTx~ z^CbG;N%WO#ny*j7Hzwgv%3qYfB46!k>zk73pCi%lmp>(cMm|j~>+dDe=OEFKk)J6) zNB*4rP5HF7t&bzI&VxvdGgSUF`Q!56$#tu zD}Pe{w0vwm>-&)C`;#1B{ww*f<=?Jv{R$HOY7+ew`8yhz&qTssC-HnUH8g(@3EzZ- z?;zh<{$u&w@?XklYh?YyB<3wjVw~CXE9KY7Uy;9~vGtiq^e0Hn`yYRRHZfnGgs()x_mdwhKSBPm{8{<)^2M9lI8{iD^Aw43zLNh*{ulXj&8&Z#L|>Og z|Azd0`9<<)bv@=C_mZpONs{2bnKS!WSpuHw`wwpM*a| z!WVqSe0dVS5(!^tnE4k-__iecQu&SYTjcA#YJF=GeGG|ynfxd6pUOWs()unW`feop zkL7pEe<}anYu5ikqQ6X{uRg~7vm|^A68`L1^VdoEe@OU-R2%0oiE)mR80W!h z=F5@r6-oH~)6JJ9;VY2v1LeodPm&)z!}^IN`Y9y(ujPM{zaT&1E$io!=ogacf06%N zK25Uuw@Iwq3KIQl`5W??XPVDSVx0F$^jqY&%V(Np{s9u>6eQ7qFaM|fU-Hp!Ti=jG z--P6T%Kt5&X14iSB<5{FqHit#=p6GkN%%S>#(7*rbj1&Mw?i9Y*$^My(H;v{^w1?C?n;fs>+J>-YUkCcyJX#Efp{i`JU-SQ{ozn70) zWPKkJeSZ@DC-VE`zmk7#vGvI$`q?D82YfP{aDgg+{O zPX0If$Cg@OheY3iL|=QE`IaPn8xp>c{Al@c@+;rBek;lSA<>_dzbJo2{*x8f?<3KF zMWWBS(tJ@8z9b3%z5Ji@f5|`of%OeY^v{s!XUngYUn75AKGQ1e?;+98B5~fnFTYCu ziu@g`t#g5JqTfoQzkP%G+$8+{B*)ogek2J$hJ@cMe^UOm z{Q6I=|AIunpG2Q)tNCIid?^yX$xibfNcheq{8IUi@>}F{?Y6!c$#F>ZJ>_4OA1(jP zUhCVF=sS_<-<97Wzgd3bm)6fC(Z55Y-z2|Z{*Zi~eb&D~qHjxbeEALXo8>F+x4tfk zz9EVJb@|!y^X2Ovu)YH6ezbk_RENc4}B=ts%Vke?;L@)zs3lIVAm z=(C?QUzmh1PQoXiH$R+&A4S6Nmp>(cM*fQn)_+H$KSiQ1^_%%>Bz#R0evbSH@@wVO z{BHfdB>EgA`uF9x$Zwa=@`v>WNc0bp=qp_`Uyp=uM8Z#ypDVvmey#j2`91Pq%l{&O zK|bA|Hhy*zD zANb4W%}Qe4>?GzbD_=vtwtNTq-tztA-;`e@zf^vw{89N6^4H|=x@z;@O=8~SB#wI( z`KRRD$S24r$xo1>KgnN}|64xK z4V$+FiQ`^|#QxNfZ!X_bzPJ1+`LXiv%5RY0EdP!C1^J8ecl~Yi-cR!SA~A1O`6lws z-a;hiEll$H$~Tv9Dc@Uul>AuvMe-lZZ0BYq+76~7esiTlL^;z98%@sM~}JR*KA9u(*H7L{$~ z=dV=jz=i4AD=xenP?#*W!j!2MCQhMhbc?AT7t=Jcebd;uTl-YAdQ3uirMTr;C2T#K zqAZtUt9**B3b(czcZsc@lo+0)dbfn0J;Rd(H^Z|8H^b8eH^cJ;H^UPJH^VapHy^t- zad5NZt<5^!6M7}3IBGllMMzfMB<;5TUB zu4h8{ED3Ig%iuY9YhSq)o-KIUm9E)7Jl1pJ)2Lee_OU&CHcpIBify0N#dB5FO6U?_ zBPJ<4WA(VM)jNjI@CLEn;uHJUOiYYVyftsN?lE!kotpM)*RyZWTN0;9c#*2dwJTFU zzEhX>-k~7NMv{+4lI0>vjhW&+xix4it5H)~4V%iQINmiI_vw~GH0qU<`kZLmp<}o3 zv*lL!I6Rw>aBESpdfpYVD^vGEyC%aM;p2v{gpV9M9n#R@J?Abk4? zN?XAI@2SC~7f8Ku6e+Hv0A2@!PnBOud3pz$>Lnt;yOfO=I_mvJ#uMPatg5Y%=Nc|FM`(b}o zS7YGT6nKM^;>}DTd@EYd2rMNE#_cVAbusLnQ#F9h#Ewi9;Rrg~EuNcrB8CmQYxw}!wbPUu^kyl7IK zmyzGS20ZUi0`|J3fkcazg-OIU0Z-Boh`ff zpJLC$Zyk8y2k(W9QoND|?*ukg_>D|(Sxs_J?9iruk>@QzW8Qje#(8wqLvMU|!h7E^ zX!$$!4BUE^)`KrQp*u-%BeYPVjo?~`HiEb1&_?+ELg>)jSN``6 zgMH%}e3=d2E`sY4+zh`V3T}qq5d}BHZ;67N;rB$r&G4I|6c=T1@bC*@cr$oS1vmfq z4TIkDhTbsP0lD?!;Q8JIH?I_LbwXu|7p9O*ahnUtlrK0Tt3gwJ6Y#%p82C#dj>>ZS7E4-1?>@IEwu|pk&9m7`#T8#I6L#@7Y;@`mdh@ z{>$@chWrnICeKGX!>#`g{Y)_f%h<|0D# zwsGvbN9ZzhAU#6Q7yom@zn({=Zj@t(ALl!bw<&cey!WEe{+)5`E<1MVFmUSgG}63T z9lQLFT}j6-`v2(gG=q=&5jx&uLyu7Rf@AlRW7pTQ8|B#HqqzTdJR&`hg^nFQn%QYQ ze6;bux~ieY1M%hH<4}aIhQ3CGI()S4zs8Hy;iF!iy0m!VO?{q58t-n$?*9Ly3!N{; z9J`7Uy4n%erN;l!h30MQ*tLt$HI6WEf@3$xv6~Q~Ywnph^gP~*(6#b(q4Q-`gzm)% z-L?o_hX~!l2whTy?o5PkK!gq-ZSb%2FH(1BI=Ait$F7`XSI4ny6QO%0!t+gX>|S&1 zW;=Fk9J}p~-C@TLzq;#R$9F=6b-}Mna_XYeyLDM3bmt<>TOdOBSA?#lWB0gYSKG0B zHbR#!bQ8dShOYAt5jws{3OzzyLWJ(tAfE9CId)?myBUt%BFAoxW4G0@+wa(Y=h*$~ z*x{e%{p-AsbUg0DH`1wJrz3TFB6N3$4!-C3mUirFI(97`yZ8uQs|foyC{C(z$X-94N(Dp1U!d*-&N0KeBw{YX9Dpmb4zA`aa<>7xP#9lFn=q5}CG zx}P$*b?NSK>k8cI_B`rlj0!yBuzx*pp}KU_GP!l1WOh4lKWB04?z_irUCL&4>l)qb z*2QIW>qg(_)-BBL)_t18t@|#gTlaS^w=Oqs#CaUfm-2a|0)-vA*7@AJSMPW0mObFs zeU;zsevtOTsK5gb&!a#=x2|d-x329&Zrz}V-MX2NxOM9byWQ8mEfN(d;IJ-%Vs2f5 z;%?njCEU99CEdE=rQEs&cw^!6e7Bcz>wYThcAv~#&TYI><=wi*72M8)_{ZG3*DJbp z%PP6uUp}ks*8TLj+kGhQ6K?BLu!>t(<4L#Y+rFw>H?*4Dd9e7Ys6Z}<>upQ*s6aV~ z?sAQ&z(WpQo~PZ`CAyZ|>vX5uQGwzP^G>Q070Bz*y;s+5ykqs;x(p56xUEb!VHnbvc^3-R~vq1hZSMBIbJTNg*T*~0yLH=JxZMvUrf)-`YI)+N5^_B~r_mjOR`aCu)+IKl0H)vSkG_e!E$x3s5QcO=Q}d0g$~ zc75E}$E_>#vfF*Fd0)5t+TebX$NMqW&q3z*$Ma47!w77r?zW+;;n3YNz^!ZG*iCfo zzH;nx4RqVT){fmA$L_RaR|G$pb6MwZj@=5!?vi6yX|UV=4Rq`_J9g<`ahtb}V>iyR z+vnKbH^goKS~zwy9lMi`-9tm&_OFX$x6HBo-LWe_%x(YrI(8czyEMby=B?@2jdtwz zICl5E>b8H+I(E|?yKfx30wdh^FV?YJ?AV=m?8=OE+rM6p-A9hy-;Q0iQEvP9s$;jy zvCA~tZQf@byD5&{*N$Dj*WC6m#<5%A*qwFkN{n&azaEa=YRB%XWB0^ZxBVO9*lly{ z?ilAbZv)3}qGR`!W0&i7xBYAF*v)b5PCIr*#=GrbH^**;V|U51t2DuF{{}jCn;pCK z6W!*m_$6wdmOua-gMi)XC1rgj@>toU4f}?`xoojEq3hAJ9cHJx$R#sbc-VVeB+N) zKQGBQJt}aILst^r!wy|D$F84aH`}q>?%17k?6S^qd%hJNyEcy9aK~{dB;M;*IBvfJ~0*s-hc*d;o4(;T~vj@>E8?#`KR>r&dWYwp+$ zaO~zfb~_!rUmd$_v)tCDvSat6V>iOFTk6>DckKRh?CyWtZCz?Ob}u=06CArWj@@y` zF70f$=UdpZYv|Y|Id(G~yG@SWkB;44bKKUYtYi1QV>igLoA20t=Ggt_*kzyVwl2|* zT|38alw-Htu{-G4U32X6&vRRsryaXE$Lew}Q?0P$P$&TF? z$L@?{mwAEPx|DP5S~_;GICcviyWNi6AC6tlg>LIo#j)$)*uCc1z34FE^3k6^DXY!HF4}-cI;+3c3U00pB=lq7rU)X1$09r{CmOx ze&L8$f4C$n@KS`IgJewAJ@_vE9lS%=2wkL~tE3*U7rI9r#!E)`kVCf_-GdI@59l6n z=+Z8A>k2q_RnfUTk63ht9QJRtW4Fw)+lS8OxLtAV@-1^)zi7wq1;?(RV>jKg`_QpF z?ATp)?Cx9cwtnT%-S2R|G(qQb{`GO}k{!Fvj@^&wTaNT{p*W zoMX4lvD<^r<-T?SU8H{}nEJkZ_xo;L8ON@PW7pHMo9x)FcI*y0c3053+;{V=a9h7< z$F4Oxm-Bg`V>i>W+knpHb?~@jcO9L}eJIyTxAm*+*u8+xW&Qd)c5k6`IS)QTm(Sro zbR1nVhc3eh`2SZpbVbp*T<7)BxxAkDK<9Gborcckd|B%_-U-Jp{VKQpEAH4eMOWBi zo%=g>^BlX+9lML@T<-Vxt#&(KDx!0F-EWO9zr(r=bnIrLbGaX^L+5fnA4lhM{#|$M za<6e4uaaZ;JUW->(HEV|x=cmqay-^Lc849iD~?@`wQl?Om}B>xW7o&Ao9fuDMdxzd zjyQH#9lP8gy4}~RId+{LyYY_Q8gwq}au}V`)lf= z^ZHZha>8@0c%SYDy8P-wI~{4fyg!7y9zNqmd%8rQu9c_5N67^rk>(xX=|aB`EmD{4 z>3aE$x8BqB_UVp$x;{SL4Nv#7PnY*pc>VBEc)>@c=MnAc`uTLNJRN`cEgzA_8{p|e zzyB>#m+a~AQGCHiq;9>Z8|2d+_jI9?H_~`FJl!ikeIFIbi;hQ z0iJHSPnYcJUiInLd%6)m-EmJh(xk75iyBF($r)4lG~9rtwjD98UC?}n!f{r=y{CKAvWVSrPdC-4yW#1k`E+^Dgx3!rg&BNA z+P`Q|H^ZlE<>}t?=>~YZWS=hC)8V5ygO5o2x8Bpu^68Fyy0?A08=h{qPnY*>c>U)1 zbkUw}u20v>)6Mhg26(#pK3%e>Tj0~J_jC(=y5pYi9iQ%or(5LH<^4Ilev5s&XitZa zN)0|Dod>Nv-Mc>B08h8nr%U#9_$b!kBhtL7Dj?zpGJN4fszcsD%V`#xRXU&8CR z!l#S&bSr(jR-O(YB^!K1dcFfZ-723h+0(7|>DGI?H9p;OPq)^myW#0R^y%`R3$GtO z3OD$O^n9Z|9X~UGk4RlBPq)sph}{5Bx8A2q_H_6t-rytByz4#PMxXAur~AaGyW#0J z`E+^Dhu3ejPZ#a!w)k|dJl&^0-2hLw)u&7LblZHo^`36KPj}qY?eOVtc)FcFUEW{A z>$l6Ni}rN*sN~=y(s|Iz(|zvK4e)gQYzsajjhF1{@KMacN2G4Or~AUEJMQW5QO^H4 z-VIOprB9dlLU{f5`E=2qZog00%G2Saq=S!0&v$^QJLuCTd%CZDy7iv!kWY8q(;fEd zZg{#QK3(45!s~~R!VW$nJ>O_gchskA<>`)jx|XSa4l)4UCcIGc=OEoZUDs4y^xGMN z=Ow$3(pbp-OWoD*bRYY4^*!A>pRSpwTkq4g@^l+~x(=RhqfZy-=|1u4l004L_g+U@ zmjRw`v(I?LJ>3?cZmg&K)Tf*5>9+cG$)0YTPdDGwZTIPxdb%Ax-6~JF)2CbS>2~>a zTRq)pKHY9l_qk7Z(9`Yq>5hB4JwDwjPxpmSch1x8_38ffbYJ>(H$2@wpDx|(@O8f5 zr@PD3@w0CDh;-g(^K=J&y1bt5E1#~Ar#s}+758+9eY$d1ueoqdr}I zPj}3xYv$>W`*f{5-8Vj62Tymxr;GD+-}-b(p6)xJZh)sd>C+AObl>}QV?EsuKHX$b zcgm+r_H?Ixy7`{&N1tw~r~ApLTjlBaSy2CV9j*6tXMMV@p6+L#ZnvlV#iu*y>CX9d z$35M7pYD{W`_-pA=jkr^bborf-+a0op6+*_F5R5){qGN-?k-Pv(WlGi>HhTT@_M>U zK3ySC$Ik@&uk)q2r@P|QmGg9e`E=2q?y65$!_!^!>FRsB>popGPj|zoYvt+w_USr! zx|=>-oTvN8r%Up5q5r`$((B*=PnQPoq5tc+4fk|ueY&xp?lzxpvZv!`!~NI1$(}B~ zPdDGwMfr3~JzWN$Zk4CI-KSgc>F)69wtBideY)MAE~8I((9_-J(;fG8nS8oao-VUb zch1vg@#+5bbfM2%iFE$m@O1b1jF)b1`2NSw2>h?}B@P!oIYK&r_1Hj)$nw=eY*OdE{{*w%+uxd=~{WZd_G+VPj|mh7w737 z@ad8~U4EZ#fTt_q(+&4@5BhXtJzYVcZnCE<=2YeO9*WK)EmcjwGKGdp*8VpiMcF)=ZY`M(%v zn#2EcoR-&vf2BH=)JLj26`b-;?Dfjy9Jk^)$GNjY#c?tEudDxh`fsfM8>jv{FE~!K z6&bf?%-o$*WJpX6XJ^If@j3DRye=6r%@S5l-M=@ZfY1Fols{QIC!#+oKT|sAuc3+K zp13|NFWxD9z0D)7XSbSFaeCWXt!5UP-cJ2ZnBIPtYG3_ctC{=rp2+jMtc;22^1Ax< z)-%1FQG?seERy368$Pn_%zc_`mJpvmvjYFCQvT-ZUwetGp1);<%HxLRd2Z&^9tvw0 zv$ABvE}ipwe@76IDaP2ex_@B{P32xRsX+CtF@-@%UfBvQw9IZwAHc5j=D0P;v@Y!z2*=#9kMkAb%}P}LX7crThq2iIz~cS`i~I*x$YPbpt*oAxx1xI9#ERowC!&<+Ir&`w z|HnF&)c=oZSaDpOQzI`gFH*rjhIps)xF#=@`^P`3$cmNKox&@sJL+FC>bonepU+rP z{gV1Fw&eV0OYU{Qm3;9rHCC2(5}X+=^3rF;<;3=Fs?hk6@$_FYBmMJ^y`C{^e_qhr zCTTqdI?R}<`sMBW<12SrR$Jd^SdB=rdfuF%fsLS1uv_>dZ^U8^(?vGj3qAqu_`;#G-DStnQ9e zG{&u>;Gq_FoSv$6`uVjlUT8XZM5PUt6l8zCNN@S`Iaw_nH^IBd%hzxCa3`jaH{5$> z_sL#|N1RT|*MHbpC#HgTuV+rgan`F-pyrd8jyk@x|D5kc^O23}1M2K@v)a}&r{*nj zW3#fmwoBHh=Dp_HQ}fXjr?5Im*v+QK>NEt(R!3>P-sWU{Tj^w~px(-dmP%oNnrp(?x6aK;}0aTO{un7p;ijY0O2V z4zbxa9pY_Qc8Idx7S~*R$JxPcH|SRASiWA#^F`Z{-L~!IWZNTZd$H-68GX`&9+7JM zuSS~%J)(|8GlCwGCeh5GN7QAM_J`j&7UB_k7@+!+tAncL&}(c%P( z^a`H8jn=6a!F3H(Mk7WGumb6=8|BV z*`p0$QcMQGB$-TrNi$ghlW3X)OsZ)CFv+GRz@(d23{&*;spz-1C`7-FB}DYM?s+X^ zY26nKi2#M8pVEh--`+;QLsay$Jriihxrw8{z3$x`t2C`OQZyd9nWLX-qo3>1kn0b` zUMG978l~8GmMDe3i$p2%T_vg{>i5lV7IibzNeTX7?sb=h7K0{wNJ8sD6Fr&m!=L6$ zLKD3tQP=-vP26P(aRqLAe{|W)`MpgdNZ~7xYOX+EdjI{qF;gRZR8 z#a@Y~1nFX*L~AQAqORY5i|TH##_1qSdj~8bM&#pV9{p^0{|7t~m(YluY-0Yd9gz=5 zjmSq_6JE#J?$`mX%*5_hPNHc+U;IX*O6q=J{MMp6-t}y}zq5ph_n8%IUz?QgkCh@O zp?F*U|6t>NAu8TKx+b)uFCJQcD(0=uV{=5?p}tth>i-uN?~GQ)99*=As!=irze<$M z!6k{3Irxpy;QHvkc-f+mo_@E4h|TjaeUg7fx5*8~@rPnl$LREmjm_1l*!<<1FgVUd z$M(h4sb|KY?eXkI(RSoF^?^XAX*M>0tJq}Q*!*J;RihM}exz1=vr+E@3ojNu@ zkWN)9)QKZT5~;pZ(}XJtmE;Nsgl7p6%`)lk+Z%^I-ASBrD4J;|n(;Q%BtWJq>*e!I z;2dW!NAvDRWe%2Da^IVx?Z^Qe&AK+41-;l-Db|KY?4fFuqFIPh>OF;(vI<+2dXI@v z5lPgx5h^MPl@};NH&{YMXmPW>Uly zBZHn6ZHKg2&qk<>vZCqjjTRH_p=y*ORF=`u_*YJ%H2#&BsLB9-UZ`ME9Zk-e6)hoR z(|Xi^M|%G?_Jlb8P;Ba%*i^Q$sS*{Nn>`Z-$9YM04w@ldzW?2K7O#ALt7tniTYVtV zVtpH%TfEqI1DfS#o9I-x2TM4`rv~Gp9#qq!F#g@-i70ld5 znW=mnotavt@a{99=Yu@!8f|dL>Bzr*>HI6jS8wh*Rs43*PW0R4`0vk8s}tkQTr|I4 zoG9guH^=TczOSK+*q}ge%vXmd9utj5{4pXkBbm>rcuZLTC1T70hV@^P(a_Z^Wl_+7 zX-TmD%SeLtpJ)lk>CC54{O6`;3yf&ATAV@=e=4s}fdW%L#!S;I#F)?o>o%pmiZLb( zj^wSQw>)?g6>F7mwNbe(Dk`_fm;gA=K90&8316K2d{N4F8I^-URM;oi zijkU6wudP-pTc;k*VMMC+c~$H8aE2NL6%HqBG62Ph&qzcQPT-G%@QI$Uk>WJ^~I(y zeJf7G#K+p@`ZhidqT!rS?5>*3)pHb5-s(XSuQ<@tzvxGR)t-SUTM*yw|21+8PkOIU5}L57#G+Deq1SUZW5OKs06^%y@hcCaX9 ziEK-VsO0`SH9jqI;A`UGO;oIX&$UtM6cv@uF(v?xQ--HYN8cE5`l$^|e-{l$%Bc^i zQG>mEH#KU6mae+nqZCV5JpiVuWKV!;{@x2g;3hjtMVW-D3|jyks?8q7?FbB}x$=AyMV#{k}NTqOfE&N)p=k=t1f}N$`@@XeRuy z^ODsVN$`@@SWAe=Pd@eL-@TS?nD?KNw-$N4jr;>qk$*781le)EbL@E6?Wg$_s;0cO zOf($%L480)p8fG7F|loPYxSYkfk*8@Dl}Q4dc2zuMpG23v*g4uT3exdec-V$nyOHJ zYhzLvt)ozVYhyB_)OQQ0tMs@djiTr_MV$S(T1Ac84@p`2z9Qb&+hSe_4~DSc9c2)+F)SQm`m={ zC8Ki?&PT&|ipF(7Cs;g)Q2|%=vWXVdKc3MxJvmsOddw33r)i~hk_GkQ=uhi=Ym+VE zf4X*XXYFwTDx(~)e((tc>Pdwfk;ol9X>c*A7}%y|$%kV*-!3i*O)9KQoMI*w&lu-y zCKXdn?gnwBWQ+GS{ZO!EZ zOb%{pt`J~~qwi_16kzS(mgXA*Obza6z9~R;N&N-VRTk9ZQ#ZcpLa(-j5Z{!3f8AGO z_Nq*AQAm91qR=#HofY5uDDiEGF&EZxo_1^kSWs=#>!ZFYJXthcXsY@^W(Lm(rp0Bo zYt@{F|L09#)F6#rFIbR<7~kwpHy})rXBb@c<_pXB{(Rf=#23V&P;a)L{w33!U&h`% z%bbei%;Vl%_of>@TT{BgdC_R0g}OJhpPw5Sx^w@EIXVr}`OOm`*^2oBBv-LOfaKy9 z3XnY9A_0x3ino=9;g;YrfW8UPtNI_UTvpU8yo{ zXUPNdn&;EkoM$#0;zGCI-ZDq0LAvG}1xVL?lK|^*L;fwgOKYRZ(9XO z+2kDos)?d+*|!-`M^}ZMhK=n87tx)1GV5gdPvaJfKu~n;ENPdC?rx0k9ur8lA;z)M z?X;v_qi<%FZX+5kv{8K^GlOSH`{P14+76hb(;!9npa3blhb$O`N2lg@1*j&{zD+-D zKphF5M;|e`h{XQ5N*lKn_**XhQ6%il<(P@Yag4ZjBkuRh>n;tKk%-m( zjPGTfjLT@-jE2rr=HPsc;_zV@qcD6F#;A{-wpb7vZTQXzko?|R0oD$3<;Ma{4U*+2 z0#v!l?_-}DP)9b+_OZ_lE+QN6J>08~H)O8}0!7x|-uTi)_A89+*CvP}vZFgY_x}B8 ze2QqaP!L(34}KeGZ&-e3j!i)n*Y7P9#7j>{&I^#d^bZ20o0S&?NcSp#6d>KI{7Hax zr}Ae3(v8Yr45%Z^_bD$LTtqhWs}Hk>oSoQD1c4%J=X}4J$X>?C{%(RO)Z5_Ng%R<0 zZP+gwCH3-r?@Cv2b7~FAk z9V@iC)fy+2dA9GZ;-HImQ6I?6uyeOOvqbEG_bH{)nmKL9`H`C)GHX)%StsT%5Y0w@ z(arMAEjA{6FEY;hv+%vhc!^Rt5*Q7QX89ya!&!cdYC~AtH`aP_p@1a#USvT@DDl#r zwumJhrxTxTr%hF-rk`*7zBt<=UFmGeK^CzNvS?HkZ-_AgQ%lM`3RYh_Y1xN^Ps$`y z=%7CeW_8JE-lA=Xj5fU9p5{;0{B4uL%%QHi-UQR+p&r0Af2a>IO(7ZpOtXlF0MkU` zPJn4H(FkCgPBaFXW)w{Trb$IpfX%!j9dVjkG(((b7a54t1S1o1nqy>HoHXV;vE~K@ zjkPei*cH{d{!0&Ce`4ia(LIXx^1DaqGEz5bZAP6oa@48lwKd(raf&5a0lNvK@^7tm zG+8uWu!Q=6YP^r?B>oI0*GY=W=gsu;g?`Y9N%CIw%(2A>XQzbWCV4M;gG+t)^iK^d zO^MG=&*{`Ev#q0ud`aHR-o0JAy?n9aPj3>@(kBWed9%FRp8Iq5Pd%Me@i|#tT4nlh zB*~j??;q;+Q+&8^k~hcuq}8-7XTCYSK3?4(^ueM@-dxYz$Wvgl4;D-EUh&LCT!H%Q z#gn{wo|(@mP#I>oO35T|zGn=t0@by1tCUXi7I?;|DX@+YCMJ0cJ!4rEnC64!lDtKp z$+ilt>w^`NyjMMwC=^)F2P-9ci#;=DDzLr}R!;JkcxDVxpz4|my*bHy%`^Ald{m!P zwIuI#&)kFZQGHU?lf0##x%1+q`mAaudCNR=m%>N&Y2B9OE%(eSy^reiN=oupcxDw@ z2U|B$E6H0K4tBCWwUi|94bLom`c3F_OHK0L^vq(OkLr_4OY&BEW`RnfDf;BGDH z4dQb>lx6vzlc;1b#-MH(7rh;*N!8Z~n}3Dtca(DT>?d70)``|CVwecd?v0RjO)kq^{PCl@GTs2bByZny(-TuZmZX^*wKE&7naO#+tc5huDEx+_nXXoG2?^e4VF_^ z#;Y<@aofDy^z7f~wd#4%a_ahcRbEoucJJx7}zNDiuUy-}Lt$V7k%ItWso;?b`S9(nb#F_ z+8deF^zd)<&#sDZo88VZOBHj*E48F$qg(fOUK#w7j_EQ*oaJ01Ja7$e8v-&A?mqHs&# zuqDK19W(Y-QpaGANN?6LM?`+%sI`^Hz*d&^j>ni2bDTRpd$tLyZfyKkt*5Grwj)i{ z2U=vOXSB^q&oQU#PAeGOBD+7XQ z$}hU}0ah~#A6{T#*N<{?nwgro3xTQY-w5<4E$$*<>iPFxH1jGj_5Hg5nprFvmBQ5u zhh~-lqi+mq<~3ka{Iw3vyberlf5AgDOMyxC?-6Kb88CJHI|Z6q4osSVyFfE5fT`=> zGtkURVCwld4m9%yF!lYr2by_PGPPB5B4!mZ>W%?1t1Tn^e2GFoZ*qsf^`p>_u5z&Y z3B>8HD@ZeEcYQ%)=Y!2v<=hPgjSd~BK8v%(gy!QfR=;7EXguPp*KeGa`H8wo#LE2C zjv`@YekM^;=I0V6Wqu)1Qs$QuC1rjkQBvmD5+!AxlPD?k8;O!Kzm=#_=63*-GQS6y zlzARtQsxf;lQJ&=Ov?Px!l=xjfMI3+3=Avt7hqVK7bO!?=C8o8GA{wc%KQx&R_0}3 zSed^A!^->v7*^(=z_2o}0K>|>3JfdrFUf?I`9EM-nb$1iIR0W4*8lAsSv*mQ zr-)ym7l?;s`LD^D?sdqSW!$_Nqd>>G%qNu)tJ=Q%Si8Q}; zO*|+GwRTFxLzWOD-Sh7@$@r;H+5vIacBIp1O(A{MhI9giw46IJ#zfC?{^F4SG5grh zw=B#XFB*^h%^|fnN!`goNbC8h9&vetiVjnK|GXnE?@kE_S*sRJ2HwLd{&%$II!lftUJvH_W7v5 zz7S(#=s4Fnu*)hmS~{}9+^wSV$iEy|dw15I83a~24;@+FxDo_Qjp2TMjXFo1*m^al;!bRNhX}YK^$z zJrzEzwHk55+bVomD>dRSv!@({RtrK0V>vKd6q;Ef88y6`(O@MoS{nL0yxT&AcEyz9 zAB^vDyy^cNT65>qU2Q|VCMvXRV@wns=M~i{Y3x36+^ctae@cdEywC#m0e|f7l*11? zNQ>*(IlXOmPG&79pSr8&@=7=1>O_3pE_Hi^tJ}Z%f`QO3cNNY3mqK|gpFwZ)@^JIU$7^rtlPw#q2n}Qzn5@jTdA$n3k?1$?#=Klnh^UiIU-K zAyH%aS^`XluNA;#_*w%@hOZ64Wcb&^|VA$|=luXF* z_=g?ftg2xRH2hg8|uPQ?1bL@d$mU(je!?N?`E4zF=#SozaA zo@lyIITB_oo{24q3r)m$kC2|x2eRZXLOw{UnRP|30H&dc&6OWH(NmN}kA8jttR43j?TS&By6YHZbC7R~AKH5s6 z%Cq@sYm4g4QqPoZxosq&x@SKN{uN43A^>;!AKw43? z{Zr5kR{#ayN%c=dGacb~ls1XUv5atrm4E!S+PXb+wtG#<{+b_3QMD}o};E7@nJD<_LB2*8g&%Lf6jxl4j4|?@sbJU>jYppVdn#eGj@JpIAs?AhI4jkLzsVQLP?u8fZ@blR5GE=eFHF@x{Fyxc;*`?eOT?`FY*RRF_LHY^+F?c2`j~tAjL$t zRE$xb<1}O`w%k6n=c~DkJ`_zy8V6GJcdJ<~ZZO%~e@2%3mOav--vzdLqeMxLnQNiY#qrh1$J z$y1LPAX(}M1W1nhK>?DXe#n4&p2U9oVS%%qenj9QH~pw2*i2851bgX;l3*)sixz{a zCOhd#@*8ZVZQ-I=W_;7xQ~aMX8|6k6v&^Wk67_&5&BW>{Ik771K5eeFoy!Y==$tP7HoUT(3|^u!ebo=?Dw4BP=r4T&y>L^zZ(ry&h^4CmJ^E%^fm% zSu0Uw=(2Xi3TNnY5~U1XUZRwtD@c?wbVZ3$hOQ)0%Fs7SlrnT>iBg8HB2miFH%ruH z=&AryhOP!MW$0S~rVL#jV9L-n0HzFG)54gcZv}=k^liX!hQ1vb&d^Dc31#RzfZ+^X z3mDGO$-r=iP6389bZuZbL#G168M+QIoT1Zz;S60D7|zi3BooTe^?~6G-M})!J9nRX zap}6#rRxawnDu5~Jv2NwvI)8|B+c&$u>8K21gpayZ zLo6BNp5{OU)T}H^)GRDZ)T}EDRE-M3va&?U826Q^SyYy&SyMJ>AVxOE10=!5c%UTM z7!Q&J8{@%}U}HQ)5^Riz3L<2The?8s@!f_HU185dhc9*AoY3(9?F!Zz-)p+U2nK__&RD%y!zSQCVkgGng625G&UlDKDF+XgC?(-x5~VDBw?ruo z-y>1V!^0&?iTGZLQYIcDQA))lC2DfRpcQ$oJq!sv|0 z0mCVIJTRP-9{`4v@`I8IW#xx};k5iPFr1ek0frOvqrh-xo&XG|=83>?Zhj0HPR^5n z;p{va7*5ZROD2?`p8$pv^plnm&UoaEC!S2tS64nT$v9(QJv2a1u{$xIiQ0)VwV=_U z-_+$vGh z<~tH4ZElk&X>+?oNt-()O4{5hQPSovi5hM02AH(D2Vm0XUVurP`v4|w?gyB(dBDP` z&4a+OHV*;A+I$xn*5+Z!gtU1C7}n-{z_2!t0>j!o1`KQSI54cu_km$;o&bim`2jGj z&6B{eHcv?=q|Fb3VQqe78OQN&=#YT+9V^zhM3qORdoFU9`hZ$jCIOK=&suqY4Du}R zep1jVQONV@3Xe^`UajPInKuJ@HcM}(Ote*J;qaSLTz=Ad=rNNnKjvJc!DCxoe#W^* zg9o>`#XOsP{aU-==|Jv{5)B>?wmKl`~55bcg20g*bB&6C;P6#HZa zQ%_dgGeT5VtDHRRKK0$cs?W!-5RFG#>Ezi=7JJ?v(OI%~@FYz)DPqOt_v_mFN#qgt z4uDhj!ynyR0IS)B-&2zTPScMebW;GXt7~W7+5p$n4_Ij6wMtq*W&Akzi_*YW#9#BB($DqZ&BI{{WRbsuhIVVy-&>sgsL2ByB1 zX%orRsbyu_6d3&+SS_D)VDytrHPZ~3+E%6+z@*x;&rD!c0RwgTEMU^COq&B!*UGd7 zF!iiVTLPn|kn}sPB$HOl%Ct2w$yTOqfKj#Z)LL6$)a;p{GQDT&U2O(jD&~mBBfgGXWH$?yeIECOM&Gw1 zN&u5aPXJ6B{QzLn=t+P{qo)8SjeZC)Y4jt2Nu#GFY&3cXVAAMWfJvht156tI1YpwW zrvQ^iKLeOF`Z>U)(Jw5F8vPO&*63G~32F3eU|6H)fMJb(0}N~QTVPnD-vPrK{T>+B z=y_mRqdx${8odAvYxGCSgf#jSFs#v^fnkmQ0t{>PqGiPD&`YblvxmF?ks@S71)#o+ zNT9#jJbD@OXc_l+&uCFpe%<OnG zlpmh#S^TR`C&k&@w4y?57c?i?&`ypD?c*x6K@>%39~*RI!WS#5FBXl5L(8S0Pf=*8 z$o6S_v_WXqc0AHPPNeK@qX6m*6S?aZjqzUY}KiqQVBxke=awEojXB7htNgeZ|5$v}&L=Rkrhh(W1~{nhy+D*)9M^OGAHW zp=Cs9Z++wB++iDT-Yw2P99mlny4Z$xNmOWG^Gp;SXOW}&jQXGY`_sDde>cdT-=vcI zM+qNMw_}{h67|O)ZNjCXt{W?BK|R+_T4XV3tR>v2YS6eSPMtrMgT`A55Mrp$K zuVut7iSr-NTc4ZvO|435;IP98-I8b)Dh_q*bS(y^Yl*HKF=`YNy=CLX-*=w*?t*CA zN;Fg)I>HUKNNXx1?Pww-ItpNt=zRc_L`MTm5*-6DNpvj0B+>f;CW(%du#xC^fJvec z08A2n5MYw%LjaRR9|o8t`Ut=z(MJI$iB7OEN^~MHEYZg#6O!m8U|6D)fnkY04h&25 z31C>FPXfadeF_+s=+nTkM5h455`6|3mgrQ;ge3YbFf7sMfMJPF1BNB~yk&$$Ta5U$ zO}Afv|5)hAN|ftJXV@${6S8Qc`=V>qD5?hE9sJ|es_PzKB$}qG!Dh0QG|f)f^yZ$r z*76vU>g_%C09Fq!_jmo&2UuN0A8r6}TClyNA;9V$k^kvC0aokGKHLak<^6oPv4w-q zUdvVuHUUO;T&m1#3XI;huN_`GFnW)YW|{$`H!5i+0~ozqNi&(i=q*c{$pS_xmyWHu zWrW8ZdA{E8w|*UvBCeqEn4+k(mGzjdqdaCC&-4V*J(B7i=<)BZ6;6uA!`*`?o$c++ zNOzA8_GoqYNYz`aB5t;X)o7x-M@NA5cB+V*1F+sq6>)O`RwJi>!8-x0H&R91&H$?k zk^ku~7S`QEO*_r2oT7`O_>jjM7 z$)uUPfKg)y{Z4Poi0)DQ`ReftI(~bvxPsyCVJFW0Z1?CN)jbAyrYDF5@6AcxH0j|d z){DkXf)5v!?vx3BmmTNK*x|o2%iRqyCHOr6Q-a?MFeUhX08@hB4=^S80{~NkKPX|7 z;12;z3I1JxDZw8Gm=gREfGNSh2QVf0qX1KaKL#)*_~RDF1phuToZwGLCY0bm0EQF% zNnkj^p8|#x{D;7Bg8v8@PVlFJ;RJsM7*6nKf#C%IF)*CqKaor*!G8)2C-~2R;ROFV zFr47Ou#8CX3%~wi%MHVa{VH^15`3uG^lO{o&qXEpZ(O5B$I0Sp@`yzv*Y;Q(pCy`( zv<#-nqS$nq&F{L}bh#Z*ghp2YOd4GYFlqD+fJvio0!$iR1u$uJHNd3NH4-)&T?;U2 zbREE?(e(h6MmGRV8hs03(&$EjNu!$pCXH^kFlzK|U|6GDBoor;R$y48?*PLZ-3AP6 zbUQGt(H+3BMt1_k8r=m9Yjig-tkFHdutxVvCZy4Qz_3R51H&3U01RvNpk>5b*4b7| zyB*ox;6))Mvz8SuJ3Vak=n=@HW!?8YqesWtq1NkYDeuigleXpW{vtduZ@2n@TFMh; zr;TkQ)h?@v9Z!r%wFz$uFq!alfXRe61DH&B2Eb&(GXW+Oo&_+O@a7gq6W#(CHsLLS zVH4g87&hUpfngKg1{gNsZGmAE-VPWx;q5IWI!BQrHHS8T>;?H&Bhxv;6{#KV2%ZBY zcv&~sHT^(zj(!WbXD&Zi&=nmo!kvRHc$c7asI3yZb9A-GDlB+62^$OE9bmHHJpd*P z-Vq?C4ecr z{{}E+_salNcK;n<%I<#vOxgWUfGN9Qu`p)$tH5w}|4TBV?EXJsIJ;j1hO_(Mz;Jf| z2N=%o{{q9={W>t5-SdFq?C#hM8t9s{dkip~-CfCqvbzTiXZKiOIJ?II!`VIFGQxpZ zI`{GL+!D$8rAC9ty)+Aztme1Ly#OTlM7N-4)F>qS>%4t)AMKP^QZ#KO8ZKF#B_%rB z##cym4!|VQxd4+yUjdjTIuBry=zM@lq6+{fi7u3|k?10TNusX;OcGrTFiCU?z$DSv z049mP4lqe{DZnJrWfn$>E(eAsx~Ff9Q9v#fSeBIx>^wP<888 zn?>J&ESl(UbB!9sGUvwJ(vNPucK5TQX|v2J3tS6Zk!p`s#2%{=sW#w60VV@}1Hfd! zivdgq{6>JufENdt40s8E$$*!%aM0O#6}%KMY`{wc!v?$zFl@jRfnft)78o|*<$z%W zULF`W;1w(*mN{E3dn)0_GKGtZD`=KEMeXZNwtG~D?om#?*3a|=(LEB5)xD$UH>oW| z@DZ%Fl zm=b&efGNQj1eg+h1Yk<=g(Peed|`ko!50CT5`0mBDZ$?WFeUh608@g$5nxL2#Q~-S zU&6we;7bC-3BHtMLJ7V!Fr47a0K*AB5g1PJWr5)YUk(^f@a2Kw1YZFdPVg0h;RIg^ z7*6mvNhXxwD+9v`z6vm$;BN+o6MR+6hy*`=`!~tA=OnfgIx-19R2*B~?nJ2(wG*Xg z#HdlNovB4`T3{>p-1>W}eRJ<6(R8G>`hZ$sgW}lEQl(w&!3vdj1(;OY4Pa7fcYsNy zJpd+^_5_$z+6!P(>0J^wD(ww0sk9Hkq|&|slS=ymOe*aUFsXC^z@*ZF0Fz1wSr}D1 z7#LRR5Xpp8IusaI=`dherFR3vD!m67R_SnHSf%#@!zvvC46Ae`Fs#y1z_3d1lT1jZ zqk&MIu;mK>HU@wWwK?C{E{8UWP2hI~M3PEmgnC+dXa%SL-ybPVkhc_W@1|3h_<=tlW)%2l@km z>ji~)CjqV>6ylwdaNSx#A>M}oD;wvx{Sm+^K_T90fNKYZcxM1k4eDjj0<6rm-}c7< zrv-(0p8#A}Z5B|U{uE&Kj#VH23}7{b@ZrxbtaVyXKT}I@M)(34{d{Q6d$hqn{$6nRCGCCkbfg8({R)1T^z4F#3rCn)wbG{Zs+Xd=HF%vVdmJOQybl zmb7Mm07gGwKr?wk-FNO6 z%NmW&2beUv0ASMSLV!u5ivT8#zA9m((Zv9hMwb9g8hs65(&*~|lSY>UOd4GVFllr- zz@*U?0Fy>n0!$ix!@{W1H-TY|t^$TNx*8bP=o(;Hqica-jjjWRHM$-c*60RcSfg(N z!y4TvnUF>|0mB;I3=C`ZZD3fVTYzDWZUu%l`i^BpA>N`1uf3XeOW6m6jHnRLml5UB z9dV{oc4wTdlr7`#iZfaibvLKmwqIE!a^DA{WvaW$kcD_DR-?LFthPN=lSg$)Q!2pp z3br}`D{tqQG^JTs_s2AT1zTNUl!>L1rh1Z5N;R)ws}GE>o6@6V1Ivi9@7YOT z$`Nt)cI*om;x)3NZ499;=QfEmQ52y~+je$dxd&SOAsP>dmREzC1);60E4tL{SM1U1 z(AL%ETdl27*xhn5TRa)Qt*H==uOu02{E z+Ing{_k-05V5)KK46ri2{-?WGI2c8_#<43f%Joy2x&gyAj@^OL($KxOhh;=)8(-L1 z>FkB#@^wMs(Aq-0yKHECM}@XeoQa|c?f%FA`t8Z=iigB?3x}2q@%mF}sm5`DJ=!3& zTCov#poGa{!YWoMz!* z7~=`s^T4nfd;u6XgVTXwGdKenHiI*PVKew5Fl+{20*1}t%fPT1oCOS!bYOQ049mv4KPXc9)L-r!vQ9V-U~2EbOgX8(UAa?L`MNk61@*#lIUm) zqeRC5!x9|}3`_KWU|6E#fMJP_2Zkm305B}k2Z3RUJ_HO)^kHCFqK`->B+*BKVTn!v zh9x=?7?$W`z_3Io0mBlVY#AX@=imEg^v>)epRjBt%7u7O#+nJ+Q?YWwmgqhmYt$(2 zF^}r`*Xpdv$I^uQ=^k^2EW~r|giUWj@T}!Ac~oyfhy_?buQ=ky0j#c}Ukw!xuzpr? z#7zKLtwQ^s&L?3dQeB9bA7JHW{7)CKuA%<_2Jta_QKLSw?uwiKp&~RD5j16>$ZP#}tKlC9KCR z8Raoc#hIQUy2svPw^clK*FZTp2zL*jbSB!Fk?tO4?a>DIU2pS0j_l0Mi56Zvt3Ni2P4iws0^O@@aV4tO|@u z6m;3D0mDybzXce*lR|fb>cH@`*=qo!#t!6nZ2UpyfiHy%7(h_^u|__yphXT}cg!8Za-34Rm6l;Af5ObPyN zfGNRmk+4bdTLGp7{|>;E;I{!x34S}kl;C#&ObLD`z?9&30Za*gH^7wO_W(=@ey@cw z!S4fx6a0Q)IKdwPh7i0(%oPS}R(2+^-p+dZmY=S=>mEh0B8a0YS zyafXWT^c)PO15a43h^>TA>L@4-}P4gF?Ku=8XXHTY4m=8Nu%QcCXJ2!ljXnzuYxFtEgfu!07}n_Xz_3PN0ERU>9T?W= z3}9HJGc6<5vKBU6+HU3e7hV-YGHY4kLcEu49-Reww5&Tj&gfCpTHQEy*sD|b-vJwe zgIcQ$QHYmf6RCDtwe5IfM5;}AD!^pI>i|q9JPlwn;dKEf6JAfk#)Q`gm`r#B3!@2d z2n?I>JAq*n-Ut{r;f;Y|6W#=a9-kmCpcy&z1*9dmyKLv^9o0Gd#F~B}9Qb{yAJ)9oEB6-B zwsGL$LcCAxz@fAIr}j|Iz@Z)ZX8==n{~Tb-?q2{*+5Jm^DZ76qVUyjz2AHz@Ie;m< ze*-XO_iq8F?EW3Vl-<7vn6mqMfGNBG05E0u3jkAg|Ixyj-G2gxv-{7$aCZL%7|!k& zf#K}_D=?hhF9E~Z{WoAZyI%%|v-|JBaCZMgGNJ7LCor7duK>f@{VFh=-TwlHv-|&m z;p~3RGQxouI`MwpeK8$Dqd_5FMyL?)Un|k;AkjoOFV?70NOb(rFP%}h#ZLcEiG~aD zrb>xEYmZb&^f`b@qSF8-i9Qc7N%RGPNutvwY$Q4ZV3O!efJve+0!$Kp31E`w%K(!^ zX8}wSoeeNabPm8I(YXMVL|?HmN^~ADEYbPEutXOC!xCKx3`=woFf7qmfnkX*28JcN z1Q?d+YrwEXUzbcsqDz5ci7o?%CAu6Kmgov#SfVR|VTrzB86nXwqqn8*uQKpKp(8U% z4i)09wh~bbM=_=nzX$du1O=S@-{T54PZm z(t?+@M=LCNIe^V7IKXBV9AL8w4lr5pN&uTxaDdG!xP{SzR{@4C_|1|DS@5dBum!IM z3|sJ9fME+>9T>LYHGp9YUehw7d#uf>G_u6Ux5+oQo0}wl_uy4<+dYz^y2l-{rYDF5 zpE9TYg|vs`cF68Qx4FZGcuVC@lx6mYycs*R2VV{_CHNHpQ-WU!FeUgm0Hy^0ri4v` zUj;BF_|*VYf?oqLCHS=fQ-WUyFeUi)08@hB05B!^w*aODzY$7cSg?N8Tm0qz2D^z+FU{dK{0Fz4p2QaDh8o;E|za?x``VYXQ(tiOam0ky! zRGJ4csnjVXw%pVumBs)}Ds=%Sm3jb^N@D>gmBv{ZRT>Wrt26-^R%t$9Sf%-aVU-pD zhE-Y+7*=Tn7*=T^U|6Mvfnk*vkxWRXMS)?J-T(}%v=}g~(i?$cl@y395!Wv?RWH#&T$yUW{Ra`(FEdrI z(Lr3l$~59W47hr2rmo3*1aUQ+@Y{dX;##xG$@ml&)UZ)MTV|1+%6eM@m;QYw8K4bS1N^)ynts##N0 zkkXaSntBE)UEQpysYvMxXH7kel&*5t)N@EFZ%+q5%~HY+FWNCBZEgDKH>HMyH%5`l zNW#;tglB++%egZP8MQi2AC~a7Q~y5pV#ht%!x1O_-itWtcLd_3-;s!uen%lr`n?Zv((h=*Nxx$dC;g5E z-01gy#7V#7EFPub@kp_LA3%!r`yf)R--nQ5{XUEo>-Q0)Sig@V#rmB9R7k%Qkz)Nm zh7{{}5>l++$w;w&A4iJy`vg*~-zSk`{XS(WQNVZ8SHIs`@`g8$35ihwpD!^I?=uM| z|4vPi`L~SwY=Y6L<6KwCo1R#4d!?x-^Y3i;glJi%#z4Hfgw1T)z8-J%t4pEs;!(f4 z6w0w@5PX_moD~DG@`QdVlxyLjf2#az-kjwjrR*;iL&YM+@6L)tO4nTJVKd%RVr)!n zlk``|e5IZg5ul}lOz}3o{5HG=AiU+=f(a&){sui8-h=6lU%&LuCU|*P9EX=zk_rdI zV{$EB4i<5X*u&LWD8*bvu@3h}K8CYmC|)!+DO@q`{1`v{4I zL(D~eNfcr=AnOp{VGlP5af()P#I1!ml}sihPBoJ$77s$4!bOv{kj} zrRAc(m1Zds;<|bNeDvrq6CV;$2=`)J+*jX*xIt8i8zz`&isHUazwSOfaP8zRqH%i5 zUZyDS+Z$(U_-Z-%{2IP}cK?zglpuX#za^rJ`wm2LT-^^kolOx99R6$17y45^YBY1RgS6+*e*s0xMX*8)O?Y zkre?Z6IlshGLbh)*qX@7h?9w|f;gGTn-M1ySru_Ik<}0<6L|~bWFo60PA0Mj;$$Lg zB2FgqR=|ykybW#DK?R*NU@2m z160UFrXj^9vMy3=BI_Z=CbB+KY$6*V#U`>LQfwmcM2byhBTI?p*6*JFv1qM@pVbf= zqvh7j&>Q%g+9_ZmyF`ZGbq*w;|#r-#Y;} z@@<4T$+xk^qvYEJDVA?jq*%V`NU?mIA;t2|K#Jv?i4@B>3n`XwbD%= z{-%nuqtH}96bOE8yUID}D&^d7;!Uq`oa5Y89vhdh%&aHI^%sptKH#px6WZ^CuHvs5 z>%MZ{9CW;4;`9{j3yAB@ClU8Y#OXQKKOwHhSO4<=j5s~X`WM92B+LK&MT^r^ zgP&#nD^mP0>q|)S)2x3(N+lM$gqM-x=UM-bl-}>5`@|ne@e{58L`sb-^jlXfCAv%G zT9+XseyPz=Tv0Qv@w7;NKT68oE*dw!K3p(3!Hz51 z7)-RsYQ`093?2iRjKL&;$rwzQur&scBTmNP3B<`5Jc&3NgQpNDWAHTMWDKStPR8IF z#K{;;MVySmvxt*1cn)x545lGY#^8C2M;U_`kYZyn9Vs>jGmv6qFcT>@1}`GT#^5ES z*ciNw6dQwCK!uFKY^2y2%t4Bc!Ca)+7`%cM8-saBu`!sB6dQvDNUqEtai>-W@fP53(*W!&*9j6~p%fIgOB2M~kg*fTAHR7b- zHi(mc+X8O%+YWKkZ+nYJ>9+$?tlw;;Sic>SV*TbI#rn-fiuKzGDb{aiq*%XQfC}li zD^jfAZb-3yyCcQ=?ST~QwsPoXkgcLotnM76I27M-4)ub<=HhrBVg^- z96JOBFd6$8fXUdq61K+PL!69#EaGJB;}9ofA8+v}W1oN&8~c1nv9ZsO6dU^jNU^am zh!h+92v8woUkE8S_Ju7aI!ecUA3t39Ogs4iII{q&FD5O(-e5=iVldK|b#II}eZq14 z86MpSoPM~?Q^&jYy&^lx3ENTF)|UiZU& z+4^#bldUh0INACN7LT&^6_H|FUkNF;^*15Kw!Sh_Z0oBa#kT%tq}bM1MT%{GHA{)k z^74$X_qXma>`rk(L!HIC`Wm*g)QsvZx5k@(Azb|jD@Uf!|NVL=(YA5*;UdIk($z1w zhiV2D?dn$mOs-%hz~lLL_UBPyw*cI$R zie14@phB)-7gFpBb|b~EU=LF43icw!u3#Th>;f1COf0Gri%fXURKl(04Rrw})*^@y9*dc@6Y zy~U$U{TZa#)SpF)P5sA6v8n$ADK_<=BE_cuGoV7I{&S?*)PG?qvHY68xPAH4LsM@Q zSJN!NibBS(?Y4?@u&qL^*2kG%Ay(_X<9D4u{PnOIqH(iYAC$qF`QP_JSK-xqd$`ip z|A4qztw-Ff)+26K>k%hg|1;udwH|S^T5s_vTmLIkZ0j!}#kT%8q}bM9Mv86y??|z& z{{tzu^?xG8w*HExM0cq%>DBjI_umeS1$1*q6gK|Pc9&~W-R18%(=&uI=>6n|P6sPA z{O{HJaA9MX+=bKJZa5IepasBW3|azA#-NpitubhgI2nUBh?6mBi#QpBc8HTPXpcA< zgARz3F~~-oj6p}l$r$7yPR1Y?aAOQQAx_4iv&Ex~K^LUh7<5I7jX^i0*cfz2ij6@J zq}UkrM2d|;FQnKQ+yzv~81zPpjX@uz*ckLhij6@(q}UkrM~aQX0HoL$3`B~J!5~Ws zV=%77)=oth-6oK9Dqr|b0usQ{0icv;CYCXg6AVn3SNLXDR?2`q~Jw}lY(DG zoD{qmaZ>OS#7V)g0d5rhI^v|@r52A;@G_)W!OM|i1+PGg6}%EDR`450v4Y=3iWR&H zDOT`mph5~>gA^-xEmExDbx5&-*CWLW-hdP<_${PZ!5fic1#hyHD2Pm4mEPg>uUp3p znbDgGGf8H&5WB^Scq@pwy!%ceqgTiAHA*5L_jsH5iKPy~qXCC$5ogJQ$U=n!YnDVwSw`F&5!bJ=jJU-S zSC-IkzXam?6_ydVB;xu7mJzoU;`;TK5w|qr%A))2mjPV8s?_uGM8x%rD`I> zstQo*1*Z9_Lhxp!bXB?jR#l{QWx1xRA*HL!HFXP8y24yj)sfOw=9;R3l&&<_R86FG zwYjElMM_tkYw9+n)ck->`F2YQEB)AnRnsrN5;tAyIIz;BG?HmyDYZh$yxxFO=C;X4s04L3rZG~5_)qv0lqlZKljP8v=}oHX3b;!zsTK#Db-i4Wkv$-oZkqzOMWTfGH%!WMyvi#Ih%(&oxXX_ z&_zSO6r%&xJY~r@8y?ALHLPo%-pd!IVO>^s6mX?s{Vua(h%3M7mz5p2c+f{{^V`hc zM@m^_Dl0pI6u-~x1Eh5QnjSt+T1t$O?``dVy~6x@gGCf*b&8@uA^s?z3GwNCGQ{QF zGxYF#8uDo zL;QusX&B)8(=U`Ur=Ziz9!e5GyyMd+|^9aDx!1s*&Fh+0Tem{pl}=Dv1+)kD5TRnQ^7vd0UyG3w_G)}&3H*w91+Qcv=dlLP&6Uj1-LPjyAdZdxd(AFlY0>-Gr13O zGL!oeCo_2faWaz!5hpWw2yrr#?;=iS@-X1WOddg;%;bBBlbJk~7N;SOCxpk5 zVl(+ZQfwwqAjM|#1EknYo{*i3$g6r0JwI;a310$VaMi;;CE}2 zgkumV3A>1sggwMb!m)^xgyRq=3C9C&B%FXaNjM+kB;ovslY|RcJW9d^kzxr)kYWiJ zLW(6^7%7%;5u{kcMS%)Q_y(j{!o`qc3EzkmOSm{vEa4JJv4l$^#S$)s6ic`?QY_&z zNU?+yEhQw}&dvF_W@PKA|CTTpNtU-huLAhIM7Lr-qgHV*y?xEkdLO(tW4dUX?xknR zBFR^HLZ~-W&$9<>MXa~T&IeqHSiN5^;x0g3T~8lhh`4^LZp2-LxLPmwKmRJ?`iZ&` zcQNA1NBW;%V(~x(YPMwxC0|2Ib!Vz8dmSmge?*(brAX;LB$`?VloGTm`qb2Nr1VY_ zO|3vmZzj>yN~DysslhiaB|K}f76TvOv2M*gaYc=16@`+kZFgA%-KCtnHlOJkqPskm zS7FDHf#qdYPPn`9 z(S2e!QvAg6JxHmsg??+Vr9^jGaQ?Mt+O#S0|92NVQ9oe2%fYDbawwna8NwjsjcWJx zg^Ba-7Jbop{BWUUYaUy4rDPj>uy$%~M-4G{(&>e9y2t6zwWe|EI#Rj1lQfv_J zLW&JSZ=~2D^g)UZLSLXl2B9BPY!Lb*#Rg#jQfv?gBE<$_5K?Rq1|!7=VF*%e5QZYf z24NUdY!L3YlrRY2oId@+hvnzz3Y{5`A1ao-*GhNO!x--HxvxH3|#;VMY6hHplSHCz=b)^IhXSi`p<#Tu@T6l=H!Qmo;cmJ(}i zr*1fRYVVMh9}A(GwYG4<5*O5TmT=MJ=XPQC zi>QU!FB43^5S?Yw!t)&t4X70nZHGDwTl{m>S=7xH-C4e|2P-Z9w}_L){|<4o_}?Q= z7XLirWbuCh+*tezh?B+t(c)1S|0kr_;{S{kTl`;;VvBzfDYp2(BE=T}5>jmOe?y8b z{$)#v&eHX_?XUMZdt#foprOuU9sZxTvs{VlELRguzYq@p(pQPS)>c}&Q?zXyez<6I zG&uY**2zeBFcxs*4(>;s+`%}+$sLSGoZP_!h?6^b5OHz`4l#W{3`gp&X_621d*l5j1= zNy5p9lY~<&9wp)0NU?-dkzxtgL5d}uh7?PbMvdO(FFTpuZxa08@R!VQsP3Eznn zOSlnIEaApTv4oo-#S(6c6iYZADVA_EO9=_r&2C(LYx|v*gwBkFL&cL>R>IArB-|pO zQL9*%U2>&j>vEgw9u!TRWm#D~`3e~PdDb&n5eKXIfE$Cq0C6(-3lTS~_=uZTe8kNv zKH_E--{MgQ|23r8;J=O(8~mk6vB6&kRLI~jM~V&p3Z&TJuSALs{u`DO%d&0OmMgtw z+OTYKMa?R{D4<+zP1_nUZE6)i!SoE#T|Ry>tyqULFO?IGhr0_~{0(67-?E1*E&fKt z%_=_PW)&ZCvx<*6S^O=48;idcakGkV@hFSG4Jo$x+mT|6zXK_@_&bqei@ysgw)ne| zVvD~ADYp1~EhW0ky3Tv^?!T>YKXFCF-NkzR1Gc*yjOs3j5=_q!2BAs2!Q)@r{Ow<& zabpm|1(e^xPMz=Vjs!cl=vDmlfE$DG1L9;5E+9?@;YY;DApC?l8HAq^Cxh?{;$#pm zB2EV3SH#I6Ttb`-!f${ZgK!yfG6=sTP6pu*#K|E1Y4Iq7a0Mwg2v?C}gYXwpY!Lp3 z6dQzVNU=fq8>o;$_y;LA2>&9*2H`qVY!LF0VuRq=nh6>e*dW9p#RkDeiVcE?6dQzC zq}U+DSxOj$UXu&_^2{xRLp z+yiVik8pidCG06stHFDOPbOq*%qBEhP#mH}~)L z%UiQkt_Z17A!U{vykh4f5WMnegBfLYl*bdLT)Y#DOZz@ z(`p5Ulxytq20BjDFC>k)YZ2G4BaOK05LZ6QFBDvlxPBFB#NB|nei3QJeG75@8q$cn z5piV={q{E@u3tf_HhwTZdd#?iy5=_GzAaH*ZmTwZNK{waM%=9u)kU^y!-qt5eQm_u zCQ)5l8*#TwR9DqT+#MEm{Ug(x9Q96(os!TSl{K+T5~{|!5S8`q21XB_`a64o(Zi=^ z_5z~^P|fTEMh~Hy*$<2!L^X2&7(I+?<{&V7Al1wvVDwO`nRkKFgQ;c?OGedKt9n+= z905iTsG4~X7(JwF<|r_FP}R&a%LvQdyG*SjH%@ z(&$^jutqlm!y4TL3~O|=Wkez5=x3W=J@IN6xF_D-F)|{7ZY^M{^xi2TtMtma+X@&h z`a9vQA>LH3=pXN19W0BdsJ^MWEQD;&8r3Ca9qh5%JgQ5`vJt13zjZ`howi>>mSge2 z@1^m}-*S;sSDs49Iw8d`f9s5tu2s`xU>8e?F|g~XkIU}a)BdIZ9s~7zGAYE}ZHRk7 zh|9S>3z%p+&L8U9(43>d`muWt7HRaDXgqS2E}m+fSDAX75bG+sh}*{=Zfr1&=m7VX zD22D5L@BuaEvn_tp&cLz4(vcla99UPf`dBP5+bNo&P~ob*JeXmao)5Rqq~+}iy3Bv zdUsS%?89<2)wj#J_WT?PTM}_(PusKo7ylc8tZBIoftx`mH9F<3pzSJ#sMca`UK}HRii`@mbx3^9IR<3#xst@9nQu`uKDYYNslv4X6PAPQ& z;*?ScB2FoF5aN_l2QwZ@sY4`6DRrnsDWwjRD5cc9B}ysv9*I&)9WGHysrOnGQtAjv za7rC1iBL)%1q`Ru`+(t;IvN;GsbhfQlsXm|PO0|;!zpzfFq~4y1H&ox0bn?#J}8+` zN__|zPN@$A!zuL`V~EiyF^m4iKIP46Tyy@~GR!bXik zqOGfp-TU@Uqo#_ctwclRV6$kasF|70w!?{(=p4k2>qXqSUc`;-MclYv#Et7k+_+xE zjq7DRB+*wTYFw{Gjq8=DalH~Xu2-VQ^-7c^y3C>=(dCk0iLQ`DNTMr&VTry03`_J) zU|6E7fMJQQ28JcN1{jv;T3}eB|JU7{heuJY?f*S9nJhDtgnbh*5LSVKge`1BNCHGz z0$~S<0bdQI4;#6_iCrcWa5Xy0`B(aXvb`%;zDtPlZ%&*2HYK-9IpYO=W9ATxp>`Z zz}?BoaaND~ot<2~Xf)vN;^e6EQi+=>%;q8?7J&1)#v!lQyym7pV;}y(T5*5>#|ur#4ziGlXD+_(#g3GKjq}y zhyU#4+=riba_+;=I63#>XPun;@N*Wo_2K7r%6<4RI^{n6SDkVn{+mv@5C2`K+=pM# zDfi)jnAFjS|EUM8KKw5|VC%y#IwDpd{_!URQ>cjtWM65pi zsv~0c;fC1|>Jj4;P`f#r!V)fynW<=}5zpfcw_|Am4 z^o~{yvusb~M3_y~=V+p}+GjfRn89SONRJzu}==Y1Ay?LW{<9tmkr8Yom8LB32un?TA=y^lnGQYNK-; z5vz^PbwsQ-I?oZY+UR^o#A>4p91*LHE_6h!HhPa9v9-}fj)>Jp7ds+W8@<;NvD)Z; zW<)z(k?HKXJ3vY^2K^jr0ch13uLr4dY#Fpw;z;x_bg|E_b{s zal0I7X;0kDuy&;4A&Qx1H)u9eG0vLh+Ko3~stc7~O8fV?32dr_{B0XS@vlitDM4Z!K+gsBC|1BFfQ)N1IjI ztQ}&QRl&)*3$N(p+=W+ia_+(_J2`jZRh*o=@TyMEU3fJo=Ptau#cf@94V`iqUQ?&s zh1b$4ci}hal)LcSI^{0Bj!wA?uWM3A7k;B2u)6RVJz(p?>p3D;7hc~HvAXbBN5tyF z8#p3X7v9hjvAXa^j)>KTH+Dph}DHRcSNi%yoDoT zb>TrXq7Adw4IcOYfLbfAeKyPXSVWxJgU361@LKNHKGhnvCi+9C6W@pbGCbv)P1OEa z#5-08E=F1Jn%#-sM7KIQH_>fQ&P{Z?lXDY&&&j!o?r?H$qVGF7H_;EAoSW!}7PmFg zojT6|N5tyG zpK?U3KKyA%#OlMJF(XvJ*>2eo#j`f%Hw>Hjh>8a`L98o#|gXTIqf>w|Xo6%E`Hv9&mDQrC&Qax6*@7&aLztC+AlB zt&?*rJ>=xvO24zXt(AVSQ*Nb)b;_;u2c2>&J)%=?rAKwjt@M~qxt0ECQb#NONe@`9 z^tc|dwbB!gh}B9@IwDppJ>`g4t@LL{#A>Cd9TBUQo^eF1R(jSEv0CXlN5pES=N%EN zmHwhfY_0THN5pESzd0gSEB)OOv0CW`Gosyj-ea#PY(w?Y30hO)JI{OQcb@-cHq?ub zhFZt{ca&e>nd!crS4w@L(jC-ei`D0)wsPU-I(PHcfaEc@0pfJ z%y0$W@A}sN5#~O*c0_I{sMx6+xbWrdb;X6_k z_3MnZkAEVL5hw9L(EYw|!SYW}UfK2Qkx<$CfTM!$4}1qx?|uENqaSS`J5JS;y+Y9a zp|A2?Uo@Kb-PJ7OIJP8SDd^tm8@BB1GcWJ2(N-iQa#JPf{>b-o$&}t({B1gtU0jx< z8DfI&UB3FKzG?LGwnrwZh?u8-(EYKmVW)R1HAwG$vq-8n&Cnp|-tC)k;mv(TP3GK6 zGl-iLDbgh9{=|3R&aO#6XS91?MMP3J1>Jjm$Ff4-PO9|5A{7y-H4nN!^}QXl@8%T~ ztF2R!Hk4X0=>E+2uLV{1P8zOChD*k-Cuah8mvz7$+b!t+!Z#yi!N`rC*!~nSt3mgm`%7Qyv-84E)r_j3 zB4Ry~gYNyl`25dzc|N>UntO1l?czdKP?h>(Fz*eNCLJLGPgZpl@uo6PZVPesNK(bz54wzCrgl_G-|bt3g`O z{jKk@AHI9NVt(E^N`|Y!fS~)3FXqVC`RP^TB8VsU!TpVt(!ikmJKtB2pPJZX*nvZ0 z0qA$#v4ex|?|l(@g$KWy^Y{>&!K@&+2i=E#g~t=}Upbc*uOedIMhD$L_*&oBBy@HE zW8+0q?J243p!RRnmxbok-Uu!wu;5$DH(TcQP6$dUO~F63UX)A zeZqGj^_ii&wsw3#q%?s1GlK4uz6W3M9QbJ1@3ekNvVwSGXQ87w<$HYIlJv{j9j8%* zYltUyHbOu9R;KJexPSD392LTvcw*-ublSH*C8n_I*UhQnC&@bEiJgbY8DGKKKJT~b zHlP+q#5@ZSIqR#w=&g7D?0)wQiild`iMsz3v(-Oo_=qvv zWOC>zJ+V(C@Ta|6ByqLy#QqDRzkG|9&+gUn@*le>Ij$F;*yj7PVdTd4Hs&C=KU7x*u_uF+S zVpfms2pN9$lfx<`ajn}dgs~)5PSC8EYc>U_fv1I{>LfeBtsNc3fN#^?T83JMc`1FYJ z>1mCrZ6@frae%pQ}*{mNY5Q_A-yEXV%|M2Q_DLJ!#oI)td zAG>8%_WIl3q-rffVpUHg6zyN|XZxi;P3$&Bg+$iRB2>ZO{_5o~r=OWQRb~RcpeOb` z0u{A&QuX69B9;8hQ?9Pv{mu8(!zU++`tc8VWq-ZHzjdxwaos22;#VjrtyvgNRPn1H zte}WlKV~CT)vw;Dph99>&q1h~Up+lfAyq%-AyVD1-m}ILG0y@-YWUSlwJ4&x4+LuZ z)yujmpt=tPYWdasKV$)*??(TDzzz2Lk)rw!1Zw-$Ydt9`)qfyR$FJT7B$GlvjQ#_G zy7sb^Z||ni6A0btSMPtQh7u)b z){o~AiuJ4C{!t;>e<0MruYR*eg=GJMP(#1^trd|844tv0ml0^Bt&^%BTM%jNSFcPI zsfqgW4tNv4`u!~M9%lc6NK?PML!BaK{n(DsO@4JEN-ke?qB{_1X5TzLRPFcxk>-AN zg;35SD#uO)T4=MV&I5s2dCxsYQz`?39Dch;;C)i}4~gu`T}r z@90;L02xLz!#oywv|Zg^%V+KjGzF@PKLgj*jcV!$rE(0RWp2~n_TrC|7KKcFp15fb zJOqO{birNEiS(Ol=|-z?_mwC*ase{X)%+9HFKqPek7}JdfNUk=LmLfQ8F`}zRp5Elnf8`WKhV-jPTM_4l;JC#TJ!#9)xE2Fyr4lz6f+LrZ=*zc#c_Ntd)w2|_7J{P}Z*alN|66b}~!X7AE{XR5t zb0M{{3yOaH?FH@DCl=Ge2>;A16<1yCf}+(=(jr7ZR6-nwPf^k87fp!sLh57Z6RqB# zK-^pij-M(-s~^Rrh_xn-u=j~pk82}Dx4+Xua9~v_THPm4oEL(_s>;#oR2Xq{Avmn6 z60II6rHHi<99LD1R!8PqC2l-4Eum=Nt_yl4R&`ZY;v1|=T%qy0>6czB`cSLHk#%86 z?VC1eAlfGOh15T)CxBe-ydn}OL*gNDS9|q*sf@*Qj81O567*PWj^WAVfUAQZYr`>m zAl%hakG18PpJJW#SUZmSDArkzwdWXq(>37gqQ??AMh}R)Zq{QRI2J~+u6iu46$e8p z*v%1CCF7-Fq9dq^hJJk4)!h+PWkbKf>q>G2RpGcPnCu9u(s5BR#Sv7+LqEvt>Y;)j zd3wUAfVv6ZQ*pz%4ILUkZFiyW`Y#78KiWvE9u;nf!C5`zGgz)$A~N&y4OgV=R`tka z#OS>8*CRq0|*Z_qVJ531USU}(@a zSP!b|hhSLHHAD}p`iEe6&^1&KniUYyh@fkjBdTg3qQ0POxFc#SB!AE~!V$HVQXuFW z>4@5jDKhA~&5YVkb-6~V-Lc#zvZ=@+7Ind{3{|PLe(TcyhvUERd@fG!w^a3z{Z=mO z9aqe|AADmWcBE!Cs#QPV~~}*=8G?^_<4l!xt6;MLv6W}t=@A7 zw|dVwz182~$yaNLC$O#i7>^$Ba&FYv8$Z$#jvNMqTy67tQ%^r$?MM$+&}{7j;=Dd> zOS6>=C{F1IJZ9_m_8*kkTRbA-F&nivEwyh(Qolic2O3^V)@;xs1^j*_`bm%3kOgcj zeihwgHel@MP|4Df5O(cwn~hhv+lk*k_n3{=(*xz*DO25jEzr%qodH@$hqU0QJn*psqsQL2UEhD#_&C^Ok^arXWxK(U*ss3P_OBJ%} z54O8hff~j;hS{xs-+1x5*j_Vow6p`;U>J}-Q0vx;WVbdTC0!Qr1hdN#-Cf^4sY8-6 z53OauQ>+Jj4e6emJ`hpyf|!7(f&Sx?K3wgclx4eKDQ|CCZu0fzb~watT3YHeW_E_7OHvsO)9QzwlR2E<@w4CXcyJS zrpI+YTdlW#Be%GyW~~X=qJw5F`o>X<>Uh3&sUk59DhA#;E_^rg{iv@GpVZ4~x2>Gw ztmZn}9nvSOdwN<%qAaE?x7k)D?=I_5w#B&?&^|NAq_WAG&25Yo(3@MX9?v}~u8o_VnPJ(haa+@A61{^7O-!fB;-y!fQj6MKmPtiriZ?6ML^Gh3 z&>P#DypY`g1IHCwt%TH%HhZR+B{a2M2~BgW!Z3^*t)BngyzJ=I@Ot&N4G^dggQ}}> z=Fc{JX1GI=`lO|&bDNuK=2&9U>jpft9JsYCq`Mp#@7JKRo9)1D4LS()-0i@4H!R^f z4&2_LLqE@42Tl;L1@p|aFmC}GNzFH@V+$-W1KJj-_|SvL7GC&LAJ6D@RQ;y2XOX!D z7MI%s_qtVK8%C_P1#<7~@b+h8KD<-k0*&ljpq<(A-S6h^jcyzEEHyJMD3|{-opSL% zpi?gW2X)$3c6bk&)SaA&oxR!am+Jx1d5Hb*3Oyj&g$O)s1!xoC_qch-{D>aFO(X%i zV_sCb^6A+X)!VebZsz)8_5tBNq-cd84?MW(p^l0U$D!==g zmMd*f5~tSrCv#77yxgATgzGk5J;Qj#s(CwGe)iY4(f2>4r5@O9t9j<@c0500ozsT& z;dMT3W>-*N=QBFxig#A0T=CB7lw19IopPi9MW@{6f7K~B`QLQf!Jtz-p5Jwf%cpd5 z$8*7f;|w~jQaY34`AesGfj7~MI>pI(qJQfY0|}y+Oe!h`+MqmZ z;MZxq z+z$kFictye2O>=>%H0~)MVSGu+^eJ<7~Qz`*ZKfeD|d58T+!@+DwQku%5GJ}+QGrf zlJ2*^P#!Rz+bLm8^O>e!`@ucHZ}r zUiyKmwt8vpB^$Uy(v!JXHZ(H}#%0sUVzLy(D6X+i2iyMO?qk&7ESL zS?2NO%DlB(6|Yt&w|=nV)JxB89<8M=4p`MrvAwxdY=<&WN>#@h?ak~8%10RqI_1%G z2c7chxuZqpHWGERlSxJSSfl68WSPrELAAZc&hMr{qWI@wQ zMEko{;Tgsbt3)4t^H8<=m)`tMOFi(RtwcMRB|6X@k{ZvWQ=HN>vnwc<=wOR-EuvxA z5R-B(Ql&Ih541K*X_y|szJg0>xEat&X@2iIcYpcrJ8iV}&`PO;Dy7@ZQW{mRlrr3^ zKn&wftCZS)dnlyGn7i~NlE6$VrD5sG-FxDqo>@xsJt26#Uxs{HtY?9FHb$Krk4AYc zG^wLi-D3u{wVS@O-|I)l?b0tC$+a_=&j;=InkRzp^XLcdbv#QvYDI8BWUbwg_3wV| z#U^|7t438O7UpFeMnlV1ap==u@1LD8IR>aI{=^0SN}~%4afQllGzZ|J{cB|hmTVd{ zQood6sU$DAASXK}Yiwq*;R-c^mjBA+YKQLLP`yPAkd<&*fi_3D(Zrf#)~sdu4Ib?K zmp;cNN;{*}aEBU=Ebj|duTG77F>RCXEg4%_j0xaE@$-}HSlOLv<2;90_q z2G%T(Tv+63HvHuw`Yd?`BIy>EFT2vFnm68lbAG?bC}JnBKG*Ujn(s+erMk7_1FCJb2KuS zfl6bWW7PQ`7l(9B_`LiamCQLRYICSN=*rI#Fz4`Vb7Z}@z5aby*Lcd$5pT|cap6*T9-2DHtgZp16Uj1Y4UJQ8D@L)|=Feh%|V>538B9O`0U`8g_> z%ZS!m<-}g=*X>EKc&j!?rToHzT*K|PXXcsAsP7U^CVinB%_=D8(CVP-KD0SR9c&$s zI@r*qlCui$3e_r<7GjGHWL zo2mZnth~2t#sHaCv8FL1^C4aXLuQrmv8r$HXqMbkAE;H*R+ncBv-cM3=5|l}@a(^e z^o5McFU&;05@OH!!tvWD#x1+2t?tY&EE}DlgX>TB4zbIUBRk&z_Vk~+l`-LkAGkO-~6$Z1gUU+j_%RwbM#U(9s$7dE#ZkazRtL3D^;&JGfib`6J zA$y1Hmid{ZTjWg69AA{5Q_?c7MK0zpX^~x)nco7DmNc1xYp7%La`Lk?vWm*$T8h*9 z0}}ff15;xL_DOFY-zq7-RjXDpJzK{lwM=T(EGDTiJ0~}%AZAcO-sG5x@oj@~alux> z-UHJSDVkE8mpisJrb$-Qn79rd+O>#p6_*e*5E&?mNi8TTEiN0MQ&39ZvkHrg3X3yK zbF#6spmjpY2}P=`185Cn5=v`jP*_pbI+NPi#fVymgFR6XBQi)9V0NkI48H?m@y?erH1OW zBDzw_q0ge=#NB-9Ii+PqX?X>G$|j5D(Zv*>tEgP8{IZ|(7P(w$wCKKN<45Ndn~QL{ z`lCMECP$7ho19iyl2@8nSYYCRm+w0xOf*?r{;pdK?##~9YQ@x|vTS?VP0lNrXrG=~sMn&>368?1 zl0a#xJqb#yNS2n36oB-}EE#8a|~A28z}QiN+AhD&5|N zS>r^RFBIk8+2sh8FY-|?Z|QZ5TwfycaQy<#rzP9k-PCdgH2E6EalJaLFF0a>Skz&o0bqSazIO8 zEpm|O$bpQP&q2X|or6^(2M?9YL2Ho%TKZa%gF;6RWW0P1O8@H|JS%cgJ(%#OGqc zi~a`-Zq`{HL*Z%GDjPi^5 z6kCDX9r}litim!JuBu~j+*pqXg|D+nDrA{+y65yiTIKfe!5R^T{|t{8!z+>gfSk;1 zDl*D`BTCA3z`XRL8Omq<2bXK=bvqK#S@Oux-Zf6oEk9tu`rnE5AB>%Y+Mh)mML$}UD>p2uf|kI zsu4-F8b%VTQHaqI|KnPiaW#^JY8E~&Lpzix&1)$J{X;T~b28%FWwdG~|Fz7{nV6TA zlTlJugu#2MJjj@w-Eu58A03F~6=da?W#^d3DtR;#&zOv%cyKH&=6_`&R0jWx$(Kwi z$-<$DTmltcM-*m=L5H(ce3kTKEWi0_y~Qor_}}a466uX-6f-y(pIg0A$=*6QdLs+G z6;r&4o=Leh6_KWJ9@q@YdU?Gup>7Wrh?KffdS1_Y14#{!PfkAY@Z!byH+4rv{pGF{ zb@8t&b}x|f1dS*fi}bva zt-TTZ?a9$l63K0GBe`D5gTGIS@kX}E_eSK|O*9sO=_r}vW0LJ5+DRjH@){x9dm?o1 z8X?-PA#~vyA==*{bm|uj#DoReVCw8eOhhfhtCLXn0t7cz8s(FWetqJG@hP*YKq9 zo;Bc8pKkb4dB#d3vGUaEm1lG}RE+pyGgjnYh@gs58+y=;jd3rv#i&70PaxAQ9b->Z zjQ`EpoxLj0NHmux#>&@;iBarzVq$!GotPN;Ibu~XO&@9uHKCNxVNk`X8Q|os;5ksW z&Q$%YF;A>~=RkYjsp3~RV^as&V^s6&nz6|vDdwu^@`P8YUfF*`c*F2T-Ef}PjaS}; zckp-gck*_w*|lbBOaaDJ9uxX4NGIgoH9X;|F_=rHQ_)q)WlIZ>lej8-!imZhWqR|v zh0pKiUC_<{V7Ewg*X2zG;kpG6muTtuyVi7C@QBHEEPl11ur_9P!x!A;!fIA@-O~*v zA3;+UT?^?uYAX`*`^8E{!V~aE`s4ixHRK8q_LRfI9b#e2>vcfk3?-g_0mnoPtRL}rss94Wv38~Zo z^ZETZ<7?%%MrvhL*G?cf$(!h^P`zOks^%<|CZ%co-<_qLgN31X<0H>h(>EFdc7sya zp}GmxC8*}Fn!0M%stK#+s+y*1imK_UW~Q1H79l?QXqqw~baL`nF!RhDow^gFW&7#0 zXJOW$Iya=BG!myR^fMXO;d}YRetA$`{$N}l>Xtu5mIt8a4_xJ8p?Ns@Z;mtM!NdRL zuumS5{HNnI!#ti+2Os9qh&h<20#B@i{|2TSF6s}xi6tdD<8i!MY=qbH1p+Q=&ROvZ zlQT!>;juhSgt$UoKK!ByzB)eGIOZqB{maz~n4-RtK5qQVA*D~3Dd|JgwV^kODLGvq z-|2b=eJI`p+F4A=X}ZotcO}z@;%%TGi77eV5#Ixx35s{abVb{A4@}pxP4~ex-KR_+ z@(+YIw@uSc+~J}Fu%;u7 zgK7fm!Pt*F2=(!}ea3M$0rj{8j<{bmZDsMe=`cf0kv~doyKX>KE|su;^$}N{4^78m zT6I1&oq}oA+0gVjOsh_bre|VWeJY?F7h_s=J``VxY1OIG^h=mlofS=g?3jN)rd20K z@uQelogYpA>F|eOnW__|cun4xlqbqhWBjR3lHz?ZtvXSf&SZZ#_-UHD>F{QXY2u19eCPOX~KxeUd=M{xR1?N_9a^}yw7nLfT_eFsD3x&78h}&%8Ij zA7)P9e`3BE-;Xn=?#`m9@)AuvXDG%qE)AwJQQywlbr|*}D<1P-`wwHWw!H>fdPkTUKfhG)E(E zTe05H`V#9#)=Frs$odJ?h~e#kJE>qbJQz4&Qy3m>jJc%XE0{mZ{222;nE%cE5h{21*O4Nf z^`uDW0`o9*BEpL>U(0+m zZ4dCBr10-1g}*YDJEc!b>63ytqw)n8+W}l`2k`mKA0Y)_O$y$V${Bu9{@}OKH271@ zH<5zB!TdEUclc=tOq|MJ#PUcgvBP9PKQuvpU!oQFCG3Fk%FILewDcg9S89qr0@?Vg?}XTS@=$T87cmjlfwTc z^W)5aW_}0u8RWl{6l@kL{O>XUlKI!n`^HHB?WFK$lfwTL^G(d(VBQ@uN`D|J{6k6c zw}Sa|%wJ^w1ia+mNDBXEQp7GW4{IQ~pA`IgQpC0}-^%h57r;KVm+%iS$n;g?|Pq{O>Z~%lu2`FE*9_cS+%Y zj}(6IO_En91;2q5e0MX+zas@dLJHorx#XQl!Ml=zcWo_se^T&4q~Hb2XEC3{oDL4D zJS&mHUyT(0k<1I27c*bgUix1mg?}R{{1=(~6C{r&1#j00iu8Mt!rz+|{C?(Zm_N&W zUT5ilm=yk1r0^eQeu4Q#=HGXb{$EJpzd#Cq=bI((OA0=K6ue_s$$OK6r;&oMVE!EQ z7nwiQP5Rf8!oQ9b{$H7gBuXAm3VuH+)^`o_XPKX5eu?>2=8aRNzXK`K??Q@nW;1_~ z`NPZ~?3 z1#i|z@-C#{xGhld5owZ-Ck3BC3jb#2JDKlhej#1@!v;#fpA`Q7q{wF$^IYbC4w5`# zu=Gcg!kWYSuSAOcR3n9d81r$=3z@GNA^p#h!v7*E{J$~}87X-%-1qsGEw@UB!&MOQut3Z z|A)DIlH{jIk^W^;_>IYu_ap@$Mhbo#^OPx)4&%~+D*YQt;onRO z{}txZ(cOZp-7V~AymowjakMtiT zh5tKJ_+uAI-j{ea|ENWp86g5R=S@{y$Ax08ZD!~8YoZ!tgfi1c42h2OJM`g@ULyALM? zAI03aO7hyI;4!2~KbQFw=F^!seN6g0k;31V6#jY4A7;La`JN}G|1c^1$4KFCx<>L& zq?8URc_LGvI6#lu)S1^B+`6rvD|9evSkCMXQ z z-%bjD#JiH;Kni{%DR}?wl4p^E=aPcI!2BKN+nHZ@U;4v7kbXZY{QXJMUb2|yGOx5# z@&=?xzX>V)1Xe5o1n{gp}KA3=)cj%PlB`L@H7e@4M+*OMr0{qAN%G#L;Ay1b-HuB> zfE0W%DfnvU>zTj8{HYVtzljw7H%Q?(PD);h6ucTKc<3p~YmkE1CI!!8UdDV1^U$B! zPfC7L_(wA@Wj>kt2WO@K04e<6lEPo_oaC)Z!P}F9&;3>M6{O&gl7b&*{wwo8n7{P9 z^lv4Fe+Mc2{tJ@VAqB5T3V!Gh$0C#=c;2r2xlN#Q@r`~vff%wNUz9`b)c3jZ!r z_$zoMuTKizh!nguRPuSG;P;S%f6Dv^=07rT?UVi#QutFz;lGdh6U?7xJ`xuwC_e?H z@E4Q9{|57qnSaWBQIzzrCWZe=Qut3W|C{+g%zNX#43z#TQus%c!oQaJ8_eHk9)tiAJ6=@7|9Ds;V&VD|4rt*nSaK7Ydz`TM+*ObQuyoC zm%Jq@cxzJd*jUNil7e?21)s%y8S~}LV;iual>DUd&t$%o`9sW)HR0Nx`$2mocBh{NvWre~1+RA4uVE)JF0IQt-~C;7f2L0HyyVDfly_;6F3J!rYZ0 z`IZjSzlRk5eWdW$=qUM3q~JkP@RPWpM(JN71;0uPo`M?=hz}tJA3+NKVpqxEB?W(v z6g<3}ym;OB}qP;6nq{j_{Yo-G5>-2YFu2W<*p}%{}odB|7ITOA$bK-@ZCM3 z@P9`N{}EE~roANZL<-)O6nyEel0QWXzLpgHH1mI$yL(GMq@VQXk-|To6#h-jKV<$f z^Q!}-zhb)dS0#miBq{P)z`U6GQ-dYnM2hs^Acg-5^XMUxS0)Ab422?{s-*DOBn7{n zc`@^e%!dw>{yRwFFCc|~6Y~$5f6RQqaOuw`g?}t5{4X)z%6td&KW>x$aNIIQ{s1Zb z{YjC}Eath)AIX$_9Vz_lN#XyUdFW`#eWc*8XF-w9E>igSkb+mumb@`3cr#M)+j1o@ zBn2-arF59@V!nsDYn=2~CWXH`DW$`_ka-F7nDNpdPYQoKQuyy=ejoE?%y$$?|9(>V z50b)vBQ9Lidc~1~w`%;!y%{)b87UquT4QRWwzUu52F zs`Pgug+GxL{&~zFX10d?)|8i3J*E8S7{C(zomPr3$QuvRNQhx52Jdu?0Lkga-O!8Yu!TXYe=Q5wd zd^+=e%#SfY!94hYOs5+u(n%&oI=h*F$NUKMh7U@Ads6s2k-|UoA<37Lf|<}-S|TFrxGc6HB#`A%nO(oGjH^W^e2$Q-s4D&mfPkT)Adr6W0Qd0O2GC$4yJoBQ*rGGXl{PRfR-^2Vc^JC2CJ}LbxNa25! z6#k>kFEGEz{K^{XkA6z}E0e-Mf)x25&wK*&I!{a9k`(E;CWU_*^Lv>uWxn(o>3@n8 z{c|B63(~uN?&%Y$EN(x?+6g-o83G+$Jn?5J~ zok-#DN(%pc=8rI6%{=UR>90u&e;rczbC^$JK8^We=8rL7!+aC-51D_={72@0GQY&U z`Z~GXrleSI3sNjMiTNPr!6IOFyGJoAoD+%hrcM78z9AUn~-9;9hu+Ed^q!b=0(gG zGk=Wv8s_gX|BU$;%+E7-za*C%N{Z#yC&hBxFi&89EA!i!XELA8d*aFml485pCq;fbGVjeijrj!TcQc>Q{88pFGT*@b1Lg;qf6Kf%x?)dV zoQEZ?f$O(C-J7Sgd3r2Q&*JGhJiUsipWx}&c^an|MS5TG^Z}ke&(ksj-Tz&;o zEWZg)H|J>#&qe-{d3q>MkK}0#FGPGYPh)o~rm-6n>4nmAYRP*y#r<5o+!)p-tZMxe zc)A;_C=cW-ji-mQ-p;DZrHH2|v#RAH8`t|d-tW>NsR4esi~f%n|F;(Zw-Nuh75}#r z|F;+aCy4($i2w0!RWY-iJ5J6XC+Clo3B<`1@Ma0&lxf7tMB-#B_%S!JaLz-#5iHG_ zTxtZfb4HitX5!t z%+Je&n?kbg$@*qZ%S>C-yhaw_N@)SJ%2~*)c0pQlP8PjBB`9Bk5yUErjFyb$Z`W(W zcQzJHDBx9E~CAgu<3k!w-G87;S0IqGP+a1_MyrD2X-?Y8~^|S literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.d b/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.d new file mode 100644 index 0000000..e95fabb --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.d @@ -0,0 +1,201 @@ +# FIXED + +F2837xD_SysCtrl.obj: ../F2837xD_SysCtrl.c +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_device.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/assert.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdarg.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h +F2837xD_SysCtrl.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stddef.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_adc.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_analogsubsys.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cla.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clb.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clbxbar.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cmpss.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cputimer.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dac.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dcsm.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dma.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ecap.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_emif.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm_xbar.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_eqep.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_flash.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_gpio.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_i2c.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_input_xbar.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ipc.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_mcbsp.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_memconfig.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_nmiintrupt.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_otp.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_output_xbar.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_piectrl.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_pievect.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sci.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sdfm.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_spi.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sysctrl.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_upp.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xbar.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xint.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_can.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Examples.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_GlobalPrototypes.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_cputimervars.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Cla_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_EPwm_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Adc_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Emif_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Gpio_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_I2c_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Ipc_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Pie_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Dma_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_SysCtrl_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Upp_defines.h +F2837xD_SysCtrl.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_defaultisr.h + +../F2837xD_SysCtrl.c: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_device.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/assert.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdarg.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stddef.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_adc.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_analogsubsys.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cla.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clb.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clbxbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cmpss.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cputimer.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dac.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dcsm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dma.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ecap.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_emif.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_eqep.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_flash.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_gpio.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_i2c.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_input_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ipc.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_mcbsp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_memconfig.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_nmiintrupt.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_otp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_output_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_piectrl.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_pievect.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sci.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sdfm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_spi.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sysctrl.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_upp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xint.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_can.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Examples.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_GlobalPrototypes.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_cputimervars.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Cla_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_EPwm_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Adc_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Emif_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Gpio_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_I2c_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Ipc_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Pie_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Dma_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_SysCtrl_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Upp_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_defaultisr.h: + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.obj b/gpio_bitfield_cpu1/CPU1_RAM/F2837xD_SysCtrl.obj new file mode 100644 index 0000000000000000000000000000000000000000..f59b5ef3557c8acda68e43bc50065ae49f306829 GIT binary patch literal 88864 zcmdpfXLwab7w(*0PD12FdX*5W6giL(AaqhmAdM87ND?4GG!RHa6+r<7K@>wTB2pAY z1Qf*r0*Zo)g(5bvfQSfUK?N1bUDNm4Cw|ZUaev+Kdt%7DX4and&YIq4C8Q*JJRTzd z=OK%T{)>=4+5E345)MIHkvm9R(q}RuO(z#t(BF;WC-~?A@^(c~9{qP`ubD^j29rIj z$w|*Awbt-(hbPZA#`K~RFT|xGn>O&kj|D%$@KX(b!bvm0ngP}vem8Gmke2YfCHrl` z?_l_;20!8O(+7U;hacjB9|L|Y_z7+W;afrYR-mI5gl`4mTS53XfVTm>4d8zGw;%r9 z0e*L2zb*J3Od{d$NccMv!bHKpqu}42;df{F9Sy&u;dfW~-3@+vupa|{TksQ1dcohl zK;8@f?#2GD2EW7Mrw{zx4=j0z31LhKV?vk)z#ip+7>tRq=3yl_vx)-9|@Sg$Y|(+HE{?P6o~mR3WD62Kul%FV?_=CwR2B}~R7DhBSpGB17>8bNMF8xV6KPi zN}nGLU)>t|^sTk?GUnGRpT+)tYuo`Zq88xhzyZM-?`;jO6;`L*v)GgQZ(d#q4RvK~W_j<-;C#>8rXL)r=)HK$ zdrg;ni}k;$j;7^V%UhRcFK<(xv%Kl#Hf`Mu22bwL{f+X0%bT{{Kd^NxmL|wu_I1c% z`gQL0O(*A;dosVNXwA5*bJQRQDm-|?+Lxmoy(<&dd-0;SSdCLbc4=NwB zoccr$$hEtc_c$6&-mDl72n{t9LM1||J0a9Cj)DJsy0@<&-xy)udZfYvpR^i~`{Acg zonofv==BOuMvvvS)n5ku6{`L+;V+s)zd{cE2|4sVZ zQvP?i`psh2`?-SQ@^`vDj{TkfSCKnDPd!D6nG`mt+*%&*HNpm$dzTL>4_bZ~c!Gxn zE$;Eb^@=U;^;kX}SeaeXkEi?A2e*&pjrppKR zF~(JEJut=?7vA~^_$G~&S*|_4!Q?GB3oCYD(-PHfhYtlZ3mzFDMKu>EXE zN$KQK5ya!Sx1IQ@NzTILNsWS&)3VdE;v%v$lT(SuXcq3bpNq7XOgZoCw_V60rL3vn z-u_HQldPN7HuVmssv>EO=6?J6FOnC%^69yEcLir>rDersr%=45-`-KH9qq1&(`=y1i zEc$N7!gGrpvUn=%;kRFoo|o`_Ql01SBG9{5Jnw&cQsk6AwYIeeNby`xvR^wKV6q#2 zM7A6ce|qxnJ<~%du7Zc|fxjF^0z z!I_8=hwpDVrrJPrFHZM%quv9HQ!!9-obQ%Xnd$OBQ7!iMnAu3Z?>VJDH76xo89vmqlPN%|1c7~b zssxLy4W?EP(`X_K>!ogRmqtZ~Lz809s|1LPQTrO&73y+;dz65Xp*mFqUV3^isYS-4R8^yegBLZLDq-_@WplC1=0^4eOPWW> zAG$C1;{D&gHE8zV1xUN^Is^buj!W!Ijntlh!L$L+%8aAsft&t=sS3CfMRNNuRwC+1 zeAG*R)FS99iULNeQqiSKM3LkcD!N>Ws3QrXqMzI%?x$3AMT z{{-kbiniiw1rstzfB5b(>pxxh)5ekKsg-vIbP3K%THL$-kW%3C*uT{T) zxbEjgvtEips(n8Q)x1VRun9a4~kEMeta@72e!sVMH>Rn;Z>-sq7704RMB=kl(GEN+hom*U$PMBTQl9Um031||&_v77X&SrNS(-*1tU2*alsd&7V^(g|WtfrD~$H4$6 zmgQ~=sY;uh>PQwVWg%2nL(6!X52k2Mj6#{GXf2FF14Wyy+6r|QwK__G*tC-0Tz>k+ z#1dpKW;0THWqrkFg8()gT9PmN(DBuqcpO)GO|U0ku5E04DC98uV0A;mCN8N_se%F$f zU=a5NfGxlMo;C50*N#tUHMc*FBO5!A1^eyyEm<_QjLk-b`0b;X%xEoRa}QPh_6L^a zC&fzD9B{h`&W-q4Cg37MN&GMKt*e)}Vx3?7BGHxQ+k-~QOz_wLmAlch^u5bB^4 zK#i*7w~twCD*8<+Trsv$kfXH&Sv|jf+>*UX_9d3M27dd5{*t3*gD7Es`=lj1T|%As z63o|pV#%%vO$1OST0MveGd8EJr!vm&{bOTU1dWKKFmv;%CA;)NsNI9OFn{xzHEPhM z%cFxDj0qCXs#Ul0+n-xoJ{mWy|Muo{nHg--rj6hJ!jjWLL84&i6X}g9b;$rDanXrhd*?JL=R-o?N4O5}J#-{jR>> z{`Taqt9UL(dL^HWxfhC@aM!rE&TQIz%IJdKbtVLe%gBk$OrVohs!SG`HXsSvyhAlw zHEXgs-U`KWj6zWxI99=^Fz#4#vCpdU;V+=i^TMbI$<=9j~O~+G@g4z7mady0j_FCE7a9`byWg1iIVmBz0a>2 z`lzdkrrl*u4j3TV>7j~CPgild&F*DNA_!@ui_6?GlUmkTb_EYxec`IOMCi^=3=FVR zGqSQofr(YA<*+C*aV}UCnRpj0%1nX_7KJ9!1&dPC*9D7WljMR$xk=WrU_Thx@25}~ z`~8&wvH$A9jd7d1Eb$@tspeo`b&t{%`{@DfXPA;`LYipy_jb8^ce6eniji_(bIpE~ zs;#n2QRT9Uootm@h6?U;Fe<1Yh*81(AdEs0rM@{>p=NxHC<%1h+#Z4jtS~UaP%L2O zfeG%^0!n{pS|pfY7#4J)UuJ^4lmO*GlaERo{#M0&36bQ?fhg(!c`66;19D)5Daj_J zmd=4)ug0|ba{u4`kaAyLodYTZUWeu)E+#{G|6Wy*F;ry0K8%VCcmty%1NLK7c>V#5 z3dcXFQSQpDxp)(!k-WKh3!@$B3P)A@kV2W;>mm5tN`PwQ59{A|`oM^(CgR0WBda>+ zh^mp_4XBadGbFu)>?NwUuRm+Zs&gxTScG)@_Co+(q3J5;1K@l>g5>-|l~jfb&OgGa z;QV8aa>m&F%`uF^^fh(*;|gWm0Apele?kcmH`B`_fB(4A=zNrZ2REulIHkDxG=Q7W z3`qn1oZ@EJ)xkrTzII_K((S9M{83j3UmA8+yzs`;DxrW0Ue0KYGr)%PUtu(omddL3 z*BI@{yDr~gG>Ug!zQt%K-gP;P(azi#&tVjbI`zfx6w3IHR(zjV0>t;HTXt-GAo%yK zh!Y3js{H?;_`Vpx_m7687Wv}gXHIxt%qh!6x*fjQNtOSffbY0u**UnPlFCrgIrtf) zqI2*IMn&h~SB>)gVZQjALS4<%RV6^&Ji7FYD&q&w?vB#$;HHzT8~;??Tnpglx*=&G zgwAw`URl(FPp5n~bm0}G+xII3;N`Tl;^rUVCPQ&^LnW1=f}4LaD!93+QAatgz^Evv zM70m1oI+E`8V(N@MA4oa6Bt+kja(=fm`Z@ytRG|S**$h%HnP~kW@pK!SG6=ju9l{u z9c)VC2zgVpd3VqH@6_HfaU0U@dt0&DMX`B{X(vajZfI4NRE7#ReHsT=&gWQBvFE|Q^IilN#84An6u8K^9-nfcRu zr85fVA>EF$7_Atp4_(oiG+7oKsH8GfFw{_^j{5I5jEefN5k{c}pzT7KLK&O7&1|d$ zh?{;BM$Q<1z3gL@eg`+vlAETAn`QyrG&dy;ge(Q;5M}YVNk?9LYU`#~k#64#2*Ar? zSH;ckrky%6HY-E2(@G^);DVpl8h3b58-=>+pSDVXY(7(e=gMIz-#>}c<*>P{wArt0 zZXaNC2UD6y$lH2eExq~vMbo3t)<(L0N9ep74CRNwMiA%v&o`ExlpGtIo}QhW9-qL6 zaNnx=Ksz}d<}tG2KQZy~nbiHO+Gn*iBROGULS`nDv3ByDLq=!kGCS~=@;f&k!Q0C7 zZak8=mfySaj=a6R;KrkPi}`~a@5G1u7u|SgKHmS)jd$S#{!4B=nveJ|yYa4sjro6a z<1nGXhW%Fp1h83(viEa<0IF#!_(ciK3`SiDp_Yo(SSjIbJDIy+imMN@zKR-#xh~e-lc7JoqHM2SV}WkfhQ@ZvaiN>4~0JY z>!#O{eZF)E0QTiVO~B2Y9c-`gR&mq~be4UkSF*1s(qVpml~+xqJ8KO{wAXL1_R6`X zAY5&L7$(}+c&DW89KYt1);)rp^#%xGrhToqX32|}BK!l3^o%)7vOnP^Wz}+CnG|tv z5HA!RC_yk6z0N!Bjy`2;_wBhT1dL*shJMmJ^4{DH%~!quqY$vkcbI`*?>*o8iCZIQaKkN6>${AH=?H7V*Dv0#kPkVnG>VN3d{xfz9L02k> z^4rgNOXIF?yIJccX*bj>Ac4J#Tf9&Fe(>hbU*69XQ6iY-uv2lXcW%Q4U%&E0ykAO~ z>99}nS#RTLV`;DZi!MtEvmJIRZu5?Ptt6(}!VR^hgc;upwr+aAy5p^!q>Gai^o)ET z*tO|4K7v^v3p+QxC%4>r%fn-a=CcT$XnNye9Z`B#H@B?Ite*uCjJ7aU%@^!T_3Un zkx%vMUgx3spzPGlNLq*T?V~eb7pM37_MjUp^T#h>iDPM=2^%=IHFN@>c+6(^gY&=a z{qE$Y^^diA0s5hBb$!v{hr7#Od}Nvz7e86bc=4mF;i7tZdO+2g)1wZzN5wCct|-LE z>FM-hZ&q?z-;{*hIA~;f^E*M-5?)bF($#{A5@b8epv@42?GlL-GC+U(mkX)KOf+6kfa3&NmoAz7Yp4$t}kDfQ95dVE}jwy2iJ z*$=PnkqLD6!|Q0&(Tl39P**>^9v0|+czrC0QvL7-NoKh zGZO?cjXZL?Jj^4h;k(W1*^NDt20~udii1YH>dCO4yNne3=Gw8J4=tFDTlZUOvs_ed%T9L7{7s{N6g z7at$dItVHDL8DK-Mz8Sq^4OCy)X1c_N~D*R+SenELgiyb|7l+|tGNAlq*#^@Jv-OW<6KJWuM+88 zN=m_~m=Q_EsF*EE)2Q$mIzmlXsB5&Ap#+GPte+QnJ2x1$5hY%-qNdTZ6f4;QtmJqk z0ff}o)0Rh{9eL`Z7dBr-ihZ|10LXtmhc*~$4aXAF5S2=_gf!Fziz(eZU9gx(ALfF^ zMEYGWSj?mkcfn!_Dc1#yC8RtJ3)boUWxhgPtdCFv#QMH|yX#*&*|#wwN3yOa=n53; zqXSqU-|IfU;euvo$Jwm+rQkqfnRc&Q$`$;G&vyPCW4X z#oLjg(s$K_);z`F`~U_Y_DHf2gRA}~Wqs~gnTQli2K8*#Bb>oV-l1Hi63G}8D;i`V*Bk^wN11MWoGU>#sDK(t^bXWPC^V=T)jz4uy;e>;lqF(N zp?Zn)<)GqW*>jeIiUpE+LLS%IajnLzYiYAXeMqTqDa(#XJ*ZggvHNCq;Q8=`@)*EG zb+FEf30Hp7iFM?>uXkcm+>M`dVx71XZ*XFrc`j^pVqN&e<0dB-%_kiQ7 z4CdMPqGu2o!KWIxATW~8Gj2s-M?S~+ECONRPBVWS0wGH&_?!Y+;fqiiyt9Sx| zq8F!6uF(&PKAb+YMnTboQwP@A*G2#BDWp^EoZEmvxp8hIM#a9lO&As1<~A#oXBwM9 ze;R>e)7&!%6no~jAP{OW>e*W*=&He?u0}W8Wu8Cp&hs5I zd+AwO<WAg6~l z%|{Rj18Le#e^-Kx2|bQ}PvVG)Lw5M?S3>^5Q-6X9HFEhtGV!6CiI1ew)W;PQhvMw3 zzwP{`2+SJF@kTKg?`PgZRBWAtky~8@0W8Oq02xiqbgRdpC-?*9mR+5OA zEy*F{{<+T^iIfUv^?2|*ui7|tUZxEo!Rz-5;(W2;$OQz7zVr_W6q|-FB2erZ`VoO* z%g`kRiXB6j5hykc{UkxgtllqlMdFCr_-{^TjQMOGd_PSkmmy{z5hs%F#$zd z)MGa!PDmC}1#MN!UjF(E^V*_BS04xg;^WlVtwK%_6Ib7-E_Cgr*@XP4)s9*IK-%(; z*FJ&N`hH?+^~lZgIQInEs(a!NtQ9@TTU8ITS^$gHJ(4hbsglZ^B@d6e#h2f` z71A5}39ALOQges0fk+l<8f@(kfj?4`)B0zm!x6j$Sa0=P2Rs$^KX_u@sq?`gOV7@L zB`JAxh~c*m`VT&MqhRmvr>T@~iHOV2WEYTFe(TLUs#h=jy7!I_ROZkM+aKskm)CE- zC5wb!@(uP|ht|BZ@`I3#f2YuRaapNw+>tHiRr6bKs|ZTO*0O5&t#<-NY%#Bv-#Q#9 zVyk&|{MHdAq7J|!)bm@a>0&8hsjcs~-g|Z9jQ+c~KX9F*eKTWXfr@M=3F&DmLsZ-_zxBcTPpr^aA5L%Xkjv=d ze(S^2zb{=+Ru5WZvj`(wSe>3-0uM`Q(h3dvsj=eh>%)++djJlR4-9x-|P_Ar-s);4aU!ejhIB zdijHER9LAa3|GF)78_Zff+ys9q$|*v*cI}06eW|skY9<6&ADD*UG@zr1RXZ!Xbr$~(qn$~<=!Y1q#GVi%lyrrF@)#eAD zJ~{e0?tX^8L!BaFpgbq2CU`p2i5j+hg`EuOB3l9hi)n>u7c6ELy1HO7xzNo8i}{7_ zE?7)4^l-sqmZ7H$784DZfrH!fx$ z5)>|4Uphuhl%T8i?JIF~ZlPD#rPFWD-MR{uZFc#IGaE$%(ognB`pc?M+#O`6NOvHl zMv!VfjGzfsUhQx+0x7?xHUt3W`pl`{6Kt28RU99LYQtV)%CzZn4SQmin(}I?pp2Nz z?BsaXWWa`(W#+hngO^=td}*5yu-!ed*=4zT$0L8NxO68u5tNxQFq!Qmg3T@~)DAzU zpOtYqOuEuk`%Pfu0BvmGDCsIwF7XG!)Hwxfzy=&sPSF7kdQ)~G0c1N|;6&+D zrtD1t$ac5D=A8|u>>U8ececRJosFhkou??X3AXKQGUe(tMVV2sXJ@l1*JLTmtb*gB zPn&Z6lA_Ek*st@9DcA2P%It#8I$KP+zQo98DqyS5RwvmJ%rw}i^Q)q!(mm z9&DR2>+hV?-naKkAq&q^Jpwk(n8SZb{A*C}=o3MSPt?gLAlq$L zdv{IEjWzdwtYkpF+3X>Zy=3<8`_us6ikD9-8L($In-8*=%~}bcjkx``&j%_Qm})j# z0J1&igz}IF&erQamL(CmHJd#G_$!)nnMO#y+3Zn}y=o4qaWubZU7adQAB(pbWUrYY z^)6o$cPs)}>Msq&d|3(x`2aB^D z@O^>lpk8P;TM5E9%)9=bKe$!-{=F;`Q??rL{gp&wY^(+00rS;^t)7b?@J_T!1@%g^ z**Xv&G^;OL`rX5SeDW^SNQ;5lY&{6xtVAUvWCIA_GD(a3qDTHcd?Am;61WKjhs=?0 zz1j59iVbFvY}i2GDUiHv%5$PZ!s2`el6OpbUP(w;9)AIn!=^l~!#~3Wr$KN;CysxH z+4B`h-ZkZc6QK-z)@=3-NZvE$aSI_~)|>^&`=&fPAS5hvzXQopQ*N0T5|&NhgX9BK zZWtF5mKQ&O<#tLBMj`S2qMK5{3T=j&w>X@a! zfZ%w5IwtxJL?=vn?2gA_9Q+P~lV%;e>8R(U54}OZBaVyHFKvJpDlzH#?8+|iP4CGTiWhaR}t2e#|?4nc3Fe)|n- zL__a`010t%xe0J_2W)2(ml7JAyc{4^El*X$Jq1ih=Z2aB#{C0B%>tvX^R;j8kN@#f z(yi$0)#;&U$JcrHz<5@44~%WNdk|(kCygLvBt#XK&HG?Wys>C_Cej@`n(EHX%!L~T zlv!VU1w!W%sv6(Ot_(9lt*;p0N*pb(Y!1Ea_n+IhKZ-t6o$f-DpAqT*PNx4nPJct= zdzn;1o`HBW{U7c+{qK8!xOOx@D-^>hI4&hqnNVSiormgF?JKXYb^q!4;>sBu6VA$FkB`*e(h3Z(I~hh!u`aJt}Z zys0F7pb2PI<1GnV@^eX4Io-ly98xkGp(9*2&T%z!&*HF8B+*Z>NNNV3F&jldz;HE* zkIGnlzvCr?udhCVtXE}>+A3&$Pty86rnRAQR5D0N1+XT{*rA>Ki#}a^GXp7xEr*;| zT1Dq*W_NfKW0F&HI{;I3m}%^khI1TdlDI4FQn++9xXFh`ctHt-kHJMghFU(dg!Uw= zosppyk+>)#H;I0LiPTb(CBKnGzrkc`MM-+CkK=pf=Lu=3N7}U~d~#{Tjc(I11!0&1 zXI1l&q9GSxPQ}MkwW5N_Sjjr3WHPBKOvorXu7nOs)KZ6{M1G0cr&c`_E%IYbtQJ5t zHS&8*t`{hJ@8BHflZCml4(?F zR5@~fX#Llc!m)nV0&4w2_iIx3>sWV~u~#}WA;pk1;oUh!HOw>rgiS=cLrX;3vy)%| zk(8dIE=@HqvZ_Pjyfswo7K|?48mgrW)Dql1#eDGK$H#7>PgWlu@JV6O6=~7W*rF!J zFEa7y9?)G!M!dVC?y*ZqJ-Y`qk)B)2&4%-BswKEZ?)jtFXc>BH8}^^Z!&ESom#T(O zHE1S9b*&bv1)?4d;ic$SB|wJvSke2)v3}-@C}pe(bfipJT|+g2H3OQ!S{`X5x~?zk z)ZQK=(=MMv>O-djuZgj6Nrmj7#d-(Q(|uXlaLx&=(=$GzbWu=E_elTe>nDbq?t#Y# zK(Fwj^*8>SzIVgi&(Vjg=g1EWi;`qMCgXgpXY`XPCxo7s5L!dN>G@#$%!&t))=+x? zQetdkOiBva)L$8u>WzhY|3Ps4kX~79q{(tBPgKyBI$eS;qcS9p3f(Qi7x$bwa`{2@ zdDc=pJ}*qmlBQ*2)544#X$2vVLdu0{GyBZDdbV2o4oG+CkDHUdUs98f5n30o8W3!DC#+?#&SvySPX!T~nnnwzwYOnkXrKmbxy-AE^DH4|E zN=x&wr45XHX%yN9e*a4s8Vqc|*{kDyI(@1__VQ_`F5pOoSV=YXkqXolZfkR> zY;=_&gD_>ZDRdeoNQ+jab#;-}*y!ew{1D<8iq87-z9E}iw)_L>_tBv!(~s)*y3C(= zEvF9@N$Y4e=Q>RkDc6Y&=V_v$pj>2G?JhAr?yLTDee`wh5bW#1Hg%-Pa33jZWHk0j zGYDy_ds$tVHaWkh-^aL@RkZ~KNKA>zO5%kD)Mt^|o?v4|NMdF@j8I|n*>9|D^i9;5 zcZ#pg)Ju_u-&i$n;~QuF3+4v}(*}S}G=}+&)v~q*P*$T<6z(_H$T|;1tRexpsoz*D zD~I63j2J%m+}v+Gabs7zpe0qBu4bQvNfdhRpRrCJ7Y$Anvlm9QHh$yDl1B5)GdJ!qSj}%FdgQzX6X-r4 z#H-;q`g&wXj)`gZ!9W>gwfshsM-FtQj1B`pR>yB7d*oC=P$I3Ll30yTh4uVKKW!ls zrYK6C!;XEGL|KyH444hXu?jy~rCHlAR z3C51gYEo7k(8fL&?m~{qNP>f;+=q=|BiB=fbpsLxd0SUb16njYIcnp<5hyvKM`-253c6~=Cy2fY8~&<8tlo^QoU9Dq zKB*I|-UJ4+L0+kB=e+~dQ}~o9-JEBXDLjsPF5AFuOj2NS+CcCjwuRf6tk8_UscZ+g zF-1WMna}`Ig;Nz23zuW?wr`rkct4(A7H&*eV8TGQecQNKAv9P=wtd@}p}>s31KH+n zL!SYl;iA~)Z37aHnWasTufY20u{13pG8VY zZHF#89n7fB|E^Js+W(IR)UtzslE`KfP=`Y1bh%_;31*;)u~Zt1TzbppS%0Pfe1A=( z-p7V%d@WYmZodu3SW{@n{1zMbKfI$m<`iRxqz-FLm`jhD9Z@JAk=XAl0UDIbHD8n> zc8!o&9TukAM`hRA{y;TVd!1Mo4c{<@Y0F2R-uJyzY4GrY{x(IPPUo7Ps`; z6c#6RZuiQ}WT@Co(+ZIPXh|mDoom?<%v!rlm1)G#*xN}1^0(KXd zq>F3@>}Z!HT2A)bU0sr{unNa2PP-eH!0rWkB~W*lgq@b8m95>wC5fa>EtB+gNnoB| zNP4*>QMBDtllIx1MTpnOcCuIQDDJ23(cwk3vEAP*OCur4x`+}j_SZVXZ9c$9KjFR4R*nitdC|7alyQo zW)F42QT&+Qoi4Z&KWI111;bi9HU2Ia+=Um`;RsXg0S{2qp zm!zvItaoEc=MJi{-s6%)sKQ$0lEA!!D3aq`66iMx$#^9}g;ic2^uG$LI^{Z171ok~ z!dmK;<&uz}ANs4U;jlGxV-y`E`Cel{r%}Au=;$=U#IQ`8e5MnnjqSN~rj1urUfFT3Sx0JOkdU z*zzN+D+p~3Ure%1TU$aG$%K2!yVcOgs^tfKOtdy$Tedbq>O;J>X<`T4GUbHy*HdRh z&R4y3=ZuSQqc4P}K>&J$LR#S+>=^KS@d^b$D&^HH6x5OV88ok2pYY0uUugs5Rm&4h zEAIw+?~)8KkoN+;!x6|kf!n&88S>3@} zLE0dA@5Tbw4l=<#Sio9BCMd!J))q3sI4oeTArp+30<=mfU+G2e#8wHJJBczkQI@$9 zSseHV?|R-+>5qia`F>FhwlDect-fK8Hbh!|_d@{wfQ)ogdn3H|2T!fBCvNzoNt-O0 zPPryPA5Ge_*{R^%^l2wL^J?!<-pX(~{Z40H?41~=kI}LI z{w|F}-$cD#_kxDG)6fl^_KOO2m66>_fO1*B(u4`3xy+3axx7aekyl(rq`v*CC7B>( zwWg=tLl1p2tHzN%NOR~D5P%=eNKyoibWFzCqh#*FUZm9I6i5j@nXD^o8aXYUE*;Ve z%^od-TW~@oIS%e_gemx}TsX)9@mL5|SEIQ(dFlhDj?K-<)CtS)7PX#z53cnZ+C|br zAXLxBpS#fW=iy@;zl#)y4uJsTM2a#yU6{?DiBmfr7zpDB>gofeaSRl1ab_xz)*^Jj zUR66wVHwG3aD8PCJh)}Uwi!EH38;@mv3YSj2Z5dVcx#{nlhdFK!e#hruxJ7*1}Onm z!6(A)!4kCiT3uH1&;*qys;9vkb(jL+bHTRiY*?I%+{EP_N)Zg(->4|>^fs{8F&3aiMSH0L7+q&@^7dmypo6RXjS_* zg_=p3aH)tI={C{=8eCu48Kwo<>T{5N`qKUF zDy@^rX~lHop4vb(LIv_2*uV zbB2Jps`fsGimN~6wCEdJK!dY^2lJKvSODyaW9$c%0P!TRR7R#ac~VmXZz-M*1@QE? zEh&M!uQX3nW{t|2k}QP{phIeK5A%rn4Zarwbf zB|sL-tD^tYVs$yvN6O-l11vsfOXEnMd#YG68VpLoV@tH=22hno#xk6oCmoJn6u_Ld`{!ez)H9}_;J6{E`^R+FBKo?Us ze=xZ`s!r95NIAQhQWQ#kozPjRRUB7>o>QqsSAu@$g2jC==UuS4^5uIMEG`zh;DW`~ zLO-}*aiP>j7c8!n`ccDzecHpiq)-?8mz4mqFRvs=1UXBix@PES#r`h=?Eh*@q6u-l zD);G%j}Mo>x^pp7&R&%h?CVQ*ez!%rV{P&uDzOaZvmExH7!}lC!>C~XI!0mDhx+DU z3Uyr#`ZpG^!oX^`f3QHetT(iP(yy-u{TB;h&@LL)n@WIkK;H3=NOIGgc(HIpD*A=6pq<6!pDCpfWD$02ejEZ936QknlxLz2A z88o`1#_sKc#pQ8*T(G!3E=I#VJK6Pdu^1Ki$Hie3HW@)Ze`X%2@_&1151h<*VM(chMNkDgV`^=8Z|wvTQ=y4kae+#z)9mLAu#fZk%s@8QuNBw|-Xf0hLtevx>7ZDtgCrFe-Y-b2ZBIhxy`z3T51Y zhl;xKAtgZE$Y*X)`W@v|-6Qv~;$}erHw$e^1A10*!P@U?H5=Zx0O@AWDspc0b#jja zH~Lw{$5c|CSEwzJg+7iIfR$G!m$PYx- zeKp&EUcKjcNz0IK-z5l;k&wyPjo|o^>XANdvA&pCP-2S)3)Jkl7%jlr`KtCpjj}GR zh{5jHd_>DAk7Dj^kw$3@`m#}c@<6_K=20!9F`%`86;Asxg)-)K`?^>O2)Rq!I%?3R z%cFxDj6t?m%X8Z*W`vfgdHJQTdHHaAnI(CnH;gMX|GDYyws7|KO!NU?6*}7qWWu#K zipQ743n01rIl`CK=0`sE=OQ-oxd)5lxQMkauV7I;7qN!-RV@Uy!$OGv42K20$_ zhsh6M$dnt|9-E!mNFS62M-h^e;VcAH4n~f08c}7?DLiAKLQS|nQZ~ZIAO)k1O!9aK zN(j#yM?$!j2HcOBUsME3w#J<FQk_gaG13BA&0XJU)RhkHh!)%JM|D zbj_B{MW*pXxpoN_@+<<4Y=2`_yYxTA;@y@qE#_IyI;E2oiYiulQ4*%+PKO1Q9awdr zs#e{nDNVdKYG_Y4B@u*_Yj&P!SYkmMUTH0p$z_ zl^SktJ^M|sv`mc2WhSFkwKuMcc239#b?_p{&5d;7<%? zZdC&0PV#X|!~tukB?qFg)lmG_bQQLSb}g@@l8|?RVo}(drFXvb;}*XRM7n+NLI8P@ zonHMt25*1SmuU17@Nre`i#CGQrYAH?cdzj9tVTVlC6s+J$o>SQP_5BE&?$wwI*y+z z0Xh;dZxBS5uoKYQ62a3KvZb-VbhR{%?9(1e2_cjQ!PCS0eQ$?;{*7xr~T(|Ue6v*Fq~^^6IFtpYilJK z6(i(QjEdQVGK~sOsWVMdD03z~doWoE5JU2^L}UWH55-}EU}&0RXnFuc_ZpH6LK^E@ zZGYjYTa$yExO&I*z`ath=lW(EXnk##N-AnYCu$W_=?SjQ5>l_y>W?ARD zU@`ChpbHig?+G6w^1V5pb@veXCL7dbC14t5BEgol^qTlF0jJQL0c& zqH4$QRZDUqpe6aiBh4e^MeTV<+JAig;E2T=k#^t94$sqTZI{4iz1DVFCD*yu_7g^h z<6Xh1aJ-)}DoXt?7!`&7SB#1>{~Ja{k-v&jvDWrGM&(-DA1+v|wf*UW#ai1n4f8Bz zYi-vtD%RTm!l+nl`x~P$14YMD|0t9>gpc( zXso%qG&b+Ku!p}u+Id{K$)}kp+k!)l4>4{DcSa)5MTez$NwCFUL)svhm2H&%1^PwHRzCbgVCsn^~*1Lu0}t&2*o zbL}k}qoViR6{Di}+)blAkJwPGyFwX1y7$~e2@pT>GW7rEN3Fi~R{Zn{;3vkAR1oqD z6iG1@>-o%;J>43e@jrwb*{f9VpQW2k-{jEP1==HZ0B|wbIE98;QsFbS}xOBy6MgXG&3`rg#hcu&WUOQ8#=|8Vs zMcRFI7p-Jeufb&-&Na9km0af<+(3;AFQVPBK?)UKBv~4a1$qr`2o^wFA!as*Dgk0i zUZ#)iKrE?MxVscf!vk2#H6$T$UzcVnXtC#|C+ZG$?ap|ZvNR+sa22l9vNKXrl!)DC zY?rA;FFC1B_pVP;sH=QURsys}_Eg5%y?<;hi@89KkVb2iasibjec-vPLKzpjW7ACu5EuL2of?0#bjb@Su?{X+Vg(mH z6&Jk%xae(3v(eCVTi3C9-o*J^ka|A!WK_d(HAO`%9MFVw#bT8qPNmn*N=eSh;IrMu7kS)(_dVYHw9E5h!;Fx5r3-o(s=1a=(D#7Dp2QW}^eH}%o4?BoQxTvgT72fwnD6WJinROi0X zn(B+)N@pHh(f&9xldY*zGbw$ZAakHxQ&s1?#N*)RU`Z2N1%Bs&vWPizVn!jQY!w*J zGf7V|JL^?obw`5bTm@E_B%l-*{nje~Ol}Fj&XuPal=BQXyUP^!kn^xI#XV)>2-yso zDRO&4jodfVC$t}rQtaCT0kTsw>CO$P=VZd|$zEHaS($NkwS=9@o1zvZq?A6}69*Sc zkq~;kZmO0Gr>D)?G=;jHe!3E%l74-A(2bS(;}@WWvXbsdsPOvx)Dp)`*AhpVJ5Uydw2J?!iCNPQ^XasrPKiBp*1_66Q-c7-;*63rZ~96BQ_E{Tm2OvgdWOo%L4 z-t}m^ZT%)binr>sv*S#=@HTmh(o|>J#o2MQNG1;*-Tr)W+?C#u{W{<@)B9dQE6+4Y z@|`Tn>>629-%bE2<_T7J6Cht3vh2u#^Q*faM5?*3fohT7Jn3usk_hQ*BV^JD$%W(y z7J~mhIP24O?QoMCI)bJ*D=kYonkU$sCLdv;bE#fk9|-?}-hx+E2xy71#@+9Be`8}_ zOPub(j!*Ekd*zkaUUm4Br@f&!M<$bye4X}_`{y(&UT6+QihZLXz#w{yt)kn0o35!+ zgfVWvqr6#mb?8{~utHIWu86wuZ`|A`YoL#?v-sj8Jn{B>%D>-Nig53Lm|*k35+)TE^Tyf}a9MClQEHoJ3Lqdb#X(|-n| z(8yEkzfvg5yNQcG-xqW1E%>f&wmb}9mriGYt8723)X3%Gb6#mC^1FjK{|q`=^LAWL zeAMp-#l!v-SyJqesPS~e3N79C$4b33=Z+~9oe)p%a%WnLom&?ndaKbB;`|dL<4&r? zf1>p8#Mie^d1X2YnG6v{q3O8)M)_OGr=}v!zG+PJAl)F_-+S#;IE~DbenBa>6O&>0 z0=0?l4f#O}L{XyMwu=fyHch!fRB&c^j{NXL7r@AFdZfw+hgUYMc7)t6sUI zAV?HBz?=E)-@URRv8Sfsf(N4+yw~@KN*)BKlmOhqZ~y6)na4uId@#KQ*S_Yx@NK<{ zzX#4=OqH`ww)WfCz0yko1rlgrc*yTBuOtiIQG0Z5i??b&(eLioU|C)Gp<5P6J!yUI za0*R@ACc9~8{WRK?hlQ>qqqw0yBGc%904_oYKHe(HUo&4Hl+JhCsFz-?MT0&P*?N1 zUkOlV@2FEVd2)^BN$A@wv-!7aW*b5Fo2ozgma9Km-#%nX1JFLR?{0tjNZGV1`0*&V z&ulPsFW_ck*c?dsq2)fPr6KPVz0NPRcOo@H=*IW%yW-jKwk)51z&)thvmDxG8?T_udHh< z-3yLo+em3OX{lzJy`mseB9?rHtJhlxcw;hC6XID@WZ{dI_&S4yFIIv=4i%rJE>`lw zB@1z|=MMTrRITdIz?c^@Pxy~~fEt;}?&IZVQuaJS)+otd0qzymw?<2%2uXsPK&U-d z_4xLhDN!FFwW0kX0H_s@6VtbcmEUal3N#mBKBHniFTdrK@oP-29hJ%WWv157%4GaX zQ)^dcGJd0#^+IJbezBGHVr4RZzm>JSG8w<>)Kc#~2{&PdAmE`VzR+Rqk&4h(Qu$Ul z;*z~&bv1Pm%ud3jn>sW1t$ z2a3wtN`=X+yJ0<1sjweAO=+#GRM?+Q0a#B~DokN>0oM9Tg{ka{7VD`>g=y?!OlyM@ zimnAUVIu;ek4nK!5|r2S3BTJcaWvN|pO8m>Q9X|Y`h{@3EwYl>imTXW*0a*b;0h^S zNo;_3Htassv#cmQixX%bepy{Tc%nGV8<#I%n1;{84fC#8z5k> z-c_|83=l-IEsxei0fJ6!*P}HrK+u^@-&pel1hCXbKmM>3F!JHPV!r>xTA*-dAKPLG z6G5y=T&QF;Yatf}uI}(g?O~&W(ffMT9E&%|%Jxw4DKhIZnOTc*W;M1Rm-#}-1)W)c z9Jsgh^KUlUg){3%omsewDCC*K>j#!y>XJJxiRJmFW(Kq*j%S#<=1xoE*$!1p-E*fU z2|UZxMR!_~$n&gNvZ*D||D$;`Ay5KSA5=0?N-UN;)ShJ8e`DFB9!=1~e$*r;RF5ZU zAq+N!P`#j_h3rBn7E`^XpoOW_HYQXLDrjLEHIE6WsMPYRK>E>Cglj*VCUGd!P_9Me z{lmcaLz}!ZemKhN>U7!&8U#uM&uZaFGo&NkhaD;0nkjvTknvjk+g~5}W@fvcp-6k^ zM6Nw08D0!ar&r$Tt^v#}YLu9bAXmD`Pl>VwwIs9OF~>+xsR(;K74<)OV%@3p=!>!e zb?6qIWJ^vrTCVBFrdCgxctW;m{X2%_mE`8%@F4x6&qDy<3p%+#m-BK?tB+%v*@}@_ z0IzWjil^a7Fw7xau?mlagKiY2j}usN3Klg21>+^?s@D@FjwT)b2Oqpqu=n@VD7ox{ zewj&!siCew7xY@xsJCt1o6w zx(`p5@bLod0~g-x3ATQBju-xr>BQrOKb^1|FI-b79xq&1xMRHVmjbz;uzt7&={f#S+W3`wv?xc6^fBVh8FV5oDCfYC=|~RSeZ(IrU{$0`0B6uvweF|epRE> zgf3cz+vms~eAYnMw$7&3Adk!>LR#wa!$*lb?FKta=AcjbTGR1^$~oR*h}SMHcsEaG z9TkWHgyZQvr&Np}91rL@rD6!-d_hk*1=TFZ5RPZ`oN>hDwm3}MEA<2VldI8a;X?i^wd)Bc60^O>V;7; zp6IPm=8PTXjywL<+nIP~OwU@8Y7(rHDX*AjG%JHC-P8h3m$=iFbHW}hrX$>rk?lw85aImyO%n2jdZd1*MD zYa*&~Ip1{7p6#tZ#2v^wlZy*S5z;~jt3G(s=ci^zM`s}fn za)v#Nl3S~^aLo9EQQ;%U=9dtUm-uz~f2YyX)dKj`{p+EXKONRo=p3=-~9Q@z770Fkotxf#TZ@p{Jcxu!{-OaPz$y-Z4^U3 z(i<2iOtHZv@8hs~Au=95Lj}&Vey* zQ!yG6(t)V*A>Ud?F+9+ZCfTZ$tU(9Kj<3i~11Jv5!=~yhO;8NE<{ubC?Ln>yqcuk* zIXP*^whyza_eU{m6%~&kLk!!Qn9cd2UqxSxJBb6T8iB_^Rf4R{Q4Cfkz?*0h!7V&e zC22zxPf^ov88xzSUwssbr6-(y!mtG(|~+xYfXaA=e$5iQ7B#cq2rHskP> zEfa9G(M84iP#Ig~cKv~e$Gtf@qI^Lo9CB3gq!C30Fiq!dMS4DV_R!m>FXK5Uo^l=D zk-Ptwtq6gdKv?VX``af*MtAHoH9j|MT4`KaNs*rpsbK!PeNJgXNoo5ry@9RQsa*5$y`5=8v0DR8ZPJqTQGYg~g@qMor2uY6p_`^v~Q8 zg=M1)3yMbNj+`(lqCL9@0ftK?J2^Z%HLGJ}hq%ZN9Xf>f?HC@{KCW%s@VMep1!D@v zhv$qhoEknkvXeg|!r#FU&j*8K!nBgYF=NZZTa9cT9?`XH=XQ}DBBH~yApxb~$>U4Q zN+yjf7+*&JJ+ioDLUBocS-~i1mgz%!xe4R*f!>_)BZ|k5Dj1cVo-wJYXwrmIxU$3N z`JVx-nDO~V#bdH2jVPT~nprTWl(hBk+yC^W$SHklZ3~cDaT6wG7mh0^iC{rnn)fBF z*}JsOu5&MAfeIHX!p(Gt;{r2&Wa+q}Tv-ciyXTdSkM!(1dfN>L%!BaYEv)A~sgXg` znvYA^#DWMdiADLPV>{5yWuI$hjPb}v*Igo$|D7;$Bnx@FG1enrxyBM6Fk{lV30Vc> z@+Ux7qJYJSGzvZPA!-&QFo-#56bl+|uMCp=fdpj672OjzdJGe{uvZ1$eplabe|vJ* zRR?SWli;Z$$m*aDKipmR;v>_%4%mz@n5?y|4Vuz#P}iPs+a2%;dW#W?=aC=of`1_XIB$!c9QaE93K}mj5Tv74JdrC?QFUuXLFgZ`|7!s!L7STL3EGqtaIT%t;~y-T&d$Fx<4Iy|$Ws35=8p^xhNgz5Xp z6CkWq<4LOVB-1zuG-ef)OfDSB@|Ws4$8>!OX;W~eTE3-P&N3~}gBFLEPz}E_E#FJx zsPj~+Px{#?O z%Ss}gK_){3GP3BN?Be9{P@N@|loXc`*=qm|W$d#Kpaj0_3^1`$3n1nMYyu#~*akqx z2O2Ss?HiR$K$s%7tJ4A8!#8v~kh@{;(MB-@MH^Wb31=;wibeqWB?YA;^PvOfNLD^4JbC=&{G!59i6sRSiR>U%feJ8r zd|7(w$cQY+T6)Edh9W6MFO{Lt;IjN82u7h602x`}h`rz+dGG_AIA%%ZjyW;EjMi~w zrRt+qfO+nZ%=v0To>0i)e02o`DAXR*9UA}=@)i7tSoNw95?4AdXFRRrSdP;EeXvI# zkk!&kGk2i{6?g^JWsd?~xO7lm)!@hLS!`iRrMgy7UAIDbV()b7VwO=o&6%#XS{IX4 zs%taV)r{%7!F4$(p?ad2u4kz(hon+nyQr>?Ojl9}A((Nhrx(-pvV|p;>e@?n^<=u1 za$SzEQ$78du7gyULsF@(!&Fx?)AbeCrSq7o$!4mKQdL?|sitF8Qx?-y4<;~@aLQspr7=&_n8R4i!4MN3a!aGHOwx#BS>$gmiB%f^0*yb0#V?2WNilH#l}3Dk zMZRn?pwgKC(wO(Nm=|cw8CT{(;=@>?an(@|9d1&1Hww%|2LxuqboFSw7Fm%S!x|=4L@E_l1HPJ zGPel&i6))HCI-E1mc>sWJ(@+Q40%24JqoN;!)~gfGu1#!pz*RuA^aB>nMsB3|Fn1J z@ljOy7VjmUbP_^<1PGf%0TIza76J-N0>~l(89{*{gam>FAw&{1AP`hUKv`5&25?{$ zLkJ*?+aQQ6Dk`q%Alu-$qoM*j>Wq%QbLyT-ZW@^Jz4!`zE#~+ zQ&5zH*Hh!>MM*(B=QhLO+)4R4Dd{=w+nfK}jm~FpH>Y@V5pEZhnA;kqquY&|IAOxX z!gd9PqsC7jonLi-q}TX~dAZ{UOqy6Sv1Ce7esR)R&g(y#)7bpn(Y(nLI;%0fVE+y4 zk1Cp6!rK(T;Veeu&c$z7z8IZp-mLoVwn46Q5>(ic{*JP@-k5I-~!^Bv|{>BED{<50$5#B~4;_?w*!M1A9nsEa949*tF* zoejaH_&-55M z77xWzIwMb^kmGaRC>My0!K{L@4yuRQaYOrpwS5t$;96g7ZC^sHFRor7+J9<>uNAh2 zf3X*9#DxuqDHaoaABbEX2#hp;D^bpA(g@R}?DV5a=S9Q>;(dYG>_A{RW@*|qM$H*O zbNa%YvN1+rZL3zSl3Ul=t+LrXwee#;!)RKI#w{OV7CtN?+i8G6Or>f3KwY*|dEgv> z(NK~|f5VgI*;xK9W!z@?DWOQz4Xd4lMMgsp8;&MsL6xglzMAG?^hR{T0@SnG17*2; zYj5GT3|8%LLF`NQoqg%lH{7F6of>BEa_rE;wkVRjHrEIe^?+IA&w_*25cJdu&Of#dvNgH7G=ELG8&Z*PQ>`}qI+%dBh zw`1+>?5R#%b&@N_L0x?gJ?DRY4t>cveWkr}W&hcOzM6g2?&N^?%BlrsR|Lzj(mCI> zf3bhxfcGLZ^0(_Sob7G=^tX`zsJHO{{Stgu^lLkDXWJ(K&3*|x49-_2e!&oiectP9 zTr1ua3=c*GgTcsPR4_W&G}t-VHP}7aD;_(pJ0v2AD_iOr33WNyEWF5l2wc7jjJMCp zhd^D$vIM2F`#D`j(XIOr|!R6;alX2IVCsUiZ#5i|9YUBNN`w>ruaWk-O zth!{*_5{yB?5*qd2kSJ9i*6EZ6}&40i|$ME_=A^3UmD#x(4|q=MuoU(=ufMG`XmyD zRl#Wb4CEJzdEPG2CuRTSq5G(>d3X*4H{X6TQ>GSrHWiB5^`lwcZ&IP5g+xC7O=+8Z7M z9cKh#&6>d)$ZVS14l=@j@mT<9I*|m_AIVj zorWP3)U5$9LA`T5?Qjtm2SFC!5|c+qUyiVT2Tz|kJRZ0+2p$)a>8;bS6?XK5nb>$N zjazB|t#2Lh-0NKN@ua1Jx0(_W&%$dJUOX4N=jgqNd5&?(_uS;3i`;XMd#=IkoS`NDhAuyE(75LgvKnb45>xo2OaLm zhq!^tlpljs-x25C^P2ayYup2O?oR7YwskL;_oGqHx@)hy%9cm>hO2Me@&>PS7nb*D z-8-thf{mkU)$;NLrq8JG15!xByy0FvLdBFvZVjkhHH7(2{(?izQ%?ln+jidD z_;W-YnDgWMT~20lenTulML51Ka(?i}fq63YJS*q^#*f@MaQtP^3#`05@+2$ogPfnt zaiE`lgnm{&82Jz@=W|f_DIN#<^PzS=9{D(HJg-_NTKQDuORfA?a{pTScW94m-PqFg$$Zxaqj>uBfrziXCYr?<#!=>2QTh;+>2bJab4l}{N5Vx zNBgd*k^4MrYvg{<<{Eh*Bo7bCBRtz{_=6#NWJn$rl1F=9sWE-6kUYloZjJG^Js;P| z!$QW#hU9gsjvcm<-&ZeWd|l5!Yt)Mi$>Z@)@7>nr^z}pX2A-xE&r>h^&h>CZwUye4-uR8^m?ud@sC38_FGtQEONKs!h8a9w|~QYDss0!!+ZvEci{Zz zhU5<-cl$~7KZ@M#Z!zB(;(rdg+u!2&*FwgB6q0{|d@mM&{W|)83K<{a9=sUOB z_6Oo4WkOPKR3CGl5dn?eJZc$}}3#1HX!_!ScJjpUblJpB3yInU+sc+=!LJigGJyW_`s zJp8aVejt8R5z80En+Pgg6>wBqhoe1#SF zvSRj6+&X=&xS!$+pjTP(@2nWj>r6|}HCD_%4QrBP7jWVWp~I|rxD~_dc#@#lm8#-V zirYik4`NNm*IRLc72lvZ1vRon%7yA|JI#dliqT*a3|@3P|gR=m)P@3G?htoVK_e$a}SBIf?gePNk6 zWA^K~?u=Jh@oL2G{$C-^V_}VA?zfeSxqq%z%x%3+F}L-4#oVTkDdx7@pqSfYqhhxI zCdF+3&5GIPk1J-|KB1Ux`=nyF+tYY)nY%&%B+hszUSX5)2g7c>f{LFpdzalmWhc(7#oR{IteAaPcYDpW z;yV@ ztpA2$)_+Se>%W88UA8}yW4^3&NHM29teDgO#qzvo#qV43$B5l!{)Al1{FxOWw>)23 z{Dc*MV|l){`1e-K#&g%*i`ZRvzZLVV5H62Y48hZ_4Ci{WFYbC`5xZ@|ev;cJ{8wl0 zyy7iCpFQaM6D)rd%g?^NTmKv@PPF0{^sD__k}Gaau5EgO-P7c&`<| zZpHf)^E~s8VxGs|ReT=e_Yu3x_93~J?NclML7pi1{~^xU<2U|u5QbZEjN+Eytq`+* z0%Bedu|DIA$kqNAlPhj-#U1ETJExN??xYxt;<;2Y+q{cnwmGk@-1?d1s^7zkudw3Y z^s9a!a>ZGSIj??-Ij{bTIj^fM|J8`OzFhZ# z-9gL$0pj4b=DL#Cu5pS#Ra_7L&lU6i^h?Ej|2=^?IN3~lid^yE6m!}i6m!}i6?0nr zYgnhP*r)O%W}7e$x8i6ku4nn27&?T5*>AoVK6E2Uzj7^kBQ+1kYe{#W@xqY4K53JkIjmVDUmLzL6fBV_V_gC0Bg6;+B}#{q(5j1LTUASn&#aP?OgeE6Ei< zY{jdrxZH}@B6ja5tRqJQrlZb!#hnm8rkK|<8x(V1n-IJ6-Au0eK4HaAS@EB&n8#Ic zv^j5JclN|7<}v2RJjNKeghnb(gx11~)3T2oBhEP1ih0b?!y%3@#SN{v5n{JaV{z7L zYQ@dz;YB%yM7-h@x3J>2h~0I$h#d3c`LLZ8^BR&o5t^d7B^0y6fRB_g@S5D;8RvEB zcIjtQ-oxkkWa;muycbT+egO3$G$@tlLh8rTs4$cB*d^~Py+O+Tk(~R7GrjbLv{}G# zXF0J0@Lq@?%5CQFWxi+P&qN;^^Yio;$C{nX@!iZdDeJaj4&`SS)F^4Dbd)nRJ76xAa}<7t#~b01h0^FH-st-Vm5?lC2b=eD9w|Ok%`*Kq%Z z|9UF?H&DShi$5>^lK438r|?gs!atJ=Kl@MQ?B|gGMZ7G`aNesX=X(_WN5sDpKPA4H z=MB^;r}n^oI4b-n#r@oG!6T^PrBwLmi7ya8DDLd<@P92{%>5kxJE-7usi?D0{3G#W z;$_^=;lGCp|NT_>kBXlV|5m(&`!W2psqoLEvcC97;>X1IMjOAgU%~%AbNJiVGW;?s zcqSEmmH1QQ&xrpbUKek2^w+1te~g-i>nZV{#e1O>LOzrV|8Oe&>3Cx#?@a~IqJrNq zzFK^(c#}HDe=!yQWGehq#qSnhB>oS)*|L5uywTEMhYEiiDtKq{uHqHq&xmgqk3i>^ z{zg>PX+}kzZS@U*oeI8>3Z8%tF#Q)&!IP-q2gSb-|5`j9Z~pZ6rox{^g?}(EQpgLa z;1j6ePl&%L{)+fPbR6jaf(rlFRQS`;iE!#uS)U5tzlq@^soLs9YX&LY(EHa(SrW--!p&xgoDb1;3h#^%^ZcR=h`| z;nz~(&!)n^Qhc-cQ{rRJHU3g6{L`rL?-GAU{DAmv=NbQED*Q{R@E;XFA^xrSO)ZRn z4i)~psqpU;|496p__Fhje?1lcO;q@Q6pv|bcwH*^Ix5;>yZA2g!{T3xpA>J~*7z@@ zqJAb7b+X0Bix-LS7e6L`T)gc?szYTRYG04%D{;@ohKEtXdr`A+yo(PP4@)w<0Tp!` zQ{f*jK2f|_yk$G%Pp86vDHZEbPujX#~r`c&2z zUnqW`_)>I`xnAq2@NcBT|BZMc)$m9vczhZZ{`0BuUq}U?AYLYZyZE&ojDIW@{_#}! zH;C^Pe?fdny75<1;eU(@|4DIwN5dni;B7lWu{@Vi;m@Rk&lJB``~mU$ml}U-D*SD! z@E3~D6rUyjck$@X#ve_-65^#INaU{MS?Azkv#WrT8}S9pW1@jDIH;{uik5hh-YxfC}E23Le?b@FrC7 z=2Y+z;zi;m;&I)LzZDh!HdOe>iBA)sDLw=qw!=6oUWHWnH;V5Pe^GpPPvc)g1zS#q z|4H#Z;(NuH^)~+XRQNYh;eSQ^i1=T{??K;^%ku~o{?%0YzY_N#CJ&?H6?Qcg{svU= z##HcB@himph;I_#Ext!QW}vCloQgUvsHjsSK3jaA_-o?tiGL_wI>^+SM@5|lRMdG_ z{4?<{#b;b&{EMjYFQ&qONc_0?3GoBh8vo~1_`jmUpFG&`?o{wzRPeMRhWDg`Ur7ZY zIMncbDtG}E{BiLY#9tPV%{KmXsqnX=!hf6iV(}&7?~8vU{=N7u!%Us|RMfeLiaLkH zkBgrWA9$Vd=To_yRQT73Zxw$|{DR@ee<>CI%c=0s5`RE^sd$4C#(x17{)?#a7mCjm zpC#Tl$M`R!!k%=#T z@5nR$eN_1OQ{n$w+&jwf02O>nJ`~5xT~zoNQo$?4pAp|K9vox*jj8aTLxsPicpve8 z;-0a_UyllZ11kJO#K(yjihnNtlenkA_%o?k&Vf|a87%&$_y^*jh_@MM{GF-rcco&! zuZkZP|3JL$4aR>N75+>r{LhNNA^x^_qw&VymI{A6D*V??G`x@sK8XsxP5gE7ed3YD z#@~bre{(AQ1>(1emx%{TjK3ij{w7rT^TbQUOT~W{uQS>B zP{9XLv3J~DOC8= zsqjw|Um$+3c=BDw-<=A7FDm@=#aDHTtZx%0DVf?pH;V+}Y z|C0D2@uT8*tu+3JsPO-h3jgQgKZ$$(XgGg1o!g~375)}f_{WRS5Wh|QzDJDzQ7Zgv zsPLZ>4_jq;kP1GBiuy~%{~-Q}_z&Vgi9b|s{2Qn}&_AZ4&X3|Ts|~M91+QNLMg7)P z_}fy!i^cB{pDW&Bjq&%Q!rzw)|9#?*imwr0Q)&ELsqjBXg+F4g;f<)^&8Xlniysz$ zPrUUyR(z`X3~}EkR{3EFFKP0|E{BiMrh}U}3`0G&Nzlw_e zDpx#T{0H%3g_zT1*h(9U5M|`h%^wY-QjEdzvmx?-L#7o7eiEkBuP5dqK zbN*!Nw5Os@8WnYJ7N09VU;K#pSK_C{J8m&``cP4)9~E^Di60j~A)fk-@n1oOzYi7u z2gEDH*NLAH_iZ))a4P)csA#uo;xomc7vC>_NPOKk;N{C88~ zUqprfE%6VS#CMumR|6@LF~hS#TpH==@Pzi#+= zDtHkU{8{lg#NQVG^iAXcI~D$aQsM9Wmf^#x;JH-r)%y(JLIr=83Lf#c;f<)^&8Xo1 zKO0`33f_ncK3e=H@u}kb#gB;}7f;`B>hz|fP8Jn)J{JF8{73N~?;8KLRQR*0@ZTUl zUHn$@#p31SmEzBf?-xHL{+)R6fT>@Liu&hKvHzrrcM{JMA0eJ6UM7Bz`2FIm#kYt* zD}F%ybMddlV-A}6Hm72JTTrn)UBvr~UoBoJK2v;__)783;!lb16aPs3n0VMBGv5YO z%(pQW^Gz4;EuJMlR(z`X4DqGn>%=#TzbbxI`~&fy#p@h4^NpuszU`@K|8C+v#q-2V z#7o5&iUdK58_cr%zSH8G2e@*nD6D{-NZ+T7m1gMFA{%Pyj*;X_+Ifh z#J>>#r?~eoX1h@FFsOywD=w34~j1n-yptI`~~qt;>X2Lh({eY^KDAS zd=sf`2M_cL^KZKNJrRs@^4?VB*C`*VyhM4a^1GEUQoc%gh4O96cPPj1@6<=LIQ8pz zP40dljQ>8ySsp5vM|p4M*C`*VyhJ(wO$z;YD_^91mGTPZ{P!EIzeD*u$`2^#zjxqx z{`&^j3-g&gNJY+nAHea6%K80#=AD!~?b%c9*+uP%+-Xnb;au;o=KHa%m!Nh?lwKfh zFYP4FkhIkD|dxz0A6 z{wp#qySL0r_V90t^EcJ`o96uO;QUQ@{&sZ!c5?n+;`~i+Z^TTUY$i`OQzn}-$)-ZG zDUobyB%311rb>#blA>iWRZ`64DW+J8sgh!#bl4`1?nkx92A+AuWsgi1{ zq?#(Jrb?=*l4`1?nks3gN}8#XW~!vAMNE}6Qzgw*Ni$W_OqDcKrGu%`!BpvBs&p__ zI+!XQoGLv{!}mnXCza&mE_2eLK1q{uCybd~ILebWY9f9u$CETVKX3B&IR%AdCc5$X zg2H?^9s_$-lAD(|DgP#Sl=JjkH^J}jxMA+3+`{Ygi`}$na$X^76jwixr22vQ&co`@ z_6QjF!6??RzF0qa!^gUu_C%TL%FZM2Yd+4U=EK3=U*a*pjblARruvC6HJ|HZ{j$uz z{JoR2JhH`pA`W9cgT{GEOZ9K^aEy6`i}e&6cTvp`067niaUK+d64lR?;UluGU$!xI z-5>CQ&3Yb<7KM+%sctamw+X5m%z4_4Q{(g>?$M9*oc1Ul>!*gyPrO*amK5?RpMSeM z*4VfH5Buh?*d23n2KC9wn_Pe&rNV>wCl%yPF5ymFJY_;jZk{J;QvP@yGl+8S&_0F` zV}iVisD>g9*{cEGpeSNLY)3;h?I!N-2EJ>LrW_-~{`hfrU$T3&wj?X+PQ2zFm~ z+nnJ__&U0YrArZ8o6|E3zL_`(F9iRce087?<7FMLo-lN<*{5Uw&0WkO;&phr+Zv(g z3Hbhs0=BOf_|qZ2#rVfV{7yK1?()$05?(lGltG+f`T5=&%R$Kb;&QYGuYj)tjP=~* zK9g@iYp?UX6Z&v!a0dE5!^@qHa3p;6@Z}zMXY!T8cK|CupL?!5lW)L<=J=qG=R6Md z;qb39-wOCD&NcPicBK!yM-AVAEF4E_Keii(Gx=8b^Li37j`NMdivxXp=9Rs^JK%G- zFVD3c&g3iVU)?V8#^(5vLh8+dkJEF$_5X!$k>zV(`S@G|w0qTlumnDy+e3#z@bR>r fs1cjtMIvZ+Q{L*6->4?YnE8)>fz0YU!JC>`ZLWiS!-c zo$7m?SB!SsXz5!)xF5OW-9*1Mcu8+}yO*1tR(nJ5W7Syi`Ee4Z6UR>|9t2SsL?Us9 zjGsp@o}fgklVtzrQY#lw>&2t@@oIPdYP;3FnC)lQ4^7MBXS2dj;Yo++V3}Nge8_SB zdL}S(!CUi!qZfk~wosv`_7hvSzN}R^P26BwedU>R^%v?NU4IHBZ*WR9_z7MlD~}&R zc~YxW_7jq6A3ox&!5?2gi=Ujw$R^Hr6;O#7>l8fg{O>?d(veMSL%+xP8Tf_b46^#_ z;?feQbqAe|sjywfmjSB0#uxe0>^*>`<&Dc=wesh|X-U9qXu-KTTwyQHVXcI#Y;BHT zDB&8rHpd?;;X2!%-< z>pLKTcn!g?5-7f`qsva0lPJ0ih}HBpe5KDRybQ~_ z`_R21NyXE-R_FTyx`x8bu&nzAI`#XNx^8K{KcLeksrcI^-P8D{E-SnY?;!vcN_-RG ziUf-H5o4*s-iPi7AiDaO@+^Iudl=Z;hk1(K!M_DQ_c^0|`~XAE--C|wG?zRZgg-6m z?n6iGkPfeq*-^R>x(%?TLzo%qKEqJg{al$(=1KQ;N%s|Wl&AR?F~|sikAZ8bsP|jw lR*5XxFTnJ^ItJN~(CyE{;z{S^Hw;yG7nA>0C}sia{s!4dUgQ7( literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/ccsObjs.opt b/gpio_bitfield_cpu1/CPU1_RAM/ccsObjs.opt new file mode 100644 index 0000000..2eeda08 --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/ccsObjs.opt @@ -0,0 +1,11 @@ +"./F2837xD_GlobalVariableDefs.obj" +"./F2837xD_Gpio.obj" +"./F2837xD_SysCtrl.obj" +"./F2837xD_usDelay.obj" +"./gpio_bitfield_main_cpu1.obj" +"./device/F2837xD_CodeStartBranch.obj" +"./device/device.obj" +"../2837xD_RAM_lnk_cpu1.cmd" +"../F2837xD_Headers_nonBIOS_cpu1.cmd" +"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib" +-llibc.a diff --git a/gpio_bitfield_cpu1/CPU1_RAM/device/F2837xD_CodeStartBranch.obj b/gpio_bitfield_cpu1/CPU1_RAM/device/F2837xD_CodeStartBranch.obj new file mode 100644 index 0000000000000000000000000000000000000000..debc84737070f3baa78a9d2c888e2d0b21981b4a GIT binary patch literal 3800 zcmd^>&ubiI7{}k4-E22$(j-+ZR;5#EArW?Fc9S;QppZ11;7W?E*|dn3VPUU0=T+w~pQ^jjgTZTYt6Yt5GF^)+{|uI+Wa zH~gJW*VndbXt|-erd6=}W~=MkzE&(WyH3Y1Gb0$+ z@yg0oR;wzttDAEreYK?Py0YT?cFS^YPuXfaePy?FNi7ytU0LmP_dTb%6DTwFS*2Jm zUoMpN;-XT+tiDoh`+?VM+3kSZ^^Vu=cxGTXn55yDj=y8twv6&$-no3?NH@H+SX?S! zx)5G8ZJ9CsZy#A6qyG;_R$f>t>Wk5t(ViK51|`cL$1gpm4<@L>F_KXwN!Rh4WiQ}Y zM#ugjaHNaEP}oR#N4IjagrKj&5e22$uK&ZJnIGANVHkIfoGjD&r&%UHb>^x3#r%8A zCoz*WEsXhO!CT8s_rkIp&jUq%&;r^ovbsN?7Q zN*aUm{TMO$%U_{;uT`1!1nQCW-No`}$HvE{C*iD@7W<~bDYjVmj|@WRtI!O&{;u`u$Kq;oS;t#I?rAk;70{LCg_vQ z8Q{kSJ;C||{ig&y$=>1mr*M29aQZZ|m24!#SdQw)lC#6bz+OVhjKnqajhM_hVRWxYVpOV|D_1tw*j~eEIKGJwDN_TxAFw*U?LK|mncA?eUej>e z+nuECI&E-~-?S{x-c1$$2{dg#k=>rvHe1j}9RUJe591n9;D2c*qgFMno`XLQW)OIe z)eC4n{(dVkEv9<5%WVxR+OArw5@K~+)pQ*b1E?$7VYJ%=9i7C1Hj_OcxYB)xaqW8G zblU2+Yc^>mffugC--%m~+}`01x@#(Q_hj=ZloyF5xq$Q-;408aozxO;8lI$0oiC#N zMh(G4ZV7|t_<=DmaxFY+^Fz3S_Z7x|iiABc%t=z@z6G~+1nvwrdus?c3m?Cn035AZ zG?9B7+(i+B7P-$4;TFL1^L`Ib84^$AemR6&7vfFgeN!0{PvkbitqtLBz=xylCS4za zqqT_U!oh!y?t#08jh%xZuhGyb9|IJ;DpOOCka&fKXPt~E{T2$(&2U_DUc}u&LC)Vs z6`Br?A4g8&K0)FA&vWt63~d-!;W+9iqxuUJKHdg6+8^Z%y<^FSaj%2Z(MKGvFtlOZ z9gf3Mrrg(P@$-Jg&5KXbq1<;IM}Hv5Xx@7$e7qmPk)PIwPg7{axceM8$#M75#(LBH n_z4_6tD^l52c44=cZ_0^kK=Yy(LMi(!gHU2%O?pCgCrjUKh`0` literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/device/device.d b/gpio_bitfield_cpu1/CPU1_RAM/device/device.d new file mode 100644 index 0000000..ede74e3 --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/device/device.d @@ -0,0 +1,267 @@ +# FIXED + +device/device.obj: ../device/device.c +device/device.obj: ../device/device.h +device/device.obj: ../device/driverlib.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memmap.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cla.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cla.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/clb.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clb.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cmpss.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cmpss.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cputimer.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cputimer.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dac.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dac.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dcsm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dcsm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dma.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dma.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ecap.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ecap.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/emif.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_emif.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memcfg.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/epwm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/eqep.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_eqep.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/flash.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_flash.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/gpio.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_gpio.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xint.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/xbar.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clbxbar.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwmxbar.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_inputxbar.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_outputxbar.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xbar.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_hrpwm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/i2c.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_i2c.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hw_reg_inclusive_terminology.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ipc.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ipc.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/mcbsp.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_mcbsp.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/memcfg.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map_legacy.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sci.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sci.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sdfm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sdfm.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/spi.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_spi.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/upp.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_upp.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/version.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/driver_inclusive_terminology_mapping.h + +../device/device.c: + +../device/device.h: + +../device/driverlib.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memmap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cla.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cla.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/clb.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clb.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cmpss.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cmpss.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cputimer.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cputimer.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dac.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dac.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dcsm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dcsm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dma.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dma.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ecap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ecap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/emif.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_emif.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memcfg.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/epwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/eqep.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_eqep.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/flash.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_flash.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/gpio.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_gpio.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xint.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/xbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clbxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwmxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_inputxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_outputxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/i2c.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_i2c.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hw_reg_inclusive_terminology.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ipc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ipc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/mcbsp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_mcbsp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/memcfg.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map_legacy.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sci.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sci.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sdfm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sdfm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/spi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_spi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/upp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_upp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/version.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/driver_inclusive_terminology_mapping.h: + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/device/device.obj b/gpio_bitfield_cpu1/CPU1_RAM/device/device.obj new file mode 100644 index 0000000000000000000000000000000000000000..8ebc45df87f990b6c82956491493be90ee67f244 GIT binary patch literal 28492 zcmdsgd3+RQw)R`qU7gNK0s&+T0Re+ZHWood=yVc^Y%vLocbMCBl7=)i>D+7tMFbSb zJq+U@f}@TfXiyww5Em3wh8esL;|BVTj?3q$GmgusbM-1SO73~8&f8s8y~ywTG4sc* zAKg!#^PKm*OTA0gTc^WS6>};TMG^8)#LXfq39%$-FcU>SofL>MVzfAzm)?2sf`j)T zyysxg!Ml%kZd8N4%P%@~^`RRMZ9H`Cp<5iChg`v4mvEl)Y#qLNeQ()T&oMFlXs>tc z$WE<$|wp2_sBEHo;B=M@(zFJy>i60 z`>bzzJr5np8{D~(JdNz!{ngl(rs~~aj%}& zZgqysxAYP!W3}$rUUDq-DwX4vg*yf3^un)$mgOSSGtUp}(Mu@v&H z+j|O>^*B>?es_Tw-&0VcKyz;%Nr!t1K2E>4kIOH*h1j4%Z?{?hc~8OLRcW(Pw}Bl# z!|9`_BG1M7Q(Ec6!M>b~8e=wNU!cOJQuGqZGOD_?yFg`MD*IB|m&(3Wm*GoIVRSR5 zGNv)6109@~gS|W0yMw(u*tN)TNbxm7Pnj$w_G+~ zmFyg&#j^FQLswN5CzL_Z2~~-lsgW~B2Qaz=0 zyI)eqVmyl!@#BkoJzKRJr{4QrVHck%VT|$QZHRe+Moz(7S7_ajGag`kO2@&S$vt3f zm*rKC)4KD;5trD}XLEU;LoM%%U2`JY}`sZ?(Htk|I4#-F|WJ$)y=;S)V`kj!}^2v)&3t+fG+w2U>V!r=T&uYnRq7 zUO7S@^tp{@8s)?=y$?7T-QCLI-91R5vPPU3$`%Ha#aYtA(0tabDy{@M4ek^tvN^qh zlwQd6hDMyoVG9GvLX{SVrZ4p`l*w_TuWm^ePHACiloS2fhk@>H;gS}H=Cj_1L`s5E zM%zQ2$Y(zWD%&gd_ET9ePK;pQz}*FkDlH7n72&5BR$NfA#Z!~BtRhR6yCTbIQv)l~ zz<&{}h}5e>_d2#$^Rk^TixZWcn}O%{UOmF#4Y?vLR5{Aj6Bp~Yy9>0eYxOcaSfjER zVlpISq>rW^*_lCoBJCAp4K(JP0pYSEPMXov8}IG&Zf|z)y{@156_VfWef5+(tm$Wq zds7Gx`paCj`idiY{m4r;p+db)tk=4obY8gytB>4bP9MF^*!#Cg2w?0cqvPk@RwNE3A)|waZ?jpDjd}6+Y`|fgo9drMn*FT z_6X{-55-HY(`6!^l0O`eUr<{{iD|0a8_)TIYI2>SDZh+IddjK3nVPaMo?jx%L?-3> zNCMU?GN~c=Ct%A(CSAWr<7MleTU}dQBC<5)v3QAfx>RIQ){iITCx|S{{E3A8M3F_= zA4teg5?M5uo=nJ3rs8SJQwjO=MHUU2g9-U5B8vvbp?G|`hgvJL?W=gjxc z_SVoOc36=MzBrqFv7g4te+sXj{eFwZk1~b~6h*yFl{W!%YRS`VUv*7It=BWB!iU=c zbz4H3mO)LuJt0j?m8Nb_NMlx1cO;~z(5$H5k&vdL&lWcCIajIJbZ4LfVpq1MCZdJCc_+hlIw`borVEqDre~S}k zsnOQykpg+E7t~hFDfU(9w=|lXX=6%!6|`)jh5Oi;QeOqF3uxRN8#B>YTaISyXVXve z)q1PYUj1#vWM6G{6&h-wjX2*&^CDVkkd2t)qgjt;X?2K=nCjDKG@57CVK%Cy#7DCZ z&4lW3J5%b@rv;kI)Dd=WqK}3YjaT(-x=Llyt90F-krn^`)-V2_rGe#DLbC=!(V;be5g1oa3pTh2c5K&QyD9>ZJdGpcFhT185*r=@~kJQzMIV_jC>zTj1S5;mz$y67BA{%GN8wwgJ~C6SIzfT&#$TTdGN?{$fPL4 zBf!%pg_qh&dB&tD#~tUhCPfAA$=qR{wL>KJDX9Q@?dMAp*f!6?&KBX@L9pYcpa z_x2{;gj&zs>NyoC(KeHMGOMYnZ#Stux(jOV?X-CsEy1Bb{cT29&MU>15*Veww8I|? zE(bR#sJk~#|K_bKwyz^@+=*529Lp6tY5z+H0suQ-&j+u zhHqaxJ%rM0kBIG_{=Ju%JXpQoYTMR?!J=ri{SmROd+K*n|1j_84OYuYIXFp*m>5lR z)2z2&-rKavXGx;@d>z5&_L9j|mZ46MbSr3QLUx+lhjgEPY=8e(t?44E`fDEPS&TBJ z`szl?jJOK=^wwd+C?g&CrB}0+Rj-IJ@7(p&TMOfP`G(H z^+EHc+U3uBd&*zDC#;4M&qfMM3(Y$|CU5qMTi&#!;1-%ts<)6=dNsGufocEu?U{$0 zM_bdOh4fVYwMyw(j1!S|eQE4R$`>Er(L0t@ksIDD=_?)1#5weF;zT&Fo&1w4#6!a$ z&L<&a?#P#3#JMn{4}DL(JiW0YcyLfY2@z8lDx9y^+Nqgm>G%5|JTk7lDAj6hX(vvW zV(zOCY$~fh`q!QoYqDjbu%CLh(_HfFR~_yw*>b}qt7T)jqdpW6PN#V|PVfHXkzc?0 z$=6m>z2s4QQyV^0SAOi?{cnC`Z9_SzQ{cv2k`Xs{e(6}8e%#{TkuSZNd(UYO^nSFE zbE~U`g+-0}TFp?{fb4}@w4g1}+E%oDmA|#CD73nvXmz-CC5_OQwxVUFQzo20wXrDV zuOA=i@~>(M1=@;A#xHLPhTFzB(zHIFm?DV2`e6IAU?9}!YiQ{xDZ)*fuf{W1)K%rz z&8?kKTI?+?E-uc$ctXCn$UAOazL%DP<$>n>1({La!zg(W40#f5X~YKduC(;8gf z)Sh3^FgCwr>eR{OON&dUEv zKzn4t)R!AY8RJO6$o{Oz)mJ#LHu;HNx)fz=#8(_P;!m!J!udOsKX16Xy)_)7hZd|Q zw5+`nab~9?p5%f=eUa{LWj(5c&6HwUa5*{AoN=@=y>QH+Wc;AIJkah9g&S7VGV@V} zw20v(Asm-SlTxe7q~kMX_v55dE}Hb$(WI2?obc+}mO!9Uy6DK1meJg8Hqt;i22d}K zn#J63Dr$G8Tm_Pu$=g^VE~iVv!$SFAJ}gv?8c&D{WAyrJ0&N|kcG@bNE}PfJkUd?v zh<&xct<4+mpmi}#xyYU*N>VDcr}S0n4~8hg40{4yFZ{zIt)FO8LXmr^;Qw1DrWAfjlniQElP|0?F~(h;pMs$$CWFF(R{mE$C8=g(O8DEfB*>W-DSINke$;j`LkqXr!VV+ttGBp{Qk&MhvM)pfa z4opT4Nk$G&Mq)EHVI!QAj2xGYEJ{Y=-XdY1=O-hlB_n4fBg>MJmC49Ul9BV0ku}N4 zg~`avl9AYxP1tynWhlaZT}k=G|9Z%RgP zPDcJD8F^bWaz`@q&Sd1zlaafUk-L+T4<;iYPDVbGjC?#9`BXCUnPlXVWaM+n$YaUK zmy(eul99hBGVKle655Mtk(CyAF?j0GSJrQdbvcB>%WH&-v!rG#w5IBhD;>>v5~-%m zBYu#18>NU(y_cB!FfsLMV(M>+sjop)P?tEJ1NGN`TzY z(@Su{X_df86{iH{D8V?r1dnEXe;eqTmgyPK`QD60ocx*;g<>zSxvB-vzIY~)PkrBe zxzPMZHKtJhr)6$jt?6W*=FzK|krk<8f}3g7t&Kh|M~kdq0?Rm+yAK0{@5E#7C%xn~ zA$f5!a&|HjPbJbVKU|pZa2u1dO-b2MQnrQIv{w2O&S!HYtxEgf?X+=Js<+{%^z^4V zjwtdH^MH)l#A(4@s?wz>)iBYwedN<8b(wYXlxv}^ZTGi#v$heqHnSJabTqRQX01<7p3ls5v^-y$)wc3{W9F=x zeQTy-GZWOsBG)LI88%EJYFlQhX3m;frkRS(EXPboGsD(aqRa-HIcsKlW-2zbk!CuY z**Rvlt!CrECBLkt=H%A$l$oj6@>H7XXn8I%t8L|(XXdP#)tIT+%odvIXl6e!t8JP2 z%$zl|pqYxzY?Ya|dHoMFXZ5Em+jQKQ;83)DVUxm;0}EDMHcfnOC6@_i32TA^Tbz`O{p zi!q{=XsyL6?Z5Q0+(%`R`>xdF#s)8TX7w_i)XTMBjc*aBjE}2yPxp=PSs4(=v%ZB3 zucvg+2Vy1Kvp$>2IbM`C9|N(#gK!V&h*?V{5Q8&>9NX8!y4S z8ciC!@G5K)&*=9XOXv+$yO6OYbSYbc&2#;2D=k+uj&3cyl>6KLHG$iwl!@H?IF6#*Ey7R>Ga$y()uB1*WN*qGR54cqgZ(Tt0*taqQ%&p`4WEMz_e1` z5(z>TGFX+m(^c`+>skZLtLT}w%Y3JMCB4M8D%0@VUbyZX9I12cV*)Dd)hqp_taPl= znXk3m`Om9$nO^JgkVvg*Vzs`+K!vOIN^h5ea4|M#zRo+H%356MNaU*wlhrSDj5ck) zUXQe)k$TwQAfXCBFshLv$CB+O)0wZut`u4b5dSG$jr1yz^G)y|h0g|p2>J^ zRBdrh)D>}jU*6UfTox@r+BIld@oV}x#Z&Z6v2&s~6M)?+D8w0SDqac6=^1kwnRtz| zDn`I2=Ak$hiF1p<$%fJUXs39ElMVbQ)!$s$Gu8spMom;bjUH_2HdJwZuoPEvo z%NCcaQVUV|F%}`BUQQvZtS&V6OHCOaAu(AK`K2V)bo!Ar>>O}Q|V zF?M%#gF9i6HF{fZEjgeD=7M4GRp$>F{EBUM3+&A57RSh9V1cH6Kn<#;)zP<$A_(`LTUySXmn8q)KLLOJJtrZ zVWYIZml^zumFI0l(hZ?aqc@J$vZ*qTPuGodY^NxCrMX$twwo_Co~QIO??Fdcq*L^A z0eu^fSvs{J6m{L`CC4*~P92D$@PwgLPZO1%Wn7GZ%>?;Ro**zOj-tNaONW!@J4G3s zkt^ITcZ%EXPIafb)7?Ye)7&%MUiZbA7vzESe(SdDVeNE}tsl_Qla;Rb^t*gPzjYoV zIZPWkM;hW5nmI4&5yok7YiEO#d12B>XKps3^oI!pQ@W9+tI6ySvxF?4r(ai%nZq1G z&$}{RtvN5u5M|7%bRx@ux!_}|rxU5iSRTQ8KcUoP2;){CWveymF?8v6Mc4n3P}T(l zmY$TkOl#}RWx_x$VeUT&=}t^PFf8%1nCtK8QjjX@6GI?{WP`uF!t4`cKx3|gP?j45 zAf6t*pRzK15mJD2RX&AQeh&B4^b69bX%`NfF{moP z*-azIu7*-5G09c>mDyRGJY6P6ZqS-?%u)I(mRyCy4V{tij6u!rYiGKDG*i27X8Nr& zsbg{eW)l?5YNQ#3G#lAXTy_(?L5j_QD#0e{vMg?+j;KxQbsH4DV3q7bU1VlAa{llL@grftZNjp>FF0yij*;;iaMyf zfHXrj={8jtBe|rRL`suBNl%k8jndF?^(ff`N7MVPto2lE4SMi&LMKnkn@9_3*@+$<6MqwIgaJHmE%;7NjV1PSd-&Qjw3m4 zs0jKoi@uF=W8{8JlHA7Ppvobnma1rID9ck<&g9x^y$8`Hr|<@&g*4idIQ`LKi1In0yXj)53m2Cd#2b|l`Ux9 z%Z$6rsW+#2mr~z0oI#UuyzRfpwqeW;8FttB*)qD#WZHX**~2mI0mW{0m^MpdwggOD z3id~F(^GnaM`7wE!h;p4u1cWRLi4n>1y)gPWUFuwPRqzpFxxbgPU-U32Ze&Mp@Sf?QW1PaqlN5(i}ZoufWJrQAp-7^gVEUqOiR ziUTsnYCx9^`7SzdGReE>9OD`X?4KY+8XS;cBz#hr4Ea?$#|H=aKM*2h6bIyY38!(b zA%mM~l0PN+7L$w-c$-N+N%DOr84Ku}COL)VBAT;sz<(CW^(MJL$;(ahP?A@hWW+FT zGs)+YeAFbDko>Aio*V1edqlm-gZ?~+O?KJj6oKDR$itz!ZE~tjPP57Bg8m3om1|_B;%0&HnR*J{PoaBu6MBiPm<+22l=?o{ymcA z`Un1`jmLX$dBFd0lI1!I`{^Xh^%gSvzFa>cx7*TROER*M<;Pf%>on{S+w4*IT$d1t zXwRKWe^m)sAp|1Tb3H;l3)E-~0lh-JM5yHpJrF&2rVy_~e~}P>Wc>$_NsoCUmkNSt z^4v*6AgDW+^8Shu^8n=U7!|tCkP&MQL|8Qt5!65gO9K%X4IIdbTLZ`lYzAWd0}-wa zL}W4$LC8SF8w1a0oW_W84}BRU#yw<2`~nf&3q%|*5FxujMCSq#hzs;HBD@wd#yb!} zvp~eh0uc%e#P|o|&IgECR^UcPM5sbWFe(snr$B_50ufCLyp3@OBf>$U|2ZRqJRu{V z6Nu1FAfhyZ2*?B?_7eCMBO)pxBX|;sI7uKvB7um01R~H8h?qtoLJo83_89SnKm-#4 z5jhA%m>}?LMnwJP&Y+)dQ=iGbLv|W<2tfdkSOfS&TmkG5NB}(|2B1fPKrY=ZAr=7F^%H7B_jLNA zbJqU0eVZ@$(Gp_p?OLHRpQU2soMxQ~~2_wcL_;$wMFk)?l9%BVKjPU}-MU3r?=xeb11>| zYR0=64>G>N_%$QOJN%R|&SPB3cpc*|#>0&7Fn-H8$ZhzU%vj6V!gw>|{ftK$-)B_l z=U^yD9^*8|#f%+{TNoc=e1!1@##b26qVW!Y6By?)1{tqmyo>SIjL$QkVpM6qfuA{y z>lv?Me1Y*K<9Cc#QfM{O?P1)@_&VcTj1%aA4|dgzs~B%!>|y*3}1@+_#opk#t#`Cv^R%#8_778aRFls zV>jcyjE5QDVm!&1O%LMmSHw7*v7T`Q<95c!7@uN%iSY#Etp0|-CdLrsJ&cDLf5Z4K zW1j&=x_*p{8J94Qr_DQ*b1vhhjH76G1^O9`UdDZlk2Ai(_%`F7K}Nb48ILpGL%}HU zcZBgd#uY;h{f&&>j2dma!+tzt38Rm;QlJkIM%JSeWAD*%uCZ6|D5iTb%uA$y6-fHm zfuv8zd_($SK+=x@lD-u42Iwm}kcYvgSkM;UIL4MB1{6P9?K=R`UlD>`gt6BdZ>%U_CN!Fi(d4cSw0?E&GAo`i2_3yF%E7qT6eHP{| z$~PZK`Hlioc`juAJl5B+zK!*pSbsh1f5!TUSig_;&$0du*1ygAZ&;s(d5-eU0#d%` z0I57vSwEfiHLP!BeG}`?!>!&p8h3mjTF&w;mY1^J$nsj2*R#Bh&#GFNEtu)45*Ge8vJs*}hX)p2;ZN zxtit0j7u4t7+V;-7}qmi$GDks8{^%KJ&bxeNAq(Fm6xiQ=rG<26gI@ZCE(WvF>eUu z>jWd1t~wf;$wbVX0c(QDpLmFv$NizrDDS8_B?8~2abJ1puR&s7cffvvo@%20JxTwb ztbd=ce^1fBr|RGI=RNgojC@K;4arDfVmK%(*hLaM*OR3?dluN67sjQ{K z7q$nw+C^a_1wxBLdU4d&enBDqiJu_-y{y8ko^1ne#HX3XS0;+bDGMtxg@QaMS&_kX50ZIOP(f7Bx_4g&5 zZGyLc-&d&UFJomH^tX62tLTq9BprRVdOEI+H<;3!?dKz>(fcf2>HniEo<{HU`Rb~C z^&LU_<5~W8>iYE^?dYRzYgV=U>qTK}AjE@&&is5@R|UR494e&0t>`CfSQ+ER7$Z^H zD0Ecj8buX6kfMsnFo~)nL!}To8-I+la9PN|90hG})eG9z#Ak`7(O5m^TzoJW>18g>%|M$p$ykO?&P*;e(bQ{h(V?-A>9g$&RM>$RYLg2w<7-myz8%TL10G zSexDZlu+OAvKiX#{z02s`aak9*sU4C&mT6sNw$37rgse0 zg7%T@huvSVH-5ezN+_=ld^|@tNyV~pNtUkX+3dclq`hDyupM^0i!R3hxD|WY?Us?9 z!(0$fVz&#<5@J`ZJF$dx=HyvbLac~mx7=peMRt$JvFo(i6< zca5Zu9OVn?IhG`|9md}i^l=Gsl{CDG?9Be5hrj3PW7cmYySqsTe`)l=0lPQoW44>J z$ao%y9c@?YM?AY~vMVMQc2pkyh-bH+>^74D>@cU`fZa#*G3T58@1*B;k?jDxf7tBK zsuyA=bs+ddd*Faw2IbC2+VelCLtDqFdY#82LUXmZ2$lO literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/device/subdir_rules.mk b/gpio_bitfield_cpu1/CPU1_RAM/device/subdir_rules.mk new file mode 100644 index 0000000..46e292e --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/device/subdir_rules.mk @@ -0,0 +1,18 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Each subdirectory must supply rules for building sources it contributes +device/%.obj: ../device/%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'C2000 Compiler - building file: "$<"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1" --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device" --include_path="/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/" --include_path="/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --include_path="/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include" --include_path="/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include" --define=DEBUG --define=CPU1 --define=_DUAL_HEADERS --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="device/$(basename $(> Linked Thu Jul 16 11:03:42 2026 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "code_start" address: 00000000 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- +PAGE 0: + BEGIN 00000000 00000002 00000002 00000000 RWIX + RAMM0 00000123 000002dd 00000010 000002cd RWIX + RAMLS0 00008000 00000800 000000d9 00000727 RWIX + RAMLS1 00008800 00000800 00000000 00000800 RWIX + RAMLS2 00009000 00000800 00000000 00000800 RWIX + RAMLS3 00009800 00000800 00000000 00000800 RWIX + RAMLS4 0000a000 00000800 00000000 00000800 RWIX + RAMD0 0000b000 00000800 00000800 00000000 RWIX + FLASHA 00080002 00001ffe 00000000 00001ffe RWIX + FLASHB 00082000 00002000 00000000 00002000 RWIX + FLASHC 00084000 00002000 00000000 00002000 RWIX + FLASHD 00086000 00002000 00000000 00002000 RWIX + FLASHE 00088000 00008000 00000000 00008000 RWIX + FLASHF 00090000 00008000 00000000 00008000 RWIX + FLASHG 00098000 00008000 00000000 00008000 RWIX + FLASHH 000a0000 00008000 00000000 00008000 RWIX + FLASHI 000a8000 00008000 00000000 00008000 RWIX + FLASHJ 000b0000 00008000 00000000 00008000 RWIX + FLASHK 000b8000 00002000 00000000 00002000 RWIX + FLASHL 000ba000 00002000 00000000 00002000 RWIX + FLASHM 000bc000 00002000 00000000 00002000 RWIX + FLASHN 000be000 00001ff0 00000000 00001ff0 RWIX + RESET 003fffc0 00000002 00000000 00000002 RWIX + +PAGE 1: + BOOT_RSVD 00000002 00000121 00000000 00000121 RWIX + RAMM1 00000400 000003f8 00000100 000002f8 RWIX + ADCARESULT 00000b00 00000018 00000000 00000018 RWIX + ADCBRESULT 00000b20 00000018 00000000 00000018 RWIX + ADCCRESULT 00000b40 00000018 00000000 00000018 RWIX + ADCDRESULT 00000b60 00000018 00000000 00000018 RWIX + CPUTIMER0 00000c00 00000008 00000000 00000008 RWIX + CPUTIMER1 00000c08 00000008 00000008 00000000 RWIX + CPUTIMER2 00000c10 00000008 00000008 00000000 RWIX + PIECTRL 00000ce0 0000001a 00000000 0000001a RWIX + PIEVECTTABLE 00000d00 00000200 00000000 00000200 RWIX + DMA 00001000 00000200 00000000 00000200 RWIX + CLA1 00001400 00000080 00000000 00000080 RWIX + CLB1LOGICCFG 00003000 00000052 00000000 00000052 RWIX + CLB1LOGICCTRL 00003100 00000040 00000000 00000040 RWIX + CLB1DATAEXCH 00003200 00000200 00000000 00000200 RWIX + CLB2LOGICCFG 00003400 00000052 00000000 00000052 RWIX + CLB2LOGICCTRL 00003500 00000040 00000000 00000040 RWIX + CLB2DATAEXCH 00003600 00000200 00000000 00000200 RWIX + CLB3LOGICCFG 00003800 00000052 00000000 00000052 RWIX + CLB3LOGICCTRL 00003900 00000040 00000000 00000040 RWIX + CLB3DATAEXCH 00003a00 00000200 00000000 00000200 RWIX + CLB4LOGICCFG 00003c00 00000052 00000000 00000052 RWIX + CLB4LOGICCTRL 00003d00 00000040 00000000 00000040 RWIX + CLB4DATAEXCH 00003e00 00000200 00000000 00000200 RWIX + EPWM1 00004000 00000100 00000000 00000100 RWIX + EPWM2 00004100 00000100 00000000 00000100 RWIX + EPWM3 00004200 00000100 00000000 00000100 RWIX + EPWM4 00004300 00000100 00000000 00000100 RWIX + EPWM5 00004400 00000100 00000000 00000100 RWIX + EPWM6 00004500 00000100 00000000 00000100 RWIX + EPWM7 00004600 00000100 00000000 00000100 RWIX + EPWM8 00004700 00000100 00000000 00000100 RWIX + EPWM9 00004800 00000100 00000000 00000100 RWIX + EPWM10 00004900 00000100 00000000 00000100 RWIX + EPWM11 00004a00 00000100 00000000 00000100 RWIX + EPWM12 00004b00 00000100 00000000 00000100 RWIX + ECAP1 00005000 00000020 00000000 00000020 RWIX + ECAP2 00005020 00000020 00000000 00000020 RWIX + ECAP3 00005040 00000020 00000000 00000020 RWIX + ECAP4 00005060 00000020 00000000 00000020 RWIX + ECAP5 00005080 00000020 00000000 00000020 RWIX + ECAP6 000050a0 00000020 00000000 00000020 RWIX + EQEP1 00005100 00000022 00000000 00000022 RWIX + EQEP2 00005140 00000022 00000000 00000022 RWIX + EQEP3 00005180 00000022 00000000 00000022 RWIX + DACA 00005c00 00000008 00000000 00000008 RWIX + DACB 00005c10 00000008 00000000 00000008 RWIX + DACC 00005c20 00000008 00000000 00000008 RWIX + CMPSS1 00005c80 00000020 00000000 00000020 RWIX + CMPSS2 00005ca0 00000020 00000000 00000020 RWIX + CMPSS3 00005cc0 00000020 00000000 00000020 RWIX + CMPSS4 00005ce0 00000020 00000000 00000020 RWIX + CMPSS5 00005d00 00000020 00000000 00000020 RWIX + CMPSS6 00005d20 00000020 00000000 00000020 RWIX + CMPSS7 00005d40 00000020 00000000 00000020 RWIX + CMPSS8 00005d60 00000020 00000000 00000020 RWIX + SDFM1 00005e00 00000080 00000000 00000080 RWIX + SDFM2 00005e80 00000080 00000000 00000080 RWIX + MCBSPA 00006000 00000024 00000000 00000024 RWIX + MCBSPB 00006040 00000024 00000000 00000024 RWIX + SPIA 00006100 00000010 00000000 00000010 RWIX + SPIB 00006110 00000010 00000000 00000010 RWIX + SPIC 00006120 00000010 00000000 00000010 RWIX + UPP 00006200 00000048 00000000 00000048 RWIX + WD 00007000 0000002b 0000002b 00000000 RWIX + NMIINTRUPT 00007060 00000007 00000000 00000007 RWIX + XINT 00007070 0000000b 00000000 0000000b RWIX + SCIA 00007200 00000010 00000000 00000010 RWIX + SCIB 00007210 00000010 00000000 00000010 RWIX + SCIC 00007220 00000010 00000000 00000010 RWIX + SCID 00007230 00000010 00000000 00000010 RWIX + I2CA 00007300 00000022 00000000 00000022 RWIX + I2CB 00007340 00000022 00000000 00000022 RWIX + ADCA 00007400 00000080 00000000 00000080 RWIX + ADCB 00007480 00000080 00000000 00000080 RWIX + ADCC 00007500 00000080 00000000 00000080 RWIX + ADCD 00007580 00000080 00000000 00000080 RWIX + INPUTXBAR 00007900 00000020 00000020 00000000 RWIX + XBAR 00007920 00000020 00000000 00000020 RWIX + SYNCSOC 00007940 00000006 00000000 00000006 RWIX + DMACLASRCSEL 00007980 0000001a 00000000 0000001a RWIX + EPWMXBAR 00007a00 00000040 00000000 00000040 RWIX + CLBXBAR 00007a40 00000040 00000000 00000040 RWIX + OUTPUTXBAR 00007a80 00000040 00000000 00000040 RWIX + GPIOCTRL 00007c00 00000180 00000180 00000000 RWIX + GPIODATA 00007f00 00000030 00000030 00000000 RWIX + RAMLS5 0000a800 00000800 00000012 000007ee RWIX + RAMD1 0000b800 00000800 00000000 00000800 RWIX + RAMGS0 0000c000 00001000 00000000 00001000 RWIX + RAMGS1 0000d000 00001000 00000000 00001000 RWIX + RAMGS2 0000e000 00001000 00000000 00001000 RWIX + RAMGS3 0000f000 00001000 00000000 00001000 RWIX + RAMGS4 00010000 00001000 00000000 00001000 RWIX + RAMGS5 00011000 00001000 00000000 00001000 RWIX + RAMGS6 00012000 00001000 00000000 00001000 RWIX + RAMGS7 00013000 00001000 00000000 00001000 RWIX + RAMGS8 00014000 00001000 00000000 00001000 RWIX + RAMGS9 00015000 00001000 00000000 00001000 RWIX + RAMGS10 00016000 00001000 00000000 00001000 RWIX + RAMGS11 00017000 00001000 00000000 00001000 RWIX + RAMGS12 00018000 00001000 00000000 00001000 RWIX + RAMGS13 00019000 00001000 00000000 00001000 RWIX + RAMGS14 0001a000 00001000 00000000 00001000 RWIX + RAMGS15 0001b000 00000ff8 00000000 00000ff8 RWIX + CPU2TOCPU1RAM 0003f800 00000400 00000000 00000400 RWIX + CPU1TOCPU2RAM 0003fc00 00000400 00000000 00000400 RWIX + EMIF1 00047000 00000070 00000000 00000070 RWIX + EMIF2 00047800 00000070 00000000 00000070 RWIX + CANA 00048000 00000200 00000000 00000200 RWIX + CANA_MSG_RAM 00049000 00000800 00000000 00000800 RWIX + CANB 0004a000 00000200 00000000 00000200 RWIX + CANB_MSG_RAM 0004b000 00000800 00000000 00000800 RWIX + IPC 00050000 00000024 00000000 00000024 RWIX + FLASHPUMPSEMAPHORE 00050024 00000002 00000002 00000000 RWIX + DEVCFG 0005d000 0000012e 0000012e 00000000 RWIX + ANALOGSUBSYS 0005d180 00000048 0000003e 0000000a RWIX + CLKCFG 0005d200 00000032 00000032 00000000 RWIX + CPUSYS 0005d300 00000082 00000082 00000000 RWIX + ROMPREFETCH 0005e608 00000002 00000000 00000002 RWIX + DCSMZ1 0005f000 00000024 00000022 00000002 RWIX + DCSMZ2 0005f040 00000024 00000022 00000002 RWIX + DCSMCOMMON 0005f070 00000008 00000000 00000008 RWIX + MEMCFG 0005f400 00000080 00000000 00000080 RWIX + EMIF1CONFIG 0005f480 00000020 00000000 00000020 RWIX + EMIF2CONFIG 0005f4a0 00000020 00000000 00000020 RWIX + ACCESSPROTECTION 0005f4c0 00000040 00000000 00000040 RWIX + MEMORYERROR 0005f500 00000040 00000000 00000040 RWIX + ROMWAITSTATE 0005f540 00000002 00000000 00000002 RWIX + FLASH0CTRL 0005f800 00000182 00000000 00000182 RWIX + FLASH0ECC 0005fb00 00000028 00000000 00000028 RWIX + UID 000703c0 00000010 00000000 00000010 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +codestart +* 0 00000000 00000002 + 00000000 00000002 F2837xD_CodeStartBranch.obj (codestart) + +.cinit 0 00000124 00000010 + 00000124 00000008 (.cinit..data.load) [load image, compression = lzss] + 0000012c 00000004 (__TI_handler_table) + 00000130 00000004 (__TI_cinit_table) + +.reset 0 003fffc0 00000000 DSECT + +.stack 1 00000400 00000100 UNINITIALIZED + 00000400 00000100 --HOLE-- + +.init_array +* 0 00000123 00000000 UNINITIALIZED + +.data 1 0000a800 0000000a UNINITIALIZED + 0000a800 00000006 rts2800_fpu32_eabi.lib : exit.c.obj (.data) + 0000a806 00000002 : _lock.c.obj (.data:_lock) + 0000a808 00000002 : _lock.c.obj (.data:_unlock) + +.const 1 0000a80a 00000008 + 0000a80a 00000008 F2837xD_SysCtrl.obj (.const) + +GETBUFFER +* 0 0003f800 00000000 DSECT + +GETWRITEIDX +* 0 0003f800 00000000 DSECT + +PUTREADIDX +* 0 0003f800 00000000 DSECT + +AnalogSubsysRegsFile +* 1 0005d180 0000003e UNINITIALIZED + 0005d180 0000003e F2837xD_GlobalVariableDefs.obj (AnalogSubsysRegsFile) + +ClkCfgRegsFile +* 1 0005d200 00000032 UNINITIALIZED + 0005d200 00000032 F2837xD_GlobalVariableDefs.obj (ClkCfgRegsFile) + +CpuTimer1RegsFile +* 1 00000c08 00000008 UNINITIALIZED + 00000c08 00000008 F2837xD_GlobalVariableDefs.obj (CpuTimer1RegsFile) + +CpuTimer2RegsFile +* 1 00000c10 00000008 UNINITIALIZED + 00000c10 00000008 F2837xD_GlobalVariableDefs.obj (CpuTimer2RegsFile) + +CpuSysRegsFile +* 1 0005d300 00000082 UNINITIALIZED + 0005d300 00000082 F2837xD_GlobalVariableDefs.obj (CpuSysRegsFile) + +DevCfgRegsFile +* 1 0005d000 0000012e UNINITIALIZED + 0005d000 0000012e F2837xD_GlobalVariableDefs.obj (DevCfgRegsFile) + +DcsmZ1RegsFile +* 1 0005f000 00000022 UNINITIALIZED + 0005f000 00000022 F2837xD_GlobalVariableDefs.obj (DcsmZ1RegsFile) + +DcsmZ2RegsFile +* 1 0005f040 00000022 UNINITIALIZED + 0005f040 00000022 F2837xD_GlobalVariableDefs.obj (DcsmZ2RegsFile) + +GpioCtrlRegsFile +* 1 00007c00 00000180 UNINITIALIZED + 00007c00 00000180 F2837xD_GlobalVariableDefs.obj (GpioCtrlRegsFile) + +GpioDataRegsFile +* 1 00007f00 00000030 UNINITIALIZED + 00007f00 00000030 F2837xD_GlobalVariableDefs.obj (GpioDataRegsFile) + +FlashPumpSemaphoreRegsFile +* 1 00050024 00000002 UNINITIALIZED + 00050024 00000002 F2837xD_GlobalVariableDefs.obj (FlashPumpSemaphoreRegsFile) + +InputXbarRegsFile +* 1 00007900 00000020 UNINITIALIZED + 00007900 00000020 F2837xD_GlobalVariableDefs.obj (InputXbarRegsFile) + +WdRegsFile +* 1 00007000 0000002b UNINITIALIZED + 00007000 0000002b F2837xD_GlobalVariableDefs.obj (WdRegsFile) + +.text.1 0 00008000 000000d9 + 00008000 0000002a rts2800_fpu32_eabi.lib : fd_cmp28.asm.obj (.text) + 0000802a 00000029 : exit.c.obj (.text) + 00008053 00000025 gpio_bitfield_main_cpu1.obj (.text) + 00008078 0000001c rts2800_fpu32_eabi.lib : fs_tofdfpu32.asm.obj (.text) + 00008094 00000017 : boot28.asm.obj (.text) + 000080ab 00000012 : args_main.c.obj (.text) + 000080bd 00000009 : _lock.c.obj (.text) + 000080c6 00000008 F2837xD_CodeStartBranch.obj (.text) + 000080ce 00000008 rts2800_fpu32_eabi.lib : copy_decompress_none.c.obj (.text:decompress:none) + 000080d6 00000002 : pre_init.c.obj (.text) + 000080d8 00000001 : startup.c.obj (.text) + +.text.2 0 0000b000 00000800 + 0000b000 000004bb F2837xD_SysCtrl.obj (.text) + 0000b4bb 00000244 F2837xD_Gpio.obj (.text) + 0000b6ff 00000088 rts2800_fpu32_eabi.lib : fs_div28.asm.obj (.text) + 0000b787 0000002e : copy_decompress_lzss.c.obj (.text:decompress:lzss) + 0000b7b5 0000002b : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit) + 0000b7e0 00000020 : memcpy.c.obj (.text) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + ./ + F2837xD_SysCtrl.obj 1211 8 0 + F2837xD_GlobalVariableDefs.obj 0 0 1137 + F2837xD_Gpio.obj 580 0 0 + gpio_bitfield_main_cpu1.obj 37 0 0 + +--+--------------------------------+------+---------+---------+ + Total: 1828 8 1137 + + ./device/ + F2837xD_CodeStartBranch.obj 10 0 0 + +--+--------------------------------+------+---------+---------+ + Total: 10 0 0 + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/rts2800_fpu32_eabi.lib + fs_div28.asm.obj 136 0 0 + exit.c.obj 41 0 6 + copy_decompress_lzss.c.obj 46 0 0 + autoinit.c.obj 43 0 0 + fd_cmp28.asm.obj 42 0 0 + memcpy.c.obj 32 0 0 + fs_tofdfpu32.asm.obj 28 0 0 + boot28.asm.obj 23 0 0 + args_main.c.obj 18 0 0 + _lock.c.obj 9 0 4 + copy_decompress_none.c.obj 8 0 0 + pre_init.c.obj 2 0 0 + startup.c.obj 1 0 0 + +--+--------------------------------+------+---------+---------+ + Total: 429 0 10 + + Stack: 0 0 256 + Linker Generated: 0 16 0 + +--+--------------------------------+------+---------+---------+ + Grand Total: 2267 24 1403 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00000130 records: 1, size/record: 4, table size: 4 + .data: load addr=00000124, load size=00000008 bytes, run addr=0000a800, run size=0000000a bytes, compression=lzss + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 0000012c records: 2, size/record: 2, table size: 4 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + + +GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE + +address data page name +-------- ---------------- ---- +00000400 10 (00000400) __stack + +00000c08 30 (00000c00) CpuTimer1Regs +00000c10 30 (00000c00) CpuTimer2Regs + +00007000 1c0 (00007000) WdRegs + +00007900 1e4 (00007900) InputXbarRegs + +00007c00 1f0 (00007c00) GpioCtrlRegs + +00007f00 1fc (00007f00) GpioDataRegs + +0000a800 2a0 (0000a800) __TI_enable_exit_profile_output +0000a802 2a0 (0000a800) __TI_cleanup_ptr +0000a804 2a0 (0000a800) __TI_dtors_ptr +0000a806 2a0 (0000a800) _lock +0000a808 2a0 (0000a800) _unlock + +00050024 1400 (00050000) FlashPumpSemaphoreRegs + +0005d000 1740 (0005d000) DevCfgRegs + +0005d180 1746 (0005d180) AnalogSubsysRegs + +0005d200 1748 (0005d200) ClkCfgRegs + +0005d300 174c (0005d300) CpuSysRegs + +0005f000 17c0 (0005f000) DcsmZ1Regs + +0005f040 17c1 (0005f040) DcsmZ2Regs + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +page address name +---- ------- ---- +1 0005d180 AnalogSubsysRegs +0 0000b44a AuxAuxClkSel +0 0000b434 AuxIntOsc2Sel +0 0000b43e AuxXtalOscSel +0 0000802a C$$EXIT +1 0005d200 ClkCfgRegs +0 0000b49e ConfigureTMXAnalogTrim +1 0005d300 CpuSysRegs +1 00000c08 CpuTimer1Regs +1 00000c10 CpuTimer2Regs +0 0000b3df CsmUnlock +1 0005f000 DcsmZ1Regs +1 0005f040 DcsmZ2Regs +1 0005d000 DevCfgRegs +0 0000b0e3 DisableDog +0 0000b0a4 DisablePeripheralClocks +1 00050024 FlashPumpSemaphoreRegs +0 0000b6b4 GPIO_EnableUnbondedIOPullups +0 0000b68f GPIO_EnableUnbondedIOPullupsFor100Pin +0 0000b676 GPIO_EnableUnbondedIOPullupsFor176Pin +0 0000b6ca GPIO_ReadPin +0 0000b61b GPIO_SetupLock +0 0000b4fb GPIO_SetupPinMux +0 0000b587 GPIO_SetupPinOptions +0 0000b644 GPIO_SetupXINT1Gpio +0 0000b64e GPIO_SetupXINT2Gpio +0 0000b658 GPIO_SetupXINT3Gpio +0 0000b662 GPIO_SetupXINT4Gpio +0 0000b66c GPIO_SetupXINT5Gpio +0 0000b6e1 GPIO_WritePin +1 00007c00 GpioCtrlRegs +1 00007f00 GpioDataRegs +0 0000b468 HALT +0 0000b481 HIB +0 0000b454 IDLE +0 0000b2f0 InitAuxPll +0 0000b4bb InitGpio +0 0000b020 InitPeripheralClocks +0 0000b000 InitSysCtrl +0 0000b0f1 InitSysPll +1 00007900 InputXbarRegs +0 0000b0cb ReleaseFlashPump +0 0000b45d STANDBY +0 0000b0bc SeizeFlashPump +0 0000b0d5 ServiceDog +0 0000b400 SysIntOsc1Sel +0 0000b410 SysIntOsc2Sel +0 0000b424 SysXtalOscSel +1 00007000 WdRegs +0 00000130 __TI_CINIT_Base +0 00000134 __TI_CINIT_Limit +0 00000134 __TI_CINIT_Warm +0 0000012c __TI_Handler_Table_Base +0 00000130 __TI_Handler_Table_Limit +1 00000500 __TI_STACK_END +abs 00000100 __TI_STACK_SIZE +0 0000b7b5 __TI_auto_init_nobinit_nopinit +1 0000a802 __TI_cleanup_ptr +0 0000b787 __TI_decompress_lzss +0 000080ce __TI_decompress_none +1 0000a804 __TI_dtors_ptr +1 0000a800 __TI_enable_exit_profile_output +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +0 00008000 __c28xabi_cmpd +0 0000b6ff __c28xabi_divf +0 00008078 __c28xabi_ftod +abs ffffffff __c_args__ +1 00000400 __stack +0 000080ab _args_main +0 00008094 _c_int00 +1 0000a806 _lock +0 000080c5 _nop +0 000080c1 _register_lock +0 000080bd _register_unlock +0 000080d8 _system_post_cinit +0 000080d6 _system_pre_init +1 0000a808 _unlock +0 0000802a abort +0 00000000 code_start +0 0000802c exit +0 00008053 main +0 0000b7e0 memcpy + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +page address name +---- ------- ---- +0 00000000 code_start +0 0000012c __TI_Handler_Table_Base +0 00000130 __TI_CINIT_Base +0 00000130 __TI_Handler_Table_Limit +0 00000134 __TI_CINIT_Limit +0 00000134 __TI_CINIT_Warm +0 00008000 __c28xabi_cmpd +0 0000802a C$$EXIT +0 0000802a abort +0 0000802c exit +0 00008053 main +0 00008078 __c28xabi_ftod +0 00008094 _c_int00 +0 000080ab _args_main +0 000080bd _register_unlock +0 000080c1 _register_lock +0 000080c5 _nop +0 000080ce __TI_decompress_none +0 000080d6 _system_pre_init +0 000080d8 _system_post_cinit +0 0000b000 InitSysCtrl +0 0000b020 InitPeripheralClocks +0 0000b0a4 DisablePeripheralClocks +0 0000b0bc SeizeFlashPump +0 0000b0cb ReleaseFlashPump +0 0000b0d5 ServiceDog +0 0000b0e3 DisableDog +0 0000b0f1 InitSysPll +0 0000b2f0 InitAuxPll +0 0000b3df CsmUnlock +0 0000b400 SysIntOsc1Sel +0 0000b410 SysIntOsc2Sel +0 0000b424 SysXtalOscSel +0 0000b434 AuxIntOsc2Sel +0 0000b43e AuxXtalOscSel +0 0000b44a AuxAuxClkSel +0 0000b454 IDLE +0 0000b45d STANDBY +0 0000b468 HALT +0 0000b481 HIB +0 0000b49e ConfigureTMXAnalogTrim +0 0000b4bb InitGpio +0 0000b4fb GPIO_SetupPinMux +0 0000b587 GPIO_SetupPinOptions +0 0000b61b GPIO_SetupLock +0 0000b644 GPIO_SetupXINT1Gpio +0 0000b64e GPIO_SetupXINT2Gpio +0 0000b658 GPIO_SetupXINT3Gpio +0 0000b662 GPIO_SetupXINT4Gpio +0 0000b66c GPIO_SetupXINT5Gpio +0 0000b676 GPIO_EnableUnbondedIOPullupsFor176Pin +0 0000b68f GPIO_EnableUnbondedIOPullupsFor100Pin +0 0000b6b4 GPIO_EnableUnbondedIOPullups +0 0000b6ca GPIO_ReadPin +0 0000b6e1 GPIO_WritePin +0 0000b6ff __c28xabi_divf +0 0000b787 __TI_decompress_lzss +0 0000b7b5 __TI_auto_init_nobinit_nopinit +0 0000b7e0 memcpy +1 00000400 __stack +1 00000500 __TI_STACK_END +1 00000c08 CpuTimer1Regs +1 00000c10 CpuTimer2Regs +1 00007000 WdRegs +1 00007900 InputXbarRegs +1 00007c00 GpioCtrlRegs +1 00007f00 GpioDataRegs +1 0000a800 __TI_enable_exit_profile_output +1 0000a802 __TI_cleanup_ptr +1 0000a804 __TI_dtors_ptr +1 0000a806 _lock +1 0000a808 _unlock +1 00050024 FlashPumpSemaphoreRegs +1 0005d000 DevCfgRegs +1 0005d180 AnalogSubsysRegs +1 0005d200 ClkCfgRegs +1 0005d300 CpuSysRegs +1 0005f000 DcsmZ1Regs +1 0005f040 DcsmZ2Regs +abs 00000100 __TI_STACK_SIZE +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +abs ffffffff __c_args__ + +[84 symbols] diff --git a/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1.out b/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1.out new file mode 100644 index 0000000000000000000000000000000000000000..3a3d3fae90b22965899c71f0badd506c22f2850f GIT binary patch literal 442712 zcmaG}2YeL8_n+InTrQW81OyTSTtbl|c%;!0(n%nVOQRBE5u! zB1NQ#AW}q{D8+(`QWQi{ke`SO+<#_v+S}k?KOwpA+nt&Boj310yE{8KDKRz4VzD6p zpN8fj{%L8M4LvBgQByPuLrfZh1hUi_(6;RV}#PkHShJbr^OvcJ3sU$9;Fd{^?R zr+lRiZS=LY|MvBbCEuOZ`uFzWHY~$GV^Pt8ouS36wTd37q)OrDCLYfw{8NE{%JI+U z0KIThvByJ>upJxJk^HvWtc4q$Yf6kynoY-_26c=nerEE)*)|kYjJDS=4lTZ8sUPe) z>l+e-o(=Zg2`#>72@AgGafE27NpJuz?=G=F^bH9_&z`>H(K4Sc4K03X(ed#i_?RKM zePy<4g%uxG3)rv(MU>`x7E~+rWH}1U?UVI&xf_DfxD7J@9l{x-aI*`xcOwH zai1-&@yzvt7v`2(USEQ+P5*qS(9yucx}hMMp?kW@n5<1ix2H<+GH>aDULyl zCT}>p{GRY&#>(_M3_tssvlxO^+T-q$Busj@lP0PfUyP` zYlwe0#EdnFX=e;dbZk4ZlqvNSF6o*!EpTQWGaDYZ;}Y(ocj z9@wN`Jz#C}*!^m^37JbWN%l1|ie#dF>wAID8gfDR~7tk;4boa!(HA*86|%gTHOB>YVJP@Nt=>` zWXX0=a)ZLq;)I~)CFB_Y;76Wu_tDt;!G}Br%?e7q+|>se_+w9XjO)4G?3pJk{Hr@_ zmRROn+>Z(h9OS6q2D?i-x$T9P<@L`T@^qSCezJb4tw{b&IH_NfRob*9yY!iooYMNm z&onbLXfFbDK7yZNj}vYsWoIY9~>D5s#Am5{vr>PgBZW&C?n>8_sGVo7KbzDB0hwRnLYvR(Yz#oNu(ApmsgknOEXhnqYG{yO;Qv_9zJ`?SmsBEy#O* zhcgd6jFMoPO$wt+=hFNw#XvUL`e4dzS>29=+NPX*Vr6m&O!(b|1Z( zX+dKHZ^U5D(66S_9wd>g7g&~g716(PD=e1w6|Ywus1|^Ah5kSDC!7TF@#&RcXmhkiA$3r~Zt{$`=e1oW6;NzrM z6DK4ri7!oVmePzI9Y4dtMtx{O!VD)H^|cBTXE?>EuU3#WgJdL<0j_vXAu_t7=}7NL zM|u}L(&J0+<2d@O(CU7`MtU$F#UaIH9P_A7V^N*XqPh!?>Np(LU2#;W;?c;X)`laq zL-27LNhA&(S~X|QWMGHk<0+<%yxV(}{K>>!r^4JI`wJ3@++ac0p6rIef~ zOewJ!7@0je$cgjt)5RIhYT;H8Pl=zETf*DGTabavBOZjsT8CwnINVnU*Dp>gX?W(L zN5|Q!A?775C=EwCkNR{F^<7xh$Kj~&ilaUiM?LW;qB#b}vP0%@K7^g}$uv6udXeTu|CcFY7qgp0G$>@3-N3zBJ zFYZa=3(40cSDVhD5yp@9DriV!=|LgME$eaaf6|#m@6EFZH1E4t=-jEiO?kWW4(0S1 zTw4cRYlq-}@y}nl->g`#N$=dTbinF=m;U<){r4XI_kZ-?Kk>gfBTtAck8c)Va>yMp z$kG%Y44rRt+Y0sEcuSmj#jK-;;~m8I=U{x~B;&|nw;w$c9uw?-FgT=m8jTzO$6Y6M zS&~v3IzP2Er6gc}8vfUNetIb`AJ>;sa?~@;qmyizyB@`rcPY``BL;RY32RQ6Ao)}BBRMc#ro8#%}*<5n;(58~phjgu{ zCu!DyS-O^dNSxZHHDa*bVPCezj!HhE4+ z@m$JF@Z-D*xl3{|FBSgj&K%54g@2|q{aK6FKG*Fu*vT=mM8Yh$Eyr{8(CLqIao)$77k@sw^z>VKakgPy*x$Ay@|ST` zUWwOy@4_VUxj_;6o1Eb+l4a$^cn_1uc!^{3Vr|2cMXBU3UTXOKBY0ky?Ib;uO1a3a z)HB&OzryTwdTypAbr#`J_IYXQAqJDTB7zimg>QEi%zounYl{L`UK4D37Fp#uqpzpU(Bu=CxsUOVe!Kw@1Di3 zk>CHbgyG+o_MydpTAF%19zQYX?liB?Lo!bN$}5^6|MDgXf4Ym$t!Q#1zP!mDe6G19 z^u&_1$MovTW@%axjJ(l;&Ysv(FSiw6U(MTXE3(nQig#Ozh~L)7@uf#SG}!HP+V(hUN#YZaw`gU~M0!q{t$l8SGpWQ{kYKy+)Qb{q z7o2a9YlC*=>fpdy?J;f_zLM?k=~Ylc3EDeqnJVa$b2QnqA$um^3xKa;*)U$SB4#?rI_6?TiKW4|>ESC_Q%kTc?JEj|AC z*MwH|T4!tT`=~dCQ?CFh*OX*o;MmP2G!Kq}- zD!NzAvKExtrd26(uAUs`@dRuP__BaphoO1lmIIqA$`7nPG^e>`T|k{eG%wl`Gbh|q zQNAXiM&TOW(mvK>sa5gDlv$Sc(@IDNUgur$+OcC(UK`YL$|a)kYXknkG4s`A!&e)s zn7g@r{jt?0-i51YOu77e$@Efx^w_g{Mn$`_fWX3XfB(XYcAgdGy+15|?BQ1O+YdeP ztgo=4Wp9!H_H|;vKTOvUvf?Q*{eMQ9@aBd8lbAT~ZeF)J%S z)18r>7@wVzk)H2P?3{&McCE8sB|R-RHz~Ca*M=Ya;l=SSxbYil(w66Nd&u*12u)ds( zP4SsI?u6Lf*n|Xnrro8b>N5|W>wRMQ7cRq`=ay!NOG`7Elcd$prKPLZgtS=oWPg{I zp_=1UVg3vy(J?CPP&~$aK>pvmzJxyzIP<;c8T|A1Q(Px za%p+`(!BV~2`}}{^d*cct!m=Zy31A(qw3N#F0F@RH4)a_rS%k6gqo39!aw-mZnt7* zg`fKDaZ~(3L{t=yv+yu-&^!2t9sW{e@GlhG!92(!Eg@_Bh*8-cx(2wU3WV@*auo1+S}A(JXny$Tkq{(IBXcQRMGqJ zvi$oE8G|gLdSC82LW5=DcP>tN^Php9b)fK|p+@2H898{YxCI+?HJ>DRVj_i+)epCL zp2n;3F~~r~=lKFfsF$qk#&h4Int>C%KwZwhurB7uLahpOWRWPW3iZUPFV=XgapIN5 zFCO!J$K8O3cj2LRCnAv=Jtw?|g`J zZ3Tz}CNnP~y(hAhgWIWiTvm_x2ctnPoiC* z;NZie;7CDZk|Wcdm=zzJnuz=eGo5(_j9v$6eX;=Yu^Fj3B(ozQ;%thrWTkXYk4;U> zNJuoO>>?}%@46R0yej~s5a!WOPvs!s#z((?`)E<0CBOxRn@A!pWVB>(ZZdf}oSSZ( z282%GClM@pta7*V4qx101SmM@Q+xpK#l+lfoF4@{9W?}Pyp>-5z4}p znt}X@sUtM?Omt@$G1y5O2pJK`j~pH&QCvwRtHhU>Vk?_)B@SYWgC<%D?TUD5Fc_y1 zogh(MNffKZo0ODT*@P>x5mOR0(Mr6Cp|doQN}_P8z-Y2WaV62L5;{gwDw}X6bf9#B zCRz!8`h=rI8b~F02oW?@pa}KEk<7Ytf3vr$_$^%rGpnc)W~ZA4*w zdfZmyk%7=AB$C&PQ#AJ^&{#oVoDjwK{zn?l9m8W9m}GCrAvAG^Q;h zOmLJjX&GsPqm5b1C;=P6gHbbpYK|V^b8WqELr{7!Axm%}Mou9lq93mT64BoTGa?3&*YABh+$fhzDhHw^M;3XL>)YXS_he1U2Nb+0O_o|a#BFjr*84($| zNoqvQfJDsXl|Uk9nP5i5Y!l3gcvHX%5py^QBI0n?8-1cyKHU})AtQpdmT@tkbFqLI z#v`JHyA2{@bYfa^Y4^IOs~#B{O+>o9 z09;HinIp)J5qkYs$}3^lfAn%>i2%v5iN=Mg0Dxb>}9*t-wOuBDCr2d ziV(wSU(0D<#|z`Zx1KW$Xz$gfRn*!4HToTt4rz}{j~4N_k>;A??Tz#Hr!3zJ4W7FPTps{G=sc)`sbV{gnq!>uxp`O+3U-P ze{wYq6d!yIAE1&abHxQhR2zf5i@XYgwKd55Ld7D&4fehSV1z;6R{)GO`1=}w_}&5` z>k z^5ne@iVqrMP?(XFgztrZ zuZac1MlrQ47lrYuWrfDuj1Xxji-nIC{G=r*rDGJPXd)W^G%g8XJ!g#W{J`aXF~Pa8gDm3 zugUV)4W01W#h6BL<{9*cQ9iyXh`^aFDW$V;XN%@zAchET74`UJ=VfHYXQXA~+xt`s z-;pMg`6BSrXYA%Sfg(gkCv)??pMSZq;F&B z@!;~&pf0E44XcZJ^Re*exG0Z%^NGeAj?jy^>5Q*CPak_eI&RJmP(#oNd;rcz#2bA3 zIVY7xp=Q_5>*T7}01*nrO~0V?Ve3t9NE1+Nfbok02QD?~I_+HI!1%r2OSW_8Qz5H2Q}VsgkHzzvkq$h z+Q@N<)$7*<6$H(Y6&SaE4R>${ox*EeQqoeg@y&DEJ*P!Q-pRCo@GW)PKWC(Y4XXgd z@To9>j$4vnba`Rj+rNN@s2#@|!aDAA;p#b!KMm#`cV6ROA+$!iT4PL9ht&7SE(A3M zt%t6rW(ZfmV6Ni(3DnguMZ>*QfvaChgW;;5Zn*ljG`JJH88Lvbt|>p4gbmQprCZv$ zf9EXj0vc(i0XLG-@SULHawQtR*SN$xDU)7>ne>`yccn~v zU7D0k`lCRBqfvJk+2;mA z9%NEmn={R3w!4=FU1AdyoJk{LCcSOWq`wL7cn^_G`ny0uCY^V;d{*F>x#vM;N+xBM zv2goCbkIFf9M7cx(|E%{CJnuHWYC1FuX=+DluXJV2a5D!(P1XlL^qf+sV)sLlUjuV zblinsI_^y!xbiN|n?3FssN9SIFOxpEkblJrAqhErq%1laYP%^0>bCqY( zDx%@0OzJNUFp~yIL#0d_C~Sa+Pfmp{s~KDGMbJn!eu<#SO!}0dp?W16YUtc!kV&7r zR?&a({OiL&4N4}BGG)?W9n48-RUelUJ7bZGHH}4lRm4Ht0FNcb%}cTI3=01g+PHfyN;Bd zneDm)uV7VgU?z$>DU+tdOqwCuT`7}hN|TaF zy9pFHdh*hkr>ajF25&Mb{mq-fLOWYHnj^~NxhGfWK7mYnVO8z*y`l@M!2TYJ`1M@0 zDUGsg^-@jA*WjXAj0vQcPWh~tK z3UBg7aXgb2=)B<|lMd=xaPi0|-j6{AN+x9syF?~^(UeJti;7H{v`89YCLJLRpySTw z9_Y4h%4_ghiW-YBla3ayj;YjfFX`MXkV(%hcz0yS)7u_ESLK|Px~gQ-ai&cAvS_#| zla7}Lm`PuehDw=qg0KM^dabToW!b&WAAv@iX^?Z$NrHySm1vlvbB{qt4Sn~68gq`! zx(I3rDnK;BxD#`YuEuMqmuf!QJu>mqPI80#Epd_KgO5S@37?<7Okm(SXTNGI(`?m0 z*a|9evge$n0v4?+#1+&^QIHX>A^IwfHxr@bxM^1Wga3X1+2i|K{rVFe-9aa@3EwQl z&m_Xd8gP6gD#79t8{aK63witC#wJ?$T|zeOEF>`|Ni;s0JS(e024iOnzhUG}Iy923 zf}po#lEvZPI2`HHa&Irglp;;!9K6oe+c0zy25@VC!>Lz3?{)3W4`I0R;w~<~wa;B) zSt`xK??I-EmKjVr^$ZIq1))y}NB9T-`)%h^|Gs;U*ABxUMDanV@F#<*2td_mfU3_$ zi&d)5NmQZgyl9Y#ste-qN>p8xCP>v6!T_Ee6qJmwks48Gx_n_z4lq@QFN~|N1y`3u z(+sXc^=~Yk7Qj`|?>{&STFvbFpIk+#VRadB^}T4a%GD1NRk*q$8f4fcqOjxN)zPj4`BdYE!ux9amJUkPyZ)Z)ECCp zpMtCVqG_C~zbu>u4PUWuzJ(geBk7Y4x9z_@=W)v0&56Yxdliu%I1 zsw%juCYr|M>M4!W0=WA0=#MW>NpN|A^3}L%sd7~la1|t)ta24BQH85oqCqCELd4;f zxT-BpkgGbv0Jy4g&_AT0^X)v~i^>)Cg>e-sxC#?Z<6PC#I4xktV6Fb_xYGBMO|x}5 zV*sh$4TfNr7$PcF*%DQ#%K5J$m@5viL{*+NL8`h71DG+qJUM7;7pLz=NELbX%p{%k zI%BGr$X2~Y%M7NRdLIiX1u(U^aM0l2lg>>6#Vd0wkk|_VQ-z|zDpUO=sxZ}Gw8s=w z1H|E#n0j8CAX5W{0WeiBddshin`|fot|)UWHLnj5OuZml#+e#w;iLejTCVnMH@n7_ z3Q)Yl6iDmC0aHby!75WDB&skqQnbg!)F^RyC8kD86J%~0ZsDW=rjqLPEP8X}BGX(! z<|&ZUX91>Wiw3Jqy(v+JsX3xOCZ^_!!z(d0PnsZ8^MwI0l{0Xa|G<+!%=j;+)QrAR zFttduj5D>^!bt&4Wpp_C&G_YqKLf=pG1W>Hzomeww?upFXRW4D5sS42^6H}YS;gy)$EKQK9Ey4hp(!bqV=f_9RT;Phr6m^9$ zwM{U!U9^ldwZpQ(#Vbs;QJLBWn0ik%SY>LrL=~p?i1wJ6+A9vP z#MC}%f=s+It-XPA{wkRbyT7XQ^!PmOiX<&4zI-2acP1~eIg8isT;$u1%CW^#sT1p5>wO_ z#?&dn)M?Q&&eRzTCk3HbE#eML-HqK|>ihGG6QKCu$@l+iEAw-?U+!i$oj~koB$wfUJ8p z0J8qo0mwSo3P9GwUI1iWYy%+gV{eGEPPRjo^|B8{SvNZ%%KF(CqO7C+1PVrSYW&f* zlNWSo0D40i$w{O)SWgFtksK%r<0HAMh4(8$PF)1jKEEvsA8#C43ltwz4lx4sChq&Q;5{8H<1 zU?mh2E2fxQi-47|OswptzjXw#5~7I}6HU(@39N)`V#Qoj>nLC)bQ3G4n_5Q$D`A{i zG2_%a23QH{#EMC$)|Y^l@=nZ{cWN$%WgTL*wF?bZb#OS?`0^0XTYQI>YYAj;BiJ&3ZjTOXn+@&;vOaGKK-TB20Lc5i zHAGpTw}B|@^R^IWecleDtk2s+l=XQBfr97LQ}+jDO?vm0MPL;2=hJv};XbFG!n(ba z==K;u|d>Gw>^OiEd;ghW*08WQ9Be{(ytv4aS5y)$ey}w5c~}1%HFlsFAdS zx%nZVJ|5zQ@i!Ph;_e`{&n`l{#>dU4MArG|7AQUF1AGAXkrbMRCfN09dKLT;SA#c! zbLp?^eCsG*1I2ri;hgN!-_ZHKNyNanLL)}arBB!SHe|$zxuCo8X$^FjK11j4s7n*> zJ947crO(v)tNhH0dzP5IT>31Xzsf94>_nSOpRMyZzL}N0i+RCt)cGs9(u!XN zB_-Qk`W&6VIZCX8W@7bm>2r17EBsvJMNeXOxb%5Ce{~X=Y0bVaeZJ0L3uI-J3ovr3 zpG#k$^NR&;!!t%=tK!m2bUwXgHj>te&EKUj)Oik+HWL2C9N^Ly>3p~_GkNGvY=JI) zvCdZjFdKOiL2T7rda2Iu^)nl}VNGn+UHTH8-`!?5a*LMOYP$5LI=`RGY~-dSu?4&I zw{(67liA2^IARNN>C1F}&yLy1jVEHO;O`CTezBez-@e9vyqz%#1`h# zSLpms1hbLLX=1DI(pT#I+MC(v6MSN9=+al|{CPh&a%LL2^wm0lz|D=EnkFuNjn1Fw zawF&F8JE6R=Z`SCk(1NhrLWWZGdphN?6_R|dYwO{B1X2M2Wf1$OW&aL-9LPdl!D<1 zmtH0o_pnpg@Q8Hj8+E>W6+MGSXOv4XH=jWkqu|1#U3!Ji_oJa_L=m{9OW$NZgS;DT zoYcytZ`NO8n;y}V=m2Z&(zk$7*GuCbr zbBs&hsq)u}H11D(Ip!OxZrPj~4DbpEOXGqVN%q~Vz^{h-cY z5a4Ff@NO>sL!B?@=2qEow@W{y^Y!?OnKeAirGI2@INy#ASDo$B59@pdH9uQ6JlCZk z(fP_^W@hVaNyEFl^rJdokIT)X;XPdXF`ciT5cy!}%6> zxa!_6{S%!pSmbBRhWB;pCv?7$kA{9L(%=G@eo}X}to7?qt>aO0R!Vv*J}Hf=#R!*v zO03{hj5I%ta_Og^WTdHJj7vZBBqJU2#V-BRCmHEj9Ou%{KFLU1JKm*#CX8U?*3$1f z44(dFkGf6qluRrwi{eunx+@JDtBJWzL5riWUn;-U56*SQ;{z}Sc&j^e|F@TMDwqtvekurnlI^It* zQflyI$NnTEaf=V#^M9bdDI`FTgX*Cv0a`7W=`=Wo}`nVs@dT|cbC zc=rIJD^v!U%?ZamHVUKXGBQ1#~XS8y8y_@>agVO%#7y2r; zIAUw#^4fLaV$-el|M?`iB%AWEAA@mp2PB*Ftlvl%_{o8vZI8I$1s+N+U*B)vsy`DV}~_=b4J9L zDR)5goXmCFJm$JsK4p7Dw1c}o-NL;@=&*D>Yh3VCeVa}+z1wq4xGuVLxW%U@-lCiA z1!hwg<7K*;=ju|tSmyai(F&jVSmwE0gXe>9xzW9>Y;y4(#uDgORyMirjx&TGW!YX5 zC4x6+P_tzbsXvSlfDF+$XS(58KrD@Ri??l@h>e#;K?Xq~w(%Cu1&ED3_LJe`Cd`@z zik7hvCu8F+B{r0$Q6e_p7FEjFkZYo3Y{+;b8e>PjdjHiBDzlvq9ggU>;_pYw2Wc$VGHAHsty_&Jc->1)@X{8{gMF<(}xwPXS&SZ&i`lFfKz7u# zZ4id6zR!6I=RlN_7a7txrp z)w1p2gd((G7MmILXTRP-%S><19Hhkp#i1+lvW4a-OYt%&N)`s#l%;sF@feOnzQoN6 z(dRzo;5fS4$0irz`M6W@ef1#6-t@gQJzusIw3`63opT!?- zKBq;*-*(X!9)CM5oCF}o=ew^SbNI(?=RncHh8SmOxyfdZA_jLkN+-f#Emg=#$+-26CpPZ4J zfP8d(oY-d8;m*&>c4x#TA{{@`@}9z-C3s?XP9_S##CT8TQzLtxQ3%_F%KJ5bJT|a$ zY&Lqu<1MZeh=~@Z87l$2#bts$F^??GA{R*B@){uv4=4tT3k2|h%~xM?BJ@lg+z-ik zz@`#J=-0fxXEFM{XLBdm12*qBIn#jt-D@M-TFVZ9```3Osr1iN>7UQ(aB%wNg@H=H zye5G3i)#W%|03RUGyUS4pfdepXWmNmFX4?;=@;Ac+7&+V9T}+-o@xSS(1Tp&G;q-4a)4!cF zjZjCKd@K{sR%w0kE7-Zgu_F28#Ve^N-jNpDJwLH~c79%LN;ZAl+dDxpE_0}NA_wVZ z9o|S@GX{MU!0`eKhIa;dG`WhPNg^5GEr}LUJO$vb$ZpXT?;`NL%y6<^l%ib)N}AXj z;U%LKPX#!>&C2jJfVUOdDV^isGVQ&;uRqsm<_)+Y+*mtGvlC^I^-ee5J8sxJPVX$< z5nwBm4qpvAqRm?gmrxj6ndEejPwkqJg1^U&DIQ)+IMM18o6|irH5KFZy2U!l%G=C! z+aE80n=DYaWSZ@RX`LbrU>|_I=oU*hPC8u`C*5Guvzv-@^qkJos3$#>3Ipn{;cj0&(ncxuTO?_e*}tv(pSE7a&>$qdnCf?`gv zfi9KIlm-@=#Px0hHM#B<2C#4`{`TUEA?vHc^kghtqD<44F~@U+G*f$=L6&R$4-TgZxN2CDf^jPds=-`2!MRNu_wJmgIU+o<(IuBnnaH!TTfg2NR)7a z@26n#xAqk%6!-Xyi7qqdAi++NO{*|~GVC8NjR3f>! zU+~V_uno0df?O;XTx4Zu@kx+%kkyCW!Ok*bV6bSfPgZIQ-o}9jzz~Tl0q}xAO#v`e z7(n{%_FmaER2>Zmtunsgg$4j=74vzx@VUt3b6x8QD|Zi}6*B#1&P5+T|LjB49kTH6PyuGd3x=w^1=;lX81o6*D#|x3^O< zW0P`wdlfS_DYth}F=LZ*yZjnETyJZ-!?wL6KhBOZx(_%>v-VCZOt%83aEuD$XH_ic z+hYMvHw350#{rz~2~P2NfYWWkDV_jux-&S%r8W`9T9T$yTxb(muKM);3!C@ca_j}& zAKKptN^=JpabQnjS>E1-r$1u~)X3hI_cuc2G6>xJDw;QY|JGViNAPA41QD&WGom8Y zC`hM0-pUAr4DKuiThmJcdnN$e(0gD@2oVo`IgU^v?rx@38P=a(A3Zjs5cE~(0DOQPu(GdMKos(T=m!I$ zvAsX>dRtX~nRjTNnS$|6dI!WD*^Vi(9n{<3}F8Z8d~w!0PLSbLu>Mi7WMobG_>K< zZu@y?Xp6IgamEE;z(bKuyzLjE0gpv?#uvf>2IKCJmxl-C)cg{R6DJ&uY@D!>D7O5u zo45RFX#d8-#~qO9FOM~g+}CpZJD`$aDbW$Qzbi@fKt-Yl@kF9X^k5ZZ5s|L5f6!4q|ceGSA54VMcCbe}(rqkm$YhZ#GT8FyJ<* zLy>4whfMqQtEDx&eWEJS^2QuFmPxd{FGoNo(Nnma^mHcCQ&o^lw74Bdj*MgyJq;Ym zBwE~qqen7{miOSu=~AMn^Af0ZONpKVa4FF<0WKwa7Qm%M&jz@Z=r>hdk?1)9ml8df z;~*<^{(R$`*5#r5L0>5n4f~1(!~z}=B`_cw+ZXb_2NFGL$MhFE-0LwLRH8^Usl+7F zcsDQ%GKv0PWHbUYiT(kAOroy$uHAuuQs z{RkSQL_Zb=Fc>dC75(-{D@=(~k!WR{u#srtJ2%-i)6Pu|?YhRt9gyf>{}=X0UbAoQ zU@$5Y9ZANW`6{}UWI}coEpCz1jB8vyi96&pV;UDv;s!avm_#q*Nr+%fqTg0ACeh1P zj7hZo+B$qLlW4Ju21>M8K?5aPE}+3BC=$Jf*G3MHkPK^+13_OY5)J!`1;j@@AP&QTXly^i`yNR2^pupYLHB+c2P#n{np9$v zXq%=;w716Fu1K^UfJ~y5T?Gj%bbk%IvZ){jnMC`7)0sre{RBxxOrqsZf&^p|Eq4(l zAd~0-P$rY;Kmc-yt_o2m(bXWzB>E|cGKsDZQ6|wfAj%}Vra(;+Eq4~A1}V{Ub3tm5 z5?u=xB_&$fUl22*NVKxMATdaZmb(j*IwGY+*9CRp0m!eSozNg9IushDM2A6xl<0cU zASJp!G)ReV01Z;28v=tO(eg{biGyS;va4wMmET}6c3Lu^_JgBy;r_phL@VQjjl`xx zqMxZG(akhI?tnzE-}&v9OVj%I2ZK?O=qTLON)r7s$*xSIkMqGuGp-@gpQsqSiaw!Y zOrlS!7?bEzD#j%Gw2Co_KBHnxqCe#rNrLi5_gNK|SJ9uTup-f)16)e%jsgzgIHvldr`X<1oME?wMDbcq8E+zUGfJ=$~RmByFz723G(Z6vVWQAMNuU@D( zcu#%MSBgZ#zG4A!mj}cjFd!P+@A19|68*-kx30YT=vos{i6YUY5|c!`REcgOa-bs7 z;Q(Y39RWZl(UAaT5*-CVCehIVWD?yHfJ~xW0gy>_YXCBdZUaCr(QP5hB)T0$nMAjT zD3j<85M>hm97LH!cN8cUTzM7U2^yqC$3TOW=vZiw5*-H&ibTglgOun5Xpj<}2n|xA zlb}ILbZ2Og5}gbUQle9!K}vKNXpj=!6&j>Orvif_(P_{iB|2Rgz+l|;W7*zIF=OEx z6Gftxal%GoHzCpPN)nx=@o|UHdifag+>Yb@&rbbxIT(z=8^vSDXd=eutLXcRME}JT zi6YStRE$aV-zvr=`X3cz68*1=F^PVtVoahRsTh;!#~gza?cp#9cPY_G+`OQ}Kt7DN zK!X%%4H~3M>(C%&T5g|4>ySDvw@{-7Db#WsHH7*j@pN$CpP!By|IWF3pr4!r@d3uu zLC{Yu9DMjvTf4)wDPbeKuZ8zK-grcY!=;M5J$BCR-yT#G^Z^Km%3|$LZ*t-%W@LG) zJwT8_^D~p{K!`HEt_o2m*wp~a75gcOGRdwEQKs27Aj(9$ra%el%7t|hG)UQ&dpprH zq;A)OXGq}=fd;AEwV^>ucO76*v|H}?L@HOVubtuygvf(0_L%ywhAke{P23X)I?p)> z#E9%X79{mVkkmH?Nn?8h3y%jN;4RUO+`6wkC#hT2sB6me*qX20UrttQox5ngB0)=p+O4xaA=SM zUIYzNz(+uX6!4MIAO(CBG)Ms-4GmJj#{h#O;4eXg6!2nU00O?~^NS%z9!@?C#)%@} z$~a+z@ns?4<0}dHD;ghn2)!dScEZ8oJNk#ea0pZqv_oX;?Dq(sdzI0G8u0UK&Io$Mr^nuCggG>HWJ|SV!MSXf#6cg z!vU^bZbv|al=4VukWwB64N}UZp+QP{OK6Z%-bxsNl+S%H?!`{Gu1^C!rbs#HF%}qY zMV4-7%F>PO?JYb8fRz9A-B+g~j(^?+e|p^!NO>pWfhy%O5M@#x3sENJ zaRB8~9uH9_*FJF*HaiFNFpv4L~O4eE`U$ysrRBZ%Qf8 z2e_2-0)Q)0UI-0R%KJfsl=A-2Af*FJJTyote+3$(lurN# zMao}=1}Wteg#k$U=vD*nPO8{G7j&K?<*@TukW3L$KDCmRzh>d_0Hi#7R?l8HI(M>w zdK4)q^_Zl*OqKGDA|)zPUJgJe{5^;=Dc>znla%j)1}Wuxp+QRdK4_3q{ys1$ zQobJ=q?CUE4N}SvK!cR>gU}$Q{6lDvQho>;q?CUI4N}SvLxYs^BhVnF{3tLeQhp2? zq?CUw3_!}S99q3>bB
0x0
+ + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./ + object + F2837xD_GlobalVariableDefs.obj + F2837xD_GlobalVariableDefs.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./ + object + F2837xD_Gpio.obj + F2837xD_Gpio.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./ + object + F2837xD_SysCtrl.obj + F2837xD_SysCtrl.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./ + object + F2837xD_usDelay.obj + F2837xD_usDelay.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./ + object + gpio_bitfield_main_cpu1.obj + gpio_bitfield_main_cpu1.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./device/ + object + F2837xD_CodeStartBranch.obj + F2837xD_CodeStartBranch.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/./device/ + object + device.obj + device.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/ + object + <internal> + <internal> + + + /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/ + archive + driverlib_eabi.lib + gpio.obj + + + /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/ + archive + driverlib_eabi.lib + sysctl.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + boot28.asm.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + fd_cmp28.asm.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + fs_div28.asm.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + fs_tofdfpu32.asm.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + pre_init.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + autoinit.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + copy_zero_init.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + copy_decompress_none.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + copy_decompress_lzss.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + exit.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + _lock.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + args_main.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + memset.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + cpy_tbl.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + memcpy.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + startup.c.obj + + + + + codestart + 0x0 + true + true + 0x0 + 0x2 + 0x1 + + + + .text + 0x8000 + true + true + 0x8000 + 0x2a + 0x1 + + + + .text + 0x802a + true + true + 0x802a + 0x29 + 0x1 + + + + .text + 0x8053 + true + true + 0x8053 + 0x25 + 0x1 + + + + .text + 0x8078 + true + true + 0x8078 + 0x1c + 0x1 + + + + .text + 0x8094 + true + true + 0x8094 + 0x17 + 0x1 + + + + .text + 0x80ab + true + true + 0x80ab + 0x12 + 0x1 + + + + .text + 0x80bd + true + true + 0x80bd + 0x9 + 0x1 + + + + .text + 0x80c6 + true + true + 0x80c6 + 0x8 + 0x1 + + + + .text:decompress:none + 0x80ce + true + true + 0x80ce + 0x8 + 0x1 + + + + .text + 0x80d6 + true + true + 0x80d6 + 0x2 + 0x1 + + + + .text + 0x80d8 + true + true + 0x80d8 + 0x1 + 0x1 + + + + .text + 0xb000 + true + true + 0xb000 + 0x4bb + 0x1 + + + + .text + 0xb4bb + true + true + 0xb4bb + 0x244 + 0x1 + + + + .text + 0xb6ff + true + true + 0xb6ff + 0x88 + 0x1 + + + + .text:decompress:lzss + 0xb787 + true + true + 0xb787 + 0x2e + 0x1 + + + + .text:__TI_auto_init_nobinit_nopinit + 0xb7b5 + true + true + 0xb7b5 + 0x2b + 0x1 + + + + .text + 0xb7e0 + true + true + 0xb7e0 + 0x20 + 0x1 + + + + .cinit..data.load + 0x124 + true + 0x124 + 0x8 + 0x1 + + + __TI_handler_table + 0x12c + true + 0x12c + 0x4 + 0x2 + + + __TI_cinit_table + 0x130 + true + 0x130 + 0x4 + 0x2 + + + .stack + true + true + 0x400 + 0x0 + 0x1 + + + + .stack + true + true + 0x400 + 0x0 + 0x2 + + + .const + 0xa80a + true + 0xa80a + 0x8 + 0x2 + + + + .data + 0xa800 + true + 0xa800 + 0x6 + 0x2 + + + + .data:_lock + 0xa806 + true + 0xa806 + 0x2 + 0x2 + + + + .data:_unlock + 0xa808 + true + 0xa808 + 0x2 + 0x2 + + + + AnalogSubsysRegsFile + true + true + 0x5d180 + 0x3e + 0x2 + + + + ClkCfgRegsFile + true + true + 0x5d200 + 0x32 + 0x2 + + + + CpuTimer1RegsFile + true + true + 0xc08 + 0x8 + 0x2 + + + + CpuTimer2RegsFile + true + true + 0xc10 + 0x8 + 0x2 + + + + CpuSysRegsFile + true + true + 0x5d300 + 0x82 + 0x2 + + + + DcsmZ1RegsFile + true + true + 0x5f000 + 0x22 + 0x2 + + + + DcsmZ2RegsFile + true + true + 0x5f040 + 0x22 + 0x2 + + + + DevCfgRegsFile + true + true + 0x5d000 + 0x12e + 0x2 + + + + FlashPumpSemaphoreRegsFile + true + true + 0x50024 + 0x2 + 0x2 + + + + GpioCtrlRegsFile + true + true + 0x7c00 + 0x180 + 0x2 + + + + GpioDataRegsFile + true + true + 0x7f00 + 0x30 + 0x2 + + + + InputXbarRegsFile + true + true + 0x7900 + 0x20 + 0x2 + + + + WdRegsFile + true + true + 0x7000 + 0x2b + 0x1 + + + + .debug_types + 0x0 + 0x0 + 0x5ffbe + 0x0 + + + + .debug_types + 0x5ffbe + 0x5ffbe + 0x5a + 0x0 + + + + .debug_types + 0x60018 + 0x60018 + 0x2f + 0x0 + + + + .debug_types + 0x0 + 0x0 + 0x0 + 0x0 + + + + .debug_types + 0x0 + 0x0 + 0x0 + 0x0 + + + + .debug_types + 0x60047 + 0x60047 + 0x563 + 0x0 + + + + .debug_types + 0x605aa + 0x605aa + 0x1c8 + 0x0 + + + + .debug_types + 0x60772 + 0x60772 + 0x191 + 0x0 + + + + .debug_types + 0x60903 + 0x60903 + 0xbf + 0x0 + + + + .debug_types + 0x609c2 + 0x609c2 + 0x2f + 0x0 + + + + .debug_types + 0x609f1 + 0x609f1 + 0xe1 + 0x0 + + + + .debug_types + 0x60ad2 + 0x60ad2 + 0xe3 + 0x0 + + + + .debug_types + 0x0 + 0x0 + 0x0 + 0x0 + + + + .debug_info + 0x0 + 0x0 + 0x139 + 0x0 + + + + .debug_info + 0x139 + 0x139 + 0x127 + 0x0 + + + + .debug_info + 0x260 + 0x260 + 0x127 + 0x0 + + + + .debug_info + 0x387 + 0x387 + 0x127 + 0x0 + + + + .debug_info + 0x4ae + 0x4ae + 0x121 + 0x0 + + + + .debug_info + 0x5cf + 0x5cf + 0x121 + 0x0 + + + + .debug_info + 0x6f0 + 0x6f0 + 0x119 + 0x0 + + + + .debug_info + 0x809 + 0x809 + 0x125 + 0x0 + + + + .debug_info + 0x92e + 0x92e + 0x121 + 0x0 + + + + .debug_info + 0xa4f + 0xa4f + 0x12c + 0x0 + + + + .debug_info + 0xb7b + 0xb7b + 0x121 + 0x0 + + + + .debug_info + 0xc9c + 0xc9c + 0x121 + 0x0 + + + + .debug_info + 0xdbd + 0xdbd + 0x125 + 0x0 + + + + .debug_info + 0xee2 + 0xee2 + 0xacd + 0x0 + + + + .debug_info + 0x19af + 0x19af + 0xc46 + 0x0 + + + + .debug_info + 0x25f5 + 0x25f5 + 0x14f + 0x0 + + + + .debug_info + 0x2744 + 0x2744 + 0x133 + 0x0 + + + + .debug_info + 0x2877 + 0x2877 + 0x134 + 0x0 + + + + .debug_info + 0x29ab + 0x29ab + 0x148 + 0x0 + + + + .debug_info + 0x2af3 + 0x2af3 + 0x121 + 0x0 + + + + .debug_info + 0x2c14 + 0x2c14 + 0x117 + 0x0 + + + + .debug_info + 0x2d2b + 0x2d2b + 0x11b + 0x0 + + + + .debug_info + 0x2e46 + 0x2e46 + 0x13d + 0x0 + + + + .debug_info + 0x2f83 + 0x2f83 + 0x1af + 0x0 + + + + .debug_info + 0x3132 + 0x3132 + 0x1a7 + 0x0 + + + + .debug_info + 0x32d9 + 0x32d9 + 0x1fc + 0x0 + + + + .debug_info + 0x34d5 + 0x34d5 + 0x18e + 0x0 + + + + .debug_info + 0x3663 + 0x3663 + 0x199 + 0x0 + + + + .debug_info + 0x37fc + 0x37fc + 0xf7 + 0x0 + + + + .debug_info + 0x38f3 + 0x38f3 + 0xfb + 0x0 + + + + .debug_info + 0x39ee + 0x39ee + 0x1f3 + 0x0 + + + + .debug_info + 0x3be1 + 0x3be1 + 0x15d + 0x0 + + + + .debug_info + 0x3d3e + 0x3d3e + 0x18b + 0x0 + + + + .debug_info + 0x3ec9 + 0x3ec9 + 0x137 + 0x0 + + + + .debug_info + 0x4000 + 0x4000 + 0xd3 + 0x0 + + + .debug_line + 0x0 + 0x0 + 0x44 + 0x0 + + + + .debug_line + 0x44 + 0x44 + 0x44 + 0x0 + + + + .debug_line + 0x88 + 0x88 + 0x44 + 0x0 + + + + .debug_line + 0xcc + 0xcc + 0x44 + 0x0 + + + + .debug_line + 0x110 + 0x110 + 0x44 + 0x0 + + + + .debug_line + 0x154 + 0x154 + 0x44 + 0x0 + + + + .debug_line + 0x198 + 0x198 + 0x44 + 0x0 + + + + .debug_line + 0x1dc + 0x1dc + 0x44 + 0x0 + + + + .debug_line + 0x220 + 0x220 + 0x44 + 0x0 + + + + .debug_line + 0x264 + 0x264 + 0x44 + 0x0 + + + + .debug_line + 0x2a8 + 0x2a8 + 0x44 + 0x0 + + + + .debug_line + 0x2ec + 0x2ec + 0x44 + 0x0 + + + + .debug_line + 0x330 + 0x330 + 0x44 + 0x0 + + + + .debug_line + 0x374 + 0x374 + 0xa8 + 0x0 + + + + .debug_line + 0x41c + 0x41c + 0x23e + 0x0 + + + + .debug_line + 0x65a + 0x65a + 0x147 + 0x0 + + + + .debug_line + 0x7a1 + 0x7a1 + 0x544 + 0x0 + + + + .debug_line + 0xce5 + 0xce5 + 0x276 + 0x0 + + + + .debug_line + 0xf5b + 0xf5b + 0x60 + 0x0 + + + + .debug_line + 0xfbb + 0xfbb + 0xea + 0x0 + + + + .debug_line + 0x10a5 + 0x10a5 + 0x55 + 0x0 + + + + .debug_line + 0x10fa + 0x10fa + 0x5d + 0x0 + + + + .debug_line + 0x1157 + 0x1157 + 0x4f + 0x0 + + + + .debug_line + 0x11a6 + 0x11a6 + 0x61 + 0x0 + + + + .debug_line + 0x1207 + 0x1207 + 0xae + 0x0 + + + + .debug_line + 0x12b5 + 0x12b5 + 0x59 + 0x0 + + + + .debug_line + 0x130e + 0x130e + 0x3f + 0x0 + + + + .debug_line + 0x134d + 0x134d + 0x21 + 0x0 + + + + .debug_line + 0x136e + 0x136e + 0x74 + 0x0 + + + + .debug_line + 0x13e2 + 0x13e2 + 0x21 + 0x0 + + + + .debug_line + 0x1403 + 0x1403 + 0x57 + 0x0 + + + + .debug_line + 0x145a + 0x145a + 0x21 + 0x0 + + + + .debug_line + 0x147b + 0x147b + 0x9a + 0x0 + + + + .debug_line + 0x1515 + 0x1515 + 0x21 + 0x0 + + + + .debug_line + 0x1536 + 0x1536 + 0x2b + 0x0 + + + + .debug_line + 0x1561 + 0x1561 + 0x66 + 0x0 + + + + .debug_line + 0x15c7 + 0x15c7 + 0x21 + 0x0 + + + + .debug_line + 0x15e8 + 0x15e8 + 0x2c + 0x0 + + + + .debug_line + 0x1614 + 0x1614 + 0x2c + 0x0 + + + + .debug_line + 0x1640 + 0x1640 + 0x5f + 0x0 + + + + .debug_line + 0x169f + 0x169f + 0x21 + 0x0 + + + + .debug_line + 0x16c0 + 0x16c0 + 0x50 + 0x0 + + + + .debug_line + 0x1710 + 0x1710 + 0x30 + 0x0 + + + + .debug_line + 0x1740 + 0x1740 + 0x57 + 0x0 + + + + .debug_line + 0x1797 + 0x1797 + 0x21 + 0x0 + + + + .debug_line + 0x17b8 + 0x17b8 + 0x3b + 0x0 + + + + .debug_line + 0x17f3 + 0x17f3 + 0x21 + 0x0 + + + + .debug_abbrev + 0x0 + 0x0 + 0x26 + 0x0 + + + + .debug_abbrev + 0x26 + 0x26 + 0x26 + 0x0 + + + + .debug_abbrev + 0x4c + 0x4c + 0x26 + 0x0 + + + + .debug_abbrev + 0x72 + 0x72 + 0x26 + 0x0 + + + + .debug_abbrev + 0x98 + 0x98 + 0x26 + 0x0 + + + + .debug_abbrev + 0xbe + 0xbe + 0x26 + 0x0 + + + + .debug_abbrev + 0xe4 + 0xe4 + 0x26 + 0x0 + + + + .debug_abbrev + 0x10a + 0x10a + 0x26 + 0x0 + + + + .debug_abbrev + 0x130 + 0x130 + 0x26 + 0x0 + + + + .debug_abbrev + 0x156 + 0x156 + 0x26 + 0x0 + + + + .debug_abbrev + 0x17c + 0x17c + 0x26 + 0x0 + + + + .debug_abbrev + 0x1a2 + 0x1a2 + 0x26 + 0x0 + + + + .debug_abbrev + 0x1c8 + 0x1c8 + 0x26 + 0x0 + + + + .debug_abbrev + 0x1ee + 0x1ee + 0x182 + 0x0 + + + + .debug_abbrev + 0x370 + 0x370 + 0xd5 + 0x0 + + + + .debug_abbrev + 0x445 + 0x445 + 0x14b + 0x0 + + + + .debug_abbrev + 0x590 + 0x590 + 0xef + 0x0 + + + + .debug_abbrev + 0x67f + 0x67f + 0x165 + 0x0 + + + + .debug_abbrev + 0x7e4 + 0x7e4 + 0x54 + 0x0 + + + + .debug_abbrev + 0x838 + 0x838 + 0x12f + 0x0 + + + + .debug_abbrev + 0x967 + 0x967 + 0x25 + 0x0 + + + + .debug_abbrev + 0x98c + 0x98c + 0x25 + 0x0 + + + + .debug_abbrev + 0x9b1 + 0x9b1 + 0x3d + 0x0 + + + + .debug_abbrev + 0x9ee + 0x9ee + 0x3b + 0x0 + + + + .debug_abbrev + 0xa29 + 0xa29 + 0x3b + 0x0 + + + + .debug_abbrev + 0xa64 + 0xa64 + 0x3b + 0x0 + + + + .debug_abbrev + 0xa9f + 0xa9f + 0x4b + 0x0 + + + + .debug_abbrev + 0xaea + 0xaea + 0x1c + 0x0 + + + + .debug_abbrev + 0xb06 + 0xb06 + 0x71 + 0x0 + + + + .debug_abbrev + 0xb77 + 0xb77 + 0xb3 + 0x0 + + + + .debug_abbrev + 0xc2a + 0xc2a + 0x6d + 0x0 + + + + .debug_abbrev + 0xc97 + 0xc97 + 0x44 + 0x0 + + + + .debug_abbrev + 0xcdb + 0xcdb + 0x5f + 0x0 + + + + .debug_abbrev + 0xd3a + 0xd3a + 0x44 + 0x0 + + + + .debug_abbrev + 0xd7e + 0xd7e + 0x28 + 0x0 + + + + .debug_abbrev + 0xda6 + 0xda6 + 0xa0 + 0x0 + + + + .debug_abbrev + 0xe46 + 0xe46 + 0x57 + 0x0 + + + + .debug_abbrev + 0xe9d + 0xe9d + 0x28 + 0x0 + + + + .debug_abbrev + 0xec5 + 0xec5 + 0x28 + 0x0 + + + + .debug_abbrev + 0xeed + 0xeed + 0x5f + 0x0 + + + + .debug_abbrev + 0xf4c + 0xf4c + 0x3a + 0x0 + + + + .debug_abbrev + 0xf86 + 0xf86 + 0x64 + 0x0 + + + + .debug_abbrev + 0xfea + 0xfea + 0x79 + 0x0 + + + + .debug_abbrev + 0x1063 + 0x1063 + 0x61 + 0x0 + + + + .debug_abbrev + 0x10c4 + 0x10c4 + 0x44 + 0x0 + + + + .debug_abbrev + 0x1108 + 0x1108 + 0x49 + 0x0 + + + + .debug_abbrev + 0x1151 + 0x1151 + 0x1c + 0x0 + + + + .debug_abbrev + 0x116d + 0x116d + 0xf + 0x0 + + + .debug_str + 0x0 + 0x0 + 0x6a + 0x0 + + + + .debug_str + 0x6a + 0x6a + 0x6a + 0x0 + + + + .debug_str + 0xd4 + 0xd4 + 0x6a + 0x0 + + + + .debug_str + 0x13e + 0x13e + 0x6a + 0x0 + + + + .debug_str + 0x1a8 + 0x1a8 + 0x6a + 0x0 + + + + .debug_str + 0x212 + 0x212 + 0x6a + 0x0 + + + + .debug_str + 0x27c + 0x27c + 0x6a + 0x0 + + + + .debug_str + 0x2e6 + 0x2e6 + 0x6a + 0x0 + + + + .debug_str + 0x350 + 0x350 + 0x6a + 0x0 + + + + .debug_str + 0x3ba + 0x3ba + 0x6a + 0x0 + + + + .debug_str + 0x424 + 0x424 + 0x6a + 0x0 + + + + .debug_str + 0x48e + 0x48e + 0x6a + 0x0 + + + + .debug_str + 0x4f8 + 0x4f8 + 0x6a + 0x0 + + + + .debug_pubnames + 0x0 + 0x0 + 0x2d + 0x0 + + + + .debug_pubnames + 0x2d + 0x2d + 0x24 + 0x0 + + + + .debug_pubnames + 0x51 + 0x51 + 0x24 + 0x0 + + + + .debug_pubnames + 0x75 + 0x75 + 0x24 + 0x0 + + + + .debug_pubnames + 0x99 + 0x99 + 0x21 + 0x0 + + + + .debug_pubnames + 0xba + 0xba + 0x21 + 0x0 + + + + .debug_pubnames + 0xdb + 0xdb + 0x1d + 0x0 + + + + .debug_pubnames + 0xf8 + 0xf8 + 0x23 + 0x0 + + + + .debug_pubnames + 0x11b + 0x11b + 0x21 + 0x0 + + + + .debug_pubnames + 0x13c + 0x13c + 0x27 + 0x0 + + + + .debug_pubnames + 0x163 + 0x163 + 0x21 + 0x0 + + + + .debug_pubnames + 0x184 + 0x184 + 0x21 + 0x0 + + + + .debug_pubnames + 0x1a5 + 0x1a5 + 0x23 + 0x0 + + + + .debug_pubnames + 0x1c8 + 0x1c8 + 0x170 + 0x0 + + + + .debug_pubnames + 0x338 + 0x338 + 0x175 + 0x0 + + + + .debug_pubnames + 0x4ad + 0x4ad + 0x1b + 0x0 + + + + .debug_pubnames + 0x4c8 + 0x4c8 + 0x44 + 0x0 + + + + .debug_pubnames + 0x50c + 0x50c + 0x45 + 0x0 + + + + .debug_pubnames + 0x551 + 0x551 + 0x1f + 0x0 + + + + .debug_pubnames + 0x570 + 0x570 + 0x25 + 0x0 + + + + .debug_pubnames + 0x595 + 0x595 + 0x25 + 0x0 + + + + .debug_pubnames + 0x5ba + 0x5ba + 0x25 + 0x0 + + + + .debug_pubnames + 0x5df + 0x5df + 0x27 + 0x0 + + + + .debug_pubnames + 0x606 + 0x606 + 0x35 + 0x0 + + + + .debug_pubnames + 0x63b + 0x63b + 0x2b + 0x0 + + + + .debug_pubnames + 0x666 + 0x666 + 0x2b + 0x0 + + + + .debug_pubnames + 0x691 + 0x691 + 0x5e + 0x0 + + + + .debug_pubnames + 0x6ef + 0x6ef + 0x25 + 0x0 + + + + .debug_pubnames + 0x714 + 0x714 + 0x1c + 0x0 + + + + .debug_pubnames + 0x730 + 0x730 + 0x1e + 0x0 + + + + .debug_pubnames + 0x74e + 0x74e + 0x43 + 0x0 + + + + .debug_pubnames + 0x791 + 0x791 + 0x21 + 0x0 + + + + .debug_pubnames + 0x7b2 + 0x7b2 + 0x1d + 0x0 + + + + .debug_pubnames + 0x7cf + 0x7cf + 0x29 + 0x0 + + + + .debug_frame + 0x0 + 0x0 + 0x1a8 + 0x4 + + + + .debug_frame + 0x1a8 + 0x1a8 + 0x248 + 0x4 + + + + .debug_frame + 0x3f0 + 0x3f0 + 0x40 + 0x4 + + + + .debug_frame + 0x430 + 0x430 + 0x40 + 0x4 + + + + .debug_frame + 0x470 + 0x470 + 0x58 + 0x4 + + + + .debug_frame + 0x4c8 + 0x4c8 + 0x40 + 0x4 + + + + .debug_frame + 0x508 + 0x508 + 0x40 + 0x4 + + + + .debug_frame + 0x548 + 0x548 + 0x60 + 0x4 + + + + .debug_frame + 0x5a8 + 0x5a8 + 0x70 + 0x4 + + + + .debug_frame + 0x618 + 0x618 + 0x40 + 0x4 + + + + .debug_frame + 0x658 + 0x658 + 0x40 + 0x4 + + + + .debug_frame + 0x698 + 0x698 + 0x40 + 0x4 + + + + .debug_aranges + 0x0 + 0x0 + 0x88 + 0x0 + + + + .debug_aranges + 0x88 + 0x88 + 0xc0 + 0x0 + + + + .debug_aranges + 0x148 + 0x148 + 0x20 + 0x0 + + + + .debug_aranges + 0x168 + 0x168 + 0x20 + 0x0 + + + + .debug_aranges + 0x188 + 0x188 + 0x20 + 0x0 + + + + .debug_aranges + 0x1a8 + 0x1a8 + 0x20 + 0x0 + + + + .debug_aranges + 0x1c8 + 0x1c8 + 0x20 + 0x0 + + + + .debug_aranges + 0x1e8 + 0x1e8 + 0x20 + 0x0 + + + + .debug_aranges + 0x208 + 0x208 + 0x20 + 0x0 + + + + .debug_aranges + 0x228 + 0x228 + 0x20 + 0x0 + + + + .debug_aranges + 0x248 + 0x248 + 0x20 + 0x0 + + + + .debug_aranges + 0x268 + 0x268 + 0x20 + 0x0 + + + + .debug_aranges + 0x288 + 0x288 + 0x20 + 0x0 + + + + .debug_aranges + 0x2a8 + 0x2a8 + 0x28 + 0x0 + + + + .debug_aranges + 0x2d0 + 0x2d0 + 0x30 + 0x0 + + + + .debug_aranges + 0x300 + 0x300 + 0x20 + 0x0 + + + + .debug_aranges + 0x320 + 0x320 + 0x20 + 0x0 + + + + .debug_aranges + 0x340 + 0x340 + 0x20 + 0x0 + + + + + + codestart + 0x0 + 0x0 + 0x2 + + + + + + .text.1 + 0x8000 + 0x8000 + 0xd9 + + + + + + + + + + + + + + + + .text.2 + 0xb000 + 0xb000 + 0x800 + + + + + + + + + + + .text + + + + + + + .cinit + 0x124 + 0x124 + 0x10 + + + + + + + + .switch + 0x0 + 0x0 + + + + + .reset + 0x3fffc0 + 0x0 + + + + + .stack + 0x400 + 0x100 + + + + + + + .bss + 0x0 + 0x0 + + + + + .bss:output + 0x0 + 0x0 + + + + + .init_array + 0x0 + 0x0 + + + + + .const + 0xa80a + 0xa80a + 0x8 + + + + + + .data + 0xa800 + 0xa + + + + + + + + .sysmem + 0x0 + 0x0 + + + + + Filter_RegsFile + 0x0 + 0x0 + + + + + ramgs0 + 0x0 + 0x0 + + + + + ramgs1 + 0x0 + 0x0 + + + + + .TI.ramfunc + 0x0 + 0x0 + + + + + PUTBUFFER + 0x0 + 0x0 + + + + + PUTWRITEIDX + 0x0 + 0x0 + + + + + GETREADIDX + 0x0 + 0x0 + + + + + GROUP_1 + 0x0 + 0x0 + + + + + + true + + + GETBUFFER + 0x3f800 + 0x0 + + + + + GETWRITEIDX + 0x3f800 + 0x0 + + + + + PUTREADIDX + 0x3f800 + 0x0 + + + + + GROUP_2 + 0x3f800 + 0x0 + + + + + + true + + + Filter1_RegsFile + 0xd000 + 0xd000 + 0x0 + + + + + Filter2_RegsFile + 0xe000 + 0xe000 + 0x0 + + + + + Filter3_RegsFile + 0xf000 + 0xf000 + 0x0 + + + + + Filter4_RegsFile + 0x10000 + 0x10000 + 0x0 + + + + + Difference_RegsFile + 0x11000 + 0x11000 + 0x0 + + + + + PieVectTableFile + 0x0 + 0x0 + + + + + EmuKeyVar + 0x0 + 0x0 + + + + + EmuBModeVar + 0x0 + 0x0 + + + + + EmuBootPinsVar + 0x0 + 0x0 + + + + + FlashCallbackVar + 0x0 + 0x0 + + + + + FlashScalingVar + 0x0 + 0x0 + + + + + GROUP_4 + 0x0 + 0x0 + + + + + + + + true + + + UNION_3 + 0x0 + 0x0 + + + + + + + AccessProtectionRegsFile + 0x0 + 0x0 + + + + + AdcaRegsFile + 0x0 + 0x0 + + + + + AdcbRegsFile + 0x0 + 0x0 + + + + + AdccRegsFile + 0x0 + 0x0 + + + + + AdcdRegsFile + 0x0 + 0x0 + + + + + AdcaResultRegsFile + 0x0 + 0x0 + + + + + AdcbResultRegsFile + 0x0 + 0x0 + + + + + AdccResultRegsFile + 0x0 + 0x0 + + + + + AdcdResultRegsFile + 0x0 + 0x0 + + + + + AnalogSubsysRegsFile + 0x5d180 + 0x3e + + + + + + CanaRegsFile + 0x0 + 0x0 + + + + + CanbRegsFile + 0x0 + 0x0 + + + + + Cla1RegsFile + 0x0 + 0x0 + + + + + Clb1DataExchRegsFile + 0x0 + 0x0 + + + + + Clb2DataExchRegsFile + 0x0 + 0x0 + + + + + Clb3DataExchRegsFile + 0x0 + 0x0 + + + + + Clb4DataExchRegsFile + 0x0 + 0x0 + + + + + Clb1LogicCfgRegsFile + 0x0 + 0x0 + + + + + Clb2LogicCfgRegsFile + 0x0 + 0x0 + + + + + Clb3LogicCfgRegsFile + 0x0 + 0x0 + + + + + Clb4LogicCfgRegsFile + 0x0 + 0x0 + + + + + Clb1LogicCtrlRegsFile + 0x0 + 0x0 + + + + + Clb2LogicCtrlRegsFile + 0x0 + 0x0 + + + + + Clb3LogicCtrlRegsFile + 0x0 + 0x0 + + + + + Clb4LogicCtrlRegsFile + 0x0 + 0x0 + + + + + ClbXbarRegsFile + 0x0 + 0x0 + + + + + ClkCfgRegsFile + 0x5d200 + 0x32 + + + + + + Cmpss1RegsFile + 0x0 + 0x0 + + + + + Cmpss2RegsFile + 0x0 + 0x0 + + + + + Cmpss3RegsFile + 0x0 + 0x0 + + + + + Cmpss4RegsFile + 0x0 + 0x0 + + + + + Cmpss5RegsFile + 0x0 + 0x0 + + + + + Cmpss6RegsFile + 0x0 + 0x0 + + + + + Cmpss7RegsFile + 0x0 + 0x0 + + + + + Cmpss8RegsFile + 0x0 + 0x0 + + + + + CpuTimer0RegsFile + 0x0 + 0x0 + + + + + CpuTimer1RegsFile + 0xc08 + 0x8 + + + + + + CpuTimer2RegsFile + 0xc10 + 0x8 + + + + + + CpuSysRegsFile + 0x5d300 + 0x82 + + + + + + DacaRegsFile + 0x0 + 0x0 + + + + + DacbRegsFile + 0x0 + 0x0 + + + + + DaccRegsFile + 0x0 + 0x0 + + + + + DcsmCommonRegsFile + 0x0 + 0x0 + + + + + DcsmZ1RegsFile + 0x5f000 + 0x22 + + + + + + DcsmZ2RegsFile + 0x5f040 + 0x22 + + + + + + DevCfgRegsFile + 0x5d000 + 0x12e + + + + + + DmaClaSrcSelRegsFile + 0x0 + 0x0 + + + + + DmaRegsFile + 0x0 + 0x0 + + + + + ECap1RegsFile + 0x0 + 0x0 + + + + + ECap2RegsFile + 0x0 + 0x0 + + + + + ECap3RegsFile + 0x0 + 0x0 + + + + + ECap4RegsFile + 0x0 + 0x0 + + + + + ECap5RegsFile + 0x0 + 0x0 + + + + + ECap6RegsFile + 0x0 + 0x0 + + + + + Emif1ConfigRegsFile + 0x0 + 0x0 + + + + + Emif2ConfigRegsFile + 0x0 + 0x0 + + + + + Emif1RegsFile + 0x0 + 0x0 + + + + + Emif2RegsFile + 0x0 + 0x0 + + + + + EPwm1RegsFile + 0x0 + 0x0 + + + + + EPwm2RegsFile + 0x0 + 0x0 + + + + + EPwm3RegsFile + 0x0 + 0x0 + + + + + EPwm4RegsFile + 0x0 + 0x0 + + + + + EPwm5RegsFile + 0x0 + 0x0 + + + + + EPwm6RegsFile + 0x0 + 0x0 + + + + + EPwm7RegsFile + 0x0 + 0x0 + + + + + EPwm8RegsFile + 0x0 + 0x0 + + + + + EPwm9RegsFile + 0x0 + 0x0 + + + + + EPwm10RegsFile + 0x0 + 0x0 + + + + + EPwm11RegsFile + 0x0 + 0x0 + + + + + EPwm12RegsFile + 0x0 + 0x0 + + + + + EPwmXbarRegsFile + 0x0 + 0x0 + + + + + EQep1RegsFile + 0x0 + 0x0 + + + + + EQep2RegsFile + 0x0 + 0x0 + + + + + EQep3RegsFile + 0x0 + 0x0 + + + + + Flash0CtrlRegsFile + 0x0 + 0x0 + + + + + Flash0EccRegsFile + 0x0 + 0x0 + + + + + FlashPumpSemaphoreRegsFile + 0x50024 + 0x2 + + + + + + GpioCtrlRegsFile + 0x7c00 + 0x180 + + + + + + GpioDataRegsFile + 0x7f00 + 0x30 + + + + + + I2caRegsFile + 0x0 + 0x0 + + + + + I2cbRegsFile + 0x0 + 0x0 + + + + + InputXbarRegsFile + 0x7900 + 0x20 + + + + + + IpcRegsFile + 0x0 + 0x0 + + + + + MemoryErrorRegsFile + 0x0 + 0x0 + + + + + MemCfgRegsFile + 0x0 + 0x0 + + + + + McbspaRegsFile + 0x0 + 0x0 + + + + + McbspbRegsFile + 0x0 + 0x0 + + + + + NmiIntruptRegsFile + 0x0 + 0x0 + + + + + OutputXbarRegsFile + 0x0 + 0x0 + + + + + PieCtrlRegsFile + 0x0 + 0x0 + + + + + RomPrefetchRegsFile + 0x0 + 0x0 + + + + + RomWaitStateRegsFile + 0x0 + 0x0 + + + + + SciaRegsFile + 0x0 + 0x0 + + + + + ScibRegsFile + 0x0 + 0x0 + + + + + ScicRegsFile + 0x0 + 0x0 + + + + + ScidRegsFile + 0x0 + 0x0 + + + + + Sdfm1RegsFile + 0x0 + 0x0 + + + + + Sdfm2RegsFile + 0x0 + 0x0 + + + + + SpiaRegsFile + 0x0 + 0x0 + + + + + SpibRegsFile + 0x0 + 0x0 + + + + + SpicRegsFile + 0x0 + 0x0 + + + + + SyncSocRegsFile + 0x0 + 0x0 + + + + + UppRegsFile + 0x0 + 0x0 + + + + + WdRegsFile + 0x7000 + 0x2b + + + + + + UidRegsFile + 0x0 + 0x0 + + + + + XbarRegsFile + 0x0 + 0x0 + + + + + XintRegsFile + 0x0 + 0x0 + + + + + .ppdata + 0x0 + 0x0 + + + + + .debug_types + 0x0 + 0x0 + 0x60bb5 + + + + + + + + + + + + + + + + + + .debug_info + 0x0 + 0x0 + 0x40d3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .debug_line + 0x0 + 0x0 + 0x1814 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .debug_abbrev + 0x0 + 0x0 + 0x117c + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .debug_str + 0x0 + 0x0 + 0x562 + + + + + + + + + + + + + + + + + + .debug_pubnames + 0x0 + 0x0 + 0x7f8 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .debug_frame + 0x0 + 0x0 + 0x6d8 + + + + + + + + + + + + + + + + + .debug_aranges + 0x0 + 0x0 + 0x360 + + + + + + + + + + + + + + + + + + + + + + + SEGMENT_0 + 0x0 + 0x0 + 0x2 + 0x5 + + + + + + SEGMENT_1 + 0x124 + 0x124 + 0x10 + 0x4 + + + + + + SEGMENT_2 + 0x8000 + 0x8000 + 0xd9 + 0x5 + + + + + + SEGMENT_3 + 0xb000 + 0xb000 + 0x800 + 0x5 + + + + + + SEGMENT_4 + 0x400 + 0x100 + 0x6 + + + + + + SEGMENT_5 + 0xc08 + 0x10 + 0x6 + + + + + + + SEGMENT_6 + 0x7000 + 0x2b + 0x6 + + + + + + SEGMENT_7 + 0x7900 + 0x20 + 0x6 + + + + + + SEGMENT_8 + 0x7c00 + 0x180 + 0x6 + + + + + + SEGMENT_9 + 0x7f00 + 0x30 + 0x6 + + + + + + SEGMENT_10 + 0xa800 + 0xa + 0x6 + + + + + + SEGMENT_11 + 0xa80a + 0xa80a + 0x8 + 0x4 + + + + + + SEGMENT_12 + 0x50024 + 0x2 + 0x6 + + + + + + SEGMENT_13 + 0x5d000 + 0x12e + 0x6 + + + + + + SEGMENT_14 + 0x5d180 + 0x3e + 0x6 + + + + + + SEGMENT_15 + 0x5d200 + 0x32 + 0x6 + + + + + + SEGMENT_16 + 0x5d300 + 0x82 + 0x6 + + + + + + SEGMENT_17 + 0x5f000 + 0x22 + 0x6 + + + + + + SEGMENT_18 + 0x5f040 + 0x22 + 0x6 + + + + + + + + BEGIN + 0x0 + 0x0 + 0x2 + 0x2 + 0x0 + RWIX + + + 0x0 + 0x2 + + + + + + RAMM0 + 0x0 + 0x123 + 0x2dd + 0x10 + 0x2cd + RWIX + + + 0x123 + 0x1 + + + 0x124 + 0x10 + + + + 0x134 + 0x2cc + + + + + RAMLS0 + 0x0 + 0x8000 + 0x800 + 0xd9 + 0x727 + RWIX + + + 0x8000 + 0xd9 + + + + 0x80d9 + 0x727 + + + + + RAMLS1 + 0x0 + 0x8800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS2 + 0x0 + 0x9000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS3 + 0x0 + 0x9800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS4 + 0x0 + 0xa000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMD0 + 0x0 + 0xb000 + 0x800 + 0x800 + 0x0 + RWIX + + + 0xb000 + 0x800 + + + + + + FLASHA + 0x0 + 0x80002 + 0x1ffe + 0x0 + 0x1ffe + RWIX + + + + + FLASHB + 0x0 + 0x82000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHC + 0x0 + 0x84000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHD + 0x0 + 0x86000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHE + 0x0 + 0x88000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHF + 0x0 + 0x90000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHG + 0x0 + 0x98000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHH + 0x0 + 0xa0000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHI + 0x0 + 0xa8000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHJ + 0x0 + 0xb0000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHK + 0x0 + 0xb8000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHL + 0x0 + 0xba000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHM + 0x0 + 0xbc000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHN + 0x0 + 0xbe000 + 0x1ff0 + 0x0 + 0x1ff0 + RWIX + + + + + RESET + 0x0 + 0x3fffc0 + 0x2 + 0x0 + 0x2 + RWIX + + + + + BOOT_RSVD + 0x1 + 0x2 + 0x121 + 0x0 + 0x121 + RWIX + + + + + RAMM1 + 0x1 + 0x400 + 0x3f8 + 0x100 + 0x2f8 + RWIX + + + 0x400 + 0x100 + + + + 0x500 + 0x2f8 + + + + + ADCARESULT + 0x1 + 0xb00 + 0x18 + 0x0 + 0x18 + RWIX + + + + + ADCBRESULT + 0x1 + 0xb20 + 0x18 + 0x0 + 0x18 + RWIX + + + + + ADCCRESULT + 0x1 + 0xb40 + 0x18 + 0x0 + 0x18 + RWIX + + + + + ADCDRESULT + 0x1 + 0xb60 + 0x18 + 0x0 + 0x18 + RWIX + + + + + CPUTIMER0 + 0x1 + 0xc00 + 0x8 + 0x0 + 0x8 + RWIX + + + + + CPUTIMER1 + 0x1 + 0xc08 + 0x8 + 0x8 + 0x0 + RWIX + + + 0xc08 + 0x8 + + + + + + CPUTIMER2 + 0x1 + 0xc10 + 0x8 + 0x8 + 0x0 + RWIX + + + 0xc10 + 0x8 + + + + + + PIECTRL + 0x1 + 0xce0 + 0x1a + 0x0 + 0x1a + RWIX + + + + + PIEVECTTABLE + 0x1 + 0xd00 + 0x200 + 0x0 + 0x200 + RWIX + + + + + DMA + 0x1 + 0x1000 + 0x200 + 0x0 + 0x200 + RWIX + + + + + CLA1 + 0x1 + 0x1400 + 0x80 + 0x0 + 0x80 + RWIX + + + + + CLB1LOGICCFG + 0x1 + 0x3000 + 0x52 + 0x0 + 0x52 + RWIX + + + + + CLB1LOGICCTRL + 0x1 + 0x3100 + 0x40 + 0x0 + 0x40 + RWIX + + + + + CLB1DATAEXCH + 0x1 + 0x3200 + 0x200 + 0x0 + 0x200 + RWIX + + + + + CLB2LOGICCFG + 0x1 + 0x3400 + 0x52 + 0x0 + 0x52 + RWIX + + + + + CLB2LOGICCTRL + 0x1 + 0x3500 + 0x40 + 0x0 + 0x40 + RWIX + + + + + CLB2DATAEXCH + 0x1 + 0x3600 + 0x200 + 0x0 + 0x200 + RWIX + + + + + CLB3LOGICCFG + 0x1 + 0x3800 + 0x52 + 0x0 + 0x52 + RWIX + + + + + CLB3LOGICCTRL + 0x1 + 0x3900 + 0x40 + 0x0 + 0x40 + RWIX + + + + + CLB3DATAEXCH + 0x1 + 0x3a00 + 0x200 + 0x0 + 0x200 + RWIX + + + + + CLB4LOGICCFG + 0x1 + 0x3c00 + 0x52 + 0x0 + 0x52 + RWIX + + + + + CLB4LOGICCTRL + 0x1 + 0x3d00 + 0x40 + 0x0 + 0x40 + RWIX + + + + + CLB4DATAEXCH + 0x1 + 0x3e00 + 0x200 + 0x0 + 0x200 + RWIX + + + + + EPWM1 + 0x1 + 0x4000 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM2 + 0x1 + 0x4100 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM3 + 0x1 + 0x4200 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM4 + 0x1 + 0x4300 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM5 + 0x1 + 0x4400 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM6 + 0x1 + 0x4500 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM7 + 0x1 + 0x4600 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM8 + 0x1 + 0x4700 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM9 + 0x1 + 0x4800 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM10 + 0x1 + 0x4900 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM11 + 0x1 + 0x4a00 + 0x100 + 0x0 + 0x100 + RWIX + + + + + EPWM12 + 0x1 + 0x4b00 + 0x100 + 0x0 + 0x100 + RWIX + + + + + ECAP1 + 0x1 + 0x5000 + 0x20 + 0x0 + 0x20 + RWIX + + + + + ECAP2 + 0x1 + 0x5020 + 0x20 + 0x0 + 0x20 + RWIX + + + + + ECAP3 + 0x1 + 0x5040 + 0x20 + 0x0 + 0x20 + RWIX + + + + + ECAP4 + 0x1 + 0x5060 + 0x20 + 0x0 + 0x20 + RWIX + + + + + ECAP5 + 0x1 + 0x5080 + 0x20 + 0x0 + 0x20 + RWIX + + + + + ECAP6 + 0x1 + 0x50a0 + 0x20 + 0x0 + 0x20 + RWIX + + + + + EQEP1 + 0x1 + 0x5100 + 0x22 + 0x0 + 0x22 + RWIX + + + + + EQEP2 + 0x1 + 0x5140 + 0x22 + 0x0 + 0x22 + RWIX + + + + + EQEP3 + 0x1 + 0x5180 + 0x22 + 0x0 + 0x22 + RWIX + + + + + DACA + 0x1 + 0x5c00 + 0x8 + 0x0 + 0x8 + RWIX + + + + + DACB + 0x1 + 0x5c10 + 0x8 + 0x0 + 0x8 + RWIX + + + + + DACC + 0x1 + 0x5c20 + 0x8 + 0x0 + 0x8 + RWIX + + + + + CMPSS1 + 0x1 + 0x5c80 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS2 + 0x1 + 0x5ca0 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS3 + 0x1 + 0x5cc0 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS4 + 0x1 + 0x5ce0 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS5 + 0x1 + 0x5d00 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS6 + 0x1 + 0x5d20 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS7 + 0x1 + 0x5d40 + 0x20 + 0x0 + 0x20 + RWIX + + + + + CMPSS8 + 0x1 + 0x5d60 + 0x20 + 0x0 + 0x20 + RWIX + + + + + SDFM1 + 0x1 + 0x5e00 + 0x80 + 0x0 + 0x80 + RWIX + + + + + SDFM2 + 0x1 + 0x5e80 + 0x80 + 0x0 + 0x80 + RWIX + + + + + MCBSPA + 0x1 + 0x6000 + 0x24 + 0x0 + 0x24 + RWIX + + + + + MCBSPB + 0x1 + 0x6040 + 0x24 + 0x0 + 0x24 + RWIX + + + + + SPIA + 0x1 + 0x6100 + 0x10 + 0x0 + 0x10 + RWIX + + + + + SPIB + 0x1 + 0x6110 + 0x10 + 0x0 + 0x10 + RWIX + + + + + SPIC + 0x1 + 0x6120 + 0x10 + 0x0 + 0x10 + RWIX + + + + + UPP + 0x1 + 0x6200 + 0x48 + 0x0 + 0x48 + RWIX + + + + + WD + 0x1 + 0x7000 + 0x2b + 0x2b + 0x0 + RWIX + + + 0x7000 + 0x2b + + + + + + NMIINTRUPT + 0x1 + 0x7060 + 0x7 + 0x0 + 0x7 + RWIX + + + + + XINT + 0x1 + 0x7070 + 0xb + 0x0 + 0xb + RWIX + + + + + SCIA + 0x1 + 0x7200 + 0x10 + 0x0 + 0x10 + RWIX + + + + + SCIB + 0x1 + 0x7210 + 0x10 + 0x0 + 0x10 + RWIX + + + + + SCIC + 0x1 + 0x7220 + 0x10 + 0x0 + 0x10 + RWIX + + + + + SCID + 0x1 + 0x7230 + 0x10 + 0x0 + 0x10 + RWIX + + + + + I2CA + 0x1 + 0x7300 + 0x22 + 0x0 + 0x22 + RWIX + + + + + I2CB + 0x1 + 0x7340 + 0x22 + 0x0 + 0x22 + RWIX + + + + + ADCA + 0x1 + 0x7400 + 0x80 + 0x0 + 0x80 + RWIX + + + + + ADCB + 0x1 + 0x7480 + 0x80 + 0x0 + 0x80 + RWIX + + + + + ADCC + 0x1 + 0x7500 + 0x80 + 0x0 + 0x80 + RWIX + + + + + ADCD + 0x1 + 0x7580 + 0x80 + 0x0 + 0x80 + RWIX + + + + + INPUTXBAR + 0x1 + 0x7900 + 0x20 + 0x20 + 0x0 + RWIX + + + 0x7900 + 0x20 + + + + + + XBAR + 0x1 + 0x7920 + 0x20 + 0x0 + 0x20 + RWIX + + + + + SYNCSOC + 0x1 + 0x7940 + 0x6 + 0x0 + 0x6 + RWIX + + + + + DMACLASRCSEL + 0x1 + 0x7980 + 0x1a + 0x0 + 0x1a + RWIX + + + + + EPWMXBAR + 0x1 + 0x7a00 + 0x40 + 0x0 + 0x40 + RWIX + + + + + CLBXBAR + 0x1 + 0x7a40 + 0x40 + 0x0 + 0x40 + RWIX + + + + + OUTPUTXBAR + 0x1 + 0x7a80 + 0x40 + 0x0 + 0x40 + RWIX + + + + + GPIOCTRL + 0x1 + 0x7c00 + 0x180 + 0x180 + 0x0 + RWIX + + + 0x7c00 + 0x180 + + + + + + GPIODATA + 0x1 + 0x7f00 + 0x30 + 0x30 + 0x0 + RWIX + + + 0x7f00 + 0x30 + + + + + + RAMLS5 + 0x1 + 0xa800 + 0x800 + 0x12 + 0x7ee + RWIX + + + 0xa800 + 0xa + + + + 0xa80a + 0x8 + + + + 0xa812 + 0x7ee + + + + + RAMD1 + 0x1 + 0xb800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMGS0 + 0x1 + 0xc000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS1 + 0x1 + 0xd000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS2 + 0x1 + 0xe000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS3 + 0x1 + 0xf000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS4 + 0x1 + 0x10000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS5 + 0x1 + 0x11000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS6 + 0x1 + 0x12000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS7 + 0x1 + 0x13000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS8 + 0x1 + 0x14000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS9 + 0x1 + 0x15000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS10 + 0x1 + 0x16000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS11 + 0x1 + 0x17000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS12 + 0x1 + 0x18000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS13 + 0x1 + 0x19000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS14 + 0x1 + 0x1a000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS15 + 0x1 + 0x1b000 + 0xff8 + 0x0 + 0xff8 + RWIX + + + + + CPU2TOCPU1RAM + 0x1 + 0x3f800 + 0x400 + 0x0 + 0x400 + RWIX + + + + + CPU1TOCPU2RAM + 0x1 + 0x3fc00 + 0x400 + 0x0 + 0x400 + RWIX + + + + + EMIF1 + 0x1 + 0x47000 + 0x70 + 0x0 + 0x70 + RWIX + + + + + EMIF2 + 0x1 + 0x47800 + 0x70 + 0x0 + 0x70 + RWIX + + + + + CANA + 0x1 + 0x48000 + 0x200 + 0x0 + 0x200 + RWIX + + + + + CANA_MSG_RAM + 0x1 + 0x49000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + CANB + 0x1 + 0x4a000 + 0x200 + 0x0 + 0x200 + RWIX + + + + + CANB_MSG_RAM + 0x1 + 0x4b000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + IPC + 0x1 + 0x50000 + 0x24 + 0x0 + 0x24 + RWIX + + + + + FLASHPUMPSEMAPHORE + 0x1 + 0x50024 + 0x2 + 0x2 + 0x0 + RWIX + + + 0x50024 + 0x2 + + + + + + DEVCFG + 0x1 + 0x5d000 + 0x12e + 0x12e + 0x0 + RWIX + + + 0x5d000 + 0x12e + + + + + + ANALOGSUBSYS + 0x1 + 0x5d180 + 0x48 + 0x3e + 0xa + RWIX + + + 0x5d180 + 0x3e + + + + 0x5d1be + 0xa + + + + + CLKCFG + 0x1 + 0x5d200 + 0x32 + 0x32 + 0x0 + RWIX + + + 0x5d200 + 0x32 + + + + + + CPUSYS + 0x1 + 0x5d300 + 0x82 + 0x82 + 0x0 + RWIX + + + 0x5d300 + 0x82 + + + + + + ROMPREFETCH + 0x1 + 0x5e608 + 0x2 + 0x0 + 0x2 + RWIX + + + + + DCSMZ1 + 0x1 + 0x5f000 + 0x24 + 0x22 + 0x2 + RWIX + + + 0x5f000 + 0x22 + + + + 0x5f022 + 0x2 + + + + + DCSMZ2 + 0x1 + 0x5f040 + 0x24 + 0x22 + 0x2 + RWIX + + + 0x5f040 + 0x22 + + + + 0x5f062 + 0x2 + + + + + DCSMCOMMON + 0x1 + 0x5f070 + 0x8 + 0x0 + 0x8 + RWIX + + + + + MEMCFG + 0x1 + 0x5f400 + 0x80 + 0x0 + 0x80 + RWIX + + + + + EMIF1CONFIG + 0x1 + 0x5f480 + 0x20 + 0x0 + 0x20 + RWIX + + + + + EMIF2CONFIG + 0x1 + 0x5f4a0 + 0x20 + 0x0 + 0x20 + RWIX + + + + + ACCESSPROTECTION + 0x1 + 0x5f4c0 + 0x40 + 0x0 + 0x40 + RWIX + + + + + MEMORYERROR + 0x1 + 0x5f500 + 0x40 + 0x0 + 0x40 + RWIX + + + + + ROMWAITSTATE + 0x1 + 0x5f540 + 0x2 + 0x0 + 0x2 + RWIX + + + + + FLASH0CTRL + 0x1 + 0x5f800 + 0x182 + 0x0 + 0x182 + RWIX + + + + + FLASH0ECC + 0x1 + 0x5fb00 + 0x28 + 0x0 + 0x28 + RWIX + + + + + UID + 0x1 + 0x703c0 + 0x10 + 0x0 + 0x10 + RWIX + + + + + + + __TI_cinit_table + + .data + 0x124 + 0x8 + 0xa800 + 0xa + lzss + + + + + __TI_handler_table + + 0x0 + __TI_decompress_lzss + + + 0x1 + __TI_decompress_none + + + + + __TI_CINIT_Base + 0x130 + + + __TI_CINIT_Limit + 0x134 + + + __TI_CINIT_Warm + 0x134 + + + __TI_Handler_Table_Base + 0x12c + + + __TI_Handler_Table_Limit + 0x130 + + + __TI_STACK_SIZE + 0x100 + + + __TI_STACK_END + 0x500 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + ClkCfgRegs + 0x5d200 + + + + DcsmZ1Regs + 0x5f000 + + + + CpuTimer2Regs + 0xc10 + + + + GpioCtrlRegs + 0x7c00 + + + + CpuSysRegs + 0x5d300 + + + + CpuTimer1Regs + 0xc08 + + + + DevCfgRegs + 0x5d000 + + + + FlashPumpSemaphoreRegs + 0x50024 + + + + WdRegs + 0x7000 + + + + GpioDataRegs + 0x7f00 + + + + InputXbarRegs + 0x7900 + + + + DcsmZ2Regs + 0x5f040 + + + + AnalogSubsysRegs + 0x5d180 + + + + GPIO_SetupPinMux + 0xb4fb + + + + GPIO_SetupLock + 0xb61b + + + + GPIO_SetupXINT2Gpio + 0xb64e + + + + GPIO_EnableUnbondedIOPullupsFor176Pin + 0xb676 + + + + GPIO_SetupXINT3Gpio + 0xb658 + + + + GPIO_WritePin + 0xb6e1 + + + + GPIO_SetupXINT1Gpio + 0xb644 + + + + GPIO_EnableUnbondedIOPullups + 0xb6b4 + + + + GPIO_ReadPin + 0xb6ca + + + + GPIO_SetupXINT4Gpio + 0xb662 + + + + GPIO_SetupPinOptions + 0xb587 + + + + GPIO_EnableUnbondedIOPullupsFor100Pin + 0xb68f + + + + GPIO_SetupXINT5Gpio + 0xb66c + + + + InitGpio + 0xb4bb + + + + DisablePeripheralClocks + 0xb0a4 + + + + STANDBY + 0xb45d + + + + InitPeripheralClocks + 0xb020 + + + + SysIntOsc1Sel + 0xb400 + + + + SysXtalOscSel + 0xb424 + + + + ServiceDog + 0xb0d5 + + + + CsmUnlock + 0xb3df + + + + AuxIntOsc2Sel + 0xb434 + + + + ConfigureTMXAnalogTrim + 0xb49e + + + + InitSysCtrl + 0xb000 + + + + InitAuxPll + 0xb2f0 + + + + DisableDog + 0xb0e3 + + + + IDLE + 0xb454 + + + + HALT + 0xb468 + + + + AuxAuxClkSel + 0xb44a + + + + HIB + 0xb481 + + + + AuxXtalOscSel + 0xb43e + + + + InitSysPll + 0xb0f1 + + + + SysIntOsc2Sel + 0xb410 + + + + ReleaseFlashPump + 0xb0cb + + + + SeizeFlashPump + 0xb0bc + + + + main + 0x8053 + + + + code_start + 0x0 + + + + _c_int00 + 0x8094 + + + + __stack + 0x400 + + + + __c28xabi_cmpd + 0x8000 + + + + __c28xabi_divf + 0xb6ff + + + + __c28xabi_ftod + 0x8078 + + + + _system_pre_init + 0x80d6 + + + + __TI_auto_init_nobinit_nopinit + 0xb7b5 + + + + __TI_decompress_none + 0x80ce + + + + __TI_decompress_lzss + 0xb787 + + + + C$$EXIT + 0x802a + + + + abort + 0x802a + + + + exit + 0x802c + + + + __TI_dtors_ptr + 0xa804 + + + + __TI_cleanup_ptr + 0xa802 + + + + __TI_enable_exit_profile_output + 0xa800 + + + + _nop + 0x80c5 + + + + _lock + 0xa806 + + + + _unlock + 0xa808 + + + + _register_lock + 0x80c1 + + + + _register_unlock + 0x80bd + + + + _args_main + 0x80ab + + + + memcpy + 0xb7e0 + + + + _system_post_cinit + 0x80d8 + + + + Link successful + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.d b/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.d new file mode 100644 index 0000000..7d94d0a --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.d @@ -0,0 +1,435 @@ +# FIXED + +gpio_bitfield_main_cpu1.obj: ../gpio_bitfield_main_cpu1.c +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F28x_Project.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Cla_typedefs.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_device.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/assert.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdarg.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stddef.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_adc.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_analogsubsys.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cla.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clb.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clbxbar.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cmpss.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cputimer.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dac.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dcsm.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dma.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ecap.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_emif.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm_xbar.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_eqep.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_flash.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_gpio.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_i2c.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_input_xbar.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ipc.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_mcbsp.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_memconfig.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_nmiintrupt.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_otp.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_output_xbar.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_piectrl.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_pievect.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sci.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sdfm.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_spi.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sysctrl.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_upp.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xbar.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xint.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_can.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Examples.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_GlobalPrototypes.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_cputimervars.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Cla_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_EPwm_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Adc_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Emif_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Gpio_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_I2c_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Ipc_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Pie_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Dma_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_SysCtrl_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Upp_defines.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_defaultisr.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device/driverlib.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memmap.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cla.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cla.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/clb.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clb.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cmpss.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cmpss.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cputimer.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cputimer.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dac.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dac.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dcsm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dcsm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dma.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dma.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ecap.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ecap.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/emif.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_emif.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memcfg.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/epwm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/eqep.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_eqep.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/flash.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_flash.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/gpio.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_gpio.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xint.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/xbar.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clbxbar.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwmxbar.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_inputxbar.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_outputxbar.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xbar.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_hrpwm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/i2c.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_i2c.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hw_reg_inclusive_terminology.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ipc.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ipc.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/mcbsp.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_mcbsp.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/memcfg.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map_legacy.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sci.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sci.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sdfm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sdfm.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/spi.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_spi.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/upp.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_upp.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/version.h +gpio_bitfield_main_cpu1.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/driver_inclusive_terminology_mapping.h +gpio_bitfield_main_cpu1.obj: /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device/device.h + +../gpio_bitfield_main_cpu1.c: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F28x_Project.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Cla_typedefs.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_device.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/assert.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdarg.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stddef.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_adc.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_analogsubsys.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cla.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clb.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_clbxbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cmpss.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_cputimer.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dac.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dcsm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_dma.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ecap.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_emif.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_epwm_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_eqep.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_flash.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_gpio.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_i2c.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_input_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_ipc.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_mcbsp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_memconfig.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_nmiintrupt.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_otp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_output_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_piectrl.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_pievect.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sci.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sdfm.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_spi.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_sysctrl.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_upp.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xbar.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_xint.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include/F2837xD_can.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Examples.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_GlobalPrototypes.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_cputimervars.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Cla_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_EPwm_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Adc_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Emif_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Gpio_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_I2c_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Ipc_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Pie_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Dma_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_SysCtrl_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_Upp_defines.h: + +/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include/F2837xD_defaultisr.h: + +/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device/driverlib.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memmap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cla.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cla.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/clb.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clb.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cmpss.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cmpss.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cputimer.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cputimer.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dac.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dac.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dcsm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dcsm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dma.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dma.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ecap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ecap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/emif.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_emif.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memcfg.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/epwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/eqep.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_eqep.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/flash.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_flash.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/gpio.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_gpio.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xint.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/xbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clbxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwmxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_inputxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_outputxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/i2c.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_i2c.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hw_reg_inclusive_terminology.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ipc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ipc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/mcbsp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_mcbsp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/memcfg.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map_legacy.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sci.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sci.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sdfm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sdfm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/spi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_spi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/upp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_upp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/version.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/driver_inclusive_terminology_mapping.h: + +/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device/device.h: + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.obj b/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_main_cpu1.obj new file mode 100644 index 0000000000000000000000000000000000000000..a8314cb742d4035cb59afb95089446ff30685d04 GIT binary patch literal 100584 zcmdqKca#-X*X>eQ;5 zoZYfXR8*8>{uAXq>F~cfPOWMFzhyYd>LnGNQcg*y!C1$+eQas(pG9wd5l(90R4IDv za_OT4pzF->XrxjvX8~!F@6u)3j}~Hr1TO zsHlkhRJcTZ!)x;{7p$w*G$)UzJ}uRBC%30QBh~6o#8c-=HNy#e>O85|a6+E?tW-0d zT%P)zRBJj3p8C90YdP_rI$x@_oj6ZjAl0;LPOK-t0CJiW@=G9BcU(_? z8RQH{ed7^#A;>k)h znm6p4ECrJ04ZS9>0ZI3UUz68?RQJ9DP2K>K;e8F7ya}X+_f=@}7LZKu+t6egkec2X zqRDa~wY={{lNCT}dtZwtZ%b0Wn)l6U@(z$R@5|BTT}vFNtMUl>r%>+m>)avlpG{Vh z^-t~|>ffw?+GjU)+<13YIKKCgAx>0ocXfEywu3!(4?C0^-)Hb>C#r zO3pkXRdVLfQYB~pB30weUqL2ko&=ekc?x85=4p`0nP)&IXP&h(I`bS5cIJ5??92;5 z*qIk42{`i-5O(HeAneTFfUq;K0AXkT4uqZg2M~7VpFr4|SAnoIuK{6a{v}DknSTRe zXI{6&aXKsGku$d?ul~o`^Xg<_p4^^wee;klZ$=qg{u?E2SV(v~}9w@kA&bEI)*Bu1^|qwJni%}nsr(Nax!Vmx(>RI97crPQ%j)pIe! zQQOta(>MugIBL@xjF%wO+qwo5B&g~A0Sz9qK&*66eO5o~T(8Vs;#1p|PJe0|(nsu& zPJ$sV;ZBY+qvtq(@sR$pVBh)ji*Jn+8xQ@%Lz-@fbgDn3wY-lWaUZigtB16<_qikP zG^wh^LyzfnkkuUWUOmIgzQNP&s6GxvnTQ5yCXfs}uCsusRfOI%+Y&Lbzx0jUl9m6H zIpVVi2R6MI4eXP4V4un{uun&sF?5{kJg{$;y6cVMbza;kHXgdk16$n=>^y&9Rr1gy z`>fqtf3m7I+#9UtK(6Hv?eiel_J?-9mG#i7HO)-e1whj5(7pgf8$!>_7lCL~X!4RJ zVraJ{AFQ`vY~i=Xrwf&J07uIx>c^_t^`Va^-N_+(1EYGTi<*_$Em}4FaGML zA{(E{JwR+YbeEs^8aM1{KlNSWP^_Mfrc_q+p;&#XQs8SKRSJ9!rAmRXkyI)0Wl5C+ zUt_6K;LDaO1->RyrNGxzswVK=4KfA3W*}4GYYs96z7`-;;A;so1-@2R_Ui#3inRv9 zfv*h^4t#BaaNuhvNg(jG2f~4`0}u{;9f5G*>jZ=YUuPg3___e$z;_Q24t!mKaNz3( zgaco9Ndked2M`W?_gdmOUD%dw;`>b9opknya8K@TzAZiXkSp)A2V%Y9KrG4a6E+@n zoMLRuAr-FBzo2F(S{ENo_wrDa?__Go~umjg>jbce_kA{6tp6B==L} zFUMJ{&OcHJD098QGsS!C|3z#!^nrST+HTWUo$leotVZTAE03#ceU?ouR1YJb+E}XT zPRLWUrK-L&Pi-RA3@6T0n@Y8Y6XU6OOEuGRJ++xsRc7-V$)Qr-IqnzRLy;e8BE+5u7CB+}jzkqmD?`(3$J z+h3H&awZx2-y6+{PBs~K&XEkeM49j3aklcLIK1Fm&u*J`ejz8tcAgY`pxDhG&*)jv z-R`Y9p3&2y2gtSjd2uhuDnol;U{5Kl z*8M1dnGP-MiEl7CJ?!D`P&++_<(MABqs&ZjoIAKs539bqU1IXL%f-gSRsBNUtaWFb zpsxfA_3vg~3l{1>gh++@Pa#sFzA8j2)YpVah59ccQlb7^h*YSr3y})-KSHEJeM5+* zP~Vg)73zPbN`?BCQGH`jp;qUm#Sc7GsiQ!qQtet9GjlW$F4i$XxLU^o;c^`(NuXZG z1L1<50E8=cE+Aa8LqND@hkjsW4Rof`<3?L0uZZYKia!kt%=K;_N{giCjROGIWa z@aWg&CLX`lSNO$bX3sCQQWvsTEDTmma*IS6*EvpIw&LBJ2X%j?!;-JXrbG37E4FNt z)xvsljj7)HhsF2po(7L**GiS_xK66%$MsSrLw+Dta^wc7k|j4vl|1>ORLPW^q)M*b zELCI6Eg+LGw}MQ@{0L-n<~ESYncG1oXYQ~vI`d;7?981&*qOV4uroiAB;d?Xfv___ z1H#VS4TPP!2M9a!b0F-@y+GKR`+%@B_XA;PegTA?c|ekYGrt7F&OB&|<9O$gDE;m$ zviZ~cyZX%*_Q~B{y+Ea3Z6C7cH`bbmz?#L~!%@bCjmf;UF3Eg-%nbDB|q zOEd$fn**yE^1!ON`?&e09p@eX`p>i&UuWpVwB2IE;g$C5=LkL9|E4p&BpPw&nBDZ% znqCTxxKBux^7E5YrTF}mP)&M%TB;PDpOGqM=ebg)=seG;dK#$H?B=-YSqV5eKPLg_ z=I15g*gRhXPR$D>;L!Yn0D;W>q68e7Uot>Ugq5S)tgCfkz)Rx$3QPnWm=~Feuox%8 z67!vl^UdGf+}WVVLoH&(hRylrHjVkTR+6aD#qEj}tk5N-N)@`KRH;Ijk}6f`(o&@g zoh((V(6>pID)jAAr3#%QRjSZsq-rX3S&*qhmjjt9ba{}eLRSEpDs)AVsX|w>GFIry zK)6ER0fZ}b6(C%pQzZ#h=&C@tLRSOA6*>(FSLk#gT%oH2;R>Arge!CnAY7p{fpCSc z34|+jElC0ux;7B5&~+>k*}3byi*KwtRJ4Y0kIBxSduVyS%NFQ*P@t3C`ccM%;(T-0 z_xe>HxiI4!v1xO@xoxM$HahR2`mB@l=VtYw`mBEj+ABnI@a0sHS~3D|zWNWkv= zi$YG<-eSAqH~m=DPF&X0h-{~0QI^?DvYk#vjfH4VHVctraT6h$Q_Vs&XPSj*PBaVA zoM$#7#Nrl0=UCiQ=z&<=N&=3>ttH@C+(rV9#cd_vSlmtmj>YW_5Z86xcKfv5&6l3< zDZZvWbX}MKHPHm7!ML0MT~jdb zZg$jHDH!*VsyVSNRdZfhs3sWqk}3t``=n}4DofRzQ#L9F{SMRFKD58I$o?AY78i0pXfF z9taoZ36cb=@SiPX)r|`7ucX z^?4c)F3{605y^P?+-cJrCe*AV++&il=N?+1XWA<JN zXF%ASyCn&Da}N;q=I21zn|pz9tC@rbiWN7CklH$UTVtJ zf6Eo#{9pEL)UcHb(bk=LqGLvm8rv_;ZzoHPww2RU)BSd`yi%?1x0B_Qs=BDwYoN+6 z)f#>~Spli4IODyxpj2!6?PP_dTFdKYinxWPTH9|YDApQvBi5eYyslo|_h(g*Gkk+q16dticoR4c)TE0m$KvoA(-nMH< zIis3y(@c=le4Ew;nQU4MWU^^(kTZOn)&aSOZ_~OUXZkk16J&Ly?(O$oR@PNCqn5R4 zJs`EMP3uciqnfp810ZSErVW9lTbnilQr+4#3rL2wX=5O&fq|@$4J6arvrp<7JV=0cf`g+o{yWhZ4_wx+#fAG`h{Ile3?9Y z0A%v$mmrfz4}we{{R(9A=+_{VN527?JbFmV#-oQpCXXHgnLK(FWb){@Ad^SG1DQPf zJ;>zIV<3}9k6Rf%`U4R5=#P>FJo*z5_UH*9?9rcrut$FZ!XEt<2z&G-5ccRPAnei8 zK-i;afUrl;N)qtsIUwxO^FY|67l5!wFIpnb4n6ly^pV|N|40`$q6SdUMr6?6Y#qG< zb+nlKd$jSQ==`euc+XZ#*Zd-{&7jV&Mp@!a@c`>l-BdTw?yB*qZmJsuvhF5~xPw7f zM_yhF-u+hA^Rc>a*waDe0U+uClX?$_0MTuG`aMH|=*~S&hFK!kzV)N`ZhpB*qy2JR z{g!w7^fa^&+Myi@LtDZf6>UZlhW4HvTd#d}PHa3lw0sVBtUt7B8PP*K&hD)q+6>)L z7;(pgOzpK3KvuKK8`_7g>|321Y$pQY4%>%;aEt9DK-79dU&ka%#L%Xnp5DFSj~x$+ zPjAbLnppOP=A(9Kr{);i$JEgJqbP=UO8)}!$Cp)jRct&swA>0hgNBxxY#+CK>kqA3 z&%ME#DP^_B=`Pz@Age=C@71%dtcSJ+ciGMXqK?UFn4SQ_UA9jG(bmwj_9;um(3V~| z@AB+pJ{$Ks`+^TW^)akIWezN+P0-mCN zj&VXu)jzy26l?``-5A*m8tvMH76NK2dd;9Q7PvXOL1S|;_4%nCG|n<{sotcRnLXA- zr^p`*=u$m@7im4r<(e!Qa%C1Q?uK3SNgby#XTkGHrGEZ7>A}*;>I3t~Z|Y~kU`yyR z|752*U^{Nl{+L3euLk%5WD0{nf=prXCy*%&o&cG`;Ljja82klf3WL8&*@VH9AX6AT z1u})f(;!nAJOeU?!LuM!7(53ug~9V6Qy9EpWxqo30oz3&90o5*5(tBrfp8f74G4$9 zD?m65{tkr0;2%IZ4E_m(!{AjQ90soe;V}3Y5DtTXOA-i!*MV>t{09h!!5cu7N9lm= zrX}JhiBm^kUfto=&((yF=qHIrf#y)h9^l>0;(V0NlqO*XoMQ2MAu;?5hY|$rxutlE)!WMnX5@FG%!@g^A&!yjw z3LjaEav$kjTSezV6-{!Vb&VTE*WhOZ&dx5o>aita(;>fWu#s#f&9nz>`r@9NHu4yg z>dSj-ft=xY4b}!(eTUv9(se-2^t%S@f~$m%?^C*K9K%6^_)&&vK}uV$}( zt`9^_T!1q)B5S`jRD0vVkb)(!MpZL}bk2 zr)mv(|5D#{@eP`cDVj=~*^JpdN5*UsZDxX)9;r2Ub-P)))IqWF;Pl{w&erzGNKcP8 zc5n6c$k3NmMclShR;!6_Hf{&9zMLxJwg*{XOcilEfUH(d?+fn;vc8Zi;&uXA9T0i1 z?rdc}J=9@`xir2D5Pj8>{&MaCqOV-iq$?0rDCleJCW%@*OwVz5Ao?mMy|o@d^p#AS z+zUjl9rSm4S|X-L^`|PtEo%46Q1J~0r-wao?ro<>pB&SpZ?u^SqQFPLkhbp8iPKh# zjhg}=Y%1L<3;aiRoil5P&fwcXrUJhmWGe7GK&Ar!G00TlcY;g>eiz78;6IVFDe#|y zOa=Zkkg34$2AK-{9+0WPe-1Jg_`M)gf!_x*75M#D#sdEZ5H9csBncGwFM)7@KL~^i z{8vD@z<&*d3;Z`gxWFF*!Ug^?5H9dXfN+673WN*%w~_=3{C7aOz<&>f3;Z!4T;Pve zA`1NCpN?Bwd2}tvNdg|-2!uWQArSWHCLrw5%|O_r zTY#`fw*q00eguR)x(x_>bUP6C=nhE&9{m^ydvqrd_UJAk?9opw5$CdwG<)NoJ=^L$ zD~x2$Wd++#ciTF;2kK~X_w#7uN5|Qs&ezeYythAnbW^Ub&%zD!wy77WQ+cB8w4N=b zI%UxnU`4&e=p-`o7R7F+N5O8&xN5_qst^`u=mbag*v zchxK$I)R@CnX3C4kg2+#1(~Y*IgqKkp9h($`vs7xx?hyCsqU9Rrs{qfWUB7JflSr? z3dmI5e+QYW`yU`vb^jA&s_s{-WzQn>MF8WrJ%TYf_!D679Yklj;DT7i0?H`9P)so*!fi-~~XY z0A3Je3gCr6rT|{p%Kl{Mv*1O5Z~!j~gaddnARNGxfN%gW4uk`E2_PK6O9J5lUdj@2 znzPxPGvdz{%ad1pgXT1+=zYD-PLJDRdX#WeTr(5I^oZYAvudTEGn$Hx2d4)|@N)k2 zFcG}G-CGgCD@fTy@QNT)1g``#MexcXQv|;QWQyQbK&A+uYGuDv^I7n!KsbU|1HutJ z4G2f@bV&jcygCq$;2A(Tg4Y1T5j@ipF+I|Ue6=U~(|<~cZ!kDLYzD7wr$?O})1$6y zW`Zd2^9s(~(D~hxJH*CKfe*IC#>&=#IC}-PSvzzFj|Z6wd;-W+;B$dY1wI5a75Fg7 zRNx~ZQ-RMdWmDkufJ_BG5o9Xxc|oQEpATdz@cBWe0$%`RD)0qCrUGBc%2?nF1K|Q+ zM3O*(FA9VUd@&$g;FExGfiDh(3w#M6T;NLr;R0U@2p9O$K)Aps1K|RHn)H^ z@F_sJz?T8S1-`5$qQH;a{Bv5B_DRizk4%9NG{;u3SE5wRaV1Knh;gGjccxBq(+Rc` zPpp2R+|NTVi%o}`s~4yfY|tFrNxHPN-C5z%E+CUj?*W-y+7)DSX*ZC`rQJa$m-Yae zTzapRjZ1riOfKyOGP(3VkjbUJK_-{>0hwId7i4m2Kak0#{jH2H9RP$~I#7~;O9ugA zmktKPF1;TJyYvAd?9w4X*rh{(uuF#lVV4dE!Y&;FgkAceBmtL>1i~&I1%zEX8VI{| zj3uH?w%DEv?ME%ly;xX@+GLHD=&H`~)~FM}s3qNpBF2-V5wCUA)ra%!Ki*z!of`47 zWFy`_-=~=wek0y~ySv(_nKk@Iye~k`^c(RGfUMGu*L3zJ$hG`Nyn`Uu_8alOl5)*z zek0!3AgdVXZTlOL)BQ%gLm*f88}SZZ#{LC*9W@xBGQrn*=_z4|+l zYkBQn5%+tL)e(dzAG5OdX)XPjOMNlIaUl9Z4x0P`MBhC?lOKWTI|yj<6A*nD0ZmQ- z(RUKiy$$20uzteS{7c3Ex_d>hY4bP;t?joE-kvB^;;$5~j{S9nd!o3nP zjuee}S32)4oWD|!g<|8>h?f;;#Cs{$HzRrU&xz{XfJh~8M^5`Ov$)k%wCXX%w znLPT6l#NGU1(`g$6lC(~Yao+HUk8~y`Uc44(KkURkG=&md2|`b7j6C?I*fRCqWXVRnbnDTG*Ns%&?y9Myx}_-tWO@W!4Uko~^EQ%cWj!A=`4Mb2 zfv6BmElsr~QBF0FV5<#8HLK8j>R2MyzB%)!-d*R$)ji_V+qF-(A=1#^WrwyN3~dRw zeykZqF|?VRj=WrAeA7R~#)Cu4XM-B~Lt9gKbg9R$*uB+5TT{1lspqeNOg)a-AgkHr z4Q&%E>!Gd5J&sL*aF65NK)A=T84$Ie(9kxwL=0_Y|7WjWiF%^H`1HY{wP#XV*`aNn zV`$sNno$%(TYqq_^W`edkazbC4lOt0wfBcsr4c=AJJ`L|Lt9I&=iXp-1etmqJAtf1 zulMTCR`yp>?s4n_M5TTjrh9;Jk7HLL+8Vl+ce6wcZM`#VlaHJ!C?6LT99r9mcds4V zo;ilLSF9ODF|<1$`|G#qZA*VDzPI4eawA?J8d~ac>}&VdA6o6$h}%!fYPr=tj{QN_ zUX8c|tgMH&HupFV1for$hiMQH?r|IpL|a3@=YC7X(C+I{`1Ss$j>(7P1c%l(;tjP! zJ1oc04v#gXC>rrr9)06R?Yq8?lSAt_;$?|OysOdBhvs5X!PmN$ski0oB}e1!AC)+FgO)t3WJYH*@VGqAX6Be z4l;$o86Z;_d>mv7gEK*3 zJ_Cfq;9MXa2Im3cF!(GG4uj7D;V}3-5DtU$fp8dHAW0w$z5s;7;EO;w488<}!{Ez6 zI1DZXqSh!nU|VE~IQ{wZh8qv;Ka*Wa_=rw_Y9EnBU$KX4ufpM4lDjlw+$b!1{HKDi zd^*^L+Z*|fcv;?q=o&Ta*uilV+&(eB7wLGdZ_Ixluk{0&EZQGrvgiPi$)W>6CW{V| zva#r3kjbL=gG?5E0A#Z05Rl2DLqR5s4g;AiIvixO=m?O>q7Q;h79DA2wCE@xY|+s` z*rH>AutmoLVT+Cf!WJD5ge^J&2wU_aAZ*czK-i)WOA@f?BS6@qlYp>ACj()NP65Ie zeG~{=bgCu7qR!0+=k{#eS>9pUT9g~{rpK5Awiz+=JjS?D{Kh<@`(N*7Pu-U( z+)uwTXURr9*B-FxOAw-MkBs#6C~o)GkMH_2kBD0WWV#W1Ns#pg9uc<`$olGzh+7(D zwQ_o2crwUzL-yN1RtH4ht8cfmzZUYdic)~^ZQ096qSg-c@XxY9RH2}+tsD@(GkbX; z`br8t2`T{Ld$U&rqSg-jJC!UE(__H4@VIW>2WCY_ zf&UO>D)5^?rUJhiWGe7mK&Aq}6=W*#AAw8-ejCVC;J1TJ1%8K>vA}-}gbVymAY9;g z0pSAw2@o#up90|m{}~W2@VkLgiR&N2b6B8u7ld1^!Tu0)IHhxKT9XE$Z9<^5{`B+loz7 zBVLwh#2abryS`L^lwD7RM@NH99vuTRd2}qup8~=jeHsXR^cf)R(YZj_qw_2g=du>peWTU# zaZkS@jAYJb1sn06w{>(r)Y0PZf>`56(Q8#;^x#)!@2mLU<;~6vAtQOd-6MluZb)4KjuBI#$LIUKa?5@H>HU2)_#mhwyqp zIE2>+!Xdl?5DwuDfp7?KWQmv@!!EYkmC>Mm(tl2lU?X0(UBR2c3SQi88e`^xm>jA9 zOzTvpol{n9n;P-F$-xo4xj#A7j}v-ww6OasB6v%XDT22GnId>=kST(<0huCrTaYP& zw*#3XczY{j1n&TZBX~zi0uj6u5RTxTfp7%x0)!*@JwP~ucLl-`yqhIrauk`fY3sE{ zk4+L^pjkPBjd=Ik$2i+_<;Av50uMIgeQOsEUERO4yJ{8= zoxr~bnX3CSkg2*K2brq-4SCFZ?p9Gnz z`zesAx}OG_s{0v`sk)!FGFJC`(Hq~y8jJ?tNV3JL;}x!;ES3cN3{cw`i*#5 zfkwQW)}sG{MU&iHF~*I;qT>er;EcE<=9&MrXs{7)wzTLRyQjjUPk>AoeG+7{=u;q* zMV|(lEc%R;jYa2zOctF7GFkLlkjbLYflL;C9%QoUe2~ea3qU4|z5p^=^hJ=#qAyt) zE&4JLw&+42Y|%wP*rJPputk>uVT-;3gf03i5Vq)2AZ*dsfUrehmn2}(H-NB3-vq)I zeG3R%bQut~=yD)z(G`{mi*_ElDPw0!zX`%e<{&xHi1)6w=zBRVx-!PNQJm&{cT~xB zlWr??NNn1i=9GwnEA~9wri0Sd+gyWwVe<*#`|2RE3f+xucUfk}jh~OnaHfO;>HfO;>HfO;> zrU;%4vN;P5vN;QGWsKk{KsbVzkt7ho%L3sDUJeLH@bW-7f>!{-5xgQ0j^LFn5z}L3 zcJlB-NAHkNY&SoWc+-Q=g4^klnqzuYjWIJp6!`QPTA#_B7`sJI5Bixq*ogOryb|S2 z`-8k$J9Gwr3uG$r%Rr_AzZ_&L@GC&30{^y@O@V(0WGe9Qf=mVeJ&>uuuLPM2{3?*C zz^?|G3j7+7sldMvG8Oo>AX9-~XJst#>w$2A{{RRV_zgg~z;6V?1^z=IT;MkW;R3%I z2p9M*K)Aqf1;PdXBS``Uej5-j@Y{iKf!_gy3;f4GxWMlO!UcYpC8EGDD0E}s)}4_~ z!bhgS2O9A{vsa?*&T%Emo``XyXvABew)XD)?XE-PfZvFh1&w%rN|#=>J1bmz4P{dL3kP=|567F1-OVx%4K;rsm3 zme-?{bdz!$PdZK??wEb=!P@bA%I=a^qlNnGj@ibt5pQU2ZOGc0ek0y6ySu)uA95OT zhl8x2a2jz(fUMGu*L3!vl+&tJ^E>fIqOKop8gWOVt{-d~aYv)BqMWz=F{tZ@nnv8Q zsOv|XM%;0z>j#>uhv=ZLLbbR338?FbnX1R=pspWf8gVCrt{$7Id-5JeT^&t$+keFB z+OuhC`qugSnuSS-^yAJnnv6(yEo(Fdk?vg9=ut$vds(BYh;#?DMvo!VUCbIyL!>*I zHJT1cJsUHgE}NWzNOv^rcRh|scQtD?6Orz0)@T+Y-QBFwY(%=lS))0KbeFS6Pasm+ zo_798i$ok=vSnuG%7!D~mLB$>7)3543qNBmJQpln!kw4fxYcobv4yXHb#uzI>5FEG zjfXssH*MQE(4;pYUif!lyr@96$-jd@CjSlwnf!adl&yasK%M+M1aev43Y+BpUc` z`|=o>tiQ$FIq}A)j`Oc7-gL)`D#^1C=Gxk7n%J^> zOt5cW@g%)}La!CdwX#1yRsB^P*Q;DKA{BoL z#USEmXT>7YJy&{zaTbZSF|$SLU+of#Ocx_SrwSVTEsQk0x$N+UV0cTo;dnEW-UWJg zct2@a@Abk|mH%S&i#9fjF0jY&1hDN^-BDK~KDr}J$;*`x(`mMb0LwP`w z^|xD{R#|SAOhKfMA84@3AmVn(vWT=@^eirCkr?8c*J{o^Iko|uEH@Qi`Peq~RkTA~ zDaR03jyIzzhPc9tbFWV7cCnYRNN|X`sV|j=SS`qUh^yM&^@liJyEx)jL!DYC(@>|L z$#kpxL!8b{lhqMvqv*lPK*Vj6H4tgL=yzpWB!;-=tsCDwa$)jAVibb2*f#gownJPe z#}L4BXVg;|y7|`&-@i zm&$raY&+D~&yd09zLN4Fu$0Zaezl+mP4IFWO>vnL{>nZLS#kMDMVI6okC<~&`pTE19b|KRjf|S8y^IwBH|EP6%mKX zYKS;QrXk`GnU07wY(BjONQ2N8$Jx`;SL z-ie4qSW(LK{xij3w5$@J*(%iZ+%2;-v)@-z6}wveH$TS`(`0x z`!+_z_RU7b_H6dPSxfUIxbs&0D*vidH)&a8t{_6)3^T^4b_LS3B`_w=t(*LQ4HcRoX1 zMH=t*hpg@!KpkPJo!3$CFd{XT2^~SCuj$b5I*LeN*P+q3i1f7`8hwXIU*Dn8_kfh8 zRi~py#}Fx36FP2@$f^65{yuR<+-;@hM4>|g(IEJfohm0_s+4eljx)2uarX06nKCw^ z*!*c@`-qK)zT~OG2ec>ssp6e8)^p{Q-CcXMr6AS`U2|eAj^CGMXS@H2H(s25+c5t^<_kSH|yUJslq~E;T1%DKkMHS>FYi8 zocIF~-_iO{L~323zjf6jFk-=vg?Wt29xc+nsr47gDD_WFnAPX3I8MjMn1MP4gU3;)U@#MP3I?-Kr(iG}bqWS^P^Vz<1n4FhJc&95gQu*XBN#l5h=aj1 zh&UL`Ma02i9wH6~&m!Vr@Ejrz2G1knU@#w0AQ&t_#KGVNL>vrWM8v`1B}5zyUPi>h zU?Cz728$4JFj#Dn2nOjLat-a!w)}qKF_Y^9&4jO7`z{6hCb_T08K*i?_6{M!U| z@^4er$-j4_PX29%I{CLb>g3-RsFQzNf^PiV3U%^tYpdt*ZyQAH-?oU@zwHpQf7>Hs z|8_vc{_Ti}{o4r<`?oWofPcFnV*lQQi2d6Y5&O3rBKB{0MC{)lh}ggPB4Ypcv`Cy+ zo1cB_t-as<@ShKLYaDDe>}^jg_JPxi#ofN~#;cCAo8#K?k@-KH`RS&5(!hKDxTgEm z%q@BT^}B)9)fGCd-LmHZje&JmbL%nHh&b3s00n}5ZbTgH^H?M%O1p%k6Z0HyC2s&{PQdCf zlTN_qvnzdmSm}$q1>(${a2)RlkA4SyW_ODj`|r8$s+=eX>_p*MUl?M25xcW`N~EbD zQS?+PiaN#mVyIKBPePqyeR0$&)|Wt?Vtq-}Db|;=dX89M8WG3(WJDb6Z$ref{&qwh z>r)VMtS^IzV|`gf9P7(jBqq!AbGwXb-e&Nf;tLH-7MtoT+R0KW$7HD-XXb@S^5i-HH(T)^~*q}RInUmN(C#VY*WG8s8cF<2X#sX@1jnr z;62nS6|6*^Qo$84T`(1efNNUlibhaj8lbuKc2Au`x^Z#?+}|d z_6;^Dc9!<-V)sSW(usFQu~L!Io~ z8+Ed8AJoadeNiX-_5*uH}hv3&<4V*B2Yi0%6TBDU`kL~P%o zh}gcv00rzj91+`h1R}QYgNWF^BN4HEME=N zgHpDk{wvhY*?QE?*?QE?*?Ozz2=#{%ai~9nh(rBRL>%hBMZ}^0J477nzXucu^~Vr# zs6TFzIQ`o2)z&2s4az7WzD;xbRWvgGWG|~Y0hd*%v-PoNR*19p(fjW`wfm>RbH&EZ z*?PYX&K&=p^rs4+t+%@?WBqB=&Dna?&Dna?&Dna?Db}Ay-JGpQ-JGqrdX89s2@%Ko z%ZNDE|AvTT{S`zU>wibYvHlN49P9r?#IgRWMPj;CeDsyioA=oaCkyDu9nskMx1BE6 zb4-_iV$IAD!Jy~#H61@GRrkNo)(0CKv*lGdP3#2+A{aCUnS#OHAX6}CCS@B8nxjs^ zpatp_3|gX2!JrlD6bxFUPQjoJ>J$vxqE5k}9qJSe+M`avpabY87<5FPfHFzA7ZgTcLk0>PjsA`S+<5OFZL4-p50-iSCD z^g+bIpf4g02K^9mFz9cQ2nJ&dZS0u1bM#K(&2N65?T|fZ`zlVq&yb=*Rcoiac@M=Wt;5CTY!S5qt2d_oM z4qj)GXoyUDr(v5zmo|TDpFqrRpRAy?QnO;e>fnSNX_m`pbv9ew3x^ zBtTt1$TH#jq>ue5O->^l zSIc8AsY}ZvFR3fxrspw^6}7n2-f`bfJ>3!dn*Caw9cYS7&m}!vJ=cGGI0JO!;Touu zhci(p57$JUJX{NP@^Ed`$-{L}ClA*}ojiOe>g3_OP$v)91KoJIKI-J*2B?#V8=_7g zZe;Zw9?n9<9&U_?J)Dh*J=_Eld$=hg_VC?+0v>LLh&|jK5qr1=BKB}gMC{>Kh}gre z5wVBcAYu=GOmf9@cGTdqGzoRy}nQcOU91 zFM9fZtNU}bIzP?q3q&d+Q(M^qMEpFnFA?efHNAWuv`DOxpKt8?Z>fc~28dChvr{w* zG{oN|m?1utAcwewdpN<2rWoR}Grrq!&*5E-#Kwa|%s)DROG8{;ch;##3)|iGhrYUQ ztBbhbqfYIo$52-@%Nye3R;Oiv`%iyB#Qmo~BI5qjpAf0_hQ62+7KtH_zaE;9FevXZ zF$%#Uw!hT=YKQn_jv+pkU`A66arK$6uNl?2uJlK6h`BlPEDf!+cJ97DPv5R!Mg};lmPCjoh;+mi1 zBCZAT=94;(cabF>65hP^Z=V*|rneQ_4h{4V34_g%Tl|wcY36`%t380F0!0UeAAxSd zak&93K$wN5oY6>J8Mm>FOgjcx-zkPzFfpzgu41ZJ$*6i`mVYW zcM0n1e7X1fS5Vh?)Qz~WqONkJ_xhz)_f4RVwoIesYlzfzroOV*5$WqkbXa@?k-mmR zqc;I5L#w7wjow0}uO!iE86tf#iAKv2DQD9LS6C!6YyPJF9^10&y_dx|YBH;6lzi7t zm-k@0lyFxjn3*A_%Zyv4whZi7Qg-D8rwbq4uHhpuJzd_nyX#LEb>yX|%UaawF5~M^ z*B7`%-1Vr_ea1gPU9GX+*S`UDwZiD2lDg0%GmciHLk zNsj6AX@Z#5Sd2P|1k}d4c+OJ$*#piTjyE$S2y+M!MXp*`vp5IUev0ih%66c9S0P644a=q4a^L7f7^J*ZPa=!!Z8 zgl<;P5fHi~;(*Wt5eI~O5ph81iHHM2FGL&=?gJDE2)z+;KAmhx4IM9?p+CdAI=Ta4AIW;nIlM!^waG9=;6`d-!%l?BNtd?BOzq*u!NJv4_hcVh@)`#2&7I zh&@~p5qr3jMdDoBSNTqSwPWD&qrzzBTwAbVvWh*`mxRC#Ue3Ty8O2J^=?NFY!Y8+V6xbR|EHZSS9463Yw>1Yh=hOn$D|%B zli%1XwrvuAuxWB6B>Yh}$;fmt8g!Em#-L8=U@YpC4#uHQ>0mtSlny4KPU+ww)F~ZI zM4i&X!>Cg_cm#Dy2a`ZI>0mPIln$n#PU+xL)F~ZIwR(cx zoDLpG#OYurpg=m9g^1I^Y($(6<{;v9@B|`G2Tvm6bnp}+P6tmT;&ku~B2EW$5pg=0 zXOT$w=brzlbcN@h9wK~Z5`Lg@@_C!^=jTZH3lfZ5g@yZX`g>dYfQHw^rj3Pzjgz;7 zg;VUVN(+|(-B`FR>SW<^sFQ`uqfQpCfI3;YBI;z}N~n{CE2B;pz5{i#a23?a!l|Ge z3s*&*EL;tBvTz#eWZ`tH=df^fL~P*S=5JH%xe{XI!Rf*ge+@+Z z_wDY=h`$zfa~2gFuI)pJDrO^7(+Z$`use+wdx_*)Ti z#Qz8pNBnJwIO1a^q5m^k8z_H;D|JrVD-!J5qR--=0^J0J)2LHGIDg3}3sFRBupiVAs2)c1`Bh<;oS*VkX8>3Dx&bE3E7dJt~E^dm5U3@npc5yRA z?BeE#*u^aX1zg+`5xck*B6e|WMC{@=h}gw#5wVNgAz~M|N5n4ffQVh(5fQt%lSQJD za($m37v5ixepOhF8Y#17Bjr8T$X&t6CEad$jAtFE2^+cQ$$VeUyYDagxRy{eZR94h zk@8*gab`8Yk@7vezrK$%^#e&G?n>14<47a!D%4d@@)`wKqplxC8gbX4t{+4iao zKZZ2ou0>r%LvQ=*P}h$jRTqA+K62F9e!Ay2;(j1i-EONc`jD#bw2inMrK+23)de3? z)%~>*cav0gYi-2cELGiA8*#T-)%EsFU*xE-)YvM4zED|%k0ek%*14&zZyON3cSxtt4-mbeYVtV{y`*Zg7l>X|HQ8s0h|E2URZA@J%(Kg+PyI$oauQwKe!$xFOR#AP z_h265NXN-yn|Ar@i658zSXBNXAM$+Mv~80>qvZS$d67K2AS9ctj7MKUojm#?>g3Uv zP$!SRj5>LAA?oDOMW~ZU7o$!dUBY_6qpwJnJo>6s$)ii9N*;Yps^rnvrAi)sL#pJ_ zH?0aDeMwvIF*IObQAxF+>aP7b=o#8j}u8y%08FXXFbm@H*8URkpboG=3~I`Wso5u5tSK%&H=T>oQ_G%< z8Egmj{v3n)K*)@r$7gTOm7%9jdi!zofx3b zm3d8LJuJ{;rII^!h21Mbx@{NhX@U5mIr+2I>qdS&td9KT-2*#Ev#Gbegr!f8OIZ5m zGM~|L8goS*-|+L}Q~fYyV$)DdwbgQZ|$m2LiIwOO6q;6Q%UWOI+fHu zs8dPpi#nCmeyCGP?ToRVt~2rAj6BeyLJPeL$*IQin*DO6pLn zLP;Ga0hiR_5(G->2q0Wi9|XcBbtDijsiS~!NgWM@OX?UPTvEpZ;gUKI2$$6HK)9q% zkR(u29|FQ9bs`WhsSg9;lKO}x;w007yZXPs_v?g}!bfzHsY#$6Y>ExNk3#58a;N4o zZWI=6o-%sJ2e*xwEjDc}8fXWbPgjbXBhv+TIgu890dnqOlX_7% zsTXyVdRY%x^cAU^)GJk!dZlVouT)Lym8wa-QYDMNX;rZ3TN1EEmq`$?=yD)z(G@`0 zqHhCXi@pPdE&47Hw&;66*rF?eutiq^VT-N?!WLa4Nx-7-17VA<1;Q3x2ZSxU-V$Na zZWmXKZ!vWd+~mHSUq%~qyVpirML&cpn&fWEW!&gE+c@@)`#iE^UcH11(xM-$7pUV> z+3uBTGMRo*Sj4Sq(~dQ%{-L-Q>iVXm5w|w#>NWsge@z|K_3cI@Ze7&XSv~LdccQLu zG#YX5LS0RH@AdVpPO-X{ZTG6r$oHxG06HEwkbrNS+E4=h5%fD6Nx-*E&5}TW2>p)6 z67cO(vn9|UL%*Ym1tMQwT#~r3**h=YCB8$GFGYh_Gn+4)=g5~WLS`J%4mDcd9R)sbEngqOt|0O|S4gVVm zui@8$@EZOP5MIM?0O2+KCJ{s9WF;ZZ<%4R<98tl`l>cnyyM z!fSXe5MIOMED>w?(PD|iw?4Q@F0>|Q1v+waS&N3iqDgKzWZdXD*?c7A)?IOXjjvig zA^ab@+dmQ#9XZ2z3D;e9!|lFGkB&f{Jo+H&g3U}sFO#> zu^#Z~c&U;{CrFh%`jAw~qZ6e{9(`D<2U(V0NlqqBgpM`ueC@aP;M?9nHHut%Q+!XACf5^=hs zS7!2y$xWsu3nS5W@lApqH*>8?=YdI!yU&JXfslqfR+%hShWAtj8J2oHbJd z&RMf0;G8vE0?t`;B;cI&gan+ko|J%d)>9UU>G9X4t&z^}uk8Mx(<9hpGuP(ud62`^ z^vGpqf{0n0zwCFZ-RK?H#kS3%aB|J&0w1gLzDlOq9q)JP8NvYBjUdpPl zgqN0pm+)i>0!#R9KzIqi9SASsDL{A$F9U>^@UlR72`>kPm+F;5?%!eFX5?{h?wPlpve$*mqTZWI>% zsqX0?5`OEJ{ht;Mwnc2^1ze}BkL+?HExHYLvgmfy$)Y<@CyRcJI$3ll>SWPfsFOuM zL7go6DeD1?ekN72=x(W!MfXUREc&@r$)bCuN*3KGRkG-QtAa(pkbo_EK!SipzXZY- zJqUy?`V|ni=+{8lqTc{viyi{P7Cj7vEqVk9Tl6Rpw&=H#1T6X;5Vq*|K-i+kfUrf6 zTOur4>9*>T#9JBDg^$dUP@wJMCtF2NKow1Lf6isxD9&b`Uiwm-=qYdQ6Ppgv*(}-i zFn~>}Q`SJcv(}_KWeq}|Qr2M9DP`S{I;E@!P^XkN1a(STLs6%cHO%TcQr2)rGG&dB zfK%3k5^%~IDFLUfQ4(;<8Z7~*tT7UB${K5dIGgp{nP?zGiMh;N5NmjqzRRa3_2_>{Y}~}G;Fass;YY(6_Qw-DJ#@@^9Ccd5XQEDP_$<_E z4WErVt>JS}r#1Wu)M*WW5_MX`pJF|*hCeM;TEm}_Dy`vjrAlk~JgL$e{;X7K4S!Cm zw1z)#RanF4OTcUR0to_Z_zOUI4Sx{`ui-BN;WhkaAiRbz1j1|hA|SkmF9yPE_!1zz zhQ9)Y*YH;*39R8uf$$ps8W3K?UkAc#_#2jpHGE;Wv<=gG|ClO#WY+M&mFdgukA};0 z{Ajo$k8z{=v4PKK#mz~0t4SoGf!K7Yxqmhbu1x<1Tzbgvt#s*O)XAksP$!ojMV(yw zE$Zab?@%X~evdl2^cd>o(&MZLT>67l$)!I^m0bFhRLP|$q)IORS*qmHU!+Pd{ne`A z(vuRfOHWAG__9sL$`F#H700L)#zPeYwl}__`kPPPcd< zF4f%;dfVAv@W!aM1qkSOB&50@hgObmv#!>G0WWz#{Z8t=A(ZOw44oK}=gOqEpP%$} zl{h^;lIrdX&7A+mnVWmAoQU(?r{p}T?kAydn?1SV@XxzfdoNd~>b;leO?5vF6?pXP zaubi=>g(z1*wWMUr@Ehoy3V`!#;QX_Yv|4By(yUL?hdUQHKFC^a7G>P<@#qi?+wYR z?w-)?XTK}AYWs`h4AJkoJ=Og@RJQI%`O9=@Sx;}Oy7z`MsqWs;gMWT_a72Y^Exb4A zixWLkA=TX%dg`o>+ei;4~F&?+5Bn!UHxY3E$IQN zm+F2M+LpZfA7{_2la<`ap95}6gH-qH(4?4|J=R30wDW+S28~kPZ$i!9oDqMvSf0Fw z=+DtO)jbqSAM(|n=uiJC;SnghBMTBf?+h6WWr-TOq-um9Gcx`y}RTBo|-1*btHng(rC z-S0z-e>%P)-;lwVyv@)wXrJmH3nia8I;2CPv|OIvu$8*L(c4nTRQGu3@RGA*n{+*L zO#cD3?z$?_Ti7 zjt33V6J$uL`)jE5x_Osp9~<|cA$leZOLb3%Dz7;B;@~x9w&_2wx@6px5vlH}-~?%8 zCdk97?&;8xW^dfHXIq_T^_JRuub-6ao(VnoPV|x8UH|YtUzR^XqEn`*h2m^z$&9Bv z+~`+lqDN?kM5jzu=v?Tf?7iO}>eIfzLF$u4r%Y4md}w8M^6)}O@9>PD<s_DMwaduA$fF;ryErmfc+JvPZBdX_||%vRu1$hrC8+@6g)dn;0wo+i;L zPbhFX)OqBljGZa{Cg=}e+xzQJDgC$LM9I<6iHANZo?$5HJj=`E>JsW$bT0)GStGK;1}bjm9V{TZ74)dP{zQ`TJdHs&GyQI;xn zH8fybcwD#c1Gf8{QwwEu%IgYT3r>qHnikP1%M|)6G-v+QyX)Mzy2slb&5P)i6$TF2 z_k5;EbolwXUB)zTGx$!A(Dc}&Kumbgu%aLIZCL1A576}3t3YhnJRI8}06l2?6^IK5 z>Pcgo9|shO52ts?HMB$9@}4&v)BHH7Ktg!`9namD=Uk;D{-*RGf2}~SaG<6%w)5jh zg+k$dOMjoZBJQ@*-p1_wIH6ED9J$_k;IIo7>-w8hD_nHSFA7A$fx6Pz&X3ayoYR)}5w!s90^sZl2C~vst ztsCDwa$)jA{!XY>FgoS30{O&eGV|kxBKgDfvv0k%_q!jw6~1wno*(}zy+HW3AAi5I zaK5+qDP2E>!rRsql_m;?%>yeuV&}(Hg$jku9Tg1H-}N+w3WrViyob#En4w6Ku({6~ z5&fQ-iWCi-n`(K)EFTIK3!9sDd%!Fo3M7Ti{XhHxP;0kZKNKh)oFCa{{ZODp*xc6B z+mu;96et-scLVY_rPg7!ekf2XIF|n1yFK)ZLZ!pzzR=#r?EF}&P;%JZ1K8i3UfEt( z;I`oW@Slt1ZEl%Dw};I$l)TN^`LRNwl(2dBk3s(Wp-`Eyd1j44{`#R%*|2%mirxto zoz-7jr9e6HnaupytVsE=xn-i>nw}q9m0lrio}Z=kCU*T$q+-}yq3#hoKXxcoDQr$e z`F~$8qB|9+9Q=BknA!1(B6oz%FNFSE^yK(VfhyuHX7NxUHEb^J^ZveBJQS!JHfKrw zP5Fz50@cK(%;KRyTG(7+;%&+-9txy~&2J+9ru@Z2f$G75^sn{v#`s5tGQ#GXGXFh# zg*c%=jqrdXzdnAhZt_e$l&Ti!aXGC}X4o{37^FY{S%qqbO$&s-IqmiH3e*ax)+l!V z0k@v#X#ESjw+A;AsU0>y#_O%=@A6-z*9n^zAjhff*kh5GGfUk)fAYadMI{wb|L>^Z z)t!Ro2qj;#C(U#1%WM4o>$o{FV^?^(eR=44^#Xn9qON*w=si=dgHtWRy_v^5a#50_ zmYRR_w2ALCb$8O)BWkxAsuLYvf>FD5E6?z`)225}s9D9+b=$2+)M1O0SSa`Tb?%V& z&w9i^=<<*{aEVI%cwhdOg;E|qp-?0J7u*ze+~OvlI{NbJ4!3@;=IQiD)NxC6;<(K} zr&Vd6)XdZEA5ljxF^M;}vCBD4j z#smA$WLNTZ`XlP-B|dRMp&J9Y?u>Nubo)ot0Zc;Tg?6nQo=I!%<hf}raw|t6`{mmA3vM7+T!mkdOH1)BvpYD&GVr>-Tsjhsstr2*)lV8Wy6u) z!3aHO)*G%;sstsPN75?fJ*dRf)!|c~MDs)wPp3a}yDC13=KcwuZvTine#)C@9*XG^ z{v_p8^+`1C+6sA>zk7c~9a!a0G}p;{I{guKSXCg=oC@=F`$yDaRl!8lQ0fu>BkH)S zP@*|97n8XBJ#A}^IJoCeIf>0&^(S$Pnz7VQ_3Q1AeeiCD{innv&Odhe;C_x%mS2|d zp4X2anp$hTcv;>)!-o%1AI-UgU--e8BTujE)I*vg@2J58hxPB5+;>p#kxo>clgh8Z zIll0*$5t1qA~!r{n0QBmQ-R+xWy-uEWu9yOmwd-KZ`-{_J8qm)j$ivup<557z1w!3 zeC?<~!$*#GqGFw@{K}4-_tpNc^{aj5EA4*JTjHHE{FWF0oD*HS+o~?|ErW;YO;_R9 z^~=AmSn2yt+?21go7QiLcU0Gu`A$r;u6RSFlX_uVrjr&^CdzCvIFKd|iZ?}hTXoI$ z64iPZ7Hp*<$spQx%JmaBozrKUF6ccaK`;)ByL`=eB%KInzFr#EW*>BVIuCumK12Ge zCkqDce%I3{cJBKAyu8b!zvuk=9%|mvaub!BT6N%v!NYs?89aKx;QmAU^%~lH@UUKe zM~q2J?W^`c&DN@&M)e;#s_MX@y+@9(I%Hhms^f-_d_ehc#HgwR(rZ<(S-W4=A-(%l z=|8^r&=EuWkE)th#oOShD*eXv9#TaS*uJ;vs_KY4tylYot(=a{k~_BQP(8g`R(iE+ z)smZ5PtK~ERk?C<*6@D)2lgM9+-cb0@yTP;Yow;7rB+LA*|CEnBPNU-JaEwH18Do&EoF8%mSyy|H=4z zW9%*L|GydM*6P!HlgRsE`jf>)CF_6x-%hpKQIn#BUy1kT7;kZRoRi-FbdITiMny$A zw{m;`rT&KZpD0Jn&e4Ob>Uq?q_sIUe(ldKitLFb-)qefQ4({8(*QhZg)O;B2&)f0+ zs`ec|bm;J5RR<62J7i41{#BcJ(|LU3UQLG#@6&ro+mXXZ4<9{YME_B#gS@}>fAyCJ z_3z!!a}oY2&no`ry-(Le{h1gi!~0#A-3zc-Tq&!6xAYWV(-z9?_>bS}81{u84Hv}{yTq@a@!mk^(jkdP}O zl%Sr9mQXjLenM74(}LcR(SJM}7MS#s(@_0)RKBR_guF!xgo`JXO_FHl=7ZW;xLLB=kKF1tk#O#Cdbn0my{TAF zj?N+LSI4l-uZ;y!zcS7fDeiQkwI5cHdJ70{n59P7WvaY7`7jSv=s8plXsJ80g1 z=Pu%J!M-7n5Y!tIZ*!`u|H@lNy)PWDr~YTY8cs8HgqOdrQq))0Fe-16vU${@;S@Du z-Zq{8@9Ihk^~bdBsG@p*+?z+{KSk94@VQqNZmNH?Yh%Nb>fbsxbD|2X|Bh`qYE=KB zs-TZ_5|ToZNR;=j_f4<$zdAV|@S5vAj{nYPHhMawh)rsXdGLPV=1q#`|ZLxqHD6_4)4Q}_KopZD3$IrKdDxxeQ* zy?(#f@3rsmcfRMhv*YZve77gVapB^?ACsu+s*eBj4XZ(mo(#RVO31H&HuT#ciob@@ zEMPk{XuFET*T%jj6fd{}x2pzihdZ5oF&G*W;q(aDuI3B~*bWKWU)^yB?5`QLzlM_) zus_n78nAtXGskcHM$E^{+UC61!u?$qw7)oLo11lN@u?Pn>flDlX%2?rR$J@gTE~^< z;Ki`lb58I}P;dVY$VY@d*YRT3yS^8U()te|pIbP-2fRt1>%1oTwY@<;%v>J}@>=q( zH^F)Yu5rA4cbd{`osT8g8-Vt>;|ju(fLkc$qAH1#zKz748qTP?JnoR!BjWvG&wr4R z;poU3;{9Thm<(2ogF9c3Ux$g}Ifr6m_(zZM6y!Wg!Ve|ki{v-SZF-U{rB?!mcJ^03UkE%5{dpY zi9P{yM&F-=e}sg;4>$ULB>X@Ux25vye+B>KK2_AQiODPJuAIj#xzCrR{Y zNc637fzjVf!Y7jONx0bPhmi28B>Zyu4f1cxr{GD4{TLGcI1>G4`91Rc<@51?v!6|( zpG%@YEPqD+ynGlg4EA+N^bJY$!{u}2C(0M%B4_^=iGCA_{)&8LwD~9!et9zx{RR^K z+a&yD`I^nm-$=r*jRDbbC(-XB;Y0Bnll~?WzCH<`(9(Q=68;eqeyRLA`StQ!TUo!4 z40oJQN%T>-n~x#kTaxfwTASZX!XF^vYu#bK1qpvE3I9I+5zq5HOu`=};Tz*U6Z$qJ zd|MKJ2>y%<{a6xyJPE&9evkZq`QO`HU+r$|BT4iFNsKc}evJHL{1BjDLt^|A68#1F zuzSo`BjLMt1<@yy==+oKugI6km&$(|Z~X-l{qH3D&I#uGknsIT_)dxDdz0|VB>ZCe zHS#6$i@I6AibTJbME|RN=>6uyN%(RS=kMxnK8%Eakc1y5?~(7-!~9SZ;}0j%ua@5` zzeB!PPxT~w68$RqE%Mvtf9_>He~7TJLZVM1aXv%jQ|0GBWWI<*znVnK8A<5>~ z^|gK%iT(o;eT{zR8TkXa2_H|w=L|CcED1l0rjd zU!6psOk)1s@@eufrI{}#G5(t*`rqWMq??Z*;Wv%~G0tuh{azA2YP9(n622t~e<;KJ zX%hY{2_KhfK9Pj)LBi*cH9wn#pG$Ha`P1@e<(rJRK8{4+jzm9Aey;oi`Q5qJA0g3y zO`?yNog{pF6238BL~=gc zknn9u_$l%)$p1q=f135PN%V6`^oQlo$e))#^n~@NN%Ut)^l?v`PbA@ckno4(Ps^W` zZ}XJ(2_*XNB>G7+%s)@U7m)A=syoP<4E**@-yY<$ak1!eG-Yj4~c$} z{3`ji@`GkuKbl0JMWWvz|DpWH@>dG1kDP0L6p4NiiN|HMe3pFSeDiOS7=IIq{)&9$ z0`pNM{Pu+)#yLQuKS;vYTV%c!2_H+sAAQmMc@n;ygm1std`}X-Hwpj567%y&_=P0= z5&3iSKg&liv;Hm;{oN$`sqzK#^X0o1TAxg!?@ywCMZQG7RDS4k>$6GpIVAe6^84gJ zm3OVQzBY-zE{T4qe71a!{OUE&r;=yGitso6R>R;bTbnQu#9Z-SRcxw!R68zB!5h@ona3 zknqou@cZPC$$u-~=3VO(Nc7!F^t0uc%D*oE=q~FsN%Ywy`c3j5$?ub&S!Vqb68$m~ z{VDlN@|Wcw*lqn_68$g|eUbbo`K|I1d#!IkqHjW?A1Oakev15^`>pRrqVGwfFOV;k zFOna2!1~8Y^tmMZZSwo&Ka+2A(E2zMeLE8UWcfMr^W={mw!WN1e}P2b@k{f)Nce|H z_^LDyNE9BS6Upi)e#Bu9ulIZ)9xc*1TkCNZ= zt@*tq#y>!!zxg}!x03L!N%-lf%`YI~7nAVEAq9f3kiWiGDhX{v-LL^2g*q`Pupt zB>Iyi`c~!UyO8klB>X4xC*)7c-}a03ok{ffk?7}NFkeK%uO{Jtl>b9MLSX`pB#1o09M`Bz)eV=4X=d zb4d8lr+Vd zkCEtC$ZwY4CO@&Z^|MIyFOcXD$)A=#E8n@U^?gY6{YdnS<=4oU$h#U^UzLB1gdah|ua@5`zeE1b80&YE=-(&NS8rjy z5eXkn!iW6Ld>s9w^(0`ME@v>$1zhrTmJRi%&#Xg{$>*W75T_k z=A%gXZg+qfXCR3_g@k`izEpmryr+%zxg`3068%p3&*cxxhqtx9K8e0DiQXfhE1xg_ z#@*KMAkn`^q7Uz2zCOuuNcg=S&3{e8e?!9G(#d>B621!wpWVg$bQ1nq68>ZPf61Sa zkBYZGhD6_zM4u)9r2Gu|xJ2s{N%TEP^ab*T@YkN^YZ2LX@jhvM53QcqF*GxN`9?;s}$?Ikm%z{^eOUViSiV^P z9r>N|N9E7Um&?}}Y{zX(;<(L79Jhmfl6)U|xBLY8N%D*2SIMuH-!6YZ{-FF%@_)*Q z4zc4lC-HsJj>P$Nlpi3UE}tp?oczo3OXau7@0C9we@_0Yyff5}+la(*V@VwMF8PP# zhs%$YpCtdhe1Uwi{5$eH<&Vq%B7af7=3{o;CM1sAoW%ThlOHIbB0pCCDfwsQUzT4h zzfQijgP*GrxUR_%{a&XEemfep?ZWn7Ed0#D^*`?uo12!O>%@*s^W=?6&B#t4=UdOp z$WHUEr{}oGR&2OEo}9FazFpo=OZYbMK^)(zJI9?pDs6&q^YJ`SHpZCX@MAL-AG`7X zUey01AlzH|p_+hm3pmjKaiagjxuvEKNJ{nOW#A)G?%dp*3{PGz@4aLv*a#$Pv2b2*vURF3m- zQ1=45=<9Uupsoa6!|Qb8;X?72g>TnK=sNf|{5TWqc*?3=(lLKH;YKig{^CN;!>t-O zw8W2cIe5zR?(^M0ZZE;jH|I|el8^b$rmtQ%^8&)ek6JqcGWRS{`1@j9X-dp!CTpQc&X3NM^wyT3v>;%-yd=4 ec>kj%??s2VxdIj>4qjRYbQjSja);l-&Hn-)WjE9S literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/makefile b/gpio_bitfield_cpu1/CPU1_RAM/makefile new file mode 100644 index 0000000..7539e9d --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/makefile @@ -0,0 +1,154 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +CG_TOOL_ROOT := /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./F2837xD_GlobalVariableDefs.obj" \ +"./F2837xD_Gpio.obj" \ +"./F2837xD_SysCtrl.obj" \ +"./F2837xD_usDelay.obj" \ +"./gpio_bitfield_main_cpu1.obj" \ +"./device/F2837xD_CodeStartBranch.obj" \ +"./device/device.obj" \ +"../2837xD_RAM_lnk_cpu1.cmd" \ +"../F2837xD_Headers_nonBIOS_cpu1.cmd" \ +"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := rm -rf +RMDIR := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include device/subdir_vars.mk +-include subdir_rules.mk +-include device/subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +gpio_bitfield_cpu1.out + +EXE_OUTPUTS__QUOTED += \ +"gpio_bitfield_cpu1.out" + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(LIB_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "gpio_bitfield_cpu1.out" + +# Tool invocations +gpio_bitfield_cpu1.out: $(OBJS) $(CMD_SRCS) $(LIB_SRCS) $(GEN_CMDS) + @echo 'C2000 Linker - building target: "$@"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --define=DEBUG --define=CPU1 --define=_DUAL_HEADERS --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi -z -m"gpio_bitfield_cpu1.map" --stack_size=0x100 --warn_sections -i"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib" -i"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="gpio_bitfield_cpu1_linkInfo.xml" --entry_point=code_start --rom_model -o "gpio_bitfield_cpu1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(EXE_OUTPUTS__QUOTED) + -$(RM) "F2837xD_GlobalVariableDefs.obj" "F2837xD_Gpio.obj" "F2837xD_SysCtrl.obj" "F2837xD_usDelay.obj" "gpio_bitfield_main_cpu1.obj" "device/F2837xD_CodeStartBranch.obj" "device/device.obj" + -$(RM) "F2837xD_GlobalVariableDefs.d" "F2837xD_Gpio.d" "F2837xD_SysCtrl.d" "gpio_bitfield_main_cpu1.d" "device/device.d" + -$(RM) "F2837xD_usDelay.d" "device/F2837xD_CodeStartBranch.d" + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/objects.mk b/gpio_bitfield_cpu1/CPU1_RAM/objects.mk new file mode 100644 index 0000000..ad64ce9 --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/sources.mk b/gpio_bitfield_cpu1/CPU1_RAM/sources.mk new file mode 100644 index 0000000..beb2fed --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/sources.mk @@ -0,0 +1,110 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +SA_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ +device \ + diff --git a/gpio_bitfield_cpu1/CPU1_RAM/subdir_rules.mk b/gpio_bitfield_cpu1/CPU1_RAM/subdir_rules.mk new file mode 100644 index 0000000..b512c3d --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/subdir_rules.mk @@ -0,0 +1,18 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'C2000 Compiler - building file: "$<"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1" --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/device" --include_path="/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/" --include_path="/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --include_path="/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/headers/include" --include_path="/Users/gmarx/ti/C2000Ware_26_00_00_00/device_support/f2837xd/common/include" --define=DEBUG --define=CPU1 --define=_DUAL_HEADERS --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="$(basename $(= 16006000 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanaRegsFile") +#else +#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); +#endif +volatile struct CAN_REGS CanaRegs; +#endif // __TI_COMPILER_VERSION__ >= 16006000 + +#if __TI_COMPILER_VERSION__ >= 16006000 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanbRegsFile") +#else +#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); +#endif +volatile struct CAN_REGS CanbRegs; +#endif // __TI_COMPILER_VERSION__ >= 16006000 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1RegsFile") +#else +#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); +#endif +volatile struct CLA_REGS Cla1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb1DataExchRegs,"Clb1DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb2DataExchRegs,"Clb2DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb3DataExchRegs,"Clb3DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4DataExchRegsFile") +#else +#pragma DATA_SECTION(Clb4DataExchRegs,"Clb4DataExchRegsFile"); +#endif +volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb1LogicCfgRegs,"Clb1LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb2LogicCfgRegs,"Clb2LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb3LogicCfgRegs,"Clb3LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4LogicCfgRegsFile") +#else +#pragma DATA_SECTION(Clb4LogicCfgRegs,"Clb4LogicCfgRegsFile"); +#endif +volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb1LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb1LogicCtrlRegs,"Clb1LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb2LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb2LogicCtrlRegs,"Clb2LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb3LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb3LogicCtrlRegs,"Clb3LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Clb4LogicCtrlRegsFile") +#else +#pragma DATA_SECTION(Clb4LogicCtrlRegs,"Clb4LogicCtrlRegsFile"); +#endif +volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClbXbarRegsFile") +#else +#pragma DATA_SECTION(ClbXbarRegs,"ClbXbarRegsFile"); +#endif +volatile struct CLB_XBAR_REGS ClbXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClkCfgRegsFile") +#else +#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); +#endif +volatile struct CLK_CFG_REGS ClkCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss1RegsFile") +#else +#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss2RegsFile") +#else +#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss3RegsFile") +#else +#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss4RegsFile") +#else +#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss5RegsFile") +#else +#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss6RegsFile") +#else +#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss7RegsFile") +#else +#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss8RegsFile") +#else +#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuSysRegsFile") +#else +#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); +#endif +volatile struct CPU_SYS_REGS CpuSysRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacaRegsFile") +#else +#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); +#endif +volatile struct DAC_REGS DacaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacbRegsFile") +#else +#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); +#endif +volatile struct DAC_REGS DacbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DaccRegsFile") +#else +#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); +#endif +volatile struct DAC_REGS DaccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmCommonRegsFile") +#else +#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); +#endif +volatile struct DCSM_COMMON_REGS DcsmCommonRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1RegsFile") +#else +#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); +#endif +volatile struct DCSM_Z1_REGS DcsmZ1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2RegsFile") +#else +#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); +#endif +volatile struct DCSM_Z2_REGS DcsmZ2Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DevCfgRegsFile") +#else +#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); +#endif +volatile struct DEV_CFG_REGS DevCfgRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaClaSrcSelRegsFile") +#else +#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); +#endif +volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); +#endif +volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); +#endif +volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1RegsFile") +#else +#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); +#endif +volatile struct EMIF_REGS Emif1Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2RegsFile") +#else +#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); +#endif +volatile struct EMIF_REGS Emif2Regs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm7RegsFile") +#else +#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); +#endif +volatile struct EPWM_REGS EPwm7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm8RegsFile") +#else +#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); +#endif +volatile struct EPWM_REGS EPwm8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm9RegsFile") +#else +#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); +#endif +volatile struct EPWM_REGS EPwm9Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm10RegsFile") +#else +#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); +#endif +volatile struct EPWM_REGS EPwm10Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm11RegsFile") +#else +#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); +#endif +volatile struct EPWM_REGS EPwm11Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm12RegsFile") +#else +#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); +#endif +volatile struct EPWM_REGS EPwm12Regs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwmXbarRegsFile") +#else +#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); +#endif +volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep3RegsFile") +#else +#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); +#endif +volatile struct EQEP_REGS EQep3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0CtrlRegsFile") +#else +#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); +#endif +volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0EccRegsFile") +#else +#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); +#endif +volatile struct FLASH_ECC_REGS Flash0EccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2cbRegsFile") +#else +#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); +#endif +volatile struct I2C_REGS I2cbRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("InputXbarRegsFile") +#else +#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif // ifdef CPU1 + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU1 IpcRegs; +#endif // ifdef CPU1 + +#ifdef CPU2 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU2 IpcRegs; +#endif // ifdef CPU2 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemoryErrorRegsFile") +#else +#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); +#endif +volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemCfgRegsFile") +#else +#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); +#endif +volatile struct MEM_CFG_REGS MemCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct McBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct McBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("NmiIntruptRegsFile") +#else +#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); +#endif +volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("OutputXbarRegsFile") +#else +#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("RomPrefetchRegsFile") +#else +#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); +#endif +volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("RomWaitStateRegsFile") +#else +#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); +#endif +volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScidRegsFile") +#else +#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); +#endif +volatile struct SCI_REGS ScidRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm1RegsFile") +#else +#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm2RegsFile") +#else +#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpibRegsFile") +#else +#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); +#endif +volatile struct SPI_REGS SpibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpicRegsFile") +#else +#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); +#endif +volatile struct SPI_REGS SpicRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SyncSocRegsFile") +#else +#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); +#endif +volatile struct SYNC_SOC_REGS SyncSocRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("UidRegsFile") +#else +#pragma DATA_SECTION(UidRegs,"UidRegsFile"); +#endif +volatile struct UID_REGS UidRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("UppRegsFile") +#else +#pragma DATA_SECTION(UppRegs,"UppRegsFile"); +#endif +volatile struct UPP_REGS UppRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("WdRegsFile") +#else +#pragma DATA_SECTION(WdRegs,"WdRegsFile"); +#endif +volatile struct WD_REGS WdRegs; + +#ifdef CPU1 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XbarRegsFile") +#else +#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); +#endif +volatile struct XBAR_REGS XbarRegs; +#endif // ifdef CPU1 + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintRegsFile") +#else +#pragma DATA_SECTION(XintRegs,"XintRegsFile"); +#endif +volatile struct XINT_REGS XintRegs; + + + +//=========================================================================== +// End of file. +//=========================================================================== + + diff --git a/gpio_bitfield_cpu1/F2837xD_Gpio.c b/gpio_bitfield_cpu1/F2837xD_Gpio.c new file mode 100644 index 0000000..d6c8aef --- /dev/null +++ b/gpio_bitfield_cpu1/F2837xD_Gpio.c @@ -0,0 +1,506 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio.c +// +// TITLE: GPIO module support functions +// +//########################################################################### +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//Low-level functions for GPIO configuration (CPU1 only) +// + +#ifdef CPU1 + // + // InitGpio - Sets all pins to be muxed to GPIO in input mode. + // Also resets CPU control to CPU1 and disables open + // drain and polarity inversion and sets the qualification to + // synchronous. Also unlocks all GPIOs. Only one CPU should call + // this function. + // + void InitGpio() + { + volatile Uint32 *gpioBaseAddr; + Uint16 regOffset; + + // + //Disable pin locks + // + EALLOW; + GpioCtrlRegs.GPALOCK.all = 0x00000000; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; + GpioCtrlRegs.GPDLOCK.all = 0x00000000; + GpioCtrlRegs.GPELOCK.all = 0x00000000; + GpioCtrlRegs.GPFLOCK.all = 0x00000000; + + // + // Fill all registers with zeros. Writing to each register separately + // for six GPIO modules would make this function *very* long. + // Fortunately, we'd be writing them all with zeros anyway, so this + // saves a lot of space. + // + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; + for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) + { + // + //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset + //0x0C in each register group of 0x40 words. Since this is a + //32-bit pointer, the addresses must be divided by 2. + // + if (regOffset % (0x40/2) != (0x0C/2)) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + } + + gpioBaseAddr = (Uint32 *)&GpioDataRegs; + for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + + EDIS; + } + + // + // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The + // appropriate parameters can be found in the GPIO Muxed + // Pins table(4.4) in the datasheet. Use the GPIO index + // row (0 to 15) to select a muxing option for the GPIO. + // + void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *mux, *gmux, *csel; + Uint16 pin32, pin16, pin8; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pin8 = gpioNumber % 8; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Sanity check for valid cpu and peripheral values + // + if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) + return; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyCSEL1-4. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + mux = gpioBaseAddr + GPYMUX + pin32/16; + gmux = gpioBaseAddr + GPYGMUX + pin32/16; + csel = gpioBaseAddr + GPYCSEL + pin32/8; + + // + //Now for the actual function + // + EALLOW; + + // + //To change the muxing, set the peripheral mux to 0/GPIO first to avoid + //glitches, then change the group mux, then set the peripheral mux to + //its target value. Finally, set the CPU select. This procedure is + //described in the TRM. Unfortunately, since we don't know the pin in + //advance we can't hardcode a bitfield reference, so there's some + //tricky bit twiddling here. + // + *mux &= ~(0x3UL << (2*pin16)); + *gmux &= ~(0x3UL << (2*pin16)); + *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); + *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); + + *csel &= ~(0x3L << (4*pin8)); + *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); + + // + //WARNING: This code does not touch the analog mode select registers, + //which are needed to give the USB module control of its IOs. + // + EDIS; + } + + // + // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the + // specified pin. + // + //The flags are a 16-bit mask produced by ORing together options. + //For input pins, the valid flags are: + //GPIO_PULLUP Enable pull-up + //GPIO_INVERT Enable input polarity inversion + //GPIO_SYNC Synchronize the input latch to PLLSYSCLK + // (default -- you don't need to specify this) + //GPIO_QUAL3 Use 3-sample qualification + //GPIO_QUAL6 Use 6-sample qualification + //GPIO_ASYNC Do not use synchronization or qualification + //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) + // + //For output pins, the valid flags are: + //GPIO_OPENDRAIN Output in open drain mode + //GPIO_PULLUP If open drain enabled, also enable the pull-up + //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. + // + //With no flags, the default input state is synchronous with no + //pull-up or polarity inversion. The default output state is + //the standard digital output. + // + void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *inv, *odr, *qsel; + Uint32 pin32, pin16, pinMask, qual; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + inv = gpioBaseAddr + GPYINV; + odr = gpioBaseAddr + GPYODR; + qsel = gpioBaseAddr + GPYQSEL + pin32/16; + + EALLOW; + + // + //Set the data direction + // + *dir &= ~pinMask; + if (output == 1) + { + // + //Output, with optional open drain mode and pull-up + // + *dir |= pinMask; + + // + //Enable open drain if necessary + // + if (flags & GPIO_OPENDRAIN) + { + *odr |= pinMask; + } + else + { + *odr &= ~pinMask; + } + + // + //Enable pull-up if necessary. Open drain mode must be active. + // + if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + } + else + { + // + //Input, with optional pull-up, qualification, and polarity + //inversion + // + *dir &= ~pinMask; + + // + //Enable pull-up if necessary + // + if (flags & GPIO_PULLUP) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + + // + //Invert polarity if necessary + // + if (flags & GPIO_INVERT) + { + *inv |= pinMask; + } + else + { + *inv &= ~pinMask; + } + } + + // + //Extract the qualification parameter and load it into the register. + //This is also needed for open drain outputs, so we might as well do it + //all the time. + // + qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; + *qsel &= ~(0x3L << (2 * pin16)); + if (qual != 0x0) + { + *qsel |= qual << (2 * pin16); + } + + EDIS; + } + + // + // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the + // specified pin. + // The valid flags are: + // GPIO_UNLOCK - Unlock the pin setup register bits for + // the specified pin + // GPIO_LOCK - Lock the pin setup register bits for the + // specified pin + // + void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *lock; + Uint32 pin32, pinMask; + + pin32 = gpioNumber % 32; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + lock = gpioBaseAddr + GPYLOCK; + + EALLOW; + if(flags) + { + //Lock the pin + *lock |= pinMask; + } + else + { + //Unlock the pin + *lock &= ~pinMask; + } + EDIS; + } + + // + //External interrupt setup + // + void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin + EDIS; + } + + // + //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded + // GPIOs on the 176PTP package: + // GPIOs Grp Bits + // 95-132 C 31 + // D 31:0 + // E 4:0 + // 134-168 E 31:6 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor176Pin() + { + EALLOW; + GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded + // GPIOs on the 100PZ package: + // GPIOs Grp Bits + // 0-1 A 1:0 + // 5-9 A 9:5 + // 22-40 A 31:22 + // B 8:0 + // 44-57 B 25:12 + // 67-68 C 4:3 + // 74-77 C 13:10 + // 79-83 C 19:15 + // 93-168 C 31:29 + // D 31:0 + // E 31:0 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor100Pin() + { + EALLOW; + GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31 + GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57 + GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function + // this takes care of enabling IO pullups. + // + void GPIO_EnableUnbondedIOPullups() + { + // + //bits 8-10 have pin count + // + unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ; + + // + //5 = 100 pin + //6 = 176 pin + //7 = 337 pin + // + if(pin_count == 5) + { + GPIO_EnableUnbondedIOPullupsFor100Pin(); + } + else if (pin_count == 6) + { + GPIO_EnableUnbondedIOPullupsFor176Pin(); + } + else + { + //do nothing - this is 337 pin package + } + } + +#endif //CPU1 + +// +// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that +// this returns the actual state of the pin, not the state of +// the output latch. +// +Uint16 GPIO_ReadPin(Uint16 gpioNumber) +{ + volatile Uint32 *gpioDataReg; + Uint16 pinVal; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; + + return pinVal; +} + +// +// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. +// +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinMask = 1UL << (gpioNumber % 32); + + if (outVal == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } +} + +// +// End of file +// diff --git a/gpio_bitfield_cpu1/F2837xD_Headers_nonBIOS_cpu1.cmd b/gpio_bitfield_cpu1/F2837xD_Headers_nonBIOS_cpu1.cmd new file mode 100644 index 0000000..706718d --- /dev/null +++ b/gpio_bitfield_cpu1/F2837xD_Headers_nonBIOS_cpu1.cmd @@ -0,0 +1,247 @@ +MEMORY +{ + PAGE 0: /* Program Memory */ + PAGE 1: /* Data Memory */ + ACCESSPROTECTION : origin = 0x0005F4C0, length = 0x00000040 + ADCA : origin = 0x00007400, length = 0x00000080 + ADCB : origin = 0x00007480, length = 0x00000080 + ADCC : origin = 0x00007500, length = 0x00000080 + ADCD : origin = 0x00007580, length = 0x00000080 + ADCARESULT : origin = 0x00000B00, length = 0x00000018 + ADCBRESULT : origin = 0x00000B20, length = 0x00000018 + ADCCRESULT : origin = 0x00000B40, length = 0x00000018 + ADCDRESULT : origin = 0x00000B60, length = 0x00000018 + ANALOGSUBSYS : origin = 0x0005D180, length = 0x00000048 + CANA : origin = 0x00048000, length = 0x00000200 + CANB : origin = 0x0004A000, length = 0x00000200 + CLA1 : origin = 0x00001400, length = 0x00000080 + CLB1DATAEXCH : origin = 0x00003200, length = 0x00000200 + CLB2DATAEXCH : origin = 0x00003600, length = 0x00000200 + CLB3DATAEXCH : origin = 0x00003A00, length = 0x00000200 + CLB4DATAEXCH : origin = 0x00003E00, length = 0x00000200 + CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052 + CLB2LOGICCFG : origin = 0x00003400, length = 0x00000052 + CLB3LOGICCFG : origin = 0x00003800, length = 0x00000052 + CLB4LOGICCFG : origin = 0x00003C00, length = 0x00000052 + CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040 + CLB2LOGICCTRL : origin = 0x00003500, length = 0x00000040 + CLB3LOGICCTRL : origin = 0x00003900, length = 0x00000040 + CLB4LOGICCTRL : origin = 0x00003D00, length = 0x00000040 + CLBXBAR : origin = 0x00007A40, length = 0x00000040 + CLKCFG : origin = 0x0005D200, length = 0x00000032 + CMPSS1 : origin = 0x00005C80, length = 0x00000020 + CMPSS2 : origin = 0x00005CA0, length = 0x00000020 + CMPSS3 : origin = 0x00005CC0, length = 0x00000020 + CMPSS4 : origin = 0x00005CE0, length = 0x00000020 + CMPSS5 : origin = 0x00005D00, length = 0x00000020 + CMPSS6 : origin = 0x00005D20, length = 0x00000020 + CMPSS7 : origin = 0x00005D40, length = 0x00000020 + CMPSS8 : origin = 0x00005D60, length = 0x00000020 + CPUTIMER0 : origin = 0x00000C00, length = 0x00000008 + CPUTIMER1 : origin = 0x00000C08, length = 0x00000008 + CPUTIMER2 : origin = 0x00000C10, length = 0x00000008 + CPUSYS : origin = 0x0005D300, length = 0x00000082 + DACA : origin = 0x00005C00, length = 0x00000008 + DACB : origin = 0x00005C10, length = 0x00000008 + DACC : origin = 0x00005C20, length = 0x00000008 + DCSMCOMMON : origin = 0x0005F070, length = 0x00000008 + DCSMZ1 : origin = 0x0005F000, length = 0x00000024 + DCSMZ2 : origin = 0x0005F040, length = 0x00000024 + DEVCFG : origin = 0x0005D000, length = 0x0000012E + DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A + DMA : origin = 0x00001000, length = 0x00000200 + ECAP1 : origin = 0x00005000, length = 0x00000020 + ECAP2 : origin = 0x00005020, length = 0x00000020 + ECAP3 : origin = 0x00005040, length = 0x00000020 + ECAP4 : origin = 0x00005060, length = 0x00000020 + ECAP5 : origin = 0x00005080, length = 0x00000020 + ECAP6 : origin = 0x000050A0, length = 0x00000020 + EMIF1CONFIG : origin = 0x0005F480, length = 0x00000020 + EMIF2CONFIG : origin = 0x0005F4A0, length = 0x00000020 + EMIF1 : origin = 0x00047000, length = 0x00000070 + EMIF2 : origin = 0x00047800, length = 0x00000070 + EPWM1 : origin = 0x00004000, length = 0x00000100 + EPWM2 : origin = 0x00004100, length = 0x00000100 + EPWM3 : origin = 0x00004200, length = 0x00000100 + EPWM4 : origin = 0x00004300, length = 0x00000100 + EPWM5 : origin = 0x00004400, length = 0x00000100 + EPWM6 : origin = 0x00004500, length = 0x00000100 + EPWM7 : origin = 0x00004600, length = 0x00000100 + EPWM8 : origin = 0x00004700, length = 0x00000100 + EPWM9 : origin = 0x00004800, length = 0x00000100 + EPWM10 : origin = 0x00004900, length = 0x00000100 + EPWM11 : origin = 0x00004A00, length = 0x00000100 + EPWM12 : origin = 0x00004B00, length = 0x00000100 + EPWMXBAR : origin = 0x00007A00, length = 0x00000040 + EQEP1 : origin = 0x00005100, length = 0x00000022 + EQEP2 : origin = 0x00005140, length = 0x00000022 + EQEP3 : origin = 0x00005180, length = 0x00000022 + FLASH0CTRL : origin = 0x0005F800, length = 0x00000182 + FLASH0ECC : origin = 0x0005FB00, length = 0x00000028 + FLASHPUMPSEMAPHORE : origin = 0x00050024, length = 0x00000002 + GPIOCTRL : origin = 0x00007C00, length = 0x00000180 + GPIODATA : origin = 0x00007F00, length = 0x00000030 + I2CA : origin = 0x00007300, length = 0x00000022 + I2CB : origin = 0x00007340, length = 0x00000022 + INPUTXBAR : origin = 0x00007900, length = 0x00000020 + IPC : origin = 0x00050000, length = 0x00000024 + MEMORYERROR : origin = 0x0005F500, length = 0x00000040 + MEMCFG : origin = 0x0005F400, length = 0x00000080 + MCBSPA : origin = 0x00006000, length = 0x00000024 + MCBSPB : origin = 0x00006040, length = 0x00000024 + NMIINTRUPT : origin = 0x00007060, length = 0x00000007 + OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040 + PIECTRL : origin = 0x00000CE0, length = 0x0000001A + PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200 + ROMPREFETCH : origin = 0x0005E608, length = 0x00000002 + ROMWAITSTATE : origin = 0x0005F540, length = 0x00000002 + SCIA : origin = 0x00007200, length = 0x00000010 + SCIB : origin = 0x00007210, length = 0x00000010 + SCIC : origin = 0x00007220, length = 0x00000010 + SCID : origin = 0x00007230, length = 0x00000010 + SDFM1 : origin = 0x00005E00, length = 0x00000080 + SDFM2 : origin = 0x00005E80, length = 0x00000080 + SPIA : origin = 0x00006100, length = 0x00000010 + SPIB : origin = 0x00006110, length = 0x00000010 + SPIC : origin = 0x00006120, length = 0x00000010 + SYNCSOC : origin = 0x00007940, length = 0x00000006 + UID : origin = 0x000703C0, length = 0x00000010 + UPP : origin = 0x00006200, length = 0x00000048 + WD : origin = 0x00007000, length = 0x0000002B + XBAR : origin = 0x00007920, length = 0x00000020 + XINT : origin = 0x00007070, length = 0x0000000B + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ +UNION run = PIEVECTTABLE +{ + PieVectTableFile + GROUP + { + EmuKeyVar + EmuBModeVar + EmuBootPinsVar + FlashCallbackVar + FlashScalingVar + } +} + + AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT + AdcaRegsFile : > ADCA, type=NOINIT + AdcbRegsFile : > ADCB, type=NOINIT + AdccRegsFile : > ADCC, type=NOINIT + AdcdRegsFile : > ADCD, type=NOINIT + AdcaResultRegsFile : > ADCARESULT, type=NOINIT + AdcbResultRegsFile : > ADCBRESULT, type=NOINIT + AdccResultRegsFile : > ADCCRESULT, type=NOINIT + AdcdResultRegsFile : > ADCDRESULT, type=NOINIT + AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT + CanaRegsFile : > CANA, type=NOINIT + CanbRegsFile : > CANB, type=NOINIT + Cla1RegsFile : > CLA1, type=NOINIT + Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT + Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT + Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT + Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT + Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT + Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT + Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT + Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT + Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT + Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT + Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT + Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT + ClbXbarRegsFile : > CLBXBAR, type=NOINIT + ClkCfgRegsFile : > CLKCFG, type=NOINIT + Cmpss1RegsFile : > CMPSS1, type=NOINIT + Cmpss2RegsFile : > CMPSS2, type=NOINIT + Cmpss3RegsFile : > CMPSS3, type=NOINIT + Cmpss4RegsFile : > CMPSS4, type=NOINIT + Cmpss5RegsFile : > CMPSS5, type=NOINIT + Cmpss6RegsFile : > CMPSS6, type=NOINIT + Cmpss7RegsFile : > CMPSS7, type=NOINIT + Cmpss8RegsFile : > CMPSS8, type=NOINIT + CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT + CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT + CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT + CpuSysRegsFile : > CPUSYS, type=NOINIT + DacaRegsFile : > DACA, type=NOINIT + DacbRegsFile : > DACB, type=NOINIT + DaccRegsFile : > DACC, type=NOINIT + DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT + DcsmZ1RegsFile : > DCSMZ1, type=NOINIT + DcsmZ2RegsFile : > DCSMZ2, type=NOINIT + DevCfgRegsFile : > DEVCFG, type=NOINIT + DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT + DmaRegsFile : > DMA, type=NOINIT + ECap1RegsFile : > ECAP1, type=NOINIT + ECap2RegsFile : > ECAP2, type=NOINIT + ECap3RegsFile : > ECAP3, type=NOINIT + ECap4RegsFile : > ECAP4, type=NOINIT + ECap5RegsFile : > ECAP5, type=NOINIT + ECap6RegsFile : > ECAP6, type=NOINIT + Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT + Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT + Emif1RegsFile : > EMIF1, type=NOINIT + Emif2RegsFile : > EMIF2, type=NOINIT + EPwm1RegsFile : > EPWM1, type=NOINIT + EPwm2RegsFile : > EPWM2, type=NOINIT + EPwm3RegsFile : > EPWM3, type=NOINIT + EPwm4RegsFile : > EPWM4, type=NOINIT + EPwm5RegsFile : > EPWM5, type=NOINIT + EPwm6RegsFile : > EPWM6, type=NOINIT + EPwm7RegsFile : > EPWM7, type=NOINIT + EPwm8RegsFile : > EPWM8, type=NOINIT + EPwm9RegsFile : > EPWM9, type=NOINIT + EPwm10RegsFile : > EPWM10, type=NOINIT + EPwm11RegsFile : > EPWM11, type=NOINIT + EPwm12RegsFile : > EPWM12, type=NOINIT + EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT + EQep1RegsFile : > EQEP1, type=NOINIT + EQep2RegsFile : > EQEP2, type=NOINIT + EQep3RegsFile : > EQEP3, type=NOINIT + Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT + Flash0EccRegsFile : > FLASH0ECC, type=NOINIT + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, type=NOINIT + GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT + GpioDataRegsFile : > GPIODATA, type=NOINIT + I2caRegsFile : > I2CA, type=NOINIT + I2cbRegsFile : > I2CB, type=NOINIT + InputXbarRegsFile : > INPUTXBAR, type=NOINIT + IpcRegsFile : > IPC, type=NOINIT + MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT + MemCfgRegsFile : > MEMCFG, type=NOINIT + McbspaRegsFile : > MCBSPA, type=NOINIT + McbspbRegsFile : > MCBSPB, type=NOINIT + NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT + OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT + PieCtrlRegsFile : > PIECTRL, type=NOINIT + RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT + RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT + SciaRegsFile : > SCIA, type=NOINIT + ScibRegsFile : > SCIB, type=NOINIT + ScicRegsFile : > SCIC, type=NOINIT + ScidRegsFile : > SCID, type=NOINIT + Sdfm1RegsFile : > SDFM1, type=NOINIT + Sdfm2RegsFile : > SDFM2, type=NOINIT + SpiaRegsFile : > SPIA, type=NOINIT + SpibRegsFile : > SPIB, type=NOINIT + SpicRegsFile : > SPIC, type=NOINIT + SyncSocRegsFile : > SYNCSOC, type=NOINIT + UppRegsFile : > UPP, type=NOINIT + WdRegsFile : > WD, type=NOINIT + UidRegsFile : > UID, type=NOINIT + XbarRegsFile : > XBAR, type=NOINIT + XintRegsFile : > XINT, type=NOINIT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/gpio_bitfield_cpu1/F2837xD_SysCtrl.c b/gpio_bitfield_cpu1/F2837xD_SysCtrl.c new file mode 100644 index 0000000..7352469 --- /dev/null +++ b/gpio_bitfield_cpu1/F2837xD_SysCtrl.c @@ -0,0 +1,1363 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl.c +// +// TITLE: F2837xD Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +#define TMR1SYSCLKCTR 0xF0000000 +#define TMR2INPCLKCTR 0x800 + +// +// Functions that will be run from RAM need to be assigned to a different +// section. This section will then be mapped to a load and run address using +// the linker cmd file. +// +// *IMPORTANT* +// +// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM +// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM +// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. +// +#ifndef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #pragma CODE_SECTION(FlashOff, "ramfuncs"); + #endif + #endif +#endif + +// +// Macro used for adding delay between 2 consecutive writes to CLKSRCCTL1 +// register. +// Delay = 300 NOPs +// +#define SYSCTRL_CLKSRCCTL1_DELAY asm(" RPT #250 || NOP \n RPT #50 || NOP") + +// +// InitSysCtrl - Initialization of system resources. +// +void InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + +#ifdef _FLASH + // + // Copy time critical code and Flash setup code to RAM. This includes the + // following functions: InitFlash() + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart + // symbols are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + InitFlash(); +#endif + + // + // *IMPORTANT* + // + // The Device_cal function, which copies the ADC & oscillator calibration + // values from TI reserved OTP into the appropriate trim registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC and + // oscillators to function according to specification. The clocks to the + // ADC MUST be enabled before calling this function. + // + // See the device data manual and/or the ADC Reference Manual for more + // information. + // +#ifdef CPU1 + EALLOW; + + // + // Enable pull-ups on unbonded IOs as soon as possible to reduce power + // consumption. + // + GPIO_EnableUnbondedIOPullups(); + + // + // Check if the device is trimmed + // + if((DevCfgRegs.PARTIDL.bit.QUAL == 0x0) && + (AnalogSubsysRegs.ANAREFTRIMA.all == 0x0)) + { + ConfigureTMXAnalogTrim(); + } + + EDIS; + + // + // Initialize the PLL control: SYSPLLMULT and SYSCLKDIVSEL. + // + // Defined options to be passed as arguments to this function are defined + // in F2837xD_Examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // PLLSYSCLK is configured to frequencies above 194 MHz. + // + // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) + // +#ifdef _LAUNCHXL_F28379D + InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2); +#else + InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2); +#endif // _LAUNCHXL_F28379D + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the InitSysCtrl function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // + Device_cal(); +#endif +#endif // CPU1 + + // + // Turn on all peripherals + // + InitPeripheralClocks(); +} + +// +// InitPeripheralClocks - Initializes the clocks for the peripherals. +// +// Note: In order to reduce power consumption, turn off the clocks to any +// peripheral that is not specified for your part-number or is not used in the +// application +// +void InitPeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.bit.CLA1 = 1; + CpuSysRegs.PCLKCR0.bit.DMA = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR0.bit.HRPWM = 1; +#endif + + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; + CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; +#endif + + CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; + + CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; + + CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; + + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + CpuSysRegs.PCLKCR7.bit.SCI_D = 1; + + CpuSysRegs.PCLKCR8.bit.SPI_A = 1; + CpuSysRegs.PCLKCR8.bit.SPI_B = 1; + CpuSysRegs.PCLKCR8.bit.SPI_C = 1; + + CpuSysRegs.PCLKCR9.bit.I2C_A = 1; + CpuSysRegs.PCLKCR9.bit.I2C_B = 1; + + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + CpuSysRegs.PCLKCR10.bit.CAN_B = 1; + + CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; + CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR11.bit.USB_A = 1; + + CpuSysRegs.PCLKCR12.bit.uPP_A = 1; +#endif + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; + + CpuSysRegs.PCLKCR16.bit.DAC_A = 1; + CpuSysRegs.PCLKCR16.bit.DAC_B = 1; + CpuSysRegs.PCLKCR16.bit.DAC_C = 1; + + EDIS; +} + +// +// DisablePeripheralClocks - Gates-off all peripheral clocks. +// +void DisablePeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.all = 0; + CpuSysRegs.PCLKCR1.all = 0; + CpuSysRegs.PCLKCR2.all = 0; + CpuSysRegs.PCLKCR3.all = 0; + CpuSysRegs.PCLKCR4.all = 0; + CpuSysRegs.PCLKCR6.all = 0; + CpuSysRegs.PCLKCR7.all = 0; + CpuSysRegs.PCLKCR8.all = 0; + CpuSysRegs.PCLKCR9.all = 0; + CpuSysRegs.PCLKCR10.all = 0; + CpuSysRegs.PCLKCR11.all = 0; + CpuSysRegs.PCLKCR12.all = 0; + CpuSysRegs.PCLKCR13.all = 0; + CpuSysRegs.PCLKCR14.all = 0; + CpuSysRegs.PCLKCR16.all = 0; + + EDIS; +} + +// +// InitFlash - This function initializes the Flash Control registers. +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void InitFlash(void) +{ + EALLOW; + + // + // The default value of VREADST is good enough for the flash to power up + // properly at the INTOSC frequency. Below VREADST configuration covers up + // to the max frequency possible for this device. This is required for + // proper flash wake up at the higher frequencies if users put it to sleep + // for power saving reason. + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // At reset bank and pump are in sleep. A Flash access will power up the + // bank and pump automatically. + // + // Power up Flash bank and pump. This also sets the fall back mode of + // flash and pump as active. + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; + + // + // Disable Cache and prefetch mechanism before changing wait states + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; + + // + // Set waitstates according to frequency + // + // *CAUTION* + // Minimum waitstates required for the flash operating at a given CPU rate + // must be characterized by TI. Refer to the datasheet for the latest + // information. + // + #if CPU_FRQ_200MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; + #endif + + #if CPU_FRQ_150MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + #if CPU_FRQ_120MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + // + // Enable Cache and prefetch mechanism to improve performance of code + // executed from Flash. + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; + + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// FlashOff - This function powers down the flash +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. Also you must seize the flash pump in +// order to power it down. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void FlashOff(void) +{ + EALLOW; + + // + // Set VREADST to the proper value for the flash banks to power up properly + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // Power down bank + // + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; + + // + // Power down pump + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; + + EDIS; +} + +// +// SeizeFlashPump - Wait until the flash pump is available. Then take control +// of it using the flash pump Semaphore. +// +void SeizeFlashPump(void) +{ + EALLOW; + #ifdef CPU1 + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x2) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x2; + } + #elif defined(CPU2) + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x1) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x1; + } + #endif + EDIS; +} + +// +// ReleaseFlashPump - Release control of the flash pump using the flash pump +// semaphore. +// +void ReleaseFlashPump(void) +{ + EALLOW; + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0; + EDIS; +} + +// +// ServiceDog - This function resets the watchdog timer. +// +// Enable this function for using ServiceDog in the application. +// +void ServiceDog(void) +{ + EALLOW; + WdRegs.WDKEY.bit.WDKEY = 0x0055; + WdRegs.WDKEY.bit.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void DisableDog(void) +{ + volatile Uint16 temp; + + // + // Grab the clock config first so we don't clobber it + // + EALLOW; + temp = WdRegs.WDCR.all & 0x0007; + WdRegs.WDCR.all = 0x0068 | temp; + EDIS; +} + +#ifdef CPU1 +// +// InitSysPll() +// This function initializes the PLL registers. +// Note: +// - The internal oscillator CANNOT be used as the PLL source if the +// PLLSYSCLK is configured to frequencies above 194 MHz. +// +// - This function uses the Watchdog as a monitor for the PLL. The user +// watchdog settings will be modified and restored upon completion. Function +// allows for a minimum re lock attempt for 5 tries. Re lock attempt is carried +// out if either SLIP condition occurs or SYSCLK to Input Clock ratio is off by 10% +// +// - This function uses the following resources to support PLL initialization: +// o Watchdog +// o CPU Timer 1 +// o CPU Timer 2 +// +void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 SCSR, WDCR, WDWCR, intStatus, t1TCR, t1TPR, t1TPRH; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale; + Uint32 t1PRD, t2PRD, ctr1; + float sysclkToInClkError, mult, div; + bool sysclkInvalidFreq=true; + + if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) + { + switch (clock_source) + { + case INT_OSC1: + SysIntOsc1Sel(); + break; + + case INT_OSC2: + SysIntOsc2Sel(); + break; + + case XTAL_OSC: + SysXtalOscSel(); + break; + } + } + + EALLOW; + if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || + fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + Uint16 i; + + // + // This bit is reset only by POR + // + if(DevCfgRegs.SYSDBGCTL.bit.BIT_0 == 1) + { + // + // The user can optionally insert handler code here. This will only + // be executed if a watchdog reset occurred after a failed system + // PLL initialization. See your device user's guide for more + // information. + // + // If the application has a watchdog reset handler, this bit should + // be checked to determine if the watchdog reset occurred because + // of the PLL. + // + // No action here will continue with retrying the PLL as normal. + // + // Failed PLL initialization is due to any of the following: + // - No PLL clock + // - SLIP condition + // - Wrong Frequency + // + } + + // + // Bypass PLL and set dividers to /1 + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase this + // number according to allotted system initialization time. + // + for(i = 0; i < 5; i++) + { + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + } + } + + // + // Set divider to produce slower output frequency to limit current increase + // + if(divsel != PLLCLK_BY_126) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the PLL + // startup sequence. If your application has already cleared the watchdog + // SCRS[WDOVERRIDE] bit this cannot be done. It is recommended not to clear + // this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + SCSR = WdRegs.SCSR.all; + WDCR = WdRegs.WDCR.all; + WDWCR = WdRegs.WDWCR.all; + + // + // Disable windowed functionality, reset counter + // + EALLOW; + WdRegs.WDWCR.all = 0x0; + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + WdRegs.SCSR.all = 0x0; + WdRegs.WDCR.all = 0x28; + + // + // This bit is reset only by power-on-reset (POR) and will not be cleared + // by a WD reset + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 1; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL prior to clearing status bit + // + asm(" RPT #20 || NOP"); + + // + // Service watchdog + // + ServiceDog(); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer counts + // are off by +/- 10%. + // At a minimum, SYSCLK check is performed. Re lock attempt is carried out + // if SLIPS bit is set. This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will be + // aborted by watchdog reset. + // + EALLOW; + while(sysclkInvalidFreq == true) + { + if(ClkCfgRegs.SYSPLLSTS.bit.SLIPS == 1) + { + // + // Bypass PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multipliers, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter to expire + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1); + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL + // + asm(" RPT #20 || NOP"); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = CpuTimer1Regs.TCR.all; + t1PRD = CpuTimer1Regs.PRD.all; + t1TPR = CpuTimer1Regs.TPR.all; + t1TPRH = CpuTimer1Regs.TPRH.all; + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer1Regs.PRD.all = TMR1SYSCLKCTR; // seed timer1 counter + CpuTimer1Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + CpuTimer1Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer1Regs.TCR.bit.TIE = 1; // enable interrupt + + // + // Configure timer2 to count Input clock cycles + // + switch(clock_source) + { + case INT_OSC1: + // Clk Src = INT_OSC1 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x1; + break; + case INT_OSC2: + // Clk Src = INT_OSC2 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x2; + break; + case XTAL_OSC: + // Clk Src = XTAL + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x3; + break; + + } + CpuTimer2Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer2Regs.TCR.bit.TIE = 1; // enable interrupt + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer2Regs.PRD.all = TMR2INPCLKCTR; // seed timer2 counter + CpuTimer2Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + + // + // Stop/Start timer counters + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer1 with value in PRD + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer2 with value in PRD + CpuTimer2Regs.TCR.bit.TIF = 1; // clear timer2 interrupt flag + CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2 + CpuTimer1Regs.TCR.bit.TSS = 0; // start timer1 + + // + // Stop timers if either timer1 or timer2 counters overflow + // + while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); + + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + + // + // Calculate elapsed counts on timer1 + // + ctr1 = TMR1SYSCLKCTR - CpuTimer1Regs.TIM.all; + + // + // Restore timer settings + // + CpuTimer1Regs.TCR.all = t1TCR; + CpuTimer1Regs.PRD.all = t1PRD; + CpuTimer1Regs.TPR.all = t1TPR; + CpuTimer1Regs.TPRH.all = t1TPRH; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float)(imult) + (float)(fmult)/4; + div = (float)((!ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV) ? 1 : (ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV << 1)); + + sysclkToInClkError = (mult/div) - ((float)ctr1/(float)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10) || (sysclkToInClkError < -0.10)); + } + + // + // Clear bit + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 0; + + // + // Restore user watchdog, first resetting counter + // + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + WDCR |= 0x28; // Setup WD key--KEY bits always read 0 + WdRegs.WDCR.all = WDCR; + WdRegs.WDWCR.all = WDWCR; + WdRegs.SCSR.all = SCSR & 0xFFFE; // Mask write to bit 0 (W1toClr) + + // + // Restore state of ST1[INTM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x1)) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x2)) + { + asm(" CLRC DBGM"); + } + + // + // 200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + asm(" RPT #200 || NOP"); + + // + // Set the divider to user value + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + + EDIS; +} +#endif // CPU1 + +// +// InitAuxPll - This function initializes the AUXPLL registers. +// +// Note: For this function to properly detect PLL startup, +// SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +// +// This function will use CPU Timer 2 to monitor a successful lock of the +// AUXPLL. +// +void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 i; + Uint16 counter = 0; + Uint16 started = 0; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale, attempts; + Uint32 t2PRD; + + if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && + (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.AUXPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + switch (clock_source) + { + case INT_OSC2: + AuxIntOsc2Sel(); + break; + + case XTAL_OSC: + AuxXtalOscSel(); + break; + + case AUXCLKIN: + AuxAuxClkSel(); + break; + } + + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; // Bypass AUXPLL + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + // + // Backup Timer 2 settings + // + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // + EALLOW; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x6; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = 0x0; // Divide by 1 + + CpuTimer2Regs.TCR.bit.TSS = 1; // Stop timer + CpuTimer2Regs.PRD.all = 10; // Small PRD value to detect overflow + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + CpuTimer2Regs.TCR.bit.TIE = 0; // Disable timer interrupts + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK/2 while using + // Timer 2 + // + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 0x3; + EDIS; + + while((counter < 5) && (started == 0)) + { + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL + asm(" RPT #20 || NOP"); // Small delay for power down + + // + // Set integer and fractional multiplier, which automatically turns on + // the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Enable AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + + // + // Enable AUXPLLCLK to be fed from AUX PLL + // + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. This is + // used to test that the PLL has successfully started. + // + CpuTimer2Regs.TCR.bit.TRB = 1; // Reload period value + CpuTimer2Regs.TCR.bit.TSS = 0; // Start Timer + + // + // Check to see timer is counting properly + // + for(i = 0; i < 1000; i++) + { + // + // Check overflow flag + // + if(CpuTimer2Regs.TCR.bit.TIF) + { + // + // Clear overflow flag + // + CpuTimer2Regs.TCR.bit.TIF = 1; + + // + // Set flag to indicate PLL started and break out of for-loop + // + started = 1; + break; + } + } + + // + // Stop timer + // + CpuTimer2Regs.TCR.bit.TSS = 1; + counter++; + EDIS; + } + + if(started == 0) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). + // + EALLOW; + ClkCfgRegs.AUXPLLMULT.all = 0; + EDIS; + + // + // The user should put some handler code here based on how this + // condition should be handled in their application. + // + asm(" ESTOP0"); + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + attempts = 0; + while(ClkCfgRegs.AUXPLLSTS.bit.SLIPS && (attempts < 10)) + { + EALLOW; + // + // Bypass AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + asm(" RPT #120 || NOP"); + + // + // Turn off AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1); + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + attempts++; + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; + + // + // Restore Timer 2 configuration + // + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Reload period value + // + CpuTimer2Regs.TCR.bit.TRB = 1; + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +Uint16 CsmUnlock(void) +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; + + DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; + EDIS; + + return(0); +} + +// +// SysIntOsc1Sel - This function switches to Internal Oscillator 1. +// +void SysIntOsc1Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + SYSCTRL_CLKSRCCTL1_DELAY; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysIntOsc2Sel - This function switches to Internal oscillator 2. +// +void SysIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + SYSCTRL_CLKSRCCTL1_DELAY; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + SYSCTRL_CLKSRCCTL1_DELAY; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void SysXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + SYSCTRL_CLKSRCCTL1_DELAY; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxIntOsc2Sel - This function switches to Internal oscillator 2. +// +void AuxIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// AuxXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void AuxXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxAUXCLKOscSel - This function switches to AUXCLKIN (from a GPIO). +// +void AuxAuxClkSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL + EDIS; +} + +// +// IDLE - Enter IDLE mode (single CPU). +// +void IDLE(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; + EDIS; + asm(" IDLE"); +} + +// +// STANDBY - Enter STANDBY mode (single CPU). +// +void STANDBY(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; + EDIS; + asm(" IDLE"); +} + +// +// HALT - Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +// +void HALT(void) +{ +#if defined(CPU2) + IDLE(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; + EDIS; + + while(DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT != 0x1); + + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + +// +// HIB - Enter HIB mode (dual CPU). Puts CPU2 in STANDBY first. Alternately, +// CPU2 may be in reset. +void HIB(void) +{ +#if defined(CPU2) + STANDBY(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HIB; + EDIS; + + while((DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT == 0x0) && + (DevCfgRegs.RSTSTAT.bit.CPU2RES == 1)); + + DisablePeripheralClocks(); + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + +#ifdef CPU1 +// +// Function to implement Analog trim of TMX devices. This function should be +// called post enabling the EALLOW protected writes. +// +void ConfigureTMXAnalogTrim(void) +{ + // + // Enable ADC clock + // + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + + // + // Device is not trimmed--apply static calibration values + // + AnalogSubsysRegs.ANAREFTRIMA.all = 0x7BDD; + AnalogSubsysRegs.ANAREFTRIMB.all = 0x7BDD; + AnalogSubsysRegs.ANAREFTRIMC.all = 0x7BDD; + AnalogSubsysRegs.ANAREFTRIMD.all = 0x7BDD; + + // + // Configure ADC offset trim. The user should generate the trim values + // by following the instructions in the "ADC Zero Offset Calibration" + // section in device TRM. The below lines needs to be uncommented and + // updated with the correct trim values. + // +// AdcaRegs.ADCOFFTRIM.all = 0x0; +// AdcbRegs.ADCOFFTRIM.all = 0x0; +// AdccRegs.ADCOFFTRIM.all = 0x0; +// AdcdRegs.ADCOFFTRIM.all = 0x0; + + // + // Configure internal oscillator trim. If the internal oscillator trim + // contains all zeros, the user can adjust the lowest 10 bits of the + // oscillator trim register between 1 (minimum) and 1023 (maximum) + // while observing the system clock on the XCLOCKOUT pin. The below + // lines needs to be uncommented and updated with the correct trim values. + // +// if(AnalogSubsysRegs.INTOSC1TRIM.all == 0x0) +// { +// AnalogSubsysRegs.INTOSC1TRIM.all = 0x0; +// } +// +// if(AnalogSubsysRegs.INTOSC2TRIM.all == 0x0) +// { +// AnalogSubsysRegs.INTOSC2TRIM.all = 0x0; +// } + + // + // Disable ADC clock + // + CpuSysRegs.PCLKCR13.bit.ADC_A = 0; + CpuSysRegs.PCLKCR13.bit.ADC_B = 0; + CpuSysRegs.PCLKCR13.bit.ADC_C = 0; + CpuSysRegs.PCLKCR13.bit.ADC_D = 0; +} +#endif diff --git a/gpio_bitfield_cpu1/F2837xD_usDelay.asm b/gpio_bitfield_cpu1/F2837xD_usDelay.asm new file mode 100644 index 0000000..4f705c9 --- /dev/null +++ b/gpio_bitfield_cpu1/F2837xD_usDelay.asm @@ -0,0 +1,109 @@ +;//########################################################################### +;// +;// FILE: F2837xD_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// To use this function: +;// 1 - update the CPU clock speed in the F2837xD_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the F2837xD_Device.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// extern void Delay(long LoopCount); +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// Or as follows (if count is less then 16-bits): +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;//########################################################################### +;// +;// $Release Date: $ +;// $Copyright: +;// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .if __TI_EABI__ + .asg F28x_usDelay, _F28x_usDelay + .endif + + .def _F28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __F28x_usDelay +_F28x_usDelay: + SUB ACC,#1 + BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +; + +;// +;// End of file +;// diff --git a/gpio_bitfield_cpu1/device/F2837xD_CodeStartBranch.asm b/gpio_bitfield_cpu1/device/F2837xD_CodeStartBranch.asm new file mode 100644 index 0000000..1fdab30 --- /dev/null +++ b/gpio_bitfield_cpu1/device/F2837xD_CodeStartBranch.asm @@ -0,0 +1,112 @@ +;//########################################################################### +;// +;// FILE: F2837xD_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example F2837xD projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// +;// $Release Date: $ +;// $Copyright: +;// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + .retain + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot._asm in RTS library + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/gpio_bitfield_cpu1/device/device.c b/gpio_bitfield_cpu1/device/device.c new file mode 100644 index 0000000..b64b33d --- /dev/null +++ b/gpio_bitfield_cpu1/device/device.c @@ -0,0 +1,706 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#include "inc/hw_ipc.h" + +#ifdef CMDTOOL +#include "device_cmd.h" +#endif + +#ifdef __cplusplus +using std::memcpy; +#endif + +#define PASS 0 +#define FAIL 1 + +uint32_t Example_Result = FAIL; +uint32_t Example_PassCount = 0; +uint32_t Example_Fail = 0; + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef CMDTOOL + CMD_init(); +#endif + +#ifdef _FLASH +#ifndef CMDTOOL + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); +#endif + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + + // + // Configure Analog Trim in case of untrimmed or TMX sample + // + if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) && + (HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U)) + { + Device_configureTMXAnalogTrim(); + } + + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the Device_init function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // Sysctl_deviceCal is a wrapper function for Device_Cal + // + SysCtl_deviceCal(); +#endif + +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); + + // + // Initialize result parameter as FAIL + // + Example_Result = FAIL; +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +#ifdef CPU1 +//***************************************************************************** +// +// Function to implement Analog trim of TMX devices +// +//***************************************************************************** +void Device_configureTMXAnalogTrim(void) +{ + // + // Enable ADC clock + // + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + // + // Configure ADC reference trim for TMX devices + // + EALLOW; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU; + + // + // Configure ADC offset trim. The user should generate the trim values + // by following the instructions in the "ADC Zero Offset Calibration" + // section in device TRM. The below lines needs to be uncommented and + // updated with the correct trim values. + // +// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U; + + // + // Configure internal oscillator trim. If the internal oscillator trim + // contains all zeros, the user can adjust the lowest 10 bits of the + // oscillator trim register between 1 (minimum) and 1023 (maximum) + // while observing the system clock on the XCLOCKOUT pin. The below + // lines needs to be uncommented and updated with the correct trim values. + // +// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U; +// } +// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U; +// } + + EDIS; + + // + // Disable ADC clock + // + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD); +} + +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +Device_bootCPU2(uint32_t bootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) & + 0x80000000U)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & + C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) || + ((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U)) + { + + } + + if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (bootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + // + //SCIA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_29_SCITXDA); + GPIO_setMasterCore(29, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_28_SCIRXDA); + GPIO_setMasterCore(28, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + + // + //SPI-A connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + EDIS; + + GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_16_SPISIMOA); + GPIO_setMasterCore(16, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_17_SPISOMIA); + GPIO_setMasterCore(17, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_18_SPICLKA); + GPIO_setMasterCore(18, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_19_GPIO19); + GPIO_setMasterCore(19, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + + // + //I2CA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_32_SDAA); + GPIO_setMasterCore(32, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_33_SCLA); + GPIO_setMasterCore(33, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC); + GPIO_setMasterCore(pin, GPIO_CORE_CPU2); + } + + GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_69_GPIO69); + GPIO_setMasterCore(69, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_70_GPIO70); + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + GPIO_setMasterCore(71, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_71_CANTXA); + GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC); + + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_70_CANRXA); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + + + GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + // + // Set CANA Bit-Clock Source Select = SYSCLK and enable CAN + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + SYSCTL_CLKSRCCTL2_CANABCLKSEL_M; + EDIS; + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U; + + } + return returnStatus; +} +#endif // #ifdef CPU1 +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(const char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} + +void Example_setResultPass(void) +{ + Example_Result = PASS; +} + +void Example_setResultFail(void) +{ + Example_Result = FAIL; +} + +void Example_done(void) +{ + while(1); +} diff --git a/gpio_bitfield_cpu1/device/device.h b/gpio_bitfield_cpu1/device/device.h new file mode 100644 index 0000000..ec143e5 --- /dev/null +++ b/gpio_bitfield_cpu1/device/device.h @@ -0,0 +1,394 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9 +#else +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 +#endif + + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX +#else +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX +#endif + +// +// GPIO assignment for CAN-A and CAN-B +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX +#else +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//I2CA GPIO pins +#define DEVICE_GPIO_PIN_SDAA 104 +#define DEVICE_GPIO_PIN_SCLA 105 + +#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA +#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA + + +//I2CB GPIO pins +#define DEVICE_GPIO_PIN_SDAB 40 +#define DEVICE_GPIO_PIN_SCLB 41 + +#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB +#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB + +#endif + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +// +// The macros that can be used as parameter to the function Device_bootCPU2 +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU + +// +// Other macros that are needed for the Device_bootCPU2 function +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U + +// +// Macros used as return value by the Device_bootCPU2 function +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +extern uint32_t Example_PassCount; +extern uint32_t Example_Fail; + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup device_api +//! @{ +// +//***************************************************************************** +//***************************************************************************** +// +//! @brief Function to initialize the device. Primarily initializes system control to a +//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +//! and enabling the clocks to the peripherals. +//! +//! \param None. +//! \return None. +// +//***************************************************************************** +extern void Device_init(void); +//***************************************************************************** +//! +//! +//! @brief Function to turn on all peripherals, enabling reads and writes to the +//! peripherals' registers. +//! +//! Note that to reduce power, unused peripherals should be disabled. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableAllPeripherals(void); +//***************************************************************************** +//! +//! +//! @brief Function to disable pin locks on GPIOs. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_initGPIO(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package: +//! GPIOs Grp Bits +//! 95-132 C 31 +//! D 31:0 +//! E 4:0 +//! 134-168 E 31:6 +//! F 8:0 +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package: +//! GPIOs Grp Bits +//! 0-1 A 1:0 +//! 5-9 A 9:5 +//! 22-40 A 31:22 +//! B 8:0 +//! 44-57 B 25:12 +//! 67-68 C 4:3 +//! 74-77 C 13:10 +//! 79-83 C 19:15 +//! 93-168 C 31:29 +//! D 31:0 +//! E 31:0 +//! F 8:0 +//! @param None +//! @return None +// +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the +//! 176PTP package. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullups(void); +#ifdef CPU1 +//***************************************************************************** +//! +//! @brief Function to implement Analog trim of TMX devices +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_configureTMXAnalogTrim(void); +//***************************************************************************** +//! @brief Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +extern uint16_t Device_bootCPU2(uint32_t ulBootMode); +#endif +//***************************************************************************** +//! +//! @brief Error handling function to be called when an ASSERT is violated +//! +//! @param *filename File name in which the error has occurred +//! @param line Line number within the file +//! @return None +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); +extern void Example_setResultPass(void); +extern void Example_setResultFail(void); +extern void Example_done(void); + +// +// End of file +// diff --git a/gpio_bitfield_cpu1/device/driverlib.h b/gpio_bitfield_cpu1/device/driverlib.h new file mode 100644 index 0000000..932ace6 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib.h @@ -0,0 +1,87 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "clb.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "ipc.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "pin_map_legacy.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#include "driver_inclusive_terminology_mapping.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/gpio_bitfield_cpu1/device/driverlib/adc.c b/gpio_bitfield_cpu1/device/driverlib/adc.c new file mode 100644 index 0000000..9e74809 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/adc.c @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: adc.c +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "adc.h" + +//***************************************************************************** +// +// Defines for locations of ADC calibration functions in OTP for use in +// ADC_setMode() ONLY. Not intended for use by application code. +// +//***************************************************************************** +// +// The following functions calibrate the ADC linearity. Use them in the +// ADC_setMode() function only. +// +#define ADC_calADCAINL 0x0703B4U +#define ADC_calADCBINL 0x0703B2U +#define ADC_calADCCINL 0x0703B0U +#define ADC_calADCDINL 0x0703AEU + +// +// This function looks up the ADC offset trim for a given condition. Use this +// in the ADC_setMode() function only. +// +#define ADC_getOffsetTrim 0x0703ACU + +//***************************************************************************** +// +// ADC_setMode +// +//***************************************************************************** +void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Check for correct signal mode & resolution. In this device: + // Single ended signal conversions are supported in 12-bit mode only + // Differential signal conversions are supported in 16-bit mode only + // + if(signalMode == ADC_MODE_SINGLE_ENDED) + { + ASSERT(resolution == ADC_RESOLUTION_12BIT); + } + else + { + ASSERT(resolution == ADC_RESOLUTION_16BIT); + } + + + // + // Apply the resolution and signalMode to the specified ADC. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE)) | + ((uint16_t)resolution | (uint16_t)signalMode); + EDIS; + + // + // Apply INL and offset trims + // + ADC_setINLTrim(base); + ADC_setOffsetTrim(base); +} + +//***************************************************************************** +// +// ADC_setINLTrim +// +//***************************************************************************** +void +ADC_setINLTrim(uint32_t base) +{ + ADC_Resolution resolution; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + + EALLOW; + switch(base) + { + case ADCA_BASE: + if(HWREGH(ADC_calADCAINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCAINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCB_BASE: + if(HWREGH(ADC_calADCBINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCBINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCC_BASE: + if(HWREGH(ADC_calADCCINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCCINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCD_BASE: + if(HWREGH(ADC_calADCDINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCDINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + default: + // + // Invalid base address! Do nothing! + // + break; + } + + // + // Apply linearity trim workaround for 12-bit resolution + // + if(resolution == ADC_RESOLUTION_12BIT) + { + // + // 12-bit linearity trim workaround + // + HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U; + } + EDIS; +} + +//***************************************************************************** +// +// ADC_setOffsetTrim +// +//***************************************************************************** +void +ADC_setOffsetTrim(uint32_t base) +{ + uint16_t offsetIndex = 0U; + uint16_t offsetTrim = 0U; + ADC_Resolution resolution; + ADC_SignalMode signalMode; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + signalMode = (ADC_SignalMode) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE); + + switch(base) + { + case ADCA_BASE: + offsetIndex = (uint16_t)(0U * 4U); + break; + case ADCB_BASE: + offsetIndex = (uint16_t)(1U * 4U); + break; + case ADCC_BASE: + offsetIndex = (uint16_t)(2U * 4U); + break; + case ADCD_BASE: + offsetIndex = (uint16_t)(3U * 4U); + break; + default: + // + // Invalid base address! + // + offsetIndex = 0U; + break; + } + + // + // Offset trim function is programmed into OTP, so call it + // + if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU) + { + // + // Calculate the index into OTP table of offset trims and call + // function to return the correct offset trim + // + offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) + + (2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U)); + + offsetTrim = + (*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex); + } + else + { + // + // Offset trim function is not populated, so set offset trim to 0 + // + offsetTrim = 0U; + } + + // + // Apply the offset trim. Offset Trim is not updated here in case of TMX or + // untrimmed devices. The default trims for TMX devices should be handled in + // Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim() + // APIs for more details. + // + if(offsetTrim > 0x0U) + { + EALLOW; + HWREGH(base + ADC_O_OFFTRIM) = offsetTrim; + EDIS; + } +} + + +//***************************************************************************** +// +// ADC_setPPBTripLimits +// +//***************************************************************************** +void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit) +{ + uint32_t ppbHiOffset; + uint32_t ppbLoOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((tripHiLimit <= 65535) && (tripHiLimit >= -65536)); + ASSERT((tripLoLimit <= 65535) && (tripLoLimit >= -65536)); + + // + // Get the offset to the appropriate trip limit registers. + // + ppbHiOffset = (ADC_PPBxTRIPHI_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPHI; + ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPLO; + + EALLOW; + + // + // Set the trip high limit. + // + HWREG(base + ppbHiOffset) = + (HWREG(base + ppbHiOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripHiLimit & ADC_PPBTRIP_MASK); + + // + // Set the trip low limit. + // + HWREG(base + ppbLoOffset) = + (HWREG(base + ppbLoOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripLoLimit & ADC_PPBTRIP_MASK); + + EDIS; +} diff --git a/gpio_bitfield_cpu1/device/driverlib/adc.h b/gpio_bitfield_cpu1/device/driverlib/adc.h new file mode 100644 index 0000000..136638d --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/adc.h @@ -0,0 +1,2098 @@ +//########################################################################### +// +// FILE: adc.h +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ADC_H +#define ADC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup adc_api ADC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_adc.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define ADC_NUM_INTERRUPTS 4U + +#define ADC_SOCxCTL_OFFSET_BASE ADC_O_SOC0CTL +#define ADC_RESULTx_OFFSET_BASE ADC_O_RESULT0 +#define ADC_INTSELxNy_OFFSET_BASE ADC_O_INTSEL1N2 +#define ADC_PPBxRESULT_OFFSET_BASE ADC_O_PPB1RESULT + + +#define ADC_PPBxCONFIG_STEP (ADC_O_PPB2CONFIG - ADC_O_PPB1CONFIG) +#define ADC_PPBxTRIPHI_STEP (ADC_O_PPB2TRIPHI - ADC_O_PPB1TRIPHI) +#define ADC_PPBxTRIPLO_STEP (ADC_O_PPB2TRIPLO - ADC_O_PPB1TRIPLO) +#define ADC_PPBxOFFCAL_STEP (ADC_O_PPB2OFFCAL - ADC_O_PPB1OFFCAL) +#define ADC_PPBxOFFREF_STEP (ADC_O_PPB2OFFREF - ADC_O_PPB1OFFREF) +#define ADC_PPBxSTAMP_STEP (ADC_O_PPB2STAMP - ADC_O_PPB1STAMP) + +#define ADC_PPBTRIP_MASK ((uint32_t)ADC_PPB1TRIPHI_LIMITHI_M |\ + (uint32_t)ADC_PPB1TRIPHI_HSIGN) +// +// Slope of the temperature sensor based in degrees C in fixed point Q15 format +// +#define ADC_getTempSlope() (*(int16_t (*)(void))0x7036E)() + +// +// Offset of the temp sensor output at 0 degrees C +// +#define ADC_getTempOffset() (*(int16_t (*)(void))0x70372)() + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(), +// ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and +// ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also +// make up the enumerated bit field returned by ADC_getPPBEventStatus(). +// +//***************************************************************************** +#define ADC_EVT_TRIPHI 0x0001U //!< Trip High Event +#define ADC_EVT_TRIPLO 0x0002U //!< Trip Low Event +#define ADC_EVT_ZERO 0x0004U //!< Zero Crossing Event +#endif + +//***************************************************************************** +// +// Values that can be passed to ADC_forceMultipleSOC() as socMask parameter. +// These values can be OR'd together to trigger multiple SOCs at a time. +// +//***************************************************************************** +#define ADC_FORCE_SOC0 0x0001U //!< SW trigger ADC SOC 0 +#define ADC_FORCE_SOC1 0x0002U //!< SW trigger ADC SOC 1 +#define ADC_FORCE_SOC2 0x0004U //!< SW trigger ADC SOC 2 +#define ADC_FORCE_SOC3 0x0008U //!< SW trigger ADC SOC 3 +#define ADC_FORCE_SOC4 0x0010U //!< SW trigger ADC SOC 4 +#define ADC_FORCE_SOC5 0x0020U //!< SW trigger ADC SOC 5 +#define ADC_FORCE_SOC6 0x0040U //!< SW trigger ADC SOC 6 +#define ADC_FORCE_SOC7 0x0080U //!< SW trigger ADC SOC 7 +#define ADC_FORCE_SOC8 0x0100U //!< SW trigger ADC SOC 8 +#define ADC_FORCE_SOC9 0x0200U //!< SW trigger ADC SOC 9 +#define ADC_FORCE_SOC10 0x0400U //!< SW trigger ADC SOC 10 +#define ADC_FORCE_SOC11 0x0800U //!< SW trigger ADC SOC 11 +#define ADC_FORCE_SOC12 0x1000U //!< SW trigger ADC SOC 12 +#define ADC_FORCE_SOC13 0x2000U //!< SW trigger ADC SOC 13 +#define ADC_FORCE_SOC14 0x4000U //!< SW trigger ADC SOC 14 +#define ADC_FORCE_SOC15 0x8000U //!< SW trigger ADC SOC 15 + + + +//***************************************************************************** +// +//! Values that can be passed to ADC_setPrescaler() as the \e clkPrescale +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_CLK_DIV_1_0 = 0U, //!< ADCCLK = (input clock) / 1.0 + ADC_CLK_DIV_2_0 = 2U, //!< ADCCLK = (input clock) / 2.0 + ADC_CLK_DIV_2_5 = 3U, //!< ADCCLK = (input clock) / 2.5 + ADC_CLK_DIV_3_0 = 4U, //!< ADCCLK = (input clock) / 3.0 + ADC_CLK_DIV_3_5 = 5U, //!< ADCCLK = (input clock) / 3.5 + ADC_CLK_DIV_4_0 = 6U, //!< ADCCLK = (input clock) / 4.0 + ADC_CLK_DIV_4_5 = 7U, //!< ADCCLK = (input clock) / 4.5 + ADC_CLK_DIV_5_0 = 8U, //!< ADCCLK = (input clock) / 5.0 + ADC_CLK_DIV_5_5 = 9U, //!< ADCCLK = (input clock) / 5.5 + ADC_CLK_DIV_6_0 = 10U, //!< ADCCLK = (input clock) / 6.0 + ADC_CLK_DIV_6_5 = 11U, //!< ADCCLK = (input clock) / 6.5 + ADC_CLK_DIV_7_0 = 12U, //!< ADCCLK = (input clock) / 7.0 + ADC_CLK_DIV_7_5 = 13U, //!< ADCCLK = (input clock) / 7.5 + ADC_CLK_DIV_8_0 = 14U, //!< ADCCLK = (input clock) / 8.0 + ADC_CLK_DIV_8_5 = 15U //!< ADCCLK = (input clock) / 8.5 +} ADC_ClkPrescale; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e resolution +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_RESOLUTION_12BIT = 0x00U, //!< 12-bit conversion resolution + ADC_RESOLUTION_16BIT = 0x40U //!< 16-bit conversion resolution +} ADC_Resolution; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e signalMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_MODE_SINGLE_ENDED = 0x00U, //!< Sample on single pin with VREFLO + ADC_MODE_DIFFERENTIAL = 0x80U //!< Sample on pair of pins +} ADC_SignalMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e trigger +//! parameter to specify the event that will trigger a conversion to start. +//! It is also used with ADC_setBurstModeConfig() and +//! ADC_triggerRepeaterSelect(). +// +//***************************************************************************** +typedef enum +{ + ADC_TRIGGER_SW_ONLY = 0U, //!< Software only + ADC_TRIGGER_CPU1_TINT0 = 1U, //!< CPU1 Timer 0, TINT0 + ADC_TRIGGER_CPU1_TINT1 = 2U, //!< CPU1 Timer 1, TINT1 + ADC_TRIGGER_CPU1_TINT2 = 3U, //!< CPU1 Timer 2, TINT2 + ADC_TRIGGER_GPIO = 4U, //!< GPIO, ADCEXTSOC + ADC_TRIGGER_EPWM1_SOCA = 5U, //!< ePWM1, ADCSOCA + ADC_TRIGGER_EPWM1_SOCB = 6U, //!< ePWM1, ADCSOCB + ADC_TRIGGER_EPWM2_SOCA = 7U, //!< ePWM2, ADCSOCA + ADC_TRIGGER_EPWM2_SOCB = 8U, //!< ePWM2, ADCSOCB + ADC_TRIGGER_EPWM3_SOCA = 9U, //!< ePWM3, ADCSOCA + ADC_TRIGGER_EPWM3_SOCB = 10U, //!< ePWM3, ADCSOCB + ADC_TRIGGER_EPWM4_SOCA = 11U, //!< ePWM4, ADCSOCA + ADC_TRIGGER_EPWM4_SOCB = 12U, //!< ePWM4, ADCSOCB + ADC_TRIGGER_EPWM5_SOCA = 13U, //!< ePWM5, ADCSOCA + ADC_TRIGGER_EPWM5_SOCB = 14U, //!< ePWM5, ADCSOCB + ADC_TRIGGER_EPWM6_SOCA = 15U, //!< ePWM6, ADCSOCA + ADC_TRIGGER_EPWM6_SOCB = 16U, //!< ePWM6, ADCSOCB + ADC_TRIGGER_EPWM7_SOCA = 17U, //!< ePWM7, ADCSOCA + ADC_TRIGGER_EPWM7_SOCB = 18U, //!< ePWM7, ADCSOCB + ADC_TRIGGER_EPWM8_SOCA = 19U, //!< ePWM8, ADCSOCA + ADC_TRIGGER_EPWM8_SOCB = 20U, //!< ePWM8, ADCSOCB + ADC_TRIGGER_EPWM9_SOCA = 21U, //!< ePWM9, ADCSOCA + ADC_TRIGGER_EPWM9_SOCB = 22U, //!< ePWM9, ADCSOCB + ADC_TRIGGER_EPWM10_SOCA = 23U, //!< ePWM10, ADCSOCA + ADC_TRIGGER_EPWM10_SOCB = 24U, //!< ePWM10, ADCSOCB + ADC_TRIGGER_EPWM11_SOCA = 25U, //!< ePWM11, ADCSOCA + ADC_TRIGGER_EPWM11_SOCB = 26U, //!< ePWM11, ADCSOCB + ADC_TRIGGER_EPWM12_SOCA = 27U, //!< ePWM12, ADCSOCA + ADC_TRIGGER_EPWM12_SOCB = 28U, //!< ePWM12, ADCSOCB + ADC_TRIGGER_CPU2_TINT0 = 29U, //!< CPU2 Timer 0, TINT0 + ADC_TRIGGER_CPU2_TINT1 = 30U, //!< CPU2 Timer 1, TINT1 + ADC_TRIGGER_CPU2_TINT2 = 31U //!< CPU2 Timer 2, TINT2 +} ADC_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e channel +//! parameter. This is the input pin on which the signal to be converted is +//! located. +// +//***************************************************************************** +typedef enum +{ + ADC_CH_ADCIN0 = 0U, //!< single-ended, ADCIN0 + ADC_CH_ADCIN1 = 1U, //!< single-ended, ADCIN1 + ADC_CH_ADCIN2 = 2U, //!< single-ended, ADCIN2 + ADC_CH_ADCIN3 = 3U, //!< single-ended, ADCIN3 + ADC_CH_ADCIN4 = 4U, //!< single-ended, ADCIN4 + ADC_CH_ADCIN5 = 5U, //!< single-ended, ADCIN5 + ADC_CH_ADCIN6 = 6U, //!< single-ended, ADCIN6 + ADC_CH_ADCIN7 = 7U, //!< single-ended, ADCIN7 + ADC_CH_ADCIN8 = 8U, //!< single-ended, ADCIN8 + ADC_CH_ADCIN9 = 9U, //!< single-ended, ADCIN9 + ADC_CH_ADCIN10 = 10U, //!< single-ended, ADCIN10 + ADC_CH_ADCIN11 = 11U, //!< single-ended, ADCIN11 + ADC_CH_ADCIN12 = 12U, //!< single-ended, ADCIN12 + ADC_CH_ADCIN13 = 13U, //!< single-ended, ADCIN13 + ADC_CH_ADCIN14 = 14U, //!< single-ended, ADCIN14 + ADC_CH_ADCIN15 = 15U, //!< single-ended, ADCIN15 + ADC_CH_ADCIN0_ADCIN1 = 0U, //!< differential, ADCIN0 and ADCIN1 + ADC_CH_ADCIN2_ADCIN3 = 2U, //!< differential, ADCIN2 and ADCIN3 + ADC_CH_ADCIN4_ADCIN5 = 4U, //!< differential, ADCIN4 and ADCIN5 + ADC_CH_ADCIN6_ADCIN7 = 6U, //!< differential, ADCIN6 and ADCIN7 + ADC_CH_ADCIN8_ADCIN9 = 8U, //!< differential, ADCIN8 and ADCIN9 + ADC_CH_ADCIN10_ADCIN11 = 10U, //!< differential, ADCIN10 and ADCIN11 + ADC_CH_ADCIN12_ADCIN13 = 12U, //!< differential, ADCIN12 and ADCIN13 + ADC_CH_ADCIN14_ADCIN15 = 14U //!< differential, ADCIN14 and ADCIN15 +} ADC_Channel; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setInterruptPulseMode() as the +//! \e pulseMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Occurs at the end of the acquisition window + ADC_PULSE_END_OF_ACQ_WIN = 0x00U, + //! Occurs at the end of the conversion + ADC_PULSE_END_OF_CONV = 0x04U +} ADC_PulseMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_enableInterrupt(), ADC_disableInterrupt(), +//! and ADC_getInterruptStatus() as the \e adcIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_NUMBER1 = 0U, //!< ADCINT1 Interrupt + ADC_INT_NUMBER2 = 1U, //!< ADCINT2 Interrupt + ADC_INT_NUMBER3 = 2U, //!< ADCINT3 Interrupt + ADC_INT_NUMBER4 = 3U //!< ADCINT4 Interrupt +} ADC_IntNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e ppbNumber parameter for several +//! functions. +// +//***************************************************************************** +typedef enum +{ + ADC_PPB_NUMBER1 = 0U, //!< Post-processing block 1 + ADC_PPB_NUMBER2 = 1U, //!< Post-processing block 2 + ADC_PPB_NUMBER3 = 2U, //!< Post-processing block 3 + ADC_PPB_NUMBER4 = 3U //!< Post-processing block 4 +} ADC_PPBNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e socNumber parameter for several +//! functions. This value identifies the start-of-conversion (SOC) that a +//! function is configuring or accessing. Note that in some cases (for example, +//! ADC_setInterruptSource()) \e socNumber is used to refer to the +//! corresponding end-of-conversion (EOC). +// +//***************************************************************************** +typedef enum +{ + ADC_SOC_NUMBER0 = 0U, //!< SOC/EOC number 0 + ADC_SOC_NUMBER1 = 1U, //!< SOC/EOC number 1 + ADC_SOC_NUMBER2 = 2U, //!< SOC/EOC number 2 + ADC_SOC_NUMBER3 = 3U, //!< SOC/EOC number 3 + ADC_SOC_NUMBER4 = 4U, //!< SOC/EOC number 4 + ADC_SOC_NUMBER5 = 5U, //!< SOC/EOC number 5 + ADC_SOC_NUMBER6 = 6U, //!< SOC/EOC number 6 + ADC_SOC_NUMBER7 = 7U, //!< SOC/EOC number 7 + ADC_SOC_NUMBER8 = 8U, //!< SOC/EOC number 8 + ADC_SOC_NUMBER9 = 9U, //!< SOC/EOC number 9 + ADC_SOC_NUMBER10 = 10U, //!< SOC/EOC number 10 + ADC_SOC_NUMBER11 = 11U, //!< SOC/EOC number 11 + ADC_SOC_NUMBER12 = 12U, //!< SOC/EOC number 12 + ADC_SOC_NUMBER13 = 13U, //!< SOC/EOC number 13 + ADC_SOC_NUMBER14 = 14U, //!< SOC/EOC number 14 + ADC_SOC_NUMBER15 = 15U //!< SOC/EOC number 15 +} ADC_SOCNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e trigger parameter for the +//! ADC_setInterruptSOCTrigger() function. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_SOC_TRIGGER_NONE = 0U, //!< No ADCINT will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT1 = 1U, //!< ADCINT1 will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT2 = 2U //!< ADCINT2 will trigger the SOC +} ADC_IntSOCTrigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setSOCPriority() as the \e priMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_PRI_ALL_ROUND_ROBIN = 0U, //!< Round robin mode is used for all + ADC_PRI_SOC0_HIPRI = 1U, //!< SOC 0 hi pri, others in round robin + ADC_PRI_THRU_SOC1_HIPRI = 2U, //!< SOC 0-1 hi pri, others in round robin + ADC_PRI_THRU_SOC2_HIPRI = 3U, //!< SOC 0-2 hi pri, others in round robin + ADC_PRI_THRU_SOC3_HIPRI = 4U, //!< SOC 0-3 hi pri, others in round robin + ADC_PRI_THRU_SOC4_HIPRI = 5U, //!< SOC 0-4 hi pri, others in round robin + ADC_PRI_THRU_SOC5_HIPRI = 6U, //!< SOC 0-5 hi pri, others in round robin + ADC_PRI_THRU_SOC6_HIPRI = 7U, //!< SOC 0-6 hi pri, others in round robin + ADC_PRI_THRU_SOC7_HIPRI = 8U, //!< SOC 0-7 hi pri, others in round robin + ADC_PRI_THRU_SOC8_HIPRI = 9U, //!< SOC 0-8 hi pri, others in round robin + ADC_PRI_THRU_SOC9_HIPRI = 10U, //!< SOC 0-9 hi pri, others in round robin + ADC_PRI_THRU_SOC10_HIPRI = 11U, //!< SOC 0-10 hi pri, others in round robin + ADC_PRI_THRU_SOC11_HIPRI = 12U, //!< SOC 0-11 hi pri, others in round robin + ADC_PRI_THRU_SOC12_HIPRI = 13U, //!< SOC 0-12 hi pri, others in round robin + ADC_PRI_THRU_SOC13_HIPRI = 14U, //!< SOC 0-13 hi pri, others in round robin + ADC_PRI_THRU_SOC14_HIPRI = 15U, //!< SOC 0-14 hi pri, SOC15 in round robin + ADC_PRI_ALL_HIPRI = 16U //!< All priorities based on SOC number +} ADC_PriorityMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_configOSDetectMode() as the \e modeVal +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_OSDETECT_MODE_DISABLED = 0x0U,//!< Open/Shorts detection cir- + //!< cuit(O/S DC) is disabled + ADC_OSDETECT_MODE_VSSA = 0x1U,//!< O/S DC is enabled at zero + //!< scale + ADC_OSDETECT_MODE_VDDA = 0x2U,//!< O/S DC is enabled at full + //!< scale + ADC_OSDETECT_MODE_5BY12_VDDA = 0x3U,//!< O/S DC is enabled at 5/12 + //!< scale + ADC_OSDETECT_MODE_7BY12_VDDA = 0x4U,//!< O/S DC is enabled at 7/12 + //!< scale + ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA = 0x5U,//!< O/S DC is enabled at 5K + //!< pulldown to VSSA + ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA = 0x6U,//!< O/S DC is enabled at 5K + //!< pullup to VDDA + ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA = 0x7U //!< O/S DC is enabled at 7K + //!< pulldown to VSSA +} ADC_OSDetectMode; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an ADC base address. +//! +//! \param base specifies the ADC module base address. +//! +//! This function determines if a ADC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +ADC_isBaseValid(uint32_t base) +{ + return( + (base == ADCA_BASE) || + (base == ADCB_BASE) || + (base == ADCC_BASE) || + (base == ADCD_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Configures the analog-to-digital converter module prescaler. +//! +//! \param base is the base address of the ADC module. +//! \param clkPrescale is the ADC clock prescaler. +//! +//! This function configures the ADC module's ADCCLK. +//! +//! The \e clkPrescale parameter specifies the value by which the input clock +//! is divided to make the ADCCLK. The clkPrescale value can be specified with +//! any of the following enum values: +//! \b ADC_CLK_DIV_1_0, \b ADC_CLK_DIV_2_0, \b ADC_CLK_DIV_2_5, ..., +//! \b ADC_CLK_DIV_7_5, \b ADC_CLK_DIV_8_0, or \b ADC_CLK_DIV_8_5. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the configuration of the ADC module prescaler. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~ADC_CTL2_PRESCALE_M) | (uint16_t)clkPrescale; + EDIS; +} + +//***************************************************************************** +// +//! Configures a start-of-conversion (SOC) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the source that will cause the SOC. +//! \param channel is the number associated with the input signal. +//! \param sampleWindow is the acquisition window duration. +//! +//! This function configures the a start-of-conversion (SOC) in the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the event that causes the SOC such as software, a +//! timer interrupt, an ePWM event, or an ADC interrupt. It should be a value +//! in the format of \b ADC_TRIGGER_XXXX where XXXX is the event such as +//! \b ADC_TRIGGER_SW_ONLY, \b ADC_TRIGGER_CPU1_TINT0, \b ADC_TRIGGER_GPIO, +//! \b ADC_TRIGGER_EPWM1_SOCA, and so on. +//! +//! The \e channel parameter specifies the channel to be converted. In +//! single-ended mode this is a single pin given by \b ADC_CH_ADCINx where x is +//! the number identifying the pin between 0 and 15 inclusive. In differential +//! mode, two pins are used as inputs and are passed in the \e channel +//! parameter as \b ADC_CH_ADCIN0_ADCIN1, \b ADC_CH_ADCIN2_ADCIN3, ..., or +//! \b ADC_CH_ADCIN14_ADCIN15. +//! +//! The \e sampleWindow parameter is the acquisition window duration in SYSCLK +//! cycles. It should be a value between 1 and 512 cycles inclusive. The +//! selected duration must be at least as long as one ADCCLK cycle. Also, the +//! datasheet will specify a minimum window duration requirement in +//! nanoseconds. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, + ADC_Channel channel, uint32_t sampleWindow) +{ + uint32_t ctlRegAddr, mask; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((sampleWindow >= 1U) && (sampleWindow <= 512U)); + + mask = (ADC_SOC0CTL_CHSEL_M | ADC_SOC0CTL_TRIGSEL_M | ADC_SOC0CTL_ACQPS_M); + + // + // Calculate address for the SOC control register. + // + ctlRegAddr = base + ADC_SOCxCTL_OFFSET_BASE + ((uint32_t)socNumber * 2U); + + // + // Set the configuration of the specified SOC. + // + EALLOW; + + HWREG(ctlRegAddr) = (HWREG(ctlRegAddr) & ~(mask)) | + ((uint32_t)channel << ADC_SOC0CTL_CHSEL_S) | + ((uint32_t)trigger << ADC_SOC0CTL_TRIGSEL_S) | + (sampleWindow - 1U); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the interrupt SOC trigger of an SOC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the interrupt source that will cause the SOC. +//! +//! This function configures the interrupt start-of-conversion trigger in +//! the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the interrupt that causes a start of conversion or +//! none. It should be one of the following values. +//! +//! - \b ADC_INT_SOC_TRIGGER_NONE +//! - \b ADC_INT_SOC_TRIGGER_ADCINT1 +//! - \b ADC_INT_SOC_TRIGGER_ADCINT2 +//! +//! This functionality is useful for creating continuous conversions. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, + ADC_IntSOCTrigger trigger) +{ + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each SOC has a 2-bit field in this register. + // + shiftVal = (uint16_t)socNumber << 1U; + + // + // Set the configuration of the specified SOC. Not that we're treating + // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here. + // + EALLOW; + HWREG(base + ADC_O_INTSOCSEL1) = (HWREG(base + ADC_O_INTSOCSEL1) & + ~((uint32_t)ADC_INTSOCSEL1_SOC0_M << + shiftVal)) | + ((uint32_t)trigger << shiftVal); + EDIS; +} + +//***************************************************************************** +// +//! Sets the timing of the end-of-conversion pulse +//! +//! \param base is the base address of the ADC module. +//! \param pulseMode is the generation mode of the EOC pulse. +//! +//! This function configures the end-of-conversion (EOC) pulse generated by ADC. +//! This pulse will be generated either at the end of the acquisition window +//!(pass \b ADC_PULSE_END_OF_ACQ_WIN into \e pulseMode) or at the end of the +//! voltage conversion, one cycle prior to the ADC result latching into it's +//! result register (pass \b ADC_PULSE_END_OF_CONV into \e pulseMode). +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the position of the pulse. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) = (HWREGH(base + ADC_O_CTL1) & + ~ADC_CTL1_INTPULSEPOS) | (uint16_t)pulseMode; + EDIS; +} + + + + +//***************************************************************************** +// +//! Powers up the analog-to-digital converter core. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers up the analog circuitry inside the analog core. +//! +//! \note Allow at least a 500us delay before sampling after calling this API. +//! If you enable multiple ADCs, you can delay after they all have begun +//! powering up. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the bit that powers up the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) |= ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Powers down the analog-to-digital converter module. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers down the analog circuitry inside the analog core. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the bit that powers down the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) &= ~ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Forces a SOC flag to a 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function forces the SOC flag associated with the SOC specified by +//! \e socNumber. This initiates a conversion once that SOC is given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to the corresponding SOC flag + // + HWREGH(base + ADC_O_SOCFRC1) = ((uint16_t)1U << (uint16_t)socNumber); +} + +//***************************************************************************** +// +//! Forces multiple SOC flags to 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socMask is the SOCs to be forced through software +//! +//! This function forces the SOCFRC1 flags associated with the SOCs specified +//! by \e socMask. This initiates a conversion once the desired SOCs are given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! Valid values for \e socMask parameter can be any of the individual +//! ADC_FORCE_SOCx values or any of their OR'd combination to trigger multiple +//! SOCs. +//! +//! \note To trigger SOC0, SOC1 and SOC2, value (ADC_FORCE_SOC0 | +//! ADC_FORCE_SOC1 | ADC_FORCE_SOC2) should be passed as socMask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceMultipleSOC(uint32_t base, uint16_t socMask) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to desired SOCs + // + HWREGH(base + ADC_O_SOCFRC1) = socMask; +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt status for the analog-to-digital +//! converter. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt status for the given interrupt number of the ADC module. +//! +//! \return \b true if the interrupt flag for the specified interrupt number is +//! set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTFLG) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt sources so that they no +//! longer assert. If not in continuous mode, this function must be called +//! before any further interrupt pulses may occur. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt. + // + HWREGH(base + ADC_O_INTFLGCLR) = (uint16_t)1U << (uint16_t)adcIntNum; + +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt overflow status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt overflow status for the +//! analog-to-digital converter. An overflow condition is generated +//! irrespective of the continuous mode. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt overflow status for the given interrupt number. +//! +//! \return \b true if the interrupt overflow flag for the specified interrupt +//! number is set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTOVF) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt overflow sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt overflow sources so that +//! they no longer assert. If software tries to clear the overflow in the same +//! cycle that hardware tries to set the overflow, then hardware has priority. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupt overflow status of the ADC module +//! should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt overflow bit. + // + HWREGH(base + ADC_O_INTOVFCLR) = (uint16_t)1U << (uint16_t)adcIntNum; +} + +//***************************************************************************** +// +//! Reads the conversion result. +//! +//! \param resultBase is the base address of the ADC results. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function returns the conversion result that corresponds to the base +//! address passed into \e resultBase and the SOC passed into \e socNumber. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC's result is to be read. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the conversion result. +// +//***************************************************************************** +static inline uint16_t +ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the ADC result for the selected SOC. + // + return(HWREGH(resultBase + (uint32_t)ADC_RESULTx_OFFSET_BASE + + (uint32_t)socNumber)); +} + +//***************************************************************************** +// +//! Determines whether the ADC is busy or not. +//! +//! \param base is the base address of the ADC. +//! +//! This function allows the caller to determine whether or not the ADC is +//! busy and can sample another channel. +//! +//! \return Returns \b true if the ADC is sampling or \b false if all +//! samples are complete. +// +//***************************************************************************** +static inline bool +ADC_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Determine if the ADC is busy. + // + return((HWREGH(base + ADC_O_CTL1) & ADC_CTL1_ADCBSY) != 0U); +} + +//***************************************************************************** +// +//! Set SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! \param trigger the source that will cause the burst conversion sequence. +//! \param burstSize is the number of SOCs converted during a burst sequence. +//! +//! This function configures the burst trigger and burstSize of an ADC module. +//! Burst mode allows a single trigger to walk through the round-robin SOCs one +//! or more at a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Instead, the source specified through the \e trigger parameter will +//! cause a burst of \e burstSize conversions to occur. +//! +//! The \e trigger parameter takes the same values as the ADC_setupSOC() API +//! The \e burstSize parameter should be a value between 1 and 16 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(((uint16_t)trigger & ~((uint16_t)0x1FU)) == 0U); + ASSERT((burstSize >= 1U) && (burstSize <= 16U)); + + // + // Write the burst mode configuration to the register. + // + EALLOW; + + regValue = (uint16_t)trigger | ((burstSize - 1U) << + ADC_BURSTCTL_BURSTSIZE_S); + + HWREGH(base + ADC_O_BURSTCTL) = (HWREGH(base + ADC_O_BURSTCTL) & + ~((uint16_t)ADC_BURSTCTL_BURSTTRIGSEL_M | + ADC_BURSTCTL_BURSTSIZE_M)) | regValue; + + EDIS; +} + +//***************************************************************************** +// +//! Enables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function enables SOC burst mode operation of the ADC. Burst mode +//! allows a single trigger to walk through the round-robin SOCs one or more at +//! a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Use ADC_setBurstMode() to configure the burst trigger and size. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Enable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) |= ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function disables SOC burst mode operation of the ADC. SOCs in +//! round-robin mode will be triggered by the trigger configured using the +//! ADC_setupSOC() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Disable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) &= ~ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Sets the priority mode of the SOCs. +//! +//! \param base is the base address of the ADC. +//! \param priMode is the priority mode of the SOCs. +//! +//! This function sets the priority mode of the SOCs. There are three main +//! modes that can be passed in the \e priMode parameter +//! +//! - All SOCs are in round-robin mode. This means no SOC has an inherent +//! higher priority over another. This is selected by passing in the value +//! \b ADC_PRI_ALL_ROUND_ROBIN. +//! - All priorities are in high priority mode. This means that the priority of +//! the SOC is determined by its SOC number. This option is selected by passing +//! in the value \b ADC_PRI_ALL_HIPRI. +//! - A range of SOCs are assigned high priority, with all others in round +//! robin mode. High priority mode means that an SOC with high priority will +//! interrupt the round robin wheel and insert itself as the next conversion. +//! Passing in the value \b ADC_PRI_SOC0_HIPRI will make SOC0 highest priority, +//! \b ADC_PRI_THRU_SOC1_HIPRI will put SOC0 and SOC 1 in high priority, and so +//! on up to \b ADC_PRI_THRU_SOC14_HIPRI where SOCs 0 through 14 are in high +//! priority. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + EALLOW; + + HWREGH(base + ADC_O_SOCPRICTL) = (HWREGH(base + ADC_O_SOCPRICTL) & + ~ADC_SOCPRICTL_SOCPRIORITY_M) | + (uint16_t)priMode; + + EDIS; +} + +//***************************************************************************** +// +//! Configures Open/Shorts Detection Circuit Mode. +//! +//! \param base is the base address of the ADC. +//! \param modeVal is the desired open/shorts detection circuit mode. +//! +//! This function configures the open/shorts detection circuit mode of the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal) +{ + // + // Configure open/shorts detection circuit mode. + // + EALLOW; + HWREGH(base + ADC_O_OSDETECT) = ((HWREGH(base + ADC_O_OSDETECT) & + (~ADC_OSDETECT_DETECTCFG_M)) | + (uint16_t)modeVal); + EDIS; +} + +//***************************************************************************** +// +//! Configures a post-processing block (PPB) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function associates a post-processing block with a SOC. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. The \e socNumber +//! number is a value \b ADC_SOC_NUMBERX where X is a number from 0 to 15 +//! specifying which SOC is to be configured on the ADC module specified by +//! \e base. +//! +//! \note You can have more that one PPB associated with the same SOC, but a +//! PPB can only be configured to correspond to one SOC at a time. Also note +//! that when you have multiple PPBs for the same SOC, the calibration offset +//! that actually gets applied will be that of the PPB with the highest number. +//! Since SOC0 is the default for all PPBs, look out for unintentional +//! overwriting of a lower numbered PPB's offset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Write the configuration to the register. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1CONFIG_CONFIG_M) | + ((uint16_t)socNumber & ADC_PPB1CONFIG_CONFIG_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function enables the indicated ADC PPB event sources. This will allow +//! the specified events to propagate through the X-BAR to a pin or to an ePWM +//! module. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Enable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) |= evtFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function disables the indicated ADC PPB event sources. This will stop +//! the specified events from propagating through the X-BAR to other modules. +//! The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Disable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) &= ~(evtFlags << ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Enable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) |= intFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt source to be disabled. +//! +//! This function disables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Disable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) &= ~(intFlags << + ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Gets the current ADC event status. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the event status for the analog-to-digital converter. +//! +//! \return Returns the current event status, enumerated as a bit field of +//! \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, and \b ADC_EVT_ZERO. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the event status for the specified post-processing block. + // + return((HWREGH(base + ADC_O_EVTSTAT) >> ((uint16_t)ppbNumber * 4U)) & + 0x7U); +} + +//***************************************************************************** +// +//! Clears ADC event flags. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event source to be cleared. +//! +//! This function clears the indicated ADC PPB event flags. After an event +//! occurs this function must be called to allow additional events to be +//! produced. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Clear the specified event interrupts. + // + HWREGH(base + ADC_O_EVTCLR) |= evtFlags << ((uint16_t)ppbNumber * 4U); +} + + +//***************************************************************************** +// +//! Reads the processed conversion result from the PPB. +//! +//! \param resultBase is the base address of the ADC results. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the processed conversion result that corresponds to +//! the base address passed into \e resultBase and the PPB passed into +//! \e ppbNumber. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the signed 32-bit conversion result. +// +//***************************************************************************** +static inline int32_t +ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the result of selected PPB. + // + return((int32_t)HWREG(resultBase + (uint32_t)ADC_PPBxRESULT_OFFSET_BASE + + ((uint32_t)ppbNumber * 2UL))); +} + +//***************************************************************************** +// +//! Reads sample delay time stamp from a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the sample delay time stamp. This delay is the number +//! of system clock cycles between the SOC being triggered and when it began +//! converting. +//! +//! \return Returns the delay time stamp. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate delay. + // + ppbOffset = (ADC_PPBxSTAMP_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1STAMP; + + // + // Return the delay time stamp. + // + return(HWREGH(base + ppbOffset) & ADC_PPB2STAMP_DLYSTAMP_M); +} + +//***************************************************************************** +// +//! Sets the post processing block offset correction. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 10-bit signed value subtracted from ADC the output. +//! +//! This function sets the PPB offset correction value. This value can be used +//! to digitally remove any system-level offset inherent in the ADCIN circuit +//! before it is stored in the appropriate result register. The \e offset +//! parameter is \b subtracted from the ADC output and is a signed value from +//! -512 to 511 inclusive. For example, when \e offset = 1, ADCRESULT = ADC +//! output - 1. When \e offset = -512, ADCRESULT = ADC output - (-512) or ADC +//! output + 512. +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation, allowing the raw ADC result to be passed unchanged into the +//! result register. +//! +//! \note If multiple PPBs are applied to the same SOC, the offset that will be +//! applied will be that of the PPB with the highest number. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, + int16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFCAL_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFCAL; + + // + // Write the offset amount. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1OFFCAL_OFFCAL_M) | + ((uint16_t)offset & ADC_PPB1OFFCAL_OFFCAL_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the post processing block reference offset. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 16-bit unsigned value subtracted from ADC the output. +//! +//! This function sets the PPB reference offset value. This can be used to +//! either calculate the feedback error or convert a unipolar signal to bipolar +//! by subtracting a reference value. The result will be stored in the +//! appropriate PPB result register which can be read using ADC_readPPBResult(). +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation and will pass the ADC result to the PPB result register +//! unchanged. +//! +//! \note If in 12-bit mode, you may only pass a 12-bit value into the \e offset +//! parameter. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFREF_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFREF; + + // + // Write the offset amount. + // + HWREGH(base + ppbOffset) = offset; +} + +//***************************************************************************** +// +//! Enables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function enables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When enabled, a two's complement +//! will be performed on the output of the offset subtraction before it is +//! stored in the appropriate PPB result register. In other words, the PPB +//! result will be the reference offset value minus the the ADC result value +//! (ADCPPBxRESULT = ADCSOCxOFFREF - ADCRESULTx). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Enable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) |= ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function disables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When disabled, a two's complement +//! will \b NOT be performed on the output of the offset subtraction before it +//! is stored in the appropriate PPB result register. In other words, the PPB +//! result will be the ADC result value minus the reference offset value +//! (ADCPPBxRESULT = ADCRESULTx - ADCSOCxOFFREF). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Disable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) &= ~ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Enables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables the indicated ADC interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1E << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables the indicated ADC interrupt source. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt. Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1E << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the source EOC for an analog-to-digital converter interrupt. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function sets which conversion is the source of an ADC interrupt. +//! +//! The \e intTrigger number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which EOC is to be configured on the ADC module +//! specified by \e base. Refer \b ADC_SOCNumber enum for valid values for +//! this input. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, + uint16_t intTrigger) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(intTrigger < 16U); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Set the specified ADC interrupt source. + // + EALLOW; + + HWREGH(intRegAddr) = + (HWREGH(intRegAddr) & ~(ADC_INTSEL1N2_INT1SEL_M << shiftVal)) | + ((uint16_t)intTrigger << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Enables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will be generated for the specified +//! ADC interrupt whenever an EOC pulse is generated irrespective of whether or +//! not the flag bit is set. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1CONT << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will not be generated for the +//! specified ADC interrupt until the corresponding interrupt flag for the +//! previous interrupt occurrence has been cleared using +//! ADC_clearInterruptStatus(). +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1CONT << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees C +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees C. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees C. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureC(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)((((int32_t)temp + (int32_t)0x4000 + + ((int32_t)273 * (int32_t)0x8000)) / + (int32_t)0x8000) - (int32_t)273)); +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees K +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees K. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees K. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureK(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)(((int32_t)temp + (int32_t)0x4000 + ((int32_t)273 * + (int32_t)0x8000)) / (int32_t)0x8000)); +} + + +//***************************************************************************** +// +//! Configures the analog-to-digital converter resolution and signal mode. +//! +//! \param base is the base address of the ADC module. +//! \param resolution is the resolution of the converter (12 or 16 bits). +//! \param signalMode is the input signal mode of the converter. +//! +//! This function configures the ADC module's conversion resolution and input +//! signal mode and ensures that the corresponding trims are loaded. +//! +//! The \e resolution parameter specifies the resolution of the conversion. +//! It can be 12-bit or 16-bit specified by \b ADC_RESOLUTION_12BIT +//! or \b ADC_RESOLUTION_16BIT. +//! +//! The \e signalMode parameter specifies the signal mode. In single-ended +//! mode, which is indicated by \b ADC_MODE_SINGLE_ENDED, the input voltage is +//! sampled on a single pin referenced to VREFLO. In differential mode, which +//! is indicated by \b ADC_MODE_DIFFERENTIAL, the input voltage to the +//! converter is sampled on a pair of input pins, a positive and a negative. +//! +//! \b Note: In this device, single-ended signal conversions are supported +//! only in 12-bit resolution mode and differential signal +//! conversions are supported only in 16-bit resolution mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode); + + +//***************************************************************************** +// +//! Configures the offset trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the offset trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setOffsetTrim(uint32_t base); + +//***************************************************************************** +// +//! Configures the INL trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the INL trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setINLTrim(uint32_t base); + +//***************************************************************************** +// +//! Sets the windowed trip limits for a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param tripHiLimit is the value is the digital comparator trip high limit. +//! \param tripLoLimit is the value is the digital comparator trip low limit. +//! +//! This function sets the windowed trip limits for a PPB. These values set +//! the digital comparator so that when one of the values is exceeded, either a +//! high or low trip event will occur. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. +//! +//! If using 16-bit mode, you may pass a 17-bit number into the \e tripHiLimit +//! and \e tripLoLimit parameters where the 17th bit is the sign bit (that is +//! a value from -65536 and 65535). In 12-bit mode, only bits 12:0 will be +//! compared against bits 12:0 of the PPB result. +//! +//! \note On some devices, signed trip values do not work properly. See the +//! silicon errata for details. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ADC_H diff --git a/gpio_bitfield_cpu1/device/driverlib/asysctl.c b/gpio_bitfield_cpu1/device/driverlib/asysctl.c new file mode 100644 index 0000000..4f3d202 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/asysctl.c @@ -0,0 +1,43 @@ +//########################################################################### +// +// FILE: asysctl.c +// +// TITLE: C28x Driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "asysctl.h" diff --git a/gpio_bitfield_cpu1/device/driverlib/asysctl.h b/gpio_bitfield_cpu1/device/driverlib/asysctl.h new file mode 100644 index 0000000..40e6c5c --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/asysctl.h @@ -0,0 +1,160 @@ +//########################################################################### +// +// FILE: asysctl.h +// +// TITLE: C28x driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ASYSCTL_H +#define ASYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup asysctl_api ASysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_asysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enable temperature sensor. +//! +//! This function enables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_enableTemperatureSensor(void) +{ + EALLOW; + + // + // Set the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) |= ASYSCTL_TSNSCTL_ENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable temperature sensor. +//! +//! This function disables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_disableTemperatureSensor(void) +{ + EALLOW; + + // + // Clear the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) &= ~(ASYSCTL_TSNSCTL_ENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the temperature sensor control register. +//! +//! \return None. +// +//***************************************************************************** +static inline void ASysCtl_lockTemperatureSensor(void) +{ + EALLOW; + + // + // Write a 1 to the lock bit in the LOCK register. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_LOCK) |= ASYSCTL_LOCK_TSNSCTL; + + EDIS; +} + + + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ASYSCTL_H diff --git a/gpio_bitfield_cpu1/device/driverlib/can.c b/gpio_bitfield_cpu1/device/driverlib/can.c new file mode 100644 index 0000000..5a33a50 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/can.c @@ -0,0 +1,1122 @@ +//########################################################################### +// +// FILE: can.c +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#include "can.h" + +//***************************************************************************** +// +// CAN_initModule +// +//***************************************************************************** +void +CAN_initModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + HWREGH(base + CAN_O_CTL) |= ((uint16_t)CAN_CTL_INIT | + (uint16_t)CAN_INIT_PARITY_DISABLE); + + // + // Initialize the message RAM before using it. + // + CAN_initRAM(base); + + // + // Force module to reset state + // + + HWREGH(base + CAN_O_CTL) |= CAN_CTL_SWR; + + // + // Delay for 14 cycles + // + SysCtl_delay(1U); + + // + // Enable write access to the configuration registers + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_CCE; +} + +//***************************************************************************** +// +// CAN_setBitRate +// +//***************************************************************************** +void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime) +{ + uint16_t brp; + uint16_t tPhase; + uint16_t phaseSeg2; + uint16_t tSync = 1U; + uint16_t tProp = 2U; + uint16_t tSeg1; + uint16_t tSeg2; + uint16_t sjw; + uint16_t prescaler; + uint16_t prescalerExtension; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((bitTime > 7U) && (bitTime < 26U)); + ASSERT(bitRate <= 1000000U); + + // + // Calculate bit timing values + // + brp = (uint16_t)(clockFreq / (bitRate * bitTime)); + tPhase = bitTime - (tSync + tProp); + if((tPhase / 2U) <= 8U) + { + phaseSeg2 = tPhase / 2U; + } + else + { + phaseSeg2 = 8U; + } + tSeg1 = ((tPhase - phaseSeg2) + tProp) - 1U; + tSeg2 = phaseSeg2 - 1U; + if(phaseSeg2 > 4U) + { + sjw = 3U; + } + else + { + sjw = tSeg2; + } + prescalerExtension = ((brp - 1U) / 64U); + prescaler = ((brp - 1U) % 64U); + + // + // Set the calculated timing parameters + // + CAN_setBitTiming(base, prescaler, prescalerExtension, tSeg1, tSeg2, sjw); +} + +//***************************************************************************** +// +// CAN_setBitTiming +// +//***************************************************************************** +void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw) +{ + uint16_t savedInit; + uint32_t bitReg; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT(prescaler < 64U); + ASSERT((tSeg1 > 0U) && (tSeg1 < 16U)); + ASSERT(tSeg2 < 8U); + ASSERT(sjw < 4U); + ASSERT(prescalerExtension < 16U); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. + // State of the init bit should be saved so it can be restored at the end. + // + savedInit = HWREGH(base + CAN_O_CTL); + HWREGH(base + CAN_O_CTL) = savedInit | CAN_CTL_INIT | CAN_CTL_CCE; + + // + // Set the bit fields of the bit timing register + // + bitReg = (uint32_t)((uint32_t)prescaler & CAN_BTR_BRP_M); + bitReg |= (uint32_t)(((uint32_t)sjw << CAN_BTR_SJW_S) & CAN_BTR_SJW_M); + bitReg |= (uint32_t)(((uint32_t)tSeg1 << CAN_BTR_TSEG1_S) & + CAN_BTR_TSEG1_M); + bitReg |= (uint32_t)(((uint32_t)tSeg2 << CAN_BTR_TSEG2_S) & + CAN_BTR_TSEG2_M); + bitReg |= (uint32_t)(((uint32_t)prescalerExtension << CAN_BTR_BRPE_S) & + CAN_BTR_BRPE_M); + + HWREG_BP(base + CAN_O_BTR) = bitReg; + + // + // Clear the config change bit, and restore the init bit. + // + savedInit &= ~((uint16_t)CAN_CTL_CCE); + + HWREGH(base + CAN_O_CTL) = savedInit; +} + + +//***************************************************************************** +// +// CAN_clearInterruptStatus +// +//***************************************************************************** +void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intClr == CAN_INT_INT0ID_STATUS) || + ((intClr >= 1U) && (intClr <= 32U))); + + if(intClr == (uint32_t)CAN_INT_INT0ID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + HWREGH(base + CAN_O_ES); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMD_CLRINTPND bit. + // + // Send the clear pending interrupt command to the CAN controller. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CLRINTPND | + (intClr & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + } +} + +//***************************************************************************** +// +// CAN_setupMessageObject +// +//***************************************************************************** +void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen) +{ + uint32_t cmdMaskReg = 0U; + uint32_t maskReg = 0U; + uint32_t arbReg = 0U; + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + switch(msgType) + { + // + // Transmit message object. + // + case CAN_MSG_OBJ_TYPE_TX: + { + // + // Set message direction to transmit. + // + arbReg = CAN_IF1ARB_DIR; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case CAN_MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Set message direction to Tx for remote receivers. + // + arbReg = CAN_IF1ARB_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + msgCtrl = (uint32_t)((uint32_t)CAN_IF1MCTL_RMTEN | + (uint32_t)CAN_IF1MCTL_UMASK); + + break; + } + + // + // Transmit remote request message object (CAN_MSG_OBJ_TYPE_TX_REMOTE) + // or Receive message object (CAN_MSG_OBJ_TYPE_RX). + // + default: + { + // + // Set message direction to read. + // + arbReg = 0U; + + break; + } + } + + // + // Set values based on Extended Frame or Standard Frame + // + if(frame == CAN_MSG_FRAME_EXT) + { + // + // Configure the Mask Registers for 29 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = msgIDMask & CAN_IF1MSK_MSK_M; + } + + // + // Set the 29 bit version of the Identifier for this message + // object. Mark the message as valid and set the extended ID bit. + // + arbReg |= (msgID & CAN_IF1ARB_ID_M) | CAN_IF1ARB_MSGVAL | + CAN_IF1ARB_XTD; + } + else + { + // + // Configure the Mask Registers for 11 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = ((msgIDMask << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M); + } + + // + // Set the 11 bit version of the Identifier for this message + // object. The lower 18 bits are set to zero. Mark the message as + // valid. + // + arbReg |= ((msgID << CAN_IF1ARB_STD_ID_S) & CAN_IF1ARB_STD_ID_M) | + CAN_IF1ARB_MSGVAL; + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_EXT_FILTER); + + // + // The caller wants to filter on the message direction field. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_DIR_FILTER); + + // + // If any filtering is requested, set the UMASK bit to use mask register + // + if(((flags & CAN_MSG_OBJ_USE_ID_FILTER) | + (flags & CAN_MSG_OBJ_USE_DIR_FILTER) | + (flags & CAN_MSG_OBJ_USE_EXT_FILTER)) != 0U) + { + msgCtrl |= CAN_IF1MCTL_UMASK; + } + + // + // Set the data length for the transfers. This is applicable only for + // Tx mailboxes. For Rx mailboxes, dlc is updated on receving a frame. + // + if((msgType == CAN_MSG_OBJ_TYPE_TX) || + (msgType == CAN_MSG_OBJ_TYPE_RXTX_REMOTE)) + { + msgCtrl |= ((uint32_t)msgLen & CAN_IF1MCTL_DLC_M); + } + + // + // If this is a single transfer or the last mailbox of a FIFO, set EOB bit. + // If this is not the last entry in a FIFO, leave the EOB bit as 0. + // + if((flags & CAN_MSG_OBJ_FIFO) == 0U) + { + msgCtrl |= CAN_IF1MCTL_EOB; + } + + // + // Enable transmit interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_TX_INT_ENABLE); + + // + // Enable receive interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_RX_INT_ENABLE); + + // + // Set the Control, Arb, and Mask bit so that they get transferred to the + // Message object. + // + cmdMaskReg |= CAN_IF1CMD_ARB; + cmdMaskReg |= CAN_IF1CMD_CONTROL; + cmdMaskReg |= CAN_IF1CMD_MASK; + cmdMaskReg |= CAN_IF1CMD_DIR; + + // + // Write out the registers to program the message object. + // + HWREG_BP(base + CAN_O_IF1MSK) = maskReg; + HWREG_BP(base + CAN_O_IF1ARB) = arbReg; + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M); +} + +//***************************************************************************** +// +// CAN_sendMessage +// +//***************************************************************************** +void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_16bit +// +//***************************************************************************** +void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_16bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_32bit +// +//***************************************************************************** +void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_32bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_updateDLC +// +//***************************************************************************** +void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Update to the new data length + // + msgCtrl &= ~CAN_IF1MCTL_DLC_M; + msgCtrl |= (msgLen & CAN_IF1MCTL_DLC_M); + + // + // Write out to the register to program the message object + // + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + (CAN_IF1CMD_CONTROL | CAN_IF1CMD_DIR | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendRemoteRequestMessage +// +//***************************************************************************** +void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check configured DLC size with 0 as this is a remote frame + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == 0U); + + // + // Set Direction to write + // + // Set Tx Request Bit for this remote frame + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_readMessage +// +//***************************************************************************** +bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData) +{ + bool status; + uint16_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID != 0U)); + + // + // Set the Message Data A, Data B, and control values to be read + // on request for data from the message object. + // + // Transfer the message object to the message object IF register. + // + HWREG_BP(base + CAN_O_IF2CMD) = + ((uint32_t)CAN_IF2CMD_DATA_A | (uint32_t)CAN_IF2CMD_DATA_B | + (uint32_t)CAN_IF2CMD_CONTROL | (objID & CAN_IF2CMD_MSG_NUM_M) | + (uint32_t)CAN_IF2CMD_ARB); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == CAN_IF2CMD_BUSY) + { + } + + // + // Read out the IF control Register. + // + msgCtrl = HWREGH(base + CAN_O_IF2MCTL); + + // + // See if there is new data available. + // + if((msgCtrl & CAN_IF2MCTL_NEWDAT) == CAN_IF2MCTL_NEWDAT) + { + // + // Read out the data from the CAN registers. + // + CAN_readDataReg(msgData, (base + CAN_O_IF2DATA), + ((uint32_t)msgCtrl & CAN_IF2MCTL_DLC_M)); + + status = true; + + // + // Now clear out the new data flag + // + HWREG_BP(base + CAN_O_IF2CMD) = ((uint32_t)CAN_IF2CMD_TXRQST | + (objID & CAN_IF2CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == + CAN_IF2CMD_BUSY) + { + } + } + else + { + status = false; + } + + return(status); +} + +//***************************************************************************** +// +// CAN_readMessageWithID +// +//***************************************************************************** +bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData) +{ + bool status; + + // + // Check the pointers. + // + ASSERT(msgID != 0U); + ASSERT(frameType != 0U); + + // + //Read the message first this fills the IF2 registers + //with received message for that mailbox + // + status = CAN_readMessage(base, objID, msgData); + // + // See if there is new data available. + // + if(status) + { + if((HWREG_BP(base + CAN_O_IF2ARB) & CAN_IF2ARB_XTD) != 0U) + { + *frameType = CAN_MSG_FRAME_EXT; + *msgID = ((HWREG_BP(base + CAN_O_IF2ARB)) & CAN_IF2ARB_ID_M); + } + else + { + *frameType = CAN_MSG_FRAME_STD; + *msgID = (((HWREG_BP(base + CAN_O_IF2ARB)) & + CAN_IF2ARB_STD_ID_M) >> + CAN_IF2ARB_STD_ID_S); + } + } + + return(status); +} + +//***************************************************************************** +// +// CAN_transferMessage +// +//***************************************************************************** +void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction) +{ + uint32_t cmdMaskReg; + + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + ASSERT((interface == 1U) || (interface == 2U)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + cmdMaskReg = + ((uint32_t)CAN_IF1CMD_DATA_A | (uint32_t)CAN_IF1CMD_DATA_B | + (uint32_t)CAN_IF1CMD_TXRQST | (uint32_t)CAN_IF1CMD_CONTROL | + (uint32_t)CAN_IF1CMD_MASK | (uint32_t)CAN_IF1CMD_ARB) | + (direction ? CAN_IF1CMD_DIR : 0U); + + // + // Ensure this IF isn't busy + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set up the request for data from the message object. Transfer the + // message object to the message object specified by objID. + // + HWREG_BP(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) = + (cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } +} + +//***************************************************************************** +// +// CAN_clearMessage +// +//***************************************************************************** +void +CAN_clearMessage(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableMessageObject +// +//***************************************************************************** +void +CAN_disableMessageObject(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableAllMessageObjects +// +//***************************************************************************** +void +CAN_disableAllMessageObjects(uint32_t base) +{ + uint32_t objID; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Loop to disable all valid message objects + // + for(objID = 0x01UL; objID <= 0x20UL; objID++) + { + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); + } +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/can.h b/gpio_bitfield_cpu1/device/driverlib/can.h new file mode 100644 index 0000000..247d1df --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/can.h @@ -0,0 +1,1924 @@ +//########################################################################### +// +// FILE: can.h +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef CAN_H +#define CAN_H + + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup can_api CAN +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_can.h" +#include "debug.h" +#include "sysctl.h" + +// +// The key value for RAM initialization +// +#define CAN_RAM_INIT_KEY (0xAU) + +// +// RAM Initialization Register Mask +// +#define CAN_RAM_INIT_MASK (0x003FU) + +// +// The Parity disable key value +// +#define CAN_INIT_PARITY_DISABLE (0x1400U) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** +//***************************************************************************** +// +// These are the flags used by the flags parameter when calling +// the CAN_setupMessageObject() function. +// +//***************************************************************************** + +//! This indicates that transmit interrupts should be enabled, or are enabled. +#define CAN_MSG_OBJ_TX_INT_ENABLE CAN_IF1MCTL_TXIE + +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +#define CAN_MSG_OBJ_RX_INT_ENABLE CAN_IF1MCTL_RXIE + +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +#define CAN_MSG_OBJ_USE_ID_FILTER (0x00000001U) + +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. +#define CAN_MSG_OBJ_USE_DIR_FILTER CAN_IF1MSK_MDIR + +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. +#define CAN_MSG_OBJ_USE_EXT_FILTER CAN_IF1MSK_MXTD + +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +#define CAN_MSG_OBJ_FIFO (0x00000002U) + +//! This indicates that a message object has no flags set. +#define CAN_MSG_OBJ_NO_FLAGS (0x00000000U) + +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to +// CAN_enableInterrupt() and CAN_disableInterrupt(). +// +//***************************************************************************** +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +#define CAN_INT_ERROR (0x00000008UL) + +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +#define CAN_INT_STATUS (0x00000004UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 0 +#define CAN_INT_IE0 (0x00000002UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 1 +#define CAN_INT_IE1 (0x00020000UL) + +//***************************************************************************** +// +// The following definitions contain all error or status indicators that can +// be returned when calling the CAN_getStatus() function. +// +//***************************************************************************** + +//! CAN controller has detected a parity error. +#define CAN_STATUS_PERR (0x00000100U) + +//! CAN controller has entered a Bus Off state. +#define CAN_STATUS_BUS_OFF (0x00000080U) + +//! CAN controller error level has reached warning level. +#define CAN_STATUS_EWARN (0x00000040U) + +//! CAN controller error level has reached error passive level. +#define CAN_STATUS_EPASS (0x00000020U) + +//! A message was received successfully since the last read of this status. +#define CAN_STATUS_RXOK (0x00000010U) + +//! A message was transmitted successfully since the last read of this +//! status. +#define CAN_STATUS_TXOK (0x00000008U) + +//! This is the mask for the last error code field. +#define CAN_STATUS_LEC_MSK (0x00000007U) + +//! There was no error. +#define CAN_STATUS_LEC_NONE (0x00000000U) + +//! A bit stuffing error has occurred. +#define CAN_STATUS_LEC_STUFF (0x00000001U) + +//! A formatting error has occurred. +#define CAN_STATUS_LEC_FORM (0x00000002U) + +//! An acknowledge error has occurred. +#define CAN_STATUS_LEC_ACK (0x00000003U) + +//! The bus remained a bit level of 1 for longer than is allowed. +#define CAN_STATUS_LEC_BIT1 (0x00000004U) + +//! The bus remained a bit level of 0 for longer than is allowed. +#define CAN_STATUS_LEC_BIT0 (0x00000005U) + +//! A CRC error has occurred. +#define CAN_STATUS_LEC_CRC (0x00000006U) + +//***************************************************************************** +// +// The following macros are added for the Global Interrupt EN/FLG/CLR +// register +// +//***************************************************************************** +//! CANINT0 global interrupt bit +#define CAN_GLOBAL_INT_CANINT0 (0x00000001U) + +//! CANINT1 global interrupt bit +#define CAN_GLOBAL_INT_CANINT1 (0x00000002U) + +//***************************************************************************** +// +// The following macros are added for accessing the interrupt register and +// the standard arbitration ID in the interface registers. +// +//***************************************************************************** +//! Status of INT0ID +#define CAN_INT_INT0ID_STATUS (0x8000U) + +//! IF1 Arbitration Standard ID Shift Offset +#define CAN_IF1ARB_STD_ID_S (18U) + +//! IF1 Arbitration Standard ID Mask +#define CAN_IF1ARB_STD_ID_M (0x1FFC0000U) + +//! IF2 Arbitration Standard ID Shift Offset +#define CAN_IF2ARB_STD_ID_S (18U) + +//! IF2 Arbitration Standard ID Mask +#define CAN_IF2ARB_STD_ID_M (0x1FFC0000U) + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! This data type is used to decide between STD_ID or EXT_ID for a mailbox. +//! This is used when calling the CAN_setupMessageObject() function. +// +//***************************************************************************** +typedef enum +{ + //! Set the message ID frame to standard. + CAN_MSG_FRAME_STD, + + //! Set the message ID frame to extended. + CAN_MSG_FRAME_EXT +} CAN_MsgFrameType; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CAN_setupMessageObject() API. +// +//***************************************************************************** +typedef enum +{ + //! Transmit message object. + CAN_MSG_OBJ_TYPE_TX, + + //! Transmit remote request message object + CAN_MSG_OBJ_TYPE_TX_REMOTE, + + //! Receive message object. + CAN_MSG_OBJ_TYPE_RX, + + //! Remote frame receive remote, with auto-transmit message object. + CAN_MSG_OBJ_TYPE_RXTX_REMOTE +} CAN_MsgObjType; + +//***************************************************************************** +// +//! This definition is used to determine the clock source that will +//! be set up via a call to the CAN_selectClockSource() API. +// +//***************************************************************************** +typedef enum +{ + //! Peripheral System Clock Source + CAN_CLOCK_SOURCE_SYS = 0x0, + + //! External Oscillator Clock Source + CAN_CLOCK_SOURCE_XTAL = 0x1, + + //! Auxiliary Clock Input Source + CAN_CLOCK_SOURCE_AUX = 0x2 +} CAN_ClockSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! +//! Checks a CAN base address. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CAN_isBaseValid(uint32_t base) +{ + return( + (base == CANA_BASE) || + (base == CANB_BASE) + ); +} +#endif + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_writeDataReg(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = data[idx]; + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 16bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_16bit(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = (uint32_t)((data[idx / 2UL]) >> ((idx % 2UL) * 8UL)); + + dataReg++; + } +} + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 32bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_32bit(const uint32_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = ((data[idx / 4UL]) >> ((idx % 4UL) * 8UL)); + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from the CAN Data registers to a buffer. +//! +//! \param data is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_readDataReg(uint16_t *data, const uint32_t address, uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Read out the data + // + data[idx] = HWREGB(dataReg); + + dataReg++; + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller's RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Performs the initialization of the RAM used for the CAN message objects. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_initRAM(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + HWREGH(base + CAN_O_RAM_INIT) = CAN_RAM_INIT_CAN_RAM_INIT | + CAN_RAM_INIT_KEY; + + while(!((HWREGH(base + CAN_O_RAM_INIT) & CAN_RAM_INIT_MASK) == + (CAN_RAM_INIT_RAM_INIT_DONE | CAN_RAM_INIT_KEY2 | + CAN_RAM_INIT_KEY0))) + { + // + // Wait until RAM Init is complete + // + } +} + +//***************************************************************************** +// +//! Select CAN Clock Source +//! +//! \param base is the base address of the CAN controller. +//! \param source is the clock source to use for the CAN controller. +//! +//! This function selects the specified clock source for the CAN controller. +//! +//! The \e source parameter can be any one of the following: +//! - \b CAN_CLOCK_SOURCE_SYS - Peripheral System Clock +//! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator +//! - \b CAN_CLOCK_SOURCE_AUX - Auxiliary Clock Input from GPIO +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_selectClockSource(uint32_t base, CAN_ClockSource source) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Determine the CAN controller and set specified clock source + // + EALLOW; + + switch(base) + { + case CANA_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANABCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANABCLKSEL_S); + break; + + case CANB_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S); + break; + + default: + + // + // Do nothing. Not a valid mode value. + // + break; + } + + EDIS; + SYSCTL_CLKSRCCTL_DELAY; +} + +//***************************************************************************** +// +//! Starts the CAN Module's Operations +//! +//! \param base is the base address of the CAN controller. +//! +//! This function starts the CAN module's operations after initialization, +//! which includes the CAN protocol controller state machine of the CAN core +//! and the message handler state machine to begin controlling the CAN's +//! internal data flow. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_startModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear Init and CCE bits + // + HWREGH(base + CAN_O_CTL) &= ~(CAN_CTL_INIT | CAN_CTL_CCE); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param base is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller will automatically transmit any pending frames, and process any +//! received frames. The controller can be stopped by calling +//! CAN_disableController(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param base is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller will no longer automatically process data on the CAN bus. The +//! controller can be restarted by calling CAN_enableController(). The state +//! of the CAN controller and the message objects in the controller are left as +//! they were before this call was made. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Enables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param mode are the the test modes to enable. +//! +//! Enables test modes within the controller. The following valid options for +//! \e mode can be OR'ed together: +//! - \b CAN_TEST_SILENT - Silent Mode +//! - \b CAN_TEST_LBACK - Loopback Mode +//! - \b CAN_TEST_EXL - External Loopback Mode +//! +//! \note Loopback mode and external loopback mode \b can \b not be +//! enabled at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableTestMode(uint32_t base, uint16_t mode) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((mode & (CAN_TEST_LBACK | CAN_TEST_EXL)) != + (CAN_TEST_LBACK | CAN_TEST_EXL)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Enable test mode and set the bits in the test register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_TEST; + HWREGH(base + CAN_O_TEST) |= mode; +} + +//***************************************************************************** +// +//! Disables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables test modes within the controller and clears the test bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableTestMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Clear the test mode enable bit + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_TEST; +} + +//***************************************************************************** +// +//! Get the current settings for the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing. +//! +//! \return Returns the value of the bit timing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getBitTiming(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read and return BTR register + // + return(HWREG_BP(base + CAN_O_BTR)); +} + +//***************************************************************************** +// +//! Enables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables direct access to the RAM while in Test mode. +//! +//! \note Test Mode must first be enabled to use this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) |= CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Disables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables direct access to the RAM while in Test mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) &= ~CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Sets the interruption debug mode of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param enable is a flag to enable or disable the interruption debug mode. +//! +//! This function sets the interruption debug mode of the CAN controller. When +//! the \e enable parameter is \b true, CAN will be configured to interrupt any +//! transmission or reception and enter debug mode immediately after it is +//! requested. When \b false, CAN will wait for a started transmission or +//! reception to be completed before entering debug mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptionDebugMode(uint32_t base, bool enable) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + if(enable) + { + // + // Enable interrupt debug support + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_IDS; + } + else + { + // + // Disable interrupt debug support + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_IDS; + } +} + + +//***************************************************************************** +// +//! Disables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the Auto-Bus-On feature of the CAN controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Enables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the Auto-Bus-On feature of the CAN controller. Be sure to also +//! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Sets the time before a Bus-Off recovery sequence is started. +//! +//! \param base is the base address of the CAN controller. +//! \param onTime is number of clock cycles before a Bus-Off recovery sequence +//! is started. +//! +//! This function sets the number of clock cycles before a Bus-Off recovery +//! sequence is started by clearing the Init bit. +//! +//! \note To enable this functionality, use CAN_enableAutoBusOn(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setAutoBusOnTime(uint32_t base, uint32_t onTime) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set bus-off timer value + // + HWREG_BP(base + CAN_O_ABOTR) = onTime; +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt +//! line 0 +//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt +//! line 1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Enable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e intFlags parameter has the same definition as in the +//! CAN_enableInterrupt() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Disable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Get the CAN controller Interrupt Line set for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! +//! Gets which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return Returns the value of the interrupt muxing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMux(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Get the interrupt muxing for the CAN peripheral + // + return(HWREG_BP(base + CAN_O_IP_MUX21)); +} + +//***************************************************************************** +// +//! Set the CAN controller Interrupt Line for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! \param mux bit packed representation of which message objects should +//! generate an interrupt on a given interrupt line. +//! +//! Selects which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptMux(uint32_t base, uint32_t mux) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the interrupt muxing for the CAN peripheral + // + HWREG_BP(base + CAN_O_IP_MUX21) = mux; +} + +//***************************************************************************** +// +//! Enables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Disables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +CAN_isRetryEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + return((bool)((HWREGH(base + CAN_O_CTL) & CAN_CTL_DAR) != CAN_CTL_DAR)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param base is the base address of the CAN controller. +//! \param rxCount is a pointer to storage for the receive error counter. +//! \param txCount is a pointer to storage for the transmit error counter. +//! +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. +//! +//! After this call, \e rxCount will hold the current receive error count +//! and \e txCount will hold the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +static inline bool +CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount) +{ + uint32_t canError = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the current count of transmit/receive errors. + // + canError = HWREG_BP(base + CAN_O_ERRC); + + // + // Extract the error numbers from the register value. + // + *rxCount = (canError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S; + *txCount = (canError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S; + + return((bool)((canError & CAN_ERRC_RP) != 0U)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error and status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the error and status register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint16_t +CAN_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return error and status register value + // + return(HWREGH(base + CAN_O_ES)); +} + +//***************************************************************************** +// +//! Reads the CAN controller TX request register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the TX request register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getTxRequests(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return Tx requests register value + // + return(HWREG_BP(base + CAN_O_TXRQ_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller new data status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the new data status register of the CAN controller for all message +//! objects. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getNewDataFlags(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return new data register value + // + return(HWREG_BP(base + CAN_O_NDAT_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller valid message object register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the valid message object register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getValidMessageObjects(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return the valid message register value + // + return(HWREG_BP(base + CAN_O_MVAL_21)); +} + +//***************************************************************************** +// +//! Get the CAN controller interrupt cause. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function returns the value of the interrupt register that indicates +//! the cause of the interrupt. +//! +//! \return Returns the value of the interrupt register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptCause(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read interrupt identifier status + // + return(HWREG_BP(base + CAN_O_INT)); +} + +//***************************************************************************** +// +//! Get the CAN controller pending interrupt message source. +//! +//! \param base is the base address of the CAN controller. +//! +//! Returns the value of the pending interrupts register that indicates +//! which messages are the source of pending interrupts. +//! +//! \return Returns the value of the pending interrupts register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMessageSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read message object interrupt status + // + return(HWREG_BP(base + CAN_O_IPEN_21)); +} + +//***************************************************************************** +// +//! CAN Global interrupt Enable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt Enable bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt Enable bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Enable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) |= intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Disable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Disable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) &= ~intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Clear function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be cleared. +//! +//! Clear the specific CAN interrupt bit in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Clear the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_CLR) |= intFlags; +} + +//***************************************************************************** +// +//! Get the CAN Global Interrupt status. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Check if any interrupt bit is set in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return True if any of the requested interrupt bits are set. False, if +//! none of the requested bits are set. +// +//***************************************************************************** +static inline bool +CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Read and return the global interrupt flag register + // + return((bool)((HWREGH(base + CAN_O_GLB_INT_FLG) & intFlags) != 0U)); +} + +//***************************************************************************** +// +//! Initializes the CAN controller +//! +//! \param base is the base address of the CAN controller. +//! +//! This function initializes the message RAM, which also clears all the +//! message objects, and places the CAN controller in an init state. Write +//! access to the configuration registers is available as a result, allowing +//! the bit timing and message objects to be setup. +//! +//! \note To exit the initialization mode and start the CAN module, use the +//! CAN_startModule() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_initModule(uint32_t base); + +//***************************************************************************** +// +//! Sets the CAN Bit Timing based on requested Bit Rate. +//! +//! \param base is the base address of the CAN controller. +//! \param clockFreq is the CAN module clock frequency before the bit rate +//! prescaler (Hertz) +//! \param bitRate is the desired bit rate (bits/sec) +//! \param bitTime is the number of time quanta per bit required for desired +//! bit time (Tq) and must be in the range from 8 to 25 +//! +//! This function sets the CAN bit timing values for the bit rate passed in the +//! \e bitRate and \e bitTime parameters based on the \e clockFreq parameter. The +//! CAN bit clock is calculated to be an average timing value that should work +//! for most systems. If tighter timing requirements are needed, then the +//! CAN_setBitTiming() function is available for full customization of all of +//! the CAN bit timing values. +//! +//! \note Not all bit-rate and bit-time combinations are valid. +//! For combinations that would yield the correct bit-rate, +//! refer to the DCAN_CANBTR_values.xlsx file in the "docs" directory. +//! The CANBTR register values calculated by the function CAN_setBitRate +//! may not be suitable for your network parameters. If this is the case +//! and you have computed the correct values for your network, you could +//! directly write those parameters in CANBTR register using the +//! function CAN_setBitTiming. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime); + +//***************************************************************************** +// +//! Manually set the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! \param prescaler is the baud rate prescaler +//! \param prescalerExtension is the baud rate prescaler extension +//! \param tSeg1 is the time segment 1 +//! \param tSeg2 is the time segment 2 +//! \param sjw is the synchronization jump width +//! +//! This function sets the various timing parameters for the CAN bus bit +//! timing: baud rate prescaler, prescaler extension, time segment 1, +//! time segment 2, and the Synchronization Jump Width. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw); + + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param base is the base address of the CAN controller. +//! \param intClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e intClr parameter should be either a number from 1 to 32 to clear a +//! specific message object interrupt or can be the following: +//! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt. +//! +//! It is not necessary to use this function to clear an interrupt. This +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr); + +//***************************************************************************** +// +//! Setup a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to configure (1-32). +//! \param msgID is the CAN message identifier used for the 11 or 29 bit +//! identifiers +//! \param frame is the CAN ID frame type +//! \param msgType is the message object type +//! \param msgIDMask is the CAN message identifier mask used when identifier +//! filtering is enabled +//! \param flags is the various flags and settings to be set for the message +//! object +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! +//! This function sets the various values required for a message object. +//! +//! The \e frame parameter can be one of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! +//! The \e msgType parameter can be one of the following values: +//! - \b CAN_MSG_OBJ_TYPE_TX - Transmit Message +//! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE - Transmit Remote Message +//! - \b CAN_MSG_OBJ_TYPE_RX - Receive Message +//! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with +//! auto-transmit +//! +//! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags +//! are required or the parameter can be a logical OR of any of the following +//! values: +//! - \b CAN_MSG_OBJ_TX_INT_ENABLE - Enable Transmit Interrupts +//! - \b CAN_MSG_OBJ_RX_INT_ENABLE - Enable Receive Interrupts +//! - \b CAN_MSG_OBJ_USE_ID_FILTER - Use filtering based on the Message ID +//! (Standard or Extended) +//! - \b CAN_MSG_OBJ_USE_EXT_FILTER - Use Extended Identifier Bit for filtering +//! (Only among Extended IDs will be accepted) +//! - \b CAN_MSG_OBJ_USE_DIR_FILTER - Use filtering based on the direction of +//! the transfer +//! - \b CAN_MSG_OBJ_FIFO - Message object is part of a FIFO +//! structure and isn't the final message +//! object in FIFO +//! +//! If filtering is based on message identifier (for Standard or Extended IDs) +//! specified by the \e msgIDMask parameter, the value \b CAN_MSG_OBJ_USE_ID_FILTER +//! has to be logically ORed with the \e flag parameter. +//! If \b CAN_MSG_OBJ_USE_EXT_FILTER is ORed with the \e flag parameter, +//! only extended identifier frames are accepted which can further be masked +//! by using the flag above. +//! +//! \note The \b msgLen Parameter for the Receive Message Object is a "don't +//! care" but its value should be between 0-8 due to the assert. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 16 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 32 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object while dynamically updating data length +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable and can be used to dynamically update the data length +//! for every subsequent call of this function. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Remote Request Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! +//! This function is used to transmit a remote request message object. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function with CAN_MSG_OBJ_TYPE_TX_REMOTE +//! as msgType flag. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Reads the data in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param msgData is a pointer to the array to store the message data +//! +//! This function is used to read the data contents of the specified message +//! object in the CAN controller. The data returned is stored in the +//! \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! -# If the DLC of the received message is larger than the \e msgData +//! buffer provided, then it is possible for a buffer overflow to occur. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData); + +//***************************************************************************** +// +//! Reads the data and Message ID in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param frameType is a pointer to the CAN_MsgFrameType to store the message +//! type that has been received in the mailbox +//! The \e frameType parameter shall be filled as of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! This parameter is filled when return value is true for this function. +//! \param msgID is a pointer to storage for the received Message ID +//! Filled when the return value is true for this function. +//! \param msgData is a pointer to the array to store the message data +//! Filled with read Data when the return value is true for this function. +//! +//! This function is used to read the data contents and the Message ID +//! of the specified message object in the CAN controller.The Message ID returned +//! is stored in the \e msgID parameter and its type in \e frameType parameter. +//! The data returned is stored in the \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData); + + + +//***************************************************************************** +// +//! Transfers a CAN message between the IF registers and Message RAM. +//! +//! \param base is the base address of the CAN controller. +//! \param interface is the interface to use for the transfer. Valid value are +//! 1 or 2. +//! \param objID is the object number to transfer (1-32). +//! \param direction is the direction of data transfer. False is Message RAM +//! to IF, True is IF to Message RAM. +//! +//! This function transfers the contents of the interface registers to message +//! RAM or vice versa depending on the value passed to direction. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction); + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function frees(disables) the specified message object from use. Once +//! a message object has been cleared, it will no longer automatically send or +//! receive messages, or generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables specific message object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function disables the specific message object. Once the message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableMessageObject(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables all message objects +//! +//! \param base is the base address of the CAN controller. +//! +//! This function disables all message objects. Once a message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. All message objects are disabled automatically on +//! reset, however this function can be used to restart CAN operations +//! without an external reset. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableAllMessageObjects(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CAN_H diff --git a/gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib.lib b/gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib.lib new file mode 100644 index 0000000000000000000000000000000000000000..62fb82036e184869d2ec9cad6588082d84765bf4 GIT binary patch literal 698 zcma)4%}T>S5T4yuEm6diJqfAwpdOkuX`3FTP{BZ;=%x20+a`1&T1nF4%_1K45qt%o zL3{|G$Jw;2TNLWR?0oZ+nQw;F&ck#x>1l?cuZgL6ORT=S-tNePKpUrg9;FFq{%9J< z4Fp2@Z9FxUTof|Co-@=T*skd~wrM%0jd69FENj}W)zCou00N)AH+~0F7UZ>nWf?$w zhUzN5ga-&JsQpuXh8~b(v|Ifwi*8sFrBJDAJ9~6N=_932l)h7Xhy`^vuFA_Ha3H2_e{bDFj|{ryqGa!hBY literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib_coff.lib b/gpio_bitfield_cpu1/device/driverlib/ccs/Debug/driverlib_coff.lib new file mode 100644 index 0000000000000000000000000000000000000000..04638f4ef8ef77f89abeb07d7c29154772f7d6a5 GIT binary patch literal 575952 zcmeFa3t(JToj-o=olKr>lAENZ6fDzHpipS@=!=JtcaxGd!z2x*Rwk2Vngo(eoILul zV0q})x=Ib$ML-u9sV#355myDosEEb&wX5QbW%0F(Ki6GBcikob&-Xm;{oa{LDJ$cy z``^>%-p~1-?>Xmt-jDm8bCzBdOZE+3T(~;qH#EjoP%J%#LWqA9V$lx& zU*mou{*b?CUJ&9(*Zcmgf+NEBw<G;nf{)8MOgn@E&uGzKNa$C zaG$Wv--FAAeWHJ_wg~$;e}S4>G3Q_WKSba}{vKT}0$KbEuDn3JuD`d9ir{Pgef2*? z5P!J~{`~d--8><3Pv9?aUZpth-=_;_ppArWCbKI$j*4aZ~2 z*3pT0GC4Um(K!*Dm_+czDqZIC9IdJD9hxv!CsM>Dc_Oh1&CN35@}Y^r z)qpRyZ4C&ft&R!``8_ZYPj)6IlYJCtTYa=I zF}h=Dpdm3yIop;%Da0oF29?{+Y2@Qj>(b4!YCw1w% z!fAE={Yf;fI7-p;dwDX3ob~J~JDVEn!WnY831z8;m`uhyhXzJth*eV4i=^qYCK*OU zVq`3qj5o*%25wDm9UYsT2q%VPs9d{6ROVikw;M&-8M`{(oJ@?gg;98lG?v&IPc|lY zj*95UaBBz2SqDK914?#7bNh(!5aYaTGB!N4W2jHoop3xkl<4<@fs7N$#PD!D*&vI< z1ceZc_=eOtltc&N);~!`HSq<{Nsl3aAB=jM~*ry}t3L4}(VBogC#GVO!{jE_<$>N@H8Wx1oeWDLq58+@3K zJvxM97>EsbjK!0(tXg8D{U{jDqT=He3a%UFl1O%uDBMY>mXmmG^CBJ{8Ojh>e|$%5 za(KdX3Db}_in1FSfn*34gvrrld|+rCJ)0Yxa%deLpNNf8UrTJPf2XQ_*<^fDyP$`w zigqQar>l-`j8D{0?m&m{`SQgk#aCk`3xW-pT?s~?Lo#2C;Yl~f_P+Yguvfpjb~Pts zBk|7NqkST(+~jbC!M$o72Cv50L~L_nw4N%U998{1HPv(T^qC40NsmL7aAcR;!>M3( zS$3t;-Jm+dt?e-?2h{|XFEpRXE)ukJXb3Utxz zONr&u!b!}`WN+?rQnDNLkflBMp{dKh5fdesj~Zd8@{4g*bE-*4ig(1lu@mzEko6$b zNn^GrS=-#MNYj?lzC<$FluRa)si~6vF~rbwVI3l<7{yY2bT+i6chf|KbeGdmI~+sW zh>&@nO)fGzv@JgW)oGr2f$HACPiz|PA4?34VsHQ}l5OnpGCbTs6FNV?w6!G0Ct4j$^T?@(Gzaiu&!7jM8mFF(SF;$+DuojwOpl$Ma1| zkBa4{#e`@YHRK?vl-1+}LQ^A-lG5+T$Oa~!V8i59LO0Gxe0*|*YF%f2N7u$q%m6Xc z=}eVWl7NSW%GRhhICyQN#Go*nXKgGeg7QzdeJ==?BwNYe7E?WM^G=L&BKRC20zyG}?iPk<|h@gf;n;b&?9 zI;UA3@>OaXgjWYl7V6w)^@LJtTsKdS7!k$|%@C*t$cc!_3fBSY!;C#uW3SS#QW)lJ2QFk9)4C#km49H4EeSKCB%YkggWI^2%Q39RbdF-GXA zlX1YdQ3fjQ9Hf%uV~j*H>27ghKqg zg8AxD1s6EM^b|fNO2lU_eqiY5At5&6Q-cuutPjcext4s%$2oZZ)b{KKl>+4BZ`DM6 z*MuSJcWEGn0BcB-R`sLAQk*mK*Bbub@$nS)jMjaO`f-N;X1)*<{)>wgu}8ZZ`N_Ie z)97^y{(el3DJE3w5jJ>GtOj1-2+{v0MJ&*6oc~hBp8y^Q|JOCY$tupz^QQ;=mz4?e zo8$2BVc~BFcFOU^Xo(``X*VAJA;$k!;IDu`)zn%ZkA zup-H43Fzw=2(kS%MKoE<^Z#+iekQMRXs6cJe~jp4658`iE? zVJ*WuSck2@5p0SiMgB>JdGqXjwtc;A-)P%U+V)pbQ&ef>1Xm9xM&hd{dq*e7W2-}gYkHD?COEl{YgxRlEXv2tBtEiq2}5r z#j~>%Lto$c>c)8QT2(-sjh4wp+g&MLJg}MR;~;+pvxVIkA}944($p}RadWC zx2kGYTURF>#&%;*d~hPPqVMcb)%oYIJFmL3YD1_izAH8!qTQP$hTPE!!dQllC9o$I z?-y2a6h#(|Vl9+NMx(;AqMjx2ZscfSC1tC13)rjz`b-jO>g;IS($(6rIa*a+-`XWa z8hIU&YelYPkB=vYCuu1wY>LZz-VLd}qp>O4*}8dSTT`@Yb7NDZ4ocD+TbrAkB2AmS zS}~d5r@~VEwQ_*9k5Vv=sGmwIe5{FX-qK#*6sgjococlflp=bR8eykU)}Z!CdBLQH z7Gb}PC`zXiL;WJJH<1_?mYp|_9piX^s1M6OVddscj`|4sc{|A^IzeujuO|V59+Rfz z(~K-Br~KyW#s z8!1p%3YAs)WmXvFSY};T*MesxOt>>lxW6-uXMAfHo;&C<(Aiaq*I;K?6<$N(20X8d z$k%W)@s2dobF_17J6;KFtC!gaLml1ny)<06u?gPogUjlu9ueByRM*zlaXG=$TQ_$} zzU8gW5h9$?+9cm+c9X3w+}X6Hu>)e+2iv#wRlBgrFTzVWF1~HSn1tc7g>*2AFO!W2UkWa zr5vjxRq|aEsh02cksA5FFtSFzFNv&`?}o@a`Q8{=FW;LY^%TsC&aP$zdv$YoOH180 zqI7@~ZMnR$wOh=)5F-r#_DS6v4T_fe2r3&}mbyFDp*CAt4gP9tk8Oo}(ZLJq$)Xb3 z)^;qYO}|8a8@3``yKP-b%{n$L6HonBl-Wz{8?Q|X4y0?C|J3l{yq5)#8eqB1>!I;_ z$k>fDwyIC4uU2- zZapv|X0@!wvs)Fum8mMc{^Cq8FZ6x>(x7>ywSZ=$mbKt4^{P>?OXRC!lwP9fdZ-EM ztY@VIH_<~3raYNjRtwm0Eb+kXeOMDwS9OVRRQpzqhFPOWu z!};yUZ;*T5fCjnXGAbjhB1$h&_~1OZEHR0I97c5n&Vpw4ZgKjZvs$97tn3zPmt{?* z7b*JJv9Vq~kD^Ih)U#s7K7q~8v6dmJStEW=&YS>-B-z^%DGY{?xx(y46fHxlrKql+ z6X0hL>}`n@2A2Sa-JXysGN(6r3?=?1pVmdo*3Ua})#tv2Jc{{W!+M1pKJWJ7B3H0C z(Kwarn8jK$DDKN@Eg2M#Sk~V3T9Tn0D;CS_fzDw4lF+P}5RY4r)|V8=LbLlO>Prgo z7L)ZQxn#%Nj)_M@DFum!>DoxHq+B5>%cklN96NT&Y{N5+&m23nc&a{^e5&V-GIW2)d!#S;nXWz9 zaA?_7RU+@EM*=hZt+PY3v$KawE{J`3>XE>}#p^)-IHRuu{o|mY1NuXZz6|t-Kwkp- z1B|{9^ansMOVrO$o*XVYCiCNP$+u;G94`5R%#Xt*FUA_CPwpAB>+_Btn8_6fXO<)x zo?>_x!;7aVb-Bp#hLw#gdEWhmrLgJHvFUvWn-3Ky8dfezJki~da|%847twRx0#M6c z`F^G4`=yreB`x1S#eRvj-N({)a;$lJUnJ0D-EJqu?G4jMZfUyt=>FPHP;LX|wm|n$ z>+mfNhrT>@A9A4akez5;**KjaTQ=3W|3a09YZp(w3-af`y3sB9yq?hPdW*`MQlrYF ztt7YKx^VUEtFvt-dGXNfh7|YBuKQ-`em-*#bZ-na7BnuQcXL7W62zWMdEAz3y?^Ge zd$ECW&!Sgn?|tT;uO42aTxOnXmK>Wia446Vrxs7`huo{hAZA)4A`Ubudc`Q7^Pzrxmy_Fh3YP6twJ<%5!a-(yE+t zY&d@3njc(zC=v{AwF^q@oRS{|=XXUq57EDFPy-{E*=1)23+()IyS&s6E(iv<1q=Qn zVh4+ZR%d!}UlxeV&T;I53b5Jv4s7`q5j(fE`?;X?T)KyUB@egDxJx65JLuT?Wx@G& z&Pj8lVBk_a#|k_xY{v=~+-Bz%tN(~AwwXl>Q1%WXb)Xg#-U_lg*1HKWP#E<0l2u%UKUpK?f|jbL>Hz57Lk}2g^kk@k zlc5I74K0NcN;ntK3nX^XT?w&HV|3H#@W?n~3&YzO?qT?DhVNnc*9^bHa2FC_!v8wM zKW6y13UypG|048N1%_b|LJD8#ukT~?T|YQG}99@vDx(dBW(r3^1eW*MG~ z7~aP4IKzL=@VyK_3#?>t#E%&M6~h7>NQP%2!>buy%P?&?(Y6CR;4tC0Bd=k?7XcfY zJ6s+|bTYgewa@U>GyE2YuK`x!JK}u|-@@?i4F46wM;U&IVcH+5lww+8!pF4Cp8_`W zJnQl};u{PL^V3 z24EBZ9WIX}?qv8zbX|t$c833&;qNp2GQ%Zk_{MJ~!yOEd0V~-YaUH|c4By4@QHE)e zeU45S;nQ?kJOoUW5$XqKTpmX}&G0c`BilXbcMbj=!%qXN@EzG}DIAqwOV`MFqXNkl z%^K4eD?_JEIYXy)jG@!soT0A(R`oL~RsyRsjmmz~#D(VN`bE`n{Ze0Ocu>V$9xe~M z5SNGi8W}jx$&5~`R3qEjj83u{I?1f!wZeo?#UD)gTs%ykQ#urnBN~CpjoLV2!`}jI z_}hRLk0W}3O`ky6@b?27{y~?=5qp76dn9c5_W>LJ8(khp+zM>k0%5~{2jjofwaJMae+{yiRw?ud=3rzTGb<0}=J@Fth;h+V)Y z9|-TzJk&>;KJ7=qCM|?bIDhZb{qj>?+91PmL@C}TErjzWU4%WlBPZlaW-Gji@eo#Y zM}&Y)S_qqPJh~%RfNs)4*zkCCM}}w8LSY*o!lr)!bY~B*qIC}tL8gS>xnkeGT(P`i zc^l;eK2(E}gFm8B2qd*fp&eK>Zwy(6hgt`HuJ$NvVLQ!7p_vA?o_yEWde|tJJqqP8 zwQ`SgK5W#UJW3UkMWHhags$^bAauk}fzZQ#3WTOq6u9zKAy`T~qd;g%7o$LE>XR4+ zLX*sl0--}bN;PC&=BGer$~DhdHDsn#FbZU@_fz0ylb-^aFZEL(bC;h2nYZ{UkoihK z1u|1^6uP-l1DPr9i~^Y{rHlfZ&+=0s^Ld=o+$rl6l|9uKt|>!9X~4oG#c=Hy>W4G( zFpU`MV>0njuuJIyL+v+U>0U=tya&}fGMFNPhi1~$PF9t>1iKTd4=IWhj)7e)Dr}rTU|IDE)r(sRu__L2yzz+(RzazRl$BTYlg>&M>g92RhemfK4372oCgW4C z4ZrIfpkMIm&t6hEWAVphs76?0XJWE%q|19JhlcxC#pvTg@8krc&~oh{b!$-=8{a+N zH!~*X-G+vt+L+O{Tf$0^#@2Oi`FRdh!>Rqr%=X9<(b_cC zgfxNoCx#~zf34wXeT(7G^xnsa=qz1hp*2$Y*X!m_{Tvx1zrm7-$5Q;oG_Rr2+wj-X z0C*zWTY>*XtSX?KtbMN1#ow2$eYpPy<*k5JPO`Ofl1-m9J>?`jRRzcPl#^_uoa8YX z_IUiYhM(oK;m`Em$A~YRjtR8iVbVtOL^dmi{pd-^82Jfb zM-Odip1gr3uqh@~>k)4Cpq%~og8$<^ifE$d{0}jH>hcbQ|C!_Pe~t0eobz|!f8jX% zFEM_a2|{};&2V{mZKgT@e(?W$kMd%=YtFw==NWOFioef-e@RU7(;SQp=jR&c#P%ET zZ`1sG4d>&pXW{pQ|542J|623YJdg|zpZ0EzX$H6!>wxZFMad-39>!1exk5~gr!~Ks zrSkA^W&BC-KZ!NOPc=WyZ^>}}2UGYzdI44;eTpv=zuq5|3>5zU3x)W*$t+~^s`-w)m_#FsRGru432{5!zE_hPICw z{F&^&4u7lm$TjMJ!NL#Z;#jCAAs)C&F;f1L z;r*3mgarLVi1(Lf5hpp-gY%a#{-@!5pk0V>jwrrH?Z@z+@SM#44Z0>3aMm>HX?W|C z0{$=3s4qR9M*Y*s(ZD9k*3v&i$?9LAs^6$W_ugk$eAc7jvkK@GpZ3m;(Plb_CED4A za!sK%L4(>7xsq{wK>kLmYxfv*wJD;UkPN0CHPH*JqkdDg>xytwv)+nd z)s)FgWGhtYjZm(a$kwi{#uN1EwJbP_NJ;W7NK%$Pg?gnJuk`2dMM_CAUfDhlo2Qbl zX0$$ad-}A;)a{>#H7E3IJj>~kpNkU92^Ha4PCrM=Uxl?;EEV!AltO-mR>-fgq(Xj$R>-eV3i%aUA-}?s3i%aU zA-_T?^$OnZf|__}AZc1=$)miOLzWauRIgl_ zt%bM>zSC0(q=ul>@*SgE?~xX$L^I`h)NANgvyGnuMKHNWKZ&OuKk)dv(*;CZNb_f? zUw#6f$OHDaaF&8Ry#Nj(My}?>G~MT)Sv;{i7pwsbXg8Ia$v7pfQ$lpVF5rDMYIH&UN>P?R6006+bb0R!Qzs``18iPDF zM%2#uK(%u5tZ;bzAiizJEtGsdeYt^cJy~T2*{NwKt7Xk>2jglv01F3hr?oUt3_X?;gjA zMg6Tf&_`Ef*P31hX$|A6arD*3M<`Dv$U%tryvtKL&P^rIPK&j$kDg-wvsmm?{nbB^ z_aDFm7O8NcYH3E6tk%|J*{!X=%{1Pj=Ip^_v|%`@YK6uq$<+FjUVd{8gWk_~Wf!s# zYfa?+yh$tob>ESC5-8<7ZJW6LLn=d7^L;kE`Ho*6Br}eHV>o#M=aR~c)^0Mg#R5u9l{ezn_)Fgu+0jBqz&fy1s?ve)&aG00PhtYIQK>Fo+Z2 zPET=qwWR$jUoTRYN}wgsUT1DNNM)tdR)to&S>sZx3F;ka{Ohs6|jdikbp zL|_lgU%sTxs~aU1qM01ZmF>bfIf}whLlG~f9QDl;a2E~4l&P#WPgYC(F9Nw)4gc}i z(|xPetX#=G>#k_k*EzYy!0Pu3T^9hcJ{?2J$yG&av1ghN$dzNJz;%7_hYsS-40VU^ zFwM1`Oet!q=x;5omvy1&*^sIW^7vwQ-3VOeZz@!`oa&m@GWt@MTm7#B-pMMgH@3E8 zODUe*5$n_Y>z)-wJC&hFxU%0|3n65C@vJDVOuabUgpd(4JAAy|i%@n0o)wOJyuef9 z`U83iZ`mn#%ys`zbUtiUY2?PDxqpT#1Sz1X3gL6gYHj#!mTN;<&Rn~VX(gVaRMRsb zn_T`LIjvc$k8A6QPZWLfbd}fr>d0RI?LuH-d7hCat9idTYZ}ICUbObVH}6-R;miB< z`=B!Be>z)M%izsfE`w-JrnzZ`st(fLv?g()^?#wN?!_Cifk|CU>QO$_Cfqp(cg$km z4vMu|-L)JP7qX*#ypbkD-Y&#;9eRV3e>h8Jk8eFiwUGK}IrsLtWHocPWI1z&0nmb4kw!lkNg-UD@Is=B-c*q$m}(@QA(d#Z!tomnoYJN{J4X@x4Mnw1&K$=l9^ zre=n6%KCQZpm;RP<@78or-?tPJ$b&f(w@#$<@8y+&C;Y%w?w$eUyZxl48|d=J>5^T zTr#h)l94Mz>TB@pNVlgWoyMr?s*cywdA@nc_`IKZPq$EhYZ4{DMU#+YGISwGA&d+; z$wD9%IwEGZ0CKXrX*(zu+L`9~$f?vt+6hl*unCUwS{}WZbCcLdNADdyQeTo6gY8a2 zcFJ*k`L8xEsXx-Pq$QUQT*Gg0Z^CbJrVxtVyreC+xukSR9d*`n!_4#-FS6{Gyp|=F z-JGXf|78aqf94P4eQ9BwG-RFKoLf6f$E`I_TL))uZaHxM?9uc3W@p}<8sbYCLVO}E z#8YI5b+eT^%$b?MK??D3?y~N~OIi*bo}NjQ_2<5jP5PXnmIE_iI=WvU=yq+YJinH{ z=qN*Vs2=4~fo*cBRvusXMEA^Mg=VHNIe13o-+SmFL(fkx4l%q^tknnc%`CPm^s$5o zW)|bh2bW$e$X^)_!E0XfME9lE6WwjnO&x=Hr5KjBjnjFNz|i7I?jVIaB55Tz)z%+9 zvb7|4fM}zNulT+t@$RkS@KIrR-*wt6Cv_jjuRu0VU;5#;54RqAayCB_+|fGy3nU!OWNBZh4S%HX>Xo3{C7)x{ehY3jfd*OGlwp*o8H~H#5z0B-JUCMfAV1CtqmUx zbYGf(bP-fZ->+&54EVW}WNblCG#3`;H!IF3IVsKk(x8=?U;!sP{K~@fhg)j~+Q(^4nPR zUH4AU9z1%Mb~|v-%6k^)ih!Mzvzzt8Ld@iaZr|l_XZrirSVXrTUHZlx;dvkPvpu zlH5ew^si%q$iK$^Eph3z6{+a49`8n8TL%x91be!2k1U!!t$9gAzFVHz_|+qe#gi>d zPDyxN1>m}GMVYv;TO2&H=szU4vXf05-1ya&XW(mJ%MyeO4&?K#O&`>_R^q$vStM$^ zbLqfFius z)9}@8v!+aEj{Z4Ht?<>>YnqQVqSRV&sHE3}%(&$cvNxl=Hp}w*qDyVn<@F_(vYFMH zM#w~Urqr!7py(QA>I}(9d^5!@OIr7f+e=VJd9l#!^KOVOD7lh@bVO^Z)qJ2akECmz z4#ol)0a}g(WQkL(_pGG4dh{rjs7jxVfANio{lIb3h;t#_I_aemzp2txlSap-yisXf z>4uo?G;VWa;^p`jmuk|u-KD%yX`FIH%yt^@c4OjcJnT|U8b9Vz{*W|=X8(D%<;f${ z8=q{QE;)F#xaHQ3AEef&Yx7f?!ajJMc94nxztV30pPRZjD!+3ur=Z@P_v5DqOzQ~Q zE$A22tn5uLwT1Np)HC^e0dJh)y@2e&iqQw5wQrrJK4ATE!=rXhhY9DuNN$$bX;?3Q;^&s6F5 zOiy%gv@(UCbDZ$)#Kx5yr)eZFe6{6HnHnkaU%3)DOZ#1}eRFR8lJEi5Q@0*!onDUI zTA^gjJ+irYxcLC)dX`6PIY49H3`Wc512ZcPokp~o+?E4sj9b<{v!r#Jddl2a`Mij7 z^s8>no8(+#Q%T-HX!e*(ZNey95VIpxYR|gV=INZ6xNRRDw`}jcjOIK|({?1MN4z&= zq2GQlW*i4@Vfp#%*e2GGt8q&CIJ$y-99(CD@XIRlh!mC|F`jd?1Z9}Q4D`_no+x(~mv8pWw_gP4BN$*+G(2VWc6`ylyp z{Lwjsujk-v`WT=OzV1vt+?qDR^&!z&pNLs;mw!V zC+4DcnJVEN8q!NYVg_-TRN_XW%E3tFE{_3r}n(#`S?^OAEn3h z@e}2vV51f&?|95N<{))%w+l<`U}>;uK9ZTYz$Y}F-Tr1`DX94P#~*$;Xx*RY9QXl_ zR;T~JJCpBI+dMa3@!3m*7MFt{5hxZe->5a0_xMFd5~=^@;T!{LKJC*S$S z`U#LwaV&h~~7QBdLA@RZBH4w_qE#I|k*Isjsd>Obb5wvY1cQ5xGz%ydN+20QQJGy>9xT|6+`S%Ql$NH4u^;97hlcU3Hz14;2VX;u zV6n`YGB1fIdGJJ2`+;1MWL`}RCkzn@Xv#q9-o4vGdfB(LOtyU>AD_WbgUzP?PpUX*bo`f{p5 zvXDy`+6!fQqiFqoj=V_Wx8w~?7Jf`MT|jj%a~f~Ue?8ovBkpUE^un^>$vcC2sOj~= zJjxqHa86*(~+V18yT9bk)e4R8JdHUq4^dWnp=^fc@!C%Gm%Ms)4Yca&2h-k zyo3zRUC0OO`iG^YC)KCdy|$6zp>>1A*a!`CxRXSW%i zuQ2>K41b&9PGqX#f1KfC4F8hh|6te-cz*L3p2u(*!zVF}ofbFVW`?oH;nLs2a1XF;h|iQXD`FI0;@0` zag^cDGW>Oh|Bhig!{jfuJcPf4d?$H+2yEo}XP3tjzhU_6c^=Qt8K#>@jNelju3~s2 z!`m4iWB35WcQO1J!*rK}iR%T1UuJk-fyYzL@OEI8c1Mgbd@aK_G5j%x?`N0}DEWxa zL&6`{dH4vhk?kukk0YLC_+F@I8lI;Z{u#ps__@E~S;BA?!wn2?WjM+3tqecT@Q;C& z{Eql%hOK!Xy^P`08D7J16T_D>OebC3rSpgIUQ1fS5nz+9gv;ZIafYv$@9~T>d;`OO z39Q0*#6t{!p5ZSuOlKS1t>qznM3)!c^JnDwh0EiJUo!knoc>{We#-Fg87{%EY7NgB z4A(Mz1;Yu3Z)EsG41b#8Z!r7|hUs8B6Yoh3uLD-;#oY!BZ)JFh;RM5U7Qx4KUJ*V; z=hYOjiR*yNgL_;U9&tRL>li-7@cj&bf#L5l{4Wd_mU&@f`&G;4i1QiV#PC}f9%lGP zh7T}IziB_J(@WUg#qxe&liqt>9!EUL@GUrn!|)to_;U<@o8f~Q_&u57Duz3N zm29|&gWJ2lHqa0 ze1=~EHavycP&4>6hSxFN#&9pgZ)f;sh93r2vN_@@hQGz|iwwWa@O)?l8NcNW)6Zoe z)afPsfF&*A#lS}X3tb*ZT*B~5OlS?yB@A~mJjC#RU=^1mKFIJr41b2<&ofNF(|lOV zN%*H)&ZmKm3_oyr9PvEEKVdvyz+~L;e}~~;G917J-SC{ua23O?3=aY;*&MN(;R6hR zgyD}dOuuOSgiaUXdAhzm0BmG<+U0S?F^0dvcs_}vI1K++82)>P|Bc~N{Kn4kpULpW z3}4Rh2*d9LRx&%{5X1K~{0WBX_k5q!X(U{s)A-lGMuu;?JdXG~hCh9p$MbcDf5EU7 z@_0^WxSHWG!y^p84_L|Oh`(g`A%;KC@Ru2W7Wh+wj1?w4Y)MP_YrrO5{{XCb9Pu-T zzr57r`98zHVz_9T=l4{G&ttfTVftOvr=xz4x!mP(#9J6{IGyn@d^N*= z2CTxzJxmNAW%xmc>9<3l(ee-;x1=TfD6o;|J1&nSzR&QNmwP$2>!xu4p8N)jmeh09U#}V&jn10dl7g|ojM$SJ6HZpw7<#EKl z3?Dql4kF^u#(3S=P^tg{U6kF5`MSN&o#hC&K8%)5p4{g zbFRm83By|$9%T4hhHqy02*Zy8D|sA2TI{!L*$7{#W&0ekxnJ#Bmk0M9GJNlOo@|dZ z{2Z_f(-Hr~@UI!h@>+aO#v7IAp8s6q*GsqIPqi;~Z(pV`IZrN&w*c70TLP?Pj>`MB zeg->K$mQJ=Cj25$O!!!?xqcTgI;K=E9Yc`IkFM0EzZLi+_@nS?kIjV7(@t?2*{~#X z!zpLk`pYc%HnY^O>H-0g#bLl)!FpRkLO^m;d(Yt|F-{`Lce~frlU-!q4 zSM^=liT5DO=V_MDcd&d80-N&XZH@BWlrNT9Zu#=Ib}^&ZGJf8^s7{)?F^}=^I(!nN zHvy}Da_+umuDVUKJ&eE9HvW2L2q6R`Gw(xq+vNQQg>UkT`U>Nh(rD<}_PYXcsd7C2 z9ioay-65*l+VSrYRXpkrQPoDQa1Y|5z7HnckB1qv27wiix_*XFgb6p-s z)B@kF`3W2TM#kUb@;G8U@W(ViVZ%?~hK&6EE|0n!^{D2jyHO24tyc{HK48V;h+BZ~ z)%=7FKi&Oe_-U@Kc(BI{e81)=Z1^8x{ExXjSW^Q(sQC#S{;xBB`c|cQFb4)!ZQlwL zHvBI!{(p9PaQ8485ljeuxamvmusHKUAiNF3~bssVVVoVgkNy!j(8Q=v}?lkn#V$3nYK)2 z^btw7!h~xzPlHQ$#6DotehIJBJU6&>M?4B_+ALv}UJ?GZOLs(jz-y<38+ABgm+px7 z1Dm!<*znxq(jD=)z@|MCHay>T>5e!#$7_Rxcj&lIb?J_H2e4^(gx71H>s>n11#H?H z;a1J_X_xMZSzyz?2%G$|G2t+6YAvv7Q-n=i8(g|0hJimN!?(hOSLwJCF5MBg0h_i% z*zkPFrQ@D*VAEa*U#P?Rs!R8`5n8i+Uh=4WolSe8xktYCOW3rRMZl)L5H>s>UES+! z+DnM>5LR?`ud}KrY8*G=tN@Rqt9zZzSXs%!A*|?*yp!6rmko@Eu%cs30XFT0u!+l~ zJE8@2(_RQ09*^!wod?ri!iR+5;75dBdm(J%^5_`vKsW7$u;KCOXyc%pF^jO_@#v1&54veDgbj~Jcf>)^O?x41 zcs#ngL*2BOTNw{w(_ZcbHtmJ53CE*5;t1%by%07$9vx#b=%&38Has5Pkq2^`_VO6x zA*|@Uy_mZp;V5s~qIWKC;q~qgFOd{;FF1_?WiACkETsobp6jayHd--wcZaWmjbimE zYheqy6aYcK$k08(Dt795C>-xz@b$1!>>gzUY-hO?0C{&dz3DDt70&svQ8?Z`+;rnO zg~KRSLacNt0HTi`FokY7RY-h+q?p{Og3u?s6ylzs2TYOY3yG)L)ot1GMs_5ga)VKj z)FM#kVTVKKJd#=p%6yN4q%QDNkT6=cdpvY2`Eox6>AJvAK`JitQ;-T;*|TsUbDN(6 znQ3KN?8;LOnMoc-fy|T}i~^bQ`GHd)Gwo7%Jaj8L_4|whnW^j<1u|3ql(@0iKxT@a zQ6Mwr2BSdcWqt~Rg#erfGB^4ukhubsQZFuep>%naHISL+D2xJ`SNJKA`D{N0GD9Tp z3o?^DEF3V@`YDjP!B2tAEq)4Q-r}bq*eiXMwUBw(Pl3$4{1nLiK|cjD(@5hXYSqGVW z{1nJc@|3yqtb@!X52HY4l7~?sGs(j!keTFR6v#~Sc$D>!ndD&<$lT+nAP|zL+?8iN zWF~nS1u~O7i~^ZS9!7!8BoCuNW|D_dAT!CsD3H0wN7(?GNuCNfrIbUq|Q!o(Hn0vC9 z_UbBG!#SlI`RC`Uk-s$JJZoe)i&;2pWjLI&PKLuN>t#5cvO$J(3Jd3a^boXycS{EY zAu66nY3^*JGNx9ic|fU_ZCO$H4b(RH`0d8hBOd(L>A+k(?563QId~|%>*xWKi@$)i zK;qQLt(uT0d6wZxlKIU;+Dfz6fJJpHo#$(shvr)Wi}n@Ld0x^yw2K?CPSH01%j5~o z9s(Bi1(XYZV{Un-8WXUnj|=)4V51#9GBgJYSTQ{H+?$BnnA@DG?+94^coMhYm>Zm_ z=L%TOc&5i?Zf!1=Jm1HYa?@|jP0bF-0V|0o<$~Xs+nK4J&Ba4IbY!S^n~TTX!c2W@ zzG_C}!9e7er@*8u*GPTTr)qrPu{`Bgqut@SyIO%bj zo0O@K4p``{GlXMqPnNY}4jyx3GSw~>PI~<@wBii89D-B8dKyof;rh)Ios5N8r`R$S%16Ih zt$Ao>rFf{G`Ax0np;@=$Y4$U~woUU;zp8ksJp5)@^Uy41uDEW{JjJfe)W-bg1Dc2W z)w$yOgyx|ctm2_I<~KM)KpN`9=L+X1nuk_xiic`|-@L4OXuhF%sBQR7Id!@)wEj{& zF-2g{(=`u`?~12^xhi;p=AqG3@uZh&hvuQ#sp3g5(;b?J=30t}+PvRfr+EaGg><^f zN1+|XuGXq}byNMNRqf6CcsX`iY5Mu5X%u~)W;$J+-ze$)*n3GZN7%{1@d8C+(K0eW z+EdIy*CNd2ssv%KTpUKuBovO?Yftn~4##=i?ABH0T~YPTl#HJ7EzR}9=yFESc)WJHd;0Ou ztKxl$(ea53R*g?2heii5!HV}z4n&8CMp2Lo4~_0f7#!>EO~$8OTQW8}5Fb~qfu~f~ zQwDNj$C;ZLnH+?W5va_K^KTUTTq!f1cSLN?(; z9(k>>w6jdmju+%QklJkpGHfb}91m-pQfi{#CIFlwa@U1WH2}o4VYu zux~iF3MXH$4rx=hetk`4_4>-nnoy`x()cqJT66w7xRB{7dL^VD*+=v(FhxJCcxjMPlZLO)^I?}&x3NdatbEVpVEPtfd!|WxwGzb8ULNY zQSkpPl^=97OK)WScL2}QBt6A&`6J9N1bjQvdJ;{xVa$xw@Ym52rmIz0%gC{Ad^|qV zOLrsZpH!GP&)#R-*W;8|+kVov??uk32|-RETjxWd`u35O!p>FZ%p^Y`6hSd!#SB4rA{qceLXlTpm(5}!_b@i%stEyJDb#=mFY7X@i=py+pD zm7!&bv~Jwk6p40rGcnQh{$MbjHHa#)ZJx7_Net$ zMsh~07I`W)j8-G^(`ai%K^l!>DNLm{REeTA8uqBtXfxq0$8hHbeSEiBAC-S*z0FggmkC|%qjw>QO3|1`s}fCVv})1pqqS4H)rpOMVnh;K{6ylc7p;CGan_4X zK4MctU08~LX&PBd-HRCvd|g|H{f|yM81Zb ziFc%to}-;x+wn?-@w5+yI=bb1X}E4<6TI68m({g*G&T|1+*H@r)^Rz((^2q}Z+UBT zga~J}Hp%yy-DGPEcQ$Ql?0{JI!S?PB60)l+$M?6>t0C%1EV@V|AoT zzH1`Y^1VJ%Bi|QB*2woIk+t&O5LqYR8zbxGdsC#If?3ho)r?@TZVqp0soO@B4p5>k zmp8U{i@XOg6Qo%NmgrroUUnuXlYMbHbE63}Zr;k|oUJ*XoHbTu?P5$B{N?f{wh3=u zMYFmnv)k5XSd_^|N|UXqvE<|I{_$jAXMC70a5)W4BkEb-nF~_NKQiBv>)$f zQ?qvcfyVPL?A|gv^W?G5H=b92p#FyD;tRWHo;mi_FD_X;MMrxsN06kR`g)E=qj_%81jINAXNgn(ILFz!%L(texhfpM6n`XG(6=ubjGcGvXF==iV#UyLd}Zd&oTTiR9wSD z$FUfE4#NfbenKC%P>x~3cf&tSxDeQ=FrV)7IN~gZOCXFJCc{k(#~8kr;oBHK0<2_E zs*6UR6%a&kV~1&xZRDv0HvE7(7wzyhF5Qy&baF&m_TiCCQrM%b z6}Ks|S7&jAkB}-@_5ZQ3vDq3EZS%>n=2kqqlT1o0gL*CbYr$JP;tN$ z!jnSuo0zszj;U>azubr5jxGHDZB5-9N3n%(c1JS}OaH}P&`d$S_WoS&>)M~Isyu(g zT6cdA`smo7`@wP{E|$qR`*YK(2};^Ic+%-rsm4@MUbzepol=!*LYlxUn&HXBUu*bT zr8E4Q-uoD_oXLL``YsCpCHk-llTa^NNvZOYX;m-zq;H$gl`(>bp<0jD<3XuaQc7(t z#c=*T%xx9$x!@0l6pf6Msk3-G%1b}N4gWY|8+%IhT% z@54v&F&)0{eg)s}%wzmN0>1SmA)Z{OLZk2LWK8`etbdtLP@D<=Df$qeVmLqj^23-g zz#XVNPoJ(Rh)Np6Uw1aFC$!(W12s|QR!%T$GuPh#efypB=|?u+eZ7{&zF!2sU?WpI z@DSFYfz2wwN;%rlh1HTU5W9~CV$+fKO2Lts9L0^ttj1d|tMR5~HC}RA?YPToP}s7%@LbHksj}l6?T(=VUFF*nvHteh zMBkw7#b|V)#r2#_S?#DQvv%YCF!h6%SyQ-aus1dy7t}1G64}=FKGpbf%RF@%$R61j zsC(=uu!YpG*d@Zps^kb|SCt}a4Dy(S)r?#%im`}Ji4UaRUJNM_mdUK=m;TZKVU@8S zjwY=jP!UNTjaKTnB#ItQ=QB%OXqZEc-gRZodb$#_5vRX&CX19*^dsk3D2~wDkE={EFeNTtznRvIjBT#1@bbJrhY0jWzA9!S zXSX2UJ7+eLq7McCgQFvXVPJnN#@>R znNP+-mC<0IL%D3oV%`weag<>x!!czTE$%Z7)mhD~-)1?pY<7jPSEDck+LJMx;IL~d zHaw{(T?%Gs;pxpdZ4hH~pP}(OUOQz`@bQjz7_9R1=!vau+^&Ut-YV&C;`)-}81S0< zl0tfKs4vN-_eJ$-_Y{+_OKkDDfFFC%dh}yA+cE3$!_(=vgZ(>hxD@g()Mj?$=I>qV zvZ-d=Cup;qJe$@fP}c^Aa1UKNqti-@qMlKZz}#qPyD;sc=t}}ofe6O$r-3`{!eDBt`Tb^ntB=_G8(v57zI&bK9vYb~NkC@xg zRCpsYyn31D#sf3ROA(Ma$34|}!{1WQx;EUOD)CQdX5bc@&6T#7VapuyjWT3}CvW3z zykREyi>N8c4ctpdw!ei9xvXtJfem@1Z7(nRQ@l%U7{9UmQ@u+~$=-)XjVn`I|=)Zaj zPQQ~*@-m&0a~^&4n?dUwpKp2N4tDoxPnTQ~2WR+WUcqDT zuSvfPhh4yPyt{DN1w1CK^jmu7r`&~8?E4a3qP|3zn!9iu?~`;HeUf(X!YSt;sM}Ci zXga_@3sQR~Lv5D~wNozoMGD5I!nty_&r*NJ-{aX_qsedGmBxmC&uvH!0>GhKg{qqfK^048N7(K8C6LQ2C?IFkLBSR%b51S!0N%(-oBpCx(ZXV}>UHY{Eg4k|zsc znJj-dZFp!eTge%fXH*zWZ-c467)*Q82GcII!L;vea5Ka04D)oM3vuN^Q+Qo6Q`%K~ zkIL`5ua(9X;8#4yKigFCsIyH?oos|(qlnZ3Z0boHu&Gx)z$)#>KigFCsIyJYc(E6L zP5AqOP53tgn|}3HVAFpRHvD%m{ySYBb+)PL>mFhJk1_tw0-HYS>%gY}A#B3`Hsk-U z%fpqS)LD=wZ+{3LJy!@n4{Y-Dcfck;2^*f@yL3m8=7`Bd!Yb_|Os66!I>s`WZiNYx zvK3626yi)?4Fa3IB3z?+u6F5;xEO`Z@o z;dpd)-k-^n4UC7dsVB9-CQk^Pa6CHClh;1ejruC3C`Zb4RGO4}MFB8*j-Nv9+o#m) zs5B{7?*z9suwls26aaa83BA1&+}6T|p#l`6rne3@(kJmK)Rz&DcNQC^9GyF(oDbV_ zAB9eEyTDJWLP7f}NLaU@f@F})g|0kRNCv4sF$#pH`oSm=nj~cBwLxg2xaYOGXSKLz zsJUmgC<@mZquw}^A|clk3(UpCbi**2%@_{Iu6`G_j=9c8=^;j#Jp2VL%JFowN0X@R z1J)`$DMY`yMO$e!30Sl?p}g^%N3|7`Ch$R$1QfIzU3jO8gxk&q@R-lwI%^J_++p2k}9x9&mJV%YF=Osg@7AhXqhbXFg?$SKoxfPU;enVgF zl|eY-Vc6(2hq1(P)sBWp`u8LKLCLpao$0H9Yz8=$A?4eYkL(MCxukr2U@miLdvFf# z(>bHEZ@`S|eUE&De(R6K&LN?fMe4(-w6pK1((cK_K6byRmh8yb_&C#(eXU=ypI^OZ zLr5C>6?=))lKmnMtD)Xm2%{x?rCTf1Uc*nRD@!rd5~#P3IhyL0-dIIQ^YGr!cq`4o zUu*bTPiXivz4tNVvkX6j?t#KTPd7%>-i-XjdOG8$dH!?cm|{Y;9^oPn%5!`x(d4ht zlP>B-$Z-B`iX@*j>fH(c4;+VoC*vo1N-=bOL-U)g;^BXg@wWi)0RPLHpL%^Vod01( zlFulfuh7t#Vrp3(7-RSm@I8V>4c+BNrb4}ZTCAVfGG&hP@t)4FP3Vj#Zv9GSgM^COSRKtsdic{)lQ2^?X*~_ofa##(_*Q1TCCJg zi>2CWu~a)PR%)lkQth-@tDWMl)lPx5+9{AxI|Wo~rvOsz6mO|^iZ|3w@pRQrfu-7M zu~IuN)@rB4O6{~*tDP1rwbNp)c3P~|PK&kLX|Yl}E!JwM#Y*k8SgV~DE49;Nt#(?h z)J}`F+9~3fYNvQhwNt#M+9}>r?G$gRc8a%DJH=b7o#HLkPVpwSQ@o_wX|bzz3JOy@ z&5vMG+|VBG?9>B&^UyF<7F%%Ag>2E(wL{k_Geeepl1 zgI>HKU6T??rij6|_cdY$%iELj0cZw6twV<4+Ddd$a_uTwsaPd!f<}uNAAzPBRw>P= zERla5W=QGvp$&OJX0G}|?pdxbTeJ2PU|n5y{$F*0s@dzTE?cl{=GCQ*)U!KAan?xZ z6`LDmouTQVzmG{_%5uedN46`@UDlqA{mdYG*{0DL9e%I}LuQoO(Z38Qc5+A0I!EWh ze5Zy+ordRMx_Z_V?-NRCv5hX^qu9dWWg0<$DNB+j>i&|HPFXI$d$V1BKbWKZMq;}t zeduUaH_PlOzy5e%GEPTAx$Zs+#)sYg@!{BR=B#aS+BLRwq;vOZUuUvUh0W|VvP_Q0 zb<~}M{X13lNukYAO_-2!Y+!b(CO#P@gO76Jm4%NeSX=o=6k2Fmr5ouf3ci9ximFb0 zSc04U*duFex^q_R)S!4iyLD<%ykzZ7?-McPm9U52-KtJ0zj;av!OE#A3!_uy^Egilj4_tnO08uoI1KCEh`)?MRt>&>%w%zo&} z*&|)KL!?1@fuV1oy(7?lH0S94>wXaE{%FDBXPOQzn_46_?`DpbJlXWj(f!(XZNvVP z75!RultiZZdQ7+}@x=^1V|)vJ@o5|4JINOxv=!6RccTm!`kK>uv4G-Uj6ME@#*2PG z+sIsSpqcA3`}@UHT2nDC)Q4rL8&8=%P36|drM+c35StfKluzh*>kqtm?C)of?r*ty z_Cta0Bi7+(UOd!_7<05NwU9;QMNiBwo@&?+9ZzUA&RpBLzgVM<`xj{Rr>NyPg4>eD z@o$y9KVUf;I(@->J;#gCltF3X?Hx+h-lHj~a@#fadfdD)_oRhM1Dn?Rvzrkp{pLO( zz5}X-4(yMk^(SYca#fbqzEADsct@r@PkM17DDxHCXIbfLbJcKNAAQI8qFomSt&`H- zzekF9$77f!hPC~Rf(1)A27`6#_2!IW-AAIVjdu5(5-1qZjHg_3Nzl4b#cKtHT^Puh zI&#>c2?{!;B~T)2y5Dj<}oQ_v0(8;W^6iml*yL!@p&C0hW=*?*`zI zj;od74u)yjxlHm{VZ!uN7?^N3unFgCm&XwahA%7fc!n5$H^X!WkqPIE4F8fXFdPR~aynv);Xh;eR)#;!FfGFt>ogKRLzl(fz(ytLGcJ!Ko?!S3z(%&aG5j6bx4CWy@u}QK^yu9RrxC{A^$)84-=lEA!n|`AQ{H9MJY{KscHf1;H@+kGM5bV^4?8VdY?*lgc zHv)(7M<0xC#naS(!iN72V8ef>%cDLp<-m>+CH(hznzR$vU!lS;x^!G=3#`Jl!h}Qk zg9&3gr0I@W0&LPqc&X-D>e3x?32;c#tuW!0ny22SJK`!}lNQ3~YMv37?w23kr(2(? z+)Y{t=WD+n-H{4JCM}B?4`D@DYE>pJA;v>k(Un>i*{O`E&X~9ehww+`Qi-QY3t_|K z(Ro^4TOH~QgyC0*qS!o24Qyz}Daub&>pgWSQgtF8PqB$w0r7Yg+WaLRzpB$hALV@5 z=nJjKL#j@v`zckbY#2|q3YjS_L1_9~$|!4;Jd6UNDc>0dLL+cafzXr^m&a9gQtD9r zGrtYKY%4ZVPLQGc8L)IsmlW@Dk%kz$!LtEROhQu3Hf^W6GZ)WJ&4VFS#}&{N@AW|q zG4z3_1y73AZywfG3~S(_59{gX^O{8UBVf_T@zOM=XElXV6R=2u;fge#?`aCDa|JB= zXr69YA!#c9w(*t$Qb>{?*Z9_#(daq8gHp_4-|KwdxN93ezGQGr*=5hb zA$M=zAXOsv2{9$&44)TC;tXW@S<*+B60&bsuc2JjH#RvjG!jo5^`h6(Em~Vytq$Om zH)PC{x<&V(cB>)L=oWpAmG?Qo-PD_;7-|yKU}Y|+xIs-V&4e^1lWtKa{#wKTU(hXj zhxSXax1$fB@SmdA46|IlT-_70o~dc{qKV$`sh3GHp<0hn??L&ygR{}&B&h|%m~M&l z_bDg&?8TEN_Nk`UZB#-$&m4Pz%h6jM(&1B{lPR@T{u3Ujhc<6QIOE`dMf003(3BUk zy~i-)T?l^qElR54{H9|io)!3`-3h_GG&n^o8l-qO|Dj%zZS+PAdTb+vYErgOogon0N_y5_E?$mXW4 zU5!l*k*4-0914%K>yE?UwXG@Afi0T3m?B#?H%FS9sAl9+IMh8wn?@#wV-rJ(QCv@i zlhH}||E^>2wjp2Gv3I25b7IHdO&gC&)95ba(P$cZ2h)+BlF>9efdlU5Bc%L%lvz$_ zKAv7U|98OM|KJ1eidr%6bt^aykN4Mc>Kkccj?c%Y5v1{CYv0@J^|E)yofpRi-f>IR z=eP&mjZjmk{wFGtdkBli1kyDrTsW7-WEY=7qFMM)7^4x?Dkq&-OU&DYktCxxILiTj z5&UNkINL=qDBhQ~6PHX842o%MuQ_Ybm%Hj5H;+_K3tW_lKB8ux`uJKH3(e-wQy*1J z@wQVws^+|!`bo7~e)^*if3yGEfX{t@iXZL9#H5%ILt;e4Me+~$bVn0L{poH?>gPG? z0Q6_J%gF6y!uBaQ9P+@Bz!TdoYMby z1f3;eaFpRV!#GFE<=F`#4F9_reu!Z@55n*ipqn+gnBfYBpMb!$A%Z3lCVT+#!Gxa# zHhzEP^5Ef9 zGf=g$DThaj;d>aU+L?LSz6Iq?rf?|OGwA_C`4+HDE0-kqQLhoI5_qTwpjiE;Pg^Pf z0#>izQQOA#nXOf$(;x3o$58?-%W;!X?y z#5eZ}`(u4(V=qMJHFx)FD%VR!w!3!=8pKkWhh}&0Q8!1`F9-kBcK1e^{5PO}((c|0 z)rGjHF0tN5r(SuY_7%vm`xdJ80_7X$mxEjd{*dab-8#(qBc50BR^T6J2)~xKk*67d z5AX-kjP|93&v*BDTV8~4{tf)kYkt#yd3yJ-@P7sD=$%hS_U(S|XAUa}BQMvePS;JZ z3ID`*_uc`~R4Cv7QOL%Ee}o3xZtRB~@ZZ-*v@f#p%Z5i`9{YN9mgv&fR}L;6|W5Bd!Dt{ zyZ5`#IZ5jbhxzpXR-3b*{jO(S_F8MNwf4HaOC_}B#YOOM4|W17((mwY^~6QhHe>Wi z9{a+v&3NoY#spj{5mdK#opch9=Vb3QX5C6b&BgpR6*r=lVb<#qU}L|Q?_t105hQbho9&S%pUWD za%1)+pXe~RK8-xtWA+^R?9A#T$6r4&ZQvt0(gW*DH`DjEep5kY-+J&qxO(2zDbFG2Cs#*#@);vRt=?IGf>9 zf04!*S^v2)#<2tkATxLiLj}Gs%~F2WS%ZA-iuiW<@7r)>@n*k_|I_&+i(JCLyk}cO z)7ySL=Z&dg?*A_r)3e@01qj0$*BO5O(6Gp8;}~uX(TxE)-L$NUIfi&1ij;GkHq=ck znB$3p|3P6cq82$%853NB2njx0;a4eqjly>*e7C~yRd@{|?><(7Eb&~}!DQD0OIQOT z2hXK&Ck8o$GpO*J6uwX4e^U6D3eQFF#Kj?PPE&Y=!W{}+q|LPf$NmT}C- zLwVZ#8d&@%UVuNC?CFTyMYd7Zicl~f@ZZ}wob3UnFoZ-&`pJRW>xM%<9c0KSJj(aYx zt6OXbIQ1{aMVBsJ1}hk9Ov{*0;auTwEiz_oZYx*MLd_wplew@n`r z$`vg~uBr0^JtGiu3h*0+uVx2AegSYm$^1;2m2}O<1^y48=m>{BPvXzp6<)>*y-c8%6KxG_8+kM zhH2UJPs>9=WD#tZ!@=PD*C%g3D11 zy=Uv2)~xPYEWz2kFd%yu24U}(n4}BP-YqpH>h2tq3h!DMo6_i}-junUmeoy|7IE={ z4_L*z3rcPh-)5vXqPY1;b+xs0uUp^KB+>Hs%{lfh^7P)mRU+r_+a!AazFi{d?^jA3 z{e6c-)8BWRau;oXf1#;}-LEp0vHR6#TI_y}nI5}ei>*@b*}De%$A(8t;%a8ZgVBR$ z*RSiwv$vt=?p$tI8;N}4bgpe#w|+fXJuDUYICWmOZERb&V_TTducfCyk9=-l-PN|n zx(Ks367fWBiP-kOorA+81D6f&K*o&2gR*PTK$e%_WnDFJ&0-TIPBbjRJtFWn@HTN` zLfOQz^?y3-21q3ghH;F?w$u|4Q-J-42VlvO+rUT2@F`h%Uy8P#2?(OkJpp zan>i9V2{DORNcSEV&PXvXRI#9jMc@MvAP&DRu^N&>SD}TU5pv(V$3*Qj2WkkF=KTx zW}Gg@jMc@MvAP&DP8Vaw>SD}zU5vPTU5r3p7bB49Vgz)$7y+y zMqsOpG2?VGX1p%OjMK%K@wyl@P8Vaw>tf6}U5pv8i!tM7Z8Cm^bjImo%y?al8K;Xe z<8?7+oG!+U*TsnNtu97ftu97ftu97ftu97ftu97ftu97ftu97ftu97fsf!U8tBWxc z>SBaM>0+#UHTKciw_?|hZNvRn@zt!y3u0SN_82j3!)7GMwpfFRuGKD@5=P%E7!AgF z=I?0BnpRc-_oL+Ygm-DENeplDtoCmk+HqBO7%$wwh^wl!0B-l~8{O2*1I2C4BR8T3+s{U(@w8GlXH&nxq?tYOM5v$n;} zvey-DTE!KKPybP8*^C=8$Y9^2tpj8B6>HztH#&%B)pwovy7BwQw%6{Bn}k{1Y#c9g zHh$OcLl|{E6n4sbJjR=FePQu+p(0W0Siv-^S27A0*N(c5Cp$Sk9@mDcXOq}8G;^TJUjShS0FoLyy9lY(?!mV=WJ$Ra|ip$?6z|g2r-iOI-i`j z7W0@XUVyFZDUQ|!Q5GPvY|^8`LegVw07*anb_~<%q;ELpcOjQq+~iLNMNa>h2mhD6 z4bx{}^gEU%u~Lp~vx6!5Z$m?jSKRD4x!BpU!evK+68>L*A2{w(;C)7FATDzA! zykkNa?h6)3X!~V^d6pMi4)Z|y*2AgW#-3?CYrJ&9#pYef+neV%A9CtbTVONt%y?<@ ze8+1&s~Mc+?X<0Yq51x@+v*Oq-~X~i$9$8xaDH=XX>YWWDs`KI%hve~6Rq=Whg(a{ z?f1_$2R2Sr^akK|lrEXbOeFWV&o3Je5=|F(nAXz8U|v|7?CmK1QGa=&ovKvfzA{A9 zLsS)_=F-}}X7EzC)jTskzxm)}Kr=0R5-4NQvp}+Uet7yDS3ywG%*>(7GqC4Ha0xFu0BoVsoPGvkMv4>z5)X(G72<#0=w zV^!;2F8t6wPs<^3mq;|vr@OjmTFx3jL{~?uqMUaACzStJPU?SIZ{5VH0dtyuyAbG7 zLg+0R0?X3QXPWO{u)F!-k$L6=(~wH$ch4D*@sL&@8Zoch7i2dk64!MhT}=3S;M z(HDH?KKoRO7b2JA3(W`U&fGQr_T<}4SB!txjemqI==!l1Z~K2^4IQVF{9fF(x%+fk zReHNMxpo|=lJ#|$!jg+S#7t$!Pj2t$`dmNRJM(sz<=RcA|3)Eszl@$+|GlBzf-HRD^Ce19x8Ejcur zO8w2pKmPGgq$;{_Nd=$C_ux5b0-pWf@?o5d95<#a?%4OvRO+3%4`5^YG%4$orO%}* zKCv&AN|e_Wq`f|IRG&UT%KAk4tf_taJZQ&lNTqh2bH_QUAd#-lfAH^rB`>1gQT6FPVw?+=XXW4^SjdR{GKKozSU0d3#LbV zxl?awoc6}X@;5c6Zf>0Rjz$dH_`TfeU}m6+`Pz@GA|=UFZ6U9YXj27SlcP&H9n+;e z)9F&4b>N1;>T%9Qx|C~Ux|C;YUCNvB7T_g^!2q;3tO03Q+tIN0qLC|W9vWG9AosGa zfHe#aYZGl;2yXdkqqTsJOI%;+@e1_wU+wY53cp6-K83l9Nci7Tn41tp&KgYc7JSzU zzDnVT6#jz3rHHWbrz!k$h0j&^B89I~_%?;#q3}BueviWMSNMp+C*%8D;TS;r$^eZSGh2HjFq3=K+NuR`@A}pI3Me zrh>$61F%~+gCmy}=5&!;UlL@AC2ki0i`z>=PTIUi;bsg23g-%iU#IY$3jd|Tk0|^U zu!}?5{JX-O7jbJ-f-Ldde7gMtSi+r&p%=$Vo7oB<4=kKA4Au*#4rRgTDx6iAI+VrF z{R(r?AFCf=f-Ldte0*LHEPnoZ$bsH!g&$Cycc9u6{(}lrU7pCl3GBj3o1ZKE8-+RM z&CT|V5AoZ5d|m(+f9B(R%5lM2DKMyL*f#9V+KE&7h z_`D5R{QpSENt=%<{Bgy3KPpY(e^TMED*R($7gpK?80{2XrZ7iAm-+Y*U*zLc1uXub z9&*y=Y=xI7&hZ$~6aG?#*C@OZ*oBog8~}6+XoD>AVjpgg;$Itb(&h$*->5iyFzzMc z-VE&gOdF1eo#LO1m~}c#_BO?TU&u+D4=Vhi;=BcojrjjTg+Hh8zbO1~z%Jah;TY3G z9|z(gABP_U%Tn`FtY3GWw5e3M3RuGZt-|Tqk^FRp8x>v+EPis-b%l*Xk5y;U?eS!C zw$09Mk8PpFEvj21Zc(-PXY8?Ux$sLN7k;_oGc1=TPK}7<3*GrPJx|}aq+u&K&i|?P zeLGIt^n!mn{`kK4;#d6N3@m9r2<$jc-}jlgCx1VFg?|88_%{JNj??$;>b)R)r{dqO z`1b-kPTKqp@M8SYe`4|fK7U=rEy;aBpS z*e}k^J`u{Desjs+7a%_#e=t_Rx#TIeQ%Rl@H+jy>Lb+2RB>BkgKh2(V1+e7Z-N2G} z#3y>rdqO#M_XE4UfEpm+Q$6SNp*(G#29`V`7Jq&e%G0I-FOuX7vG_ARltV{3u;c}? z__HLGr!kBYr9ZK7s2s!POFYd>5nrh{YJesEiOc=7L~^%1MACn*;t)&v*8xlV6N^8Q z-05VO^rt)F5KHk!DJTI^tK?BhutJ9q~3b5NUFh1d%>2E`NpAwn9vWxcRZaosR2d{>WwtbpOHO z2tvL;vO%KCa^~YV-^iv2rp#m;#AG7`Q#cu1nePcCvYCM;CK+%$gKS}l=(52EpUdEI zi_PK4(j(dAFw1hd%^}~s-%FXo$zTw_b$KNJZEN4Dymv zcr^b5Is99}Up58*p&b5SgMZl+{BJ8hJ2Kw@|GFvozg2v846E?--YNLARC=NxWHy5T z51!Ai1dV>)(-r@fu=@w_=bdk9;Vx*+Z&mzu&|Z!2n;lc|`6(#o9)L%{|GeiHO8=dT ze+c}Ng~mMX`RoqR==i)@@jnT>g{N6c?59z2HYOsg%OQU^zN_BK2ZwQ=N$8}5!}o>e zoyzU^Apbr3;_r6fccLl4e?U0?Un%}ufdAEfZ#hfxk;CpRqH4 zLR%fvJ;;v9wmNpBTbq1}{omksc$KhuZB0{8_xjG2D{+2C*ShxZOPbcVahsbGH?_7j z+3jgLGP?&cM`m{-=E&@R#2i`M#ogTY7ne5IbL(G@tbyDAa%4-m1u#dpl-mGvWDEtH z0prq^dTt2Jku`8rV2*5wnUN=3YO3;N45d0(+FEaF@?;GrohMsjX6DJ3;!vEN*t9Z~ zOia45b8UCMd3m0!!OYK-EitdilPxuMd9riN2{Bn)_L4RAUF%w!%t;01&F17hd4uJj zQc&J(PR)}qvHXPv<;~`_Jo!?~KfR#5*_@FlKgaUVEGTa_XXVM4S^n7t<;`YMp8Q

2T-rX$~`*}3T~ zWMkc27_;eWZC_L0z8Y^-PeFNu=`AQn%h=(u3g)?cBOBtytr*`s|lP3 zojb76aAeocu{HKkrfKk@>{}QddRfWXNZ*c8D4LWYxObY3VNb3_iQTLi`T?Ge2)7U` zuS*7Y^q~tAhG%zNpNDp~C)c9H9rM>Uv~R#}zGgezqhw*sY?QeP+cG3tR$4MLFtlUH zJro$_mZ4-Nn|6(ij!6)e);bb}AqZi5ECeep86D}rWTbDWP^v6N3rjW+jE-qajitn- zmcuOweA1bry_GNovC4?=p-r=WfU$v{bUFK4rV;p&)cPFVf;7jH7*S#UVm-=d zhUK%8i!M@izrpV;yMaEFKoV4z<0n-&1HVPtQ13RzJ4MJ_5C}KMySwcSGTaysu?fmz z+wE^5J=$*nF7o|$`^a6P4fTI74&8?O$Hd`(cSC&?s%)UIgV&W8;+0I*t;27v-B4d^ zH`LeK4fVBlLw&8?P+w~|)Yo!DeXZM2U+Xs1*V+yBwQfUwt=&*xYd6%_x()TUc0+xw z-%yXM-%t>hT+Hs0X$i>TBJG`dYuCzSeE1uk{=1 zYu$$WTEC&b)@`V-^&9GI-G=&FzoEX?ZK$vH8|rJ_hWc8+p}y8_sIT=K>Jh%(P>-wK zP>-wKP>-wKP>-wKP>-wKP>-wKP>-wKP>(A&)Z=0|)Ypa^>LJk^>hHxcIIDhFBeFgi zz~|wp{XWANJvY=Bur1a;5Bq6Yv=hcSkk)Tj27BdXD_ad(rN-D`&#KJUhg@{k6W%3) zE2ZYN7U2yxd|9WFCo`cUIdm8I1y=h)m-Jt5X4~}D%7#mr>a*4GAm}ETgW(>uvQ@h< zVHV|xt$JZ$pl3FoSI(xW`LwoZ+K_BM^+$)mMM;c&8f8oVA)AIoE`MxmBkh8{!HC8+ z%#6q;yhCOb$hvEDJZ5epmm>FabF5jW^N>>?u}nRcf;pIiWTp;c?kCDrY5ZX4R=nzW zFtjXc*1op5S$loKtcB8vG3h)oXKk*>B+UInIf60}W^UN>+l-qms|)$U44=fC|4No~ z-Z+-!3n`exAxUKU7_6f#XDL`GyQt3Scx*CWw39@ zj)85kGKMn>IxobosM&E^P~7|&4zO$?$QH^Eeysbir2j+``LA>@K^E-GaRiaCyeD;a z44GkjI=b0Bi^=XB=5|oAGAC~3dORJu;;_Nom}_I}*6q1c`<7iBN!@sY3|kzCEO25- zIQ(E8y(zNG9fUX-S#2H~jgMTsm3DL9#$QwY?s={R>JA}n?2M%y-eB?6mPIUpgXR^* z+i;C8-XNB!2H`2QQ6I0s8$O2Uftt@l0U?arKPtO2@5=nmo4@IeG3p*5t{5 zwJ_mWsGj3mB_!iwtg>N2$}Og_%}vO#h!<^>r7Z~$CyJ)M#`^!Y#4(n%KQt+?#bP8T zW!`HYOUpdlqL#~lD{^8!Q>?`N8D^iEn0Zwz6BDn#d&Bc=i<+2MCW~7#$C3qm$id~? zIfTwJcz4)&fm#tFci4Hv$}hfoJsvllfOZBofj_ppuErhPJ-e@NqOqpAdM2*DxK`nM z0M|-f@5Qwg*N1RTj&J8`{Z=>xsX#KGkbOPLvGeI(OpvdAq4Nqx6OLdt2|9xRyd?#+7E7 zKOU%kye831#TTD%AD`(_>-gLd>s9?l;1xk{4R9jUQotrRnx+ACi4_>r02|_XaCz zJ#^%F^USo(M~r~KX$nJVC$hL@w@WSPoSv5sRPLm zZKrh=+-A&?`#Y*jx6-GpeGGJXE_5BA^=FtI@I&U^UhZcvj2F z55S)XA9>(Qj?-&7NpN~=x`ydbOVx)K&NUCfr}Hn4cn2)61iS+^7a%@&hVcRV)xFj> z1>1XT7Tb{S%!v@7{gYHJk6N9>;rE2Yf58jkw-{YcH<%^;Hb> z&AhMrAMKlYU-eh1l4b71N1G3J92&pVq`b z@u}+C-j0LM%6-YNs%P|;CpxSun5sUD$SeOsbs5518u~HQax(mV{rJK5(l5N8KF`7Z z2j~Cep{B!?)_%6LzZ~{g(0;m=j`RKcJi|CH$G*zjQ>3 z$H8Ac^8A;ceB>uzYM$SLn2cY}klIV#lRkE+qVG|JAIVCF-QCT9gsMxnbFPTUT=Z{ZUlJhbh#FO5PL+to%qir67zv4IH>ZF>(@ zj64CAAg`#2X$^t4m0PHa<*7vF%)N;XaW}Cn~G=rz#T3 z>O@JJ0;o%ghefR_uZB%YI#E%*Kar|Rq-NS*D3Hl#UhbJyiHfSkteX9ak}AX>-WMV# z{~a1(oX=H>%8<_>3iIDY7#>o;vm?2S_qbCJdFguyi)^Mt{59&b>X>&ivmt8f{g}<-xGYYRl!IQA4(nRpZ3O_T$m|Lrsb)m@71$8qIB7FO;hzEvr=&We|Mi~sLX_%4OH@S@4bllW^s zo_`L!&dSr~Z$nPnd_v*FSlBO|`xXAQ!vCW1PZg#*5pg?5;bp)sK54U3;f)FpDLkw& z7bUd#XCeNjf0o_A64qNnPTIUp;j1wwDV$psKBDmF75-O+f2ME+Dj4zSG+-B>v{|9> zDupjsc$31Mi*NJKLd7q!oN|N6QG?wZp1hGG=BkD;+DZ2s^dWQfx^E77S1emmIa@!aHqoCfyJNe z6uwPii~)q4&nf&Zg@3Ma8RiYe&pL%)sqiHVk1BkP!km9R$EO4FEBt$O09c;u9U%uQ zO%%RcarR+!Pxx<9_)cKwf7)=S$+fvbmUyKP>phD9w;>1hkHYUn<1PMwNa2Tpou6s* zuL^%pVNT(k=bw>yl@Ir6VDa;XkdsE|QTS=|B(QLPqwp-uXE;Bh_C(>+73Q4B`954? zzYRQF4=jFO7;@5Pt-|#f!o9%G&$PK(;XMj-g5Xs?T;dV`yw?GX+Lk*)PTIUn z;p;FSF5%v;@cR`0n8IHLc44K>zbX79h52f^GT=_>U1j6eW7RJ7dHiB=k}9kUUs+(oT{Qi@%ckJXi`G|QGJH~bBsa4Jyprse>_^aXkJ3MwaP8~tm5ZFB|jEF88>l@ zsw<2q<0kUcm0YJ`nc|=e7P{4($cJF(Sc@wZJdp+hLuzMeS45zo{r@{ZpLEblV0_&129H&CcrT^3_q#VbokaBr6wF)W6aVn&wZ!?t&Dd}UJ6i8lAtwPF`2dMV} z-?f85mRQn>ejd~ad0ZwlpU z^B2HPRvcuB`R>7Fx!>2x)8<>il8?lTJ?FcjJZ+|-QkJ|UUg9}bp*(F~4eas)>MntM zJf|s?r_DXUl1IeNo^x*~kLOD%?4=FDXGEAs#O2;?BzJ15B#-7Q4zc7>9kApPvG^0o zomwi%qlJn??Br0x1uS_)EdE4tr5X<|O z1(rM_7JnkSQ%fazv{7-0JmOLUBe-!@gxCC*&T}wi>U1@m>AZajHg5xAw!wD)vlSIv%YqVCA2nbbAOnkG-dcp2DA9f+nD))zhezC8RsF-shEQEZO>t^G8r7tUoVL+ zzx8k$Z3C9|e2!=lVd+c;$f{5m2%tBjIfSJl8N3p|e8RY4kAa3|IvH?IET1D9LaHt2 z9{%DlZbU0c4aCXd5Ps=n+=wO+)~U(hlW|LbC)zx0E(Fx)u^^8p8fjA2AL^v}LLNu7 zd}J(#dOq@vX!hW{kqma?_ryHXKY5qasm#h^rghwW&vW?hI1ZmbZhql8GeUouA8}L4 z7XoHl$YI{c&GDX76>^woadU>}REHeqS=^lOIffiFfIBMb>br2`IbEBVx#eGa^=p9@ zpGp+1U9`fyMR-=4x0=jW1uLwb4oZpROHA`DqF|L(Uf{}Zswm_xdsfbzm0R|lCk~fA z=h@h0&v{b2f;mqr%iLci{askvrz36C*a;*cB?_NF$)f#J_Mp0~82&Km01nr`)LZAAsc))wV9aHaY)s$jDhK((*A zhP4uFZkz5omMH#trp`-rOC+R1{6^ucR!R7Ut_PHGRN<3R`O^RES!KhpzeFSPCtkoG zZ&+V_fXz*gscVb`DwkrM{_;Uf8IjV4{k+w%a@Ab~g{s!Q44l37ZK6@x)76M#?v@9b5CXA2A z$F8sG1VqiHR!OQzt1j&8(Qo7VC#0}xdN1;9GKEc#qpTexGJzVeOaND}OaRC$ z695ur0)S4L0Dx5{fU8v|fGd;<;5Sqz0Bn^B)Hr1VHC~xOjZ-F2&Ek=CH$;4dhF&n>}#}3_*sLvCHymF-+4rW$SvWISZS9;y6?#vK1i!B z4coq8CO^{xGwmd_0X9{&6Ij{LhNl^yJlkR>_n`UTnd18YooFvlEG6Bh{zx=)flVO4 z$pK2^KNEbcxq5aV7E@>4CWl5`t8m|oYbCA+a4p64UR)D7n;i6(gHn6iW`kXTo=Mnk z1CLHzaO40MnOA-Aks~*I*>zmJ|HrjFcfj;xT4^U17qiJ{M~?&dFV+HGRsntit39QV z!v*1~f#omBB31j!4k8}KTBWM`OVKjb|IIa&^RXzkJn@Pkwh+}Gxwja$r@ST=9B@`g zS==bc*roE0u`7*EuPcjAuPb+_*Hy^rb(PT}a#Ni(H!Y$?XU&Cc7^le^Mt>IGE2mq( zFvu5MP*~*_6jsZE!kTD7VLEo!+)TZokmU{)7Yql{oH@~7S%$Q647U()wzY6)#m)41 z1^C5-bmWnv^BaYqSD1~q`*sPk#3%UplmN@5-Eko& zZCrSN=U=YQIMsyN(ZKdRjKk6V1;^3_ceOMLjD@ZDCxlG z6aR_*hh8?4y9qP#f3D&X=llQPo9wZ}?mkX#Y6p^VaNJGg=)njSTMR+sC&%ak2zE{i za@3#$)20xI-Y(z|42lvs@|Igs_#=Y_C`#ZkhZ$%CZYZ3e|M^Bf_?iF7fF;@IzM|gkG4sL=(el~i=A+>)heW@F zI}V8scJF&_cFQ>h`gVR0FR#z1<$3+{7iWO4aNl0_TaPjnH?VzZ%O5flS6{!hzRnts z#Fg5SxI0iX+|ZMZ#9={IXif)ORv^3N<7G(Di^4 zE>`#j#D)G}@5?`5P#TH9U@OGW3HZA*|6K|B$2`)M{5?W-9+ebpL$uBQ{$lmZ`uj&0 zwGM3BwH5DAUH6)=@cxx4WU?>}6-y zpS`-f3l=-Cfr^^JvATu*r`6S;ciytI8Wz_tuj?Mz+c#R*xnp!}WY_kA9b?4(!y`L~ zNBYJFHk%-62XqpCKqnC&&`IPD=p>>6orDbNL?ju|Nw@)>$ifZiB>aF)B=-Y0)jb)9s#ieX4-txxl4h!}VBV=Uk0%s=3;cf^>sNA( zeqUy&_#6PS9WTLa*Etubd56M3<`zEj9lWW|FtKN0ZXv^3(p|=k09@zVqx{1mBv*_76x>{n75k6h6 zMfiNV7U2`-S}c=i%(Yl951DI$V?O<3=GipJgXY;R4WATNv1ffbA9D=twd9O1S1s$- zWN}JOPg9taITp=frsY_)Nc^OTidU^+By2ev7-<>azO!#+0289SI4fAeSloxt@GvTC zvOTNUHMRC&3bti!_j)(gDkTdMjN4}0)_1PM(F8uT^XxfM+v7=6;6jp=_yUf*E?wKA z!k5AqI^_g$Nb&wlNi0m#F_E&F$6U8|^`&Srd;#T~7pB->cVMlF#qxT-hPTB=V(u-O81#qspaVT(AwyMgT2lUM!H_-JNUNnwz@X zVkII9K{MhRUYN5X+tY&LF0Wi+5^GFH^I2Ay=KN~L;Yqg6DNGW-nsIVc0b0GQ-dV2~ ze0s6BmAJ1Y;{i29KKPhXN>k#m24RqxVm#k$385aIMMtF z&23L8DcQVh?3#=Fwl&c%VeLYR*frCxMB6nRoJ6vFUQOQm~kCK&)ZE6`Cv2QP|r?E-ziA1yw-A-rwN=qk!9cyp# zc?Mf3*oHFyZoBwRwBMxPlBMQ~7E3qRXC1n*d%u#NEbNe{mhQl5<_-GwUGOG;q z$`jG0OVusJZ^o`e$=G!$8M_W8W7nZ%>^hW;U5Aq4I+ToChmvvYP%?HMO2(~2$=G!$ z8M_W8^hW;Ux$LLUxxzZ*P#H(Iut;+4h6ujL&4RqL%|j6Q1BbBLjktyP%>^E zO2)54$+&eW8NUuCrgUo9ZJTpL&>;xC>g&FCF9niWc)gmj9Z72 z@#|0!zFmict6hhJt6hhJt6hhJt6hhJt6hhJt6hhJt6hhJE7zgmV%MQ$!gVN+sC6ha z`Y~@}tI@o1Zhm_3ixTTl*lW(SFV?~Z4ioj8;;ln*{=X_(hr%z8a2?7(Y%LCJ?Vh+O zEh|$ZXAoT*Clzp4>yl9~JV7O7f?74^kBC4OEf=#x!}f)^+LU+8es_%wxatYEsE63k zc0T4>7dKy8i=}7VfA0*imgD(;C%kO%wiTB67iMEhc#g0A-3 zM#8p9wmph&;eOB9rtHXOG>B#w3rTnftKI$EcQ%DKas!K9z|Gpi-W14wJVQMDISvsk z51c=Rz<<~B4dj=w{s=k2G2{)kc3GTD)8EHKOF7mD_hK9S79DU6DTi}{+V-xKPQur< z-Mtvyy*6gYiM+_}me}1RvAfx5w+jTD9T*uJ-fXz5Rc!rI|Lh>Xkh=zlwv4fRZuJ}p z0}mb9nsv%8Y;qpRbj7XX-%4GBeVd2(g#CXGjH*DU$3o%|@lk#HyJI1J=2%EyI2O{Q$3ptw z$3pt%v5>xhETn%w781w9kD8djI~EdG86DN9vST4}A9gT1&0kZs9eoU2LFtwe)rsA? zY(FCMY>U~#4Vv$!inb<`U5`QY(^Rx5GuB$UMVXOkHrI0Cq=TQ#iTY@{RUT7{^E8uH z^2M4Ww$1e*7StDQhTA39^wLQ>YW*D6am})WXnJ!K5Ta}Icm-PGyp9;YS6D*%YpTDF zUB}Xd<}|P%*hN%f>gU)Ox1_EucH&<-S>o>uyBPL6JG#Y@LW7w7@7g&qusQ07*w5_( z@=3BR@-D}B@b?$+W-{*!SJlo%B;;oFBzb_V6AZ1Z-(^Q*fNH>=MWedLe zjqM%h$l&sIDu~=5VZAR5B`?ftMz7h?&lboBU<*r*3_k1?A2cmT2HKucJIavfU#_%3 z37n*B@+y=jR14cqnydu6@dp+>6w=8Go+A~vyp2^9xyJspis(Gz=qm|hgHvQa${TG} zvT4{tc1Z>J3XJ+gn;&d?jq%J+DT1CMtN*vZ*xc7Wf)|5j<(Csk5+p?XS$ z2;!P4A`9!i1!8;b1?B>j0n`@({4%>agl`phk+qPd0CnK|>LPBXfl((K>(SS;@PS@7glaaaQZWtrMMR9r;pl z*OrO80dPw|EABUq60%t3TSxxoh>uPnBB^U47(;n4mksq4J&7QYDjnvpP>xoX&c__GB`_g{!mZursV@dOahrto%g?UV~ z$1$Hwm>=A%n5)dsCf)>frY?1Z^_@ox{pQZM2lw1xbstjc$fxJwxf$EX3{&csr!h?Y z12lJg>VAMBncUdqxiot|^2C!7+M~(LW4TxJH77|tCdfQ?;T0lV<&mW4qTZ%6%wq}f=Cc(9;&r!+U5>fCTDBY(5Q zIibK#LTQFw!Zl#+HvEL)>Xm%*kU+f?!#M` z>yCq2-rf3KJB~VfyUTO!rgF#87w2wlf37=zAUnIgy}5Rcq22E5a_we^cKf<%$LAHp zl{n7Nkz`GRwoqJ+vDTzjogD4|WIh?cQ3&KnuJ3 zFzx7PbH2N8)OfoO=G*;V>>Bg!Cem>C>d{oi@&$7jEm)9BEo{R9ZpY2aXZ~s?nCI_a zoT@lKn+lrp316)R;g!431Y^Z7Qo&!v8A&7+HK;7wmI`|Ft;TUg-f?H9=A4;2c}{A{ zoK)&%+YhY0;nKwXbgE+2f2301NL4i5{{2+tuW@^O;^oze`7`f&B9;2iiZhq3Xl`q2 zOI5U9v@tbfMK)QvHJhs3oT^wW_g7?770GE=T=W{+Uvycr@`{TtO9hv@I2=Wb%M6n& zZWI2X3rzm8a@CPYIjDE)Atc6oSbCJhXLDS{&#R^jejmY~H=3*g{|Fy!eLbxJtR`@tn%_5(#a0(F< zd8NYKk1O&&Q+ON$O(Lfn8NqWg%p{oVUj)Bf;rA(g7JB5uX;ApD75+PgA5r*eg%em! zDE^$NaJ#}hGfy~gQ24zHKcw(e3jbK)pDFw+g|EhhulRpJ;Rh7{gu=g4_$0iu;`TI! z7b*Nj6yjC3Yy?^2yO7^7*++oI?UNxVZGNcm|C$kTeyDH>27JVAox<(FF08bQ_-qCiKd%irX>)_ZTkzru=YYcRQut#Ee_i2UC_EkCa^la)3bz5f zxIvYZ!qmPi@;58|L4_Yt_!|m8t?;u7Cs0XN~s!mSE()wt7d9%PA6^zXtjpZ@@su*&gm;y7tDUEyB>3#Sqbz638)IIHlW!f#dh6TssCBMN^-VJ;}+ zv>ry9v&5JCc>W8pg!}7|lQzFs_$iz%C!F6ZTzkCunKq{=e5S%&-oz;ahD-b&AMO%h z@v|%Bpx#rs1sww6T(0nLg>P5*Z-8A`Y4Zhzzoami1U32i5X(7>Uj>%1eiU-j=06nv z3YJR<=Z6Xh=%9#vp2DvJc46VXI)%Fx<{Fq5A0J}Q48UYx11x^-4moMFPvJf++Yrt^ zh2Np@UntD;=UiCs{5ioqe@?Jn3gY8KOm&@%56?@Gu#T(4Lvdxf7*&~*)+Cq8STnQ}YjTl`Qnk>g~oIGu=1(q^KEdDTDCr=x`r>>3)vc$r< zJCx%Lcwkqz1X*I?d_0t=%|8RX`Yp&33+J&=j(#R^lZ|GOB^J&zp*(FW@D92gqrGaAa%<`A&t zJ2C5enCzd0^0fIdu;exIO`h|Yp*)_yrLdQ_o^6WcHF3Fj8_ECQd6tsbS(QG-lGhu7 zC9jDk4I{a$ZzZpL6^Gc#(}wk}x z`%4ADat>uZBrFY~Vq}~UXw33Z0$`Ux^BSFkxdeCYr$nbEJS>PIwwvW7?o%uB{BZf^7bR6snL zQgQZ}Y4~-P4AT7NZOky$X{O;X8D#j&+n8Z*n1E#=9MRgzH*+$7L{leAc`{%* z&JRnpb29ak!GeMu(a2e2IgJH5qJ`5wb%0^c0%3{fO`F02=f%zdFK$HJ<}8Slfz(EE zj%dteEszZA@lXrn1l);M*_7pc|5ViPc^uKCX=58~@u?oCiT2Dn)}I6TJuOba-OGHk z@=ZxtU-)cs)8IL*Hynqd#!Y9KJyhN<8Yvuyl2O=G`Ech&S6#ia?c6DsFS~{CdPjM< zG+y>p`HeZzn)#fqyUs!3O`el^#%&*whuKi8MI@8Z{f@2BqbauuO~P_}Izr3BYyNGm zv|_5I-kxFioaq$P@&dXxa;$SwPumtwL(Rzd-lk*@MWttsO-`!j*iMP>8AK5&>uuncKr`BJHB{+Qxl349`((HzsL+Jh2>_k;I6@IUGOXDdy^zLGqz z|E{$1HE{bHG{LLb*u$`QK%>*=ZYQ$8Kf~|+1v)dD|A68z2EGH9fA9U5q!oS>8?5e5 zV;lEW)9C2HcATR)V#?=KmQ7C_NF;8=W}rmkp+uq+Iq6cXq@-9Y==eJI+t~jJ>2$8_ zMIJ{Q6@oxjFbR%PBx>(KCqQ_IPT%1##i6?`!9!SwqB=3|T26>471fEQ zp{hjZDm)=##twK~HU#gIbvx*3?z2}}Rf$zrRbrJ@l~`p}C01EgiB(orVii>-RykFP zRZdl6l~t8kCXFc1ZtcT=8>QKIJxoBocrIyN-^n_NNdj!hy{3QLz^HK! z9iApzaib6*g7TicARyjf*n`($52g#%`W)U>yIj$ITYgsu)vBIivk?=pc?)Vd`UA!C zr=ew&obB8Jeb3q9ZG9s{W7oji4fjSlAGa@V&R<^SoPT?;uVBtQwZ16oO@?2`J?b9W z8{ReN*itd@P1iW<&K;Wv_G)`40Aa5qbd8M+ZyL}HFPWsMgrVlgiA5%~&X3eFmyeoe zTO2A@qo-htgDz4m3GCe21j(~4W;qzdP*70|!k~Fo5bVz{2?cVZhTrw55V)TdyIn7G zJ7g>S>Lwa5aywfO;F`!eFShiB)@!4kpQZN1*z@cj!q($WP3aK#My~KX6fZ1&c7E&I zTOKtJP26+jOKo?|Nw_m*&EhufY4vy4!G3Yu;f%MN_%iMMo!x<1QXs@lHiVW#WqqDG z59-Z^J)S%9LaVYlU?Q9ACsrz(MrHHai4J8`r)<7A@yB@H?bT-BzjfX%-w(G}X8(rV zJvMAV{ob5Cxpw@had!I>O|a}l2@B7{o&J*Sud!dkgNR4bcGpDT2GQo1k0r2I-biU1a@&Wz@}y2$g+*^T#^djk#GMUY~@HbU6-mj_0m*oU4cum%J02MnM7r>-0!VO zq)aEioszP}q9kvNMJn1^Q5x;6D04e2%A>svQ|*+fh-g#ol<=qThMOR!E!9z-?lwWp zkWCO((I$xM*d~Y?eO~UF$U?MPFzf_4!*WT(GDySnrj28|O$!UGh1;~i!D&v0aMMDa z$K13a_%#ZDL*XANOf{IouT%K73J)v1OW`_1jFU>JaW&_^`r%rSKyP|48BK=>NI6VUeZ6Co0T7q8ro> zvcx9_HqzPCfn_1Z1tBMGS`=OhEb(86&V}If73M|`=RXJ01^3uNmzUX~+yXlesG&<{ z2UtYT&aB9f#qC1yF05PkKLer&sP?$q}1vzRUnD0m-4#eSLF3SVX zMW!gvtnd<4A>c42PyyzcOZ+|aJQ=XXVa(!Y%-`bG2Zuwo`Q|1s;umZ(;Bc!9u}0k6 zJ!CAvfp^ToxVhWkazHm3a2Ph<$iOShM>0Tm+KJpa?-TwuI;WY>A2(m|x6F4p9hlqV zVl!3fgp+@1JQpYbRxNJ7bmP9|m{8+Di~jzSIhLv9c>_1v5iH~1?l02JOu-SMaG)q2 zq#BVp%GAu3ZGEGI>NwT-Z$gf#!95GDe({9zPyv3Ox707;RQyKas~1xEg{}vb@Y}A_U?rni z6vO!Zt!w$rr#(;N&s$gcoCW1e>KxX;b&b*8D^Lu@kl$4&chObz&sY4DKp6%9ZLEc1 zq)O2I%N3s;)lb$L^S?Y_vPSa{C_dNR%sRoCpHIPmzv8p%S_6J9Yhai{{{MsGv*CIj z_~%W*|B>R;{|CXpVhVnFf+0IY|Nj;I8>ZlM<)j!kv=s}C`M?zXHpM>${BywnqURS% z|1FBoD(MFBQ*04oTz3GSfJS?3e{NEIHi%^>8uQPd&jx}<^Z#7&8UORaKW>?&6)X=A zDgI|c+X{ZJX;f*xF&WwZCFD<`&~5Pkvx%nBGj(54{*M6v84~GNo_L0%$7bq&sQ9PA z|FY9ONnP~&^=rky8Jx55F8Y9X-uWYga*5+RhfIr@3#(Rcm)`-^7De=~?it9BNPY zlJz}ZtJ~VLcs(N@oVdGbZEN$TF|VyfQ%iT}#XQ$gg_0fK;}u{hZe;{}* znIBLn_WlLpUv}5_oyxyo!M|!d9a-k5Bg^8`k!874a%ItUWSLAyMkJYzEOXP5k%gO% zEY;JI_u?^1qv^=M#BG_Mj*Q&-=}7O;%|Cua9J<>di9?x=jJuZU$TFFZEDNV2ZE(@a zZ8cr+seCOmzof1UzmY%wB)7Dkj!fI>$h4h~Oxx+mw4IJj+v&(Orz6vDIx_91Bhz*| zGVP`#({?&CZKosCZaOk;rz6vTIuchu9SP*8BY|W(63|UY0@&$DTrH^VuY#3q0P2k z3TCQ)d?j-uVz;%lFp`eU@2D6#lPlmzO6VG2D6D>MMYdsQ>%g|YYfRl_1iOOnDRNu*`{-pIg~fwBHU`wbsDL!2&&(wAM&&}v{uAC}rU57`IF zvB2>l&Od%1=GY;X>@YwutC^Oj@C(?8d$l(I>|b1SLDpQr`VbI;s3GBvw6ei?%~^noQvm;&AC||%?r%5 zn=sbn@+P;yFn`!DzY_g{Nh-RcX49bgPI0qo&^-QM%%)jfoQTBxBwi6oyjZ1PFzsTD zA}8H1ik)=7vPmZ`tZg>sh7GFVn1xTa={t~oVXdNC4yGDMNPKCFH!DR>umwe1KC#7) z(hZt(gDE>N|I>XGjvdF^2ip&sbt1)P`neeS2(v8gfY{0g1lw1LaxHFOXHCaQC;m&wQax_1f#i1Nz zuyya*a8KpG`8jd~NCUrMi9-&E%=aGH;X4#&; zncj?7&*hQpK8L+z<`9QeeGcW=7CC?JDti7L!3r~+B~-*dul*34Wjm*4`h(~Kxn$1$ zx?wtVDB7oUu624q9<`O@zPWlz6}2(zGZb8=I8_sb0Ah7)1t`bcV?p4z54|& zaSQh1C+*%xja}?ZCvV`vRl@H3bNUG8aa_9U5e6CAVhVH4F6xqmeM_MfIjz?hJ*_t- zj`Cfw*$(pA!AA#=(uvIDM;UXJamq=)0qh8(ThE=k&HUDU#(eC^{aC@>8+`18Z^sPK zXYM;BCnCZAxykJHi8Ez5ujkZ2&bw(jRK31zsBYrSP_kfm^TFUWoIz7Q{=Nt2PCWC# zmmYj%eEz)Mh0iy-Ou1`4^?@_sE;us#{EIJ}un1@TY?-(c=it=2wcw@qy_x3@eQ>_N z|9kN_T7S;?9ZN??3Nc#!pUyO3mAhJzr+QZu-Kt=|N)r&PU%l zZ?~iq&yF!TAE<8P(*@Y$r3{D9o6pBrK%Vc3NqvVZu{<_?e|{3*=OiLNP67h+nTg7* z#3VNdFA3Q#hbC+eZVV+0cFzyf%-A&Z_dd>-)kpliLAMnt9Bo;A6?JHCul0n7iuVmdo{>!_N0IoZ~fQSKmiD=i+c)jZ{hOv^kko(7Vvd9**&Gea3C>J{0Dj4Egy+NpL*^V{;i_9*w$?U-IDDFmZ zKW2vTJ7V_(3`4re^qU5=*#6rCe`pi8-vayPP%n6{*=sg?yKP`GOejsjzJjaFR>(KQ z?U30G*$84Zgm4#`T(^ZeQT+Syf^jg3YfpJ%#JuSlQ(jtLR$g9SQC?X-t^8%>=a*kl z-cr6&)@XtZ!y!+25ukDg;tzKtAURQ zkI%<|Ylp{|D9mM*BHyI&%?iIo;h!t~YlWMT5aQ3L6@FA3SXk|n8J4hzuKqUhZX*!!rxT*-xZ#Y zWhmnIbcH(<-lXvL3g4yhM-~3E!cQyw6NS0_rP0PY$P#}7`2>^wC9tGbS-Ei1h9~_t zT1whH11y|rmkW$k?vRrYZ5_+(6~G+1xaW|_jTRG1SlOD!kJ5)b)sTYx3pD?(1%^eMas16so2Au5933cS>Z z`yPcqpfG15micgrxu_N<`ypWQ=kp;4b%nxzfd*7KUsU*Kz|K!(78+f_r3!Okez^~q zxZj6616ce#DdeQhLWR?4(1mlR!s~&ZpJ~&t@Q}hBuXZcIgDmkzAMQ?I@$;sTlQuUi zyd49v!g-^@4*)wqQ70(;IfXfh%bjKTzQ__k=)-*&SoSDB9dgp<#|nQFA2Jf|&lRq~ z0H(-KP#9VZd{}9-LE$Y5Z&Mgu0AGK)0~1P$0w(Vu z0>??)IJ*3u`XB9MBvKL)CUnbPTDlW&sTc?iN*g`V2M8u`f!}I zJ=Ds57X(>;e+j==@izm@x5HlGM(;nd@b@b|M&&&xZQcRg?D@pPzfXoJgLwX&~jHLve_m zJZ-YT^q2WaEdE6DwAl!`lm}wrL~>V$OL^#39AYPThZ{(}F{n7iQdjH*Zp0tsLo8uM zavW>|c{3^C5DO=g>pJ1+x)mznN2E!CDa;ntNdT;_174#;61W+Ht|HwE%nQ155&(Z( z31cTJ|IhK9NGAewVK)Ap1i-B44@`7y!nwF(%N!k>@LCdJqGJ=5gydRIyT|+o)aCLKwS^?#~qSD>#uuG z`~U=U+~Eea{(oP>&=dM@f)CtXY%<$${aI=n#O_ zJOF_beFy*^6()nxNqYc-Jrqki=3X+W zp(xMDHg@)VC*yD|m4@$4GB^pp7;MZjmwOKTnaSWx{^l@@VVh0EHz66YR?g?V-*cF< zPNzmbN4BCf7n8x*#?dw0dTkxJm1LHZ<|xW%^=kSel z9L7FwPWPPX2m+>K+?*d~;ei7QGk`nl6WP$xxo+>!7FlGJyAQ^%JsKK~t!j!^B&iJy zkuY4QWEX))^7x8sFV9)W>!rD?PGe-Zh%e5J$()~DjOIy&mREVzCvN>!?sMl@#-9G{ z?#{EJ9e&HM9sMgJ|5Zv9Cd5;vFejcu1vojWRe+J3as?>P6PIEIti2DD+DEAyOQnKo zoS#%`uWo^`?P7Afxv_wy-X!=Yjxl6&kM{S#l&@#b{=ZDDJeV^}G(;nIz-P;M{4uk)6= zA)bogD16l@3%}6yfD-b9O3Yk*H8DOr-4}s**jq^adCP937*>7v*BSE__V-{UDe4;S zt^HXQLE9yKtWF6$)cj4#nq8S^>WulJ_h0Hv&A(ppK{e}7K-UUgCz?Y1yPcK&We4~W z_=`PXvO@d+am8mx_xIrUPT~JQD?UFE-n{@P+fBj$vEuVF=beZ&oq|72*W&@-yU>_# zobM!n*68y8u;TOls1x%05q2Sh`2TgqKLFpJIm?)jzsmW0n!AMjW7j#8!JF!Gqi8y3 zY<1ahWB4beawgr2{D^j*$4-Yxw&I0Iex0>Iuoy)osMy%tw7#cvZFWO9sv>pQ5VKoi z63T9=NvgYZOo_T%W>V_zTvMvBuz?^wrMF) z1qJJiTeKo@5kdR#QMu^#0YVXqqA21oa=D6%S9~D~3L;m8{NLJpubDNEleYX!uioEj zGv}MNzu9}wT6^!=Gqd;F`bx-IJly427%z>>qaL?ixG>YWI9uD;l3ld8whkAI3-yW? zFKM&jx<(6o2D&_}6J%K}oCM?m`W2uNif0kmcktQ#Kc z8t7~9ZS2z-zm5{5!7C=t3zt+iWm_+9uHjUbU|wt0qD)hrhqS=ROxlW9rOt$(AC>xr z>)|tFbx%h-U7+eM$6lx8zV0Shv$&-$Ta#JhT%;q&)-+YkucN=^yB7 z?dpX}tynLmG6sduTv=6fRny{yuuN-JbyHm}U!M`zHESswrV2XhU!ybqABbtv|ByeS zEw}*TPw4$PJUD+sU*r?DKcRd_;aB+=!msi#gkSP6gdgQ! zsMPT<1c~r3H2x0UP*p9(lT9tRLaMyeEeiD!PKLt6BN|L=?vIfzcVgmivo~NO>bjmj zi)urb0GtTnr*W}G4LC^vOW^6iLxNxnMM3U;syaIdtQY8Xj|7y>IA>A&;AKwa>Hq>xz3B!mXs{d==|W|gF)_Sq=XS|eKEl*DKU=lL!SHB}^P7l`Q(_12G;gU9 z5ZSOXbqk!|@$HPPO~(gqBYJqYt#Nk-aOkL z3REY1`Q`E{#-c~1tXK4Aje0qrRP?e~%5?4_8FsL{XZ29k+97RL=LkU?y{U&}C}{aW zb4s7$>?sRqZxwwTAE&tX1+5B>`nIE<5_O*iJ&+(TTI-)3we?#=tRIPG$$U)3AL{Yf@QEGyO{fzw_$@H7?55I}0(%O*c80~@k0Z7?`aD=!uNQ0J z(z_6Z`GI*Xi8{ z+p;ODq*@co@ChsMcucyXdqwcUIU>ajuWBDSrQ5nM9+hTH0^f-%)dXH8#Ow=6UH{7O z_E6Za4v@GVaagkA>&_IWVd2(F3!Q$nYDe|<-O2^ZgK^h|O4W_K3#?7MmsfA!zr%Ir zvO7jDa^OIx+v`B5;Ejb_s>`)&m?T`Htgy~Bu0`zQYe(jf%o&+Ba+FnDZpU_(S8qS+ zhCL_mOrE{8zI?`ph1>0xf|W(FTDY32Pm-&df_^?)GP3`H?|gmQhU?*uBo9ln%J@4% z`e$eE&YxLL(e(!XzMZM>ZJc}LJbF@^SHC)0jhNq_B$ z6Z&hm$65+j#ajN@ZngZj-EMiV{m=dJmfyGMwfv#|#s1pudF|CVQr;+?q%WUe2+e0u z59cTMR2TG?c=W(WS`T1U7WR%c3@yv==VQ_w7*z$m6FhP75$p0j$YX&okAFOpGm zo%EKK>ZEl`@eOlE8p;VBbwkYv*3UqRX*jt)IcJ38kH^kls;`SB4JS8_KYOWmShP*0 z#-)bRsykp>=X=uPSkFJ1%93?U{Dy||hV8+4JDhl%lZp29$QyQZasHb0NT(yGE0}V_ z`Q_)IJc2yem)plTCo4zJUP{*{>&J`@wWtO9nrgQ-sQNH%gHF+_w{0Tspx*LtnCs}R zdSsGMZ^Z}Ho376%#Hx#n+E2tjA6K>8Nzq?=?c@Ddp=cd9rMta zJsq~8-yfEC!Zxq)htZRVK5z4YKaAe4>#*Ti27!2faW)#WWzyT?KaV=kI&5gYKa7R} znXrIkC3<~f!UBs)j~1tU4I2X2;GVZZ<>d-Iqs6iGI=TV2HS4fAEHYgiTwFw*Gxegg z8}Ub)0F`KLjz6UP^5L21%2;8^ykCcU?)f!&?pd0!V@2b=ZhhkLnKTz+TVsXAu>$(P zAW?W#EPqlW5zC(th>Pe?laHXcD?SLZF%yC@zC@I(k)6c2`AhlVnH7mdykl;x_~b+( zoFZKjJnb`-%jGgBSH$vDl#_{x!Yg70fWIT4W#PH|4aIS(6UQZqLR=H_>-$|6dTBS4 zucvp$ibxL+J~t2ALPVj=dx^QiFn@>NP}Yx$wVa|ETYTG{-+)Fd9=t7-`A+isw?9xJV=OjA8rRDZ7mC_`~ zzf_6GztqIj)Y9>jw415P>}IOebu(4waWgeVx|!O727z8%^CVqDbO)o2?pCzXor$)z z+Vj*#jF>gYdU~LKpGhJfC`xw&+NcGmjaqry_*frt%G$kDMhW#Y?@b1ug|@!g;H3h; zUEp?sD{(>0r|CkBuMzlqf&W`z8db~uZro`YuNC+Q0zW12bUfQK|6>C07Wn@N{BwbS zCGhVA{-eNW<2?$;Uny|Cz<DQlj~;2L-+X zSf`t^J|XZ|1>PqxjeI%F=#B8ljNZNh%z1d);iRl*1b$$w%lV2)s;S8s%}0$s1uay)csn<~Y|ooRqam;Hv~@#dw$BFYtQ>-X-uu0{;?N=OJai zBJke?ra=$7&9XCu|7vs?2X0pRPgzGhoRoEpz{U6&&z$20t`&HNz*h-;v%vQV{4-#k zAGk;p_!WU^5J08TE#b#Zo?i#%{2Y;D4qVg;JPVjPmtwqMVETMrZSqX`PbSZg0&^aI=WtTi3j+Tbb1s?lqQHqsuKXy0-zM-9f%^ph zAh6C)%KEs#cM1F@f$4*7t;s*($4&n41LnLv<#1Bg(*i$)_ms?eLf~HsOgCEQqy;`l z;8ubAfpvaT)>eVvBQSk(tT%Zkyxrva1HhctCml}8+AZ+=%3RK^0`C?05rKat@ZSV3 z!DFV*L&};WFnvC2FnJ^VUX!<@fH`lcIh>SrroczzLl1M#6?nP8!vb#?_!Gc7-IPTi zj4DhX2p?hcuv_rI=5SKh0|M_CoKN6;2j}N*fxiZ<<4;-iO=ONqi|`VY)bIzR&%w>ZxOh#M4Z4=v+>OGfR!pv^~=CVZnWiERwf#>57Z%HyMv1fiK zF!Q^CH78|l0bYPV;uB{6R$%5|3#>WXZPOVzCjL#>Gyhg#=HCviIofU0SvV&C7qMsl zSAd!SHDJxrZkx`*G4UVAp7~DzGyf@I&Cza~_@4f};J+yNF9Y*^wg7dp62}xjVUFML zwn=le+oo#6pC$OSfjK`k15tCd+a|IT#a}7-wSwOOtU20k6Sv#s-huP8Qtg8qVF0JZ1e5xY}?Cb3C+K zxR%3REHIY=!pw=G;b6NT56pHato4s}z>%k{i-FnJggHOU9l6)ON#u*~9TR}r)`SaG zp0$f5Eyq0?GPX5g=D2e0Vu@{?797G_u3ap#t!E1kVQx1lO>I*w{}+!pw2y($)udpM*y{+-KRT&WOsQ*^Pn3EE@=Tf+666`lNePlZ+bcnyN%Pt* z6vZ6hkA*Hsf;zjwoeQ);7DOS@_ca*B=0 zsCH`(*~7b?WH?lpHHU2P-DomAZLZ6wAO}lSsg3RzIv!oOwN&qE*%{iX{n4D0v_S0N zYdCZV(VVmh)$n%1q4rR7s7!meFBlHBewq`^^J9iX?X%`k{qb%;HyjHt`C`@>lnuDD zT60=mb${0aETt3};};n7XdD*>h(_)oKPkn5$-pu&F!59ds!4fbili^ho%JOH5My`% zVhheN@trw3!5@Q}*C68n1p`>+aCu*-7+>uRaR>UoHLjX?_`XO{o7JyYN9wtHb8$|f z@3I`Zn{7wro%^lDq4Rs3pd4qohIHcg(`*YO}8y-omVlZree;VIq8M-(lw{noOoio2GbGNboHf| z^z{sdFFzXE9T5SBi+_D+&-9Y>>C^! zSiiQbZ-_7^hpg)#Xdmk8wCuR@DiT}O-`{K5vDjeGn!c{iw04}4jIHnU2nu2wDI_~& z*~!>ocmDuD!X+6=eypd@8=#K!W6IA*Oq`$vI>7k*@P)D$kl5(6zzJ*=F_ht?svaDmp}a zl|HbKym|A_Jkx2hCaMhDu`*SDoBT>(84^VSLQ7x2%b zhiPp5Y#{lv4@S>|`^qe9!zlbKR7`qD`o97Xt9Khdt5(LpL-1it>wDloIST)7!KZ6K zW-7iOkHUXk@Mi$80l%Cc-?4?|=S3Z)_G#=t1Ag@={7J%IbhrE+_^U_Zn+2#;{Fh>X z+%yF}yGjw~P|OWF1M;7Pzsf>lljWyN@Gk`JlDGU2 zz8NK=LRMn`CHMo`Mux^_-cTR<9WwSh9vZbZBJ(jv%}s~O=KmrWbK|oxncGS9x|pMf zt~f0SVA<~n%`R-LsL9qYX}h@Q;+m$q>^!_+@rh2GW5LOnqOBj=RI{mr?q`(5g#RHI zU(|CFF22U#Vh+y5*E}%QiQ2^%Ju|;0F1=EFk)wh=h%PU^mm>9dL`sxPuM*|bt3Ca_Lo~U3!%$mtG~xrB{h|=~bd!dX*TLUidXG zy?~5MFCcd51*lzm0VtPV_*E{w@C%n-*gG!0fR#(H67ABf#JKb-(JsA8j7zT)?b55n zxb!N~F1<>OORo~`(yPR{^eWLVy-JKruM+LjtHikUD$y>zN{mY{q_13h;a9oz!mo1a zgsSScTxxlctU@%)e{j=aNAG0~o3+?ELeRQZJwq+% zdz%x?0cIL^I&A?pBU$&b7>>YvNkFs(Glw$+U4tF%Xg#R;p$W>40EEr#TtEf#0Ro0Q z;p}U@Imuv%H@YeMGB8n_ZIB#~2|r;I{eHrvfbO^UB)Sv8ao7*>;2N|%9>>@BcGVAb zUB14nuVa%cCDiu`D{PG3N+DeTQ6Va8fS{gh#<# zN<2bX{_m}H(ZiT63lqKP_Xu?9qK+L(*I7lnbZNiojvF)t>Sq&Op8TPamY`2XTY|o! zW*!Gi&}KYn!{z##LERuYMAg z9hQQPW*P0r(OTh?@HDIx-ru*nXU+P7F8>`JG%HP9t@K>9NELrp#ENeSE#bIT4?8z| z@2x*a;m3{L>FM!J-4Pr_RnV5vE=I@v9B)8FEK}3l-*K6@b4KqhLe1mjMrxzQ5!>ie zTe-CKwL-Abh8#9R&`@MOt)MaK{f(zDq&i2F=%o-GanX<>GG>qHtRqB?H2Nw%B=`d( zv{kote5AJOwobLf8nTc|GYK!gpdNCjQl1{M2Ce&TxJXI1r$;IW;VPxw`qHi&W9|0+ zJGZ~f=Kv!KMyM z^3YeZLFKdv=e3z!wpeh@V6J1M3eA|1wl|gkIU_ReOPB6ErBS7KCN)cMeHrHuJaMjoD;rO& zQ}&H`Vx96cI(B2lF~#b2dxL?BD%R?4PkiUR*q-sV9`&-Rqzj zF#Xiz;(T*vQ%GsJ_6@StKbGT*9t?c!2)ez9O&dGODo7UO7Zel}78DhXDLAs=?1J+O zY6=$Wp@7tk(uNk+nt1iiR@KC-E}VFEl^Q0f0iZhUt^q&o&*f9+aEtYXqm7ce;9SNbl89Cru8$Aaq>A*YW8$KgS-$Kk;QJ#rz%o(@V}PX`k{o(?8SPY26UNl-tr z(Tg;_QKLm0HBhusV?-M@HndU0LK`(Av{8dWTUza%nKR~yW7gv+>XbAEZ$g$;W$>A{ zWz`r=vjG`jBJfIqZxwh7GSB?u1inz&cSV4B6k=l;9EE1`;0Remr_47dzo*fQQ!2c=mD*}(lhZ0VAw!n?RI-e=)5`ixh_;P{igNq(> zYG(+qFxNE<%<I?Md0}Y z(>rDi_s3>u2(LkT#g;i6nB!@4IG9Nz@L705W6p&FcME(iu#P`veMI0}1g2N8dOWY4 zA>3{9a0f8Qf1ksFCkcVcYXWmVjUn-j?-TfOfu9G~X{D^!1&-tWB+Kbt<(Wzic82if zCO<{M9RG0+CuN-|@I<_SW6lWzR|$M6u#P`v^$9#AFulj486adA!Z({dTmj7S-|BEu z*6jknzu4v6Deyf4KOyj6fOT3as{pUF7>^g2UUR+8CXHYFwg9K#o?r^zY6>YFz4-Q zJWMktPX>(t3asN#sZk~x>si<5sdV+s?28R9!!OI}gAU8l^qP3GYQ!sZP=p;$u5+pR z<8;x~Iq{?FJLg8hL6hU8g{mK#RxVB)e9klFGwgb2I~+Sh*o-j>%%W!f*Mf5@{-|CM zW_|-O+qwx@bM&mfxi}{NO6(~OY?)5%nBNVoIVtOUU~ZEMbNufY{2Lrj%K9WQx1WTW zzgzG>>u}(W09dy(c7`zX_XBf&9&tGEC;-fD5n<*(1I+wq9Zt%66`0!%!p#4h;L{5u zuH!WR%&FJFv%tfanF7r5AL(#VS+M1)eJt}6{A#<{3Ll~5R^}N;uJgn8qWqj?IIrQC zZB&8y*+zu5eyq%CjvRe3V73e4lT19ljvV(FV73Ke=G^4Saqj?T{S!Xk#IxU#r{Ege z)j8o~4d?fc9A1}D*;vnnk20Kzjyz?Z3e37CJl$|A9JyDYRIjS?bxW8zu3XRhW!=se9Ku?jQZtZQw{rxCFyG(L0A}41=CoWnX4ON^ z<(V*ZT)Ce0%erk49Ku?jvNFJ|Tf!WVE0?-G@GRSLh(ph^RdY0PG{GYwJ&eVlcTO$U zE>}W&AicYi1vskkNJu}#b2+3P`g0|uA8IRI3C*cp;+4RtmwF{gh_1q&<2x6brW^_h zrj?!Ol^`>xcqPa*l^AgrGEMW*gajETO9%-v-RzOjoZ6*c38JNYojaen0(qX|l_1Y) zuLMcY_DYavipQPfOLJUUtcb;CDweo6-L{Qi{D}NOOkx2NDRP zf6SK%3Jg>dVIkvcL}=)E5E-6p=t6Fe@B8^%Gokaq-}G}2Z&4uu73q)19<%tBuP7n< zQ*ysKl&~Y0xPaT0PLdw#zEQ;5WTms+s+Cz?qsAXI7k^rj2H5 zPEzxpX5&VqgpznYr2%Gn09wI#aN^^9| zo0#`>i)l3|iXm!Rk)Mp|lxI!66Yy*LiK;hc#Of|QG?|aw-*lym2VJQ6A3OkmyWn39 zyc_)eGqsRaE#v>J;8VYLXQ^d9ZTNg?lK+U{gKDLz+v3~O;`lcL(;cjoe{Bu!~`EM5d)4{(B{IRnDu!ZSowct}fle`bkGJGz2GXARtzXSYx zsDtL)Dg|d7Ckjq2rqaT2XQrX;%o>Nr1< z&8`QUy8ttnV-FyA3HOkEuO-dQWcNHXGufP|XE#xgOP#0>3vm(ZM4q|qJ)37PCwb;_ z(wVue&vIrir>OgxPkut;=|PIrf9?OA?DY3I*=bxC9y=Pj8k>>C_4=`nZe`h!u!t%- z%C_n2bXW_<9fm|Mx3}1KX3aqV`gPXNQF^l)V&vV`0im48foFLP3BHQ<)|e0B5!%%e zO&Qa@NrdW`Rv2r_7p7*Enc%~4eVZa1>CP8~NwT}_t1!Hi1w6B2VQ>Gc_Fkm}d(t`h z#jJqu;zfcWcCBt--#gUM-q(pmRuz-FHd0%iUdmz6*j*)uA(8K4Y%Z0tbv<26yE=w+ z(c=Re_PGJl##${m*eY-}*Mn7Q*R=O8Ue^Wh7d`!bQiarelPb)`Jq(xm)Zx(OFEAEe zsHSgi&uH2Z!G}Qs&mRs2yb1*rj>9W4Q9jTHQNijTXlo}YBeYR3-BT`noWr0F43atw zsZ7OSYN}j4y8853W=wfu310WPI?@mEN;ULAB2{C84ntm#J}eqpg60OdxgKt!o7b;h zg$9>;uecwXTdomO>*JT@B3=pNU~SJJm9b9iDifV6L0nrvS?Jzgog)NYq3*D1*>CsO zs}2#kIiv;5eUqUlLd+#-6Mb2F#pNj=PDs5!#8Y(6r_f1@Xm5?p;)Rl1bUZu|)N3MD2Xb&C zw{W+$FZyECZ9QyXHHkj1KqG^Azu;c2sW77BN8eX`D)EvIgHC>MICS!#j!rOit6;;N z~{x2i_ z*uOB+i~Y|=da&O&vKsrVM>?<{d1EE*U%!<0uU$g>zg$H77usn5vkPgzubK8&U(inz zA^Oy$j=KJ>EmhYaxoT_6kJ}4cQmYDD9&O*b)jl3mini`5{%t!}GH&^5d#vRitUG*f z`?LKMTJCR8x9n@LY-zrWz`zsK(R z^D|@Z%$}E@8Jo0@*zn?r^;u#om~)Vc*iKc-8i2TE?v*oyV6}*?S7CaeFR(cz0D1$^W7zTYd6AEQX2j zPu_RzIKA#Qt>|2}y?zI2q-IC`_H@hiZd$8&&lGFK`j>?xBe&M>s6E-fdG$!$j`-4A z#0p(4w{NM&l&q0k_nf?DWdFzZr0c%DXXe=caVEqPPFV|t=GGFw(Ve+-y zKUIf1+&XN_dVd&o!%SGL34u4#`$X$!klKf9_1GTnM@BnQ$4N!MId`Y)?4yY+DNNTH zi)CDGx^6vt26JbAkRwP8fkSFYiJQ-4F-9=f76_zf&1Bpd=*dc^xz{Bxozmu$iAIJUx+G zk|=yAaYX#8UnWv>6Nz_y{B~z`Q#rBd6LiAcFS$ysB0K)$v9S{qMRz6&KTb=_PF1VX zUKE_i^AmN_MdqYCV&f)OV4HVGqUdUz8Y?JKhlrxU6NR0yVny)+H75pN0upLPPpn5b zZ%iY)iFxG1b3$_B7{`xiqST5POjLnM*QICvvFf~nQxND~#?&(t=U*zvs+Ca--L*&E zl}v+^af-rdp%I4874k6sE3&$ifPyqJS19*{BC{InTRKyy6RiW932gjrPn3!z0T#3w#VRrt@rP2v;IrY?)($ng2G2ld`G=J{eyCm{TqA z#lSkwl$8~jz8GLI9X2~d_ym*IYG97%YKN1uu8|lWVSR4OdauCr7M(|d5^%V z`8kJ^vi?nAn)Sn+2Lz_~&D!2rrwI566X%PLJY~@us+yCseuK}w=b7swjFy+S%o~n8 zWyLUvO>eMEwTNw@iZiR$WXc*$KboUwrs%qpRnxk4`OK=Zt-5SyRm;eHic{y=D?b5pUEi~6 z-6O{53;t{e>lqxT&li}%!8)k~pLIf*`L)2TlLm*Q*KXo=Y#HRH&zV^+_$z_AT^a)B zwumstKMc(AZ*e#&>;1so&Jdo3KWv#Buw(v*fi)*(-382T2;nsTu&FiinEw?BxD9z6 znA;G-Y5ZZ!Jb@kap91DKheJcD_%0gD{1#Z-(N_2f6>4RkcjQ>*1n07S2{R|(kz;LJV74jYN)yiv zM~=D!%yuNaz;ISMay{dNZAUXcW*QF7_+Wc|1(@wcnDcY5BTrdB0A?EzW)7|I!gl!s zaFvSR&Jdn!()yz#$9192V_Oi`dayDx9C^xW17`gb)_f~N<4n2jqNs5@#-{rf+zw2D zg!NAtw;|dxu3XOwVf{}*Aae+7dCE!yv;GM)$Cc|@A*}z|feb|AaXnSFYEB zWBs2YIE1;5R06a933EKIT+a$&{Wk~>VJ+9QLRkM9!6B^Wx;Ek>Snq5M7Czn%!JfG~9AkUyl4)RR)5N9FJq!A%Oo~gVD3G#fA zSAsmR^-7TEE4>m#I|&kZz6s4PA&m(M@=Uhy&MqN|m`j2TlSIrML7pdiCCKx!kT`Qm znrOu~YN3P#c?L~Nkmpk&5$nYv&s3jW$$aFwNlKhqDtf)RQ-->RhY(I18ZgWmuEs`s z^ls$igEn`TioV}zsouZMaNLpbJDcY+?6slccrwR+Yp|+Qb;!yvz>t7)xqY>87r@B$z=0;LkK@@!sNY+PYdH$ zGGE-sm>>4LRS3T%TD+UmmPPU3OgC?A<_(pTf0F5^0YZ9Z;@QVo)=$sX$9yT3Rr;9r z?JiXQ4aA`Xx1wd{Z9N10UN5kOlK);2K=+ipkRSh+u5=}Lx={5p9|M29?*2P>Sjpe# z<3A7nv{Cp^3jU?QMd%tGYxs08r%lHHdo5D?^ReF#{&vHsegK ze!>Ju{?US;M)=L(msVG4>2n?R1FSxt;Jxr z0jr>_D1U5hYb^FIxW$dd9*D(0j8pZ6=H*8VOlSCHSX(RVWL^iu(Hp=RypRR<-HDj=22Q!*-tzsH62(_#71WL z#ketvMD>_neE*U;F+zRDl!R&w8#6Va3=XyTb#z(wXQ|+NM1oe6Su!`<)}O_1MK-g3 zsCxbC)o2Io`Do|WNjV6)qFC7FL~(Cu6fPn58ZOTsPdQVGH0eyVpdVsn6$+&#-PaIR0l6qFNObhCU5hG<^+spvip7Ei8y+DskMR?< zCgjGsbc)hr)*Nej1<8}@1SPLPXNJ;VgsR)VMkS9?YgRH%>DwR2E*&F?m96d1<9Dk$ z!g0avcpWl6A@od{1V^ZzLTQ;5N>yi*1r&18K+jNDV_#?2u*&TsYP7s!VzqR&cRHjb zlU!-SwE|KpP&sf#6zWZ^xY~VyU8yTdXOj8aDzKt&Oganncs+tSP(z+e^K4P-RwyK%hcunoyOvG*bu(R7ic(LJBEx&LM#cX=zR1;qX>O}) zX`%?mI+PlgN=^fD#``%9rbzZq87B8YGUH!1oVN})Ds*Bc@Nvor|R!JRBZB<(pMWd@fbCgtZTIv=p#ue6Onl2`q zZViYg1GGt7yZSn7)^_qGyo4+tNm-t@6T4*kGnD(qcnhg7p{1^7Y2XrAXp*j38oUIe zxR*dj!Ao$YDxRjrHC0U^S0Lp20$RE{Hi!%O5;A-wWq8^e?2_qT%KLuo@>I0dix;<< zlIYrig$`rU;@Ub=oNEK3D5*}gy1#!24cXdtthbFw;Ydnm+E1}drhkEb!3S_Fo1r3= zC50lkeh)pX8wDXI)mOmXSN%)1$wzNg>Vzc zOdg^Y+)T|Dl^i2eu`L>0)6%{++cea#O6nA+e#ijHY#HiTwQZW8sR9&p@#@usT|?QL z{(%8X_(+E-0~FI~3yD{LKI)vxpet4^r>P=V`uogs#oCbE@1W}Y2dLyove~#hu(R*M zt~Ry{`!O~~dH45pT7|J>`T+>Wnu+>jy%Y7v`X{T8btmeN<%#+(i6`oh?NJl;-2io* zUnD2$Plp|f+===p<1m>%7kj%MySx}d+_A@+$@^|xX7av?OwZQu0a-<+56M@oy&Jm; zs=SZMN7ST#6&X+H_r}N*`p5Ew{;|%4etniRq5sIop|5c-A-ZJxRf^QFqv>k((&=jT z(&=jT(&=jT(&=jT(&=jT(&@B%>2$q%>2$q%>2$Sv>2&)YEtwhw_10&wUt3H2zSd=n z@YA2c-mG4VU$c5CkXgMHh*vKK)T@^QsMSmHt5z??FIF$b-dVjASgl?zziRbT{L<>B_))8uPIp!> zg+#1gnz|WZXsF%~(*42oQRz{RUXIxqqpB;N42|khPQB3Bl#Dd`Pth~>@}6}a)I+zZ zr=R5mJk+gL%Lu9#NkjOkqux0+R&{-9cC6BfUxsy(xHqp(=7Ts^Ng}Sk11SX2fLiKZ z5f!4R#6ZdrUdcK0WRsrU{ppjHd@|6k80Z?ZRDKB@wVVuUr9OnOWMuCF^u?vU&-d6{ zhDK_T&qizSC+#6Qut z45?noh&Uk{rpVD7bxRfA?6Lubdn#HroA<>eu}ob`x?$`cSTcn4`W1X`PZYh z{3P`*HD@~?ZpB>24Y%GEhi*Oov^tf{BhBinUyZo5kD@OdwpH>Dn3<}j`T(n6>!`OC z2-T~a=vo^Hj?{EV+R@tXTpMk6&T6}S?cf@%gNN{TBcvrV!}| z)I#m$RZa}v_^4Lrh!8=W*YSHAOFfskhX@>A!*5S4^*G`lB5>ou7901yEe(A^ad8DS zD%U=WKK|I&g#W@3l@aQpnOA>p{cb6tZ+_lxoR1V~S*eS-tX!$e3Rym^KbO0#TzF9T z_!TG{`ZXv4>PM`i^+9!?N<&z5v=Zcr0Nn6K0|Dw5e}HZ#Xqz^=?^)?dFe{D`JWSm- z{eo46x`zn#_6%fs!sD>FfSD4finMh&D=h8QQtr)erQqbxU5C zr{qyqOv!U;k(Rw{BQAUQ{Il#i@BH8DvUgOcDrA#Cn&!sMErkd%-x*b_=LSSrn!2qE zqWidr=iY9sS$$T_*<%TNK0JhnM)UC&noD4`Py!>d6IL33 z4diQp7UkryT7=bJL!J*F-aTytE!vs)M$MM$^3Tr3APh)r=GaR=Y3<)uoqV>OLJ{+o z9A0U{KV=of9>!v{)ye&jedl}2Mi#Ezx3tc#-9DqeW{<n5APlAL+~EX2eLxQ&f0O zMN@Krd}lfFvB0fL^N9zi_RBMJ#lR^vC7)0+q7`-W9P6(;v2HtEbP^=KR`g_9q`Mmy#!v4W8r7HP3?4ynRwTv8Gv-A39QHH?Z)<=SV*QOLHg2cIbPL{CcqQd29>c=H%0I;~W8{5- z@>uzy0&Ag)ry7g(ehT{CpR6yh-A3W{N!nkp>`@16(fRpn(jyqT4V%aq>U=TOs>Nz+ z)%jX0jaSx|SMRP)=3{}@na=rnvD)JN)#;I0Lei`x$2bzL$#SbvYZAF@gcj0Td(c$% zw&vvgk^21o3f1RtEqu1THd&v4ZQ)L{eDVGVtGC&)=9AA}`UFDek2K`(EHBW@>pobU zY`_^i%Zto0#nymxUq)=tZrgvNUI2MN5NQ(D{b=2e+S~a`nw(tLsw-RM9Fvt1!^7X) zzHrCO*f;Db=wGxwzOwPeasB$ZVf@bWh1>00<2UTtx-+?}_>b+4+mCCvkFR|=zI0)H zKP-{|%C)oVx2M{xw~>VOus=UmxCixUibWbnjY(E5eb~~mEZm{e!~Th6-Ey*yw!S~l z?{o5~^Zb72nDT7&pz>|5UFCk^^~i5=@k)ISWBMgehrNXSpVY4OdJV1ud2Wb5oWHAF zU&Z8hZO3WIIhS8uYHIgCd|fTd?~|(h{;<43>7-!?r{1vrn>+NC{G)jYS!abT)@vW^ zV!g#^XD41oi}emK!g9Mj%TcwyZrJ8S3ZvJ-CeGN~5h-3RI2*k>)L}!h24C3GPS}R5 zKQCz~Y*TNwg#87#ow!9SbK15w>F_Mt%P-fW^$4Q6 z4Y=9}yFK)XiOq2+@)G&qSiEt@`3ZZ5$2kU^joeJGG0xsNV}(CV`Tcm5LUG!Yp40N; zIPtIKNTefC7%MJ5Ju&X=y?bM+$$R%E3cv7hA~7ov8J+Pt%0?&77*~AOgL@xJj5{kf zaZ;kNBNzW?#9x(|d^a3(jGNe;u+I9sj6N$$Yg=c>rB3#9U z)QSrdiJ{O-eNS9O^Pa?*ZFHG#MDI={dJ)lcI-*G>D-wz8op`XyusvbS80|+SmZuI- z84}VLNuKsak{Ab{A{ArKC^9ZelI)u#Kj53BV4{hraI!TKPmV>duaYrGTc<(-SN-vV zF=NgJ9H(8DjGqn3kvJ|U-zAPWj|tNCi0dmP=%XYRP7FE~DUn2WD-w)vVi?VdEpdJ2 z80E=i(x^0N)#J%7Eq9WoK~gZmGEH(6G-bZB)p=u$S*Ge^b2RNVyk7Ej zcfI6t&w9y6$@P+{ebqg34E{44-5Y50|5Dpe8@2PaQJYR%TJ7ESm8o5(joM(j=@j&A z<$4vM*G;ZA_zbkp7}kx=&Jex>f7mkAYS$`=*}D!0v!n&S02jfW%LIPEz@HQN8v;K8 ztkX?dH1PNom6n|$yusw*$AbT|!@=5x0{;mQIGl$gaIuWf5%_#y9e>KYPRQ>Rc(=fN z1%684p9)-*aMPkOna7&^6FyF1D^udgQ`RiOUjRJY@Cnx#{+W(EWsyghS|v|en}AO+ ze8SA%;>c6ht%84_zy%mG$MK94_$YzT6u3p;cL;o)z#kBJyTCUIe7nFq1-?t*{Q^HD zu!XnFoabW%t{1pl;13A=?*iW=@IHYb7Wmr&|5)JH1U?!ATR1=U0yhbKp}?yIewVjb`0;4cgOGl8EKm^|cgS}zFvvcN_7KE|Ar z1-?+=VS(=uc$dJR75Hv}zbx=~1%6TBNw}+V9%#*L#vKCFn%68}EAXJe!vcR$;C~bN zM*{y$;AaJXPT&^=F2dwt&ckT}X9a$rz;_G$9|F^~YL182wr1Qa@Fsz86ZlSncMJSE zfxjT|eu2-z+ip&)QQ*Y_w+VcSz}E@9L*QEk{)E7v7Wid>|6AY@fj^B2LKuCG&CU>h z(cC*e1I&5e=WtTiLjpe{IJ+>d&N$sGdoCklL=z~>6w zCh$81zFOe-0?#+sMZ;benCl|^in*>EfH~byJDilYSKtp%b~&FB_+f#c5%@KMOH18z zPZ4+_u+C4)Y8QBuz*h@QBRJra0h^s6{B@K6_W*PL?{GLNwMLlcr>qZ^xtyH>-zV@B z0zWTs0uTBe53Q@k_$+}d1*S0vXPJBwo`rrAw#-6c&gV*pld?Jmz5pM_nbRroRRVuZ z;4cdNJ%N8GaKSV;&Y1$A1FZ9zvK9%vLf}q;=~MhU=DG-*HSsc+0dt<;<8V^eHi7Zt z)!}S}%M<3`An;uRKPvD~1%5@~vH0xE@fzf0hc3A`8h9CckOYoEYR3jDOd z^toA2C$=+$yNrE*0nGWKg+w(69-jm*1ZK`l0*@_s{qrevmoD>*MsS^*(?%-ntmT6T8Il92=I_X-_?NY;13FG$b#DnT( zp5wA=4coWlm^kRV9`IZ=71na1gO4I?p3!oji`%agCvIO(ekc!>_~UpkH8_o5)}hob z*{BkK#78&Hi6>Y5^t{FKECJSKBdfgsRO0wxsYS=c`lg3}GFom3h>W<9!P-+l%ll#kVrAIr5ZsWQ_H1X9zQgyzQ}FDuLN9 zgtZ>546XLew&(>u$K;3bLX#GG*41+Kdx2U1gsI$P%Y4a^Q%!bto&>H{l9ck-!TO&7 zS%H#kPkmahJ@v8vrw9&V)_)q9^-q}Napl@mAM1a%;1K4zLvgVF33EKITzl$c{gW=4 zLzwGGB`_UR8Lq^hIfS)bd+KBTHwX@4)_(?=^-q}Napl@mAM1aa;1CX$`7lp?g~~G? z=v+>4e<5FawCS8+rj3%!f)~EIkkU1{zSl^5lp|L%4@Vb!B&5|#Jd)FJREcSAslKeoCDDR3OikA0a`W zkMl~9=M%jWe3$&sx^FzVdvYV51=^0LOH_k54FKz z9Ez57LmQRBxJ|7EvAtWnIi!A3+`ir$XpYvKU#d5`IPWza>W9Q_e&cV1=I2iHOZ_g* z2`XTp;ZPqY7w1XCq4FBHsb@r~dbi)3L$ZC`J|BBs6D2FpBtKqpj>evPx89BY>ChF$ z?KJj5PNj)wg5q>yZ(0~2-q>#rwc>G`>TobW>?@~4ak@e|>>p>M;^pl4$rH&n{w zHhHfO>1T%H`kf2r+q~ma z?N3bcgYnQ}!L*SFR1M3FgzBI^i?rt5<{A!pF4b_6k+?qhsC;<06^27?osOC8>fMG6 zhuSF3A-j4v`ffy<>jUs;EfD)V4TpTRYPioxEJyPFfaKYL=noB=h31Cwg&F?~%9)MX!YDu8FcT8mm2wp1x->cCA{!CfnQ7*TuM}Z*@Q8_EoC}x;8jR1MPilx(0*OD05D{ z@mftCg=R~Ic>JKalb)Tkc#5AA1SX0oX^2M5>3$0+u_r}$GPWq1W-gMD@XQx6i9v>X z7w(<4YJE>{=PB(&(DthJL(rX3`09c7wO!WQj#Y!}PU&Cuj#JZWn|u1{^X62XK4;Ep z>9qC-DEH~~nWxP^&Gi%5V%>M{-ky)v+1962tHpi-w^2iHwiEEXA>@`w_Y1mHsPbaC z{BwHks*9@->7%KwkRpExYQd-YSAc)@DEx~BpY*dG{5wbC5BvCE0sot$@OKD4<^QMP|85limj$2lle`Ph zI;FYw`K;hm{3n4wZxntWb)d~g@wb70(J1_xKK^F#uNZ}2CHSQO+rj_%DEw7|Px*NQ z{D(&2-{9l_75rb1!oN@ODL?6d!_#e9Zhihl@Mn^Kz(3XSxv0zf9ur+?;@=GZWux#< z_VJ$qf7d8{8r#4d>F3zHE$bJfN4|L7?E8RC&@KH`55`1g*&uNQpE&mX}5*(m%@AAiOd(e6*p ztqw8G({$-=^ zpA`HF;BN>2L!zZ?87jKUvFFBHsHg5RgW|Bq4lvju+=_mu8?KEbDF=LYZ>8-7@O_z}UU_&0$6zER@eC-@Zq&EVfVO8mbPeA4G5 z;QwWm_>1Y~i`k~&_YdG7ccd;qVfm*qLcCG@+9vJB+F;B;GYWqH^BeA;q$FT@_PlJ-nGyA z8v0j9<&OV@f2c0cN)dHKgxL&kpuM*{A(_`3uzE`Klzzf$nqz+d$M`iC=ge!}wKDfo-P zFZw#l=gi#sr!i@~(L2;ng74od_327{Ysw8RfI(+Gg!a?KZ`1_0UhbRBkBa!8Ls>oH zQS^uB>InbSL`Cg3mknAqkGFlGO?rxt++WGRPwO?lVIPF{@xv2gT7gTthw)TKm@zbaYu*yB_ZA zDUG6sDWRz-8G+PV4wPDeU~_6M-qgNFsZkn5^C+PYh}2qJ7G{0%WSd$uHBE3^YA!#F zvIvA_*-T?IilMne(0s|#x-6xXSkb2`#XOW)8K+O1VafU_lx&Mi)=?~y_38GDlq@Ay zbTp+nD3V2dnZ-?2Esbp#XImOu8=Dtq>uMLmkmgclczsn40-Phh5Nd6j1o)Rs3l~Se`XX4VuwKzI&Xk6GJO&i8(T6_`Ob|-ZwRafOP zBveYN6|JKr9~0@qeg~m)u)>tXhRNg9TY@UzOleb!MbA^RwRm~M*Nj-huE%rDIXHC9 zVX3;;{0gN@sTFlnlHV2S>IP7^d)fi4X#`Enm}$(CINQ89TU*yubuo+^PB5WU`0{o8 zIMlyxQGX{|$UdZ5N(mSJno_5EBYf%Ajcu*jOkGR%qQxz>*)tpyd*yR0thA}tzJLW* zWoQ7tvabvem~U+j4VYJ9-Ol;1g%k4Xo}s}^*T6;n1D#gvk8}l;@1i}F`BTt^;46U3 z;7nC>Ej2IAi<|45EAYwDBvxnZ8(Ui2tOAq1U@XZtRb7;Ag>UEy!N4jf&{c5%+I8@( zjxRG>!(TwIN-0-Gjg+-diTqK;)#l4WciA~k27LkWxo(p71ytZeovBo$m)fr0_D!T5 zE7po+N-3?PeUxAuI>j6ZwGgc>rp2P0ZA)EMEeeoH!W#_V(b>iI*=o8UI|}ep-1^~^ z1TR4~kaaCBi(4>0$Y}$dPi5TjeT%Y887&&1+|u+L&To10>nwqkg z)U_;jdIllkt&Izt(MLCxqN%Pvcs}%9$@ys+ZtYpqS2sM=)i>DF-=|Ht1z9Mid=%y3 zA;-Rzc1BCo+PF$=t!rsS$Av12qem|zRF7Uth#tL!Fg>;m2lO}|*({~J7TrS`z7)?N zoNL@`Rqv{ys=2wYsWn^ITvgpv=jIu9tI=U7@J)3!ZHPPs%Q;YQ3PYRz&BX zV#SP>S}$I-sIH~05gx#o5z~p(?a$y&kCi|Ax_Y(B_fzI6%SGhc+Wx-C{GugIh{y#d)Qq)07)#4eF({pmIYo2Ht{2^}J;15CLV9ekT znPqfL{>^M7Tt?o{;_yKF39Up&jl?DsjEdJ z6UaZewG2-p*+7WHt?k*+(@E=m#Ae$2@Vw$sIlwU0(?*+GYa&KZ8-~YX$!bxoI6Wmu z7Q~u`b_jXYk1t3zkNWkRC_^;2&C5+tXIyh-h~}y%38&|Qn3L3*)@*N>%WskVeCiIn zd^e0OtU4AjbNgD{ejX+hkm8HZ#V(Pq!9M>AJb~xu4N_m%*rBz>Yl@IC#jhI}=pU%< z8tUp8QpQkrBeD!oOqB~Z4=yvN>_${ih~j3}_YQUmZrtH|LUfMVm}C^{oo7{ES*kc_ ziCxPjs1L13u2`|^TbD__CaKS>crt*Misu7Lht=8)HI|YZi#~!~B7HMy^s{&ulhm2~ z2UV-C6nWGG7iy(CK^I@&>J~O=KS3R4qcAss6^7ouRM@AWpi)v$(KoP5q#wmT{|k77 zJSMNVzkl7T_KwTwzT+*0fsnkRjs2>Dkz899!azvgx}HAO57QpHIp&yRhlJ&=qn2x~ zYPy=b`qm6}Qwi5aF&L!T6+U*JD!7X63DQ-$l{@>SJnHJ}TI`5T4yZTnW*|vD>a5Oy z2r=mk2_nsRxfLQL4-TYdPZ-Ps>Iaj1YAMenH`H#|6|_R?xT@uaTyb7cpK%hcItpMF zQD4zri%f~R7_<$mn}TVLo`ls)$?8Qk-!qZ^KKA)Ebuz+I5N1`~7#*xtMHx7NRr3zk zstMOpbETzp(Ge1;SCoJQST+CPtXdFeRa(gcy>7N?A@#PiQW#=)>f7e9dyB{JPs7fo zWapy&*d@~6!ao0+Qfe+u@2{qReczD2b6ffjuX}|o&s#S%VESx>O<4TT+~gml&Ok6I zZ>{K9(j{qn9`$FlAz^vzxbvxr3F>@irO++UzCNqE%RYhYDW&Tv`XqLV^d9WQ{^-%-sy9iBSOf!*|dXhK(M_GtyvpAEv2qgLY6nUu7}IB z?q#unueLSQxTu|0k|Y}6+dqtpE2WDox*WSidIR?PlaS54H*v9|$ycwH{7t^dE)*A2 z&4Q50ONgtEV#p=5_O@^6l2`Cf~6MEVTuC+h`l%)&K=-i2!l{fn{`x(nA7 z^1?MPi5IRZ#I3-x6K;Sy&M%M)*W8A*3*3ck_Noj~4KFlH)wpMyrE1LSdTpAg`E-5w zdv!XM8Fe}@PUDS(7pE!Y#c2wi#cA|e&f+xgd1!|4cu`P#A)+qo!P7`0-G_adTAZd# zElyLW7N;pwi_?^;#c9ga;xuKnI8B*eoTf}KPE%(0U{#tjy*N#oTAZd#ElyLW7pEyx zi_?^u#cA+s7N-F+i_-w{;xvGIaT)-%I1PT);xzch;xyPhi_-wB#c9g);xuJuahfu{ zI8B*ZoTf}KPE%$Urzz8m)0COTY0C8CG-YOSnlimOO_^Dorc5tRQ)U*YDbtJ7l$ph8 zkiJ@+2ES@?8vLroY4EESr@^mUoCd#YaT@%p#cA-X7N@~4Elz_UwKz?gvp5YTVsV-Y z_fNMh{hetD!>9+>_6*HkfY)u*)oAYTQ%|-uAe%NCWMO9yf*g^*JpQgYFRHa-Ie~NS z%`rQ(3Vm2hwW$il?B&#{)3+RjCc!hgj|9<`KGqbYv7W(dM7XrQ7mHuvvD31ri0_BE z`;$QHR(TwsyI_^Jf|`eIPepeRZwDq^g?TGEEa0&f8s6Nta+nbtsy=E%E&HD}RL@}B za0|SyZ&LH=a@h|ZHhiYVZJ+FS#L<5H&8s+s>K00l*orHow&G=>R)nv8Rg+W=P9*L0nc?<#H_JFe5h0VAN)L_u({)Tb0o7 z&S@=ARr;4%Y^{N=j;@{!T{&-D>NL~1j>e7HVjqawVmF0a%wBG;xt4BU>M=+P!tY{R zBqeZ8ShXAdo<`HF+*=ynq@qbw{RwNrJC4m|N2e-Lr9(&Dxuf}w=nx~e;O$Xc@b14~ z3-%1Qgx&1ChE*n=s@g|uLd9&KVVyS8-?I#C?rqUiLC2hs%Z^UH%TYlcBRa&0E%@E2E%>v)Uki>>L0!Yj3R*n&BsMIjHtW}n ztv#E&$e7A&3qS06LnAifucJ0$0_(u!e7w`2TOUCASMTc0*H?Q5`isu+oW1lJK?-8D zY!qIg5ksG$-n)85;ni3@Eruov{uY@?Al0xsj_-5czAs+BdIh=*bs~wa@#9Ys1wema za0=KwSN~ z0O8sPH5Y;aA>wi{H}Z0@-nKV{wgk@S3hPzR*9-WxSYf`hcs@N?IVyL~c&Kvcis*_} zYB-5%LNo+>GnxXue7jEAJw)Ipb{`=bJ{f4k{hgiaMy#W7jt;6J$x)1|buqfRf{T&% zOyDg=ie#D+e|W@&2+J2noWj@tS%_%G#{ZW>RHX~i&*yU?GEI#$j*gllM=riaa z>F+EZ{e7!@)~p}Ezy~$ljtY^bdQaw#79d1ij8?{?zNLL4mg5PDMpjVg#C+dxz|cK4 zWJJi&&j|S_w&fts47-B_UMiaB8EqQ%SfVmy#wcQBocr!rg<@2uB;b>@hhV0iIfEDR zb;b?X&4)X#Q+Y&mzVeuRln7Q2ReTjl9YOTURi)44G|=646L9nIWZ*OkpLz!Et?@6N z9Vmn*!wA=|ANhvp6hbCMTnP6>UI>5sk5dSZ&T|w(HOP6iLTDNmrwn)sVUBWycjlgQ z zldP~axjB#@C=a4hQ*VS?F;F;1nQGHhWI`r8`dc_BCN=&WFQ|I@JC!?Lry)ZL^O7#= z=^X0j2J3h#LVOjf!E(twlT{Tn=5VLWp^5SAG$jR{d^bX;qo0edTEeMl2dNxij0XkZ zO4 z3YyGp33${N1RYCATDkmSP)>7nH=gFORpdNuaT&tpXIAf-GC^!2~?K8>{!Ax#{X_ zFvp`>bKjg5Gmji&Qrz0X-6Hp1hB4%Bu!@FmWjs+ve{)(OIsA~o-x_h3IA8>-W^rEq z5wyz){DGS&aO%5gZ;iVd_0(6}yfbw`(+c1=n)yMD>3TCY zGyJ^&Z8a13CbwqdfJ^Bi)lA&7MyZ+Ja_7`7JuH&b^VLk`gqFGR-nN1@Q$1sI6uRy> zdGU4!)qOJ4IJ!wVF99%w(U*wx2Ee?UP|xz7Y^V-i$Sbyax#M!u z!#7AbJzurNeOwK$@+9Uw-r*gWd#0*zPEdm{$p2vHe>U^?aWi!ORP}sjjjvx4R@#E@?fM|?ss_3WhF45#*ZzLEuNPp|?yRm5Mh#3Q1=V)<)NoiAhl z+S5qkQ&k)yE=N)h7>DRb1m_If_9$o~Jl9Ka`a^`C?Y8?O7DwKr60M3RjTf|-d8`Q)=Bs?MKy#Gv1%WWT(wW<`q;h}-W;q#6u+!OAypls zD}Ai6A|3wGb1Jo#wpEf^F7)rc8wR!S4Ubs&e~euBuaBzx=gGOz0d?=P4qf-}xRiBo z8e#FapOjA~^0v}~5V7{hMEqvH+bWG8tG70C^|s_11kmIA7`Km_Zoe=`EAFR-o*PyTMs3?u z_v76x_l0>1DH&-R{yZIJ4vg43w?uB8T@e(1JbluQvaf@ciNbG20f}#~q*rg@4{{<_ z@A`;eS$A94z;^E zn@_KS@QBqqCvvr(9i3Vy_pn-3PsKMPfi&xFs{?};B3AB&kt;Ww$k9~${G~RNb5x%! zM?>vng`IiG&2-7Ocd(^&0T<&4eFFqT>qBmO#1?#SycaJ zJJA*P$NE^Y-dku;uYvH0)%v5z)%wfm)H=M5)vBI{LT<6t({|t7;-i;$Twuh?eJyh3 z7AF7BZ?UHH{=(&KDQ-C2MXN@?#~zR$u??q0{1Lj_nwgBOYu`D@YB%l5!D{_L^oW&S z5xLUe7M;>x9b%=cR>|9Mq1&jxQSve(R_)@*Rl7V_o0PMs5@FBAv_Ie6AZ+3c{*m*J z$S^bU=iV(sX%SneFLLW#k;^)(Y28Nkb&Y5LsZotVaSm$*i8;`{&CAxCW54@7R-TXLCp9jy!GxmIPGpg4zVgTx%?zXhhf zY_l+J*dU{zO~Y6b8}oCK8}r^=#_YtCaK2$opDBh}eAJj@*1djIMui#FeaA-AfZ{^XWAZ9$72gQZI7(rZO5FcbgC*xtpDFeuKz#h(!X(M ztFE$pEUX{}Icy;*fpZSQE~Xv3`g&m(?-Y7>!er1wxtI~#Dp?S9Z*F2ij^13(b}5IQ za`F$|Mq{>lY!qyv$Ufe7tZg{Rir6;CM{b+CT($|cPdRK7;2nZ3Ognbx`#iQ7y&c1s zGci3mV*PK9T>sbQ(!Xqzwv0LSb}VqtA=t&VW9NOqV;AS`rkOz()`Iyt5!>h1$nCQy zmwjj{Y@>*)xR-2>bJUbk&Ny`2{P=^yHe%dQPTK@I5!>ee$ZhlJLD=Sx2~-`S`2*X= zf5xHPX7C1K8#BE%r(L|^5!>Xak=x|CTsG+-=e$M>-?phe6M`I8k(9tWhi;cK+l5`w z9~K!1wq@S%i0$%vTDZCO%BBq`jgX7V?rp&O3A) z-FcI+k-676ISZ>tHOjd?yE=~8Mw=qH(RBxBqZoCqz3M+G8-<*A$Tmv7`Z2bVcXdfJ z&jkFb57v6{hnEnsbv{y96mbf-7ryla0kKE}URtIW-6ECht_Vm86uA+!+6 zRkKxc;%y$iyM>kXPUFO+-rdlM_5O><_5M<5QO5d{o0UpEYo+^r@`Py_&mCcoW~e>D zqhjoh>hko6wbHuZ{!(>uvOPUgxw5)A)^2@i*Nw4u`~IEV-}OdPvHmZ6=K^0varXb& zb8?as5(rBIA|gga1yKkAxrj<`go|8`AtG8e2_!%?5KIC@L_npAXa%XoyVYt@v{hSM z+p1MtX>FCNZMC)4T5GAbeZAH4w$_)D|L>WZXZG21P7c_bem?L2|6j;C-+kt{&pbOj zJ3D(hvt@X=Qq|^s{xrqTT^totMDXbl2yeWS^-t?x>W?YLyspbaWrY%`sXVtb)0eV%s+ zmAY9y@y_QX*G1+<>b;v)O;Co(>wR$+M_RFYkM_MsuXlKTUKA?wy(g{j@G^sA>^VEb z_BkIKabD|Goag`Oa!+3C`<;%w?d!(d51lHWVGVwptmrJo4&P{f19o4pQ2_Bxj#Gou)KfbZOE?aTW^-CL^*8K?GIAZwZreZe5{Y%`}MYGkLi}l zkMs7*53P@#OS?X!+%n1QW0nf94|^(T4N`;k;nZ}ot#|oYmEAitE%PO}jIB?*yZ%nw zCsXah?>6mG(=GEq2U_O$smthkkSU)?Zc0A;50uZ5Da-s_Z_`ZqOi5Yhe-60Jc`3{M z^MK2&Pg%y)HyK;Ft-0APQL%Y5l%-2fEFb+g?j^)O%Yf zrfz#_d&TBz=#qV9*Q+h{YGQwRxBAhgBu1zARMawL<6Lz5Yp|hiZsf_hhd> z6RMC`)?X6z8%?zD=_RIZ+fb9eluG!0Jzu#kufAgQzTHP`sKOo@oj)zU{`e+pDl9Q?qt-RIl4PTtzBt3+t=471v}fdAe)b_P(uCar~RUed@O9 zx9`6-I)A4({rcFg)3#@6`?T%T`c$7#k<%x4=VtHb#a-uh?Rsic+9<9Pd73rfEG++i z6efo16DW#ZH>Qu_Ws#$a;TOX4@5ewT(f5EQQH*m9QwMl^94RdSeiSAKSrVv+ZZD%+ z*c9Zqxgz@|-DXs6rfvUH?cn-%&f$IToo$htg8F@Ke%H2`-5;}BSyPd{+b&;`y;rn8 z;T#_b<@j2VqxV{Ezxq8chdtY(HL?1=ZeDud*RA(=Lf-cT-s5{}`-}C#8uopsHotz? zwqErwi99$SUV|#M?8$4I+^$eLj={N^-I6Frk#E+XjJdpHBTS!5_WtU7xuvCCmbqN2 zH`5j{EpAq;`L4=VFHw6^z4^6m<=d+_S7q-#*H}z?HP)rKU8Z{T9;?}RuBVrZN2+m- zU6s8{N0b|ytKR%lN^ZSEiYu_ECrA6^gN*hi8_7Evq7Bx_L`!RDYC)#BQ)A56_5ZYy z(?(7oNo8fOG>pXAZ|c_Dv#q&-_W-Wr?`%5_b*8u`+Wh4F)4UlYXO5gY@|4!83trlM z{kEsOs<&5{4PG{5TW)=|ty53VpW#(+L)*Biy3dY+y!xumFKwQ>ZP)cX&#kaq>+n{1 ziVSL<8Cq&4mYTkOx?ZXmmZBUgvah!#6m2~XXNpsM;V8FlYVG$H_ix>W_T0oYb!0Cc zk5+F{`dG!vy^BxVb`7>v`cn8XZ7Eb_a~<8Y&8umw4@zQYN=cj?Dv84~ltk(}{rlzc z{ZCvDrp8iRu%|ZGfbW5OYNw+O;{7Gaw9B?&`3CK?4t_3BOJHxrvdwCh&Zh;m5VquH(`l9=f`#z4LXAS)H2v?5e-WY| zhQBUMQRR7q@{3eFJDwAd$8+Po;(77G@yYQi@ya+}h%}H^)lPIlws76es=RRR>4odc zKb17POm2LxsY&*kDeYg4C6iBjWZtgdf=?1lrsaAf&P+ZttzV|)GNlFUwz65QT##Q|a(Z*59@mT5V9JCXHyMzYU;b-7?2)}*x8)UMn7<|pU( zuP%3d;Pd=spC<)roylpHE^Sq$9EtLnQz6pIlG6Uw%lG18jT4#hRq4Y^FQ!?AV zGjbZz-pW@hs(uNp=cyIF@riFec|AQ?EpqA6Tj7h$dc^4VvWj`pjj`Ub*n2TAQs8Gt zBDB6P=_X40OQcsnq{jLrr+z(S>Wh>biTZZwg5;(Da)9)!voq!W<&3F6pwuAmzR7vt zk`wsOPl@br@yts3M`g<9d{&mLGeIeg@ zDJ6Piex}I2o-y?WN_BCk`hL%)_le|ERm@A-WS{HJE?ANh;a3kVd6p#IR`)#_Q!nqs z5%i1nDMFBaQX;rtN($3TejP~CuIEPwNWZzjMG?!5#QR4I22egJJNBQ1E?s$E**EZ$ zE`6ssI2hvlswNR>s>!a zbvlh~8Eqf!BdM_?AJM-mz5S3LI7z4boM+djTTgcgMP^@*3T4V+OGot+p~&p(Pgjr77;@{!!|4yB!L&!Sbx8W8D4O%O^w66=S3BdcGmH_b#3#Wuiv?jS1H zzHkyxE%WG>h<1X5CY&I@4--)z(u2=0H%)$BpVUdZpr4C=!ZlA9$s4-( zbax>VD?~xX3L{xXD7!5E?MI>okt`qfXb}o9)*q#kv{UF(*%|aI0yq7&8`>Bdm;Gb9 zWhsQ5qDWSO&eixdpn=n8E)p9+At1&=3JmqV zZ;UortoQrtV*bXzM$mZl|1fqailP5|vHp8whmx`vjFIS|WOHs&%#Yr_{@vK&(e;;1n*FOI}LW5s@UXv|v|IwI)O{~dMBB2gDtA!Uv2-d$XUY2rcvF0P^=TpiaP zBCd-*L0ot1W+qDYH%`SwW#sBJ8VcIFD02D_wgrjpsH; zeKX4PI8#56Ws0p|AnQJ|LL)jke@ebCyqYyjMg$kOIzv&_jP5j+mI$fxuiFG{Rou2Ki=Xw6_ zZh5vJWwO&lffDjOFVEj2t&YEWdHx<}(|Ml1yR*}UE}B^PNxwNRx)4PZuRqVz#VeYU z=Xp840FgXT7mR44i##-)WWH3T{boDQ(}f$F=pqeGbU}uuvF1zBg%+CVq6$ryn=eHd zOK7S!U;2&G7WJ2@QIQ0Gv!_<*%O5^&7b(?Zc{0A2TRv0pIf54o{+{3;3Vu%Ti-Jd^ zVzd8of+q<+RqzhM_X~bV@HYh?9u52t6@0AV;{{(Wc&p$q2)Flo-y--I4E+yvjkr(c&Ff>3*IMqI1Zldr$+Eag1;#EM}mJM_-BG& z5&Rp$9|<0YgFWYay5RMKcMATQ;QfM!_YeHc72GcP2Ek7W{(<0U1-~fxWx?+WK6F5k z?{vWz3cf?|mj&M^_#wgH6#Ts4e+V9qPLV4&!5ajBR`6!QTLphX@I!)M6&ytei}N~0 zaHZg7g4+bI7JP}|%LLyh_=kf3Bsd$xMsW!7MzO?Eaz1q z_#PI7>s@<`d+xc*?*=^n9Fc1m}8soG`>1p@XQf`W|81a1m7U|aj?nDS3eQF zM{t+m*l~eA4?NSxN$f=wO^JLk$2rVtd^KEfpOJy)Xu*|&7Yn{j@Xdn1BlvZ&iN{y( z3s%Pm_H4oV;8`|)V%)*k@%ILE{6{;DuSN*&dqSW&R`688O9gKfe5>Hc1it|`@%ZX5 zf+M2>dt7iI@EjXI@iZHM0hr@I&S`u#O7OtZfo8Pe8G`EsuNJ&b@J_+s7raMstR%?m zSg?uNR}%%#5Ik4#8Q_FnN8+h=9p{629alJwuQ~*uJ0{R{2)_3C<}E ze2x%2Q*aB|#O$j}1Yaxodcik?YwS7_^LD%i%-{>S@3@ej*biT zLj<2Fc#hx|g0B<&FxbTGt6hR$7W}H<-+^oGIui4Cd=t#;xX)>PrA}nMul@vPjT#^D zAi*Vqrwd*rc#YuC3;w3yUkLsPY-09R?u38`2`(0V40yg>N8-=gx_T^_poyJ$c75tMaf#y$wv&#beQG!nco4kB=j^K5I?-KmH;12~K zQ6Bi2EqI>bv%u$h3X_*0?vHE4m=b4$dA-&+jjz@TURDukHVM94@Kb{S2sU~7>LbBL zm4SVX;JJd&7kriAdjx-9@b3jjs{;Q=3N918Q1DX0%fa;?6^WN1{wPAM60Kk^pDj+~ ztIrF*Y-*snP4IUFzbtqk*yQD_-qit*5L_*|QSf@fw+nt;@Gk{_BzWMoAg_sn&lX%S zcrlpnsZf~^)BOfai6vkzldGJ@SDzESO=vEg9_Viq{2jqB3;s}W&WvE$V+79?yjt+> zf}arlTd-LdUwt6B&&WT z@zn`}2hR&MlLVhBc%|UGz$P#BwFJK=_+!C?Y6Jab!F7T!75rtvy9EDM@W+A&oe}sy zNpP9qYVfah^X4UpkJV+R64St3KIb}(uNnk53C)c8f&Lu9OTfmzua<#dvw0DpVe?up z^qZW-d_}`05S8&nyTuzZU!v z*!V=B|Ez!u1osEOVe=*4VDlXS=6uIGjjtvM9(s1587Fv};IjpHf=yn&x=QdC!CwHs zY2zVYYvb7t=6Js5G`{+#;M+eFXdV*$wBTO|-U~K)`6_l!zE4fLbI$f&~FfY zJJ|U5)q{e+Dflt)2Q~&`-Y*^pa}2LIjjvu4{KKX|^DDuB2OFQhiZ2ehkKiKkhc;hg z-Y@!tIo}ee@zprNhc6Kt!E?aIr?2V+HwnG~yw~PSe4nRh5-niPceB&@>RQ2TmIj*b zf*%(AqTr9fCNH$x%>fq(?hpQ(jfZ%pjb{Lu<0*3*Tyqe7^7(;guHa>0;}hqYf;S4@ z4F1UGOMJb}_i8Zbd#}^@>MMe8xFFCxAoz!ZUl;7Pa9+OZCwQRXA>fZ~Jj7fNj{tK# zlbr_l@&u1q7HCcud^Xtl#B*+fFBH5QywB!K%=NGn%=v!aX?%5q;0?=#M)23b#;32o zFZf4-p9k-^`4V$Id;!e)zUwr&_AdB0t%2qrf(NV!>|+Ig25j>3Rg2&@!JS~G>wuRa zUTy2cMPQESZm03py@Kz&FwlHM@Xx@;r>}l5_)mi02S;qa#9aSB0CT>B+F0YOA%X|A z2bvLrr-6-6Uo8-Pp5R7smd%%#>wgoN^S#Vze07E33p)bMCc$?I{!ep2uc!2N7I#2n8L!5q&Xr}5R> zf?rx6Xg(0!dqZG9PH+v_!0% zmjwR}Z1VC|&Se4j7EG^;9^ffVUV@n8DFSmmlbps^rwA^&JkU%NTqk(7;G4lFFJIj+ z_-lgc)yM;FJjB;%R*7$eIi6oRjjw(qc=yIY^IO4x6`b?gKywV(^77RSf?pO)ufiQ{<00nl^%|Jt@vdYI z&V>bk1ZGXarhtzXJVo$Au*u6;?Sd~7ydFHn#zV~8YXg|`y3=WV^<}}=UlnNX5&W3o z7X-ftHhKA~OK@y+V5ire7Tb7;d3)u9Ii6#k##bW+7hN4_P7pjzaD(70z$P#B2?gIK zm|pog)W$=6t7etB8_e-M?KHl6M({VT2{gL}|3UD6!9zdCdHHIr;7Nk%RhPqTJj5JN z8JOd#a~jlV!HH`F%~HXa3cgwJ6JV1U>a*aN1=H&tkFoI(^Y(fT%<=r)X?*oRg7<6* zH2)NQ$kxCswkw}rQkZjSAf~i4T5hId>6RX#zV~4!0!fg`8@74xOXFXm(bjIQ=tE@;8(%MKhA3e ze<+wA?#@iT(J2k7s z95DM|;xxEcAh_n%K+`CAwcyQy?**H@&@UDIq+oiH(L@^$@nRd#55Y88p;CC}!D(>r zEcn^mf_Q!-_yfUxZfE~EPZWH#;0StszoxFAs#9@%p08u5qn|X{dRwOsMiYge{p1Qi zdBV@ZXbvW?gVB6id3{=b4kqS<(R^C*d|H0~lQDl=x^*8N~K z2ea<~UxN*f_VC|n$Npa~!-J`Z2ctQdGW?`|a>RZuk8yoqH^=KbCG+i0-y8b(@JIEe z5TCrPj3*m*KAuutGX20hMR}Rye)!nhojxCWnHMj6uyLBc*}<>ZpOGJ}7qw%bbXn5} z``7Z~WwVek_a$VXMD`{6Lc?WC<QHb$+dn)KY|cCC)Un_`);{ zZ?4H0|3%jSF!;%~JOUiIJPLfA<#AwhU#U(_1S@Ml*nEds{b5*?^C|{&UPpt?Id7e! z_4*tBXn!0{U!Nc^AM)2}87xcn{58w89pAJ(6yLL~Ps;aWYo~noS*G=6&1CR?Yp=j} zmR)u__$_Onh3`F<=i&Pu%Lh|F2OIND5%UMuKgIl^Wr~?KlfZkey$s(US)PXPH!RP= z_uH1K9p?6j+KuyVUes>OHpE=_tJCAmm}{hU>Tqbd49A1bwaPk0dDU7!rwe<7uwNwj zU}G@XitF^?^aHH_BjAV2gzD!&Yo~3Luv{bT3x$1+U^>QeJ)t&}>(U`$u1kZ#+&&b8 zxqYCz)XU~|9GLfgs>8hBjRo_5HvxQ{)t?0BGAsvk-J|$E0Vp31~%d{qxN+sjK3v%V3``lU|etF_=a@JI0wvwj1Z^&7!& z;E%3L+=x$8H@pNf>u&|K{tl<{)i=O<@JIfMS^sS?>mLUjjjvt=oA$&@5VQUzp?}3` zaNP;~HvY&zG3!47vwvy>j0Vpmp{|*Jj+Y>2eLk4=R2PiK*VnMgFZmxP^uvYzc(Bp< z`uEeO&*mk{guY7Xr-O|Kzexd8tmL1V{O=!ZLvuTBOl^Mj)T4F6M6|^)@Ok^ zp19NaYA~4gH!6Q())x!?FsH%qbHV0V<0Xh$f3nb*IgPJs!9~_TG3yry{W(tKs}*2# zJoOU9tnU!|PN%^$8(?#s^%BIar}4yieXn;KJU0dAd&_ca{O6fqw&>1usJ4r31Zd{7W!hR z!E>8nYBy>760?4y(4XuyzDj`2G1^NIv%Xg77dQ=`X9Ewn{)t(?Lg+i3##fub<~Z&p zh*^J)&~J4bU)>Ep-ufqI{k=l}6{o>H6tL-6cnMz|nQ1Hrs~Y4}c~@l^@fT+{Fp#H=4D^b?)NSF^wq zt$$+HCxpJ%X?(R5e3I1@v!2GX<9Jp$jjuL>Pqunu)^8H}Yn;YccYsf|dSce!E%f&~ z4Su@>F0*=K);}fmyPU>XuYfD8o|yHo3H=*RgJ}xe}~ZD?KF7i4P0aO#H@c@=$~>LU%dpbwR&RKzasRn zISqcd2%c~C#H`;d^dC8mukv&F_uyWFnDu?ZyuFH?2IGx@&$j-FS%19HrIYgUO|XZO`HV1+UzKg8^3gtOyX0hrHCh*>ku+3{N> zFrSYQ7n4iW`6g%g)n#Bl2O&PnYCh}ic$N>$=N-hXp+2p#<6Hym&NYPQIcN9Pe}Vb@ zf|z4|&)MsUJAQ)?9$+=Ztf79RvHR+);DJ^{Jly(u$k~1MGML&6+NQ+p=M`u7)qjJz|4+;s z-S^YW;+YxrAGps?%y|uTc09WaF1C4Trfjj@%beX;=YqL!Ph6}eDpBw3c!mmGYW)xo zwwevj?yH-?+~+4|KeswNo{a%>KcAR2)CV(mJU<2=Zu25$4fVB*-B8y^)|~9@zB&uceRX2ioa5}ix(GbZQ<%I2G1t|#&W`6r z!Q-ulnEl-B?7sRIc%s!1A4x8;y&iRT^hLoZSq(8=|0T_<&hD$fgSr1qe5}=c?CkhW z4UUi8XC|g=*_aYXIy=UP1ee*oh`ElP>g;%46wG~N;-S{hVrR#1I>6i?CZ=n|m=c?u z9luosSKGXZ+0WOV-B&*aPq!Lk_Cx&yW5@HNVD9S@(|rQUYrnIjU5y9*L*l7cGs4;N zJQ$e!z{KolxwGS#3+8?=G5fj6*?sjYnESfKta;tpas3K69mgi{*;Yf$dHt8OV~m1cLI0Du%=#&DcC?vb?sF0^ zu$mRl?kgJCy58nRJjZH&a0B6T<2f*B)BxcP6&hD$q{Gbm>e1`Q? z?d<5sf|uHOi0Qrvro=7I9_}k*cX7`O_62jlkr3MCD=d0AH_q=n!t{0 zys&e>k(f1s-P~v4e&dZoLu~B0)&bs+Kg#P4e6k;6W5@MIu(I`>m^FbN*Zg7Uej_n! z0z1yTVds7$F>3-lu6@DI{YGNe1a|ZZ$!_D(jCo9nz;5mVali3JB(fi3W5=-%%>71U z)&zE33x%Egjl`@8>}UgF=YAtGYXUp23Bb<%Mq<_kc3hW(o%@Z%tO@LBPq5zHZzN_- zU^n-txZg6WG!Iz|Q?fV%7w9v_G(Ozmb?VfgSA+>@-hxjF>fn z9qkY7+;1diO<*_Yzua$}C^W>zZtk6Nzp+ech>acX519Ln#GF@PNBaXi#YZs{vnH^c zb8XW}Y>r=YAtGYXUpkAK1CyNX(kRj`jz3?l%&%Ca|OZ zfxQfW6b~_L0=v2A$oSQv_If_>xY>A1a@=nXra~6wIkLL8#~$`aHG`_vnH^k{egY4)ey5Lu%rEf zeW}$DvnH_1ej|>1@Ri@G~=zNm(yHkHF-`$ zPw-G)c}{bS)#N+PM61bnnuo2Xx6{zmS`<%jr+L9@`Z&#)5|dXSt{0ai#O;4Q$gSdg-Cf7xV%iCinbD$;TRMmtykY5FBBQ&B`hc)%F9>)s<*Bi^rVdQ zg90Kyc$UF#FLV4tpCZtpfJoENX-vCH?|gH9P(T!Oq0`v$1P~KzN^SWRIn4$ePyaxJ z5+gtTo#tk%84zeth7`{Lr+L_F4hb|UL(&}LH1ystng#|Mlp*Cc&}rVXnnME(N|pQ^ z>NI_@U(qxu(4d@2GstO9w3@>L4a%AFI?QS2TFu}O+%9#v zTWTyym6kf(Ej1QpNJ|+DE%kZ3)R15)lp!rOBv=Y1MoSqBE%i0K)Dgi_w$>ft)`G4q z(^MR2Y>5>+&6`$pWS~KbQSL`N%|ESXXrQqrHq>bb;;Ji6M+F*NVn;a*J!wJHus~yL z<}jx@&uWf#nsK%akJcJ0`Ee-2{_rC#D6wH-3rY+|s{yFB*7GreXIsaPak9#C!LNwnmL~nqgLRe4w!{+wo3wveldrXl#j{;577f1x=#@jV-ZJ zPSa*JqXUgCvC&RLSHNj12{g8jl{n3PRx>8h*g7`GX?9snX`n$lQwvb)G{3T%u}(AI zwti!s<~^$!7ierbk8_%=m<}0(yK^~@M>$hoCu$AV)$z8i8y{HgemWtrpu}(y3RhaP z?9qHY%7-kI0t-rmJf9R;u z2cEGAc@`GLOrC`WF_ULuu`vsajk&^ko@8Sd78|p$*qDXI#w;v0=E}gcjagW1%)(-0 z78V<`upnk?$Euv?F(oB>n@Y zQusMh-<6S;@w!x{WrDtfFD(<{BkX6Ae&egqpyP68Sc8sBW0Iv*El#qG)n_cy&p6eR zq&ZPtm}D8R+LJ63^wZ_i&qTE$Ni#{8#%V!mprb(hvb31`EG?yI=faw?dJ9U;IK2g> zS*euwWKM6zo_loYlHn5)!5L{V3|5SX*CPmsp{y74%q25lsL#9sp+gY>J^eH zWg2TWIY==Y+tm_EdNz?JI(P3*L(e19l#9QpS45vQ8=C03Lz;TwuRG0sRzv-O?(+Jv z)lfg6JIx=hhT5R+^2#-r1N8AS>J1_#{=!qS)fB+oou3M;p?0b}KXm__CLe#@#oTE% z{W55_TMcc^?&6{Q-!$p1ptpPKdhM~A{?K*jCyOctrUCftF6N`G=8z1Ua;q7rHR;QF zq1Dhn)?Hp(twww3X1%^^HS}y+ciZAORx?;@j>4y{EFhjD_Cgii+mCwbH78ijkPMpB zt%ja8=x)7MSWR&T&9zoTJ=CZ-l0NYlo*uNCp)hx+dC_WUjk+tJkF91{2F*~~(J>v3 zzo<8kK4~^IRa?z5uy&VMqtzUnL354O4A+|Uc|Bw`BQp4T-fE~%-(5T(SdA{>ZrX%? z)PP|+9)I2Wq5J(boq)gYG;^$m`fc55+N_3t57?b%yVamO-mQk-rA-s{2)pz13#&nw z9U9%5(ITPgFIF=a*6!+aJ~iH$^p^5;Yi11MbGX&eSx0y6PnFeB?=!0X(9teDEw>u# zLq|Pog;MwBFIWwoDRt-PNvpvLL$`k3vKqR6Y}P$Bo&q{3VVaD;s7EbcYCI=e&BI>ER#T=mm1#AvSWUUsRHW7Xx7AQ; z)JyNDkPgV0C^hP(_fujuRa!$^#8x^GPjjqhDhyGN_72-jvKR#UAtRNAS2uC1~3%z!!S)!>uP!o$@IN^6>2&->y(iQ3e3kmH)llh0y#*0|YKWHOX}8tT*>OaBq3s%;-nJUL z`eZcJ28E}5TV!9T4XhJ#lvW*_J^m7t%lA@ zjE1&rc)H1IPIY-59~NNl0jrtfG_=o$r>Cu^(rHp-{PvR->Uh z9i9%Q!w4oiqcbRzuf_jE35&@bs$H(6vgVNiDDRBt2z_S%d47N8ZP1llR>IoXE9@WM^jtd$`u{+T35C$ za?YCDYdUM18XBDwh-*8$71xHvHk8`ct%;>5g__QAD5-WGN@eS^6%ET9o0l(8x&RSk^S}qUDRGwzajkRW)@qE$RrDN=;`KE)3{ZuW0UQ=RA{wsqH41z^+#{eK73n zK+%|>YY!yTIi(F6DQ<-mD_h!|5>0K*t*$DiB%j&b*s-*#c~x^`QyZ^1MDuE8&1aAw$a|J={))Qf;=PRSYGYjJr$KStmD!q2+`2 zGi25^@&F5RTN+xB8=jy=4JF(5rkhk9Zc>AmW^qxQlG@miSbGaMTA}o$P|>c2lEa}U zr|JUA6e@e~wrNe5*};i*-WgU5>2AlCZE`5b6j7*UPL`%?pFC7Z(RE)}t) zwAi7=^%^HN>8XP5TJL0KO=tSHHdU9};-+e3yPKR^dyqM$Yui(OWzNZMa(m25US8}q z-6+Cse(Lh_h>)C`uKiEehzMMZo~%he79^)99}z<7;p0L|Qa3Gr(lH{mSf(RIM_a@4 z_GQf-W5%NwN4w*k*5&$ekB(uuDM?XgmW?evScguT-eFtQqNe6mIQ|{TU$QWxJC|v< z>ucRPVS0CZucvaG*Sw}FTwr>CPoHEP8q@>Rj|wkn+L>+=U6Y()QPjV5eiyYaU);Q8 zWm}W2pW$3xs;!;fq>6o{8->_Ix>3~XbBF5Iwq*?+-AK&oMMg=uUFz14Y$m%A%}dOf z-O!FxGu@vJ?K`eipqbawu&T*OnqY75IB8USN1NVJ8k-ibTvFH4yc~7FaP#uTt;`Jz z7q&I6a&y?_mf$sIwy)-LkR@x=QuaAnTaz@dqNdTfJmj{q%O}@1Yfh{}QcBtF>UP1D-8I=^s6r(hO25XKwDWoEh;L;lYmX#_V|9mh|z_F9}ysmEsn?hr38)wBA6 z4Wi;QGf$r*0@RNQ9f`ZeS7gvv34J~IPtf02Iv}JbUPV*xf^cM>~U5K7g4Z93hY9R8bgo*mJU%gmr;t|^n zdh-K9v(Qoax`{rLCh6b&7|aN0TmKgN>J0wP4||NBE~j=K!2eoN-|C@1VVGG~ewGPM zBpRf2!u~Gw=h=8lY!dxQh;MCOBbGfL%Qj)7-A;Ej95mF-P!qdS^Mw>7P3Z6Cd;w4|hDbwgW|onKr!aqNW7 zM$EM|;Tmh*iVK#EZfrxhw5_Fi;b=|`EVlVugi!EkRS#vdXi@v zQb}$l^*|v0l=&y!ede&7H-oN=rwLA2nvwtlD`}Fu()bffOU6tru5IdUXfK|DzD?W8WlhUFh!?fCt!Qm)=xAzGUY~{7BEdnx^Xh_` zC=DYMrLk(1_f^Qe+}TrSS5{A}n>DYde0JsBIkh!&XU&>gQ&*Wdqi*h;S!dzaW(Gy& ztnx9+Q`xhdmQ^lZVx6=u?`Ugn!DgM;)S@C3j7Rm+Wi>4|t1&?~X;Mo?7A85I#ZM@U zTV)otQ|HyzRi81ZvUbMYIpw(J$t$4~&a9bHJGHK=ytX_DN+e9JtW=RS3na?1+*xST zd39@>+B$|EIcQ$eswzjq?FOt)aI~7fh#fz3Uv?(t;XC>}f2tzz)HKo*b zP+I%a);2&a5Lru3PV@3`f}YRGX=%loUqmcm3_00#bt@qmTMEaKqp_8jkgRf@XE$Zi;U!%WTs!6-7iawXm zTQD16tqFWawieHwufLB>luw(A#UopXmd~DBHI-=2)bd%g=AKD-)QmZ`S~qM)bqyJg zo-tK_A2XlkW+moLJ)>$a!isF2J%26*SzBI1(VVfse9tehp{UNpEPdmv6kliA@3YHm z#$xs}n5FM?%4^2q>s-vz_j%OEHSyQ6p z7+o_)e~+yx)!!3p#_I3MHRJU6l$sOucV*3Z{XMN_g8rUaQ$cQq&#SG5+Y71_XG||Y zn=Er-shfUg)r|S7_g&d|64mUebj7_=pK0pGub!HNy418DY7K7S@JQfnQ=luCClzU~b4XgVtfBn^m%=kh=xl3R;_Q}TUe#_IsyQo{S!cmKk~^TByLd6Sl1U9_Wh+I` z7JEgT^$wMHG#((ctrQkB{k%~BiRu8I_{lnuM%L4HVUpM5mEl~^TZPJiiy!uIU<)yr zk9g6DC|B>j&j@5<5OPIMEX>Df5Ss- z!M07)H-=2nNtoQWX=FXUZJT<2+g|EDMwi&r8}F)~-+0d*xRv(K!SzdX zx<#jYb#4v?F8Xg~*IMQ}d`fSw|5Wo#*I3iVD7W`;+KxpV=u_pL($8)0=H<;Du9u2b z{kuN5--c3qdW-+O=eM{Y(fu8{cj`S!8feSP`4mBFvC_p%Pxbm*p)1xUO&v3+WIGx< zR<={ID!NGM-A|_hc25gSdb)5Ajr90&?(B%S=0I)X0Si~}IHuH08)rDR%(qf`s$Qe< ztFWLz=QrcwEP7zAys@#Z$^P{4C{k)?8H7Du{tJ7){MSeHu?SaUs#_YCm?nv5sN9)# zQSc0vcY`e~oxn3lSkvCojvnDcTq?EOf@h0{n$q8d-`fR+TG`sxrk_}nrB4@OlS@BE z*wdwdWzU!XEv9Kfkp-pCGgSJ_T#{NPt2NF*(L(Ev7JmGJTR=grGp&i*ntnb0fc1FJu7_S9tjEtkh4pwOv>hU$?JzX79V$ZGA>y{fP`e!}{^jkE zPxUBLHN?~(-iG%V6rl!j{pyocn@lbGSVv!x-F4l}Azox=L0*G5VrF((*UTaDNL5ai zwtZAzmFG;A@Nq3|<3MZ*@O=_~5#g05Xjwet;Z)oV~Y?#p4&BK(5g+yF?;`1&e83)l;bj&Bjr|w(we$0j#7`N`OoY4*i&NT&Lz1>?ftioW_1zxIJ$XCxy3WM9(wfpX zJ*|(~rXyOb5o2E)qbd7RZ7T`chHG0QWE-MwD?+xS(00?U30jp`Y^(A*eP{0|*kiY! zY#oQCtU0xpvUMy>TJt>HT2lGH=1O4bs1X%FX?m{I&Xwu88ap>h&$ZdPQr&v? zb9-&6-D_*yUYmn9wM|pSD~%xld)G7A=0WLHK1{tW`k-qO$T*os?=)bTq!(< zQut=Wf7w!a)Rw|y4R5wq+*R>>`3v_A>{99p^~n7Nk$Ufudp;j&@SfPQZKK}L=(t&M z-GZ(-*8bi;)i@5ky|?P#Y~)D%Be341mv|#m_UNTmn|Ec?9!B-ci&PX)4Z&LxZArzp z9P{71vgzoSjr7=-?EkL1*R~HCy^Y4`F0B~Pr3r6YUa1zU<@jvJTpQ*)R5L!?Ft-Al zcJLyMqg0~*tyT>>C7iw(=@ZphjDXaM2WU)M3zl!tKI`D;0*o&+8fk6ty-MfP0$K=L z^0MhP6z4KTu^3)P;oFQxNAH=6D$g5~U!>yM@tk-(o*VBK&x;R^PmWKCSH|&UV00DT zR1Yd#ce5%lTpKyBa9z1fYZPe#(&-F<@>G2zrwl=aRDUHseP1>5smZUT~&$Ib8B2vol?$r_H_KC#%R7B(#0=jTYq~Mq| z0X-T)K=(!Z6t#stex*FpuU{JdTcqC^>C^AtvRH0=B*%}%XpK{g>8dD#y*n1WD01{6 zVb?otpxJ%yM#0Mu#Mv?>Qg~b%cRz<#~PcaGx&{Q;}ZL_>8`nmf?}BXiUw( zE|*oH#^w>kd@maBn_ZZ9Sp4Yt)n(9U4^Yu~p-#*h2F%Ml71sDMdbwO2$Kr!A-)j`y zN8`TN&zq93eP3P{-&hv=Y+2qFW$`P^Vw=kHt}nx_raUP`2;Io?)5-Euy!Fl~%i~P@ z7}?4BQ}Xp%7mSl-(04Lc0;4ExxYW}t)$cL@l@VH-O+Z?$&1D#+por#t?rZ|H*4#!T6F>JxjVn#mkkUkrCQZ~p(nO6RP1Nwo$>bQJcSPb~ zNfTbWhR^dYpNwXZ=E+Xa8#13Oc#+^A3w~bk@mN7#c8uT$1XrRFW=)OYTLs@K_#VME z7~LVEmOkDAK(j{h&4Rxr_@{#ZBsdE#0OvJS@F`#u z8(s(`n4ULSU}GkJ&BivUXmYZHVM8@@H2v67yPl{L(v$S7<_evV7ecE zwvCPWr#7}@z%APDt7%T-tJ4Hm;eIP?77M;g@J_+c3H~$K4gKB z5`PDCUVRE!gBLvtrUryHg9T3#JYVn%!J7o%CHN`9zXqGw@S+95ber-#8#D2lHs(Kq zIi4=3@m17ky|4ZXW=#=pe=&~%8=tNI%ipx|E%&F-Q={|CYQ1s{t0DC~0t z*yQUgy1!zMJ6?j=4osgY5&F4KLY}cKbo;k;q zxC+cK-@VUieD#3fhrzrq_uwGM{FLBd34UMj$6%8$USN+5m+EZm^b7blTmGbW8sLxp z&_gop2fMhlWA{3s{TQJiF7%(&j>Cn^7tOZImwYDhhZ7(DLNZ!UOo`+1!DU`T2C||L zP=(JL&0d0-_0z$upXD^>rC;V)<0a~ap0+>hsho@kFE9qr#~;N*%>FlkS-%l%H0H%x z-2UGv^tTHA9bj&szX9epnV9{58_fP6cN+8Zs&g<;@w|vn*1rU1{VQOj!3&JR++Gp0 z{sW=k>on#CQT3Q7|8dlJ*5`xSe_ycC`1-|3+&&Bw`r$%X7v2ZY5&C+eZv^xHLY}keLq!rB@M-Far}<}zoU{AtQ83pB;t^K! zU1#^z@4@G2yO$uIYc=%p3uE_HX(ZV0#8p;9FSg)g%_?xc^+SBB)m-H4c#$)Bq16zN zvYKx>yRYc=5WG!^kF=UUI6IDmQQk&gf|%EfUPzp7+hxN?i}r&T0^ystBXL~Y%?lBY z-MkQyx8p#eAvShj6@z&@60@JcZeEDU+i|$i5c75{0rPewWgsM|4!kG8S{kg)HMRM@t4vorpOq#lSKi zb2CDg379)KWT7P}_Z*iyT{fiL0}H+WXJpudtSKg;DK&#t3JV0Y!x{wL5Vjy_%02FK zAA_JNcVR)$wC=)!plRKO1wqrA1QvQF53RefU=dn(VL{Bru;jYjOA+(2VGCl0E2%-u zm0=5FJ|k>F%uB)+gm+Qcf|xgjEcC(~AC_J&9(v);ps)ooQ~3xDVy30?f~64ikgx?Y z(^5i%n5k6rgQXBNvXd6Xd{Wqgm}%XErRW7Sw3USgPRykO^OUd!G1G(kfrehPLhX^TAm*m91u=JqEr|Kjumv$+ z9kw96Yr_`AO#NT;nl4(e@rb!!*n*e`ge{2qh>(R|pppkm@Zzosh`ARm=A~TZc>-cC zlomJqy?H5@{5?1hn;6g&A4!w^4R{o3X*J?^-_!=D(~#S~^nrHkDe`LlLLZd=XZfsH~&jG5AdN^E3%C z<>N2vQJqND{DuUWXxm4)yeOryCpMe`S{q2rg)P#p?SIks4- zS70>tVFBg_Sq&W-yVH!e8fyKFhU!OnsT>5SlGwg^@sB}{$*9OdrHMA*dd)91vwtSo3)gHxO#uN1d=TpO+G|`?)$5&l*lF~M$(HC2d>@VGWl+ z7kvlTr~BR@j4!)31A}Q7W4#d1R_X|1`iuF}eGQ7AreByZ{Ylp(N2NB4p)q6L6?*DF zHA4SdnK5$F72A2T#_X|z7za1Cnf#a29F9}wE98HO&=({9QRs(d&`%J0I%D}5`so?; z{1R2ln)IV^+SQUl&&PSv({X$u^jkCNZxHd2elzsn$e`!rHud#~(z5)G18T5P%CqLBpoR3cGM^>M1 z`_lC;o~8m`hkkISv82^*blsJw-BBjIWE9JGoS@V$>wmgUqMz~c z{>%LcN_r5>-Z~ol%QPdz$&;SAy`q`liFj^9zNg_#EqRjq_l5pm2;ate+_z_#B_`Sh zS%2_j>fBe%dw-9OsY8c{MLNL$iw4x`TZc^+jG+@AQ0Gn5@90LVzUL8ypo7KDnZW?{&T|!+0lZ=jHl6pa7JWC3o^5PF`HF< zBt8pE@DZm`{0eC{UWSjX;;A%0ljalnIJg0c7D6coBx>gc|J?zJ3Li$TioXJPS;fC0 zr^y2n73l$qiu8a)MS4J@B0V5cksgq!NDoLds~%z#8idO)HgJ0KCh?SMoeJ0KB=2P6WT0f_*5Kq7qW0g3R90g3SG1|$OO0f~yt zfJ8-hK%yc~4@gvG2P7&o0}>V40f~w{Js?q$9gwKV3`kUD2P7&o0}>V40f~ytfJ8-h zK%ycuAW@MWkO=wf0g3Rf2PDF`9*_v%dO#w4>j8=Itp_B+w;qrP-+DkIeA9qL_|gLs z6}bV4U=afn<*&oxl$r^g0#ycs5mEojs|(wE=wV-Tv>MY>zsEK1&(goeU5F9s6dfk& zG-1$@&X)ESi&`$2zQ&l{9FkToY*^XIY7k5v7*hZP0~@1dA3tVH@(a`2M*GqWog2^e z*Ci_7!9raOufI6;qmFFIKs}6*;ZS3sZDWU9#fT{@F-F+nAi<0oYwdL9+Z%8SeX9Ho zxT;Bu>Y=VN_;Fi#TN~cVLQ^>@bc9KXJ-Xo=dUnI#pnn9Mw1F@LMT1`LGpH^YjCkj@ zG%a7!u~bn5TW7hOt(&qmbQh;zd`+`)*sM~wJ~9e#+dN~S4bIWsXbZ+Uhml|uul(ik=z8}_x$!p|LvwdcXMg>`P5xEeZxJV zl8Rd8&BlEgDrDP0hfA5x%}pt%B==}BVK&BA1P?ME$0oW(godXHx7@sQFMhY zMj4^YCZ0Y7cO&Z20y(aS3;ZlEU9Toh^@V9Isy9X?r#GsZAw+bkBpXxfd5lU>c2MX} zr8i)y~sckXd1u?I6aR&{# zT+@V3yM7#k_lLY6;=&wl5F}Jk_mw8PwrAQKw)SYTU*=`^sQ;~IjIq@Ae3k3H>$>gc zsNw?45QLidA)E)+7|Sg4Hq=&;Y+Bn>B6WhY?sob z1#&|V7x-Oi>v@_YOl>_X{`c_FyqCRX^{^ zqvKNbYPy4CnnD~vw`M$5(1LzFt$*lLj!K7Wm@b)6N{<#zw8w_Dp|kU)7#{8*3+EHo zu!4tiUx^Aae41o)FHAh}frnxH3n6Jp@s47sl{;!h58mpie__SKqdZ zf?oJ8#&?UQjsJ6cF6o4 zYUfVxPz5jci#i(c&IK}=D*iDdQVhm zt6RLSJ1_tlZ=*65(bkBzX4yRgcmB0CD`fRlTwCMXYU|ISV%1k$`)aGLEwHB6*IW!M zcb*-$>K(@(xNK`#O|0RaZN*!Qb$UeEHFv7GvTN-ueO1NgceeH2+E*`83@`Dm zam{7mtgTs^H>j#?s--lrS`gJ@7gbP7hc*OdQ`k_f%exrm-MgVoa~U|NVT0xk;H-L6 zo70ript7{vt4wdN?|z-iY2%x-yp375b@a_D z<&CJyPPZR!-2cSY$?J4$uuisy#dUuFy9R-4$G~sRxO=&j4&N9!?tjw&b{zX6L{8TX z=@;u5x-N3CL)YOvQ5CMIq3hP2Rk%JplpJ*+ZQAL{Y1GTHY4elQii5QClGEt2lU;7X zCrP7@zg?~-dAUq!nc}3UPmIq?)+YO;rxZ-u+V#n4lY_L2lGCbO+PX*u5-ES4rUL9b zL@JZg=oXTVB{C~1EqS?Oc8Kqz-E!-$^f3M)jloyA{+Up|$=i{}!;h+;V@c0b{r@9F z?U~CR$gv0ezqAWra%1uRoQBhzh~e4}DNG(;?Q$BfZStO&*O{DhyGgk?=B-Xnx+dE$ z6zNxxoc4E@mYTIMj2eBzX;bQk;u^|&CbQL&o7BjnF`HGG4H6<;D5(aM1~Z`VsmUXy*`&*!*s}((Qt(|k-~nD#Jq*s z5gKXK)>@r>10_%XgWJ6SSB>`PhVc`l{bd?r(2n*;V-W^2H+G=&RuGIG*!?(!eUnBG z^g|;D_A?^~7V^k}MZw5{{X-)M4v-@U-i;QAZa?99RQ*XGbWEj*+FhFX7*MR|%#~L{ zIu_DI$1j@roAq>jqKS@0G|_Q~COXE@M8^f1=-5FM&(kr1CeGi?afD{1!A@=T(eE*% zAJQ+kY2+4k3o-e6lso3Lg}q+zI;=QrE*E?!jxTIK9L2(Xyx>y769k_uxLk0x;8}uC z7d&6^2Ekhd|4Q)dg7*mCk{ygLLi|3~8B<~_nAhb?PUEW`f-lVpG&c%wq9q85$yz*2rd_Vw%|6wor38Z+=bewmmrRqiknyu=Jnd{G`_l7@EY8fX3ggW ze@XDS1V1PEcY^;aI3KrZO+3CjT=00orwi^7Od}lfvh=WNqg^lJF1x)h1#`?dIE}Av z5xfS^LbB#_g1;pATY{ex{5!#a6`YSpA5A=1FTvvlpDwsv@I`{@5z57Oy@;FadTju6 z%r`oXuWl852_B$f&Gmxs7yJy^`1jQ-f?pR*&+#p_F%UP~82$ie|NEWBSCKxf_tjfq z*8Ed2y>5l=C1B&$oPU@rz6|GuJ;5}8jI zOrs#OogR-`ZsQ^5ZFC-(^IGmSzG@RZ8wUy2Gzz|0@U?>P7W^pKDP+9*2!M_6={}_E&@JE8_`GEO02I6yV3|(OMIRu?5qw&>H!N-7E zQ-BT{^H9O3f_d4wg3l04H`W)}7>MbYZkQ71fZ69-r}5PW!5f8UIqo5|{!+oWfsKER zt||B%g6aPA*)|5^xi*H!!0hwqPUEXz3Vu~+zI%9}fARmY_a^XFRp;9H+UMkCVn{Xt zLQpXxD2fA*R$7p*SOan&ie}dBCtu{ zSAP{aju*2|&X=^Stq#OaheBYd!_$+5*e5;M}pm zW^QRwm=0|pZqdJ2F=OrTOULxj7X4}LDx{m*?!%S+X!=G1skw5oEUpe&Z@1zvH7_jH z1CH#6Ga)zqxkZ0jdK*tY%KkY6OryidmT3*gSf+K?#2TE-HbY3(W8=nS0|k`g9FtAxOdr4x)e?st|3OK%c z9(aqbPvU7BtK^G<|8l_b)o2XtZp$Zj>C>8o(|>%x!QvkwM{i@vpJDID8Znj%49RD( zapUVX3h>AFC7!IYO8yypBZtL!=;Ou|u}fz{Aotbjz$^8+UXs}9IV+I+Y7wv-JH(FD z5XgOfKiX{5;k~KjYy>uPU%d_3jS*s}^9_L<_v65;Z92q`^PxcQtIq?wu|Vv~#rAdm zpY7Oc(;=R!u}Xd~kYjBLyvA~fIUgY;Uk&8GdMnz<^>bp!sSM=4x*6E@ZQ}Vhop%Rv zUp)%!`ZKZP91P^XdJWk1Vd6%c&YuH0JQT#keoK71!0<4Lu}-} zF1PEStOJ)0vFo4AvlV|Fzr>Cc%FQ)#jpeio4zZCNi^Q&fZWJ71BlmSXyZ+fNIK)Qo zYm1^hhx%;8*6BlRn%Vxj`rlQa%Sq zOgXd?OdHPQqY@OJWfz<|<}HMgAPP?TOc)iU47(;e<bMWxQhN-*Q@;Raz$$U))BF*bM^_aHY2V?z!KPflnlm$sm}Iu7mG&OzD7 zMI|UZuNH!Xl5!m#TCbghl1_|DP|{PP5|orPuQ&_kx*#e+DVTC-1$Pc~X3C+2wxCan zN}%(pQ3-TrON+ChGfQf0=hD9JT&uH?Kxg)8A%V`PMJ3RgJx_3;b5&Gg>$xNtJG2E| z3XYIK=c!Q%bY}es4s=H1QUaZ;qY~(hN3`f?Zk*Bg51)bS~LIRyx8$yDtnY)lcXVyk2 zp)F{pTe~C^0`6WE6>Pr)(HzWhx2KAUd|#R$4}hL%;7x= z18YC-jpvq!k>D&3a)b}Z`HW3xtmb4c*OQjRejoSViY-eR4bG}yF~o7N5?j`IGubNInH|EIL)cy7Jt#;EC%Y9^4R;+InGL;t{IOjzI2YW3^;+YIvw_;XmHj5 zIl|-KbZl*92%571$Qft2{^P9v=^FOFBF+w>v)rd!+@tM249b+?tauwIGkbg7qfNi`;H>y@o{D?-V#~1}4M%J`oO_K$Vzx&#l-O$J3}85Hm1vk|Ih;2P zhiw)OZ?zoGV}`>vi-uK}6I!cgUyO!!%i*j(Twd2$PH1VF{WTi+D-(v$sx$j*GSwJ2&D$BHuk zOwPt-{*jlCO#LmB6Gnb;qlFoNHKJ$vb8R+NFfX;Lt+QjDGf>T6_e6fBE9lYRor;KP z=^_ys%NSu~E~%iTmNyy|DYb}tqq2v_!^BA`R-{Bs)Vz?0NHsenqS9=oh&U7~)%b*n z&1iW-#5=19QBm;Q{eO-D?64~YnwlYi+=HxiKgy`C>z2XE){2LghqbQ{(`rgfQ(8mI zqV3?)(uO01NwPPzM!jzRW@(Ok_Wb#CXU&;EYu3E-@>%5!atmwK3+B(Ct>vwSU&V^* z!MA>@V@id4`rxcl)61y~T*0kRzhvpVORiIN%Q>>$@5#U~w{dda^26OyO z`&~l#vc0BI^s_0joD6-g;KCE(M`jo3&%=4*>cuO|<`XSR?8+;`13vF_p$y=5@Nc%4 zQCD@6Z@*E|r;z`3@IN&I-+s%X`Q_ODH~3GEz<;06hwJ_M)0Fz7#6|GozPD$CE5{t>~aJ`-@s8W@2;U9=bZZQwsP0)L6%mxKRF@C$L@ zz>rCQw+3T8)BipAXIOrMLIhbqcZu{*M%+0#=?cq7SJFZ9=>^S&^8s!G|1QhVwGop4 zl;HC@*btRU2^FFa*SSK0!*>8*fl|-f^l>AmgS5{4E0O+I;6^lB6BR?4VRn)J{};hO z3F#l4X-Q(oH8;mQL!r=T7mi=R?erYGOk)3FaQsRNRxVQBRO}O#y}j+5VI8kW<(C%b zjgIY##oi7ZF|pVqvDl9>Qcc3yv(C)vaxK+U|BK8sk7-4l4QHPDgQ(K@1*})^9?)QW zxTbC?>@zp4tZiz+y?^9*PD=b-T4)yhd1#ZZ7tY0lZJF!J?cMDvc7S=4dl(kRHZUv=4du>=4du>=4du>=4du>=4du>=4du>=4 zdm0wTP8$~X1H;0Q2*bjKAH!27JxqeO*0z>f3u`LiI}4_+Z~K`W`)BvAi6eVB8b?r zUeAS!(`$>x5MP4|@8~jF8VKRlCSK2AoG&e3ACEIlqVFhNd)4Wrbu=F`c~OpuZR~IF zS<$w+yR&1KeQjtv`EZtQ9A-PqN+PCHG^m|{cMRUzv{CRV}~il+)s#Un-0 zarDG#N{@KOB}SxUiTLbxtn0JfvA*c_JCj6Vr+_KrjC}&;j9pg}9d3?7`x|rBVG-&C|JtZ+o;NfA;3uYN$pW3e5egm(@*1}y{?2v>#&YEJDB>3L}j;vF3)xabqIs3VFh7` zu9quSF=Xu8b(lf<24~rBEW00i9Y;jC4(FQ{uVfOpYV>Bj`_Ro19TSKY?GcU3Zi8&g zc7t61|8|3{#0{!$5KJ{@g3?!6Hb^=Cf@`se%Wi|*p6v#KEzxZmFJf=d*Ks*BjEt+6 z%;RTA+q!jFX7rkcl{)~}Uc2nz%Qzg5VvQun9UsU<#vR{QdL{hU3*+wXm=2@OoW5KF zQ$H3;Y4dbqc00i5v)uu{@%MLtuCz6#UfHCJv(O#VGZ`lD43l!^&LL-Mz1}Io13~td ztypBc-jcRHVK*tqU(ij`7}@O~uV=e|6vY1S31VIN1ci@eTEuY{dW1+lHMgVg18#!Y zikI%L$y1h`Y;Zok3>rKoKD*6*Z1ybHnkD7we}8lLhU;=Y7R7NEnp>ovn%hw~clwa$ zgK!M_+p$1%?a${V=6WB!QD#Tr4RFvAh9hRTM^t3HM>`sq3TSXrz;~ z+Yu&a&#tgpO3e8CJHk<~?z1pW9ChCR@Py%v`Ce{}`R2Bj5AC`<-FR=#k?I{)!aQax zOi3zjM09GucS?L!bxu{DUqCay%A4FzbDF7VTs_#>i{x`CkssuRBJ0c^k`zz7j~%Q&dBBBcz2- zM^bbdR}kp(XRS-&NV=R5m@=*#C~u-JQv-?9MWmRgQyeu?inYP{b;k_tWQuix#HCmg z=%{v$RJx79nJ%r4K;qIGf0Svxo_6Mh;LM#zbh+XqmFw8R=&`FQyhTo_`!L04BCW<= zT0IcoQ!`jS@XeuGY-jDM8>}5TzA4^uU{&q$Rk<~*>n^M4hnbVrwUy4tTV6%M=9v^bwq2fj97Jd3sUKyAsbm;_Ca5dY&qJa}0=@t1q(5=K5hR(nknP zh~7@Kj;AHO|BP6Cgqh8M*Y+OoJ?^H2cU)@RYa_(%rESNCf9cG4;umz}#|Jx)yCg%h ze;Vo357KOD15eGQ(W61^#TgR*)rhgLCPvWsPMST{*`{f%O<6ugTca18cishwg7XuJ z*_T~*c_Nb;(d%jYbD5we3YM%+BpP=l3QkXWH<=24GtFQ+8I2&mVokXpr!`#)v)2B4dxT*x94>Lwl6tBK9at zq&>4L%S%k@!s%qfF`(}N5qXJcn_ zk&f{7Z-{FxKG%cYDvMVMe5t@~0%M64@E;NQOcd0mGf&_f1%`FifCFC+0X|P){*KUy}G@Q{l-az%HHkfCC$w0x!!AIco*pA@G2}_X_-oz&{Z9 zWr2^+bGrFzvA|afe22gv6quh3~+1CFo0D)2q%zmD^uz)uPM zg24RAo8y-WJX_#}0=Ef#Be2oaSDzI48v;KgFby*~{uF_y3Cyp3PO)VtJ`w#4AvqJ+ z=~)qQVCzQUdcipbufiSwe1R7NoAiCfPdaAWyohhJc`XBW=dKGl_`Scti}A`Y;0R3n zkWPM=zz2Y5>b!jQgup)#nBPyBpA2|OVrS3rXTUDaR{{=fRtWr4Om>d*s=&qg2*Al_ z3Y-KsdHJeM;0*%v1A;Sc{SZHA>t_qFOY89(53oSOvxl)#S({40TD zckGyT9W{ksB=uRbL3t)(I7 zUV*}GCfxzv+^R52<0^cO?y9MU^q;qWj6Hl`G?*(@0|69QE)mH@m z1QsEVb5P*l2+W^qJ5H&OA`Ot_WApPUB3S( z;P~ph0zZr&13S)-1b$6mA5YF5=VXCv1zs=kJAsWpu)Qqs-2(Gz{9A0D6Q6DC{2pLu zW9spM<15;MG<;uu6UIfHKEDt+ACGyRe1^bp6?nD4HwgSGV3+;@fu9ig2LfXmWv_$A z9$mFAON+K`vE1UL;c$&Hj0T{Uhi8 zBjw^WZ2EAEzRxgyqeXv!ZRVC1bs{)soSHf}*VYzo4aZ!wTJ*QIX5G@FP6pqs8H~+F zb6sfB-^rT!wnhKe%dOvLfRAp^kUR|=H!fxYyERx1uu0!b5<7mq;5P&uW0%S3FtV*e zx3<}Vb4|ItB(Y0>7qHXkhJa&iADOa`Y^%_4jIBab4 zqk!Y97lBQCjclvXT`%%6cbYc!lEg0k(ZH^}#R11xv`=XI$;h?}-F#R9zUfON+bVQ( z(Q5E%*@f#dVy6#YGX(mq3plWa1zc(Q#E!oM*y+D3;P{%!ae_rh^5@vPzDJBp7(?<| zY+QeP4cPTJVwe7(1G%rpBYoG$h#jXiki+g7up#RUoh^YJcD;aIpCNYXyep8y_W`i$C&Z4kKal(CAh7Ej#E$dLK<=w&fn9$f zcKZA}ko(%MziD4DIRv>&hkgu<9QO8sUAq%=?m$SE2XfrI0at1<#y+sAE0tUr$fNCx z+w0)^h-G`w*2K7_Wk`l{Uq5bkZH*;Qz#%qrV+YT*b-CaWyE%mOm}_fdmscn^cJN$V z&k`JBBR6*NTw5;?9AY;=Q~BuHyzFwEV_?z_UUdZg-M^5ZZ8Ko04N}xY7O??andf(5l-5IARc1-OvSjma*!l z&zfV-3hlgoSD!FC*azf8Yk8C_D?@muDF}Z#oWh1VeGiK?RW$ z+HjkV3S!Dag6d$O2yL&;M&WV0D{Q9G?%edK1SREMAKF!$gOZ*rC4nt3VnuO84;rgVltzQI_K*j0+$-ZYO2Cn`@W2r{9LHI8 zDA1g8Zt)il&XNNjo*|u+u*GB2l)$IG45RQD_sY4&Uo<>pIb8Y2J+?u5I?hT1$JlUr zIm-;}AH#8+HHIS1Dd!e{(cmmFa9$WL9cOic{VeYB8fDfJG9_nefjuwoosX@VJtW6j zS18e(%Vku6orQ!6nnN22GlDn=oD~t)T->7_ksrCJVDBs^;2{Ldm7%wW))F|P;@&Q7 z*&fkQW~(f;1ZA($f;P)?LQ7dJe>Bh%t_idRbtR5y_i4+vo_RfO&Gut7`Qr)md0OOm zU`7=EDN^tioA|;lMV9_eQ$R@jPCkf9`Jg(G5BGg-214W;%Se3M*LIOuQ<8M8oh2gv zI$GA0lt=1IMnr2(#zcQ*lrd&xU64RpJ*Fg+QkyBU!`11qv`EcnV5QY>2F}scviX@S z)iWsu7QDhAsIz1yDfLe>2^FR-GBzE==p(Wezv+8JdraLO(i~HHV2|mns3j(2m8raZ z?wr}e9@7cxA=qPjYLil5(1Y07V|r0cgr_0~o~_dYXI5T)bR(q1c4y$1TaLV%y3;c8 zD;!^3Ssg#qewPsPJ)sNdV3ol1E0!2Zx1BSc{*=Dv$k=n%+|MOkN+_=g1w~@sodod@ z!QZvo#Jj8|e|ic(59^(ekH9})@cArfKKS1nfqzj7zXkjkN8tAeKGzpFfnRJFvaac+ z{!-`)}Ue-ixTz&{K8FIv7^cS!w@ zje%qXtECJ4S1g~a8V1RqE%>}QI~i-wZT7;>RT+ci*9$)H72gg1Vav}{-nA+G-+}+~ z2>hKX{6$#Oj&IRw1Zy9u&j$scUHKmH7mUDvNbs?QR{YufYRh*+S*HK2;17bo75tA| zK38rGlAq%$0dm&oN6v>m|5gA57bW>qoDlJE!CxLW-K_u!E=uy}J0arh@%J|H_qGBc zxG2d_Iw9hxt2lcZKFA1p*_#>E4jElDtlXJ&2qJslQruZxE!w43jQxLw^h=DCJTS&?|EW< zkaHErXHFRhY3x1dIo_xh$wjcXRoB?EvblC?a^=OiZxbRkfjpcYJz(_O31^rRjxdoukz&K0+lZh&rt>P5Kl1*BgeDVsL1ggH9B%USB;4r&r@R~$7iXc z$nn{#SRU71*wBE74SB4XmD^Zb4ekByohrtfj{OIEzo^Hi^m=S+j?`mQbEF=dnj`ht z)EueDrshaJHZ@1;v8g#yk4?>ydTeTr)MHa~q#mJ0q#kh`sYe_~>Ji70dc<+09&sG0 zM;u4$v8mbAV_36I%{8@kl@~Uwgy$1oxyHtKF-T)Y1s;7Ou^lT0_25< zAI4##`~jBgd)UNdg!wV${Q~=#Ir5bE5{`1rQCt;tc5T_9VnP8Ua2dfe9?akUH%`$R znZta{WcoyBNiI~MXIp7r!TQcF8qdoqSl6``<{gQ2ygkgxnOKE{3pXRVM0pPrO|7d^ zZAq?FTaqi)mgGvcCAm^2|k}IVpxl&_EuGCnPE7g|dN{uDCQf*1DR9liOHJ0Q` zwI#VyYe^1!Ye^2sT9N~DmgE49B{=|XNe+8$Ne+8hlEXHzBnPZ5$(0&Qa;4UiT&b}n zS86TEl^RQOrPh*Msj(ziYAwl?8cTAe){wl3b~=Bv)!J$svDj zNe+8$Ne+8$Ne+8$Ne+8$Ne+8$Ne+8$Ne+8$Ne+8jlEY40k}C}?$w4A4$rbO!lSod> zc>GY^wPk(B27NW>A_#`QBJyl~g07bkv%Rb)f3epW_mXR1LtOFNZS2OyV>k44_I9uB z+*E(H5eG+cZ*{ku)i{H;1V?f2^39xgILozYgk-wcbo9Y8n@ijtAfjs>9&B9Hv952U z;t1Ae6U^awXDck!2cjKo+P1E9Dgr@tO^|g|5ky^`q6tLXd)hY`ds;fb;AoO=O!>SE z>L_oLSlaMWazrpORWLnOa7Lq>81#_rW0bST}*!4Y~!U&bzj7Bu$0M(h>ojmi6mNZaxKLPWsF8WF*X6qMn04V&sV zydz*!nFpVNA#_BVm$9a~Qe(5)WZSdbWbgBKWNfmlaY?T0Y}?RlMqzN2p=HvW0Sm5Z zCG%B~SEh%FD*hvG)mh2*A@XpwoEDwcYW_%etNGD4y_&~dR&1&{gX4mrJL}=aw#Y!r zYIT1*yVd=ocXfKN&d_xs+R@j(x!ZJdjnaE_<|~Bl%|-tQukl!e8C@!{qV=^vUv@H5 zvRcirWVf0p!&qZ_J!4kS#_YilRA9&EcO|C2ySqAR2zFW57T!m%~V*4sd}U9-_l^H$~%uLoWHZY~9?r{-Um)b-kwL#W5HDecNi}CIwYP6c)g>YZd0S8W=C+P4=wyPKA_MKJwOw2ByuwtK zh7k657(oX|&DK6!Etp?y;Uf}I`g+nR5lM#e!QSg$uVZ4<-=*6TU|+{mif+!qL^AGJ z@hq`peV3jCH+S@z3O_bvq>V22c>S@RO#)Z{h*zfS@Z8ivKj{{E_*MxYV7aJ%q-Ezs|IRp&b+FQzFx%1o3fP1tj-Fb%kr%7 zUC-;zI4f+?^SE9HYJ{1<4N~3n-2wXY)hUk+AiBzRX7zPW8o?2Jz8eZADmX$^uS+yF zhn`?`$#KCKrM90AH(`@uZ{bFtj*f3G7i-%)`rBup9W*W9=!I*7o^~0Z)zTpwrU!mpo^*E&1lRu zS#HeRW8M}2-QOD{I=0kqhLhEb{Yg$XA3|+ZzsVVHwh!MQtTb+Kesp!nX3E;(_h-Ecjp_OucHn2XbIn$!dKu|-TW6_7pZCgYskI% zsoEo(M@sicl3RDAGjobR&v7=qt6@DmucLhEnNYHOw9xvY&*Voe!RNNB+b&n<#@JTN za=lY3hmu9P8z?(Z%XY=~OgIzB zb31wbR(%Z1^0~`zuh=v6!TsM^cn4w+KQOcqmf#_efBD(v&;EI&G(Pr(>#>h=K6TKiuOg5 z`o8qkCmk7zq(12-9*3z<`ZJVTen{;0fbkFNVt4`WEgze;Awr*m!uJm!J{p1S9 zSLJrPdeO%<;jyYdH3RF1_FIeare10XX?=e5k-EEU?yW)(Ys`?t z1wl&Y9J5_+(@73|ZD`?O5?a*{E}FS`=8~BWGZzjlS~(v!@E3cF2a20Y)>DI;o0l}- zKhOv*_TIi>=w5sFlETG>mhD-#eAu<;zM;A9=DmXr_NtM|@aR!GTf83^u{0{}OD6_ADO!CB}Av8H0= zv$T0P@@W{@ixihO->maoTFBV{L@ie4n|!Kb%LjHpee=(%2bqt_W63~nYkbwB{Kbcs z4JNwcs}|=k0%FeNjwG*bM9wN!KP74N=Jm?-vE?%{$LYM6H@^${C3W7*n{U;5FE3=Q z$@{_qn|r)^@Lf;e`m-?a#(`0-^z*PZ|B|7G>GvJ_#CMi`x_(Mwmy<2ivIfWobl+q> zG@u@0x^5e6IU5Qod2M6kKs|cjLRY87EGg5{Ez-lI#lqL8tsWEZ)T`KVuSRS&YLe z-YLtbUowQN1j@K?N_{r{)=YUoxS)>8w&kH#%K zJU6rhZB=X37HoTQ)Pv(b@XiEkSKZ+B0QK^T#*_Vmf_m8GVo5$ zo|jBLkM|)qze^d%`g375fIaUfud?LoSTlS^lUsR=#FSy%HK}p@ zpuoiS$LdnjoF2q&Uz>VfYY?|Jb~z#|6a0bm_aKEwj?>;8j~x059dgX#Jtv1ILg0_% z)AWI{KHKT7Qn!rtsX5$FMv%sx8PfP(Bn>dmO-uq$T7K<`V-D4e6^xA) zj*S(8H8z$%E|ypP@{2FW^2a8;fm}FBK-V!ftN-I>%Q;jsuCr z-l&#N?~JHYos*b= z*bgN}#V^DD%LyM_edctYiKE2(+1CnQP82gHF~*!Zjb}oV_=s*y{603)n4jao8B7$g zr|J|FW%28NtCM@*`T_JPbc*zH{RC%Ccr=kX4=195jVe&HEPkyy_pVqGn&XO>QAHUm z=4OmLCa__+1U_gIh!svuBy`u!pv5Cdq~Lw&YIhE!^)HV$(}|_XbV5m>xrb0ZYE;Rn zMa6jXlcNtXttM2gFrKfyz2G;-3B}k%k(#S%xxN?AFU~C)bxi*B{C8F0{XyPD70)+m zwkQ|F+;V0&T(IYvOvA$w_Z=5HI=?-efhMs4%Tbb)C z@^7d}_dQdTi58?5_^~M-kv7V?yYWNXNQD>|(uVhnQ({PgSDf(?uQ(HoSDcB?D^6+X z6=zb!D^8j8igOqj5xz)A`{^w=T>3D$%edQfnZ@AtTv{=38O7kvdl#P^{OAtZMJyK?OfIIwIk@K#KDj&qB^`viVa;Kv329k9vQSAP+B48HDl@+ksO z6PUlhzQ*cIY;Bk(X97EYssoO%779EAFCiW00)bZv+yiXV_to_Rzf)lTu=rZ51Mvo1 zZ+n1U`uhV8JR1po8(uy;&OU)368Oi!CVgMMAn?lq^LMv9tq#OahyMn4>5nUN9A8Zo z_!wZvIU=x+%b}A`6SxA{QRBeDKLM%dA-$v*m+^0#~qjc%K^t%uL%6Q;QSgF1jqlYz!OSB`3!+8 z1-?Y!E`e_XHo9RP3H+eIKNtAd0`pgr@37?}J_&O%Lh?mmr{^eK^S2l zg!oK>mk8V;@H+&4zrddr_z8hu75MmxVP0<$c$vWK1%9W%_W--HJS^~20{>Cq($bJW zN8l!bdj!5+;78;0M{+j4r zw!Flyyk`KrveX0|SjiW7soF{DQ^hb(+8z z0GqPF`O%u5m)N0moN=5cu)wA?I0vj{uuAalJb!#1jPOC)FJ`U*bla@3Fux-+2KC-Zcb1 zUvQ?J9P(!iycF1^@2krNUMDcWN#102Aa*)z0(LrFA8>qilfds1oXs;r{w{$(0Bq97 zI#b}!3d|3AH(MQu@38goWnibnj{=Ubo)-AvDIwRvzX&|(RF@a7eFE1AyjWm< z729QXBkr@hEeCeGZ3#HO>JhkKa4wq}^1B7T1=ytTs}BnNMS&j{n4g1QY4ss~yVd9G zz)qjv1RSi-1^)hNA?G=P|0M93(?iZFz$PzWohxvK!2DFQ*Xlz|U{!#SYUoExYg=FY%Mt__W?VPN?#8+zWTPnpE)zk_v-@x zSm56aTsX_+<*Q=^K22cy>@fQHDh9pQYTa72CGq!IT!{VWEq*gOapdXrDFAl*j1u~c z1@6EfTJxy%9|Ptl%Rid*kEXmwlMbJYIsN$z&DCcDI8zyMs~vD~YZ9D`rFtO8B`c6) z3J>HMMu8mNCy>t-^0S3p>Ypb#vfX_lm-?3r`H8@;T(aJB1&8hUw{VW8evT%uVxa@u z!s&peXi!&JvITNX!*)JtQJ8YbtyX>>_M0uP z#@_YAM&K?hUm+NaD24`*vug#dnGg+4aayTH0?ODS3<)vUI|Tq7}+bK;TW%kSE3AD z=f8-pEAPv|uDq`R8xHP0aoy|1G5I5TB{Ur4mC*Fzk-ZWcj;|_^{#7=8Vzx0tvIf}c zQy*~Pu?%>-rg%wWELjH!T*-v9|krYUp)i-Hp?e=>HiAYmG}98gXgrs9K)=CV#ntN%<*%84F{g{ zfX(>wlEjWrFA9!d9&mg$518`;(X z-Gbj2aNsc!_}!LI?D)3`{+@sXFWSJjSw6Aj^Zkn}@BIPC*UTKfjU|7Ey_q*Wjqxah zA^8k8Za#Sp*v%)zctpUE{4+Lg4w-;{$)Ar_8t;yISX{%OWO-WLG7aZP-(>Eaoasj(BOMHP%=ZAsZS0(XqoD!dFITHgpyo3T@ujO8nc)I1#Lxqv! zz6sckN8*oK&elKVk7tUwZe@lUN>Ai#71tsd%7{jvN{g2ksI%xZcHr@9AYEKbqd&x zDPosSC^z0c-I%Hu9AYEK7zcJ^irA$S%8hqVH>R2ehuB>=TY=qmlh~yb%8hqVH>NfU z4zasFb_2UHMeNcE%Gu5;gHE{YYKs?h4J*0jF zM+{>E&N=$Xc}Qj40d5e4Kh#+!ozVN~(}p6wpQ1XbkMVx$JgxE`T1ap?;Zp?R>l9Ts zDJnV3T)hMb6Z*_32Ze`9G946^r4?tPU@Uv+MU~HAsE?39=jl-iF0P{>5nfcGb4gSJ zow?Q#9O!&vR05q(k4m63Q#QU=SwC~2FjE#1=**Nu$z15nl!XL3Gi4!x&aBn(_)x}p z^POvT782-O8s$J|u8;%=IQKS!DGSen&f}sI=*&4$aG*2(O9^y7FDik~MUYGmQl1Z;OQI6!JT)qT&TolI zpmSYR0-f_9IVMaQIu}PJ(3!a(8*-p9a~Bfm%-n?pIxmVy_^as4r6lm9e4I-ek~x}V zB+@Tr3}?nYY*K>s1sO+NMvn0Rhy`Xw4wHS28w9Q-<6f!8sT=3Fk+l~0CUKieQO;K* zudc&!oPWjw&EeQfPv;_AUOv@~dzm>smc!Y^cyVS4qrpD0*YkMXn}Eo4&Sz~p?DwYZ z>H6@Fi-Em7?y+a5bN*yG>@jigIBXO6iw5UQk^KxdK(M9u(J-40j=)hD_t0^5KcyrL z^_HVG@yqYUoY13oy3WfjhqJm#hwT~-?Uuupp5bsDMnj+FgdV=r%l;0_ z;T6rK!@d{|cUlftDTc%G6AhoS9A4uLhy67gzHT|CSall?$4@l;!g3TjY81K=y@_vM z)ZdY8USmvdNHcxf28Xatr;nwrH7!UrA>@P+yH{G6X01jW64Fr_O<-p}$(dKlcwQuO z81o^{t#yjULLnAq7E)PqAxqR<=Jx<$?w>~rk!`Z5}mX1YC z)P#0=MEV&nEo&+@{S+6`4(H^(ednIh+t&j_{pyT$?Q6DfXo16zc85E*tnYHTZOxjV z_Ws}qR^2zW_XdXMQmar85T}XN(GD7I65Q&bMQN?0rNh^(j!tcDEp!>m)Wa^MDYElu zL9~LkC}X2bvMkUr_R@v3vp4kfzP)#CUuWp*{SE!R&ss2VemO&H;a63;_Vd1Oz41nj z+12}?o_K!{%(qJ6gB&%Hi|3TUbspEkx{sv9Rb=3oTaH}YyVEl9D;!^}^Bq6aewPp) zw%2Zo_>~gVZ&+dor`wf<)1T7$Rz}RC-!O|P8p_3?{n|}SxYoZV6Tc!np-rUERq==3 zfd5Xx=RL{i-hh9%;ByW7)i>ZjDEM4wzYPAyivbW^)s~c%RB3`Qu%sLB0onzc~ke)bib3pX8q|_*?XC@|QRvxLkP-f}a{Bzf15ZgIIh%e(`71&s3kc3jRj$YrszpGW`bx|EnO5 zPhSq}uMJ!p&x`q!Z=mmdE5?`AXQd?-L(ch=;SrJk77X~&XyoQr9i=MFPCvhKe3;-0 z!Z@UJH7hkG6yw1U*x*I zh~FzzCof#tvAMk`qy2IIn5rcsBTH4iwtH(IwSi&RTgPWVj{$E-%zC;V#iDBGHG$>8 zP~?n}KZ%|eREJ(s!JAm=T>5!sWv0>xF|mY|-rkpN@9F4ThdA^2 zU(|UJm;EZQdo!wh860h-_wyKiBOUV?P+tk>Fr#>!NJjJG(%AF ze8|VEy1Q5k_X)faimoz-A!ol?cE1_T@}7*%@(2_+tvxkrkCNR zSxb1Bp=Ees$dC%eJHqo)l95*hv=Jt#letwTzs6B`!SFnB^@wlBSc-Fms**8Kcg6PJ z>b}kvW8NCf$g$yhES6WmF0g26ZBt8iLu2)lmKBW`HdWWQthjguK5EJww`keQ#ue4G zhdtNC&rz{q&Tn2>*`VUXL{?tdtYE!1=$Nug##l0swUwrJvZ;1Ob!7vJfd?O{Nr#bh zMmiIQfrdYGLAu6ava`>|L%2}qWY9rk2dVJ_EC{>;RB83fhL)PzRf|x;%P&MFs1#vx z(X#5s3zw}-V=r2^Vr3<4xi5o?(RAt>Dp%A)x2QB(*|c&|jmk+8*HtcE)Nrv%q=?C0 z)~Iq*#MMZ81yadVxwiY%wD)(cZBMrKv~6z3WAwEu){n-R(BIXuPUWrX>grTpEU&j? z!oja@weiI8L^d3hc1lq)0jab9jq%T}P-XXE_X zzoJ@m!^1~$nAh2bXZtacpb@we=g#4YzjY^?!#}wb%QZPC%fqc(8_v$j)xezl z7L2&ObzNK6bhaZ#XJ2j)b8;rGL(2JGpyZVIk(gQ+rCt)fpwwGlS&wZ~l6Xauc-@L5 zw(ZR;v0cy2h7~JkVYhL`%Gua;B&)H#qDk*M>&V?)!|j$8%}cTCN@5$^Q{K2r?@vfp zF094ru{~2Omp0ba5-qE(Y-nh_i10*=Sk0TZsIG~E>5FRh{-jkrYDliAy|AVcYQ^>} zUDZe>S5`Jrn+u!GepO`?wYmt0++#NfyNm7qlFFvJIJ^{x+^?=|nupzGIOP8F%BHih zYr!G+t(8q@W7md5?$=Z{&Btyn4zZ8znb|Z;>v3k&Y`ve`G)M2}H_g@i^P1-A{RK^D z>3wz6*?PaQX};bsZmME3GghpuL$aIdk{8xjUP4JDBrWw9)ht@2#=QfpaNFbgzN5N( zYq-Mu=KNi?)xxQMorT%KAiy0nr z(%;tEv97MC{YuNwMU!HXujsHkF~JVbEGw#4G#OcN zgs6=?xTvODMCl_$Z7@+6MdNsg$n{vO+52}>_TUha?R~RX24`sq;W`MDE*lLYT&sok zRxe8HnfjW(Ibi}CLf8gjkbs5|wrZhEfKr`6OW&O8h9y{(+mzjryaCe>1-~a=61Rx*9NsK5^K)5BZKUo46;vUkUgYj zbt|S#;}VCj>%B?t=wp#18ej}{P1Wn?kyxYGtCW@Hb1G6}mf-P1Pz!y*6#>~RzNigu zMKMtYk=dTBo{QyXJBx`qUiYw*)peOCs~wrdQ2?dNYr$o}(CBm|8_o zGkr-viydwpp~EB_8uSlc!X9eQ+nOP*+cL<0oF*0fHxJ^n-35=&ofGa5G<$w@M#H~x(>%r4ZKM3w^!dG0g zQe%R*0{9k%{W?4+?cplF#*mEkJEqDMh91`DHni46*-18X6S_1Kg~w3seOTwK=7>0Q z2EVZh$I|e(1$+-8H4f|H3dWS_v8Kj6J~d@jgx5gOv=Qo*p%D_YJwE;|`{U!UIr>FP zcrTWIYj)kRk#gC=m)2pknB|0?VDzKlvW1LRW6qv7Ty5K#l69{8+As?fOUri6ClXn| zS-2pfU)2sR&ew7ndw0_W&~ok zTVQSWTj0y41-iq>?|iY)B97U~ao@MK-Q3q2$j&V|spph!VD+iu>9`*W*6q=I5mquk zx(O$dXnc0-cB6VaFU!-%M)h2tcU>7ixs>E$)JbADp*6F=pt$-unyU5crxD6%8IshIWIsnceZ5#j>V;>vV z0dQ_B4Q6~)I}FXSjzQI~bcd)){hQ=W8am+InpV%GD@^0kRH?sMm!`iuJhZcVusHdv zK{_a<`%}lugUjL5;64)Hk>k9on+>xZOq)O4sz#lf@{D?MMqTbxQ=%G@adXJH{?~`q zuKl}E7pI`^cHL7HZ}r|E>r$rftP|uM>&O(Yl2Jo>ZRJCs3sNw$ajmT59p5{6__d*G zxW%pgqq^$g;cpJ@-yL676W<5PT+}1VzIiS+*TJKhnvy*DT&+0J{f=5u=W*AYE9fW z{z>nYgSq=B;gjR{EF8LjO3kV&RXJ2Mg`Ayx?w``Ws$SLaugR^?u7f$nDx24(MHrTaa*C#CtZ_CDVj|An>3k*wBvjBpYGiS$FIB7HHbg^ zP|nmNHB*u^m(OgPd0^FrUL3td?TNqV<3(&?+$P_)M)w+1zd3CyXTCJ_TdyXU9Lm^U zW1l=Y>90eR`%86CoZ5fi%umcvyU4kBlG=4&(HW@0)4qGKLf6d9nt`2rl6QKi)UZBV z)q5I-mfx8iXgb6;UY@`2P}AV5nX3j8O(h#l%14IIM~gQNuoVstCT^REQ90DPs*s$Q zHr5>8b^JGm8V4_EDr{r=jkg~>{K$|8_sR$F$U|$REpXh3o^#QwQ@fjAJ*E5NS5NI$ z80n{WcMP!v`TeubdwAfI!KwX}PVJt7?J3<_pPv+E;SQ->8qnh*BvMvz53O$qc3~4XteJ618swszdC+&{ef|# zTV9G*#r8W#R~0{30dpYnXP2Q5pcf5XuqUVWz^WBqqKkOf(2Btuo?WbP-VFAl$Kl-Q;Ik{d zPlM0n^5?Mrz}XE-z2Cdbd%pEQKK*QiH}?6B>-YY~Q{z8bxF!KvcpO`&?ov&-&b2WFt2(XY{?FFJe#bvCtoa{nb2 zvCYM&Tv8d^Tz<-onCa;}HyjU~M<@3mShdnyInXim(IcOJ_Te15H?EpeJF{-)!kP6m zqjSN3!d0%B3z*KN$e6DR=7TDX?ploQs$g`-SMATQ#R!;!xoGE}MT3|}53Bg1I~VP) z9lNjS7egOWRVk%?X6Rd}bM)GQWrIu5;x!lx4HyecF&3smW26xDq(Y1X^f`=K^f|Pn z?jg8VvgagjoAxBwaZ}PIT~6;KLvdRpwU||)*PUeOGGW9|M(N7Y-X2ExU-k6}WyK8O z&S4I&XQMaTUb=YZ;$xnVkK15+Xd!wg;`DeNKl;F`h3GYKbPdMK8yRCpL0#eG{yNNJ z@eK)ybkL7m&cV(f9P8d!o^SjQax%Mj-)9XnID zW5etA%lKw*HBLnjGBp+ErdtI$x|o-Oyk&cp;XJHoQgR>L)jU*n@P|RpKM!*L zEpj$%Ip)k-uEC1vG`%9q3)WA0di_)rtecK{8`UF>J>iv)GsU51Ca!DY; z`XZ0(wW=veDbs6?sws6^b})D7J@<~SnsR|Yx_`#83Mp~j^77PGRa53cTBuV;T02qzdrU%>NO$Xcl(3OBR zx9O*Cc}>r>z0g%P!1Daha+19kPO`UZ=iPMc-2->oe0uXgs|>xc7ugH@oqehk`mcrl zcnquU>%Nh@Z~n5_1wK%rtL8=6OF17ZP`)HZ&U0 z+#V^8`k3>sO>-O0hn+UAIn|A{AH-ePm>S1d;8vH*QseOG$)(v|va>2uA4N8<5qnu~ zel2FwyC%lWWE@|f*tng{i|ykAznEcMRmpW?>IN!|E3-kf*s)hw%w8>wzNPV9NH^~moEbcncm zE41`Hb@`j)qT9R%q$b(&(k*_|nY~PU-Rn#iB=iRUG(0FL#&*ZzV`K56gx8r1<36a{ zz+3pw$0Oc{m*7Hp6^=%|#Hg{GV>xN(X@AkT(qHr;oLLg}2d*RU){)vA00Ssn z(q(^SyWrF-WARCeF^8{2Qn?V7m<07!C+R;K%NY*^;w6U=P|4W-2u;oZNCw+n{2!N? za3$*TN}V9dKv6Gib4T!(VTU+`jMJXF-!?#H;Lf>)y0iGm)p)y2&%KD0TJIINo?5e~o{ zHsEuKF^P$XIup}2CFX8QBzn;VIyu%r0@YoF8f53lVLc{Fpo8x3sD&pxzoYeH$qwnt z8+)iH;cxCn&9fpgD1feHyZEu3$!yJ7&IFW^U2a_BxJ}r{$0f?h%^iOzF(bZt6QyX= zlfmjtl*IS%+=L9_oZNq$jfRq4sY}V$L^=iEP31rEi=jYq#{ zhr-#1`FG_ZbTOuNIFX1i-4q*BuNyS=^mi1FN%)w&HgDFaqt2-u64D6Du?#Fv{6eHr zkui;LB8|l3Y@Gr-`Y}mo82!K0Jm!;+9176?`NwfkNDNsn{(zxR{Bt`u#m27=((#=8 z_E^MyJB+~7eS3~`-=0Ww-<}(~Z_f+;w&xqa?FG(ndtvCwT)JaV_p?4KGcn!M`Y@j0 z17hH7J>m&|csJ_85Bx|j*@YkYkd~gQ@B=@5mck3XBLyi19_2ImfDcGP8MEO7{y{7q z_@>&}U(!IoBqib+o`Gw22CmT=xaMYXd$;cAx{rZtT?VeB8MtO<;QE+>YhDJfMH#r3 zW#C$sfooC*u0I*L)?{$$>y?`k>1~eQ8lUeU)fhfXu>X+7=ONu~8hc6N*(RSPt;XJM zITr>TUtKKlWr9Nssg6&d=MJw2Ht8GRC|Bz=y(DdotjGBX$<2a)3$Wq9Hom}bi-&3M z75MYOj{gmTX>H5NX{KX`&6jwc&G&o2cWXI(K?WROy(;jpQGt&0n!sfVm!_{y6_`Hj zOOf3CGziHtz;|ottJ4Awe0d0b;^>ewU*M#`8wI{r;5!8V z46xAwejEfoAUHo2_!)tJBXB-`_3CsUEAS%%e_h}n{4&h(uM)Tk6QYwpCh*S$&cpTB zaV84fByhLDTLq>scz5nen3Q)b1}{nMd|aLk>^K($9A8xnJPW@PFz5Q}B7wIHyi;KQ z!0=|97coD%M@ZfXe7AO%s5OmJ?-1;p|15%_?>KNR@C1fGUpEEpXyM+wYd z=iQ=p@RG#VvR`sGu*<7H;P|RR;N^mI-o%jKEO58Ly9NHZz@G&+I{1n|LA%xJL;Q&x zeUSXJ;6D~{eD$QjKNOq?aS?X;mkWH2zEIG0?!3D_3x`o1>P?3y9K^a z-~$4GPvGYS{t5o3W0#^%sk-(P;%wNmxQ4IL`81VC0D3VB@o{0A8q~^{B42x<^7;e-%Ap2 zu=zd#?9%*0z`;6J;1^E}IR(=~e4@a!fKB>Xy8_>7^CI41^O`UCD*_I#i2|<{oTbyl zysi-VMuGPMo4kB=zrg$``!1^kafj96v%s#rPX-)c{XpQK3eFQJh5Q!;&N(@hPXIP~ z!5=hmkIk33(B^xr;Li^@zB*6f<7c>YeZ}u>`)oSIQ*AmY0XzMd1RP&A3cNyaX#LWp z1HXa5{WeYFzi6zI^}x>mSG>JDHhzenIt3H*@2T#J1f$JCQQ+H{!f zM~C?XO_x4@nCa3Vi?f{0#lWuq%YYpR)3zPsE!wx9liwydKNt7~f&U;dz5oo;JPq<4 z_@mCVu)WUW`PjeR;ycBqbq=2UM#OG z`#4}%b_`8>?Jz#jZ^kk8#PABnIPoNkF^97(ZXB^Jrk;&IL^qZzAb0#4!LJ8)<22OY zOAHf8j6U2elMuPJPkV>MPurswowyy3vlFR-aY`1u8P{5^udH{clGe>-r@ z^zX&i@$UzA=|2E$IPmieZ0Z)@+X()*1pjcrfuCRCUHD`A&tU7){}r%H|9RkD_~X;B zzhG28IJKq zyW6IZul$1cS}FL=z=mV|GMm0+{4zUzIt9NQ*l>Jx12Ef(`V%|;Zo$7L;J}|FuvsU2 zN#Ys$T$TK|;NKf?eDy70wms7)F4tHk>5JLb{}TbnSI+|vXpWa8cKW<1_%8<>_+`Q5 z$o|Cii5;Im33us_4mj{<3T)OAUXs}HrwRUyfa5FrT)xw$Pwe;=f?pGG;4>8XF3Tr& z{MCZr8gR_h)*Q``CF@ZxGp;?2%e7o3mjrUtzGf_&_QmZ3Lvj;1M((TYf!(#37)x=@ zxiOHNc68&K?dUk1+uc}x2-uBf;&PkLBZ1skKLg&OjalMpHXVg} zFmhj=0KChlL(KURA<1^xr6K&f0=uz5jHMJqa!DZf6`$F@U5h>a{I*aUEHd2qB0kr0W(IQHzW}>2 zMSK(L2qD=X$bI$OoNycw`hI%FLq;L zf#47uxw&4uu}~p6#BMCq1Mk8g=QLuMS133Bi+5X2QgDck-1skkyX7L3d*f`8fZ)vmwQxg2Z`lor9yoKmwo^bAw=NjI;fx%0}0vojvH@dgR@XU zIfw~;0nbKtu*O3Fyt7gGiBSoP$`wG!p>JYd%Y_8xIzK8w=U5h%pj>#dftGeU&p|2J z6NCh%K;lvYoq69G`re%bomoFZ0-YP966nmH7jo#ExGgGy&fQT7bncHzp!55q66pMe zs02D6h)SUIe?}$H`Sqv-Ivf;54@D)=nJZ|K7j*t{R05s3QVu!vP5fU`33QHQwIVpsc^t|f`bs_vI&Xrn}G{&7?SoqrjXK?4FKn!%j2z*4jq`XW4wH4>(|CQ0dt|1EYO4dU=y8uvCeuTk z<#4SL_jsL15BB}3{x&Gig?WZ>w@rs@h2cCtKWI73WjL?L&g&U_%y66`n+~tv!+CRd z-pzOgjeC>1#a}cyk7m4L#XX;y*q8{#_=|gdBAU)|p38I!-VAW;NkA?*Z)F^H zaZl&yqJq8iP*$Qj?4!1z0Yj;8+oU;n#Jx%p6GG>SY=Y+S3oGUq4S%xfa2&=xetpH3 ziw5U$j3Yem?ZGy^e>g8=lQgHETl__X^DI^dvGK4Rjpvc`CZ=0Tw^w@Eod+?lRN~&o z^h6+WUcP_2=e!wm-i&+nXXtzwhE(SfO!o?pKEcw1^8!|m zsJQnCw&`ug@39!lu!@W6V!y=*#J0o^@z7&0+anrIvYcF|qod|o39nWrWwvxQ)LRaI zvTk!{D@H@B<%Is7(@Wue9CHm|@^atyg=sk-$Dwaxws$mq$mUfN=);i^4WG6g&gv$w z^xp6t%Tc;EoS{gQ4oa$CMLazkFS>Yc+lt=xfz^*xbCJ#($nd6793!w76536ZUZ6s0 zx~;S@F3o&f7!?{Uld`~hjt~ZR-2OlA-UYCZs#+i4b5735Nz&IeO(~_6Lus+RN|W>n z6_Peh(~!1@z9^-TrcK%gLQ<2o6lhBel2E zLg3uo5a;5YAm`}pkOJ<`rsX=_GVD4=Vb}L}Z0UFIc8g7g&wv<9qM4Pw!Xa*5Ck-sIPdDV*2W+wy9;NLS)!AVFVB~-liT@3V%AK1F=Sv^YGJ_BYVw! zT0VXq^FXKw_>AFBbqYK`M zf5jW{FJdx&iT}Yj;LEHTTgSE0M~yCVE=3O*8F-3b2h zNk*7Y|I30;G?cL|7YY8k&~-O;Ewi>d!J#`uysd(~4Hq%`WFw(5H*Lefq4Gl8)#BWxkbgOi zd4Osiq{f*a_bpjEq?sVzZUpv^;iKSJ=I8qaeN!Q4-bS)l{9WB`ekcp%2yitw@eS zU&-o1)f68>^`-Y8pm`O`GMUzf1@*0Sn(7xWoZHemAH%e4*_jwgrmS$zhPLi*EFv7E zSiIjk9ZQ=Qw=S8#a&GIiDYMUBI@fA(((0NST5KY8;+m<`v^Z|`FWrFt+lHR5_9dN{ z;B!JBhW65J$go&(ti2r{Q;Hp<$o5u!RMOSi-C;h=hk)24$SbXZsASE>{XuA4hXx{j z?xJ<;(2|nY5_htdxyx<9m(F@SH}>O02(ctA8A0ZhzZbhi`u%i#2OWPDyV6lGprmB& zrr!FHtt_CB+0rIsaY#y>7I{_1?vT`(W>aE`S++HHzqW~t7*UH|`AqC8^@pj-?1!n! zLf@fEmSum8sVw*~RT+PnDj@NPsmjcUse%CWVXBn;FxBmdI~9DG>JvCjq{+u4XjlHM zKK>#0W%hGbfj0ZODyzfGQr>fGQr>fGQr>fGQr>fGQr>dgQQ&pMIQ&pMIQ&s8D zQ&pMIQ&oBNd8#V?d8#V&d8#V?d8#V=c`E$c&r<=}&r<>M=cxeA=cxen=c(|kKTn0< zW0x!J-RG%*_2;Ro%;%}9?B}VfJpFm9D*Jh=D)V`&D*Jh=Do=l&s>*(zs>*zxs>*(z zs>*zxs>*(zs>*zxs>*(zs>*zxs>*(z3i0dDQ{h*Co(jME^HliNpQpmF{yY_a_2;SZ zt3OYLU;TM1{L<&C@S{IZRpmZU1&R1P)zGhC&V{NYlwMR_i#yudUB#g*bLzu*t%Vp7 zEyrovlG>=2AvNk-g3s~lico)o8{cU}e$}-y)#0yrz(N+r_k11)}?tBzUdTtr%54thmKMR14xvl zIVKm`7KIXtdg~^U@-ZS!r;DRarSPD6Su!m+y*^`yB?I7oqa)B%5-$McjAkXw9yE}>!tovAy%XbdV919`p{dc8uKSz zk&4iCvb6JT`sNljWDVuX%CMXShta?osdN62+|;RG+uyml1L4II$C4sVn}?%KoA3WG zPn#4*r$IH?IKOcbK10>fdtqDe1v+tPlEBkrghH%HQ|Bkqrp{mf1*xN*_f|^|O@m-L z`k&#>DEYk?9lga{7WA!OT)#jki>}agWflsGG%XHBn-)Vo-GAuaGP|v>!whyUMqi<= zx3}$L^%ONh2BKfl)zQ7ae}mHgwHOm97xkF2trlBMbzUC55O2*<4B@4DG(&tzr-`dm zaRs@^;%3lZNtD4wV zQ&4FbSIO*{$5k>oQdfN-VprX6T$R5>Z_gvPuHw&YtWgiEhwwR#)!svQzX!{s+fPZ@ zk8gAr4eiPw%AcXA+YHAqPU_Eb%#6{|oV|lr4>6zQz!Js{_#}Zn+CH?0w0Ljw;M{Eu_n1YDS?fxzb?)9#s~fI(e1F<#eyrh&hTYzA-<$CK{dbKW=VZUQ zX1u}M59=ZJWET>!Yn<#C*G#eOs}OhU;Jlo;cj~z3?X6sWykRCA$4=C!;fnpq$HzA8 zZruCq%?-Qf?tT8|;XS7~&Wr*a`d~%L!8u#QSNIX@w_&SK)aSwDAD|B-#12Di&l4;wR`{GSN42$pyB3}wUm!@Q??X~faB5S zcjI9xcU_O>%q>U%c-P^cySm*pzjXN4w?7L@n>Au}}CmTxd9(&W? zuie~OPN9EXM=2N1HKcoNUfoAIsnjhsH?H{F-kU@e!;Tb*5RC5%RH_PlcopSPumP7{{F3|(A(7uq~e4gHraHcT_V z`nj|STe7vdAZ%`h-#^gOwkIaMPluL{#k!+c(VDgS0zQy8K(CWK1*a@{Z=!56R_^?H zNTCk?9xZFD!#CWuZNps&uQQkPH{vWJ9cOPiHG{u|H!GKQJFRMaICz)ag-YpiHj3no|SzEh_dh_iLwV1{+LAB>4_ubmwt+%SDzc@E#%8$t!U7M!dvkGG~d+(n`-8R)MM9RIt`2RxydEDk@HcwA`$4OR{ zR4G=*%tLcaRf?4{g9S7bSJqWrRhPQD&MkXs*T$SRNbAD$BvVwZJf5=7syr1}kK2tq zc6xe!(yGe=C>*a2Tmu+S`QGk23{DTDBj3B0uwMBQa=W6%cKF%)ds;F_{%87ipodI`Mmk#WQj9#>{s3YMH<*1zs&MJ-fktdK;cG zmV$P;RN#>UpDgeKfoU~L)^nr4Hw*j$fj=nlT>^hx;0FYLOyK_~Z~}v2j`w7NrwV+E zz^4oRMS;H|@Y4c+Pv9R3{DQ#c$O>%3;R3G}c!R**0@D}s@VW>#FGKhqqzAUlXkgYk z&2fBnioi$V9w&3A2s~flRRZ@4e2u^#0X8=H>N5g=QDC~Cda5?f%MkvMwevAxwt-f) zG#p?3RN$|mNHOR80{=$fg97`wC&>JF2;2zF`p**hT!HC+BHg$me-i$dwX+?Vb?$H+ ztSTXJCnn>Wvt8i#3j8sF9})P60{>ayN>r}K9$$?Y_;`Wo4%_M0X2Q2yo2!A@o&}EM zt1|^&E;y&4f@1z6fjb1gRN(gr{7GPAgRdSF_(_53=25-1lklz9&Tj*Aye~VBuYM=+ zp9JUog9H9=1onmmavH3%&XWaR0BmgV)p-K93rx3B=2$xkvp+8YW}R0%j<2p0c#q)p zqe5r?wF2KE@Mi@6mcYLOHa1|T7J*~9jlgocrGTfPuz4B6KeGNT1LkyP zM}gU%XC22^&k6jz;CunIo6P@~z|R5KYL&jC8Bn}-h|S9oKEcNIQ^9}LaeVcf!2b}O zpW;<4j_WT1$1#Oy^!tjY6Q|p_2ydE*7_I6wRanDYZ+ z=Dg(738r2C7VI#+CSitr8 zqdY^H;|k8xN~oM||svjPdF z`(XT)In9(3M}#DlzQ=_mw0;bo6|9s~U2V#nkl;;>Sz!(?gU&K5<>)nLa2a&9LIR`d z6%HYR(PXn(J4c@dqeq1$Fq&)@92k9MNJ4AFydx}u&Buo&i28)E1U6IbgPnh9Z5WDO zNMJL?E+nv-ViywFOtA|IY^KyYgQHZn0a;VhBJxWWm zKD^y;4>6zzhvxBeIp4IL3eBOip38aJawvbqy-9gF{DvBpxsq|umXF;Z;e%I4!t)vE{Df&K9Uu2kKTRc_ZEYlSAV5Kd5erX)WaI@b*2cooZ3Tp|lTg^f)|iR4xkX@u)yx zqf%LjQ)xL=LmCd{kMMS)IN8Yz4|9j+9!*7sJPMdA|)M-$}rRZuLD8m1h;4cAw4E)!N*zV>N`0gV|1QDb2L8{$f3^t!Yl8o7@SndF~kH8;agnzZ*SAu^K{8>f#w+jCA;E&&dGGqDq{Qr5uzXSZ| z;iO$f_|FMGmF3Y_DD|M_=kxzx1s_SPF4=|hX!&+NAynRniq1TeO7&ie{Qo@wZ29=_ z5d7KTbYG>ZpC{xt`2lDlKL+b{8b<<2medf{(S!bfZ*={ zf5%tqKOg+9yYW|qPxs<^qw<)! z4&|!|e}dqn>QpCQk33g|KU46RfF{7&%D#|4bHwvJ8Lw!Jk!xPtOMMRt3=g zA879^KV}1@{@sF4{=5bJT}AZYDflbFZ$hQ`U=jX9g5L%H>)^jwg#T^9C;iXvLHqR_ z05%Si_P@kJgjeJ5nj6s`72)e;MoAeq^3TiQ_gj8G{~Rd>zr-K07b|-g;h&ntKMnkk z6yYz);%@-|OGWryf=~75UhtnS!oO1R)8Ky&{NEPge^Bt}ga1F^m;4X_8@pQi|FeQW z5}e)dL3?NU`TY5H!CwddL*Ta*(f>=qC;wl56UuK9{jX*5?*;#+BK!)jR{|dpU zIhheRYiejm_m6nHQ;c^;l`8cV__M73*DXn|1N0uDe;m&JA`(BM`iS%GzcVoxG@V(pX(hw3$Al6H-lWO$93WcC^{$zY9`B(D(@ka&%lq*)^- z(b@`7J*~B0#Xb#V67J{=I0{ZPE69KyEE)40(St+kx$DCjr0X>t#nUNRpS0`8n3&A+ zFk>L6n9R|5V!5lZtIOD^3}ZI&DJpZg1c&i7xkfAJHD|sgC zunS>q>BCy-S4pX}1@HW0Nh3UnnyGKWBdBNAH(|dxLwE^prTKb|8DFn4IbGzF&_D~^p!A=6oW};{}b+j+;SRast477ft z;YH6)9Rb4}BCwYN^`c)c3Vk#L?@v-t9^(+S)x{jB)RC&;VlJ{AN#;qx=xo6R5>(Ek zy{hOyYvvMoaYtJ_#OCIeHZ2?!Y0}>sZPI`HUz_xAId!*f>YQOxlWKb8N_%7yeul|A z9Au7UD!p%<}x7CRDU7bRR4{)wQzwi zQrvP}TS+4vPnE^ck+l9<+<}_~+HGm+HY1MIX?QCuQvJidqJ_m-8x6_|B$4#9X*s57KbOs~Vn5rK!woPIuJ3(wHI^M7sh__Uv7dhy zE7k-bvbLjgjPde)XgFk35pps;Fu+bWEr|<`)W@$z?Bi7YU*lsvtAJ(fN3oAh8E{Ud zjC>gRIH!$plt}$NHXdzTQ4{}H)fu|`qf+-Du074(vsDhcd6{%`R(Pa7-WsuwZ!79! z)E93wU3UnpZdsStk;5yO(q5GFU6YH*GYxqU#!(Rmn$+G?hLXaVmZL zP1QJj*}7b#Gd|pX+xsXP$qD4R&;Zr~ysqNpmB%8^$x(8$kxsjGoS9G=VI0?YEISSp zCToT7bOE6$Vbn$cnu!#osK6yJIWyN^ERwZz^C(o=)hcPx+e!fuY( zaUU$|IG%r^OYP|6X;s|JV8L6;n7;OGsvOV#ncPQO_!gVKm&_9*$eA1#sdqmWv3I{* z)VpuVc{=B*vV|vT=gCns>c4fJ>)~5Gx=J4AXBD_7Xu~6QWIP#d`Tk+D*whk_midbF z57+clN(cK-juG21LJSJFJe@3RKs|z=AI(j#^bp_n)0GyzoTw2=Ji}xyX z4aky%u5WexvttfCUDeqKn*xKJB&Q*ef;!3=mH$P1RW|D+E`V&W$s%0I(Th3UxaKk< z%}0Yuqs>P*lpe}_wDy9I{_sOhIx9Ib=ca#kYMX({?IyLaJ2`)9bH)2W!PF*3q^W&( z#Hl?ekBl5<)B|u zJR&^_>}m#A(K(5%8t}+V_~A%>i$XG*iBWmK$xe^pH6FCy^xk*4*3h$7)b@mfBF#W+ zQ_)rz*QGo>BaUE|JxHS4 zw>*!@%B0jI1S!x}1q4Vp{iLON&UvBD6JhD9ywdaYO1F@-5^v*DgHw-tyrGQ2bM9)0B4HZm8k4aKJbt9Biafan zmCR;S$%tGU*3Wqt)P6_Rk%oC%Br{!3l~YIgK;%OG&~7*a2eJfBlX|tS&)St7iFIu zh${6|w<=qSN7YbChy*atARuMTDqp&y$PJD(aXKSToXg7oO*3+px|LUD&&NJHQ^J17jlKHKZJp+Rfv)6qIg_q;lt?}Q z#fUxsi?>@Hy@~q9^>bZaP=W5oeikPyv;1Gz!A`rq6tFKb}+H zB;RhE?L;7%yTs@Q1tUc2g@s-*%jweS9!2G4Ixm%7g>E*oin#qp4ys>!0fONpB2iY# z6CP<v4Vg+wFSb7XJLcmbSkBOdHLr*tcs!qT+dH+Z&!QYlH%~;m@N4Qe}xc zor-eqRVL#KPR4wMNYnAoh|}?lQY4L}`wLXaXKDAR2BAo0)wh{V=60YS0OYHX zi4dvlpNZJ@_Akc zpdv^=_T-Yxb*`L5CSrlIe4$Rnva{#vM5Jc4v1?P`21u3CBX*t*GU7;+>|GHj*=H)= zX0?eKKi!9UtM?DyL^@n#(&6`b_Zf96wOETg-nFTtuYW#GyI@@w3a7LP2Su75UynFF zUVghp=uMOkH_&jU!%5yms^~Y!RN1?+#zeO3gC~^q17|r&^DlTjX&~bCNe_CPRb1rh zqf3P<`~Ljw^bxNf=;ueWlE(%|T6$^+McV+KHmF!_R>bu=`Mz=lRW7P*+ZoP{G?mPA zv7vr62Sn<+xb#fAJ2*?{jus%YN9>hk_M%aG$;02*%;z^K| zl!!b@MXdyx6Zr(l^${o4y@x8PB1n(3O|kg`T4>ukG;LbL1q5OG>!q&I7GaSVo+lzs zk=NdCtH32Bf8qJ3UICC*T7l6DP3>TwHz z2z~iXmnxZydhNX_DnWR-A?Wr7L6H`q&WO`v=bK88L+b2NSfmd8MZ^w#{;-aPVmf+=t&Yo^N zg+=*LrSYfx!nwhbx^eW7XnR*D4kZvTvd%`&M$b98=VhJ1c3WSqvej;BgSRd_hlp2fJIp!o_264v5s%S4ZsXTZ_8- zt@yE0H{q)6zp;Kg+{SY#^vK_aHoQS-9psnwMV4g}J$?TnTZ%99dTuF->V7xF6&qE+#Xgok!8^Wwnf|f>_ zNdFyiBK`f)<#s!lx@@&}8lE7@^%)Bzb=jby(YAYs4LxMt2kWwH+O*5iKge|%3nO*e zu@Sqh=8(JWt828&GEHY^dM@hdU9^s>QBgW&K%}ml9kJ^c9CFvaj&*lXt2qzRqYCC5 zUb-0)@<<(bZp4o3Jamq;?fC6z0Yp1(9t6{m>+ubvMQ~)OEzjaa>d?y~cIb^o9r`Bv zprGi72(q4VG>1jn@}doP9l5-c9u+_b^%tlGkU|*8a%ZZKJE~ZjHW(LV6CzEQ4@aCX z_ZLlh-#xR3CfgKHN33o$zTuS|+UCWYh7M|rVPDo3$KHgm z*Wq4lA*3ol#=BIkq({B~o{4G)T|>5x>z$6q zUhJ zbY+z>_L+BTIeYEOrm?ekKRcvl?2AL1$2KJ!Z<+hPhTSd6{kI&zZ*%hW0YXj5msYnV ze~JA4;_CFkAai|nqcjnv5HHV(~OuJ zipGS{te6^-*}0oydd9_+v?+@8d^BZn@}5x#2U-XAeT_P>wLl64Km zHzCd*Cm%PA^^SXSLc=X{-e;`KW?$jhP01;3!%!bpx23V4)HWIW6WZ#qpV*ecenQ)7 z?8mij#QvzZ9oUa)+k^e#ZFgcnvh4xvE88B$epuVn*bi=d0sHc{SFk6$t`jj)?o~I$ zyqjQOldiwKO zmNsfj8?~j4+R{dCX`{CE5fM`b@?Oj%dz#Ab_Hbf95Y|4{#s}! zk4JYMe-JSpy}Bv6uP)WaSF`_#I+Ps98l-H8k``fya}n#YSei9A79jn?U! zrew>Ftpj&`d;dG>%997@X4T(wN;q#e>ojcEY1pjOuvw>JvrfZiorcXi4V!fuHtRHO z)@j(R)38~mVY5!dW}Sx3It`n38lK@|Qn7}ybN3EzYfhG|jsd57S}cmA&1e|goE(lc zj_WkWH5_@Kuh6LHQ6-O>&lDE0KUIv%xiMoP>|-R=#8KErw)+G5aV zSR^IZRe4&5k2s5?%oF#zSdjJ$P@B4(Y;r`IO=pv$lppft;U7pXqXvFzTCwMxH0l!i zf{3ZimC*f9tcJZKd(s0cjhbh*ytZKo313^fz_lHo;5-`jRUGYNLRvU49^<5q$#QXR zrW{VRS63Ojx_t+}jWQ~)w+>e~Jd~FE4&325#Z$M8rOtf1Y^iFuna|)V8J_Ro+e8sg}bzb#Wc% zz6OeWgi7@6n?sUe7K-~CJ}@Vwd2o*Al0frptGS+j>y(LMqKhGIW1!kG z->8Fn03%8{-G-r05LG{8jEkkk`mp($u%93==qHmVD+c1L=_RIzRl0107yS9d8ysa@=iahy% zlMRctXs@>D_OwN}r!BfYZPD#%i*8R_bbH#O+tU`^p0?=rv_-e4ExJ8z(d}uAZcj0; zL(HFZu{0*z+8UCrZH>G4FPPlbcm>il{rEjCIxjX{p>9BK9P&7>pYxmPSvQSsnpe_= zb4GirsiC~9X?8*%4O1mOBu%NNMlDJ1A6u;@$~&n?#rA7W$Wzb^FFVcTw`|QNs%b7X z&nc|g#HGAz;NS9t&DOW3$8dfs$ejzd9~WvrF4TTpsQtK5`*ET6<3jDnh1!n`wI3I1 zKQ7dMT&VrHQ2TMA_9MpX@MEuwWhrv!kzEUuYaaHFn=>$bY{O%V_j|F%$1sLU(g@c( zuKnSKNfQ!#IFp<`&^Wf~F%veXXJK+}!SmJ?Ja0Fyd(gp_JDcxmve$0<=Jz?PhQ%`a z+B5pvGy2*y`r0%4+B5pvGy2*y`r0%4+B5pvGy2*y`r0%4+B5pvGy2*;<6>E?uRW8* zH9i!3SYP8;apn5Dn|Id??8m5O%|jlpIvm!rd;i!mJ#^l>g6FL*a2}5Wn|0hl$=11O z)TIM7w}P++s^3Z!*AM}ZYPGbkH%)KPoHspmUP@8+ zihcKZWesB=e`5d5UaWq3vuaMhx?06d{>+}S>TxzjopKk6n1-#Mvp3$BLhnXBeAnJO zJsL8jVCv(P>vVIYz5@r5>o{l2*6O29W7IwA`$SCPJ~P>7N=evW>Q|=p%$2nGznq>H zo!6pkPk%0ADp~!=@_Dg%5B46lo2HMk|A~1|m9(jtclZd5KE2~iE@~XRFj;|I)Of|N zy$$y~K5JppJA5Hze?<{)H`a{H^dRN8r<*&^y#;Ehxb`jH1ac%KEC!$R^a|a&!Z4+>1 z`xXojjjH$6jSd~tY_%UAnbnn9h8dSpTaa(u^R%-f>a=`L#8kKzPureqcAiTP`d8(- zAtENWGhthshOrI0Zl*aMY8Uh6pc(Fbo)=qRt4lT%z zGMa5PvlvFQ%S!Uud!y45wY~3iF>x;?u-Ej^ss0TtHZrpL%b&`g<2@jBMLQe)tc!_8 zi5NA&!sctp&-->?{+(O5m!TvFlB*zTO8U4Tv9E>ZOU-znMrx(VZRY4vopT<(F87{K z`KesysNWCdV?LG3L|;B1^W|LTsK4jc86U!_ zH^|(-8bbO?4rce%j&eM@H@Vty_5G<-aDT91UuljzJL)`ghKPxK75O}Lz2li{q5N~( zo_$xEs}IjheA#iMoY{HY#WFN@*Vy>-=GeZI?n<7zya9PIqjO$Ea@oNCrw)9Z?s_$0 z?6`73vqqk}eC5E$_cq+}vAuI{Y1q%~{g35q6aMI8Ne_(CT4M#;1b-;!3}(g)Fi*%~ zsshY;j>&VcbcZuv`mD)e?$fy|ANNYfjXHPTAYwuq?4L8>9bT<#Rm|VSZ+a}Bb@#Y) zhQ=uTWVJ!{s0$T7fUY*FHL4r?J{(cl}weUQmL|3d8#5cCUt7+^wgZxJhKKSsCuJE!z(X)zpAg?7Hh1$te#%D;|)|7 zHa9Db9(^?DZC{KaCC^K{ux;nPm9TN{yzQ&A&%-K*9N(7gu<1eArtC0U2*cQUaqLV4 zN;{{zux)+W=N;+7wx5$7c0>?%c6QidE^OPf?674)SZoObr7i6)Y%U#&^*wU;pdTNk$c4dXpmy0;;vaB$Amd=LJC4|y_WDrKtg~I4f z8+%?RJB+^AVZ$hiLgzj2!nVbJgh1)DJ4D!RSz)voz0rAT>=RjGTV2>Cu}iYTw!5&4 zV_UPrXeBcY0gs4|f870dI*@=~#DpamnW zuVds;s`q%KmojYF)gD!98!ETgS6=otS{qo}m90aD(YxDLM-SA8&MRhf6k)~6M%vk# zThG#aRP3X9S!q(NoUU`{ZHu*MofpOR71LSF&PC47?Xd+}cG9z=_SzRx`i;eFB5|~n zxU1o*34^i6uim_9*YwkIBx3ZF@ZvvFgA<8!W936)!-mExhQ~^We=||G^N)$dfrR(9 zWGqJ3Ir5Ge$U8twl${+b^%GvKbZ9o`HV>ThoWgIix^E`D+HCF%#62fgK0M+5HaqO< zxDKlr604|8ls%b9#LDoyJ(2hW?Y;lb=HK@wZ2KW`&e8V&H?BHSruW{qY+YZ-j$6lB zDCTQQ1}6^RmPo8fjHpdi*48Ex(-UQ}L5IJx^W2?xCkDgxR}y8ftilzP4r73C;pKQ^ zcLLU(i_1kKFt6wd-=Y(6IhB7zN~DHmU&X67csP<0QD+C=o;1-7-*$H%V_vtRLt;}8 zhdr^f5qU_TDm4ZWiLykwA1fb<$jWmfdof^+PL!=m4BieGl~#s-%SOg3s&M)sKik$X zr4Z5OF=U3Rhp*D-pPd-8Ju&#~9ms2RTpsh`vsJOm!*Kra;o0ZkQO1VW!qDxpGUT{C z9(%^obWBEZYG|VDu2>lvmh0o2%31ML7*8g^lrnQhB~GGDoA12m?Roif{%b*4taM2B zrQBR$V#Jv_`Sw#m*oU&uyK)fDL+*kLDFt4M4H-$vup?1+Zo;3r;uQQ#l*QN8#E*{+ z@e+e~B6ZAv1jEzVpPd-Ko%Vyzjisvc1&2wv?$VruykQ7iK?y;ToU8Ky_BKVy9+a7~ zb14QLk7H~%X)YNQNls?_#SzX$In~NNLlJg2xdByP?Z`wKO6bnJVyO|7!|CEKr+wAg zA59Ft0_YQo!TVMf3H5el`}r5cOytn6uW<0t*wCujU@8_vaxA^a2l=C9jUf*i78_Cp z9>{}p$R8XI@=Eerg|D5qlAKnyGL{-1mf$KNKRd5)UM3~ykdgv9dT%8NC}TTg<&@>i za?JQ55nM)sqtH}P{d{hoN_@u%aJ9E7(^>8}chdQ&Q&PjHCn``ku1buJUm7d*5*1q$ zi8XoZnU_fo+8tBRtb#-HT6Sj@Xs8dlIx3?UD)$1uOSCH-4OIwQf*6W<;&N@y*@@Bd z?N4Z9TJsol&q$nZt{(}EGK5AjQFa+BW71J}8Coc+z;o;OKhTNJJbfZsv{-2sa$v%b zrBEBj%0?Q5IwPkN`}$!rV&lx*HhLh3h3Y*|J@V;M#+rOJ&<|{waU`+|D*rr{-}Q&f z3qpn=T3Jqy;A=#4si(CiVks0oG{K`O;d08~Llmm>U+rir`el`| z!TA#LzpWOOm7H4e`mrX4eCOR|!{E-G^Bya5-j9Rx@?^IiN4ZNLiOZ_U$t54QgrH~S zB~+|Do|->wXI)CESVGN5A38o%)m9KF@x3_Ohn^QJa1S$<$J@u(+6plSJb6;)g`X1tGKEzb#-0hn!1Xc>afmznIt0S0<`jc zv8*MbZMjOp~(U#VGrN-G` zn(?BIX18dYYJL>WTG2)`RJ74-6m84Q4`vz7Ml(vZ(d-dzG*d*Id6!hFo#s%{=!`ZR ziP1*0IJD8Ils1~3p^au@Xk$LjzR*T9Ews_B3T?B^j~h|b%m{5X3qsoty*D2+AV{+S zw9%{uZEW8bbEp>=Cdk*v@$-2!%BRgN)u0p~(+Hn7=4b!%^`$jSDH=`F#(tntGHu!C zWgj!2Mys^Z$W(47C&V&I2zTf)sgJo|_|4*(_}y;tGJ#hL{Di>I3jC_TCCGTJXSl$l z1fDGLX#%enxJTek0zV?~eu2Ls@FraB>-ysH9X#OIU>~;3W?;7MTF3D*Vb6SDbtMAM zbpk&i@G}DcPT(>)m-SB&xDMFZ@Cra9l?UJRR8B=Bp-w&lb2<;0|D=?e{W-DW74>tOI8K7dwux zwh4T0S-{yM@Lph}(^t0$d^>Q=#znZ@#&riU$Mt~Y`07D{Zz>Ns_X_;Dz&{cAFTf@) zU%f7H46Rd%wSn+DYeO8EZK!e_UmY&+-vnnkDstwZAaH}gcvi#4<*PLUZvakO8wl51 z8#;km=QhXj)lPx05}XZaIhlWjz_$S#{l5CJ!25txHeSM;Y`h->W<6hZ9AAA+;QNOJ zoNo&JD}lYCtlw9|1s)~vSm1JN1K~bv!%@I&!*s{-)u{rHL#4@_(*#~Aa6hook8&sQ zbpqcAJjmKW_+@LuUSQV$VaM^+-2&e$IM?|B|2~1A7WhvBk3yr#`fCJk6!>g`dw`9d zzS<=4rNBe1{e(AI`?mtK{+k>JWl-ST1m_AgZp^=3;4cdN17H)EuYN4>&w+b9k@H>H-KS$vCz{734gt-oB24+2L9miMe1zv4I|vJ{ZURQv^O+;LQT>1vc@bJ`s4I!1n`> zvbGWah_&qjV2^KtwJQ3LF^wlJRrvM*o<05>z z^}|$P*3;}bzFH`7&9MPzfxzp5jZR-(C~zO}L>m`j8Vg~|^aFETS2>Qab_;yLI|9zN z0^cq0SAdOv^o0ce7Vz;lUc&FR@jeC2@xI_VzIsvMUklFHCkFf%1wIID^!uvhxB!;} zpJ?MH+z>O@TLH}RPH-Gw9VhVc;{#5$z{>@`T;NX${G7ml7P#^Rp%d8H=BwEPHwnBD zc#^fB@b9eO76G&U7dVcudIVm1V!*jr;13G?gup)&*gGjW_b6avgRdqFJWb$Pz>}?= zgcn&qzZ014Jlk=6b*{iolLF3qf!{6gX9Rvm;J*qy_T)g%=>ne%Y;5yYx4@SPe5JtG z0b{ipY+i;ieaQ@4=6YbhmJd3PuRbd9wUYzRJpw-^@Sg=9Q62Cn3)~EBZ1B}N0>4Y( zs|CJI;7<$ud4V4Ro?@?y@a6Wp9tGy>`kv$X>W2bFzEm~eQja6ngFkkO^j)U>0zze1ZoGyWH z5cp#Pe?#D(0GoJGj{(oHHW1!yZTN-YA9Nh_`KK}8S1$vzon_Mle4M~@1zrkl;_?-J z#`_c-FX1gV-g5+hljHd6Vu9Dp2;$l)@COC{vcLy`Of2b zx#ZM<|2}~~EATS{|4!htS;4sz1fDB!r@+?={9#~YKjwJ^{(`{tx#T)~jf9`D>HZa9 zzQ+G@9AEuZ;3wZ1aDF9l`Duatc!8S*?gTdR`sxyacL+?M-<@r3BYc^)?P_4Q?L&^^ ztGfi=b9%tJU*M+%ehJv<_tk3x4+xy7Lm$A}K)BTAfg~{7aHQk->S%$F6`YFtfPcKe zO#-hKc)P&w6Zk=apAq=?z{XBrPy91Z&JN`CCDukyVe>MCAJJ>~P5>t+UGdFx=-Nu&JQ>b2>cCTqtjPU3ryee%hTaudm)E@I?aChw&C$+X(Nme%KDow%zDBzIv~~?-!g) zTLS+31^$A--xv55U=y#eyafR+6_~yTx76B3_&#gf5MZ`#yyN(4qQHX}2AmTGK11O3 z0$(BUZNMg8UwuO02L+}tqb;|#5$5vsMPRn=JC5V4?+N@P!FhO5!2hwp{}A}_Ou(rH zHu3tZLEvVA=|f;EtZjrZw0=7im~C6@ZW%qPG8^HW=vmwT4k@7@EJC)Qecj2oa6ZF zSb>Kv4LBzVJQvvL^wk*x(}$7HvvCpTd5p!t9M^is@zn(aFIpCG&KGzWu+fRR2!ZL# zL91fnPotTRjm_DPc>uJz$Fz#P|0j^nG} z3j7Db`QBLp{}qADSFnCx4HKBYPSbAVCERc0Jq(!Ro$NTinj-L+vjff)ffoq8PT=jp zCN5v?5|}>jvd-E-nD0GZ2h29y?l`{skid5f&NV9o{@nsUA@B>pCN5w7LEyg%Odmek zVC^A1-TLGpFxxZu9OmF&fWRYxne!)shpYC>%+U!r~V?J~O zGv{@IN45r>F#^+9A-Zi`gllbF#{jdQ8prX~G=WE~4mc+ZJRjKT^wlDPmjQ3IaS`UY zmIHHK9gc%%KLnoF7I4-GycO8!^ws48(^m+3J%!E75I$97mAMv}SzzXWS>Ue%o3iX>2=mVaUuH) z=`UnY9dxokXOn(W$Ff}3V{f%w6td?~mAgXv->QH9UHquy{df79+9u9FqeQ+cbiGl_ z3;Cf?yl*vM71C3v9xKHEcgf%C^-e^ZnmW+S5FUd+Y?%|W<9^^|V8g+D4)8(zQU9DU z^QnGjehaYS_-Zw<(shxSANy9Cl=9btV znvY?7+JOzn*M0mEmQVeC=5H1J9l(a;tDAsF;*abh%=}w`S^uq$IKDanJQ{z*C(Qh(ftmlTNvRf3QT#6^b={ekJ{cnSVg= zpLQJF#|NHd`GlGOlHmW=aWDrP=Vwm53}NP%0CRe!9LHBgn)ePV% zmQR@Zvjo4+aeTEDc$(!CX8sDnU*$Ny+6X+u@(DA)U+}j$j<2o?Kqg51#Yx_!pxr`__G|xR~cZcA4xx9<}Vfe6^?^v zBY~SOpD^<`3Vy%i`05(q7Rx8h{ObjOkK_0XUpR611PL?$9>K@=N!&fYM}ad|KVjzY z7yKt32lqID7h67I=D#5LFFKB|{s(xe z^&#*I%O}kII>B#n9Mp%vD=nWe^H&M}YR5r+2)xSj2{V6-;BR#t)Q7<5Sw3Or-z50A zI1cJV;MJB-nECY17hms#j)VFTc#Y)~X8r-ef7)?S9|BW*O!<>A^IsDD-#QNJ!z9n` zqdo*?ehDz!lX4u?hrk=Ge!|R83;uY=L462(zU32U{w%?#ch(FC^&xPV6POlPR!$JCDL(#()%WT8`b&WlZ zPtsUrb~w4OJ_a1K`U#K6AGXYW*crL6o&x4RKVcdhV9R_5JMQQIjU-kNVYc%hPVVb| zU&?Z*4@lz*Y?;G>jojCDbBX0pJYA$+{$eA&rOKZ^Uw z)Q_V1AZ(dm0UJ5qiJLFaGDJpZUlly8du<7f18N%Q9rM?aS`UYmO44!9RQwe zIfUD+o{dh9atd5yIfS{qf5*vv^><+IuM%d?K_|yEDyV0sSv`d3+PF?|a@YergY5x6 zn(c9NU;PI#_eBXa=SC;@)&0QS|0K+H%cq>&SN{dfeNMvjY+OHaa$k)@9av}WACrA4N++aC`xm@%)Icx@|x{1ml;hEN+PdPcpmB3AwL%7aze&giu zb1LX75)PH=L(V*Va&oj^z}(*>Tx<3G+{t}aiOH|!Ru5s;Gt$X@bqeqb%OO18>UpP=`|3Pk z?#mJ8>uPgyJmU(?{WrqQ+2-WFx*3@JY=oKfJ}39pr-0X3dk8b9~qgxTir zIJvL>2)xd62y;FEs*~ec2uxybupGi%M~!fDU!4q0Z5!n=!V|53YMk6xX908Hi7?x| z(#i46ByhLYLzp?6o!nRN2Ht2ngqgF~$?@C{aIfVMX3i&^9Pb$cb6;9!0y)-9fSmh0gjr7@$9NWU?(-04P9R5L1@a-*X2Q$~T{5DpNBAW0y+A+kaM4hFmnPq#-5OKpNBAW0=bzF=RVKVfUBC%9Q6<6rf-A#M{oi;>L18SFWEzw^#pR%Kag{uhcI&jxw*%| zeV#3XL)ges{{VBJhcN32q1gqah_QU5@`5r3qIFmnRAxi`dpo|goNu#uzw z0q(~i=^@N|0y*j*$hpr$m^pzQ^$*6~TdW?!%n9VO&x1b5fWj9SXd9;YG_kj1M^cTS zGrpx7l0o>x7gq2`5*l$+FDj5wzn%K!fn*AfW`!hEaa8Xl04hy8Y^5%)X*i;|N?lyj zaYS(ik{LLnxB>}{m`({vswbPVR=}yoWsv5S(_D?q7y?OIAi-tOQ$j+5%bIjIY$khz1U4@XOKjd473hJ@qredo*t{Stfz4-yB-3Ft`7k(ZI&AI=ORUX@ zySS#?ydfm8nc@->*i7jqB(S+VEP>6Jg(a|=^2X>OE}Nf^aFQ7|KaU9{u$j&}GLTrC z#|9E>vyi}Myn=Hg|?NGp(Nm2R2_4 z=D_Cng(a~0_OJvte<&=0%^wR(VDl4U32gpGSOS~B9g)&eC7Gggf;?-g`e+tsn)-N_WV-r9mSl!b)1!lHubHXSR7lVew&E-) zsn)qyN@}zZ#|3)O5YEO~QZhxSvXo5KPq9hKG~Ie0BlJwyo|lptdM->#X6n05LV|`6 zg#|6BOVcUUdiGgLYV?&#Nv&={#*4G2=rv%aWU9W>34$|C*TzyZU3>Ld!I`1GAtf{Q zER>L-A*6a$N~(2RASE@r>_|ziw&xu|Tv%MB0eYlls%p-XOw;wDYlWapdox$_$)MpbT?IUYIF{l665EIfz8vV=$2Yars`FArDU4E3MrYc{Uaqa)VYXV zN@nV`I4+0_4I$-BDXG?;my#M?Ye|W*`FNqn*eoSeb(%_vu~|x{>(z^;#Mmq)#?L~6 zhHwLHmXd0HT_*(g%&5`VB_*}GXC)<5bl*lwrmFLxSxTnqeu9)t*Zl-3G4;lYBKDa& zb|FDSxEPwHq*~`FDXGCX@WPy0eO)I7nrBYYnx(|}SxTnq6qFKE1}6zUrVL7nDT9He z2JImA$E3vg`DCZ3X0mAqCku(G>!f6g_Pmssc2G*D=_{=kdZz0um692{oJz?|-AfS? zw1d>|tqJsCKuG;wDXGzVq@-5&52a*^?%PPoRNa%25@U0%h|Ab4CB|kcF*XYc+Cl2Y zO$qeWRHG*tmKZ-z6&#Z{rU}Uut!KKBOx2PZLSk&5DJ0Xi$4(KF8G4*6B{TInS4hwf zlFg?EXJJ4{HHnlMn`a4*vH6`sGDWvLQetdAO>m6OrwfV6&vim#%3!^an7VFuAVE7w zHqQ|fW3!YPn;V$ZxJ1v3(A{imJty^dZ0Uy%+G6;Ndm4szliJ(*+pHvBh_j}zk54Ko zz@cy&&C`~|U)*c5h$O*g@3Ui`ggEoCCw6#SX%A_BDDI8Go~#dV8|@)(If9eMK9@s% zOxkeUtssYb?zG{y8#v>z&(-q)5wH!yU)(zdd-6hfJ75nf&Eg)q@_9JFvK%V&ac>Fs zxpDp7a;RS$_oye7%Q5$f%&b`4quH5Uj(vX_^9iKqh`gLdHa`s4oWt^RF0h9r!7F^qfU?Oe{)Rz#^8_sHA1 zoLjAkX7S?Q^VsKJ`{yl(?#ai!JMwa#vz)Z%Q0~t4&tEO)XwBJ*y`8NE;%z8Z7}&<) zFYax}K9}CTULovfOPsRF@aZ^Sdnv(pT{K)gLITeDqHy``lYyYg}%+j3vb=21_=bf6fF0YTtJE5XremQ(3Cxz|q5deTPo zbwPdZ;Z7Z}(bGo#W)%{5i{^@q3}`deU+RI}Y_2!rPB6hh`57 z>3P|5=sud^(D)&|y=FNyLuEL*b!Hh2g0T&A92#kax3uNZy-}lw#$e&?RLh}RnnE@& zv>e}YXmk|b+AW9f9UDE{!UP;$W;ry2S17LcS`N)08V>b+!`t1KLw73-hsG-5?emsH z^IC>O{mAh4P0OJV>nv*dc>Q98X-&hXazc3u?!GyOGnvlRo^TvjAz7dH1 zD9fRHWQKEx2sN9GalE*rt=&v$osvz`(_BI- zsZiI{)7QUbQ{TppZl}OX7kBh^^s~}Hw&}u-Ea8%k9UblSLfrY?{SBRcZELzZ=Ja&; z_x5y&QxG<{yI|0g{^rW;GC|G zwq9XsL&xUg1gW9{GmA@m*01l9?&Q;hz~XUqNymnx@9N5PDty@8u~xbXC&7nn^U3Sm z+k2OUk`-hUhSOSJ6!fp_T%X@1CM-uGU$O}ft8Sd%xG3LgfjrD-T@4HB^PMJwO%4=> ziZGj}@&zKz>NmG_O0T;U5f-*aqz9#E{n`tJO6j%SP^mPtNv4+!S<(?IwB(h>u1$R# zvZ7hs@vcoBef{$n7LsRY6tc~pl(!V*W(+zbf6i#yv?f2@283NkdNLRFn#9X87xKoo zOB>AWQ!eSMuh-PSq62J(Hb0~YkO zcZ4s{B_DF=hBg#NnU%;SIz{M39?FuyiY!T{>Fi9;MIF71)~yp~I%&5Ma`c(DwHI{s z&*|CJ-5)NHxNhe3Y0Ep-_H_64pE9Yhzqhj+CA+<2&8GFOU7g*q(%{bSbv=yR)~xC6 z*zAsa+q&0x^eNM9^@pqRkdWilR8ekl3fE&HzUGm;MD`*AiC7nxDw0c?sdP=A&pyYR zsOxnOL%y?_M{3IQpbVmjb#Y@F6B(}Ysab}3jpu2)`wvm&HJB!0dE5N--sv&+=lj35ti z@{(bQUE~wGQVz|oXGkmC6l%Rg0k}SD4M`?!Hc_zO5P&OQD+)$dh0YhiSwWNnX8|?W zx}9%rZSCmo?dff8RpZxe>g;Nt)YgxhaLuNE)N8f^Tt^LtD&O4EOKroXo;By6oW@o? zeR}QWn(31#Pfe#MlOVKDr)y@`8gY7c`D2)s`0{C==-h>|su^AE@NUyXgNwxg;dtP` z=$T3(1f($(O@PQd+RRAjPS&cl4U~7ci}CB2FYa_RKi}^TA*306-oB2>WwK|5ovj&U z1K55#l;c5~i~hBpUA0vGldcPnt_z?d@gKl{$?B)`X`}gHE8@4^wfsM^uf}ZPC_6*o z_>eQ7X0&`Tps2~}x0C;lUw<43OXn+Z9DWn^eSIAlV#L&| zQiqk74vOuF#V(JwqS}sqFC0h z?K`=Fx)8YT^wI@OYHKFXA;Z)2YSVL0o^!$p={cw+)^~KLmvwh;NpG&HnKW%u^`w@i zOAxT};@-~n8~W1|*B+Oyo;h>cNi~zJXQY>QY-#ID&qpt%7p+8hKjF1Ky&HRa+xk1& zm6zDu)7h@#YkDvW^M=q!TA%wM=v^Ty9_Tug!q^XKZ{W0%uWOJ>R3Wetm9R&39L<%`J3rS*%+ znq@1@@ACS^WYt+Xq+k5h;OA`nyRv?9Ee_AYA^onZUpxgr=i-ol&#PZN6+f*wq~F!` zi>KkI4Tto*rhf5s{H(H&Rv=M4AXv{2Ys$WTxMUb>Moz*aZxhkQxwU(Q

=&ne@o{Y zd!!2*)j8gGkOf-vb0R8-L20j!zCxMeZ7-$T3s<>s;_COcd;qVc;gA+DisQBS(St^) zR5DeXN~OwD<*AC)nAEAM(^GR&^UO;~+E3V#t17p@U)AIHJ@|{Oi?H`RHES^T_|==I zB6pdNCxJ!4xT`{ ze5a>k!|e{gFkJDb`BY2++>j1liR?`P(w=3U(s7s7h-Q3C0~6Dj)O^B z{=C3nM3R}t&dU%UY#f}SwRw2msqZ@uzKtO8Pk~wIV=%zzG3zC;&WVW8-o?sUYnJ(B z72CfPn9n6_XKFLMoSdHK3ix!rYy-8>e6DD%^_md5aq+vAvOh&$j`|5fvWzyeJnot6 z)&jAkCs=4hP5_5`Fu6SLbD6v7)a&A&7M*D}?$=N*h6bQoZfYq#Xp^<2>jD8iH^m#_2i}0+!esms zf5UsnI)q+pG&~ zzXktC4MxbNUHbD2g8vlo6nao7Ym@vZMOYnh47>N+qHSu!AiduFXk#N>hYB29Nj##) zR2RRsI*$KCLk;h9NMo;b#q9dUt&5f|%`8LrTFJv26_ba!tuGJJft82jz z=iIw@Kiad~-nNvswA%s|%V)ZuZNVSiFM4aX?aG!~1#(%zLbYXyZAmG$DWrZtVkD>q zBZ>IKZ7NFqp_ups6D3h80b__JCH^K+3Ghq*NPXU!cjlcrbLMWvEVt?2_ssLo$1`)z zoadZ--Z?|6)88Cci~P+kD)%?H;>rIuQ}MB*4<9><8!W0quQSSigUMgo)ZBIF{>_`4 zW4orNr~8^?d+*peg_btFW+ptEd+umX#s!UxkBv<115Y8w1x$>MO!ZMWsA{|I5e=c* zuy!2fm7>ee-RM2a)`yF>A~-fVs!JYJl?X$F#&mKKk3loq0nD~II zL=X`lFvJVkP_YFdz9?+LkPshGSpUvIw-qG2#)%#0OQi0BtqZqT7Y|(y-dtg^5RgsAbd~ z;Sof{hYaxowyoF#5MLIyV4DyhQdtCoxZau2;Sq)=jhkaUg!*`5!>9`J6+yKnE=)Y~ zW8yf*BZ!C(8{!3wCpT#Uh_4J=&?m%)RThDkI7U3em^hB{0>m>H_BSEEDy%kkVd9Y= z6UQ-LfOrCvT0m}1Sj#{Yxu^Gxji@X_z)T+|7}5x1W;loo5YJxNUxnG)u+G?pnMHog z3=N2&iT!)0Keu~KpRWoaPhZjm(C!VJFvPS+RTd$ZHU>1pm^KdK0yNy59`Cz-axeC$ zJ-cudPi+V*EZ{_#9C3y&IBp3FLd&lS3);#!b`Mk0#+JBOQNeLrP!KA*E-0vfGvnBa zOhubo;$B4s$G)H-RCGgFP(S0?Elfo>wZy%O3XTIoL8$1Ku%JQU{r(tjZi#yp6�x zf>2R^SP%_1RpiEKuqEzQRB)u7K?*`e!(lG2d! z9pcou=Y;trkmDXi=d3`FJ1i9B=tEY{o`X}RBF8-xGh9KBdmx$=3UY_>83|w1UEs`m zIpx5lV=rbcYTPS=uLR;9s&NN~avZ!_H+v3_w}^2M1@D3y_dwaT5X4ULDINl<~JrukPTHFKCs8EbstRS_)o3(PvfqBPX%v+SWR|4@4rMLq_ zEe_r+nmq@{Ta>tmTHYA%I4koOE$%Y%yv8yayje!49GG|P#k@s`yApWn;wnImRkP=S z%z+N~An+;(aSvo(qQo5*>TK|0ot$!DUa=SR5*hB5P@=;f8VYf+X3^|97}g@gJ;<`g zXqM)qy;y{}%UDp_PKl=+h;=B%oo7mmJBO4QPdRvXu^M-tDLHN(l6pMl;MK)~+%bjORmpg})Fi$ynb+Iyco+)YW98%gm<>1xD z;@o+r)VXy?%JY|~y5Nql=yL&KX}%)Q1!KOV&MlM@=LwwovNjhd<}1=%AmSS;bBm>fx!{hk z=yCyJ6=bAXE+8z;SLC>0%vaR7 zg;HWXfiqv$;^KtzLn$s0@eP%@#Zp3CaK~44xPY(zbDFH6H<16}GKvE|(0{1FnjcpxM65HY_ zg`L2?idbM<$CSRdcuHO;aIYd(*VZv5t}UL@)(PCJh^4i4Oet%|lfpWIdlj*+wvI_z z4F^wEcdv$ct>MuozUi&!+ve?)JIwF1n4swvB(9{5a4v@%iQKFSC+&UnLT)D+tEGkW z?axW8;S0GLZm3#mZp@0NQWR$a!jc|00w zd8r2vt}bK6JRS{oMX3i5u`XlfJRS{oWvK@bv@T=SJRS|Ty3~V*TbHqB9*+iAdD6d5 zl@GcuW9>X14YjV+!~c1@cOH+1T5o=DlXhqekE>;+04}e}0SKgW0H^kH0BdBF1H*Wl zzF4_Y7bA$SC`U$BM}%Mo&un=w;#%i!9iD6Op z2qV31ZVxOi#mu#Iy%aOooy$rwbB(sV6f@T|D@rk={jZ2Id7@%v1Y%&#-H$6%P(R+1 zRx;?6Ye20|L4$a|Ur8==t#(xk>c<=Z61fJ{x)d~scm0**GWSu|ry#87$iJ`3!H3?U zT)3!DLD21G5MT49Alx8JK?ACmg76$_1o=;+OsbBScmwauF7}Jbk8_89NTsVK-cXAY zIL;e7|KgT-L*)q^=M0^{yCvRGJta6jWq|Xi&cCE3-ay1@%%AdG{`Ho4LoG|-mjCjW zctfp7;FkXtE%An0S>c z)-ud(V=Zeo*0SbeEp>GgYbp6mAZcf=gD-O(e3|Ru%UlOv<~sN?*TI)L1z+YS_%b)a zm$?qU%uVoRo>A~+u7fXg6MUKL;LDtYFY(R6m#{ea5|$0VglU2=Vd&sXeCyy#d?WZ0 ze_ik;Y#n@=o8ZelGr^a6rh_kY4!+Dy@MX@ymwBdxFLMsQ%uVoR&cT-4wu~aRAP)0ZyaUrFHp?81P_3a@UjNtx3JQe}GutRZXfrnyF551kM{nY3B$T9t0Ko_>JFD`Ij|L5cGYjZwO?H`UmJ9c(_SNoyrzOk(G{KVO|S+XY1 zj`w8O@3^FXu>R@M-fJG2IDM}3^oh}%&)q$7x>~ty-<_9e`_(sIe{-(4S{Z-x+}*eB z`~0Q3_7`9K$%R*Y*F5s|58E%h?9rP|iF3UhE~yg}-RGa0*gw~9%f<`$PK-Y(rGNMT zD1CcL>Dv>fPn_+ZRh7}+)w31+T{+u^zsq&X(%FgE)ur>_{9tD8G+LaUTk_t_+&5uW z=9auW^WJP$nd_Z+=F-#WZ=P$vZQnRpZFqFFU#Z&1?Uq%1rk1x$ofbD|647 zzM}d%b$yF;efdYOkNVNn`08(|?2R~X%%Trj%S9hB54#T?XL`|x<;M>#KQ&@k4A3~K z1jY{kFBr|2obQohzG8jjcxt?=jv_~vsjEJgg(ke%SX`qM(^^*T>#o%f)Vd~~tJUuR z#SN7!m({ZC+bb1nmGgO9g-)yLB~E8D-|5Cmsnbj3^yymnjpOw1mhoDxdU#W1$#w74 zvdYq)V!am=-jyz_jPX6=owZ@bi^W)vp;FTeS?EPC(6!Nm8Evv)MokvXXy1f&FxF!E zfevk;oX*Q#LZi!fOs}-D2zOYpzy`N#u~~N`f8uew?nbx2?goX4>yhzRU!XmQKD1ZT z$9~h^MjwltEnLrP!>r3e3qjGk9JGq@C)mCfd)_D6{-bBV;n{zIc(*=pd-h$BmNxxf z&pw7j%ch_3>@NIFWYc>*`vPQ-P5+Z;uLK#J{)}h;$g?ka_C?Qr4bOC$6|b`?vcC^L z_)J}ZZOeSe`P9`vJo_!&pte5mdUiW5^KANB&mQ*dDbKzKwrN9M(Iw(K-Gpq4>~C>< z?)UspIiI?E!m}U1RgA6olxIKd*)Mwb?>zf&p8a>&rVV(XJnZ${9WVH7uIBcTZQfC@rk?ivf9ibd>gS&Q zOV8(pVQJ5=J^L-s{=l>8HDRXSx*`RP-4CB^itIz&C!MhES~MG+PhD;F>>LN6?T70; zd%I`fH$u@JBn)0$e66&*Y7OJQ3sWOw2}K6?Eh%ViZ3EElq^kEGYt2BcdqWLqCeH~Y-hz-V9Hgum8@ zY?EGBn9|(1kZpY=-REN0BicB&QNO{E*5je|cA%(`g6T-F>m(_dDD+$XI-C!t1??j# zI54#jy%EBcgF{dIND2-jy$%SyEyVb2MGEz+q|jPJw1$wRAS6z&H{_*Yrd|^IpwYcy z3K~sJyj*BBwbDz$W)&&)1`pGoJ~W!zrAccIx(+6n|wN zI?I2&>pt;*je7l$RTCXZtY&u0_fYx`uarW2Q_AN-&SKVmqVbGB-{2(L&#GB@d+2DV z5A`hGW{G2PsowVgyu=$d?L+Gc?e<}9+ZAshQc%tt5l#tz;M5*`SF`Q-YmN?1)?a_+ z4Oxfk79ZC3`sPuhwTV)?P(htF^XTul1_ewzk){);_G}|NCZUcW39EB&XD1FaHjl zeEa+6H{U$=+u7Nj-PyxW2u16gP8u>Z=nb64y z$k;#eGm46tvAW0myJs^q)ZhQKF*EQnGmqKW|F8R4W+wRghP}&t$6qIYF9(^Aet%o- z{8BEcWXb-lp_^F0zvj1@)z|O2A22J4pMUvkHkiM_NB6UTKCQI(a2fNd4cYnx;3tf*iaEVMQ(4Y#+48p9mNqM_FIHQ}hLQ#iHRbLyI7 zGG(l=IaUKxt&O^=+T0wQR^Jj1Max@b;b^p@Emj>1#X8)atHNs|v2a!R+>UU2OwBSH z4%x*zr8(AAUTkOC(I#oj>&_0>i;^@nw}jP%5CW6iD2F*H?2i>SC- z$&R*$P%K{Nx;wy~nh71)j8D3!cqZAVKe)*NZ&UQ}FAR2%DP4J%GoTvWZZ zwlN$#Ez%m!DQyY0Hs-v|fQhyFNiVPUH6b-|7+QX!*4zCTh zHASLf5#zG69kyMjc-!?Yq2{%km8Au;C2OR^vtmb8(9jUYArWp@bVW^}*4A)~qABc% zw#O8FN;K4_K;C{OMFo}dty+RTA#?ADhO3(!TSG03E8})R$;l<$KzVChN31f^5`r78 zXSTK|vbHT04Ht2LVZ6a>6}J|Ob)j>@rP0XRipr&u(iT}4juuDOwX#K(<;$sjCwGKe zn%6YfyL+C;ph+u34br^Ljn_CwcV)9{vH+EeH1bxkQx-Qzamd=fWotcoSB9g_kp@vN z{*g{rnxxh_q9i&(^($W%+7LoUq=M>e-9>FO!SHgg!klsw(guNFxrutd z8?Z-FQ1mKAf2iD*C%3lBfS=d4KE|yO5L1OOy+FWHiXxNI$C07q1Fb}RE-c_ zqoPs#!%g41wmCkn$WBYT5_>Qbt)YUbF=*h%P|NbRaFn}{W2~~Mwxcx~ZftHxcje^A z%Ar>}+?vSA9pMfblxq0(T2zJO#EE$=#A(Y-iheA+wkA>wnNzzc94qWtgEJYo;)$y4 zP@~FQ+hd_tbkmeOb;RD>L-u)yjvf*baY3l0A@}(iFHuqZ*$buEPlG}kANt?9Fj)h(e; z^4PG<28U?4xig$SCvgd7v{Qj)kyfn^x`B9xs0oVXDXZN!PR{WOZAw46I|pG+S7|h~ zHe9{FwO-cDPVHo%72HW$6_*rUWEI~d)y*61hJsG)B}FH@mVS0p+-}tyw68+dB-+0+ zKcy+dYm3%2^4_Uh^tJ75snDUki>h&QbbGC8oX_0IiasOJH?C-{k3^#-(P$(p&yGsU z8XCND4{~ynxJC|s7sqx}C|VGWhSoFEBov_oV2tJ5|*D5CBPA0@dQ_Er!(z|WRC=7Kp z@KS(%3Z0`{LXE7txYQmRa8KdGJXI@B`62Yd3>{3Z?bA7VI9%JgN_8lqu}S=}@sN~c zC>4{OPC8%~<&m}pd5LqnvH*qaok9^t~AQeng=YF4NdH>;Z!j`u{l#Wf#N#JBqT z_M%t|&VwzqYXv|t3OZ!J=c&2GnFvp%+}rl7*BS>9eRhw-ir z46v))!r=zd?@K+k0eP~WoE%=oA_K=9idI>n5&P>sZ}^j)ihy@+7xMN;Cf^Rz3fosVMBcGvFJM58*$`wrfRtW`?NF6)pX*+Da7Ro zi?l;d!IciqL(y}T61b&fE2<02BJDAG5m&yfh%Wd@ThiLl7HMwf=edH;P;-k-ty~u^ zrQu2mAJ32$JEgd}y*`2=Hm>P}!cLCbw6r8Niu1VS(qUd5=7`E-X8@agpdyP%tVM!F z^%94uR8*FoT1ms=<*j5ABNe+5MeWKu>Xba3XqceUB_&zbvDPkeyR>Oz>=~sb%WD=@ zW8{L)Nj8~QUpnp!;6|`Xr7UgfXm28bbi9+rCYsB(?WqLxHU&i#&1)0MguP8!$TCuM zsp^_YVMY-&!JNiZYapcgQqAviI0@vz;$8! z_^?w_r^3(7ZaO;(*|a!^v~%>^?RIr+ zWjIQQ5}k7@n(HKDs|pLMsIR1p>ZLdbh{1)e#SIuuSubu<;ToHtg*g!x`BgV*WRuzk zmUqNJb#1UvL;Z|M-Pz8q_w2cIb7$quot2#v461kA?R)Xrb7tqv<2T(`54o_UqSP=9 z+(C4urHm0#Eb}}E58$ls{E_jRg6`bgo?Yw|9Z9|F zL0``n-Z||;*<3rDNKIm&aX%6(?R`fHV|2Fi;K!3lYpA7x|&}Tt^uc99d{k_nS ziWK%xo9xQi$J=99#;d$Nc4fTD+hbS8yP=})Lsqw$g{gbC_W0Sho~)>{-KlJMDcch| zsdj#}c+vFY>1x}(r_``y$G+}O+e&u~j}%SMiafQlDCJQ48yHW2hmL`Ev{SzSmF4@b zEZ>K+e7_0(7InKvsoNo;((X-FzSYK!W`x~X)V+Iq$u)bniq?D^Ey!QQzB?Q5!y*dG-c{sv>g z%-+v?D>72U!QOdV{4ytg8IPZ@#QRn*@)f5QXOS#TE6qagern?izj1ZX?RSr7?5^>j z_ul>dT`%m)5-~k{OF3g%0)~j`**l?g3(C#dOxDCAY%L38tAo|CR{U)TiUP-2GyX<_ z+Q4bYc0J2sv-rPtEW~5H@oNx2kL9wttcx|sv@J*<;x=nx=N#4ueFM@qvre8*3%2T@ z)6*v6gpjhH&A^Yb)A38e4}XvNc6!dwe|CIT5Fnj2bcCB{(S~8%n?`r;t4gYuSFETh zU%sq1JEyR`hB3>yFD_;d#pGMY{S4J`%#X}ie1E8FUsn(+$GpX@hT9`89ds$geC7jo zG1!@I+RNYHnYR7=FWultYpw>tFwF1r0xVr#TvA(IzHCuNNo~op;*w&N&3w#_DlRWA zEvYJ5R#T4A^CruD+*7#Br~mUX|MtDV_GG{dCvJW6lcUdk!Y&BgguG?D{pPH1cV4pS zzU`j0#w8%2aM?zHs)$LA+GQ)27M4_HQ@L_|l)9HnuW zedW@O~P zVBB$Den+b(MF3|NC&i{s-7QnLFZ+u(#X7QG8)K%Q9qDrK8PmHV`&*R{dAYbMiN?_8 zIAR>DHIKhI|BYq0)_a*wIb@PlHpNYH{hu!PO+W4aQ@lxMQ@!b^(RivcR;g{79mAYT^&JLZX=>BTeCylhWxWU^G%d++{AVdZnb+ui0(wx%V5TdrmbJIXE2Wo!3# zW_NF$?PWGZI_NHVN{V`bo_N(eJ-q@#80k zq4r^(8YGoclEW|W{MffD{T0$XbYIZ6qVD4)5B+9zcCxcIXEsIFhG%xvwRW_Jqcda8 zGo#_QNc+tCoLRGGt;0l<#A|Zq<<9MD0OIp=wQc7#&TNR{PC~S$xo)N%>uP9pOy@(K z@dhb}`ug^n#o@Y+#@dpC!g5wq9;{hfotrbOh)Nz@lp8FXSu}lmum~5fjp5ediq__? zU}sLwj5#y1XH?WwBcg3Rrfi#H!D;nJ2eaqTpL1N!tn7Kgns8UBJxDVIQCya^#%LQi zLfayk<_I@1!`Fh=tF6V{b|hL`%Z3@bE->tUW!T36!)f9GHa0c*p$B85`_YPY`fYA6 z#Psk=OkLt^Dl2Ok_ZYV4>zqMyK639S_Ml;GG>pnRl!)0oJjL96fk$CY;01m3K)V5* zi4VGC?=k5HxX$N8NNQTDs9}`Sp10M5xYz61ImQNkryIr@xHD@Hy6uscOwXdvLN|8Rveel zr?IYoA^xPc;tyk+540z(My3ayCwTa~rFV%59V)^f zTr6*G2zN32(u(>yq32I6D(dqR_lg_#vsd(=jK)c=#UI9ge4zdC3}kxH`QcAoKlDCj zN=-~PHjEjD^hGaWP~EY{FgkU2#2LD+txn##vG48}=H?jYgWJlQ`O~q?zOIHoO8Sb3 zSD(nIH^OXLvpCY!LEr}HDr;JbI^`U$ozkgyRbu&h`gG_RyAZz=+`y!U zH(2j561Z5QV6Z`I@&>vD!&q44Vq626f_t>02ty7?5yW7e7r=r?qIC@4J-%UNia^!!6Ld#TtLWiX|?AafebC>p6yEo%^Acw(w=kdiBVi$E>uBm7<7md5T#2r4{jy zRK#1%vBpAQznRea)*fSyI?_t})Eqrxmu2NzY30*z zv5aFy6>juYVc3^eh5JnGqy^jFdZ)5@((iv~8HbAE{TDCZYxsNMIsoVBJ1`v#zg>*U z#NHGf(1tN#XeJBz1F3;PAT2N?kRF&ASP)nkC<-jX6qFOF%N%{d4Xj}F##2XMP_SP% z=rU8-*sykgZO~X>+Azt;6ySffE~_0IUFKQ)X@kzqq8y#(X|RDC_vJwhP(~WQz=(09 z(+>?y4P2g&^Nw$ZVT|?#=BFQ@z99XCLlz#=8bDIe&GEi~l4PVY%7{-!TAtJ@54Hv_ z%@2Gv-`bL&zCC{!dgDCDhPCA)gN-yU%Rgj)Y^PJ9xb5`5Z2JNujjd$ef1q{m!)RLn2;$Qa!z5InjpQ+VEM2BH?w4Xm1SW{icj z3h=_tTFl2pSzz3d)S>1WDC=|Pb%pAhnL&3VQVhQw{{qOMDpJhfW0dR$6N5#{fecX~ zd<3L@E+I^_Hg+1*^zqw|Ajt*=!Xd~ijs$MPc8h|^ecbX|{PMu9pT*8cyjy;YZ3Y&%tjV6mE(dnY zXR&VJAbu1m{(8vC90|M=+cfh^f#UCkbjxe8dw~ln5`p3$f?Ujzz>i~liGrWOc8!9c z$My;Zzl?2qsDc97dmYlPub$!KrME2d8Oxh=$WOJXFKOG(4Pb_t?+S z@CXf$)bJ<`kJfOehR3j-p8UpYc$|jEYxociPhj8j*gKRx=D`6ieximC({PrCCuumy ze&De`S&KiMz2b>KLc>!uJXOO-YWOJjj>q0K4Ii!HV>CQn!^g5eNPDZ{#-nh&q=>GU z_hX~be~pls`i)WOUnWURUQcmHOH8MgQ8-@cM3)I2&b-V*mrs3NCJtEY;|OO;OnnMr zI`$}j8cB3+(@Emi9GN9Men{d`|4qCUsn_k(O%mc0PtBJGk%Z~AOX;aECCu{y7S+c& z1mPn5d`C)&PJm++j7ucs63-}5nS3WPJQD_q$3xZ{*jOm_`BI+?J;lS`xl*169$`Ah zN#emCE>o$pcKQODK2N4cIe2==m6Q&W+krfl(nB^$xlYPUrMyAP2c&#h%Euv{{0e1$ zIH~aRqP{#o$Wtjl$TOv!Na=y6OF2u**-{=ayYl=X&!BuD zS4-JU>4CeXJYUL-rQ8DP*e#ZJ=SsWSPuwnKE!l&tm-1#x5Bx1DsXYk4Amxvwd=1jE zUnr(%@)YI`tcF6C^&Qy{p&s?crAoa_neznv$Nc{y;zfJ15Oa1*)zgOzNFZFLq z{qLmy4^r>P!AJRyCrRx?66KjM^-H9FxzvZGzFq3qNqx7}-y!w8rT%%Te^ct;mU`+8 zDBn>ek?&ZN$oFWeUm*1hrGB;4N2R_~>aUghJEi_^seexDeq+8T#fkJUa_{B;yY?`Hq(u{S1%C0G7w2AK>@|iE*5A ze4@lSo?w>wFnAgv?Qx7bWR78vV_ffW40{~IILENZakj*YJ=>0*-cD!pad`9% zR!XZ;zZtP`S4{jpUccJoaa?O(-FY}6Dkw@R zeviC{O8%@yhY=*cH729D7z#s&fD%YYRW0ox=70mJn0oe5h!cnLc(oaELy_FvYA|k z^etE6c#f-byocv3-eR7y25$jT?PF11`}QWe)mK*&ucv;Ae$-DyhI2f%L;K?a*w46NGQ1@N>@l5qrStgrIcU>xu$MaW>= zqj3>!BbtXG&fDLW+azrLrP#L9kpAc3eba6vQpj)(q{_Q+2*!Gb4c;CUr7?oKMdOcQ6WbD6n67b#lsqJzC4g~UDJ79Rm zgU;KOB(En)ULY&Ed@K6k(J`aeV;gvMtm;AMJp~>egL=?;hfZRQ`UE}bysv<_UMB(T zyw8*5tqUfX?=Qi-3i;^a`%tLu(ssDGw$phpYrLO<7t~3>I`6MZ@(!7toW1!;@=oo8 z_cqFCDCJ%c-jNEnH{ZsF%DV+T{ErK7L!ST6t8r~p3Ejz3k1m!C2QN+G?L*y`S1|H-zgd| z6W0#op(mc*7ZC46jd!fVL-srnkM4V@`4)pW4|=j^pO%Q%1s?E)*yLd&cxpOQ67Mq2 z-WKpkPxh#u6cX{aDZG(_mXLRy!ow+theY;vD!kGC@OCS_Ooey7R*(C^v)ehXAKnkZ z%SSxb7pH6G;z%jykh=)@)4~ckP3U6pXybr)zg?O@uQ#%id?B!2~{~?xm!#PXr zk3Cv_cY^l;9G7@xhXTp(YP>BV(0(Nz%}h~9#Jf)6jT5wlyxj_q+M7ZmdygtSy6;IL z5$^{I52tJ%i1&h4kJl9*4$(e&A1J&j{qX*x@a+C5QN96rPXKhMA56p>ukdg?fd}Hf zrPX5^c%&zL(>P0Doi|J2!DV?!WN)6rgNyaa%U5`Coj!SG3XkrgP@sJ2-aPsxr+=vg z&)#30B>&Jod+HB^5}ys;NoofRJxsBo8gF+t{4)VB)V{vGKGx!_XE4xO208O{0{fj)Zvy-M zRXV67(SG~WOLQ#T@08LZBU7kvdAeoc?@DrZ-*0)kY>)kc-tu&l4fK|$%XHt`q=QqI zTz$*arSg)y{1f24l5Y&s^KkaDT92aP>S1tR->mT{k!5g7Bhv>}5J^S<`^iBvw*&oB+(1fOZLQU_6dK;x&%>kToFN@HXn{_y!k_>i;J7bbUej21%kkbR9vDj1@?IwbY*?_4J}N@z0a`3#I-BslP|+@0a>#r2Z#T z|1+uolho5aDatpUB=S9iB<%C~ROshR{b^F)LK6BmsoyO1JEWe^_rlJ7QvW@vf0iWl z$hNP5d69Ew=QVV$%~@jKZZ5SY z{m7>&40JD7umtaC*dKbJ>nwHu48ut!UscEiL5;T*$JgO9P8B+@wGSSh($s9O0?)qI zRPE`!o#4^&tB2#EQ0+YqUb9XDF2N5~Y_p@L!mlwLjSHtkqc+zn@ODC%f!`4PDA2VQ zo&T^eoU!s>z{8>B2{;7!yC|wY1&OFXB3mdA55(JypURsE-X>Ixcy@V+cP)O%%E|X8 z^mB>E=y!rg_JjCQco@8s#isL@+U-94R9-4F`HsU78^o&*wL0VTAc8YS&rQ7E*zCF4 z*>i{(9C(cWAr%6_9;44Njx%Vzv6QRWCR%T7&+fvE)DX~4+A_5@#sZ%gXBF-)%PRAy zVwI`0oK>QjS(;VhFU=UyEY^1_yQHW4*%J)2EVV4lFiTTK>>t+9nonLEUyHLbuGu)c z)Sur=YfP1P8{2xWDcgE+@1Eo8dwWjQEq<85;!|-J59JmMdS^+SJw3i{WO0{&^2%LV zWm|W3_r#U;1CM39ej}U9w)T8~&lb6g)dhNae$P`;d(zrltcqGG&9v9z%I9l#J+-oD zg4pWmUbt;))!$ar>TPZsKVP|Rwp@LzXM&MgDAr=z+A{%e>ge+sr5lBnze=;7TDin{ zYGnnFv)6uW;b>8JYL%~fLY2RXO0kyfGOo%m+_QUChQEWVXNv>n-HUIo*xq~7(jAMtdv98X zzbREI%}=dd?(;>KbuZsh2JN%GCv&-QTjh?W-32?Abr+O4XlU9HkD?ihf4h^p`ckRTm2Oti}v5NXLo5v z%Id0UwrhIl~ zd=etB82Wj|`Ag8I%q-3-%__@UoF#lncx1YBgapmX3|~_vKbnU++EdV~sm;OOVUDJ+ zyfPv)ds%*2)(9z4pHYiAnvZ4ti@XN<<6D!5)gekN)w)X5T z!*)P!FUIyzxm|htUDL(B+_R_n`Jxw2>$Uf3&z>u=*M@vvetzlhV(hgttfc4mAU)20 z2%5{Vzn1a+^{k^Um;3Acj%JzSGsP$q`OFB%XP}WDX8R14k$64B%d*P1up2Y5k5WUy z-nSi#W!Q5W+h|?N5k~3O;#4YKdAAkvp$943?c;l#a=mLh`RblMv`0n#c>WVMBloTS z)G@>9CDl6ODLB{{c?q8!>1e*FI^u~(na5z)5o3LslUm2q9j(0|&u}zfR2@4Vi-TRq zZ#p@tb=>7>?K#bS5A2dD%{08(!ku zoD!FEe7l2}`3tiuw~C&+d`Efr6tvbfQAYpnWy4!aw_>bkxVo~fbk6I+*|KzN&vaW) zXS5!F*;a9mo4m3otGt_fO8@8TxQJTx1t;gld@QjzBegNuyU)><;4GUKGOK8>z36C5 zyHi5!hE24_thw%F8uOHNn^h^R*_A;9{q~g@acteLwCC?bi>dM}YiTrTQ3VajLNMRwEr}|F_o5 zt;aiSt(co@!tm?=+FHMM+3QjA75Jr46B#wCnY*j&<>&*R)Mn5&%Ad)S8STE|)Az1E>bxuu)wm7W8iubo z)vm$v!o{^Ur&gBK)}V5h&oC0jU|r*-%WFzd8(&HSLe(l}TE5hTF*U2~#6HV61g%K7 zrDYM{_)Ami-mQ1atE4cbeT>$2AXGdlgN3-TzCI$IqZ-TY~kv6Jo_hwuV%~F*gee3w-@+T zSF?Tfhv%EWoUy0Kn+)c8qD=pE+iqWTnr@k#YREZFx<@OW$6lw`n~S;vur=Tcz)nUf z?h3$ucLm_1+}tj{`J;Dl{=?)op4`l!y|@*hOpyf(NB0f!n-~A$Xry*BNVl1OvY;N) zmt3^sYoC7okS9s+(9NK2MYX*0={-ds&B^$K*RpLuSe^!oua4P2888f+{Rbu z#T`0t{DD?KcG;diFwnfXn{1$YahK`NbJOI2^agca+@)&s;xySP`S!ZS-X^zKKaOj1 zdqrKX$!#mDU)pQHdZ?DuDs~sU17{UkmO)#Q4fpD4gn*fYgKUC6J+W(%&L3Mx@z9{1v4JZh+ z2PRmgF(kgb?5vzfOER|82RH3rf!18~B!Xh2o(j4R%?({@qAp5ARkjT&OD583%6~X- zjM#zpH9GAbY$pXDtwW%@ll*KvwKCP&FuoG!ags8qes|Nqn%_;M7GVe6@92@M|3CaL zH>a*S#v7UHY#0y6`<+%@DKHOcA_t;zoQ{LW2YSG{tj>c9ejRA&*xEp zM_*7?Ppwp0!+4K7oEkT%p7x32Y4&{w#nbGI)4tEFb|Tf&>{LmeS;gZ|;|{cIQMLzN zmo`DV7JcoWzTZoMDry)hCLgg&{h+$kSTmUqoABZ&-(x|^nLf%AZza*YDF<{!PY)^{ zbgogLxCWM9=)i}lC{SGuW0vh4GG-9{1K-d70^B1F#kTB1lc#5p!gFhYu2}iUBp6%c zJHQ?kLf!|R2Q{M=smZa}3%(uCzx$4AVmgjI=yWY+P(A2t1}+G_Urxda>g;;@dU|Oz ze6DlZ25l3@bG)qfr5qOXhpMI-OUBsu$>}`h`Ro!D>l2W=>Y{CGqII##Ci;AnVyCl> zG}Yn8997#9t6tw)uWDkk%4o!64Bxg6H)gAxC}}))&TT(?oyury!&ffqL$rvgQih15 zE$NDd@##i<%hQe)2aVG2regOg{qArtq=(#;*vSOlJ&i`B<$2D877tlcn0cU&v<75) z&>d+xo+C}RGBq#N)-ZO&?SVl(+MY@LL5w)h!xyXiaXcJ~I0{q`r!l41!=Y){Jly*^ zG#X^m@vPjLf$BUbTgT1mh<3E`M*$t*?V-+aLpcUSPNKMDgGL>S_osUyy)&i6(wS6& zQ@oHapp;meTlClC4<743(8HTjWO~pYGBt8|BR|X@!xzmu+G6rE?9|LuYs1(_hfYGy zpdLbhjvw;C*Ee9Ixu_-ToUP!MUU!dkNK{hwB0dUoS0SU$+Fyb{cwgo~_rq@>(}T{b z%G`dqqit!py*<DthT6|jZJjOFG;;=0=H_PbD#GsQBF=-M*jT@| zfh=jA_J+0bx~@>PPNQ`qhoV@t#VH3Yc6h4*O-!#t+>t|f?UnwQ);&=my%?;(BLV$C z#~;RCJ#6qz1$2hvYv@7x}4ZIH(iZ(XXaVLZ-nd8u)OdhGNXMl8Xx6V;9#eqgB1 zjSC038QrmC_G2*Q-ui{Zh6JRp1YW!jI@Nrf%W5NYeue9H_HU%0bg_eRlHv-Ggrd9Q%!M#a6EtTC$8$T-r)bIJ}w*g-=6*jf44l5 zr@M1y!qcnbJbloo%Iev*|GcN$&(-zYn=7P$jo!RgG_K<5wAdJ3vf}TcjUb$7(Qfir>=^A8}!WRvt+6_A( zwWOszWdSUB8%`RA?;&%TWlgh;-}$i?vtjH~i}lw-zqDe#W@cJr8!ao(O8dPvda;#u z_M_IMv#il!%Vx z-by>u$|$hX?tRY6m}nV~h_=kYdDPwebH21vUWAj*A@5sbH&|net+B+_?Hjjx%75SnMEY6hT0hF4V_9=ved9M)`XtNx`2{an#s|WI@B0@imasFEmIpf}+UYu6^W})V(z2~#mlixW z%d$SQj7g%D-n~EMODpAbRLXhLjTf!4(#KiW!~aXdct8}AX64=U&zI+-f2Kmt-upV= z^KV?>c;~-L`ECd#F5d&5_B(K6bNvv1g37lXC)**TtV7DJ)D~;lbSu?NAM<_d7+Im7u>)KMsKVheL=x~*_iCu=v=+OHfUiMQI5{W{k1`h zY)BjD?5_=4H$mDsb$@Np)6}v}SM9HjiLQ;)_SZ(pvC(4I!pQ#kM}uRd)2!Q18>Nno zjb`zF+Mw5CM4LvqvvXCpbFY`J$k2 zhGC5M1?Hz8pT594;gE%gv<5JGQk3bolD@-fj`sx=J0p!zM!YT33VY?j*1)Ctfv@IU zTk_Ml=i^znlsw0VwdEp%jWjOHr&TrnaoYn~_60^7TgkTn-}z8m*!yIlcKes#BkAO$ z+^f?2@~SUr-~T(Of942vTd&Wf{|nkrmg5os&S^h-(u1@020r(Eao%?z^BSoC{^Dx& z@0^@-VG0IG>FIn>gGD#Y43?Wt!yw;Se3;fA>R@o=Kptzk-)i^AP)k&gq-b{Zcju?#s?}$!JoBxcs*RUEbRvQ9NC`+aXarU6$J+Q9NC8 z+aXarT~6B}Q9NBL+aXar>Fkgwo-T3ikSLxmU+s`6o-R%8kSLxmJMEAto-QfvFc|T4 znP-PY_URJN4vFIFvd9jJ;_1@M4vFFiN>7(Nc1V=|ABiVl6#h%Aub1F%AU*7)uN{7b z!=lBxZI{zB1Ol`~Rn-Y|NmcydOC~cOyl;YtI zgVrQe8On-!E{T?%vq{>bX>OCyidkNgvfdMY`2aZ~&?-STE#dk#L~jJ{g$n?h;xLN#ss%ttPVTzD-HxnCbB8%|Df& z@O3mwGTBK&?`qje)VGL;1v5;0ldwX~-o^Fk@z_=l)Lrpr@)aT6W z3e`0;BMl(M@Z%u%233(_{vOZnxxvKqWt2mPR1v1Sk5Vvsr5#Mu$3IX-Z!b|GoDVsY z00Lp^;DZDZ2-8{?b}-Ep{_SozeG30xxSL-Ji-3HTOhEh&J29kbTI>o)H@(HWf!*{L zyB?T!3c@RMRw;#BrLw%q(u*~`FgeN)-%z!;A3 zV44B;U)UPq;57C=w(UWIX{NE?0^28H!XE?EePRlPKZQJ=BY{oqz!Mal2E16oBY-Ou zJPz32$EG=iWdXbS4`EY*-TDq;#{yH|NrCvez;vWgAbdRV3;{VV02U90iuf{MxBlsD zIk1~wI$H_s);FD<2|U@cm(Ci1=PURe;9>>i&Z*&l)3{&yt%8*rgx ze8*wwG=6s<|vi{>>i(^*jQknnu2m4s92dA)&9*psT2m9H59-PX) z=fMH?ng^$`-+1s4h9QL$d}ca3+=GX*lRS7BtMTCBtj&Wn*cBc;g5Bf6BiRoX8qU)2Bn<~Oe7J@u zYxoEaPtovH4IioDqcl8C!$)iQ7!6O?@Ua>`PQx=aJX6E7*j1kP&em{_hI2KXr{UQe zo}=Np8lI=&`5Hc6!wWQgf`(7j@JSk8sNsAK7ihRp!$le{)^Lf2OEtVm!)5G7Py3f^ zc(I0;Xt+YdOEtVq!^<^Xso|3~T&3Y^4cBORg@#vZ_!JGV((tJoK25`?YxoQepQ+)q z*lthz*0P5^_z*3AwT43)uG4V6h8r{-*6q!8VzsP@UTu;G<-Yzt8VGVwxFh0tXSi}!!c@j79_#v#s6Q99Om$;P2r?Z&EG!Zb$9LcVhxQOG?>`sYk zB4ZTpKRhWh-IyO`j$>~~49KXw?|I_Kvd<-^Yvxh7pEN8$OtEa;D02imN@7u;QEaZn zA#g_F{!yvKBEK<=ptV(eFgg=Aa|XgF63fINooDN*d9BOEJv6dM*Or;MAR9w+ropKA zl%DPh5s$9Dh)3~+>Dq%Z-LoM)S>iKE;^q?#x1IbEpDyF+o*MD#+KtlFH5*}SC&GtI zJVj!Nuoj+aMP<}MgM)v6bDPhW&@R1VR?Lhb9NYC2| zJgProy5?5PeT2kxZ;#^X8j<4ZS~(MA{x8%XZh(HF_E5?FwYN>yw_DctCRty)%u)S_ z+L79W?yXS!*nV`9#Q8Gb_8;1B#G`9tN@wp^x)vr}LJ}9s+|R+|`x$zDKl6M}a{Y23 zyFu8cd~LtB{Y=k?{Fr$BxIw=EEDyK&5HMGOa1nmKE2aFJlvhcK2IuitONoZ(_!=p< zOL?u7JEZ)&l-Eg#o0dG?4N~4HC3Ya!<0dATH%obolsl!oRm$7&&>@xgSB%dE_#R{I z1_O#;OZ{)8{&B|E%6gqEL@JCM9xA?bWY z`Y}=-s@nU#w6|BE!#d%=cNDFOEB&FJwKn8)T!D$C7>E1yU}Sa=DbW zza6`Ol6Jo@?czA*b|JaHL2`eC97*MZ3`$9}+k{V&vPep5N5}pr(*ASOKKci4ACmhI zB=IXyr3c<2 zXDA0*EY zlII8M$?vZ+zvpFs=vR4ukUSsACaNFgRa9Qco28_=1;UR@`GS#xk^f!Ya!ezCEvfm7Xdr=Kb7|PN&7f2aQl$lKOnh( zke=*7ZjzGM5BLs=_egmkq+|c@(*BFmKF&AXJ|y2iki6X>c{@S!c7mk26(8htQj*^} zc0ZGLUy^ol{^E8ad3ho0s9hkpQF=(4`yol|qLO?F)EXMFY!(g?9q37)k zeFtIa;R0NLpXC3C)T0aF`kzbvTT;)<0Xyd#h=-kvNW#u;lF)xw>YtSQA4>f%rT#ss z|BKWQp?bj1aFVb?bDm`9c&Vr7iAaB%)VD}|o77(__18)LO;Ufq)N}uU{qIZte@p$J zNJ9TtsZXc=7x~g08tD%wiF^yCzDDX-N&Pyhzf9_{l=|IL|6QqnQtIE9`aekhCsIEa zgKElm8cF0!b2OB1fz($^{V7u4CiNFf{iRZWqtt&(>K~B$=cWElsefDQ|0wkqE(R#y zG?K`7DoK=QuGBA(`ZJ|IBK7T3e~r|CQ|k9f{gYDvBdLE?>VGTsy;ASP0G09`PZIea zLlWhgA@z%-{#2OYYB52fC~#TDf{nk4caM-t`9 zmii*8UnKRbr9LY4ol<|f)PF9~1?u~{TBe&+a9i7_7L_$Lx$T+8um5@TG- z@lPebTH@Cw?w0sx5@Wo_`8a5Kei)~5{D#CBFLC^)#2Dvr{0oUO9^n`VJ5P^s1jqj+ zG0yiKzb!G&uN?nUVx0dten(=QuQ>j1iP70`{I0|}KXCk>#OTL4eqZ996913Hw@Unh z#J9=om~V=E2-LpVt<1MeVze*EcS?-*<#@NmXkU)^NR0O7_%4ajz8v2zG1`~odn88t za{Mic(Y_qtD>2%aV|1<~s9b1Yj_;Qk?aT245~F=N{0679t$ z+KEfF50_{cF3}!bq8+$I{kcTFxkP=rL_N7g{kTNExI}%pL_N4f`ME^7aa!ps)RbqR z6I!%*ZrQmNaZlq;DVkD|&FF6qkMlf(OX^%6naBUmj-$wDJ&8DnQ|9u&^Wur(K~Eyi z=alSOLS%EQ`s6KfvU5aiE|0aJxaBdTDA}_GLFAe(vdx|+lp=>5kwcEGp0JoB>XRd^ z{-H4_AFs3dzLVjJxkcio+XTB&l1+MX9;uJv!p%8#ic#lsk5cM zY-!K-QQ7e^+ZC_Fj#Au-;WF57O&O`QW^( zPWYg_8=c_6cs0^}5I&(cuFlE_4CS|(5~p(?Z1=_|e30Fxs1L3u)XE3d-8lWhbT`KH zAiAqg_~3b5bo_(nGwLI)?Xlx$w8x_KJ@6TPA(h(Z)-@4(yQR4`Y;TLNcS=&It}Ytx zw4-9{+rsTOfHiwFgeB@5-I%tHy4KKI;Oh15MX{FJhHy)0JwJCS`+#G;3CPP8j@*Yr zOJB8@E~L|h2a`6TOWE{t-h`(6X@yslYVqPN+C}O=dXQzirYhR zyki`edmVe2#ybnRI029HQS-&6JF7~-J6Yp>418JwUaQ7i2IF%Q@HT6_&ETnZw(E;q zA)fNlyFK#~*u$*@50Bo#*_(j(w8s0ki8+7-yq{{k4Y==mMFQR@8qbgWqYvAKmvNMA zG<2l4_wVDlkBQq^POy_4t?_muK_Xs>#@h_XNW=?iyruwSZFXkJ-QK)N=1IsN1P^b6*J)>_=xP2zN9?ZrZS`zj?L#Ot767~4WTuj3y!F%fXe{OwPRyz&mXTW2H&7%g&{EMkWc~C(GrW zrvV^?5KJI-2s`Fg;^ZTGmK z=X=gd#xN}q7j$0gDU4w{Aui~=+rYzZ`M99-YF4@LMyh0;_qQZ@J5LqoTGbY9>-PQw zgO_C5FLZixyo@uF<2?c1(|X|&l<)jA@vKS`yvZ2YVcH`u==J>xc)Q|Q@$GV6ZF2br zS9`|?wrM@zr<3HZ4l#!5nz*3b8&ik=Ks``piu1MO_l$b)csHdF-p(X>?lDv8013$mv32;yepFA{U}LZW@B>YTa_g5rX+c9C&`=A zlwA3mlH}c!B=4g>cw4pOEw9;IKKnq{d0pV43ycdo?^W=SbzIPSC!C!e?~WvSL(lPE z*V+Zp^IZd8GUa;-JY*dgbbIq!lH=W$ByZ^2<7=BzZR`$$KnG-Wy5sK24H$Xe_zE}|+}88G3%q37 z@2B7$nS{O1z{9PnxS;2IbXRh`72wT^vxaMN&9A-!UTzY+N5M;`9&aUCz9H+~wR+U- z_44I`m&|@U9lT`r+g9)r)t5i#ja%Y&S)S;FNB8jX-w7XqHzE`J1P3c#vE^X|{=N-T zn#01z*TgfCbS>|b`T*po8gGQcOHp|A-jr%DsPHU>ccR9d1>ShXQ@*JRuUg}kfj3R^ zs9Y3CwrIRI@baN2dv2t<@>qD`+>q6&RK$&g+^EHjo;?l%TRbHX}l(dNBf@w?$4Jf+yvsD+N8rsuJk?{A!ncFDnyLL%PZ z6`p;(C*q}ayY}*gxrFwHD!keK@G=$NoPKx{72e!_cvBP}?LP{M>T#^Xn=fbyd3g#C zQwTgHvUh^QThI@$SmB+}53fSuVM>CBMETYzyp#IjouTj+_QPvXc=`SCS`=PEKfIX2 zE9{52QQ;N!!`rOziu>VRq3}xj;cZuVrTy@3Qh19LUZZxr-2t9`{9;Ox2ik8s?{V<* zp{L{WQ2Zz);{6@GGQ<&YB9Rah@rti;d6=T)ArbEig_qS2?^W>f5l{JIDwBsq_AUITcm5l{9G?}yg|UX$ca?uU2mwK#W4-Vy!q?f`F<^_jmACOWxFecxUVo zgC44fJ-$oSF8dUoJswNMJK^iDy=ndAdym39x*y)e>)d)A(+_W>!kgX??@jRR_Or*^ ziRzJey_>H+&QHYK4xVjqMnCy}sPJa?!z;eQ^*=iQQ=oj;S>E&GcJQ|Og#R7FS%SAk z<4w8Q9e0-Z!^=~6i~HdfE4(HB@M;uZML)a-g}1aHUQFRF>xZ{l;Vtinw_V{?_QShF z;ho$M??HuE)eo;n;Z^s;dsX4p^uv2s;jQS0_p!oT*$*$}7S~@+>4%r8@W}ruke|l+ zpTawpvl8?26y9n5@QM{4ret|Yly8l~v*#HS@fs8!rds>77gKm=DZJ~o<88CT>*|NM zUE!_ohj)j<+t3g1L4|i-KfE4=x3M4Is|xS@et7RHybJo_eXQ^A5n zi1)F=!zFm1yuT~FtNY=l-0J3wp)U`K@*S%1FjVc6m#OeDwCs~NQQ=`I*e7p_!ov`+ zPu{T#4@0*;d3g%&x_)>kD7@?Y;T0=940(7+)P5BT@5X+3H45*het2gnyl?cwYfyMN z#qyA-d@TwOU16WRn8MrH4{xKw!zK@j^4+ZPZtI74g~GdC;XRGx4gc*fn{5Ygf{a(i zk3qt4lm(^oUhqz#0x7}3_Rlq*br+sjhE5H{t8WR-h}4}uGbls$+_|~4a^}v;&Itx* zah>`%7@V6oA2AeG54o_UqLe6uG;e7uOsV?k_8!#aTzng8?Bub1pFj`pp@ z7k+M>w5>R+q}x|ztzlPPy1sCCN`zgt1#)s{uUWXY__zftSM>Hgz3+R)#}#fZyrgva zf|Whb?|b3dtO=c$e(vYb+2M8>Ldt({dhzj--Vdz~0^oL+nA0&(XMB|0JSU~7qM){> zpn6GdHm$tX;^G`;Sms(6=VEblv(?3U%x9Sq7tdxXmf7awIn1)mb6q@_`7JZ*;(099 zGTX&1L0Qy0U)xvJRQ%?dK@`p@s>w?jYCmUL$J#o4-Nt9e>?*Nuf+f>_XKQ2ojc;3@ zdD0rRzA&n}O=MeDzGzWNRc-b1(wb8Ws!FKBS9@X#ii--esovMbsdK3M+vC)^)C$+e zsq?5YcEqVmR@P9fd|i(y%%;Y4|8ZFGH{I+q13^M*Ke9+p5cZ;Vq@rb8_ACOx7k zo26UkH{#SeY^Y`49H-7@!z}ZbICUNyZkapd)Rbw4W!|bs6lb#$mU&y8I){z4%-iGC zxonhW-VvwHW1}ten{jH&G}AJ7c_LPoFRRIBhgs(CICT!ovdlek>RdL-GVh90<5;!K zyW`ZevBk7A}<=0kBY^C{+7%X~O4CVLh|9cP)3#7FT~ zm|>ZZ#z*mHm}!~c@kG_Y)+|WN>-$}MxRS5N#xw%9VC@#ss63MzTcmRRPqaWTAN6_)w^xEQ{Fms;j?aWQ=V zF0;%Z#KrLayWBGWGcJbj-%87T-Wzjri6~pOW$ufM;bp6_%opQgc-dB1=1ZQK>f%!2 z$+edGa$F3zw%Rg(?1@=XDGG3oWxnQ#sIDxpSyg~0Wos?-bv>#|M73Jx&-AF8RfUu) zVwpeJqpCzyn`OSCN7bwPKh>Wnlui02d}ZRDyue)ihM^SV4VUtJ{9LMwIB4M$0Qq~rCg9$In6U0z~) zb7O0`Az0rOiZa8`Kkg;@pLLD>#U&4nJI>4RX!WEB@F`rGV$-JXmMPnp{l%MN9oepp zF?>$#NVhcijOpEw{jJJ}yxjJtNHm5MGM`wNR%;%AasC_2Zmst+opQ(|seH|4ndJIE zUGAHH+Wn_^lQg$-({yiD@)|}xbjYOD?|26hKF2gqkjg*MBolO&-FNp()gza94Yx$F zQUX2&Lw92(@tdLHZ_WEv(W_pfV_Bp~g&Bva*WNN=cbe&P^MDjyXq$jg>u@n;q! z``s~5^h__FndW7CY9o`Ss{8ovuM}23_q*L~-ehZ9A|ZG~3V+B#W^mcsy`9F1v_(c zX3Uw9J)@$g8WC;l(Zw{yg461c4rb4vKj*ldS=sY~HQ}yMd$1hKd_+6ehFfE_T_1_I zMWR?PqJbG9(`mdxtD4hz)PU423|dZKQX~2r(28^^gO~GbL`Pp8>4?^cslvR*hLN2x zez3fWH~A?>mtj=K+{-Kb8q6?G#zG4Gd}N=oQq0X4v`6c!!!1?eMrQXj&~9vRYF-mt z8ER3L=Or)-?grheHI=u(VfdTEzuiXH&G-;0guH$xVHk7^B!$KJHWt|T5(c%6kfm6a z8h;I6_Atu|KWL@ZZ?de=ar^$qGLH6}CJOiquu|Bo_?w^xgIK^OD&8R47o8d^g>0ta z*Nc#Xni|H0p_we;52OYHfwaJoKzd+eU_oGEpeV3N-rk^+ao-+&!40fnbXUXZ3ksMq zlKBE7#*I!tG%z)Ad44)5IKi9aeSz{Ij{A`Y#f~&a;WP0L!#4w8jrRpeE501R@Q~KP zrTKxc=BIDTPv4$D3{9Ws*s!)-WU#(IIPd+iywClxe2VuI@|O67yx;zW{FnRXc5EBX|TEN1$&4kA|cl1;U4jP5zhGC7tBKrt|$; zQu}b)Ki(5>u~HBAYdBTI0nZu{K78Y(){}k+|1N;7^5L7q-uQH8&uJ0Ihi}4ocBJpqqbzO`V9yIH=Wa_wc@lRS|~a9TfvZ@AQBQeiD&@XwW! zukj4b*Jg&S#SW)U*W$hjNg9N2=iO zCJ8(Dkc9q+QvXY-r|;2_{u8MWpf1E8N)q}>B$02n)X$dsSaT?7xop3;=#g4p^Oi-#%TSV@ZytW6=Dre{#RR2Fwr>X zz%31zxVz&^JlSh>^;5tve?6*$W2GSSA^MSzQOFa*`D^7H*DI{z-P%9{z^87e_;*FdVg%fTy8z^l`EuY%W{fJf&n z)!vDt7z-xgZPa*Yf;T+@?+WNJkJn~LZ2>RW28z55+jJVV!{gxPqacSuVUI_s-@6Mx z_~?Z;@9&62x9tfyjj+e?Q}uyNF>j7)d)`}kLF3W87j*t5p1se=p3a*FUcTg^YvzG? zZ{Vlq+XUVSRE+GQ9e5z#hxn;^OiokbC57G_oW zi?c*NDL~5{6acDpP;SKVa4iov&BHw`VtTlK4|j-%n;Kcv{Y1#9dO2iPy%(C$xdkOo zK})ISJ%g9GXnIk1O4Z0lwBVJ@^sOv1_5_%*=ZrnOsU5cOEgC}cA2+clgT2FLdu-;` zig$bMt>yL#dD|9m?Lqr7pJ>bCOMXHv>mal&-+r&BXK(Q(!CpT{e*#Kuc{8^RdnVZ{ zzNE+hEIb9RA<<8O(8?0M2ZXkf=ucT>b0(g^j$m{j##RTb!+K#ItQ{x{97C@<6I)?) zc@b!5;tTgVa6|gHj)i!PH+~J`=b=xWi|4f)WZD*_4{@8duyYP;guVf3n^`B%rv+Pe z(CKLtaq972I+o4kPmR+%ZT}a`UXR1>Wc);roKo+y3g|?8}TOrUbYc`0N}@B2|;P}KW~_F*ooKmJQRc($Ec6nigdKb!qIkI zP`+Yk-Pc@>lQOm6xg3XF3&M7=W_C}>*U^ie6;VQtN!$t#ooOsCS0=T(1c4$fjvQ_PPm*q_nzPU zv2g2^-gGqK!c&d03T(@L%^bPK6Z1fQ&K$W!rye3jpEE~J3ZFW2lrrGVk(Tj^{1%Auz4Ng&=peNSJxY)_L8G=1eJ8)*8&r8>Xsmc(flyH9Aw*i4pv z(B^0`@}vG6czi2BRD|C}?PihTGd+PoVl{{y+A<1wgB!?Ejqi-Se`$++jgL#8+;D2MEm z4yDLqhq;VZ4Xexjcg4BQHFfi9+G^LRf@Z!`Zea(gF06#L>$3yKi#cWwm}vt12A* z=8H<$hUHszL5l@J%Ub55$P}$pqT)crbs&*`4uT6ZwM*R$J8hJkSuun9YdxQw{Z(Nt zIXlxh`BCl2ImV8|W11jVeq1~9Q`(WwYDYc~^3+oNIL`R)?)mvxntB`oD@ znN>AwL8~fU<~8LmwS2nt!K!mN+Yc7%ess_W!G#Tuo>s_s2&_gtkC_;&^23w=yR~&@ zr*OzsmUE=CsKz6#EX-@lJ&%>e@afXZ@{!ESf>wCl`o_kJnzkB8&yU1ape-4wjC#~w zW2)@q`1$V5Jae+bw}8;Cb?X>JddStSN~v44Z4_25W;Nwr%BmH5bZO1{L_0OBb&aZ7 zdQPvMnq{G~saYxZrT$069DI@Bw0p)X&o0WbGQorwZslC}TF`JEX?{1YBjp>vavqy+ zt|R?K5(`O3dhY-Ft4G6RB~UWs4qCEqXR@Yw?z1T@-E-YfBe7v=6&$o=y`z%#>>DGu zZM(^HNBU*6LkTuX+8C_VPaKjedm}-ZIbK+ z)xnX7=vYG?SeRdx#yHGhl%KgE-(QSBV#8nT}!QD*4)>pgXxKQI5bfVg^Wz{aupRJ~LasF%( zwTts-Yo}eDKU*^G;{4f4X*UuVe){>X)ZYw~`K516fa0gL5EYsBrpgf5VgRjqL;{&c zKVHs>YmFVu=yH^tve3+T(u`h;Mj?ur`E>mbNtAETYG|X-_#Exe8S=W zLhZPZ>93jrUaC@rUDsy)HeL_i&3p!s16*{E-%) zw)mqgex&ocNPMH52O@mF#TQw8vBj4-zlg*)#p0)0{4|R{&f=$A{P7llg7XK7k1hWIJU@RGp1s)svOUv6Q2mQTQH| zqaoCI;tHUIU$;n)63X_MJik_v^6L~SzebVr>l5ibp*lU-E1~rB!$L>#_NM>h_S5AT zkFgIDqv1;sCW(Y9ieZSN=;9Schoa~Rp=ey0mgMoWKN1;Q>q3A=T**%qIfeskiG%+0 zg|clU|6!px`9$%w$sB}7htxnkR@bTUNS6u^`XPn`tr6Or;lZnWdV<7%l7v52!XrN_ zJg5o}s=|X#Wq8mEq05AxCv=_A4WL2#P8R(WML)_(=?AT6xQ6q-V1B7TI>X+q}y7-e^8be`H@18 z7CI3$&{rz@CW}7Yf29vp=>t{zKqoOg=t)9P7rI0!%QetDQ}p5iQ0YW{QhGs`GM%8y zgz^I+`4fef3RU)g_5CiFeYQoi&$bM9rV(8da-|<~r5|#R6)68aDdhK(LjH)zpA) zME-k`za#SegdcAoQt08(mFZFCgm|&@MagSK-bxDjMv>nj^4%i;g2?xX{AVIp^|Q=z z{zv3FNncMcDdfkHBHkGyFBSO;k++C^gUGKC`7I*pvL@)t$^ipbv;c|Y_6jF=R}d8B62iAPO@0`{i5Ade2MUAw-k@H?(7TL4k>=B@Ms4VKTUW%uZl;9q40R# z6hB>fJSVFC9qI2sV>_$(QNklW#g7&q@hN_c@Q6?GV}(b2ibqG$5B-5bH2)=DL&_GDDqVlDIK#G`>6u8_hUz2 zdDT|v6Jk;xdRS==J=%GNH2~o&YbZ2cQA1()N;(NzTiZ^Ugd>I;a5h$VZWWJwu4j=L z-?zzzi3}IUDOfv;vsCtiZRY=y<$myYz~fM@u$tIaG2+=?b&P_HDjD%Gt7XI^yz7$= zjotWuTgUc}Z66)CHknShg?xXoacKGjr*UYOBe-+Hqv;Nu#xbm^ZyWe!0m}Cyy8wSC z?j`VFriVDKZyk6OcO97d8YF&XKPJ~YzZ}DyO%HKe-%a36eKQjNo_ZViMZv*axt+M! zpp`(P<=@1$A$C&etIt3`Y`e!T+&OrmQtvMo(8fKMkNxI4G6QSle$q?cM+^)vZQM(J zkdG|%E$xr-Ytm8{qwj|WnElK`-(T@gtH$G&N;`dvFn&jRi5eo0g+kG zp9PNd3%1Jz$i(GioS(Kq;BDM7S>jI35_fKvxE)#I?#UAOcssbmta5oBI22)qvvK|K zel$JNjDzT>mRtppCQsu|AKcP((JG8xXsJ(MNxKY>Hl&v0ta#5hOBMP~6zoZ(JF zeiMdt3UKQ@zYZ=EIp0h9H7?J<-7(33AD#i3ZZmRmz0$%x1KbM8iGy0@h`ZdvO_}V^ zFAw{VSyKE_8!`cvSb|6(P;&qskX^F=vv98a0@oxoAf zcrgS}E)I92f#cjYT^w$gfx}Qixj5Y22JWy9a1R(b{T(t+-$MotLyvaj-DBV|r4iu% z$10b{fMa|t7yZ4E@!Gf-fGZUohHlEm;nJ9NDTOcf^;Rgq{A_(IfLkFr4DpnU)3*n> z8wJ<51Kd(PybA@_uLIoOz%3OVhK$O^#mh4iw7vlb4xff2^=ct-yC7qJ^9>y5j?MbF z4=*%K7jeToz&V)L(l`vslw8hRIqQpl7mmaI(!k+Txj5Vl25wphxK|Avrcm3}x6i;$?*R9XfjhnfoP$K^ z{GMRoPD8n%-wE3LT;OzjCNM=l1Y8nVX%UVDZaQS9L(`|u&@*voBk|2KxZ1VrT3d}1 zygIX=R5Z1)cuJbC^Ygo2kczI)?^@)XF6Vb`UFM(PHKHcHf7i0IzQaKGfDQ(I0dxSU z^CACyuQX^r_)^dm=nBw;b-q{X-HHp#x0FRrt~y?w2UT%R)wTO?-ha!U{dZTV8h8TN z30l5v|INuIyK{DLzvTJkk~{M5dc5-bksF4nGokiA(RWYfLF1g#i z>+zSbuR@Ie8C!dYl_D*2J>*;ahixd|j?>3*-qzlWDz^8LtJ&KJ$<@E&`CDsohF2^8 zO~P4Vjx!2>{s=SY-$p=C7ATE_ZUlrqirf=@yi*z?HE?GuDV932Jvb^1_g)T;3PLGM z9S#y0N%f%O3?eTGpM+;MG~&3PIk0D>ikW$)1szpgG7w!_ z9crD0%8E|pL=$Y(Z>?FouCab0PMWH%f!Qj3po8mv*!MZJp{cHUV<=C2bYt5Zpw~1v z)&U zhh?oK*S}>}*}13{bbg&)8V~5=D!uXlw<>*g_gCpdveUlKs?u|L8q|U&n8aOt*8Fl+ zul?TpVzXXbs4lMDx5plTu?BrfWm64J4C;Xe+UmyUjg~OBNsbB3<~TEScFk_eA3VI; z{grYKZqXq(czDCAl#9?ctE$M{y6(MZRaAamTmhett$=H5HZgK^(?KVV3RqWP+fq-v zj1f5wOslJJthvAvZd$i-?cxiXY8SWEhB`2?fUQeWy?9OC#-M)3R^^yvuqwx6UpK|UMi(~%_Pb!uS-j46?@ z@b)u#=f8o2R!;e>=UwTO?VdZuk(P;^x(+AKYwCN!-1Y*!BMlXW7CF%sUytG<^#?PyC*r1BQXn^>FV=1 zaLPf}b~XQfmPOAK{}s;X(1%wfqK8)`!^10b{KG43i>Ez47^hY6Ins{91q|ij{P|U0 z@p;$oK>Rz?&u37((YWyA=NvD0;rSy+`($~}^!qqY|An}Wi76@`7l1jf5)al>0{rgn zE9U#EjkVsQsGQ#p{Q!KIumc3+;BGiCf@^2SFiCJcAA;A+Ivsi52ff~j=R|`)=%3@91U~f7arkZ-`s3gt@PqM3$MYQ)fMN-`a^%mz6-$SX{4&rmJ)ZjV8tO}_ zHM4^hn)sC3>lwzMf-NTOr#1XJp4IDJh~EYtODdEj{|UJ!aj~ELQwGoTAIvq~NtDl5 zBK}F|sR*B=?89jh&wuF6&yeDhh;MX+@8Oh0_&kfxxA>kG-^=2ATYMkql!*Sm7T?d} z`&;|~iyvt51r|TZIV}?3V2eM@;)huLP>Ua?_6UdNcet}EqCeO2A8zqSSo{c!KhomU zYVU3s-$={w8f9H_^}p$wDXCGzHt^m-r|q3_z4z&tlDGD^s_x4famo; zM8D7HIFAd@=bYysykf-9^AY|eJlk8Ir@$6II3EEEPJ5EC@YkMt;5i*l{-4FQ7oKYf z84urB84sUz^6X>C`^ojsH@FNk91f-SrzDXu#SamRfQrYWD}K&R;v4;Wq$3@tnM$z8 zPRX%|PRY?IHH*Ghq3Rq1=;zvE#>4$Vq&$}(2#>}_g&!^9kq#9ew3gvOR|~z5;lV#F z^l_o=fGGbtXrLF1@swUP*eYGfm(mNW(gVt8BMEvB!-IZZ=wm{EEc9v6KyQiY9V>cK zPD(GRN+&2kTyuZ%M;IP-htR8pe#+E0Mf73)yGkd@Tj>K;`{O}ts1Ni%7#{SyLe)NW z@GlDgd!cWF2I-w9`~T5Nunr`r`lmo8AwPvYj6>bF@VLzaxeG z4&-48+>krZn_xO7u=qs zcqM)vJS4WYvmN3e+a)@5@e!xnDei-^aZ3!O#_=80#O(mTE(SNl!m;0t!!5ON=R$d0 zycbxwJ;3dROgo)E%6N_LPPv7+cvP-QwEQ+)>oAn}LH{%peUR<$gTTZsKtZW7rv2o@@1^p32ql&q}AB36I^RQoSmdIX<+U2joz&l2`M3(W2JLCk*Dc&Tz@-g;eQD!{V9c2fZhDru zrCH)OwS)U#B-FfbHv)%Yc!sladw|36I>Xtx{{oI3c<%-d{KXQ~xdS*e9OcB>dzl{q zj&kOM`J{`(J!Ihe`>&oW5}e4!5RV+;jtnB5xNr$H3|Ki1G4#$2A7TpVtVfjg!H+&Tk?X_9vJZ8C7Woo2ivkq^&kU$z3L@0X}k zWD0O>57Q#N3AjiD3l_K5;aO1;91>-pRYY9vy7g@hYwKI|cGu4Kx=x>3T$om_^S!Pd zGtue2t`lJRKJjkZ2<&6+27 zsg8nFpIy0V0b)(MOWVUOI%EEOkrFT5{?4{E;MWV`C+1%WS zZ;)!pBS5`7EedRHSlv`#m-hFSrBw4Ec)emaieKLp36ZNB6A7_(>otv|ubcl)G{i>g zUf$;50}vZB!QMA$|K_4EEc|K|i=7fJZI0`yR{%kp8$*L~$O+ORL3*gwNfPAKf4L$# z;p_*_j4E$vQmQ#x6kOeauMRzO#Y_K);sVtwKo2!VApy*dp+Q=b%a;dRJcsAZ)Jl0; zhK@+@(1=8o3_=a^W@^pmt=%x^{(GNX-2b#ls2qQrXS*9igJgw8)XB!sAcSP3q!@Q= zc;_2K!*K6qV`vacWhAZAmgA{0vJ~>mgTA?ULdE2~Xtsm9!VnUyhgqZU{aD$;AN=v| zbi*-&)Nj%Y)YQ`fwn3&nGC%!lTrt6tjsz31P2JE~MAA;hy^ zleFtCo#P=2a+dcDKTHh8OK(Tf(+bOp&s1+HYuC5xj&I$2bKsdzHxCDfL|KL?A0wv2wuO! zo5d%&#(k{k{@L7Oq0`n)y99J=;rEYW+6s}hC0>u$Jon>%>Rv|5bDUq}w;Rog>eQ){ z>!PQ^sv*eWX#Blbo1*OFWbeQk2fFT`?SibgKb<=8Zc&v+3)xlnFF%;;?f*IJhn_Z@ z*duBTG1oVSn5T^)=6^7jm+NUn+@gs5ZS~SDp zxkkAx!Y7;$Mfjw1VT8|du8i<0i|=9axoVx94w8h8Ja!)1B@_7;-_zoIId^CBw@+D#B^IH+TXZiQD`2Nll5&S^Qe}MCgh<|~_4|0AV@gHpQhed4sagD6L!K{>A zW6PeNYh-(XdMU99hHqDXJ@D72Zi8Pk*HP=wlXw>d%t_*=H<9+i8aaaTom|N=7FF`T zkW07?LhFE|9)1%d<$0QVe@^6Yi2P3?$25_OcQ7f^GmI4ZV#}PwaJY~Z^;hwDpcIe#sGfsfvSt$gipR$= zexC}SANXrIZgYE%Yb8%xGiB;o<(uMrirD3n%FIt>nVp^qHV65#m`;0TbSejJ5n?zQ z5_FCkiSySF>Q#g~5C44jK1l2SbgnWoe~4I|VZG-cp94B`tUz8r7wnsC+#~|TY1~Ng zCT=D8u^J?PWXt3l&75-E@w->9NwoZQTx;Ew&jnM6Ho$fthQP#aL55VHXaQ~9ACWQD z_jQ8nf%k9Kr&+jjt#}*Jrd(!W$lAC+0e5p2xGT_R-I@h%JjMX8#^Bg*o8?k~F+qia zLo=(Kja%9dj(Icn-3;7h(P0uB_aoqznE<)AaYv(pW?9+J#$65E`8Ejr)%Y{hmq4G< z5QAgco4E6UOJ{+*q8;45mcDy|)8D>LwKncq;Mix`?qLX$#+o8d{gl`s@IS?$epcu` z12_uCgJ1}$9Q(ZI@P}?Oa5FG=L^rDTLm?jJ&`mo3z#kr+U~Nw|aAr6HiR0cCQ@#Q? z$}vQUtaY(*YYbdZVCficgr#qtkv`ov#o@LCSBmhAmu(bX9PTmT7Q&A>`qPneJZa`* z2*$u1!x5*O8REDP(!{O97@6ftoVmuv#%(olctn+>zJ->)odym`Z5Ox8z#*vtj(fw* z^gRF^<6-&+`!L1ZxQ7fJE|p`rjnIeu2lZeNJmc12d>lB|pR@|;IKLteGSiX0+QPks z%J-QVTwP7AUVfogR%EdT!#{33i}S{>Ykv)foHw42H5mPHzIX~W4Qj8!$bUEa(k!PU za*p^3Y8A%)kneh>;0vjhJVX3MC9Bx+);0TgR$ae;=hl6@bGPoVx<2u$;{xe&-Ns`t zRk_Ya=MO0DjmekhI9L82#kA4cxcgfJ`tCmb;{84A@3*8|7p3Z`eZJB@azp4}vEwd; zdg}>i|6SMa{?S`E4BN2d-4xp8HP}PPl@*h*%3>wn>DFT}9oJb*R%i5qf?`NqW-JkKOJq*an2^E4tR!b#9xilxg2`Vb5=uM2cHJKFEXA+T&;x6 z4jYH5gQi+p0Wu0j;rC4cJ}X zhyol=j0RGje0@Ytsa{>7*2zk+XMS>F;>Ah3%cH?`paO4#)~golN+7*bA`&RfM#sx9 z%)|u?DY9685rzvwWwHDs2=(uCxwBY)5tdf4{KBYWE#GmfUb*nkCq-_1LLt@ClfzPV zdM$^!R>EAh5k?TM!Z;Q+Rw|acY9oYZw`wE6cjs~5oJo_kch$FBcBZu`B8&*T=%Y{V z!CJ7#zAu%aZGBVyf>o<9F;?BuuogMRBs~6Hx0v_e^6kPZQ0tuSwz=-Y z=)v8IofBH>SJk)FH`UfJX>M$*S&i|ibV57_GlGU-b4Tb+P4yd%tQvYY;*@X0N3Z$x z>_>nNy|I{sZ@vc07df!C#nU&{tZZ0b*RWxg`gm?YDga3>!H@q=c955UT#IDn;2nau zyStWu_>VgaAY5IsT~>bl)m-_Zlhr*Ze};W*m@FQxIemF!@yx4VKWv-l4$1Pc#nH&x z!B{WB$JSpj(U#z%i~m2@OZ=;!u*XhVyWzM%GY#jDFnPthtldal`2HLi@f)h$U=cYc zK(Xi4D63^Bu;XP9Oqeunj?0!W$4$AM7qp!zid*-9ZLX1Z51b{?b7frjFdn>~i{rWn z&P(f3AwL!TO#IQ2KM{16;(T8FQN(o;RpLj&brK6Ad;&8Zp-V#FMIj4(PULJjp569| zh<^`@&viZ>@z1mPe2edC@x7coBjI~nd>`k_5&yo)%oiyE`clw1&ZqL!l*nAlw*#b>m4{@&R0c#2Ul`L#DNdPoiFrk;K-}9 zzCia2uNEun@R)~G;Ri~1#HYf8sxz)YYZwkxotXuy&ddV+H1bQiI&%s15#iN30`NZo zAEXn_0HRduMA#xE50|s9z?>rTa*=ark%WAW$QwnzP2@L<{AQ6qB=W~a{-nrX7WrRA z{x^~Hd8hs~DIQvN))mq-Q{?KbE6CM44#@d-OuRbl3i6A|L%vJoUnYh8L6QGlZ~>Be^KPGh`dJ< z{*VtPh5jQ*fj>#)3q-zHj&y;RRl zUs-IdDS|^}6$Zu|sO|h?{imDali*iB581B6 z;8@Ajw-Wpp18u$^*=hJA4$YQw{lI)fu1U1K64yEnls^vUWjy<~TLgiL`yw)=`c4aI z;|@nBuKLJMaOr&M<1C!LuHz4AQ!cYGWNqBJ7%<+D1AVa;-$1KeaopT4wl8-ZJE(o(7I-v7L=O2@SZJK8^nvF3j{@ z0vyLYw%ZATiF+Nmv<(7p$KMe!0|o8 zcHe_QKP&Wm0Ju^JsPiZa;E**nhR#!*|FaKcz*1cDJ3Zo2j^o+a@rOqz`2JpqKHCgO zAaQ@kpDE|M4$7%7AAfXlxC#S@?pQhExZc*(Hy1dLA*oNdO>ww7;7SE&uEVhP-2vPh z!BGz#>ETwqy)c$ohw@{*9zk%#9c$sX92UP0!^T}{;PB`vM|~$*`ffIGNNT&d`wSf4 zGw7(#Uf1ymaFjD27!D~Hhudr5a2epZUK{xj>cJE6#Op(b+W;KvPg;C_58NooOh=aI zPn) zE}7$0qzZvNHI-a3C-quwZekYgk|TV6aMdfg>Jwa*r3TfM0q0%SZ{OY#Wjmh1)c|$% zGOh~L)myk4j4Q6skW^oqnd*$!f# zU6fPvttI7&yk_sJ5&QODQ+EB#i7WTJJIk*x5AIl>MgCoQRpqDr8XYc?C>z0W>3!uB z_g=$LyZeN9+Si{j^nbWr{XJHs_aE)@PE)rZ14HTa1@y0mUz+1(>Il*ysA=lAOL@ddL0z6Sp6chDdc6Y%*Ma25{ZP z`n-zr#q*ZWtDLuB(OJu@=FcoIuUx#is%&m0$8;MazGp9(Us;45d5Mh~;$oOSPi%^a zXPq&3?s8w9lk^f7U}Y7elr(*8?UGX;e*LrsX^4U}rTnDSuWfF*U~yYb+xk{a#ckHf zcODLd=iT0P^MAdayFU`#eG~v>>Fa(n7R{VDcX1(e@l8XZ(*LL-P$~bGAt+&L_ZWgH zPL7xOwjr46cwXW=fuN$$NqLFyhJ2CJ!%OV-`SQ6lojzXTd;V!`lKXF;wC}eU&d+-; zl6*h+NHq?bS&xG)l8Nu@Y&u1_WfJyhLwo(?f6jU1tw>mR3INFZQ+}k2E6b}FELuL3 zng3}-RL0x)vxumix9;hPsDefCOhi=4Lil+^G>gUXY(zAhCGm@hXbubGml08wlj|j( zi-=Bj^1Q^aBBIlrd@u3qh-j|U(@Q)b5zTXYd5Qmwh~~q-SK>GRP)`c&<+kC^-}{rV zzYr-jzrYvQ*S0mcptOIhOID4YC1CQ1;vIdSST{Hl(B;G-O8Z_v+J%c2RHMKvD_Gq3 z`LZ+Shf0HpRZKMk|yF0P!X;#ZHtM{TKk9zGUH)`T@b zYIKiBi;y0z=X&RI8g-BvzRH9E}wIwg6Jf}}$jU_LkJk=-Bpye1OhUwVc z@X5W$Upu%pk`6x~Xag74w6<<+ZmC0BkdbqBqSZ=pxj$##SvdN0S1-MCJah)FRxhnK zmwL?=P$xe4<_|wS`g;Q@58ydzt;N*r-SEmO_4N<_I;vSK@HLNu8cE12BQN{f7sfsL zhlu9<4$qnj640ZQv!+5|JgNgpSs8aUGtwFJL0rwKKXnkgcMq~=UN5XPqENcs6pN=tr=(a1?iizxo2H%!#9UU zVpE0I*|}Ch9MRl#cCJ+zELd21beJ4-g=C2AbcJLH&2EKcfbXTxwaRFz%yX>*cuuG1 zS_ROsRP>{NZa8A;s-<-5HMbVUiP@VjTBCH(mPm5iHT*=-=@Lm=f03@CtBS%XZI*by zL$TDSpcvIV$m;qw48+x#MrYP_Z*uipi;d}`+NX+qjdO>q4k}vfzZU3s2Odq-QnOax zlk|88(hDsO*y|7}OV53v$a#9HK-btn^O*P%YFLQZqH*P(L|>mgT%T67&+-_+P# zdmigf5nf4D5i`TCTcp|?%eyP93?`GfGtZ)u*@yuPU}kQz&9S=&-)tMd4FmD^BU zJZajbqDgbB7pKdc*Im%kuzF2fdR*=JbkXt0Pn%d=STsFdUB9WOHC@%z+SamuZGBT4 zuWOrI)-|`(wAI%+ZZf9I6-TSwN31HRyt}r_ee;7^<#?Q7_YSZ4`Rb5sb$_q#jlMOimPNo_TgU$1 z-oRe!jyWQ;M)gMD$WQh`?b5F;TtARH96vA(+wHaLkZipgtXfsvZtInF<0_Vo@7k($ zM0?}?u57=!5Vw2#NiLN;d!*TkC^~LSl#H#4xD8S4HMJhj+`l>oSF` ziojo@?YYUDlD)lx3eT(kgXfO-_qSdjNn7E;OWRkGHm~i;&w1{Xe#-VlQZ}LcQs#eI z!jcXa9!jmKw|7{*S8$bgSe@ssN%ZLZXoHt`ve!G2>f4Y=4Z6zfnQZu^=l$}PS6=zO zmsbzsxxe@G@a+#u9{!G{F@p~<6E{aP(T!Eaz7c!5alFmT`^g&wbOcebLknIC!ahk*OQyd6i=-#sm$}3##mXf#2>kToHCXUDfy3uUx+xr^qPh z;)D5UT)o#b82BAq>`lx+P@5I}!Y4ZB9jFd|<N2*oO7V*;5(7%SazT~I7;?)Y*BVmy84U`uPWV?yR9_$@=|YmY0v9Q zu}v;#ijx?U%&kgeD6{<%*Xi$myp-EokQ6N!6D$4Q0q($_hv$yTy`mJa;K@m@J206` zsj@24mAZSLGE~ytv%PdPB|Dh%)IXJrZjC9p8{LqrZi~x1WoQsryS40nx?3N(xPqt0 zw@PF^G70;Ui7TpP_(0}Fs`=ZYIDhtv+8u~Ldm`=P!c(SQoPTHG{V6M7LtJ?FK-$Imvv<*MBrg2&;flan7!&DF zTl%{Ykz5h$qqqdjMA_dai5?rEx$+`FTT4;0LIw*AxMtW-0Y9w=Iy?9-%rhzc5d27* z5h60@&9sCu@bj0Ax4*?OL>L1i&dp0gD^3xh6!Gn=@>1Y5b4BmYTU zh5kL9Pk|5pdnlU@Lwz{H_i%2H;B%dOBKTZoYl`1l=@PJw^$_R)#rgcVaIN?I(*OJ5 z!~Eu}{p3Ree7^GxuKiE844AVF0P=8P7HSnwnbcsYyXPo^AF3v`-U+_whN- zDZ+CEHvsMXS;BL~HURB6M%s>-hP@Tgf;N8-pvg1(0))vC92fEs$3CS1p4vYp{<-2$ zz4Z5+Q~wOSOCd{+bR0!T2^}pIovM;!D5vPrLdOXmFBC%><&RF6aVF>c=g1_d!=@l3 zTOjgJ%Pn7V;rwR|M;ssTDK-VyS(6vHaO+6T(oXdD;h#r)a(gUjWfGRzpN)M>g0~*m& zEqYE8Jt$|T2UO()^gQMV^g~Ps=t`l~8MT6aC8j>?{8jloMfBl*D}A6UU7#vmpvv|mXdU%}(gtFXt}{hXspvs{QF=gCxvH zJ)kN*puHI$bf6g?4=~4F$#Su2dA8$l{yqu$eIkE=6!Pap{)Wi^B=Q@1KY+i76nef$ z3j8x7|GmgL=Am5Kf&~8Xq>n$66!J1s$g4%ZROAnc{5vB5zR3599K$meZ;BLpW|KnC zSt9?C$S)W9r$v5?$oqOe{wUINjO$6EXQ9YfihPyGFBbXLBL9@g?-BVUBHttO=S2R7 z$p0jAHY`l%08+#|m=y7j7x{@IKSktciTpf~H;eoVk>4Wn&x-tOBLAVte=PDBMgC`z zzb*2D9)5bpk|I6FkRm-ZL_S~Si$uOwpt{?AU zQp7uq6!D%Y@_8aZUF7RTeyPZ}iTraS{|}KrB=TR0{7sSX6M4TpKi-j~h<7Y0;yqd9 z3q@Wn^7SIWT;x}X{5Fw)N#tJ@`QsvgUgR%`{BI)fmG8&fkCgYF6!qamk)I;+YLTxJ z`MDzJTY9oW&ZZnGXH`}TKT7yn!jBeyw(w(wpCkNO;j4r{TKH3iA1C~2!jBhzuJFeQ zj~CxUrVH&1sukwU{r6n$CCr z+SATIZgo}0G?bo}vL~FfJOgy@aq2wK>FW1*^;=ZvlOmrK`=rDt{vo18{wbnG>KM_v zMZS(AUrCX#rP$X}>}x6ZwG{hWihV7`zLsKNOR=w|SZT>Tnv^T(jLoESG^t4K%p1Pe z>{_gknoTo&+L=9zK}6=VGX3q@u^2>q8e(R@jL@;OT?g+}R=Eva)@El}*H8KtSqr@* zevyJuKH;rXHz?f2t$bsPzzV0f{+Y29XT}m!(9x4)|6TLMxN-Z%9$)i5NQdU~CWiG% z)r(1}LB=B$`ufd5)VIARAs!W}WmY_*$$n1SK}9uHS50cYVC~B0#z{4e4K=Nf3RK6{ z8_Th0wBF-fjMj}F~p#Ob~eL%a-J+CXX?=M7AKc#RC~z7no+Ct5hZ z>pVz+IE};WV?^ILc*NnFE!=N_!%!k{THncQ z7UuWQ7H$`CctsDKj<-K9c&+cp^T1)~6*!IK>1n)%w{pFbID22NNwmCFaN6rJ;I?Ai zX}ftAZVo1R)clAAv~dsi#i3+6G6QSl-sms$9R`M%Hg0l(%tLg7``qB{aD(viL(NBY zqVK}PWuBoE+|#JwY965z+(~JfALs=4sgW3GXHkCN!?;?#?_2uLvhLe2$Ht#CZR5_t zxcg>H7g-zkHgGp(fx8+H$KEV(XJ9=4y)1CUFwWnV1@0SJ;?Bls%ntV~a4*N`HAZbxYO`Hdu|r`zM3WONW2#} zW})wjEOBpViL1qcBb#`C0^EnQNZ&-f&o9mbw-vZg#o)GD_hS&|1sY;-S6H}(;m;$$?ZnH*CxKii=zgG&0hecl#u3D7zVUR(azvgB%5M}VZkd7e z3|tN(HF1r=F+BC@u{U{st1)qHzzq=`--+mmn{VN+H1yG*jEduN z7`P*SSS;>U1DEaqx6i;G)dB7u12?h*oKxnfoAm`#;L0%{U$^c@E^xZO^yvVX2CfwT z)YrEI+zJE7=YlRS-d(`WfgkntCkQSM_o{&#;KO2Zh2^2XfgRvB0k;tTj2EwR%EiU| zn4xb_2e^J1glT<)JHV{~t`z=^_plCdy9^xf3mwzP_x3iFFs zCFSC9{R|vlmD3C0nH!0B;;z!Vt`9R53L5uOU%`4kw=#r3fk?qMW; zS`4mkZH;NJC*7I7o|2+zMa5~l75Nue&Yi_Qo!YsuOdE2Jvt_04qwV$Va&B`H@0N{7 z?@#x09(5lq>pQq6y}z_yS>FMmD?s~zZUxN;-36Kg-2Z`z>W*;vg{q^xWhJNqJEsv)?Ng)H4gP^6g6c3#XbslhPIe-)+R%3<=422ycH_u zL{2m4kp2G{wt@DAQt!^%RdKftmr|C6rYV~?BR9<2+b>Z@`#|5BwReDARqP!STn&?} zVH>tVQ_i~;7ltYDHC2msoMcUUQL2IIIYUV*uGxLKv#)2}?!))@&0RTLaXE@h)f085 zqyUy{uGxR{GuM~xsJP~3{La4SP1v*XttMs0woZj|5q|gGbNZ%MQ`7m90y928b~C=# zAig<>@2%_0x99qKyQpG&o?Nvb@0F2wb61}#aepGKxUZ79=X@w%#dOJk?!B;ldoPLg z)DQIzq!ruyT4}M%d$;I1uX*>kuD@XS5NCh+{ky-3tG}fC?SA5g{qDluZ>9TfYIeup z3x8Of%Ds2Ue&?Pa-TSzYDpjZiP^JCq1yw%g9_YFE@q2#cV^%0k5||bJ7B^E*d7t~n z4RP*)rW2QhxUCA81KierryxBy2I;}oUv?>955Bwl6{?tSw9-S=9)(H)wWr?^&1HM} z?A_J3U)^1O_u{!rP*3JveSb#FRYUfFrEJHXYxdsg z-^JW_=iEKZcs?fu&*z*SFQ-y9b1qBocS>LBJ7~q69dBtq=P!MGugFczQ5LiM)Tk@s za=+KN2jYT}8PqpE^8*y7fWMdR-7zcmy~`*)4E*Ou{NS3I*XJw$!M^`8_ zpReyQj-i%+AMwXCsr>iu9hRt2SBG0jKaF!P+nbuR<1df@<3}$){^pO$M$AD<_AX;g zvr_z>v*Vd-@@k$y{GlwT+2^+7dHz?k@3hvb!92qn)u8`tro9$v{|u%Aa#S92j%%Fh zo_oiz8ELS+DPqs%-U zW#iUoh-u5lU6moGg(r7)hM0Dq+%*~E$|cn>bmTVJ9%V%^cI2L$Aufi&Blo-vaS4nb zxs4g(DKLEGuFViL(tOWtvOUU+U;@c)&JY*F43fJpLtKLMUflCD#8Y6B%5BLIGt$1E z+iH7M6gmAow=F|l?DY5C^%>$4XMpE!$PiC)272zs3^5}u@Z3!ikEK=ftBaf?Ja==3 zxY!xtxgW_8mpDgy?v@NOhCQBpVTO3BbCl;^6cJZ0Jab;r;sxb1ozb4VHP)*Pt7P3v zGQ5gasIi`VX{=Y7bF}APmf=;RLXGp>kH&hHIpaO|V;NpkRH$P-cU!DinKQw2FVFCr zszM#>x!YsC%AARw`|%8~X)4qt&)pI0Rpw0g+$%D?j#HruJ@?93uQI2|b3c*cHC=@& z_S{d#dX+gPo_ke>*YPUU6wlom>s97V_1vp7yow4{uxXxqO}t;3bDZa1o9X9QkLjL! zUA$kJbG+w%D$~!eASZb4_3?gX&WWCTL&UEd4?v+);klpA5EnU>o_kY44|Z6zhdOcV{*Ob!y^IRr2xPV-FH>wh;aGL z>g8pXv#aLMubPi(3>Zl?eJbZypi@u$087I|#RFS=Uia|#(rppNDn(UIFgwt)eq9@^ zC(;nzV>%7aB+Rl%y8gHK({oQ+IQQ$3;3;mEAMPf8o70A+WUZ^}TdE~@?y$rQx(t%a zu0aq1%*?^}MV+2xeN)ZK#`+);%52@R#P9S;n#tPcrd18A7dLFKSC;FBC0@~IJ12Fl zD&aI=H!Sgoz_X>kp{c>o6TEVVC0+}>R<3VpZPOa_hb7(!e6&XG*=tzhzXH$JmfAC0 zYSwALKEo3G0>8TY);80#->}4=Bc42flNlH=Eb&(00gYN-Ff8#GQ(mUh*jB%efd&st zyz|UYE=;^QX?J;&QAK4NFwqS_u%(h^N4ARk=ZNV@IS`M^ircJ)>M-1)foU-Dj zNZI8on|wvnmbW=a=ds*NZx2EKA;S(Q^=m9Cz*xTLtSytuHiFg?2@T|T*d!UWj&sjFXI-;_S1 zsbN$4eKGvgh|&u;rF3dqFc}V?x~eF`!e)VwIur|?OXoRiXlSJ=EEtPvsAFDLW?lEl z@BnQK(?yk!CBDWPjZ?E-ci~E;$UIX0qKLp7=_j~Rlu&f$c1AVpvecD@)yJ${qJh>KGwb7B3oA=&eOu6|sA(rw7UtM>Kb(vObZKR2ODa2PkzofckHX?vy`yK?XaOby zpozT*!n2#6Br;_5Qa!<@{N+6BySp}xLEML2ZQ3NY$)DR4+dSBHOUDeS+(OKO6PlZX@#qeZMs@H(SQDN_r3AwvK^oBE1R0f)-!l+ z;-eR^ZbgJ~HSofSCLp$;_C-QvQ~Qj{$aUrhdoQb+=%zOPeT7w3PkExPwCfjYZ-86n?eZ5@On zGiod6{8RiK=s4f#?%K))*@s+hH$=#&5@c2 zfpqs4va@={S7xIDn@Bb+mhg>ldep-ocF&0lgTW4$0U26Ur?WOHQxEKgS{9uS->StK zlNgt4AA2#*4(*XK2lh$$q^`z~zw7598wkA?$;ffq@XH-NJ-Ww+oca>P0thW#-bMp_ z!#(#k-?ZKJ@C%bQ_@E{03YrEz>5roqdhX~CR>~gpKBy`CT}H~-O?(jU=5JCcv&CKza?c%W8hO+YXs?5owx3{Gzc+L9 z=C?+iT#SX$!#-H4d&5uNHl*&<(}L7}28A2eyMtGDm(x1y%+0sHHDbwWOTy&+B9grG z4%)4~gUL%I`zP}HUgY(@DA8jOEDc|j=;@PupY-yH>F0ULT^DakzUd^elr`BG|2_8t zzh2xC$y(k)%i3;sE61)$<|jtF8}7K{sXLDG@+MBha{6QZbpBSQ^I80|``h1b>0E;t zovs?ay&pD8MUtI^kREbSano2z&yRZB};p^B`d!RZvxi0Bg zf1o-zDJVKNAE*va*NBcp1(b{i|6c9j@}*hp_{;(7;JcBpV?$ymbYRhIRT^)HzLmsG zqoTfT!Wlzp_7gz?|KQjn^*Xbl`hMBA{C7M<59Ho=s|D9X(JF1X=cya4#2(i8idtdq5m;eWs&WHXnQYAqjk4zZMp=7Cjk5Ogjk5OEMp^rO zFpRQtNTS_vTwo>^&YyVX6^9$zb%j5N0NTarXZNmMoIks6?c)4rXiv~Me|@fa6+Bt<9biBa+{KeT`g- zr;!=|h{9I+Dq4pvWB1hs65I7#-7e$62^?4_K6hBZ$QNf%dl^hiS z`E4)?48ClIAbx_0f`ShSVNr87JqpsZy^OKDY_uN1$lwx*gjz73R-DgsONDl{;mWV0 zy+lBMruGD-%~tNx4E=MQb0YqpI!7|}_nZw8|CDnDc(o@3lr~j4dCIS}bmVUU9ilj& z=YtU9eVeKwA8%82a1cIM*;M8Ipi3ljoo|8aJd^)E_)uS-vZ;C)!Em&>`V6RU49Nc) zJU_(Ik$(v^44481k$)TXSjGALySNU^t0zvU@a_E(LYu6;z=!v* zr!x?IVGzEjGYov0!5;;FiNW&>|9XR;41SZrPXm9Y!Jh>FI)kqOALg%@a~k;Ye)Vz| zfe+KyOPy&RmTxa-1^g!m`g$q5Y@aarCiw3(`1Rnma}&Lt3&HENh{=D<@TW~$o(-&B z67~DD5kBdBJ;LWWPe*vq`D27nIeB=jwWCd1HkR5YQD2Ua@OcjH(`lE){aqd5dpcVp zd@tv^2;bYeJ;L|3_Y{6LE@u=qh1KiJ|Av-lwvKh)xfIrm4>f4IdDxA-G0 zeuTvzY4K@`Kg!}qTKp)BA8qktEPkxTAMHFG$(ODWaoF0^p{%x zr#OF%_|LTXGK(*__zH`!wD?&TKilHxSbUYmpK9@^Isb^Hcdo_Hv-tTIzrf-bTKwr2 zzsTYjTYR;}pJDM!oZc9*&~X4uo3v@+*$2|*?G)jOp^e*E#eRxOu1_+LQBXKM*h8x#OIL1R9#~cjDc*t{%L0;#phsbsLXt~NS@H$@; z1UFH_PbaN^aP<8c&4bg#t{y1y%V4 zRknaZo2UnrwvI_JF!iDERQW9weW)KwAE>&Yph_>OvMCIz^nhMUeW0`_PI|r2n@#=a zivH6@KkA**5BeeA7tk7^8yFt^$An%d^md_l3;iN!P#))r{zal6^;zi$rCpySsEP-4 z8^eQsO6VOzzasP@p^t(F`Wr?6V$qN1MCk`r`azX`&{Bp6T_Cht=-H+|Jn*W#t3@B4 zH>D3$)qhY`|3PVgD+$W&KBUWp@`arI4xyhD`k>Iqg}x~C??P##oZ%)3EfIP=XprA# zv8jB9KOvHAavWt77jk727jk727xLerT}nc}j}-E^NFhHi*Oyn3LauD!LcT%d+eLmQ zDdczO`}l8=0{2(o-bzc_Lpf@>-E!Ao43jewD~?7x`C3 z{&kT*EAm%G{-(&^6?wnje!K;wD2J(}NY8AMpC$1RdS?LQKU~%q)SnxM^U6h zQN*t(;#G8(P{gBn=tpzFgX(YajumZ&iH+%0{kD4&eE zT6#@YUKw+<^zuy>e=uz)&n@;XFqilim`i*M%q6}B<`UlmbBS+(xx}}?T;gY^#LrKO zZ^yYrX;Frlkz>%}s99WVW?d|)W|Y1y54Ou{qp}E*QTkz^jM5Li?3r-e$DjGOrNKN7PfSGLq|aKsdA#857*scLy(k<||rSYr)W z4hOjjMd4!N@NAmUSEoIc_{9|RsvJVrpUYQ8VB9hDn@U(b(dW*VAM$rTavKkz8f0E9)_GwRSlQwYtr2HFhcSM}9f|m6K93Ra%x5y$@^w{4Z}hnf)XG*k972>yJ3yf8sSD1BdQ5 za2m(&6{fz;;Kv52us_C-B7)o14sL;k`+hsPb1mGP;4w@IoKD}zATiT763nRqDoo#P z7LF%#VR#rgt?#QA?pN^G6re(VPg*#B+qg0Y_d5&s8{kgRk%=FJy<_2qo|8(#Cybgv{M^g8M_-w|!^9GW1OyC37tn(2n+SAqyPsq~4ST z?jKp=Za_nljlLo@2D`F|_ou+!oCR(z-g$1#0@oAoLfPPU1IISUc6K?>!MoJ2Z4h`H zH|hk;!DNB^5pZmCY*%5`g9q@AhS#mYp}A4c#=Vs#ZaO}KWTS6Ombg7x;&M*PF5Wp= z;;zgR_f(d+0=%gRxYvNgkR!v{xc;-kwOA(D#+?Y<1QQ_FHf~jxxT~{__hI11W)bg;z>UuW zmybEaFV!qY>XP7iTy7H*A!%cn9p;yz*Fb^$j8a+V)H2`NY1T^8;k;MPG- zTrY+4^?e68RPIsPAb@-xS~|r@r9=jKj?^a7T22t1xgQI>5~}a7T84 zt2S`y4sgp1+)*9i>I~e-4seYIZd3=jHUl@h1Kbt^r=Rz@a{j1+8*AwMops-?1Wwl% zd{R=5`fS`Cz?DMI``ZtHbaA+sfkV|-xc&+ikDIbM#0}^G_fZ2kumjvP2Ckq3-012s z-a#GU+JIXDf94lc1j@zb_Zb6sSO>T%XN3A#-gI&Lt^-b&-%uYGi+dTkUGQi6h8eg& zTle>)OR&BN4JmPb3|tOm=5zhTS^j+`Zd?br=MCKW4sdT8IK28R$Nbvy{-1%<{cs$v z*V$qE_^psG4maGuVJbnnINY%YZc+!h83se`9pLUWa2V1m$8xdL_lSY3>;U(Kft%Fi{>yz|HRfS7G2d zH%-TM*y)>V;Mg9~#o?+A9EKFi#o?A2ICK&1;_3_>n)G&YjRp=)aJ#rR1BWKFUECG} zhbA+?&A@%bxG@+HeH6H1;%}1qz~R4>7U8YHT||N5Ff?_RSh(TK(J#c{>T7G(nTESN zv)es=O5yaha-G}lPD=)~-R=okQR>_6M%NSA?M^TB?RJ-f_Njq=V9%(T!IM3d8rg{}~oorSItpJ4!KT$mKoLRT1~a|>M|wlfP|Au>ou zXBN7`APv5SE{;W{>`bd!Audp@0<>#2D+rK$Z&tIyaPP%xRuC$u6RTMvFvv$IRMflcp|ic#qqE}O?zAcG$$yP+BG$>*_f+lS0zMOo!6*3M7Fk= zSL&hzb!rcm*(`p54woi%YBr1Kh;?6Sv&2Uoilv^5VpJWYxpYhCw!nQ_*ZmAk7gax1 z!`C?fnT;u&kxZvrgx|dtfm3^j+~c=UR|G8Ms*DVhSjfyW%uT3TkOAn*s!;2k7;|v7 z*e=oIyx22-*V4L)MtB+Zm#-Vf(W{(JP92V)55z&GHzFB182qadvyI{1fa!xje&>iJR!=XTX8Z$`ftrmYZ3JNb6c-RGz41tcKH z`2~}K^mNbZc43)y(KDb{_`;H)a;lg|;$F$?#D}qB3Vevdpp4GKU`5IVq6F8o)q372qOd|aG zfiL+SXKRE{S$q$R&yB1vg%xy*&$sxV7T?QZSE5}K=YvG~KF*!m6EvCV>wG1`dzODc zi|_C3iQorX{sWvJMf?jaevtF4i2q=VKg@Yu{8{$~pgheR%>DK3#|uFD9ooYr8awg= zd<6BoB!55lrI01@=B6k<_;9W*S>UhrN#cVL&sgE1ElQ3LUFXst9|D^sT#Hb(4-|S< z08f2M#t*8_MA6~#0ZfJOC*cvF3J+StaG>=}TOag2i42BbvBxbdjT0U&-~JGTi=^sNBy=oo!A z?sDMRKiQ7sRCKHBwEQc;m1xGGKg6|uRw#ZII10vt=rwih*M5q>Jp5_*D*8io(GI$2 zHO8bIU8VEi_`{d6=-U~Q}r#_BR>B!r-0t44mp?ur`OW$zdbozAL zM13}H3UH;6GhVh)baA*g;136U= z+_44@kDhYGaZidF?+gQnB(#g0Yv3>>4{&E%`j!F5c$hv6`IRGY(@4{dM|4tijOavmR7Fw zH4%@n0O0hRi2k^Pqrm%ZV2=4&oJm#fL!!ga;sMO<j@emoLqqEQAVUUhLi-)*CwR{#I6XtNkocr&6a&iCD(h!9KI{8o?0t3zZ zL-jGC>M5Ih*3~wAb7-dO&ORNtqrbCH$6>I}J{^b1PCp%oQ0vq2@pzh~V!K^5d#j$+ zT9hb;0Bf4p)=yr)vT1#5eaqywhRH4U>zZ39*A^ER7H+I*sTY1#@${18Hr0V^tgmUU zU%u|V)syR58aC9oG&Zc9tbIet!TMUu8MGXA24Ku&I~oSJQ-Iqaua^A|J3Mzx?iHo% z=-hD9G~rK=CiV2F<5X9rtLH5)DK0E$fu(1cq{}ClPneJ{$48#k^-bwBni@8xHxw67 znl`Cu(%kCB@K|>Nj6<$zOOLA^pDsH7_-PZ13yY?wtLrz_w5F??aHzuiwe?MHysm9- zS=ZcB(^g;C$rL1p1Ws-7^i4G@8yuINY07G#nGO7DXU{)!zK}Y!4`!P6|24{*0m>0 ztE*T(0Cti72vOKGo+$L>vU~;0>0V9p29}@0^7C1KBg^k)`GYK{?`TN>Yb^f-%Rggz zGWs`^Z#q%vKb9!)GgwY*9Fv^B(I$B#%Uf8!o#kTPJ?OcS<+K(s;eSLF@@H6%Y-0r) zKiPWfn$1hgm#Ps2x#~--g+zK-LdL5kp+N+%Mp})ehvi1fOK9bhs^-S2m5mLRScilb z;Lxphc{YGj)K=59ys34Kl^bd4lJ-`ybV*x1AH}L5Q%-eBf8^5?rc2`ds=B7jR~=I% z;eLVhVFv1J>Nr~eRa`d)Fk;{q;`%zqzz`e3pRVuB7&v<7(Q#h|jvigiVB&58j;>!b zsPP0P{~mA+iqU8xj!{JCxoRBzG*gRLho|8{udZ_7Zi5Vur_S>Y_5bPihjZcdlRpIx zmw+eWQWCpzdgMq%?NJ*3V2=od+m1gSHxjrDP*H?a_7LtG{2?nR-|KP0{rczM1djAa z@JHd>z%7%9&M%#Z2k@uk==%SjgOCS=t8Ll5$+v%=9f@R!ez^V{iDb{7K1+7cd+wjt zY?b+_{`vRNvIh3&UOTQcbmeicbiMG8?%e0Pt}XntwRv=BL-$3PQ_M4(bL5QXshF{B z<>n1MfoNXdz~hMK=M5Z3v>BQn)GJr7}QZdYcg@`Q%F$0@1)J&Q7z|ri#gqC`-{#k^pr9+RpnB+J6IV)$)8xYAgy@v z6RS#+lACed?}=5#0dQeEPn@&BuybQ~$&|g%+c(yA?|E*) zl%lIn@BV4`M#OZzxcB*@-N9WX@49v;YAPI+_ck~00cSujSrC8)MLP<@dC7ZszHnZ+ zSsizscL{W)>@Pldfye$|rYZXu49Fqd2IQs|ja{_c-eoTzv7t!lS+qNNQ}@k#r!3mN zv72b|?z-;1J1V-nUb^cBiRe0SaC1R;(G<$H7-)*$*ewy#mag-52rqH#IV|SV&k%Fz z^LBR8JbHLW{s83}{q`5_DHyx!-Qe5BR>|arlNU{vej?MAigf9LBIMY$JFq<5K;>92 zq-iWAd_QsApMEdyT2~N$W<5z|x`J@mI^t3UhEhH7c9(V6Sed44_gy=?uHHL^&duHd zdmqOtn49Il%YU0Hyq_!+nuP@;>g2I~W7ia!0_$fwDQxQjpeZ*>HN073gR8o1(j6PA zN;r2z(N0)rlZFT0x8AZgU-4U9X`6?>U1F8&wr|$86z#nHx0K($p!MFfz$oOxD5SMn zBHsyE@9of#i>&|czLaaJYq!0;q^I0>lw4)svS+|usHMG+k4Cx4+I<$))aAd$tEuz)mzqVn#D-1wRO>f+k@TzOkwQ7q*@H zfT!aRT~7MlGyj{7Z`bdtkAM+FzSM8BE9u7$d^3=~V(p6j^3saJvek?8OBYoXl&q>i z4>T0m;~SNQ`CkEg^Pd9+oWtFZ9@)L}{_D3yAaZg@Ua_?;zr9iEEokU$sHttmL-gGN zWsz9DiFN$`p3@h6wZT8Kx+;A5U*uAXw$*XQ5;=*J!tQ-o#Z z4V!B7FoKld+|kr7zI6%)A6G@P{((|(F>g&t`q8!l{Z91g2z1M0HnByeOY_BfC@DZ; z>0AVx{bJ};1Y7)KrsJJt@GQTW*;K4nzZk6cl@toL`9)#XTI|Q%?iV$4x)lxuJN%+D zvu0b#p&%OMd2ad7{W$IDscX}I?J2*k!~DkP>N6cT32s(ZCC2Z$`m(S8eE99Je5Ic! zd7wW$8eVdNw4!)Lesl$1=pQGl@FM>>QHdA($IYZ_-0mMYo9gi^{&ATZRFjv)h|Hq8 zyfjASbgE2r0#0@-^QMPxX>a?+Eth#}Lslj#!CRe|sj3sNdAT}|9JXWR2i1GldlcAT zM-HgY0d~6Qs>@%xxGZ;hVMQ)E$C#5fLHu|`dPTs!SFQTX8ve4SBZVlm5rIdi2<!A+Ti~7&fbGsBK-^(caQQjW>HzKpACS>#EBQ z&nUeud%I{O9yVCa=xfv%xTmR95!=Pp@LNY~7+sOZwAtI2o178OxkvY?o*q}@?5 z1xSt8g-)SNVA5xYw*{L$1&8SQe+CxLB^XRdK9uyBACKh$lZ;{NBpHc@)_X z$&2NzD1+dke4<&-)owFt}C~!aCA*?oT^1hQIs%eG5G4!(#y$U1Rr)|8k+DPv3*6u#-_?f5gi^A zd?cj4@C&w~d)#=Y%qwtg%9!AzZc-Z6L?k*xq&96#@OvTE#}2kv<+rzr#uQQMV}jog zseUO%If?p>3H~6YdRvI04uMkGe@yVPkm@{ms&_)_%SHEBJaCk!dZZW0f|Ox3{7r4} zo5w?{D#bf6_M7uoWdH5_y8qoi37+CS2@F(P(@3rURdBzw;N1Hjdg4x!JMd6MX^Ax( z!h!aWI~&4*rS>oz!UZNa8^XmqFZ9({$rDi$t_yuOgqx!0*$^(ar`ZrL(y^nb*${4$ z__HBgoTEDaA^}c<6n&9^P_9~e0IOp-HFMUidq4anZ|8q_PJ4>GNI*FEv7y0_ul(%u zg<^d{u1|gLg_B!q4|6YEpi>St_kvzQvFatS9yfN;zAN7F8YBxM7YPXEf1`51o3nqH zzfUj7_viim&77y2CV11iiv)y=lxFdv3+JZK^l)kb<%J4II48ohhxO43&&aB>)^RwIaNcl6Z=9C*lGjeu5eWzD_y z<*|5iMI$wMk9L^NRtX;9+5$(S$KH3fO*KC7aIE#Qs74-hqwoD_I8Pq}Q02Dm?6 z^^z~5w^QBTh)-*Om?YL3sNvy2)vdud<>#BSkhnC(wwZnF9yDHc*jGVvaK)vJ=q6MtC{t!xJ@d=twVOcBtyrsaqvBS?5XhOL-%V;M&Bi9(8r$B|q zM8j|_Oz%2Gzp(ET6xB4~XQ{5E?-~?dNGQsYgD97_2t_*B@L>Glla@YrtTD*-uxn#( z(i}_Ne9BsD+o~%Y*{`U~w!OshD+AKIZgsl9TeUbAs)uFUKD{1OSy!~w*4DW8tH)(u z$BR}1*tR%YqJ5L@aGG!S1Ir7f%f&cn`kXvT4jo1qwqqpGHY z+x8UcJkd8+f$LrGnVTH@##t+e4AoGfZ!0Elp9V0xq4K+l%31b(-#eo(3J*JH(|c!b zBSkJIzh<`A$nkFYm=@i;u2q-f>sl?;hKe~4@jGTdxWpWbzH7lch5v5F{_o$~*ug5F zR;;YHwV_$w{bU1nw&Pst$$%lf>tJ7r;b6kNL_Ev~n3#*nwrdcYwZ0u>pp}dcyS8g6 zs!`o2#aVM^XsoEOtZCltOa!3Inrgtd|LHhf+yuSrev?w|cH1tiLUU%RL4Dg^SB=>v zJRv|$MZwcSqngd2=0Et|O}DkyZft1743(vIb!e#_t-zk+qZZ<`{q$~a+uBr3eFs*f zJ^yY|_~@w3ZKAe)(nVhreh(fr$H=no>+@!J9CAJEu89Y=X4mWDc%$4=E2^3bZrkmt z{@0Gg_3jmLO{%>m;VXa~xaUUsATEJu#fdrWF`^dfgR;JD#B-4EVdt=KXbx-4k&>*a zY%02Kzm%q2)*sosPWzWMyVJ*MX=GW>=CW?(>0fBJo5lPtOU;wA1KT@l#UvOtb>;w@ z@v~J6Umo4WZ}l+&>bDp+B<9@nMSb^uC-?~Dd)PU*-U;^37@}IHBGbalG}|0^Z7-lV zeYqN6xt{Ik%AU2M)$AufPd&HR7aHwi#sj<F=VIGXjlzSf zo15wyHg>eu%DGdbj;X|9yTCWTcO9(Wwp)EXjHWzQHuAhKH6aTQw$0NShT!a2$Sq>t znV89@=8^!uxxK2awFX@meQ2PwdQ(fTA?tuFPnSizEPa8j4UW^;rp6vgY@Aox)H#qk zaY-BR9O!#)Cr&-_axYB`+0jH9!kCN6S)Y^3bdR`mqfr~~}F7_B`+ zXeCvrZ2npUPUen%8hiT(r zPn2isO)N==#ErNK2UVB1#ToKfFOdx;EN`B=z)GmKT4Y}+-A zy!{Z?*cAg{*vWo1c8CqTj|`(zd7gPH$*_Tk&c|LK1jA0*6SDv0XV@V;m473{sK&NQ z!|w20m4~p!=pIZp))q>gJ#OT*apOXviG?9MFlwkY^G1)Ehp_%W8v--W{6l#t^~~$B z$D_3FCXaQ8uo7Px4(m?pJTW7bI`>Z@`&-hyt3Bq8?7OR?8W|%vH!Rv7XYB_e`(OZ$En6|MjlvWc;U84B)Wueqy`ub(3 zQT(z~gK6uRof@*&$_jW}RKPFr+jrd=y)V%>JtncA$${<G-M`qwBlQE(t<{%m-oX8 z@ore59XaV&=k!Noj^!Xm22)BRX!CbmXj=!p8&=5KX{#4>_hfZ2Ww5<7XA~Yf|8HgZ zcRr{?azf=3fx+0cZ_tRr_7Hn$y0gk|aH?$&r8*yC&q<$~KCefw`uF(}s}mpY^>*+( z;vJ~RxjDsbZDRPGw)b8LFKILu-%SMjV@2Mq^w}e&TT`o;Bt@$<6%IwaxrsNk5H+CH>{%)dSSx)dRmAd;3uzPX+O* zhhXH(H9DmJn+ksM)HhSXFJ8Yt`o+u7TBHWQc@e2Cpa*g`Ru^( z&c%GULP}{#1Zf3*Y^0-&S5gFaO{T9u9I*fE9!fx8PfP7I<=;sVZHsuRMJXmYDNO6N zS;Yi&4W}sxeyX)eq_Z5YG^0`n$9+*m`M5=(iD$8s$~Q-pA_IT2&@}T$PvQTLhtf=R z(wL?3zU(LL@eY>Wj63@MUh94ln`y$&oM5hHPkUvO=_=4(nRCF*U;*(oPh_^n7xFQY z0M@!+4~m|w2*mSH0rMg2Y#hl?ZV4Z zr#+h2j zEB*}}U!n28!ST%+{{fDFr15{mG3_y_(tnQQe`tI+j%klj6(8nf;%)48N-w)k7qOB* zLW`%p8pe3|fOWEm4_f6OKFMnJ@FD9;45Yp>4c(0and4>tHA20zr`hZ+2EgFnLHM;QD_gCAw^qYeH@ zgCAq?M;ZKB>v>Q4jyCv+!5?Gr;|%^-gCB436Ab=1gFoKjCmQ@DgFnIGCmZ~U20z96 zxu?8S4St%zXBd2@!DktKw!u#~_!$O2)8JICUGWe4X z{uG0sZ}2$=pKI`W2A^;61qNSe@I?l{z~GCmZcq6Z8u2Aon%iB+vbBp0zSQ6s8~hT3 zUuy7W2EWYUmmB;FgD*Gul?K1c;8$CtJmpzq@M{hJRD(aw;MW=adV@dR;42J%gTYrC ze3ijh8+?s5iOWNM{UNx&ouZYG?nA`}znXb^b{K-ax#{!|!;hF*%B#))%K;^OWJy5yI7kySMG)Qyw6qcsI4MQa?C3>yg&xj~ZZzD=m+KAFLHlj3jjVMi18-`41I@&N) z7EM1Jh7J-f%sLE!UeeL}_BzFg)CCWlB@Dh^Kj2L}{`W z(HofF#gyhok(?$#5v5s9L}@A$QJSwrlqMw+rI|-W|A#5fAtIh83K9J)Q*r>}>7kG) z^=F788bR*)v>ivmOy2uEizzDbB9c#MI)mvFA_64R40 zeoOiqcyFo2ytnKbEI*UwOL$Lo*we~()xlV@kNUDiM+GE38k9Dw5_%gsJx+KNr9(MH zdQj>k6Tg8ez5gVh_HJ_0Z{qZ2oF3&D=|QPa9R#IwOmse_2VKH+1=F>uY9x%UK`JhtLNq^ni-`0UbwrKr@-nWJ-Ic zJLPR*eJfZW&a2P|D#{6ZCfNxp$_Gl*(23v3l=fP8^qs}}%2^-$L+ArNo%Dc;a)XNc z0~PfLD)fVT>JN!U{jFqu@H3$gROkT}~I z57bkCn_1tftPj_-&<856E6^I!2YLh91G8 z=^m!fGJT8bKbannn-A$-#c%jup*a^VNS3qJs!7H1~;H;6*Mmng~Ue36_e$%#TP{15VXSpGiC z#rc4o`r?HDGg07=p?Zcqn<(V7h(i7&mcPpKpR+ub>KFJUi2^Uq5AYkP{vfCQ$w}Tx z6!N=S{us-jWO)+RBk)HM1%5P9;8(D`mgNmB|2@mQSx)67=qV-&J*6!F2%Qv? z?Xx!i9%k+@>f~@F3W$%@}cO=5q<(u;3pA9zFFwUki38>Z62viy3M-_7#- zS^gr+-(vYYEdLA3QwPd?`x8aJlZe8ec`TpL@=BJsv3xVjuVeXMmfy$nXITDomj8<7 z|6ut5^gF4%Lx>{Z=_^C*wtOPEJ_1iz4Zlt=K3 zm`8a8U&_2z9wA3L1cm*A!frufub{9~&?2U=OYpEqP}m_T@)s2O3X1$})LV=|dyy_I zS(??laYeirR#C5}#^;YO&9vw@%UO%Td?7`#*-otS0*WH1%SithP6U|Yq&9Sm7fghh z=^(ThN)$26iBL)T1rkNhb|T}xFe2z2QAlj5LQJMCa;95mZ+iLGNFcLig6WdXki@mt z|J{*DIZI+^OCs~nlKE$Gm1l{#ESX1^%p*(Yku_7sNiEnNhjeC1E!k2_w$y?RcPK7f zXenADPbX-W+E2ElRMoMQBdp zjWC?T8|gi%#)oO~pz{2C5&mb|i}Ah{)Z)yyfKwr8YoAM7={7WNv^+cT%H4Py8=7jB zybjCgJB)YBU(YVVwEr)w!pi$i8*8yyuhiCp-OZt+OA^mZ;19t)J zFs{I9b6k+h1 z(DQv3{CEfD_Rr8Y_uxJPk8Y&!S_c zZwSUQ=ovxK<^v zISyl@36!I3QeyV)oy=pNJ>=VOD&C>s9Gk(cmk6FI#Tc&vG;u%0v!xij?E!Z`o+-tc zY!A4>c$O4nh6e6w!(Xn*ap&UbP!l&e*RpQW0eo!Y?g#GX1aJ%UFh-mJ?l%eIw&B?} z5q-na7$kzbKS3Prke7(Qw}AU*0_DB5$g*xt05<{8>R(R)*9F}53ESH_Y?9 z9%BN(_0dQ3tMudr7&AZ>Iw6UVOx%tHaW5o@8-y{6MDi_95O;loxHl5SMKE@fhOkG2af?a%|W>bChkMvPIaT5BNJD+1n+X4Sogrh z-40y68|@sKxYVVI;m%4B_lpE^xn+svyEj4H;AM&F+nONme-gx%po4mbQ@iegSrH%X-RH;~afp_|<;{*Wkpu2cH?Z;&RK1xY5p$iK|Z#wGBjLR!`*1$iZvV_Aw?j4Pa3!l z8jj*A5T$1g-M%dvPRR+k-@xtCaA~9rfpAk$$toSm_Gq|t5+D$6g@Jog!}Sv=i95%@ zy{_TvMe;nr!m zV>QDILzN+EW^OPU%W(}7?nIib%?$vOr-{FUQOv9=Bx*zTZ4X5s}ez-R@ zoVx$};XcxEGh{J*%kd8lH!}{dU$a}!v*O^!Xt>#Na3^ZGIdO0&X}Gx>u0MQ3zt5Cv zI1D9-K=oqc)@e9A(#OO#YB)Sv$HZ;Za7*IgzN+Dt#=+gJ;i&zf;8%`&HQX`@^Tj=; z;g-k2y`bUnXefeTzHex_@;JDUG#nlsV(R;chC`P-CazzL>woCdI=G182V;OEyQw`` zBVmF!apN`I+BmoqHJln>A^oPl=^E~|IQmY~aB3XJPhWwCTOUVXsfNR}F%kUqm20?) zIJk8hZbKYgjfSg?gKN}q=vs>4XJ5O9tB!-)rs2?4aP&=wAB432>2~1M{f}XS6aj}@ zh|?Fn6}U~1=>fMVYl(qN?|?t~;A+pRZJF9!b;h)a44JcLWoKl~%E-)$L^6a(|BXa4 zGiGE+$%eG^3rmY=ku()->pwit+yxOCGhJ9a5$_#mS%Lj|V|M0He7wr#Q;r#{Y=5Nazo6`wR%flP2D=lkIfVhGqtwG@i z;^zuJZ|B1Br(+AQ%74Lnvip|3&lg@dB9NE7cW2iNRz~4-dv`E*9^x|!uN}s5-7irb zbLU-x9Fu%zdH}mnx?)?Q?%mtPkbAI;%Eha~cd7`^mi-~A4|J}VE zR?wJfJ-(UVWYyxR!>YpfEFD%GxK{A(82Orpqgp)HHbXiMU&Lo&#wGpRY*mUFZ+so% zXXCkdmbJyI;k1oNUnz7}K+l=hM#yWBwgK;(DW66hRY7K^^~2O!X9;Vjif{9eh5gdi zlHMJ6@gw(5eDS>qL{u!{AED0Xh8nq$1H%Tdx$_r4yJ+?n4=h;K+}wx{u*LH~10U&l z{mO?{uDja{qy^qSqsfyZMZ9t56c=2uyK(&0 zOFs9e*i5=B+AXXeaGd3o?%v_uXJ_75_K+9bR^Qy(PHQYpbCKnb{bbIsmfT+LMLKqH zl4S7;pAEU;v&(~%PknH;H%SBb5{7CTvSD1!kcUPcz2WVDdU1|wksw)&wQz#Rh6X>r z^0UtudJ+UGDmnnooQXn?Ny=49#aIrfQ(HKB(>bYzhjNu>u|@}{>MVZXo)=dPUgSv? zY;49oS_a6z)OL_zYER=pr< zqbzSaDu_rmJXEAKTl9#@1(|+!dQEl1b4b@$`_)s-G+`c;T*x-uQr?!<~yZSzUTbq(-;on9Dmq4X#OlmE;cG zjwmhqIZp6$q>tFxmfqTAL)`b|jk>q8sIG3CR#02jv9Y2sH?IWWSw_kiugK2I$j{2a zEp$P4B!61|CkUGS>r(7*e!1w@8uWj|~o2BS!*r8t3fV&j^!vU;Ce_Y7^vs{V&29I6C`pz!d zEp+Y5f?3s1eS67{KQ0Q{A4%ix_ZZhl>-STona2GZ>*R;d`XH1#|MpPmavx$}DlMkB z8cEhL{Q4|xPeSqVd7$gLQ|CsmalLKjfvl4~66sW+8=};)W%I%6pw@}k>ki~X37(Nl zB50%K^2X6i8;eC<(@z>Te^e6<=K+3zDlWqzZoV%H%i317q#o}O`AzcoDRU8j2QO>26N2TyGY1>$L- zM9s^fH9a%H52r{3;%9=o@k!!a5H~)_%0s*w@1`|Ai@}e>9|hv+-PG}dlYBXjX?%?W z#nU^B>4KAd6^>8Rc)X6aay1^q=1#CN5VghOFuoqJ#rhda6h!&1Q4DAh<@uI}PqKdE z;X|G^LTL@hH$3s)HAI7fR3kpkdf$UjH~4-A-{0T|82mu%Q;)tu20z%~htTc73BkZn zXFX051~CfijUQ(4!wvojYm7(VNF#oPb-X8jl);ZS_#>^E9{d=CKg!_8I_rnhbvp$9 zvQA4+Yp&5cLKNt_AA<8sEdk9PO92fH;x*Rb)HoD8J$(!V9}6ed$+fjE0yc=rAc7*H zptyKwuq-%^*VKXYi|=;Om&4njVk<#f(SzKZ4bEN^7_B`m+5ImfuJe@_SkSAj|2S zHIl!>^7mPuLiGaqXrjn>EK%eu*6xBlpXCc!UQHBonmb7Ntt`KZ<+Kbn$;J7Do}aS( zH!OdTDCFHN9~_kU;Y1;yNfi2vSzgNW4J>bEc_+&+XZbBGzn$ejVEIp2{!^BJz;c=k zLw3?dMEMRUihRY|O^{D!InB!o9?ffZz|RFAVIKY|_+yxdp9w$34W6!5x=sWSClfsI zf*-}ahF3ThkJA$?&>9!Z&uVSoe8!6CK|itNf?Om)E{7m~<&p|=MFqK_f?Q8QE~gM< zO$edNT}?rJxUAMYF#8z%RWpgBhLyZ=-af>kTL6Gf^_t@jR>$Zb^}Dgxc3ALC;pN?wa&rJLj<5s`~_&J1LWj$4a@`+e7I;(m+@5d8o{ zp^1A1lh4F`y$9T7{VYq|uMOOJhJ6JC{l6nMaX$u*?$c&4aTRE+Z!tmOO&qOT_3Z?3 z_v7K^7$4kD$n<)C8Mp!sr%sKDqjg^s!L5mbyUxh>X5iHGjF!D+;+_X?oetn*6L&oB zbJTw{gNgfEg1El}rZa1kV==Vj#&aB=JR z_`@aZgg4NiL03uCA>bmU;I}_2S;r-zp984CDPJbs6yVULoG%jMXAE$9I+7Fa6hq%c z;7A_9ADRXc{BRi>PCfVg;bv>N0h+!gM!q?~sd7*oPl5EAxHZ7#Kpw###Z&OZT@TzE z#6|F@%I$~y7`QUVrGZi)9Ia=o(vd6&&uxGfq^ zjl1~ac4#;>4I&Wk0wdq+H5`f*6Sqghp-3@tk7_u5{ynW9s@Kc2z>z%>{NYdp;!WJk z8jeP)Dfr=D*KlJcOyItWd_$T)zXhDKpJ9T~UL%#OZ33k;e=^&D{$zIctjw7a3O&!C?5dGgsri%tWj!P2Plm3vKF5Nt5AWTB8Iv1q z&x}c$Uy1m?$BIwd@6M-8-Vo`=xXYFB-cCGa?jE>2xgpYhq9YmCnYYuP6kL^`(sjo@ zBfCGo`}upG>l!<{lV&J-=Sh;LQ?+yj$KO2}>Fm8n%v*J8w>X*-ys@tP^zOYoA^|Zk zGkn)&_dIv^^WPlH{L@OW*FN|$+c&OrJg3|{a({RJ19y#O{wbM~N-pP#k~Lq~(qV3? zO?ldZuIpd8VRR?WEcK!v_d$1sDIY3tH2zmU_&`kUSclyygR+IR|1*a65djyUx08?` zcc+ypOUyI4+Ck^EN0iv7js>U!?Gr&EQja64qPs0 z+~&#|x8Y&?1ZrRKwLF2h_erY%=C9K^c`UUj|JmByAZEL|=R)Rpk)hvW{TA!@o)4Mk zKRJyBYse~P3t|7Y=F-+-<}J<3t;fW)Kxp`)A=#_B@hKm~w0N)e}MwM7}n z=#G{5ILmt!9!~qPx~a~q}cQxB)soA?UsWD23y{;(?|F?5|Azxn5Xudk>Q8g_Bf7356bS-991)w*|y7F-}6Fx+5PHbyI&PdwbVmDruDZtPs!?eI;J;zk^;3Y zI&BQ^q?S(ePI|u)rtc#0Dy{F`kw(D}J9ng|njLra4lYnNQ<-i19M>JakY0Aj%VWEv z>q2U@B&PdCLt}WGPg@wq+X#eteeZ1}knLgTZKpWiR@+pG@1o0EYwK#;tLsH2Q;BW+ zM)oxW(952-SALTjb>H=Msu=ErvgwT#y_^gmAxd^~-@6aJnmz2?C&zIgwZ(_-KU8Gf zew6*kMD(%){kWGLh%O4tn$hGMW>p8O7`PAF&^oi@>vzTqRUG|0Fv}BtzweMYreD<)rY0*am zvWG3(91Jgs7KaLJ+d~3oTrambqybKiT+ame>!(PAD7`M8_ZI|MVyjq`L(Xdsc(L_G?* zQQpCAnh(us^#1WoQ|vsp&oN`@=5`W&CkGkcF3riMKzjVa4L36C#q~2?Tx>#X3x%$k$_r$}p zH{0ZR;^xXTYl~W&H9`Y-^<}#ce$Ql+gK4NBV_+FjCCAr`^#h4pS*_M;M5o`$aBOY ztg-*3g_l#i{QDt0 z;%D2TJgGMZVcW?cPTU*goE}Qs9%b8}_!8RovoCSIeflM?x7|t7->!DfskebUl-KDi zWZQzLzBT?m=R&>B)4=uR#ZZl$5opyG{Mx~}ux-V@51u;X!ZXUs8_QO%3fXhRSc1m3 zy^V0+EHWqWsiuwpq*dl}KWN<cO8s(yBvqowp-}7n)`uk+W!dCUdOM`N_V~5 zJrrG$Udo|{mXcO$CZfY2CypKHdVMq}m)GlCa+Rq5mOeLq-odXL+jr~J_FYa%wmmdGU9KmLcL8c)+@N=1+$48l+>l%tH$2e_ zri^hCCd+klQ`9=Ssb7wDa;dMU0=-fa4=w!eljJ?c(>+%Ozx33HQ^7Bu`e!Qm#mmVf z65$t5{VEmw;{UJd>E5n_pML7csNfe*eH0b^;;H|kf?vFz|3m=g`Js>f7T^&46T!f|D-P`!bK>>E)nQN}q3dkj_gMF|6$c)8u*&*!x5!)&k9gb)n{KNy3tM0)#+Q9$l>dI+9}Pji|)Y3^y0&c?C+qaSo8? zGr2(TTpV(GsgCBbxG4Q?lRp3ASO-rN4_v(Q(%j9QUWB?Z_e~x2Xl16CR4z(?heEh7 zWLask!UJie;J2}aRQ zCy6!D)HOrvMz<(1XaMU#Uka+$p(6f2Jn>=cPVjDiVe4*Be6sZf__!R4HHyZh;iglRX^r=|L#|?o%nl%7dwHu#i4X1$s4uL?rHNg{~ZecYaCjZ0-`@)20#zZ1`Z(Id542A9@PjN`TUUi(V2HsF zHTYo$KiuGtF!&J$Khoew8T@F2KhogG82nKNKi1%nHu#9O##7#741S!!A8YXA4Ss^b zA7}8#8~j9rpJebS82n^|KhfZ)82nU&pJwnGR*k3pnFgO_@Yx1G-QZ^!{7i$NW$?2N zevZMsa+3_jQ3^9(-U;0p}C(BO*b|{>Wd76-oY$a<)^_( z!qGDil_NqFLh6YRLx+RjWmVOZqiB$DG{ zPt`{lJn5(NK>CFp&`)-gemb9|KNg<)h=db(;B4>~_V}dVi}4p6&lCm=9#2t%;z>qO zJf;YWf(Uv7)5%OvWIBcERHi7Xz-KVc#3UffZ-a$BoI&#}vF0e2kdyK%mghrG@vw`Q z9Uw}5Iij@p1bjl^H6 z>#JjZ3s@h{kI)Ay^nnU}pyiaF%(~#`ang!fr@$qoj~b9r!$?y zbiS^yp7oWmKKP5!2P)1Zs5ppDXVf0kSiI=GDYjcI{@BRUBA z3Zjs&CJH&tjwJclSWYtnNlwq!B&RjA2|t)9*dH_7vfLcX5mR8EqMb`NrDr%2E3EdK^k$bZ1{pRio) z^8)$1EdLA3|4tP0k>n51a{^K5pGp++9F{L<`6`xEU!L$6v;0z)?`65z-vxS}VEKQu z{EtK-|BU4+Nm9>fqL7azihSp?yp-i-EN^A`c9!p8`5u;kpXEPf`OjGXKFdF1dH;~i z_h_QX_gJFHcNWV_SiYF$RV;63`4*P%X8D~g-^21BvHVq*|D5F?v3x(vF$^K{MH6QQ zm-9X~<7M9^2xrY8`2^<6na6!k;8!w_`<38VF^~I?;Nj#VJ??|9__Z^ zPh}pA;7?#S%XLq%7e1f0J zJjy5dSB4=}?F-%WUb2!QzmZ!MP3{N`wb+d@b^rq5cR6V#O?IJ-oC(vzIL+b({w`Izd zCC!u@GiA!1nKI?pOqp_TrmPIw#;IsUX(rPwxe*g@$E51m`$eJLn@7cY>YujeX|3E; z*U?nX-?@3~-#6a-8pRjlJqytg<6J}o%rg>=kSb*5N5^_zibO}dCrGaxzw;BFR(s(Q z9qGR2h>p`=ZXB}xuGkISFCC>ow@pgilDG?e{@dBGbVl@v{nvE1FUP)OJvBhIx0oNs zXoO@r7uO6UB?2)#Nql+d%p1&>JaVfO~mQ^^MmX z1Udn2TQ^lTH%`SOvz2X@NFwF}S2Q*>;gTQ~l5c3LYu0)8G8a&X`;8|>Wou>AMl3_A zDQW4bY61!}%DJ|>y`i~jYF%UHMo8M)TiYwEKvaV zHE|IQsc^>{ICPsWKODMO9)0cLF(l&zr4QX&5AHGW=t?_5;Vy)Pj#W8^fk79~2?}>7 zBsz|sCDG+{g2Fvx;I<(GT~8+{+N;u&$Isw5=@ebvD2Ps8|yrcXgl+@^j!ZmIxGP2A1_JU-e3?hZV}i1E%IaASt@ zIA#yHdxm5GKvfwU*0gWbNbI|t0B+4_9#7PC(V?mDhA|j}Pe9)*V|o0q2YvmIu`DsJ z*8^@o8VE5?*8}eRcrMl7$tk#5j%9fM6ysY8z|_S33eTZpoXWucx8YX{aq(VkV2Cww zKLPHB1aNhDeoX||4csjW=(`z>#?1-fX5+ay5!}86aV=Si>FbxB7;aC3xB@gniIn3l z;1a37b1^I-=re>QGkk9)Wnqmmq@;y z!1N;MpfxlkZ|^zK-${9R4Wy z;oj14$4Zzl?tKk6J`V0<4L2bU?sE-yTpXN*_uHx*c%>_XUpZ1V+{8GzK^ksS9Nb6^ zr`lh?d?Ol8wda1gi5gDbAN+6`8g5D)`(|r6JkpEcr!Pmtss1+MMjHN73>=1Pgue`t z>O{SpxDCMNFm7lZ+-(|eSRCA2z^!3@7*Z0!&%W6!-3VZOL68g6tP+_M_)$T+x>E8Tp@#KF}Ar|R#hIJhT)dl2zde;67Q!LPh6 zt7QM4a7V|%y$;+4#1k%pKMJI8qTyGwS6kMjxCan!Fo6&VH^;zzyjISOAY3Ma5d3h~ zsV*){!hCUqG+cHZTtvf7kAut5a5LiIax@%;s(kGKwQq2VttYdGABW8&V@aJc2f z#C@#c&?LpgS*N-FhbAN@ZjgqxEu|KOD`s_Ov6$8L4o|# ztmh3H4wtA1ez+D5hpLQ;yFkO?FeYx7hFcd0cbkS=ui@4k{_-GjWH+@hr^mrPs^Kc) z;GWcQ8{*)e)o_(@a4&1PsyMjUHC%NZ+*=y1CJyd>4Obfn_pyeni-Y@I!)=U%qd`4& zKI-G(QZ!sc9NZucr^cN~zv%}fHQbq+zO&#jcn)&<*%9DIbG%M21`b_v=bkqgxKBu+ z1slhg8@MSOEbAJ`^gy_cEe*|6o2$;47Lg%y)~xJ|tXUbE*^x+w5b3{>NOpGi%;`eD zA?^Ia(jr=sOa*-HYPp7*28%N1NHX9-@GbNY5(x9-4vIyf5EoA zv6RwU9^OD&<^+h#3)_zf37}=n9Wpb=TOtcH6tQ zi}d-9g(HQ9XA2EOnx9xz5FAUtNk`IeXe9mi8&1Fdhcp*V9@Lz_JFq;ZDzN;ImDcj# zRocrxsQj!sxcv8(Nz4CG`Ehf>?xf1RtH?IWCv4dH9bY@6>tSJdZ(d5{5KlcQPSyhu zIjN2P7$IfJ&5Ea*10px2agaxc;#6H;BF>h#F8`R2jaHy|tg@)<#TQ;$(;ciV#-wY< z0x8>2Jle*$XnZ~$T)-+0(|JtWU*epHUk`zxV88B}Z)y3$}ogz0?Qp&5a$GjGL@={tCP9a~iZVK)y z9$UOST5q+ZcS$%@8R_0{FBzD;G184MkNA3`5{%rnaO}b<-LSc6tUYN-IH!BwDk__P zeT?fYz*Qj2RIsyHTo0-w-g?`q>Gob@lvnbuOsC%Rx`!F{Hn7Kflh^YJfxLlfm6P$C zj8g4!ax}fyo@ACnUe&{t7l^A`amo|P8&arE8Nh7=v@GbhZtA95o!TjovZU<2$uYRxOS? z@MfS1zir@J!M9rt_-zH(0!$l@tF0`I7Sg}X_%MWGyzzC2pN;XlS=JV;1R>)ZfvOZb zE1>60Ya`?}NZVj_ihLSzR0Wxt)(^7XIxgJ!J3GCD~TLko}r2nT};o?VsU`5!3+JPI%I!Gj?x0X^N+Ig0fPY zS~}X7bZoMMfuE~NwCG_%Rcz_bC9BF#c-E8Dre42o2hRyFC@Wc7QBbnHV)4>~Lewy7 zH@MA^E?rrUIu4#|!L1#==WPk35C7}Z9FN|hRM*fdr|?<9;Cb(I{?_Gg+Q}<_GrWB7 z?D3wo_7woYrWa)HB}>XH*5HTEckm}(8J+Uri(VO>_25fh8J+mx%U&6s``}M4i=HpJ zin6YlA0GF^%Q8IX$f6W(X|HWMcHnh=PG#jl<)Stsrt?R9tHM=0H8cq z%lwzE%q^{0v35y5mFF5wmc1f(aan0073o?{Jd?#J)peRUSExX-u9rh>T!bI~_D}P- z41UG02+KM!hqJDsx{@YUiZ3XF!5fst78%JpHVl5{+rt8zzvC^%c3F!1qz(B?mlsy# zm#q|M<$gm}kzbmdN#%IJ8<9n)=0QUy!6?YLyVufDCUwdg^T6W15dO(ebm;=P{EFPX(!v5d8~^Ev zDO@5WP>wr1raiZ2^GoMWtsCUgE=|jYi!^WK%Dq#WVIAw5_U^cgAGvShi|=_7r*t+q z)L7#4axTH(HFy5vXBW-h;(;YqH8(d}c0jyCW8fnluV4Al%5`^pfo%;Nn`&z!)%BIF zmK_#zH5vcUEl2$N;%|-cwjfCzO`a4f;_U*bxZr}_jpMIg^0_yM&7`}c-3o-o8!pD) zJG}es%=^k7@?zWSn_JuA54f*6r>Oj~pUnBylH04jNXHINk}MXCV&yk{c6o5}sSmF9 zCTVCAs;9WBYlb{D>gWw`|I>?eREq@3V%{e!er#y)<10V=e4!^nu%e;^(9D@A&n8=m$yezylGbMZCCX==8JGYpNR_ zALW6HDvF3wCxygoP)5Hq{PC{I1=CW!Xiq(HvSi&?@A*nz*^mFQr^TDBuCciiUY(>{ ze%Yp{Ix~0goZ&^*Gduhu-+W zTZihR4v`w&l4CCK{4}^G{Z*1{b*QxH-jm>kPM@7~J@(d4QexDCx_Nj>-Al`pS68=9 zE1)IHD++V-O0W_}qglIDE4J)AX6;WN4M=|Eig;nB(Uk|`Cb5RL#iXR z{qtyY0`IPb+kGFq%m8G5*j=c!9D;Z#X=sD9tU_0~h8#vrv#{;=RBLHMddY7@lUQ$k zAl!z0Ks6D{Clnv*FRY}GG5WUM$V9$}ofB+RPJpJNKs}r~Yr;~IZ97xAKop=i9ibWv zUv^@1YuypB!zb91rIvcWHa!FUHgco9%C_3vnwnNi^{)_dHj*x`Y&%nTtF2yjA=A@? zD81PNWeDe6*yqj{LB5Bb^DS1+x6#k}sK_|y>THX%69w#DCp=T^KdU=o!af(}O(?7G zP1IKn%NZiH;d9?MWz&)QVdqWfDsK|K91KpicC5>+r2*S6nR=TY4)T~P0O+Ymddzvk1T9Z>gd3;XJF zEPkMhm5|5L`wL5~6yCQUM{lJLJCD0hc^vMl(eF#BqN&)nJ=#_cTr{e8T`$|V+s&5F zUU!!MZpTtDfey$g&%!H}lBSy4Espyk`Iff&hPw9LP3^jHvwv<;-fG;N(@}HbnN)|? zRjB5^^;Viif7p5JwaQ!3K1TZ?RWudbw&&T(BUD2fjqY8qT@mfIUx0IxAL{KTRCY!= zY?ND~()8Q57;2*tdCPjB&)sqkay{(a^4rQS%|^7WwzZ+TMpQKw+_q2iZ$=r{yDqsk z+9mD4_STw)&W4)WR=vGD_%0*0pslqVG1{o>J2)TJ#%5?tKTK0FENge4yX;|k-@it4 zSv<_Nw>CF6*0$0_15wNJrhlR1tp=ob9rb!2N43}CEmW6h)T?mik&`wHy+k-qT+dcXqTs_H@H8g4CII_um-f=KDws-yOJ;%S;81*pBUKK6f zwy9&w^4g8!9f$_@dj}HzI1`c&B=jYRyPte_fAme%rxLc+O9d9oCc0ayUnflHz%OOp zH(T2C>ucnRE-_pIzjpBPWbA0a_JiZU9pO9rc0;xkn{b#LH|4y0_3I(gD2L?_FrLGUz z+ojF-d2H^ROT@P}?;$@dkSBcg_d=l`gi=@kG!(i61e|;N@BXqF{5~062!r!NsV{{> z`Py%erZ}_s9_X9F759VF>p<~=F9^-}_ zy1M%n88`c>_g0Ye zcPMm4j2cWkbf@@vGI7Gpg|o)Y{oCmwd!#(UZ;2ZGIezJ8*f(7mxBt*LeWdXyT{l7! zZe19J?>Ed!38y5dq@<*#q@|>%j7gc7GCw6hWx+_`RG`6g?F`@iG zbCnKpy z8fr?pBq!z4oY0P(^s965h@Ujw(Gc2kp=||I2HQJxM&Z$)xWV>ibbR3Xq?bfEr}S7k z9lUNTyeLIX-CtBG=8x*R9A8{seOIc!%gL#~-uAeV;}w07)8Sbv_KH5Jzb{WtPAimz z_BB0Swy$V_2U^)^!_e*?fhJK(iA@?0Ha-0mw8)|3tdgN2|7uUp#d`RPc+Zu7wJI@jdD9seF3+W08?OKlGha5k75- zno3EgjB{Z0Z3@A}5VG-M#Y6{1A1^qlsEPHY(Z$kSa|atW|Cz9~t|LGQG?UoD`b~qS zZmERQv`-!CP81_WE{-;-aBxwx&cq}VN+70NIXLq*xAQ@Pi>C=M4nF2=jj7Nq?WLIr z4&KzSy+)_c24xC*5v->$UQv?K6C5zTpVPtG+am(H^+B&$bfEhdfN;4-;Rm};+jJ3! za@*Q!H{pxORx4#hT5`X@a0sijW^bviYOrjY0G?!r;VWj)MM;4_;=$Do0SrHn1>28B z#FKF<1Oh?vCJgPG2*l6D5luCsKzt6Un?A`Z0#80fA%O2ZOF^mPDG*N=yqi8G)=N}2 z1@N`=>4+ahUV3FQjHq%t>CG{N`d&TpmZTqApQbSDkBBrF9oIRfdcVY zfKCydkjb8Iq}IBjX}EUldW%omvaY5UouvClG7Ux8PRav+dmy$yaI{wNUtJ5aYiQ>~A|yXPm(`iqB8 zxAub{ft`N5#rlJXPqhZ%l2joW zNE7>FyL`Gu`s&r`mm4L)M<#~A!LgFn{b#~b_vgFnvTk2iR%yXLWP zlEI%~@RJSxM1!AVJ>$_g)!?TYe1^ei8hn<)XB+%d0 zk-?W5{9=P&V(?21zRcj48T@jCUt#d&2EWqaR~h_jE19MhaR>(182nm;Kh@w*Gx&7| zzuw?aH~0#J-(c{S247|H)dpW-eo=_;zQQo zJ@Ng-x|<>NGijdeu&d>Imcx=PD;azUH&!JlHzawO<<#Sgho_ISh9Oa`bg|@Q9_2&& zDSzsVP(BJzeL+9FO!+XzQD05B)6`4)Ngwqw2q$mH==CC8gufsvR?sO-(U}xH7P}D? z1r-!0NKka%1jPqwf=*{TgXv7BI6)#Foi(b{V2#|G~R3 z-%{3>#ri;nK2V_#bPc5k-N>|&Db=fE-zL^q#`@rQt%weSiuwa>AUi>?ru3k9FvWVV zg1=wa*Tnjku|D{(&<85?feL+~bUuTiUuF6=rq}8Enpxj+)`#mr=mXtIc7al#nkemo zNc0A#!anfSXC?V}biFOCcLnRkbtUwIR*^o?I;ONP0P&YI-NlqXuyE?}EY?@f`fz;; zeW0h49#EkdbTy?1UB{G$9~?bM1Xr|zD_IY&Z=nZNoL^9JenCqpJ?K(BeY<@A39gdQ zk-;`Ruv7k!&m;=@T%wSR>lN~|Sl+>M+P9SO|BvNAVfiO4r|X*Zq!NXmi--a*`~&jq zS^hN3Un2_nFIZlPMw;-ei9&uFQRumhntCD_MGq$qQH+Q3j89L)4I$guVndN zmj8g|Pq3W!RV6*2v-}?{?;n!#qlrS#u|%PNCd-RiUdr-1mTzJCHkMz{^1E4nKg+vV z{xg>UlI4G3IW^RjZxT`Ddkj(7na%Q9EH7dCX)Lc``PnT0D$94V{M#(=V)?Tyf1l-l zV>vBuO8E}PO`GyPmMH8wo+#w`EMLj;wJbk}<^RF*ud)1FEPtBiKW6z`EdLYB|IG4q z+uL zDDoXo6!y$y`COJSWqBpbYgvw4s1;l-_vWGdso>WzkNcwF*D{a$n&7b>A#Ne!z9jh5 zn1@jC>zK#=K=A9C&te{f5F&jx^A*fbXMO|oX!k_=O6F%WU&TDyArW8AJlYeugB8S} z%pjtO6#PldqdbDghovGOEtfkMan=hJt3JUuKg&10-kUXr<~u53|pcG=qKQSmg9520&&{PZCFJOS6Ps3!_PD4;9k397$=Zgdom`gAHN+*k;7 zeH*}!Q6P>Zmh#bY+rXo{=me#&3=$ppCiol&CF6)~#Gj5E3#Q%&cd3E91h_kWa9=lY zCj=~uY*c~rqVNd*^nC9E4#N{pP`IBPxM6tiMEBhZ3ilTS*9aUvo2#I3qi{gS>b$)P zoL|25Jg(zP@jU8RFG~&FcY*WMN8=%+55*K=Jf1JNkbr}dcQQ`NZ-$}g;915D7aO<{ z=-`X7MFVK!zA_lkt|~JPYvLXqim}rKaE}j{V?~-OacJtBJ5r9#^@Q6o+OotLodGoU zg)xCajJ@@MYdji$kU%-!JjSxbSXmGHzB=Br#28o)xMPp!F|8hOKbvG(VyvnMTq7C{ zF&5PW?nONFi7_VwcctMkN8wrTVgp00iMtKBn-ajy!?WV`3E*A@?mrX2b>La^#sqK! z(I9>|0o>ETeJcT6JDy?hPXIR#&$iUonZc~T9|3oZ2?B58PRFzH?FrzzflDOcTk&jt zM*{kC@vA z;%-Y2_fCSii5MeE#JzKgF?NIDrl?@zHUg*LS5*QN_Y!dH zRHQ~t+~oOkj9!C?LlbumaMbrPgNd_q64Q5Pg1Fa!OC;ai+{E&|2e?G^jmS$(--QX{ zK1>j|GC#5N_ATHV%##8BVZ*OR!|DBSKQeF^0~hhpXX5Ti5chO~xZfm*`~U2H31C&l z)&IS3%SIA**^Cc@EP{}QRS~l<5CSF<5s~C&0iq$nBp@INDk6<*gQZrj)lWsKw%Tf~ zySB#Vvxv6RR_oeItqU$yT&hU^zcb6dbLZW>JgJ0!{5$Y+?m6?DGiTO2Gxy#ZFV-ld zu`e}BTyB)OnkaD>MTxsPO577s;@*l9=f&EtTmHSE)q_;vFcb@OI&Kzlqry;zq2pEn zhoM-Q({a~FiF*dPabeoRDNmazyXeaL*_>8J=*vHQbvDE}oRZ5$;P3_a$&+Ag6TD zdphI@mx4l*`bicnxAU(T3E&8KvWA-m9F-I4OT>>H;T8dheA>VS_)`R&s-NV9TdwJ= z0FLCOFNhyGH{2oxH=M&+aI#-@E4OljY?yPyl_)qlpK`-3QgCSz^ff3r zEbVj|?>YsS5dn9Zg3FA6yI#Rfih#RQ!A*{Udsx9uiGbUw;HE~vy{h1*MZoPy8PSh%~ide94#T6y1^9RW8?!Ieb7jaP7UBH(5yxY7u?5(PIm0&bClqkfAV z<%^!)1_gHtL%HMDDL4!jm~+#2nSw(X+$HXM1&6M%OWd6b4qaE5xQ7)Sx|%L=I~5$d z1`GFFtscAz9Ho!?4eH;>5wGL+D7e!Z${n{?!7Yq{+o#}AWtnq}cfW$eWtTYLnRYsG z*(I)*f?FH`*I&U^M!*eIa8(g-BNbdI0&cv5tB!!1q~K~I;ASYeS_Stf)B}w7t?_9d zaPs~qV2r#29R6El(Z#^^l@kg9G(kVsa4V3=uPC762)C?x#ktETG*zE9G00r{)Tx6Pqw8Yx=^j2 z2y2I6=c+Pv*C)c-XovppPK33Cb$24HjkHgArOAM>Ts;xihBC`-JiV|j@a7@fN{hGE z8W@H(^<_=V>n7qQt(7fx%@bSeCpOouXlj{QL#L&l8)~i-{F01mnNwHSf@`S5DRY%8 z&R#mPwz+;)U2{Wy^+f4wOKJ|&DXd4c-0qLRE?b|Guv>uH$DrMfti6p4)819X!#B?G z%8fI6ZoiDk-`CT`&-%WeR%gP$u2=h0{o8u_mRZgn5!mqJTlr(?LO8F-r}2Kr8lxBA zrpd7@1@U@3Mu7~>_*e}eBl>s#?Nop;_;WT<)cu)cERw=Ikk$jnuHwgJ=A-_h*uNU(Bh5T6|-zDUGg#2?M|4PV{U>E5R5`{hNTMO8e zE#&1wei~88*|#sipC{xSg#22fkl!ifcMJIwLjFe~e_6;s6Y?0Wc~QIxM4>;GDD+Gg za#{l<`9dLQ-v9x>LdZ7>IlUi1daf06+G2wA{6@&16mmq{m7{l@o60g9W*1GCZ#PDM zleC+cN1aNddS}n6kzUj5<~_U!Z;EyCW*CL|j^6O1yrdu1X>xMT$~pU4C$(NR-wF3J z%0qXoi&KP&xS_CiqsZtoh@YyDzM~mV9-0e+S8)wp;OKUy;w}eHu4Abxb=(cWQTx>$ z&1F@64+2-OgTUwGha|3$Ua6?Ra=k&yh|-)x&8`aIZiFluKe>KP^JBXEp)9O%@;>0u z1RM@c$!NvTAx9wUk4P8nVUBQ{@KbSvfZK?K5l-4exF6t$sH}LeL4muC&u;^c^at@H z_epGbZ@&snuM*cGu|LrNIH*>^xW5*72a9&C;PfpB^ zw!HSvt2(yDH^q30Qj(ei_?yt=$KTkdypHXG&qAhWd-7+YFPijNiUMh!+4Ju(3U(B? zn`JRoIc)_2b8J@Uo^5eWUeETFoHiNTo|ALhaxN-p-*dxj+uD$hM}8Tel2y#oc!aAE zR+bst12P@wGT(W^r{bXOPwP~5pE-Z~x3>JzO9QN=)Drk9v&>{US@z>oer&o-XPxA3ZAt3 zG_41i)||H8J5ToPNXknQHWhjsa))>fVG-j@BQLPYVOLC5urp{Dq^qdoMRfle}3DSw^Na!;(iSX zA7VNyq33L4Dde>XTW_pl@igG78Ztes8>SxmYp|yh^|tfzL+4I^?|5SC@;8!C_&NxN zb(+*enY8?bQG0JQrZ^+FGVj!i({oSHEy=IU%tV)I_R+J0wUZwQ}2BL)10=;o#Cud1N_-ib62Ytwt0LF!q2t_6Y6gbCA~iF-Q3*{ z^?oZIJVXo|;~h{tS7dXfNuE%CsE+TWu^aWE7)c&s%QfBxz& zbTO3fvCO6nr)7~NF4F_ZMY<){x8z_g4@VN#*HT(pVoh_bDQmutIYgC@s`oNuqG_(f zX|~m{NIfC(e22i#UxlCriXN>7ls`vYHF!o=gT{L0lRH)uD7~hc$tr-;_Yl^B8f>~l z2O2v{oDSk_S<_O}aCXsJt6o63qPo7dEYxb(6&yWRYYp+_Fpy3PbEt!09nO@S*Id_9 z6T(Jv8+= z;%d*yqW09*w}e+8O0j9~qUsaoe@N@kM~AfjP&a_b3O!wah9lA=uKv&_i&Q_b3xw76 zl(&XjSGKTBrZk)87qY!~fjp#jsh?@C)$h5kgTvOkqIoy{t)1 zjZ5m6u57N;NBET0lycKNf!C(4fQPh36}j|Fs8OrK<^ryr6~_EwGuiI?ELPL_+dZ@w zYmY9Yq#(bKxSDpQdrix2XsS8eIs2sKo90}%>ZYL&X`MUMG*|2QLe#lcVRa6|)_;3i z8CD;)#Sxkr(&j60^isrOK6-sCGlAw!^!{LSkDTnv*FO;@CON1}_-lH1(AmA?{pKh9 zMAu(J>SOPskXc9dm|1+4$~J2ftXlY*r*~gZucROO6GzXWe>k7Jb>!oo#AJV5#dUuF zGk)^|ZuMRNAy$7t=Zc^6nkTvMQ<~AAsU~|-=C?RZ?wNDN?Z-QIM&C-ObZ5VJDUK2M z`}yB3bZuV3v-Us5&RyJ2I_})n&YS*2^79L_GxxnVf7~U0f0p=bj^delgTu(4Iqlr7 z(66ILf6|9%`QuLU`_HGp=6Y@+y*0+$zX$Dq#9?dy50ZtGAO4HqYz^S0Vbin?qmJqD zW!>{+*r^{r>Nnd1SPnMLH&~AS34h73o;d^C>c|h#?VG(}i$`V5Ayp%B@omqqrU#n* zeByPd9PIhTwU&-nPc@V{?C^Ab7B}IfqX!ZFHqcqz=U-xG_gmvx2u1xiJe>`>Ltm6< zd((1`NY}E1O&6_n2_5wZtAplnT*unVgViy@(y^}UV08p79WLjCM<^o-CmoGfl`>i< ziwNHa6$derKV;`XcYlJdbu#L=J!3k-I*GRj&S&nqlZ=nVn7Xe8-_hyTJ$gFxf6nQ` zUF4o})-YaF$FYa{S;Ky6{66Q=!+!fCsQ^EEI7T^o7<&Fg&m5-Pp>*_l0-Jwfs3l#k zya09cr`woxZvOl!14p>|(=A6jH-EaFNayBHw+iXp{DaaH)Xkr|c$!w-&ss^+cfAi=jLQT7&B%h_)s~;Ua$qH~

  • VC|wfs(bH{w*M#t4pgfa?c~;Q^C_WGvtV;%)XfgJJepmL83;(r95-fkyH{EeUq#K3txe&aUK zL5$=4&v6}8_+R0AjKV*RYdd_vcmn)j%RgW|i|gSE|9f2X$Kj+uV7vt04j*ICT<9nZ zA7i|YYuWJWT;C7C+vOQ+>;rGx8*6+GK8PPVI=2@yKLsCW#DTZ-Ki=pKUOE%!4h~Xy z`qq^81ecD!6`kbZy~Z2|?=$GED(Sq)PulBNI{NnXrw%^Gc-q0o8gDyz*vp$9Q$gqE zraSlqBg?@jYJ8H$Cu@9fjqjuJeKo$H#`o9w0UAG$ogHVV|0s})#Q-Vqv~s_`Q={#cD4rSYRRevHPC)%fF#I!F1AGw4h|>FAtf zr~i13KVIV}X#7NtPt*8xjnB~dOpTvpY;@Q+Mf0D`&Z@KRpQ`cGG=93qpP=z4YWxh1 zKS|?fYW&IUyJFj(ERE0B_#BPT)%ZM(&)4_@jW5*rBIBnb|Hi>6I!E;}!4GFV&e<0H z2*$@69|@iYe|>R(!hhzd&+Lo-Vx-`MjE^(21y7*f2s>NwG&rPlSeFZ)27`Uke-Yas zxEN4B1~Ku(*+Vo}&|*~|z6@mc_3w@|(OdlxI1Io@B1)WFXK`RBV74$4s-x)$* zfzX#O^ntQ+24&?8x{AVsUMy&vpjWB-Fu0}hm$#6QW4((Eql$RQn}r@A)@|T5tuaF-QavIB#o?%3xe*#g&n<3<-LS7~0wL-pD$S)J}tAzX(A*X$| zNza2q{%0Y7SI9pQ@=hV|L-_#w0HUyml_TuQ5ptS|k$f3Z$kz%vo$W#L8-)CBA-`A1 zpB8f3LxJ?aCglGT@&vRik|z^|9y*ho^ydnBp^z^X@-;$E`*0He2SR?Ekl!KXJB6Ii zgCYHY6Y|f6JQkfh$$Jrnp5a6hZ>Eq>74lPryhg~E3i(DMZx`}yLVkykKO*G65ppzr z!&@ZIeH<&!fh-n0`Z4A|OYrD-7(ZL^U>IK_c(ixM&k;P@E#pfCk9NoSxq?UgVf;M7 zqyDr09FwfxWEbpV{A9ty9>z}*JnUioRKY_TrEI!!7 z_!)v%>|t`)!6@Qq6!9{O_!vbzj6y%7(90w(|o&U(rMib{g(rbO{S84p*G$wT}Fm>gjFDThKeF4e#30p9-y<8TEY){t(A;r6^ z1)we=+JetvJF1cLJ1kR3=#m{IcFhQvLStBGu4qYiLD;WQ*`J1n>(JW*JH1_+ zfD_=_7&M5p4cIk2B1~&4N65j4bibq@-9O36byv>W_tO{%blfNj5`M%UEv}_L4E2p? z$U``Jf5xrdp>G5{9+n{CM=Z_Z)p%bAgXyB>q`uV}E(7Ds`4-Af$5suu1-Kj++}#@P zS>WaztiVaH0*o{NjGykN zXt<-}Fh`;YG^gX*;>8@j8{GGM83vnkcY|A)jBzH?qB}j_GyC$nXm_~l`XirZW+-4? z-zx(RgUw|X3|;EDk%J9`%~89-H4eqOOHsu85*h-VQ)>EhwDMRMbU(LG$Gs2S4>euH z>bMJs$oV2&6~ zyc?s$bpTi5l8!U9eD008D5j5LPRE@L+@dfP_9N8vT?gD*QQ-WT^G1VfiW2v7l(<~X ztsA1S?=Ik?v2QTu=F#9TiW2t$aOb$#N89kI?PD?40P0z%iF>*W+(lYG{{uL6ye6|;$0cHI22C@}>9{GtVL2wu>9|JV zjtfKKo~PM&4RB~8VNSCEhu6Jp;)e27D6A1T} zhPx5CK|-G&lpNs(!8kSE`xTrV%M)&@hI>K5(Hwys;TCAPcN84?lOuYbhBL6HC+(B= z5bl38+#m%PPs-p3w+lGfyMYPtCk;5MN6HBIhNf=@a3rUErufOZ;qnyRU=DM|l_4ns@k+~QrN;D$xO)halei;;8F*P!51ILsB-s^E@^fLo{Ff(nkF<*NC=2{>84 zi4kzu1D6GVDvzWHxL1K&AaKbMaFeh`EOFG%$WgxN_FV?tJjf~DKKPMy!@a8DFlAxR z4L2T>JgKi=1l&3WhpA1M`gSU~0TFP+PO{_06v)!osg(zvCroXX(%VbH^+so-mRkp& z%~HM*ZbSs!ZUvVb0k=oNjf{ZXr{FNuXO8k&x6hYl+b8dHZn*vm4nuS1+;Afm+?WWs zNeXUk1YDkiJ5Iq3*YdeS!Qrt7b7Y^6tIe|0JB`CwJ=Jlo3JzT`b8h-JDL6E#E^${Y zI5dGSaknTqRM{?Z_bND4#V&Cj3J$Lsbcx%o;81le+$1fZ_W(!vK=m1y%n`5S_Ga0* zYz|}Lblg4#mlFZEU%}-@!1)lFv`@~v-0bV6;PNBr>#yJnBH)H8xWWjykqWLz!4)B& zF|ODkM8U3?|y&v>C^a$ zNZs$RULi6pV@ybw;@-WL_KKJ}0{Qcn)N5o7yyS z)q&2{`1?)gO8ou0vl)NC=xoB@k2)Lh_l?ea{C%u*3I1;Atij*T16B0*n=|R}*9+i6U$4cq%hS^QDA9f?#nLEE}V_Ei=VbvSUUJ1pP^{I|6`(0@JMsqCo zh2MBv^1Gq!*k%2Jkf-dykgx2a(4MB=Wsin}Wsilj${r8B*0g=75!=6-{yu|H2xH!s z{2;&b+?ITQX!{n(eA|=n3q9S${CnSqYjzd9E%{#VpS3;tm!V%b(Z1cZ&-W<&CgNvY zyJO$qdhOV^2fw%Rdk4Sw@Y{>uhxmPr-zWI(!|!wazQpe>{Qi#LKk$1OzxVO`0Kbp$ z`zL;%;`bSTU*PwzUOPT}vzIw<$G$gv1&pDqKJGOB_K1=8wh_S2=wk=Y&xUVy`+=(- z@66ejJ=93@F3XACXdJuBXi~9+>`LZ2Fk;nX^RvC#?QfPPE~Py8&d)Y?#2Se^&V2Ir z?0AxY!FJ5Q<&lwzi@6n%=iBUJZiVu8vx~V6w9?VdF6LGU zk&tM2F}K5gn_bMUP%I(c?P6}D9jWPV7jrvUce|L|$ZmHrx1rJPVs7DMJWdFL1{M4$EQGCtxDoFYtz2H$*h<$mP0cHsnz8?PtzmlT9b&um#S1)P#s6Y>@jIbC zQ2sAlIc2w$zKp;8BHlR%{6un zQT%(Lj@*VG!H(P6A(4GPzIaKG#|}ev7zhiFxau&}Q5|aQmV{O|v=)ULYa8mCDa#E? zbzk#trC6Mp9;g=2o2$L(DOS|i&Bpo%e=m! zp>AoYVeX1L3^VGR8r2FyN$+dE)IGQdYRX&YT4T?DYruCln6wMEad~}sq3?C|?}2ju z66G9wc-KTOGdd zXl5OKfP5Gx5cEv=NUICpUpndn|89t7GNsluhbvV;c=kZapUSssu9u4yr7M?LV}K%0 zQJ@XMBlxX{UrQc8&!g6mQ(pvH2aiI1N^%~XlFSLUoNZS#9Mz%?HT=cW7WsLYm}FBu zR6Kbe2|s$dEkF|+!}#mrsj{Vr`iQHtdmL3(%o|uPQ*ur7Or_3B-yW#6xBZ{3wAQi# zy&a=eW=me+lshUpy~PojgFk%5;V^Gv{v(*-GuGlS?S0#~XLbvgU4z`8){hE`j5NKE z(bmg-{N~$y$Kd}g<6d+c_oyT1f<2sb{JDs|3HTIbT&X`Xt#o3DqOX)@z8=#68S zecDL~pON^<2F2TLzpx=4AVDf5+j?2=UW<<>lYfyW=`muRK^CG};zAJS9-_ZTCj!d#Lv@`Uh36l=CN&#Bd+o_F^QHha zW9MLctHucqf1-MyZPipCfJFb@2ik(2^Au&Pe%TW%c2enS9%LB$q7Mz~l zIpL9>JJ}Y|6CY{0PCy*%{cSQHzTBaN1G+oznyA86;y(Z1wV59Bvv#HWGh zZ(E^s!1Gl|iTAQSyzTH_qrws1Ybq0|!^snl z_(wn~&&Uzq0ZLVh9Pz&cr931@{2xG%XB_8W#x>5Sw2hq$J1 z56O}LXP~Dsj`RC*y1Y;ifB85K18ZY zc-jY@_6C)X_Cf!igZCP@Ie4G(xP$i_uQ>Ps`_|gl7h{azEtQG9*teYyiI>jni8Ic0 z@bN~ggHJH%Yy#CXf@xwKKgvO_8{7B;-hyBND{3wkdt?^?teyqkHr}5)7e!RvX zukjO%#~t=fWZ%Bq^(9gBPt*8xjnB~dOpTwU@sl-vipEdX_-PtH-FU@e|B0Ia3C7zF z{}~#8lE%-}_>(n0OXIUOK1btoH9k+{^Nr6O_7!M+p~e?!e6hyQ()igLU!w7IG`>{h z=Nf)-bEGiw%|$D8);uD zc)I8HMSpgsBYX_IH~Db`qx*jU3n>&RZqPBHe%xs2Uf|y-_Fdn^AE%Q)-P344bstgi zbWiLLqY4C_CH#5!%lA3I1Txxhno-;&8O6pB} z?->R=yTqGs7%ddpA|XFh$YD^6i1%DU_fAk_SO8JF0}9Vxb55#Poo& z{lP(LUmq{1kHUk-37V|x2?;$Y7-kRhndt##;X!H7IWH)U`K|b?MY!1_9Lj}-18pQc zD1FpH6t`zPT#X2an|%w!UX&vX2O1(gD6=2*9q?9swIbXc5f0_f!hxPe;XqlupaH~3 zd@nU#yqD5M@u2~+c&Cc+pe$Zc7B48>yS<>d3;Hub**!&;;}W57uF!{icP{A%ttNXw zY0N_O3JMRpUC>7bW&74cPWzdV|KCBa^e*G$Rqs5pkNHwQp7cU~GQ|UVE>Xzm6NMcA znY=;BHw*bSLVmrF-!J6P3i&P}-y`Io3;9<9yimw%gnT7Y z$kzxtjlBrZ$`SHk2>I`Y{4Ju8|3k=WpAEwIL7zzS0Ynk+6rzyRck(1J5%MY_Zx-@Z zLVl@`|5(Ux67q+H{5c{2y^y~rZpG@|IQ7+)rM z2pL~4c=R8PuMj-?1IC{!c(iZEqcSmlXt#_%P4H-sj9(ylv@gb=E_k#T#$)2g!lOR3 zei$1~^cMCpeum%yVmxkO%pdkKex~4IALCKknLq4fe3sy0ALFwH5BnIOBY4=y_*}um zKE~$>Ua^nKVHcyYhf&zUDB@=n@iL0|7)3mcLO-L>i)tI@Xig>N@$vDP*QYO^Th}@} zqj70h%QE5nncM3(&LtT_PGUQsPiB9oC@QVx7y?aY-qYCM>FjTM8Yk(T@SW4sGdag~ zrgNp~Q@D`pNasq@xt0vBC4+0p;94@cmJF^XgKNp)S~9qn46Y@EYsutVGP#yav5Py` zlF7AXaxIx$OD5Nn$+cv1Et8m*@NLoMgKFoeZ4>xT)|RI;V|8CEGj$JTElc;()~G185-YE9_sMPW(tez|NS;=V|reuyS6v?(fC$+uw z98-L{dS#vEp4?*JGTgC_+C>J7m-uww|Bvd@f6^}KR?*q{-(1(A7miZPlnuqLuzLM* z!^l?WqTOnF6~z-;)-11XYM2mes1LR94cTk!s#h+pY^ZOnQ~CPFB~21lC|$9#x-qnzWE3;r)y78|6P7fDmO_G0Lt8`Dpv%Nn*gdQ(0o~W=NB2K+ zxFtKByzj+8s^f+zNQoP%;b^YwhQqDbp$|hN;{blrNqv|CI&d@|Un@bvkJwe>TBhSo z;Aku(oz(XO2oDGYN`gS8T;FFq2jk9c{B)Nq^hxwLvE_QUU~>tCibx$GGojuH)tf4dcg}E@E}u2T|hM zh8xCjqtI6}!Z7ZS0_RILjGLpt-3HusQQ&gWF-3!W4Y*%Kq3;SjMvVq{@+jVy=qmMm z-VYqIFwE)uX9q_cMwWt-O`9 zO^zlVc~RoFbb+JwLHxJePT(+Y4|6*1Yv2mPP<*{n)t7x-bht}^TNZ`BkASO)0+)+N z_-c8`AbL731rEyrVNS7M#Jw0L?$a)Cbp9g#Tdp4( zC9*oq>9{Q5pfb$qxJKa6gu|SU`yp_s`e9DT{T4X<4|6*1p8!n@Lt*c7Exlv078gyt z6~N(tnA7!b0tj7xnA3500EaF*%-sn4FeF_eJzfM3%YR|+KH%h7l{{n9@yA8-ITLBz~Yz!ymgroIp z$%8evDDlRV0FH3eHQY781tF(+6YwKPxKn`(DEqV0KJTi2iCd!S>i~|zlRi10B3{Ss zRB%H{8Jrt#w}Qjak~ufrs|xPu2)I28E+qnPuY$u+l{vR~_bIqw1l)cFH#`E)cY>XN zBO>5>DL4!*nIrq?+*-Aq`U5BHOHu^fc;K?&Pvw>z0Z046OB~f}a&Gb730x8UNM9cU z!MWk~DL71lm~+F;z|EZc7t+^{!(8>XDmXb0cGGvKf*TM)-yYzy;7{>lO2wR;zLA(r z&x0@Fj^Z$P`+%zwI4T!%q;IoUZo7dS0~zT{BoG|oeyHL0i)R>w!%&|&H(W3AY=dwZ z!gq-qrr>11>ZWhJf*TV--wXveHUh3h!C@%KoLjt$6r8+|xZxTU9EMt5>RYGaxK&m-==pI9zs#dsV?@MZoP z4MJpG2AsTKNf}XkP1y??BnIxTEUa6QKyfCn-_>wcs3f04raHpauc#3_ya$=DYyhj)7l;dkudA$I?E zaFZIMD-AM+lE7}J5pyfcW=~W8xcqiXb^L*X8!1<0%H~)p+r8^mSUn~5*!*I14lMGC z@Oc+?1fEP$CA$Mf4u0N6dw?iy?;j%65F_i#VJs}^zSS_tK6y#OMS1g!jI7R%m?u*L zO$BX5$OTVR@wnplHrNz%0~D+Yu;8 z$!jD3f&l&9!pb8brA6UmmIgb$CY710Az#ywmqNaIEIiMZ;`MncIk)EoVyc3jsaANO zCoef>Nw5=d-Uy98PbrfeYe{%crWnOMCt+PNav{ib4>^_7RvMVpSrF5~t_or{#_dVT z3lzj`irb#j%acPX`fW~|=_x(_#QD47GpVyEW_wDk@W~4lA;k8Scnety$)>n{(6*^44RmI~Hn>b&T zv^}M;-Mrp=)sBtZ1GgprGgRC@I%JN`d(u0<(AxpKV?N(BvY@?BD5s4iln)&-p12)o zM}rK?akQ8~_WUOeuBC7riw}Qy2l5wD{`1n;ZNAj9k=uNk#gokBjzeI%tiQb06Il!GAhf^QG1@0;tVcMhuHLco?_yPxfR(Zm8GZ7F+6_H)BI_r zi0jqgKfP(t%6D=darL4oD%Py1t86tqzGtL8#)U9JgnMSxD{%wv{lj`kxVVb}h&6qm z25Op?FUQu1hMDBsXKg(cs;zCVYiYsOyQ!We-)EM*Hq;tAH=V@3B;V&waR!M4Nxm%W6KfKLh1+#t*A_^_#3HVYP%a&$D(4yM63XdzzDRBgi2}+G@bxS~# zZ_X(5o|Kj4fSTz@s|8QQtuGA%5u&{%W8$s1{_F3~5VVl9QAUvHr7$1bVaClH*!Wf5 z*q=DU#Qqb2B-1y}^v_$_nzM4r5_}D14)l#TrTt#W3-CCbu@3Oj3t>qgS=$mN!7S>s@c~WBs`qJzO;pNmDKhT%% z2*OB4`s(YgJPFY#El8Vsl%QR*7u;n_TpnCF> z8$UDr7tl=3YAF4s+CHRLE%Ki~PM_nM$u#_&k+9Qzk^KRXmw~%iExH5@r0CeX{o2KC50C?TDWhzg78I zIs;~buvAUx+x6$2IOq5)UT}nt2}-5LCw4?5|F+_j?W@}29niSX0O)P{UI z6qfztsFnA;5%>C52Q==-C=c8_US;J`o?n`mJ9iG1$!juoyiDMcotMWl8aI*G!#wk{ zE3zqHa4UJk;aQeHXD)Iye_qMyTUT3yRrD56j^mVT;y(|0pI!A0VL8*lu{w)l9Vf5HHx5fDC z9niSzdA99g*;baHJ6~km-(})hwvmUDZEuHpD%tiAhiA#$-0TuH*WQudj$HfXjZ5CX z;qwPRbQs5St*owQm6~hs%5#xfVp7Y z)K&XC0tw7-PRr7=(DKTX)+W~G2c`N3+Cv<&PyotWn^#O5Q1{z9FW(i!uwWyAgQ@Q+-2CdGB%Dwtwc%x8Y*K*R)P zK(^{H;_S2FmY4r@;k4BbXi_(ag;@i$r05O{v+-f46OFOcr5+Y$hv@#WFdN(5VPQ7X zvZK4h!t5aR5f2Nqah7Tppv%L;tN^{#!@~U8wS9jz_?W7{ePd+UIU`S)a1>H6`>?P; zwmgPRtp#!x;RqEIl*-h)Du;#+D66YJ38$IRv9?L8itf5&S9zb=ju1)RoJ3}&ImybT zZcZYzLWo@ACz1JcZw)2AKJDGy-D)n$p5I{-%Ow_SK%k)X#Zf7xOKo$C^0L&oIr)?2lHo&u4spMkKbc z_z=M~pH}uWmO`sB`J5-b$WIhZ^Djy$OKJsUAGeA|c*u@mJ7TMYhkxErBR4rNG6tH3 zazx{h8yBKf|C`eXd%&5U(`>o8qKU5;+r!;HX0BWqqI~ZH_1{wXw~m?Xq7>{|MISRy zu3Ckaf{ijx!*f;977o=d!oCU7jVSpDycu~HA{XuZM04HJ`WAeVNy%mDHO)_5d=Jqb zxn6!;ht1Euk$1p1%|*+^QB!gPhC>-5o#e321;184fsywze-caiv_3Jp(Tx**1tSa~Ijs;oQMa3EU--`1cRGiUNad7{|Diy89v867% zLz->seut{MV9dG9C}kC85pD(a0N9Yvhf#Nyu#aYC*FoJ+m}I>kOmr}}_H;d=1>i$< zmpoh(DKEXW$?F21Lx>0LR8J_e0dtK!tw)C(!s=3E+-k1Iy-6?ju-ampi>V8tHQ4+{ zc2t(M*7R&zCEpg1bqlgqf?KB+LC{QZ30Q*YY9COn=W>Y_UgtH}wOU6U`4>@68h7<{ zMWvT4kGP7;4#q-<){OTH)QU=p4VZVzqNj?gLJny~{gc^>TGY~gO+{7fs;ZicWKEUp zbfR7x7Vp`#f>l&0aIL88bTvS+v6-a@g4JXNp3tgw{#-|uEv6dFwsz{#dBJc*dc;-P zyG7qB2W{3YfaNhIIbgodD=eQf*nmS?Z9g|xp^mxKT8LnRRXNZJuUKN8HtLuoIDx2H z>)erRF*u~haIzN$a*ZCba_V$E@pT}NZ&}I>l&=KR)R^^?l_ggHM}tlwEVG1EW5YsIpBfe%!nG^p3wwrqqX5#?ORaY+ z<%h z-&BXOEqF~vgC5eVy`EKVs!PSexL5W-p?gN+oqV{-C|| zbjzqiq(@xKh!rh^N=j7sg65{>cH5v-2h2^5w&4msq^;w@|F#aQ@^)jP))Al^F?Pek z&u6@fzb+@|9ja1M9&{k$Llg_!6HuNbYntm>LR)(_q1I!2IBa$CX|i+eeg32e{Ql|Hr}*Q>_!Fn6`s0rECwN;+{Qj5yaVPy6 zB7dBxcc1D~zkiM2Oyx;<+>wO-hb;-4y-32!pZk-3fkTcr`xDyyaW($LsU!SxBPkIV z`~406xD(%l2#M(5cd_5U#cz(_X}FcWQg%K5_TczO_Nj+xQq!SrX^!&NXwp8>3#$LyV8cw_lV%rgel>Ax7w@gtg<&@Y94MVKIk@?c;^pNAi<%Qc=nm`-fV1JzW%<}8?@+MeRU-PU zjD%@}c=tpIpF_j~`MJo(1QY>7#K`r<<;HZvJ#bm5v_E^8BGAD^9|X z7WJ(!MF>XwB60|Q9wH%KeY_A|0OdV<1US};fnK`LCnMwt8!s#=uZ+`IXWSHeh1v;J z9ykMKjIf~e(kz1_VfrhdHi}-Ev{B9%{%jPzuO?CIt5g)@7%N6P{mn+{@2?Q{I15W} zXGpA_1S|anW*>qA21n1&B|7ZkE&=F+W)7uilM?FkxQxK#EHFK;kzm*72L%5PP76oT zS}y#oaK90>e31;CMLOBR#~AtGrwN(I6Kl-I^*n{AeIEG(C<-6T&asxwfp}`VITk(+ zyFuCeLV9pEX+8Kt#lH#Hy(~W7Sn1#s4BDZ__V2}ZY@%+KoCjwye-D&C_a;aDRiKHC zBRasC-x+wmtE z&x5z)Pcr@lo*EfBk0;4^4U}pLIpX(#PG%hE-^cX=g{NI$suliU;+lx*Nv3J0<>+kf z7zgh$hB|n!G10;M*!e0_ffr}dE^_z>jB_1)jB&Yxk2P*~@Nvci4nE%aqk~T{K6UWD z4ElmmIxq5foP$p?W;ys|<8%k#N8|fyd_RrvukiykexSx5rSXF_ez3+5(fFYnKTP9~ z*7y{o&XK-jG(M>D!!>?{#;0ohNR2;M<40-yXpJAE@nbdqIE^2t@#8iAc;g&LdM9Z7 zM2%0=_;iiW(D+P^pQQ1VHGYc5Pc_bW*f&i(8@{*ZKV9Qb(D)NIeul=Mr13K~{$!2M z()etR&(Zi?jnC8geB(!s^cHIV1;#B7|00bq*7#W(KU?EVG=7f8mumc6ji0CSr#Q}3 z@_NcNzFgxgH2zeLpRe(!Y5W3>KV9P&YWx`*zewZH)cD256C%HZ=p^avaCvq+-Glq0 zzx+fg4>}t>0pkwoh(B8Jbf2cP#g7;KaK^_Qxq_!5a9`X{7YM#L`sqF%pV1~f%Zq@ z=(|Ib4C6t|&rt0{Lt^nGgIRdw2MZ5c zN#Q_i1kI%I;OUGI%f7`Te4Yr8d}QH47g9LT#e$BY@ZiU&;VVV>d=Vb`&%%SU@SrR_ z=*<)!bcY(gN`x;E;m3;bpe#Hn3lGZ9+y-Um)XDM*iSUIYJj$EJ4_ZZbgVqYVn&Jn4 zm7v=Ny+cqs%iGGAYN5AC=tccudO@p6A1FNnF1%IXhj9oY-|K7|MUO3-94 z=cykc`4CXc-a4Uow$O|A!t{bNJ3*I{UeJ$7ALs!=y`&F(oT_iBIE%i7_a)vXhCyG8 z)7j*kh(f-FDC9pC@`r`|aUoBm_<+wL3VZ=k;LjHF^+JAukZ%+6+lBm2A%8~5|03kC z3;BK_r?~*>?@JW=KO~BHX(M}*`-nn5ktpQZLY^<=i-mlJkhco?_k{d9A^(Yx`+Z!` zQADACC{gIo5%LNlUm)bmg?xjMUnJxo2zjTFd;MI`IHIugB%;utE#&ise3_6p2zg0> z;};VJzM3fPxlG7!5c2;K@`r@{IU)bOkiRYDUkdqtA>S0k^=~5z{nrv*Vi->d`5%S+ zWg-7W$bGRKA4?SYqlqp>IS6^CkUuEoJB9oOA^(?;gnWgNUm)aLh5Uy?ezTDOO2{7&@?ApyrjYLu@-Kuu zE|J@V7nqnmqlv@_j=7rI5!b z@py+3Ex}lYDDvk-A)h1UrwDnAkY6n1-xKm3LjI7DKPKe6h5T(He^1B*Sa+uM4kC(p zhY>}*6NNlm$n%9fB;+kZey))JNXYLH^1Fomc_II+kpErC&E7oTenb)PQA82%cp;xD z7ZwvXCLcU+f2lnCij3Ekp#uJ4-`9gl0 zke?ysD}?+)A>Sukoj}?5G;Exl0x!}hM zzC!SbjKzlmYZ}>cyx`{xeu7~HNIr?5dqegy9*bwl1~$%O{1m~%KE_WKJnUoqG{M6@ z#$%$u!oxnspCEYH$M_Qk591g=L-4SV@h1sh+Ltcmm^d*1OhI8c<6$qOu#-{P$0+P# z6!tI*I~Ya$j3Qn}5g%@sUAc1mws(CIvQIuD=D6{K?w>0CuR*OAVZq;oA9TuX+q zfosX&S~9qn46Y@EYsp|*3d&*igx0#%t;U3!ChS;xg5$x^WkKsJUz-DZ`d! zR8}yV&~SpCQP$%Urdsi^pDplMS#;{-5D|bqB(WcV*i!Xzhbq+{Z`gizl$L!;++mL| z?0_zhD{N2K#}gt8>4f?E#-)Zhubv-huO4>qILDqdq3Y`9x>YiWIP;!+L7S9YC*5-& z>y&#cG`Do}Ph-M9QnE6lQrl2Z@u+WM8#YJ{@`HZjW$9XI)*8ZclAw;~bN1slD`chk zP}u%xAuN==aT$48&jh(4_D%zm5C1@g721ERH~(D6uEF0`^>){vc%1$#`#uK#lhWFjq^E@FVsCaV_(?78#L49>Pg| ze*~}Uqcx!{2@-z9ek!h|zPEvUhCGCm`jT*=>iang=3WT`mAG*lt{Q6z&${4d2^^wh zZamfw)O?Zh(*;hdcpJFuG0xW=t*PO^^?W%I^SRq~5O^K;7H~I2fxBR4bhu;i zd?lKAp9b!UDB^9)!g_fWxYBI2Bh(??oe!BR{xSz=D=Hv#hs^1?8M)EnHb#l-h!PhI zQQ~$-i5rw3oqdbCz~KZ%M|s=`+-XXA$V(mf1#n}er$TkyF$K}#3Zuj| z0k=?zPhRTr{%@4H)WYcWtp{$gj7*_=yst!wn_h(bs-j0;>iTYu5|>yUoxXE{YmkvC zRFC(qC~xc zPL#OiQQ|I-68EzxanE&uyGJXJ4}eQm%0XW0xZYS##*%25({b5R;+laQ8>S6oF3rB{ zfEyPD?kV6#MS@|!PQa%{Z1F*y$=3WL)&PB+x1UPygcpI)a2sBMl{|a23;E4=dz}s6Du4Q-x zGybLFW&lTW!UganNBkfJQuXC2xEO}wxC{+f0$dUNtMDT| zXt)mG#t2+IC^^Dy)^K|jTmnOJ9Bq{=^^>^&>3kkqh3j4_qsdf;Q;vEK@Dt{a}l2_rEiXS;Q+%pPpB!{`;UQlqyM!>zK z;AFdVi}y_hH#&m8cNE;12)K_G+}H@XFBKf7e9XDoM}rrVSK%kyu^TQ{!O8xEaO1V| z=ndQ;p-)cx-Ed=o3kqCcP;zd#A_dov!(4I86kPuZxGlhC!M_T>0r-(~i}x7?H;}_z zaj|FE`mlt-oSVKP1xNWq&JDLk!42jxSKKqep$W5e42ggXVu4KJhDN}xR&ZDnVb0CI z7Zlvl5pZM95*dq%-gzeUas_mYB>;|Vw1I|>d<9n87mzEp7X{^f>?t+mrjYp&$naDx;amQI*+ z!;MjJcm&)fZkmFds^I7yC$--#QgB5Pa0?V%aRl5l1&1L#bCeD}-qi|jb_CoO1&1Lc zb8h;sQE(V)b&0!O!C{EfCGLI&hoMK8xMvjHya>3L6x=Ba?i{T=-T{u%SA}0$1l-38 zt~>(nO9fXE0cX_N@tzt17pvgrN5J(~aB|*H>C)3XNWoG6M$QcvRB*T@GUtXHqu|i> zcZo|=aOi@$Fh=rX&+Whppxg63!NG$v91 z27~ESGcwbrkw;bhhWwHO+CxS<)41HQIgBZKVbBOSiCHnmc))wV*K;5zCD>_H8IPLx zDo{;(I_Vx=81PnrDtwPYUn5tms4Ibl4+?~PuJvlKu+Bybx zZU{&HT1O2rHWJErAa|Xr?T;2Nr)}@f&Y$EyyLa0r7u@Gg+&?7FXghhuCoRos+rxD4Vd-|J z=LH2ty7##1c7_?|mzo0+%4f2U>Y{v3vv4_W`*!{Vd9csL&MPdGjPq-j?|Q25uyCYp ze;3-GvQV)RQt*b3>LLYZK<0c zXZ(6TwOCT=h6 zM?vJb@7|WvRsfu?D^NuxGR;FHrkp_TBBFXt(a@JvJ;(>=`54 zY@Ud7rXqQwGk;qiQj+i6-db?}jxmNOx1wKFUVE_2xAck5!fm~q@^Sww+Lqs5bi;w` zz4LdNMOXW;FWly1^1^L}Nd?E}#3aS-Xfv-}(z&>^W#Mzi$P%LCp!&L#vfhEyTVNG9TJ< z0=rqCk=I6Lzq?{s)!s$2&FyXXlqFZ~xA=~Bzi5xXCW*-j>=fa10{fKS#~I_#9WlOY z$7sG<(YI=k6~mr(Z<)VppT(=%_jjp%uS5GDTYK!DiUCS`kiy=3D|%IRw8vNNR^pKM z$Q0zEXV+7z_bZf->DJsV5BaFX>)R7Cmc7D4_gDf43T~G@Eyc3jilv~9N`Uvcz9vrd z0>*CYp$pnxZO`6T(3Th2cP5u`{{o~XQG_XI+aoah&oo)6SWf}w*m;2tW>K7jD`?vt z7F)anu^BC0xAuRdw05_!WN!p(?G$lqDRsOSM6x^F#$K%c&mLDeu4o+P6<=u>XU%@q z(%aKsACfIV*73dVvr%V)W#0P7=Hr0UakIwdk2|R;f5GmytJ|OGEZA0%HEeltdt6n4 zs8f&4FE$I>(Kl`>NZOv9P?guVyDh)HK!46{${!cc>|y9D4R)`R$bCy@w_k>ma?gcN zTyr5OAnWL!cC)Ou%Fc;dVL36wkrP8B(bRG~lWlGCiytW;raVhOQNO2DJ>0pWapYziNLCtZ%{3N69dJZ{7O!?E@!2 z+zmd#tVunbX?ixBiF0yu%I8()FQ~{bE6pyctXNQ)TQWCyc4hh8Q_FJmX^Hg` zGl7GOOS=Mj{GKh)I}=((w0qZl_3`fCZ#W?ckri#soEnO(Vs$Q^s#M;zvbmGM(jRg_WB1l_ll#a!Y0#NJCsC*c^ZsRL(0dHN1XL0#ci8 zM}GDz38@J)_cb~q7pX;*dV&*8X|0;zePiE#Wb0#tdOH&=Rfi?GA@ifV?)+x)N=KYB z!2{KlXmwXf@KKRql;AR!U{vEl&IC{Y#X}o*+>x-#5xJdUy(SMfrL}5;udY9ER{Njd z`=v9%QZ-NTId&%hJZE?Blg_{RdyY8GRsc}K_sNtXvGeAZWS13JoL*U0TwYvSSec(! z$Qtag-7p2&B_$RJ3B4Z)&9Wn1&^~%69h5Y8!EgBJUMDUDRq`Rnn6 zZdi8T;#-~Rl$yiR`Gc3*@A$mols`D4lGjV?eY)Nesk6N*>3qtRMylxyTz>hPuMD1az?n{|nWuBTowbdh%&RnxnKH%^rMVFR zl;>G82`Epi6E47)#rc)xrSY#z4mUPq+nc>o~Q zBa~FTr6n)BBAaeKsokZy46i}=_Ir*+g6Zu7(MSHJ=G2+}US4~VBW^3f>aqh~kbN?Lch}ufGm0qQS-(*U2)f7L!b%5`^<+HVh zEVYMK@WH|1TgN}P>0C#&vVyOcDM3SyT*24K!Uoc}ENS?Ufe=k4!ae$MjCuUO=WRF?Bkl~hM6=R3N= zQ8^>MwBwOd&STSF{@=y3?|IJ=b$EJ}a{ieq%~ezE{dCz6{yh2dtQ{JSzXwevW88mjZyA{rx09NaUkOem!Sy9=jp6_fq}J=M`6yPi5)c%DnuNY`ngK zCcM=hBLIUi@WRGNwk`L3eco;7KKSvi4qIaR_>zwE&+h?1+FucA&nd1bubh`(R(aaovb@S^)R13w z^}<#bLBHoUcfTn{mf!Qbs~@(qsPcQ>aQB;JZ1j8HboI;3FmCjF{%RQb`bu_^(?7d^ z;nmk{8stck$ici&Ybd9_wPjvi^Jz`ZwaCN2$qZ2QFztc)mpnRh$>q*Gl!|#C(hJ(6 zTR#7RwDi<-J$^@wo}U7MJbYgmo;!EWyzJ6E8mg4eEoIebue%q#bxCc)D?aZ z4m!26B>S|=^85;_Umu72XIuWLUjKAVU!KmLSAA^mO+Rp$Dyvu1@)e=RT5My%>X+B^ ziA!-f!w}1Fm|2fX=lB#)jec#TmZ#Fh&pY`j#Nsc(FN2Hc>fk;9b z#ts#gvra9qC@wf14Wp!_a$$biT*|KtMd#`QDK9R>dymM8O#)MrUl6VZRV~Z!*=!iO zwozX{bW`?*D|gO!7$xdV+3NE8rH%QkTk9HIu(5&Yh_}des9EvoKY#q%w1L$xII}`3 z=UG7&Lo}4XZEhHs{LlxVI%4%a0syk&Co(G>HK#nktQboh)G1SD+~^9@E6+`?C}-vQ zA6JaC^4#L6Jnv@hAM(qglP_~vZ{=Bd<=HNitLE6a@h?1Z@2RVDojE2|^BjBD&ar;K zd9U)<7kjH5ahlKZ96Lh}KrlUIi$6u#rKR~L<(2uR**PWoEW;K_44Pmr_eZZ%**Wg|h9K~&{3tu7=d5gKt*_w;o)>Cvt*0$S&_7QyrO9fl0cW7pFWvZ#tpvXkJ9hGLD#Mu6JxvG`s6leMF{w!thnx>1U zI3l*jw$Ab`Go_hoN-zD}jlcTK`GYE)DV2J8N@d?y=zzbCgV-zi4G@5$@R zcd8NN_v9nl${6v4=$bPEDfoc zm&Tc>R-!bjr==I{_C8J`b3~wwbmlD!wbZdGBa-w7X^xtr=H!Q-=(Drm7tRz(y*x!3$VZW) zuP%7^XB&QU|AUSQ1Cs%W#mvF<)v&ejvO-#dDQE~SHOzR=tJZn(Ug@1zzpB2rt{I1P zq?$>d*UWRK-ueEgIc=8<09#A1SWVuZ!JgMmxlXQnmoabeV9y(-TwdnhxLYHBz8nt) zzG0p>O}QS+5fx5^f0*a5|Bt=zfUl~^{-5`f7ea3VX-cF>5g~;R(gjgeBoR8hRQ0IRa|%1uIOTKsMs5>|L@E__uiTF?zfHbML!vCgMK8bQtQfv3JJ_Eh+7zA4J@Te?DiD&Z*Zv`ccGvaE2cdp_{4I z7PUUB>#?zGh0$u{dFuWS?w2=DE=NC!xGk)A(nl@ceR+P%_HE2ganb4lQQz6 zeNH{ruq|a92q}@Mh$iT(Nc4}&*6*&ocdr9fOT_n8)FcG-RZ`R&p9%UZ*;UcFNKt?z*nyOoN(o83+v{(Pq));?mOj zGxPH2%Eg;IY?}KmU9qTC#b!Snk+4Cuh0mB@RHE)v4=R!SGdd~|4jV*UY8)BfGgW+_ zP*^g%VvZbs7&>Wwcg&ZREJjIg5^d#EoS^JJVSjMPW& zk479umdQXcY~wTX&8G|~BefkOyZZnksQ`~?{JU~w*KZqb7jMnEcug~l|@{r8Frpvf$<6LG* z(+%A=OnR(?QC=+F)uN7sB9}=%>zEm*-1goH1~ugZ$7Q+(yUc!mXD4u(Za%~5Dc0AB zwcY)`4s-{2Ob?$D=MKqjqdmjjA=W;+zu(zT8KyhHVS4$Dcz3ARE_y(SJEXRa_V(SO z+_@WfouPimXrHKiiyi1I8BzCs((skpuY8|*&bg1~7#-rp7sFRFqi*l%zH;9KuPwg% z!kbPpeZ^H9=POy)7i>9t^6zgM<;BunE#fxeg_kiMKizt3>d=o3YRWng5bMWBlj%-r zbm@YU3OOe>i5}wj;QWd*y0s{uP*kq+5jmPh4~?FB&9;xO`L5Hfqef(i&+&)< zbN=TGR(Chs(^VhWp4b02dEy-{u5N3T8%uY!=j`A5YDB_OUw>%zJ_DIU?%TP;bv4 zVk>97GUs}3Uwba zH8_?X?MEsn#!MQgt@se9j)^`xBXbQZZPa8m&I2)hvk)H#*u1hwunThN8LK>E&TeIu_xa9 z=z?F&7IwAAweY`2ow;;lk8NKY#m3TIE#fLPAhqy!CmoVM=iwnw8q}0)Bq0)=6Wqc@ zyoI#}jI@oOkf;GMna&Mtz@+xkVyywS=cWJXdR5`1UymJSnCCZOPI2DCLZkgkqHc}! z_WP~-8%Mm=t=XMs`?<>F+VB2>PkeU&30uwQrLlBZi`ra;+VA5|D<8VE`#(N43~aiv zw5Y&20hVaZr{4J1>!%K^G-&l_mX;P{Eu}UgBH}{}-aP-oqo&<%66I7>SdflzjGNgM zwdn)#-Bq{AUw|jb+7+p48yvb~#fl4yyIg$uFXk1Cr0(ezBATMMP9pBQR(~$ZymR7% zCbxV}X&G+8VtC=t^P}ALFAaL<@aytTre_CTQcra8FS+8!bCUKy=AJ3$C0K+>)d%>z zf))?9?KtCuKTMvdT3t|2ZQ4s#uWy;O?ff5qImEaib^7!Lpl0?*B|9XKbd};INv{s> z?T2}tcU7y{NLRBuPLxV>Cp+V+Sh}lBboC2Zc<|kK{3ECNp$4^naVa);kH+*~y(zEB zdjmfoZBBLdy(&9b7*?!*;%U2qg}0fo!wAqUMK6Uu4)w<>uT2P ze8Ier21Tz;8Eae>OLvutp2BO?zDpVw8cvZF|~IUHReaH9^bhCm_GFl z#b(9nvU<9o-f`NfiO+p~>wNRFS;eJ!@aSaS^0VeWwJ`I-v-_FMg3<-J`w_{>`cORZ z{0}xhvw7>!CRG}p?(=&Kucnqmaex1c4Y^}B-TdI@FU+vyhJd)RwC_0!e@L3z@D;ys|>Vv$6(e52!2v zDlWtw-1PZ#XZI;6D_U4sR$Mf*kDKeKI9na$qYBs>tcJ?S&oA#Yrf}wh+0zdiIchx4 zze~?OEGIiFW3;qAeOz|>=su(O-#>jcrp?)fCFw_%6ji1#%*yKBzjtQu3As7Qn7_EJ zX!e|n^zQjR(lZAQ>VH61M&`iu+``Jd@^rc5f7yb0g(Vg8-}$9w^GnO}DhdlkB&h`V zNdCzIjU(AUh`4PZ@qAn~jCx&PQ%#{aw`}s3dt$T8BgdSVP>RY&!3ig0Gx-8pTUFgi zWR@Y&V*IM?fB&As^vyPtc5Z*v(6o=Wfb=H+@ZiZG-Luj zim2lXoKeH>aHEww#Cs`fBw~IrX#kkwI8C2Ar>PdFky}YR?e3fa6W}xVk1Q zk;t@pSoa9`1)#Xe2ni<{j97d)N^%GB%9gs ztZ#kKGAT9eSAT@~mHUQoV!v`3JLFgWcD-NikxS))o?p?*XH4Zp`T|e-6)l(>COKn1 zo>Rk~)jG*$xf~ymP%AwkY3n0-eD^NArFGkIkDKiJdyeBQe**ocEBQ?vrH0)mquSl3 zY}dQZ9=S$Z;JJ-j{)~6OAg7mLm)qFEG#QqFyDP+$9)4h zaB53L-l19UfL-r(?a%{zT(HXUysoHxQstz=yaM@Zv9p(JByv@f`=HgGNL)@0``Ink z7^d2)3e|UnT$gsJ%7lgPGq!qkFf$7c|x;%PPPJ}Z;0!j$_f7ppMklIz0MZuq)D z4^z2uVd}+X9;RGQ4g1*}$^4KH-EB&C{W^M&yn8#*TSu$g zveD+-(b99ARnd{;IYF!%cAn|6z(o;zbJzV{c;K2S0e6R%L`Uv=kJ}@kPs;BPoE5ec zg(g+1*Ti$oU+>7DT>5eAEF*3uzM_Ub@#1O^V>5TXQ|*yq4BP7JU)0GL=KUXW_)+X; zJ&Kv68g`xggM(OsxBr8?(L-STil^;R=&D7fc;vAeB_OVUX z9-itJ=hfpli5BOE-@I*1a_-{1=H2GwYImF6usGi%A95RubL@#3zc`oGjzoU#8`zAW-8dRCS2iW+vR1FPMscEdg29yvQ2_k6jP=IxwZjysd%5#&ee z`#h6W!>%(ecy5fpnXBG=K4(TeXV=e&ozdod+=~Y1c{3s$$ctKPlNjvcSybx$3Pn~u z5-IUrEs$Bm{*THYGI zGO;^ODJrO#<94xZbH^#qP2`jYzlL4&s$kcgFZWt9>FQTL#>dK`y8sMUPJ_nVK%Z=5?*jZ(vI^G&t8&2D&5E4Mb-<8Bg+ z2eoR~Pv_TK&eosOb7Zx#(<*ICqu!!`v1sa<6CZj>$UcwA54~X`aJkCAD%f{ne?hbie#jao8?~#w& z7U|1-dNV%Yv?u9$&V#q3b=Olr3ksmuun*2k;DdPCNNx!x+%u?xy^pgj{cgAYaAS}3 zJL88NlPcMsgS0!p?{$lOuS-O(VV_$S>~r28mcl(UAkgXJX*=X~yWz`)zG(bCZbfH& zxiG0xzK!ATLF(+wFFj7yJQBH5_qcds4SU-o!QM7g9UkBw5)kNVCdJarvSq!+Zt$`_ zGPW@{-|Z(mM*qJrX3)zk-OCURF1QR_C5|#tfQU zOoOM}8uq-Fse$*Z@l#`<-^J5*$m@1PY}@l^(A>}&w1@6-yL<*cDA?P~ z=`qmLOp2wK)y<&Q8QY8*6fZw&laoJ#F46rYja6%U7Fo&1WCp%N^PtC(c@JjqYijR>R(QTd=pub8^T|_o(qeXA9uf`Py#SGQjXP z?Wb;WzV?LgYw@%i_O%zQ^fmX?@2Y&w|P-QYNT;CW5{>`1sFFmO6E7?!hGa}|t6?0TP)zYyKy zd}_4mQ+||@tt@LCiF~O0luxK(pZY!^3`L@=mME8T!(*IN1^5su7Bx>s_+Vp6HU-C3HzI z+M(J));$tg8|;rBvxc4VzTNDM{*h(cqS5qFxoS(1vxpFNL9=>(G9MQ-y{VhuQ9D8N zQNu|C$u;b!&s6EB7tH%;Q1sfAu~i05m$<`0(_c>31x@^7e0E`V{(2!UXnJ1eg+dtt zoS^wqus?dt8g|D2>}F?77&Ltk)q>{TyM9{lg`V2uR+{&D)4JNTMy}Lyik1{guN1Pv zk;tcxTbkK5?2EBTpfk!_Y4tjvC~NxI)6F-v{5cXi9$y8PW2eq3rDX*o>d+4U|v7{%^!E_=W3 zvd+H1p3BM#MkB2H}qoTX((Bjz+P2 zoX>va`7CWlh_|SmpE9aumUWIqGRbY@C^hW43nGz)k;p{jxnv|VE&g}bh_>{T#qh7F zEwkm8As*YKi3WtB%n@{ys`| z#235X-(|sjoWFnN`MY}vobK+j%8|%Pr@y&tNp zW_F_c-_7XmQ)<}X8%OJ+dy0%WLexd~>hX6T-F;t{tt{I*C6X3(*5K~(E^hpXV?0w#0fsc_B za08anXo$E+9on6?Dv`D^kZ<#o2DQ%=+YDK5U*c!;pOozD=f>^9-ObO7-`8C}Xz|se zO!+)ZndP3Fkzp{XAH5&E^h0jSK>R_M?)uTw2gUAjqbE6j^iX%JW|no1L~i4w$EDQp z=y|W!j2^0R;OL3laNHa{+=;c(gP|8R2=+sx`@@8fJ~@a|daK?!Y1a>ep(uEd8w4xj z2Z44(o@#1Y??~hmJ`i+T4G)ISNr|SCvFaD;&Qwy?w)>AwZpm$#XetTflCSA6xuHSA zrV{T*`+)-@@$S^-$ndo2$9Z*;C3~}$NimKp>R}MIj_{@nIY>yAyUg|Uv2zdQ7Jx*h zX-iYcxN-tY8G=7T9JT8QU^a@~;|Ac=_yMT>N?$d#tal``e-c~j>9iUifYYr8;GwPe zp0(=151zLffG&4O2cTBzzyauaxjwMkqXDf3R=Ppd%JK$QSD)cN9rTK1gGF2NRXMQa zVk0FBe}s5y*AJ{ID0YtrirKR&{=H<^7@`o(ul;CB_ zZ{Yl)%dk)>D0>s!dud zgB?&Vrzqb_$C5FH#d(YIrhd743`Dt3#m7`mEGkj?;$Z(uGF8i*;Ag5*)zK1V3+7i) zD9S;8%4GZz;+9=MiYKAiJ#G}=9zTjFsRMVlQ7kJSi9F3mvB9h1QQSP)ViadxU$Euq z$-lp4F^XL(xvAayv?fNe(}-%!B_73-LPjz2%u%dqG)FP+_Dbi?&nqdw&kI#N8H9fI zN3nCAKZ-}N+?=A>B?nbj6qc0B)4a#ATs~9}M}EqY_#;GXJc``KPa{{N*gbBjwnZbd zC91jQyJ~G&^+=>`vir??_!TugY~M_dlm$<|hvm;Hp~?69-zHDIqs7&26D@0lsY{DW z3JNQ|um0sk9rsGXV()c?k#TvIUf!svjG z3VKI-Wla8#%O8Q>mnmv=%J;|gyx{%%J2T@qw1MpnwH__JFg!zvW}|3hRjPe@X&Evp`hY)KRu*cCM#8Lo<1M275{ zQ+iH+saYcYh=Joy|a-4Q@6JLy%`zIew*l?Wu#s$4~`5lq$7NRG7%YqPC=57 zqKpyj*`TlC6I?7;j0rBDnK)|+vQp&yg=2g%*Wo{WcG)+WxhQOpiwtt@#Z~}06UQHx zC*P>^4kMB^k3?>u4)eapG>J7F4}Oa!THu>z{A<*iOE>n|_I08)elXj2b@Pr|`;it~ z+-qZu=2h<&UH*2d}?#4hiPNasHKUI$GH`CGPv)E=G1x!02u;w6B&ZB=ky@?+tbB z#fbQ!&Lf34)Xf;64RtdH@MnVu8RqbzJ|4L#G8zbRGX75%3-LD+iHJWNOA(P7NDwvT zcLnk#quz6J&6}lVwX)6rR%_er?NH0ocH@e#Ak z?9OJpG1#tbf;Jm@-w(0KwxB_w)>_NntF@N>QEM$*)1tQe*`u}AvbS8zYF*U$Eum%dp>6lwxQ4u> zCH!m_i&&(@X|pxR^S_1NorXOt9LwaBtJR);=DfZ;?b{;l8;O=Xy|%U7_hcEh z9NAZUTJGEk`CP4QxwT|jZEd+nYi-ND6xecC8PQ}{MqnQ1K9}|tz4~OV{%}0}c*7a8 zrg=?vV-!9=3iHNad2XzJ@1MLo`CDpD>)kKSEBWHh+!e98se@iSjDHeIv zY027S>YoWseWJFR`eM@mnO40tIgzQ^2&H4J2Sp8FqV~yt)$C@8m6stcu z7F+2pS#PX0#@^<<10;=|2V-OPi*-9|y;w-b$e*KAk`o6)e5Bb`xobFFF8bPL>?;$F7(WG`fxqe!#dD1l}{}|gl z>0~%sG`3Xf`uX>yrP0)glNyUAw~a+kb^6e3m9pK~D(}meo6ssNR;*I3(o$BuetfHZ zzarNB^q-@#mN7I(+n>-X-^E(};&X`F~nRnpc-4 zlXkW))uE%dv}twJrJdKN%ckzmHmwdj_N0EPj=EHbe^iGZ)uF@pk0m?pr`2Icb?B&$ zx^(u&?UKBm9k;bbM|HGmb?A^g-Z*pRlA@h$)9TPs9sW@rI{NzUQMR+~Q5|+vhmJj| zF4fTrz|n z@cVYjPT$YT`$L-NChu%})D}DB57DVEC+uup2KzcHcUH$}PshUONGREvd-YM8juAVl zqqf)~cLAh+S+uilD)${B9rJcphuj98bS&9f9ofE)6L(g}6i-KGR0g4)@ejHGkyDq- zs0_+GqhqC~qbz#LPU={t={R*Kb>wy+qvhI21Y}F)=HgLB&9an zt7XIXsa;dg8PQOPq~4K8%cRsn4F@+I(r{?o;cZJ&aVhB0Hc6@4CCwu(BJr2WRCQ@= ze0oXh=_69l7!f;jM8k_mV4t7lzMhWQnWscV^T=5v+ym zaQmdL-Dh6Is z7u4MgRPX^_2gH7{u+6B+g-N?+qGrwsukZ(kEvvQ3)`@v z^HnOorq!VQj<&H#O3i9Gu#NjwE52NHlKg~NQ<2?JeqWo?(oj{eHLmq(sUB41`dyIQ zu;DNi(qKO^9&fHR?2eQUG1rnt8U(4af}WjCG>F`$LvXDS%|=F=?bQ`0tuOa&n>LXD^DL^QeIKEU|wNKh5UDZY1#bJvb>7I z0wIrsQG57{WLd2G$oFyFPfg^@ce&h8kp8Oj|5y8}(l6iNb3Z#{Usc!FwEb1-ud4o4 zU0+pxP1nCF{qkLO_Y>5A|7(6#^{*;_f7dw3Ap5Gyud4o4<@c?k{Hm_6D!-=nS5^N1 z^?do>uKNk{kE;AjzF+Eog08P>{8x3odTHAU7|qBBc&f_`vND?=v@NxF@-8^QxS*(fQstz=yn@A&Btq2YR_>VETup5i4I$4Q zo|9Kzh(kx^C%hpTS%wN!2%i$8UaBG3Vdj!G5dS;;BMrXO%9AR+V-620D=RG@$ zUm*`Omml9(W*XP3vdrTOCEc>tI1O5U>}pNqkXqyPIP(a1saysmr`9=!OqhW9BWhxBROnSauh5PohYbUX2= zbU|5up`?p`_}{5*1+OiQ?UKA=ua)U&KzX5@ZJY}OVomUo~U@k8SG0Qs(-8&Q052177n>na?LoU$5k=7sK<`kFa z&$T1tv}Q*3+h%@6T%V%j`e1 zs6qy6X}JhvW@qV4e?2kLuy|2fQAMGt)TfS!r-t|}|cFDzP! zR!dM?rgz;nq1Ww5VV;G&C95dRyUr-g_nW&73%zAPPSFx4ZN91z+Iw&e+njd3hCz=U;J4@DxsVt`{maY>y7+W@rse3D&8{k>x&`-$+aa_VqUs(}8{cjl?YD`o?0paeZTP znvvf`tTFPNh#QRjrs8p6-@c||qmkcCd|_PQOnhtPHx~^sfc@*6i{{RNR!tC%wh%pl z{ra^K8Ag6fG0w_)xX{S&AZ|1AJBWLX{Jq5sz`lKZi+>sU`-m@%{C&iCMt(=p3enBK zzN6>>?0%xrba9}OpDxB2`TL4IBY$5p2UrF!`H4pN6{Wyk9H{U@V7bteADMp=u=|Nd zJBf>deS12ItBm~4V!e^ySv+mzcM)5R{4U~CVBelD;%ne8RA4mPMf?ct+tWpC2X;Tv zXjjoPrrXn1v;%fO(dd4npOL?x7;5Bq6H|=*ZsK?&zq?pqVx7V7 zFYY(+0P(1S2a3NLc#wD=*td7Ecp2FDufgJV;C;RF2a9)s<C_ z(H>Yn`jek%bd2Z>e5eBz-XHjI4QB)U`VSIAfc^E(L1Hwpum2!%D6p^pAdv&?uSds< zV}ZMQ`p1fVV86Y_in+i;wfu76Lo~b;_%IEx1fHVdbASspd=c<04POO3Tf;X17i;(q z;1e}`KXAE*9|K;d;irLDX!u27zrN$dE5N@0juYvLapHSm zzdy!_-+`xU{G|Fq6l%C3uwTD%q9yPgEx$eRJPmgSF4OS-z!e(K20lr{Lx4}w@Mz$M z9zIwc3hb}94i-7UZMFPkfhTD=-?)Cfm}^`=UX&Zxj~7dU{q`9zRsy@9Nc0eK4)6?0 zkoY1kKPeg!R~R@d?lo|dc*(%Y;xhxsM7;)XX?R@=lW7+N*At@*oGPXpxV~6n;0EGS z12+^88Mu*n$-s@pmj-SkQr*UfSxM2RqPu~ciChCW7v%FYpv-sS=T|^^ya#H1W6+H~RpE$(8-Nal2cNb?GxQDpOz&*wD2HszM zY2aR>K~oe=pCqi;dKkF37;WG_;y43mh)M%zii-@KCDt1_TYO;PzM`QU%wR)Ow4cZ{ zaDQ>Mfd`1?1|BGGHt-fahLd@92$8D7QkX$+sv@EHuB$?#bWpUv<&46kPRT!znM_zBrGkgQX zH!^$^!#6X03&XcEd>g~JGkgcb>lnV1;ky{Vo8fyHzL(+q7`~t32N-^k;lDEc5W^2M z{0PI3GW;0B>luEW;U^e=lHm;u|Bd0N7=D`JjSN4-@Usj*$MEwE|DE9%7=DrAO$@)p z@IM%Snc;sj{4a+8&G0J>zsm4y48P9s8w|h6@LLSO&G0)6Z)W&ihTjt(8}aEs3~yoh zeTF|^_(O(2V)$c*KVkS&hCgHYbB4cQ_)CVjGW-?8Uo-p-!`m4Cmf`Oh{+{6<82*vr zpBVm`;a?d3mEqqQ{+;3N4FAFKe;NLhVG%L?Bf@Z$;UtEW8ICcW!f-u?QyH$$a07-L zGTeya#tb)MxGBTU7;esR3x-=VoW^h~hFded7sG8BZp&~xhTAjTf#JOw-iP6i45u@^ zFTI>R#<&SQ8c!}$ysFkHy+EQV(@Jcr>ThEHI4F2ltP&ttfR;nGNBBOaZ|^5;j| z82M!kmor?!@B)SxGQ5c4N`@CRyoBMU3@>B&B!-tWd@{o;7(RvJQyE^#@G6E+WB7E2 z&tUjWhRGkguh*D}18;p-T_p5Yr9zLDXZ7`~a|TNu8T;oBI#o#8teUdQmA4By4@-3;Hu z@VyM*$MF3OKfv&V4F8qkhZugC;YT9fjQH~?!;dk%p5ezCeuCjA8Q#F~-xz+1;inni z$nY}^Kg;lQ3_s8C-x+>^;TIX+#PCZD|AXO|8U823|6=&x48Owgs|>%!@aqh}!SI_5 zzs2y|48OzhW`^Ho_&tXI!|)b{-)Hy(hCgKZBZfa__!EXdW%x6OKWF$0hQDNZE5lzg z{58YhFuaZ7ZyElM;qMv#f#Dw+{)yqA8UBUgUm5<5;olkF&hQ@$|CixE85U79-bA7U zDE{=pZCeYxzjHX@T!jx7a|z3LT3X=y&T|OMcT8H~eVJPbk5c$R@i^gC3gi6_!t$qs zEutgDcZ3g9c)VyrFVD15cz`&7u%xw!4irZixW71&uv6Y}aRy;|8`>h8C2l7SD4OA2 z*awXKzTyqS@|~I%c;Dzd!cP6NMT=JQO6O-`E$}|k0fc)Ytp(m^8%bEcv(y6bryWIj zw8BG0G2uxHA0*Bs?9^|NxP|aal|NQIV_ZK>z+{nzKX|Q0#9qPfG!o+_-$dz2#FwvS zNWOd>LGlx&C(@HBeMj}|C_hoTiPCpe|BmvjtK1#clgLi#*Ro%wn}+r4&hir3nJ7Jx zoptHq{ZrHJlc>KEr6;ndDn4Gf6tP$RxFlcCNh`*?C{p5Lo-bb?O2Z3pGM-DGs~@lV zDm^l8NxxQlN)qSG*Pc8*;Dwfl7yLr=VT>FvX;tw~u+#&de2w0V+h`v*4$IefWP7Rl zqn<8L#&wyl>ViLi1v~PJ?T$wIV~_y{57F92n|&}1U* zNYe9uRN$Wq=Sc~?m}ID4EF$H)Ds8M#zxzvra@Bum6xA+oN7cKvX#g`N4|oYl6_?Q7 za@@&&kn6uR^g{EPkPp(5{d8%BLcaX#=Z@iQ! zF9NB4bBVtz@qg0mB;O$UCds!*zD@ESlAB4sOY%LE{~@`Be>bkZh+mUQfvIEJzBWjE%{T2~(r60|Sh*IfXzf<~l zN-sh>`B^#1Gm^x<33?TG@wAR{e=Mp!7j1`yiElkbBGPA$yUOJ8MZi zK-ZT<`sR~9#1o|tQt5$2SBWG@*-lckkh0d$QdN}lGg+8 zM{<9X(oV1aVx+H(^dY_}eUQpNNM#?SvQJ{E2U6JwY1o%S`pQY)7Sac)?1NPHK`Q$o zm3@%PK1jp9dZe#{^u15|AXWcDs{Vyk{R^r37gF^vq|v{rq;CP~`+)R8s{Vyk^@dda z3#s}SQuQyS(Z3kf%3l_ez7I(sq#C!77}_EUQu?iwvq=_{l=}jC{ed55D}9SdALbF& zACTxGkpzjNlpG?j2R?-45hRb&^))1Ym81{zkeuPJ?ysy`rAe?Y4KfK>efsrm!b=#R#vZwcwc{HXLns{Vjf{Q;@^15)(|r0Ney zqd%IEzNMrO^Q_Vbsrmy_^#`Qt4@lJ?kg7i*js8HeR{gPz^kKeM`lOWo0EwM zz^WY~k0d-rZ$CVoQ~FLKeVF%^K1kKSkg9(nRsTY&{)JTi3u*LkbJB+m1ysEHlJr5U z{)JTi3#sgaRQ(I7`WMpZ-xj3rWYULqh_Vk-wHqWttw@5D*Gaj6q}+!`;-cbSCBl7!#f&moncLn=RqRDKR=`1xL>Zx!joI#B6@RDKSr`U_I|Ii&J)Nag2{hM%_~ zeW#H=tS6N|NTm-_>4Q}IAeBByr4Q23*Ov61PWrwleUNhflq509<7N8;&m*b&AGlKQ zk9MT*4AO`7ZMp1sNY%fPm=YCM^Axa}ry$il1!>Gv?MdI6qz~(4r4Lg14W!Zwsm2YY z8aI$?+&~)RrUU6ai}Yc=t@J^v{)JTi3#s%$Dt(YjAEcoVPN4kyY|{5L>4Q{uL8|&f zs`^5z`a-JuLK^kmhxDC8`hFpOkgC3rN-w0c4^r6&sqBL^?1R%Q`&N^_Ur8UNsxPFf zFQn23sq{fAeUOH}bkcV&>HCfJK`K3vY8?VON%{$79!aT3;$q!j_9cDik-pzaAEeR; zsq{fAeUM5Yq|ygz=<7uK&L@4_Ngt%DFQn27sp<=<>IAoq|ytSEA>F;lbl0R>hBD`f z(g&&ZK`MQaN*|=s2dVTy8v1Y(r2P33(uez5r4Mq3j4O~T?nA1057}GV1*zgaq!I6X zkiJVvUlQqqRQe#5K1ihxQt5+K`XCK`xam{&T}JwnNgrgMv=36%8*;F;3vxWk!%50^ z@Y-*G(sw!Oi;+G^r4Lf+gGA9H2~yf4rMfSJ9HZ;&Mf$EFeJP|5QpJ0TrJazfKOj|q zK%OM^LY_+UOkFQ-N>#nDB)#=WFC=bBMG~Z1KR~K_LLMjeK&p8Jay8+9Fl6j0#@Zf8uL{j(z}NA)+fD?%5F$yH>7G$$it*wNVQIZ zTt--}gMiNf_WCb_^j}T-8<2iTwLXJX>q$rzFCa^$K1kWVQl3llB3&;Q8>&67A-xSr zFQkf>kg8oE)wqXL;~sLk)CVcsSIRXcuh;cwk^XB*eb%5F$y zH>6=V292_NE$MAcdLie^{)1F@Ln^x=mEDlaZb)S}q_P{*u)8nmzmD`bA^nhQJVO@9 zav;x^^@hBH3@Aag&Dd~k&dLflwNVz^ug1nOCZ6xm^`2eJ+w?FB< zf%G;by^#6RPRQ9LpOe=EzfSUFl3$SA2I=V?KzeT^z0FB4j#au&&FlKhb5 zXC%Ld^z;rSy*H8G7Ni$a*$b)cg;e%JDtjT7y^zXYNW)$PE#((Clirr37gE^^sqBSR z_ChLqA(g$5%3esrUIbaC_ZHHN=Z$KKEDtjT-`T|m|FCbOCgH(P7`KW9UNL3%m z?+Ld`a?-O&4kS4Y(rdRNWXG*!2cCB-J0O)Ekjf57We23P15()msqBDMc0g{HE7 zkY4={Bs*>=JMes0)gMyX0jcbORCYirJ0O)Ekn3c*kgt*anPewf9?}mdnM3kuy?g|3 zgI#{pz9NmV|uDj#yCEC=!$l8=&ng{1Ujncqm33)z+A7?LwdE+=^v z$;U`;Ao(n$*IvWP-gRUzo_{NQA(g$5%3eriFQl>;QrQcs?1fbJLMnS9mA#P4UPxsx zq_P)M*$cTs+6B3mPvo{%LZRe8Yer5?xuB#$Gxgyb5M z50QL}34!gAcn^lL~eyMg~n_-m4lWcwk#Imx~Bb{tK1-$Qoe`xVuWkjnocmH$EJ zOM4(yoPxZZu$<>)`oBqjOR}XbAL%MyLdxxIB`zZ=_h6LxMv_mF+(PnWl5#Iauip=f zs_$Bp?v1GLNRzM#JPFxJNIzdnq+cW@(x0UCe^L5tl#WMEiZ5h;fRClQ;ulH@J&P!P zDW%^+>5owQ1v&TbTxk>{Vhs=S4yO- zafS#rZxwU&bdwT#_LmZRj;8dvlwL~dXHvS{J5lnlq4fGGjvl$kp-k^6CG;FY z>3Ni1Na@QdUG70B`4?0AZGx6k ziy-W(rEjHl`5QCohdrePzqgd&kE8UXDg8J~-$?1NQ~KMK zF5i`wdeWtYo-R^C&w-RK-<6i>Ih6iaN`IcxH&Oa8l-{6~!*3!b^mLOF`Ug?^fs{VF zwUd67l+b^)l;EFE>6cUb8cKhV(x0RB7b(5O9?%%NC`cEPAzFq&JWf>HVdIod;9;1WGTY z^hK1ul+rJt^y?}8W=ikAkE3U>lqh$Yl+a&9=}Rg7WJ5qyD0r>N`H;g-=g%~ zbVvUzDWU%aDWU%oO238D@1XRJl>R!UzfI}iP*VnFlM?pyloEP|Q~HsVeiWr|rS$(&dbG2{?0eQL%6<;Njg+vbgOt#dN$I00eH^7vrSuahy@b+Fq4bL={W40wm(ri6 z^yeu3LrVXV(toA&rrjKS_LUO$bd?hJ45IWyDg6jaFQ)Y6lzu9uUrgyYQ~K?c{tTtR zLFw;M`X7|uw7XMoODR!qwv=ekgD8DGr5{h}^C`W8($ApuD=7VHN`HjXU!?SxDg9eY zPwL^6TTe=q+f7Q8JBZQ`r1VLYUO?${D18N`Ur6bfQu;%b{&z}$iPGPv^zSMCXG(9> z(~DgAItpG4^;l)i$}S5f-alzum*-%shi1oYh(QSU0s_q-IopYR)m zA0YfD;Rgx7Mfk6T-zNMJ;dcl>On5V4+$3bka^EHVDB<@AKSuaJgx3?^LKrs}>iYKy zKSB5d!cP+Zknje=9})f=;g1PFMfelKPZR!>@J7O)5q^g7=Y*dn`~~6X2!BcVdBR%> z|DEtxgkK>1HQ^Tte?xc^;cbLpBK$4ke-QqT@XLh1C;U&sKM?*G;U5YAoA6JBUm^T6 z;a3U&LijbpzY@kxp6ZX^2){x2cfxNH-cI-}!uUQ=`Pg8n^A?| zB^)9A9^okA{}4_hyoE4sV%7EU6UO&J3V%R2h46=j>kb^RxV8xa1K za6`hl`Bm-Hi16ox@w{GL{{`VDguf(==jJLOH_hsLJnvTcE5gkQe@z(AkyZXTgz@}W z;cbNRoL1p)3FCRG!ru{YP567lc#f#@e;|zKc?$nX7|+8L{)sT2V=4SIVLbm)_!q)> zzM}B2g!iWRQPU%8-)R|tQe<4%moVaw!kq{s{wUm;FyfEGT?ixoDBP7W;*Y}n5k~w` zxEo=_ABDRUM*LB@2Vuk?g?kc4{84y+!iYZ#_acn=qwoQQ5q}i!O&IY<;XZ^Be-zFj z{0ZSq!iYaAKZ`KpkHXo65q}i!OBnG-;eLb>e-!Rdcq`!ngb{yK{y@TrKMD^bjQFGQ zV8Vz$3J)QS_@nSp!iYZ#A4nMSN8w?F5q}gOP8jh=;Sq!pe-s``81YBpQG^kH6dp|& z@kik?gb{xfK8P^lkHTXKBmO8njxgen!Uq#Z{84y3VZqwrM1h(8J+O&IY<;bRCR{wRDbVZ;pv1C ze-xfU81YBpJi>@S3eO~r_@i(>VZP!i)pNsI?2F%Fc3|0@ZY@S__vbqYbD{&O2Utog#RiDzf}_cswDhWN%*Id@Jl7(k4nN1m4yE(3BOYk{-z}S zOiB2clJF}f;ZI7!k0O|_5`1#UXO?7-DPNR5YhJ(s*Ih<;nUE>u-z>`I$6Cw0Y|3ND zSj()wl%>ufG>@&8+5P-%=giNF()sGdQkmJ`EK)mZTILQg3T2rCeZ7<7&WDy)4Kq{{f?lO?CG(@cGxVb#}ZiN0=2sLJSvD631{hCptjQYm%U2k`<@FYWltd z9O3kGU(Igs08uaW^wS24cB&_xUo4gO)B0RH##3jwqeWFgKhjuTZ&qJB@L1&<)%QKN zv^Wn(`z}@$>8Dj)v%ouaSm`kw!aT!R4siTyfa6~S94!MJEdv}a z0~{>_94!MJEdv}a0~{>_9W4VLEdw1b105{`9W4VLEdw1b105{`9W4VLErT2_gB&e` z94&(!ErT2_gB&e`94&(!ErT2_gB&fH8IGFF3`b99hNCDm!_kzP;i$^YaCBv6ILb0J z9Br8yj=IbY(&x==qz`kO?2XJ!(w9m4GD%-1>B}U2nWQh1^kF7Z*JqKwEYg=n`Vi}# zeA1Ui`m#u07U|0(eH2ME5lYo{*`yEg(!r!JoAhOqzHHK$P5QD)ABCJuiaD7SbTScj zl)k>CuP^EAOZq5CWcDR}2os8rfZ#~7uOHdhkM#8;eHfGukM#8;`}&c-exwgWMDhA7 zePeT+RTgBH=v`4*S>gO0d|3XdoQczm%17mu7f#MAE-En6`C3d}N!K_N$b{0;`7`tK z=Ngwevq#bFl7lKM3QNk1N=taQxfavaQjywnOV4!*O^~UI9bZyWSXQ=Regy?e{c3+L zrl+dt8Gf0&_R=qN*BG>dnN(@ik=7K!naWVMe$iDs7i%Gxt+aHm(q*nk^lWA&R#JMd zX(h{4?Gj?8t2*JjDWD`Pt|~Zjm5}YvR||^E3nvzq6_uKf8^wCE?@a(NnWv6>j2kQ1qCmnn7*JjR2)TLEwRi*i={YP z{8BBB5?V}^)vba+$FL`AEPcHcXPBqjTkJ53HaHVesQg6Pd^MyOU@nGuj=!eSbJ$WS zE-Uz|in6?t@_9uSnf*rnvyb)7pP2)H`!h}MN0~ehEhX1Fo)s@I(|-GNl9U`ahV(QgYvvc8D#p3ye%88DqvstGkn^yOSu#bYnP$niA{oBqmO;yOXG_pvMQw zC-e#1f9k7G%ZgTaCt*HVWerq!Cn4`(ylL8-X!T~|OAdWa5ylHs=9O55GLILi%$)6Y zTa@qD-APRMmP*EoRc|SeF{#RX4YsmLphXW%##H8&WG=k})fg+^-ncUUPQth?*ooT; zi#v(w({sm9pShr@xL|r-1#V+zE~t?A8|91VRpiYSy~_%Vb>nG<@*nH6d}m#qFk3mZ z`7Jyz0TlN1mlZ)K=nr`r!!aU+pv;I{h%qhN(_ogP242;ddryVgi}8F0Uce~Ka=DCS4Ab%ef@-@eEO(1Z z{4_YYRBOI6BD|`g_z(H?r^u}6IG*_=Ii4N(G?~$;0rZE)jN!C%2myA*KUroFWsZulpWr zJ*05nejdx+qu$xWU*{bIP7rSh)3+i4Z!+WE42+-Rc^}ul1xV4${ReOm??T4IPYVL= zyNB`cig+OJCC0-m(t+jTClrQ#CxEB7wX|J+lJO7uZ?`|L0SKxGUO6{-&jJVO!>ir~ z?>FF}{=h5J1}{At%v;EKW5Elu?^4DqNucj3#=AIyzV{h#eFA-dGTsLXcpZ=qs@Kk` zNx|)ht)UFwQ1F7y!Hf1@SInyfYJ&EBA%b^{oeQtaK3i$UOOZlkuX-!MrH0 z*YzEofG77k(s}2B7gUeYjQ2nS-VDZj8$3Ct-H%(36^xe=3+An5ywkx8^83Ft-lGY4 z+ZgX_@aDM2LAv&}gxz|(Oil?dH-qucPQaVOcu#;ARPGYS+Yf;_sJ@pmp4`7Bi1#q# zotJ?37UMmYfcF#Q{gi;$678zDU(eKF`}#B9@dk{Z2#CV&*o9Yy${<`Jn zFrM7sry_tikMV8=@ALrP*^Jk_kr1l_csDcNec%P@dz$eEVqc#ieg9#+_288Sl)Ihr zdN&c`_yAs8j0e4)SA$m>z?1tv>AYm@^D`@ecP!(b0Nz~zyptHOO*0{G4B%bMcqxRKYuUDc-y`}|x<|CYkl*Nb?V zuGObenh?v~Or*H!Lx@K-ads;qp6cl$UmnbO6Gk|D(fbVNU!3>YNIJ8J5jpRL(Ky%5 zHA>@h-k%5289N$B{*&{v4tDl-XS6upd51WA@>j+CWCEQ@z=*uujz`d016A-QA4z-6 zSHatqLua~F!TaMVJALH{LfED_?!)VGBW|Ry{cGHZ^WL3iSKqYhbjAVG$n~9`M`v_Y z!Fwm4_HeI)Hxj|XrXEY?*wy3S6YT2Id7cncEZT2Lsa<_vKGCke{V;i`vqP$AmyHXB zxXQx5>5GNhJDI7A8%JL(wQJ|j%kA3vm=$*Iyy;Xs-mud!e^}J_uV>heqh4p*^~Z&) z?RdYOXIE~?U+na~dXXJ(@TGKC1M6TuE^ofvj@RNUyK*b9w&T5bEuDo>g?*E*x8psF z$y`1g;2&P!zPH%%uD{LB@87w@j+cf-Nv?%`bMU|j+b_j^csTeS11 zf5*A;7QCxA31^S>D(Z30%fi_+y$asqf7|IRdd*JXlsAP?d!$!U?j`Tw%vL`kNJecoBcII6(jM>f2s*b~WycRP4C_Km@w zN;bUrz_TfLG4^D#;iX}(CYy5avg93%y`HX#YvuU(_X&75<*vY9Q8v7G*h9*u+=s!l z(KiWuP}%UdTJlcE9#%H`(y_Od4ewD)UT$kUeP3Jh&cxnYHuiPGo?AA&^_INJZSC}J z1JB0q&%vHwHuG;6>;<;g!k;&SXH(zf@kOzXzW;(}qwjL;MP{RK;68Tx{tcduzOs%u z8^NMony1_G?g05%>|Vm_aW8l_ z^__+<@^5#QXp-wo*)Jj<(DL1Xa^9oh>Ce#<@#b`k2!w>V57)OGd)V3VF2){rcgJaq zZ@CH?f!A7>(yH^*OHt_S&=I&9LO%XvzD`lGh7+0NU6$-;(!$ zCGQtY-camKXk*_BOWsCHUMluNv?+IjCGP@D-m8|pHrS)l#=dEmytS6Rk1ToJv3I16 zeZ`i%dn|cBSn>v9PfHv7mRa&PSn`swho()r2V3%1Tk`&C$xFlDo;LPPwdAd_kNa@mmzKPo5qA0>v*dLiX{YZTOWyaEykkeo6oxV~_-W!&@;p6Pey~UE(6nm%J^xGm! z-hV84LnhhrZUE25zQ#Fr zyhWD0_bqvc=Gv9}pe3*4QFi*yvgCbl$vbYcUAfO$@-nB`>AT937n^FQuhf$FmL+fW z(RStDY02B`7(0EZSn|FEuh?RJHRV`4-qYaOjJE@(+3_v|Z%crEOWFEw(Q!EQI)HaN z<81*i-GV2Mx8tQ-@=S7Ljv9utgN+)`ibIT4X*p>G^``&sbjS?asSQr|}KZ0h?RcsA|VvB)`dm{*1O#}VKS z7QFMovuWq`;MuhE=ip^nl-su0jyE2>K^FQ>1#f@_?-B59+GQ(vHuY^g&#v5w z;MtVB5#7r#y!&7kCI@bI7ax%GyK zXakf4j{Eb}RNxO8Z-d55rmH1S?n|WWdsE}ZG+tN6+oti{JzS)|v5c2`qi3@#bi}h8piH##^EB8fm-%!gyOWp7ay>k@dZX@qW>G%@xbx{f+UO-Q@RM3yt?7 z<8{|~Ej3;;8cA=L5gIQ|<8^1esT!}9#ygtv=4-sx8t*K|J5%HBrSaA=-dgawBVUdq zIiBQ4w%@Ca_q@hyt5^;%iq6*SyG`S@(|A1?ug%SVJGa+(hcaG<#_OQ*iW%=(>cUKG+q~tcQfOq-s1O1SB>`^+Ld8<4Hf1AE_^k z@#bi}9*X7gau{!g#_Or^mN4Gs8gGA%cOB#1qw#uayp4?ayv92~<9*6_TQpv8jTb}k z(%a=1jn_xxb!NO~xBC5-q47pBUU!Y>u4807=P}+0@Y0bkG`Uy|qE z*GS&OjCZD{&t0EL-p7o0tESIg&q`iX1Z%xr{;BD6*ZGn+gz>g%`rP|q$tz&IHn;ip zb=U8bcLC!K1g|^NWqsZI2FZJb@n&c|_ql}Ry}@{AYP=!HmmkUdk@4=)c<%ER$!m?t zNpF`oHJfp70cmm1rO`clPO93 z0-j!fnJ)GH!Sp5H6;bK39@s)keS&z6G~Q()yflq>c?hqA#=9bf*G1#Gzk3d{ub0Mi zf9D;<>#OnBgp@l}<6RxX8>8{ueFlQcouKjD-$w`Way8!CkaDMKyz4@E1sd=A5MHsy zyCH;Eq491E;Vsj6H-+$4X}p_5c&jzuEg`&%HQucuyfqr{wh-Qp8t?WH-a3tUM+ol$ zjkhj@w_fAj8N%DB@$L%YZPIvmhwxt2c=v?xHfy|lLwFx)y!%3UTQ%POA-o?n-UA`L z?HcdF5MJ`#e*F7u2(OXGdnkmLrtuyQ;dRh>kA(2LXuL;5c)c{Yw5 zJcKt!<2@0=o1pQY4B_Q!ybU3|X&UcuA-n>O_f!b4SmQk%!mH4D8$)=@G~P2Iyj2?S z*%01pjrUv#?_!PjdnyZPa-G2;ptg zcrS6oc>fCFeWdaJ9m3nH@m>kx{h;w)4dHFqc&~-uAe7_ z@TP$`f_R68@YaAgk$8uP@V08aBSLsX@AdUbz49a1oxC2aHQtem70lbL@g{}vdfn%j zn-juYrtxw^c$+ldQ6anz_xt5e4&fDRyeT2P^%`$#2(Qrtez`}7@TO_JV?ucAG~Tfx zyzLrqS_p5#gT8&oh49vByyHW7TQ%PF5Z=(g`sL0D;jPwqc_F;b8gFI@uh&EV{ds-} zZpM4uw;8+@r0={C-n3^U;vV9iAHr+&oU`wswC{ot z-UHyte98Mu2ye{uKJUU1-mBm}O!_Vg;jR9=UyqA5-rj7TJ@f^<7um?M?@*1`oAHWY zkBDYe?temf%QW7W5Z-Ey_kIX(jmG;Rgtt!PeHg-9ukk(#;ce1*ABXTZYrIcFcw05z zry;!U8t=0ZUZXes{`fqE*Focb5yI=G@xBb<4b^yCLwFN3-d7>KX&UeA5MHsy`zD09 zOyg|};jPwq--htkXuR)2cr=A-rB1@AnYiP>r`egf~Is{Sm^Ort$t8!YkHze}?duX*>~eh;seH z1c5gtuAarG)UdYP@UK+1q2ydvyYZStppz#`q@TO_JCLz3Hjn_1Uw@l+T3*oKSc+Eq2YcyVq z5Z*eC*D{2+UgM>O@HT0@Rw2C28n1N-Z>z@JD}=XQlF@(2FQC%@lFomZPIuv zLU@}s-YFrxts3vt5Z-o;w=#s+XtVEst3r4kG~Q_;yj~jb^bp=qjdw-}Z-T}UOs4B>UqcsGUc{vUha0$)XOwm-WkdvcNh3HOT#M+5}XkQ;Z9+z152MTm%s zCMQ>-A;BaBL=;3+L@kKade>TuptiNG+J3ECw6yxQ)cUV{ezw|bt*y4Tt!-^@4h$i^)bCkU2dFPpTZtu>{&d%)Y33+!aJZ!y9$a`4fVT)Qq-V+KBTR9T)4k#pDbD1g^T;XNO~ z8>H}l9Kai?@LmYuja7L6FMxNN!uv@8uR!6w7{HsY@D2y?N)_J!1n?>p-b(?zN`?2o z0lZZT@8tkqox=NR0Iyl$VTmB2|8*!lT*@WnZBlrcawp_%Q+SvfCFI?p@Nf!C$lIgv za0n#i-Kp^KGa>JOh4;$<-opy-jR4-G3h!3|yeAain*qFo3h&neyh94_HvzoE3h%7| z-m41l?Ev1J3h%c8ymu7d?*e%5DZJkY@IFv@?*#Bt(5d!${|^DYJ__%T0lYy9?@s}| zkqYnK0Nz-I_vZlKX$tQz0lWf*_tya4Y=!q;0IyWx{Vjl3q4545z^hbv{|Ml%Qh4tN z@ah!aKLdEp3h!S5ybgu;?*QH=h4(=KZ=1sVPXO-*g?A)?w@2Z11@P`vc=iiC=s3{l zIrl3(19M{v#B0F(*;1Zcd>FhDJl6YX19%~*qEh{R@LnD4 zuc>Wl%x*v zhGPtyduE!2*vdDi^OV-&u(gxD*LBmuTMykW@XXnbp?NlfC+#jhy;W$i3{ z?_hZUh_0@KqXvU7a@#w~m^HbJ9od`to7mp)k7M|4?#=uO$&|gB{}UV0x%Ei+Bb9%> zEdL~@{AYI^JaFjgX-*9Up6t{?;8R+89m4yEy^9j_THyBq{+nvTcKO%i*Qm!2Wj%O( zP>&ZshI%~i=?Bx(4`V$2Q0(ak)9HsXvLA|%x*z(GADN}2g#Xxm_)z8`c#!R1{WNb9 zUi2?s`r>fcO$$dE=EBU3m@#o-xUg&CsEApbTFQ0rSC@v3iTj7W-o8cnt+AKX# z@^tCxsphN|WuumcXRTN;YE0)e^h@Nu{rf6X_wOhRi@tI-3&O%Xt(_C%IJQP`#=y>k zIF79moGispS9TrLyz_PR>J9MD$dUP*ie;PF$53i4+Er}O@k2)swHejD4D~GIbuUBR z%SM^9?q!+pSC8oonWd*&JIB5^|C9$O&02w)J%8xOdq?fxKWoK#U3WwHE(wWt!nKoeNVJhxK$u(r4gOiz*e6lXTp{!q1}hk zxG`d=)~lHUht&FFMOfC?ub=I@E<|0arqrir_7iG(|DGx&5|67hmDau))Dz4ruw0bYr>Rl%5U5t8sN;Jz}xSY?h7MF`u!Y!^CP;^ zm>73NuP)tjFib}n`Ili9XOf5PaazjSIsR`4!*q5FBi`B>{#)rjIX(nhn~X2?w6Zm< zo=s-!SPg5z-*%uj;0}C+V={i#<1G!X&`xHxcz;R`|8G5u@fdG>1LCLS-6_+skGM{z zZASVSw^;={7qdp_>yWmIb@F_g@v8V$NXF>-h7|n6-`g6m+VIt% z6?%ve+UQt=JicT}F17Yv+}JyqZ<`+VA+}(5b$0F9<02Ag5H7^Ojdu zm7Tq~q_TX;;-U&F@(^$2Im^l`=T(&!RTfcchxtX$D=EQo92(&lx3mc9&!y;*sOU_$ zfX|#?zw+PL*WDF`$|;~-(aQSvjzz6?_2`uo4ZAArWHTm{{wweQ=}TLuZ}8BAP+*WyVL;VB;`hBN)|2h34rYe=3#%pf;lW)S zbHB9oF)z1$b!%G(Isu2I<1Up?{Ak82i$7oMWjf`MNmAKZH_2^(yFN7OyhqOQCTVKn zrcZZybpsw7KDzpi|9E+hX`UceZS2kkUwP>H<^9j}CTMPLX+-y{jrYY^zh6xMZOLIT z(XlL2r1CdR$_82d;`mW#9{$X$o)lJ9)jE_SKM(CUGNr_}%HJd<(|v2!|Nf%znU-O24NQhCW;{v_A*fy&ZDdmnrCcN3v<4#Gb6!H`O3)RLTZedl|jl^HLR-l2!0wiUIH zlRQA0F(}A(G$*faT~j}KT}{in_WHKT9Zi$l>esfmPp-|&$;nwCYpa*IA#ZyAv<-DY z&GoVN`l_`TH%_i=YwE0TYi_EUY{$A9c@a+MB%F16D3jXS_Q|F7HR~Fy<`or}v&!;l z<)Y>Jc{wFi_~`unXvyS~Nt2=_7}FZ-TcT&TG;N4>=H+Ei&CboPs9cVSwU@RvHLmW6 zPNgjnoxznSS^&4XC(ejq|j<$7c>RUSKcWrCi+SayMM|~YLLak`Ps;c_7 zw$`?)D%RJ?cY$Gdmth|Uj7703(wpr~ZC-smw)@FwNO@LnZmqqzq_w4?sgY{St7{l} z@sT~`dX9fL8k-DbDd6(@+K#5ymUd?Mdy2X33O_wYP}_4xqvYW#UIEPVd)-Iskn?eO zY@Xu!$hsEIOQ^zz(JH;f6W!B(viBqVi5N?dg`ZR(=YCS#x@JvNN8D)gW$7oL=$`hI zUw>pj5#!0;V=$gve?0ohes?@+ukTpe*4iNkdel`sKWrF(kdESw?`coTHH41$)V#!wW)n|Q$xp!ShK3!xF*(qv8LP5R^O(0<5{*KkENO$#tg%CSs!9gyY2;s z(FxaWi`la#$3+ZdRjsGY_KFhCrhNDbeYc~2&05DQSeN>nRa`O?EfbzjZN#=71D70+ ze2+VqyxQZEJ}YU|+EjDHs8?LlhuG6Dd8J`&@VKNqk&p99d%4i-lWqd;l)i)FWnM3| z4e4G;i)r}4!7=c{E0OPU=Y^m5c%ie*No`E^HH_;N-*cjS+T(th`220G>af>h?G;<{ zwKdLFraH3qz`1)}T=t5GPC%1|x8M(s++*OO^eUj^&O;}<9@^B>)ZwfpP$N@?4dX@I zMLqF7?W6roemUZvcs+xhazb|Xx~GU&Je3>+Pr2!M^prB!QyS|#%E?(eVjb(mi^!

    j+Pt)H#+%vbfaY+H(Jru+8m?R z%c8ovw)%GAOjK{fs4?vxah)lS-qS9%+2oTm+;=K#jy0+$zbkxnn_{vScFEy(8{0eD zae-P>-{z#Y#-M_X6&wSXqSsg*cjvHa9+xUhPFuX^P|XeF3qGFXlc1-4=fA{o zr27e--F$Su!;xos!Wu#j#lP^9f^9%lQ-gK&C4n1_6!3-Dp1Dt3N4HP2SIb#@C31YFh7er<7kgIVwfY=|*Jd3`PGTyyl`e5-H4TlC+w?|%0!%L>)!hQ^tL z49mz1n&tiDss)J*%|j6eM0Ih4FEFEpN)JYSUjkxx#^ zzicQa|HBmgH{-eI{@_#Q?|I5R{8+a3A5i9@g_gCz967|wIL}IJKiA3#UB1$?YMwl| z?Sctb--&;EN&JtBTrxg1+{}dAoFW>3zo#O7k7Y%^WuozC{a}KXG1W>dnL?E)u&g;F zKd_7wL}Bms6gKNv7WOw(*pk0sQ)SxZD=n+aGDe9qe&18Zk;k%(*M;C2HI}u=95>X; zsI}5I*HELzEUWQ~hDlc6(;lyJ{)cNcPYj)C4uor*Dr)kirzWQ!%bL81nppMbgrPI6 zzBA2mruuKrFMkQmFHwODr-e>4Pe28xiwb<(Q-Qo=S%KS9P=WR4gdtYn;+MpK^Q`{n z2}4Y)zty+BtPRCqKGz&M$1==*{Y3FShvt8Bj%D%RNXbI+t+bzf{_rJM#uw;^m2sD4 z?YE3eL}BmrwDp){S=ehWwDs9m+GUpYnq_o|^4+hN@7Olx7c6Sb`>c#&pLU#wnNA9u zjlaD&`H?dZKKtqU`Be|);GI6vtPMThg^+^wG>j2_2C+yuk{XFb(jw`RjL68ytjOF* zNo4*o@a#~H9|NzrofQq-WL`M%ilU>jL7QuA8#PC1D9VPiwx(b}Nf6LwuTA7x!={aD!8WNti48?>+}Y-}`l9;FRhPm=8sJKFZ3 z1q4}_#Yby{E+u6-&L$h!+g%>Tb#;F{T97q#V8#iNagpl_vC}q`Z5RVXkr^2?GiGJX z9zJ(?O9V+lH;08HN|OG@03$vbX+=^>cuisC+QN+Og&BJa`(mIgaBNuHuQXUF(%;xo zI2>yWg!&uT(eF=l;tlV#p4G#xXMLK}NASH~ZN2iSJfeERC%Vt;sE=2)S@+gIrm-QZ zyqub(VC2il;KLUl;WrgX<6g9h1MyY> zJZl&k>6lGZAV}%65Q|3~ij1tGONWXYG_1nQOo=)p_@QbHYwjKQ9 z>2z!dns$ozr$;6h;9@}Dbkg>5Q=J8mwnHmC&z5eonvm())Jsfy_D9&Ht+R?v@2*aw z(xYI4N_!W*RG-~+-XyfQ%$vk#w-Y6yO+X?S+6d%L;%rhOqFYDWkD(AfTLp;e){*YV zD@^YlVxrPBX(D&J=jx@#-T(6@pgU^b1aWtFD1qCGbSuT1z-LjPk`$eYKb7UopapZQ zsJ*>@4Iam8W09fhseMd(XGm?{^bN6^CT7r`niL}p7t({ON-_V8b#}&1k|YyL${48l zLyx2)OjEH_2_O)rhcJPp6y{6cIFuze7jW{5vdOExGF zUI>}bk-%r+_bdgk#P3B4rv2YB1vlWgn_mi^7*_L3!E?=O{Zbfh*l_EY!nOjt^-E#b z0lW1};olZ=>zBelhxjP|Q84ig;@yzscoYbK5i*A(fgi^25(R%9zt2|ixA0p$a1H1hdVf2XZIfBmlCj-Y6d@At83eE+-Lc!C4 z-SVWdxxn<0Ed|p|V`adu|D>@+z;5}{SS4_gpmYBDzzY;y1AL)^n}9D-@LFKEKhoHG zVAp@s*%iQUf2Xsnfu}g>)7cHcZh6w#&A@Y&czV~cc&35slg>U5T%*MA1Fl!_SAaJt z_;KJX6-@8Yyk5cd?nwK4Tx6f#nMh*-1=Gx6^sc}G0&-06$fNOx0>!@$Ok)BC!t_qG z3;}`rFnSkQx`X>NdIuJbF%(R*FZ%%44p;|+k;cs3JBuJ+XDL=BJ9@MsN3HGGnW$7uLu4Ug6E zI1P{2@F^Oepy7!cK9$|%sox|GpQho{HJq*C$r{elaIS{)G@P&D0u4{m@KkoUr~K2{ z!ycTe#ZTAp3=PlJ@GK3_*6;Vh8JsiiH4VI_$>CKr~Jz_yj;VT8a`XYD>QtLhF5C%Tn(S6;qx`T zO2ZehU&-=s!mv32=i`4!Ow;xO7=H)JYt0!Phgq(~bYV0A=ZD1-U&(QV#U!S4*Z|C@ zIwhtHtpPaS+$1p|%fi@whs4!9-eg~r_$H3i*)tN?aU5bVdH5;pcM_k><1_e0qJ>E* zo%04^!w6l}1>qB9Jk6{$1r3b!I%9~X?*GfC6+*+z1`jOj#(WCuTkx6mv+`j zJMaT;2eO*V0a+*I=O{h!ol@SX+PO~JX_0o|N8Ao1Z)Zr}&XA)iJtXxv$x~H3JEWaf zX{S=!f#mHB$=ex{=71r{A}Qyqb}&%zen;c*_JJRFP&+}crusnA8$n1eqV$l<)$}*W z^q0u=@PD2jlBb8{=^;<2^pJT{PFL;RDDAXKJ2-y09Z23!ki4HDD=0lAZBurRgPn{G zqjI;4F(>pH^e18HVVdi2A_@I7Qh!+LUzYkjsweoRBw>eE9f-eC>gig9^t+_~1S$vk zyk5}f5(fWVslS*c^sQ3Q{R(_~6qEF~NIgA7Om@C4_1}^DpGy7jrT$M+pMi4(@lPZP zJ13DuzSE?>Tq9zd-8Glllv#ev8!amik+y{&A^)PU;Uy{hLz%cd7rE)SqC9d`~Bdd~->n9p*{> zIZ}VV)UTELtx|uD)ZZ)hUz7UBrT)iK|4XU=wbcJh>ib|Ir+l+WBHz==T8`^4ylXwuZ{Jb!*w!lCc%J{BIuro6r9i@V`^|->LlXH2!xw z|2u>K&CL-)q|Oz|b4B`GVIWsn$Q34Xg^gTcBv)9;6ISwM8HANQVI@yk$rD!cgq1vD zB~Mt%6ISwtm3(0(Usgp}$ro1gg_V3^C0|&{7gq9xl>%XQzlG4XyU?=BAc<`*#DLO>{u4rlzgF(~j!6bZvdR4Pedw8EcERG`cZs@$xg+ zXt(b*c^X4@GrGp7aotFt&XJL5K%Y9gDV+{+RmwX?TqAKU>Apoul9YR7ZZhQoL8

    %iex zLl1(p?Dk97bi`^{HeUYcDZS!xad93ui;ML*TwJU+5bD_?+UI!lv*L5i`q7+YFfP(F z7R1GBgQH$fM924jWjQrxO>1*@thp(M#-&tZh!ew_i$x#1SUP~KkYk^#a7H#)<&19G zl(Tp#MRo(8qNIN9Xyg6bzFPiDH1~#g((Y%R5fe_ALdmcq=Gdk~p!*b_aw3eju z-UEKlhevBLWw_pW-(k7--qLsr(coijBQlPXQ68kW`=c2RUq%r!*h%Q# zqRRUkcu|`KY4hm%Smpf$ylfv{qvWA^MTmI&!`637o=rOd-gvvPwi5CxjrW^=SSz4{ zXhG+#zy%0jGwX)8ae!RQ>V|jUpyYTz7{VA|)9S`v$8g5@npHQvR4k_QHK}fRH)1iB zuQ_$Yn|zX7Q|g9y?#YbtHKT5L_l}cmL*4NHdJ6Uo*qyI%^?sXls$AnyIP`O;<_DMK zLiQ?+87_jT~Tl>~1MoSu$pJ?P~-X)ljKdn3Axm6WXMGA+?*uukpw*2 z*dZ*A8BD zTnT3 z03N0$aY5((za)A825(ZFHO6#%ZH#59FB zc8R$6Pz9Zx9+xg`1c1sbP? zQ^ceD(yF}q80z;uV93dTr(k{5c4onvV3uTdvuA0X))Ezm38_3Vyto72aq;^X0v+@S*{{w-w$= z0laq=-k1R1`wH*m03KWF)^}_GFQV{pDaV6fyJRW6@d3PH3J;fj3GGD{-h=?&1cf(I z;niyWn*-i3#8dxf1@IPtw?Ojx2k>?&JS-9LK<%RE`?A6t7{H63<>rf}1RnhCtyXx0 z19*=pJS;gRwD-Qk8ydhXT;`UK+L3}^`L-*(;ezJNdjY&c#8ZEa2;gNcck?|VfVUF7 zLd26jEQ#hXUoc(gZ&c$tF6%ePJAMR6~g{DgS+`HSr7yc~sxB?lh-c!dfN zO9=^iOBJ5Ie&%PdTH#F&u(wv>r02n}z6TT@ zF6k5UUQl>b72apH{(W8Hl?CwLRe19Qc=SMq?Jo-gcv%XsJb)Kfcnbq~ISTL00A8WO zs|esNRd|a6c-0DTaR6_v!o#VF2kKwFKei}544DaeyA&RVE{C^I>)(69qkQQ2#Zbco zVV$>6;bCY<$a_TLRR-|BsqnBpC850o3J)%pkoTOz!_S1g7Zl#g0N%?A@7w_1>k99@ z0N&dQ58G>a@N4IH72c`<-unvg0)i!5;p1c%zZo>!eTu@!D&f+z*3CyZ<(LL4MARWWNnQ@=B4J{cZ4nvw!iglSaF6 zOX(@&@#4&W_(o|~TXAMOWE3(CnFDFYnDb>+`-|NC%f`!6tD{{J=c}gp&MCgjd~n3c zES`0;!%7#dVO`&m{9zw-#q;}z?61ml{#D;Q#0vLsVNap7g%4zgs*O9$R(1zAg7WXR z#;4!pq%YpVZhz(>(5^k@Y&nMnCIQA3PUvUzsvyw+v6Ym~PueYsb(ez=;rGx*oF7ls9zDN%mcg3NFe#m|yo-=;JR z!+BkMM=kgQGe`e@=!(5;|9)dQzP~-Oc*lNxAD-Pbzw7WV#XCxOckOx=^5CIiT@^n# zcuR4Z(u!~5&bz#HpEv(T#Xeg$ELJvY-tMx>Q=3Gp%w-?M%CvoCc&aSS?l5-k#kYy=J}P7;*P2|LB991@rEqPEM{BSM*G9Nj`p<|c z%i`KBu9e;bZM?sxIbWRiDao+!borEI*nhfwN;2$7mrqHCz1HPZ5@@L;{QJ@T%jTk8 zXe7XspVG&Rcf7fK%dRcULe-@sQrJ7rZv(#zcNH$PV(;vZ?uznw6HgHGal>In>|?~y zWU=BM@9fUnmBmv;VI{IF!haXycgn65{(B264U?DBH<#T~VGp`2mD@_gV{Y3Fj752S zN73GWV}<;8A%3UEw(#Fu@H?eic(YF{jVSc(uR`8mPkxQsY15`JJHXcO_zgzo^`SRPnK7|6>~|b)JMz@^dY$fc>m)ra!t?vT^?m4ed=t6} z_w85n6Vw0Ave%;Q)i`yF)v}aF-~7w)o8B$n7loQ8CXCMNMlJpthIwUpc}aOyS$Wx# zs>+qPJhIHKs)oK-ZC<5n^6-sZbDOHkXCceHTGbS=6wACu)l9(@#JpD3Ol4uq+^%Y- zu~f^vPSs3j5zE}6YG$xB%e-FIV0Uo3W!~UX<+2RRywRh|V|^_1GagkwUOj8>^r#A0 zKg-oxE1xC^yzN% zX1g=g4q6l&b>aiJ|8%A&vE4y;xmhn09dx&<;T?33s^J}Uud3l4^m$doJLo=D!#n5; zs)l#a{i=p{&=*w=@1VV^hIh~dsz!9sK97ob(0-4KchG|#74M*jJSyHn4|`O+gTCZZ z@eca3r-SCyUv}0n?mqEXo;Kzkw9L~%U$HxbzrR5CuKE#gr*~5WKjQ7sQo8www@dVV zk~`r?yj{NY#2Kpr3*y()v|bp8c7Be{T3wWX7>>Mr|vqPwIA7YK4`X-~mRRdMskfbA;PL1LwC|aE zxV|NZm!aW8mXh0Wd_ zDTX22<8FASHv>|e*EO|kUP9G1j8WW6ys73ZB31< zJE9Y6Cq{E;%$Rz5UQX`xXl4C|SbMY_k8`)JTT|cCLBDHT+t#+W#X9Qim=P*=9BBF4 zSZ#fP2kp^3$e-V%E_Cn5>_U@!+l6Q++Hp4q(W{1N+{e?lVtHEm9xhebFuoeHSG4_j zJ?b(~erzs7lX*Pz@~O*w45NOG8s5_Y|tCVdRpdxDh?*9kuLS{y}!nii}}y+tA#;wzm1=1sk1p zIw(79V(aQuMF-x-LnT+frR`nI!`jZKx~9&iI`z}qR5^7~5)Gj)@1%Jl?X*=Ee`tcu zk0bAL1nmRoYR^K~OlZS%@COe<_qNj(A=Be-KJ_E%wCmfNI_gVS$J&b8+G3aT2B!KN zMvOXFi|tYO{T%=JyVre@Y`)*Q)Ey@{Z?EI!r7CdUSM zH`R~nM5=fyo*)x0>0K}BXRGx&DGjdDrvLQ|JtGh<#2?0BMU{I#t< zR_AqQs;*(&6Cc^5zWh>vFWWcUKa?-qiF(7AJ(FO?mwi`r=rNlxjn4SGLvOosDKb6o zT$z?E$y>$gue_zBzO8NDS~2^i3LC~R{Gxl*oj-`5c488-5gSm-_$#Io&KlxIR#Z+M zS!sq4F2Nth&ggCLnTJe|JMW=4Lz8>RIhEIasK$noV)znz)PcqrJ>^0C79t%NjGfin z9z>5&9d{m7DLsh4^-c~x%EAfN*)UEu>_eV>$%opb-gK@Jf2HF)55xc^Mo(D*yU=mN zl7(6+6TZHH;YIj^SHbtTQyrJXQloUL+UELLn=>dWZY74M7$2H^Nj>UNm-XoI#J$aT zMTt+I#Nb5(cMA8ol%5(=+-+%;&p7<+shp14_Ow#zXIOD5rWFpmqG4kzcP(4rqu#X3 z@R|K%&Bbparo*!k<2#7Ot-4fI$ueaQf0%&=WIuE;(FAXzTh)7#kon``3yBs&u7X$D|!|;h2iNboW%`>uVO-APbUR~ z^-xXtdvCF4P~>9V3@N@xNm-}&N)g1SMP2}l8i!d%=tZNiWsR|ne}+vH&9KK)tRcs& zSXZT>Sabep8JCN4efASluDeCKw%{Iw-e4yBao90yup7c?u!%b??cZPg$J=WzwTy*gxOmP}x)YCC>E6IIl-AW| z+CZ!C{np@9t-ejxz`j=BFIp#sI?ObKt8PgUVYG|79Q4#>)G@2eJ#-4Yj@M-mIIZ7L69jy&2 zleDqoXl+DY8y6m}4ch4~%dzrU+MrFJvK-5fwj3XajgO;WXs?i{%f?MdTNm23A#7~e ze6%*`X1TO+>CxIKb!==hi(%wwjyYNlmVIlM9HkAqQ6byZtT;*=f#on0j~`LwZ3kLs z9k`jsk1MVF8Mw3F*Y+qR@-E0N_;q`$F)Y={4Em*4(~lL@6B5E(h+4Hb)8ah-p$AmCr_N1Gg*EHoo+)zn0+=T zm@*bHBjXI5sjcy>9H;g01ZYM&2~%eQ;%zxaM%K`A{qQpEEpR+a$yjB1v~tn%{Jfl! zyquhz==}U>$>fqrlkjj}U43JHOZ4oPrVY`~ypR0+4DG|_3wpR#vIAWU*}*TK<|lUW zi&w9!{Nkf_Vo1Muy7sWc(Zthy-wuB1yNmCx{4|fZgP(nxquaqRp61_n@QbIpwH^H8 zX})R)zj&Gx+rclsyYw`dwS!-Jwg1O}DExoG?k2-XE(8s2`Poofrx>T5?J=8Ww+xJgI zw+m>?x=oDVaP8Kc_5<5Izum0#iZGEi?ftZwzB?D`ePDu0oBV95&%QG%soP4ldCMmI z?kXbsDEt$)X%CJ~w|9yVV~oR~4HgQ+*#bbUq7(6_vYZ)1Ag!YI_WCt=NWP6lhNh?X zF$Y5_w{0+kw!NkpVH^|Qpej<#KVuor4JKBlbEUMZ8tFYDm#pyuDw+D3b1Q0mAwJ%+Dm1> z1$OPFvUh>)V44y1iE0n;&s93aG}G8{_*Oy%l?Aq(g zZUCm^m4a#ZWj6z#Dj>(V1J6+K=Yie&^yA-$bM5tGUqSpy4!%eaPGud0f)0Ox?0+%TGZ@`%j&SD<`yXDWq z%TC?zkeFr`-l#0bJxW5jKd{?gS!@{aWW^p04{rWhj9$m%_D2>w9oRm{l0ACd^h_oF zEMT|({aG=v+aLW|Ij~#b{%k3*n_qu+4zOF_{_H|v*WN%@4{Qg+9K_ZDUnmuX>AO>Q z2w^Y9Wgcv@n>;wg_IYp$JK(_8V z;6CgQ5AMsp?!o=ok32Y&z3stS%yOr?C{KSj)`JJIsUAF#Re10qcD@G>(eO|W57Y2) z4Uf?92^t=$;S)7HO2eZy9M$ki8XlwJlQle6!{anOUc;wocmiwmwAVxppQ_|fqv2c)=V>@!!vz|iqT#6;o~GgH8lIuynHrv@;n}R+(|&U_e1?YSYPe9t zMH(*FaEXRXH9SwlWg4EZ;RPBl*YH9OpQ+&r4KLF0Vz$N8K1oi=i z;RX#iYIwDVn>2iphA-A|vxe7bxJARQ8eXg6OElc3;dTvoXm}la%+o%d8eXsA4H~{w z!y7exnT9uM_;L+jq2bLM-lE|vHM~{BS7~^ghOgG}H5$H_eNVOzt$Pf>{PTY$rge$| zm>>O7Vwy7z!1*}U67z*3j{C3?5{vjuHd$g?hZ%tR^c;yxIqt{Kl6V})1K0%;1F|g4 zO&T@aDKV{U3@``s%fvz8VQG$8^BJRk)q`Hf+>qq|A$^$2zd(FrkIGNi2!!bk4TNb< zOqj0q2-8~6pj15JOA>8D-Qv_2Jh~dAF^EFi1 z&q@8QQhy2bvfTK|%YPntRF4a#?2?l2-n7%-Ceydc^r$aS4@uXkA;>BzGtkI{>07xZ z=^BXSIBI;`-tE#}yR?UPCP9Ho~-cQUl=g7EaC?v|$qpp%XGppRCR`rD1IharlJ_qpKQ17tKSPk* z46CMyw0otr zi}9D+g&_X}hi*@2|BC6Xsfc`~F^ zu7|`rX6Pz$ZVo*t#}nu`QMsVsLK6B1NJ9T#Qcr7eq|d-NZkMB=ifU{yeF_ zQ0iNy{z|F8TIz3=`Uj={%ToWG)c;KCe z>Kml~Dyjdh)ZZrc4@v!#QvbBnzbf@Kr=)!UBK0(%p?t@ag#J{LD9=KvUnTX`Qol~> zua)}irT%`Ye_ZOnCG{^#{ja6|w^DyZ>a%bnr+f#IM82n!M0w^)eTmeskowh9-z@dp zrT%uQzgy}LNc~Tw{w1mZyVOT8pQC*HkVL*?Nh05=Qa@Ab&zJf&Qh$lmUoG{YllnWP z{t>BvM(V#W^{-3)U!?x;QlE**9OZiwNt9B*r+)@l6tAyySSd#2D{5zFA_7TO99^7~>4bpOqNn1-h4ou&A3Q z+lS*SiP1hBS4&(WaZF;g509^r812Jxt;A>_j_V{w`*2(@G1`aY28q!=95+gg_ThN7 z#AqLmFOqMTf!d|aYj7>*N#%JSTn zma>|byp0`kH_ykGjIGFJ^fym=U6A}N1gZ1Y_rNIn0%=Npr#tbdaAQ;X-)a2sbjkF+ zDNadda2h_AMj%&|CRY@vsonq1IA`XI1O-BfjB}^*-1Ph7oIlNu^4t*TQKF2#cffhP zC}N%{VxDZUJf3l$C`O(rMxH1}o@jtP(E@qX1yfkb7gq9xm3(0(Us%Z(R`P|Fd|@SD zSjiVw@`aTGVWmJ=DG*i)gp~qer9fCI5LOC=l>%X-2sgsJ0m9Ym8y?)4xD5_&l+T6+H_~?lgBxvc zSnz0^4GP(Kzh`^L%xt`(y{V;O)d5I?}oP68VAH`YTD{M?Wm4R z*Veb&0M_iEv9?%CqZ_k!T}=yYwDTj^+eQiA7({B{DpG{j{G^I&MpC+6M@a7j$>47W zaX(_Ey-q`toR<6ah)|o=^)9VT+z4-PyL!Dh+?cqobfbFvi14`gQ5+sg91&GjmE~16 z>zbPDs$v~D9BbBf&~ej#>6(sM4a;t;Z+5Hi9cMjJ+F0v})5cpZ&VS6+ND0PW4=Zl$ z)nmQmuP4@j4E9jmgW20Cy61TkY2N3Fi}OHFY`hnGqWwJ4L+~BEyd`(WXiq|DozW({ zvYb4jrnNa6pLvVHFNi8eYcWE*Sh%N)rSG~5IgGmsXOMPP&Ops`uCMKAYHi7G;BR%L zlLdFl_SN!NqKT@mr#UVCqd6{x0wJ8g_M8`&fN{L34$GYz)1ETb9;VmMJ{+Rk_9!2f zw+lFj2r}3_T=sZ)2Y?Il&ki;Z(|!++fLa%uhs#e7uOI>M0gbmBya{%uGLGQW^0(c7 zyAtqT(Rkkk&#%7!(s*x!hb2fS0P@feKj^oeFYTY)D&t7lyi+vZZ@}yH;n99L)!wQQ zW4QEof^F|yjrS&axCD2C&Fj#3Eh&s)>D~!8?`i+$LLAv3cHA>!(=!Ul~njG&N zW90paZtT4?mN9-Gp&Q=kPhpJT2k3^^dMaal9lsmi%+uxid^fxeld-=tiT?OjE@ON> zy&HR(82tG9csIQD7{vMdcQ?EzrsD|!pYqX-Th+~9o5|Q!nk^1BUd=4NL>|x7c>e_N z)_4}b5v=BW(`?3WOM-XmoaF31lO*rFGm^9Smn3;R<|b!vOkr~M{Wf@aC($nF7BO}x z3EsG3#-2-p_XqI4o&@jSlH_>HOL4pmXI-L`A%ycY0q$rTrL-e^t!DQ+jwAOIvGg6Encew}B!X z!NdPfXa?_*zKs17nir%t3$hiYG>3(~V3_0#1HKObkPifE8gFcqSZ5_(A0i=8-RZl2v=&n z_rSC3F_5zakJf477ufA7LLW?;(rh3l+1sqy8wQ@8uRSjK@uCXP9vA$06BOQQ0r}=A zJbV1`vo~GgWe3|*SHmprmdfy$@nyHw!~=PZBTy$Wwc0PkIecR~QK5Eol^ z`LLAFgJ1b}DLlH@N5PNxy28VfKM#JqoHcH~qXT$bz*~!WYUgMG?_Ka#OWsKVyp=63 zZ%hF10C;x0oE*T*YIS*I19;U6Z(IQH5%5+bp6YAQPyE_1f<{>&dG>DVhhr_RCRtWdXcGg@+~Pg!YyyyafTgYK2!G zz+0>E76$OPD7-TRc)Ju{MF8(!g|{ex_lUw2c^42Om44DaeTNEA*aTNUOyG!9+B51z6dlg<=0PhinhoOcCzkClUJh((c-U|v3 zKONp-&7WUKB;`ZnbElwjtn=PhcDY zvfw0re0c434QsMnYc84`6(M)pwEUdBX*s$1(P$1=sehx<{JiM}LQ|c-d0s`C^NBX( zX|Nmd&kfUS#qR=M+6nAi?7x_KqG(~PmlAGq0!8Bguq zz4b_#r5q{QR6L6MoGnYOj&@ZWY$vWefX8$i6GJOXQi@air|sWya0D|(bZ+xWu`yAK zVO>W=itv%L%jbD=xz$NSdCcQ^l#UwHS-Rukp{~E~-yT{~7T)`VgSU+6yaqYOr~j6d zzU%~Mq^^#3ecRE*TV!2j0k)3Br5upvl;z*NEa^dIImxtJtZa958I@&>qp{1PSWM*> zGlDE)*Np6gvJ<*Clf^PeV_O{Pl#y)-svUOfXttUhjcsdClD7UCmvXR^a`O>huTW6E zMuwcS$d+dwPw$v}AW^SLrP!yPxfvhrc`HsP&0XfQa5cq|eXG^}ReH!^`!ATcO7aTR)|4LF#GdY&w`#vkyB+z``toYlil@Ho z@oOFK^0nY^J5U>N2kz!g#;r9P3tqTq)R?D#bVd|_ zPDy+$GH49JAhkKXytHglRatpO<-BE8SedenEgn@KGc4muk18LdsIk?fDqtbYzEn(>wA#p~A8;ANX3bDLd4zJpXIuleu4X8gMLufOsn zH*SP6!!U33WWKz7aYh#TZp_QJ}sFkV2LpG?&Eq1ZdtxikqdG_1;-`{9#_9QmyL{+{j@-Ho_EUGG7vTRXN zWmWFfs^W4~CdK@Ed}Mwek2F%u$HbcoWeLxm@U!&mfAeCQClgV^CF?rYuIr#@2+CU9 z*2Fqc&d2RC@fVUx6TcpF)i=I0;rX{bCQ>_Fn^4qoD6ORRUwQveU)nl-gNK$<)7sk1 z43j_HDv94%_wvri&R+GPm)PFa*iv5?tz8{!V@4S6>KOjdh9N({>Z?Of_wv`Zcv3|8 z?LV2rmMy!R$L?ADzBk2svR&1|@OskmuJwlpcWuo5($dGg-1gP2Z5?oN9Ar*8Dxdh# zj8_(azShfh${~}a^80PFAh-SP`p~5F9y!OG1Rpae)2F+p>jpeFe0232|MBu1(>y^c z->@zXKQS=$?#{oxztEE)R8_SORQO2;8<|pM8|61BWx7kIJ^cH>7Vo&xo6bo!*ebFu zt6kf<;42S3zr6pMo>VE#t$6+n6DOssz8LHGi|M~DIqW4m^$;mM6-bM z6tW`lX{tzxZB?y^{Q-DyI;sdyHP|Y%E%W=3vib!ZGwN!ao*eE;#VZo!WlOR6T|CKt zbMTV~CzVc4^Rhj)k;zh3k9z3p;-%02ao<{RvWDhX9Aah)znv{JxNgleow>VrOz|@7 zTG!!q!z?95J!t0aeBhdQs$5{_lmLA&s*sH&r2$eI;rrC#{MP}5J zoOFHXd!dyXFOuG&n^D_}+Q&&Aj`UU>Sw(KDo5MW?f^|yrSar zUVCM~5u%3!+$S6R8u>0T?9MXmgMhJAvo~9toM#~Z9e1ssj%MUj5&iAT<*)X;#`^5ODuP|$p8!wql&Y0KXt8- z{y7#Sw90lZ`Jif?Z*361<&ExH=ep{cJJ;>K?p#s0^l^6zyUTViJd7+Hi(iA%;Y;;3 zjGKjXd82#QxxQc+8K%Y4T;L~Qgi8b9>W zc~cqs`T&N-wuArI>)uJ%sK=dm9**lHwjjM`%x&6`IH?i%cyjXGS!D!wvt=ouQqP;s+j3U?L&Z+k+P93+XM(s?s zHjIBd-W*5jSvO8IKh*GB=dK9atA`)me|?N5<+yVA{c5idzqD|2+Tk!;dVT?5SB>^S~8l`8w^z;wsrR{FfKfY1c$7oVsst>Odcys=DuRHB= zIcGSeIBiMmnzdq9yP&CYb>(Wz|5mp)*YW12${R+Zw0I*~M{AoHo3#~(_dISKN9Ue$*<2c!AGC``WQ{hf#u}) zr@ij6$K^cYRn23Cug0$_&}2f)C5DKN5||0QbBTC<&-(9#59hy$*9ktl8z;7%lsD^> zWHGN8fZGkdy9RN}@i-h0Mlw?H{sXa z9RGCt(}(E2K%s}+d`OYP8DiAujZ9Sz8&@eu zg+l1rqvD%Jr_T)$-MMiu#6Bn#S5EGr@JT3dj;II9#<&CJ(u9*090sEC`1FpJksXH? z`uI~LZOIoT&wcVSj@o;RlSXF8X51nv?K5*?wWX=)hzpAccIh#T6l|2G#Q=lh%j*!> zOhdt7J=ClGwZ7S_WiG}Z{7AvBU{Qq3UMYgyDZ+~&-WX~bp_|RVmUWtC{3UFfXot^v z$~ENJmFpK&uBCq*`yI;|`w1)B`*B6P^^?+SdqQZn)xW<*X|~%wDP?<{m+g1|bIaJv zoj(1{QVtVyyr*NB`Uj4)r?oFS4iCiLE^p%xhBI4sW4H zIY2jug(6Cl{>A_!J{f6wQmZ`L61k=@a&4ity)a`>VPA~81&$4C`;`XkZ(LVMhv0{| z-JRu7q`$F)Y==M1huXsKlTX|2Q-8x@Z5?NRkU@hKA8RrajWr+Bh;Z~drC?Oe$Pl9{ zhTTk-pFx9ZXb7{%T7oHK0W&hrz&LD;XXTjWgeO2V(n**)3lLA&6&YDW$MwVOg|=WI zrIdL4VtKT3(enJfoRYkpoSf+V{AkJKl1Y=IC9QS!jrA?jvs;=rL_0tF_Jfhg3pc?K z#2pv&CcJPbu&VG0CQQJ7=(b%UM zfF1nO&$c5W=>~x4A9|jz46BxWZCZaAZLCA1XT2PnXNi@p(hW9Yjvm}`c-}QvFOeR? zaERUoUn0`0Cxu1Y40c21WDdwNC!tMqW>&$ek%hnMlcg>O%!l$})W||>JM}W%@v0_hr z3Om~qpTf@f#9Mg(24fgcc`)%jdWZZ?!oNZmhuQ7G_PaPK{$5}^m}V;8x})+_ z*>~(nNYjk4mpt(i_A0PzFXH*mi)p5@5E{(QKaHgWyZkgvrriuoGo9sl_~~q#ho8>Q z@bEL(`5t}-tMSD5Vb^%#`>-2<-TeEoJ;42C5lpi$y8~D}N=o(Z$L<3b_v!`S4{VRR z6i?q?o9U$Q$G!n<2Lq?e?Y_eB9IK;nMW~UF~f%(4TpyR3#`ggnshgpRO zr?QJZIKsAja2lhd*A5}H_lq8!!T#>SeOMF+l^sH8pV=PVkFE6JOxEbZ{WUy5!vi%u zNW+6QJVe7oH9Sni!!>qso!V~M>TwshR105WDSqi@Hh>R*YGJC zo}l508a`FSlQevqhEHdkJ@w7j@MI0=XgF8Hc^b~waDj%WXn3lIr)hY)hG%GaCcD8? zpIPj756;r!XKQ$lhR@LOTn!g$xJbjr8ZOarsfOoixJ<+IHN1d5;Hlq2Exw$6%@cp7 zhAT9@NW+UYyhOuGHGGzamuYyphATCEwuV<|_#F1Mr#>q+e6EJi)A0EkUZvp+G<>0k zt2A7#;h2VNG+e9UI`;o$eQ2IA0Oy;xB&M150F1}~QRXZ11^mN5Uc4@K{#QUh}lg%etUb5w(jZcGc*+*A?gHB+4J~s%Npvr6z zrj5MbXk6OdF$kBtV@O(Jli8qD#@`h)2os*^q{qZhoZd0#MA(XdAxtK?#HAOP=twRx zkL41R3obEHAN%(x#UQF66mG;mc z+#ckGWCxPwbR)Ve=>m}O1**LoX>Xpihj!)mAh|tAZVz%BrH8y(%3Gzp8`7z7 zt+ZDr?V*3TJ;;lxT#&6&K1}I>zb)ktr2Mgz{{!jRt&?`=OS|ZAZWpqS>_O6Zl}YZR z^pN*RdB2nos`l!oy#>-9{D#|u!#qrDSLh|DWvYzZh-bU#md3!>>C2>Yb=(D68 z0_n8F#nS#_X&>VPw-3qfLvs6&_mMqF-cOLfkeIFoNI!_|L*__1Mao%ferv=xAwo;U zN>QkpF?xq^2>P8Qp}(0V^iN3r^HTp4sb5I-1)q;Y;PY_^{A;EDHj>caMH2dVq#o}- z<$9CK3;kr0u*1h6@aIYW3aO`W|B{_%soyO1H%a|xrJnm6>^v>?v|K{=e@PPhze@c- zq@KS2L;BGqVgF>3;M2kc>FIkuq+cZU7fJmlsox^?yQThqsoy8{-9WLc@j^S7z;q$KK}6dRTAU)M73C`K&&@WeK?*X zG3vwdREbd^j;BeC`f!YiOBUHdeK?*WG0s06W3hwBqdpvC-zmo^49A$La*XG zhvPFOMtwM*D{+p*g%T_E;XKrXOO&5Wl$%SGmrInBOO%gGl#5H0hf9=$OXSZb^5qiw zVfaWCD$8?QHgt3pESp*qzZ^ZbWNbw)qrZ6~(z6In`h21HE;>_0fr#)fGE>A9Eh2tV znOIYKuG1WD+)^@;raRHv(lJHO;1+Uo98RJYV{h$QrzNwJSEX$y~2!JoR5oB7UQ$Q zZts|x-QLlLH{Y;qzJ?=OuB&N*jdtPfqNqx7l!qW(Usc{f`Kcob2l&6@NFJ{^3a?7Sk*caH%d2YEH8s~& z#X8`{HS0Ra-P$i*(-Es-*=_aBivN4Z7jK+4#&{#OaV9~e&sY=3j2~~}DEgQaM@TsC z1TeiW<4cSme|%{P#~?2|ejM_PR}TK{%5v(qn%3s*SaVYhok$79h$KcK7YkoquQf|-o-xluF!ak!Q0@&yIt~-9S_feN7v$n{0V7X8$Djs4`hVK=;IaPh&{1H0jk#+oi)=j(>| zBo=)6x?MNC-NP8;>v7%iW@Am6udj8(`}2v6@%6H9cuz$c71xt@B*8lo*O|%i zz6su)N!Y8*!}?Sbyg!4NjJ+H4le2d!2K;35eKtv69j>>NDIe|fNhaUBz`H+*b}7Pj z{g;#A{RzA`eR$7nesvh@1EmTN!xs-aZy44OlHsjNl6P;Cyf>5NO~ATFGUaPdlJ`iG zy!VpiO~-mmGUeNpB=10yyp-Ag`M#q0!2<9wbi@Unw;sGzaV*Ak-izSTTtyE$Z`PdT zcwb18mx1-GWb$oKlJ`oIyb`RJC6n(%N%963CTH)mBzeCA54Tj}g5DpCijw1f1H76z zYmEI?^Q+;-4Bw-Q5ASKbt>8uDX?(vIs7|;qN!~L_^4>_2XO<*azA;Jiij(BkB+1*F zB=5c?dCw%tdm~AniNP=G^rHJCWP0b%W5C1GdtA_Y<={<-V_{uhvv&!2n2N;(op*bZ zyzhcX*K~T&?fnxxzwuP(O_;~{x1PGQcQ$y*LW1Vd@kYblzXV!znH< z=)BX*#QheXsPoQEz#E8u3yIIPa}!sC=U2Xo;NgEKd=tD!B8+_#n(b1HOB|L9QkuiU zSh_^qe{Fyc`S5^bY>~#>qVQ4_-bEVkR)uFNylXYyBjAyrQodn@N4wY6^1ZCsqcsQ$ zRKCL+?_I?n#Zw^pH;p%Jshh8z5Ao>UtBombp~Ax@DG$V3pz&6Nhf6qKj|@TM`L=4j zEs8x{y7EBw?$UVsz>7jp?a~+jC=l;SjrSaQInWaim$*C-@8{s5JvU1gdmlWtUZf}9 zA2oX^X9+#oi{c*zKVBb&caos_@&+lqF#)`h3h(3q-dKezqj1_ba9f(IAmJS?5?K;_f(9fZX-n>Q$cSEul>#KME0y+^@YiC8M%5JBU9s^{Bh zxts6M0NyI_YleTc>OT=tK-S5;C&NgEZNIac%wDm9yA`s6E8b}cfZ1$9Kd^2;pGJI4l2Cd z0N!DRmlwc$Q{m+Y@ZM8+1p&O2bKQ2C62Kdz@a*{x`Jdj-V-+5jI(YEo6)3#v0lZR$ zHzR;osqpN15#^hs`9Yn+J5#Zz^Ewn>MF4M`!dn!;+oSLn2k`D!c$iY~;8%}F72eVS z-a&+aqv>1Q-c9;iN<>pjeD67uYGM(c5BT=lcO@^PMemWlQ%6VH$NK9;X3tiG&*H! z!HhhvuTI}QucFL(9U}5H*p2w-hKh&8?*d-h32e48%P@}=kBWBT%hgXAj~8dA$D&@BDpKcbX?%#261gp-le?{Z@ zlXU*Du6rbZSl4Uu{O{}hLu~Z3UGcnMIXr32;iVj*ugJS4u5rF*U(CNhpSA3RSjqN? zDDxHD;%a!E#%JIc@A!bXg>L(+E_cV_c}La+*?n2%mK|yKxA(E)E+Li@KI(h8syYi|e+Sdq*w)0y9Vdedvm% zY;X7>89STDp0zs^%UTw0BK{n%Dc*5#ez=+N861aJ%nP4&bK$P8yY~NZ{^t;T=#j4Z zKR9>`^k!sN*$?L5QoQ5Pp+7@+=oUAh{ripKrK5^>lmhDHLx<1UF{920RQKHPN zx&4K_%oVa!O3hR60tq(iW<*`2OPlR3T!(Ic{tV2iEsePD7K+n;l8&dmy0SyhY(3W7iuk{}3V0TKuhLV&1f)*FaqGn;{; zq9P(LU{pj!>sEz|b*W2h-KtcrrM6Yu+G@2`+gj`AQnjD$zcv5ootbm)oVhobQ))s# zemzRw`@HkaJKH;R=FFLMjw$Pk<6!Pb&!zAJf0JD=92W&Kn@c6}e_3=M^~Qp2g+uQe zv%fcShp~I_rn~%iCq`qm8E=qxk-rvgHO#`3XRf>}F}fkW?*vD`Z$c8=*IRhY-jj=Z z8~XOH7BwRN&fB>KDI|P3|JI^Cl)}<5Da>&!sWF#HJ7vAk_AS_1hFlfzESa=$(xOSF zlNR)rROB{3wQ`}cus5kZwSjU_v~5x4zTTzC#kJS0>Dwb?FN#|jN1Trug>8&0YwdU` z4fFk0wa~}33Rzk?f7`V?OJ%H&8%yFStsgZkoK)Pqup+fFa!SPcs6kjNuK34V5i6xJ zQaTjpV;ScP)YZ^07jK+DW@;ZZ%XvLN=G4xTNlSWt<#B87UA?68vN!HreeI+raisZT z?Xup|o#nmH_btNTz8wp9-n;tVGoM#SAXNo#l3|)=W}1Zilg4PjHkV<@+zM8vN#GAX|L#&srw3dUjD{azX_(jv^T!mnCM%%IOg=e(((7a z_{|?JxvzLkT&t~H!gZz4^>W{&dMHIbn7nRFWjRaZNb|+orM<=Qz6ExjCQ(UIrzWMh z$f;9mxwJ3K&s!!-hIZiR1*~q$-m`qt^4=(3vgMUmpfu&YWXmge@RBW$qfk+@Rd&gu z3U^-d#tx-q%X&vtFW$Ou!bps==!avBiA%hd9&sC4H&3StziOe=oNdG|FDt2$jzwu}WXRUV76jAEB+28*?f5|;{(1;km#Lboo1#aqTAw=NUU{urfhT^8P9 zYAkl^ve{6}SmM@AXNi`v)UC_GGekz2OE-T-X(?%!q4rNfGsq^ISN+yGzkfdK4ObII zQNvX9P}7tKx&uwPTUKt^jmf?fY~b7e-~E4iV_nv5uGr@HcmtcOmGsM<1~$)hsi}d@ zvs@}_V6)1lq6RjrT`Fo|TrdQEsJxOI*sOJ_sDaHomx>zLtaquXfz5zRMGb5=xKz}@ z<{FoZH?XkSEiRpGV6)YwEt)q! ze?@5pJJvGW+%2DX`G)&%OnG9stL=Epm%Cd29K&v9e&bB~&6@}6?tI~kzgD?oo0l`{ z+U6LMg|hOc6;)+ROQ)3;=ks<>57lQ-%Z_#HGdLekFfLS|LCucI8pHkw+lSB3_{9ZV zUi$NVS6+k<0Xm zNWUn*BEPD%q@tp9Ue&xMMJ4%I2(--WmB50M1$GFUV;6EpYojuWtDd^@)CV77ces+^ zISaJZH`cV!SG9fS4ThZ+{_MYu`}?sMKYH(km;UIA8`s_1ST9}^Bx%W&cmC=Z7v=T1 zXwkK;Xi3B5&+SR#qg}6Ue|W{}Z@P&cjcZy0_33qMYucIN=j-f}|IeP`zq$B<5huI( zT`jH{G5n6KjIn7`Z_~JImwe%laW2`e>STBW)CtU~nSI0hHe}pe_OP3ak4(0AVr;{F zz+qNA{^J?1FS)JG&2;i1qeS!9U&)Nz@cHGwNvGex${nS#g`39Hf_C%Nr#w9B*y^|c z>E=16d4y=bzg-%BJk|H{_Rqgq=!$^vEp>sKk%K}W9hGkz<$Ks=Jo~F6?s!hDVOG9v zneW(;u`ash<9BcQ%h(22EMK~9Ol_>D+PO=k$4~EdQ4P9#;j`&}Q`|<8##4Sct7p@1 z+h&BuFr651X1ehrW8C!X^?OeF$%&PrF`}FpSbrNIjL}_u-#sraPhRAT5#7{^=desm zHT{j6p>O8>sqj@d(P;<~!_^W?UO8dRqF1kSpOj@wWM%S}D73ArE%DgQU%ol_nU?Xc zlq_lq9&4C2-?q%(pC*f*y&=B7uJMUcu2{Sv={#>ymO382JM4-5lZvLsy4kMM$Y{}O zm$>JWg0km7+|%Zc*3i^igU%DBI>u$q&va+>Zkz6A*0*-y6>}^qO6~QhZhw3K58n9T zf8A8dbb63Ki8+n@bVbpDyB>by{fSV;;~!tOOt8m}m~>LnO>J2*$6en2nXfYb71BF& zU%G8YZDWt)Nh6$28Xu_7B+9oRaKz9 zy|ulniVZQcg21rb%CP$Y1_z7@gI3va5&k~BBd*eEWTndi{r#aMP+-Hj&#*mT=M2!d z1IWGC;;9y6qyFiukWUj@!>Li&F@x;}Ba!G4=LYH04df%3xH9CGOJy~T1e01{2^!GG zA8C4NeBB?Be}+@2J$ld{Hb40=wha8&K{BW0Ov#v1TCp5&i*8%rj?amArcbDwn4U3X zM$XBZ(=zhXD*`<=9qA=_+PuB1IndHczw27t+gkDMw?I8Jd}F19*w5j*J>&%LA!^uw zx=7|%>>~6goIyR6q`@zbxG^MCy2zS9r&wHC-dWSx)xkR<71%JoZ`$io)O~f{fV#|& zzcQCeN4+t#V*r4*rUv-BXN{zlcUVJ z?TwuQdOtxyQ)}HiydH&?vw7E~VjISpK604wtO0eKR-ds!pS&8z>Uv~V{n&8m7g}8m zOP}D-?jU7?Ll>-^qmQCP5#XnJn|J}_pq|!-A<-l5w6;PzTzjCVKCHh{sSRVZvsgtf z7nVGrZnx9-6-}FMuW}8v^lXNoPU4K6KG?$;P2-O^ucDVPgdL!kw6-`SnYakw7k(tO zi393YPY&8(<`*VbR|FBhJ;LQH#>m3R_zm8rN{| zqM{l`hC5&Y{i%+fW^{&3+|AAHO&x7@P3wv`F#FyEX7g?Kjstshf?=H1OgHT9`}u~s zxvjRbvmDE3!FcB8R+{9mYOL>E8}V9TV{J`Wy%P@}`?Zh+q1@m~5sLNgfi){@nz{mx z@etRxP^-#i1U;LpKspC2kZy-6knX1{FbB{t9xCY?>>-zSP#kgnpeH!w7NGsP@1UIg z_N-yl$e!Q?4QO9D$LI;u7rI0Hg1Na<_j7n+$knaeqeI+MySk<2d&Sde#8u$&fc{MU zp=T2Yc>t!(9Y>twohltq+~O%|>BMc6uC`8I!&G3ySWnKU2M?$N-Vk~@i!pTrHapDc z?|`%i;}B;H@huci^`2NjKMiG!&HAtRdw+AuyN4+_f}P#+o{W>3pkctV>_=QIAvl|gkR z+NF8KInuk*k=k0D@Mh~ZauJNLf7I~TQ1iN`q8r9>hP}{0ZqH}Jy_13YxO9U3x>@ZdH(SWmOZ4hWm(#SudxI&P9sY=q?hWc-bVROv z-67Aoo$?+-W_CeiX9urfDz9NY#0McQct8iApBYA5n8Bxop9SrU5ez$F28|81H66iK zUv$fJ?QY4M(`A!fB>SJizPvaUX&-SX z%#Wpywg>70jopEa9LGhexQ6j7*G$mO8c*VWv--ZgFO z=gb%4#66C`+K*qsiMt)oR+L>~k|u`_O&i*dpmzhc_dloPw<;n`MQBOSKMQ{t8+3;+ zMxsZ$!z*Jl71uCgO?w!mR*?=bSp(|ud8W}6GBp274!l_JP)5A5cbk+H=JxLy<=K1t2kY^xrNdwYG)(Xh@Zph3k&1B*WE9?hB(jh&C|MBC zZ1N0P7(sE;GJN;>hFI1Kmho4=X`&kFS~-}l;fF0-S41IOr+&E6GB*BaW$Z3JW7j%0 zX2ORi9JU(!zJ(f_@oUSt)NdMS$^Vpmy{YBvMyI~0&mBGw`;8yg^ozn!~NL?`%9$=yE6ovgc+|8aHqic)vT-MIg(0p!=QRCn*c=2Y8mSBFR(v;m|J z>EdwC1ewTJ)pd7%bltY~RcBOfv5c91(}#iNdXR#rgu|D=-{Cb~*4*pv{4|)gy{@c{ zJZx3>H_BT6`&R5K%i7BSUT*)sln=;sYW+{i>}`gJ%s%X@*})s7b*KCxGMjpeWzGJx z6}!x`W?8W_`QP*Ozjimj-<9#h=MtYewY<`@D&0O|dkLMY$urzNZ0KQgNcvu0WG`PPu#R$8Mq zKoeBB0m5jeU z=6H$;WZg#R-PpfdNfcrY5i!S6OlYjTEn}Ccojt0veR=qX#)o`~7=NtTZ(7M?tk~Js zs7m@_6-_y{&@w&|d3`|5>pu@)UVrUNvWAse)^S$sZY%j%D|XI0p5J3FYyPKJY*wvh zEwzkfk?C)%nPy3c&Hc7v);|p6&r~b+b}RW9WV*!~8ne`*1{I2sVt-327|G9}^uD6B8Q~7ZV?I zbj-|{IWdJX3&ca@s0tkPBx>sUH?sWHjVn^m&p#v^WKY^yc{pvP1@lpUsQLIRY|wiO zM15>nb*TBEtsAmVmmjK)VB2mu5 z0`k-IFE#R0H<*>MlzPGQ`Op*3@%sq&(!sM2+I^td+t@12xommtLv%-8)=_gv`3{SX z4TqeMoM2fx549|`fl|~*4^^wXeLU6&ZBY|8+RbZWVzkP&@f3R?xzuHH*_;e|6AK}6eRzA7}w~uh~>GIk>!iBH410lnO z(`Ax?eS`}?So!D@&pyJ%FSY|A!-dnOnSF!{ zueJjr$Ks#xZ+gr9JlrjzEqD4m+K+Qs^b&NNr98w#7K5hfMc6h;eVT<>^mP*i_#vL|fPn@??<;h)_h{v?NAuJFS?vqN<9H({RMNZ7A=`vF3V zLR-W|6nbZY9Ys$;jd8LQgWf7;$LQyoC`uyTi9qj$QX(jCHX7@2=)E}#$9c622uhRC zOHOQ-{tgae(l;$Y!9g#yu$f_B$3V|n3M#$3z@~L&G-aLJBt|+7oA|z*`O{nucxNAkr}Z7 zQHCGGfPSc|DDxBSISd{q?gCR9$x=o5c>K0cRD{VN?8C&qj648((1H%av&Bz|qu3Js z3Wi6q3Rk$rzit=|xA0BI;9=q`N*B4}`}rrwY=&t@v)cjeG7#Ql2SS==4EsK0(0&Yi z-W49p-USZEk7e(>!s8g#VK9CizA_Rdm}Wei033`T&!z%X`_Mt*Il!3m@WV6{*r~ww z#DZ`UFm*>d2rmMrZbS#+a$xZkv%seTQ=QX6;nl#w{0(7ifP?7|VJ*P+iNrLAur6Rs z)c9eVL)k`P%-9@!G4N3e-UduQKnL-!20mFpj_DgOtF{DVt}(nFb_`z4%$m$!-3PC@D%>_kzjZ# z8;9^E*;V3SJEyP;eda zxeBJYI&M<%Ilx;KOs^ojQo$DhU#;LRz`_2J#;ybojxTA99-$cR@YC2$z`^z(#%>3; zC#og}xxK*0Is9Sle&AdMKMG9G64OEaCxH_M1Rl^>d|BO2bEM_!te3(eSYvPS@~p8Xl|R<25`^!{ar4f`(7j@B|G{ z)bL3fo}}T)8a`RWQ#3qP!_zdJq2WySsH^_7G@PyB=^D<_aIS{)G(1DYr)YSlhG%K` zR1MG8@Ei@#)o{Ls3p8A);UW#s)9`!^FVJwYhD$WOP{WJZv#$0i)$n2sFVXN)4VP(n znTE?Xyj;T-8eXB{l^R~9;Ytmkrs2~ye1?WsYxqnJpQYg{4OeTpM#Hu2r>^?0V{f|f zXf3>6!vPI9Xn2i=*J`*?!)I%Foraq<+^pdi4Yz8zO~dDCxLv~?8t&9^mxjAFe6EIj zG`wEJ8`z&+^}kUI{~G(NEBrhSpReHyG`vZ}7i#z-4PUI`%^JQ$!&@|bsfM>|_%aP| z)9~dQzCy!SYWOM*Z`be+4PUL{UJYNvEWa}yzof^Jg!@D$mgNAR^@J$-t zt>K$Be2a#^uHjoXe4B=E*YF)0zEi{B(C}RvzFWh4G`v^C-(tT zN3v5S9?$Uzwpe0X98JOeyUG=R2y2y?7H3m1pW7xe&Dm2h-`_1UAWOnr`!0!B^Y8@r zki@hYn1buYA4#0UaWZ>XVp<$dF;f_p6!;`JKu3gDKT_dGIi69=Xr%%^hX(0C(zrT3>@#z|j(x+=zN}q-;CttY0q%{cA z)3uHTOluH?$4X4?OPH>8DSV2=h0&=;OZ8E$^hF>i8mrB`75_Y+NAb+-hkiVv3v5LPK8+yBac)deUJSq?O z6Xf6K)3r6l>o43uIA4Xt-wW~2hbNi2td_Dy%33Mwq^y@RAZ3G;YouH&Wuug5OSw+U zCMlbxY>~26N>mij$2n5AOW7f1r<7gTxkdSYiZLX`eA^joHt^$VssFyz?|`1dQ9hXD z@^tVBpCzRMXCWL-PGiS^M#jHd#;=y~A!+T-2YIHH6pt{i5s^Gf%Htp%d(TRHXlS0F z8fg!b=LeGK2Qrr8LynY^Zt@U5UbVMh+Pg;DtCjX3xgE$_1Mwh7nLd2uX%{CBUXSoYZWpqS>_O7nDM_j?lC<_la*>o}Qm%w_?7krFUN7x7NV|~S z9^^W*3rTlSNG_MMQp&Sbdq0%+c1e5aA3UFs4P*!MY$+#FeBeAO>8Xkh$`^k@_T|5iS>l2-c+l8zodyuQ8e30S; ze_zUdV@O)F^+A%~lH~OdN&e{Adr8{6S=z(+#qB{>QN2KN zzk@u1>_ASJl5XD-o~zpXiL`f%w1-OP_8@D>9wcv1$SD*blKTTBZ&%1-)!t8~y{}7q z7*Dx9NS-f9?!S<9ht~(m`x_+r7vU1s-p{1HTctgW%iJC$@2`;by>=huR*DaKy_DaT zlGa*D&;0`O_rOklzAWwEChcRq=k_6axgoh9L(U@qfm|kKK*~#`yi-bA%Ou|GQvOZK zkx@dQA>~pjo29%+%1foZ64J@%D>9$A%X}h}JfHZ($9+iNUXbK}KFAxSyhX}8Asu_K zN_%%mdpNHl3iCno{sl?*fCxWF@ge^p<)5YeM78&GY41*H59dd250cx1v-p)Zan=0RF=y!T&Bv z@P8-upGy7zNf5CLBB|dZ^|wm>gHr#9)W0nCbZtcT-;??; zr9LTI=xH8G=}sVt@}45~v!(tFsc)A0bEN)aslQI@Z;<+jr2aXne^Kf`koqsB9=CaU zx?@Qq-E5L~V_cT{#Zq4-^>tEzfz)3u_18)L15*F2)ITrv?@0aUQvWxpPly%ijvYtJNUrYT5Qvb2kC&!6&k0*(APb7(SXG;BI zsb41b4N~7D^&6#rr_}F}`h8OW1F8R|)W0tEA4@%M=kRp>B$4i98khEn`f@XVvMsK zKOr&3O^%tfAM^EyYfY+ej@L_!`sR3p#HeqMza}y2o8yfVqrN#lPh!+J$LC9o z`sVloi5n!|Br)onhhHc$>YL+>Bu0I6e6hr+Z;m%hjQZyI5{a86-XbyTn}=U2G3uM+ ztrDZYIlfF{)Hlc5Bu0I6e7VG^Z;r2!81>EZl@g=AIlf9_rM|fy^~@#emrK+um#9xJ zQIA}r{W53z3zw)5E>RC$Zjln@<{0JW66NF)<>M0N;u7WI66N3$ z`8VJv{Tvk~87(CRnFZ6EmWS*Z99KB5G=tIKOdh7}6C`C8SE~C0Nt?~J`aVDknQn); z_We;v4i5>x&yT`$dAPpoj=#d2g7d;hw|C_cWky&FDkEbWr}VQ?k8EU!y2!}nRg#e< zM79vqg~$;iSBN|zW^j=?O$b?|!b+yFk}0fY3M-kyN~W-qDXe4)D_O!ymavi~tYir* zS;9(|u#zRLWC<%-!b+B~k}a%c3oF^eO17|)Ev#e=eSj;bFT*FgPT-?f5~8ZXuM>PtORN06}h9b?KZfszI&3B{dil zvIR956lTk5Ffi;E(_nD_TS`MX`diV11bgSE+~OGwaBmR}(TDJDLvm|pNCaD7*V@w2 zdCHWI&USqAfla9o)OM|@YHVp}wSVJVGXeW|LwilL18Qn(+XLNpQ0Mx#K!*)r&Hh<~ zcjvDOhO~9nw!lUQ9|!F`%FHY8YnHhqjZIQi?w2|f32x!I0O5YN>MAM77o`W^s42}z z?;;e&8Au)04Je?02cS^hA4wPDiT@o5Fc9*=?!O~}`=b*f9auVWi2kb`30&R!5QYU0 zBSBSFMM+g{S7TFsRZS;`q1vua8ZSE5H+R<5vMKF>reGP>Q=lurbsBVqgq#ZXQ1|K3 z6&i9*MEyw(y%*&D^NR?h6@WD&o*kGI>SY@!zxP1foofvrqnbw*1(;K zEKaWCgc`)6R|T=`azTYW>jo9hIW?$iv(KwjDCGeE9^8}${z+OoxAUIVu~z=-=Q1r+ zP1khvkFN3P$QHu+YhUw4L!J>BIf1Fg&_P zqVl@?;ce1*ulB>cS>t6!;r>pTbRXAvw}3}&ZXc8$z`5icVtg6^fMyimt2_?(i#+7-hsQI<@82IJ-D6KcKk{JjJPcO+ ze)~b}J&i$#-#%wONKtDA9_7wA&B2UJQ!~u21$NjS|jTA-p2`q-)}w$?<72I z!|x*>gx5Yp-XA^)?|U=lecprcZk>(ij4*cShhC183mN10Pc@>>``J8szwjWuXNtY? zzP*Ssen0ad_KKH;w|9rue`hSi{X@+bL7n$Fc-VRpa_GF}<+#rr!V0zbfk)mY%Ng6{ z!QL?y-gpm#cZ&ym%U5{ged3X~eWf>hC$I8Wf6sw;tA}zlR5Esx2cB^nWA}RCeaj>7 zjMH%++k?HdGZ=fw1Mda!yp*GEHJ;N9b3W4j^ujY4+vg$OlQGG8*aPov@E-NRy8-vl z_ITjsSBtr$PSwlt5Afd6Nx=7M{rtBz*cYbo>>*C)jjQ#>TkDax&m-?+kG$+UZ~5!- z$a~x)kJWoix5y)JD|lrd+T%6wNO@ zHO6#%KljL+17lv&y&F6)=_ar9W^X-sUhKW&(cU6lgnF^}ut(mp&ED)?=8^X)ct|?r z(A%x5#ap^R1ka1T>DV9PrCz@7kr#{o6<*Tq^2qxgcwX|i2>Up^r28m%7l+g`V=rp` z{FHXF?@*`yT;tsVUb;>K)_Ko*G-gNLP>kVEI~ z1#f%^i!q(|l1F==fp?Mzdt%FBr2fT3UeujSOV+?0;ajXF^od3mv1gdlF2Cq69_eu<`d*UA*N%%+ay@};W z{Q1W=v7dh*AcFW2gTIqBUfShBUX;R{r|~8$JWJu#X}ltZ=T~?aYP{9pr6Zj37p?HV zq472EBwx^YyOnh9dLZ6M8t);67e~f$5N{X?Z^t9u0q`b3QvTvefrEIbXuQwB ztAw6-3HV0`@yaz`=@sHVWW*anBpk$}_xGsjZU%28^u!yAe{>LUo5tI%@De#o@b+rF zhZG+92_0nbMU8hr;laK5LA?Lbc<+Kokq z%bTX~R%yK53U8Rg>(F=)DZJqdZ@b1j03MZ(@;5@^?bCR#D)uO!bWpq(z=MBdm$EoM z08cGHX^HnM&E6MEy7o92j>oPF=5M-4BCNd_g_je7m!$A=Bk)Elyu1j!bcHt~0&jxC zv+wVQEAKRgH#360JcTza0&lLuJ2e8YSmEK82|vQ+uT0_1iNLE=cylB0suf;-1m0SO zR}g{Mrtk_Q@Ol(pQ3T#5g*Pt(Z>z$aAAz?+;Vp>3+okY|Bk*ojcqI{ddlcS6h4&|| zU)~R%Jq{fef%gJ?D=uH zdamxpyh-v-j9~9+@a%F-h`>v_Cdiu@fmf~Y?0I>({N1ncCPlEvt__xBas*yAczX~| z?QwDhUd(mDa!iT9t5kSXBk=YpylD}5Uw~JPaLQjs1m4`8!Tj0RT~vR6)B5iY@Om)U zBYW6V!4Kla;Uuk|mt$@e^JU_d3L5WkI&Y-HTO5HmLE$Zlz{^v3OC#`#6(0E^9pTDR zsqmHwT3Fs%g;ySd*Q4;3N8oK$coh+NyAT z6y9lq7MAy(!aF?z?+b;8TfF=Tmu?Jh{w5)m{Lj7*5{@@g;o%l9Kf>`QC_LP{?U$FQ z@Twy4iWOdU1YV`WtBJr{tMF`{2P+Z4gx zcNE@*5qK{syo)06UQ>7%N8r7u@HR)_eWCC!iNK559rV8~5qKjN-lY+E6BORo2)sOn zcUc5pvBJX=20y~JTcyIoC3wHQwF>Ww2)rJJhfB16?QKBDow0`*>cvSy1USUeX55hX{V}*xPd%wId6dq35 z{qoq&!E~>Wz>86MyCU$C6y6OHcq0`ahID>}D{s2OL)Yt77hDLnk_mzSsT zZi&E~tMI-afmf{XZjHbzQ+T&U;8iNT+avI*72X{Ycxx5joe_9#3hx^ccs&a5t_ZwM z3h(X+ysZjvPXyi$g|{~XZW+K9#Xs!5b~ZRZ#&Rrok*-Djx%HQnbnt z`!-f4`9k(-+}Ei-poMpkRBk6K~HNzl%yGba@EQsE_ZU1PtDIDifl{2#MDdI%I zPT?fg(myz>VB5O~`YtHknN;@f&dnMxx;niN`}L73#j}~|V9NAIe$+>Cf_bDE#Y&9% z{#VDib4Uz)f5NtT@$V0?O?x+?E+(Q*Hr<`*t2S;jTe1C+>Q2@{)R#r)6>g+jqZ*1v zP2md@(t^;XR8t*qd}aTEFZv2!+`n_)U)j0)4?N$ucdKt@k?$^OMt75L^OucixAeZB zMpKC>uBeg!$7`Q{`&mq|#%uOY*tB!kO~qr1TCMFdFYouWn|wRwkD2d}sxi&^iT-Lk z+}B#*FCJrUANsQINx`}+ab&f%J?&*<;(q_$k#P5`7xe8LQ?#;x<@XhhA^<4Iu>o}$ngie4PehIVvS>`%q-B%JCq1=tg+cFJWIKFU-q(CvggD zaPrUg&*e2Usi^mY9c8@U4$|AD9bjGOoVX#e%m zXl=9w@KSirs?W!^RenCP?X=HNYGdf>C$%;9Q3+zYr_Fq__w=1(yGc8?Z36yIY~wi| zjd!V1>3EO#@zQ*ejG0sW*l+hf5tqQs zy-y6~A?ZAXID0XU5KI1^OTW`l2ckb2W&3v?(@H(d#IKQ#-UpQ2Dq8feF_nEE)fn)B zy?gFT{HVs1zuv6bi#!SYkm5J&i{F&Dv;_3zm^+_H;W-=5Ig~SE*tw^8f=fC(-)a1p zV-+QkzcDJ=@%QrIR5FAuwVHVem;S9OoNZA@_dFGoaF1`{m@`lZ^HE=`KSLdVChEAR zcmK|_kV-LfTlE?0__GlS=6goe{5p^qxfS2rOW*_WqTV?>qN<-- zx!kZ?>G!6-J+P!hL7IZ;u*0UQ~ImXJHR$M>2yT~v4klll<>J`04`S1Gne@VWFzBKYn z^f%G}DtjlOp5fQ<=v4>4M4gRo8{K{ST(dc8;_3NjbNa*yrtox%8|)7>j*jkrYGs8{ z(c9Q}`2b7)8IAvjl(=UCgvy$rTblyp(6o$oLEe6mL7VN^lB zb`gV@2|a!^N|%oIHqg8O$B311k9yCSvPO7l96S?Yyg#NT zJhgHGyk=n>F+N^PA)*(|j~m@RAETIW&4S(sYZmlI^VE=^Nu#^RcaQB}g504Nb}m9$ zicrc@lyR{vqsYPN?o7K>Jcr~Fqq`^AI*iIAWJyJfQOSv8m)kD0T4JH2@)ENcdE}w_ zLz;?vJCOZZZ>WAV;;C^fa?e6-^Nv?D+7 z^_J}9sr4>|#JQ?>5k_Gia^N3*G+y!0NoqSb_St89Te9taK0bTcL;3Z;%6@K#=#p&X z?2i_+`wqu4tTFCcxy<&Fsy{KT18!KimBmcMW@9@=3{M$eBAHmnj*@x}(ATBAVuF1!Kxo9iMX)jG51M`~7`a?-^P! zW)4UDCLGORiRLXIk6l?XCL7u~ZXLGzgsqdf&W?9HNBbs>wBz+rypgTUEEqGaHL5(J zHmdxU8diR9jZywkjamM9jjw!v%_prEwEptfYog14Tl0QvK`)hODt39d;*Grl{OV%0 z_}*R@>i}v8?!+6hr{Y%tcc5CKoyzL4H*6aJ?_5^HL)_sF2+zYlpIp|12Qfrg6XMr! zn^my04jcWaBCH*@yLmcI_*Dy?9yc7P4i>t2z9`3da}D34{(q|s9c(>nqYkBLLjLQ} z$$x}@QTT_y&F`GN>POQro|g^~Pa3+OG+&}0hOa)huxv#|$>MqCRfVNX3l~)_U%H~a za9-8&({M+_@-_4mT(YEM>GHx1eEQ0_HXRsGQ53&4r~z}B9$2zuc||^6 zc(erNH;3z?^GoxW7o+6n2tA}Mzr3QP2xT@$>Ou4K7nhWt#w^Pmr3X>0B}?Hq=4d^r z5J@eE#c0bs%7+z%U^VtU{r8yW`3tAJsv&Cm`i{cRrmCVqcVk_k4Da1&4&V(nb(m5d z?XxS6-?^8S`TMaKKYH(km;UIo64%|@ST8mPOImW}oxl3UMR`3gn!mQSwTa=?1CxWf zdbI1c?GLY5{Y^Kqqj613pgz5BZB08f{OIpaWB#*e_-`(LV8qF8epibtMhxGhC$q9? zQ*YC_YnOcCj&Uy8uIgl_pYNZQ+$oc&uUm`L<=g30f8;dqaGEUE>p@T(NjT(s|yZEWY(t zvfmx{#QsS|Q)At1S7~IlXw{?cxul@%`49KBxuZ2SwbsD*qSOT1pJ64xKkw61T}+EJ zc_~Ij*W1SUr*37wE^B_KJEM1-yIcF~Tf6X4V-^*q_O(;DzrFtlZ+!5-t`tOpgZxR% zam1%9iVocM@Eh+>geo5Y_*pf^JUEA6mn2MJGb#(;Vr*<|@Z4b1yc1*3yoHlLRxi#$pi5oKWvT}Rsftms}9f7L0 zb!(>9w>NeN+M60{r`n-GjaXj|XjxMpo<`h>cP=@~O- z&cq3Z2gH9RPs$a|g7;T*Iqg$QWG-Wz{eb8E*29hJKTbe^qk+L}(I~Erf z@d^F>n#QKC_CQgf6E8PI@1=uEZx~f^_IP>FNCWK+fjD?W9M9Wt4@3W_JC;YBH@p+< z|G1P1biyHc1yf-Sqcu)8x)V0gZQM<5EbjTH27CNKReOiHlPpfaRPGV@H&BTkt`o73 zzD?#_zc+RiU}~}w?@biFoJyQ#TxECiu)G0k^t!gLPFho#vX=E48x5nZ7CB?~Nj}Ql ze7;Lz4W}03Z@7|^zJY3~5VuG{x&xKiVRMT@)h+ldM3-WwiaGze^YLa&Ue{FaG~-ss zDMDET?;3l&xQ3HM)xA+Zh6}hrdwXkpRTZDh_>+0L=xu8M^`U=%j_;$-v^jMj@)}#J zYvDo<_fHyl4|-w%JZS!5@SrqQ=Mgsw(Ff=p=jiBcZR5+#yq8jW(~Q4`2_1N!@fpU3 zgPxIaiaM{et{o@St^l(aw1SJn>R5#3P<1S#S*$;mmy#-Au*V|WrFX=6QmNaMYT7%4 zu0#b+GbS2}FFD}@?@W0E>r8Z^<{!nKiC%F#*v>?!)FaNB=zFw5X9;wc1=<^1>v$Xo^3Dhtm*9P;1y1VPcya}Ay;Gl#2I*hyE=@&gCt(rE+lML!L50yK=(9by}Sz2m?z&T4b+ zr`tE)L!6B!U0Ot_HipJjF8vZv3H}qQI`{{bhUm z6`XESfeoWHT<`!no3mt7kM%>DuDFeaY%-tIN%|Q`X~i)}3SH(P2Z|bsKY04&FbrPH zknWM@K)&vv1EE#;xWy}&3Tqfm_AEv=rb8KM2l}?rjSIgz+U8W!QoO-6n+mJl*coVU zQ)wGoJL=>PDZ3CDp?Y}arCq`KnI((X|7{rZUB7tbe)(Z=yZj^3?dZ!9L7&R+>Ir%t zl{e0K%x<(WtbumEPX^EV=Ay88$Cx$v7mTrJfg^4-8;OdP4nv;@qv3;BFcsD?{$|hU zb;>|H)bC8=bQ;cDTN)bIsDsqTP}PRcjI#0~mDJOjscE|FI@>c;N@oY|p*5|mXf0_e zY+5&u*4ml9n+T&`dvjM)r>Z!ozOj3GpvhS-1E;NVF_G*AG-z5IbWKZJQcvg;a#)`{Gev~<%AulenPbC?o(cB2}-k;d`mh4{*bl9RQhTvb%)QmzroRc>tq zwtUHJImJMrGo!-ItB0n{Wv`BFiq&*$J2SOtHPE=DRdbCiT2*IeVd*05D0OTpvtU|p zJoq_hn8Fg56ic1c8C{>+7R2m|E-!42zB^=-5+>N!hiL8&(R?dJ^8{(Cs_HWHdTMGL z@mbIA26h?lTkE z4bbU2-%@$~#vjcv!2>-m4v#Y0!j6mQhmMOILq@@`g&B=D)Y0M_c7iLNe?3N|cG^#) z=z8!OPK+s?9jfwNK1?dCZr9M%6*3xhhKvRsp`$^2q|tzu`0Sn`yq}hkZH?CR(QIX< zrHqzuY=(%_6{5kTpc?0`5Y77`nomMBc&3>7Prx6>9trlvLAz$B7oQwyebM}`+81dV zh(94hRZPV-jAQLB`J(xG=s@?x`=X3?9~N-joeY|It z6Xa@oeMRn6S9s`hM7}GW4>Dr$WgZ2{;ncM%L+^{T1DwrV^fEGA>0+O*1oVG(O1DG8 zmHKSxEgA+Gn}c)dV4p>ck?xV!bA1J4oQ9VdJ3#`zkGdFjjJ?9MJIee+r=GZ{uGS z`xX8gcnewI5EA?v2a16@P1n=YU)W@gV_++aCqX5! z!}mtw5X&06+wAu(W6OVF z<{s8EcQa}=3NN=1t$LVi?r+H4h}me^_glEzQPbYy%HZI1)_&b?uZawvVp-!pY?y5s z8^g8lVb0-m$f0%0hn7(mE^|W;Z_n83L*^!2YZ)Ji%-!*y)V2>&<{Cb$TJaF?TEG~W+O@U)S9I5YSG zWiZ!@U3GT1H6+kr#ZI?|-1N!iR&1d)O$MJm{CL9O<#&>rI@}%RJv&;nNd{rRw}9_ zE(PH)z4X#AT7F_$iKcHT{(lMePufl^xwYMlN(3G7W&G-}M*JAf6EzxEp&n*hL#<&{ zy~i{|`ckY>#Pz4WWKHljH_ zP6z>(g`RK@5=N?&JJTnAq*#eRMz*7n1~Qu1YQ_6XP)IXrVTSaDW()>W?+hckokPzJwe4OwHxB(5=Ilf*wiWE}m5 z&X0fi{Rpc0p$lrvwAGeTD~hpz51+H~cktFD-1F-JT9O$2MGyYEtv(!4m@dQ`qZ86t zj6WtiCMG5}CN3sE=IEH2F>_)HV;0bJjrKt=l}SDSMwSmb4*%@<@gC#TvtQxjM|+GP z-A{ZYLi~}4V;>{%gQuUmaYgF+`K~f}wL$lQq>Zw}X@lBD!9_W`O{$DT zu|a)H+PEO3F3kS>DWzo}w2d?Mf*V;u>iOR@@>83AJ`+`vdcpsLaj$tg+BODBTc1Rp z+I-^;%9VFJYX75s8^TVzdDS7-PqAZTqd5(7>A9UYP z!)!o(;Khk0>9~KAZ1`f5Mx@3c6*E5O^0^o_eNzkr@86see@gsJYu2baqgrBcnWre@ zZ6z~Ak?U3a?s~HY`^u|7F`UtNmK`#UvZss0RK2r_ynpK(DE< zs63Y5#Q)dRaeVAQwdOpH0r9#!^D)3_^QeE%hv$rPYH7gxiS8DlE;GltIgvfr9*Cd*mj(F5SsqrX*nf{!h9e; zUYyD?VNf8=77|$&&V!gC3}^PFfgs*VCLs^?j{}U4pN$yNC$JJca1k>Bnxh@Fu?hq! zZYDzUrp0_CX~cLuUYf88QwFk&cP|Xmds=By%5SUUqSZd=qSQXZg(K(A5iXoAD(xd& zI9)W_N4RjhAheG|30E&b!o{bFrhSA9rwcIq2p3KlSN0Jue1aVa87`bIitHm?I9>GE zN4RjhSg?<9;dHTLAK}93;=?||h0{faeS`}ywgVxqLh|Z>A)cvmso4oeELu zh3X>Hw9m;!4c*L55oiOsh(NEVb43W*Y)<^~4xe5`=Hdr;pA+!}hgcFybY6i(%%Dkn ziICf*vvHk>nfM0=4thU~i-^5h{k_^GSS9rK4_7R)@0V{Tl#fl5@nFtr(;Y>S8^ByU z)rmP4|3JY(&*m#kX9pjJ1kSOdIBTp=(K4*gy-zRrLypk0SKeCJ-UCgva|OjCm*ycR*8aIa&OY41cJ?_)qc3` zcN8K282qUyVFtaW)5`DY2sGm*@a-&SL|k-&Ne>mu=l7UFr)UMhll zIK3PB3QwmN4{)>W-0{)wV z#{z$;;EBK%(x8LvPXivN;9THJ1=FdeTEX*xZ&EP5K=11crg4($(6)a%@QVtr0Y0GM zwZOkpa4Yb~3Z@r+e5&B{fPMI9+uw}e_SDZbQ`qIeEg~4@OJTjhn-zQm@U05I75H8S z-wphLg1-g)9R)uOOnsIPvi~^n4+P}+S>RtO_(kA%6#O&be=7Jj;5eszDeNs^d?=6~ zWd9Gql@33Z{SR=xfaU zcO%$J;9z-1urqB$d=qeRd>Fwl1-8!t z6#pvVvlRYyzySsC2DT5w9Leqku9XVH`;>4Wwh}++!X|stg?;RG7mlJ&t~iGe=cAD> z>}Odn9L*|RIEHn)a4fshh2z-WE*#IEcHsnuPmel>594>V?F`WRFkT<$!ig-`g_BsB z3n#M%7fxXpxNs`F-i6cHLoPgw{nCYpv(H_41RE~i1JCp9L;a6;;n5mCO2bEM_!te3 z(eSYvPS@~p8Xl|R<25`^!{ar4f`(7j@B|G{)bL3fo}}T)8a`RWQ#3r4Ww`2hnuaqp zoT=d~4QFe3x`uN!oU7qH4bRZE0u2{xxJbkEG(4Z3 z>ZT@-#bm382_?a3$OT$$fuGVmkhHEukr{Q`H2Q=KE;WZjwtKmispRM6_8g9~X zvxZwV+^XR=4WGjTuKMlJ!rNJ!E4)*~T^jDz@VOf9(eQc=Z_x19G`vy6=V|zS4PT() zO&Y#X!xw4zVhwNB@Fg1FqTx$5yp>(xs?Wp|l2ktkiOTW4dxhUC+=c^dSzyq=a|h*#Gl{wBhR zbUjJnyQTb=lynV8dU_{RT8hEwJy0ZR{eUFB=ZWIe+ntCv6nsiIiQ=LBv?fA&db>?p zvVpG^3%p&*x1@Yu%1@-EH`Gu(x<*Pv;b^TP4aVsjEDaY{)Q)K|o=+0xo<|aiE+&bE z2f7waL*tz;aXm?tA6eseD1Vesx<;dXo=7rYwr>(1Wd!DHZuq+y|9s6-wn*8^*cQ^a zNqLTx?NW9~*(oIo&iPox;PPB)r$@^5Qf`p)Yf^5M@;oWem+}HBH%WP+@KxUr7`~&7 zeBHqK8W4L<>YtbT8^yW`l?Pel<*G+v39ps%11bLk>BN6Q#>b)yip=Q4#ymb`3-KY_ zrKFd95gtm;Xs7=}8GpBokNV^BA zDJM{TU|KUGIZH}_TQyd`QX<$puoS(jNR7ROW-^`Ge&7gUqJ*kn|BG zlEqRkfpqNsRNA{k+C#tK_8@63)CYNvl)V0dDLD2o!f=v{twCRLpD)-NS;r~b5%R9N;?>+;o{7P@q*idM>l%pV>di#aU?_QZ-jE6kGki5K*yu6UVqw+$2D&;WBKk$iC&X97El(a@h;jL0$ zDCHI@uYh#&@k^PHZ_0dNJm&d;tRg>vtdsIKN+0;UQvOWJPozvH`v^Zt%0ekCr94N< z>!rL;%7>(U4ARNhYcgN=$b8}a!1D#k>jjegKjd+gJ|x}NB1w0jNK!v_?EOmG+b8Ye zJj3llo=xS0|W7xcV+q2DX@_e%cL zlK-;Q|3d0NmU>$2B>R4nurrn<>|{%Qp42aq`f91Km--&5-zN1}N&P)i|Af?kU+Q0x z`rk|apQIk&(dOw6CyD%wCW-valKLf5UoQ3SQomX1w@Up@Qh%@1KOpr#mio7({vD~e z{36{EB$4h>B$4h+sb4Jh%cQc1xSbgf7HTc!R%seeT3=~{&9ldeI?{%@t;h!*-( zlF*MJ2|JUeezw#XNd0Q5Z;|?TslQz6Z(cTO~$)a(tP@s85c!NsRjB z_;QI+pB!HyG3t}!D0V6O;}YfK66N6%<=_(e=Mwqm68XjO-QQ7BlF?G$wrugL_LcTl z82ydQa)(U+yPd`rjw{Vz^f%MC;p}k=yPJuqSv*2^aJy6J9wwqq4-!K5EKzt)Fg&B7o%VP(3oGF@1i zF04!!R;CLp(}k7k!pd}EB}Z7v5ms`9l^kIuM_9=bR&s=u9APC#SjiDqa)p&#VI@~s z$rV;|g_T@kC0AI<6;^VEm0V#ZPguzlR`P_EJYgkISjiJs@`RN$AZjcQ#u1Zooq@)$&~h*=7z48I-xm5_D{Xra=IPZf9G}4oNg<$VLPuD6xwYy zLP)pO!h_v5B*5vmdWh3)wSa!Qt;P!Npn?!?E1)X`=EaUaUF+=4a|JkC`*dx8bZ6_H z7Qy{$)<}VJYo3dOT)Vg8>7gMn%A11Mm3MTWGNq%ly|HBto5CM^u4-&)XtjSgHMRuo z-wkj_2h`Nowg^t=pRE6Z( z=><+Dx-`L^jzJslS_yvB*@-AyI~YT>z7y_h7g_b%Cj}gCun_<4$j-Qe9wNViDSXli z_-{uR@5a}=s@rAt(2!0Mz9YMOZI=8vA(&p zrj|`<4>V~F9_BO>N(w!dgmRSANw~n^DJ4v3&>KSo`}4?9W|-59Lz2URYwj1U4Sk>q z2??H2bc+aaM#(VIoI$alu;B0*LI^#5UwhJY;Bp+&{VUAJgT#udsN3-`K!MR9bHe?MD&lYk?6=4 z!ue}oGhrzrgcswmg4b558gCYGN*LZWjkg4Nco^O)jaLsmGz<@y@vi*gGMr5b!^35$ zi+3yVxG+2{H@kRPJ_yVEp~ia;cmn>}hh2YfL!s6)ZZW#*+UEU3;}s!btZht&5v0Ay z6vu8iy7x7k0^~tqbj;LvcLJA*ApY0pt=4#-0gnm8>(+QFSOdL14DSk!_Yim&h2ece z`@FUhXl(rk$&)lz zjLz{kbyn@TRO6k5&PLA&=!edGegyW-d*FR{l)T@o84R&^6l3ptuy@ZfSYNdZso2!* zJ#(zQFRO6qr_S?_756taS_rQgg8{#fsu6X2y(ftKks2+;-dh+9R6n)(y1kPpVb6kx z@?LVXykBV>l2W&4V1VWKLk_|#$dvaN55oH{oSEN8JP0o-7tg_9onAlm{7uA(f!|-# zh&u1#IgIi9T?gT{7Rvir2jM+9Pu{OO2=BuM;{K^d3u)gu3&Yp*HClh$RLa;NbYs9e zuVFFzr3ao5C(Ii?@NNcgw+G&grQUcy2hU6X+HsQc!b@Dn*liy2cRzTyd*GFqdrS8t zkGw0EGrlKEPg-xctO{@Ccon>dbYsA}y{#)4yT=1BYb9g1gc(nDdq2ZOYKI42&1sCi z>?PgP8GF(L?-TGI^}yS6hPV1FS&iqWJlIP*6Ze(Fl=tgezg&G5?$avv?5T&&+wGC} zhDYAfRXA^XNVnP}?@o`r_dN0@S9{A}n@8S59(iAQ7L9`NSd zfr`}aJ?YV&8DI=UN64YuI}5zEAuPsp-g6##QyRS4+v$<_rAJ=F8nM?^FN$7{pMvM5 zym=tulo@j9_O^l76v7IvzrTWqp)%yq?Nu~-v-dQ3XNOn|P4^^_Fa(Aidb*c^=f&Qq zAbIhtrR%(v<9pzFsh3fxWZW7LIUdvc?i^ux&$Xn)-caBHi)gE~dc;x-eBkvQByyRAo_2-ed%p>m{ zkG!k<;k~N$j|adzIZQv&d2fP;OXZM5=M8HUZ)?$sI&UU;SV9OnbY25^86hmjbl&yg zP4mEe9=wSjcprmzk_X=CbG+Fr1TV*fz4hREDepJI^OC<;!8^f2x_<}HOT8T5?#*5a zcwX$agEzrL{%!=%i=RFZUX}-Ye+O@h2i}B^@a^#~`jJm;_2pJh120^c-5X+JHb6~UB5Bzn&XsM5Zq`l!P?_GsQ;dGFsJ>x3x9}3Ub z6K}1?OS>ePZX6lIK|I<6Y{w(rWQ7+`3LM0{L*o@Gyadh?ydP`4)!%g+52C<&E9K@y$l&S z9PhUZFEaw~J%wlce>i&|E4=Io_P$Vf(R^b&!;I%2dq6oYmg*Q*({Z8vgo4~XC@8}4;UEs|{IE@FmmBbJ7Ki%GI3h(F$ zypdaj_Ku0btNj1$y$N7d#o0bS=iHo|n}o209Wh+?J&>>qNC&Zh7(+u`j6uMF{I-;j2A?#QJN z5qOTiNzg+F@jll2+fMLaHtq7_(ycs*hgT>0=Dig+dFzM;?eI1zyrOn^TNK{Hc6d7# zUU56Ty$WwpJG=u5ucRH`lL~KfJG>t&ywY}fuPeM$+u^;Z@M!#?Bd9(8q3}+#X@R`R zZm->zw8I;q@Rqj28>8@W2}>S9_RUmyxP;XvuSntH5>}hM6$t&yv^g?CXqyds6Sy&c{Pg?Di~ zybTI(M?1VN3h$D3csmu|rS0(cD!j|u;T=$Tm$$=vQsG_E4)4bb52qON2=eFG6&{vk zZSvkzcsmu|D6Jp;13b!y=6x(>vJWTCv z@}de4Q*oQTF$(X7c6gH&-i__>W-2^PCGrTWzg&ffF5f1vNa3Mr+T@ifJp9=vZ-v79 zayz^=3U5z4ybTKPmUeiX6dtYb=m@HpEeh{en-<91q3~{NhqqJV-QEuGMum4rJG{LL z?@onx68aJTcZM)=H+ar@7Sp6C0SQ|~BFcf^0k1Kc0Sg1NT;pZIsIw8K9>iZD-~9Ui%wcZWyE{kNe{b(! zN9@UNjK|J#!`|IFmDyJ!@5rGAt@6G^=DlEd?=|CWX1FkOjQp$MvgYt}nFYHFcfY!) zVAuTJZ|=#cJIUqDY=g5C`6M0E>+N2yx1MVz$aJXj+naZrH=0Y(Vz-N>)M5pwy*cf~ z7VM__YpuIEP`7cT(T;9Cwk_T7uKOR~%Y6e*W&l@}AWTR~7CkTygLKdDQ*kg5>)%Z{Gc*J%y{eNFS3rS3}RaVm-nuk+vG| z_@;bn@Yh;|>1l&Fc-JBR%Yq&D4nqHLz_I2pB!;jP0@6NY7sK;l_Q%DV5pdg|r{H#J=lMUbmI%o_7I z#A<7+YVg+Ik%nW0+!E)+lfV7WzXshiDdbCR(Aw89@ZCFUSb5Qs)k_zyoWFYd)Olx= z&xdK|BrPU8XQqrYEOW9Jl{0O+j0#z1HVmHw)tvX^mk(|lU6=cjFK=mh`35}nx}mP7 za%uI}D%hT5ICf&tb<@wQ$$$9uyRZ1fm)@fFM%XYH8lhNaWxX)Eo5jX=X8-c7+-GY? zn)E14eqB>-qcF_jW_NRuao&sv|MY+Jc3o$#y`a&H!uPpLyeLX_>biA!oQIO(OWBLv zIA4K&JpSb0_WSdT6MY6bEm2U_P*GpKsj;pe1u8WhS$3lKezGaUO&EJ-Y0&|jsjaVofxs^g0GIw zIV0(YdwiNLI)h0v%+rlfMN@qqSMCb0auGUDtwhxC8E!?Hh%HfTA62~4jm7K3yxhNh z|6lIg+c$iUFL$RJ*`b#<#u}R%P?KjGjld^G%G?M0wrtIQsO&L67hSO)u5V!sbeZMf``N5t zm)=w1XS#N9l4LQ$OLFTc*M!EeeB^Y0l4|OVmc0DSMpR}zHgL$AxBuhkxvFJ?WcfS` zC-`3P&__3X@{eL)g5=e!n?TK;jzSJj%5#*;_snxTr|d=>6vh4bQ-!kwiO|zp#ZfUdWn~T2wz>7m32+{#EnQw zQhV;nH@w~a+?#*?yPqme@c83B+n*^fcwzrzZ@%w$2B-hGa)zPTZ2ntlMcOMq^+{1j zi`vE=924kGXI$%MoW8|QCs?%f!Pb48a;T_im{d@;wrTz9`FZmeChX&RMu^_;=Dm&} z-I(G5!)YsbF2rdoE@vdHvZ=y*bj3=i59!cKR{!i871l7$GaS#?IdO76a_o+t;$5f1sX3v^6 zePYh!?3vN>sx7gG=t8{Sq`qlmRc#~vT~SxRsjfcOSXC(uEEOF$Sh8gvs(m@0aj%s1 zYdgY~nj@&JxVpmCwky<2t9;I&1%2TT(Pg#OTcVqDj;cG92fD-UnmeehxVpnW+Z`HP zyMq?Q?$DIz(SepDU2bOH!lMJu&#{NHq$*bF?jOi8f(mUIQ)rF|qQuc7DnyB~Ri7#h zV-?Q5N3H_%Rpvm?@KHbKBedLo2v^QE%%S&-HrmbXkv0}PLoRYD(ZOX%u^ z?n3Kwj#uwX=Gw80DVVDe-Z2x$}%ItzGVH-Fx7LmDrII&dyMf%Wcyc7wTF% zrdb%+}h?Q&C*X_s?3`Z6N96kY&?u`b^pM|d-gYMBac7#FlfiL2x7F*bM1@fz&S zJ7?!D(Dhn#wpP?Oa!Hj{_XVADN!n5nBH^PT?aOpImvlzK>IQFwE32xlq_-5(L4`Jq zeg0Fm*3`JV=HnfjhJze2c-plc*eO!0Q80ueD-&-jVA#H&a$}-L!7k}?n|KsdT`mu= zAlqDpnsz+yDW`etWs&D`%#5qUy>`4fT*Ak=A!vXuJI2}5ZsEehQ%}d%ME%BC{khWP zsL+P-mb0_(O}~C>TwU(dxVW5Cqz;X7_Ol54z8K?;P%!yL5p_nT7iU@+?eso6ytWE;$R|%N}}ueRX41 zd21K#Z;+4rW8>vq3cbfdA?h&>b5i1u}0+$_e8I2Dz3+CD2K=QYdt*ltL=ci1zn-!U`o z7Xr3bziOqNvir{u@BXu8e95+NpU=Jl$IQNek$nxnw^HU^xo>$R{#nN9wuN+;wpW8a zj+uq~3|Kh#%T~(dPc7?h%Q*4)GViI5n0M^j_boDSCAIG_EbB?j=x*2ESJlS-cjAU$ zz2~+V8J4yF*H+3$R+{#MrJYxqsveCkeSiJ7lQpl~fX zk}xJ1#-MI}L?j$Zjzl6Uk<>_9WN>75WNsusvS0vs&OukudvCu@)2f1SsirBz-6g9mO5x_gY7u$$nDs26v|@j zz&)c2qu6TdWrQL<`}a;eAu=*@O)jo+hO!K!cPKI|?WDBXX>$h79atMd5kNNwgd$3k zUPgw|IvIt^q}IY{ZRE<_$W^)4&fK({bJH==PIYxyJ1;RrFXQUmf&YKfoko=@>m;qM zItfL38M~-f!bem?T{I`xrxH+qT{W-6^~$5#G9%4!w4NX>WU)pd#r1faYE|lcR2*jqPoq{nhWt3RhTZqpQ~V zoi-Z~&xYg~J^PRBj#qE(z@SCh;EBnF(elMhr{qk|&zU@Va&*CzX#S-9@#AreUS-w# zs@kJ=v({kbB~JjcB5@8{aX3dj;%OD&96|bNhIfvjc$&SPBPgC`X6NWkJk6-i(V6sW z{==Ziu3x(0cs}-r?5kb=yCi8{XtU^kRF9=@o{~jv@znh*;?Ye+wm!Op&CwTha}}{i zyKK4`$rrSjvYFjrucxI@I)r*4ab!fWp-Zq*p!aBNDwsHwESan;Me}=oN z>Dq^*+P6DTrSqznHlQ7ve}j~Gc_-qhe4#Mz;p1A4#L+$di-QTn}$Ov5{GFf%kNd>*ihno@V94QL>vHi&XY_tBEAmn*%uLy z15+K+LGj;*Bu}S%?|%P&Rz3fRjpMf?uf%P&QKC*I31MSOsG zFTWJ=39y%6iuerJ%P&QQ;1FJZsUj7a{EH6LOvPeWEl;W#0E{_99;TTl@bs>r#V#F$ zNBQ_^@;mht>}VN3)tA1T{PvTVzMGimOW#c_1oqN*6J@~8VPFznq2Q2dh_ijz#9jFg zn;yOh3Hs)fbA;fJ_xi9Up7r6d_>B)Ii+}rYL=3dY4yiI^rikf2oGQwFI8D$ulbj=D zb`zKRaJry7xtt?p_Rw%o4foP;hK740neV_*?Fv6OMC#eYUq^ljDFPzkpo@CaO%6dL;xXjnW zITq`oxs>donf!RW*B?CAxoJRFzcUuY7`$t<&3Vv!=_r?5l=NIZ?@be1z% z&SW_YdoZMTwf)V7&;lVgQl@J-JjUTg25Dl%$}7`D%Jh&jJ)}$z=}TY9=@)T&)YExnKjd1< z7m~h1Npdyi4_V8yf#n6NJy?)dQ~DCthx(TKAXk$f$O@KcPWC4D!`)wiDYm9jpxztjgQ^+8H~kkUR#X&w_OjeULFKCu9{%`qm!dbu4LZL-;(^K2)BpzcSVbf0X(lrG1dnK1gXFq_huG z+6U>g?;O^58ta2!OMQ@Ml3kFpT_9!sLCX4ryoKz8yo2ReR6EaQy-Qdx`iayFDg6#o z`W@spN)LGr%iCDe_qZthK1jEH&;aX7s< zp7;|3|<{7ep)^-X#>{7Mer zOA_I--jMHO9R4E?|1XjVpAxe5&nF4~LXrsI%;7Y)Q#gH7k;3oc@NaVX6CD0Bhri9? zzvuA3b9f2{UDA_I5_+N}QLY>gpU&ZB9KM#r*Kzoz9DXy0@8$4^Is6$8Z|3mVIsAPN z|A52OFz!>nCz6CcLrGFSaQJ)F&J@IQ0-M;xAt`IPb5MUd$oLhEr!YQ)F~)Bh zzmhS=TZzwPjPX+9Rg5v-NqiP#j8_t$%^2egs$Yb#snL@p?3MUr#;{jnESO|G?3H*f zW7sQkE@Rj$aUNsXEAc$Wuvg-I#;{l70>-dc;`xkWuf&Cn6?Nak+P8PcWd(~UzlB&J>!hiE?9O(tF6xw`6EiQ1^wo5oVwvj;ZtPn zRE|}*IVpCUjGZojXUN}~@^_Z}&7N!vJBREX8`&DOr`pKYkZr5TwsmCNO0sP&IkuJ@ zw$s*Ws0q3imhdet!0X>Ws0q3imhde zt!1jzQn(bAmep9brP2O9N#9YHaU7~vs2Z+Tr57HwL#)RtJHlR6&<;{}T@sZrkGNzyms8c$Z#*pU=B|uF?rt>wtHyUR}O$_1dQDn#$F& zM!5FcrbhC?h6^?}#@33g`l=ew|4IQc%S z@kZeMD2Vr4jkg0lEQ{R3(f1#X_f#AD`XB+NaoTMV&X zq2*hyweNXjgt$!O5Y%~p1Mij&@U9u#G2XCo9pil)yxTjFZ~1s3?(P8ZZ{U5U1H3&r zQKLN^{m|=W+Qg3WUhN>S0h{gj>zM-U`3}OlVn=vC0PlYT^wGG8|J~zWoNMB=%sntX z$V2D7*FoL{oU3+3-=+@ozSTkAKRU>pgLCJO*tesDyygz_A~;9yNWM644dl`OpxSOX zf`=wQ3R!xEfMcjR#{co=$H9p42{UB=xF-pdhOmjUx~W@D)=eh6NQl6n*NOa}n3z(0$_ zkxaa+@pdXa=Ny7~Nyt>ycelc$b3i(XH%j9@sqiSC4w6M0?`4JOiOc$Er|&W-5^;?*cT=X^Pc*QoG@*y;lHZBuyBc6gU7yrJ#zu2p!$+Tq=-@Ng<3 zkDzkgq3}ku!@F1EjckYapu!ua@cvh8w{L;x^p76x@Lm8f7xC1-)X(Uka_IWHE%11~ zBrBL#qVRC)Dvuz2*Me7uSjxAzO$*HTO@)V3TzLfPn^5HG>)Q@*o5JhY4(|np*S{U! z;DuhkRNr(2*;fM|m6iStBodAwUbDg*WYZ+?|FrfUT#RoUVt^%m*m95u=}SVG+OM0j zu|(}kyfKnx=d1HxRd{3D;k~2q#qv`&KrXAEl_xq+tF99@NnuSk05=O3J<4BF0ZfFZjA~ruN~gy3U6LJyqgtXemlH- z6`pf`M&;1$`LYLHU*_ zywhx2Ag^5EEoq0hO5rVShgYfa%G=@9D75zf<1N#qC3B8D>$BZZQ+TDX|cK?fCUF-Y`oM zYU0-p-5^8luj(1Io1Z^;MM0*Gigq{8A$Ibb;xK(Vtpqq+SF+Pa&D(8O0YdHX#_9Il zcNlx_XM0MdJtb_<0mYu?=kxcdwv@QGG(TUkCtSyt>@HwdK5QxIPS(&@3;nh8F6Sn{ zD)_uv);x#4Uub{r&S56U)Njh=?~b4*ZGHs&NS%WYzVP=Jr_}T%J~e%g`-M0)eUg^` z-<)2xlXA!1s%T02qTL$K`CuVF+hKOAbMbuKHDo5$iQ5j05j&i3Fsc^dsS(yu7(O^a ze72&6G+(ELirZUmT+xymOOtsN?ryp9?3U&q9eA;M4pI~)<9m(KmPnE;`LhUFXonPW zNKl?nE84w0pHV{XJd-)k=I0B4>f~m$%8f$Q+`1j2FFFddFta(cD6=@T#8>0JO{cuZ z>{O@Lt|-c!x9ipJC7JJZFU~9q7w(;ZYr(FPaP!_5AdACuTj;N%@Ox`Y!oP=qzk@IS zb+gNtn_5#iNEj}D-ay+$TT0Ye)4_&GdJ4nWN?-DO!cDGSwpC8=ay28Tf_8I4td>(j zSodyfTReBbEgt3;MSDIIvHuPq7;va%bxZRPg4*q0tx`7cRns-!N~zSbhVmO3a`K}( zF32>-zB965Z~m>ebvpYpmt7Q|8taMiC_5I#Z&qwFe#ggh@jE6~hToB~HTWGC+l1dC zu^spw9J>*}17mmNw_ofL{PvDLgWsO9m+_k(`yGB$V;|v{?7BwDiM&@_XBs!dz9Kn( z8DqtDVdG}SQoZ-#o=&&tkfnvv(n4uzp|rG6T3RSAEtHlPN=pl+rG?VcLTPECw6suK zS|}|ol$I7sOP^M9N`vp22H9J*+v$gW>k46Wua--M8fu4KhOh-LGpJSnsA!LGIX+f$ z8oH(^d@wgshfrwvqOp5Th4nuq0eT~7jjK#vsn~MEc&Xc z?%(&i7RS@KA9Qm;+b_mw>Uy&65h>ixc8iif1o`kURV@QrerwNSxVt$)J@j`FFCs@V@~lzI))O)QvPIh{+dwN(rNCX@TwiDlw-$%Hp@rd8rEGRT9K)sS z?JM2E7hXaiRm+=;(q;JC^56@1xt#V}H|AR4tf@#_kRNPs#XR`J)5s-=d%Me>hp#FJ zbDmH*_KZxL^f{|r*sHhr&RKnwocf|I(&Q*XYwfb|!IDtTj;GAJXRsbhmEqL0KWw>N zl!gm3DLx4+h#exmu3*qJA{D<;(HFlxMFxH+iyn1Yi-p8Z`!iRxe1iE=82fvCK+@db zLcXX>vm{&w~Y&cOPNZ9n7bY zp2AK`;}2=dt|Oe$lJC=;-b!>S3pIYc=J8XbeqI%oyZC)sJYo>&va zYn?IJ&839vuz07xo)F$2~VN)=m9#2XxaqGIFT!ZdzHZXAgL;fk%vja41$7PKHlD;)eA!OJuE<$oaHH z&Zi}EJ}r^+X^EUqOXPf7BInZ*IiHru`LsmNrzLVeEs^tSiJVVyUWc}O(#@qX9E%l% zSH}u>H7}lAQ+OFHiavLsMEYXEW%zzFR&~#z{N$_TZ+1T}$}C!tRD(2w3{g~&T2nO7 zlBlOhs-w_|C@Pd8;pWV286u2{b;4|xn&4B=j9PXzQ@!b$lSI*cXwGk2vz?bP=sWGH zhl;sw?G?j05vOi@;=G!?vsBh&sjSCRS&yZ%9!q6Cmdbi8mGxLE>#py)^;qxbQV#Dtv8FV<_9J5+La@qr>PyS+Al$hE4cStiR~Cd*zX%U&kS zUM9<4Cd*zX%U&kSUM9<4Cd*zX%U&kSUM9<4Cd*zX%l?>~%Mw}kvM|c{xcQVU;}21C zS?=OpIW5gNYgzlafl~Y9N_I784z8ng>)K3L(MCGwEU;MS?e%QwMFTEup}iHv70~#W zB%Be#i;zAALMb;PVe+`=lsxHdpRpbZ++sdFxB-5@zdm5 z&EX$>;X}-`sd9#QQXG8Yw>1?j&H~NEbpgEPSzTHl*uSK5XPD%Y!u-fsvr|P zVvxBV_tHqV|$rAXNaGF_E2)NZ7*Wm%jo>iwLQGCa2JhC z#=ueVMSE_c5)@}*Bnub!2vrw{%{u&r9T8(}Svap{UUD?01m2Y%!#>Al2M-u21)0x1 z-@L~#^OhHj;_xSHglYSyzGGGA+7$1WJ73AE=bHT8p;!c~8}Zcs-MR8?$UY0EHBPE* zH}|aXg+uT<$FtSh>ONOvp=`PMov}Zpxf zG;9nkMcCirK{TuBJ%3V~(|h9WKQok^daCCwc}dt4H3kmBnKA7%7G!3y|Iq#k&bV{! z_#TKi#x7{FIre&p7&Pt*GswR-yE(?&zqTtm^-#(dx^V*LbbIf>z`AWDN_KE@hVQKU zVD2CvrrqjZ{xh@O6lU1xWi%HAo%g)#S`qKId|k<@?NL0+D^=a+!rc<(bKRAk96K$Z zZ3;3Asf4vkX=7UVy*t|q!pb;oCPoxmM+{vD_@)ZJ;lZua%7 z?xe5vwaFnakFG7QvAOd4RK&YJ*ydU(-%TBFA6ca2XbBVSLmRij==7e579M5o=p*EP~TQNl&%mpsf z*?XlcoI&lgwiWZB^sXT86)rd4-gTXl6WX9Tzr`4sEk{-C--K>{HpsdIZkiq@#nUq- z8$=!6`c#F#n(&sJTKqNu)dM%;NrOrFs|vR{*CBM0s1P|~vi$FS5tA|g_;rY%iTj{u zh%KU$)7Bt;OzK<>J?Dz`2(LuiYJ3oh@~OdJYZ0cW4dRe(cw!lL2>F)NBuLy7`0lXF zo_J`?i+_j$P@x3fCt_``tF9DcB>rStuNC+H>a|N}ZiynurG?hk)z#2zvFPqRCO*;h z`VEgQTlFZB=CyU#YDZMp%9fmHE!+DgFGWT3?EYyg!js?AWopX2i{<|L~_c zpLDNo6nJOaD9@S)`?hS&eyHp*Keu5+U40|H3xATwEdSomX8pSKo(ezHwS$u+%eU9E zA-8^VO=$eeM^5)Asjii(>4tXZ?L2W{Pce7R+diJT8ZSp^%$^RDPYmTcss!C1$jM%P z=_2!gvJU3^lR1g{B#n3U%A5N+QDw$s1Ba}6`#-)!A-5RPxMcZ+Gbi|7@6bm#eDaTC zUji7{_N?hvy~#&>Za} z+HEo=N4Cj4N0(~C^DzPp?pWH+9=K!q5bKoQDmyVNrjGPwSI5h_|7czu5h6*l@WE6 z$@l4UQ%v2OR#{Q~{eeEJtly|CMv||R-|74P=J5rSQv7V!87T!POIADW16Rx|`_Tsn zHu;mStEr2jdnc)uU%m0!&DpzmP4hD=>zeSQXpxkpj!P%s@OJZaZ~po3eyTLVGUbg)ytO7TUc9J zwdHjB9wrr4menxM(qiKDEhyWkcge2+H&su`p-%t^r=jr~)-4n`zqWEy9nFPG#Ab?+ zmRD6Ssamf_HB!{_SWS~pQ$2+)t={Sd;zO9*DbSZEeJ|5h?P^uN$eM~OQXt)FtUy|W zh3&iE={<`H8xfGLe3^Z`#-56bhDilgYn#@uo}V{wVZy$|VT2B-PP(KjR!Jq5MKz2& z9Di_qRTARrsxKXVSM88fUer`QQ@Xow7E-pS&a@rf2~=FM1CClKE3m87fx$^|^!P+<+@4ENm0nTH%sTwSQq=-f<{MuW;w>G*kx_71#6r0aP{f$bd&Ya0uy z8)DdP$*-$ztjA_B9aLh&xQfP>)`YnF$Ng>i2hRJp((qPTwbswSv8^(9ohy3wzb)h%n?n2Yag9LqKAfYGoc<8w6 zxzO#d3t{2e*wi4amP%?E5!31C_Bh0ZxH`{j)2I(RQ!TQ4LUrw+z%;c!{jQS&8;dys)n8`Q{wW zH`OVU3Tzm=0$tSM#nn^4V+NnYwdsxIzM8`+&LbCCQ>F9JNoqm|HhQI0ms@_%aGi%2 zSnifJRWcRXFn(tGR#+}0u8#Az8N3AV{1Pi{zdI}^(SCD6SM-}{uHV>eCf6y*ZK%YC z@d>+)Mu@A|L_$a1YwS0&%uck|&Nw=zT<8&VAO{?&Ek3FB7PKskk_yQhi5b#no}{Y{PNdybgQ>%O7Pml#5b_ z%kg7>D=?v}A-YJ^i&cNEe=u;S`xS0@=; z0=KfTr$l=Jt^EvFe--1LOTZZB zIRlb;ImGw*c7Cb7dVeDb2aAM->5%;v=5zbXV zGNP)%cjrO7w}#6Rq!&4g=$GgbgziZ1a-K5K=PAz3np9N7c+_%EqwQ4;H5M`A>M`GM z!(%!$w~&Vm@lv8a<4t7RmF6uftE;KOZKqZBn`1Rb@n>E`1lW?Q$-Cn>*M!Eou9!GeJ_J4WnDK z|D?_1#MP~@OFj~}t~j@<(f9aXC-zT2hil5ct9{Zn-%PY?KGGFk^S5odrZXc`p$+5y zK-Y}>oSYvqHn*{-FGo+OH@Rb)bKj~Qab4GR?p!sDvz1ZP2@Ra!5oq7f8mtM?TZ2`} z$F;I}X(IdeF}OxX=#P)c<%ln1 z#rNnOM}aidTJCe@_S+Fk1Hx7Xgq;%*wgq9~3-KdFYAC^%9kwIWF6Y|ms70UmI%77K z)-d+_T|4fB^~;eqo+V%pZtdFqkO8@`<-nAYr7GS&+D!&2VS3RW02n5s_!^@ z5ZUNP%Fg4&C|y7st8-DWUXPG(TJU!W8RYK|GRWT@WRUC)bZf>jxTkL(GVOA`LA$4~ zU~!&*yr)7NMl=OI#_>cSC$7W(X(^ptW7}nL*EjIm*4tDFl(!+2R-LcWExM^d2zsz1 zp?jMHkZG55FnWg4?>zPm>9UHc#D-C=c^4Dn>RK14#PO0FtxkoYyR8%IKXj{nm-8Qb zklXJ+{G^PmV=A&?+@v{>!-%T~9f+p~+204RO0);jB;4gZXoKcKxc@G1bFA9F(S%BD z7~f4%w$9yo&LzgxkKX;flU%#AS$pTu+L=l&iXJ`_KSI2dXh++DOuL+;{h_s^Ip-Es zUc+cfab7H{j%aYRxSwU5mfESajG1)%pKxBx>YQEp*8OdIBTf_i$-%UDfAsXhn?Io2 z=iL`H;{NUyXu>{S`qDQO?Mt*5)8z)T z$8BFy7kp(+_HBApUc>l#Y8w+a(c&{hew~s! z&m!;w5X-leo!hvi@&fm*qKexF4T06tZ7)i++jhwt=XbPr+oe_f+EDw(`O#@@_^sr{ z)p5^G`@C~7uk*_5W3>(C7i{X_dzM`Xbk5uq2MiiF?c3>#6YYRoy5hLG*mgj=0#R7g z)UZMJZ7Qi@oR@}~*Ncd&t38(XIp-16Z3ADqTzdy!$cqQZu|=Khcgw&$V?q z$66cUSl%N)RAg+)wDPV5Jns|j_BrRsqv~SRt%MkyXcwag2D+S!4Qb_K%3D#W#D+1Y zn}7UbLR`nNQ@RDujDdcnO?BZuJwYq z@Chu6oE4u&%1WQFeXPVeHiQL>q?aAF=%7UzUZ+k(azQ-hcPlc{hbGtq-nmps)Q>T{mLSW^uiFr@Dp$U3&q^>!;Bq%z{_Mt8R1MxWzkFZzXt z9EDFX4R7rs&Yg(lBesh?q`QbiiK~x1dE`El@K=Cz$x(z~0YdxPn1WgjAU{#OBN4Yj zzk1|;k?T6fs5{z&*&+M=koE_YhPUuiqFe8Ez@oTs|3 zmM^1{kBBJ#8OEUQIJId_h^v20=-$RvuA}_@(A-2XUKgTDyPOl{+lyD{sZwX-h01Ce zr*u~~UQ|k49q6<+2ADQ?T{<%IDBF3tC|kG)KSK0Ov=4R3_uKWheQ0rAWtHPU_M7dl zQvJt?j;rt7(T4AI#6`li!W5z*(LS*bnRdBxWwY%Q&ecVFcz8n$ufwFv2Y6>U{u#z& zG&=<_;_4x9wlzKRO=6BctuB2!_B%sjpi3c8K3%*x)^M(?K^c3rTNLT75n+2LDK*h< z*Co%V(rve+^C=o{$k%uS<}c)IZg^Z>?B7Q+2-&w`M85Ebqp&lVW_tskN79_3TMsyc z6C77x=-=ZA&X&ILg=MwXTcVqDj-D^zWJvRcQRE9wa9n*M=g55_;S1I-IZN<@wXEoj zvbyuD>Q7xq>k((7m`DDgM#a@979Y7!B>c7QUGgM`U)%0BJUvl^*B9fTVVvc2iQ4!+ z0#ZDxr=ps=+$juyEX+9}upbqckEA>Ib5gMl<6`oTHdt{TJ8o*jQ`+1p zL4p)gI0{CmcU-iC(-p8IMp6Yc@yg`hVuB#F)VH4HHm%RHpHD-6cOkDN z(MUNW>+T6Lp{ZeQmi^^MVc{$Uufj7zZ;5ovnsnQT4>qo_Qs!*1tTQa5JZzdU>uxZP z2NUl!VB%z$xWX}Ug=Gx3ZM@mF(L^A{oy_$fQ$BB85Cd0hpws}^{&~vLT;~d+Y-Nmarm8JS)&N2K7ij)>XVl7E!*-t zj}y!9N^u-w3aWb?I@Ai=K>wV6>^juXZ37*bMOB_|rA%Mv+IhfNk;%ub&oz&5!LG_)W4EYdKn*(|OJDV%I+%yKXza?AnvY z^~LMmKeH_o0lyg17^)h^aAj+0^?=z(I* zIBx^SIV#r-D}CbhRaI86p;mep{q`L?%}Sqyze4HRR{E?FZN?cB?1K5XeU4pwz1tH7 zlPe?HUYFm24{%<8e3^Kl7fhT+Godu``Y&B?8CTdQKH+nZV|T`NPXij`9S zv1Pnwo3`IqYsaqJe3wkaFlR5<(fO@h?3yCTG74-ADdE-nFG8+2Ig#&r{-45@JW_6+Dch%S=m+^mg>W;L80w)t+er$HP$i)*me7m z&v%bqFFVi=rt_|XJiUa$Ns8uymp|^z*@^#W4G+V;l3}G|j zc&W|n2ena~{!Q#&$80|OBN;g5Cx5-&GCnxIdhqTOV42c`kC&0+iP>hTm)V2Hbj_jJ;2hZO-iFEK81;j(OFIG+=z{p3~oPoK)K5WS2ZU zonox4yvjW%JznbVFS6cnR)3sr#9y09?RorNAlNVM`tZ1`uV;_b`udGiUwlEuKbRf6 zi)A~8z`yunnPsdxzE(e9CF5qn$@n&r6Xjsm2fuXHPP;df0!JXK1xFH2z40`Ew>}~g zjwDASk(5YkBrP&HGCMLik{?+>Z~bx(da}9q_S-~W@2zHG@9lY=(Xl|$F~5^Ks93fg z+m=9u=!_jvSI5?~kEM=bt{vOfbk>fOJRMs)t7C?zqp7nx=vDJ}yVRSfK}l!YWtyvF zYeQ%4Am?ZQIJ2`lPVjV`(ODh+T^(DObymkRPlve_N;*@gm9CC$=Gso`xJc1)VJCIm z;Of|7Ue`$-%UvDY%<@j^pa*c+Kg^m=>bOMFad9Vg^!0R5({^ec>*wj9>gbdXdUX!h zM_Ffe(5r)32X*~U+3}{UW2^ZFlyt_|>C&ui$5!*sPU@fyXcb#+ZCG+Lm6&&3(?K4&$p2v+ead@tlL+h|>FFTCZ=v%E;?|kx5R{`{EzvA>600 zgX{lxZR(&7dNDGWs}9z5%8sMaMqNqA(U^OqZo72;e28A{<@oFZ-Df-KA4g+7L(kmX zc5F2(J84H(@{glYmZQ-w^iZ?oAB#KLF7(_g>nNr1!?47{C>{~-WrQL<`}a;eAu=*@ zO)g%B6v{G;-l52>w3E_ir_C8ScVKMi{P1~89 zc5`kz?o^oSYOr=*Vu(dGOxtdVB&I0Wc?*Fuf)~h7ddr$PE6>i{zW_eztK)#j1ot%%KV~7 z9myKK1GN{=K6Je5PGpZvWL{lyMo47+B{HwB*j8VZ=}1PruIYVUvs7Pr`jL2g;%cvJ zdS4<-mB_pj=NDh(^#4Zx?TYQx=^oWXOi7d1f%@SZj(x3%U}ywjTG}bNgp@Q&EX1`{ zYc@h~eJ9W8*?(krA(D6CB$B8?lrM~yFJ3w&XL5edCRT?2ugpF6A2j< zPj{p`M^HT7ZR#9B@zb10$e?(-OVl}n;^_`h=Lm|YyE~mDD1Mm}2^kb$d6;;*ti=*-v)^IY&_Z;l>C1%Ne$Yp!D%B z|Kao>&VIVv#W{lPr#o4kV<`Tx=l6Rc<{Lt+#tYdO)>c++IlaER(f-<0)Fs`gla^G) z?CHc)MBnZpMbJavrdrz6u&JunCJk{FW&24>sv4>q5ov$q6LC1Ew4yX^wCx#&SerA* z&sn;us;bg?(fnwaMc-y+ix$>4@;8U`>uMY8>+HTX%B9ZrQSI+mt4yy1dwtBMjj_h2 z2B;CjQ#LDrqADBXW;@l#WDA{F=S!_#X>xpA+r&1gvwc+CMjv&AYr$C_)nO=Qn&|S@ zc|2-eKR3UoDpoJeo!};*4|j0oe3TRoU0YRQJN0mvL!X}aGDkyKC^S#iC?74ava;U! zK8MGlua$eMh~s#^=T|Rz9JMlG+q&xYFiMDV_y-b>TRg7PP&U=c-DAJm4%@NAEA}rv zHhpu|uhgTZhTI}~G)J44cYv?b#~5Xy9810aGRMo?b&$n*%J=HM>N+Km>U^Y}D#=q@ z6~Kj$=53Bu+kP|>bZ~II6HIjq=H-8ZM^u`C+&Qn}T&Zd-er=^i9#?HzmF!vYO^@u> z0koDi+5YKuj*EhcORHLq;Kd%3+N!XosbPaO(QD3S9)(QgZ#ge4l{Bx^tJ|P?eax%% z!GT<5r1IvW3O`ltL>_5*Ym(C}-q={}ClxiVRh4C*c7DCmA-#H` zkIr)kXIf#bsRl!CY%Pz1o;O5;xvJ}W`747ED^_%R#Zd+rrm5;Yo?@r=(RONRukDm+ zxb^qDiRv{=u2&rO8_h(bvuDKOpby7!{Wu@urC_fD>9e;?aJ}CD(bi1xZDsVWQl+xp z59)c@(f2EvfzH`J!TI(c+2fT;G1&bk7k{TM>KdZVA}+~3qY0c-oq`2?%E{~gig)PW z+93<`sF39gg+VJzE3cuUY9lalKC;7 z{PqqLFHWYFXg3ZbJPdzR7#)PE*~nMuAe;p`MF<$)3ihrq_Y!4cpEUe6CH#vgY@`e zu?yJahs9069zQJh0y}kPn#tlWVCPJL@P1%wCpri}1Q{iOgYdT?z4Q@5Z;~89kvL2< zBA$h$ah?vsKY^Sik&R!*-!m2bOZ@HWOA&7Yd-_tuyTCN0&|#V>;?Iy1B(m}U;qPe* z{ulo4&QSRYZWj_DvN%fXftqKVZ+EG;t!Zmw%cV0i5IV)5LfmznjSM;dC*} zhr5ehAMPO*0MB#v^$?}L_?}{!FTST(1x!9ihiUc{6~Jq4DDgSI^u5G+zVyAs7GL^a z;$q+xZu(y0O5jQbUk7}lf^P=){4GP=4xI1CXNa!=mnirk@M#Ku1bC@}p8#H`;HQAS z{4&IIz}G49F93V((_6d(oa@H-7H4p6nL>s z2fvT_5Af* zJ4jpzyhcfXDR6~?uLkzocaXRdxLS#)(*dvk28n&ZTa|d)3ZOTn&_VV*2)xgR64R3N zD+>M&@YfXl1K{Ts{A1vsDws}PUQ+ODz^^FyE#Nm4{Ci-peoqh|0Oz{#Cx}mhJ%2wz z90Fdh#D_yd&IuG`nkR_vz%eDhAMhpxX990m@F?KR6`TdUQ^C`LZ&2_lz;`OR5V(hn z2a8hR-U?n0Ob__bVVZ-**}z_Z8Z6cUZ?vOjd@V4|QFIW0Gw>E0O1vG|vwyI-68KUj z{(9is6ubxcD+=BRe4m2%13#ePhk+kf@Z-Q<`L*jY1w7B?XNungd+n7eJ^-dUnGVy;6rTcn^XU+A2-vI7AtIb)FV$@R5YZjj*(o*6 zA)+6!H=hj=nZUE8cG5pYi~`P8a2BvP9!JG=U}xvfG^64aV6QwwMIo>^-VGI{z+Qa~ z6U%|U@(vSc1Jjy^4$~Ya)&VcJp~SVo-uOC9YzAJb#BT@o@*gg)1TJvnhl}fhixs>F z_*4b&13p8+`+>djWVm=3nAT8qnC5WtIPiHkl=vy&ixm7ku;-7%#f!jR{f!W>0q48? z5#lZ2g$n*XuxIZG@d2<`{t@C+;IkC|Az-h5M~bi|l=>Yhx&wRlIa2fk_Qs2mA`{rN zZA&^*KRg0(<^2L5%XHpD40?=_iWmz+V5EC{6+P z=Ie=~5ZLplEKv&V`BRoy?n|E~&Ib0@KUrcOaD`jHS)vx$o6obvW?-+rCyDLAUil`8 zD}g=xCW-5TJ^Ln!J-+ml#XjIcZhn)+eqVgHc-V(?#N$3ZMLgxhQ^oT>JWad^?A6C~ z@fxsq{xn^@1)S;TKVAIZmwtx$0N5+v4DqQiex^9&!?Q#BDoxC?7sqWclzZV!98{6{i4u_RSTAzW7{G3hW$)nJ1PjIE0UcuJU11oae(KafJ^j ziQ9bG5)b)sSp2|;lf^H6I3oV)!zrR$#IX*yu9&G}h!3ZUSw7rNEc4-XvB`(Ki)(zi zhxn=w_Y}=O+)KRU!x`EXQh^5LQ4S|1)J?)Ty0;u#+vA>Q=ik>Z~| zJW6EXz9Z)dnWM!7A08v-`tVq>+=s`BdLJGyuJhpu;wwHpQ9R+pS>h!ho+SR@!;{4! zAI=tox;fU8|K*4oK0HN~`tVe-&WERo?LItR-0H(K#KS&3Q#|d%v&64`_$2WcAD%4^ z`S2Xk!x>CqcE~(gjPT)8#7rNaD^~b$t~k$!^TZAx&ew2(hUaUzP{Ru}T%_TJ8ZOrG zA`O>lc(H~{HGHau%QSqNhL>n~sfNonyiCK(HGH~;S7`VQ4X@PjnHpZD;j=V+wuV=0 zc#Vc*8eXg63Jq6kxJtw8G`wEJ8#G+4;d3;6u7+zgyivoo8m`muCJmpb;d%`>Xt+_s zO&Z>;;qx`TMZ*_pc&mml)bKV9U!>vf8opS=J2ZTWhA$P@`uhK68ope^S7`W34PT|< zof^Jc!@D$mjfSt)@O2u#Uc)zN_(l!iq~YBf{*s1o*6^1#yhp>gXn3!NZ`JT^8oph_ zcWC%d4e!(NT^hby!}n+d1sn?5{G_~Vl_zNO)?hLbfM(Qt}}Q#G8X;cgmE z*Kl_Y_t0=p4foP;hK74|4i`?V>|z; z;#0;8C4YvnsGvCLo{S9KPa0)R_t0jTNn#S?VG<{cxs2(WeTF$flrpA!pfb!8#cIZH zN<2t3F$R=((qGJYfQ*ldn;F~ojTZ+QpCscW;wi?p5|0)?XH3`VGtBPd4~*#^i45G| zi7JqXt?y*f%ZE=ACo(=!^1F#CzW6DkfU)gglf-hyQOUPN1!KGXBgIz6%Vc~HaV_Ih zC7vtxGp2j&GR%SETRuEZJkOY}(P!ZPuD2N5%9!pk$}q=@5OoY3+4z@XP8NL_ z+vV*ihB2o5x-)Qp;Yp065{E?*;~5gCh*gZ&Njyu?<#+2-A?UJgpEpf;F9c!of5PMk zghw(yQaDMt`-lllEEKBh^CO@V4ejSV_cOgC%J4m0d|MTKgSbuIC`af^H zULSK=e_k8<=Wsmb6I4FEz7{fnQ5$^S-ox=fZ++=}JwH8OFCX~@wI@wWR9@-_glT*r zT*SDT@!|B963-N370Yv2(s)kcdVadSGCl4Yk?A32dPtcbQqNycuj|i6zEmC>AE-Q^ z*B^BKN1Fa{_8;x|Bh`1b%iE9JgXXWG{-xXdd9iMk~p ziBnjnvP@&yjb%E^?kw@(kWAN;WiOT)EPJ!;!?G_+JYXc#^=CPN2(5|BJ&fKsfuyc`VNWkNo8xKVH zy^zvgNNF!*GNp&?#*&^Da`pU&^=xB3@PDZX@^rEb@=TWFC_V5bmh_B}tLG5wxrp_k z|42QMvYe2zoRAYJJtVy)gX9cVPYdhW&U(=Qq#nqXWC!HgEPGRW-~lW%RXxJA+Zhj< z$@WD5m3kmoQ+mh>mg6Zs@JTG`Eg6L8tNIMqw}bUz9FY1Tr9F^qNgw1`N)I`c<;g7R znJKrvOxAY^>%({=^+C#dhm`dWc@w3F+{5w?RZocZT*`Vd9!Wir(k@787bLw}BLqqH zO_J<#?ZE?P)qtVPSdYniAlFd2AS+o;r1Zd2A0(C2)nl=q%UKV`Lun7Btar!?(gP{$ z9da`1gPgAF3A3InSWgn`fs}e6r5?zslpc~EJSR!*=h_43m*v6(hSCo(9!q;5r9VQ- z@cex=Qr}gq597Mj2U$hsf~;m)M(Kg+SvQiEEYDH(rLex8tPk^p z)CXBfdLTEjET#0o^nwVIYgukk_2EfxY2VeX5A%%F2PySIN_~)fDLv%sU6adb_h;Jdi5= z2lKMj3n|AnNa;tAa-4-k5k&~nH_rB8J=e1y%FyovQ-T_W{B%6)2?W#T)E%kkg^^hL(2Ib@@B>dSbmS?%PeKS;Qbod&95Kl_hrrx>pPhrq|6Ue<_9VD zLdx<${*?4W{)Xj8EJGnXJi@X&q?=!V&TkLrhjpaP4^q|}q^vhc*^eN7<0PC`*844- z9_vq;9#Yx~Df=a)oOdB})$-y2W|@93r^mWgriYY%1u6Xsat@UTlEw?yemJR2e=DaS z!091n{*W?%$Wtjj7MSXQh0PGEhvvA%(<4^pnPAY;R)i;>+ z-Ol<3u|7yyK1f+UNNEpbJ?ViwpXEiWz7tvB9jxyJ)(0u=f|TPmWDcc=%wt)|lEy{1 z{;-&m^>-)h8_fD3WqBc`UdTHsJ>-Kdzrm9H&((*)Nb1|i`c7nhkaFCIlzs)dp3*~Z zW_ck?>hG?;DC@h6^<}a?$kVAEAkSne*9X9~{-W?AmNcKb`i8Q;yIJ25)(0u|K&~cz zkaH)i;dw-NX8#tPfJQFQjZ=$c2<1as|t?SW>&Y_6=u!UtxViSs$dd z3sU+sB!(stf~0YpB&y2OgULX)!&h0)FxCTk29*!;ES8HYJ@6`)F_zRmu3aNp-@UAF zIO~Iy`XHq~Nb27qNZH>Y%Neg!^^IbE_p!batPgS(*##-<4^q}U)X%zMzTIgsSi@>gOvRMavAA^B)dqiQT2^sefP7zQLGPA`U#|L4@fkb2tmsJ204TA z$*Mk_EXeja!1_kBK1gX7WF?gw5<{|-7&@eci+SyU$zAF>$a==G9>^G_hpb|Wp;cl! zU!rhYAGqy_MY+`THP$nh^+3w075vU_B48o^h-PQr0`9EFYv? zUqE8279mLTTi2e6tmi@2GoJN8NId>9 zvIA1~b4cHL;3U@bFzcDfdLX60LrQ;#r1e$^au&-|SQbFK<(tgv57MCYkYSeHR6Q8Pr9IzdJvpogQtE+} zdLX49NT~KiAk(w@gy&s5d}xq|8iQu-%k zGL;9C>>x?~#jPI<3R2JGtY;eQft2k9xq*9xIs9Uh2)~=d zALa1JIs6wK{s#{K6NgLxp?aWtr+Od>J+dDoyo|%kIlPf1!ms4;T^xRp!@tYnPjmRI z9R7O_f1ktu!{I$>U53_#~2;=`@9A*4A&h?=T+D z_+7>r{G|ThGaktpgO{uytTSc&dyGdj{v+ctjNfNGmN5oBnI7venf}j=$20y5W2}c{ z{0EG&zLEGt##xL%VvKc#jQ^N1)(H~-l`-afiT{sr4&%Qup2GMO#+W}P|5L`(82_E| zbiST5%Md-ezsu`BCox8Umv}Z~^mmEpFh+lu_+-ZD?-HNF82w%1xs1`@CC+7x{w{GI zWAt~4=P^cqmpGp>`n$vhjM3jEp3fNlUE)H<=zmcZnA=Mt_&Mm@)dh z#ETfCze`-g82w%1#f;J4B`#%*{x0#UjM3jEE@O=TF7auM(cdLr!WjKs;-!qy-z6?* zjQ%e1GREld5-(?r{w^^ld)dC|?-H+IjQ%e18H~~2C0@xG{axZS8Kb{TyoxdUyToTP zMt_(1Y{uyC60c^A{x0zv#^~=7#~7o(OT3mb`n$vxjM3jEu4Ihp+AT-0btAc0^=Fc*r5ii&u{ii&sIYD+;BFSXu9rIu3LQZFsmOR2SrcUra8sx8X< zo1K~6XJ_|J=F|U+eLwwo`Ed5kJl}n0=GkXv=h^I;g;SbAGv$@kGqH8xO@1EyN92+d-#XDhhMmR_=CHLAGmv*e@xTU zZIx4;=GrOw6Hht5UVr7opoxPj9L7IW?q`AfS?GQi`LO%y2Tm2ck`ni`)cqXgemePL zCv-VNnIp70LY-425TU{mIvk;WEVL90EyY4hvCvX1v=j?1#X?K5&{8b4 zln5;)LQ9FzQX;gJ2rVT-ONr1@BD9nUEhR!rsnAj?w3G@hr9w-o&{8V2lnO1SLQAR8 zQYy5J5?V$HEu(~%Q9{cop=FfNGD>I}CA5qZT1E*iPQFm%@45 zz1op(?MT0Nq+>hMvmNQ$j`VFuI=53G+biAMk^b#S2X~~0JJQ7+>En)caz}c(Bi-DQ ze(n@X`$HLoLen+~$BmLiz9l()2z>!_Rk$u3CoxqX3z>(d+k^R7t9l?=3!I53T zk$u6Doxzd4!I9m;k^RAu9m0`4!jWCVk$u9Eox+j5!jav=k^RDv9mA15!;xLXk$uCF zox_p6!;#&?k^KYj3v|cal>nxFKT@)Pq-6g{$^Ma&{Uas&M@sgOlAO-Tg_a1q<;rAR-k$Bw$UOM5v0f|cFn>4~%QLua+ zgn9*mUni6bQbWeI0C`FW~f?Y%4BG5UK}MxevDwv8Uq+Sbz0gf2U;uC{%Cbwg8qv-;lH z(1c-K<@G)K_YHDj+>XxWf+qsMDT2%tt)YqDpnx^@_WN~|K6Lhqy*YJ5xD!dUF z9n}K2XSlshUWqh^KrZY?hAfex4u=n`VNX-adzE07Pa`Eg#PvAkCNf(&Ig-Iq2N~XZ zY2qqzeUV*99!k0b6=M)|uW-oI&j+$p3-InRQj@St0*x4Dkn4{JNGMkd(qb6qT~Xw_ z?uW18DC8VbsDWiYC@siJwU z7SuptBNIcX96xqJ;&v^O#oCamubb}0C;#f^i6>uMwBaByo zQtrz%1;GOTJ2?&vZGOKA8`K;4qD1P76qex}{daQA1MSgrNK@mZXDaT}WJVB`|KG_m zY!sXeqaOz|)QrZnAH80NGym5o$AOvdzc5p_m>gGES5B#}ZEt9tS6$PFnR#t{8=peA zp1Y{6rk0IpscRJN)UQ`zfw-aL5mI1tj5#kuDZ96?I|O zrRrKjYvEmj(jBBvi*%);NOjd9HWX6@QD(GQ&k%n%a-dk+>PUcUcklhAD_Y$Dp;F!? z@vh@gk^a;=y(q#Bcx{6*Pw4Q-bIy-Td(!FUk5-=_L;{vjNq#gCB?{ap($%Wl2Hwmi z0+5kYlYFSTmnrL)%*1YiR2N`7Pa(2od@Gxdr~8KgYngLb3Bc)pHGe zjU$~~<55D!ll=K?%56jX+gu#xd;=Y$y=O$^~GH~M*BxO7~TYgvVcsvb< z=r~aBKfsl71#&~u-7dx_|E~1$=d9a=$o*8@cQoz+a7_{1BN~^)bIuzgIQ|?uEtkKm zabX0vTjTQa-16uMjw_@37J@5|;P9wffV&;shzJgkI0d-pz}*$W;nAW1$DfCOHiE;W zHvw)O49=gmR~y9cc8$i3hC||UH*Zs4@6)*1SZ`>vM~Sj{@&%3K@3h(#!F`}{Z-9%d z!oaJq{P!9ByYiPeyD)ZiguZ?nmy5-Y_%ozxQ~C-ut`yuL1!1o^{`)~%ZWXw}5gh;B z9OW(s_oz}r^exr6(OntCV`|=}zTT*DOS|D6xJpR$J*aW7VC_9T_U>)!kY8!s3wWRs zkGp!C;@;G_9Xl_v(drB!I++`YfG#2-|KZ0AYaj${f8NofNara^|rzpRFS>vw6Vqzah z==(t9mi1-q&Im4sae|vc^^buEM~@r*G;RmDsD4zcaeoIFWtXWMx8V@xzQ0{nQJot8 z`w?2d(+_3r6$N3hxMdob!UgZa2<|$Kdk0)?1h+}!%KJsP_h%Z{l7@RzDUWGMd|@afNBP$2IP(G~DwVcR9GI_P(WY4}$wH^Ec(E8R%%Vy{8Uf45+s$ zE>Ch8R^6=)+~XdFYn}W)RB}o*VjyGdQ5StH)wtgriFakI!U(K$#~p=tT&uzi-0q=_ z@!zoNo38I_OkUjIHfo^GeGeA}{0uX+>D&{>^2K-LOo+|Sa1Uym{^-eYq0KDU!9F* zx-nPLH=WCAw)4M6EC4gkqJEoOv2Lja_m_6OL)wCywUn{uw*d=;nk=D6mpTydt7Tlk} z!4*QAuJ6*P7`r({h0E>tH0Dhf++&v9jIDO{`w|?DlT{V;cHHq3J8sG|j6r2+)Ae=! zDP!m&p-t!R2X{+|3fphWHaqT3a2Se0n_lknpE35m5EU->(Cv(U--3G*+(Q;z%g=*x zk2*xJ->_#HyF&@dUgv%d&gT5K{~~yQQmNGS4fv&N&<4f6 z<8OlZ!_w(H=(mhvC<<+Qxi5jU@zW)^Nod3MdCAT$zX69!S7_7gcggR9_s!G+I#&W` zu^I1wZ^>Qwik;v0f%Dne0T+3T_`nv44 z7iL4UTZ-vUc+vnBVjC0F?6B!%PhIeEx8?*T#t|K z>Q`yW-E7J2vgDGV*wt^IC3h#dX%^SFFD&(q{i|L5R#8}gZ5{TeN~`z^UoExFRa+tqJ*8tzPOUbhw8NaFYEtImA{Zh;b# zz0S@0Jor4ELUryZmfX-U?DXAW$?XHzs47MFdi~D+(yrW>EV<+UVOQ?mmRz5I+STtO zOYTE(Hg=h{*N*!sxP`>N>Z@+&;a}NtH(7GAukG}mZOOf4$sM=PuG~$QTrWHwVq?Ga z!P%U*_bv5JkJ**`q$PJG9>%n3$F-K+KfzTgXCiyuuV!V~aX+@?y5r`ljh)Z4%OKwcIoxUG}v$0Fh&UX6F181Y}T}yqZ zbg?V<2}|yX96Np2SaM&2vuST#u3fp$gR{{$rmG#d5uA;m_UvZIooC6tZONV7-LBln zEV;vb*y+0(oQ<8o1V``dsUh`jZJu~cPw}orC0F|;8n*#lQVGdk=eApN?^tqK2iTQ6 z*pi!U$<+T)ic?%97h)$!)jf-m&DedRyAhlACPF z)mw6_EV&Jq+;&Uu9ZN3jKuh~sa+58&dP{DVCAYzn+iuCdW65P5WNAN3Zn7m;Z^^B) ze z+y+Z-yCwIIC6|SF4OrRFlACPF)u-Vu)#i1pz#T#6bLy+k-3@M#5|X{nJ#VS+Q*eh9 zJ?g8jug@WN<&FV2SScZUU0)5jp+v5}>fCB@M=K%O>)gZOY})avr9S>n&S9iH^;Iu- zBsiOPoNmco3T}uhjO_Jt?*Zo!x%#SeuY=21LbBJnZg{tb4RL+!Mk5<$}I*rTqz-YUEf@AHs!7cXXEz| zgR>g1z}cKP{z5*R_6`GQbKYiwv$-BEx8&{sXEUz-!jk(0oQ+-j4zROJ88{n1I0u|f zxi^EeY427`?mcie=dIU3yYp5GZUFIj^;P%#)4)U8q?z5KM``~Q+ zwAN|62C;Nm2`72IN62*=^z$E2VKB=hxVtp&4RHBV zUmoFhXk3q(F*Z(e{RsE2#!Vw!f5OGlS%7-m8gNOZcsta%k5k45Xx#mTQ}Z3p9jkFK z5Khg@Id_)EeM~qt?sM)!jq5SXuis$E`Np|*8kbMFBV9^xk89jC!VMwZiyF6>a7Pht zkH)Pb+|h*N>mgA)-w#gtv%3ECb_~_Htwf)?UURNYaqbh1TR}K=9p+pv z25V~PHH0hV%CK>6h{oMcxFVMlT$#q*Pq<>j&DFTA;F6GYJC_h{xyHRg^pz6sT8;ad z=o>}2A8A~V(|kLRCfv_8E=jmCgxjTY`GgxwxKA{09N~^3To+sv>G_yOxMK-7P~+x+ zOG3`=cO2m+YupN=Zye#~g2O!JLYc+ZfTQ)``P>iMG=1y9@qAwHN)BO*;?@)HQh`Ns zn+dndz&%K~%M9EW!d-6Qwh`_M1Gj^4R~opTguBYX?IPT21Gk%SR~xuJg!{IE`;>6k z7`VNJTVvodPxt-cS_79$xa$mDZ^B(~;PME!*1!!S+zke97~yU-aD{}s$-s>z+|35A zjBvLYxC+AEYTzmfcbkE$BHTIyH;-`NF>sB9`>ug&Bi#24+;YO*Zs1lD?hXUDnsDDY zaBB(o0|U2?aO(}+dcytCz-=bn1_SpX;Wiq$Erh$%z-=SkCIh#FaCaHForJsF!0jU3 zW&^jIaQ7IvJ%qd0znLytDjrD-7H`!c8@B zn+bQ4f%}wjCmXo2)qeeWyZIJnzm?#WT}}~LB)5}rry96Hb9{Z%4O|=HDh=E=!p$&n zy=#0wooV122{+5YZ3CzLnfDXEMcFU6*5^(WSR_|TxYG^XI>Mb{;C6#k=dH@X70&g! zGY#BIaB4g_%fRgdw-|EXkE#t^#XO&zW8k)c8wWYpS7YGz60X+3jji+b%{6e#!72OA zGjKZyS7+ez>V19n2Ck8C^9|eub!nGN=2MO11 z;Pw)3iGeFS+ppiZ4BTqMEj4gE!Kw3hu7MlW=$E_9z%_zX`pz?OTZq2p1}<}vU+(z^ zu7YqE7`U~BQ#akB{Aw5BRv7dRYVzBAk%4OiR}MKJCod-4T5bNf1>6g9!A&6C4>fM} zIsX0AZ3b=~;eKY|HWO~Uf!jj3pBuOxgnQP&?IPSS4BQ^V{nEhgCETwJTyBeRza0iH zk8r;>aKi}qoPirlxaSRA1>s&Wa8-nR(ZDql?l%T*IpKb5;8qiEr-55XxR(svX2Si> zz-=Mi%LZ--;a)Lty9oEHf!jm4*9_cV!u{UB<+l3%x68og5$+ELZW!TSH*jMK_eTR) zLAW;zTovK|WZ)VJ_ojhcPPn%W+-kz@HgM|*_qKuCOt^Op+!n&UYv6Ve?mYvyi*WB7 zxIKjXz`*S#+=m7(x6SvzJq9k1aDO&%!wB~m12>j%9~rm`!hLMustEUqfomk(Uk%)H z!u`#_ttQ;325ueUJ~MEe3HNscw}o(@8@L^W`@+EOBHWh-ZV%!9Vc_->?wOu`J_A=lIEFbJ-}pRHpNCZuE@t2w2^S~a!`i%VIpHQ5xYdN4 zY~a=r?sx;YnQ-L>ZVTb27`PpTJHf#1BHW1vZV%xq4BTGAO*L@2OML%3$-w0i?qmZu zjBwKo+*rb$V&EzWcdCJ_BHVNX*GRZZ1Gk)TGYs5n!p$^r>j;NOf834tBi-*e6Aq7% zq~*2{4u2v~%k3Z>{*;uK+eJ9sQcuh6AslXPr{(q%4!5Gya=G8~{SUW<({g!)!!6vj z+%Ur7mTOvWEa7mAG%Z&_INYjC%T*B$w-(cKjfBIkz_i?Q!r|6kT5dJraH}mXw~lbQ z<&~D(OgP-4O3Q5_9BwJ4<#rGbw|3HUy9kF{F=@Fygu|_qwA^08;TA?(E_bQ#f4Jq4 zmdhhtvw<5%xWxu;Ea4EUr!BXFa0sc=a#e)G)Hf~HNH|PU(sIiQhf7IXZZ+Z1<6qJZU^C(8Ms}9JI}!FA>48Ux0i6|8@OClz6V;#?}uGr;PMD} zp@ADlxD^I&Ea5IPa215R*uYg0?h?ZNLYvn$g5%dc-rki4u8nY)8o1?zTV>!@67Dhs zx0-O58@RQEyTZV&Bixk+Zav|yGH{y-x7xrxNVuyF+!n%p+rVuj+%*Pn2jSKjxSfQ% z*1+u|+;s+SH{q@~aC->1*1&yAxEl=IUc%jI;4(4zD8IkSz~vI|W&_uoaJLw^Ji^^- z;06)yHUl?|aO(_QA>qDb;KmZ}y9Ta|aNjd<6@4G8MwWKd)UBbVp65X zzefyQF5woln1Rb9+~Wpr5aFIMaKi|<#lRI3?nwhTmT*rQxH7^$ZQv>hx7EN^ z67DAku8MHa5bh6{*CojBHRgdkL`>HMpC5tCKu%KTUI4D;fB?d{+RruaV@z6N-NM|G zx|Y_4=B5$NwF^fku{k9r1^KCxe5W9p%;y<_&t$T2R6((uot)FtXsE)C# z-Lh3FTV;8LZf%FKek_k|8ZzgWircc>H3BkSF!Sw!mppRMkmue_BI#yvjTuXt8|E?h zC(sh>IeY!9zq`0}X#k7YHa9o2Slsno31X~;CH`UEc&RtN`!eUwO zZ@(n})zX9haLJGQ3=i_{O@Sk_-Cw=SBUY@qu5r-XlfDQZ@hz^qx{bxN+?8S^yZOL< z%ba_rJrrbH7c{rDu~@=gBSeywTYf$2_b1&kH%NN*kcV_~m-mo|-16B~8ADIMe^&62 zh9+0_aHf9xoH_4+hYmh$&YNEaIZw5FKqqSKCFS?s{oM4PCk78_Y;Ky*;t6WJAJ%kx zz4ZNwJA9>RXpSbhey8=hVs;k>ki-HvFmlvO?w6c_c+~Z?jetq0C zO-BTe^Nu<&W3tlhE>s~cRJbf>-rR;K4-Om^=haHOb<0e+KVz5l?gO9PHnePH=O7(u zjXbOqJ;!%nI$_$+|8nQz;9>QR%{B0bOm|%cS-=&Go>}5tcV$tKoY&l5+gQgkGpQRN zbIqIEezt4R=Rwr1xz8Viz9Ln}MlNVxR5!A{wyC|fu4QCf!^oDp#m%iF=ce-W^S@Qo zQYX{(snUXyrSp(#tgC6Qt6qHe{E_oo8ZZzvHq?$(Qa?wH5aOx1_&YFL_Fl1hyz9^s6r zsGJVL;&WRX<}YYV4w-vY(it_Xcz7z`DNR<^Ev;!yPHAdwYiVCp*VM+p&uwm5+}u*r zRyU8uKK-T*$guG<_Mc|R_~)?XOmQ`-o?q8i(NHT>yv1&lV=+f{;%IO``Ihg&g|Q1V z_|=o)TEy$r8=w3Nwy!JS@#_xH;QwQ5@tMi^BW_$UHVEwZilSJ|2k^WWK4Zrw65SH9 zXR_kBgvUCpINsliqxNCTL<2HohvfEV*;(10va_>0XLrfY$($0x zveyN-vhmo*da{h{9({V{9GZPZ_EqC@+^iVS>KQvAMzZ50VzFKs**tet&gh&mImaD5 zCE1j{YFzeZ<8m$^m$P;ppM_k0QH=GBT`}%puIC`A7VMNHI>8_$b8?PF5gB9f6(%1a z>(S>3cjE9(jRAS6muqR)Ns+)N##Hfr2zElw2Mhkk$!PE8^mu-HDyQ&v;>?Y2ZLM2` zk-ddw_vz9pH+~>8=cY=R*3>qzSZ5?MV_DqWw2fwE#y^2``dbE^pqHOy8S!{vov{pD zZ$<{>2{tB>&eGDIv~)I8zrWyzWyCwP%E0kmSZyGkp~-WYdj3`%-&K?6GWDFNkauHO z1oUbT{w&HyWrj1e2>I<4#ADw{9Kvei821{F6Z0jejYfU z=6{Rf`@hQl7xZ|zUti9{AGvd6-~R=AC*D8_`y`v`u`Dj_&0n=DD+!hNk*vCcif}G}Wo^^({4v zyhKfHZA;w}C2Bi&ab2rQU_PS0*0j_#&G#jXF@uAS)^wwcbrl2U{R{QAsA6?><&^5$ z_J+oJ)irHxEe*BpZM-3^=PqiisbwQ7r|_?}&5a{!8XIaLz??H+Ge0fr=ci@m{S0YX zKf^PdpXHg(ExB%P8;@-38*AqCI<>X9b!uH8zom1Ba6b1P{-666-wMUf`&7P#;U>hv zg}qI2hf7Wg#^THI@Lhf5KCO=7vP;0Y(n7S_aQi5hQ8@s0ZztH9YT68{?q!M z1+F22Ytp!%gG)wm=WE=%;P^PDZ&xD&r*yH(?}c%!Kqbij2l$R*(c8+wB~jr+k<(M= z^6~C&{Ku(MKR;j#aD4lo) zbYo^S|2FByvTm`Xj^D>_J8aE_{sWgxTCp*E#j***H&#trkr5v=bH+ZN-uB#%=Qs4v zh?iZlv1-iB)Aw!2y8D-R{c2nPLzb-iI?G!3gyBNthW^QYY}ur)o35NRdqbAe&8}g~ z%C7LWul;|}J}yH0xHQ@)-PpC6#V7PXxH*o`gPJq(*~`u8(L8Af+qdcRPii)-K#gM? zyMI)(;c|S7Z|MH#nva@e@eTbaUAJ$|rr{g1#>^~3tCHtV=(Ood_7r=#%x%}~ees&u z!yB*1=TjT56Sm^zWxM5dam&m7m&@aJ6eVtZhUVY!LeEi|W;AyoAQ`ES+P6 zlxZ+VIV=%>yCbOjc>bOc*qth`*}~Crunb&EY0z8HxCNozw|% zYl12SYf^!+KM{Xlr>2~Q^Tm&JaQ8bA|3H^dteD^yQOM#Df2fO5zlm=BG9cX(l%_-# zu=9{LA!u|O~{BOEg8YG2aG7m-i$VSmT@Hh|Mu&$${7+ph4N`z8I}zU-lopFBz%IT) zaue~dI-;aOfPSr`(jce|r2Dc0eWJLU8>CPe1Y(@vfV@Pn4lL3w5s!s1&m@KTTUa6< z4*|+1a1zKfLUL)8LWH7;IBwnqs!=Mcf%D^ArAGqeXGfSc3)rj>ixMY@fdt}CAu%^h zkuVJ8*_wQmULzRhfJD4=2=fe6#9{!tga8=Ebx52a$a6w+RI^NsClKcb#f}_Z;WfTt zdMDytJH(`6z;+9<(l8iOAnqO#bHfx1!$96clgm-ouMrG$P$J$lgn5Q3#x1=>{D2Uk z3@dG==q+!4w6k?@eFtkA2M-$7@)GrYYKO_5g%n{NTGm7YcO{tUm*%THW43#5S`!kmtn=SXFm9};Nsu)4ulmM zVj|#%Bvad$PHb+fZ;&lsUR{Dw82kW+KQRn>vjY)? zRfGv#5l9#|H4LDdejs*|E|(Jo?6^O`COF|IcK}JFfSeX4rBy^Ac1l>z&Ekh*r|N*5 zKFIpOE^xT%VaT(Kh{YCZ%0O zJa$@G&h6qyWT)#uFeZat(9g~YL!MnkNLCdlU>6dUof!tCT|`)RmM#wlX7Cqu@9GX9 zX%~=l!lbl|2+L~1a&8wtFss#pU}OfnV04)qhCI87xNKgSP9>I1sy=L%^)ufld{bsBwG=dYcbhHIuQ)Y zU=;*S7l$EX6%mqM5*90~z!Px%$}k|UB7(9@b$L`&wyFb&Tg4B{F4O6#xa@KriVDoG z=l~++A~L&Dr=vo%t28JwHe1~RM9M{QcC}7NMQ7jEp{VfenhqdRF5RE)M(hoXYC8#;hUxrowk)aj@&?Ish%oK(keJ)UkJ6sdhM+InG&5X1M zdi+m9ptOew&z=d1xjp>o?5CPMDmdE~Vmy0@*z9K^K-oitX4^w@X%7*Z{ah1A1!m8h z8EFs1Wxoi4D9aDaei;&Td-ze=uQYj7P_`q)c=ix6*{?$Y>_I}Z=R$JS(T~WU4~ioL zvKP#Zv#YzYtRaH0-65&6hKRl14#}l8MCkR7CXR}{ z-ZeAa8h+sQo(4z7UGHm5RM_=_nIVND>iSTFqk^tIK_)Wh`m>oKg(Bqoiv~wUTpwvn zRKWGInIVND-ugs?qr$DfYD`qL^*1v^3PrH>sRl>ITAyi5RH*fLGeZhRr1iN5M+I76 zXiQX`^`)61g(A%QhXzMQS^o?&kwMm8GeZhRjP;cUM}=5lBgEoQe#^gyRebhI-L4-z zcS0ak5Fr-2KaH^V#Z*|qevF6tO#9y~tEgt~g#i z(1I%yzweJ*LU@YAh?MiE^SVVNa*|%b|G3lLh?MgO^?F1j@^26oe5T*ih?KJgo*;=v zF!YNSAsp;wM9NtwJV+9aV9XX;FnK=Eh?KL=cy=Tjkx#``@UXLw5h-Umcy=Tj@or{f z;(D+VDQ8{r3`sO1pU9}-;q9SDq?~ofGbGW7^cOt+QNi#0_v?r%XFc%{Ni-$B#?^(p z_J?&um9t)WkR+OtzT@h`{B1x-R5?2kkCjAI(t})GxaEC#M^riMgXc@4Dd|V9F3h8j z=!hz32jkI_Xo@~#h1=Rkc0`r4L-ABeG$nn?trw;|M|DJ%vwnE8B$}en`ryX!(2l5b zb{HNiiHm3X{PD>BhUca+%;ZN45m!U#L<=z!g)kK@#JmW?f@on8emsgtHKK*Zc#a#- zXoQ4fx;CC=L0X(fI)Qb9v?L_OXfE%IWJ6w>R$jz9Lp~}>F5~7dkdIC)FJd{6kBO4Y zxGER&v1#Q+tSjWlM9JmUyc^`lrj-}5?vNiBlJj6m+yev{Kg1G}BpA?q+kH8%SU~&k6bBJ4SeIPzQojAq%LR_9s zT)+;7cuG2PAv*-(6QaZ-a6c5{6Vr)PEDz#}bm9Wm58|om#D%Os#3x0G#SOi~AU-*r z7%P!ro-jR~7xu1qIJ5C-v#D6za50P)OpV%#@|cvd=b0j5ECsv(^izt4d9w2+uS zZdk!OfjQmCl(TFwXQW|pU38yB>_$pLegktt`nV5-wFxE{KC zx`LTwWXf4LFf|bje-sRJ2UkybFttXeob>=RHw~lg(-X`*BU6qaz2g~&G>o!OFEI5+ zrkwQ#Gd~TZ>~kQP1xBWv9R#KUzd#)2Py1hGKY8o=8=HbZDiYKFDNXoc&Sd=R77xHJ zjH~&5x)q-=(Z|&j|GOAheDbhF2P;1LU|{{Gv@1UOytmAcSR*R!ickI#9k2N0vmLGY ztCLHsQ*vgU9h@ncSle%p9*Yr(0jjD=i^bi%Pq`ln;9C5J#k4U&=c|Hbks1 zmC@n)QvPxN`cj!4t}o>sr0LB zdAdxR&wF)Oon|!pvUI8awIY@Kd)c|D87|5DX(gV2*K$jxx*u>Z^-N5(a|MnIx)wPwstQ{ zOA-b~ufRQYZe!tDE0t#ju?QTIH_Vz z?pyNOMy`v?U2tkm>)G^bd0zPNM2XwP;&0rO{v)Saqm(Dj#d5MOo-es3<_(U;UUR)i z6YpQo`D#CTj+jC5H6D#?hknNe+TGU2SeI{P?NBnX;*8>nFCe_sWEkH7sT@)Mm0V2#re<$d2z#QOXntKrHRt>M9b4L1dB*#F;W z!+UuRrzN_MID!9jPDms&77dMeAG|LSi}&az%=v$&vahA7Y`ilT|5-08`$yNZzmwfZ zTbp-(4jc<)`Fd+=M?)uSKs1GafcuCxm%<$HhPVn=c=_PY`GT|>ZoizkY%jPANnocAMHQ8>` zE2J|?LfSFPMvA6E_g~H{RRT_OHl!FI8LA@wEJ-0gCeZZGg$R z4Xk3+s5@{&JeuE+qIB?H2`~LfkJU8?qF;{smEeJ*r#2#V;q+kq7ggrLfJbXnRZi}= zb-lZA?bza&m+`euySgcn<_o6#@(gxZK%U|LJ;j%2x@(*I$7eD;mg23ei9bIx9`|5< zPfQwaW|em0pGfl^eOn>pQLBwJAXk3-#A~5eUY0I>3V$6@X}dq z5x)E7XR$V<{qnQec}V-^XR(Ws_RG(5*9rH_&thvJR~ug!{YI6*p0A7kU?82rUI?T! z*@uC20?)1Z85wws%i)1^wwCU!rMqb994(!zrMt3`0sY;ybayS?LreG6(g$eiURt_0 z<13k{Edz_u2h#^>={{Pzua-WTl?U`4!e$22oizEOS~^cl_tVn-we(?ZZb1J4O`c>; z0r@~JeYln$q@|D0(u3Lg0ewem=^c++Z2&FzC4i{|LUv{}W_>mCTF z@5}su%KWY@?~yl*@A3awnLk11&y)E}Wd1Ulf2+*jEc5S|`9GEUFUkB@W&UR} zzf*}QH;3<0?r^?`>^PY}QRdH;`Ry|QT$z8Z%>RMR-zf8+mHDs9{MTjvUuAw~sVFy_ z?@?|)zDKzuWqyIopDOdKW&T{5&mU08I7+_Hp^sQMJ>zJZ?km$nWg7k8Nv%tJEzdmpGEFxvHMx#ewMnQqufs{=H(tNj&{W1jyT>C z3LK%q5h@&^!x2gxp(T|cc;!X98N2(=iP1_LoS_G0ff+dwMa;m7RGV>sbMM%QZj#Ck zG{();D(dD%G)*Z8MLuqu<@-g_LBuZj^Zhqv?Ek(kAbnN@H(ulZl7{1D&~ht~SRA2mna1&Vvqsf#t>l!7zL*c4i?Lka z?mz}FS8dmhmUB;)A@@4>{1`dM>wrrgE9a6Oa95AB)A#WNIXCP;-{?tl4ybYWAWhrb zc06MPG=?X2?gnt&2KuIR#pR5BUx$#^xmPT?WmCklx=LN&ktf)3JHfrBD?|D*{HJz# z^hC_X38(H|>D*pRZd`?(zLl2TvuU{PT03&5Vopukp}y+eVc=*#O2?gN$-QjJ6`T|t zH`0}REjXL{{TUqZ`}(#M8T9;KbaM2&bok$RDE9%lq^=BUo$E5qjyu|tJHe7$n1L<<$47CO6RrzbzD04*5-vwzkzDpHzua5{S5CODgqy0h_i}LMa3J0eKDXf;uisf3 z_rmGIKR9yG7|^XZYpv^TM|%t_R@|4!RrXnzeQ$2{+Kd zjQ{`u literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib.lib b/gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib.lib new file mode 100644 index 0000000000000000000000000000000000000000..62fb82036e184869d2ec9cad6588082d84765bf4 GIT binary patch literal 698 zcma)4%}T>S5T4yuEm6diJqfAwpdOkuX`3FTP{BZ;=%x20+a`1&T1nF4%_1K45qt%o zL3{|G$Jw;2TNLWR?0oZ+nQw;F&ck#x>1l?cuZgL6ORT=S-tNePKpUrg9;FFq{%9J< z4Fp2@Z9FxUTof|Co-@=T*skd~wrM%0jd69FENj}W)zCou00N)AH+~0F7UZ>nWf?$w zhUzN5ga-&JsQpuXh8~b(v|Ifwi*8sFrBJDAJ9~6N=_932l)h7Xhy`^vuFA_Ha3H2_e{bDFj|{ryqGa!hBY literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib_coff.lib b/gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib_coff.lib new file mode 100644 index 0000000000000000000000000000000000000000..861e1b2354ecd85666e1aa5d5fdeb02b1d4ba299 GIT binary patch literal 375766 zcmeEv31A$>m3H-vW;D7zk}<|1W-tZ}2CTy;5Ukr4NY;2H%MJm?V`(faNE$JcY-0=v zW5D4w<_Lk1HDGLyO|pR;n+pQOz><)JB;?v9A<3U*caz->o8(V+m;C7eULD=9r$@Gv zKa<@*yJf5Ut5>h9URS-UuJg^Q7beoZn=UF|5OKR|=2e(qBay{5OO`5@^~FMnp9wK@ zqx7VZt;@{sq>YsJyG?DXf?Y{}@{XX?~`!m9# zzrQ%*{C(;p!aCl+fBmJfj`HU_xmry5*Yd3J9naq_dxS5KfBre^#qagEexdLm>+h~} zgrEK%`{wWe_lv(4{^R&7So&dc)W75oQSjgFFOZxo0wdqd{);y>H^oPjV;!l!q%fXn zw6QxqFw#CSG%z-5Q`=UxgF0mUJ2!5`gNoGDuqvKTCi*&(qoav_#6*PAGb%>Sl3u$Y#h-Os|=ay;dou`hJi5?=UC&wST`ga?pKt)fziZ~!rFnc zO>NC8xv_L&cywbjo%O7pKk=Hy>=hmI_(&h3Zf%gE)XG<>f%7K1LnX$(bLnEL>*PzgnX?lg0q4B}Q*g$GnDP40zQ+#ZE zILY;?xv8roK0Z8{>b>&P)NryEUJ=hC);Preg}iFC3_Dj2vmxovo4d@Pz8OhCD=7IB$-ab9l}WlQ49WNSJ#)E-6QDbh%4OETS@ z+A=KSE23?kBxeHzN%bq)4b5&Nq63U`^>|`%VBD1t0GTkJL z!$gG`jQEDsJdj2MVe6kHLrq-KGkFj+#S_s)Uv}J6MS>S)+-#b>O zVupK>sgfmUdr2X>(X;bO@lz2v`Jm#>iV`nlKV<3&MVK6>M$`_{>C1A5y5x+?of@7n z4SRe5#n7J^>>Np^Wm&CE4ELd6IEzY;Qz*I~luIhzO``B1{kELMwarO*cxWI;T7Ail ziSfZPCnQRrykV5x&=4d;v>=QRr<45yqiEUe=u|-4@aR}#nA%!mW9>Vs_UiHExDG)J zR}=3}QA<}FUy&SZ9N&lr-+9WFniOAsD_IomgV~*8^eH5Br5GKzQ|#z%?20=2)xEVf zoft}XT|L|@;wnsjj_`4>S&WZYb7Cy9DmC0l3Mjv-Zl1c@sd;*hg2cROs1lBCwOcq9 ztuD*%Y`Ps)SG27oLFJ&Tpn3|`C$^OY?HbsI{I-eR9->Ot6Fq8ta$s}PewpmIwUh7O z+5ue|=r!%KO3DsaQnaShLkYCwosQ=PYSIy?7{M_sZL$QHmIM{=lXV}Bg2Q_ldtE7UmaPafn~VNii? z>U}A(Y+5vpo|$aTZBBaaCjH6M5BH*~%eE06C7X{bVV8Oq-&M`2IvrV$BkdJk=m&tT zKQdkP&2}VfpE?xpv}U+Bl}@*$)2Vd!TgmnqV(7lGjuBLR#j>90YHIT~(?o=HYw1%v zn83RcA$LEULS%BNTfG0RqcE>bUhn6HsIo7K>YQ#!rxW-@5slizEE2?NOpK#h?P_i{ zT@KZeNT6|dk*P+j?j*?3DZ~Ta)TG*lXp2x*#LIP3lX8d+#u4-i(5^w>sG}=;R|%~! z6p!c2M?{mLY%g@|crQDTz@lGMb^Vz@vWDqLrYHzJt)=HLq~-JqdG%=1*dWpygsygu z_NuOb!}!){dpoj%hpy{xa7ca0L0L+MVGNJxCc*WP9i<%^v?K@bnEPQcwWqdpjUhGtXqluJ1qeXOuMYp6|WIxXpQ#8?gC8;)sk0x=RNLP}&NJyDt z*F)g8RqjNk7OY^B)0-H7b|%QkC|g?x$44<(RQZI=9EN_oB%}8>u^5r;@?=@j(ZF7d zCCBqkNe{)c-^IjeDmCOFsg&2`1Y%QP93`du86z8*_zN2*M+xmTW69C+A=0|8#?I~) zUFZSgOQ$ncQb__H7nH48O>l5+qnANpwoHq#S&Qxm#se8`9}YG{T)8X!9&CM)a!ydQe(*)qGC z@iKVhURE(=M;-}oNZPfFs{*S9JfVioi2?LhdXj0}bl1rQVA?1Lm1YjI$@+7LXjETB#(?DHd;yVk#*0K>?|G>W@3$8jYL+aitFB#A zU5iBpzOJBfB(h}TLVI=Lc~K@_x#(j9C!Zw5*_iJaV#0b@-v3cv)rCTC_A!En({K;r z@4T_(*0HSMkLTczXrA->P-4fyUvKy~jE-ip=k!i6>NbX-E)jy{8L3i4EPhC5U{uai68Ss({M$nMQ|2`HR2L1){pQwl?YdQbhjQ``n zVZ6{x&2Qdq8XlzbA~&pV@*1;*cn(b8)BI&RjGi<6H#7dz!CzI$2s!xgWx-2y_-Hb{U~FJPIysUWUC>)wU0uBe6K&eRv36QJaU^~xlCc}k(TcXUBaNrShJba!;s)mAr=*pU@=k){Pr^XEsJ&?xpN zha+o-2ew8w*Vdl5_`I6)+Pk|DFmg3!tv8KD=JlQxsadvc@wv6tHA^Gi$*qae2+gmg z@lhNeBaDI4ND8w?$v$C);_)OpO{p!yvf?%-YTv-9rb+Zc6s}cBD;cqtuFm!~-EEz# z;x)C6ZQVk6$cu?wFA5}kax^tKPNPlX+ki;QDW>2P6x~1Dadvbzx5T^JR;_4niMOn3 zZfVw$N_ul!YimoaWmR_@dfpQ%RyDaQzlOd~Q>+wM&<9Pn-bWWH64qGatJZWhw!~_5 zd=917!&4`GSx;f5O{Ip%)E7bcN)dZGB@s;FQnooY&?f>LQmH{<`2wSu@=f+dFtL#q zRxmI=>>`8$TPP$xMq%i1rvU;Elcp2~2GFzR0n%Ss5RZ=o)hx#IzSod;f#dxtyn(?K zmTPkVDGF>~DSYK8;}Sd@7bju$ph-YIxsaZu1eCXh9_^t=lk_M(5s{A- zuoqy|!obGC6lQOH1%bZQI88MI$#Cs0D5$WaD9#FNb;C+rV^P9gQNn#)QCySjx^dk| zm;SEqYTPz;b=TlF5N*Qs{V{nPY$e{IX1We{t?R%og{klg-|k3fkG!86ZCKHQ$9=o! zG>|$GTGi6f-rl*E;Aw5Ex+UM-w$>OCPH$_G_cMCP*B$@>Mdh4Q{Uwn*NaVvFT{MQn+@ zUmRQsi}!Gf2q|Y<9NRv zTd6CyC$nNJb;VYQy31pmW-{8W1=C&+%cimwJo+A6^g$PvD7gqH9;jropQT`+`)M*r1Px&mQr`lQbIE|GO|JUMW`1Ncf9BfZ^OLb z$jSk^sYKA19+RvN0SsHo-=4~1Fa(r}w;^*97;~prYIXD27i1?_YOUv~+2JO&@R_oB z#nVq6n7#5y>z#8pTW9%u_W3in9tiF$Y%a>&_`+kE^ABTiaA@W`lh)mbzkKK`FU+Q} z)}qX<`-4Xw15Jlg*pb<@Ha~M)5b_Utb$NQIv9r3#)Yyz2@7k;|>KB9oJok5`KjuF*Re0CO8Fdz@ANS7y^(jWJ0QD(<38F>Yj(LK}GKXU6MH;%lX{=t!;*nMR7Be%W~-1>d7d-Llr%vO}=K!1+%>t>TjsnN`<6C>pA+yT#gAb^S{X?r<6&+u_%!a7xEG`gGahjaAovz~@_Ab=}Ji z#L3g4-igiEsp46MLi3AJgjklSDZ>?a=`4}gW+4BFTuPhMw>6kA(-B%tC z`jC5;umk_rLg2PX9}ATEN~Ucc@o&FqIsO8H)qx^ksLB_b=D#-OE1dR;U{nfinN#-l!ymT%p=rUYl6Qqp58YOe@PZk_ zAF3*8L%$?27qFz{B2a^82%;3u1Lb7+L+1fpSh~Da#!`gVbecaDwkj=2xv@U9vp#TB zeaX%Bp?GJFQZ z^BJyYIL2^-;f)Mm$?(Mi%wWkpv7&@OgLi|AUIJ`nc%RJ^7IB7`B6AH7WwgP=4ByP~ zM;QJB!#@C4GK9r%82%l@G?1F1S(J8 zLMux64K3Rbf$8%?wc@unPguOo@EaHh8QFfr@Cj&541F=foeXbecqhaA82&V{k}WJ~ z$ffc&j+t=tE^*n}H1f{_J%T^D=sCC;`Ky6VJS%}sSrCrk4-Ru34u2HbMAT1lW}OZeUXv2uJV-7rhr3!~X!V(NzjG?aZ~n=3NNCn*#Cd1TIGY2Z4?J zgwMwxT=ZdFjLfeA8<`1jz#m-nySNxR7o(hwoP*3Arqh6poPpjzZ)w zx=WzcfICk92<&~LgRtqjVXf@8#bhqn{6L!b&P$A8 z052NCc9twL+RrU5% z5uA-1wUF74Y71#Nucd}(eGdMJ4&*iVX#DktpVeN&pX)xsh-g@BN4-muXD2leaHgIa z`H4o@xKjaoHLs!3-S8jx8lZm?sj7$y@-{Q0i@!HtW60kBj3q$7T*LC|H7uWN$tvi} zUc>S^Ygj(BhUGAsH7p-ijZA|0mShf;$Cm2{|Lb!IFqe zJ^p@uhVeP~2nA?2-vHbn!{6AMjG!UsZ)3sLz@PJe$_3|7Wbw~JN3y3`5w-X({w<83 z`rq5YpY3@353#`2z)u~6{|k)&65wu9iY&+D|2_*_3H-BT@c)MKQ}1>g&tM(K<1aIr zfH3MY|I;z}=Q4ikcV3FihNI+X1LHpd{7->@_$d5q8UGCMzfOr{IWGSe#!uxHqAq`y z{c@eL{Q${M+>V)@!-=PNHwI_}?x-ySf1UD-fC*8u;I7aFpdZ|GzW-2f%kR>h6oW64BU;oZ&z2UWAW^TDlhz$kRkIHOIYD zyg#d*MCG)(M{jyp+v2gK$mREUP|jL+gU>3WgTozNE8?wm^fTVo4Nc0TwO|8?C4!Q1 zv|nz^?7n&gJ4q;^FvSw0dC-Cg!7xpIhG;I(s)2Gk@pm>}9PfT_v?bn+p{|_*qhdc( zM`w3Su18|)gwOj(Y+d&{^N`<`4=19PbkCDCBtxhbmua$dRj4~xh3?K(VRq-L(CJ(i zn$DHOWI9)cs&f^T8-3J%pnXUx2(t1WhR=CSb-lpt>=$~O*d6cp;Vp>#4A=0#;}V)A zMBY#lN~|DKj%&CIm(WSL6zWc#lY;KV=_J&SA)4-$Nht4y@D@Z!0m7Hz652qByrDr{ z3L;mLe>3^F<06wV-9dLcnp#+Bx`TywcThcLcL$y4)PAf`_$w6u>$p_Py+@UD?@^`P zdsHd+9#zV{N0oB#Q6=p?s#JTAD%IYjO1bx_Qtdsev}o^9rQCZ|srDXK%DqRGdhZeL zdhZdC-g^XO_8tMMy+;6Y?-A~D?-B0UdxWdK_Xt?-J*rfDk1F-vqe@HeJ*w1uk1EyP zqe{K^sM3;qk1F-vqe`{+s8a7es#JTAD)ru@O11Z>Qtv&gRC|vq_1+_-FZUkdF83bc zF83bcF83bcF83bcF83bcF83bcF83bcPJ54VlY5UU?Y&2!u)RlR2QU{z)twzYrFN3O zu9mbkzyk8xI9KOu1gYBoE@uM6mZlc673u2Gc6PG^W;q+5q0Jtk+?Zrtx$dty$A&(p8k6jb>gq z?Ab;^uYA+I?*nctlKq-Ble%-S>#F~P)-%x(oyzea{e`wdY+wC-w-o<;+4 z1yR8fD7)p0;M>VPf6a?`~u(T(2`=D{IioH$=DN9(v z3hPoCz0w2)p&Uv^+P)Jl8aq9<;MadZs@rHMOJw>rqNmZCgsDp@Jr7jEXuT zdDYD?ab0+&6uuwzs;+hQs=T21=@+cq!X8d#!;k+(gQWfna9ZcfxfMR#%XZ^ zxfCs$L(xdzy`>%-C5s+XaETBb9ksIy+<2zbN+kA@`>H%8tBq$-`O;*ar+jsIUQ4;q zm)|DnVxP4&XA`tJZ>8M*M=WJq!)CiR?6^yxCg)K4G~UXp*V;N9l|D`FdP`qfkIQT6 z$MRhI_x%w|pC&SnqmJjL^lxydecYvgu`2!GiQdw8EaZ^}&|-jB100^bYQe*K)`Bws zR0GbuwE@&Q@P1|SP5vXc4awvE0z{P-^r1Iu+JKyf8A%anRl-q(oNRg3g%kYw{T?*? zr|Ru{bRkz?-}`-@PP@Nw-l!J)!YFr{p)<-)xlCozB&8hH^U%EJV|$+Sarg1(BkL#8 zOf+jlv-?9=c*a)V{HECwW%NmAs>Yz28Yjp4#)DC_r2sZ8Z`Os+E3Jb5kI5Bh_7jsF?HwK->xY0OhY%=k=>ZfLPa4SLj?iR?3D zJV#3dROWyfaixKpsmq+D3hO*Yzg{Kh8guo?@s*7KX?Jq=c&y(^PIbg(YIJCtDc<@V zDx{{}cm*w%8bM3U=t0fKjxN#&Y2k`lq$Pc*Cl*=1vqSS*QZMGYj{m|x#q1jUdGWIY&=@#&W2TwZ`%0ny0uIg}#mME7GVX2*-#-#Y}WzHE5R z{L`0Hv5AttQ&h>yi7jJj7(sGpu_{(qP+rUQw|Oqp%7Xu=@1M6)PM0e=qU3WCm5VSe zL1swZ2BO`$nUf{2xjHLv+XvNL!lHcTs(+3vSG~r%DQBHNo6cD;TV8YbJ$cUEctNgq z2(7zn4CI80f@mPJz9YJOCVcN??tFYt>k9=5@!-TmzLfB7S$*l`zCFHJ!TO2K5zC*N z*etBQH|`HwJ&%hQI)62k9oG1z#yyj}_uklef5ZI7ARSI^oUOPUgD=d^=H@Z&c!v(K zK7HuvM+@HRKGOXBnq8}Ij_zo@ZvX6tYh$-y3!b$B59R z=1+)MgQ;gXi^>I)qCRuyzCBiKW}O^ z`pUssVxl5N+@KylICJupl|7G_WgaCYL!UkT<;OekOG z#zQm3v&})GiifP-hrV+7%j+fsi37pREHUlC?1nvl$XU3)aZknW%w;&n`;4d?G9(tuh+%lP2kU9Sle1~5t6t_)g&cyL!_$qvle_;9KrIYZ< zW5zF@N=IS~-r2Y7;#)Fz-uQYFM~M$)_U#hBm5-hBn-hBui2ZvGU-s-|C|0m>|DI8zE_ru%&vWVUYN{WzW=h!`E>Ah zC$u1QD{>oewSP8JMnPBtIXnwHnxF$OWEADz&diN(5A6?%J4&s4ckNvL!fa^IA-wsc zE9JA7PEK2$xmjt*wxzLfne0Fvw zvwQVRvtR0*9D3;xT`8UW%f&+#yPrUbOrH#k{j)QNi=lhg_jc~td+Cc8W)53Fe6-@< zH$J|nAmP6Y`@d7-wah`%g`J3r%7*kC5<ss4acJ$%@D@X)LR@nYshXc2aK zJZM@u-#hzmYd`Y%j?B%gZf$&?bYH|WyJjXbhpHw|7nz%%4<1}qGW6VhYO$V2$*MN% zOS218U+j6#dj7FPXraE8+40UZJNEB!4zt(4`rIsQ`WJido>l+q-FuerK0Wrk_0OS= zvwW1obF=CN)nL@HBUC4NUCJC3pH}S)Y87hVUbHDxs}7(wv0gjn8R8c;lH;}mvL(*k z_`z4i#DA>c_sXPrE|V#@Uf+v)ST24!`TM5Pd?a(L1p@?PVt++Aku8~$Cxp0Pka_si zJ;#46pPFRj>H+j|`Rl5#Z;)q}P1s{j*ezBA9l39)+J2kAp=z6Nch&axs%yW3!~E(5 zzB$7uAEj+46lWtH^&e74@Ohdh98nHanzV_tmvzOsM*AQ{1X+|yQ2P_=_zs=`s zueuHbT>o+d#b+E%NNc`Zh)>JxYj#Pic08D8XbB_NGmwwHp*e%7o}y(f`|IM?dm**hpNa

    _hR*a&I}t&p;XvRsfuc`>6r3I?N(2Ib z% zZ4VUPjtI8nWzI(gg;h%eMav{Xfv1B${Nfk0Z}E`;B6|)A7r7Fi?h97_?WZpYl-wBz z3`k)%7Wk0Hzii(Xm~m^M>ZgICI|5aBzd+FiO98G%mp)MBf55*h5ctQSFXT$&TLnnt zXP%dvE@OP@Iy=TsQ;fb6M05e6c%W#b6ZID@6?L&I>Rm^R`o~#Oqugc0=AI?|<2h4! z+7IC$m_qp9IVt4Ij$3t%?(Fy~m34|@JOL%M6=e;3B2cnBWPbd5dps~Bfvmo6G2N>^ z&2k!E=&8)WQZej4Fr&jkwm zQK7az87TA>&O$j}5ID&{yf{#}lJ4>BIDZRyj~3@ERHt?aDxRkLIx|r5Bk0+tUFxl; zvUd`Y) zsFWR*%{GlvuGnn*EEO(ODbv(xy09^oQt6mVsdAZ0na)h5hN!Eignf5q?%48O@R z8D}%`yv;Bjbush+!^I3&Fnj{Tvlu>w;WmcXF?*vPQk<_U{?86F8bJUbYE2w24#7LPDY8`xNpkn`+3hA(8eli^JaPcVEh z!}}S29$39sSo}4^v!($A8h~dvM{56Ju#4y>EF)~z?IGC(et<+^l+o?C`_a%IV)}_-JKiR-iJYmty z@Y&clYvNzda2Lb<437buc(yT2+izR741^EqJih_h#Q$NNCoJ|dd{ddj^C5;m#_;nD ze~;l`FK5jp54~zKY>p3_r^7=NbM6!~ekWB*QbXY1YUy7g*&_SkPwL zZk<-=J0GoF|#pVf%(-;oHfR5ognc*6SS2Dbw;W379V)y}uKg#eChQH77 zzcBne;FuIYENHV~RAMVi*u0k?*vR~DnMfz*vLH3<_U{)7@mpA2E%g>!^;_t zF?q#B3iKoNn35(SX_b{IGvAM|buVQ#3!`Cr< zAH#$S{;TeZHO!uS{3Jg~vX@JwtI zFmay4@N$M@3||4P(t@4?U#8O~++*~d@$ayC!s2Fzha*n9I~cx?;e!l+5?G}b7M}yY zLXfkfgxhqwp9eO!JYn%8hF>|=N%swgf64Iw0XEN`BTSzvE^Y0pdJz}+{EFN0 zhn*SH7MszTd7wZg$a!q-new80t7NgFgqKPz@QVVD{M42xp0L;ston5r7XU}_2N#{d z#k}uMVAJ>eF!06rqx>O!vcw{~7k9(I4_NVp#b7C)Cui;|&zXxpE;eVq*{E<9_7fLLmzr)?|W180f9-RZMzPVPEu;H%;Hv9{1 zp0Kpy)Ggz*qU%AA==l2>|0ZC?6UO3-Y2U0UVUs^Q8UHSuCoDb;yiUhYc&UzmFXN{% zwc-hj*MKk8{DdQ#|9ikj{?~1uu=q9bWtyMxOwIpqjQ@8wPgu|odl>yEY~m-I7AF4b zHV@ix;PpCw!Y2M|#=p?!!B_xzgXSk}@@FNmiND?ELH_}+Kwf>(AK*?pO=V5^bcsdu zN4P6G`cZfnqyL1j*E|869u_wM8=WV-O!H6~89o0Tu+dw>=V+d%ZF*R|32f>D;SSC7 zk2XCl>hLZ`p9%MAp2apjEItTqbeQn_G|z)JJuH3+Z1k4!2F*ir8m14~?KgU8MF}gq zh_1EiSg8g!{RhHv9Z$xlheZGxuJp}{5G9XC9L6+JBFGI|wZJcNy2%>y=iML2{%xTr%9%lSW} zSJenKJcLcVx)j*x6=B2U(8Ho0bfZ^<4Ua<)OSz0*tz;s=y&`OQ96H)+ z(AVRSuWtS=_^MqLYUSujCuXvRN_>n0p{e)bSZl4RRW@-M z1wvEmi~^zOxG4~tQfE9!`a(AaLX$Q#9td-#n*yOzE=nz;9d}b8^9)ePLa5GX$c*6@ zr)ZfO4`hzGc_1^rd$AJ_WS#~}i9>> zO@YjmW94?t3nBAqZVF_c@1{UzB*&kE%t($?APkjGg%dMmrXGMpS%gT=byE-tgycN% zLI6&I%n?wg*)cDI%xAbMcmxy8sF_B`7C~lwT9A)61u_?dQsqz}Gx1D!D3F<2fD>%W zV#qw*O@YiO+7xax&8sy@TI6tZ^{Y;kJk)}C-@QST!jk8NoIJ*! z9@S^RH3L_#GdA?95Hw{T>a<7~r;5ke$|Fhq)=A!kKr#02NQ37Yop@v){TcX4}D=3 zkGHOVO7l=VHkHg@*F4nvDIU@Qw|hhL(ARS+dH#>)acp^e->ZxoFgR+BRXkKT+-|Ps zp?-_vsdqELw@mZU_e=43>vL4|(6?Lhc-xLEHIE?u5f8ve_GdQ@)eTi|wJm_>I^`rA z?(>adqHG%_?oh{Uk%umATDhpheL2sVX7T9LBys0J@)Qi}%=#38HH%^O#@IQhw;WA6 zwk+5){0vxbvOed>0+|&vM$LKB#T)KDufcd+XOFV!ZNqL;J%5;)^{kVQ>ZmHu99i%= z4gWYH=H!%C5<6$LodKgej&?}OlqXgUf3~jir`(5(WC$w<9m5nFX5xoDQY)pOmAo!u zNzOjiXUA;xQfZcl?5L~T>f4m2ot62R-oZp}+s@UwZ96ZjUV;#EWRbpDTBLslpIOze z8QadL??H{r+4%cSj;|1Xzp0NS)eLv;BD%eE(X@y6*-UsY{(8gD`fr9m*L{K!(fzdD zKcaI)@&AT8C2;2JW#lIsVdLm)Qbe7cEElPF2p@2uAaVov=TK(_j{2D7xGh}Xl2f1U z2JpwS`9Y`rB-gBN^7=VkPu8+CvXt5I$5=oF_&ea=q2s5%208P-$8QVw?~rrqBapXW z)h6}rmE!$b*}^^UU)BBwDwb8))ZP&9Zs@usUW1{9?V(?&wmtOY)V2q|OYL|Ti2}#7 zSOgr;5)pJfOKG}6#(*QP=EtlzAo)^~AxN{h))N@l=rm((D^|3`;$5As-D?|SEk-U) z#&2yj)MT*|t=34%`09+XjJD9o%xEn=-9~ta+E`=WfzfJ3p?WVys}ms)ZJ{Xg&?uGS zY-&@DDDlv0MX85YC(1mug`(U;qf{!gsm(QFnuk^^!X8?ksPxbliYgC{Qkm|euEUR6 z*NAs}XtiRthgK&}@z55Eh=;aFoa&;rMAvrIARRH+L#`$A=^k<&k9{Yh2{6=2oS3aSvHWvff2r6ICf*>7sT;+q%~^ zAg{zwHa({3!`bxib&bTI%BIH@eI%RSy{?J)uga#!6g};tH?=p)61qN{D&J@#n<{hV zhHR=Vo*lYrPY?9>!_KMiEo#@PH4i?6ONq2W9?&+(18y7SfovP(0mlY;z}O&nn2Zhb z04y!w2VR^2=`Rdu+u#me+XgRC=Es#W@C(pyDIoLX%G(aFe9&0@c0X+_eg}-j?|^Ob zTRml4{4SGbz00Io?=orDyG)w(E|X@x%cNQFGBWF3rp$VmDYM>X(yVuxGV5I?&3czf zv)*OOtaq6->s_YJdgHFmdIM>*-ay8zH=r`>4Is^W<1Wp5;|{alxY}mDfu&jRGG*4g zOq=yCQ)a!(v{~;mW!Ae)oAoYJX1&X_S?@As*1Jrb^)6Fpz00&&?=of9yG)z)E>mW` z%d}Za+6{O$PF(isf%=OU5s`pSo-`-P@HMB%6+xqdvtQZ!zo| zZ5r4(){_|2LB?19F3NoT&hx}U{0_B$H-6dLf9d3bJ$@Wq7kAx!wLc~9+I97u&4*gRp8WVi#un|L-cd?Ujj zVfZr)e~aOt04o{P?|~Y5=0OmelZW%{K{NamX!7=2VDl{D*%XLpCveHdPwP%bej2Nr zXU(`BB)Lb!`)u~wJH_IxY}3jBm9e7m*&5Q4T&rPxhK9!fIeFNu483tK9+2&s6}75H zy6JUhb_9xmcxZma(OkoAW^~lb3C-!4c^t#x%$iUR`7N3^@j5e80>uGO1XnXZ0;pX= z-?A@@su^qp~HkRBvh6(Rn->^S$k~LRU$D9e=kb5R@ieGtKytsCW zoCuUNfo1Yn-rBHiGgrR7nF;)r&I`JojlY{!)556E%o5iv!|?GO{1F|<_3UW;^@gA6 zoZ-)PpI}723rg6WqM|;Uh}aUX6q{j(W>EJmue<qqac^v0o%|hP`+;|Lr+U;lD0|37Ue~Xrf-jf`knH*Ild8OT! zw_|29pclDJQapcdWBlI$t~QY}I_Lioqf;HGAK!gM$8RQC4S&N~VCZfW)*Rde4WpyU zAy@}Xi_nS1g{8g;pKk|j#`%2D`h3$-l6q#cAaA|I4S$X^lST1(GBG%q+Jb}KaT^mA zt1Fr&(XCJhD}*6xys0}@jj3r3G3{p{X8S}yl2hZuSX&xZKh0G}j}|_ROQ{@q2KB%* z=pJ|mvj?6*XW$t$15by^3_R&qt}yU)0`$O>|GX8Bt&4#3^Hy}CBB%$Z&U1QT8sG!d z^UZ^5U`j^#{gKOXExQtz!m9|8x9}QV{E-Rr-$ee~aFI!vA*?$cGlUJAA#Bhd!m6k2 zA#AxE!j{V+Y`Gl5mdhb*xg5fl%OPwz4PndG5Vl+mVaw$Zwpp2wSd)u;pq9Tds$& zp2wSd)u;pq9Tds$&#hr$*xXB@Gxjlphg$-egd(eL&P47(&Zye}vQu^MW zO2A;`Snnp;#!>4`1KBB=^4d^U=grXTAhm<59jkhz|LXUtVA8c$+)Ng zeU4pEr!>78K8-pk$QJoqW64CANlP%QUQQ5)*@|rDI<~LievFsm^a3xQ05syIs5$s$p={hk7s8G}{&X8~0|)#oLp@C+;Y>?js9{Pd#xka~oNL+jkgz{v*M=VH?rse@)&C{6CfVp#Rsn zOB-%CQf&9Z%A(JAWH#Lke6PuS(Dzf^e~maZH^SQFo{L{t`B>{Mb2iUUSg{!iU+j|g zb2ex8`ktx3!)M_si>x?4{Cwut`wj=6v3xX*_VDw?&zzAWE-MFDz~(A?rb=>&99#u9 zSLm6{UTG=v*84Ile&c`m`TM@4D6=-t+Dvan<2;&E@e9j$ypwm-5|VweF5LN;n3@9H zPFauF-WaJeg~zgylN2oLc5(xSwI#G;8?N3~yn0JHt0Hd<(<3GkiD0BX~je?)U*q zVA?7I7rhGDq`TYZfdL(c$>5IRxrgDy3_r{8cNzXU!_a*@o|70pm*FOcqrgh$u%N!X zn#HlAgiqA+uVwu2w|T;1nBj}jBQ)|~#&AEdiZhJGWIC=v4nHgboY3(PGyWTFp0K!y z;RNP9P5fIJzJuY%7=9jDrKJq<7))I>H4~!@@tDKgWQfO1od4M735&mD_*u-C8X3OB z@INu^Ll4F9gn?CBVL1t-@1Y^S6rXxq=GnkTX2OQ&RGS_a?*TS)67JXW)Z29G-8iyAJ?*lfxQ(2IQLN?u!w+e=mhJcPY@n7t?grO#TFpuBL7rPaY#>!MJb z-0Y$(g0IJ>@abkWSD4PnCCl+C=0EOIhWR?U6FftE>23WM<*-+%3pEervENcTr%Cp0 zwMM9d;K}~tsK8OpgS8Ow(B!R|u+;&$U9TaUQj!NXw_a16o0-xjeeql0Z~_?mkj9jP z-&%^R(kR9v4r-5c$iXZ35zXTq%%D7SyVtZgXdhhh=JiiCPY5-Z>YLF(O~%i%t0kJ| zmVu2uwJB$b2D3BHAk1F4agA*m)fsp(;uLd0f9Oijl=DS$=*NcE*+a;zq2V!>hl+cL zMn*^33Q^6HC3V%cOR8(9S|3`rtU7yr=sFBoPnUUY)`#@RRMO7I_5Zi^p}UR7;658Q zfYyi3&~gX)(XvNrj-A|*dc$E(xhwxkxGg>gzy4Ur z2Z(>uG5F77?a^NFKM4M9dOb#c0PrC|9#G>%?k07U*HS!tKA6r|JpsG9;ra70-O^Gy?%!+B$71)Cdrm-8^ab4Z864zLia2Ko;mBVQX>As;Mwgk6ccyZS&Jh;mh9^B;$5AJe>2Y0!`gS%Ye z!CkKK;4W8qaHka>+~f*RiM_%D3R~eRJOkb8rjBS=mtNy(9T>!t=1No`S;eVs#bkGG zhI~yM=_V$BTNQNzQER(pMdfk}RRgu$Vp*4sCWb}^lhJf?v^O!B6jaONSv1SKLQ&QZ z4EJGGnek|f<=c79*e1lWDK*%q!X0nOS}&7bVkaB&BumDdvXc#ECChkpvLP$xBqM_z zZ>j2-7tX|2$XlfCcnxw>6*-0Hxy0AyZF8zF@h$&NOZsp2r*m5K2V-;t9)N*VY;en1971mRQSF>ly zt{0ChWJR5aWuW6Nr8!ee6uuk%H(pFJG(@s+sLSmx92u17A~~GzB6)p^>Nu3xO7BNI zw`If1{3w#XWN$i2T{t`3MWKebFFBaFngwegg0_up8S1)vxVJ0atKw#U1YbQqn$$^m zZR*>iG$M8(P+B_l;JK)$m+5s)}dPBkhPi#D8rZ^jeVAEQn9jVrL+YX z9~1heua*TX&TPGB&gM5?`7wS8Zt`J&&q3?Jm*2eqFn%|$An_)C8P1=2b5^~WwYm7! z@^9R~{e)LPa_#+VY29q!uFS2E@7a%Mt*(N^>oea5=j-@wD|+trnUimmPZZGhc$v#0y;^shXcPv&w_=^1@`D-7TWcI9)`JFYg0%wgZpw`HOuBEZUulm&$?zbG_MwYx=#{`qHduuOR#Qz@l<)y9=Shrzsm&7>^h*?q z9}5ZSgqb+&8NQt1F@|qvIK%K~flZv$u~XCER+R7+D0?bjTHG>=J>Rx@!s7c3e;(7~ zMxJjm{40hlG0Sdv7BC!Rc$ndv8Q#zE5r%)nun#>R6aR_8>Rr^Li+Qhkc%cZr72fL{ zT+Dk_0~`L8z@}UX>*;mOGC2HEn+H~YfsMWqj^Gb2+J}pYe-p4N_X%KAj|fNb2N&Im zi{ak|Z1kA|QI+6)(d%(F??QM!k@4&fT#WpOfKB{__4g(EQJWqXF9Mr)BzzYB;G!?% zV)Wq`z~;ROzZ-vW(O=?X-h~K8HdG@!|7pI_$VoVaKRCIlX5^%NHF6R*JPutgsu?*W zjEAt1a~`mfldy@$p{r0OXZE5Rb(h^IeQ4^`q13?#C1#c;X;BU8#VCv5qcj|Al#Ah` zcT<%A++{ZN-GMmFQSOjKLxtri^DUAj`*N{Hl%rGGZ0pxNXbh(0xk>Y&vVw=^z?BYY zvb^1`J!s&;L+c1Dc(BA~W}I^0Zyof66XCF?QVLTovzc>E&JvpU{lBB*ahAu-cUuSG z_RktR%XMBJbDG3C3FR)2#mEgh33YLQMZ&Tw4XIfXj@>QdPgH4$qW zJp%j)-gS|VpV|>}hX43izWxr6>Xk2lzGg*?`u-U%epzJY9tWJFYr5MyVE?G4V@-QQ zcU$MGj?U(mcvp94w4t@TCAO+%U3YU!Q>>+<1=c=bv*{@O-Iun+I-xRCF~!!bYK^tD zkRlaOJk&D8TZYC56JrCZ;SMbC3Ey%^RZ5}->6cUfg!VkN*^ZjU@i9n&8Y#_oC~qgc z$7k;BnjGpo}+mIOx;pmp>d}Sz_LwW|Gdy93+m01h0&%<*zOa6rQiP!cVo! z+%s`@95y(RYiyUfWli&k!d9iVymab)<$pZ$8*;{71YSf2g2ez z4F4^|KVq0pD;a(|L}T!M4DVw&!|=x#z5{~MkO~SGCHy|50T;a!*bMHUuzAAb;|xE7 z95(5Gg5eh!rrq6!=O@4_Ej7tu(w&C{&7{RSz$V>lV8ah+58QXybW2Vo=)q9*CY#O& z&}x^yk%78bCSB9j0!a?^y=j@j_kZqyI9rz>FP!PDQlHarQFj$ZljTeY8yOEC>SCL2 zwZmvSv80K9i@LF1XF9IbclKKmTq#Dk+o-+Hz|k%DUWC)YaowejOWr?vr9Hx%@;mSc z4)Ugq?-)b0;=V+$8J@|J*D=Rvif=nZZ|nl{(jE@_*0tSC^R3VQ63uiVSvwq|1YxnL8od#u2J3O_0zbnQ7tZ` zI{8n;C<}=Im*8E$uH!dKZ{GL#$7p|#NA(yjUpog$eg6!HXa5EECSoHYHYKVN(5Iop ze%nX=IA`Bqj-8A2`DQy8Y5D8;_A6GQnz8+gbKxysgiC;acj5QhujrQ>7u6_?j9CGp$%znXo`=G4<|b}Zd9ffhh%d_4XqW=5tyg3lxk~g z^R-7tMSrQa&1_mC&DUELu{SiG+?Y%!hkKJfsll;Ce^QW2<0O3+HDs-myOi4OheNp@ zzH5qy5qTfWX8PU8xSLek+BJ7>b6byG*|Eybqe7sqCQl#A-2BT|CdK6LiMKMLiOI}+ z=WPBuj!^pkL0EJI-MZkBJ(-&_Pva-dx2S&~coScxE#mL-(b{tRn}`SW{a>uC_~k2N za{oPg?aWqt2`vKpTRoA`TAa`>-fH2!0W7(f%9O!(g zoFO3XzwnnWoae7x^)6o|9Q0vxjrCuB^8}42Z>>j1Qdp}o)M35z(x%h6PsIIm!s&ITL$LkvI9@DG8_NbIK!S0I1X@`pNiYGj)S zI{m?UmdH&!6bSL)e9>!hHO~^(%UjV2oBroDdX(P=yqnvZZZvh1{T6kkRsL`;)AdIo zfQLH&ro-=WHEKwj>$j+b?RBP0O{0dXMvrm*m@|5G*BR5)Dz=FUpV$M4@npKUZ$skJ z)UX*(=J*KyVFSq=5gl^`**iMKhmgk_LDtkPs;-qoNLu9!OM8qDoS}Z@&>2C7Q7Mh1 zVrx|c2}6>1Ga|_~f*i@gAJI?e8bRjbuQ&XEzzA{{8ZG0JIA=%k|4wi6*ro%F{NyEU z+%kY~dl$Q1=k4YjX55K?#SBK!FjDW(S{*3Y^*?(I{(i`zj`J^M{OiEC54yAdboGE~kPQFvkH{0yL{%{g0{QACQ*+QO z1zxO}mxL`@n9Z4(K068N!>`w<1f>tZTf=;dM8NhnSBs$IsS$1k6uORNOhF5^pj|CZ-JP*`gArBx8?(ZjOpfUAW+Slnw-}MNztsq>{VR;z+P~6> zuKjHyq+Uh)FBU~E|0SZ><;QVGm%l@ly8Nrq%&Pq8O7@PW@M9IU92}+>FS-F2g>IvK z_>Pkq(O73U@}s5MS~`aZZGE_pB0U-X8~s#k zdsj<`e8N@(heQ@mjj%(Bkxi*|61@u);4es0ilt}~F2RrC67r*lUy{7K8uqkK6Q4o{ zDQ*Zl1PS;~^RbW`p+oRfPrlO%SV*l2siTk}3#mhgRjN5EQZz9-x+RtFL#kMvhYVp7 zr0B14DTsWP{NE%${Sy2%d0IE5PwR%sG4Mx|RC0ZlyY{Td7a$R;tswmHM=9r8=!!sZZ-xs_Cyv zeOk9toz|_?r*$jUY28YFS{La{d#t$2)4I6J)4I6J)4I6J)4I6J)4I6J)4I6J)4I6R zXb{l$VW+Hgz;pg{P_=w|x~XjwvhuZ*TpygQ42tZ=C=T@$=ej9DuAc|3l%`wnV4#l z1<;=ylj`3(m>AuJkDc!LP*tG5z5I%*+AsxYehcMDo(tuNa%;_~>Pt{B0zWe(`xO<| zdX09wsH@Y-ew>ILPYRlh!c4LDRantc)n}xBM_l778YEd&G|IC?*(S`-xiTGny5q`n z7hire{LMUP_}enWu`7vsvebvAy-S3V;Tqk@sICkweFHXKcm~!Ux7KEJ<~I}lR-SY5 z-PW=7_U1p9-j>e6kl2;&E`5Ydh!bGslLi}Xy zz!0^#T}eG8p!|~?J**<^a#3w<4zB!WUt_+r@4YJfw$b>9Mm}+g&}z#2`8K7B=H)F> z+J`w6nPF*V!N{9swAjJ2EGJ)nGcA$tOxui1tHPIBtp&E+RsYrtM^5$~n7!hz$d3KN z+R6R11F8MN8{Vh}IuI=F+aDCW56%=5>n8vA`UAnb$?21)ZOz;mdiB0w={JgTEr0dl z;C;c&!EoY8u;s4kTQAIRxhwY8YeBkqzx7kxe;o|m)$`U7X}J37r&{h3PKp!9m!khD zDNd6qR_YX|+bPb_DbCp(xNGFCBlE=Lvo?zdkKE(GTXa3yld)hRdspDDvA6IGbJmf^ zGBf7%TsnCep}wx7^?|$AzqS9|Blq-9T6Z5T4+VD@|u}AG+#V(WRHJ$=F9`Z!xc~V z?6>xVcPFRtgZMO3vDad^cn{R)3RfG-@E{yjAbOt0J(y>;9rgPpy?A9wBXB;# zxEzEjy>8t93N5H#d>aURiEsGRtRbuJIg-q0Yq1IO! z&k9WU`N{)tMFfcr@G#STcBvSub^E0&$97- z5liF5Jf-3Pu@B4bRrf-GdxO40mx=MmePz;6_}k)6SpUBLdS9`8nHm18eIYB`;K7ZW z`Lh-=f9*Qt2&|7kWg!Qo|4!sXaE8wp_HVy)kAK`(;ECZ)OC|R?8N*kvJ8E)AH1oen z=DT!q|EiO_>$+nn_q=}bUhl(rZYU|)C%mZW_FZm7Xu2BYM)B}nz0tkGWhG*ovJw$CRw61LD-l(EYXenw)O9#~`n975i=4Sr14Yg(GEH^o zjS2Cq7}b`DGl_up(D&ndn#O&YKR;b#+Er)pj~E_-aE3n4FzpXA^y?Yk$?yjlz81Z3 z!@q;!TNu8b;ky~WpW&Y~{1(GCcv%zwVumkZxSnCMOkwy38NQj}y$l~=_+^H_#_($l zf1lwWGJI*kNq2zZ8yLQeVX}g8x-KI!@ow1;#yI{H=xYmqE7-Fo|kPNtb;TB zN$gNCJY@3R;GZ*Gh^awCpUv=mV3lrI(Db3&K4L`)8yRXD|HU>>Sgc}r5oW$j{GALB zGQ5l7zhL+YV3lrI&`gD|AygmbU_Wz zyMR@?VR0(MG@VgW)}lX980ThW~zsKgRHj41Wt)r3-5y4AT_FNje`0H)(l( z1Z?7e$L0wOANC?C{;((nHax##xCrBKL!SX`_)lh-#^|T&bP3n!bWZ~|&n~xl!lH@c zm5iqv169M{$Z!X+ia#u9Fss^PD@r)5)9MB`+qu#Fn8~%1+BSX~Y35!j@MrOjgQyU#*{3A9`SWEz$awM!bnRqOf zn6jX4Peu<38~(k(MxK2(Pgr~g*wh!ohW`tU|5=+SEM5aP^_{Tc{~oZ3|8<)uEZzcE z=Sw#vmFrY#nLTMFt>2oipK#yIzA}7N!9zRCRNdiRW^Z9Y^3d)= zv!l@AGW*Razx@{NIP*HQ$BgvdZ>_`C>@0J5sl_DcY*F==**eWbnyG%I!pk$Hc}Ncx zkGDK_X&%zdsdygOJfz`M@jS129E(5Rw0@v@%ItW&YM3+VrA_yGMJ|S{^`;ywHLf*}TntBvBgeG=AGqN- zM`q>BCil{=OLliqmej7m?8P;AV2((0yr+65XGtAnt90K`f^U?L9CN31?ZU;?5puLs zxnxVa?}b?ODRh^JB*t2EEmy!-trrkX*u}o4L|z| z82()M2}b-V!|9p$LLmOeIf{6T4m0wT*L*<;Q(t9=?)Z@3xJbQ0_>~g}${+JNcnp5_ zD1Hu8h$F|~@5ze)hq}Yd$gZ8wSFr&4>iows_{|rJ9$SOIa&!yspGQ9DKstZlHM(V^ z@VD^y8SsBo^CNqu<2#uj(KNcvg6+_*pdl}> zmss#h;Qu%kzkEW93TN6}!+-ocnTPQzN)hw7lNr^uSBm-Hb0hQb(Eq~b(T;|AcdTv2 z3RsEi>TK;^+YoD^&8dvs(A?A@HL~9O}tsO zTH45)MXRIDyjiq`w4pbPMyX(1ubbM0pZoC8YH53K7GIqx^UxNGau1DCsmP`_*NABz zTCE6sXmz5}Lt7}SJTyvWx{JE5ZB=)Tc(;dED`tCWb>b8cZJ~&GXp6+DE?NtIQlO@* zv#CMM%}H+*r+etNlK+gH^hR-}hh8W7=jEg~inBcQg_8g5ob*Q6ap2`h@-LG7=j5a} zigP{m#ghNLob*Pqz(Zdm`Kxo%8%2$WzEtwp=A<`@IuCuBQvc0o~BlYSHYW)rb}ktyZ+UXdO+BUD1Y)b)^3* za)rbwWTiKxQ9aX^D?~nXu`8sjxwWIFwH-Aoo|9fH*5{_>O!LKz_|cwi1C|W{n+R0+kieun7&m-<>;bVE9fF01arKhJKor` zqHWcxwpA9N?3J(8hm8_9x}fj@aqRa}rxIWf0E}@T(tR>>AjXlt(7$hu-uLHc6T- znG~6hPDlBNX( zDVHpq=#d?0CU+qGY1v9WtfStqZzKM>f+$<_eJUxhRP8Bs)r12*oO2T*o-e#Ap+pywNQ0 zvSYG&l!7*;hBprMM-%D95Kel?<8j>{CG)`UrGiq67C9f6UL6|loRMEIYBGks!!OI}wp9ig4|cc9C(olVjzlm^BR4x+~qE_%a!?~^Z}tttok@RO35?v)-KZL;H$0k&^Ct%;z7$}z*^l#uy=$wJDmC3aw5GxGiUEvM^q zRucS5*qG@6P=U!JbWu=`pxjRJ7!L~6&QtsAt@GYnk2bjClr_vnK}|CeXO*LqN>(}Q znpS}oJ*OP0`yk7Z=I?k*Cj;_YemCd0{2rdF{E%<5(_|MPCrnv-zMWgC_}ovrD8FX` z^HgQ|a>CTb8*`;8A9PVr!O8E`aN9Q>tAD7-Wjk?l%TWN?|0fNg32d$aG9a%CurI#~ zFh`xv@V2yLdOWCyXL@kx+qqr!092jU7}@Fl#+eAJ(7nd^PDOwgR6ipNMdRtW%SpP0)({XcbrV9sC=dwY zCJ0olTJ1%{rM_tWQ^ml7y=d!bUx87R&_U5%-^8KEfdCqyx?ncnB zOTYj7O|oZx=b7is%z0+coH;YkGgEy<^d(}xj}4{Fz9dWBa|74(&T&n0F@25G=e%Atydr0hO?4$?knT&6f`cu|^`?DS z>LGy;)h3>i$*&$1Qn#>s*V9q&ra1Y~)Vl{`r^LM-@h3k0Z1)}8HpIHNtt;!o&W6|c zI~z_uGAgeyS$h!2xpVeDyyubhzHNwQqv9(7 z-^TK>t&|oxPuYW*e4Ylyi5L99lg4??daci=k9I0wM45ob`Bi8awlZ@t8Fh{^FJFj|Gqu@ z?kaeH=k>k2b{^{WM8~G>H_;-4>1+Ew8-1cr*Fzmu+tPP!zpUd^M2#Wdj>z#{69@XV z{!f&4bwtWR>xc~Ksu3YYp#S~he?Id3!+(5)uK3Ai6vyC|KkaYX{a5~?qqOni4(y4E zT`+&zulqfx74(n_-B{2Hzh5_Uc-{N^ul;aK7s^RMdTV>;G8bl>%TUkE3$NATJd=hX z)#y`r2(7=2_ej^#vqaaO4}UC0WE{;pdg-a96ss!M-Rx9VTpgNTu?~bss=TEY`(Osq zv7W>gwr$lN8?zXmr^{pGdW9AR8^t&`&@P*yf(n!{TL93br%0v#H>|aJYGXxcIxyIx+?dJ1?%kuOZ}|)^NYJ z_WA#k)d|~(9Kq&<**uFA&om`37AM})n!Tm{Ne!wV9x6D}tJ98J2y*m9lVhK{d*tXz zCPz=MbUFrYZ!%Z~xK;~%+AtVHWmXg3a|wf^c=IwY6S%j)vnf6@JXnMTF1mr68?;BkxM3kIi3j~4|Yox_(Y7@G0zx*YXxo;c$L7n2z)27 z&Vy^wD4^D9w3CGIGWoej@PFUqajks*yy~u z77Z662+mFtwspglECc2|4EA`i%dfy8M8Z5L2s}aHIRdu}e3QU;3;ck}WI(>@N_=Z3|(J zeC35LS{_Gu3q08UoBRB&_=YR`N8DjNBQ2VO*J~|Nz%^d zHtmPNe7}TKCZ7Es9gP^A?2{xE#Z@|DoSp?>B)! z<{`}Wgk;J0OPG0ly0%Z@`yDBG2=o0;0OtE8%<=eidB2%w+tjU(A_1l?E6X&k;|lQwSly?xd2XzLHsn5Oa!I@Zyp zyT<;?c;d3%LxzMd4|u4&^%EgEe`QXh*2aw?6-)NLy<~WN%MQA?p!=seE%f5aE)TYR zDgFSSlg*t(Jf3X%j4?b#9#61bNnePpHkQ>dyz1<+zSV{|9jpcfRgH$hhDY@V5VJzm zP+=C;pK{I$(nFM4WF8~_h=vqiPIdGm>m0Eld3PgdevSoE2}7K#n>~V^LvvH(QfcUL zBs+&OW5$hzkprB+@ADaWOmx}uo?_IFu{#}rt#g=0KD{64Syr+of^Z3Hm@-_#oXfU} zS#t4LGQVi2m_L`lQ4pzBWw#3tFU7x(8WlKn&6MN((+OdA)Mh+H4OxauRQiOQeP|K+ z8Svj?9#{R2MVv^JF@Wf_IifiRR$HCHK*!lrqq_s zS(nf@&M9zMA*(=N7u?19T%=P%iA8qf5LGKOhs}!2;oyqQ{yxY}dL81hzan#(S7i2? zctz&0QXdQZ0a~3bu#0mXbzSV@d?HSdZWm|TKSo`smB{Acv}7R;k(C?;ufFW3FO|r` zy!vw3TYXt2?61BYQ;RLf)MCpqwb*h@Ew&s}i!I00V#_gFY&oVETaM|)mSbwM<(OV< zIi?m{j;Y0#V|uaWm|AQ(W)@q9Zx&kyGK(z(@nXw>da-2ywb(Lzwb(NJQ|DMXdW$Us ztHqXMda>o0S!_9`b;e?5vE`UvY&m8YTaM|)mSbkI<(OVBW{~X0c_YuNGT|uNGT|uNGT|uNGT|uNGT|uNGT|uNGT|uNGT|Pm3+XQ;RLf zyv3G55sNJsb)s!i^*L*IW@^f)4YpIc!}B!rU|OQQDUO-=&-Im;sGbLRZKmf~Prw$N zS@X3XPqEpx`KumJoEmtXr8o8N+IqPAy!4H|yD&*u+WGL-!2Zo8N4W&IVY*D!S8jP+AoEG?N z0-uh`!u;n5+$3Ubfr>|MgC-sc@TJ9y$ zwLU%9XoBqbLU{PD!y&`TzV5&FJ6z{IBRQ|1N!>-qrkK${B*yoyL zp#Bc09%#1XJ}0$8j-9}fVhp-@=G0%&Aeisl5KiBRHI2(g*PgS2t@?8}{2%RGEq7c; z`l?#ovf#sfRgD@oc8vO{QeRaOWj+2MC~*BG^H-Ig`O_jf9p3mHHHPb-tX)QkRznW{ zgb9>2?SuF$ng1hvRgL6`$w!r^{LuC)=2ZEde>x$|ZV*6&;bj{6%zxBhB@XSAsUs@L z*LvE`RQyf(TKTi--?62VqrMD6=F1=y{4xl6rXuFcAmo1;g!s$AXW}n|kp4381N4_c zNL!19eYz$TssQfK2SeE?B*gvskk_BrS9!asST?=x2Na!BbaN#dlaT*@cl4`S)h>Q5 zP&1$1{PTdYe8`S{6Hbpr(0v@I)Ew52oY#Co%lVdR@fzpNYinL<_1I>$ELqTMMVptd z`cQiVPM9!el;38Rs5Yw@6B&9em)oqpB8Svwol0`baQqBQaWYFX2YQGD8+xGo<>kh98=Vsf5s*`)q3Bnr$Csb{6wXHDo1vxJ=_oe?_(7Ra{NA& z{QGo}IuqJ|8vQR+fcf8bk@bQs_Sc0WLjTc zdqE1DMW--Zl#7i0z^uYqYnE5HFJktZmX$5@$*#AF;yMl0%Z^e^sp^@tXVha6is>_J zCZ%R45n(pDX68jRdf-o~uuzVRX4TJ3rf5v-l1Zo_g(}wimc`8zu~krY>xw1DEcjcL zpCZ&C&QI;kYISqdYLF|sL7krf88?`VOrLK#xF=vwyBy?Ea6O(ZFqN=8Q|StW`K8xnE~VZ9y0?b@J(h0 zVDi!2W>&~(zR|3ZvEH2`C~&U{y3JL18FR^)dR0AhdJ=1!sEr7<@G=4>dWDt|P|f+{ zD#}sSc$rZ3sJX4Wb@9^1wq{JCsO=GBl#4W)WG^ezld0O7RW+%ZGg8$v>g)6XEY~b# zFc_MgR5xuV%-Bs~XNA-7ZOSllh4YxW#^<aJQ%|8Uk<8xmWma`zYUb?vEE9k*iI|+Pi|at=EVw~L>W+P80aGLuZO(rr%j(Uv1-<&K#j=F5iIcBJhPLj zYE*ZAcX6k>zI7aZSXMJL<8?&BSp{#Ckh9*hcB*o!a%RGN8NXaMg&LMlzVt zXg>y16?2EH7`PS8SrU_0Hp4hQbPpBB4)ixnh9*s)U0YQ@jp{zVFsdfg%V@@=x%H{~ ziCjB!@~FLAt1qrb4aka0Or_{*KPfnsG8XBVQznYPk3;15_;@dM7PK`lo3>=?)wJq? z6~zZf%A+{*SG2Feu3uFY7E)mzg~KLNSb+?iXkq<|mCbEf3}WGu#zl%DGKL}!lAYyv zRWG`V(=JkR2%1A3ATZ#)LTN;)JCG7Ir+r>^dz*TW5nMtq_moefQ199py=f^>QxHb& zIL92PcNIcCnt94~{&}H^^B$8yq*E{@<(_HWuL^eUt+mN{69)1zD5 z;BLN9&r5v^r{#xmD1M5g;P2SrA_@E*>+K3!s6J?QEH+B{=ywTq)x?#nCazpHapkIs zD_2cixoYCdrHLz7Ph7cr;>uMMSFWD8a@E9@t0t~oJ#po#i7VGkT){UJS3qXs3Wz7J z0QJNbfSS01uO_bGW8w-&Z{iAAOtA>SFWD8a?Qk*t0%5pGjZkWi7VGkT)BGU z$~6;LuAaDZ&BT?fC$3yGapmfXE7we1A$>J*1z$~E!B-Pk@YTc>d^K?eUrk)WR})w8 z)x;Hinz(|eCazp>;tCWoaTT8iZ5q|6=A5`ft*41A>O*IR=WF7MzWbZ3{7qcx_&?!K zT+xHzO`<4^NddxdSUWb4m>v}xR~agk|ssd>d(2ZB;+&sEl+Qr4FQI7)I{ zb7A|uWZQha$*j*&sCQNhgWSbStGoa{DYY8_CrY|HDYY-0Z@wti+lWtkO`bJm2)<0M zaa5+>+4+GpQm^#GXlTSgyMxXuQdHVB-FZk&cIv6lLzwE^cRyJuhTh+KZL}+W{pQWI zVc4m^IC%Ko?%fX`+&1YAYgPZ1u_xk~9KGF%J+b-WpFFzZx$C=2x^_SOlWm(jqFq(n zegfVqoZa5Bc}sePy?sGT|tX8 z=U&@sW$r$To36O|#bU)-)iJ%%t~;&q>(BqxE`Mp7qJ7~-+zWWp5A-Ta-`Hu=uvUHj z`6oj+BP_kS;J^RdwO*>S5-(kgU#0cMm)!$jeAzni1;jeFmExjYeEntXIcpWi)`{5c z?VX!FGnA3iAt#grGv2LO?ApIlygpNfTtC-?n za%`sf^~(gg%~J!79&%IrqBE}`dE_Yx)kdoXFvJTH;%I*&9KJ3RDv~Cj7h`<-S&M)#wqwsSoc*n2t@C>u*tu&xp;v(JYg>zu$K%9z zUmGF{^};@9uWSex|HYVnhDv*fqnpCT{|LoOv6WlYUiYeV%`5(|eQhX?fVJyFrDe|g zSN?<@(i~foRN^on{apDg≧rT!5|EoHtsLENFMeUvVA|AtRt|Tl$Kk{juy7=f^fO z1lq5cXug+0ORrrE%BKr)f6kXS0EdcKf+_6mT%waGc7EEM?&I;RLNU7E`+BP_++b?^ z>Q$i_>2eM8`H3tWlBn1}TK7@vUe zOU8o)E<&PAj|;q6;M)X#2qR0(e^}rF5uctA_$vZqk5up4k?4AIJmUoZw!l9S_yK_r z3jAw<{~>T0gv{}e6nK`vWOU0s9Rhz{;70}iyTES>{I0;zq4MG^6gVa@Z8FB`eo5dT z3*03z8R;_rZw2myPhF25V|5%m`CH&tUAL0I17@DrJs#J3Tj1YAFN%5I7PvRQ!kB)R zz}3K*AyajdzSOj8i=8CgOIP;f`M|8k)a3EF)0fpy+o>lA^<2wWxbOo3+$Og-vT)cvN^QWA`*H_e#((u}Dm&3GuVmemKVTd_PV z!O!v}JOMwrWDO21&#AzCUlfSP6AqmxlsTtGxI)pb^@#!*t))C;%h|a?m{&qlQG*%U$jKLZD<${O0 zW!nRkaX9;7fHEFuG$riEd^XPB3Q#8CtN=3bc}RteHl6V)WHd$_&jHD~IC=cbfcmYA!mdSohdtmGpq)=@f{QS~tN)uZal0xYxJ z4BeGw%^%8&Y3zhidb1X#Z>M!vy3o{WJ6zUX`Kl2qd8gy|f1B>g9Fc#rFe2TRgLpZT zqx&Hz8astG)lx$(BdFeHxJ0E-;75rl)CkfGKhsJ62Snf%zz>1{M|f$H<4P}eSI*Z# z>i8s%v?THgC?#_IK+62j(?RM;4JS5G&T^7}sR*S9?+)-UHSv4-0iE#C>#qDKvW8wL zTtU7ROH_4lQfcHXiGPcdVUe2VDKJWg1vK#3JU^jz3L^!XN`?i#l3@WW8Tw4DWLTh; z4E+GDWay+){_@q^(55>6X(vvLzl%foK^zKSjbI7HP{PgG6yMAcMJR893n)l^SZ zP4z@+swb+adZK!&C#t4;qI#+)s-}9PYN{uyr+T7lswZludf=O>9w0N-1H@B3fO@J2 zKuz_)S5rOkG1Y^kH`N2Irh1}!swZludZK!&Cu*j8qI#+)YNmRkda5UCrh1}!swZlu zdZK!&Cu*j8qI#+)YNmRkda5UCrh1URn(BeCrh4G3sUG-hst3NB>VdDOdf=<69{6gi z2R=>pz*AE_QE#dT6fxBk`7ZhflP;W;q^TUEO;W8^hgVN7wV0TE$QhomktcdhHenav z{Kj8zud~hS*7OMIsUF+DOuy_cda}%mA2ZL_UEQP=Z7?0MqS;ax1SqzBdDEJvMOY79 zU#M}RS^ByZ)n6x2=q2!oNT84w1yzbXI)23;pp;Ob-nJr7quu7xn6?BOC&|`DjcqOM zYgB1b*V`|xV0eC|d0C!IYjY2!rPT>gJ*zBgXpDM+I!BRsp%XJgNg?67wK{m(lKIW6 zWw<6#p&Mm|_O{k}&5~o5rsOK#q?cxuwIm})g@GIeLnm6O1TsS+SZAovzA%s-J zLLXzOR-FU)-M_PA^5#h!?Yc-~=S{tzKG?7O{cx*7m|VCA6Aw(^(9QIX)-FMRz@t}M z_AKUp)}tn@{WsI3ROi6Shx&HyeAGJd>1W>f>9)hx$n+!k{72s>u#6_~o!4x8wEOYi zn1tH4jrfNkgY*^cK>qz>y{)21QDIS0QE^eUsHEtGqH~MRE2=JNgIJ+|%SFLwee|GHs&dMvtM?!@(vKxjPm{T;Z9OI?vHD;LuI=(qzfp0Dl*5-hb zqq71m3=Fsy=>gYb9&nBN1Fj`E}O z6V>-Pb%AUBMBs-6J}fY;*}(iHb;ePF%LKks;8uZ)kug0mVkZfc#UWfW3e0g1@p!Oj zyTEb0L78Wez@HTO5`mWpe67HD3Va{1&W~%+8(Mex?Iht-kZ;P{_kejw>K7i5YyC># zA41TawebN=ZICPBGJ{?EXH^FI=p z`KJPNSrAU(2bZ-j7t4nNQ50SOvtf>Rcf9RIgL;P?p}LxAM>Jh~3$IH|6( zeCW%J;}>6PY6yQkuIr*)!y z$~c@22~cPVj%4rikYvsZP$uAvV%I$X-eEDigKWp&@~B)Gh9W6sJN_Qm!(#MBPTWDq zV-9#w5D$$yoE~Jr**rsuDjxb$&vr`<>4S#FHW(g%SS&l=+YAp$UJsoG@Bc8uX%Otn z1vAfInoN3wV5VCh?C9|zSk6BCM;ryq8JG825KR9F!(a;*H7>tGn4KPJEuV4Y#)!3i zV#K>erEXTi6bZP_gYO-#~sl88d2@ueE~o8^#H{*mrW}Fa+#|Z)TI3a)8^( z^*CYNj1$K7IAPq36UOy8Vcd)p#`QR1+>8^(^*CYNj1$K7IAPq36UOy8Vcd)pB7HSZ z2w#m8!dK&j@YOgWd^Ju8UyT#OSL1~6)i@!18YhIO#tGxzI3XxvoUr&y=mzV@(Ch(9 zhEC+@^q9@-^VZ3A8Cy@TT^*MP#;VQ5{ctXV_kCU2{{DAHpZt7;05x zOZ)Qn#&(Pa(zBHk=NJI?q8Jc}5M#j{g$m#kj3A5af0Gek=_Hc9ReTUVSX}^1so|<= zUA2TtMtvu6(fA>GE}3icT{0aXR5B1)4 z^IDCsKmu^y$mf^sICgOfJNxbSHKE9uP`Er}vl!<+OLIK!w6AflU5`CwLWN^OkxafR zDw_XO@H=LTjB(z!XoHxVP?7EY&-zfY?R>)~TtoZPyhXdysN}*lYFc31<+N!=C@_5L zWDTDl?P_XJGyQn%yqFqJHX6y9QrJbM+#gkaI?T0 z1-=!Si0(7kEFgj?=a1{f&P(J4twyiT@BV zkC6V(<8iHL1%42(Gmif`foTUEu)*mOSdBke36l9MaTVV$VN>6-lps0(bHT&qMVR?7 z1LpiUcs#mha$Wr|&^d2}2jd5q`~wc0A5zKV{16_hSgd5kqr28{V9o>KDTap>2Du!G z#Ob1lJh{$;-|;&7J1boV`twALCPx=Y8NY|ernkMq!& zj$_kE50CEnd_4Ar2Nygv`o$w&KF_rVl5`!LMu4*2ErvwnO^!VhM_m?@^Z%F=+8IHQ zv}Wh~KEvaW#%9atpyBChRQEN6(}-=``4gJkuEvOM{j@Wo1-M|vlBSQDZzb8o%n|JO z*K-7lPq2?RqN_W=BAOhTG9*7EM;O^%xU{8J4D2S3G_pHt?5GJ^!I4&J@2y65PesK` zD%tYL?gn}!j5{6vuc-QGII7W93+0pKvFHchJ0*}XXY#2sByJ$QQv#Ld>`d{58B$Jf zqo7_Qp61bg5Pw}$)>S}V5}{J$NhX_Ov0IkHa5 z@9aoLzAX^^i-6xq@YTLA`P&8mQn1WJq}Q4T`($$o^H)(m>!(>Z zB^<6=zPx$yyhRwjE$SOBjD! zZAHWxRtFPj=U7GJ48|PA@^q9Hm8YYv5_vktipkTl_@oKz9FYoUG6kT-}SJD7=Z{`KuqElOxj2x_)KyF% zu>}Yuxd4HL7a%}>Ch1A5u^<(eI+(UZ-@+D3pHeN1;$g5C&_Q2&;q0nfwL})DuLxsi zRZUOQDnNp1yrG#~D84FMTno>azG1UwRZ}A^V5Qf<>W!3oQF4WwD9z{ngsW#_1+(hp zZ12WBLaMs9Y7{5U)X{wR9znBl+SRRC+oE|91dh#wDN#zQ@GVMjJYJ0EMyh61)y|xP z5}Z{vv361o-?Jf4nxUy&fK`xS>q31aAw<%PVk)e~!Bz7t5u>Ud394#GGF7!BzN&VF zRkeL4R@IJZRc${&t7?a(s`h^BwxvSNwp6Iu zmI|6}snD}66?(R%Ld~{R=-HMEHQQ35W?L%sY)gfjZK*J`E%4233y_&@0pi&fKt0<6 zpk`a(tJxO#m~Fw)n{5GBvn>^Rwxz<%wp8fZmI^c5QlV#CD$Hz4g`RDxFtaTcdbXv) z%(hhM*_H}3+ft!tTPn?X+&ranI&+pqaZ(7;r?Od;h zs+YDbv8dXo2w+MD-n5w(HOxc-EVJiP&{@n=#ynq?JPi~n&C$?CRMrq;4p7SMI>a)) zarsqVYU-r-NhDt@_CtKvD`mh)wyBw=-@+INi#*vlUl?rACz>yBKPEepU{_XV!kxM#smZgOIb9CY#$@TIZ9*loD$X z_0(|XS74XsTVQK)2#l0xc-1`hi1Uf=#mVY9kAqap%_qHS$P(?qh6-Q8cm={JYY|45 z=o3>3H`oYdFyvRRpU$^jZ_6cDvMt2D(CLGYx;f!an>p=GQ@Bp5O)Q%n70aOmkN$XP>A7=Ai-_Xbx2JO; z#WJPay1o0B^!5F_?i!&vFX`@#>@L+gNN+;Cn-3o7|IFbZr_+ZXd-U;L13M#CxW>8V z+&PzY?~3ewc+VqSK+_bR!~NGspz);dq~@TGX;%kwI>JU?F6kb;va=&Sv1swmP3iRP z?q1JO-U?fHsR^#B%DwjRkdXLwtKtYixU@HN3r`wP1Uw)!9CH>Cv}fQ zJ<+Ap+2PDd+XwHa+B6s?w70{#g{0`GnZ7B#iSyIznRDmt8c4NaZnx85g+i?bp`Du` zrwB?%Q41P6BX*J~@fHW8apE)P&y+NuRW}$JK8nYtLZxCEs?>9cUOmvw1?mU zA+3ue8QDthHJWrIBic*hOFF$ni9Qd$oY*zC-!Z*M-+8{u> zk4W_Mqg5rdaW2zJ;GDu5GUzf7lAm5o#NU{~pD^@>3_8u05&xnLIt}Cyy$(LvhdLHn z6G21oxMQNBXT}qdWS&~})$r zDc@r!;FjiP2JN7r;h(#^=Zk+x^0*)p8W_0Am+27`3l!L6(|g*thbI_*UM9+RD3#H+?NW zQ>rOOrJAC$AKz42bX{fmGnFORR~Fq+8RqpiOL8-oWHH8$!04^unRB7f?1W2Yd{C`a z`SX(XVk-+MQkIXiXzyEB>r?h(eaZ@7pR%{qr=+J|RZpVSUtk9}&Uu(B@N|Le1b$55X9O<9kUhuK zN8kYhCj>rK;Nb#~6u1m3ZKo=k+eyNoK^ed$%Yiwq(>)&7I#b|Yn3Z9kAp(yVc&fln z0&f)f3&1)Lu0=CFy52#f9{4nqpRI!b>mCnQND%mYg6DQjR&d_-3jA$g9lvYQgvJna z?}V3|w0Iz0*}YFW(s@` z21%J`mcWYzzCqyIfpuE0MFXs77&#DTedN0Y{{fE&`pW|UT=3kF_L=kW6M+u{>-b%Z z#uatX(oPbdXYTPy!T%4B$F<%R7<&kK@xLW-3=J`-n-KU+V4aq0(eT_*bB}~CFzJpH z{7H|;wdw^v7Xwcmf33iu5_pNgYk+lHu0?}Zr<-&MUt`kUDEPnR@wnFQ0f(0vcPWu>pZv?jr=4`eh7~<`FRhRb+;>yV;+&l3Re8|2B`uweAJx_X}Z;{~Ln;TOJRd z9bm49gqiM5T&0i9WmFDYk)mtc2u*iYnR6LY z`7;k;ey1dW=|^QmKJyT!AKR%6R#@AqFwaoXG~HGA!DU4E#5{yG-BpWra~Vw#JcPN7 zDuF3p%1hR1c{gjkA*ilrcCP7NAi1o)w@_Z6^u&@laj*M1XQO z&d>>i6$ht9S5VG;3N74?mzJQ=!rgdPNXjU^{+EB%C}g@{kO!HjyAV9cH1U*psgFXY zsfGy(GELHm`#i`r#Um)lH07tv=Rv0FsqiVIk>^1{3i3>~LGwsk13X5sIKd&qN&5nP z9_8i{HU$Me@KChnbbzC0)3N!>Rgt^{l`=VevVccFF^V7#^#)V@(pEAe(7?sUNB18* z=Vdd1a=oEO6;HyP1--k>Db*OqPMEWx_kcN#!S5;0&lnzbnZZM)lI>V;zZ5||rNz4X z=%Rv0Kb@H|v3@?u+p*E<%i&nZosgDIckt) zvA%t8#j_O0le6O4WUizduC1D~W%MP(Lr;_DNo2+IRm0<3K4sUlhYe56izoZupEo?d zl@%VQ4EMU>p(nSe{Lnj(T<$~~U!GW(?Ap(j_Tm0k818Xn)GYp{-392XfL zY9Vzz!Dr)6gp<|Rs=A9N*Up~B>vZwlUO;Wa%sYh1DrIzyf$MgBZmKolM|kY7_QUSNh0Ji1>F9x0f6P0lF}FQ|tr zeEE2B2lA-ug%{*=AHhEFiZwp||6B^IU6+K2lps?;BOzG61+C2YdGBEgAB10{;iYqSe7{F+|Kz-fRCPoJ`O+QJ#ov^#S*E6@<6gx!jLiG@ae{YLj|xI zMlh7kFhXpG5%SD1^i`f2hJ}q+oT33mrxe{>iQZDkpWAWt{D!Jp)Ia3;1nT4Io;QC_ z^EZKf%BTh(+ny;s6G2B`+VobOdiBUDE0*A`sM~eZe)rgDskXjlbdzYY5=XWv9(ndS z-Dpvp<*GKT^kmDbR$1aU>m+`#L8Ufp@&`P_Qkp6f9G2$bPnf`5ZB{P+O6LCvZPp;P z7VKU@V?*(Wj2-V16Toc{of2k;&m-$%>P%+1M5RxlFF1BodWVj{KZ}{+Qy={k^l_Ep zWcz$lVZl%Nf8+@KuM2+q_I=?9{G&vDdl~$N z_!>B!K1tyc>WDG|55HrM6Xp8=@L#~c$1u{jEjd}fW<3%`e;3EE(MNKIll{zOe9ZQw5W2rHAgl~);fsC;u5F0xJYGX$LW$XxF89Ty< zu_KP2u_LfDb}ZG#j-|%fu~Zv7mKtM6Y=>S|HyT;K*!Y)J)s4aFr8p)3vZ}hV@IHl8 z@-MHd8wW3iQ}P?C>c+!s#3}jns_M>$*Mw8}#@G?QGIoToj2+=CV@LSP*b%-mc7(5t z9pNiuNBCsy2u~S1mU_mHpa^5f=*bwM^IckDba9m?vE+-N1~=S07wQ zKVO;9s6Fhde(RlKNGqQ9bzXGU)T=E;_RbJ=^}Lq$I`nyU2%o^_W4_lAP!o{yPfP5} zRSIfb6opFcIxk8^_0CG{c^su?H;I+V_;1RLzk&7fRc`sD#BP|ccd^lAjj?$z3et*R zgI8R3Y2t$xtBFo-YhJdZc}de6Rr1tN$yM^1ym_q%i}G6$zI-ey0&36d#Tf!tMUzSV zm)Dq$Sv4jzNmbi2iByAHR<_K?LLnJ7t3FrF8mDX4lNgqun$^6d5o?TiBR#4vQ6E#+ zrOeR0)}DLvTYDbtsrKN573(`KT&~6Eo#AQDY7sDuWq4IlcxPoah>GWRI6g*6s#r=S zTddR-*J8~I&Z}G>%dcGj@-L8UohQi*xuPczxfWd%({jc5;It*iWO^1B4PLPv;rb)W zR+XQGpMxo{@_jSE@~zN@HyQ80?Alod89`RX-^V8zi2=Rc#?+dW04^AWHp4jp#>5t`E(o=I* z%Ma+5W!KoAdst;OpuNO3<>+^?^K0h39W%$7b>x;G`d zo;rM9C|$Z`N@!8&!a-f++ZWP;-!+lLx22~!iw^g%w02j87wz1Xc;-<5gtfb}V9}tb z4+1H!yZ3fn-hKGM-VVjv?}6?;Fg-Ke{hsYkYi=Oo*7@xmSaY|3kC5jb-M4HZDcm$! zNu1>^LN?XFyz9Ks?y6sI3op9orUcSQt|)Hgsge|8@F0=mnuDpS58883j&ah*N3O-Z z>2ov}ogP-ASHhR^P{%VDoqA5W=+qwPqW2U(z4@5`hv;oP7WE%&+v;~rOqcxOIN$W= z&t%^+AErOcPJzKqcQ}5_sm|I{=!er#Nf}w_ta~&ZZqGD~8H?-2(si?q&ldz^DD63h zH_0Gp98$U@TzsCg!MP~Y*5@8#nLJ#DSF7Vv95b`>7;#;GsS4M}TwFgOtDsTHarQRJ4LSD%RVpW8~u1j zHDNaT$+?Jmwuw%_h^S{19c)1=cBzc%xvMza=9K!jIc3r|ryi9S10isFhKmqAg5>Ct zBS((_IeMhX(IZ5T9vN~RPLG6ia?XtO-Du9N1;^nA(^&WjgI5VmI-gAcw7_Je!1S91 zF2oHmy^p|^0?!n?Gk!aBr0VA%g#WkH@uU2>c05YI2gV{|b)>dfEav#{KwL3;YFvcMAMXV4aq0(U;{ZCSAf;nsk34_$LEU0H0>kC49)FI|P_@?9caj@Qet29vVE3bB@5P z1>P#~UV+K(hOd1dSm#08Xz(*T6#43>@|L|rD?baB2{bN;7#JlaNs>(X4o zf0^KK0OtCz6nGGR=*lDsbNubV9RF%y&Er}(0`oIMnE5{^_;2xeTx$m~mpftR-wDj| z@Ai0H>wCalUWA$dM}q%=$KzUEz+9gRGyhY-9RF`T9{t8bGY%I@UV|f-1z|H6pWNut zUF$o*EPuii@qk4InblKRuwSImN4_w zcy!mIsRx!PVWSh4r00q2JWWZm3<>u!Y2E12Ve16Uaw9y%@Z9OqgR;V_!>iBbz$`by zMdn(cuI&_9Zd4}BLzv~30A{%nW*(oepO--hqxv}%N9G}{>Do?#*GF=FYZ_6+W(Z+)mWSWM#1rIWf*QB&KK&GkA2^$1th9o8^$TVJfh@JC8 zwgcrJMQRXHXXx1KV^KL|JCZXwl96L`A6t>U!z_bH){afG%XZ5QsTjUvbKgA3N3Ae9 zlB{EMzg>~M!)}8}j*d;T%XWtiiAuVs{Jd^>D7TJHC7113y9O^+@Q{8D)zhFG1S+{O zevVB#R!h{mJh0Xc<<_y^l|ddp*Th3PaqPJ`vVM)nVx4bze2w~SSuZv`zJ`DHz1?7V zsAg*I^lVvw+3@%p{@L~8fZ_4A_p|f!8^hyk!e^KLpAC<%;h$ZuCHm_?J>5Fb!MaGA z`_LV1A3tI2nx>iKS)-nYP=ne6nIqQfq5D`a%>faTV`4>wX3iCgpse{W5!Tex=y=aO z8AG~~G1r{ON89q{$ivP`S~;gsR7loM=a6n@F({TCVpjA_0V`sU;>(em)uZz00&KR^ zY+({kuSRTiNRO!TK60Gckw$Bel4;Kc>S1N=(Z85_O~ljj`@cc-Qdr32|*yM1a|ZlegOO@nD`SWKx&V=;9<87*S?BExI=eoy*HgK-(iBE zlnJlx$5;ElR(;MwaczymXp?Uf3#{5UGJ-Qk-5fu@xAYZzjesj>I63SOPP5%y4 zh(c`mqEuh-Vl=HDZL3aZ;Hg|e;5Q9=&I@vc(O&IGvx9qFDV`P>ql|)}QARiD~EjKgVxG1~C2Ge#TcLak}~DZWsjl09cB zZ95kJ0!P8-9l?0myrY24I|@AW4wZ1iGw<-PYr3Mb&9aNI{Cia`)@LP6RBS_#Bs?og zc>b&;j?HuHafBvnnbt%t)0(JdN)xrrzOpV^ji5!7iFa`g9hc0SI~`st_A)LrnyB!N zCMuB8Ltsv}9uc4w<2y&Y`#Qgyss9UIkgzB(>c$1Bxwu{thQ$K`aiq66@4>dRYfRfu4# zig-kEh~Q%&t2KF3kP@Z7%Us`+h~~e8qFJ)I<%6Ul zf{%d!UOg59cnbn3z6fJS{)0jd!W?Wf*4kE2imUXXs3kuF^&*4k7>ENsvSX0S@ldOB z>8k=7XOE$M@WrCLh)NptDI}#~f{sD<1|1V2%!Ux~Mr+|F6`S(RLz77zJHN+kh%uWK zcJ)|+A#KjhHxGQvYqU1>eCrv*wME2d_*I zjl?UzXjxD1PhS?g%DF|xA41X-;nsueW%80#q*+-BhTI6aq3E}r-Yxi-`Z~7 zo__85Sm$ehh*{s+{o0GM^lLB2cE9#VP+kT8AK<^j|2xiK1AYVeE%^V9^A~_$0)7Sl zpK$(X;J*O>Ew<~mf8hLeoWF_lw`1wopNrYa^lQ(>B02MaNw?0IeaoKB>5Yk5r3>S; zPPxL`UOwylSg*YM%ezM`=-!>!{c!r^{;g17#A^24w{+i;zH#@^Ws%OU&YazL`m((p zHdeR?b%ecrL3ihfgSRd0PAAfj>^^xHR&pb?F;Vn76TRZevlMJFlp& zp|NwLJuJ~}ZQNBhzOfU$4UM6?OR<9doW_V%UN^llQ8%@*vaT9uodc|*-t*`<0$1T0 zdso>gjY7N1hBbEH2wFjB*&yPj@bX<{$La9IuClleuk0*?t`+3py+IuxP{(K0@h|H5 zraHc(j_;}C`*hsUO~(h+krWZnTKN}sd{Z6YQOEbx@qHWvGW}FyRzJw}oGZ#_oxNZW zR27Ys66wvU?#{<|pKPt-zn1Pw)Qlk?AZK67mt)rgzRp@@-`)bbFYMlZ+TIR|WAAJK z6}u-O`^>sa^@8dzjoQ&%GZy9!eUREC&A+jujuWkfKCxnb`25hsifeW|ljYzPjpk7} z_3kB|dgDY70eqPF#+&Qtv8lw59erz2d~>i${A5}w9>1BB=F}joy|PA0qb~N>rR1p3cN?)ZwUMyfqx|M zPXzv%z>f+1l)%3g_&I@J6!=wv|1R)b0>3YC0fzASzM=xt(B3d3H^L=GZZ0s(%I$o9EPIwwa}RYrg1R5E0TnZO+4c~x@(;yFs&0m-0%}7JuA566ps$wNrBHRX5Ak< zNf?c@;-Br&UF%|jD^Y<@Q!H4=6u7V9uL9=#N_jl4)g-b%ZzDY-!v-h0(3cNyKnrqVKm{Qt1r>Oj-l#bAFgX!}@*QJ!&6N2$j&^5o- z|4JzSY<)@1qxG}6jHZIuOt4|p-@o4^FqcIG@G$(Sjy2%O{PTfXK34#19=)cu&a<6d z4SE7UxU4m;HIHlEhCnWB!W{n{z#RV$kH@vX0j%%cP7qV;k)-9+VZDH1ByS2WGhuMiWFX>C?5o zB+HHNm3auW+!DYnH^R*0)3v@N%WbIOA`ybKR>1X1NjO zczn8k9$9Wv1rOouI>zg&k#;1-T#TQu9XVQ^N&Q5Mfp~nq!m&8(gP*T6NWBHhu}`7? z2T?Tzz_V;Au{Lh>H7NTc#9!^0?wnKsdN2^;=MI8|McpxQ*#S z3ZhL0Dai1wAO*KECrCj9eQ}V2OkWnHAk(P;g)}JV1u4jLbC7~OUlF7r&sPO0$n%mQ z1$kZ;q#(};P)Pqy%Xu{NOwX;LAkWi+6y&)C6s`4nW;=HC#u+(0e9-k%FmRA7!_nI( zCy!VSj#{`}JQV2=I>6Br?bvvw=WvyVRtVp*kE5fZ_+F!d^prSul^-Aw>)TMB?kTNK z!%sPJY^uxIZoeUs)Et|o73BMkImHVfJX9k|nnCwBa~g;5*uTWJElM|_)Zb698WL{7*g(iYH--0CO(gjr%ilAmpHXlhJbLod%&2#+O=Zs8{ zqt!es)M}pg$1JrkgXOJ2yg)P&r=z}hW;b)5KBFogRjd6&R}TJ!36^a(Uy+NylKDmZ z&HTCije;s-*Z^hG|OFgi-rLZ8SN;?C8DzG<5s^3vV@Y^v)nxS*3kCp6Wwo zDJ4!lxRDw!;~-$q-RPkpko+@55VCL0PhjlBG+iv(M5WKP*oUfLatHXw8GbHG$$zup zKNEP!AoNTOKZ{QC-zE6_0dEBV#UBv=1A?E#_6_ha`+)dqoS5BkfYF1oBIyV4zroD# zN8xuP_&@sr{HsI$1qs~XAHl!X@RNMWNqx^=;9>W12t10;!3+AcSoJz7OxB;%1^<)4 zlXX{~qfox&pCI^?2t6Kk^UvrHk)z%yIp#llea|A?imn|6h4~u&Msw4oviHAA)3eNf zQ)V>3c3@sP_~JQk2a3_Z(!3-BR~TBsZ>fiN9Bo$Q^YeQmZ~+tb6=gZ~Lx~DLe1nr3 zDxp4MRqoT0)p(ICZ*N@E)NI**L*F75APKhWI`4~%=)U@)Qs8F z(RYm!Q~jEy&8c=PvG>tav)QGm{)aWD+4fD_#prYM$2sgDZUJOkz z%3NFHUdSY zvw;i!Y;0B8pd1v@#;oOGdUmR+FQ78l)td<_WLEtwzqU{a5p>9;dR0$UJyszgsF3Pf zJfvL1DTD|rWOD5k3MulgA%Y62n>DAVZjuU(dZA3zvCf=5qkd9dEkzLXSgM&Sd8QIi zX(rE9^O(^Skg9HPOVu?mq=GpCvgl8;=ri@f5IV>_$%d}_PN!!P&cW1PS!0j(Ij0xC;JwN#lHnQ%f1DVs^Y1g zSzT3|;|>H}-#}e+(@Jpz@6ZiUhWp)%LnLt@<-HhVAq6Vhi8E)`o0{mC0TVrr=`(94 zk>LC?AQnZ{iB4>7ZAX)~cqz;6M@XhWCDZR@93qLKI2O^qyMtAvvZheP)@Wo?y~hF} zidU3~%ERl-DgzX!xOL(z_zp6mB9#I9reuDJH!=blRJ?&((T@6|9x2l@j&wD;(faI)eZ&goQ|4dF5pg3nPSg^dgJyqS>)6nkwQ-^x;P!oC;N6bAQ zuZ(1%W|0U(BK-?-h{th=8MB#K&}=4_X*Lt{&1Pb3Hsdp~*-WfOna%hC>bx*2&1M!M z)u?Yavks?`#OHCezkx$Rh#=nLF=I;O$7M`uOk~=2=6hgPk?GT)Q#5blP_AlzNg<-9 zg6L1Q_ZR`GeDW#3{WOF1C+_l05Z85piOQDXp@@(%H(E%Hn|y~Ol}4!lbZqBjbfZF5+K$+aYS0*>`VRD0`XL19qOl}5flbZp?7PHWi+F7-eW)zZTa-@*4d;_G-tztYv8veG^#pEs)|9$4)L#t2V2aN<+uKoI38* zh)q()eU_3)2F(dww~~AQ>S8`YKs)j3HT+p`r6Gp7cnXY z4f|$gXb}ZwWT>w_m$RU*<&(blJe3JWRH(0Ar}CgECO65p=5~Fb1Wu$$LECa$d+B=8 zhF*TPs3*e%^+bl|wIJ`!Z$0^yy$&U{mW$%Z6$R^}W)wosnqptZWkD^l_q}N9nWc!T zV37K1RUV3zSx?Rk))P~4RUvXcsmsXDqMY@_%T9=bId7(xS&C@t$vl+@MKQUV6{shu zt;C6*vtQfk;pbFN4uKEnVPQQ&G1hCC)`t(LY!Pgt~xX4|0@`D1mq7+e6Bjhvo1{LCB;OVq3jF z0b!Gn)$EQQ&QW6%Bw#fxttFfloLBLlVCPr9pM)t&&-MSZ#mg6J8PGUP$~(iGSW7-t zE1wOVp;cUGg6aZ6b-l7vS9t|(zV*0l5&idL7UNWlb^v>{}^iq)_FlZU6O0)dS zn9k;2lNp?=Z}rQwhPVQqrwpdNmg=NDm+Cbz_tRyRs~6RCsa}}zO3M9)yc`9jhbIZ3 z#MjKD)!B8AM8m%JtX2MyBz+*I#JQ*mk)y2%b2GA*`)xUoa`X_zNuaM?ud}0=IcFDA z7f26-s*L%k=xb%XF|#|ICsynFRf5?Ws$X=qsXCL}S{M5@tSV5$aDn}h_5OpfMjwL@Z)N6}|{A+8VdN@Q4oR^~pqL%eo11|~Gz!NJ~ZNnjq z8N@JpVPPwQU);V9n~;45%RgLimD@KUJj1<04+jsxq z{X0jD?5_Mgv&&`)`g|`}U+q z?7Qm^2kq^ti!|(j{nlHJ zdxxLWy0_!xMthhuXOENKbg-~<;9VVsZ(Kj5v@yM7@cx5^q2lzW&hZ;p_Cr(NX+0RJ znsdk+y!{UcDfRStd(J)9gKM9P9J=Wb1NUFMw`2eH5o_m&efN`f;=Vom?n+-fcsp_J zv<@Cj-_?2O-n(Ypeg5@D&p!0nD~7@XEpaAsfW6WpfW?vsFo?bD#xjY}?%*GTN%7 z1)1C*eInKcxgalh9JHU@a%lG@4|b$)eCV{jrPDTcmK8Vb>KN7-?b>qi!5jBNE^jy9 z-7y%_DC%~-!rxTSE{z`Hh+JjxmeZ{LU#pu6d`PUzZpL;tRtIlr_jySEkoa$u}$ z%T4y}d$&5b9{dvW`{dmnoa0>sQJ(6`Nh9>NyCM%Bnta-?AA9!ksfXrv_icRf3kM>5 zP)Y{}cHQt?fgb?h7nNo@Da zpytrPuB~_Pij3`!b?quYI53^wRk*SE5AZt+uPfd%Fwtd)&YiRM?xzM8b#;PkZ{e1K z(Jl(zh*09buK2Zqf7lf3Iy8LCO$UcV0}=I+w5mUho{5WMajJpI2FDFcW+lburd)H`vt`*L*fqRk7}7r@7*qM-cVT zt0-oCNO_LFn}~ldd>IeD9=!b2c=4>3@vtrfMK;{+#!gUS+u0 zS$W>YDnDldhR-g4~v z5X{i^4l;CpC9ZGB^R{AxnsQvCn6l1f3Bs0~+MQc_Ve4a2UX z0(F9?DPU=c`Dh9a$6;MJx@1DsSO!MQtTF1c!YoU~B5dh}SfTQMoK*oY>RTq346@Dw zCFUC_#L2pW*8`1U~rzC#7Hg@dK#*PDgW5*K$#*QaS zW5-%F7`hWvKy8O|+_X}2PL7&?a@1Utqvo01aP1j`33CEZ$E1xM>5G$$8C!7FO+1Xh z(D>@O^`hO3zar?53QU^->$L48;nP%{R`NZM?qYE+Kh8nGT8Y|D60SD{)HahwQc}r{@nuqL*Tareox>KUO9Yip};YLU4i=uJV4-tz^4d&y1-`% zJXYXy1pcJJNrA5vc$2`l3;aES_Y3?}fqy3OqXIuE@b3ivFM3WsKLy4&fR|QS;Hbc50w)Bn6nKHaHw%2Lz_f`9-`6gI9}@V_ z0{6nyG4uBmm^M*i`dI=`6Szs>YXtt1z~2`5Hv+#a@DQi~a9YCzK2zYa0+T^2^UoBx zP2g<;?-TeXfnOE)ZvxXMEgb*50{4Of0@KF{e6heA1l}$1R|URb;O_~%Pv9p7ena4s zFpJN57$Wd6fzJ|ntiUq`zFOd&0(S}grobmaQGnB(Ebvl+ZxeXG!2d1q%L4yd;J*v} zmcYe$Cv&=`0@I6~>7Nz&Hi7RH_-=vI0{=?j7X<#Jz<(9^ZGqnx*opc1DH1p?Fc~Iu zo)-&TSc(sN^-i&qgomQ7hf5X#Gye%5k833aK1J{pz`lt2`wM)wz!wR;Sm2EUZxwj2 zz&{iCC4t`+xDn>F zxHo3Xm}j`a69sMp*72jyCNRyioz8LqevIV+%yE9!<8iIe3*6qv=lQ(Ay9EA;z`qmt zHGxYp3B_p*75Hpmoj2E_iK>LjC*cNDS3fEEFZOs`>r(>H6Fldm!^vqi3A{<*I|aT^ z;D-f%LE!fV9*8Lzj{h8iFA%s%;57o@Eby0r_5HdQP3xR$?wv3#MGTj`6POL{f9UbJ z)&l|`1m^sF4V`Dk4+;E|z#&WwGS6`WpDA#yzzYT5DDVz}e<<*y0>2>eI|7H%Y1jAb zsyeIt{PUGObbo%nRS5wwo(Rl5=0L!!y#O zV-q%DmKEV^T!|;5^qhm1&R3>hR37>0t3OqVqf^aN{2rxgV<-jZx z!bSMOsYM%DCM4s*ifktdGmlS4e+G2=Q8|*&JcQ{-b&u|YWkQ&Fe7fG`ie)lV@DOI1 zOaT6W$a@#~D5|r6{LIYmW|I&$O9CP)u0Rz<5ds2gTN84DXdvq*B3d*F5Fi=|O~M@k z!3&}-8WGfLr3%4_wtel}t9Qk=QmnDn*0y+QOIvMiwJlcLD*OLF=Q8um?gnVzuAl$! zedm+ReCIjeIp>+@T;}Y|InSYMC@sP!9#0+>rH~t&5H=i7&TW$Fkb%NHM+zl4!=sl; z#^H=w5RWq+XJ`2&bXMw-|wy^g>urn(7IYKxwkRlJM!TD3X{Ok6p^f zr@T_TmyyG!xl%dJ#Gz=ZjM7GB*s&_GSEZU{W>e+FEJd}^h<(R%^cj^4$I8snbxpe7 za4gDi(%!$Bsi%1mD}Bfc{_RG6ik}+bP|Zs>(!H94pA_H>#y&kBGp)2ha>}qzkH<_U z?Jqf_GIIU~DQ)QTBP|r24DpyLpj6JVoEL5!ovxJ4Of$x-2ykekabB82r)degz~Ip2 z(Dcnr2c~9SxJMEjdgt`^f3%iHXJHy8j77VnkXgI49{ia^nrc8zzl;-Qo=LDnKo4I z-}J43Tjs;drTsDuH1r!*4;Ia!xeW2mNcAR(xL29`k%F{4k9o5j;99oHM&)v0hy(hRt1Jt0Wd1LjvDE78`f=Sre6y|R@l0Lo)>zfhiMf%H*$Kk(BnXs6C>2e#Toc99mXGT=CVxuQp0DDI>XO& zT*riM?8#Gu-xC!7O>-3C&$@Xq`jeC%>t>^Sdh`Nw<{e|D9@bGw0X66Qj=vEUFqMrJ-?B{uRj8xe8`z?J3u%1udGxOJSF7D z^*Ed(Rs3J&bHut1*=FTWE1z5!Z>XG!x!}{`%x!`sH%b)4H}L?Q@!i{Yi@c_nFd294U=7f@RW3_|w=<(buD@ zn)|3rOle5Dx}l~nUS0#21Nv4oQKo?~vmstR9i>U%4QMHe1t^`TQW8tCSEj^LDU?`3 zCgz$BiKSTYvy{%sDBDJD#1gNqDN9t>U(%4MuB)CtrJ=H73NlFF77wo~tEq7bZX!B` zcw1`|M!K&M_G^^JCYA;)=ceI{!z989T#3~D@zR(~(f@;`0X^NqR)ya&l?`>5Ooyij ze{loLEpZuGVUtVs%d2Qv*t!*q=9qFvzQU~e=u&*;i9u zNZc^JwxOc3rtA`Anr^pJ2s(7IxmDF-b+#>re?hcazo3NQWeHENuCHr|S0)-Ru1!=l zOmef%FUMl_FO@_=2&Z3pQA17H#SL}v zxl))OSmp+LW^G%z7+#E87R^_79YhKpVp>tqAF4F4+)wN(w1=^5zWte@hQ zX*bvX1lgcfCK9y?e0_22u{%4}G*p90M;dZs6iuLUsBbv`qPqI(s!Na=H8l;FRwmHV z)@3M9e} z=onB1aBW5{iD%M`HuF<5*vwDJWV6KbG@DhEnxD_}Y=$SD?6XWQn?Aj=rmmrKdfDWf zN>5YdOt}g}@vW&WudlA1?vjk*)kO`{%IYqttYFc3mk3*zmby!(O{+}QSHn-vOk%o` zdOZg`XBRXrTGZUC%=;dxOrvp3YSS*N!S!0H`ipBD;$?`C6mxUhN2!#>f|1;kKMm_f zw!kX}B^GaL?`)xE6NP<05-XwXW&kxK2IYTwa)WXP&vdV&uES5tKkv zKQ9$mS5=Q#^-c}(>UU}gD!A4;HDsJ{`Un{>0)2#>C4zl~Oc0?yLMDnFbHlE2C(C(* z_9nXHukkycT2@!tfc8~A@!X0MmvYKvSp$UIQKCjGzM!e2Sw7x{y&91fQH*kRztGwJ z@l(s0L#d%}NZp$%?MhAj5rYD-j%`Ya%dKcx+A^0s>Dj}r(>c`yXr}C?*GunfHvJON zQ5rF4B_zwCzC33^tXODOprh*cBiR6T$Q6-?C~m!<8>IfU;_?v1mA!JeSAdv9)FD=E zf0)NlaDEPTZauyiX7W`&{*k#&3-RE1g|dJQpL-#8f!GY}i#|i=P1uEQ$Jd%1r-OQ$ zI!Edf{!GabCi#`^?QQK9&7D}gQf70csO2-)ZN-`*! zG52BY05Zbp8=`p#%83m+!Q;wJo0AH0Mfs?)Xb)T8PuRtW7pQ zoNLK~nHJ(KZdoMzSIS?FiP@Iy3}MbbNV`8c^TZQy@hB;|8Sw3(@H_2_nt$xFsyafj1N0uLUzqeQok` z!sQORGx55lpyg8MS32hO#7@g1?XN_36u`=(ZmYMFsT7+6QNLV1GIU#&gU`Z6lMSy?zj z{^lHA{)RKrxG+NrpniBCB_QD|0mo2|Q$FV=u?xfk196VYS|T@s zUFiF?b9CRZylu&%PW7x8s!yQ$j7IJ(?rhgRx{eyS($U?5bE*4~9^@=!-A=kWMGsK7 zydguFv)FV^6){L%(*`c|%6LkTRz8=Hr8}eh$$bmEKYrF zzf)?6Q*K95?M!z{?9{ta^Z@m!)9zHpZtheOQ|=T(bEk>rneG(J|A`{HpWGi~7l^$= z=daTFudxd~fKeIYf2oz9qq~W$n_#a!Os9~ws~PLvGGB|TY8;a}9gAB`X;*zUBQW<} z7q6byM82AcX8Hwxq}!yM%iW7zAoc?GMK96$&#?Pd zu;&mmY#c&*B;yb=jK_$uf?j|;&&lBqA@h;vIi5qv<8T^?QA3R=V(I>|Sh{~KmhK;mrTfQXa{pMY+&>m8_m9O^OB@T! zD)*1Y(*0wxbpKea+&>me_m9Qe{UeUr{UeZe{|IEr^ELQFxi?#d5V&(p^Si65LR_-5*wfo0n<^Hi)yMHWJ?jMV_`^RGC{;^oQe=Jt+ zAB(m7$71FFu~@r*MEcVGBaYJjBaYJjBaYJjBaYJjBaYJjBaYJjBaYJjBaY<$5eMo1 zvDkJ02nlol7zvVTYF6@zpJ)Q;#Y1Kc8wVlPMHn8&9s`>yp}VwO$+ ze6~&h`p0B?)$aHIi?PC z#@ivv=g4U$pY_;yjO$YGzYwk_dzpHjM#yq*kIi~+FX=0{-S=<8|2htnX)ed_Yx<<@ zdxIvTRwAvs&hlb8k=}`Ur>L$b7FiL^Nz~H*C1ry!TYgTBTJuno)gm4$P45(ZGtq<- zQe=Zrl_{$~7-h0rIi>dJv?S@idTMx1+46MmzB~HA zkZJ>2JsmdfQ5f^xbH|E5l-5we`sjdr%1?=RWb>WqDG`d~#i zh^sHZG#*8MlVh@sKQ&XXo0svr#*X&+GIl-kLypEtkqs&(!;6BvacSA32goB_hzZ2f z4_7yP3?a+e)06e=dF}rf*&_#5rDo4rWOz|<UN0o8iwiaxs^370Vg+ znv;Bl@JwSt_#lQ%lMi{(uO748Q<}PZ-+&g7h1iaNH3a$a+$?9_v4Lzidanem_P#Q2 z+MET8bd94SOOy>v6t(JG;mBzjTH&fuCJ83Tp-YZQj z-M&G2U-&P)Znggr?7N@jzf~HFNJZN(?W?!sXT6^BT9Z@$K2w~m z&VtzEcLoIwq7RYC!iOhk%0hQ2B1l4z&y7qu=&`b#fmppF%PG`_4x54Aozn12oqwM2 zFxlskc4xYhZm<@WK?dM@3(Yz!sJ_%mFFuz_%xG)A_(pwef{aV6ZAG&+Ub(hJS9 zEq|SLTmCh(E&t6iZ$W8H(X**y&w;XJYj^0SZTr`RM9+rb;Oy1aSc7b1&!+NQySqdp z)R^15W#5VGa(jbqVTr=MJsX`F_lLXp?%ca&E9d4leh8))`XNFO`XmP->DgeN`s^p3 z|H_`Bg#U;X`T6r*dnAYC3SXMs*|qc5XOhrq-OjF_eeWiF{?KzqEGg{nNThM+t+Beu zf?fM8(X(+^SN9hW-Q~>avAVYe?{eCtbRAabDk#kD*<{^0FS+OTkoZr;*Z)5ppV9B~ zw`=RKyMCFxN%ZUO+L!$3-c9{_ z{{UHd|DM6gwSVYZ*!ax4U0tz+(^84`)hb4nkD5HHY?SET)wR9;vn@Z~wB@obUC$(Y zHtwt#wXnQvDAuCG+4CPI`!xj;c}<~2xT)WZJ^KzhcRs)N(6z~&HhC7g^Z9#{8S^c})dk%tefo z5o55avMUg;+!|`@c|g2GD*!&T&U$5g+cRD3^j(SGytW^2>Um(xWmt31CWiIOGq}IM z&8zIX?vPo9u4ltz4-e?QZC~>J0lf$I-nO-8qzE6VKejQCWbfqlzO7`1Z`Vf}_jDCV zxp+74#h3Qx_ujpA|E;%m<@eq{>9(yD$NR|vy$8YH*A;9GzxwQufC#kVIQXAQxe6h2 z%09H?x?Mw`?g})%gM4t>-Wej+0sZdhUE-y(t-C^hxs3GOwMpgE-mZR45`*=tuClGx zOS?k$?8Bx7Hjq}bPqyx!mKdjY)lhkmzJ ztrY0q@kaxCUs88xzf?cE@$HTBo?p*k%lb{fz-;Kgky%L96MZMtXcHpH0s;(*?t@7=aFuQ$AZ zTUXBz5gX8Z&sJisMauVV%?A=mD{iEe$GEaH} z!i&09cuVH&`^bamy7HRdNA3DqmnGYaKdTV51mWJl?|on9@-2IFd*9!RI&{x1d-HnV z0eT^M3+n$nTdD53wg1q7-u=)B?VYv1et6@7qpJM}x|~Fgto^1wr`B`RDo|P#dwMo` zJrL@B(CcDyEPtf6GmF79TNr@WmYj+sms3}Vctw=m1pVe`FXLO2 z9v}UZO^eT-QFN8NdZ}5&PDM%YF4FmpK0dbty~s=B-{_DXZathG=wqI%H?41q8;L=`F!p+=TI&PDWT40T3pi(6l3vC zdw?Ar6teSui*LR~OL^+>B0Kk(ke%xb|BhO4)cGii$g$$+O^Y%l^1LSfG`P*VwV&+} zu{#s-bDDU|fNh|Buy9+dy4yA3n$R}qANeZDu0?6ItpU>7KFL|N?Mu$mZFFma0km}L zfM9`bp9qwXl}2r+Fl2{)x096S_%|;60j;ZgbSe4`__d=?(SPBcVY$?+^HvzE)M8;+ z%h|SUTQImiU^{Pw$$Vd5Mgg|-N)9aUd}kHyzZ=-55UnKZBv(U57AXuy?EqGt1#;FR z66d0Abd3JM4itUSS+UJ_ih~1fX8_8Qs?FT9y9ygTKxcT+D5>dT_e&b3I6lv)Y(oQQ4XugF=21cN6y zYh^j}=icvv$|O(dlF{3VcW$u2AH!G$R^IXUWm1AWd=HD(T6XYsr)k?aoX-cP4W0Ko z)CJe0+^GwabPKWyeIbNm=3h+r%@AdJa1fICuQle1mr)7T6?@je7&QT$-v-9_1JY8? zo>iob?YxY2h*cV2R}v`oN8;GQM&}{2VIV+Jwk+jOwOYN{y`TG8JyD++Q9j&%2Z+tH`FOWr@ zN0&*}q3CPjZO-{PadrnmORYs4`pHIP01{kUD^$b<&im5d z)Rx`5Vw>||KgjLCM(54t+nl>m)Bh>9IS;IY(D@0DY$R+`)S4q8WLr$4#3bGv&xSFhB!<2+Aw&H0+M&G|L)weA^PmWx%(@*HlQR=svxmA3=3RT-4hJlwJ>tyRG_fg#WfMxbl9 zr(E$w>J?stvdc6m%a5`_c`&3*a+hvU{z?rB(hC$xyL^-EV%m@gbsKW4ZghTtHd2-N zM^++ttoCin&=O=jjK7dN^taolijd)K$mmHriJ-YpTl`0_e^kKK% z_yM(`vfZHSX4}OwlfQL1wFjkkQDoqA6u2Gcgg!`F zEwqi+*3NUndi`i8WvOl~OR1LX4yG;D9WqOG=Xh&$hrPwQbJgP9d2(^?Ap8QERl57} zb+2Wz8%o31lm^q*f+;-%!Gta+aAOh+kOc>O!}Sx{}pmiJNgYr8_Xp)`h7^7`E5wQ{b(~hbET2fZ#3G>k$!{G zW{%tCnUEtg3DR#S+UU0sZSkQKZ*Cw8FhVNx~7sJI+-tdoQ z_y&eQ&+z*Uf5>nPGSS4dh~b|yyr1DXjA{56F&xH>LnAL>cmTu4FnmA54>4SfLSy1N zmSI}B*vOw|xDvnbjQo6t|IF~;7~YZR@p~8^gb7+Ep5qvfG5iUJuVeT|hL>afjfv+f zhW9f30>dvc{4<6RGJIlz7v~g)7c#t+;inmXm*E&jxf|W4F`QudVumkccs9fH8E$3x z28O@E@GluIz!+hp!&wYp%J6!Izs&I082%Q+k2CxX!?c*NN$Yurf6wqS7;0-clNnyb z@K%N&WB4tG|HSZL8U8!NhZuG+RM(^%W_UQmwG3ay@PiEhoZ$dQD4ICWVE7V-H!%DF z!@Uguo#8_aI~cZV;?HHcKf^@~4`z5A!wn4I#PD|*KEQARUiz4H&t`ZI!f1&ILUAT4_y=g z2@FqVcp1an8GeD`ml*yT!>==ZfZ?|o{u9Hw7|CPw8PD)6hSxHD7sKCW_y-L4GW-*U zf5Gq@4F85<>WmnDPGz`;;TDFw7~aP4T@2sL@GgcQWOyX}R+w}rGW;oqCo?>S;Tnc7 zWOxC;oBI#li_<9-ofyeV3A~oBk=5G(jCU|c!sMOz7SZY6&2(a zYOYR~Fs;giEk2X+*SMUhSkLeh4DUASexBi73_r>6kAPKLQ9-_vR6o^<6V@wf#ec^5 zAG#bg<}t&Mig$rcy16HLco@UyGCU1fr4<$ABB&8Ji1*%c!sdSK8GohAiHbE0e|DIc z)+UDUWB5^qe+aD7iVE_NGh3%i*xc{Sz~){)a5+)&A;WJE_c*~39v;f@M24$@XUnvr zg51JfuG1y_M@yc>u$Di!QIR;qi78Mg1 zCVwikw9bUz)H;6(*x2eKmlGA2FkE_y$GMo{B@Exr@YfjL%kY~F<43TY?oeQ*TU3xM zkVRTg!hg_ueuD8!T~1U~Fg*HHFV0Ga8yN0n_(q0zGW-a`KW6wK!?~v!J)?r$T3n%Z zCj6Gxxe$1hlt;yBz*lHIn&D$cd7RM!wEYLa=Hg-P1 z_=j9hRM?{pKPvtJyh+>NKGVa;Gdz~zsSM9%csav2GyGo+e-~Kk85J~VeyP@(@IAV0 zJkR)Vx}2zZo8g~~@$~!)!~Ms4^3xcOGu#ZU(#3lQ;PqMu!bXQy#=qX>M8%B^FDdcT zx`p9~7=Di7cNh+gGwDVJ%~@{OIuJI`hVjs2I)g@#8(tB!=r5Ud-^dz$z`= z3-B79E@6}IO^m<~pqpVWZE}z(${6xtyr@EyFKQ@;L7@ zoPV|_KbhfLV3k%>T*2^ShH19pVyzEhS^*7Pd>OFO=MI+>6?ZdyFXMEbh~eKdoO_5j5;nNwWDPSwLO$a}u+s|>p#wPVHCn{z#Jhjy0%wzZ(hVNzghrlYWsCbLvcNl&T zc)6g>iW7cJ>+?5YqtBo+!-eC>{sTo|&=?fy0_1-=yjlwYOT8$QhA@}~kT4$3pI zx)&=>*ziea?A+*bqOy%q_h`kby*VEL*y8kjF#P4fiW3z#0XO2G^dW5GzZux@$E;fH|@zn{xNxdm>;^%Os0!;dlk2$vHT zJnk0Kn?{EfgS{+nD5 z@(Z|Aa*$uZV>JJM#(&V|!2ZBXHJ@-y^Irir@$YvzQE?D>x#kl#@qfVhAG#d;zOzjm zYsCp0J|-Br@t^K;qJkW)tk&@pHujmx__V^c;-EYOQynII5{^kM;x{w?7MBwh4+5`~ z94k(Egyw&h@&DW9p#211ula;yn*S28vCk_m2k%vYuhD$MraT;E{104C6st;@Hr9$0 zHvE3TCjLT~6O}Osfqc`as)L;eXJPcyKRN5%EPvo(h>eqz%W-{i`p;;X=O zrPzuSK1pH`|C%e0iWh-RyFnPQ8fc4C88&SNl}Xc95Jopra{lSc(GN#nnD&9N;f#0X z=+gq5Hi59=(05oRkBa+%O*=r?aJpT2RO|;<_1cOPE`lD|;`FUn$)n;OM!Bn zX->5(kBT#LOntQCgw1`8aph4_8uscb;W;{5n zn0iOpa6EZb#2`2Ij>Mp2%EG#x#}Y=Mi}WsN5dhkM z<2y{f+sHVCl{_kL2BvsPAHqf-Pac(ZdZp&v&NzgXJSw&Wn`b3q6OSj4iu)m7gMUhk zu;F-ew6~D2!#{Bd8;&QBif=)_o+#iDHXKhL6;DEb4gQJqB=&|wSjnT}`@p8&5jGr8 z&g-2Jhw#f{z8FzHq6ROiC=NlGB0CN#&D;3bmC$A8$BjK^8TC&3FGDamy? z6Cj~@@?8mDhDb?)E13idwIlsq3AOO_%fOS29iyI$Oai6ps)&0P7Oa+6F$t88`8iOU zt}67dg3^>0lR#;@ib`9w$E57O;<4ql%}gZNeOfw2FU>TsuJjYieCbq%l#7Q zTpTE;0#p z{+yo!o#{6p<3Q)z{SxSWr(Xh{M?g~KT5KG2hDuxlovAE(obe#!K~n5qH6A+m^Gl%f z$$kkUK~(%I=!{oRTmqfXgk+!>GjyiZnFKmhJWK+e3n3ZgT?N9iKFL|o`8dA>I?wb= zpfkmDj2q8cNSfkd66j3vFbQ;~rxBAt=aV2A?8O6}$r?-oohSPx(0Qs)G66c*`X$hL zhF=1m=ldnld7)ndojd&!=uEAxr_TiFOy!VCpz{X51Uhf@OQ7>6pJXC*zSS>*&bRp` z(0K?X$GY~J2%X73Oah%p`X$gA9U5F|+JuSFnOaCDfzD)kCV|cr&vD*W(0Q~g0g!o4 z$Kxf35a~kO2~sk;vw1n$k2V|sjwPXQH(ENEP$H)<&g_m3b5WoV4uyYGlR}ac)@T01 z9DRyzDfB@nH^W9bLmS25Sc4=^-R;x@vaDkbP7RjlPiiUEdB-BH(zmy?i1Nd+GV2`C zcB7U8gS*osfn<{A6i80yv@X}2{*ptvo4)Dq>GJ95SeZGu>v*WnJJzY`kwEed&50g{ zL%-8#8-Rbu+KxSy694vh%_)M|u~3vVY{%)#iY2E4`}BA|twjSRrz}G(=!a_#<+x)} zuRJ}TwOVwH-my?cGsIIsl?EHN zt&W9?onafLImb&*=CUzGbEx-#@%tHK!S6LKrv8LuJ%OTMoyKd^9I9E4RZ}U%pLGs; z)K!`jlN|kZ&I^|42F*E1a$dpy{1gVB(wak0SX-u&UOxU?bErj9=6ppmehk*tE+W>gQ=Ig=ai-=_e@t=G>&6t#p{JhWP#N-X&6<D}%G|Y7X_06lZ%H=Qo-|PY}hS^6K9($3kxOOi`Tl@;XFw zs6VebTEL<@SBt0zt2pU)uG1XqYbj0zi$TG~nnTZS#i6?D-!^Lw^_mnXz3tegIrK|G zankG9_cVw4T8cyMi+?+yIe9K8J)RsbqF+ENp7i`0sX6^zj?NsN+!Y9~uO8dEqUD0x zMU$`W!%q|U-sJholF#&WbeLITGJWN%jI{K{;e0f|JGRsy=F!U+l)Cs9UncFa#L48( zl2*ga#Bxf>H&==}@fKTxY+ZV}mf!!CQ!t?gq z7e%cVkU11y`8>C7eNw!&iT!!v-cE{h&&&~Vx8Hp+j(9u9b-phG=@ia$WR@Prs>$5u z*-Pd(w6-j27NZqzSv0TB;HKGFS7)hvhJ{+^H+PtN=-w`O4xduv++xSeX9~xyl^Hm0 z8r)j?`qW~n#c2gn%iXB_t`~JEDmAOQo{;(O)56rMqQ$B8+pT9h+)X~EtfvMmEwsn# z^gva5wcNC8u9Z_0OPi- z&~FoZGRjISCEjjK27XKj^WUT9icI`c!)L!u4L{Ry9TU=bTeFS84+)C@tDjI3dOJm% z(cfSx#O_@D*HdRdWs8-1f>9onZ$|bWfnUk^)T6(Yeki1DJpLvYMryx(1pc**Prqd* z(2tCijmO`^!l;LM#S!>VGk!VnPmaKUmGMcRSwopXL#|Jf1yjDb4DmG-}CZ(FXJx~*%i9;;p2_LH_9LrqdYw2?&Qc}Z*wT`c(Gy0G9bHpjhk(T^ z+FRx?=!}h=b82kt*=J8Uqh!q3NwNCoO~!$?MoImFX|*br>%W)TYFPy^ITzt z8ycFMT3g$eVNQI5i%E({ot8;N-{P&DX_eE;tEM#6)FsNMmDf(MPt?}bR3;kA;}3g8AVK97D$OlOLKzrTHCM|j2#Hh zZCiqROo%Rs>C-^KOJCh)xX_Bj?uFKcWmB`#i1o$j{Ox0d1$R7?!pS%FRGh44TrWk_V&%O+8OeAQoL+RB`&vb9#%H3wxW{I z^vbfDn%avA4zHeGFL@)Xs}dymM0KS+o;-ujYT|X37gf|kE&JwaGipi6`mzLRbJ0w7 zoKcn_tuDqX9dRhZ;Sznkv@9_Wr=P(o9cPs##^Z1qPU(1gS>h}l8gNR-#J)+Vmw0bxhtlLc!BZH_JQlPNP$0J<59npB24Apt^Lv4iXgx>h|-(kb#!% zLUDHXR`xXw{AH?C;MIk0;gvzzxoyqD3n$i9rA}&tUxcjp3trB|x!lcgnJ?}cidARx z!o@0OiK6s#$`W~Z*i_^uwpYJv(9p>oR|sa$VnbYqn`kRnJYgvwbzKht1e2Dq|nP2nU_9 zEsI(@-L4_!Y&lU(&iX>LowYyCe%40S^4Pq(s3(ludUoI`c=-Aioh*%*dpw4BXd}*V z?yM#|b~be`QKNq76`J*3>Pcs$WZRU-W^dhG^W3@gs7#sQrq0k*#XFSE)bm8)XhIoy z8^*?X)|=7N*4jkBV9MssZEx0ttK^eIUV9i~wv9bI`^H|YjE#31RkT{7ykm2M@@k+o zusOkVph=rb^34hO9i1KMdCkTvNo{v?s$2ft?_$W2XVLPu_V!9zVUe4jUiw-orcWbg z+w|9G-}GNlriaNq)0>khDmWgLxx?`q*E82e^p-N+VDxr4)nFN@**4jI**Dp@4`Z^! zl*-gDBn^K@FSL8;u%*_yXC}p=?)zwUwFd@^jg^}h9}MC@(pI@S4irC_2Q&r< z|3HO6g$H+qE=oT8n7*6D^G-9v5Y(GBYiTT1rXamuwzM;v@$)VVW) zn@1eHDEZwV{_ureLwkBik6oeNdms40o}v8ShArLE)vvKT6x>{KF!^W76UvW0Pwsmv z2l-TSaCetykG@OAN%Ed{M~29I+KpTo+7_|ha&h~$ z2W1}2w@%f0uwUlEf;}P99IxOvhu%XTWemSGX-ciUzexVv?#S8tuDWqo-J!FZPL+4n z9XUR$(9L^2rh4aJ5htCb4 z7cLK@J5A$v%|7qhCeBprt*uz=7fD7%4IdHmO zJbaF`rs>=G|K{hM&rY15X}8nFyFaq zVleodZ`^z~Vk{Wbxgr6XWPZ8>zp{hC35S$*}>ei z?ffXY^N*xz_+z@+O1i1zPx&0oGv{pD!AOf;BauRM?S#~8OK@qqwC*r=snhOWNmrej zdeyIJA(BrAb02e7-gr|mzr}YKspR{DAP)-WpA8r8tC1JYV29j$PG#RgQCHz!jvEed z_Qwqh7Cb%4nLTl~v&#KPJZIb(vh(n<*fZ+&l*);zZs@;EnWsw+zdv8`3F+d~mxuN= zN9^!e>V%8(t5NfUp8xfb^1q&A+^&a5gZ0UN=kYb>fvYuk}ui27)S~=RN)uGMEsWqdGS})p6%!a3=My@=bUoM64goxv%8qY%?RE>Lvmo$c7 zWcVix|AOJOaZ~16n$2NwIm1&KewN|A48OqeT>R)T@pLe}oZ+h&UKqs48F?@Gb^xqL z?!?Knxryf*mxGzW40qy-so`v47`G%n&2Zo4` zWBeMIgIVGXpO@#w*}(7`hVN$hI}HDr;ombHzy~g)=Sd8Y1y*`S1$_il^}>o1?$I`% z#Q2xEoT#{r;fwI?#Kgap;X4`rHpAqZ-SB@7tkR7N`UZ2pwi{vNVd|HRZ)0kg;zUJ= z;Uut$^CWyCFu0uIW`?h0cpI>ZlRht0XdMXuOxxj$jQ@3)6BXZPco%+OnsmuSy1}nA z{7;4lqCqj7(F|8I+`#Z+V5M7B(3|w>T2I2{eFR&48RKtuIZ<&d!yE9j)}(tM!(Rth zaYhBb(5=_;6V{{c;*T=^%PuD>e#Y=?jPpZGYcpy6iDB|=Zsdc2Ra)>m1RU4t5;mS~ zPhk8{x*T|FV7QWTCZd~b;;&_RKEqctd<(EjH!A2g;S8+<;WM>uZ)f~(x*XVw;U^jA zVZ8G)Iy?!i;*1J<7e;R+@iHP#_%a>;_kfM3n>Sq!JUub|XJ8ZOZw7hzBZddy<&oi> z0Ibqd9yCn5Iufbl)dy{99=l9CS&BeY7YG|Z$&8*E13>Tyo`6E=MEUS#4A zyBv600XF59u;Cxi_%W9QZz;etb^L@4e>~&Uj9SHkKG*_sZ^zf+Xvz}d3HZkr-+-Md zKi>dWWy6XSz5xH&;@`&3lo|As-7-U1*+)nZW#-vb2l-TaDZFe0pCPe`&v51NNCIri z2I1kFv%!_as}8WqU&5c%oNiYh6|V!EGDFzh*RNc8R1CDed?#%58SKj8B?{Q&HQ~`Z ztx8vp@(*nCm+&Ob>2T%nS^_*n%Hg#Hc#!7ocI8p=IIzh_!V@*;DOc{#yAZ-n`%nlx zS@JFEwI{5v_2kNfkI6?WBZfoR;_esX% z>`b5JES!z?NhaXzY@dWm7douW*UTiG75XG}#TcK2Ji<`yo`;&TNa!5D1WJF}FM-lj zs@PRf8eLD=#@y*xL|g2aKxxvFad1j$F$t8W`p+a#dWug%9%1m40C#KBB9Acr{SxRr z01}$5s(tZ5=fQpnbf(<#yy}!d=aGI1bROlGKxb+-*j3P(tjZ+NnR3ySkVlw-kkG7G zrO!C%Oj9qI1Ulo7OQ1954&xwN%2y@9ouhsU6eg>(tDrOGj^|@&JaneqVG`(E1c~QkXgqX2-Yssd&5IPdJ1XzAQ7$?bSt@<2)FLV| zjzzXh-0y*3v?K7_RdOKN-QP^9SlPGi!=s=*ugL{_Q4fRA2XHW;;=BaV(nelx{~e zV=pK1F7B&7oFQaZuq>wmhmd*r+!3#W_)PsD)IV^zuR8G->lZ7o^vXYR&OHAf(^> ze9fU}lS(T+zpm9BY7Z4By_^{@E!1i$PI@`}wvNa1=s`8#+sLCUc~YoYc45`r_!aK7 z^$a8X&1`WM#E1E%g~Yvq*lA%I2HvJ|GK~53bJ&Cfe}Hd{nm-8RveJePr7<#$!ARq< z(Oqd_X@g$;4Btq8J<<4Iono)-pXqMQ@G_n^OvZA>NSPgt$fu$a`pjyCzL_0Hh_o~0 z9t+Ko|0Wdol)?Tilv$oh(`XioP4Ij8%lX!h!5 zH8OL$U)3!U2~WfSQhE%hY*dHoX($UtO4#-c{FvtOr@Of<6Tj5(*^}PzGac74A@5a` z3=o3iKlcPhXwy8SKb`XSXc*3aM301&EmrCY$R=i^HfYcwbLJg6zswWMHv&VCz@NeR zBY@|E-$sgIGg-sqZ&5*VAH)8^BgDTxh5z;u_}dwuo&l%hnVY(CeI8+f#BV$T|EG*k zz2YrL;J;&x04}{@+6VqBZ6C51ZH2ZfpM>A1o!$;WegIwgQJP5U(Z)8*RTU`^$kO0BYCh)3`}$usf!d;(yH>ca zyt<*Px~jIJe&!ey26l=m&-}DR*!*-HzDhIlcoE>IXNe#`oghN|bfU=Nr;|jOpPnsp z`6=E;(e~C#dFikDWmCx_^P33DUf7b@~UKIW+PwEqRzl_Fw?~S@tA4iAu~-pa@k!$FM! z`n7C&?r^mKR)b%j)yK`)Y)vRtPqRy`)tF2=n>=<jCv6G&IKb}XLLdgauWO6;B? zX!-1>C36iM2%@E!H8`(jz7lHO&zdD8qa_|xwEe8vI!wwmjt(P}iu_ODO%T~tx+*J& zJBYIO_NEo`aVr_p=qZ6&wR}@{Ex%1p<4v_ZW^2gXK8~!Wplw~=+Pr9f=K?`3T7$-! z%p2EX)Z7_flwQeN(UX*sH{w+q8M(c=X|CVKF(ODC`@^zo;(M}d;-4JW#QFbW6T>wT zmE+g&CX!67oWfNv>TGUrU$VFpfo6(prqHaK`L*nt`NNE6#w2t+m1(w2hiVtxvy4U8 z4V7(!duAq~PQrUxvYU2aSKWtM(}J^V*Fe^$DyqhLn3{r`+D80GEt^XNtjMx*_M$GV zYzkux#nzIKhCWDHweV?Kw(unxEu3CJqpEV}eGjko$qsYi)qM4WqQFvkr>j{v+?TJ4ope5=JsCSwPkC6 z@y{f_gC_b*d0y|9ed5ILB_oM{Hkt7E5#FHbnM##_S;kJR;*Q71c_b@?h(Z4SBCVJ0vE0Dgv$f`}Y8`YX(1& zl-CUYC@HTQd?@K&Gx+tSz6Qu#le@5|EN5X)WpH5+wCtG@Y~6>@eH6c&7WB|*l_D)_ zPiQQjgL$2Yo7IIEpYBG#L5kMiDK5+_%Z~%ow^FlFWumYO9L*b23Zptm^0J~e*IP|R zYrj|K4<|j`@YyPyry0}Xl;(6`o~8+FOp((YWQz0Bqm+}r#Gi%Z8+ec7h#v!4mN@=n znWg2vQ_W)2vj8`QO^xWstgBy%f&knFI$sM`1}vOEzw%Ulek#rfI)7PNDbKftuEKeN z^S2e1kajjXS2juc_qBY_imyv~$VNe8Q-`+E{HbxN(ythgiN?L0s;#>NMSI!h~qxfce5qk_3pUDDWi>=EZSmn?;WYxq0Jn5Ge~k3kD6XZ!?b8n z27QRbcqfU^#as4sHNFJO7<@UyqrflrZ1Ma78>(_1_m zo=Wy1JV)zuGO)S!lP(8SK^Q&}FQ*KrgyAU+e}>^UhF1ftbfaQD!}P*yoYsdh4L`>g zzX8~!^(B`R6+0Qe4sUV{=Wd3-#_)3tzXGh%iVAuQgfW5GtT^FIb-J%J{s%56Dn4ZR z4OCE*?)wZE;2nsO4`;XpSfz!9Qh_n1QKn1y44v-Tj9>3^FbtaE%NS=e-U^ts>KSeT zR`Ev#y*Zeu(;_@ur!|l9H@F-up3HC?en^}6uVeTwh9745DPWaWRM3y`GjzIyYjwKc zXZ%-O4$3^k-^7<_lkN{0{td(LGn|K?qbjYaC}fy^rk<*GAbgzG;TT{u&100y!NR`` z_s4HCqeG10QNSurOkYIYbu#`2Ij~gKH7h<6GTpYOO#w3Xu>u^U8)4n0l*8qXZZ$3^ zD!YE8a86~Fo&_<2s3VQo8U9>g#fi#g1daVyLmtCFw)i^i4F4KnW4F72&%{5)PxyF= zMSMGshQ9+?anzKav67<}Yc={m%J@$LD-ISp2R3z_u;IT1Y~p{#<)|q=rf$B;_-`}* zyTGPS3FNIQ=Y&oCsZ)AP`NXB}^Nxmo39C3oe4{Imif;fL+Y%nF)1u*vne2(jsatnYOa#r?Q!lP=YfwPfS7@ zQc3kV<8gM9PePhdJl;f$2{@y8JPBzy&?g~V(EC=8L%l>A!0b(#ps6WT7MKL)%k@j3 zbb((2rSTBrS3zmghs6V>>Asi*N+0W&Kxt~l7zav|&P)QONkeby1x-yMYcL6PCViL$ zIv4vT(3w(a9Oz6jd($dtY6`{7B+!{+W)kR3F*6BtrkI%oI@6QKn~XtIQwseO=uGxu z9O!(UE8#;NQHe1y9lMl`4{Jn6J~M|6WeoJep=e1v+Q=e~HB92v-Dz5oBRLdX`c|ez zR7)Idcsc=+8Cpu^%&|sbpMG;KnnU^FSTTL(KdjfM`8f8)*{(U1AALti||Zz4guKE0abO(dYQ=xydxfRe0RXNwPU1r7JFonAe) zb5gq*?oXcvQpQxs`g@M~+Twm1@QcgUcn`l&ewkq+|3Cs3kl|A!3r+oS&VtfD@3OFr z-`oDZk@jSjR4vjBA_W-}l_44K(L|w*Cr{JvNJ>+(M9TcuG;v9rA7R*gUdP;d3;DqJ zBduk2R!PZOF}cyW_k20-{W;WWRSC_w_lLalCda*>jAkQsqXvZY zgt;seztr&A!@}@09oI3TY0OFVWhhDU-$AV;Hr1u`k8?H;8Vaw%{~>DOQ?^*CCopl4 z1kX&diCX)Vjq{&iVKaf>2LJ0iQQdX(jnh7#@jFnxEAXTkNG&fmdeG5k>`!<$?ez8? z9KT6Vjg*b^7qhUDz@LR}T6FxbK9CbW`f=J1fbPhcv$ociEben;8vm;XY9IAVR}Y{x zSUGhSRnst{yQUt?TcP~<&atqR?|d9qd*b}@$fJM~w6tPSi1rg~)9XAdhKl09ysmnB zc|%oMU42S2QjRr)d~r)*iHM~O$6+=sPqluXuZ=-fe=i()uZ1Gfk0%FYn_*SXXi&3dj%5NfVxfqo?{Q#%^a#1Tn zgRwih^{h?8Q^P!yjrQJ8_s-nvwBy(&5CIdBx~Sry1}$pvy;GTh8#`Kkgr zF1bLCOD>S(k_%{Da)BC`T%g7!7szqR1!`P!fgG1yAjc&asBy^!a$ItO9+!-x9+wQH z$0Y-qamj#cTrz+hmyDwvmy9FEC1dZ7O9qzXk_*(hCeF3{tW3)Hye0zEFd zK#fZ-(BqQfmY9~UD$wJSv7QMnTUDUPCBtPlEn8Kf$0cKh5?Z#ZK#xmC`f^+{j&fWw zj&fWwj&fWwj&fWwj&fWwj&fWwj&fWwjx;VA2RSaez#W$i2^*K3TZpz@7HKtpw!CfO z;wCJG*VZl@JbKVzs0>y8wD4?wVx`{298sUOK{G1;)!ryWD(8BnvRo+xLyyM_sz3Uk z$I_VO)$0CBgk+nOJnM2fZl=+VBF~HB1Rh16l`t1cvN_4KE}SRZL_y7LgT{HZTmbyi zD>W3%vu3MM*^W`GsoC7O?w2kgIp@1Cu=vNR7@?%cOp?0G(!voWcp811rQ z2h!N_Jha(Zao-MT(6g?)>%_!2W^|vZw7WmB6WR^Ln4YzVdM+E-ixi!m(2gW;BnS3( z0~gVVpLIpO4*(ZST->|+_ATd;Z)y4wNiWPDQFYYbj;VlV@(N51k?{)LhKk~dm&v4- z82a&yD^ZOGlFVi;S%CPlxg$$9$RQ3GfUwn`f4(!^F0hgqgz)NBqab?Ksy-d#FLIsx z*IX-ykvwLNIz8#!jlG>40qsFad(W;u{gJ#L-NNNeum)^BxX1h8NPwx zARY{cQ_S$O3=d^^D#NtWsJV6)!%YmA;-wnB=R*aF6V~r{;$^_*+RwP0sAyogBII!{ zVYr>)>lwa_;s0j%2MoW#@ZTBEL*GN`iLar+>K8DakOAKfn_`Pcfz4O9Q7#8xKp8H^ zGtb=DsSKAfJcHpY8Q#F~oeb{+R{E%~HAc6QP-?JLE!}CN;g=%ZwLjxm0GoT6>T;q$ zrgYlz*MUu1gz2X{w)n5GGx1M^ZA|=xKPf39PIF6*JxRpNv#}2yP5gv$o3zQVTqb_H zKNCM;!|~)?=hQDfpTHH~SDX@@jrK|COHZXM;jeN~Meq(6yOfQ;zCkh1%wex==)N<> zL(wWbnD_ftBud-Ns}>Y7#FN@eDEj&OD)sK3UYHQuznND;s9uPNUJ99*J>F~$$@Y## zFH+LC#ag7^?~lZp&JjjktFia~I$iIrn&Z7M_TT?LgyXI5k}C{vg!gu2TTf+(Yw^*rnPSxFP^l{|v5kg#Yj*^(9Ilsn` zaXbnCBhY#@ABI1V@u9w$N3BiD#^Ybb!l?S}I0C2(WW~03L3HYfSzhCvKNHGTC@V6uIVg304`(kACI!U^;GnqKc#ro zP}0WB^Jd1UYadQ;k$rsK4UzGz!~Rs%mEVwqO2X>k@{j(lbv=qMJ;?Bg4rc2I1)9G( zGKv3HFRd|W1ijk4y146Iq;guk{u1?pmG@KB!}rB@Oj>a(NtO2R|^ zc7$3!JL24DN1XfYh;yGEaqhDt&V6=F%v5&d8dOwPm0eU*j}bc3xIX74>rp;!>J=#C z#uK&m4e{EVG4ZKordVzRPT@AxR_HpELZ<)> z;-WGo7X!CxWcvV0Gxr7T>`2hux%_%kQ(a$QQ`t~Cy`s8ox{gr>Os<|{q?U@VdC}aK zrbV;{r~NaElVZvpj-5hhxM(6!RDNj*Yxgi=zk8T)s(YBQ=N=|(+{1Vz;~plAsibfZ z;|0j`oDg>pa~IMMdG28z#AzV*7^$`oyWAgPXZ;>K$0lKpEvyf4wAGmg$>_wD_n5(8%EYyA8JrF{2fN&A6NULkb zCQ~H8(G2EYe>Kjdw{zg-zzR?uvZ!|^f8%>e^MpLA|(G=-#G)3wgO_BaaQ>4Dp6zOj? zNMC-V!BKvr!BKvr!BKvr!BKvr!BKvr!BKvr!BKvr!I8ev;2^)z6uIAMAYtEVBIn@8 zA=Nm)?-=U-;$6N^p4HAo_I$_4z6yNDINEm%m1^}x#^JtWq}cTx<5;s6n?{hDzXtcr zu`XZOHn&+&v(z9FqFFw>r8Cjg*(_A#`UC;X<~DUUUEDGk9#N=5Hh8Cn)@=DXV7jYL zp_Opcms0nvkZCi+r%j>O<|S8~LaW&*qoUTz6k3g5;`x-QcRG-I&z6XM8^2<7p3`6* zc}LXEqaQbJX>dcbS{|CR<_AQUhtFDTGM0zcuFX@*1B!|E{ z&%pc*DhpCWvziSnvYQQe^py>+=LKnO_bijOJueN?s4jQlG0Lj* z@rIqOnl^mRZ`QQntlITU*|qCa*|%%Iu86X0hS7s$S$aWW$=oC3XCP(OzRzXXzHeu; zZ+hVzNRtID(f_Y_OF&l0I0Tc7CEH*5xXnn(s;LfU*HlB`>LPPf>(>@*l=X^ zjRDHQi`!b^se1nOwngOfv7Ua;G|jh8=LzSsK87(_UF)|v-Aahb^UE1EfunC^v7tLpPmLe;(W_D`3 zpcT+}?~@c-GuqP_J_+6E~% z7UloWa#4QKvN|&s<#uT^+1^WppIIjB{KX92ZDVe+pNfrphElW4AFf@IPnm%+TwZt8m6j1FPD2 zBg;C#x-{tUtd@pcJG(uMNw&54KU^BxOfICBhLvvq%T~ZWqgKGp|C9#8R~kw_p3*>H zxzUNKMoYn4`f(+0<3Jy*{Vlx?%xYOE&2m||)b69x(s}eP{l8V?(_8v_nd1MjrI)W+ z2Fe;P@-N0)P*%5DX42PU@5imK+aE`M&dzdv-fCNm{=;>9VPAE7g+RW4bIJv0iXY|Y=Dn8x zi@g0kH%{x?GdOwAGlP?_W88G(Q$s{dym;Hz-TNY<=QF$ay_-C%sqoGRzSwid?yhH& z$-8=HMIOI*=C-bR$(~d4dT*0{8w=sLG2CnY{I>J@i@zrGJ?VnT7!Hf z+Pt&Lpa1BT+t0Ip)?fT7*-yNjysv9u(|sFNYFEE@bgA@gysxXf{_pe15959CF`1Iy zI-cG~>n3lyYpqIe=cfEu^Y+u7!;|Fe>kmD?{_*R`yJPs!j&%>ss`>mwmtC5?et*w7 z*T1@B<3qD5w^c0PdD*r5;brn~*NxgS>xmgn439m$YiRYx9azHc zw&eHreKmRYYdt^MvCkIWcTBy$>b|R!-&^y-^MA&8^__cP*eayg%LfHKUEcLO>6Nl- z5Bx&jr{vvIeqbxb`PjYv4n4H)p^ZB(x&HMVU)wdS`!jW?IFDa*)rL|1#i8UwvmSyL zWnpL%xPJeQua=*;W7f{g=$^jRmDfaL@-GOV|CNc!YWz?AN^ToTriST^q!)bUCbAo> zM(O0~bgp~-2AR%(|Tp zYfrH<#cyA`|9W5i!6s+MlyKGFK$|n8Dm-QHMjhvljXj$l99by3yB_S^`TueECV*9x z*W36zGr2c6dnSo&Y7Dr6yKJJMCL|yz%OxPbLN@zo;mM2%Xqx5(#N#AB#or`;uTKJTI2qrM#aR}rZR@qBqpeSqOyd<=^B9~XDfVX; zVt@MaI7KO+chGe_PV+ty+79_{n-@E?tZ>!Uc3I)dYn-ye6?SvsN(i1s)Xk^MWKd1& zfXqTe26fzu3kuhinOB45?!Ml>{g%8;M|K8ChTy>5!o?!1*o?taX+R84rmd_8Pu1bA=JESsCcb|fHu8-``r*?orM^ic0ON@asiC2x;_+|9m+xw*xB*ZgPx{o zN2iAhon_NQ8FNCRVWEsF`Fj=rjX&xOI$c-*>J0fiOaA^OlyQH2B-T4Afp13r%up{* zP>Y11yh^y!7Nm#^z&I5njA8L0Lly)0V=1P}cOm;zS%8 z@nf@QsMxHTCN^u<2~bb5PYbLwv!(8}rIE`^Lsyh$U0E8rsx-8&G;3oi9u#LMCuSL< z7j`v=6U_{$M18r*Xr4AN*}N`kUZVMd`Bbi&PgP*%Qx*F2sfq%zUJv54t5%}nQg7^{ zZPp7t0-(iochn8iLR}s$)V0wiDN;q2;w&;n#MnBE+QXE%|Vz>lTa}4Jch9@z63B#)xzJ=lY z8E$8IKf|9hoQYROOu9!fJQNpEzWq0fu(8kA8i(cz3g(c>UqBf}@50vY{hFbh#-0}#euv>N8O}h*`WfR>tXaizMIVL_12*Yq75MmYhKDmep5YpXS227e!}l=! z6JTQly(BPH+f4XXUEd#N{NH&TSL|cBt0`u3XQRh)#d3z% zFisUZeZybE@J5F3XZUG`=|jWjSPD#O@SzN!!f-XPvKj3I!}Kt5q&^qI=3Ev48=aSX z99OJk_&Ua!-^b@)!SG!S?_l`%4F8qkT-^FL=^o4QD2D5RmCdeL%rHF)8>Y{NuqjI` zfsM|aJdP{A&+sw~=nUsthVNwfF@}G~@c%G;fZ;+sj4?V-2UfPZqMTuRU{k7XCT#qF zHn5pZJ;UQ*mOjJtfQ|mK7&sbS&G2f5f57lV48OqehYY7vffkQ#n+gSCx!++8yri9joGYD_*0+fz=qmiV`;bm5kryaa?f&uo;69HvEl@e~ZU)#Wr9w zb|P%}6o=c`^AnGQZ#w{+aR_0OPc((qpxGF%9SPYDDbdE-^7n8Z~bgj zmaHh@owv5(pcO5bn@m*S7^1JGLKDWakP8;&nmanMa(k6|3bO74m%u*qw}MvpJY zcQ7EQW5^!DhU3ds`)u-h2ICMm*GF@KOzsgu@@7gvaw@jSL;g{i>nW;&5>%~O zK?w@?f}jLOFAqv!^va+FMz0M@VDz;?35>ozD1p)0kObqh_YX)YE<1V5=M03+bQFuZ z4x6bRVG`I(o@Wx+Oh>VJ>ah9npaeFP9>#&qR08~X>I1dSOae#aW{t?Bshr}7@*~Dk zTy|;$m;^TCrUsY5W?X)A32dga#g2l_xcuM}*i4%9{j^|nW>5l~^MexD+%qVF&7{Zm z^bCg0q=!jhGwERx*i3qu1U8d@3Vc1<&rAZF3xXWj+$$)7%@|y2Jv`Kh4QaCIGd#Qp zn&IRe7SbcF6Ar}QJyPBbxcwYjaO*N#h+tQ znMhnrs0`e00jEbI0g@8!4$|OQR00wg6B2`JLT4Nk27^kKV-+VVfy9KeD3TlsWZYl|ut7C-uaV!oDW4z)I&=^3Iqex#&Blw$Tf zR&)G__=)9yn&$YC^%KkeJk9Z=_)~ceE-N*M+8Y{;;|G8z~~{VI}Czb-f(F`Q)GGEu+I)m4jxRDpj-{de3#jS+RDvOL7? zL(NWDO0km{zg+82=FeOs1h)czJ$VLdU0gri?lKFV?+?4-Ut$|J z-u=X}IY$X`rMAZmQg~FZvzdMh9C|aNc+ELY=`bBBFK;s$pN22#C-~_Z#Q6&ue=Z1{ zP?q=6H7S-7`KyM=lo#JTD%Yf57!1jy)6!D)zL#pAX313kp9;*CPoIjNysW;wp|)za zoRnx`Dh1zmc2HB2Syfe2U0YkX1aC4`d6=Z=ue6L%MwN*MP=!gzHH#K4UWoa4mNg4X zaGdVk0{bpRDYYWy(Q~Ja9gmMxl#iQOeoocoiRV_9kE)t{{$w=I$@h(&FlFN8azwZ4 zazDadb+Uij6a-gtI@wuv?lfGthA8EE^J^AWmDkqIx^!~g;zhIYEsDqCGb;~eE+Oe? z<*3Q!Wr)v2-`a>*?eD~gH#*;m_j@|uIV{m)UoAplr7@eMi)!j;Ro7zrs@+IFraOvO z1THO~GOns()YP$X@T7C$1Q92U;zJ%2&z*qpX2k6nJ7MyaGR)hU0270HMvp6-JO;J} zrO~p=DPs|NDo#AQZ2Z`9=ZjFBnAj60ig28`9I7WnOS%Z@f>}}1IB!->6dyd8U(>K? z-YjAF$Eg*_;8I~7Tq+z4E)|XsE*18JONC8vDW7D5ONCL05nRgOA-B^*Jh&7U?T{Z_ zsvetR9T>_#P6vk42dYR=x0(ah=6%>Kq{^25oKax{Lk0Diz))cm7%C)z(((lz>jjFE zhWLS^d_6R=7};ASBS#g<$WcWya#WFw991MEM-|D)QAHFvsz^nSDpHZ7ie%)dA{9BR zNJfq-l98i|ROF~489Ay*M~=c;M~(v0k)wc21|-j=~y|qwwoRjsljE zql#4Is3ILXsz^nSD$1Ytjw0LJP; zw}UVR@EqLA(q6$emTZxwM`&nfQN=OGdV5ptlG>EJ3_-5xFe0SoIMz2T05F9$vrRAWsh|%E_O^=_V%XQ0biuNEWc%2-?0(v zM13_HC{hvrnGl9V8(RSPEg(q#_}N zOQdj&HjAWVNO@z!Kwp7`u5~eF-tiK;2Q{IOQwhIk!CIItO`y| zUIo{fdLs*=*+3CmjheEkp=P!!17-s|R#i7pxyE&$JjB~_tx5B}dMgpgD-#PMRhfj6 zNR=f?QA9QAv@BkbQ10T&5k0Q*OG#YGL$*f|iJ2Y``5aaLs6&jGtxY0(A&HFcDa9YV zKZ)$GBTMqJ~95nlV zNx;pTmTF&yLMgAQXNJ1=We+vz%}Vd-xeS+R)}{ z)`iMh@}#CFZV8?Z-YowappzH?c%)=x}5@y*eJJ zbR>SRV@-aPw(j0hkWELge7Wtp10CUL+a@}u?YXBq=(CZ8xsB%75_zoBiVzOaLpmaR z+7Qs8Pvg7}I!7&$Hj%D8e6F&sk1hH%Cfgg@aKfIp(og1_6qI$!va;s3<;EYB*66VG z1}q=h9QzF3_^hWqD`i!A^R7)5&F!1omXY;j&6Qr5lYWiUI$DYks!o`g_Nh&@_&%k2~;Pz#E(! zCls4A&4p*ahG%-(N)o$Q+_0^eXc||H@E9}1OLtz_ukNm9YrvWtV&}*19oOO95W6sK z=co9q1SVTS6O(_Ozi~^nl+wYAFQGUCp~X&b*;~ z)0vfFoK3$yZOvy!BRGeCd#ufE&p**ozL7rr8T-87LUC&a)&mxf!tXH)M{nBp*)a?I zHJ*Fxy_>gvcI3hs{`xdV8c!O&v-zw|{Tj&*aclq0l=`;M`eFZoh3yFWp>lIxha=C* z+WARGjzu}vW6zyO-+OFZ^Y$GDc`cu3XKy|FuE#U8t>IM4w(sbX7yCRnd(5V5-b39u zIre#8_BHQih_Ra{evq-H?Rd)nvo~!)NzZ@3RNRBI-iopwgBB_g+1V#{h&N+9GPAeu z$jzRxmE@G`*^&{HHOa%JQXcE6b9;MUw$APCc`p1zCH^0%FPZR=!cH`;j$~8kV9xSel5EP` z=$l40_eV|+SXj{s_+bS$+N(>mVjXcw}yqFz$jsMxd>HHCTvs>waGN29i8?i7!RThaQ5 zi9s!;DuXS^^;YEiHr-mrbbny_i9U@Zk4@V%vU$P`WxWGWQx1{MWHDOdTgcDy%uxIL z;2cY2+r#*1--%BtH#NTRB=!@kM5oQq6<>8^)NKQAWPeL+Lp|6Qs8@X&GsR;aBb(Eu zHN|_{j_uQUBtC9TXMa|68(Mg(E2EmX;;g6-7>#Y-3-oC`5&aF>>e$pykyU@wlAiL+ zzSd_Z8Tvd&$@8S6+HYyYIhr#J>M76E=U$dsTi%>mnSP0%LodSKJDX)6jJDX6%yq0x zQZI2|aa-w#`LcHji(Ap!qohphaH_X&57lk&-?Zu8{6 z@L3&nL{xtoDXx!Rb)w_w zHWAlH_x6+OTkN!1g)2w$XjNPvT}0AxOXBp=jmo6@mO7bT>7(ambes*q)1k{RlAnt; z`Oz$N)j;yenIp4CWsc4ooq1N)Sp1y@IX|A;xgbn0<(xqyX-mxc?*x4^H#uQeimqX1 zEnM6{uY;UGZ!e`Pk$QC=G6_Gv)cK)MAz}di(ngdV=a$v@jgOu5!wACj*l9(f-hbSO zz(|dI8$t)$PEWukdu=CopR;CfsQ0pcp@Xq^WrH0ma8~SH(g2;;E+?Iztln#fEA6yg z+nI(qN`Dr6m)enoY^MMU_N}rV%UN&PVM`JU!2eMgTT8I{#v2WG*j<+9IRBefzxY+e zgUWDjYN(geGzUlT$*M;xx6el^pySY6)1j`xPV2c3R@zQ4`J20MpB*mP*I+wt{FyzP zfipX(A(Uh146?(0oZ9+*&YXI(E__fZbRcY_wzD8oUsyRZ-46?pBFwRzP4o9^Nxd}h zr}JR|JOCT=mf{o}5Ik!VMZLHaKhQ_bGooR9|nW6|8WU?QK}?H0<5C|Bcu7 zhmLTbUJX0ou3uaAp`6#2+396cMZQD%YlHBedOJN=>P^et_kkVCmF~|a5YDyJ3ql9k zS%r2e|9kjz8lc2ZJH}4ScUJ9v-C0#noDlgnbO;^c{f9W58!CjmaX_S(+)=O}N9^6_ zEZvKIK~X{0)UR6OEZ)0s-@dm(uI=Q#PTuKdACn)-b8cI`7iND58?6R;zCX|0+aO)L zYjM31?30357Vm{AUOvgmLn%(YwF=K=hBe7cb?Qt)PO^8!kiH*h?H_LLQP#%MZEBC{IH<@1h#&q;uZ@3}w94 zfO=Yw8v0f!W69F}&howc-;k31Z$P1AEe++pLALisa`msix)`z7#^QYJoU`H1{CH3P zk5Dz??}a(A#d5B$RrTQSg{mI>uy!vD3iX7>O!7vg(9VLVi$WQ%k#F*m#}n*K1cS5F zD&hl&Jw>@x2&?uk#o?iRkTOtn@$EcT72lR5=qj8>tq@A);(BK(H6tiQfJ;#6UPHlE z#TR?h6PmSOP$)4dIG<$LKWWX}N(AV+AV2SfL3qR^*2mlR?EOq}uvYJWK1rLyXNv2dQ2^ zPNTk3E;P`hg$7o%&_Ib68W_<+0|;7ZU_%QHRA`}r2`w}bp~djjmU`D6sUf~8zCta9 zuBgSjT4Nf9%+h!U!}l=!1jCD9xZy8h_z1_B4`4VAr)c<13~ylg=M4Xb;pZ9N!*DL% z0WmuF;KasD`>iP99eTKSXca!VS2^ve65r4EUoiTgr(dS zUwa%E?+O~ei#IfV&c_UA-~}ynEQRqhcqqf8fK|G#pclHTv<-ykX&c5d{w$A!@GcD3 zGR{=IwPey-#PHP&|B&Gy1FLiqwh0*T7-O-bgqs|>5q+5PpY}Mec%I=sjPq!gZ^QEp zzr*ks4CkQ27@H4g_!NfEX82NuH!yrJ!@C%Mo8f;lOd+~Vx<@fQg5fB`H4Lv}cq7Bx z7=Dc5H-MFIUGZ0j!}Ri#bTe*2G2EZw6BwqKrOuOlD@ypss$q!^0XF9{&f{RJKf|Y? z(J`DT!*dy?5MYLLE5i>k+|KYmhX2BF209v}r-b3tfR+6SC&BO{hOcCJGs8b-_}2{o zj^WoBrWac#YF`naqJ8x?u(9n6kAphSFzyI?oPRQ$kNL0W*!~QcGJFBU%NYIv!xRq8 z=y{3Zj~LFws}9P3R~*CeNet8L5R>#d5-!#4#wox?f2GH9#Z-pR!WFCGdCre{1XG(pc#zh=1lSyVi^p-rZ4BRp&dPAM0xLbPpvT1*YMq2H);jM6HvC;4#}&^o z{37E#(ZlDz%J4sdm439)dOyeT|H?3+?#rs=q;F-v3iE_hrX_kDevF?_ z0#+Oq*2L7)Qpktl4@#}#h^pNBu&X!=4VA&-}=4zbt%}2tMeky2pef5JwOFISo^CQGf{@ss>xD1CqhmItYIhtU+;xV5?U^G89|=0+Lg()juF14<3#`3h1EpoQf^d zRE9fgWCH7J46R|X|W=*^%6M!y%7!00~(B{2HKpae!Ak2>k6 zP63IA1SPPUuG1I?HqQx4U^C6dWgOUiV^9K{zaNyq=7)k3*!)OP0-JXQC9wIafP?}P z^~QPmL6io;X38%nfz6cnOahx{LgEKe8U(`fpaeEI2PLri2SEvJzB4F+%?|`6uz6QN zLIH_>6O_Q_mx2=5{83N>oBtM+z-9;D@Xul}Y|aPA5A!q_HWvjYu$kI@#(~YHK?!W8 zvg&h&z~(|o{NPYSU~>*6eo&_&u$eea0-FyCN?>!JpaeD_5|qGZ3T?vlz~+*m1U4TP zl)&a=0+OMy`S_p&HbclX4~5N0j!R(k=|Kr>9vPItW;%C2Sk+J{!9^gKz~%v-ghzX@ zA*FnaUwDKEr!x+V>Od`EGCibM_mXIzh(pZ81l7?+v&cBasQw( z<&a~IW_x`2iH4MCjzwiO(Pk4Zfjr|_R38!-8Y$93wXQRpO_YNI$)Pw0htVN{#YEm9 zuQ(RP-ncukpEgYN1FB<=MQv{4LL*CBsLngqT>O^cFSzI+@@NlD0H8!)o4`*Ik3)GM zTz;a{l7WQeF1*wx7eD-vxwGmYxkqy{Jk3;Mg3E`R>p>gIlD!l~aaB^3!FNNcEB+HhL%rEd9pxCtqwj)|L25~tCd*4O1h`W5kbP6OoX zt?A$%@4eszaqunbgxv`*3nwuA6ld4WTzp9tz6D<+bd02V3+B`rTs?E{6ALYyg!v59H)wytL+r2cg@bxm;#wSLqN%Uq1x zw=fC6M00qLXAVooFExDD`x$<+brTcv9&$aJVA3BxSP^d1JYzp?5;jW@fG-o93{g^M z7{P#e)G{AM2gNNVrM_T{59PJTxNi8f8K0;tlku57bbrPy)RS&Y#xFGtA#U}d?45UZ z!~Z$slm0#3@J(+_hq?Ispd0?@ti1gN{LG%XChA8=`+XUYA@p~(Oa9V*xi7*0-Qh~u zTkqrfo5%Ez0-k3`Ob_QD%J|d3`7wsCwjN&5NR}4E|K>4-u0%;x6(cQ_qIZX=IhZBQ z`+q8ckVQAQtju$x(W;8^WmV;4$|g)0HLhwbN=m$J5(ahYT39}pK4xAk?9*_#OFA-E zduW}9nmu%zhgv*DBOZ&s9jDTtGN!U>^4JSTRSg|H^86{Iv<05@hkrD0`{A65!pL`jgC!*u?M1t{oBJuHgB7S_Hh>6eRlT3V`h>FkS?@;l1(s_Iy z3bvl^$LDzwn`tHFWA_vMWPDDDHZ$__hLkJFKR3S{J-0vWldKt}Ee*g{ zBHMl%l2}!pF;d#~3`*5JP}Q@IlXF04R@c|4W>F&Bx(MY}w)E7-SD6jly11U&S87?S zB+9ccl1I=d`l=+#L#Pma>{@$Le_3jszbSc{@6`DSl0k81s7tKUIM13f%Zu|O#}oc$ z*ZaE2xQF91PN!AH(k-MxGG+}=#jQKaym|G0g^1QHm_2X7C6sr#D+St}R4F@Sr8EQY zNNol_k~{;GH(FgbQS>~;Yu*a!zABvi6z+M(yRB?i!@R~Ca;?0+OYU1uN~vpirq;E; z`;WQyPVQRt3c57QLaA{f-Ry?LkHF1gzbT@?=;u`<3hDgnMVCsC%hD{z*PXFa>hd>I z>+-+-$6UUhyIhy%oZq6!Ah#{TsHSr1`1(sK%f?Hu(k%qlzz24v)RhNP>&iS!`f}0I zk=}qtV+?7k7cHt@Cg|#+NS*irwlit6cUauLF1EgHlrEtwtWx?Y*(?`7t9d{1aJRR!&Nq%;myfZ!xkcmGD>r2t{I-(v3^Jseg zS0+yScP8ca7@h@VhM}E#VpUlyOYhP7BQM8H~9(7eIb}*v<^> z_^rU6Mc8wOv*ySF74p|vb^5e;1s#~(6PM0>nNBF6?hep0=7#M^K)O>)(*x2sl5)Q! zgDxV2MxSw}v-XrG5k-4si+zMgc#0ZIG^Ez7(SEX2@FqWcpAfF z@Q#RjEM-LruR>m8iH-#}Hq>|=luw2y;D(^#%wl*c!|NITA;Ujq_;FxmgDdDJqk3d& zMG5PVg++HU{(g_+inkeV$Ae*G&pw7fVc5#>IXxIYmSLLHrEI_)0ATe9&WaM=q5X3@ zdIxq@y~sds&>DB72KV|q=z{&jPnv+-7@yP$M8QH z&d1fc;S>X_bX`GL?T2a`2vZx1C3+;|(>yN4am5)7ABIlZ=p4*2b=F2cgW*PouVHu# z!;dih6vHn98yo0inC^dKoE9bgQ*ATN%QEu~{>S6E;x7!pj84wj_5s6RGhBpgH^VuG z;WHVY!ti$(UcvBMU}dLzm)+RhAC~JrIbn{9;g^DA+C9RCUjb~+ag4`N@06Q%X&U4u z_`?#t2tS5D1K6}1OMy+k6E^zkoe9Hl@;GWvi>bdiF#blyzXjOTwQazvoLf=CM*n?` z{}YdcPi+I6xCwcOquh5-(bph4L z^BduaKGv73xgW-FlqZHm*z}<#z{YQc4ab+O`eOXnpK%BqznuhZ{6^U5@#SjnhdRf^ z&s;0Hnh$3DR?74cHhvoeZ2U&pq~*)G-^`qiBk-Z%lfg#kf$MNHM`9qh=r)lr8HBA2 z{Q0vu24jo->Pv=T3mqX+HhP9?jxRX{5=zUT*D(xRl$I|!6Eb7D;cvz{*q4;U z-iD)Eo{U3k$)mK8-JN~FR<-=W{7pj z=qF`HgR-XBGTlTDJq)LXO0VK1`jOt2qJ?UT;w0vo97bLQj9hk}dC58Prn7#bn06$4H6mfR|1gs43_M<7$0U1r*~xDGWR2}r52b_8 ziV}7QpKAYmABUxrPiASSuY<@P!5j2a6mWx-Bzv$fckuM|sY|)a1m)VS;Ap}9hk{s+IW1Rqi-gT>fS_(b~A3-w<0jb_VV zmz4Ur!iTaSxvU%h1&mMa>UG`l`EELu?OdRBaeLM={d9VdcEi7m@#%aY>xTbR#;2C- z>2CPD8K3&n*Sq0=#Q0|cpSXkxH00;o!FE#_+|dpHVBL<=VTa)F`EK|_8K0^`Xek{T zT(~`x8J|X@2Y17#Uezp=zvp+uzk>0p{M2;AH~kN#LHxDd@bwix(Ix-RZusrY9NgPJeDeW&N}cRE zu^ayPn0{)PhIhl?%=o1L!fyCKV*De(zoZ*Jy~Au4x^lR`8~%RAC;fZ7;afC_*UQOR z_g!wb{B=pGkNYt`2Ag7SH~dn@-wJ+fH~i_0Pv`sb3O{XwxIOi8{GMhIZ^&44{?&}1 zhJ9t-@b6;$%=4gV3wr}pR0ZurkJ{xI@6o?N#8v(1m`NoT3-%k3Q~3|Iv(3_2r-4@Jkt=u8$6;PzZ4gx4)Y4dw@5n8~$3x zKOX$5ZuoaF{^8*Nyc_<{82<$DJG$ZTVf>!pU$_Q8aSK1+KQlg^@73M#GwH%lFTJpS zxEub_j6WRwce~+_X8c3Jzpx2EaSOM97UNTUcym)68JnEHnDNiRzB{|&Z({tTz(4dd z{KPF>|09gw7rc4h@Lytlx+}K58~&deAH!SmRyX_{a*AHg!TN#knJs_K?LUt3sXm^y z*5?_-`4x;$@Z4_r=QBPPz3OiG6wcZ#bn5fE;a|b7U$)`cdhq|M+n=wrB0g(wEz^G* z2Dk^W7vk5u6mh5FV@+dCT5e_h@fOZ^qmuJqetm(+=-xu<-gPtD+ZUDSalOaz%V@wn zWvsCJVI3-~udkUulRhFI>6w|HZ8zEW_wZtyZ9ie#_ao~ad32hSsyD}Qc{xia@&DAU zxg0qcDx~K^g@SXTLh*Bc6BjDgRtK@Xv(Pi9bW(~zv*~0~ zYV!na+9hY=H+KSl!W6YImo~!}<3}cFW>5w7ni*8;6X?QD3wblB)KPjfEzLg;QzPix z=eaZ}4e!Jc-q|Y~hu=wMWAIxUB|JGwc=qHderu*p!7t`g<*B(;d1@|Io}5dSr{+@S z$+=W{axPV#noE@@=ThbAxl~x|xl}-UE)|fOO9iOrQUS=hR9MToR9Is!6@IzQShr(iV;n^^0)R9MToR9MToR9MToR9MToR9MToR9MToR9MToR9Mqo zDy-yOsyuHl6(npfRn`_XT2<#x9yxZw?3$(L(L1cNAvg@bRdMo^wm#ES_S&j!+}2ww zEi1Zs-k^cRdC`*YV-BdHXvgQ(>#AKi~5>0)5 z(o>^0v9p18%1N)@KDm``&7eKfwpjt&vaL$m;~C=Z^(5KW#l&D%cpN6nwq_DbS>h4Y zX0}yB`=lk_E^XHoPj}o23%3|$#1ffLqQCS?N+n)fmj#F}Amlj)ccrup-Im%i^x}WF z4E>A6L>6wZPn`vuD)UN;`)U(3sf1Q@e-yq1b3vgguI#B67rF?y7N{>x+!TLcWJb1iO6saXtg&g zYiOc6Ep%tkbCMFL)I}n769{BWT!0A#ojb|G4Asf>$!kFahboP;t&6A`O4>X|HRnmj zckwaO2l6Gi`I?nGzhaAysxBAx;DhINyX^ZP;&NG!tLX7hlEj1#E zvaKl%oRg2VBX1M*OQzOIi z*eTEhc%yUdmv76NR!R2|-u{$2_4yP#^^aXTH5Gk;?04~rVm#*HeSqgqayQ-PHSSiO zfVVrP-u^tr-i|n372$u|+w%G{d5=pE571=LtJ%EC@Z3q>mN}Bp8+eqIdc4?4ZLct} zOOJQeXvkqqCoQ;(i)M1`%HGng##O9`rH2V#I~=z^r4C)0Vu#+|r9({-HfQXQ8$F4> zpXP0QV?~Ctm!v zIf2ZQ_f}QQ;f+$%W>-~1wl~I~B3TB?9yfW5L~kZq?&0(+B58QIj7&smS)(pK59#T! z%)?GNDb2#SQ=El|r+t(Dz_=z!W%|F9g);Np(^VE8jpq?@^{}G4p?XT)C70Byn>zG@ zQ9?CjoRnta@U+x+Fjs%;EW~X!<_vXjjS2qkEbji{M3g72Zql)Y^<#;owOBXNjO{fa zOy-`XipYBlUs=vz_GD8ni-@JZ-ZYis@5c2sA% zrYI@Ry24Ou8{~6B|F`jzWp>m6PCx^q{`_sr2lRUIc?#V_8`uFaWu2|OvpR`O^3 zb-Ui5Qnxwb)b>q#!`AXH9UO^D8=$6rt#HFqt(l5>+nX8M`AM2RO*0zXJy>qQ@gssuy7@rI(ziJ5CO|d~VXoodem;;XSN*^+?xG z)RX8d3vb&?#*^UT2btq-Cu7JLqmn+RkuP0&C*jpsPeKo1pq)9)<1m@FGTv1lHGYSF z9W2gO9z9O3ub`4%UAcEr1rU*kG1WjdD8_VE2}~0{*VGd>`1Tnottr{*sjVs3rFZ!> z@0-6BC^K}{r8Nz~cea9JQ>{{1o;!a_ru*x3S)YOyd&Md!?y^)-Kj6-jLybxp)t*ky0NfO;7(2fRMalc3qDB?|e(3?@Am7lQa5LkzZK#F7$F=1NNP z*L9}SzNE!Oc7>ivUc2H+vaJhD(#A%Q#BDUU3ynbmk~C2l_@rH4e*7El@`hl7R9+<~ zNaYP?_Y_qG`wWdMf~H-gd602MFy#$eONxu&?udog;AATyGuJCUatmcbj_SO;^mcm^ zyws_xH7kOwp<+_6F*6w)q?tm<8VN5o)82JHV(Y#TPE9bAwL#2Gj2u0tv?)mYR|=wh zVZMk;4J&a{h#R7bLR`||!PY?f6_LX*s}~KS@iToFL|)&Rq1$kx(Irk&MoOE-l8n?g zi<2_GZ6~Wocgkb_^@H9vY&K&qw?^vkuneYGXS266lO?fVlqNXb8$$WlO{!vBejj?RVlcp!N zCTT?FW0hf3mPRjasGPmbn=9-ITzO$D(jOn4P&g*n=$XN?1x{8vBqOE8|W}+&?Zpcl1OOsy5z> zbS(4q?v&=upzPH4TxWEdHztV1HE23?!KFtz=3cbC^<_$|*^yFrOii&nmUih5JQi6= zHv+xJ!0RDB2`F-E40*%v!{rus$#6rRbO*9YPujP4|D0d;?J^Os@se9zJvdYMSVa2J zXdrLRofVn4^88rFr~IzUwJFZu`~Fk;+es$Mj7XY^-QPUv;vTcS9VQ~ZD!r^4vv?-u zu&IfG32SU$N-N{86lc~K+28h}OV>DA7reSEw@?}7`*5A)i*=};+p zyVRzh)|USCYg8^*gZe{M($ZXjk~9dV)Ng4hW>Pl zUGmB|a>-5SbC;O1kgTwneJL#`@21!(fB7a(N#AvWbjs*O)$?m6ES^8JMozXMr^pE} zW+)uDKc$X2kYdMV|*`bqn-e3v!wt<1le|N}bjx zH?`xHB!%`VXe7GO1rvGh;zHSIsMsY-dUxdq#>KJE?2Oc7N^tZEh2}YRX&s z&WokT$JfoSN$PF0Bc-0cD#f0@txHeqn+8dSYT8MW`Wezm=B5X|qd2!3lTOupGle|&ZQrT%Rvx#h~h zh$6DGT4oyEzobG;O>}VNETt*UppR3WLI3PBgUon&?M&$iyyB7Q2O~_W8?y6K+e7ut z>#AEfZdgA{x&gg&q8p4brEWMX#cmk*jok3iZ0UyRnDe7`OKKKPoHHj_Gx&~_x?^OD z-7&sPcXZL{%X!EmvJXuLZUuY(SRno6O`B)(l)7npirqBt-*uB3Kt#Te$#QU$=^NGC zQss4v5i3>CpU;Nl0`CIHaZ>8OH7R!Aja|C$U+E*sWqwyCJ&13ucYZfd-aa>O_aEYV z5`C;vc-Yz-H7 zTdcJ>^Nn4*emgC8MeNE8I^NB_4;)GvscheV+L;|~&ph`mZMPL~zc+Rop=li-%!qA& zZw6U)b6aeSv}HZnqRx`ras!L&){Yydb);9{y|$$}>-F}hwms86qNQ0}7fFkavFtHZH|EgRn6%hfwWW`1zPRJF zCtAW)&}B_(`&Cd|rqtH)7kH{e>U_c1DFQmxmdqXGjV<#vwqEAvXs6bqd>iG|3arKE zZT&?P&vjKU{@IaMM<^|>OsKto*Lx#!uiJ4Ma(RX<6D`FR;ZU{Pu@(}iPHeEP*tVAR z*m^2!`(;^6WVD2>sdtMKd3+yyG70QH`54S<-0PDL5BEu9@_$0U~Nf~tPd68(d}6?V%wCDT9LnPPi=dFY7d>Wmaio_$_Vn4B;-3BzpfSKpykE3 z)5GHKb+PrM+bdvqW_2tUs%{NC)s}77*>+2@T_<+NVnvXJknx~~-L#lFEmD-TDGz4Btx@U=QC3ZY`AL`whwb8Z-TgSDZePwLR zTkug!^Ojg_Tw3k+{!PNE+ur{P5j*YPW2v6CY>i#Ny_azA#dMiiEU&txLs;AMBDA)* z=Vi`_opw?*To*g7BBw!s?N zg!0~+L*=|Rd*gCQ%38yvQIY{yq|c9)w}wmPb{cY~f0WuB^2~rbrCsK(r#(w*NBg6+ zmu_6n_4^w0J&i?LBl)tmxd2-8@!k#LHnMNrj;Sq8znt3gL~Oe%N63W{JFleDgAy1X z-Bz&`g@J0Yje>upuN3* zJM6UV`|`roREO^o?Q6ny3Xvzb&^hCbcRaY`-W_*E4#cjR+CD8j<$IM^#>VH*kKJnx zn6fW5Qg$&nqSam<)s z(^2aV?EIec@Qw#tieu}~-in$YhNVw!Ya%PR`&KrGw3XH3fUPxa9{B~ z*WZ0jG&})T=1D8(Xgh4O61@tgHtUgGY2)l9`({2eu*2H4eKHbo=4=Bhj_mF;uI`qpB!lG_SqP)mkAC>61?g88bKg0Hr<>Rd0ZGl=p(j5^)X zaWDQd$zKD`>Y!e&r5HWe$!#NI_?9AC-?bNX#J2oo>K5yPsax#rQcp|qnD$+}w!Dy5 zEo`ed@^XtcpsZs%&NsFetyJ~p&6n+`9{;Nu!lv?3(SAWkYgqLfEyYe?#e<7duHyJI=Yajb!LUtxfA%!tHtX-1atVb=!Y!v?CX*+jm{|#^sw@q;}{=xs7ep zJkw<++?t9-423YI*!^L*~9c& z!H!E)+){HCm1||?$sHIs9iL|ppL%Wwd84Rf6v}`#KwK9^kJs+Nxxs2KYf`e2hZ~;k`~N9@5bX2L#7O4Vr2XES zPq+1XNcVlzGf|t?oBEBC*1RmVX1s6uVMkLG?XQ&Smg~6}J4$7qd2QKqDt)8tAgwDS zpsOT`vdZ-2N7J!wbj(n7sh#@b)^HBS2|t(eac`N)lHlJ_>j{;MS%LtiRxoYs+sdR*%DXsA=Nk5p+kZ9WkeDD8r@ zmv*K-*q0^Oj*{kSC*PKOBcRxpiuSYMy;0Te+fudtO-G&YB7-_sz-J zrenSvC#TtWB*&|YGK@Y}a-q_Om!pSsm0%X?Vw-551_AWP@2K zh>W*i>s?-3xN4-YF5utJ>aZyTQRw6T$=3SE#mReUd3^rSY%H>8KGxhnG>6Z#vs(Fw zmx&Yf{)w5Rvhc=4puEtGc{+At=IE^WHmNf^NH-lb4QqZr6z7EGE8^tzbdltEG9KXb zvd`_M&j1kr!pyPKUY^ELdf%KlU46B@I!=DDmS2c9_ZiK9qBLZgvgb&r@pP!Yqy07j zmv@%O{9HJ{v$9Ti=t=)5tcRkJcSJpqWr=w?_{CZ-R%)kU$}~dMC5e#byk49W3iS-z z>12i{{WVE@gfVdD(#?lJ`T-7F(ijS@31zHwR@xyeY=;7@7OgRO?AF6nI(C42)uE6U z$ESWr7}CpZCpX@J^&#x|i?hN`v+T5jP=+1uDK|nP+c^lEA=->2ShOw;huKbEsJF9b ze<-ws){UWz&sI1q8f~Yi?G%!>96KF4oTZJSoYkO*NqT@a8z%?}B>z4_o| zY5XXu^y#G1cauv0)CYQPr_a02^8F|q@mcXPmD%3$(x+fQ3Qch+<0EGo3Yi@_G?ejH zDCb?&kuXYR@NBO~63Nc?!E~84v@EqVT{{bTlofEtFC#f9sG-3~AiF4(`KM6E3M%!r zb~e%oX6KfJd|hd7*vRb+tg-NjdQrod4 zj;nN+Qf3`&hYD8ES@(99p-qD*+$TPPck`voVAh}QoIIytKYqiu8!+N_s&sbv5Zj4U zmv)%5V*iSGmD^mRN1*Z(J3HT5w4Z)gH7=vS_^ki1fVhqu%J?5=schwfUfD^lv+bZY z4Yny?QEPg&baSu}Hc^voI|rjdUxbVcg)Waj^oJQrWhmo4-LM9e+@@S!LZvXhz|Jfp z$LGO~p?qi#_fn@EZ1P`5u|$J-Gzcg_mNP>py@`CE2U(~vl!d%N1qfw1tILnBRM3c}P1ySG9IQR|IXBj>}A`)5$ES<@(K@6Z8VP~(g07vy4e#lb<=Yg!uY z)iz~;`$2q$Kd7bD{L=$OQKFuVVNXj0}9g#B}rzk{j(`A-C!MyJQkfSii zXB{A&>-th$ez~;eT2~Vm*%%1Rv9Nr5T#k+LF-5h|@SYaB9YKrPR(!ZniRI@N3DWHu zTFz1{`H@S4<`M+XmkV9m(qi-({qbwFpKfo^LYLgM7@pbR*_tjvX)*ihHUTY0kJ+YM z1hmjC0b1x504;_`mou~+r&hw)KTL0%^P@{=TIdpz7ULgd2l<;8v!5<)X`xG5TIiCM z7P>s8#atfJB_=I&NlA-2AG&0u1UH;KRmwU9}YECZ39&@}oFS;z_i;~+> z;)UcznJaI(SsLGowWIO<4DV)mKf@n0{J#ump&%JOy%`?P@YxJU89tZc3mC3qcs9e2 zGu+1T#W>k#<;h!7!XvQ{OSB5u*tW>yxT2BabKy9{X<+yV3_r&3?-~A-;XF9n=o!TD z6o%^e`dsd0{D(Y_D;{O|F~<1;3W~AkXAHm2@BxNZ^*F9*W%xeExgI^D zv0)p-j{+juFv_1;V?P_b8KIRPX<->v3FhKEq|`$PH&Y!%G>yiQ%olH_NnKL0<>o zpwlIMo<84u8UIO-NYeg5GLk7Brn;YMJUt}E!H(vN8y2)An+Rx$o<9tZsz!`CCWqOtQw3_s8C z2MmWX7&81L86EBj3{S#9&~O$qd;`PV8Gf4K z4;cOju(H7w2NSX@SDKO23NcX z{HdVDiV}W6+w(rKvA+XYaa`f__3?+mhLh3H#{(FyV0b3Omoa=Ju+dMS9{mK?kUfMS z)AroL_z!y=^bri-g9`^^PaDJUFx?FFDHBeH(03ER*7^z0 z)%sf*|K}bDV-<$)INI0$ONRF{{5OUp{Y_e~pidBX=yVAmtJBQ`HhI+75y$!Z$1;3AusUB?(0BDd*XK@ns;$m_2IH^vIId`7_|oHj z{p%Tikm27m{5OVs;o{un<4}gDFua1{A2NJDu(H_|^u@EkYx@abr0su%@%MNfSNx9Q zU!CaN@Fv5NlYIFJ3{PNqA;Z@*d>_NFF#ILMStlEtT|wX0dS2U4c&)a-0ND8FXpiHH zV;RmH=yOhBcnZVI8Q#qB!wkR7@IM$nbdaxq1j82rE1O-hh~ae%U(YaoCUGW9OxkG(< z5ySKmq4)JU5>}7CMf6}`bB?EY9E_0|KI#;oGm7Ck3}40Yc7~r}_ydL`!+f2+ft78p zpwG;_t?eZIkZxB?82?m{(L3ori_j9IIbAW@C3#g zbcWBbWOyON*D&0|a2vyaWcX`_4>{AMu(9WSkK>Bz z44*a9=geXFa)$3>_+em`mMbXM{p&hi!iU-_-CqKmbYJ#3uJ}E}uQATA%6) zcZJUx#PB4B>lnV8;jIim!SEhnWxp#Za{R0MTnN9feYltLKlM1S_?+P{8RyMWzMXh8 z-SflYqkTM*;Ta6CWw?dmp93q~TtPw1pVoE~-m2|8evIMQ8U71!Os4A! z3MbvFZ6JJyw&CxH~eSQhU zCjl#aTtN|JAJw)I{-d_-6viL#aa=Kp;h~d!{pT{=!0-(WZ)f;vhTmt{uJm;l04v*E zLE%$>uI(gj?osq+{1ZKnD+Vz!%t1|Id3z3fZ^Wf`kVp456QG#LGdfM>vRbps?$A*@z3@+u9(2^ zDN}u&qk)wkS5UOZA8DP057RowGyYtU0@$u+r}eidc7*PK$80PU|Vgf79c*;vI&cyU^GF4#QtD zTy&Ao=?kpV!dMjeWt}eJMLOO7j6dAtxZ+HPD;Vd<>AwC7hG#O|#PChPDqZ9S@O9b- z!bfTwHZy+AyX$(+F%hD}g@} zv{+HX>6YAxt^zhXuk|>txPjpXGkwk~V5P?u6lm#ct&_0Pc{$_X*lQIo+Mkvr`b>A)LfO0)eF8-60Hi(|L5XLyp}|2naTv zbSG&H-I;!b=%6-c#UbAM~^ zwf0_Bb*iKH`!avr`o44OS8M%h?X`C8+O=w*+I0w@&3@jj`0w+a*xaS?4MV}^`xO2N zu(KH(dL7X9Y@hHlw*PU(|B~m#=Bo|o;!eV z#E05*2fl^B7FhV*z>b5lT;Mn1Lwv%*M|b7^QM`4)~q;5T9^~AnN~@_!9o}z>X7}TD0qT5d(a}Vt)>>@aKC@Y)ZiIVLoBu zFID{Io)epP;M8 zjE4iipZSDK7Mt=7z{0=Db8vitKgfK-V*f+H!aw9WIKIGlGoP^VKdbm(@Ejap;Cq-) zSolvX{xhC~;|qL{`Gkf4OT~ZQb7K2&<6-8TLf}^ci~qI2j)UAA_+I7{7W)eozvMZw zsRwqsUsNV6{AR^(_ng>t1G~H~Dianyjg5&vWzUJtRlpChKZJ!(&$bDFm*>Q0AMnSR zPq<{UDPO1f`#lHaQNVJICM@>vQ2Y;gPHa93{7JS?SnPjX@gMXY9ADs1F`uy5e_HXM z@f;jq;Lk9h@Is4m{wn_So)ep@qWsnzl?jXeT41T4Ii3@ng}|R@`-FvGQv9W!6Psq> zhnY`!Is4PD_!oFiY_0(QBJ&B0{i}e*pCQkQ%_Q(+%qJ}TeTsjb=fvi%z>hPZu<&nD z{98RIHXj213iAmI|B&L}=Q*+YEU>%wMP z|BdYv7XE(4zrk~2b1SgqMTCX_Ud6w|b7FHJ@ORigVc~yN@jvc4v3V5uS>_WK{+AX1 zNzXz31OEr}370H3R$zyw;@n$QI%3sG??0gg0$zyxoNUr`<#i6{{$zxlWlAlw(ik&|LJ2`&Sk0jrY z%7jmW4oi7~m&fKD;I~_GR3_YJu_@E@J5Cg;nUckJzkFcCg2Y;hp-&eo4p)kXux+fhp=!S@bcJDUUUz02#Y`8 z_HsP?3Ve_`gvFm+8-S+!eXc7<+y(VzLzE*HcH1M;`A>7QI&v|)lehvH| z%ptsyIluLC%yF0@Ia^dF+{2vny&U75z&~U=gimMA-+Os%J^=hv<`6D1=WZ{L%@=@w z#vH=<*_4*@7ri_-vuZ=$Mfhyy%=L2oZUy`cE04;Ar5(~7A}7Z)A;7<44&hd|)8pl_ z`5(Z)VGdzAzuxHOvH39YZ<#~*9JccjFGt@C`~q_b%Q;B%jGR0+{|i|1CBm;`JHPYt z*o@5#ITGOs=8SuJY<>j%2QG`S#Qsw+M=l5aN9GU~&L6!T&z;T+`43^?#9of;Ah6^- zgoU%r%VS##x)CgH-k*$@&WGfBE04;A5hg7bJ2~zVAh^+rqcUOP1UbgdAb%5c2n&a> zlgGCIcr&)CA6SlW;ShFmY*ie>PL8}6SaKf1VkgKk)(81*_)uAd zg%jj%y!UqI>`@%TPL93{_)g{!7CS+Xz8!MOc?b(9$lX}+2caW>Zo;>42s=5h*T8q< zLma}w337}e737DB0uEu} z1i2fdzLz-MM;{0*IS*m66XdwpgZ!WIp|S`IC&=CS_5;j$N^uA~Ir3rPk1>a^ z*a>pnCqn)|nL}7Ogq_@tjZ4n+oZ=96^4L5N{3(3MXToA9$k8uB{u!cxLs&RLj{YPH zIS*ms1i2e~mz<|oaR@s(?oWXq=CTNjoghd51Nj%3Ls&RL?#AsOXHH3R2s=6YAK$7C&lycAuOCAcfU2b+y?!R;t+On^gqCo^AHw0L5}_h@@Kg$ z!omr1_dA8;Jo^=gu#=}ye|dp9Pbm&zCwKSbzhllbibL4R(fz3>s{5Ef35gM-E8JjVPP9Ln35B_u7_nu*UmZ>JSo#0!!(Y^_a5+Ob7t&G&n)wp;Xe3Ms3h-o0C5 zL6E@d+2AP&oTeyF2pl*~mX!p~5a-0efz!lM5;#2rl9K}mPE%Y;0;h>{O5nh0;si+} ze5SHWp3}%aD+zq2@lz#%&x?~1_)Pa&iUXf1_Qk<6e4d|_z~_08ED0R=JO`4O1POem z*n^}AKG!8B@R=+t4tzc(DS^*tCMEEBc~SzOS0yFzncC=5?@tqaCJ&VaJ|73knSleJ z7bGOj@Oed20-tGgBka`-pFz_S_zaqsz~?KH68Jojl)&fhNeO(uF)4x1Hzg(T`R0VA z1@Dy)PDC{BfBg)hAoQBd1(5&-K9t$3jWqGxY#U0-xzjY4WPCuN&=r3Bqi{f?&lQ;K2wja zB=Gs%qy#=wSuLR~_)KLf34A^wDdBo<4SR7t2gz#qOg&PY=d6a$bWD|m>$yE};4>V+ z9j>&o)$p0@tO*kMOf5l4u*=e<1U~;wQUagp=v)x&z-Kz{LDEoPZ|!JFgFOfT#_!co z-)Q?oEori&v|7?^_qtH+)nfP3l2*IdOBJWhwmL0ow{1*IR@+}Dlmr*cixGvEG}sqq zYe}QQBc};YlNnA)n(eizBly$Mg6n`WTGDFII4xTBn81v0_Bm+U&BIMU+qE*|~{1bY>PKs)6is7mMf$k>~Tr znL}5aVno)m%Tp|(p0tSnny9q=f`xQu7NZT7D4d|oT9Zx zP7q^Nj3~P7(#IUSiWH+WvII!Rm_xllUOnH)oCTIs`FP#I9O@JEj_Cu;q5dw9^B8kZ zn#P|WGKc!RVnj8NUH;6RQ=rN#>qKrcbZyRyy@@$=#meKnf;n`g@;D>Rp}sYb^G4>- z6{{G{$9H!5C+5)6%(L?m=9Dalt^wKQOUzjeRWYKYmR-KjoFz~dqsn$7>Qt~$pID4= zF{`jFVGda+M${U!O9yi(cPU19X9K=L4Sko3R~ zMVDQ^$sD9X;85?8U4G3RBu2SD&#HF&Ayop0dYJ68j5+pbMr*PJNY*n4=@jhHS)X0D zGv|D$^3LTc=1?ic=)$ZKNZ!qy3oM7uj_mRY=1~4ujOeV-F5h4dl~RnT$IC9iX3k5Y zDn`4q1W4xcWxvC6US5%NE^|69r*d0e%bbfWhc{BzE@N?*uR=)<{%OoE-Ig;SHa?#uVCzBV z%thu|uvW4;$JdxM$8)l|%a55u*}JoIR;H{MnL{H~jziujm)U%XN}jVcNx;@3=Fr%M zvy<)XTbV=mo{p34J9?Qz<2H_yEo+oH3q6N}P+sk4PQB-3`?A}aLwBsMtZYB^QRdLt zm*Zq}j>nm^z;m*B(lgAVaS3N9dkuSzIdtFTIN5XcMdr}BgyUqdPqS-XMO@@L+4{l1 zR@sH_g`J&j-@1}Ht2`&0mvl0R?sJ`;>@mHRIdre*INAPXlsPmG={VUsypB0EuH`s) zt0V5}wb#l3fIp=#$wtgO94&7}zJK4VMtIS#JIobZ@JIq<_Ioa#M^UR@f z+Pv70Fo(vd^EfBa4HK4?p2LmBiS759%sI|;viAmSm~)!vWb3DoIWz|A{K>ZG9n7Ke z4adn|Q(woN<2@%^);}<(#&fc9-NBrho|Cn6h&eN+;XKG38jW{8XYawj#+)-eCtKEc znbYMt+3VBKnL{I-d3E>)=3w3fbF%k)^SSG%F=}Tgn~Set&gq_$_4z{P)Oij!I@Nyq znL}euuB>ccGRB;fJSSV$jm)9n3!I(o`Tic}(0HcfP^Oq%4l`$w=Vbe+&oF1U=VaT@ z)=}WKh^z%$!co$@<*HoaLUA zZDZ@1bE@ZLkHwYDp%G5!Pcnyo2lV|L8>U{qp=ab3TQ4^Q1NbNUjiW=u`z{?HnH*Nz zy~Be;#tu!LPn>f1W#zGJhsQUMRub;mp`@GpH}nlpOpJ_;_74B;)bPY)QnzVrXjn=lqq@n+VS;+Q@bZ!9porE(5yCZuiPC_S35>_rVOPT3B}SqwXJh#XuK~| z0j$VYp&VLQHI=GB7;7=Q+CR2)=k9ccYeMJtSEsxbZN(5OJ4@1}r|ZWDuNlT!ux&W4 z*tmZ4`rT6#yQI|Axf;%t^P!yglpipX^-e;}G%rz<2e-d^c(QA33g>3x z& z!&+9DZTevPwly@oZEEMh?vYWPYz~i%?idq1xNY0`@Ls<)J~+B_c*3~G%)LL#v^{)6 zDD`ToDjw9cRAYi~d8vMd2qY3)Qja9pGS^kOW0T%TA6L<#N99(hEv3#Jt)hbM86g(< zN-7<>i2LN)Ap)sn+D=!3jhN1U*Qqc?4j^sn7^wwl8Fv6$wAPiCHi`XuT@*qS|eQkLC5;+tw!#Ph{(>g?i^k;Lo)T}^2-o1T!AJkXVgoPj$7 z-P*{MTpp#bkRsG&h(yYnG*j{bqN%)!HsPEP+pCaWkq$1oR+RS0@4@vUbx7XIsmKP{ z6>-km)yE`s)?S5pbpYOrgpFidLxz?-Ik@?%HslV9&0IEKY|9F5Kn^e0wrVF7sc6%Q zBSk1ap=G+gq$<1uCl*~#h^%~0lA%Dv+qq{WYU&zIB6dz^N(m3B3$_=brQ4=Pb`Px_ zoSYmV*)}za&WwA#9dzM0dxysc-Vp zT)Jx3BY2wOUoX6WRW?@P$I*aky3l z$(X8W)vmE?hF48(8=aaM9$z&%vTA&I&)CGO?Tz*I_16xL5A*hp#`dPReM8v79mB-% zz@As{Ts1U4f>yeFWZNpy28lG^?Y5Z0F)C&I_K8)!&Lc!#>fhAY)L7p|u9r46mAY1S ztyod&Lf^1+c(ioM=*Yg(-p0n2tt%T=_Vo8bvFA18BRh9ZmX>cnyVS6Hb?bSJ^$qQ% z{^5Ot6Qzx#6O-e(HjGXZ-aaqW7;Yw`LUCeb=jiZIY5OkR zNJTZpsnLX>wsegF2d&#Ryu}N#J8nL>J*OzzpHevIX z*rfFpoxROiU5QOvzpAsh1*-vU()y~--d3yzu}SM~oxN>XZO10og}VT^)}db zQ*WbPxAivJ^_t#hyMAeJi(Pm1w%YZE-Zr~_S?@(;W_e%#dYFCn`tl{+otKkjGb97u zm#*Eo#Z-M2XYUqwbr{$=JlQj{jknwxjqm7NXaWP3ImhTs4Ci~pvF}ovqu0-%{tHna zUVhbWJ@{2_DK_cV21Rsfr_NbmYHMm|)YjI{tesUmyLMsin%bAvcGYf3{sTI7(8s?X z|D2BXE%+48wfL@z%xnHz{<%C<8A_FxwO26aGYUhW^_~8V1L;4GYzbTLRMCZaU#yE5cNItlc#UuQkX?LnwxF9PTBfAo2_5HUS=>$w*GQ=lGsY2Z2c4N?Bq&vD`|kbc?sbM z75F7q>ZUdwzeD({*$KbWdcP9hukbGXNK5`aLXVbUxy-E+*)GK*%b5V(*&kmL**ZPt zB+CkbcN~S^BV??J|J+gdyA+=~m<#CCngo%Pjg4 zT0>O3^`g$+fz6lnmoGsYZuDlODd!;y@!khzxy{Vco9*bms+@Xi za?jKxhF?r!JKUK^KGpo59D4y*jNskCrc1Wg*AH}UD);p@40QGPZY;y+Zsl+eV_*_2wP=%P{42i(1P;9bv^bCbGW#h%DN7}6cw|Qx0SINqW#U-~(^O zO>0^yfw!1KM#q6Snqo@T?21L{A@JIyxxQQ$2u@RV+K z+5-fBT+)NpA@CLxWt0fqHYQYfMhBPHx^q0KYT%9yM>Pb#AW>`u3J0Fyao{+|Gb#$a z)dil?apx91K;S1PJ!lAlx0)!Ul)!PsGdd0&=XgrRJr~+r2>j$^u~`ZSp5bxeILA{e z?!ZDR2=3HmDNO^|yKi$>r-?EeL}pJD9MX)ABg09YQgPRW_8KBvm@G3(;m9&PjtmZD zRO`0(_g!{zm%U!4l-zv<7ZCQMqzf$^_C+SjXe4YL(2S15#wnaqwGQ;HZCKyakM^{A z6TK^^lq@i%r+|rwD|Cw3mM{d*mn03fvmVXE6|{6(y(%b0T%9n4g3d}9YOH5H8j&k# z`LudfP>R@)Foc56Ng8ToJ(`6p=-g@bs-P6HDPaf&txOtfhQ3iBqxxy}s-P6HC1D5! zH6{(w!KQ-zF>0PxuL?>LsWAjYD5y1Qh#CXw{V{5vR<8<55vef*Ln!F{grO#C45atR z=z?kWs-P5+8bdIIg76TuN{Ba2?c-l63p9yw9woyy^DuT6y@kG9E=?T^=D&muoT*_0 zPuGTxc1hN0pVgA8(*|b6a;9##8YEG-Ta7+X?;ju8W3%*=QT{w~qUKKW9Et8M-2&k4dEHN=4VPM2_xt$s`^1%GtCc_)ImV=t_%TFO{P!C0t4- z>0ZZIDXggC5Hsh{c?1qR%i^d*hOR77*vS;#EBO+~q1%+S3unW7_Z&ZQN>#~l)MrA6GS3|%QX z?vSE;T`~d3@#YLVkHB$fSsZuB&y@v=JDH$+WimrY+?+})f{#1o=SnMa<9KIx<+wwJ z?srV)--w$N=sW_)on@hjWO}YFP~6G<+$)m_I^yO`S`mEQAw5@G#GT5|l@d-R6Lis~ z(r?7g`EwqDpTL-on>*{AvyOJxa;B~5E^IFih!LHxw%pyu2gcalpI&c&b=;~dm}E+o%0AB zSC++bh16VGsF0g`Z8AAW)SO5wf{Qw&=1L_|<7iggk6Lj^&i#(5?AvGOc?60&nVx%Q zUViQgc?o(RL6yZBx@YF4=t9WN(entZEKbrrGcQZ`guFC8kD$upJl!+%5_M0=%hdA- zsw_^`Ju@#?_k_G;J&Ν%wbB^U`%s$jjIB2&ybj*gZ2ZV;4eh%AQA1WpU2#nYl?j zF;vQakaA?ojB6gI^!R0`_#Cy+f}uT>_t@rV8`(Q67(EB$IJP7Ai;hzJr631H<_J_E-yI`dLM7d&4Ussm6`_~{7Gi!tjbNy zbMzc9=jDOK@rJZKs3_iKRxY}{q&(<-ydftKN+26=NXdha;|&?PsPYo>96iU&`FJ34 zydfPIRbDn8^w>3#j0X)+Di;qr4k)DJqRPv}bMzb#C*py`0fjs~s4Ar4qRh*}gWg3O zlJKAbveAYdJm@&ukb;XUF9XlfQ?$thT!?x3x9IcI?;O1~A?79AqR-2> zbM&epPPc`amu<5?H`&h7tAaS!7GiFy4T8$FN07nJqYSoY1*NgC#>+~0G}`vO1M7P> zxLQNZo=Cq0oKIqoQ!lN*{&FK{x`UmYr zM`3iEGu*99XnYpoQMag~0ykQf6-bpTD{zsotiXFSDl1w|bw=Uxj84qpNV_E&$c&5z zeIeiQ*5>M3%*;wUzLA=ht7|c{E9p2vpOdR=!BhI_2;e8@h4XTCEv7D`qs-e46wI%v zb9dEoMV-3?J+7k8-K`y8QRnV#7F5)^yMPn2y6_Cfi5VphpBo1`DNogi|1C*Z8Sm9( zPRUa>n^P;P++Evgd8$UUFi+KFPR~;{n?;pWZbapbJQd#Y$iKdZlMivxUbwx_Qz3(| zq~g23JQW7b@>ETxI!}dXSTid9{7R3RF|EGa)aK}M?XZuv%$!!=ZD!@@aow={&z@G_ zZRX_Yam}#%&z)A^ZRS#R86;e1e?`7$2085b3A!R zH^*}s<~rCN-DW#B?T#|XGr70S@vN3Pp4EPir`yZV@eKR939PkscG72^o%C5}Cwmr);S!XAG*11Wab#~Hc9Z&kinkRh% z@uW{6ne++hCVc|fNuOBTNuO9_(kH(Cq)%Ww>9fvF`mBrGq|ds@PWr6lNuPCY(q|n{ z`mBrWq|Z8@^jYU7eb(`$&pJ2hvyLZy*11Wabv)^_&Q1EP<4K<=-%k3(+D`h!+D`h! z+D`h!+D`h!+D`h!+D`h!+D`h!nkIc>WhZ^s`AMIUs7ar*A43mpA1cBdGd9}??Zd4T z&3mBfGH{qC090Tc+i4faY{n-~>*$MKUx>%awnft$e(rVvnIm#Re=&R6PAUmZ-+E<=o}jbE4i*>0e5-UnLc-E1hP$q0%45 z`<|uJ6Qc#$I!~yNZI$0}jH~>Bt@1(pGvDaoZbLut4TQ}^<5IIIL1w-}WUs4#jhuR-O8mtv@4$Kq+Dg$(0!5Ko@Za*P z2Q@zxcd#fKqejJsxz#gQR9D~HRyg&znnHoR@w#V?SC-GB%n ze?vztDlYR*imLEVit6xAikh>`Mobl+vD_4E7gl4a-U67Lxe}5K=Dc){H8<-oeRaib zO~kI(chug{k$uC(91J-GXXm>2UCi76hRAwT_eKEH<5^ez;tQIlZI6n2{QybQ^P@XuAaLE%<~ zuS2&l{5L54_X^*v@GT0@!DUwVJx$?t3im6#7Q@H$>~V?8gwaB1DX#+-JApM}*p(X_y1zM&eIWcM_F;|U<2h93;Qxme?nIg{_ODd^uy#y&iv_}}xK*!)Q0pDE5a@fR@Spfjm~^3xHi&v7!9d{ii`xCd~iq zQ9cb=UQR>*-03*6X;b)&_F!|3!u<*l0?WSCe@J^He6o$#WL{b$ZKDHvX&Z!vzZO`0 z>-HS?zw~k(w<`V>ihmWb)cGD@sdK_&e-c>i@ADk@|L{^*H!1#G75^4si5Jknbm#TJ z5<6knPa69&9*Os#AeVRv^M5In>HURH9^3ylml!{(IG+ZVxSj@(`@#W;P z`9HuC3*mF|!BTz^UzPl)SLvKe4D{jTi^M{>mc;xLAc=+QQeq)2oFK=4m_shH5Ef35 z<3G$Hmski3C&=+1=8#J)goP92F{E-V0;w%A@yI6|R zEtExXeQ_;HlkevZRqp!QpgI`Hk<42$iG&L3LB zE1I(P_`IW_4a&a_Wb3iU_3e0(RzBx+=7fK2$ktIKbHcxZB#FW6W)1gG9V{T`QwBY KVmQi6u>LRp$|r>Y literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib_eabi.lib b/gpio_bitfield_cpu1/device/driverlib/ccs/Release/driverlib_eabi.lib new file mode 100644 index 0000000000000000000000000000000000000000..1464424a687bd967a299d6872969a911df13f136 GIT binary patch literal 654036 zcmeEv34B$>+5Vh!?zu?_d)P(1ASj3e2|I4tA<7bxu!v~5NiHOs&6@>KD^bu=+z=6W zi^_Jv)}__jRxK)MwbZ5hSr=-nf7{RQws!HWwfR5qoSAdx%)Lpjt$}`gonLO|yw5!I z&U)s|nVB;)@{Dk_vihtZ6GMJ8NfDiE^?xWdb>@^Q4rN6T#@MeI8+^I{x99`L{*~V! zUSURG=Kq~NfEntqb_X-of5?nG$9Dev{m+<@;Afs0VrKac=ePCy%%tBpn!VpUa7*%M zEm*-i{oVN?vpV|yGQ_MTeu48gvhMuZl|N&j>-YKwW_R%mo_dJ!--4wq_<4Un+Q@=Q z{8HvT!8-lj@j6TSKlV$zESsg>a6td%(V99Yka-PN5qVuSf3E6O zT$~HBac)grO>+~=%b5=i^;PpCO-#@w5Yy05{s4R4fQK)R^>IcP_E5wKu(04E2~-FyyDW*a>uc-rWS5`^41@*;C z=9Qi|A8Atbl!WUVSzhrX6k{YxF)yfVsSP*RG}QB2l%JDV-rQ0jQ7Tz}Ug^B@Rgvap z4fT<%!rE|Cb-~gCQLL(4W@m0CIrB7ME%mhxl^1iR2!L@-(Fp2JQ-r|MNL{$Gx*-~I zTs(HB%a(D9*Iii~uBp?s%*zouStcqx%Xguis;Ve%iAa-zm#)alG_q(YF6YW z(Qu<8^872v%PEe})dG}+2)!j5DXm#mAFgE_j4ObGg#}zeQGH`eb8$m$7}aPklW1N; zU1K;J$>a5f@eD6lsuDYHK6WJgPlKS$XB6MQ~%yK`3wmQJaaIu=OGb%4SbDS5e7}0VRrv zqE*SG3SAhbwynN$Z6b!>(XY|b;b%nZshM-5$=s{*s>sT4OKtOvW zaLXDNwnSQ>P{63ybw~=A6MN>Va2{KpSF~f9of=|)=wbOBqI<{*YhGn;X|Z<$m#pDM%`~{QxM*IOlFjR_Py=cz6T6mm7{}7ua4Xf= zhzJI^Xr!h!k~uAL4283sfcXveS{if(@eC&=h>|a^GH=|F<2_1BC!xDHVcD9(Xt*v? zy0*Sjq)hsD1JEMwdM%0biYBszmq=;Nr81*{Ii;jvqG{=*km8C}&(Mw{RhFoHMR-b9 zM(XlbuHvmzsngarv3U-L_|7iH!_jNCO7T4N9OriEh_-Q2ePu&5S`dvkM8(rl@mWTl zH(rC>kcy+|*YUPq@}LAQa6%Py4T^)|*M5E!gjF1G4KEVkaeRANPIMiB2Mcl)Lc*trIO_KCxTQG9NEmb@g zU@xI(bZvMQE6p#IT?1ZIcsEZ)okxBcZ7@RvQ!eXt))d^XO&n4yl!HhTzioUZ#T#Nl zG2-1?(%guLCK@K{m6lN#DeROcIjMKJqfSXM+!JLh;KbSL1%>-PQD|}52OsgdzP2f^ zxfajCS}IycKs0h%M7!rf`H|L|%1CjT8i(d+O{HWvp|e@pytFK5t{+*@R4Kago(^=d zOB*ARDyQ8SIOPG=Wa*tMyec~ZxattK;<-v#UR)Oy7nj#G1bMoJD)RE%{eI3)(D5`!G}kP$8$7N zfh@tB4xU5NiZ|jj?~oFCRB>&xZu)lUK-&N#YF}HoxGzWqDZXS4vW&| z+@b;~o^xI?b&D6&lS=edWF|VPo6}OEgyA|v1@$h;%lwu)8RI6QQ_3hAB_<2XW|yMp zg2qW?nU-F2;h=}C_33IiKIeaQxGDKlwB%Z z*05?7x_16RoV;+$fWlC`Be#|0QJj^GR`qLY$f>lYsWF0{9>U`y-BpTeCC|MQQwmzf z+{p!B66fW3)r(Y%%=U^EIV7U3l%iBfIaDel=9ac}^o0YWlV@)BxK(N8N|`RDR79An zE{Yy9(H~z?+4Coz5KOImOS^Z!j33hD6$(Owkl^0->2^w~silrrKeqydBkwU8wAa+J#gQo8 zO7zT`TT>wtfYZ5nasRpo?+ii_N#_sr?jCr`?nJ}GNPD5Q?I%dz;(teKOi@j>?$J=PV>Ei?=RL+_3; z*!9el7@INH!KbhgF2=H4mcyQWWcP?U2MTW()oP5h7VofPn|23xq~xc?)*rk-Hf!Gy z#`X^RN4s&;z8ClY;NS>yD@==R+7&!-KQQ4+ZU;sTYklh4AoRtqec@0xi=F(!p*9w4 z3$?d3-`l58IMmKs?(LHXyAAe3i+8by7w_sBXh?m^YzRD+a^nNmfeVarq4xInoqdLe zci+5sd|RotV((bQ|Bih(Ki~R*m0kMq;+SFKw`=R(t*g#rC3bjJ>*=rDw9O0o$-O-6 zWusaV9>SeK;lVyZgx^<$f7*(a8^3NH*yx0~tIwG5^Q~XEMmD6}_>h7Q1Nx9P2`Z1aH;_ij2ET=N#&+mBwvL3Q8BuT~t=IV19XKR&G%lW47^NoXa$F$+nG$P%YqFsPEV3oQJ|C zht`Aux#|O4Yow{6wuL&v%rYOA(O}~}zqPmiq;x=V^&8_cmA>*nhw=UY_8SDNVZ}2BqYIKr&qLTmSu>I1^uN6P)=c0ogZAKBXi5|1;i672i<+dAjLeJ_>vJJ;vSu5G}(g=w?Np8AL0 z{rx2=&zdLuh=>+qH8~5hI^N2ax)|;Yc|(24I(1L;bDLlGdy}391SUznYAwEU_woy$ zNeMOkYq3=2)MBL;?F{#Rcg8RCUiXDzyIJfc#+S$QUpr~Uxv$@F*yls!F;C5KD^F@w z^Y}Zb|M=bPXX?lJ{ZSrsUjqY$QnQ+z+Pe-V*^ACs z>Yi!M+_Gt^pIOz=Lc_g*fO`9%dE@&B4j%r^U;R{ybjaghh}KTDw#LNjhPueamWuk8 zrbu*RbIrtPq_LrCVrAB(Nt0G%7DLD@vt~@5zNQKipZqCrym-~bswiGlqqQ{^6Q!$% zP}i#xDPYX(rVuJCn9?(Rir+& zsJ>=Rs5L8V!n6sQ6Xuqc!l7|3W(2F7Lt`t)g)(Q(oOW8)q|6zivdEfnQ-}tjqv-Y4 zH`6u7*%})#iXN##ds|)}K_?s2dF};4RW(fnki~8=-5l<&^m{o>xlHYIcZGEHa@x8H z`ACmlyfpYH$z_@iV}g;8&`q_@$@MbBxZE&`D=-bpWFul2%NrXjMCU+0?hSLpr5Mg? zoKwRm_nB-!fv+KaZi62W7!_QpY_9^UQrWWz7-gzX*;EIN6{<=J+tiStw|Jy$&;2u~@4`D;oHEl%o2o$QmZQDFLI{fy-!_ ziieh92vfeF$X5OQ|)C zCQ-YjOSe|7*NjW`MlQZ)Elp5a>|8`PNN?JVwH)bc(GP(hgVkbcz%VXM&|1V-p5=;PIph)W`IUnQwpQ_JltW@lQ`-x05Q|!2j>j*+ z2H-ypw-OKEIrrpm>?T@(E-rw<+ZS80OWvAt5TkFoI-%k8;tSk6+_72g?eZAz|ocC}Z6nEGOfNFB>Z});*uY z__)#M)k8fxSI=diPY=ag8hUoSdU7+q^cB-wl5xcgIi&HQNguWQuD%6Myo`Q^mD+c3 zM*4B7V^XipPRB!V0<%)j7<%^5`c&{S+GY;1Qj0=xaH#!^{)R%gCKyJBl}hN$^jYbr z+vM?@?9?x3+Z(gfw`QYh4NP%$*c-1zn`wL{d+0x-J3SfQo3e*qPwInTP*CX|C*z0( zMfr=s^h5=a_37zOwxfI$5#?wNLOD8aRC)ndOefJE4cGMavp@`<#ELQ)OBoAfxT`Hy z5kX2j9j=%q$T9j39@Cq#^fnYEDPl)#0EKQ<{_w*sEzMYY0Xva9-HOsAa;IBNnndn& z%Sb~n#7_7$Ofwt30nxdLA7Y@p)1lJ)vqDw+9He%n%cIvIg(o}eL>l3es8g(v+zwq1 zby~`bm@x>porA^Bbr|A{vedynQhJ&L0aj+sSQDhx`@km$HTS`qJVcX+ zYVt7l2cN#-n)`9=?>_hAHF<<4pPE_B}v$aLNn_&o{vO8hLencVIpY`kr7836>z zeI#QwWDjPn!oUS?7LK1NaNLY_LeC|_4ueN}Bf`E8%>&6>V7va&6mh+{VYz>V&;7%u z@q7z5g-7;c@(=rbVTV;cxS_coGy+@?;?MQKKA-%d%3WekblVa!fq1wT2&tkfZ8bwtv5B`7Fy{D*}zu|{4#;xEAVd!{96Kl zMd0rX{1*bxq7J=U`@b3!zhXQ|9 z;C~Rfg&UUir;v?&4v|geF7RmrpD*wg0b7W1k^M6*t-Wn%JC#84h!)0&G2lC$6gsMnI3$4&!*}%j#)>%j7 z^-5ZoEQN4IMKsbXrRKGb_#{pE!IYuA#8T$^Rh~;DrdXk)N%l3BD5~Rk+Avqbq#miv z@TKgZ$eAQEqrAMVsJx=3rnag)+>F_)ik4=|vZl3l&EX0*0kh2simI%L2o(*r6YzOl z7<8gJ<>!={Cp)qBWRWBf5C!W2Zn1fgTXYjBWas;d2`jPwkYd^#7racgd%Pdh1#b@8Ki)sl zc$BAVI-W-RI#T11sPoXt#fs1g{U;^V^c(?FR3?1iWj2sp;K_ ze(fBEhetFwI`5Svc|*|YQ|og_`l`W86zp7&I~D!y zi<98pnk3I0#@Izk=&J>f@>DnX0#MWYNARd0uA2t{sJ!#hPY>xN$U5(`Bzbox$@^{x zyzgr9dj~ukThNWp3!-0!u2`JWc@w}J6USmq=aqt|wrkSM4{(9*Z=;l3z?&=u#eNUh z=%%}74|v7!m<=RTpwyrGC4Ol_ChHUQ+Xz1iKXf~}L6gYZ@e4Ax&OsPU4f*{MPQ1P- zTvguy@CYY;z3?NGh&Mds@zAB@CJ}G6!b6kUA@5X$N9iF$`a)X#ri7gLJBputJS5`H z1uq*M;*mRh;Vr&TKoaU$LTg?C~n`i3h!M3o!T zw-)iUmHToucxZa#%(dX5da#giISafCfT@PWn>F5@Na)=Oc;TkCO_j~H?sqI*eZ!J9 zGfRBV()Bki`zc{C@*9?ZXptyy0vrvfOVcSyjG||Dx-{LT8C@(*_lUlQ<{d6g_xSF* z+Dg8dy~CyHo{z4VrhDA3mZp15Hy&LrP4~QDkuuH0orY`_Su9tPhX8pzS2g#L!k=Tp zgIwV4_aGOGPw+I$wbOp0t68qdKE?B)E_(Lj!j}$ncE^jJJ+@DOSBsuKZ(S{V_L$xx zW*YnunW8Rw_NYAO9{()VUcv9SMbF}1twhwiZFao!sI7aZ$3&+qYPuvC{V@61cd$D} z%?xk$(sU*!EjclH+(6`p=CI^*od64S67u=z$N^2Zef?ky zAJoj`nw)ddE^D%tz?-2L{0)L2X;Li&DzXbl4!2c}p6m;S#+;p#!ic;UYeiRx>yeNbv`=T#ek$=Nm8SF zevLGc*TqO(Cu4FQjKLknu{4?SH0Jge%0oBQzgEkq7al77zR`#wjkf^z*GP>+VhBG~ zUtSw65V&*lW`x&cUP5uJ_I$p zmV&n(7`-3LcPn}aq~{;n7xx|Z6Yy{=`3!C`zV=eZ1Mo!c5$QsFxFOyK{8Zj>@Y;|t z;>q|B?-u+JlpF3{Xy+33(RYJK`a}4Uc?`UT&ZYaG^6f$VR9*@K`L@e&E{Indu6O(A zA(*cE=#yv8n40W&=9@2d!jXOS*V${#{73ADom&bI2Ey!)wmZ!RX0BeitbNB8vm~&h ztuDZ}b4NJr+~C0xI$PCr z)j#OF^e6W|d0*fkWe4(~S+sHfHN{uuUa@OL&X-EQOdrYb3Jz&E*tP|+Yd@{a*~0z{ z*&DV>tT1~e*s#Bq^`F?zvST;w*kY6n3FmK#WvA7~_B}ARKZ^}%PhmHmzBsl%b|1<6 zW=Ul45B3aWZG9Su4Rqh0A?+v3S-i7X>^{2UuKV}B7`tKL_I!K|zGn!_rWEDh?|f6w z+8imie(w;rKR-w)yVKab_Xqo4T-t7jcL!s`Sl`_va<*8AXUdA)Eqyk}mgDRE2X~J^ zh&j81ZN+mI@9vo&+bpif`N)o&&%SAPTj9wC6Q4V6&(a6B?Anx5{M@$P zhb(q=d#vq&A>V87c{ny}_k*z;_8#iPzT6(07@M^h(!N6}?ArF&$=Fo@QXg~YSI%x< z)((m99`M{q`qDk{j~yG&`Eu-r^@k(aAz*iG$3|w(x&MT}3|_pO?b@<$`Tq9QlEBJc zTlTk`4XJnRYL2x9N{n}}{HaxA-C;KD-jZ|0m4|cJ=xi3-xMRz~_Sglxmd9q% z_w*Z33u2p)+ep=}5eOLtVKC(IFx>yB0|#RcvUNdh{ik)ig6#U9#@3A+79Jdd+Oroa zzi$rryR5zM!q_!VjoCedd_KQd)}P%Y$S2Rg8}^?cyDv86qjq*v?5dqqKBu9MJh*>E zEVg;!^CO;L&|dfaUiwerZ0pVL?6dg+l*oYger(r>*uEa9d&Zj^wrpSa+!?Wb#=H0R z`Ja_Lw*gm+!@>3Qs0injCXhU`K=bC zefK$W^6JYM6RUx4tg?BWj5qH?%|fhhPJO$weS6z;XFBouD5>}q@*H{qHQ=AgA(YEw z#!okF*}W9yf?U`hS1$YZxw(KE9b50zI0`SeePDYUN_X!tjLKdgGMe<*;|9I-EU0b|8DzaaBdYCcbdy8)xmi@|2Th87*rsVG{ zo<n}12>X+fa z`Td|-W#djs8>jkCmpX%_RQ(it=GD`8t$8*2FyU@sW=Qf?&0qi1@9hf)&Ku*`EEPDK zzX~-X8GG*d^yfF7eAx(}X5&5(kU#AyGJh82o>N|SUU5Nr8M4l{3?q>X_AQyWpsaxM zDv*FsvJ^WDSSblz%9cvcmTmPw8PUt9h~hh+R2M$8>APq8qG*Yn#?H?opVJMQ7BxFI zzccZt55M*DZ~fUJRXW*mq8FAr_~>TzfA+<2I`rPo3SA98x>;w7!AG=~vN$&$KeR79 zd&T>{;&k?t;JaKLAIO$lZ1C3sQ43yw`Ag<|6JmLOZ&1%Y4Y0>cy&Vm7dU0}x3&lVu zy^x7eP}Ds*0{_$=9JaRy$H`u3SKaf`2lxDO)Jk7yW=MV$tJdS*`_DKv^!AxC ze?688oO(d3KI0?s(Ft?me;jvRYLx2PN+pK~vdz(2K@hwbglX^JGbA5scw%VRyK@A}R7t^TZ(dYr7J!9j8Vb=O!wz4KS1#P9~uO`pLXy@7tS z7WpUkPj&WgHH`o2=>sfzS1?9qvBExH95y8$mmrV6R0S2_kC-J_4_jM+-1{e`44u4$F8S}u1M{mOSX z)Kf6{yNi4qfu4Hqi)xo!wSd+-%YNM|Zf>|3yt$Ej_ddWbJX!@`s@LUZPK3P5Eg~de zMFZxBbuvcsttntcya>5I%?+135mJyVM1;JX>B2hg9>Gl*j#j954emI2%WIC-x~aAA zqXK5XJJPNDBm{a4-bnN;x{rvTfU}}&H#Gu;mPa+6(ry?7d8eI@RZ2+g){38R8CN9eBVF$ABVm(4t;{d~Ej|~49)q>`$pp37IbW1=nG$UnC2=*_VRUQly~Q-vBxv+n zKS%AA1G5Qh@4sGE-Md5%3u7pw%i4PmW$Tfzy>k%g|B>439HL9POo_(KYFzDg7~NWX z&-vGDZ>MeV7g&4c1XMD$cQ$1!yYoo5y)=1!4A$Oz;@e)Hzm#0Vc*4;74c)a-pEC#2 zo?r)Jyhz2528&0weBDX5w@~pfcMZC3Txam?qqW;d^zCT+u~|KD7uAzauaie`QwCFV z4P&k)Cj+ROs+?|ZST`s2E~HdSIi-&mZhsBDu=BSidLMVrQmR6hl?TWjf4meHD^^V+O;UY#ie zK4~FWlsWHXnCXz~8_)ubH zTn~dcF0I=0ktp^4rUd~(n##x8xg%Yn2O`j8utN6|64#p3rWd zNA&G)DDJFd@F7HVjMVWEr}tu^ShS^49^6fh38mXG4t2=s);jao#E&2>Ld&a-D$@u0 zl-LTvkQ2N%Re5^|rH8fQ7vQ_p8b;hvBi)o5vDHL1g-_XeH~xD^hNSlbgt%~Hbno~N z55qmpxem}T2@ z?4FO$!Z9HYGpvS6+kW3p+hO;N*lA|!AgjvkW#qtZ?F>8Z*YKBmve|bqoO<@N?frJz z6M%vP?6in&f6we4`i`}3#!UY2X6v$VpXnUY@eNh!KK!pQqD^Pe9P~wd#8Hd(VLI_72hqN0yltmPl!2o z+Qq1Cmyfs8CffGTPqot~aM8KADQNaZLU#O{B;=ML60#I`M2`$a^3ozZJ=3;-Y+W+G z)yeP~e9`*rh%Mc@Lyl~QcT+1xBgCSKa$AUdY~;h2>~!2t)}?3K=_uA6_gxb`#ZEup zwr6uWKVYJSe|PyJd(aX)<3>AenVn%>HpWgnLvhNuSYZ2Lwh@5cJ7+p(K>Pg=;kiUfK0cQ5a7gIbqqd9_L8 z72TS2w0eLY`_0-9sd=Agr(3C?p{A`t!*&`Pwq?Ak{ps>E?LlXwNxNbU*%?u#MT2Oq z9mA{G7VAv3a;NMKVvi@oxLtj2{p|?1Y3SRc8;}2nb!Q5mSHG~+?zVe<^OV=JojahH zuT+oBd1yzY!JX6#1!!AuTNeZj>*33%22AT^>jFD{1q#fzzH|A1RiHVg1LC%+rS<7? zN47atO6v}sc$bcr>W}xV&2s9|*VUM@QAaIiPp0;=d+oGS&O>*4%`J9{)$3F1vV~LZ zp;rAwJ0*wgh5uf8`PURZFSq;hGIZ4P@(}gqTkJl!(_6|AyU#b!AF8f%$~&9in$z+B z$i0oa{k(4K3#o6r-4uk|x=_Ap=LH%apF8M`0H9jHWaF1{1)V#1`4t&gKD-A8bC;ho}Hey|ZGYykW zE7!x*dTG6$*5RG#7$748o8rau3-)OIk~yD|c+$`^S&>&?F>tQpwWc{Y;|gTZx)*Yi z)ko=&h88WldC$*j`5DJ}bPb+7*C%aqn z$Vtz|b+UP=)?b=KcjKbg-^(g9E~mtz;)&{;w0O(#via-6zaAkc9G*u_F`SLZoiz0H=HnX}nv#Zk-qIv;S9^2+j63;} zCXs)22iipL)H{_XkvsJ;rAg#Yy+mmexl`{?nndo@vy&!~yR$0CVI*>=9+xzU+zFE= zk$YGEsV5}ONw{#zmv*P2^FC>|S>HK@*tCt1!=x=kB(sC3jGv@L={&h>rLKhmYq zx8#1B`yDiWkn03Y6XqVNgYQJa=Ic`(FZ3y<>P4)@&^{v^>jps|y(Qv%A8d8a^*)ao zLp8E4@z!cxU|MO0ZUn*>*XsgAC+8Xfg>rT^`%a*w5m{& z5-xTlx>pReo=l_1FL5F-UM-+?Mbe9J*$dIUh|tOsAFYVC&(T&zbbbl}-CXV|1ZfbG zJ^MSAq5@-LOgRHK`6WX#-7)E0a^w?m-A|Ee_c-!HhWL~s;*cRZ6E>9z8Iq|5k*y@j zXF{GvjxZ$W!FIm1aAf+VjaGq@p|i%R1*9`1$dJ4gwilko${~*;M;LNn3EK3Iyu6S{4#9HLoy`40ecRY9Qh}> zE>h$Va4pZCGBHp3Ysj>J9T}4U2;0-2%Kis(HhyHt9XrXg97p7G3S>`T8ly8CJbh_w zAY`w6)7WsxR0qhIW*R#Y@>!0^`$0xZ+0DITJuiEL}!c6eDd7;^0O+u`>`Lp7w&R=%ryJ4J&?Wn z){i|1SsFT57w3A6EO^)7Z^E zxd)5+8_hm&sxgV?c$r+kFK$8b*@*qtf ztjR+(d8j52)8ykcdAKGYugN1c`2)~;d4Jvlb31o`I@|3lP}QZ3pKf1 zlUHbRSd%L>xl)s>G&!QlD>ZqQCRej(eCe;z!Q0c@6uKlK#GUcKuYy^k&^3{g2-ZIh)HSKW~ekXw*mRkN(e4@$jcU zOnej!sI zwm&~`=OAj-`yYmNpuOgp?-XS^pE-r*@>^sMhe-{*O&KI2YlD*;|w_H z^t}dri+3BLp^SG$uf&y=%^0_Hgqb-u{!xzHKkSv{5B5dE-cSA^Kd1V?R`{%xg z|EQ2`t#D!tSl=xk>1$7kY4?aXql<99|1HuOF}{l7HBA zUY;9|Ey90;@IO!Zht2)L=Jg8p81fH$yz2jE;lEM%$9>Jiht2N~*!=#0eFFK1O?uq$ zw+jF8R0r5Xd%*p}=JAKk;{lt;A2xkLNxWIAo^9fs#HctY@fPGC=>yL70jF^T3;5jv ze~@h8^v+NCA%VXu@b?A&SAnNdeuCeNZ17Ja8~W)TnD8?M{(`{Y5%^C99;A3vJjn)s zIN8v{&o2Z%Tj1vkd^y>`>jfSa_|*cxRp2zjM|vI=`11ni^$z%d3;cfs{u$Z8Gb~5{ z7_t$cabyEOQ{W2(UMlcLfnO!?YXp9q!1oIL>jHmS;O`0i=K>D|oNxz`jc{?OkCP7q zpDpln1zsocbpl^6aC(+f{yZx1Zwve-f&Wb49|-(2f%mbUa5Kn8dQT-Add?DfuE3WF zyhh-40>4J!w+Z|%fj=nlrv-jc;O`0iV}buw;6sB>xZ}x2K1?JV@mV17u)re%zf|DY z34F7_V*>xKz`rN(HwFGHf&Wh6R*DnuK(Z0;P_hwjmca7`K1bjy1RfQ5tH5s+cue45 z6Zq2te@);&7Wi)j{ttoE@D+tSoNVO(1hNsIEP>A#_zHnn3H(&LADf(UCM(++kFzk4 zNPQrBo^$sWA?FIYRmgclUM=K&A+Hf~fsoe}Z+nXqhaM;%J%dXqoJ2ne1qp>}Z+nXqoJ2nc`@f z;%J%TXqh5%#L+Uv(K5x+GR4s{#nCdw(K6N1GS$&C)zLE5(K6N1GS$&C)zLE5(K6N1 zGS$&C&CxO~Qy#k899h#mE79cR1lJ|OWTVf~n_SdkKAEV39ZVkjDe;qqiQS#a!NhLP zWMD!!C*?fN>SUkCRZuax=ea49c^;T>@-EIfezMM^_$KExSf7lW(D`A@&fx)q6&e57$BVZHGd2gmwv*pVcR-Ga9GdDFp{@_Ns|aa|)8s zgx_RKdcysQ$uYjb94~Q4LJ%wpE50-oN0COcF$p;+?`R1 z+=E(%c{N|j#((2`(04;Q=ZHHuXKhV=MBZJU+>lA!gI%0!9*xv`nTCcMH<{Du`WzDE zrq5le-4i-FDcwmG`Ba-APZrtX0V3%h5SA^C2f3{c4;dQ);RJ^X&Z!|2kU!1g3O1ps zT3mI|^GEz$oWmw}sqcD?N8@n!5kVNq`x<1rmio3@SpOnP z!i~fi#I@wnSny_Y5Ju|zIb>DecfiAIjB6zCQ;kROo%JruOGiI=Q1#sb9=ffrk@`;4 zcz*=%6qn`c%hh;vHaopjNF(*pI1OFP^y2*Ig!#NdP0C-t4P}md}nePam zBQf?ac&qWQr<>O)@GnC=tk#lA0)?iLufycqgIq@v+b@ zcz>P17$58Gf@f!nG0iS`vnGqN%Px44sbY+>3*M&bVhmE_y{6UE12g$>r^aGT=gpbL z*u8PAc-}9;`=2Cu@1M@tx02x9eumT5=~O*_6=yQGM<+qnc|Gs|ps`Th=)A(S8JnC0 zZ*6vR`X0?eyOxB$_i}M$auU2@7#q1;PXuH=9p3_v+HBqEyzdv_{?JK~bzVgwV~-@k z8-THxWb}O#B6#85ko%(5~r7 z-v;oK3HSTpWxLus4mTBJQN>B{mV$?2A=h*izi%eV>x(h3WYW77ykydQ7kDe&*ma!V zzb6@PKE~j(lhC&TykydGC`o-iG1iwTy|hM7t$)SfO;qA1FLmBJ@YHhai1$vCyy+Nw zOh(_$;9VpGQ*1qcpCzg9JXF$T!hJMJUO$W-C!?<}N!|;GLWV?{)CTB*FV1@X*DNGkW|^#mn@hI2P7*Yw2AM z-l<9OHYUmYCU|(2iZgn+ZzsuPn8QjYey4($O#UqdFVS;Vk6#;j$>j4lz)Pll-|iq> z+R7HMNbZ1u4yCG4{kttf_%~DSj9_;fCb% zHQoV*2emHmGL3gg;q_8@Tfqx5h8bVSybhik4?-#2otnO%Df(pjCE|Uk@J@1qNT}~4 zg(u4;k-kq9-q=p`u~lCFjq8M$s_LFPv59ccuT>P={Qm09W?#*bUSz-;Xy(1>#y)= z9c`MB$=clDtRW%ZG=Wn(bl!G_H@y?yLke$3C%pX%Z)PXFR}|i?PIy04co^d2CQ&** zQg~-{!lNfFJs&AwFvQ1AB7J=o9)|cjxVuhF632%kM z%j<;KsPN>tM526YQ+Nf6K3aF_tA7d)T^?>opU&H^@RoJLdr0A(-wAKO!jtc=?mU4;jUUC z@bKsMElvS13m#QtKp3m>mLpQ?_s7I1US(}~0?wS77!oFP`t-?@vZhbUnh^?3;+XnB z6q-J58eGV%=&`O~ZlQZB1J`#w*Gam`)QXPb6dv2L=!Xqwv9>)Mjd9jyYjMn4*1mg- zRT5aqZoFo#)xd7txOPDFjhEjJ@>FFfX?A=H`@_<&>UVo=Mxt)_QUlGirCgqPqKyLnYPuhc5^La-(YU7>1iJ zp5Ibe5sBiHm1dbFzCD2O``w?g-_>7#?_=Xszo}AVfK;-bK{u#xZ(7xK=g;iV2zP@r z_JDv~+3du!q-gf+f|Bym1%+ixa!Lv)e{S-*7EE{c`UypOiB9}3?`Cy#OWO6ylHXn*}nL;in+vdY@E>p>6tZhCL z=Q534#@XgK;#{Va%PF?`%{Z4C9n5XPq+dLTO!V@;vHlK@g;pIEeHlL4k;pIEuHoqU| z!pnDoZN3oa!ppbVHed9+EG%&1R%)Av;#_##%53w8aV|V=i)`~HpG#?ep;ME~ZS&PQ z7p`rEZT`sTvZ&aJz{R%thR>n2xTtJt4ziTh+2)(NQ;FkLZ<}xFPGw7T$ybAIzO6fz zI8KeW`Ht>Xwlt4?U1FPub*B=?DQcTP@j2zq&E@5~&Nly_?!Xh%ORkXX!%}0v8iTNeWWT>SsjitBgkk-RPg0#$$oxIz0XG~-!M%0XlvV2J9_K< zPy9YslkW0nh7aaX^0YrNu>I1^uN6P)=QdS0M4R#a=2H_wYuOV&ocYfDdn^4+Hy*-E z3LEVyzx~hGTH}{Jw8ZZPCx($~8XXp@e9L|3!pBZaTh6{_dIcG8G*U%%n7&xcuF-hx<6&O-hTxALS` zzOqvI`_Ab`Z0cguCIZCLaCY0=Lug^E={khta);%&zD8f3h}rFY(DEF*dGjh z^1%4~iD`beFEzqjidx3|uFfrf{&#yC{oYpAHiS_d0(`ni1n`x*XIeA2Y?|t4RyDNX z)KrE~NNMC>P|v*a{R0ON|K_iLDv!CxzYtw&!8f{Ve|o%lR3ciKj_R%uDw`&jL~0}9 zrbu}~PHqu)a0r#nE1jG*DKBf%q)DOKlS6qE^Tv-4PVi|T9Egj%z*CQO@< zIbm*DDI6NtqD`u94vnoG7s{MDbJ}THlQL(7$|7sRO`)QCtTJz@i_|yMb!9`eu^}36 zj#Q!DC@+tMYik=;GxvfZd`dz9S*#r64I+oTE&Xl|Q!WobCUe@VKt9s@6uxCBa~>b1 z4K2~i2ql@P*)TE_x_4Kl*eD2|p z@}_8IX{5F!vPwDGv81WGW@Yo@aIK4pQ(|e_BfvLcOK@-oy%yfa2{cMVgd=n$o>wVp z$qrsY4J#9ef7IJ)U$gCBPI~ss&Z!?i;cH20qDYU#-R_hwstavyh1HkD9+)y=;9nB>jRL<};9nE?_XPf|z<(<6KM4HK0#8TY zQMkvGjrfct8}XSc@Yw=CSK!qGzf|B?2z;}^?-Tegfj=$q*987!f&WV2e-}7yLdx@# zY{X{*+4yA%yiDLL1%8phHwpYMfo~W1;{tzC;4caM_X0Q2V3B^CY@~N6*$8*Mz$Xek zU*L-czD(fM`?hdBiEPv>ULR4$P~nqN9Xc|!SHjY=ip<50i=6Ea`2Q^b7r}|TLB3Bf zKi9{mzK>Ot`0_My>&U-0m7mae5RN9EJlW8*_sszdanI!0!SW4Zrj9Yght9hN|zYxbH@491?Zje(>%} zg0~zu-+Kvovw^AMX7_W}-$<(S&W0zC#%lvFBuR>`^R|PxTyd9|I`8k`$#oBsLv{sz zYWx=U_vWWnUY*8!3cQd?5Z9M$ym!GHpMZBAFia^nN~bh*NG3}`vG2n*JvOB|1H5cR z_&5O6hap4l-d_ArN8S0(%Ln+^e-ICk9rj)P(CoWrBY1=(dz@)5*d+e|Kb5x`JbGRe zPnKCC-X8F>1rJR#H^h4fKULp{#6!YJAM$}4;{66cl{XfP>nMH1lQ{7{Q)FDS843?w z6K;st7kMT95jY1t!bu;hHa8@X1`qLd^RF1ZMDxYdz@zwvxKG9|0`J@6T3Vp6vozj` z$hYb!q2d~qg5O|n8{x}GoINH0V%a=tj1<*?ZL{jJQfp2EiH*E2J=eRr?e zCiACTW4+m@?aXA?_cm@B5oAw3^1zp<|P5$t-?dY#(=>jQ2Ftv|tj z>e?W*lD1od;Ft$SkR32z=XTKi0QR4tGq(Q8M|NyE=ir?C3%@+7b$r+;85A~4&RsF8 zHMZS+D*JkLx~~ryL)r~?_cO6gx9kf(WtcQuefKjxo;s<4SVjVt?XuFI%HS-PfE93A zsZYhWQy2&#=IEF5-Ot?etb+_|9o9;zT8O-J>Uy9uxO>~YmlyX40ix={+YFd^hJ>T{coeb;?7PW724_1UD5ors?ZNFBO&14`+1=-#CTx){3mh`xdN4u|eN zzB^v)4EA?8bnp4-dg$Kcb~SYGG2M7{HFWQJ>3rzkz7P_;MX7LZo1y@kH*)zuYrLaskx(x0yngPGwk2tM1e}Zq!u+I-`@Ulua93n?pJ=z zQh}rS6fYv`T!@=7ysWyK3-Q>#0_$on#PinGT!_c?<~C0CVy@1Gc+{gY7gF(mc`oD= zbSy-r?!LJYnZqc3-VyD#kdE4{ll3X`k)FnU)3Cy#!Uau~Sf1LTu~c*EwlQwX=qf({ zQGuB^cTyr?T*zhF;MjQ4fSH0m^${(5dMP*t%bxZzrxIQrt!a*UWlyOM8W(FW-CFjS z8J8PIv9Ih6V|imsZEb$IIn3l^Bw#G|)d$ROxg7Zb!h#ZCZKfBQAYNc#MjYvSL)G;d ztT!V?y`e4NylO*<4H{Qb_InQ9T5GP4Z!vhSX{zS6M)rdAR)p6Y!IAwZo8Fb3FGP=M z%R<97$6yWFBWg%xL;cE{Re8>v-rR<8)x2Xz|e~dapbK!1>$(^Tv6Dyk2?y>v5Wv5NH`%Sd%r9rIPGK|~R z`2FqZ#qZZx6>YDxjfJ+Ieb-%g1+ijIi(ET~n~{fNT+8UbiT?P^yUOTo+r`gbeeSvZ zFNir(!^q)1-`7RS9;p==B68h$Pdd#42A7aBzQUuAZ9g|5U|P>xJ1335Xl~KOQ%{|^ zDqz^XtQRjoH(=Vf^{924=5j!|d{=ducg=*KPMB~}z_4Dv{4^&MkIqt&if&#i;?^L; z7>!Jn>qIh)VLb=1)L?2#YHDg)YLC?P)ZwY8r=FdfmpXd@<+d<1)}C?29T-9NuQM^s zj{Ogpo?%nRF=HM4XI$}RV{yj1=b=cANB<<_K|P5?@i3E&2R&NccwCHlWTO@AXIQCy z2WO-ompUf(+U#^Zb|+xM|H!O+>4r5mU(jLlpJ(+>H>4u@L)rNfp@6qU$aa+P}vVAvuYKdg-jGqzmy1OILK`NJBRiZvqu}=e5^iByy(;FU?3?IR0sf z#94ymdm$pCN1}IWNz&c}L#`%zagrpjZ%>L&b2&Q|PAA>IFJRddpO>J($pp+lV4PY$pKpKSZ~ zG`4WY+-9G9swSstat}>T_svyXI0KLRdeYFDvVOU@Cil_gzM70Pccn7emf2sEGc#Yn>!yp@ZdjAFRnkG9+2VJ{z5DMTVLIT8B17$aGuN8HjYw6&bpX`=h?nki`HD zIXkd&h9Jh9uY{YGCTy%PdXHp0&G`BtOqkb@jF;I8@{G2E<9J)(I0B?Oep=^tiLm)u zXpqanC;TtM{=4cQo1Ad}NC5Yb@VS53+&^sYANFZz1}J`6!kz)!jR$VL8VVPk4z36B z=Xzi-qi|uqr`f=K~6Jl zjYRw@KEQc=fOCDoZxQ%zvVrd-8~6c%zaj9q1^#P+)0{o=>3xCt1IUJcewG<=#!;0*%5QQ-Fqe5b&_Bk)54e?{QG6!@nCZx{HGfD!^8p`59;kcQDD&&(A_bKJc^9fagk_ z>J5e|F}=?3Lz;22(136m_Y;@#AmcLb3oc{v2A5IK`F-9?tPjL}%w;SR=}UUxpUYSb z!e#j9G6XIw{-r<3mplV{IxtvgxaOj{la}VqcFqP8=OOXchT;SwemzxNdFbnvh!ZCK zqtPDd^*TJPgI>mwT)pTUJJ$xD{R5$$jB_2)Y&rUCCh1rX=iDc)u#btwlyslakM0{X zQyk0vFYluiAUf|Pm*u#Th)0)?w+!+mau7!9%Y>}z+XQ*EBndYX3&gdI-`62OLJq=6 zeJdf$YjRovVKLe&-82DEd5=MHg$f7{I&TQtDBj1=6zaSIXsdW1q6^;Ko}#bN1+N}$ zBJUGuJX#c|Mtg8S=PgO2@x^m0Zw7eVbrNJ<-<#mwodmB1eY9kF{m~aIP$MFA>)|dz zU+cXD;a&?&^*#fAs%(Xa#~3#{Zw+{JlHl!6QXj)JFp<975QZARIpBqqaOI`Ws|Ihm zbX07ecL2PL6nA;4^CsY#oQ%FrN%DRHUWE)yv3KFxm);>xUss{<%ZD}I!{CK<5@enC zYLdJ^B+2WCzDS~Q_akgI9hu;b0j8V%094-MBzc#Cr?zWSudeT_;AKij#eN0X=o&Uk z=oRoLOF^-JfooHd1L$jg1RxvOc!5*j>38^{d*zxxp}|Je#y`nMINXq&g2bX}q}!95 zzk{dxBanFXZm8m^cz2Wf(7od(5wEYpLlf5_Z-~NE*9Pn1h7=y9lMIDBR*TyiuL- z)+oFaJK?n{JlTFwxK|qfHSrt4!>t}?ZU&F;=a6u@54;>;sv(iiHKJhR?2`*`9@YAbL+`c6+S>27 z7Vj~3zxa!7`?eS*f$%See6QVV_{FenHmtSBE4^RccKN_p?)lQTCA3O>$Hv&Eom+On zuTdHZA0F~4n1^w!IQcs~r2SKpSb+9iOiNfzFnHx#j0YG*6Ij%MNc2#Tpn26##sPAD1?38ID+IWsMdB{q>|&9)M|6|j#UgRnhe)@x zNZjmlHyO{Lw@BRbc9T)kEf<9N(=C^BJLx_JX&2d~F1U6B;py&b!L`TsCBCZ#*Pgeo z7F>JGE*D&TRBgfa1TUrP9!ehHjk~-hm8{(ISkLLZelvcnKP#mkCo5N=VG&u`ZM)m> zM?xi4*kf=_SQ7i&&_2x~kGpM6oRY_s&(x*qwy=)gs_tJQC-deNmzI`0gQO+lI_Hgt z(rXy|;@rAxU607_!wFa0)rHqk#Aq8D*%^;k6ogY2)g; z(zW%KrO`@Hhq+;GOH)LsF0HOw&E&m|9dh&q#7ZROqXdihe39_*Qa27Bwor+Jhn8qD zkZp|Zbhc@lO|mSIdlFX8IcR2hMmx1L zGro3mMmJZ_;{UDHlLpZ`-4X9zPH4q{EE4~8$dOqru6ASH71IwG{cU^8#ENuIHwg1$Q0w1@Y^-2PV0moBCgg)^jHt4{EsF zcr1yJ$G@WISX&qFuBh(L)!N;u+rKHK>8<#-oE6^zXNk8hmv{&NJ(hUOxe-*=giE~T zoJ~jWRL7;k)F8v79L9M?q$|~(#=jkR8Zjxt$dvj_ci;6-b7}OpsnfJKAPQrw>w#Vv zbPrxnmbf%l=EQ;eZ;82X&*KYN^o>NiMy~mm^JQ|)H>UKtA(`?^&I_7YgG=RuB_iCA zJO)=-lHtlU94P1M$X%T~rZwQx1(z&Z13up;TiTlM0K3-bZfk3#Q#3hMlhZW0hbE`9 zZ~FB2)Z|{8+*_0TXmVdo?#K4~^!L}~3{4)O$phIBef|e&YpjEs`(RBTqRB%wc^Lc9 zr+>KSejNMQ=YG5{3G&#gjEo z;xs=?hU%%lSLu3Sw1$)0sMOp}7d9$&klfK|Tue45rK?C6`UD)ucoWA_x#_zE($get zxn{c(e8PW@JDKcX(~T|tBSPFiZZ_^8;dB46YsepLn!6>tn*772wZpFeknoR$a{q`o z_Ya%mNo%yLg?%gehkUo{f28n_o16PbdbxkteD77*JRY#A)uO#zzpDC2V@dCsw6>Po zRa%2g4WkA8Y=P$qe6hgkb&2@30>4J!)CDB`E`dKT@D~OClE6O@_+JG6H-Y!2bRygk z+0ZkZY{ZA=kqIvq_!5EhbOFCi;Ohi_2id?M5cop^|B=8y5cr1zPo;bTe;C;ampM6(X(F8T_a__pAhN-qDDWJC z7YO_Uf%7%s;5P|;tH5`W4ScV_pAtA<0}lLkf%CQCCo;y@f&=Gk!4d9IJWeS-8TjKu<6M!n@SzQN#fPjUZYF-~9MpWlyt zgbe>&h9h@}e=g&p#AU_5^e6d}hvMzX(3ngC;d59-?orR9vc<0~;`s=xm ziDlc2?j`!sy+vkA^fo%bd(i1!b=;601>lJ^6;;ANtn z0o&?M#9<8U3kbcyEGtcM|$qG7|4KtjDh( z`df+8L1C!rodVt*C0tq5I*<0s%}#>%M3VXf=+7kzcdr(|x!{GAaOI`Ws|9blbX07e z_x&V!qtRbXMqgW!yu;v~uEa}TQXfz)kHP3y)JR9gepchPffrKT<)zNso+NL7lDwaF z!26LFKk77}EF-1ZI`3rgG8K1usq>bCNBtw+=)4W!QU6>w?*p)ub=$P=eX>r1{0V-h zf`0%Wd8Bq$hEM$~Dl{}@>*$iq2k5t<$?}<0Nd3T5@sGeG{3QH(33ejhCkhWu7dMG` z^im@Ap=;P7FID03_=8FQMr!fv3mzqz;-{|1)_G&W%N9J+Lne{FYK15BArWtn!t3Fv zOQ`Qdg@-OLH>599O9!nh&qhH~I#5pB5HDBbRiEJWmx8C&&siekl!wmyzQV(0hx*=Bcp-(iQj6b* z;8A=i|3-Gg`$*x9>V)@+!aK1O9t(Nlj#hY=B7W$KtP>DR1uxNhZ2ny|NO0z66fWr7 zZ`F{v75{MiyS(d1GIkF+D2Bw!#+K%qx=2(m$?j@B_S6|Or-iubdOdcVsF-p+Hb2vP z{m&1zf4t+xpKtS>Q~koJ6X$0f+B!9aC{eLcGv%IBT^7tMUQ|{z563YV%v&@!r>tnf z{CNxV3(8B&78K_cmKBuDFIZZZUyxT)Fs}focw(S(vE7-MvSkG&3oy!TnM*t3l`NWH zSW-}c*jVN=r^#@-7=c$myW;I}r<_n8LJZxgniL%6V|hVcOKrHhrlEcwPRe7ZdA>}V zx@+(o2j6+9?-MutbeyUqO==F1YDTq41gWm}c7sfEkMFLI=XCX1$*uPG_;E{1$9geV zkLUD!biLZ!<94;$+he-%=xVjM=cV)2-X70Y-T7*7*Mm4i^KysSIf6OW|zyiJ*u{RI~&cMxW~I~b+v5ZE0L?{BX-w%m!r1mm%fq~dDv}< z^XDPuBlXR?Ex4nWm)7aXO!rZSb3*-3GnsJOzf?Z&;z-?9!MrkU9X)T|N2s=g zHrA4IclqG8(bs~Zo@u9xoVIepTKuP-FvlL5r8!iQtVzA>lv&O;qW=vf zz~04wiq{c3@>9mEn&Q*_#Y~|fdHyv#!6et-(ETab-WdI`wTy2M#DBx%K5h57&;J!$ z`%(T%L*om)j`AHV=Ay(pZXL+a7qBdXzaPl(<+=zd)4B!uu1grLTTsVL=!{RlZ1Zsv z&wo&pQ#3i1oh!*)e;QlrlY6k0KH1XT)A?Mkq|n}Ve*Zn$719y5W%kAqOrEjKKJJ(+ zm4iNSehvA-%OAP%d16xnu*sK=8u? zZx;A90^cO?9Rhz$;NKDW8v^I^!O;I3fulNb{R7AbK7?$<=Tw28CGcE<)A{2Rpa0L^ zmjG5(oNb@wo|}y&KtM#mD}sUuCSliFvI5Zn5yGa{5JG@xNMaH;kws8kD;O5{r4@mI zRjX~)DoPbGd?oDp|eiQofIdC&)o_Xe-<-BLk zoLMhqdD3BZrWl8ad$p-%fvVo6f{9BAqWxSN} za>g%Vd^6+MGyX8+&oKTx<9}t`L^Fxvb;w4%{mDkW>5PwLypZwp7@x=Zdd9ahek0>Q zVEl2$pJe=1#{b0lUl^zQg2t88$wu0Qp5lcp#(xzzZdXf&#(5{yES)uaVp(tux5Z{j z2M)Qmn1-*G)Nh73sT*bZg38i`b;fXf`XZbjdL(VMx zRNf!JyMa73lLfcRTZw1#LybeuLXEcw9o<>v!3K}DFmv!%mA4B#^*ziqvEQf4dj!05 zrKe)+@{Yp0XOZGBFBjrMmA3}G3hAlX^qy0B?}Han{N?2(8ZQw_Ky{UFXzUWzRgJ{Q zf~U4CB)$_DsQNuq30?#V!BB}e7nAC~d-21q_xgaZK^=`-5-_-x#yJ7;?@pEtB2n5i)J)L(de%HtcCqto5Py$2aTV`}gi{-0=5<%|`R4 zwTBuL*EToK8L;&E_e{fj-!QY#j5AOBUPI$$jeC1_HI}*mu6z$Az0CL{%5B*-?;+8^ zcRb#`>)#I=%{w+XKJ)kMu`9_2+VkXic)Hs0%`PKc4#kf?JMMQ=zE>7O(TE3v?z-jm zE5_@0_JeT0GgT5S`ig!>ryAquz8w&a%`?Chy~zEntQ$YM+8%oLeY3=PGY5P5`Bm0i z!y9vh!DOH`d#IEv29-IGJaRG+$j?UWecWCqzTO>82Khy?bke8sm5ZNPn$d98D8fCu6}Kndr)oXvw0|~>Zm*tn zs^-fm8%JQrZyRYA>Hzda(X@T zv?SH;JaVwzeabObq+1vri>4Vj^#hT5c}7udYdDD~4LuCrTF~qstFE*z=&|~j*RX@gZ0}m@u6vi%&%9Z*VFJxP+|AJer|AIXi@sNKx+ZVw0!=`y`VL5r=s!oi+2jUJbLI#a>!^T> zbyUE`Ix65|9To69n14U>MZY=lUorki#y=z*c$mrsazsBl0~b*}&goT&%}~`~=(+!jC2!^81ku{B*`e|2XjJj8`(gnrz_f z7{7_}yBWWa@fR5X1LJ>WT&$l$yq!a?oNi7F-!UTB-tlcr>*4SD_6}=^k*DED#>yYJPQ@cG z>PuK(sbBm&3c!YBkcr?YugTqjADtJYn_&P{-Xwh0iMm@O>b%{k*hSr}@y2QLdM3s0 z7uR{C!MjzHMNXafQVa6(wRk@UuSk(6vp!AZ<)ObjqVVLU&YKV3`O;Idb>4H}ou>H9 z%elBv%Q>lqe(?)5UM+YLV7j>ofGV#6ydgRX?yK-aRazsx9szHZbSU;6xJH%lnM2^E zBLW&vMpvsa=$aLK0HA0+6G2^!>RoVTcyb@W4=UpI|6;mMpnsVJ5bqWIRCyy6d20Xp zdm0Z1;>PSh*LlU@O+r}815{fWikIH!YP`3AHyars9?DA?;?X#{%KI3NASwsqNt}54 z-t{4nBoD70VTd^30=5@QegfV&DW!DOJ z^Vtnx-_(+9Q^=0^>{eyF?EXHRWe-@|xS8^_tB-NlevDQ$uH8Mii8xdYryxZ!Ti8|wPQ&&-_%@9Y-=gu2D8z0A#YVVX;l@^Yt7E}5J^dFr$|B?VKm zb93{jPcO(RM78diO9Q@VPo0vVfk|WLvM4wcL%-(o06bwvVPT0Y&afSGg?WmradqvA>Gh@cOX~1(bdgNH@d&saJn7D=TmJlMVsjw4`4|YM zX+7*FV_Np)!s+SAg|$}!DE-!B3P35h9#?=7NUgO`0Y(}j$NHH9j4~X@dcp(p(v7fV zJ?XnMj0DHp@49mfvyCo}g-Us>pZuSle&~%=Q<8oYNWPnUq#8>mmSDF=+xof8rrN{2 zblbAV>rehoG`?E zQ>T?=Q_;Qp;JqVlV$hIysFE= znqGlqnTtWdz1-tws%YBOV%*OBJi3{8yV#5=K8pMK0~alrk~?+UG;m9(8lby+59Vk1 zu{~w~>R;h!ANed0n_CF^v-77`Rmw-&vhI~BGp76D@B85BA)gLda!Vk*Nu3Eu?Rqy2 z6AGv2PZsfu$M{km70>czfn*I`^i0*GHDCNKAXeU+#iccis%y*7uCAiTZG%jLdW$BM zcJ6auW5LegEs|2*TXdb8|G3S)>H_I-vyJM$sI;zbS#|Av zqy_mtUnW}3_pH0p2Y&y$+1CW~EycR|KGBcww4Z$R%ku^v=n;r76p>O?$Gd_G`+g5$~d~eiS9w;!_PqDh{ z%MTHM)tAqWx9ZDhdg+Ka`tAqe(f46~g4GdmpXZ5geMH;~5LVClu;ZTb;fMPwtG>KY z335bS8MD3b_kX=G;YsVnfT|!_$bcBL?Pur6(RFne!7BUYUG+cT^n5Uw43rj1mvW8a zewp1>+U56SKgfMK5GcVbvpA#gUN*SU+PcEb59c2c67mlSImu6-x@61?B?>Lxi61^Y zkehf*#{6L3aJo`Ir~}JIB1bDWnX}}`!U(=d-qSp-N#%m ztaYZ2G}$+Xw-O_=56wwKf}LKJbc41(?byc45vnFM4fmr~NV2M5DK_qWoScN;}j! zy*gZ-=nZ-Vwsnq{>Qq))TCq5~olDs^&75F6HwL$T^=OX!^16t|FXWH}UP{6(2QHi* zr26sqc=V#@C!R_Bm~#SLE=n?k02 z%^EA&bdoHqm%YMDG~Hv%Qq{uvWWW(z80)RxqA(sdPeoxoxBA?WW#4bE7T2dbNq?R@ z`rBLGGBMRM`B$$axJ=$N(?ps4)I160@a*bCPEx_%|7(h|-*gq@Goct8g<||oD8|Os zLB$BxXx%$lF_Z`U2~ndBS~)0ebwZ8y1|Is5m=W1=8;OaRpQv!!vqs~$E1t-K$YWd9 zThY8zX=r@KTW_`Oe}48}JUN})xStvItIGY%0{Lkrd~cZ<*z^TJ;U_0gO3A_Xkt!pt zmGYpbt2A^i%kyxopX-qG3cH!K?_D>uyV)blr34%HT#N7OzZ)FW!BLsC-bYGdl*w>Xry8Fwi62?sEq!LrKc#x zks^!ZYfF3kO8;u*9)cdEq{wXtv3Ac+%uE^E+Xd)0Va*dkJ`n0^j7SkTuty+lIJoRH z!9Tn*(LKB}DY&O$vU`?giag7*(|^ZVmQ+_uL+=873B$OZRCE>3pXz97VuhzVSenD( zuhxGjAR%u4XuNrn9NvmC>>iit4XV<*HdiK%J9;u(95VCyG*ad9V-A~8xzW@YS3V6{ zMDewbEDGVrKz-7Bh+q#X@%q~}vg5fP0PJ)A$ z3{x=8sF++c?2h;$Em%WK{T^6qA&fi|loq9vA@{Mc#|W3}9)xQ@ye+0I`r+L(LH+Qy z2CMpG znVNfq<{qiJM``ZSntP1q9&6kah<}{sK2>v{rn$eRxlh;J-`3pYHFuWr7{^cV$L{FJ z{B6LUX#6waPB3U+05bGGrac2_n2Zd)f4ieTpmphFTz}h`#%@=>V^p%6-iO`syu0Gv zy#>|*v#}^n*r)`BjfHZ5AiO)3vN8XQ^^{!@SRXJFME7CKV;M7Vae4*{~SC9>S71_Y=VElf@f5N!fgBbGP zV*Fjkza$%YDw@|MCyi{#sU#ctYR1yj4x&U3dXNt{QHdmi1CLQKgjs+8GoDcX2!cEy7BfT z8|82!*+|bg#!qK_Hsj|rUd8w(#=p<_4#t1Z_^XV+#`s?uH>EQ-FUl^jd+KUjd)LEd_3cG8Lwr0DdSf$ zehcGwF#co4pJMzO#@}W9Q^vnwoW5A>lX!1zya$APD7#Ug3pf6x6A$&Za1Ud5cXkhF zH|k5_e+s)%?+G^oi}0wwggb-XsE?qA;_PQcCEiEEeYE>MVFMIyED9I?h+nv|k*#ne ze&O!RZp1I#{n(B8g}Xny5x;QbgG7W^;ukpL6*l4%HsTRB^eg$;Sah8$FDEg9M~ ze9q)qHIp(H7eG;;$y+J^*Hv}Yvm9F3O=54@T@BY7(|-rN>=w`#m=Tj1^0c#pQgqp?p) zgUm0ri3h_i4f&Dz4}S8R+}+U@?j{!Kk;^y9AgR3L@j@>EgxAYy8Rt`J_aByYH|kRA)2I+@Tn$@&Z}%A??>Qeu?(_WlJ_xq zd2Qg09nv=5#cky6Ya=g&c70Zi^qr!WUmkc7g(oj{-hA-Rm7a>N^Y*oo*B9Rz>V1|$U7C^OH>9nkG7Hb5qO!pFt~Mj{nOp=X`QO`rhwNLd27K#QAZik$EobIcMo_YqFCsoLm^uV z{tkF^(ce`KYzpJ4urC7-ZJ{-inm5|tZ%$%~xY!0>k_2EEfk$`_erQq%6N@)n;o(!i zMc!P6M}78WV#!;i@TlLEOe|iF!b1~9m{`2!3Qx9YWAWB1JTzrmly`-~Lzjie+o6@; zCh#czRDQBqN%88uUEpOguM=!Cv3Tz*JTyUtiNza?{`@TXQoLORE4I8v;7wv)*H(D< zDLm3AGO^6EA@6=X!Zz{agTH(E~ z@Sw87P&)K@4=Frcw#fTT;eERmo&isp-|?;R5*1#S!fQtP;dSP{w^G5A^*7Um)y+bm zHm)KJo&?^dz*GZK?id*C2z%U<<*ub?r?7}Oe{re0ZE4(dzcR*+$rv3W6Mx^*kC8Sq zBSk6(8)xIxyuJ7D=s)4Wq&o*JO>WxL(D{W+-e|sM+nP>I+b-_fblbLVt8jvs*lUzn z1C}PfkkquZq4}17ZoBPb>DRbE4?dCRwW)V?O`U&N*RiFM<_NAA!_I;|6ZTx#S*5kr zk>)#a)f>n@*yqnRhwOR$h86bA?TLGOHygX3+4FSc-WyglezGsM@!*@y;iATm_odFN zZUm>Xx6!=)Uf1^y;p@Qnj?_ujdmi7mVtbdn2lqC1L&j+{_dLD(nZ~`_AZ4xKg}_^z zITVd`wfG;*$vc?@xdJ%-c`@=@|;~#JMD6z|trC7-pZPFE(^3eY#=5Qgd3U z^vT}M|FNrqTf%p3s2XeZCceVu^+UX|Z`5 z2$=joFC}ksc1iKHf{7FJrVhbk_7yc3 zM!~eZsJSQ#&YxL~4KU3L-6JOhn_!yfN5Prc2-CbE3Lb&YFwM#+cqBH&G#5v~6lt+u|1|)69tdJ3O@6~D0n0`LN#lnV2ZS>W7g>&c^O8kW7bE(nMOCq zToMJ3FuG&E+9-IW(F6O{M!^(m8g{G=c+4)CQk-G*bIgmP;7p^xW3G&XM;OOC=EYGk zsw>A_6$Otnj&sb_0XV;C*5r)oQ**P8fsVO0rdN(J$T2U8^2!vUPH@b1F}-q(6CHDX zl-CFmYOrHo8q+Js7~+_hMR|=Bp-ytl4KclPjG>Nsd6d^E5$a^eydtJojxo$JuZ;2< zEkX@<%&TI0g5Zj=3?)Yn%u* z(lIy1^vW?tIp%dyUK!~k*l5RWi0zkSjB(7((SELajCIT{vHfz4agMn)+Rs&xQyp_# zY`+}iG{?L?;8%@1Gye--@#|>HFn77CB6d})W%sT>})AJ@w&X`b$r?cH#`GFtlso3`m|i1|1&+BV=v7pZT|C=Z?3njN z;nQXtRgQVDj^}`1?U?sP;o#Re<_~o|7yJty^ZqCt{94C+Ab{r<=43!ej5Ut=W8EW@ zJk~nqPjrtF^_(c)%GdyHA@-BAt)I$w zxVo|I?!mA8`>x!r+tCm0zt_7+amggln1LTR1FjzM?Lmo7^)ZC|&4Af(VZ-4kMOu-* zlI-G=ocxIeQ>GM5nTTe9bwKsWpOQygUOyGs+q_3z%9ckCMCt>AMFtA0upM6QlA3yK z@l87p|3aq07>))wr|VyxUn)GksPN%H@NfnQeNF3)P6u_br(oyS%D&US+wL2(jUCAL|ctuP(c+x@tki!s!(km5V)x`&jSFo%?JV zt4KI)Jlx0nqvu&$UQt!y<_TVjeXI{WuX#&q>*}S%%GwlF!1t&=))$^HL>BYSn9iYl_p!c|{uYJS2}k#_Ow(h?Y;x#6eXNl0>E)As zkLhD2c)kIJ>o@+c51)N(&ai;SB+wI+EAD7fX>I9Z+Dkvll**+(HyesC$-k|-J{){* zq)_*{IT4Qq>*w5;PkH429}oONAT}o=rKpmBb=vtC&0Ib6FG0ytfGe50WLUDg)wB0R zc5=6R9_rIhH=lcH-@1WiL8&ruRC;?~|HaE|Y8pS#(krE?>Fs^-Z_>YAf92Id$x?tT znYw&9z1?PS|II7w#x4&?PKvYVw3o4@w(U9X^S$kO<(9UC{iLXSPWvI^?>X&rc7~o8Z)5Ae@wdbFB1-f^ z^$cZ8$*Pi;*B(p`TkBpA=0=_;8l|Li$Lm1ilH~5$G@!z{PO18j5!mZ5Yo(AG|S8k8NjO_|$pHuMg^5!YV%r_NTlgsGHin5VsBI(#K< zH=-P=_2RZisjWwu6}b(Y8#JGGQZ%=qZ>4>Ti^MU{vZ67qOD~e`Hfkw*xOpyM(GZkx z7EqUat+*ifJi-IykU2MaoU}PljYigf*lt@!BVTJFb6Ox4pX$dVxsE%6xTd2ul?GOi zKuuj2&{Wyj7urfW4x8uu+UohXtH!R0t+Dm;LnWw&o-TPRYx+7Pu^5^e5a;WgCr+vx zc6|2~U1E-Sr->zG{5onc#RyiG-#s!_aAH6O#rHYsALTY|Zuiws__V9)4RCiO4Az$B zx%J#pAv-BhD_-o@>|WgoHPPxmFO=-m37PXakW@G48p@|QcDY0K=m@RKrU&$h`bx^{ z>dNax8M}2^y01*Wce`rT#2A&Cc`nr`qAy2&n49K#cqay+=sHUY#$Wl+IxiSQTsKv8 z^y`u4;j~vRco-XUw8Y$38qt#`^og;O;pq+)m9#WZ#x`}7?@PkxxdMznD?+pY)E|=F$H$ z_O@@m+)QuuYll{n~`(aQnua1e!thxz&6XT7#2pIl6zVSUF`)^tps_|$-TJFN|F}} z2OH+TX<)FzUOjd5S?*@2Th*L>e%Q)9&vC9Ro>5SA-IO9EjFe%EnlR(ACCq-FcD=rK z$`fat=@!^1(OdU2Qb)=;sbf{49Up>4$PtY95H!+8td`T)G3^UyI1a|m?F(^~wBwv_ zC8yE<&OJhwl`?haZP;Hoe+D+&HSP7GTOH?|vz??n?Tg=qvc0$Z)|t&SZ*zD5ejU<7 zhAg<|4l6j3v34vt?)5Xxfym%j-N%(W3cYB)i9|E3NDv7hi2>_qfQK z+~Z;Z&t&&l{mX1oSV!z0t6z0*RO|q%Z?^h%?k>u*+hym{c9V^LOXHOZZCHC1?M538 z>>b1sv+nPFZThnlGThjz@TT>w_(Q}GDP?P*!PLthTPE&%roOW_| zIqfWWIqmY_vCApdh|=`M1wI~NLgFv|q1r{7SpHOdNfXOIUU;f?q=^-tY87dY!-bnZ z8ey7F-}(+9p@F4=6`6AxB(uMdQE~% z|BIh0W>+44?gm-%V~nI__ro9TL1*@Y?PQ||YB8oP)f$OMB`0*U=o=>P)}SaJ&&Yj2 zNg5f;3W;GPxgLkyv=%OlJYmR9YnY0K%XL%1E>PSwB)vj$ldQ`XH+?8g@Z1RomVbEb zi7lL;kqdXB;(rFNrz-BV_?j%+GL2aQw`I8Bv@S^dfL<2x4~f0fBxGYB(jQ3&Y#aLu zJ{@o;7;gvMNt!!ZbEjzTPMW*3=I)}oyBdE9#FwhMyJ_z3n!AVQPSe~yHFqz~eU$Ne zApYK(`)JMGM{^&ex%+DFenx_#fVS1&=oxS)YW~M+?uh0-PIC{?+{bI~fd=g_AdPLE zp!p9nh6Vgj)ZBwL_Ylo}lI9+&xlcB}6_7tna}U?tr)chU&7GmSGmS!)Pc>|J=sz9o zO~!RQMjgAU2JMdLjn?y$p&FO=)!fQ%dIQkDncLY-H9GB^NxZZycMWe^4)#hUHx^`3 zr$`zeUV6UM@~E$XjJsdvCAhMY0AXWssIak!QP|zs#?b3q#6!ekvN4gRf^00FooC|W zB*sy}2pq44#pDmU7qWd0c;u!$lf504DcQSWd*P8#5gt{k2#@rL@UTTV*t8!D?X$Ux z!oyy#h9Ab^`*V2YLxhJd;)gBdz|NuYuxVdJFaF^i9t9`jNB%{4*mEgf*z?(@Q`^X0 ztcE{@!$&wg%1wlaeJ+KAE#$ynNa0~GR>P-r_~SS{%3FkoO>VF&^&h#@m~0ltW*#ksfqSiu9nXP2dw4FJpWO<0}}yn(jK9M8`;33Y_{n%&?c;f0N0f_A>J=aEgSds7sw>Ex zjUQpsNZu#_DsL&=eWWM*QJ6FMTFTo5PAqxzHQwFerI7$OQuIY|)3ubh502fE#D3&# zP_D^+zJ>2})TO$)9e|WgewCb&QWIMJSt!&{DeShSnt@V-F(EZWC$c)2J% z(GHHoyPn$R$g^(re1wiO4AEZIhnW-mf>cf!7u9 z-QTu>_W^h}wt=?}N`FHeczy6bAEy=ohtcyf9q;+KV#s?Cm>PT}zT+k-ybxdOJlaRE zExi5U<+VXx;z@0jR|H;G8{};QZ*C0Ueqd^T4}lj^c=A%`r4Eg~FQ3k=$vZmfwHCqwjOw(7>h2TQEF!IqSR) zZRG7}Bk$*JPX2jHRVh%)~MVk`U9bxV)EPhEE?fm*%ifmakV#Q9L;St@-W&^tLviDe5uVklnv zmO=M|Fp2m(8a%vH*Dz!}3W6GraN<#?yo&z43h!ivcZ-(a2zV5p z?k`?p!jN0%4OVz~MYPCES9qv0TjY&Zc&G|nBUovXg=2p-DBE}DJ8{I zOU}-pHkJ0sSgHF@n3kVk0+L}l7GnPvUr6b;Ie?JJX_NPjM%T8TV@AEv- ztuLwf0$>TQw>Z8HOX~e_UMO`*y>e^SHS%64+g;wLl2Yh*<63hBfkDOqRE@z71>Sy-YysB7dsy2y9DHS#_? zka-T);u?8BSiCjzKGR?GPH!hp`RN(YF6ZQ3=p95xBU68t4XuMU})t!kGy z<2)S`&QA(k$wXUQ)@l!#oG+DK~IWFbYl+*m_zVWBz zYLi)m(@kxEx@pLrZt4W5n}*%#rU`PoY2ts!bW47w9EccL-TW0QQGD;{ts8}kBgTk}s5=QBu( zZQ-18>40rpos5eD?k>ia0e4q#?0{|o&G(|O898rj9j@5sXh@d^Y1^-W2#t8NY(@Ysdz^i}9Z_{utvg zGcL}{h5SD;PUmV-ymSUN#VgM7g&f+Yknmi_Cz1_(4&xUvUd{MbjNiie9gIK0_{)sH z%J^rDC!>rh-Y#TA{&8d@-VuzCVSGB{<&0M_el_E_GX6crf5!MrjQ^VPLyTj3polk2 zHsbA1HsVcZd?e#D7+=Wv1&ps@{5rP-hp_JWGVhK>oYXoeDKtFuMDE|mVtM!^i*t}_Y!z> z6n}YHh6^=)GzYXodMb96#@h;BMDdrGt27?X1(p5Al0)`)@k13=BeA!@8zCKveJ8F_ zt$QX7@7o9xd<+md?v#q_J^10)d*fImQUBtW1PpGa@hE;Oo&_G^B#U&I47m^Dr}D7I zR=lT)C+}G--dymqz#$$~Rv6;FhMy|$4&otW#6vj#g z#vz4=SB@~m>xQzD;RFa_0*3=Zgdz7J@Q_}w{1U;7)xSLkJW6jwgv0_L@b2YnX@O#l z*LW|0S3n+$A!qsGiUnV#e>-zrrrY7&hW_n+lrb3DzugTbc|6?i{R^o*yW$p5daPD^ zc0HOIr)SqEwykH^=X*V7Ws6F&QE{RewdEA6J-dF0_&vKmH(t-K&-Bs}uV>c}(t6LX z&+|lc&+Z`qo~V7Tete`y>+S2;+`Ej}k zsDAM{<80Wjg-uYdGQ6Iwu=_%Za z8b5*4TNrZhLN@S$WFtMeRI}NOwUir9Tu?G^Nk!%SlG1u?N;q#xJ+`+SUbkX#ed#=7cq?CX zZX7h{+|322k3y7}(O~rO1(l@>NmhNWkX5&cuUaY~9jCISAL%ric;8?y%jNwB_d_>n z0Mz@_87~#_+-Ssz#w*10b)3c_X9Pc0-r^Q`^h#5C*MdjwTHWZp+rgvfS2w2uP~|-W zUWHDAJ0Cw}u||3ggkEPzhhm?DYqhv$gLeloYA56KNfa79zr0hk4P5MBMk8_#ZTq+1#c}fMm(7w;%&tbQF-y+f_g4i8+|8uBtL>5nV*1n zmV4>_rE;ToyUI&IBoBKG_kwukHOm%%l{R|Dh*2X)M##iJ!*BL*Hy+tWKMAup8`mEY zGf>?5CkHV9WbgfSlAQJB_I1fkjT<&^992-gnT@dhdJd|(Qi1dNU4`2?G_CuxVVgW(@I0slDku88Yy8g2w-;?% z6oEs0sM8Z>meL>7+-apupEEtTxUhtde# z?6DG>33hfq8YA|jfo#qiw)yt)yB|6fNMfQ$S#ibU@|@DT^4#hrReYL~y;o+*__v?U z+Y&=RySPiIlLIoWW;dHvoT9?1x#B()YM&hU8dPRvk({cKDp+*8}-? z%P_aHy6gf^P3&c|sElMNEC(NP!)HCe_u^%p0>Q1$AV5pjx~Z5nJvX`lFNy6Zif~%=cn)5FGl_=_1>ym1L;d}Q$;+oRha!kKm zQi&tX>>j4flR+OiTu__3|Dxg_olmR{$T4TSYSY(C(Bz_$!l~JLC74EyZvu)1_UZV}y}VWzwp#!O$* z=HH$BpRK1hF9=97Y4`w&m}^#%BOhh#EFIC<+K?$19GK~ zmk#)qaZ2|a(gP`LC8M|(TTGc9<9-O^ho$VOegByJ#~Ggo1ereu0a?5-DnZcD;)2Qf zIoZ?my$7bQRhIuOENPX8cXckR9I8&2wMwKnx=V!?uV|I(%FH2UUfC*9%FMwD#P+I~ z)C{*lLM;*8#5JvQM56=mj7ws&GJQ#SYS*{Q5t2|<(mq0G__u%M?wp&~-gnXUfxFhq z?ayC|t~=3T?uS!orf=Il0heGi1-ynf_e-kUcvv7ypyb`kayW$iUP z=i;wUx##p>Z+P;PA;^l?RP8FICX-m>82?%Lcu9KCci;cPM8Z9KxIYM8O#1;Rw4k>9 z!h)(v7a3+>`$tag6Gp+itNwAiJ%364ikYRA*>r-V)z|)Ulur)%g!8f|HgHd0$j<*`;yg>IqyDqZgphNqs2R6(I>WTWX|V%gFkUb=KK)xN9KHP zypcJd>7^sy$ebUf^^rNB=ZS88&4m|$kMk49EA|a#%Y_{3aengngn*VP#~3>PF@}SD z4N%7cz1ZTNOXw55e8_P?>M~`uRo7g2Ap++ThT@(}=!f&yTsRY?WL5L!c{D-ImuoIu z%|FRcoH|J9Mbf5o34L}T^YI2L{b1f8B~8QNvXWJ31dzu}6il%^<*4v{dB~xm)C^ZH zeqw1x!&RdK!IJ#3$`-~py%^jK`~2a4iewEO6zyeMKAI)|OQYRJL#bD^3@Jk=Z9B~d zKYYWXZ8*>HRJ80_P1-B}qT|^uVk+jOBeJON(@~J(BRb~#56U#H|DYbXC_+2w9hdv* zG1q^T2bQSFwpxrsx`IU6)N^Pg!!X|OaP66kDxtj;_3%BY_J>k?+yl^-)Rwz#JyFV( z=dhV4lt=e(U)@<`noDCGZ$oXa(n@ZJ%JyH#oUI*ib9R6yTaO|0tonIHwe!)I_fBP^ zliwECWCx+SfO3M+S@XHaTQ^l<_0usOv--(@efj5Y(CVj*u$72((4_j1*b0f#RMo+0YA5ByXIoi)fX)1_=7c0(qHY1EgJ`-SY6VbO{ zKdeq&>@`-hdGSZ~st^2M{YtAdJXT(8b?Iua{@_D<34*DRh#cJ=*Q9=6pSSYXkm)4Z z|Exx|z;5gOf&H|FgaF%C^MSzr)b#`VXC@K^?AKK;?|op6D^~)!Bmw!euU~^}D`_c6 zj=jCgjUvf@GL7=_`~_Ag%I^=;kPP}%E z>mkGZ)kVO#t_MlItkUXDj4wRK_bX+*zwfa!Y;}ijzlFOJGG4`B((R5}+1F93$IT_= zE3mdNsf}yr!v5TCe*!90-Z6qnAG<|U)s#N~)Ae2RN*xO3qiuDGe`bE@J#3+^e3 zdp6wD6n6>Sa}@UixTT>vqBNgU8k*yIg>=BCb1Lo(xE;+M*4zn!H3v2tEb1BrT1Ogm zCu{B$uk0vVS|=*Y(sg$>ei2Ad7vq(HJEZw{)!eCpwLmsrIzf5*ITq39R{SRrUr!_G z?q$#*I~h`cI_F>jy9uLpml^D)$A{LnQu8(qI#2hNY-+}mO-)y_skutF8_bfL}^B_~m3ra4rDjcQM{5al}u2kzVj=z7FwUWc(enfm209 z_?x!N|2x^h|4BCRC1d<@yZf5!MrjQ^VPBvkUmKZb1Zk0l%Yxww&p*OCo< zDcQhxGyW*!`xp-;xcpvZgWrd2@TW6g&Ugjme`dUyahh*T{Ly41-brLbP9ftTK}iY! zl5F7EeL?U~B^!7l*}#h!r?qT^zstBd*8uW+q`3GXvcVrhHt-zAiy5EIcxfk>Uq?3h z%g6@*dyGH8_=Ai$G5$8=?=k)bq9c{!?L#)w)1Pd_o5^?{PnEwgm37DKq`As1k{DEXc&S=I@Wqcar^BG^n_?3*`%=qn$Kfw3_#(&B9pBVo) z<20F>;_XQ`;ysaUq-QAO`HatE{2azlHo(I~-gL5o3HLGVMm>ke(6G~ZT{rxNyC=I9 ze~Fvmw_s@Qeg3@4*^AR_zLtId2j&he%y5qh$Qa>D94Y7H)2#ecWA|IS+q1{)mg>MY z=F~RS+k0BCQ0(M?EjbLVV`yoi!h+h;#VxFZpj8W8Sfx0wc_A%Va91GIESXn@V0G~p zHF*2v$G#D*ta)%(XZUL#T37?&6F46};3e6Iykv{j7Kdr=1U*A!=$jUgmS^NMbvzKd zmb?kL-e-98D~ z(Rq)8H<$g$lDryRtMd9r3TjAgC=h=c=Z0!jn2CfyrDV??p^pn)u|YT*$*BKDC>sW)RqE% z2HqwBgMppEcq;6lmU*VzIDGc$#xM?yRfd|1OS@d%VfQiL>2fQr!5fAAWCKhiX3S$v`iHGL2FvRPn z#d{5SH$d5mCv~29Cu+QbxM@_b#6z=Hm{`1#3J=Xnk2hA6m#6Tk4}%QJ(|N@T4^^Bn z#5+@yHy=F0DSfEogo(wYa{(j|pQ0X*MqE(to*vYL7i*2wh2W9?MBJdpwct$zrW$gt z(0ISX!?8XFul&ODue49^m@(rrBf`XABb7*n0VCH)4Z%~gqyOIfw>M1KoWItb7B1a! zRoZL&dpCdSREsODp}7m|Yb3s=S>kJroeKWAhi4h)bjg0hLnFpxSJT?79sMU9II3y; zv&OzlUjOHl+YTD(jnCY5<54f9HEqZBZL79D+x&bQ)>>`bM*QQEQda{5J1mHYfeJ3v z>O3xwX2scI!6&wD9+%ILnk+KdPqDhgf*&IOJT9LbZyuM=^wJS;9+w}a^?6)A&lBDH zJT5PQsqUR?#hu6Hhx7N&wf%Wqc$B0Dl-C|i4qNM99|Fh=6_#_t>AgOBH+>GJAS#JF^sR0fv}M%9SjzAr*Rdkpa^yOApEvQ&1ikUKPni*1ugM{|g z;o_J&?DpV!6T(dE(u>O6Wr&yowxryUFI^~h*^07Cbc@O6N3@Qf%fe){g=UwjvgB-T z2cujt82f_C(dSHzc_akx7K9}(;ok!~W)hYEqVgsn*{>Vj9B03ibk2j0b0A>dNv<$< z>NUl>Ie!}3v4=0UnV5#Q+FpL;$ouW3=Z_BKn0C{QTh_t(E>o|Q*%hn2x;+6PM?e}mtH$6H&`K(+^=K$NT6>}&L5He zHx|bCsqcmQb;yt#!%kl2$c=7MZx0=E4}yCjeq_i^4Q|R58FFX9K1H}(_ZVEuemwF& zo&Ct7`5n0dw`G(B+_teY;C3{3SaTdcwA?o|?Ot*C$R2O!GIsU_L1< z&G&G-pp2iXTrJyTo(9}vo(Am4 zpxWfWpEO;DhhmBF7#tDd5uXSTTZD%#!o#L>Xem8)YIuwbP#$b3EIp7k?m3KX;Nux5 zT_SuY@P{tn~R_e=49&bZi<4e>@$K7@-s*${6wxq;J` z1%!(|*?@~Z*?@~Z*?_Mhf8b(IHsE4UHsE4UHsCL^oOf8x`^-cT)O7hU7K?YGCht}7P>n_zo%bPl z=SHzGKLMDUzKN(S+rp!HVW-8Aw?>oqd+;h^@UGH$6H#YJ+Q6fEW3hNQYVv44*~u~F z>AVM8;58yFURgC##2es^kPgLu9M^c&dL|7oo(KTyS&uME@1m#hgQ`>U2s09GDX4V7 zB*OJ7ekz^?9^t(eJQi<~!b=914DsH_PnA~$9?7B~9#LUp@fLxX1z+OHIwBTtm%>XB z(%g7I!?hak`@}=JkUXjLBrgfdr}75l-A?62JUn{B#Nv%rcu;MR*GH2#N#V)ogyiYG z*$Ph`s~)DwTLd13r}W`c7;@{p8il8hRZ}|?r4LPwNZQUYeL(h0;%4Vcz(s8pe@yDv~KGuy*j#ZDssCDC21C~ab zwuB>1#&velmi_~AJ+R5dRUb?}Cg1)*8habf{hQK&y4=Rz|86#}lkCRcUp6y;ecpZw zvDFK)6(P2=^sSJ-RY>33zwwTv(A3=7|0yv4)BKd@Hir=MB@pZ|nt0&OJ-wR`?S5v@ z(+8N*c$H=Czv1AGZurLargh+kXK(yD!hF`8T=a9KIsrS5Ry2nV`YLucICRpm+sd{K za()s4B$S^@+B}v1nARL;LSgpwNhLYiQ_jRax6a1m3ixo)A=iEW+xyec7#{)T1+^y7 zT`I{bt-4^!lEw4HUXAC-NW`>#4*h7)zZ|&i%6onp2yL!}EJR$RL|jrdYg)Hn@^a>2^CYWQ_sh;LE|^K%Tv>I2E$@EOdDCN8e>hHPT&$EARWB=dx4W^e zdYMr1PT|B?uRibN6EAL<5=?xFoA_0njG`IX3NDcN)w&NS5NXHLM12!1f9n}D8(!VI zdQw0>7j4m!#WiXI*UH4SG=;&-;Wx+sx(x-}8@G)&g~2O2yY(pyKF<@~`VC+K7tk{MfWs=b*dWkHKE}vXaWWuV9x1yO_+da zk3da0&(nm8stUQeE)_B5*ECOcRYCD!XIMzs= z!f{?y{Sh+f%D}QpK{cZUmMuCbpRyi*7RQ$$`P+q{cMr2Y=<5!~Y_Dx(WW9+v+VvhR z64~%4iri{;4q4c(cT{!2)BoRx56z3D?Gyf7d~Q4JI_iq?Z2$Hl1%$Pldkiqls+@? z*K$(B_|7>zd+fLmjZo=!eQ4Y^Ix-oYE7Y}(d+bo7Gu9qEz1tX`-rKRlPiSL!s_bR> z|D}8Iq_ngLPdD?*ESmdbw&!H1;1)hsaBh_C&y5PXbEBN#Mmu45s#JoUDwX)(F;$AR zQW~0>fu;hC`#nZiq;=B7@+Ym5W*{!y@bpbrfak<*S?FIQ13VtJ_I;k;7$u3vdn{@R z`YffLLbP_9XGOxvM4xr&&XaO|$=^2IuPhg_aUi@p-fCl(Wze0Vxf3;alD7wt8-KFq zPSM<*GEYP&E3yeS z?wAij89{HCgT?}zMk>R8E<6#5yl^9 z{0+wc#`q_Ucfq}`X4GX4tVG^TIk!A&O{ zWgy%bFcxm4O}M+U8)3xrh~8#U1Yful*$uvMV*pzCD}2e5{!qJ?49y#xlb>5tH)olg zGKDEe*u-POlBzQPyjEX=wADq>*MIdz`zbHHj+-VH)h7`BDt8e-q-%M9rM}ZZjn3=uv0OiL4$^qj;HGC%8YwRufGTet+}B7F`;qfJ<(k|y zZ}(4lK6OLyIVqd`K0}7YyI3RYymL_ph<9!r-uZa9i+5`rUVSHihibfKaI5Ki33cUh z8i$-Z?_=;V#XidDynmuDq|^Cyqw{E=sv&LQ4MCgcU0oR5>+w^Ar}n_RP2r&`6-MV3 zwUM`}1>Pn|RpV^}FXBcO_^a~{ffs8Yo6ajlTdgg;U2Wur&~}>>NSW)n4VIdZ?|@ek zgV(6>ehyxw4ZQc-$P1%w7)#zmTD&KKH#kPTI&TViC$xcA58jC}c)tLK*LaQex*5C? z(xKSD$2FQ-o@oLv0)V(Y{YbpS--8=f05wa6IfOO}Uhe^eM_;u0Rs7%J5l*sFm>r83 zLPvw-;gJ_67O#`SQ|G58Knc`%)4)U2B3`81lc)1e1}_V~ls++d4x8fDd6f!}{K>@P z-L3FsdWd(FmcEa`y94D+@yhC#c!M?GHTY0S1x`FvNy5b9-JGaTJY~8hMs_WDc#ez+IbiyON4lXJa$cnI2H|CXX$;=Nnu=;=x?sec zFE}m|Nyn_f;NM6jbM&aOZJjT;rN~W{oG-W)yNfkmm3Lsk(%zeln|Jg#hwK>ExT~@E zo6YIXeVUJjU$b@E%o)x5_Z|G%&Tv-qX)|f2o|s3te!x<5h&}TzbI%>eZffk6+kAHO zo`&5+%}tFbHr_!J_9U1|EM>hdq#W4y?9aA$Ic+A*?;{y|ckk#=QYJPVH#cu;+|Z}# z`@>x3+08q`ySlh3Xj~7uoA>YQ^ZLP`H8vi2?%C&e_TLfCMi_h3X*17m-WlHW^zLW2 z0CN#Hg^z6rV=khblf3<|q@4{&=`a&%IlFnl(j5(rIf;w6uWxLe(cJxYN?Stpb`cj` zNFn^Q$e&{GBoOi^He6uCKRaP@V`J)TZux|(Q(xQDu>XeL4F_+a-0kSU9jBTn&aKiqkk~%+p(`uBK9Go)Fi(~cP9aR5$$QfwHJS*yhE0IhjRE1*~%SC^X^dBn0IJL z{~b!1?ZBK&sTp+V)Kp+cBrg@X_EJGQMY>_!yr*H;DMC9MNiXOQr#I&}kAj}KcV|a~ zJ+sl=eWi#@!KU zXzq@%Swu+cYx|!&2wtdkN7w?gBTRD5A$iToO(Q)`cO`EL4}e_k+l07jrn1|*3cXvG z9y;!%moJUr`4N>iJ-B8+{Kd4-Uxa7pWKSz8n1bV3GibKwFBO1JS+<^5fDstfv7S+Y zku=lupaP7-sh`%f3NRXH2V2i6z!)5sY(1|4blSAlqyXb^%BS^$0^s!JB*%JDMKW-_ zr}dJGWEv@s^|FeLFgiKbuT*5D(b=(HK|cpdfJ-MlWXSmq3%@liP&&3-D6}mHrqrVQ z^VhNv#dg@TU<Nj7U6U@F8 z>t=s7awqTLw|~^>=Ca>^8Hmrk#LfN|H@Roc$SxFTIaBtxD%gnW*^`UtAXLZRrof{a zMj>3Uz}a*hG?l^)Zj+2t@Ys8QAHTfYi?MRd2OO7`($_nm!hGYqoMJW8`F-#FxpV%s z>w}q=lHE*Go;b?6-Cn#u&06+AFw>X1nf`&BaMfke1>I=31pQ_J({7FaOy-nuG6z~3iI>mUVlH} zlRw4vK(_A;pf=lwVa|(>&f=Kb? z=_4}Jb2HP^(<2i{L~>8b9Xd3UTRp#gVR=<#Mpeb~$kNQr;iHFV3@+bjP{5mPZ!-$8ptb@+!x{**&45%l#p-23RBEQt*NN;Ca2RhRC#Qqtimvplqj+`!UkcIAtA@@lF8|C z^%-zvs!x7P>LXfUq&$>y)9e#lc?7F{RcAyD)iKY#a7k%p#exdAp>N1`J9az_>W{{g zt$yb?%9+ur!?h?Ku^xeyP*+8ZuoI=Sp&@11G@tRb$M%(}&dIajjbX6Zp=PUX^88*#5@=a9adA6@QyczTL14SraQKPPxng>XE z{gA2%hEx>1py-W8YbUbj&#yIP6FX#119fs~-38wJ&G|N|l#$orIu${zN1#qkRCEd* zTIIF1OKR$iaJ$Gv@H5Risa661_SLLAqczJs7iTje3DgZLyU{`>>5`&aMLtJ%z=cd? z2i>QJ>|b>-CBkry#UD%u{6>$ymTwb#rlLoAvTN9D?L<)2*nn3mQjpNTnp7N1lb|#O zQw`Y{jRtX0i>SE_f7yc#Eo*c2{a?)72dK({;O0!5z4F4yTcWV;ynTt>KLg|3$<<_ z?ag+YDZiD4`o(0oubNGdRx?elxWzN6!*%22BU3ldRCL4t;6h%-9DdV$Uw#`)mGDXJ zs|wxYszS@(ThtH=d~dl*L|<#uu!LP^$r(!d6cdm;w!0a#dym9=rkkQm!NxHaGi4fE z3CQNE)Tbb^eRb-Bs8+OIyL6+J#^09!a}F>^l`kdfYq%_t-DS>n6@s5FKsu8v~@pbsC9IgiEi3%RLkv))WesyXYB5dbLyB`{XXqC z=7YL0ZR>8{t0wN#{)aDdd(2*rbGlNrOPSR3Xe}}cpaUO8Xlh*Tv z3{1chdf2mrliW@Z>+*S}wZs1(dtU-rMRoN*Gw;pI%R&MH*~LfLcL@6?*&!MhlZdEj zNJxNaNHBy=QBY73m)fxChgwk~5U|=>YwJdB4QMH9RNA`Wj#VpGtGF-u|IVFzXYSlL zFL`YR`tkoRe8!CpYdcvO3{GTwdtXPXO?ZF9fOD=jW6v?o zF=p&Q_WQnR&NO4+58$h7UH_?_Tq?ybC$1C^(JehZfFnk9{SB5V(UCPBmqa=J%rWZ7 zCO!uvlfn)a-6ic+!7TFO-b7D_}mb_ zigTN4@;j!QOv_YLz-_82W~7#jkB5Vn#im$cu_^Aq!(tPS%fiw3glsvEaa}kXcZKuv zr*Ty{FMk>@h4bofqvrQN2FI4 z*;XtIPOth!3}NqX(`>d3S*3g5i?ID{EIoLYvC0EM0{61P^xRDbOV5M|=oA(`PqBfXoBM=!3W4_6WxTWV zOE@QIWWYhjh3D*;*#{Hf5F4R$q$qL_A;oB+vDGJ|S;X5dNM}_aC9df0=v%+^# z_^t|ns={|u_|p_Vr10GpK1JbsD11+a@1^j)wf9~5>7(#{6~3Rs_gDA<3O`Wc2Pynu zg&(5uLlu6Q_PHy)sc6HZwNZO+rT7n5_z?;}QsGA_{Ah(Aqwr%Dew@OOSNI7EKT&J# zO8+Fq|8$L>3Jd2m(iA>j;WHFIQ{l4|K3m~)6n?V8Pf_?>g+D{1K~XrLai+rODg0E0 zpQiBB6@G@opQZ5m3SXe`g$jSRHjbw^1&JnmhJ~D`0XZ4{?L5v;V!Wv>=X{9q0qsW4 zcV~Pov;TohEyVa3?IG?@b5XLN_<}2ZoOXosG}k11i$8Fl=3dE0g4WK53%C^gCDSGx zA_I(1;db68^K)!57?b@& zI$)1%uK04f90{fuH_5JDHK*mk5xb5083f;X%o!mk)FSr+q0r_`!1c89Y3U0VK;m7ju-FbLWRu7=896+i5eV}=A z_yQh&91owu!-KMLpe!Arw4U&RCWG4P#|9;us^%Nd?RFMoQmuoBd=yd0#}S2`r3dm$ zxO@qh|Ar{!f8_FKxSZMDgq$9Wksdl zcP{@2m&cfvo=!xe=TxH5Q^w`Xxco9MznjY+mvi|_F29}2@8j|ZxcpCC{u-CR#pPdcc`(+BH-RYP?L`#vj^^_5TwcKCWn5m) zd=}?JoX_Tbch2WY--q)^FXQ`i9_eL#Kh7h)jPK8Rq?hqnD7U6~kY2_k(TqoW89#{gNH60D zb6!d>lOvss_U07nVm#8rDAK_w;%5}`GK%;ZMLdi`Kf1?A4t8NLEnSpTnm#Z4Up`N~ zXJ*g5u~w*|78z!dRErF^$Owy!w8$unjJC)ai&$DxEiI|Tgqc=$Qh9URUDnawo(Q(R z<@R^BvlO|#edU(BwyWG;?oAxGpRyh0_LR1tBoEK+Cbz${z2ufFDJd;0Su($v=HgYcs_qCDmn1g_p}}Ext|{^5W{^%K3OJkZW7Cq@)r$7JKhPvO*WH zt~n_d6%;OU6|sOxWh6xITneez4k+{UEKd>2X$Au8tzD_d|7(==I=j2^ITh-by9<;z z9ajtcH(F>Ejk2hyFt?~=NqI$SQE^R8b$Q7WI+JPe;uQ;Pic2)ITaC+-s*1t*0=gI; z)nyf~yTswG^f^3Fyd&VZk|VHh6h~y=EG%ZrlGfmP6~*%@O*PdlO^X-st4KYxhn)Iz z`lJ4x+z5-Y#BMhfncMCxa1>TO%ttI$vFG2jejZ?5<#lRdKU{yFCirS5e|NV$OL- z6#9mtBl%SnxWmAmB4><;QSOY;yPjuzDWgvS8+cF?i~*t?Ssh0bu;z`(Wavh5jLVrn9#ko*%3!=oWixRgpO5D>?;@*!E7aS8^e)~p=n-V2% zL6o?45pWxodfN#cZp|>K;$8s`U0|3~adBg<7fMv1ic5_WcOGyUGQ*sz?`q&M6oxq! z_e5b%dPi4NEHKym0pdmj++LB{7s$->SYN5{}vvIWK(!GaY?x zESM**Lc%3CgS!{FDe$NCwQUA>RMOY38Qcg={?g!2`c7#ES0mxtH-mdn!gXi{cT~br zy^!-NzY*C^`Z`%KhWkvZ-x}ba@LBo5(waHa=QrHV`W}>USh7UK zHAuLj&EO77I85PfeWxh(c38rtHG?}U;nJJI`Ok3b4Yx9LR4!_~?Iav-sff6q5)Mr} zB5s6)Lz9h&%aU+8&EN_p+~j6(r4nvRGq@TFhoWT8t6bJfI9%E|dXFNO^F%hnlfu*e zaV81ih*xp9OSn9S^2TkGa8sMX-7DdyHG_Ll!cA`m_n3s6(G0FZ!kyI&?tp~LZw7Zz z!WA@wJ0#%>o53BHaA!-n38*(ynhzZTt~2+S$u!{5&1xYo44_g6kU(RJnl+hk!}JzR<~zXXOy)ay+hBMLCi9&TEt|}Duq~O)caU~E zS~8jM1Szkq!PyUNdBKagH2K$^PMh=g_aT(5gR@n$05R+f03KlJl>2u-ThQiAcYqd* z*n4OeM(q0|Vy;@Y=I(@GHqjZ{Z?XjiM;|`r@rD6eLt@LE4dL#oRbRV^Memu#*tE3Pi%{JhjL!$&VK1!q}kUv%;OA*I#jOUtS& z%1ed_Uq>?cgjsW^#g|{BsWNpb%6Ho&Y!RTh(R{(y9l8X21+PzwCq>SuVTSefmrs2C zg@-H0$xMCoU#!p)Vs7e~<;5lCnvP|%M$gAoCyV^XKT$T03qQ}^XMf8^(~8Pv>%azCiMGh(gZZ69)b=E?>pvTZlq_FPHy<%b(=(KXduZTu$Et z5I%;+W9W}33jIBZLOznq*?Y*4pU34DT)v1XdFK#7Ky}IDmNN+3r`>!KJc>RE0VEB<sB)v-=a61KwllO_k`ej!j3a;gav8v{vq6!?MZ&8W?gO#b6f&ac<4-QGS-@?DjP`-z@JEi; z`ZNNfF6_NSdiNH$lFQ+iVc)gMaz6r5e?+>F9_9$Q7Jo9XD{!k(P=pidA>1bXAu2oG z+fm_ObMzg+k^T_=$UOv{Sc_N^tK9AfBjaKa$-@G`Db-hb>Rf4t9%}LI&S7Im4o?k{ zYk7{ojVcjN%+W7FHPx?~(vWqJX5{QmXguwU4m0bt`g*++ot@Zp^QO)9^}%A@*q!7n zHXHp_fkvY$rm+raLhjJ&#|>>tpSfGxR$EuE=f@WNj2+#C-@B8{Dx99!FRkg_&2_c! z{_M5Q0mN0`clG95Z_B!;t{cT?VI#)42QltJjC-t5I02H!OXoiROYyD`H6A=L$*51< zIN7K$&g$MsRL5)CIJq=%;MV$FU&VpWY1+_w25{ zu<5`PyK5P?`72EXq2&@Z8LEGxM^Gh7U(`hW!miJaQ-&5qdHj-WUYrntKcjod0&otv81tvNan_ z-;$aYnJea2lwqpSRu?H?a|V&B3og81#l1V9?I(wg6&g)a`LDuzAPCnkuOjV~#WcH$ zv|%kByygI-TSYo}d!f?8D$)tj@+#87wzP_Lkajv+T17fRnqNgaI9oMeMbc=;>*TSv zzE6Jg`B!IzAhH9v4qo%6i=`=h`p3gvGWy;RKg(EuqdS~)@R~neXpXdIwPS1P;57$m z=Yy?6F};;CA|JeFhj1Od=F8k(ocQ{f4>AwR84-3t!!yE;YdgiCBQ(n`UmXA7zEOlO z>qhC1BITteFR1OrMRh!ygLY-UrQ^|@U@a}E9i+2Brdb6~xxAoupvr=JJbECGKUNEB z8d&EdSs3O|y7lx?%v^Z!9jnYa#YaUr>ZB}2-at6g zlvU1MLHTC|pz9SagO5>Lv#R3`W|_7GN5|OKiRlcq#VZ!it+;r~rLyqSlJc5-oTcZ; z^x38Ma4rUDgkHW-$*$;=V9%e$Bzi6!P-92r$Vx;!j!24UH=iE(^*L%Z4t|a}q0Nc8 zuykf|#S$m+Cf-njyYqOr`w58jSlwYKZadC*w`aR&MNB!?_2JP_ z9@Eaatz~-N)f>auysOVN6If~o9PdU!ThAw9qZrH^MOkHWNky66E?5~;mUVqQwFK4s zm^Oob-aQuZ$8OoarP7MxkFO+9p zf0o)ynEx?tFdzTh4JO}iRCa@D&)Pm2I61BjhIVRC!UmJU8_e9Q%6aAUmsFQ|Ed?m= zx;{>)mJ<Op2MBA9q!Y)-8aghhN@P^jR8jw$uMj!7sNDs(P!fuRgim~1a?}b#`vm|Nu zO!?OJE>_d?0v*#9$B*N7O`NIwvPU&d25G z0BH}+KB43zI?muCoXK-ZAJZIV#3h-nw)FK~)`$K`5T9hmPWG*Q%`{h92QfV6N_fW; zmhcfs_XtY&*_`$QrR27{xwr4KUi3$TM5I5{xAGa&tg+I6o1Fe{C!DbKf2rdvp9^#U zWX9fLnrE4@Pg{qXY?YIz4LxDW+peR0mu8x=Ri?R^{Wjv)D#HJkG(Jmdth2^6y-=4U3cbkFR;<9BE zC!4WZruk|{=``;qoO?Df}Vtk^DX4? z6QT@H`>S5zTSXb3W{qCq+eR6lwn@CgcZf1PEt|chVaUo z&9d`2nm>R8!DFm)8K}lQ*cB7OpEUupol7w#ev;dST(b{Hd1}&dZ;AQQ^G& zsh1Sa%imhGSO_owmg1*gOgMU_#mXPO7C<(HXzkbXBkf*xIC`w=9gf98udG-R(8DbO z^myDt=-xJ%9(o9{x+71>J~oo}y9F|AFP5M~Y$)w?3TVX5HwxmE3hit~2%_w>P`Cm3 zLjXA1jj+RcEs_b;{1*VH0AYUtKyRV?^=Q8Vur_v)7QC}ht*s;e$PwQOl>W#OPu~ED z?@EcMniX~zh^IU`cprN|w+m$C4A>kW4N9$$9PtxDsr<+hp9xCu3z8%L3{duJ599sp z{a5Qj7y0{{%`dzb%N(7VQG_eeqKTgeUVMj5{6g^bJ}x;rY zL9NEc$7&l~e7wRZD10l0PgM9Mg>S9!Z4^FP;oE9=y3*55;ZITc_6pxY;X5jPCx!2< z@Ld$XtHPhE?RKTFo5G)_@F9iouJ9=e-$UVhDts^Px32hmYx`V$oZ{a{;rl9lKZWnF z@BhSMI0D*i*X*Inryrtql>KV0EQDEvr;AEof46@HBNkt_bO3O`Qa z$1D5X+>%!h<9icXwSbjFP00|Q3U88eDb zm{EKV$0&@E;By7dhxho)iT1^}RXQ%lb2$>sD@v;f zkB**&$BU;dJkrO)gOUw3I!j?Lr*}|z@b}2!Pv_w=z_9Sh7Yh%{!hz1G@SsT)9+YeV z*zr%|;qm$?3y<<(;X&t6IM7l~sm_QWB8N}o;Ro^XC`T3^w3xzymT^k65#oo*;nR6| z44y20ls^j(%Dxc;WoJo%inA0lD%=5khlz?01{!r#EdJTALa6Z-_jFD6!E4IMZ6=pd<>VL%jFkyc@>wh;qpyf{y$uPAD2JDPKT>&~iVJkkzE8+?-B1BoyNjR?+95;IX zZy4creF+qtHlj(zJi0uTfOu?nX1Kqyu1dcu+rfZRp zSzyH841oo1i-Nlb9w7p7CvcC0r)#0F4vbg&-c@i<0Ec1Ac0!*Y7vh>c-v&eHDygoG zf_nrBU~3NrsN%jx1+g_o3%Gw`!-uUUTEJ~=#n%ii;Og-j8(SN+fP1M8Ujwv&i*2WA zY_8t|F0VbG)3<1jf?2x9t<$(Tyz(o`9-Y9Y1u_lN{-{n!_UXBtsvbUx!5Sf%{mQo*g07rWcs++Fh z0$9t0R1kO-*E>pFPL#NLQR1$N5?2=`ZeNtRzeT`ZsFol0>affWb1Lq1;IMrc=2YB# z;IPdV=2RS=QGxBeFsI`707uV-RHx!T01nIlFsI_WA`{W%w-7j*o2icNmq~VH)&S=f z?^=|zAqD;|aBrH}=Yeb{m(yCF_M0$eq3IZNw<6M5!EhP`y#qK|z705%XW)+>-;wje z-7DcR1z^q#_n?Hsc1A?pV-gNig^0KY35V^Eh`0k1PRtj*(sxk8VX6>O-ysRtRl@yT zDZj(OQTnO;#4|dISH*n?TpGtEfRgjVO~6J{8vIBfrh?3Q;Z{nx#Aa}hNw}nDaNkL| z*3IB1V2>{i{**pUEt&I7pM(?7KD}^{NjNcX67F%OoWBEZmSM#!o}CizSp`>!g%qWq z(ub)Qb6&Vo35O|EL|l!83pImVE8)5~gWD+KQkuch*%%@pm;x~8m5&D{9ER+OxCRM_ zA=bvdp_Jc235Oz&h&wFduzea4cT~cO{*CgX#_PwPs>m;bMAX+#!r?L^uBU{<_H0Dl z2nmO6+laU<2`Bn}%EzZl`4s|3a%z9r=4H+cM`x7?+_+|Nr4nv@Gq?%~H=!9^jf9)n z3~r@_JG~j)S_wC)8QcvLE=|G(a8F}6v&XHCz={5w!x&-DKX4V|!ux>RkFc^sRcIl| zd_=j&a#U7-4;((MD66hsvZ#hzBeQJW?PvB{s#T>dt?wIXmG%=&JG7^MwsCvI) zZq<2dKnpG%I(|=W@1>Ya;14f!Y|(D3Kl*k;-O-DBPb`F}?v@^7Ge|?Y6Rj|6& zZ*o)9%}ux0uiM%8l0e-i-^`tQ{p{Vf`fW@)NZ&HAsculit@E4eL-l{!*<(kop6@S4 z4E^@h2DH`r_3OHptj?cR9L#T163m}dT(?^97i!X0??@U|TnFr&Vk7_jVt@Y3;(*pV ze`;|ke@by$ekQoOE?Tf%3H=U2D1^~>Bn`8!j2%h+itE-v=C4cYPFV79y(8%q%RjUu zsg>oQR+nVLf5_6NRqXe7?Dq}!i-W2m|C0TF%YMISzdz9LswVpV9s4EwX+xHN%znRQ zzu&Uo@7eDU_;r=(1)+kDDATbES{IC-w+j~5>a9`=)o&G8<;JVE@_yMrXOq!P^$0TCiN^glO4vnS*V~a+!m))6tUUGA9W7CryuN|JuRX zs#yS+!7pK7EQIQ?1L#FXwhgkbEn6;g!r7rtY1wj_9m=rmkeO^tm^T$+W6YH-!_G$w zmdk9_JR{5oS=W{=mpS1mBhgwevqJ^MH+nuwHd}G>?8uhOY&gp|H$fKB6u5(SWxgfL zWlpe`ESEXR7A==KP{nc??d9{Fe!sl^YioYlVGxyogSXQz?y;va4D%4j%+{Gbc+W*z zus}XWALz_IVHU)VBK{N-FE;au%3@8J8T9f)0RFtyJA{WPZ2y%NS5#CjgTZ2cK_VbY zKt%i7@vlp&Pg>xegms!LsFmYRWFlZ?b;G)BhMXZM#{)Xy8}+rP_BV zrlwChIcvHJrRmfry#_E7_PeX93&}1Et8&V?u4{T^)N!czPOydGYsb>_$%(1|^pmsx zKMSjW>pc@z)RbpkU*WEK?tdIAeFy41jU`0Gy7)Mc)D-VY-@BJrRFusxu9&{4th%_S zys9$1tA9zV{0QLV&=TH3zdy!l1IKE_Ef>Qcw@*uLU=;q2ReUFI*5;!(9-OMR-Xo*z za(k-XrS6`49*1f^+p>6LSHrX=3rjHZ5GxwkIaR%cxh=n50!BRC(nmQh%l17E&F2zkziobX)sjV;Flz2^j}-aw%8TZw zO?`hR{p8S3F8$=u&vg2s^!v}IpIP*CKK;;Z3jSjHDW#wJ^m7sY&^HDCMf8KE2i!#` zrhT1(s87PaX`!oq@%11pXUedyUm$f(!uL2duO0tE?{uMe@8ofxP*XKM-~2^5(|BHIO%V72BduY`H zzitHPn{fxt*uB1Lqm^#NxAk4Rz%c2z(liaTyWjAAcEyvH5wky{n4G?&>xn2VsX2~9 zEhd_+d_#>a-FJC$^#22}f1v9ruA1+2A~JK_@8H*X&3|*n2;9UQ^e@f0OU>BbM(d8g z*^NerPDT)x#O^|s-*p9SocU2ox45dj%ZVr@smg!B?%ZnY)@^a9>xr}r+hB&#IiZ~v z3!C-7KE*Kx|8XO;-6wC}x7Vp9V&Ngz|uG*rdx4ptV!$@y?`A%P^tml*{ZB)@- zsIXBbhfj|(e0qfNKUO~eQ(I|zGx2c|Cna%x+&(!2H zJENJntesvfHk$K$m3g#fMpHPY?z3?I8Xa0I*%vbgur5OJFtg!E8n^+b*+tlT^hYh8l4t*5?K6E zX+h5Il(=;`+4xs&fqCS}KSDD)`hvM3-1@G}{j0j;!z`HnN9v+TDizRrs)>LrCaV?w zTg}34&C77kO!oEGa@%4+w#;{#!hBcYzr%c292%o=)WKq<4(DgT^g|t_a9;k@0Sf2k z-;#dXjTO!-JatUMdHGXkBAk~$br!>tHUmxh>ZC(i1Q9g&WHLPLu3pQJ?Dgo6JrZZ4{CtyH->x zLl|fAl&O&tFWxsMkpa6iS)k$@0^+HeiFdk*p8=jKk{t0fK`9J5;x7Q5%s7iL#kFXv z-$CI!Dtsq}@2v1$6uzs% zpQ^p0No@d`2II@2l|r z6u!U04^a4l3O`8U2Wzcd=^3i{4`DWTob(M-_*8`-uJ9uiex$;WQuxsdKSt~0O5a$8 zAE)r+6@G%kPgMBR6@HS!r!fnVlz+B83p-&mczUSMOh*4v!ufQ@`)xa6af~;#8@NAB zC&&&N+0Y_K)0brQ7r)`Wg*VxI`sN&~4>IRk-#eM}tiui3VTC}O^F*y?W7!v@KG)Y> zV|}kLMbkba9-}goV>D$v1{%hr2{OJ9=lfdY71@>0;qPD}bYPF5>hXPT9R7;+?|7V=!dlkslTwl*I>n zF@*!A;h*SHP&MTDfcorVzz`}#FctOcVqYu>%)gWtensenLbcfzM!mrL0KP}&D-O2Zto1=lhCx< zH_iGc)(1J=8$QT0xt!)DBwxVg6mf)<==5RtpX`tS_}Cm zaJymMIX{u}DV)cLT0;rfgY#%4jK_V?!l!W__c7zsIgk5*@fn;)J7#<)=g}?$q_;n} z8;1B9KY;UypYaIPn#a%hL7YeYj33N-#LxI4obSzfB$kCo{LCK<0>(@6GdbdA6!9^N zco>C#MxmEc=wlRm(44{?jYA{{rOP;tESBX@uDNvVnbV`PSmvx;?L}SB%$|A2(1;nS zPaS3%QnM_nrCO%cQY~9*sg^OdRLh!Ls+E#d%br^5Shpc7@iy_Jmclre9kX4cDqbv$!{qK|@Nu+tW~W(s)a^76k!D9i1;Y0sSGa69lUtO!jh_r!NnEj#f!DUj@`2V zMTX9(f2BX_hslZk8jExK!cm*+k zXpgyr>b{0Rq?P=-q2SpXNCB$2zX$o6rv=`<%IAsYP=U>fe}r-Uja8L3Vpq>QA=%Cb!xny0@phVeH}xX!>h``tNMNg zoL4!kcKZ$jM}3EI;#N^{U7;*ZfIuVRW=Dy;9k^)XJshRJo+<8rC{p@v1}>U>Gy><9 zzHYj^J$J+!1JmpH6tJFe z&Eay|3!wRwc*aQLDTtKjLmBu(Jj@00d#i$*1001X9Ql(Y`XF$KW)&0QXAy9+ev%Vz zucB`ya3m*vm?|*mg8;V`9$s86>4hABlvoNWIM zQ;LW<+5Q`*3O4S~O8Gs8^oe?lZw5#9+Nj-AIb+Jm9OYNlmw=ls4RXS@!XG&=T%Lr( z)RH+b+zr5qc$1pJHAwneH-qzI59%fOQ~KI8gF6J=430}~1~(ATE=2k;rDcxt@vc(N zrNFf|taxc^PL6P2D7cyt&ix^tv3udxO1RUQHgA0!C0wW(+%^foW;7_uYc4of%;u{JISWh(a*MNjQ3zL(WUzy%H{sp)A~Bl%FY$ zTMq&!+A)VQk_H@&iyXy=S`lqZ^*8VzMGFW?Cz^;+xOO=zi)%D>gbxi z8}3=RGqElyFlQ_5Zhcj}dqA(M-L*Z6^?tsYyL|O)8e;0Y-CY~=#Wg(>i|e}iNG zV(Zt`jat35qo&WS)Aj|@XYSQfwj6Gt*y~5>Gq-E|E;|_5yZ&&uJy-3n-E&Pq+cxO& z2gs`2v_1H+{?Bb{kdNmOWSPxrXw%eNf8MlszaL=(oydJIZDg zE0MZx8cJjH&dw;KO{}y~CJ)3tpU{YML0WEa&|loRcjtNgYU|fM)n|8N?&`Xv*f~3D z`xVDEZfw}MZa2#1>*9NAQ&1YgM&HcczU>VgV|H}Adjpk6QgO$mOR=oivOFRr>-8A+wapCmB^t_^J zXHV4((|F3-spWAUdj6@k9hbbH>540Xq9|OksH~_)Gki~r^sv|g{E~gT+D?9dTa6#SoSzvC}!i6v=r0I#i zqxNV0#igayWs4VUy3xZ(^nGs2ON(oYmklGaKhgJvTbxSbK%(zUA;y7UPAVGBpL|i* z>9NhORIp|+6%iHBw_3tiBC%{8$}=#f^qtB5r)A{1g2se|M!6NFToio!&X@W>>uxkc zfz@aRJBdoVCpF(UF)hudS*IzOt-Texb4=4kVb(5A9kPA<*YCPR&?IZMNKY#th53gQ zX26X0mEV;0yVDgW_)h>5b>9HpoUx=PW68XEFsq=q_YKrVYJHIBR20u=mC)WdNEhWw z9_Lh-*OcW}mXB)btwGh>onIgY1$o>%r+OUjl|jr)AVbx}NW zJ(i4|xAk+)ywY8dLTww;E4PsQ9-h2rgi-gXE54YJ&?0NTX&`l?kK3(L}r?eF-mwsJjL}`RpHci`G(`f$9 zusC}kqo=H97^Wt9fldzz$fZc?Nz8Bo`>_T?;CHh`;$usjXG_t<% zpi7>UH<{$YMBkrX^8A9CS^3$_FD}vd7nfh=^s}cGX6NToz=TBKU%fo1kY{3|?h&G$U57=O778hbkcD7M3_*z&V8XYyiuS7eSA8+k~@_O~!kso36g zdFD;eOwW@`?S0|xDz#7Fxb|;9`{Ln$xDv-oEx&B;Qn}PV5c!ZxZRXrRJo)*p&s^>< zHK8=D)aE{W@z!at?(61?EhZ$iu&+3HshRzUr#||NyH0aKW9MinR^4}mm0HI1>4ofG zPxO5xGRI1dJf=?1%BJ>$#`X{4=^FI><9_qgSMo1<%oPF4c}7)LP0@@c3m4ff=3|i> zIq%>8^O;Y3yq0>3JMThmSl(wn_i)D8*3b5H#TOG2TG-pOJn!wE*-$(GSDo&1L4)*q zafoJ8R>`|t4_{|pjG`?!??H&R;(K=|8y;F(DC9&eRX*pSo=8r#F|oGbI#QnWFts-dfwt+V=8at{Su4 zr8%($L*MqwCNVlg-wr;^2ytI0DXUl4R`lFB?JIXuS~m3UXm82Tw}Z6P(UPHWCrEj- zhQ1w~t(pahXz1GxkRTiS_NNQm!5VEk^GXudyj&%d;28Qg(}f9fxzUIeFM%n1HT+y)F2!vg9PQ$jJ}(%S2j#Z<{9*Vg`D zS?3iNgfgoZt*9=azn~`6cW%GXu(4xD4N4t4Y)q)IY^enL@7FG`qN*i}P z#~->)yW;O89ET>N9I2d_R92VGFJFvfIPCF-a?P?G(7%raIYtAsHT1XB^_99l8w@>x z)5Ie+U7rCFk||kto+m)!X`EySRg7))W>ugI%N4yXaNK4u6k`_tPQupXLpf5@Sd2{< z{=}rPiaj%7#Z0*l=-IlMI!1sV(?)c;u3u`k7^M--UbuL^l~nOiMc2=w=ZUoMl5Ksj zClapf7Xqz`CtkX-c11}=)!d71W8r?iV43rzORW3+dRV*k>rTAl5szP=rNk>{;IK_j z@rtK~e!b9&*6}~9+J1uO#F}4SRwE^C#ysqwFShR%Gm}-$UygSVN^9nm@E)KSjYPxF zm640!bh9^>s7QR$Ga2HDg$Z7~~HzWwE=|Q_K z@NDm8R-9se?hlL8Y0R@kln%Ir#pv+)EJBB$Avbk%5EVT8^y#?v?i~^7N!YT<%m6i8 z@0kH*I-tMq4LGK)`wKGGf1w!hBTox(3oM#vA50>)aXlNU3>3S-(iDO(s!yRTTQ9E1 z9`6}M`pMbG68H>)hA}>a$f>Sc=*%G~-vNECYYyQFKBi6X5uJKens@%FvxsHtEMku5 zEMkVI^go_kusMx0w_Xt# zOYG6T4U46V8JH6(2 z5;pdAys)Kv6wk~HfBekvksiYgXU>Y8!xfd37I*R+M%`ve~$6}rsHgheE~}Y-ow6}C8Gwv zbYQ}9N{0Pd;QtbU5{O|B2VUV-aN6-{38D&))!irz4h`ll%|3PHd$RdI-qd}U3LvW#F#NF=MBi z@xGcRW-JcwFk3ClFwM)%*vpJy5*RwM#dp4up!;<*_F~4(Os8wZ91TwQotdUDnTx9}H0y=r}WW{t#-(#in_K8GEJ? zi{o7eprt0Z^{vV-!BH<4Wm^sP5jl%rAE!gCJhJ$6y`5>EY3gU2=5X=bi(OBo-`F!J z{f^HKb*y4>id)xvqQ1pBGm&#r^ zT8rEHosZmQxa(n9l=-6-j>w;GYPlgS^1_amVQ0x$XT;C}GjyViUp`*O9Lx@bVF*(o z#E~!Zc{A4eDdMyl>!6w+ANMbx#zI-TCM|evnz=45o}D`5S5A6~aD2+Y8WRp`p-eX) zmwjZ;zp5Q4-`LvYBjw~j(H?ec&Ht4WJ|t}E93-_Z*)@Q{t8IKdyXE}s(z-EVM4*-C z3#P`8>1f?igz&pWERbo5985qGFhop}Hk@4q+dBG97=w`5co^fQ2MY1_c|In^mteC@ zL96cC5Flac%NLA~KOL7z)+s-&`$Ez+UZlLuNOty5vUT=PTXFVJyZ?@}f8-97y-0(6 z)6`rz8kB_d@~1&YI4^%1EQIs&r@=rtFMsOPh4b>K&RV$BaKY9k%sl!e%!O!^%6@~7 zVDuQ$g3xPw0ut$!vgiUx?>->_ZADr!(2G!$c_Jdc#6vIgT4;LlMW7?Rw2@+i=?wuH zEN@BowNY~FQiDhR1Q5wh@IOpOlP+>cV_*vk`lP4VUMW7QHXYuoJP2bs& zGjOiSLQpDma>UbyA2kAU#M7t7!qK@pR|*EyXBgTh7w^;RUA$j=+{K&Pt1dpEedXd~ z@JYHO@EJjk&fgWzhy3Ka_&BY|#m8%xy7*QKpQ!Lj3g24c+bDdp!nalUb_#!r!narW z4%#)Y^mbJEP72>y;kzh&SA{=S;kzmPX$l`w`0fgyqVPSmT37meDts@6@2&8C6uz&* z_fz=(+MTZW253Kb@d=9mK!qQq@Pie8h{6w5_+bj4s_?@VeuTo0)E;rAceLU^irMOO z+WQ!VAFJ@=6n?zIPf+-Y3V*tG(3PG^3ZJI%=?b5r@R+)_R=eG+q!TwL}G;rkw5OT75amF(Na6L9Jr5&LMgaem=bK z@)l7P#Fa!bs4#hF&UfJy1<(9X#gjY2VK6Btib0E=$AbZj$xr8U3|<+C%-7Dci%A0- z^Pj~1Q83IO30?=B?VrZ|u?fNaVQ|vrpU(X;38OKK(tio3r4%1{`f!Ela1;(vI_8il zYXc%3C}@^`Gzg{#`Dc1S*||ZW^GOfr4-_8MPlYJLXY%kvczBc>3lBP*!hz1=^dN-? z{|cxbK8uIP!#);2%A17;EunCr^Ef@1!h^q%Q`S~RIlgvkq3YrZL(R!tQ0wL~GOdy3?{xco6Le}c9{ zAwAb~`A@j~K`!6N<@>q(4KDvDmw(RXiByl!6Cw)zJ&8hp8kgsD`Ajaa;qq&^d_9-X zL#IJ{mJ@}Zl|-Ru2bVw0<&SguU%32zED-*b6VjHRb7QRw-M zDD;~_OCC!U^5H}w&*t)6E-&Ho8ZKYXCLm8E|PQOH*i zrSx<816=+Pmp{klZ*lp%T&^ctdfF0&o(@Ezr!SX}e`w-_PaGa`~HF{wbG#!R2jQTk-ZFit_106zR$3^7Fa8h|5=T`A@lg6PNGe^2fOR z2`)dx<^SOFPr2M|W5wHnDB|rx6!DJc@?0*T%H>sDekGS*&E?y<{5M?wD3|}0%Rk`q zkGR}Ow&HC^6!CT>ig<@{c_x=n=JGjQUd`o8x%?(B-^%6NxO^{{|CP&M94=qU%=qz~$9RoyQ}d-*Hh(ET#`oYn;$wVI&Lcj?_u@R_ zV|;JUBR`r=Z4DxfE;Onsw==K!*ZjLm3qfhqpc$M4j9j-8JfZ5E+`sLVZz#{NFCNcnPK z@+en|JR9!f0hu2b-rpQFMDg67}|9er7!sK_wHG3 z{eR!~YVg%5jwCBBD_JrhH8ihETw6zzS@L<+#S6=XM{!9>b=gwE;bU}hSzKLQIp0yX zXh}&Wf{`hO!rY>gCFK>RMa4BW)#W8iY6yih(Q1lItkcjuIskS`nsw|Ns?_u5b`D(w z!lM>S9P_+)?oBY?L!@UZLPLfBKtXQD zoJw_Ms!Ybchdn5^$E5&O+=rM8kuf{fskn16Ct`bA3Q)zpfrb$cZa(HrVt-Rssp{K~ zIThQ(l0mpuarG&Duc`&y8qB%aUQ`RX_b?Y@drmFjj`rt!OD*8u8pQXI6kI2z-Y!Dp zyH>#vtK$9%+?7$_s)t2~`z%UaO)6dw@Mte;`c@6sv}sY`oG4$ z6z@c#Zz7i6-yC)O-eBz@S9Vot?X05>BF++)DaiUQXT zYooL%aD~7{qwikeqRGe62=S&W6}LM|+>24-z6I_g5t&5Q zc*`bY&s*{rmn!bbC~@8KY$BR?uLmxgct3~|HyO`7W{bp2RL#ddzou|9|jkkd7A(e-?RB`?c z>=g-5iK@7fQR3zSH(1gmE>(RSfx{3N=2YD8fx~u3m{W1@0Y`f}s#9@oF>$0hrs`B& z25`~Dy8yTWsxt5wp+0=ld3qaw!w?tdRs&~9(x-u2jY;il$j;~T)}S;;isd|!DQ8&i z9>fkG#PwDMw*Y{SkQ2_tA34JPLBXvCfZ`#Xm{Sw(9R+tY03;_|4F1Rw|Gk2{RnkZP zDo4UY<#^TJJ#aM;R^h?_0psJ)W&(zg=0De$9su~p8T7p?)g zH24w@TiVQd;rw|HPAsRqa9O~Kc-u9j?*>U9UJr;E?*R#iC0ayW!c-@H*uJ)LyOes% z18xj%T*_~PgnLxMtu1u=18hGtNBLE88zmf;N)d6}B%J71z4SdO;jpBNsINi7^=$@s zP{Q?V26tG(^_Or5lyW&L;V^|~j`E@6{AWAmhsO{RaqT1=rsffGJtZ8b$PsZPBpjxo z5ph`(4pYmBxIzhssi2Lc=k{_xSqdDL1GOtm@t7lC#Z^eSGz-SUskj;mm);C+rG(39 z2DetiVTfhUD}6UexU6Py8zo$JGq~F&Tuw8%Z4z#BGq`&t+!P7-8R`S$yFI==2wZ3G zFB3A@ivO%nCi%0#eSxsD)4|YQhKy^#BCi7pBuBV~b4wO4l1>_I>72n)V}_-Ui1M7l zwJ%$diE{==>!bAg^;r#v)0-;l0tat7bVWd`U-K@w*H+@>ymj^KGdI-LYWaaVv5gxK zoVGf)(X0xxt6*dOI^WEl!Mgq1_ix-RW8>z02c+Zs9ej_vBu62sU!(Wi+v}P88@kc; zM~G48pQ&wN7?NAp=QVAw-M-<;CZuWg_S*UbpET8fSU)J#q#1QdNprSu2o)qP*l|GD z>eub4t^3&zxBF(+>vbE=+kI6`x*BK7wQ3z(zh2)muc_hIfc9hPOZ<`biS%9A)bPZQ zn?g(D;}6iegMlCFuSsa!c2)L(+5_L=e7<+~*KU5N_N}HHw1mdm15MxGy*{DwL&$=M z8ag(u`mlE4oF`ZBs14=&%Cr0GTGoKf0T~0*2WX8uYPS|%QvTxljTdaJeX^;3-S(^j z3o~oG;RHo+&wSsMQ0&i-D-PrbixZx&Kk$QZ%QLHfxVkB(ig8I>p1HGWO;f`2JNIwd zoPI?nGzY8d64Te!CHaf9`x@HNs)pLF8|yFVQYTdTe@$b?6c#c-yEa~clOhd5=r28q{CzPmyY`wN z#Mz1UYaV|fxpC8hrZ1Bl5AWZ!xxTL!JY3jmP8`WTj%z$($yy&NOq$bB+ltAxPvV|G zxIez}j?ITQY^sfK+&N~`X43IxQ*z@`;1ATAbAqq!?d;e5RiGWeZDMCe_p5%`87 zg3kvV?>z8cQ|*4bx@B`LxbK>R&)4q1bMp&K`>H0=zFLcGeDA<>z+Lsjdz-EEE$tkC zpWJxR%AIkraPXWX>sX%Oh78C|;_d8z-?9kmalHw^vo*oJApn@Yvd=-q1^re z$#;-6)CT5kZ-{$+A97??u`8rE9tf=|zVQGMg#MnFja(A@*X`)GYXI)|)^&Y$qegMn zad%SgoR1GQy;ryYTSvbx3)j68jXnOSbUA zIHWy}O5kJfT>M?ig>{XVL9L=uM{d8wl|JLk&2nC--)PlXf6cb5T0Kua#}7@d&~t3r z{NV=bGg_g(sTa}nSIzm9N~)l|nOovA-c(G|GdW}92dW}}DUW0MG*Jvg68iRSS z(Vz7i13i0-mNZ4vTWtIHdy8-F-ok%4ik{(H)Ft&KPS4=0`n;p)7tp4z-_h;&VZFlh zyjS>u)$Et3gFn{B6@Q7l>*ZRV^%wuNe9#jF8^7NFC9CD1?vHK!ax?CsJAb-AuJL1B zJ=gS8-2WeMrhCu6`+rDoJcJaXztayD_Ly@xs=NPituH@@-TmTzR_}AsD^Ofn4fX4t z83@fj7GtVn?alk&+5YX$_9Gvw2tmY_s5DQ~(fg6bfot?uQ!_IPW)x-5!og_MaFT1` ztfEXD_;qGc!Su89GclJm^=tKb3zSRe(RqSk<%G6`XiCnbJ+k7PPYyo6YFr2+JKC73 zb1AaI<(Xvbx1efC_1rSeFs{=@BIShdANQDlXXW5~TpD=7joPq;=Z7WS*btWRFc8kM z-RMqu`zgHaChSq^Y&a7T9z#{TlrRrR~$m%1W% za-cSzPP#}fdyAge!F?GATTi^=>g!xe^cs!T!9yZxNd1iIdFlDNh36LK=N9Bnn_QHg zHJKW{@f$BpPI_LR4MNI)isiRwEBm2kw`h= zn_jBj{YAxDFSvAwg#SS#3Ju3jxGPae`IBBCId^DYd)*12@zjXdzv%th<*rEGZC*w9`iQb?MMo1Atb4kw_Ct-0o^}@XlR!QNg*>aL%UaY>bP=Jqx7W z-*_N{rm+y2$Z!&{?~;;9or;rgawWhn{TzC$s9;6qT)Wq)(nXTB<&Kv7i=MvwnyxD! zbZOBq0|41bk+R{HICg|0s-Q+@~SI}@hgoafS}UkU(n@-rzXQt8@_YD(^8tmjSR&K7Wa)6daR z6|~Qv+_q&W$re0-b1H#NH1#ml`8@EjbUfRZc~@*BFS=1)O~Q{B@1u7X|_v? zsEJ)tHkzx6-7Vm#CXj)9-8Io~=*xe+@XTNR-4%6s2Bez!xh|5+-b@nx>4!_&cgX&% ztxJz_y~Y~TPZO>Afi-ckuGyiPXh5|IvR}cB+#>QRnl`;CD?2a!Ty`65@WyaJM-0*I z<0)~Q{Oa4wb}W13lkKjw1g)usHL<9vS~Rt)l%^J&@8b#Ao<&-DW)^i`ntWaRCy%-m z7|&aod6j1-Be$@iXhwE^(K*xevx=~}Y8r<;y@sV~A=7xx+i#SXW*V=1`lSxl=9tDC z-hLyr)u!>Lr{C~YZL4X#Wo>No9F6__x94rVb!|sij(Cw|!JvFbdClS(W!2|YRhObr z-WCNQpAI+l;hER&={fI4+LpE_Y;A<%IMS@`z#otCiid{|>#@u*Np8c9UEt8We8>}y zgJ@@@Ps^eqbK3N2Y+OC!?S+X$Mo~^~enBC1Cm)4_&MwMJKc}bw=Psk){3P5z-S$U& z`KN0t`c&qOl3tm2ZE_`5w3n)di;62t%PZ%z2IDh66&YjS-}B7+KK!iy(wJW_c4;uK zurm8CPYiYbR--OL+bJ4KE#^CKzhN}R``+6xRl~&M2Uml?{MGe;-+xI}y(@aDcC*SV zidRq-qi&l-TD9LGc|84R#=rFR?yokwheqQOEB(LY>7W6(AfFG#v<}G6PS3&(Y8p>? zB5(|I(e#|63|cKvrTpF#<#cIum;AvK!=?b)`T5iH@d2CB;F{0+k~$5aRy}d5SKbSk z+iz~$J@7t}SM8@x{=Z*cnSRl4jwHI2P_IIb^-7+md<=PoMQ5B{P?(!@F4|&VUeS5k z`O~QYuHqe(2c#f(@-*yUo5os>$;-|O*Mi27W*XOMTBehzZy&uYebrA6%ycD+*J}Rq zg7W#5*~@FnDi@bmRr1bkoydnqRmbc0?Q1FqBt81kXD&6y;{YIUcZ$5Z>b4*|KNm|q z>ewiETRlN)_1@))a#!!&o)~xaZgW-d2Wj7RexS?98(gWk3n9FE>qK_7{Z0|I{r%sI zesi^Nj!TLDj8z2Zi*XZkcec8nl0I!(c3weI_O$ejylhqivjqmNKGX6?SCf~WS(rP0 znhnG~d!YbYfs3Z57o3@$C8>3S(QRBL;05PSotm9rn43vUK15wDRCyHd*#cuVv)(CTYBwsehOp4^oMwzrozQd_mrbqG}LG#Rv zNWLRA(=;+8`Hs>8rjZrNceEB`8rjG;J+tLyv-h(VQ-<`aToced$ed5J}B^aHQv<4=9Gmf zbR*2J##_4B{IL*hqsv~KKue&D@wP6uSsYBhjEU)D9M;8-hGl|@m)f%S*Y!Hzyi;?P z8gEK$;ehs3ypU#5f73+?%awFE`L*X3we8Z;T}eW#RY~-g2#@ZWPrm6tX7Ek!sf!sB zT4c>bnzl{6x z>&GFtW}(2+{E^dW9(*;BzMD zp=$kZgjI9a{g0|O4Y66m>&|sknx`27Lu^L4>TcYw>${cidEC9>X^)=nx{EPH@yI2- z=)mN+f}{JN>n>rTH>~c?Y=7#!wZDG*X;%rGA)!UqysS-H`}og)v&pSlD6lls;{$%f z-*V+;)9<_Mv=W!*z%2m8>qcwCUr|-HsHAxA#WZ;nH)R{AVrrIEv4O(zW_M+>gIH8v z$<}(-VTzUt^v!WbTM0vB%`i6D?l|wXmro!-!JJsl7h~=Vd{rsEj|Ng?_4Yd)TMbZ9<-SKxdL?z1Y z;Kr}_c27TJ*a&w!5Ng9(*riEN^m!ux(XOs`V1|SiS@WKz>Web-e$mOTStzhH-{`b3 z|8?ihxw8KCi(HxmH(M>Nmv;;6?X-;uEv%1&uqsw*8tC}@I!(i~^`L?Eb0A@@$KT25 z-+b#ayBGtUwqeELZarvU106(o>xt=X3~HwJ1Ungnoz}D1T3(B`6MLF5#1IQ|&!#oh z5KC28)0+R{XTz?)@sR>oh1k89t7#20MD589;DHDKyyA}9?N_=RfKVIOv{LUbee>Lz z-@fdM&kPAIvgT>auRM6s$BECmH46on=6cQUys}Pv@5s*Jgm+z<1NQ=efhX7S^JQCR z)so5@8qX7rGn@)vR8!5@Ig9gf<}sf$CK+cMSN-h&vG*nLSrq60d%T+y2qfGhydo-~ z0y($@H6fe|h!7Exnu7#L4GAUzxdapx6ct3OcvP_>649#lthW}g3axF?YODTiYg@Hy zt;N<_HUIB3^X%^IWb^o4W$o~~|DrQ1!R3;dSl-u?uhxV5|YrF}1*G5)DQ z`uT*wLzgL~v=KR(;VYeK6y|ekVV6nN@n^efp#%x%zXTZlF1)_E0 zt`*htnO$aY%enRG`9aIB0crULlsAv1KDpqOxeFd1^<=0{ z>)XwhH^vR;hL*Q|m{p~ew=#MAlcR2^nEsEm#{`n+m-mdS(j^sv;;y#b9I1u!dH-LY z_WCg$?+O-*YrIKu-#6lkcklc52f?{sC+=ENEkFCiZY%z=cH{9u%dP=w`AEOGf8TfQ zLwEK6$sYsx$yicTS#B6d`Ls^6cD(-TMI)95XsKm2HB}g8iZ9-{`W{;R+NKB2m~%&v zNLSs8@;ELfm~%)HU*<92y?qJt7i0EY36Ubco#hZ~)@-Tjw{_}g!4T(@?c#a^>ysXB zc#Y}KE{)5x@0#{NkXyH)rWUupj`#wPtrk7DZ{)A1-ZD4H^wPmWlEuaz9OSxBH`>R} zzURzf5DZVr^znWo$}=D6(Wm6MUj})eX%Qe0)jT$+AMDBfDFq{{vORT`PEY_dq*xU8W+P!H>)8@c(SK8Q;iFfb*$&5~?1`?85RZ~45Q|fA)xvjLrTO-~p3=RTP zy#kdX0wp^27f1I#b^n!b1Wa>@=H`eJEp)A_CF*wL!EjWfB2<^yc-OL8qVCR{flyA| zHKvxRyJu#wh+G3rO4QxAFi3X|OZq^=YyNr5)63^pJ{}ykh!Ty9LW()!V^D4g?{s;5 z&#_|%rv{Q8ELIMdte#`LFCH`P`Hyxj3I>~3Ra1(yF{YNwr3;@~lD*}!p+RPO&0<>N zDHc<^krOxlcF(hKeDL=ml@cBI`GX8ErxCl66a70Xvz4|dl3$|CMbhv^Y%9evcW&L_ z=@nHKxSKB?S1@LhQ8X!DG-XC^&XB^KAw!15C*;Np2NxcDY`hQ`{`nQv@iVF`m&TXm zySe({x1g?Vvjtt_wV=8ROx{rEGox~Og*Z=&>uzLQ z5i^vA`+O9epO-0bxVe+i=$bB|J8OFNO$P8=nBGTCqZTMh?z32GhKg191-Y1cdeErX zEW3yTyY}EW%kFKnS<>naUbCAXY?hQ|)BIzYcPqC_=fA8~c0frv-9*!zcJP~KQrm2r zGrXo*TQRqya!G|ZYMWY9E#5|P2X0gVrum3$sENp}+-#o>z3y^?sK+bT$eTsSzfKHjmYsMUNNdiB&W{?|VLO>^9~-ahf|yw*NV^8%h1k?qrGv~v4= zI{Y5gZ)g9x?enIC-+$6$vNqU%-s1J2<#KzJUUWS-(6WVQ2V1C5Y2_BW_`k6al`V8GZfp+nv$O4}uQu3+&O=Gc5hiv8 znpZi0aV=g>Uy=in9GDRUQ8^ZR}7d!{k7 zsIt1eVyQBIY@(Q@4OeFeO}Q_!;yJE1KDE}Z_C_29P5f4Qeq);WUEui@%%jiK+=7ka zVY25nM)z8Q7yfH%@oun3$FpcLWOhFijOhv|{PtljDzq6d`YJr>X8atIiG!htwhf+U z{=|WDnu(`vGw>OhC~V5PY5sxl_d;o{d}1AGn=8XlEcGiS_sgx2IVhYrD%1V)%gGZN zTzT*ZzGK^FYg+9Me3fQGk1)p9)Goy9X5=XAra9kk(p4+GR&Gy^+UC;m_C#rzCO=4Y zKlP!ze|oLPeM=^0&O&oii0+p{+-(IP#AhM5p&tF%6wcJf8G z*Bt!zH3t#5!S=PbY5T%A9NsqtqO>XNSiK-g>)!&rR&HrClA7z^0;zDnISB9J0#x^- zh0v~S5_0T&D6fNHi5?^AY*8xf4t^V)hltx?8(bgS2L11dL~&EzP4iZ+74Kqwc@`H#g;_xM|3=@1eBAnea%GFU=i-8+7`1stvZokQ?;r zO>fXC^QQTBb2sQ(h*oZqH#iY)(A_T){|z_j?x&9bDL3f&dh~1Fp!;)wtNfEpf3&iR zPP6Orb4YH`>9d+Pc$$UWpif^Kyg{d&o940l9hFLJfAwQLWDf3d{Kt&W z_{Fv|Mq_&t_{y3b3Df*1eq+XK__g4%EJ$e8e2V8wts27u1{dtGeq{UOg+c`D)sIp%R=t25xHN2U&?*wgPnW7YV1u` zd&envQcqZ(WTiJrS@%PjviD4+tlmj2{Bx3(ij*~aEvC(%F!m#6d(mjV>~u-Yv@fr| zM4mJ@x(@%O8GW!T=V103_C79xUpkZQtJ^(|V%S-Iu{?YHmeA(=4*Lo&hO08qK@ohm z@ElnL!IsdbyH9&N7s0xubL`L4??y3fspev62=t>p5B3S6^rP3r&|95huQ(>#UUJO% zm+XXzrAxzqPRZVvxMV4@zYTQa=N;@e zdr&*^>r>=)?7bB1h!`^+)4ulnRgSYhX4!A2tiqZ60Jh9AfnH0tY}0;Z1^qr3TP2SW zAk}VM37yma6Q`3E%Yd|3!+?FpDw3UkV8ya7wwJB4?9NUX%g)3_)3l#V2IEtld&#}+ z^Q~lxw}<`oQtTm!FdsWzF2>ruv7YuavfIUSju3%1Q=oNPppS!r91hgUzHK!ka@yM; z8h=K*?2NyBYOg>{&f)fIj8^DmA0MdY>^5D?e{^ImKbc;GDt)=$N}?+LFy&{W0=J(p zFe>fSBpg}JadzoR-?FcCM3b;Tt&{ZiNeE2!y==P}`rMFoQWDlTGtH_%NtU$fl6*G_ zeVyfWMe*IcYM&^NSIm8)Jocxds?OzxabpLW$*6*_Io7naju>CV@pB!gT3zYYuHeKFt$7IW0-@cMcRyIX+A&;d# z>o{YrY{cMNG| z(SC2)Hv7(YKvryn{qE9j_IH!E+5a@Q*>|jf(tb52j&O;1;(~4VGuAeA`}VSJH`_Z_ zqc1-IvCaOojR@?kR?-ptFSjp*veDQkV*lQ9H}{mWJ8lF&z? z(|IINVbj}mh3!Ze71jwAwzAl9=Ay!WzTB;_M^Kfraz0viuc)qVN%x9Ye&Ob7$X>k>r|Ov-Np^Z1m1;Rz{y^)479j^DV81V@IZ~X?cvs)NwUUo6vM5*(s0X3 z{iUe#hmvaC@ztF?zPg%+V=p=KLiXr#Ilg)@hVfMlUEQ|>MR#$VK3Vo8i>{8wSFcTkxqFCQ-cM8h%2XzmM z9^j>vHI6glwf?7zPUpV!KMdZmm?IXR^;Wdc2Sb6pA!vQ}Mh6hNxsorvM->2Fy0t`Wm`Z6>^( zAUv(+=Q=v3_{XFbrWfK^%|lWG8)_NQGx)GPeA6cYzZn}#>7=FfpV#Ob>2ILKO!b0BNgdb1$wf=jJ}td$$>f~;lMwyc#1XH|LAy6FL8JgmoRg{HUh0Hfz-wvZnTRQPV_kvw3N%YnrBS+UF$dx79wEUSx64 zd9#yYr*!O=m3~;tQ7Ieq)8U29Fs$x&%A`160O@3sZznU;R2cRk)6B9{NINq9g!EDA zC-P{?lwbUb>xDOm}PA{_iU9|Fsjt z(9fOLY=i&BwkO58M``x#q5kJG>Qj=wQU7v?%jkc(P_82p>f+y5UjJ)h|I#%+Lfw4r zYrNCaxqc8V$1tQxPZz@(+*V^c--8$u+3hh%%1Iy5UHa3=C?-|D!pSgl)5#|(%MS}v z$z2iFr=@sMkW>4?H$D9%M3Q#2F$t?fr1yuWm*b|SodQ8>FQAvs4hn>C#wdg}jE)6n z$8JYqHTh0!F!Z7{83%2{AsU0r_l)VzS~?`jb7B58kKwv7f10OoU6{W*ClTgPa}2Hv z^KU7AeohP{EPPA$`@4}thJ|m*pYG9J7Z$!H|LtyI$guG8qZ3IA^QU`X*M<4hJ*?}( z{O7oykYWCGkLkKFf4Wz6U6?=J>$xt>pYGvY7v@j*Wv&bJZ>fIie#&*UyPs_TCqqoa z)S&#jB=Me6ekj^(scES2)tis@;-U?9{7}IaXDDSpllD9bFqO~ZiAne9puo`r?>;lp zeh9?Q#=i_li+DF5Zj8EBRtu4Nxz^V~Zy_=-Tp%(!%VY{^;axw4`hvxjo5WoI<7eX1 z*(dGNa+JQ^ChK@cAO|fE@hsCS1-@l(`G$}M@Ms%LnVMidC}Dyh3)7x_G5~#58ybo7 zoo6r)v`|rK2>%N{-~5_za$s2zGC$Z$5UmjsVm`QN1qErbptNNLC`^k5rG73=0sNda zQ&3Glob_8qGX>>-$4KUBO=#p7j=ui$v#ouWMg*TqUw&y+|C1!57SPu|MUxDZuAxpr zU0uaO?A=&vq;yM5ZfA9Ya&FFurKM$+hM5WwGn3F`=}uL}tiRwPj+<0Sd^JLATDcs{ zvJIN(!DvJ{3r}+C%h?PC9~Hok*k02QpDg+kAEz4Be^WllSyq~HA|%-)N0^>H#0kI= zJ_XX}ryHjO`}}lc7H}N@3PiYru^Gp532=$81*SZZBY)aEd6Ga9--csa%Y+>H(^l_i3MBD; zI6hm!kKnjU!B6A3R>3dec$tEKisK6v{3?zwQSh5M-k{)jaD0V=|Ab>&>wz4l?-R&v z0!jQ29Lr@OBsNSrS56eXHeny|?_^8??kMTtXBtJoJrsO4@L>ur1Ew}c zj`)><@L9&9K=>@<{6P3DV-;|j436+w#>K!#c(}81Ik2DK&c@ZiV-)}EfhQ{X7U0tq zybE}yg6{^NuiyuPsm+tKtj@;cz|`i+5#9s5QbK`W0=`heKL=i`;Malu_S4yT8~8HC z|Bt{|E0|uA`i_D>1@7tLF2)zYe*U`{wk5CFM6uARr2$iKMh-6l8J&Rr{-~?b9ry_8 zE&Tfg!gn){2BzMgoMm-0=&MlISyp$0b^>*sW%V%5RIrV22)`A;mO-n8xeo7+84Up( zGkz4nj`3yyCmFmuiZEg0U5$Yl4YIT zFxo3OKsL_LK>^&+m=?gDjD-Q5X>1DMEaL|O+}U_FfV&uf58$pw59J2YMtuwm;O@rh z0o=o=3gE*u+)KlUYq+;UhHMSHnkYxSxiP((ut5K1Rd+H9SDW12ufChL6+m z@fsea;lUanqTy@}=V&RtCu?|$u`W1OvB4H zyh6h(HGF}FR~dH(>SK-OzuI^x;D4cpFVgT@4X@Mi#Tvdu!|OG?LBp47_%aP|)bQmR zzCy!SYIu`|H*5GR4R6u#)f(Qa;qPep8Vz5o;cdoqf%3mj!`Ey01`Xe+;qPkrCJo=L z;q4l}MZ@3I@U0r&q2b#!yi>!sYj~H28#H`}hIecDP7U9s;qPnsZVlgKyvpTI^Qf5^ zpMA)9p1@f~T9O>CrU+~q0~wDMxT7(iaesl+jX8{O5V*6koN$NHlkue)M>8f}CdTuV0=TM&zQ2AiShjH zjAwn1lOAMoi z{E^Q(met@9u4Q>5?$HPr(!H7+9uqIZ?s^W7@)6-7MR-UN9&$8=hZOgcZumzz{00t> zauwkrX-!##^EpJ@TdH0B0QvsA5z2*DdL9=#Q!vhzmmhFy^8RV<&lU7F580?WKzkMA3dJd2NS%ilabGx_&%^DXp*{&ik1j*#uO3l%gq^jlU(fmnSpPihUt;~hnB>EuVMW<*8iFHcsW_{X-|9N z4<(6sC$Roh*5AweAF=*<);F@gQXb0PFw2`p;PZ1?zWokaiv<2|JIF zgq`z`u%bD5I=8cC$*4U#{@bB-*jKa3>weMmz8ZPu@3 z{TkNa$@(W){|xJY&H4{n{}LTqQNfP#tAqo4Zvwkk?=d*qd>$kA}8rJV-{o|~E zn)Sb8{Rgc7nDy^>mGOQ-67d?{WW2|bM7ftAC1PISy<|6!7_{}@T+_g&V1&ib!d->rw_4&LSG*R21L^?zY~zdn*bjO0zY zK9Pi-8LY2heI@Hxv3@h_x3c~&)<4PmAF+ORT-vW93Hysk!v3wSe}MHrWc|-s{|@Wl zW&M||&p1Nb$s!3m$C0G=$@(#@|A6&hvEJ${`FSM4A5RkLIfeCeS-+U|%UFLU>$kIh z2kRea{ZCo{3)as$QrfR33H!AqDZi|Lfb~CQ{m)td4(s1#{g?!V3D!Tu`nOpBG3yVoKJ6$OZ!eO_SDYl$lgIk;tUrbI z^I5-)^%t;y6YFnb{cWs&iuFHd{j041jP-b1SH#vyyM zan?W0`d_jB1J-}c`qch1-or>D-aaG|?{L;nV*M1>SF?T%>({Y<8|&|2{r6e_Bi6sd z`qx?iSJpcNWW1>)5$|yZx`n?`1rX@edf!XM7*y1&r@!T*>$W#@}ZAAmej+{%oOqPln1riRz=8G0I=y8pbGp zffq4G`3rm=W0b$ZwTw~z0@pD{`3qdn809bUV#X+cftN5w`3rnLW0b$ZOBtj51zyG& z8E4iE%X(d-$$(2@erIlQ1C0AO>l~(ek zl{{%BPg=?25|LK&q?J5rB~Mz(lUDMim7&tgP-$hTv@%p$87i#|l~#sID?_D~q0-7w zX=RwSGE7<-CanyUR)$F{!=#mA(#kMtWtg-wOj;Q(tqhk|hD$5MrIq2*%5Z6AxU@1{ zS{W{_3?Ioa+iUO4D*HS5Z^sU*uUJ}dh~E=hdPP5s)$}EEl@)viU-MC3xmSG>y<(q; z=e^|~Lh@3nzCxdf7ivs@MP4sAu36_2wALri7ss?G^N9I4xu(@QQgeCYokMI~~+;!b>?R$}7qi&o8d5o>yZG zlE+n*)fMjXyxP)*9w;pU=Gl=i($AU@RYg3{{hiYna8{qNE+X2!JQW?Qk^f#~h9sh?kw zs^9-E4aG`}ZuuIgo=<8yDn^vkq8Y}&;nEQ3=fB2vBEqGixVUIiaoOU^s`BE}`uf_+ zvc>gu0jXQIu)eg+7*tzP6`DQm85Us+Quy3Zq*Cx!Rx-uER#qx10S#B(n1c#Ss}7>}+z=kjJiquQGaOmi}> zb9tDu2=H)g>wSwvT$i_A<6-K?`vytnVG1T-4^t%Gw?is#zs7qGIE4u8+<3nLR`c-_ z;C3#F{RkcblFIuPbkoR#oonwzjW-ZDjCYpCTMj(kH3kVN+!Bqqw;3LNqeNlccF^0x zTq!BoxrYyFymM?k%W_GOF7Gvs_X2nuLU^BRJo;7z(+{3=?R7(X=-5r)&%t}xWBKup z)OeRUhOswm9U5*o>$R$C#yjwKh+u&iE$8#=^z9ph#Hy=~c zs4%4QoXdM#<2?diSiAbC#(NGt*ESh-?R7=@yT_#83tk`0&Fbz*jrXT)eg{t@>b&D} z`CYpfcr`=$ow^oy_YUWG=UU)RJi#!;yKyb>em9!mL2H3G{A7MNrUl-`1<~xiUKq{Z zG2{6ivlilgequD<{8Razu@>y5qT?0smbJj!jZR3sbJPMa6DNmwx2OeP3FesT+|r%i zuHMF6b4dhVKIWLkJ6oDT-QFI|HH&w#THsACiI(5{=0?k}IWJm%FI*5UzrR7JE8cl( zAs-!a0Tu5yX}rPOd43Y+qL0ux1a)39c#RQw=PWXeuOjf~V9xvc2)w^Vxvh3| zY+KLA)tFnytJF=L&bz)on!WF0Za#{=9hkent4XX)%lUN7?MLB#6_K|a&j_N}n}ufx ze~3^nC*j$`DG_)Z@a%!!Wz?Ns&Y$7gL{S9ZWIVIDHv;d=HHPs-1m2?;8OA3Ocz59$ z$fyXscQ2OjO16~WnHaDRh+uE^23!YqW59a(b-mOuu8F|A6TIJt@J4CwbB(^v#OM+ZK`cT0~y=D@-gQwo_H)roR5$&Cb zi(3?Xw@2i4+7>Op7l0QfzpsNAC4Gh0MYDG^c(dI?Q>0!W|A@$&fx+|JiXHcGrq&I5qT>k@@|aCdn_XF zjflK2BJz5DH)8okpUdqjeF;KDN9_sdTBJ$>dH^McdNZsC6@Gw=_#Ob^jBib{!N3%B!yyKe0 zihEeCoXaBet_1J+2=*S0$a@#Oya@Js-6Gfg)Tw$trhu2DlYn*JYVe}u67cIZzz{`$cZwYu&^1BPXDEWN_ykjH8Yup;nTZ49mKg^a%cPw~e<#G*3mP>*x z0q>qpXw#-YKh+WXo4`v|cpV>*&$oU6T?f{uKt8AO;tG%KkR#p)8gGcg%M>ih%ft(o;URY4%ovM|vukq4*~k z##^WG+5Jz?*zQg56O8SN?)G@ygA_I!=HF@{F4jI z?~MxY2uTa&y`k{>CgAmY*pK(f1iU#4uU`V*jSBCm1iUvC-q8toy?*GY@0bLG=GXd{@g*Ph!Z;!$|D*#Xq3Nx|+c_G7>OZAifD ztne;P!0V^*E=$16Q+OK_@Wv{<%MB!LQz4>J=Uy*)_{sr|>o> z;B8fSS0&)>PCI2pi>?37FH~rJ8%A= znzC;Xj+4tCK0J3w&hQ~QBjfQQLZkl1<2fUS4<9DVS z%`@U4^fzuXwi`Qp_g!L+8r*1nwe!~9-3{Z8?ndM8jCQ3B4Sh?YwRUG5Ml!ZLqjTwz zHO?mEz_?BE1ACGhx_{ibr?;~y|G=|2eyZ`=-g}aa&3k%x0w@1K5`N_!tYeqM6h@wPQ; z=Iyrc4OZqJ7IelQns`Atj1m)V8nbE6c+@?hb9Q=a4z1!6E+}>bXV=ptZZ_h|anr>^j zJt@EO_TDLPB30XO&-kpQp}`zb*x1nhs|@3++k5Zc(r0tS@ySSO!`g;jO;eh|DNW&& zb}n%?O%!F*UzAM>(qhisVKi(%qj3*Xv{y+{<5fF*8?TtwPEk5Lk&d0cEu>>7N~iA< zDxV$4T)d>;fjf>JHPhMD@4y+2&;8^lKfS$oLj$Gb_N3iEzT>4mz16(+U9w|KyONzr z&Ze;k8vjCdLiMrdsl87pqn^ed*uBLskLFv&5h72!GkS_V?M5y1uF0^xcCl^mbteO% zRczaL9a>4xMzoUlA#GyMw#KXWUPtMpxTvM6?JvE2cgAt0vR&@ZXph#|zx4PT*$xk< zn3HyAbS>>CV$MX1%sH@!W1b#}IT>lGJtLmj;U*3P6|9d@F9zk5K`!F+Q7*TEa24i@Z5qLiDkpY$o}DAa#;quXjl{xZ_b zcV>*_Tv#3Xe&(CqUNxM1J!`eqk}`j-T%S37vPw6T36+ow?K8 zxdpqkY&!Z=nVaT%g68VnLdo~_N`6eB=sJfuk-WJ|6qVbzt_!QyY$|l z=bjb^NFxpPSXMn9nC2HLQ^rjx96zCW@{H*PQwmR;S~UH%$&<%TFD{&RM)7G=C*zLT zF~3YiDx6%9jS@7!l3P@9q$ASyo;UUV?th3Q8ZXk=l!}Fg^X7A0HP!XCHC5PaYz985 zwXH@so#JU0oB7-QgR(CB-qN81R5R(W@g%Y?UM^z#IsaI(|EiKxhLhfl)vN(BO)JGr z=Dbd5npeyyIaX>SMh-G*rJ?M`!W_p}{-b98wJx(sV@8hl*MEPbWB&iWFD^2EHn)R-Y641a6^|__Dxl1D5Az&XScvn%>KW!YtpMTAB5&Go>jXc6&zxN`>z^CT zzZ-|jOQ2gWMHO}RQ)F#L+hW~RTC@?*QP9uBmKyJ-*@dpclH0t z9|Mu4E~%+3H;kivTBlh%UVrtX5laI!r>v%?iY}5gGs>m=(BjuNJ#faHJA%Zz%K6n5 zN$mc_{4bYweRJ)--Hs3P7gq;Dq=>m;4zXs)skh7xGQD(gkYuswI|sS$(~b7A zv+p@G7^JdVn5Ic!=9OnY(4$YuZ@&!kJkugTvRc?nCf>dKCo?*o8VpcXQ#~K8MJ>GB zN;|wY;=RKCL850_hDa7K9B^8u{^ID~r|!SAxD;Uqq8Ie1DX*p0;MQL3{@uG9*4=%5* zTvAb6RarLJ_4PG8pr4Dh;kwpJk<6W2H+VWHXk5XVNe6AaY||<(t|+alsyW~A4oHRN z5lBJ8=xTX|+*b}l!yP%j^qN?5g%Au>VVQf4EEn_0$ZLMZ_=uSiXO21{$+FkA-hDw=o zY?_yv+%i<})@~RtnOe*68ir}k!KxT?q~(sC0*%FR+e%Dfx?``Hc~0Ge%6auOORGGK zF|%x8Y2CR&)%4nm`I?4ThM2l|p%>JdK;>lIaR{2@B*fbWo8w)9<~Xgkre5|8qMRwu zrum`Y9u@!AZjsr|w@7Q<%0)7vV*DT4g{iGlCHswadPu`OCrZOC3u%~W(`dk_&6|gl z)^DwJLSqH?L(p33hNTU*)^h``Rn9d8?u@CtDetB^Qt3uRh^^gxza^V5*0JMDt=B5h zp<*p1WzNE#hCu%r^l)b_!aLED`ig~%JgZJW%DPc|2-+IWwzt8yMjONUJzvNy43#(K z-83tdwiZHc?Y4HI-q!qKU6aP;Yd5d?+R)H%U4e0+--w){)F{O6=X}rJS{1cWK7^C^ z>=b7q{#z@uLwM70nBOWYt1IjIl7d@y&a!F#!tH_r{;l0KI$5G^s6B}?8dKHoxXT$M z5=|@X9PGByMz2$+`)y->Mg7dmnyOM-P_Ll8ytblFHW7K1Dzn_W;XWjc-r6l@wQMn% zWF3zM|GeP~dJ^CYE>-ViBIQs&kyTv%DJ zJV}waMBnFD6Yy^B`v3jcyeT>yts`c1#xK19*oZyZNeV~8G#|ik%s5{hn?|1?p|x`* z(&6Alq}O%qKO5~GXXF&8z18{1DfX&UufYGtD*L?Srr68GzvI|P;$4;`%R<6mKp;Qi zhabv>Uuq-avz_!wPB*)1pp$-*le*4Hw=WpzI6E$?JPsMk>N9boy=tzxxfT^Px=bA1Jl?Ck%5^kNnVa z*30zW7f4_4Lz%uDByaesbb|J+v{y|!^?3SOZ`U4ss=ZA7qpbTrEtCDjK(dcGl*#@D zou8wJAlm4M# zPm*OKS@(O%qU-q~y=;G(A5yR8-_ptCsMGQ|*Lc_xMj2NEg4a33@ix{59=V9RsBZjBh z{IKxfH2obT#!quxVe!w17@lT3!otTQhNt`8u<&1}{LN0Lozk&eR{CKnN2P4cPsbd> zAj3`>-Q(mQ)hUPvF9BQK?UYGzct~m|Gt*S)_8`;DvQtPqGW~?~QRx)$lKhnQ`RN<- z)3@fg$EYpOv*B#G&@?)km*&$G!hhMeL!580$6qp^m9o4}w($}EpAwyV)e^R_?%8cBcA%*mAczi-` zyl`;gvB$;>@!81yit6|o)s;)*OLB4s4I7j_XmZgEcr030TRDG0eZ2qN0rBjSBZnQI zGbDRNyr^PnXDueMF#ne9)3wueVd3f8=(;d}za+!UM@>Ji zza-0_CXs132c8ma^6oX2nq<-|%?eX}*_M)Zj7OxGO@l<`El8pc_NerxUyvH|=2y>U6PU%%}Q z+V{_|-}c7!z<&LzhP!CE ztA@L2xVwgXXt<|_4>Pg?`RS$M!!_Jn!+kUy*YFVgQpRt;Mp)oz+KTgBrH9SGX6E!?Z!>4HYR1Hto z@DvSC)$nN=o@UU#7p}9d(=|L@!!tBoq~S9(JX6DGYIv50&(iR04WF&yImUUM{z7CT z6W7m+8Pk18CdLQfV@%_!OpGU$&(Vu5Cru&vmx;`?dYh)(IZ?gmZ_C_^hnZ8tB-v@(GxOMoqF&GmPg8(7(Sr)Jy z!?KX&SeD~h;^Hd8VUQ&xGA1NqNFw{^$t5l9GYzAHu3fdPuVXz1fQvXCG?t_E%mt6+ ze3qSY%^}>Au03vekgJG)7KcarMR-WM=G&0-SYArufj6n)7jyX896q1JLzYuG$OSBS zQF!3*tKpY$__H~D0f&dIqHvHjwjeo=!b4W6;m_yrb2$7M4i729LyGVuErf?$0_o*{ zDTn_She!R0{6m&fypUAhBs)@gNV-4q!Y||S=Wuw`s|XJ%${$jcKO}{-A$zIemvi`H z4v+RA!b5(W;)SecIhn!(PgldQ;P53J9_>hkhZOmT6#0i7LE#}!Qp2z0@TD9c?N5Y< z6!ixw>JKu9!b6fBFaH;C_%aTUb}Pa|iu6N@^h0){@Q}1;vKM|8ho8&g(cVRPNKt-} zqWmC5`-Kd&-!*caY?sUNuD#k2_bxW{S0EbFUqur7XGlW7pY^Y?{x7Vzshq)2CJDZ% zfAH&APh(orH;{z>QPw}ndfHo>^zXC&Bi1jYd_zxj6l9;yAF}fh>tAI3KGy$%^`Ei+ z3)Z){r5zf3kR94Xmh22;J?+&*`pK-H$NHtLU&;DytiOZx-)H?E*1yX7U$Oop)*CTt zKSmPq9zhcM%4Pj<)=y&n*{m;S{c_e{&ic))zm@e5u>Oave}(mbWc{C5-`){RY-=XZ;UY{~+ss$@=$L{~_zmBpGiONyOWYB;q}e^(V1@ z4D08xzMA#5tfzSdyF%XIP=74&JjN$8p3gX+@dCyLj4K(BVf<~zg^bT-JeDy!dAgsX z{zJrv2>^k|Gp=SlfpHCEoUek9i;Ljn{6jVj`&2o9LFpHGGGnA);3@N5}ATN=og7P6&@Y-uA~8p)Pca-@|UPJ^_P zBdz2}D>>3ijj26Inqk5w2~{W43$=fN-IN08iVR9 zme$MP6T&8)g}>{gPBQBr%A~UH6*7seQ$i+<0~BSFIG_(q3I}|`CV_QA$fU1MQ6_nH zuO^ea0YYFBcTjmn+2Z-dmDTfV3_h-^tgdj6=i!}w50sYSQ~V{aSN*a@6?HDa;~V#| zw6?T*zVEXL%L&0oo%`S*P%d1rsJ)P4_B}(Yi9J!4Aw}hf^i~1!RZ4U4jWj7S_EKus zCo3h-%D~eQ)&+{$58U)KGEq7IYv|rLP=UsZ3Ra3+_i9pY0Yab#xN!$s?bm4a5gK}N zanYpWvc;8E<;A7-^|h5{i?Pg$F{p0Y!urxOV^Gl~IxMTH8dO?USqcvtpEOk9ySLvUwv*hxm@P6Iv zZZb4F54V|~b9qN-JbJHsv&ZtU<0ojm6JTIV2oFPmK)idwqvtlRbK}J=XMjidg=$`0 z-VGY>6!5BCW9&!pK0bEK1l!I@ew&9H{m- zgSXQqLAt!-G~Te7|15;)E{~o`(6O7olfVnhFWnEiVJQ3^;B9aNk%C>l#>+|Pxf7Sr z4DZ@@e2>`z@7@kP7t#VRzZ1`Sw7~l)3;9Le=}ynb?5;eAp%Hc7%iVddq6OX`FsUWx zBwFBEhx6P+3%sH}Jjc)iZ_5!pm(T+5$4Bye1 zhdOU7c$j8x;&k4}5qXn`MzgmoA}=;9n!S>UyvHK)x(_!DOn*0Vdbuo#$lD*0hlvPd zMw3{v&x=;S7lRk2-hKn#B_Z~1*X+$78NO%z4>aD(;Kf7i>Aa64@;YK58pYm_h`ebL zd5a?QHb>;$6Os3FMBc{{c^&a^FH-q6!+Tn*-)Z3CQr*Pqyyf8G(%;1Cyj#J;rMijJ zc|QRUU0@TZ^UTrFczNJq2-C#r_U3>WCBK(|hf7=&r`vldV*1_(FG{&|IWbziN?zzEh|1@)aI#34{x?H&Njooq#t@;o;VyS$ne-UVnv0&yCgkEdj4P{HcC3 z67ZISm(M(EPvlbYuiJZA;dK(MaNcJMFEase#3Vo7tOUHJ3a@hl-opy7O9I|!3JC<`n3eW8?!|Y8{c(~;gE{s>A@Ng^FEN_v*8zM&aQW ztyz1U6&`NUn&oX*c<%KkEFbqMJlxteYwszA=l1(y_Fh(a80t4`?`?&LA-u;Mqt)-n z3J;Gro8=j&`R!nQ0$xXjhf7Yg_Tma}VglX}g@;qLS$p{k52s4AylDy#r$Dp35`{N8 z0dJAQo05RHM&Y5zg`@h_>tnOR!(p?$?Fw(2!aGB&-+RELctOUHz6yEFvJlgo&t&g)4 z@KO}s9EDej`gN3XT}SZT>jBe*SOFf!lSZ7C1Hrr0orGW=hKR;mjdvd^>k8;pN4&bZ zmHq~W@d$eq<_yh~yB4;*N8y~YGB$UQ!d1ov#*SwjE=zm)wk=zywqIyW?^)Wg;lj7x znb263`ttfMTd(P0{Ie0G+vy#IKJDeLdyPKNH)c%#XQ}J|clbA4wzp>rM!}E&py9HH zwc~F+<=Kfz=75~Wv^N{Be71YzlY6^=fj#K@{H@!}?FM%F>oL1=LSy6R{nzZ?(zyAJ zYxeBz-gx`AJ*)TjJkoe#BU!oow-e2~e>>i2*tqczsm8`XVC4O7YJUC_!?^oh<89;o zP45~{8RuUHJr-R$f9I2#8MK2O+5FixJ7M$nYsk)R8+NRvyzNBZ+97Y zj?+FEYgNUkeNbps=3#}23zKFP zPAVQhY5Zx$MYD$BtS~Q9HDU+2wW=lu8$FrpR81~+(laksHF-wNF)vXyLk-6<*Q=Ug zMv`N0P&LDiWXHTz)r>Gw9P=_&Gtx+P%#ErBZ_=bW=H&rZwvq0bR|Hf!Mmxv6GN8)E zYFg%|fGW@E;Fy~Os-Z@PV_p?d4Kq4A<`(&N7?<&BFP?cq_xm>eK8~XG%Gjo&Em}&2 zJGo+s*bMJ#w=&cUno`>P@Y}C{{e(bZt|05Xe$>-N1z9(#8mb`cW>rHKWNlY9R6*7) zs)j1a`ktzx3bJlhHB>>?4pl=HWZkA}sDiAWs)j1ax?R&}3RD#*GkprQ)0z8|Qd6DwAn{?<*0|1MC*qJpLeD(G&vG7P$p<=Rzu zqVsAuIpI!p9xc|wPINvou&-RRJJI=kZ$B})cU`kP(fJ`--iglVwzLzS&-BvK(oS@K z5V5hGBfc=@B35^z^Ld_W5g@Q#++$hx$D2O=?37@I%I)H^hl%at3S6V=c5&wozw=Lj z9dp?g!Em%)oCwt=R^VDzH(a~urjOsb>65z9YfMaTaZV~~_ogLT7ri+E?Z?YW zs>^i9f@*o~g=bv(&ue=;L3)pF#a%1nvsAXMZocPHV{$9KW;fsSiC$sK5P{Nkx5x{m z!v5Db-}7R!|CP=6yilp$O0JX$ahuHfRyW`C=px@OZNBHT1DS7W^F2RUOPlZcOn);y zx*_M3tDEon)M%UU`Ft? z7;RdXoQ62(*H+e76k?Opg4){BWt3r&W78}R@olB`#bkkBD;9w*!|syaYV_D}rBo!# z?PyK&oT`fI`SlA7w@=2x_9BSC(ET)KxV^ALld{ecB5PmxC*Q$oJ=9cNE2g=JZ2L>Q z5#>nj18?!3S$b}TSSOwen6jH>UTf-pt=e#Il{@wXT8`c<9GVHhng9p8_n?7j8?67a z+j{E3pMS#g)(fKH#hZc)yDH`f+350*ZK8_Eb?UmTA=EGZReXVDrefX7aTPY@pVak zMQ!ckMe1HEvH=Y=-K#+})K+ayXGIyv$X0Re!EP1wgryDkD0D5Ss;;Om#Uf^ts<~kx zv+|*mX}%Ta-Kx#ti;!LgyYym~i^kdNhJj6PeLRjgWRY)F4E|qp`8TXgY1*^~1GR_p z%DU#-OH7Pinh;vG#q z7SU`%Nv+y+R{UF=&SBJVink^cZp)J=reXGrjGKQtI2${71LRgL&IKa-hPUU>Z;ie& z3)?N+=gf**vGq$~vKYfpvS9eFR++7FjaQ z&9E;Qi=_PpMjw>z8oYADBpRABJ!Q79r7cHh$TVfDb!l`zxM@0wb(xJU+ua|CS@v7@ zQ8Cm0-pZro@fd*bt~~Lp*?^DR3zM+?m1*7(sHu(zw^Wpxx`=A3KdNl;6iBN_ha{}# zWtxE#@csS=H+cuK(rz}76erW)VmF8r@Uj)BGCozDfcLDBC)=YA`M0-!w!F^ivgu;M z*_9-9?=1Thbh5EOrB>_Th8)~-Q>yh2tDECYcX}^$Qr9}pB-;6jet#u?8tZ_x9+jh^a-%xR! zgf8!~ zj;MBMy4JH(7Gfu2nZ(HsmkGTaOm^Kei6^kp89dj;aS*n@%QxNM=9`A^6*2u(KW_TX zPS}Pau)hpm74x=(`Tu20nM1OD3T?`B8Ev$abkO$q_*ZMTbvJ7HS9T`(8Yyqh4Q3+S z4sM}hWf-|)w-kRb6#--Z<|&TcJS8c(TS~IrEhWX>EhY6oW49E#!njV%st6z_bLh}N zlB;%#+d4%nA6iKZVd1HFc3qf%-1UU~I{xb0{9)l+@~1Gaqc0F;{%9g*0xsG#8Pm*L zFOo>bz$J%GY|~ei(k#sjyUZq2mSBl@BPEsQ16^w9G!@ZXYj2P=G7d+3d(bzL?)Q^~ zX@=YVUXd_8AUOj6@WUsGEcxM+#JAG!cagL=29`e%He~oDu}=fOHxZ8ZwkX6= zl7i`5t5gNkH%9FhOyAaYP;fDh{rHo`-XMPZlf~X3a@L;GpDfnnbz3yy6$mdM0!jai zfc^BO7?%S3`AyOG21yZXxVYmc+B@SW@csBw#NHsjy;QL`h;J`dtas(-CsphX;@e9V zdxQA)QpMgN^emj5g}oVm3fWO0iC@LBpZ_$2?i=JhqV#`iT4B8GHBgk*V&jR z>k+^)V;E(bS;1uJ^08SO_5BuTMj28m_?KIq8!yPo7q2Z1i?xf*N z4QFY%vxd7E`vd9gs^M-L?ylh;8t$p#!!+DW!-s3Qw}$&@IBvWhNbeCE?yKP=HQZ0b zM``$I4IiW7{u&-&d>Ba2K;xeQoUZvFtKs7`e7uGSX?U=PhiEuk!#NtxHBw}MEt;rp z4b}Yf4B8ONb+$E3!^1T^Lc=39e1e8YX?V1TPt@>9M&CesPS$X~h6^-2M#F^~9;@MT z8Xm9V31XdfDxWz1X)gqN*Nt2p|Fn0(*^H@A&P0D!&$zF^ma(2OjZ!kPx6qA@X;ejf zBhVITN@7#IkQ%f7(e{@Idy*N9)w@+o#C&b?jl-Q^|w^9|;TnWY*&Xxsc;SGDN(^ z;8FZy&3MRMq?s@cZ%B$Y?_E3iNVt;1jbJ-Sudo9-hwMO>u>72*7_PYCF+m{0kL2*k zrw9)@oA{9DusoUK2OdXd=!VC4sv`Ue93JH(!b8rYaF8M$kjGGX$m3Yj^Iy*nCU1nD zQEUh0E9^ju_#wp}4v_S!n+-XP1<~-+d=&ZJCLG0A?H)NAjKXCkhEr{myYQi z9_yfpdKtjsAw@YtmQ#4h0Te$Zjr+Xt_=vd@&_0R7qdkcDAxkM7q}YQ2@^}glN%iZ6 zFXHegbNFL9JfsK*N&8jVkV7dvq}bo-RBl%@c@Ken-a`N%L5sZ$pkGPhpkG50`rAoD z|3lV4&iZs)>JKLg{t+a>7i;o^Kb!UEu)c;Q^cS+8_CF!MSeqYuu{J;Kh_(5le}Va8 zO@8R#V*cl>Zx@sCb|eY@(IjDK1nWn$ej4k`SU->TYgzvt)?df^-K>9{^-r_@4c33e z`cGKj*^%)cO%mxGND}Eeh4ph-U&8vutY6RijjZ3nda))y>^#EypR)cpB%%L3>px?C zT9VXvAc=Sfl0-R-W_>>E%UEB}`lYPj#`-&0|9#d!&-&L{|0e4{Wqoq8j5nPm;ysQe z;ysD=V^}|v^$S>E#rg|be>Ll`W&ORZ{}Jn-XZ>*o>=*Ew{73Q{{bLySV_eAiD8^$M zAI*3i<6{_)XN>b(*q^`{=c~XI8RPsDcoJirPbdb%K3MTV-%d-*zotTC2HNja2Umr5d;Ct$`3cgR1Sp?rJbk^YDEk;iT70fJYLb6Hf z(6o|=HgiO(CRrw>|78Rry}XzqszQ5hoW1D~FhrUiRzaN{lRUs~YZhZ}rxpQ7=;0#@teBh2?7p>YW6ybMg* z(muhu(|Hr(hOt#A0qeY9gV!~Jy}uxFH%G9yxo@=ey@2uMo(T3X$GG$E2)t1kk4E9W z4_;b?{2n-3&S&URQ&=_lYZ&LM{aTCz=sa47K3_4`9B&SIYJb%nZ%0Jl2jE3X-w=$) zqoi+9MBY6Sc^@~!>!y|S5ZoW&RBz&RULknYx9d*l-5ink&xpJ;ali6yJyKvj-lxHf zlD@-nb9PPydn>?;V(*s`dAYd%i(+pRcx55!J4&m!zkpX6!W*LTX5;=Y9)Y(!BJcW$ zyhkGPeif1Tc|=}M+{Z@A?+Fokvzy`3+$;V(w;Vj2a!s7hyA?ciflZvwdl9^TO;~bl zp~m|mc(^n)ak{+>+}ESaYT|U>aPZKynmC$dcteLOH$S` zECNprM^xf%)$Elh_SE%vb>0Gn*PV>Ph1pxA@Z9INVZ5aZkDgtS3*)U(cyGCk`S7LuW(rogy;%y+y{?DZ z+ote3C$RUL!t0{&?$_$0JD#)9dd-wR+}a37@jk2ZUdD3}Di7ivAy_gWI`3_T*Ea$0 zV}*yIuW(`U8YlVjy8UVxucN}lkhWQSafRph=VA7SC_D^lo3)p(@cJj^ zIhQCry2mF+>C<_O6dt`>LoSTBM&aR<5-yClS>d5+H_O|u@X*AX<=vz3(8QYMJ*DtQ zC*ZxT@X&OcwfDBd!=cA}Pb=q-;YsB{?HP~Qgd?o;K2v!4k|x6GJTl_iD@edgQFvn# z@H#5I!UVkT3eUZ-3Cl-Z;f+gRufM_@pMW<+;Z0C@U!t6GJzmW!V+43TU7*Me^f?$G z7;)B32k$-TR0mUHUv-r?3Wat=2(PYu-a>UD;q2kVbBE*%ACfaN9+&F{tH1I1h~Xph z;=;AOj_|vD!Oat??T_(de`Cjn*^N8*+D5~gzDvvj_RQO3yOSF(>-6%@y+e$x`x^gx zabu^Kcl~(lHPCE%zH#e5gK^I#w_)AdzDsuO>Galf-5bA3tLeK$hThp5;oo|$r(yP7 z(sxPb%eP^xMOgahrHz?y?E3MZYY;L&4IyvayVBURuQ7Q;qts$W+_gIp$BunS&4#hJ z?m!9}*6iHUXZnLPclME~+ZDSFsq2Due^-Ci@U1Q{BS!l+q>eOiH+Fe>CyujdRp2#Q zFW-UV&f>W9%e%L2J-O$SB%=;B5ffDt%X|6e-hH3mcTyY><1{&%HkZ(WX{~l>s>d$7xm}0X<4}3g zS~9lEDl9NCb@9ToidwwOw$4qVahV^y?8U#P|9DAwqE=XHlZqEv&M$JqSwgg62u5puX zl=@lO`uw8}pDj062LhYrGAsAW_{SC$6%>y@ZTgggqGBxKIc5?v6SMAX>Y1A(Jk6N( zfb0jkxKHi>tF(=O_{I1@Br=7kEv{d*xPEMDed+j`+J&X{NaurYnwnc8)~m6kgiFMF zG`oc*Vtrz?C1QPkla(X;`z5<(&6cWuTc>^&$h6(^60yGZmX?V1nO-_tS|ZjDf@LV^ zdlkCN<63f8a}6fgGc5uH7BzJjat#Eq{SC@Q-ELtqSD)x*yM@JEy%3yloC5VmFT3!z(hhHpc&~83x-_o4ZVe^X5BIMu z=IVt?ac#xOSaXZHdUTQRmKJmM*@4Wrw3w?Otfj?VeP)Y`x%yOXG1p>T#<_-DZE04z z_|K(cZG)@npqW;bR#nxUZ+Hi!!t-%bkTB+9K*UAdTB`|(@s%uMDrOoQwpLVg58Vo! zvLhH7)mC;%n)VMaoU!(i zR(tc0SVQ2=3;IL#rdc=ui*cmdyH+g|3voPd_8;&^`@8tHQZqoiQ_w!O3J2_!D-CoP z*KN1ldbianW-ItezB!nF?MnC~kAYqZsl8rzxKnxM1q7ae* z(S$$<5fA|d5kVFsA}+OT2A*KG*4pJ0+!AdS6>+Im)cV!7w%TgzQf-y@|DCxr_s*TX zygXZj{`oqPH}{(g zy`!#tuWt;(7yM&;jO#I<_PB5}WOO$J`DvITY-mS4Meh`UO5lvZhD_{cn}c+{6McG~ zqK}Fn9Y3Z$Kf?YxvXu{|yP{Bb{-`LX`+c;}{yy6Bejn|(zmJX)-$w_&8{bEZ-9j`> z*zc36WrgdH3pQ%8rRzi}n>5uat1cHyiw^}WO^YP^oA^=|dL^<6-)H;{-P^uTCARoh z7LT==6W_{;Jyr3oEDy%!h|cbDUE0vH1OcDEt-Q=bTMF%0=osg@C`B`kfI`PAbeuxR zYl}VUB`9Iv_n&|S5s zc{piY3cf{tlhdSO^eva&e)cz9zXQ+oYZ~)$kBUpp>}bE6Vq%D(Z-MB+9OL7`8@;n) z;=$y69*@>z6rX)F1fP8~1iu`*Nc<~EjYWJskYn+oFf2aOWAWj$`0!bL_%~5}_ziOW zuKb%FJjkSHw@Bve;ntRaQ+pXKcDm0a{hMCzl-w^az6XU2=ZUz{6BL37vzKg73ZfwrzzdO zGpj1+SIBhb{5dr;%`@*tm{VI??TLZg6yU9Vh>xe!I?lI7_!{G1;l+RsuU~eQu-}tGn01S}_3cDN`Ve^;*RB?|7_-nH z41=TRpfWB4>zuSGa7C@)Zdc^h0!QQvm_t>A))i0OBMi2n?5Lj@uEkK!831lM7` zbp!?L2M&Kk&)!jb8Z^2MRS$DVFn?ic@;Gz_?KS+#{A0iozq`Z_hkIATVTxmpaPQ$y zmiGa0B#Ztqy)qXL=fixPiBQ6c?j8=8E8%GDAxF5+@h7Ld2DlxlD3T|1o^Y|KD;d|f zhdnrVv^~lSWaA-p2!r_V~9GcL<(U~%G{>p))_>@0XC38fp zxGD*UqC2=O$V0t5dQb;kxOY*e0SEol((I_(Cg48i*TMrtyHvql3t{yBs_ckdwBYO6 zv>rNic!vElO55+E^qp&`Cf-GPQ2P-qNFTiS;4b6%o@Ts5a$WY0;QE9k!PN!*&L6BD zjgO6cEB=kRW5ErR8=AU@e(+@X(A#*&WY*(7wKVO;Tes~$oTLRW-GBI_(D2gaJMO(Z zc+UQYCqtpTf-{m1?JBvgVNNL6FYd^#%no)k>|h6u=&#>8E>Zh96z_89B^}E42WAP* zm!)6zi>q;|>`h-G(%tLq)UJIix>SPeb~iK@e=&#bTJMI< zZY8}{a(Z8_%3gohN;|!K*2ljYcZ^C7%iM2Ycl^+Ght`s{?7;CotL~dou<5?bE(zUm zEI9gxH}|Z&Z^roBa+ln5+4aX@wfnQR1NY2$bb40uqtmmEoRyjNnzrt^UyEb$rmVgs zwDwqV2gS+1?H;^+bK|jz+wOs-?fWh>Sj-9A*1n0@fne~S%OJtDC9H>pgAeXa&0n|Y zIbFLo^z`8eLf5_(e0I-aLut`NXbIt03iQ4hdeKYPu zF0um1iSLGE8{W(rw`ayZmrf!z39xkX0}~-}!u>HUjR}m(zkj_XKfvW*|Mm?` z{?vYYIQho)$8PY*w@S_F69Re9_-f4Qd4UPftm88GtP8F`&_7vgY&cMN5A^xv@uBL# zk*(WaX13AEp7_hKAdZcl8pC*****7KJNJ>*^QmO@oZB9UZS%tz`fOY0$&$VCG_CU% z?aq>ruhe7TobY7NoNS|a|IlOCT*AAy&9khkrtT|4O+8n!G+riOwrQSCw$$TcOWn0^ zu4VeQA7JRQM|}qFuSj@0?wui+mYv*`a%(Ql{hsA7bkN2>caqT=0i&@v6;9)WI+7mr2 zW?wts!?F!*PxA7Zh3)gbJZ56Mz{_JcwkLae%*gf>FOON-p6cZ>Guwq8UfzWT1@y+) z1*m;`VU{=1_*ri+{Qc8IkEMa-G?9-Q#%mtENEeN%{mgCPo&S2^@5injy3-Te_#eB0 zXGrN6l{gK2nTO39_;L@6HSkOii#6~p4~sQ$sfWcHc(#Yd8o12EVhvpGVX+3T@UU0| z&+)KW1JCua>;|6a<*^2?^zv8(U*YAk2ENkEV+~y8<*^2?_VQQ*&-d^|1J`)Cx#RP) zE-Wb4PP2>!-j*M^Vc7$Bq#W$(X*<^PUc2iHb^?fK>BpUw2dHZ}l& zuAORUp|EIb@yx=h1w#raX0dioYspWiw=R2o`RNRg7c~2}o$hvGA{Nh(XeB%6`1eW!j(dy2DLiNQ{OOHne)n17jh>vbx|m#3 zPVaIK(?#ax^3QmraLt8(9r7!0`GqjM{4?EDHUx9dJNW1sBRr`XvjIT)x7pcc?|v5K z7Z(?dpE-U?ZhqDjD$8wBV0Qil5rW3vj)IJIli2j=#`7M0SljJMf)%776c~MVTF7NN=SbqQ1jnVe|r!Kaw_fK74^zA|>S;^MiPgoICEjdhn*m${gt16ZEHh0AlQlQ-v9V{T zy?$QMtGPmet+|8Tma3YaIW^{t;SCIEn^r?40J>( z#+|P(-8cG$ekCnq_?#HHYaNJ0d3nWKHr_%Auw95VT)6zctZx-ss;MnsEUH_Q zTTxZI)ZyX9TjhnxX;RW+G>64>H)%0X`HVFy+_W98UL+;$3MdpQyR1uUE2>K?=c8r3 z`Sj@}b-YMuIye8Y%Uv6uUsR4yfuu5dX^R%;cx?f*;R)?k^!`M9_1|xAaKf9NcCV_V zu2fxFH#8%=vThNpVk)t&XByO-l;C#lMVA<1dr=)z3o!|!{|Frv>k+8%)k4)Yu{;8E zsn9c*+2S4cVkX>ug?P3QE)?8~Fs5`zMfvULMJHS>PyfH6mKnnwwWJd3`a^7x7i!6a z+f^-J)b+YBgL`chYPrnOK(Wq;T3+Sos>5udmY4r0YI!QDWg32P5c7#1El)$DC*f%M z2p=uoV?(KSsj#}9P9uaH(5||8vA#TvDlV&9w4ki&%8AP~X_Qc7#11Tw1Xt} zgkXVs$?VFyqSCqwHy+fJRPUn7a%s(ig@dxZC~{JCht3&JiefJg%MzBN*qid{6(T`5 z+AKFcXUt8d+SMkVXyv6lp_5Q~C%ei^C)%42Uni(t6?kEokAm<8kfTnH z0vl_V30)C9pFSfBHJl})2^F*KH!B`J(b_~Wd!2;Z^aR(Y+KRG@%K8dv-AD!2_1T7K zFH$Tos$Es<7DJ!kVsO-F*qhC4w^{5TV-ukWp#ah-%u($+3hRbm`=6=s!Z0cv_5FRjj>7afMAJ^hm+PK=-DD(s5~?u!aNXV4 zol-MD+}17?Ue{0es59RQ4ilqYRePu&X7P%%6T)rs+Bfi`54K#n7D}rf*-Wh zKvlOa`vqq*GJ8UGf;K}>LY*M94>X0UCSph-sK~m$G+c1IYQgO-wE%Z7%kh>(9{XfT zXsD_h7(N_~b9da0O2RD1{a0NEjTn?ZsGxXST29S^rL~oF=hdb4FB_1SK5Ep6b25gc zk4!7BSW>zuEq^|~1Y2BPF~5$k%W7&D)ZmbF58)L-kI8sM9f3swib;^DGRGm@g z%2CDmGv|(CfqPesVj+LmN6j%SD&~NBirKWHf-%>}5a?9%Z;%jw7g)Oam1!jCmSz5B z#m(k!-SATq9n3GUwxz7`QH0Ls=bXOItYG0cUt3$lBWlrSn~}mHGks62n$VlDycr+!;n1I- zpu*>+TUNy=bIH<-kvJZycBy5R`C))q*Y|pI+Vfk>=|d)R`ahG*tNQiNH<$G5KM~nn z*w3;G&87VY`Hci*b(bfrXMAf}%|K2!8!_F?`ioGr)ftvmXVzzoeco@xB9~h{xjaE9 zafuN^YWjERyr(KZPEOJFyFGbI{?=;lcTmUJ*Hh8qt~u4RMxlv2{>5)}{SM`DeTy6> zBZnz1a@g@(tHamPQDXma8r5N{Wl?WV{FmK7;@LZqVs09HVsm%`=cb)BH<=r(>v5pl zr^~Kq*ZEfbGnRFe6@L$Y?c>XSC@cLJC%8JKj`%CRvt^Z7ovycHZ?&vxR_rGBi|pc> z|Jpge$H}pQS>u8e+kjGzzo4OGt`$4WvP#)+Is1Lkiv7`dE2BH0e>JS5D3Hu z;sWu3UV$-zaer{V9rxpL640;93mQgpeg^UR0q_l;jmv)?TUdD>! zDNlTa@^ltL;M3a^;(WorxQ?d2<+ClQ?wx#~dN-iHubSWK8q_jsnrb=vc9iAPBTQB9 zk}Ljmx%6B~mAkaOb-Bq=)+253hpWe~QO2iT*>Lf@M;V`Vv_0adMwvd{-;4D1jyS+E zxtnzG{p9Lj9*}gE3FXxCh||?1OM)rGs!GF3vs( zH(nfsoABK@2$z;*!m-a#7-8?a)1|zu2^UVwCE>z_(^5#daN)GX5iVS~ynGB7PD>Ht z!iCe4Lb!0@v@{SdTsTer!i5W0m!E9Mjz6`acx{E#)GXXNxUl2XcYPDE$fh0n2;Zd9 z_px>a`Zh#F5Fai`uT4eu|kEqOZnvfm!DpJMH2F+HD9YRUv0!_m=i<-TDk@ z_kecsvDyL9eeg%lzz+0};k)r;wO@b^P#~OvE&s>iyYb_+UxKzM5Y8~-wHM&~8D-P2 z;yPBMX^TRfk4N}-L3fnG-^aB$$Bx4P4%(HMpnU;4&cP!mP$)5&8rbKL0c}6`r}PuF zM9^;h4q6w`Zu}1HEKN6l2d$4Meh2L=&~Et?wRF&K`4ichoj6jGIm1ZQ$o8`se2LBj zZ9g2O{3L3VK?_Icp3}K{!kIW&y3RwJ+C~rU(;7XrrTxM~``KBKuDlrSJx@4Ff_^TX ziT3X9q2si%9y(sT*h431i#&7(_R63uFHyVC6P~Ql9Thr7p*tybXNB&f&|MX}n?iS2 z=pG8)Q=v~$=w1qaD*NorEpMtqpQg}h3Vpgl_g3gW3f)(s&rs+y6}q27_gClv3VoJB z4^-&0H9Cu2IMX;sp$94SV1*u{(CG@Dq0mDWdYD2FSLhK6eXc@}ROnIKQBQeBYrpl- zNlN$_g&wQW=PC5}6ndOOXDW1-LT4*NL=ot!q znL=N#&@&Z!mO_^*^lXJL)4K8UoQ`6pz^=quoTeL;6uc}jmeX{TKz1Fba+=l%DVYCD zIUUbvzqXLmbOT0qA#UO{-LRx!KDe9HbOV)QSlR(j(+x=q=3}xAK#p!8QZSz#<222o zDOex;lhZT@rqKNB!v&m8cVK>JoOeKTBKhp<9i|IqXL*e zocklVj|Cp%kL3O+O?!vpjpj5Kk1TvF_ptzE^!My_f>~*w4{c7yF>X2{UcvcSa{d%e zqct4mXCe3J0!Q?f+%H5O5IvphLd37)@u%|mCa^N#L@R=O=Ob&b|2fjxR7O_mu1zZm5k;#F73FQa=<=p=%(kJ?$ zoR1nFzlg_2{j>P+nOzO|vnW3Ni4-6H6gmC^9)B8-k9K46;j?t%&!+hBe@5})Q~KmT zDa%15R*qsW2kp+}z-MycGdb{?9QaHQe2<)3F6Tln2YSQgz-MycGdb{?9QaHQe2<(( zT+VbZ2YSckz`ugZ1AjjES^I!y=g5opt>f`8;_;!cEIxeJuJD<@!B3?6fZtiJkHtKG z36BpwXYt{)_JChb>BApD@!^vl6Gy-5dHjoceDn_%AATvtgHPu_9{fs*4}TcNhd)}5ztkQp%uBg_mnE7OBs}*4B_I4ha{d>bPj=Ob zznl6W@IN6R_@9#x{yUuiG3Wn-^Q$pN5q>54z^^7B_y;)u3C@3t^WWzDzj6MjoWB$| zLL_Gc`H-`je3HZYPjLQIoc}iG|BdrM<@{{iu#lW$@*$^$e8^eB`CB-DE9c+G`Hyn` zlbnBy^Z&~Ef9L%87+e0S8b`7dz( zOPv2F&i@zZhd93zZcC`VXONHl3?Lu*$>aPI&Y!{gWY~=Gt2loR=l_87f5iDe;rw57 z{+~GiFPz^Y)|PV``AD}9`AByp=TGANDV#r-^Oth|HJpDt=kMqI`#Jwv&VQ5h-{JhP zI6o=QPPY^JNcU{=QLgWCem3V{$oX?Q|4Pokf%9+Y{O@!Aqn!UD=fA@FpK^W-76Vk? zc=C~MU-FUe2+kkP`9+*x&iV5=|3=Qglk7sY z9L$%DzKqkD_ZWRSr!jvq8XGLMwxRim(X%*>`GwJ?oW?xC=-Hee$>}mqkK%MWr!fvQ zdF;24Zxtzwh$LM*S#yE!VrJ0%Bo)5~y=qyg7JdDofG|I#198RM=jLzjW z%ERdKoJM&VoyTdEhtU%_jq)&hBBxOvM(1-HEtQAyQ4Z!K z|IA0enUDN3ANgc{9`}(iMk7DWM?RR3^qG%znUC~z)LSc#>>L$dQdv=#EN6EvOMO3JXQp|)oWNVg@V+al6!8R@o=bX!V>EhWR2 zl3`29u%%?!QZj5Q8Mc%RTS|s4CBv37)Rr>TmNL|qGSrqb)Rr>TmNL|qGSrqb)Rr>T zmNLwiGR&4T%$73DmNLwiGR&4T%$73jT(1G8)_3^16(srCN9{yN}7PM7xWXk9Fv!1Ysb&$oihR&d9G!xGVPLLTh_h-(TQ?Zfl21PA6^ z&>n}3%TDI|X%51^P;u9GZ?z%siC%mks|{Q-Hc;8V zP#d_HPLB?^t#5R=i~EJQOQ_cK`vdsCQ5*RS4dnYnZQuqC;`=~t;ATQe*?y0LTc+sC z?YMtJ)wFOb?iaxIL!VQfihBq5TlcCU&?;^N?!)#+fg6GQv&JZJ$AH@!1#SWE?{-Cj zOTl0o4ep^Rano_%m?U>po(HvFDsVsfU=;c5hWpH56u8Ht#8qMtdLRmUJ#hc}P8i%; zMX$aDZkB|@@Wq^pn}JCtHwxU2C~@xshg)ICwU+ML<1{VPL5UC1HBHT56>ud{;F_Yu z^+KZ2$g2Ym{~gy_IUWKC{~gyF?h}CU-*K(shGj*Et7`>!i=qb)0oTb%)xA)0^s&MW zH`uvSaecDc7P=EIE>zscC~^M)E}C?w$_xErFxeGJ^?QhMT2 zP4@!qA4P+^AGm1hB|a}Y+}tQ}PXf1EWM1-jDteWNeXmL>TwESdaQ6e3CITg2#k~+E z?!zc?Nf?BpNq2CRxT#U%YNEt#juLl&l(-k7#C;egE(!aXQPp27IA(uNYVWDQrAxH9 zRB@|-8z2HDU&RHZ#2p2$uOvrYs`5Sq?o1IV`6{j#_I3M9;o?%oJN*UDI)&0(X`}xfiOu)3ASyrEv?V;wAw%xCKhno<*XjWY2jiaCk(} z!o35WA#o1?mmFuWiNv}Rw^rJpfQyxIk6dWKw^#ul(qS%uUoyEQc6roalFi+pg$A32@!PC%vbBK`tC_0dScJBOJCImg1l7{u1f^mW59|0b&Y@vU~w;S-6G%$B^=cwxp3v! z4qPU}s9t*Dk6bw1YZ4AyEX;+&b-&n^cS;0YiG=GF0k>Vkohsq>Df;pna35iSq;e!l zIQkAn9(R6unXONR6Y~g_L&d!&;jksbTsYi&5>Cty;c%ZzIBcD?DldS=GwD0!Ppl`x z$?GoRuyw**I9z`TC+4MaxRDZ0%){Yu6D8d62^CaB45pYW++{g&HbrNor zgnLHOgY6OyO9keryee*=gu|5GD(+_zt{?*LmlAGr1l(&9Zb}5)dlGJH1l;Emt}p^F zFw@n)3nJjUOSqy4xc(AuS_Irk30E8eH&Mc23BX*qb}Nx^7}6cwn~EOH1CHWTf5Q;W z9MLLnfrP_Q*eY&`gu{^3DsGj8qh}-J!lk=T!d+^^!s50_IB{PcPTqD2hari%aJU^3 z4yw~CZl8q1WvjRcB;2eBxSvV5(g?W6B;4!>xL-=RG70xL=z%4zPmcg6<~0suo{2dH z|FtyE{4;QU!~&c1uw>Wb6ZRSl|{eZ}B3a_Q%uJ9J3KxkEBW zrKJsF9Qijb4S_>!&aAkV;|ucey|E)v*EVV{rD>#l~wSx~Hy!YTP|8Z;c@|Ui!k2^YkbN8c7mk=gv zo3**`(cq&g33;i(PrD}U{{_O_=Qa<(-$?SkrNgcdhgK#R61C@GN&>}R{!-K7;~{@x(>99Jbol8|)3%=V zbS>vm#7$#yZK)rINDj#e9Bu0UVW?+)Wr)hiIV?{kE2*Y;eN#_E>scQz)Y?4gXjA5g z)glEucXrOQ8k&}g`k=J({H!*R^X!J;C#a22y0KE(xyosHYFlnY^R}j?lzYm}+T(|= zJGA!D20!vt5^7BCQmSu88|-UL>QHL%t5asN{G$#G)Inkm<*{RpU8aA8{s~DLR4?7X zbgz3Rqb!wZRlD61(Qbo|2G=%a{v~us*S459Pe~OeO+?Lng_`MR*qq?K+LnFYwN(YF zB_ZD|?Zus!_O990pbuENC3tc0-hz<1C3vat(D=<~zi4glebk)3JJ5W~&S#niTANAI z@z7Z0#oFBYXcP3JE9xy&m8g9j+STw>Xxx^ZZR3jkC{6F9O%3A;11Ll9qxv09&pj5( z*}CtUrftDbdoR%L%!NN-!Fc?hwIFZXzE93t(7XP^JMXA_Ev5;puHR?FWu^}W~~P3KViPujKv znx6c}Ozj@%`d;XI5K>4Z5)uZ7wBH5~#wF}On3ynSH}R>}6Br`MdXjUU$@sx;ytVfy zCGghXpVSfcLmK}%`b!*Y$i6lUeKo`*4Pbf*dFZ?W(mBd0`c6*`QtdwE_8*i<(myw^ z6vIZz`RvSc%=;nl`%E_ajx8G{VAoU<;HFyW6}X=IMO8T2`yUM?G@=G3uG7ctLd`UO zl9-Ucj_PT@NhNFiBq?FiI_Tx;qzR44{SNe;d(dz8qTfJAwwSZ@JA5_f^d=qpml#9~ zVboy%sAWiFcPTvmz1e@A@?PvJ{f@LhW@(A}8*R#IBZ zLom~*P96}3C(x+uzS{`g=#GzxRU%(1>aG zchSFl@gD!7)63m)wP{<27UKa6#h4(E1A*hg4OB*q-BOR%_IRk@0cB7}zj6glPTS6XsYuq92VeL+g{(eHxNNMX}BU*hgT74fMErWbM5c5RO`s{(e zquC8pX4$znQPb2ylxNB@M&a#L&#YwV{XJ2}G&c4~c#Q9ar<7OK|IutYPuLpmt4`Fu z48_*$11`J2uI)oV*yrh2J?rDN{|RL`#IW3?9&H-fv;K^FN@@8^6B?Q@!c$)v->@5{ zqB$TBv^)#+tRIZ|hVp6}G)_^jKI5EjtYlyDk}(7?=Xh35iq*Wm31t)|^vcPJ<7Ll^ ztIBDJD~g%xw$Ka6@6HA`2V*Q2nz>HWNtz`Nq&8)at!A@}U%L~dJv5~xWR~vVZ`JJY zziQjP{kJ3S#G~e+CKle9)Oi+-_xgY)|AY|5$VJb}!dyn-E4Lg-wWjaaE}GtmSm+ht zjoVTZN-Aygo702TtJi79X`gkYa7TVH=x4Qp-gxwq5XFf>oH!mQNs2>AUs1wrUs0b@ zt!QMaUNpGWDC$>g7WFQTsj-SuO8rG~r7=Zjsb=_*gSaCH`gdouXWWq{|GvZ!KCvLK zo%=7S7Xi^rYx4J=P9cFKe_=cdF9@+-#<4LhW`I%SF)R8tl$81{tCfcO8qRRD0`XdtNz_N7d<|v;VaM2hAIEr}E_9rskYKbK2Aki*m-#oOUtpwk%^#E5Z3wil)fKffbE;~} zuAEl0xVEf9GtC-Ncy>SmmoTLJMFT&6sA!Exf*f+QFNHp<=4Bap?L*a(g9Ro2!4+?Hn(D@qAB=0DC^iW2{=$P}O(ql+V2}t|Hkp>u5}*X9XO4pi5|3 z`hA5z@nRRvtEsI+v$LmL99jIxbEDpvva`&Kbn?NY#IOgCJj(5#ZZHR4^1wyjD6r*0 zqG_X*F9^sKr=0}@9{d|%qf^X)`#ek-dKp}hivV>5L zc0zePVSvaR&xzH=$`X?0rmdfN|NiHvbv)k_%c`oGKNq?$H`P6*iEoYkQ_jm?pi>Sz zhNmD?UOF@N{FgT!^Tgl<8JfWgk|U(b1rerFyz!_YELImQPe^7DGI{ZZ@f3Py4K5SWhd0FMb9>jOxtlVj=C_all)#T`RyBus9m^(Pui}nzc)o6|exg3TVZC=0 zu*z!|&#tP_d_K8rp11jbo0^Y(@DEQ4c7a{|*YBE-yCbvSUI*#gJ4j_HHXbRrQzB($ ziv|}}R8^ENs+c)GD?48+&QB|zJZ)&kkR0qs4N03YG%aUv&cJ~%LsMQcw_<+Uh4U+y zq}69+{O9&*X3nfAt*WZIN^>quT;Xd6VvuLd6km_bL?@`IrSB#dX<`fr8|Z67yYShd zyrQafDQ3r45=Lv2^YRIIMvM~+%l$%#GeIt~!U@=?eQHfcRb-f^5a64)B zBGGlq^%Y`qV5B5xgkMMW$b!FoVR3&fTMHo!V>evl~D6p=d z=4%<+-c5hMPp>tNH7n~figSuIu}T1E1vrHgN56zICb}5Cq%I?;;C!s7T^@{p*JTtI zQ`8y_C`Efhk_R zr=mgZ&f!AZyAOQj(^tR(ZjF;CG52{h#Cj{ev|^n_nP$Tx9~s-L$y(^gbC^KdE3t1; zKTOo4GxpW7Jr7pHR9s#ELfi zlSV9`KD~1C;;K4lxbo?j%uyJH82(fi#7I#J7ug@ciVE=Qvq&YXuFRibUs_dJo>yD3 zP;&xd=B=)xdcm}uY3{gza1iwJD*VPTxr+I%sBbb=j_cA_VSPEf~_P$@3PzNXXG zbx;I%ZlDtT^*T1O)??%W-w zenGWo0-@pEvr5Mxd$lsAvh_E{X3t2xG|Z@q)x12aiVkHDj0sR;!BG}tyf1c?5O$m^ zTX0sl;5^@g^I8ke+buYM2gjenhT9Wi!&clBBUR?|@Ou*WtWoZ8i{nk)Zbik_^(wIh z=Do{-w0GC~F&kRT=&4u!{E5q)S>2~sxJ+l=g|!JfjRY!Ups9=N9G*3vwc^NcVWOsc zg_BTo#&|TRpysM+3o0tgT@9jQ>-q#|2hmj_FSfl^=~8=|cGX7cv`-JCCT=d>lK49_ z-8t)9(4E|qQ+LR8gIm)roy%G% zan;Tbc9|=8T0Jh?Wu1bMStW**VqU%T(h@YvP0L_R%=~c0PQzbh_!7-$wfAA*`LEi} z8AhPXM~MCUHSe42br`2d=tqFw=g0M>AQ~G>41dSVe5Uzv{6!b3^n{c&8iWz%sC@aA%?$;Wv%h!(0pCLo@wywydT4|Bovw5NMUf% z+PCG|1Nrt%LhZ$0=rDneM*TA^3g~ES-P~5ak#i=qwtuMlIq20C!e}DUTn3aCYXtgi1!~Ik zM_B^TCTuL4Vy>LLX){ab$BQN#zLX2ir5mS|m~|UB-O{k-7OSuMs};{d0iVz(TOGDc zGh(uyKVq&R%|p-?lZ}|fDbFJto9;5KMEK8>=T9_ZQmigUd?&+7o`FBJ4v`JtS%xp! zyk_Ig<~5TEVWc`0?kphX7R1=N$y~A#I&QASRsH0PE;bi$ z+_Y)atyaeuZniqSW}KC5C7E}v*odtD8F|yEuoC_}ZsQbIwxHTM~enct5+?wqTVo5sJkzD#W1^=OBNbdck>#<)L*;GtXXIcHD@oh ztQ}BKUndkW1|1>MFcV+JpJ8^budOwgE&TOw&BchE^eWoP-wCY-?F+742u(4sv^p-T z|FyZ|m0!QXgSuU1bu@fEYZ>!Rs3>&N-_1JJyqda155w$!%v|~kVW50Tq?yT9$E#|Q zp4H)V{g2qZSWzGUB1kovqkS)c(on!&8hnY?vFqT-%uXU2;$SSN9WMf0AB5 z9hYKR-6xzk*oxg~S%0^-}#C$hdo_Fzuj zt%i3Eegb+^`zFDbIaGi4xkJLHd{UIQ#OXaZVN1L(u0?#^=$X)23-|*ufj}TO5EqCK z^a_j#j0@xhCJX~kIC@h`w())=Y|<~^U}kk%Y6Lqihmm?%reEZs< zQp3g9BgChA6fPGR6n|P=cKrCby!gDh3Gw;(n*jcQTHks{-3%mm>lA-V;EceA%y?{e z4}xvyu{~@n+W1ghkYw4!H;6vK2#ks!9Y4k*3^6TB%TGgAxTubL3d~1K;#d^ovS{(# zc)DYn+a!zij>UAJ$9}z?xi%!iB)e*m-Na`t-OT`HiwShZTORRW*RXt;l)g#vvgPtt zt#ms@@wZD+{%y1C;p)b11y=9hP}b#Ya+D z02zL_yD56UW7VA*d3SBTGb8VoYu(*%TX&D~T6YgfB!-n(+t_=YF!mn*-7xk}bGLB4 zaKUzFustLk&CSAv3#YkNxNzY#cM2CSoaR2^!iCe^CS161nwx|R7fy4JaN)vfZV@hA zxSYQ;0krFfz9yK2KfYt{c`KKs(X3=6>CJNqX}^fzyfRH+^4K_fPqzimeea8e_IAM3 zJ|3|2=zFk(qSv}SD9@{8()&pC8JwL9vWn=5;(c4i%>li`AOW2x>yX4gL9)fs^J*{3 z`|y;|^c|UvrYDqMbl690Zf@xzl{bRt>B=`?5uJ7zT_1K$o-fSxLaSK)fPL@&biT8UnU>)%TBwYdI+M6bj3pCo!SuKz62+i-mjuS81! z`=EzQ^d8V;JCPiP?}tA}q8|jkS)zXq`euoK4D@Xh{WRzwOEkT$^RPs}0{SV5J_h<} ziT)kv9{3|?z=kW8#jXDs?QfvPy$gkZ4th5J$dOI=5PYgLazxWtyA3wU=nkN7m*~!* zcS`grpv9O=@q2@QN(vtU`j-+t1oVp%eJ<$tCHi}yKa=S3py^X%awNY1*U2^sI+ocy zw_g~b@K|PVl!g>?M3(}e$tas98zQcL#j+PoJ2~NTT0O$)rB!ldGyWRTZg{-52DIBB z;GC7KWJLpuKWb_WuX%f8`G>y~b2>(OS{7rX8{{%GkNpcka2=9R+mA5q@Ml1uCxyQVI$NS&1MQYCL3QBhK-=M=W3`7pbe#6GhmO}i_0X^x zj2S{W6E=pubdo|RD|APNPEqJi3f)-C6 zjm_C+zNW1qdJ=3clYc&^3%Ea-^QUkci#~=g^3CMHr?mu?qk{XdqMnKVko%u- z|DW(3c~^0Hv$#BzpUHzy>qe@NE4bf<;)BM4P0UY|Nbl_J}I`9{8KZ)`Qn)2^x?C5g3sy+{xC`p{%H74{N+48ZakPCK@VAc_)LG`UrFVFPiq_U>E@Dry1#Se zT*Kwe;c}qIOb&e3-tftemI~*;j?;% z&*~XImCuBqDaT)B-^ZErxNY>6n)V9Bo8Ytl3I6*;gWrwv2|lgm2~YP&#Qz=Vf6DpH zb~^Yh-@p&2bb+V0-U)vewHNqf$p=4^eDD`={&k$cmh*4p{2=Gw$N7(O{!z|vx`;{5HLe=q0%kn>;Q{C7D2_niL)=QEq|NH;0QPIn0T z$WJ!;;OB8Zvjq=+HRm&1@W>~#1rI*61rI#41rPq&8sb-K+7R+5a{3BRV;pATS8^KT zD5EhLF+9dOMptvXfYb9ijq!$s*Kiu+0;3mj8vUEm3ptH`$>>^6qkp0JnmNtBKc)OJ zx|q|*AEPhiH1fyj>6}LX7>x~)WRg?B=@L#Oe=PiBP9uMezJ$}rAER+VGmDS>F?t54 zrTj5I^2L1Qhxy0{^N~LDkuLL*9`lh7^C6%4kc)2LnuD$F>|tdKrVUwE6?W5+nb6kg zmm95S*S4`~+t##gYWlzSx9y5i?Qc`f4YRFy53{X!54Wv&54Wv&54WpzxNXIIIImb+ z%5b}Chud{K+?F!jmNLSYGQyTJ!j>|^mNLSYGJ>~{EoFpb3mislak$x>#q-OA>0tZh zGtXu-H@a(wNSn)H`0i%16391?6>hlAVg=%E4toNe&0v-5-TYNUTWt2K0B3Xe1RC?U zE7txvFwE=uE~`cEd63j59*)}@t_*MeIB?!RF3$e8#|aPDQp)Gw4%TflVVnEEYG#|J zwp$vytE$;|$+&j75x_N|-EtHNALiD6GSkPiWo8Us;ISLNT1$G}o7;*wPo?nY}X+IlF z5621IYz3Esdx$%*z86m5a9ixj-vO+Fv7~dHz}>0fdLjd7LZ)y6_mG0iM5Wv$Ks=1d zXZW=!$6?^kq5$rMy!SxUwZMG_+&Tf`VMN9PB;!`ZhA#&_Um=`u9{~4LYD~oqR&cvJ z^8J!FaP!dMY(Jz8+?*~rqfV+n0aw$V)m_urK865rU&XEJ$@d}Jz^#GuvHgZNaJQ#v z8rv6W1NU*C@HV8?{GD?qzrSxoUS)qxWB2K8;BJGmu={ZZH%4ieYkL&s_-r`pFA5yi zr`nE|#cff4uL9Q`1@6v~nzlCzT=pn?-&2K7P}+CPXp}<&Ve5c76?X)?naM8#+5~aLkObpS;TL4@p@-JL#<#-@U+(*FSR@ZT@$;-q;(M$*B)?cyG9;<-E zt#}Kk;+_Srs0B*XRNSfG!@gq_xaCpe-TB=`EZpPshR=Q*{fc;xd2> zm%p3P9;W@MfyuZOxNzm&1)L$JvIRIg&3hBPTREThC+`IgOIOEj!Tu$d#%#<&I?NIM zO9i(bIEs($OlJ-x+`9^HpCr#hI61=6r@V5y4*=I6e3B>D=!B!gGiBUsz-4kAg_9$n zp83eQ?wE{-Px4S~=7_!=ILOB?w(Zh@lj9MWa5aj&vn6?0A~P2bH%!8v5&<_>!u5)P z%aw4aM!*$FI4sSX3zxrQ33plq+zbhq76Df-;ZBc$tCDcNBjD;JTptOyQfZInz~PpL zwQphs+*aTwa$Hgb+%e$rpUF#(fIAxsCFFICfU5&;9+#IA0e1|zOpfam0oMzQoK+mx zIRfr3;4(Q5w}#A-9;o$q3^-Aat`Ts3u{fB8aAZ^K76G>gxJ-_tb|FXUZdTf@3Amqu zNAfxl2##<&6x?$DJce**5C|?D?j{L`TSMl;;qH=f{UYEFNVxtHaF0m10TFPAC7hTy z!{zUogc}$^-Ukv6x1`L4llP^B6Z300Tmqgmk-k$si}{OiKT_JGmxRMopSf_jvn3ps z=B?t!N;oW~Tg4SfI4qG{#m$g#nGtYR5-uwOZn=cZj)1#K!sSH3-6i3$RA4S#{T+~S zG-Z<`T$9osj{rw}YPUT6kqd`wl5i7jSXkU)2{$nU?qvy=9|3nv!cB^Rdso7V`@L}G z_&~xHM3DE1gqs`z_oalJ5&`EcaqAgN59TO;uc1A#o^jR@3BZYU0f#Z~&%n_-DvdMG z1a6v-6Wqg+N&CBkTRKD2z64Kpgj>8|fom`}t!&UH5{g3!+M#CR@ZC*`P z`LxPqFm-2S=pvtTGj03zfcvKP9!Y?5dm}zP97~Pd&+5TL8cr4*9xS zT3!yLV~NHjT^uB5R8`Ke$f;ROmb#2SMxt@PE)F6zW-qOCgK(lsfg41zrp}qOsDeeq zp(~S}Fi-h^IqE#khg5c70F%uc*`%O z+U2LU9k1?r&v$sK_qZ_+d6M&`2`RGV=ISFIf4MpPQ?Fzpz?Qtsm7Ke~U&h70%{x7k zt!oIN8yD$j+2YzPUb!W1<${|nS0d{7VyB`EgciuPk1D>z3Dwy5UA$bk?)}R>+q?L$ z@T4xPk&g`g9DCEaR2P|*jbr7_`*c!euh{22B7A8=vRpOq-+kqttiQegfVXOd0K01X zP|5L!U)gM))4$>)n$2@yfi}$Mxj>H*yjIQTxp>DM85zUV^j6L0xiQ){o9ANNGMncj zoqV)qHqVU$qXZGm=D9dWG>hP|HYbeRrJ;eG2r;tRJhM%+d2T${Y@W|Gn+b&O z-MjzZdyXeHUz!+5WZg=9Z0y--ub&t6>Xr~->y|XDRn#7i^BdQ_>4giyE&BiJYcJgN zuiJVYQZgc>$QhabSTN_K5lMgdN)`fa$#fUWm0Y$A=u}Lg4a93+T5c%gR5#Q>ne(uOkOm%D9gV2r2^}EH@#(O zJ1LW0-~DxVK5*TVY#5DnPNUcL8Kt$gFt{iNR$afms$%}!x_OS>2OY*BYV4(?7}tGz z1()NVd_UWkBZh6CUdZK$!QH1{z{R+n%PXB^EPHFT@I>n$?eMmjrhj|g*qp}o4|f2# z-7TspEq88cP+@nyJ*f zeyBCo;mCH?oL9do&A~9GSp2kNSt0*B4yDy+WDFWHD1A^t@wBv@ngvU1E9cIuOY2`Y zAT52=s1fI63`rlER$Q^9bWvLV{6%%Oi>oW<*U@!ZP3?l3+ETK&r<-CN!dEv~rsw77 zO}z*qwbiAySF(Dx$Dy~xjTenW;h^oRO`m;J+Qi496(@Qe>WHd53CE#p`8Z@NM2>y? z#Gf*d@=&pLeW|N6UP!y@%(iek6K+w?hZphi0@i)Y9FxCd)3X(3Gz)kxUOX|e?Dxp% ztv#Pc?`(xRXPlTnV1POs@UQ+S0p*9e-iPK4^8EZN<*DI=*7Xj`QOX z2VK8K&Z5@!Tg&1w9Oqta#rB7VmpEkWE;(CY4f)ox^@^5kS*We?3&-VNg}>_EcC~$1 zS~jFBEqfnpSqoK2kAr>e#1hiZQ@*t-yc;L=$1e06ffji>F$TE8b%;Zhr)9QLgYQZ` zy(QJt?Q+{4AN#Gf-9NP?%X-F&EnK%{-Hq25*ya`9WSM&zzhQ>GcAO68A;tEx?j$J* zI*aEF`K}Spq^Gf8INDzcccy)(DC5%(a=7@BY$o&)iNmLzGdlA>r_+iX^x{q{pU(Pb z%Ml-CIcTjJt{ibu#-|&faPj}s^gBkGKCO2|`g%v4!|$;LKu_$&LHb76!}v|xB7k$e ze-y{S|Jz5i<7{))c)&My?E8t4ZLQ0U-wF$E+BcbR=Lq?4{xJNncbfdy)s=Ra9<{be z2jAmmSfc~_K}P(@?zWwa{4~7!YO`F1FG(9}pM&4YJv1M2{oX_KV;qu!1MZ>uvG$?) zandRIh#qgBlAj<>$?x#pI3=G(d*Nsl#!VEQ{m7fHXfzitTsV!^!i5WOOFoUV!i9@( z@739eaN%vmr%_P2zPPZ*+OYYGaOpljSDY2+#U+$*G1DNg%I7^4R#jY zN8&tBo!Z>WTC}L5dUjPstrqAO7n5Mn^X#&WkxNQvS86)#n)&pWrx2h?94F4CXD_#a zYv7Dk(nj&k5YatA+dFU+Zfd82w(n_e`V7!QL+H%{|ynJchlA?S==~_uX!IK%0a30Y_e}R*h>nzp?DDhX>=G zQ{6d#op>h7-yi}RZE6pAXrK11hqko;_0Y(fRN*Ghd_UDg2iVyMB8rJK(l7Re$18M# zLU&N;M1@XL=wyZNsL&}2-HDyA>gKPrLU&Qb<#Zei$1As< za7!D{Xd<@Xc$A?EW z4w@tEGZjos#p84^FyJ!&NY2NAO=BRXvyl6j14lGFs}}w;}Riw~cr51*wEpQR7qlm0j!|7;!~?akuD zXYt{)`0#1%Wx~HsPCtvEF?lD-P3;MO9r@rdAs>9&vLybGIR7V{|2*gamh<1` z{I57aNw?+DdFUkPZ1S@-?R(@yem42wUrK%!%0WK(G=`htuO~lC)9xZ4{2kz=X`dyH}aE=ML)@>bLC0?a`M4vXBvaw!1<4I{)^;; z{|e{-ne)HoeERs1CLjEjoPRs#@8|scIsaMC zf0Ogy;rxGaek=wUlGA~Fz=ltWGpNxejrQ4Z&;QNse`J*`hJkGzE^RMLm8qU9&^LKOpUe14-^MAwn zZ*o4JUq|u-v39x%Z(4 zqx*1LN}utOF7uHd^N|koA)on>%Y4XVKIG`gcPoz0a2|Qlva8BwSF=Ni?K6Sf^}J?w zgf2fmxaD2EeZVg9!`-#3q0(Kt8|1kwciG|Y!o!F1yKXly++DUB>U}1C;*JBRstQ-M z)~b;B;r0QD@7+*QCG%<_wx^0+iQd;fh;KKd)J)=tUv|JPA-rk2wR$o%|F?fk?@4jw zEsbCFN8=ee4AmYd#y3otEpRlJ3x{PHa~Lu`xLKgjWFhvCkcXwY2e%gVkTAFs1@|-1 z;nJ;9aPNY~^x!y=?nZFr^8OPvrWwZx+`Zt)xI_@)xjdY*gakwxQdSaUak$?k1=Pnd$u-kLr{6_ z-lz>+73OSq57q|mXPCRAk@pGK7VMr%krx6j*K<7-_jCnAq>8%@xZP3UMyJ6}WfZs< zf!h%UZXq%kO}d?-d|RWCw=YWESgdiPk#_{R??;htbze<;Ck!qgje-A;D?CHfG9Ai& z_M+mpM2R~B+{7s4b;n>8O}Zsf;+hy3#a1N0!QDC zt4_r|1RRRe!l}5ofkPK*;Z&R-dkxW~I}AAdZ{bvVrBTY;+zPG`^=C@wk{$$ZXp2;B zTWE&F{|LApmZs6V3r7+%NB87plg%%kueAljVtKgm0=QTSoXo!qIO1pH54ZWug~RQU zaAG|c4oByu3whWUXjR@r5)Mm`R&kF=IBX-diffW^SfaFwJ1pT&iGX`q!eJ@n$lI*c z-!b4Q|5ShRHjI^D#eD)?CdVa2zzxHVfWUQ#fUA>mi4kxQNjNM)nWOe;kv|DX`a~`q zZW#8EG7(1Q#Zr~IaJV`NXMgA$Ufx3zu9GD12TDDE0^B_8`IJQM*AEnWOTm`RgU&pc1X(&X#Z^ zBH+eKxN{@m3MAY}3HP#6e=~rid{a3_MZlFyI8+gH6i<~`CE;+{Dy~k#jg5d?F5ze| zfLyqA*GRbU*|4ypt2hx)^Gwvw~7yMXH{2+98^aF{Q(G|qb%xLQL3 z;1Uqc08hsCN9Gg4;1(~M9rj$vp+nNr@E=b8#kr9g8KW{r62I+pA-mJVO*nBbWQ^%I zgX{HUO-}_69}hK+^=mez7t(cO>YfI@sByi&bQVYWYUs)iO$o*5!S&i5giOLScf=e+ zq2J#Uyq>6+6B|?Y0q>r1NvP4k|CxKAC0=l~wlTq{kJ;K3_h$1`!Rz;?2KS|eOdTgR zW(KO7A-Q?%UVpHsrteMFHWv7{`h%GXRfOq;v~;6s`{CPJxUn~NuOAXuH>MuES4-E& zXhu_TZ))6IPd)WYN$~pM+Dk&ePdoq&rHoYe?;kxb)bz~ZXNhh~-G6UzG+mX1-kTNN z|A$$Wt6Q6bJ6K-UQ(o*+%6Ylf&I>Te%WBsfo|nN>Qq+jz4|gRkAO zufMiRZgpEP{uT1o(3MZo2|M&3JT$;UJBF@BE6-v&(U_X+w@N#PR)b^K;P_}gxUUiC zjFPUs&2+6LqS3EU-=n3m_&q~9Vm9?m#_Ew@cmELQdJ4Wz;{OZ$gAeARzB4xt@o5`1 zU!#9t;$5j*58w4=H{)E zdy&UraO*Y6vk+DgQ@z*UF?2n0^4J~z8gab}Qb=ZFYMwv0IXF3{YOkN-HpW~RODOw# zZ7lT(l$Z5~Tz_73{H)+UyN>pveVd-%_dN9;Dl_M=CO&io?MWP}JH%hN7kbe6LeqKn zS*Ll;xyW~1X)tJ&?)96cx?$89Mq{c`qa6wcJA>y(I{Rai(L?`y!oal-ayB`nj zd&Ve?2S1s59_M}quHC}6)>=HL7I2L*PEPnJaqz(d=ywxW7dB1VUC=yfZE(jssH4V) z9l>CMuWEn)Rhn6|zyD)6TlU_8)Xy4s2RH5Su9^2@K^hDum8OL>eScDbd}Du7+^pc} zA%*^$;OMkM6TiuY!A;aIL#l)O??G#%gmTc+cQjC)B!@bn_h}n_`d-jLWv_z1@9jW( zzBgg(GH|l?`ZEiOhwI#!>R`@Ze;T8GXqo(X)gjTNCZkA`fTXCJK#P-TaifC9PDnx_(EGn!Tvw zglbRwW+q|eOJ>?Ztxmle`j_bg*Y4p5A4Hx~^)Y$73vQUyJaKg*Mh1+xoAx80x^W=M zUrK%W9<6z$zsA0zn%qHUMu`tTc<|nXy8_398>Tmx_=~SAS{t04TpheuA5eBECzPEU zT&o+oPvkv0F*W#LWwSQGCP!qI1`_sSnG}-y3Vd) zoKBn?Tt8_ydb%GueR|(2%H@7Hmkk!rC1#^_)MAG=G-6(%eEN^$#ND6-uq_;Y60l@-ShuAI=ErhaOMOzBl*D;Ql<8yS2w3OSN-H^JA_*3!_FF zUcSg}qR~;?Xz2QYt(ZHtjedQrG<(|UoKQOO!S#7f80E~ZPteGYF{mjxIo8vXs|o|W z=h|(U$;Rj0^?Oq>O72UUMI#wPpcTQalxlmHLS60K%Uiuujku!r_oGjTLige?j_PZ` zgb>YYjj5Qq(woKxgKYF&eMu;|z^U(V7D(vRHcOG117_N>vEYSyf($E*?5r#EU(W%{eNLnNgc zW!~FFJj|i`wsnpE<|JcYa}$la%})sFXvNazr>=c#&9+7+9kQXf!F_y2T5Z;3Vn*V+ zni*3?V=&31zC*L2w^nJqpq`M%Yt33Tr6t?fes%2kj;BEPvtga zY?yp1V(ew(G@mKDpBti85sfo@{Q)tGW$*Q`64z{W>jJqHkH#D}!*st|is!SjnIabH zwVliK5Y|oSBpG9-Ul^j==o}gk9nc488w)XGHb4K|3p6L^gvLx4tG2DFV&*j2%!!<1 z9y@*3-gUG}60=tGQ<=1KL#}1sDw~(xN8s4p|1VYt-Z^g^Rx)pdo%dG$ZC}qH^SO^^ zCK}Uv(7chhHz^*YnLIcBAhfCw<1gd!k?Zgap-k3h&RBNXPG89C!ezyJWTh2CS0y>g zg)yLoj9GSHYNm6?_xd|vo$$c)#=wuDkpk1$kXcA=Pko5b;m*uC38k3WY_B{p!(pDL zUhmV<=Gj|UhM#S`^H-xkh`Cg|xg_L6KhAV!H1sJpN7`wwx??bMU`y9XdS+|Vy>nT3 z>CiMsI@N8avjPh4$Zej0+8bZmJo$8tBzt4DhiUZk>CI1WOKeJQ^xHkcUI_&!m{rX^ zeOPruQ*wOO%{>EHD>P%37tHHheL6;$y)lickJaOLYNIAea5VjTTY|1JUCZ`LFd7&v;jXeUA{@T4ktjuT+1KT(BD<64`VZgp`vmzdO?7+-6jy!gO(H(j0;#-_m z+Mn`D+0%ThRy9=h-8$v-G!Sl#wvRk^vHbjEOB+n`@Q2^xN1hw?#+039X&_vrlaK$$ z-gm%fQKbLR?wbt>2`vFDVnjq#N*Ya2fgnX`Ld0??CL};KB$$GrDA*f{1v_>GRP0@` zdwSksxzqF1L+|vk<9T}46XpMXW}e-hop;~OdYa^Z`MV#;^L}T(^UTb%&&c-4sBUfHWR3g>N<+}&<+ zdu2bJm#SOB-(H#STygO}d+*bgd*3i?RiJn_r5XZ5YB)R^~%Q^T&SDMI=(&RqmowxiTrcY#6HSiHTa~ceU$AISF4~Kew>rL z4M-p-XXL%5#R!RxxeC%q zgHCrhb;DyszfrYw6)QR(3AzQ*cWCys%d^+i4$VH>b9K2rvb1elJGuCVYkTYIqozFf z&$aXO^fD!y+M(Icz~6Bh54+rw>pL|2R9OU{-{0rETV4eV;gx+BZ}d*j+_=~m-Jd;p z_2#`+1WoDcQKlS*J6%j~whf(er*0NXg#lwTZG$kY)i!h%xHHM-Yp%-CjZS4gGGV(m zX~skXc0736s43$Pn^JpRW!>Z&s;jK5WgXEe7}HEnr0iVPN$#!GSXERwO5Z{kd$oCC zZWraqW-ISlx2O+Lw$0^jt=E+B`Iw*&%$_ZsfNE=5qXJHVsAlzoi9f{)99hi5mhK7Y zVQ?Gt0(#F0?R|3T*lCsZ^;NYsQ!9^ctgLU4My5Jj)(#y*3C-#eeLIHt3)tel9J|8R zH3;vzYRyRMDbRZ`%e^K$9c6{y_br;%{mklh^l(;n^yQbRo%h>E^W}UGe+8KXiGaHt$}QVj!3WS zsqSe1nlkKv7P!n&oh|DtJCx9@9act)%NsstwwSzbOm*2D-Dkosdh&*vBD((R&_E8` z;Iy>!&(0TSYoX5SEk&UU!mi4fu`;HsmtgiE>`WBGaH+g;8PjDSMUNT%~N2-;e zPd>EhB#Yh|X@jn_uje|WtLl?F9;&ouy}%uh$!J#hc{jyS>8JEOVeX^eNon!R7QMRC z2HnTMY_W5=T??u!x7EaKox2``(5%k0rkVO4eo?8V`<^y>GnXF*j;pP2nATW7A0G}Q zuaT<(EbH&MVCgZ<>Mx(9nwEt;3{{3SaF-o=1asJ&|u6G;I9S7kne%>7w_ih>wOFXV0E^o(8t(;R;kI!Lxw|4pa zeUn?-x!ULuc4~-oNxxDTq34tQs(CL&A7_PkDb4FrYMIlPU$0ib$e0H2dehSYx>`*+ zu5L_OV|9aiEFk?#t$4bqLpY;Z`>U%vggaMSD=mI%qoWmG{G^|MzI~=Sz-^`jxRhq~ zfCr;J;EP{-fM28s_$tr?BsKo$wR6vr&3e{fjXvvN{(9Dbk+c3y;H zyBpiA=lx&N=e?k%hmf@MR2!V1&t2v&b%&wXvdwQy`WmRdXog>Ra-Z|wyvz9vO-viPyEipSPcIuy*NRGhvr`m|9z^J zv1&kgUQ2fnz2IPNu!Fe3?;yrCmXEBcsGG)jI;p~z^{jjEN{emQF5W zE$we@v;(9s$+9Q8_E$IX{oA;zC%h{WL2Fjed#Q=Fl5V;6-Y?YiQZAzOH26K8^hjfc z9BoJJsP1lkOS>O!=+OqdyT_B=Z**BhS!wN@Io0aHG*#TPhNT(ar?HyV`OZ!YzcH7( z+rta3TH)NcT2u9gVLqAaiabSE?7j%g%g%$Y%1<-2a=2FwCm;3{qNJt$m$txegZ@ij z?+o$Gk+Y7GW~N$O)^+VuP@2_qA8G#+JvZXjs-zCmp=W#e2y3E+r<^w;(>CZvb74or zN3@$2RB6jfq=z$_)rsCnw~n{8tvlRq1l^gOb$E`UMaY@Q#Il7`$`)1EmR0DNC1)~+A0ihPBpHOZfDH&Q_s9+xAf4V zjk;o0&=rHz{AJm02gjX0ot|c&IJtc$HtX*Jcs+-&)FZnwdBH=i^rG0{S9BhL=aRmFs_%V~m zR5#YomByvITGp|&u!_F=t0J1!1Md5&i>lmhI z^-wvhnO1eY9~i!xG}ZV^&N8$N{Rx5eRF$6}C?_g1J3mZLYNQIUV2*mJE*<@5i_RSA z<4|p|!^~7ubm|w?)ZBegNcFX>SsC1E`jO4**XL$f^HWUBYiM%nb$jkO5*=qXMNkE3 zFp13pJy${8(QaJ8j}b9fMi|=>Os7C&b|L4)Uben#9`0&(bM>QCM~ng)-W)dhFglHG zV0Fg`+btxFZXc(s@0vZ@(w%!7-4)>py>p*hi90-WsQnODy6)zk8cAr@rts1)-^B+S zL3n2_eKf?~Q+MXF`!_rtEntZ1w%x7ON`Cr^CEZ`BE2hjcP+B4Bj>vvuJko8 z!ahw!7+rbTZO>F)`E*aU+n4*BAC-D>GFv}liY$)I)$RHHj$8H)^hDnX>X{rwlaqAX zc)t}kDWPq3+F(QAO-fupa+?9w*0T21cZ1X^&DxnCl;V~E8pGny#_&^mXWnqU#UFmQ z(bcv5@YC&|v==|s^4i7v{*eZ&S)J(WpSog%oyaYta62jv=bE|wucOx6HnjA3GP`Z| zLdU_5m^``0pHepKn97Ed+D7b5%4;#H;+D09wxUkKYF2l;FvY&aDf=Wu$OTBU65cH9 zr}R|JRSH~hbZFZsAr`c>-_cyF4PN~g1^v!nEaNYIqncaRHMIE1bv%>Ste*GCPhNeL zV$tPKxjh;-V54VnLeOgI7M+0fL#A!e^Da*IylIuZOA}SuvUbmMKYL}kp5!&F&mH;S z-jXk^E32t5T{K_64Jz;O7&nTfFS^aiywv(i++L5n!qSCPj%k=$vB>LA9hwjbK`RJb z)F*dErftwCpGx-0DUIs8090ek`cwN9E=jaz^~m;FKlKieoFEUOu3ETXvcol5E|f5C z?Z}%lhJ&VB^+S9A29>&d{s!;;%k(s3@_aST!VUT%o(p^Tb$XHqi@&wB3)5H8+Mo-+ zo9x2wl$L6Ytw=IcxNx)I<2mT3F2+@gl6@xB|p`_+?n{#SuT=#KGfnbJ#GgVZ-c!Wzx3!{uSQQC>2AV6ZJH`=Sr;1a z<}#Yq-`4)G_#1WYLab`(-fb8%ZG--{CaHJxS8b4;soIv6XLy{?X;z;*=)d(jRX%Ob zAqRnzDvygF5q6s>)lgDixLLJ3S9kU%^R@iT;5#AHHt46x{bI@7vYMJoHQb|0Th@KF zCxzB?x{PM^(TzX#DV=*Ac1!0DQN!OklUH1q>iQPn2bx$`e~jnj4y`&7;@7W$=KUhu zB=J{3M^`Q|Ha^LwM=x%0vwGIHDW0|PMtF43zD4i$?F;v6gFVY)bp^yJb-NDpt$(Vx zW&MNR`cJ`XRzKLaIiGyU{>81hb_ZHs>eN)h?RDh){?0zs%ZR#`cD~-ov<*66W0><* zSNo6MsNR;9>m>P}OKMivJJ9)wH!<9c+s~O~hPfWCXBA>@OMBfe$g~Z5-7(=_Cv8ks zwyZzWbKYQQS6$t_k2bb6XE!HD=rOywJZXpemi9GT*xCktjh1KxeTkk$xw}G8rLp-S z?FylJo6Bg{zHQlm@f@OjeEoznY?v(9B#YH#u7I#U{2vTnc z5q8T%K2b~6aR!UyjuUxyY78FLW}|Plw0j@eHr@O0DcswA$V=6>tTmzT-Rw_zOEP}y zsF7Fk2mQ%guJ5knmka0JQ2ruChpot%V05X>bq2T*u=YfWVE!)kf*jmm&ppaj5{u(%39Xlj(dL8 z@SjdavyX}%P2oCWvqwkW*r&%@X@b`DSe7NWb|8Tr+36r*Sr_1MnxG3~J47rB5}LIk zAWN)hgN^amO1#yhgX3(QZd-verMGICo}w~sqsnw8imB`b1Afz|)$DX-_iY@f*0BaU z&R8dN^qc9n^FL&<)uCt6Zq>7RYgQfwwh;Mla4a&-H>jl z!=bL$3-$eutyZXWoE*nFY|*Js=3|Q-=NKpR#`l!RKdTo|v|a(vN`uvoa<)$_DRG=V zNcM3u5AByYq0iiklbjBJaxxPO`#2r)9p_#r)6U#BaRTZw+sV8paRO>WrVgI}*6Ufm za!`}m!<2ci*UkH5k5)VX4<|Y~PJ@$q_D7C0-pL%WT#0l$Ey;4N*K%GU%l+nfbvlEV z+oshlcP3eGhLc(KZ^s$xWbR(8gtDA})oOY~x$xg+hh6ypS4y`uv~>R~Zg$UhVQxkv;nurwY~8kllR3k2UQV|&(3kn%PsM7z z4)=K~R=MNw#p!?L3|_ROe+K_o%5>ZRV40r(A1u>*TA2cF{-4&nWPh|nuH&3>#6e5c zMf-onr9P#3!S-riaE*68#Qf>I*1H})w|!T~xzEX*vXA3zax%v_9S*q897WI-yY)`y z`8%M`+FzZ?OFXMlKiaj`MiFNP*2d6_~_m>^V z&hF~8uXHkpzL}`Dv#oSH8^v4^C}!&oU$5&1`yJ(E?pBphZDe{s5;h>$wF zo%Np6qojMPEEHHu+trZ zGq`K3mFe?sP^Md)%zj~{IMI52*n6E}Ph2v`*&RA18iwL;y4?lm`zpPB-?iR#^J)vm`)tWD zC-aO49Ow3Fxc5WuxJoacXuS?)Z5NpDeJ69Wo!vQ6w;%mIvG*SIUtLjyO}X_3NRM?# zId50(B6u^e_1eW2x|uudB{jDUTp_+_Jwq+sc}K^2$gy6)EnQ`I{nSFW|xBQJF__k1|f?gyvC15V~yjwBIoioeoHWXl4yIky)7&2@{?4sd{H0w{ z{L>s~vy*vSLE?l19j9?aZLO1ao0D09lAqAmlg@Ny_~107^)4}w9VTOjmTr^% z0xjy>*7MwtbGkWBnUgt{TU4MAYQ<~vMKG9CifL?O;VWup@o>NiTkrYH^*Jcnola(> zo!!OhFw@DrQ~td}{vDi{G0+V^OT{Wjyf#q!-mTVz?x#B!b$0f4iN?dw3Cy_(quZ}l z5&i3Q>ppB)rajJI8!%f=tC?*R-6lxnlsK7#oDM~Jys7-KH z=wn=JoEj%{@6T25^G(1Jk8CwZJg+0lWvA!iYBKD3%>UAN#IL$zoDPd<9+>NN#6!+M zs5=(8$FVIjIyspy+3C57m2^AeCnZs*=gPTDNoF7+R**T{(1V7VNa#T$9$i_l@qRGM%sdsmaBCq8FOjRvc-#ciPU{A-k){ zNY7}Ok&%&^(LN(9qkG1%jQui7GRAfV&pl{)eC|nCijk0d`t+FTX3?qicFg=~MPgX~Ki7WkW9HvJMgDulOut8p^a(rl`ByuCAR&&i_@BE3=RfzPv#sg5 zOP(JQ^n;9;<;WmCA%4_7W_l`9So*A(>1luOu=G2}Oi$le3rqiV{m_cYUq26SJJ`Sd zsH{==KN{uH+vCq|Pd_*P&$UCB2s`NgQI{0wp|#8ZbL-#Q>8+UkL1(hR>JQGeCgm=9 z4i^U94}Wew;+BK*^vY45T#jxr{fTy84{O&^*9Y1)&pl*0(65bZzke3JB&pk?AZ8f~ zkS?qYIWg1cq(~oSODd;((8FlYmZNe{JlnRf$vx@$kz`f9K0nu{KR10^OnanJeL}7^ zePgDl-Ot0)N7+;FtL3%AZ6ik{`(~7$V)vv#(&rDo^D>go%gEft=O#wxE}Wmc82Ask zD66v+^t&kidO77a)h*{?DCem7dejc_s<1^N8^$2^a+uL|*l z?3n4Zsa_%Jw~3j4n-uB$#Y|88JBQ^T_x#f4@}B>cCHtWhQ4YP2qaD7f93|~XX6=vP zdY_Ppse^XeBpoz<8DZ%7x%S*Hq73@jf$9`y&tWms4@;4Lrwsj-aWQCd%-L`Inv63>WSlv|Icr4LiV+>Kz^mBP;hc4{ zCAwH=kJ$eIcilhN5aaWb%-jqrf59^sQs7^;|Jq)tmubm9B+KicvYMlRYF;l-YVyBe z3u;l_KewxD(ZV*Tk$-VR{C}wM|J3>U1q=IYU(=#jj{n0W+vfF@=GES8U40g7ZkBOC zQ>CUE(>XK?O8;3Mc9v)R|I4*N%kt{cEVIVu)!x*({$HK%Hm_BF)h_R#wB+38|L_&6 zMcdHN>T-WIa?4KGf3PpKy<`czS&A9%1oK*{>=4|J?Yd@~0(I z?h#i0rt)t}e{;vvV|(`qD}Ph@)8jn%2un{(e%vE0zNz%IT*p1a($jJr_XvxpjS z7T;9)nu_;(5+TC$>q|Gn;+yh+T9)D-Vd*K%J;LH?xrlp&#W&TzH02+(Y{Nam^wY8o z_XvwupVd~3uy|Tl;T~b}v|PeH!s68jM-?M1zNzx*kMzUR(=rA32#cp>2<{OU-&Fge zWd!aKmcF+e2^khoO90#>ES?_myGL03TsIOjEdIbI;+yiXrt05R`=UqV?vaNdd_9F2 zYsqidOc{6Bl-lDe>n7Jo8ref}@D^_pXZCDK+TA13-qoyVa_QJKk8P~1 zZ;(_vze*o{ywRt6A0FJzBmC$SCN<7;Kg&_??r!XB(n>~ZT!LS!zJ963*EFav-nsf@ zsmLo-srC$^V#D=@y4q^Vr2a=SPY+>Ail6V$07ZRCJ4L>OL#TSbeY|{!1(^If-OHP+9stf`O{>gnaZjX|1USy|zlJI`bF3bLkF);G?pl$w0& z^-SVaDhKfk{~!PSQ;FD%)Y+5Te489*YLgB(evFOz8D>I#C@LEbpOv#aLFTzh!x zJ`Ae!nwy{Dc|k?v8q3{H=1G;$qmQ3!j>0_G3+Vc!DsV!O=X$95y-B*@s|4%A6VUgu zN^9rLsa7uJTfHPT-~Hm2e>y7@fl|Ar(QLJgSCBJZ%%)NqpZ*_iH%@ zdQ|P)F9_s8AC%yD)YLV#vaCYJ_^N1!em>2C@ZtfaOP{WkXyzKhZ4*0_u=-}e^3?fbp^1>p&%RdP?~Uwj@9XHIEUy_8S< zTR73Rl;53IgcCeY1Mu6u(PG=3#X-P+ zdAo>1fqi{l#LPf^j-XMmAD<)U0sH#9%5PNolw-n`J+dagS_?7M9 zoyG6)+ppiw;w51B#*A(6EM5cl_3bR)0;Y3H2gPrKq;p6I;ZGo`3DQCM3&;TyDf}IN zXLvYIe(=LDPafU}7Q(%8VcWZij=)_#{w|^$@Ln434(v{JiN7mwz81eHuzRC~;tPOh zXz@dU>73I+@%sVKQc&VCz^7|?BJf!nE(JbU!@mJOU&H0V*J`*5*spI-F(0^#7vEDH z2kf8EUByYjzWsLm%L)_VxD>G&pr{9N6|A;xl01fA$bx z1N;8iPy7JvpZ|U$4ZWMMufL$r;ZV0mhi&&4IlzAV=r6Vh_RHH}{5)V^e}SNJldr!((9qkx5og;4;uK)teud&}U_bvtLBk@yKPVEH0sHnW z64wCt^zttjHvtdQ@H${W{a|qquzx-Wi-&<}G)RYS4;D`XQy)zS;okxK_8uZ=tm~h@ zA>y?_`XPe8cj~u~q2hgDzyBF3{s~Oi6gq5ssQ5a--&_0`;O{MH*zEI%iH^WMRdS>s zCbj|g{bQKu0Zi8%Iw-z3@FWE#?hj1Y6gnt=5b)s&O1v*{rH01<`~CZHF$s8AFMha~ z4(zvw;o?YO-+zaT*}%R%hl?6u|N1ywEC3#(={pH{oQBT;K0w3g1G`58-#J{^Ppl8%{^GR& z9w0so;CzwccCNB~1!C6#E)@F)aFIAXfQ!Y#03Ik-1n?knQveSZzYX9aVp9MQ6+Z^> z-eL!L@F>eSObiKN^cMlVkC+$0`-+nTct3GT0FMwi2k z-)`VL41A}7?=tY+2ENC@_Zs*<1K)4p2Mqk6fgdvP!v=oD!0QeCsDU3d@Z$!4!oW`& z_$l#Zpg(xpz|R=?w+4RJz|R@@cLsjmz`r-}9}K*~z%Lm1MFYQN;Fk^jM+5)Kz^@qi zRRjOoz^@tjF9v?yz;77%O#}bcz#9$xmVw_k@ZSvlcLTp;;CBuD4+C#9@OuV+-@qRj z_(KDKWZ;ht{E2}#8~9TL|I@&q8TelY{@lP{82H}?{?fo-8Te}he`DZp4g8&f|6}0q z4ZOv`KN$E&18+63u!8N|vR(|dciY++z#~O4K4I|F4D1*<-N5Y(oMGTh1GhJDmVvVk z+`+&d4cy7VoekW@z&QraHE>r0cQf!d2Hw`d+ZlL!1Mgtq9Sz*wz&jbZhkp@s_010Q1GLk)bGfe$zEZwx%c zz(*MPNCVF_@KFXXGjO?qXBoJ{z?BA`ZQwZuo@?ML10QYRV+>qv;CTkFF>tMc=NtG~ z1J@b2-oOn8ZZz-$10QGLg$7<^;NuN^f`Jzs_(TJrWZ)$RUTWZz4Sb4~a340w`;Vs@ z_%s8bZs0Qve5QfVGVs|3KF7f48hDw3&ol7(23~I93k-arfiE)f#Rgts;7bgAsevyu z@Z|=+!oXJ=_$mXhH1O31zQ(}U8u&T`UvJgaEF#|tt z;3o|Hq?OCdQjA;!|4xTUX%a|VXy_Z0mZD|_I1V1VCA9LiYLx3iebSlJ)zQ5X-A`R^{yVtk{-yNGKT(;9*t zyHMQ2Sd}MN{Ejg_bI-y0thX5VleoY5oH3oY9DEZcofj`Cef`8PjFrBGz<1*0q419M ztxS24nR4*0si}eZ?Zhm`sy;i3M#ieXIpP$?v}Ps8&J$NKrZqP?_Fm#v##GE4yRY~y zV|ommV~-H8FjoHDOT5Q;n2awLKQN{>BRN=~(1jOIsQkN$o{Uv~JBT92s($;5k&Nfc z^uxqqf%IL(9LBV!AP3HI0%KZJkz)^(YdgAP!N6|7B+0Kx(wdO2qtx05l6@ItxeX31 z62x&b{wJ2OT*?xGGW-;lr?Nba<>@TXV0k9Xvsj+Z@*I}uvRuaUJeKFPT+Z?WmKUpBSFpT<<)tjKpiY+ea+X)HyprWrELXC;nk5$A$#mDUypHAdEN@_mh9G&XSl+~P zHOnDC+ZkG43yqD#DEbnLe0LuqiKEx6W17*1% zVY!~=qj(XS&N~*KRgwHr$Te|diKW7qa`;vu*Futi97{aN!!0F`WcedYTC?S)Kbg}D zOQm1R=^<(DTmo_?OIi_2m=@4_=}+PG7N<_v`IH`bke>cjPLH)N^Po0y z3a5uWgwjFEazJik{4u1L|7n~)!Rg`uvi^{=+>o;<9VES1LXuuu^3r1gpR{Wlr$@Vy z=^*eT zUdRfTeJDLJt%>u}pT+61P*bKy`hLm=IY)|Ef?8LGw%N_LkEN6XKXgiPUg??9-2U50YNZFnt z=|wJzC%^FQc>$;I#Ocvr%k+@aA0VYaK+@XF1Y~bL{e_&qGp9#CFVjOxdqPTkLVip2 zgCx6n`Cr88yKwpoIX$F2pOEr=LLNf-Lmr{$j|H>xeCBX^Tvv`IJ3z{EL&|bMPNejZ z)AaN!IDIas$Ms02hm`q4%KRb!L*<90cI}n_5>DTh)8jfO(?iOB1ac0ggOvRVWS~E} zl+$Bjv^;;f{>k)^viy*;{E+`5J&?4<*317gPLEI7%k;Qz%Jh)(yhF-*K+@}M2}n8* zUi!;9{kEJQ*ISt$QsxgS^M|Cj7ZQ-vF1_?uaQf{yJ+9L-J>;R3AEfka$oCm<*7LuT z({In|aebHRA!Yd?W%(h`rTif;)bqcJ)9=9PF)onlA!T|>bLCW$#j->REWA*gca{3;e9^)UG9#YmHQkDa9Rs!iEt02AecpazTnbTw3 zB-2C6ehpIgYmoFhZ32?chnN0(PM^o=ujBNPGCibB4_QI!A?bX0>2KilyKwsJIX$F2 zkC3t+kR2&KB=v`0`WrcYPfmXWr-zjN7^L)PNLs_4fIJe?OTUWK@5;5vLWr|-k**K&GDSszGwz9FT*Lk9f)7EZqhr@xugLrOn~lCbv@XFZV8FCgXh83y8OnA6|O=^@(nI2N6hoqNA6Oixd=^x?rdvp4SIX$H8FCnErL(;fD0oh(pzn;?%X|--pvb%IP6xdPtcb zlIEoe$ZS3R6PA1*D6y|4-*ZVkZi#->o)EqtNrab>MEGiIo~zsTX6IQ(l4{||>_N+bDsB$00~lE`-?hfm{h*}f1i{Tk&wfy0+D|2pQQi;#NI zM5LZSbNB}w{t1UmyFkx&WFN8vN$B5~B*Ld~cqxa=>jT2i;P7)e{AQ8}m)B+Jd7Q&v z7*3W?yptJ^VtfkY62_-89?keP#``lqo$(mPXdE)Xv5e1TJdW{MjK?!RoACjR z&tZHZ<8v8LV7!d+M8@Yap2YZk#*-N@XFP@R1&j}3d?Dkhj4xu0#wYD_G2>FkD;OWl z_!7p`8DGj6jaH_=j4>vQ5~I_Q_Q9ZC;wu=V^OE>V#<-YDd==vvjM3T1^ysW*{MC$) zWQ=)_jGxIE^B9SbVtgHAbn-I&^^9@xlK2M37+gtwBV$}#BwocB7h8#MVvLKP#281* z{4mIr7~^7zaZ!>O<6Mc+nMsUstHikYON?=-#2B1PjB%yJ)r{9Mp2ryDJsDra7~?mI zYZ+r4Ch>g6cQQVfF~&(UzK$`*JrdV5#yCde2F4hVNZiO6;|qxwFvfU6;^P?O`Y-W9 z#<)mGyofQb&k`Tc7}r~g(aFpDLcCm1hf{3K(v zcNzZ_W3+dPpJt5qF7Y#r(cUHgEn~EIiJxVB2IJ=#qrJ=c-!Vpem-uxVXynXzvog#2D>e;+Gj;!1#}h(cWeJpBSUPOZ*CB zw0DVLWsLSN@t+x^y-WNWW3+dP|H2sUUEX8Kb>Rypb{5 zyTorXMthg|ZN_Nt690`c+PlPmXM7#wcNn9+%lLO0qrFS~55{Qk5^rLR_Ac>zjM3gD zexLDb#vd?7dzbMaGDdrs_#?(>?-GB^80}r+PZ*=UOT3x!I>w(eMthg>|748zF7aoK z(cUHg7vnn_f6f@~UB-XG80}r+e=|mVm-tJ@Xzvn##Te~f;;$K_y-WNJW3+dPzh#W} zF7bDa(cUHg4`Z}iUrGsoloEa@CHzlH_??vSH!0y~Qo_HagkMPsf07b@BqjVuO8AYG@E0lJ zCsM*cq=a8c34f3hejp{zza>&0rQ-`m&6_syn8tw%M6Z%w6AI+tLix8y{w~rE{<<=wPK~u+lPEX&J1v z3|3kOD=kBmmLW>Z5T#{^(lSJ88KSfdQCfy5Ekl%+Axg_orDdqnGE`|9s4W=WYoXP{?sf z$@FbMy~!85hVBG8BjW>wAXTG3zquCA)7bbrsLompK_R$g9LxxhsYi{@9>yP&?I&iz?dS5`B}kD1?C zUIQKV0w;w!1>UOI?b!5FMHZ4felpeVw77FZXt3TYz%?-3-#s&iQu0v6bu9rzWpOib zeT#!#+W-c)cSV49?F8~JWp3@XE>DlfS&^4Bgqhb#1i3XB?Qc$s(Bz9R0yVdAJ2`|> zDb>EXDxK_#gKXc4RJcn?zK9~;D-g~I`5l7DTzW9?IvmVI@3;};UimpWtgRVZ-x1f) zZ>XWH-7UA7InBN5GS<$kf5xbjH8d+LP^ecIuhU^_a4T&D!a`hZ?JRo9VIkQyDxxa6 z8yUz4L}fG8$%5~>5{6uyxpr1KPhA(gtlu0cK)aZ-5)3|)Yp!{Vt5OwKFQjp$fIh9K z05UFs2yu16b(L+|=$fA*o9b$}f?n%)1Kfi$@HJ@Ez?n~ zg!k9I*W3;vCaXNU0e4c;W+9wEE~4PG^Hn7$bXZy|6R{=0`;k46OO z^;irXR*y3b-Z{Ws@!vgMeb*yE*N4Y&Vya8xID&Yb6X4--fw%uQ#k=}mG04&-mZm7*8iThCyq+QTecIsNo+95j4c>+n z`F?HiXw7Pv{c;fws%Mu?DR_Gtynm(OjWT#!fb&A?dziuNo(M1BF$S*>c;iC!(YsZ8 zJ?4YAX9({qgLh>Lee^{hUEjOlm51otXz)g(Gw2n<`_ACa1rJM@yu&*0$|Z*Tu}%G}NO5QEnqyhFXx`MjeIUO9MS?U&Zh>Gik{y!j#eE;V?a zaRCVHUv4pYE<3(@yagSQd9?Lv4RaX$6>ehFUR5Z(ZT zmzRNcq#?ZV2Jd+A#)R<74c-&r(KX6F-1B>a!RwysePG7`*Q7h1ffU*A9M8Y2Z%sm=0c8zqXyhD+iCR!S3PaJH+6< z4c-Ko1nKe)F?h63!l)45u?DXiyg?zn^92_9U_J6yYD;6&)>V^8p4Lho>S-I?b`6odB{Vn}?~d6pdWICv6Z--Z?w)dk0PM8oKj)icRnqV6YLVe2eq=J?19# zt?S9}D>uP=vlqXY+yrmd?)?646TIv8;P;H1;Qe(kevhdM-VXia<$DM^p*Viw_iqiN$vbvG z5Mt;%c4Rz1tuNvCW}C>jYJYw|wh3O@Sbh(-3ErjSh1eX!ey1GB@3l6eFLx5Zchm&$ z)G2tSCWig&X+ph++JwHR4(9jon&4#~%I}pn!K?cXzdzap?}sDQ`&I@`nEo>7D1IN* zAey`r%7uFGvkBfC75si@6TEeEaQ(oT%RJ0{??0N~%QT24@3?vVo@EofrSs$ULyyjcZTZTc7e6O(y-sC0x-eMEH!c)}yg$6CjU#>ij z-#;{n=K07tGhTaJcs9RJ*o3~kW%2Y~aDKe&^zj$)`+rU3`^`oCo?jEZd6)3}d`@4DJ!6~8~%gua7TW84|iJ_Z`& zza!TA-xt$Wn!J<1TcH#9x5>-7IUa8{c-O?xH~N-%`d*L8tG+d!KCw;+xK`3(*7p+d zu1{j&T5H&O&}~BeJ_b+R9y4F?Zi=CAZ>*n>Q;(Oxi=(gM&Up6Az`A@ixunCi%eCOe z@q>Ntj>r2ecyau+_MUjCZ| zj-M`lP6)V6(qWcw-`@#wV-hRbU)}*Pj^8&vFX+;mbeQ?>f{SIG>(R5|U6-USxqP$# z5YK);g7m0iaULzTtm~ zSH8vIjgHYio`|VWydE##5#UXUk?#dD^}QUE*ZGZj<(m?dcL8{D&hP8s9TlU#L*9(1 zZz*_(#?bdVcq3x)w)<;5-k~vhm&fG29+S7-#&~u)3cNV}yecN|L-69*ug_cYcynX& z*2d(07?aoM?Ra*n1}{#1*Tv**j>+r$w|M8b0lYZnyEi89%b2|4zsJkBAq8)eF|NB8 zyj+odn7rq}n~_WtCU4hw;_;Tmk2{ScFP*yeck zeIO>U+o$pBaV&U;$LQDo0N&9tcmw|#FW(Eni=*#*@Z$6bhkX{0_W*ct{3Z8a@p!f1 z#VOwlF?oA^9#7xdF?k<=7pJ}@U&P~G8fE$vFn^Gw|}Xc=xBt z>-23r-hi0A$uW7gF?q{l^6rSqdnqRGvzWY2-^H|FOy1;}yxN$&s|t{ zmpho#q{;g?c)Mxw?oX4qov_4SZloqnUI}=+Xz}h(lUD)W9&V&2P2PDi_1zw`d~bla zr&G4uTscyZ3}H{kVlGt;D* z?@l(plc2@BKTY09@Z#970=zi(TMk|vyF3Ek?rxzpX_oKZnEE>6Mecr@9`~oIZy0!S z@+}9ikE=wJroMAx>bncPo|+!_r>XCinE8GmlecS{CBGHx=I2T?-%{}M-AGNEywkvo zW9PfTi{l4xffvW`Z6_XYcktqzx5?ne@%y@%`CbNI9KU)Dyg2Rh-I)3^)8pBtKX`HM zG9A1)esBhO1)86@KTUsm0K7Q;={w-Xxz4n27mrs2UY!2w$e6sd!HeV1_kq{nHHIcl zyZj@jzD^nOuG9J8#W`8y-+{}2qk>JH?Z*#$m z)83ZFrpEgnzGt=_ z@Y9y?>YV}nxWW6o#&g>f@!kXv|CYEazXea%PvOM-#L$<9@1RjQ<$EfTaD?%)HQs58 z7Ru|Y@lKE6b=P=jMDTiPyfY(seKp=$5xioJcXkACxW+ptf;U>@og2ZMpz)SP@Jcn_ zc@exB8t?oFUWLY69>J^Dco#(Q8Z_R85xm73@1h9aX&Ue12;MS{w<3bKLgQT$!CR^E zE{))=(s-9e@YZR(%OiOAYP>5Vc5G~SvB zUSEy3HiB2I@otXb4cBO zyatVTR|Idd#=AR$cbdk#CxW+3XXXg11rQJr=>+r12h);BD4;Peky()Ob&7yzh;1 z-4^iN@#LroURQjFb_C*S{8tjeE7f?TBX}z`-u@B1S2f<42wqow-*yDzseEH2c%>R| zTm)~0#v32OdsX8d5W(v@$S>c45xi23Hz9(zLgP)0;JvExCPnbN;`_WK5Ks1-9KkEq zcvB*HE5M_8(sxhfMlkQF2;Mr4R~EtBtntbtczuWa`Ob>qRcpM82;Mr4R~f{_L~#Is|Jt!j(Bq;c+Y71sv>x4_&%_!@8}5L4Dd!Ep7K2=g11uRRY&kP zYP@+7yzcm}?+CS z(|8RLyv-V~F@o23q@VAC2wt_uJ1&B^4m{T`3nO@6YWfyM@QO$IWMDY4*yjLT5!!_QYBX|=u-fI!O85-{|5xi=R_j&|xvBrBNg11cLy&1t< zsqy|A!CR;CHb(H)YrMB2cpEg{+Y!8t8t-oryv-W#?-9H$8t*8azK!55)_C7V@Rn)3|3vUsYP|0wcI<86)LZPs`KV=+2toM?{MwrD&{9(>#p(kkKpyy zcw-`X!!;g;3MuoQpz+Y9r{vAhcxZYldDR*ZCQ8X$tnu(OC2yI=n-IZUsqrR8@YZR( zNfEsD8jrpqLPywn+o18LMDR9hyn`Zmn>F6l2;LTrH!Xsf4Wo5N*=b%;8o}$X@eYpQ z_0@ROBY49#-XRgZ2^#Ov2;K~hcUT0kTH_ra!CS2HeiOl4rtxM(@K$QPBO-X~G~SUB zy!9GyW(048#ycv4w^8GjMesIjyz&U%7L7M6f|rfP==xtp1h2cstBm0F)p)Zbc*8Z` zoCw|ojW;)fH$&r9MewRM-q8`f#TxIJ2;MS{R~^AysqyAT@YZR(nh4%{jaM7N+o190 zNANakykjGHn>Ait1aFJRtB>Giqmy_2uOWihUE?)I@cL@J1rfaA8t=FW-UN-eFoHKj z<1LEdRcpNCBY2B7-U$)BWg2gB1aGCrJ28T{PUD>v!CSBKmPGJ2XuPEnyp0;~LB6!_3-kA}+UK;PL2wq=} zcXkA?SmT`&!5gme&W+%W)_BVzcoQ_J^7co#(Qsx{t)5xfSC zcTogyvBtYNf_Iw6TM@xqrtvO`;H}VjmqzebYP`!Lc&jwt~3<6RxWdsX9I6T#c4@ve>FZPIwxMesIjyz3))UuwJ?B6wRg-i;Bw zG)#)z{%=(TFI(f?6v6AN@m5Fhx@){O5xia+Z*2sxug1GMf>*5ZZi(Ox*Lb%^@J4IA zbrHM?8t=9UUa7{rJ%TqwLqB@t%m_ZPs{CYP?d6>m2QUjW5C5fo}E~$87Kt2+QN}j<|_)VaFhe z)YcfhYcY9Wh%o&i-h#@ydirp3ZTZmy@^BOk9$b`PI5@v>XkK1E1qA-)~uQ=q_&VbJP_Ru1c5h;-yJy+Iu}uec-k} zFMdEI8ALh~3u>z>)GN?T>vHI-H(ons$ie{4F0ZYv7M3mFNn+vyjju1i@8B7?1c~)k zb80Fp@@CB~s}okbd^d^tKP=qltyAyXwqKCnSQAK*A>XFs6ib(0RNZUEq;G>Mjw9VO z8w5UG+FNi{MB2J;TaPceZOVN?ZvEWax&~o6^4%=fTDty)p?{rp{j4Cr=!q^d@$?&lYxBImyCcRuRfAA&qjwM@`XzL&|07mT~())%LBIWU-@ zy0&JHupQlaHDHGYv#;Gl%l8*_Umq! zxLQS_@C^Czu)n-L;;EY5g6X_e-4bJ5&GJPy&aL?PtcqDxk8U4GWmB>8WZBXj`Pvq< zH+6gTnY~62$PBUrwc%v#^mBac>7%AR_s_NSgUM!B*OtK>(&YPFoWa@io?1|F(K!Qy z%!=B^^6E;FmZrP$KFi;I=C>O+e-ot2lKcGq&{kNrHDGS-yvhNMFsm>>KmWM0x=O~g3x^a9URVKCU0GINIdlFoa|Tq@RiPuOt|}kk#`+;{5204W z+0B&8tXcH~rgDk)A318gC>@_yI&oT2VSWjfKW}VNUde!xz4pp0sjaA-Q(2RDa81?1 zyak1Y{Rj0g=s%%!8Y1Q|s;inaw;`|3tUdAyh7KLnuQ0!0NM32>!m|3j@iq7oeB->z zng;qktF~@_ZCzPICAK^Gx}{AhaL_qxd#1F%gDt14E6U6{l?@ZB${A6eWu+~vz-`Fk z#Afm@-;0Z_lM-|V6}TQznY!XHUB$L`AVJq23ZVbih4`B$X!%+iA{GS+&0bJsi!lM# zY~io9uj6z~w=EQ^$x_P;#8w<>D14f=Lv~k@k)F{mBO@a-qkTqJM)!+9eyCPhCB%Pho@l;QowUPDpmGjWE z*NKd6+qcWMyCHB^;gE%8e$GH9@5?9bgb|-5+;z1oeFq~xTe#~tReVQrc0hk8 z@B3AB5^_*KWe->t$LaV_%{QH7dm-kL1SlaA+(?FJb2!Gk$1=Z>B|WR5^z=-G5%HHV+U;g@sxN)CUJ!)Xm6>3@;KH*xsa z98PN-DBq4$KIEH668v5y5k8W`>6t5qAHw1EOo;e&FP*}da5&wAqHvnKQ}~@6PWO!| z{LdWz28Vye;qBo0#Lps0b|48py}M4~B^*AB!y7q#5r<#M;Wu*l8V>&*hrh|;Z*%w; z9G-@AL;5pFBHx`zBHsZVUc}*j$xdiW`6Ll0&p#$o^sGh4s7|V*bbP_6h4o{`)XqCV z^lzwK*r5LI9e#c4Ur|}!IA>;6&FosizpJZiD&60+>&oVNpsc*Su5y7J)v#!OWxWe9 z8gYM?)s@xE@nhy=1P2}Usd|~%MGWNkUz9gS5ogXU9Y3?Yv8uXaW?4f+T~&Ew168Dc z(Y%JTa?!tZJpC-Mt?pk|T~&q%j5z}~^RX(QkGb%E02|g1@XY21d8U&&SI%mnneFWA zvN=?yhB{fM`nmiol{+Mdlkd=f@+~@wmGJ($zD3h(lLr^}4wttp^W2Ex_%Rl~YaZm& zZW@X^6&%^m8AOx!EILlvpBX&LN7wfRDzuBiA!zd60q>F+yag~on7(mHtLJ+;cq24@ z?#1?CgZDak`nAqYV)8x#kMb}NlUIb3v6o2#o`wH<`HlpyDuh>K@SX!NFNAlZ!TSI_ z>Zi=(JOtpB&UeFe(T^3mK$AD(H@Zdd7zbV+3cMpix^O7$#+lc?VzE{Dc>k#RK z9ppj0Pw`*potCZobK<$-#G`d~F2+x>LgV35ArInpK^{796?ifnah()R;@!a0@4>AD zFYF%NVDPBCd7SoH@b2K>t^h^QVOBXCX{-%y&w~DKFzToh!t1rH_ z-R8xrE?j>D!OzI9Fdt-rtJ56|@20b2;I-Cfgk1ZldJ zwXErJ%U*d~#qn$U-PGacb9_y!d)!KzcE9;%(zROZTHS+~#CztcI9f-<);dDddUL;Z zFNm#cm##evxmjyEwJ%#uzwFhW5@q7CwA!@C>{|OV%U;uC-G;5==6-9^hfQD8V|9AB ztyC=+--@ueMfSln#c}cUG6O)k{M(zM5W}{c2im`&aGSj8`ptbq{e~ z-Xf)WH8ij2kuDyc}E_C;7zJOvLB`&mUU74Lr0CAI&<>DrBeFwnksQ)!~DjENsaR`jkwCKqU?e>?bJlcPXD;B z)1p1}v>jZH>7-IjgHqQ@h1V2+v)gU!DcsA-o{pcEWxwNAXp90&BgW>G=nj+1dJay&-+?ciBH<=?xmyFzhI_z&d_6KI<{v{))6wnzG3CI30 z!#!WJBq&0#Book`JN8E=Yy2dfUP@Vj8`_Tju^C@7VU*0GSlEdE#EeGyN@V#Gh}|5F zEmTE-@Qsn?*q=7VVrziu~1_o*G*x#8f&mcv@Li~Tsco;+)9Ug+{@6Bj7ND(H^j=d!qJ4h7) zcJU38?btsw#bSei`lCr@gP<^o-P$hDCI-zUgA^-+AX-?#_`zmzV3CfFZ6(n>lN1XJ z1Ure~+5}F5_(W1X8>JYtOUF(#qKBwr;QaVj>Fl7p4VE^U#%2LGJ&B7PN2!hk(e09= z$uI+zVGy5T#1Az~1jFPwc4iXIGt59?fzUpQ0K-U!#Q8ydR#H5QIa>86h|Ug17jW+i zukj7j)v-G?Nn^u++cAmDhC!Et=uSz|WSBw9Fo^GL#B(p}mk5U0#<9C3(LBQp!d*JY z&PgJ;hJnW*J~t_z4TF9K(Or#b?rGt_zG1d=>~2lc*f8L3lf-4ipld<&wnjAfrhbm7 z_zsS}T@npircEvxDJ;ZppA?H)%jO7oK>Q9#@myWj1m@NcS(wM%>rjY ze9xqKHVe8BMDJ=u51Kh`bitSjrSQ$k6Q^JRlIPgHqB&#`B4Z2!@@@usa6lny)YGwh z8=N7`fhVd=dpY**(Ht#Pkoy?qp#g=+w6|mL5#$u+GY8J7GVSBodq#7#OhMkuAQuD_ zBGWw`yRX41WDdMfW!l%V`$coKOhN8%kc$Eek!gR&9$;{a!70?wX})9UM{~4HK`t=J z0|N??X`y2m8XR&Y%G5ij#g1JR&CxOix!53+Bl!xE=^)1*XmH4ph~u5pA&xyLnxkb3 z@?e8Zj^ryurh7Z~kRYds9EmvIIUVlUL!&ubrXcTakjasJg~)VY#~y}RH{HnRX~pqR zef(w7DX(=6Oe+%F3}#~E!jjsW*;R8ekJ-n{Ar#6B$>rn#kPZ z=lIYer}y4+P_Ipa9PQgcz(nRIHMyXk6n7dOd$o_z3pw^09}mVv&tB`}AvBJ@*~ddM z$+K_qaX~(fD{s{T3NXd9*J%NTG|oav2Kl9ZdC!NgU%ve9?*gS&GrZEes`+Yuce`6B z-7E!vJ|rtE@%@mXSzLX}EGK1qC!*)YXKp(B>IdfqGO|tv0cIIvWy({s|CB=}hRpEf z^loeu9C8&oyBn8GL{IL`@5U!b)9AyS;T^zE=9MKl$Ag#QJRO)!^2Q!&iZ>ydf$NPn z$(xu=Kr#Jk-Xt@ghaV8+KClV=V{#KDHVT+il9_B3HO)IHIiAeoPxPjm1Rk7ld0-d# z=d@&!XBRcoD@|s&c0mh(ii490Y!@}#n{LMQ00qTiyP#bh(gca^0_LH~Oty=f?H!gJ zPj>O=dxx8Z;EWG;L9_f#GRd=xn()m?X234ml<$aS0^3DR`i?Z?gVR3v3wnc@O_10w zU>=psWV@(IUs-ZI*~Opsm79d%ybpFkXEZCB~d`YMtcu3g|SP*IsoV7sV!-)u8J zIHQAIFcq8A1c~he=GRmt&W7k}1wv`Gj~`(PK$$&N`Td3I5gzUpKK?4r&3 z<|PwQP=DH2W5gTtKG+2_vDzj`Y!@)+Co|bDYR-3Tay;3^pY+w4gy5_XcEOaaKAGg% zMa}sdk{PaD;4e_om`q^1s9E0vGoJfho`k_Jn5Z4s1c~he=E7tq+eJzCIDW#&V}C`i#dKw|PT-$&r(SGags1n(=7Q{j!E%U;Iq>H&zAm9wMJaJ*0;e(s2J_J*0>R+>huX#WW>cuZIkz!RMoT$RHX9KBk8Z zrh(Ywf#-f#4PQCq(p`p(3KU(<3P(0BoK`hQ%?qD!tEgM)yowL+J^s}EFN0QcH7YCZ zp6$&Gclq(yo>$$SdrKfIYflg`FI>ZOHT2u5riE*xDdaYCR(Nv~4}HBiDZC{qmIf!@ zobXn5H@6&NQ^Ivg9B*WzW`wsT5ui?+5Z;~?j}rRx!8?p-9+vR*3zum4$DPp}HU@}y zB@x*gYBG3tQZ$*vp9|h&#D`4j~mfp z)4wO8IcyJf5Kkr%*&b^0_f%3e*~6dvJ#EB?P5qup;&}E@Gr!*^5nOwyiQltH@oWz@ z?|aUO4x9Gb;u8@$8{ydVfwL zxb{#Jz1NcB*&b@1_ZK5NY?}9aG>7ehS>78-M7D>T<;Dk-*{uRy9GR17}bAucM~ zgB&)K`^w;iP2|3g=4hE>9`}tw4x7e(YjDD5ao1Cii4{*=@>kj_umJ>&}7ftouR0%p}uRPpsrMY37&-W7XOnT*&Al1ny5^ z!AvA&94$ob7*63a{RDc_)G3lOj@Bf04yW(~kqI<0=n_d8Cmbx638&ynp=yN5W^N>9 zoM?wNGvO3;@k$HE+T9{4<3uKw$%IpQ0nh}R)NUI|87H!^OeUP--C4yrcl$`nIMD&i zWx^@E_+$c2o_CC-j1!%(Tqc~t{(^-r6X-F-PEE1Ki7r?#6V76!rHCCR+97suQY<=uzKxQB_#r9d2Z~I@4-JdwX?A z8n5Q|xri?bjaPHsu81EU8n5Pl-4MTja=gFVZyONCBoW{o>Q3FZh#s3Nx=?I~=y9o{ zi^TSb9-k_@SnPo41Hz)!Jby<-ADAk-P;^K1gjCT*VkbmTOch-$dLVjIShTwTw=<$A zr;5ftDi|kBOBIcqONcH_6^%I?q7M#>=6eT-o}MZiccl@1NUG=}41=)5B2_frTtW0< zNzwYs$_b(!IEP1a#)%AYev^WO>!MtAnF-E}NX|IX9-JdmaBxkOda}SdGLkb+WP>v^ z1qatdsiy-tM@4eRiH_iug>Y!q8^#V&PbYB7BRS(lXK-ev;JEhb0!~FFXB=MH$AXI# z9M?X%;LMKXj1yhKnUjL!+NT>hb0az9#5Ukm;r+>>{w(1Q@#H@)zO*Lzx|NzGjIY5f zOJnfPFxL7VZM)-peTtAb=qh=B$XN{pWn14a@xR9ZwWL`{?w8xsu@qb3+_ETL-* z8h@!R*fjJ95TECr_spC*oqO+KxVxr$l6&9#KIb{_IcM&fGiT<`edfvJDS`&im!jp?=;7JlHsu^F$%vT9fntx!P?D<&qitxBq4#r#MDDb&v@sfHDosH}z+b1SJ~ z#muN3mDI4}BIVVvVqO$l)v)+4Z#}6z(H^}1$oUJ&lgfN3S+!&tC98rJMq&kU(*sddSJiMOF;IN(=Fp=kP~x^lPOwtZsPu08j7(Fa1G*tw4YjW>pgUiaE+ z_21gW+{_Cu$xR)s!-kamt@mx;zfS(g8(%y#-G-P~DN2>bo^Jb_{QG@>{T^wSXZ|ki z`y1|xZqzro-sdBl`LA)_-xAZzefxR;_B}gxpsSvlvkQIfrMGIz#}k(h)f&3fx9bKU zvBp#KRvK<*cG~who6(dcRCg>Ll(7WynooM>j|qv9WbWO;ND`9yPeb0{7>^@!+Ybhp zJC26fziF74F41vh&r69b`rOLlFgj$0Q6j&(qv&ZFMH6!4)9#5~p1GGPF_g^D2pCE+ z)7%S{7*FPBh?3*!{Zl?K4PyIVg7eZ+GcQ4}GCKFWY5&Cj16WNUvD?1?oLS+?&`P0J zcXa(;M%T{h)YP18=KUQpXihZq{#KoXjM8RdK)O<#@-fqmdN08-(`&}eHc061jYf@Z zWOmv2UzKs!3vY zO|B6Q{j)Umk9g;9;%Ez3b0W9{ReIH|AiTJMZY6Yv7i82K=Gn5*8Ri+5(J5Y(u{>9J z)hIuhv3@QG((3QdSe}OmQ{HbCQRRf7GDJ_8&%Ji;?mF=Bcz|4IP`A2>gJ?)~^p}H+ z^_N}sEdF9 z(aEmq_f|s`vvv?jSHVQ9vs^^07dNV_!E%w?7)ot78L92&2R`e2tcKFnQ=_`yg}Sha zLJBX|@e`*8lhX3J>znkS5&s>tE9$_;MrajHs$Pt?0&q$z(t$wtU<|qFGR|*MWSRh%BexhgddAVx3w*F z#i#f?hOH##&&Ma~c{1hj#1uI$gs%AfvS(R7Zc_1PTmGnirlBS}|HEYxHPJU42bLP; z_aywh_tk`7@P3f+YrJ14{5r?4cl-v&Z*=@7$8YwyGB7E~&2apgj^E<=t&ZR3`0bA0 z;r+!_1{+{0mGoyj{v5~ebo{yA*+jg{ytfm6t&@Mb<99j!`y79s<{KyvYcA*gSuy)P09Vl)x>`g7`5=lVtyBkpP|G;b5<+_aiI}0z&-d?ra!DD>UmWN%F3;p%5QF$!pr2HH$k9J6TSk@E3^7+TKD_I`)2D>~u zCgmY8EcK)PQXckpmV*`Tepsm=Hc>yOKPiuiM#`h#QXW>?4=e45UCjDnN9_7BFH3m{ z{z~~7S{`=@-2l`^4j{_RgG+!f?&q|?|DgCO#ksE#pUJr3x6^_@ zObh%&imz1sA+(kFU-lSn;EZ|4i}UDSlG%16PJ|K1Yi<{-)wB%fdK4w20GBi#Vf-uU33q@vVyQRs2(mKdSh*6@OasUnqW3 z@mCZ-qqv8IBkRr6qTWtg^l?b>#fsmk_{SBWP<)@_4=et8#g8cd6UARpd{Xfk7k9|<)>lS^M1>%X1MH3*IKgDlTAMwP;B1`fSPy7z`t#~Gm zDR0UdKBk>giOd$(pc;yqo=;Yf3xb{qQ%X@K!jylO=e!I=mqSU!M~1 zUWa!tcq>zQk15Y&@%gWBV9s^ZVF1XA(z93V8aG114=%6e8eL0P;BCFu3)id_c+afJ z7VpCKx(2NfZ}`Ky)^vE!!ngZNy}xdUL)Ycq4c<31@Mf&`yl-XT9m~jDgTZ$+L%g%# zeK!N|>olzzCphrt`p!22P1i!$&gGuGR%F}!x^hI|J= zU_I|>1iYm#34RB@G@e?UbO(5kq9Atn=vdc+&t2fvSkF7UaC7oGKP+E|*A?K^)6ta2 z!A)@ZIHi@8#%r>8tdA*;*J1HmLs}}Y%i>|#E-5WupT#rROv$^(>Blg5oxrcai}_4x zyj9>`hdlDkc1YtLvUoV%kd(%I(crX(+aOI&YL8Qv<3*KF~|o&FvIuMU$p`%!E0 zwm7^mZ4S?Q$eUG$_YI3TyA1D`#hX)xcf#WFdtu`CbKCb@i#JzTA#ab + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu1/device/driverlib/cla.c b/gpio_bitfield_cpu1/device/driverlib/cla.c new file mode 100644 index 0000000..d933af4 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cla.c @@ -0,0 +1,89 @@ +//########################################################################### +// +// FILE: cla.c +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cla.h" + +//***************************************************************************** +// +// CLA_setTriggerSource() +// +//***************************************************************************** +void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger) +{ + uint32_t srcSelReg; + uint32_t shiftVal; + + // + // Calculate the shift value for the specified task. + // + shiftVal = ((uint32_t)taskNumber * SYSCTL_CLA1TASKSRCSEL1_TASK2_S) % 32U; + + // + // Calculate the register address for the specified task. + // + if(taskNumber <= CLA_TASK_4) + { + // + // Tasks 1-4 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL1; + } + else + { + // + // Tasks 5-8 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL2; + } + + EALLOW; + + // + // Write trigger selection to the appropriate register. + // + HWREG(srcSelReg) &= ~((uint32_t)SYSCTL_CLA1TASKSRCSEL1_TASK1_M + << shiftVal); + HWREG(srcSelReg) = HWREG(srcSelReg) | ((uint32_t)trigger << shiftVal); + + EDIS; +} diff --git a/gpio_bitfield_cpu1/device/driverlib/cla.h b/gpio_bitfield_cpu1/device/driverlib/cla.h new file mode 100644 index 0000000..fee905c --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cla.h @@ -0,0 +1,984 @@ +//########################################################################### +// +// FILE: cla.h +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLA_H +#define CLA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cla_api CLA +//! \brief This module is used for configurating CLA. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "cpu.h" +#include "debug.h" +#include "inc/hw_cla.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CLA_NUM_EOT_INTERRUPTS (8U) + + +//***************************************************************************** +// +// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(), +// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt() +// as the taskFlags parameter. +// +//***************************************************************************** +#define CLA_TASKFLAG_1 (0x01U) //!< CLA Task 1 Flag +#define CLA_TASKFLAG_2 (0x02U) //!< CLA Task 2 Flag +#define CLA_TASKFLAG_3 (0x04U) //!< CLA Task 3 Flag +#define CLA_TASKFLAG_4 (0x08U) //!< CLA Task 4 Flag +#define CLA_TASKFLAG_5 (0x10U) //!< CLA Task 5 Flag +#define CLA_TASKFLAG_6 (0x20U) //!< CLA Task 6 Flag +#define CLA_TASKFLAG_7 (0x40U) //!< CLA Task 7 Flag +#define CLA_TASKFLAG_8 (0x80U) //!< CLA Task 8 Flag +#define CLA_TASKFLAG_ALL (0xFFU) //!< CLA All Task Flag + +//***************************************************************************** +// +//! Values that can be passed to CLA_getPendingTaskFlag(), +//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(), +//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt() +//! as the taskNumber parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TASK_1, //!< CLA Task 1 + CLA_TASK_2, //!< CLA Task 2 + CLA_TASK_3, //!< CLA Task 3 + CLA_TASK_4, //!< CLA Task 4 + CLA_TASK_5, //!< CLA Task 5 + CLA_TASK_6, //!< CLA Task 6 + CLA_TASK_7, //!< CLA Task 7 + CLA_TASK_8 //!< CLA Task 8 +} CLA_TaskNumber; + +#ifdef __TMS320C28XX__ // These enums are only accessible by C28x +//***************************************************************************** +// +//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_MVECT_1 = CLA_O_MVECT1, //!< Task Interrupt Vector 1 + CLA_MVECT_2 = CLA_O_MVECT2, //!< Task Interrupt Vector 2 + CLA_MVECT_3 = CLA_O_MVECT3, //!< Task Interrupt Vector 3 + CLA_MVECT_4 = CLA_O_MVECT4, //!< Task Interrupt Vector 4 + CLA_MVECT_5 = CLA_O_MVECT5, //!< Task Interrupt Vector 5 + CLA_MVECT_6 = CLA_O_MVECT6, //!< Task Interrupt Vector 6 + CLA_MVECT_7 = CLA_O_MVECT7, //!< Task Interrupt Vector 7 + CLA_MVECT_8 = CLA_O_MVECT8 //!< Task Interrupt Vector 8 +} CLA_MVECTNumber; + +//***************************************************************************** +// +//! Values that can be passed to CLA_setTriggerSource() as the \e trigger +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software + + CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1 + CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2 + CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3 + CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4 + CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT + CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1 + CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2 + CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3 + CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4 + CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT + CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1 + CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2 + CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3 + CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4 + CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT + CLA_TRIGGER_ADCD1 = 16U, //!< CLA Task Trigger Source is ADCD1 + CLA_TRIGGER_ADCD2 = 17U, //!< CLA Task Trigger Source is ADCD2 + CLA_TRIGGER_ADCD3 = 18U, //!< CLA Task Trigger Source is ADCD3 + CLA_TRIGGER_ADCD4 = 19U, //!< CLA Task Trigger Source is ADCD4 + CLA_TRIGGER_ADCDEVT = 20U, //!< CLA Task Trigger Source is ADCDEVT + + CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1 + CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2 + CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3 + CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4 + CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5 + + CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT + CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT + CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT + CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT + CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT + CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT + CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT + CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT + CLA_TRIGGER_EPWM9INT = 44U, //!< CLA Task Trigger Source is EPWM9INT + CLA_TRIGGER_EPWM10INT = 45U, //!< CLA Task Trigger Source is EPWM10INT + CLA_TRIGGER_EPWM11INT = 46U, //!< CLA Task Trigger Source is EPWM11INT + CLA_TRIGGER_EPWM12INT = 47U, //!< CLA Task Trigger Source is EPWM12INT + + + CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0 + CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1 + CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2 + + CLA_TRIGGER_MXINTA = 71U, //!< CLA Task Trigger Source is MXINTA + CLA_TRIGGER_MRINTA = 72U, //!< CLA Task Trigger Source is MRINTA + CLA_TRIGGER_MXINTB = 73U, //!< CLA Task Trigger Source is MXINTB + CLA_TRIGGER_MRINTB = 74U, //!< CLA Task Trigger Source is MRINTB + + CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT + CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT + CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT + CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT + CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT + CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT + + CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT + CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT + CLA_TRIGGER_EQEP3INT = 85U, //!< CLA Task Trigger Source is EQEP3INT + + + CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT + CLA_TRIGGER_SDFM2INT = 96U, //!< CLA Task Trigger Source is SDFM2INT + + + + CLA_TRIGGER_UPP1INT = 107U, //!< CLA Task Trigger Source is UPP1INT + + CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT + CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT + CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT + CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT + CLA_TRIGGER_SPITXCINT = 113U, //!< CLA Task Trigger Source is SPITXCINT + CLA_TRIGGER_SPIRXCINT = 114U, //!< CLA Task Trigger Source is SPIRXCINT + + + + + + CLA_TRIGGER_CLB1INT = 127, //!< CLA Task Trigger Source is CLB1INT + CLA_TRIGGER_CLB2INT = 128, //!< CLA Task Trigger Source is CLB2INT + CLA_TRIGGER_CLB3INT = 129, //!< CLA Task Trigger Source is CLB3INT + CLA_TRIGGER_CLB4INT = 130, //!< CLA Task Trigger Source is CLB4INT + +} CLA_Trigger; +#endif // __TMS320C28XX__ + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a CLA base address. +//! +//! \param base is the base address of the CLA controller. +//! +//! This function determines if a CLA controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CLA_isBaseValid(uint32_t base) +{ + return(base == CLA1_BASE); +} +#endif + +#ifdef __TMS320C28XX__ // These functions are only accessible from the C28x +//***************************************************************************** +// +//! Map CLA Task Interrupt Vector +//! +//! \param base is the base address of the CLA controller. +//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8) +//! the value of claIntVect can be any of the following: +//! - \b CLA_MVECT_1 - Task Interrupt Vector 1 +//! - \b CLA_MVECT_2 - Task Interrupt Vector 2 +//! - \b CLA_MVECT_3 - Task Interrupt Vector 3 +//! - \b CLA_MVECT_4 - Task Interrupt Vector 4 +//! - \b CLA_MVECT_5 - Task Interrupt Vector 5 +//! - \b CLA_MVECT_6 - Task Interrupt Vector 6 +//! - \b CLA_MVECT_7 - Task Interrupt Vector 7 +//! - \b CLA_MVECT_8 - Task Interrupt Vector 8 +//! \param claTaskAddr is the start address of the code for task +//! +//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is +//! triggered, the CLA loads the MVECTx register of the task in question +//! to the MPC (CLA program counter) and begins execution from that point. +//! The CLA has a 16-bit address bus, and can therefore, access the lower +//! 64 KW space. The MVECTx registers take an address anywhere in this space. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect, + uint16_t claTaskAddr) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + HWREGH(base + (uint16_t)claIntVect) = claTaskAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Hard Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a hard reset of the CLA and set all CLA registers +//! to their default state. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performHardReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Hard reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_HARDRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! Soft Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a soft reset of the CLA. This will stop the +//! current task, clear the MIRUN flag and clear all bits in the MIER register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performSoftReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Soft reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_SOFTRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! IACK enable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function enables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! IACK disable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function disables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) &= ~CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! Query task N to see if it is flagged and pending execution +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the interrupt flag register +//! corresponds to a CLA task. The corresponding bit is automatically set +//! when the task is triggered (either from a peripheral, through software, or +//! through the MIFRC register). The bit gets cleared when the CLA starts to +//! execute the flagged task. +//! +//! \return \b True if the queried task has been triggered but pending +//! execution. +// +//***************************************************************************** +static inline bool +CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIFR) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the interrupt flag register (MIFR) +//! +//! \return the value of Interrupt Flag Register (MIFR) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllPendingTaskFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Flag Register (MIFR) since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIFR); + + // + // Return the Interrupt Flag Register value + // + return(status); +} + +//***************************************************************************** +// +//! Get status of Task n Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the overflow flag register +//! corresponds to a CLA task, This bit is set when an interrupt overflow event +//! has occurred for the specific task. +//! +//! \return True if any of task interrupt overflow has occurred. +// +//***************************************************************************** +static inline bool +CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIOVF) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the Interrupt Overflow Flag Register +//! +//! \return the value of Interrupt Overflow Flag Register(MIOVF) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskOverflowFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return Interrupt Overflow Flag Register(MIOVF) since that is what + // was requested. + // + status = HWREGH(base + CLA_O_MIOVF); + + // + // Return the Interrupt Overflow Flag Register + // + return(status); +} + +//***************************************************************************** +// +//! Clear the task interrupt flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to clear all flags. +//! +//! This function is used to manually clear bits in the interrupt +//! flag (MIFR) register +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + //Modify protected register + // + EALLOW; + + // + // Clear the task interrupt flag + // + HWREGH(base + CLA_O_MICLR) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Force a CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be forced +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to force all tasks. +//! +//! This function forces a task through software. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Force the task interrupt. + // + HWREGH(base + CLA_O_MIFRC) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enable CLA task(s) +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to enable all tasks +//! +//! This function allows an incoming interrupt or main CPU software to +//! start the corresponding CLA task. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable CLA task + // + HWREGH(base + CLA_O_MIER) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disable CLA task interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to disable all tasks +//! +//! This function disables CLA task interrupt by setting the MIER register bit +//! to 0, while the corresponding task is executing this will have no effect +//! on the task. The task will continue to run until it hits the MSTOP +//! instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Disable CLA task interrupt + // + HWREGH(base + CLA_O_MIER) &= ~taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Get the value of a task run status +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the Interrupt Run Status +//! Register which indicates whether the task is currently executing +//! +//! \return True if the task is executing. +// +//***************************************************************************** +static inline bool +CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIRUN) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get the value of all task run status +//! +//! \param base is the base address of the CLA controller. +//! +//! This function indicates which task is currently executing. +//! +//! \return the value of Interrupt Run Status Register (MIRUN) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskRunStatus(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Run Status Register since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIRUN); + + // + // Return the Interrupt Run Status Register (MIRUN) + // + return(status); +} +#endif // #ifdef __TMS320C28XX__ + +// +// These functions are accessible only from the CLA (Type - 1/2) +// +#if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) +//***************************************************************************** +// +//! Enable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be enabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to enable software interrupts of all tasks +//! +//! This function enables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1SOFTINTEN register. By setting a task's SOFTINT bit, you disable its +//! ability to generate an end-of-task interrupt +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) |= taskFlags; + + __medis(); +} + +//***************************************************************************** +// +//! Disable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be disabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to disable software interrupts of all +//! tasks +//! +//! This function disables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 0 to the task's bit in the +//! CLA1SOFTINTEN register. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Disabling a given task's software interrupt ability allows that +//! task to generate an End-of-Task interrupt to the main CPU. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) &= ~taskFlags; + + __medis(); +} +//***************************************************************************** +// +//! Force a particular Task's Software Interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the task's whose software +//! interrupts are to be forced, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to force software interrupts for all tasks +//! +//! This function forces the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1INTFRC register. +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! -# This function will set the INTFRC bit for a task, but does not check +//! that its SOFTINT bit is set. It falls to the user to ensure that software +//! interrupt for a given task is enabled before it can be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Force Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTFRC) |= taskFlags; + + __medis(); +} + +#endif // #if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) + +// +// These functions can only be called from the C28x +// +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! Configures CLA task triggers. +//! +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. +//! \param trigger is the trigger source to be assigned to the selected task. +//! +//! This function configures the trigger source of a CLA task. The +//! \e taskNumber parameter indicates which task is being configured, and the +//! \e trigger parameter is the interrupt source from a specific peripheral +//! interrupt (or software) that will trigger the task. +//! +//! \return None. +// +//***************************************************************************** +extern void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger); + +#endif //#ifdef __TMS320C28XX__ +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLA_H diff --git a/gpio_bitfield_cpu1/device/driverlib/clb.c b/gpio_bitfield_cpu1/device/driverlib/clb.c new file mode 100644 index 0000000..2e79cb4 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/clb.c @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: clb.c +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "clb.h" + +//***************************************************************************** +// +// CLB_configCounterLoadMatch +// +//***************************************************************************** +void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, uint32_t match2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + switch(counterID) + { + case CLB_CTR0: + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2); + break; + + case CLB_CTR1: + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2); + break; + + case CLB_CTR2: + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2); + break; + + default: + // + // Invalid counterID value + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// CLB_clearFIFOs +// +//***************************************************************************** +void CLB_clearFIFOs(uint32_t base) +{ + uint16_t i; + + ASSERT(CLB_isBaseValid(base)); + + for(i = 0U; i < CLB_FIFO_SIZE; i++) + { + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U; + } + + HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U; +} + +//***************************************************************************** +// +// CLB_writeFIFOs +// +//***************************************************************************** +void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Clear the FIFO and pointer + // + CLB_clearFIFOs(base); + + // + // Write data into the FIFO. + // + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0U)) = pullData[0U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1U)) = pullData[1U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2U)) = pullData[2U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3U)) = pullData[3U]; +} + +//***************************************************************************** +// +// CLB_readFIFOs +// +//***************************************************************************** +void CLB_readFIFOs(uint32_t base , uint32_t pushData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Read data from the FIFO. + // + pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0U)) ; + pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1U)) ; + pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2U)) ; + pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3U)) ; +} + + diff --git a/gpio_bitfield_cpu1/device/driverlib/clb.h b/gpio_bitfield_cpu1/device/driverlib/clb.h new file mode 100644 index 0000000..37cb68f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/clb.h @@ -0,0 +1,1290 @@ +//########################################################################### +// +// FILE: clb.h +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLB_H +#define CLB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup clb_api CLB +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clb.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Address offsets from LOGICCFG to LOGICCTL and DATAEXCH register memory maps +// +//***************************************************************************** +#define CLB_LOGICCTL 0x0100U +#define CLB_DATAEXCH 0x0200U + +//***************************************************************************** +// +// Address offsets for CLB-internal memory space +// +//***************************************************************************** +#define CLB_ADDR_COUNTER_0_LOAD 0x0U +#define CLB_ADDR_COUNTER_1_LOAD 0x1U +#define CLB_ADDR_COUNTER_2_LOAD 0x2U + +#define CLB_ADDR_COUNTER_0_MATCH1 0x4U +#define CLB_ADDR_COUNTER_1_MATCH1 0x5U +#define CLB_ADDR_COUNTER_2_MATCH1 0x6U + +#define CLB_ADDR_COUNTER_0_MATCH2 0x8U +#define CLB_ADDR_COUNTER_1_MATCH2 0x9U +#define CLB_ADDR_COUNTER_2_MATCH2 0xAU + +#define CLB_ADDR_HLC_R0 0xCU +#define CLB_ADDR_HLC_R1 0xDU +#define CLB_ADDR_HLC_R2 0xEU +#define CLB_ADDR_HLC_R3 0xFU + +#define CLB_ADDR_HLC_BASE 0x20U +#define CLB_NUM_HLC_INSTR 31U + +//***************************************************************************** +// +// PUSH/PULL FIFO size (32-bit registers) +// +//***************************************************************************** +#define CLB_FIFO_SIZE 4U + +//***************************************************************************** +// +// Key to enable writes to the CLB registers +// +//***************************************************************************** +#define CLB_LOCK_KEY 0x5A5AU + +//***************************************************************************** +// +// Shift and masks needed by the API for Input selection +// +//***************************************************************************** +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M 0x20U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S 28U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM (uint32_t)1U + +//***************************************************************************** +// +//! Values that can be passed to control the CLB output enable signal. It can +//! be passed to CLB_setOutputMask() as the \e outputMask parameter. +// +//***************************************************************************** +#define CLB_OUTPUT_00 0x00000001U //!< Mask for CLB OUTPUT ENABLE/DISABLE 0 +#define CLB_OUTPUT_01 0x00000002U //!< Mask for CLB OUTPUT ENABLE/DISABLE 1 +#define CLB_OUTPUT_02 0x00000004U //!< Mask for CLB OUTPUT ENABLE/DISABLE 2 +#define CLB_OUTPUT_03 0x00000008U //!< Mask for CLB OUTPUT ENABLE/DISABLE 3 +#define CLB_OUTPUT_04 0x00000010U //!< Mask for CLB OUTPUT ENABLE/DISABLE 4 +#define CLB_OUTPUT_05 0x00000020U //!< Mask for CLB OUTPUT ENABLE/DISABLE 5 +#define CLB_OUTPUT_06 0x00000040U //!< Mask for CLB OUTPUT ENABLE/DISABLE 6 +#define CLB_OUTPUT_07 0x00000080U //!< Mask for CLB OUTPUT ENABLE/DISABLE 7 +#define CLB_OUTPUT_08 0x00000100U //!< Mask for CLB OUTPUT ENABLE/DISABLE 8 +#define CLB_OUTPUT_09 0x00000200U //!< Mask for CLB OUTPUT ENABLE/DISABLE 9 +#define CLB_OUTPUT_10 0x00000400U //!< Mask for CLB OUTPUT ENABLE/DISABLE 10 +#define CLB_OUTPUT_11 0x00000800U //!< Mask for CLB OUTPUT ENABLE/DISABLE 11 +#define CLB_OUTPUT_12 0x00001000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 12 +#define CLB_OUTPUT_13 0x00002000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 13 +#define CLB_OUTPUT_14 0x00004000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 14 +#define CLB_OUTPUT_15 0x00008000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 15 +#define CLB_OUTPUT_16 0x00010000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 16 +#define CLB_OUTPUT_17 0x00020000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 17 +#define CLB_OUTPUT_18 0x00040000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 18 +#define CLB_OUTPUT_19 0x00080000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 19 +#define CLB_OUTPUT_20 0x00100000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 20 +#define CLB_OUTPUT_21 0x00200000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 21 +#define CLB_OUTPUT_22 0x00400000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 22 +#define CLB_OUTPUT_23 0x00800000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 23 +#define CLB_OUTPUT_24 0x01000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 24 +#define CLB_OUTPUT_25 0x02000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 25 +#define CLB_OUTPUT_26 0x04000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 26 +#define CLB_OUTPUT_27 0x08000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 27 +#define CLB_OUTPUT_28 0x10000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 28 +#define CLB_OUTPUT_29 0x20000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 29 +#define CLB_OUTPUT_30 0x40000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 30 +#define CLB_OUTPUT_31 0x80000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 31 + +//***************************************************************************** +// +//! Values that can be passed to select CLB input signal +// +//***************************************************************************** +typedef enum +{ + CLB_IN0 = 0, //!< Input 0 + CLB_IN1 = 1, //!< Input 1 + CLB_IN2 = 2, //!< Input 2 + CLB_IN3 = 3, //!< Input 3 + CLB_IN4 = 4, //!< Input 4 + CLB_IN5 = 5, //!< Input 5 + CLB_IN6 = 6, //!< Input 6 + CLB_IN7 = 7 //!< Input 7 +} CLB_Inputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB output signal. It can be passed to +//! CLB_configOutputLUT() as the \e outID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_OUT0 = 0, //!< Output 0 + CLB_OUT1 = 1, //!< Output 1 + CLB_OUT2 = 2, //!< Output 2 + CLB_OUT3 = 3, //!< Output 3 + CLB_OUT4 = 4, //!< Output 4 + CLB_OUT5 = 5, //!< Output 5 + CLB_OUT6 = 6, //!< Output 6 + CLB_OUT7 = 7 //!< Output 7 +} CLB_Outputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB counter. It can be passed to +//! CLB_configCounterLoadMatch() as the \e counterID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_CTR0 = 0, //!< Counter 0 + CLB_CTR1 = 1, //!< Counter 1 + CLB_CTR2 = 2 //!< Counter 2 +} CLB_Counters; + +//***************************************************************************** +// +//! Values that can be passed to CLB_getRegister() as the \e registerID +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_REG_HLC_R0 = CLB_O_DBG_R0, //!< HLC R0 register + CLB_REG_HLC_R1 = CLB_O_DBG_R1, //!< HLC R1 register + CLB_REG_HLC_R2 = CLB_O_DBG_R2, //!< HLC R2 register + CLB_REG_HLC_R3 = CLB_O_DBG_R3, //!< HLC R3 register + CLB_REG_CTR_C0 = CLB_O_DBG_C0, //!< Counter 0 register + CLB_REG_CTR_C1 = CLB_O_DBG_C1, //!< Counter 1 register + CLB_REG_CTR_C2 = CLB_O_DBG_C2 //!< Counter 2 register +} CLB_Register; + +//***************************************************************************** +// +//! Values that can be passed to CLB_selectInputFilter() as the \e filterType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_FILTER_NONE = 0, //!< No filtering + CLB_FILTER_RISING_EDGE = 1, //!< Rising edge detect + CLB_FILTER_FALLING_EDGE = 2, //!< Falling edge detect + CLB_FILTER_ANY_EDGE = 3 //!< Any edge detect +} CLB_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGPInputMux() as the \e gpMuxCfg +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GP_IN_MUX_EXTERNAL = 0, //!< Use external input path + CLB_GP_IN_MUX_GP_REG = 1 //!< Use CLB_GP_REG bit value as input +} CLB_GPInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configLocalInputMux() as the +//! \e localMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_LOCAL_IN_MUX_GLOBAL_IN = 0, //!< Global input mux selection + CLB_LOCAL_IN_MUX_EPWM_DCAEVT1 = 1, //!< EPWMx DCAEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCAEVT2 = 2, //!< EPWMx DCAEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT1 = 3, //!< EPWMx DCBEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT2 = 4, //!< EPWMx DCBEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCAH = 5, //!< EPWMx DCAH + CLB_LOCAL_IN_MUX_EPWM_DCAL = 6, //!< EPWMx DCAL + CLB_LOCAL_IN_MUX_EPWM_DCBH = 7, //!< EPWMx DCBH + CLB_LOCAL_IN_MUX_EPWM_DCBL = 8, //!< EPWMx DCBL + CLB_LOCAL_IN_MUX_EPWM_OST = 9, //!< EPWMx OST + CLB_LOCAL_IN_MUX_EPWM_CBC = 10, //!< EPWMx CBC + CLB_LOCAL_IN_MUX_ECAP_ECAPIN = 11, //!< ECAPx ECAPIN + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT = 12, //!< ECAPx ECAP_OUT + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN = 13, //!< ECAPx ECAP_OUT_EN + CLB_LOCAL_IN_MUX_ECAP_CEVT1 = 14, //!< ECAPx CEVT1 + CLB_LOCAL_IN_MUX_ECAP_CEVT2 = 15, //!< ECAPx CEVT2 + CLB_LOCAL_IN_MUX_ECAP_CEVT3 = 16, //!< ECAPx CEVT3 + CLB_LOCAL_IN_MUX_ECAP_CEVT4 = 17, //!< ECAPx CEVT4 + CLB_LOCAL_IN_MUX_EQEP_EQEPA = 18, //!< EQEPx EQEPA + CLB_LOCAL_IN_MUX_EQEP_EQEPB = 19, //!< EQEPx EQEPB + CLB_LOCAL_IN_MUX_EQEP_EQEPI = 20, //!< EQEPx EQEPI + CLB_LOCAL_IN_MUX_EQEP_EQEPS = 21, //!< EQEPx EQEPS + CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC = 22, //!< CPU1.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC = 23, //!< CPU2.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU1_HALT = 24, //!< CPU1.HALT + CLB_LOCAL_IN_MUX_CPU2_HALT = 25, //!< CPU2.HALT +} CLB_LocalInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGlobalInputMux() as the +//! \e globalMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GLOBAL_IN_MUX_EPWM1A = 0, //!< EPWM1A + CLB_GLOBAL_IN_MUX_EPWM1A_OE = 1, //!< EPWM1A trip output + CLB_GLOBAL_IN_MUX_EPWM1B = 2, //!< EPWM1B + CLB_GLOBAL_IN_MUX_EPWM1B_OE = 3, //!< EPWM1B trip output + CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO = 4, //!< EPWM1 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD = 5, //!< EPWM1 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR = 6, //!< EPWM1 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM1_TBCLK = 7, //!< EPWM1 TBCLK + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA = 8, //!< EPWM1 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB = 9, //!< EPWM1 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC = 10, //!< EPWM1 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD = 11, //!< EPWM1 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM1A_AQ = 12, //!< EPWM1A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_AQ = 13, //!< EPWM1B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1A_DB = 14, //!< EPWM1A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_DB = 15, //!< EPWM1B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM2A = 16, //!< EPWM2A + CLB_GLOBAL_IN_MUX_EPWM2A_OE = 17, //!< EPWM2A trip output + CLB_GLOBAL_IN_MUX_EPWM2B = 18, //!< EPWM2B + CLB_GLOBAL_IN_MUX_EPWM2B_OE = 19, //!< EPWM2B trip output + CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO = 20, //!< EPWM2 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD = 21, //!< EPWM2 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR = 22, //!< EPWM2 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM2_TBCLK = 23, //!< EPWM2 TBCLK + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA = 24, //!< EPWM2 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB = 25, //!< EPWM2 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC = 26, //!< EPWM2 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD = 27, //!< EPWM2 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM2A_AQ = 28, //!< EPWM2A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_AQ = 29, //!< EPWM2B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2A_DB = 30, //!< EPWM2A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_DB = 31, //!< EPWM2B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM3A = 32, //!< EPWM3A + CLB_GLOBAL_IN_MUX_EPWM3A_OE = 33, //!< EPWM3A trip output + CLB_GLOBAL_IN_MUX_EPWM3B = 34, //!< EPWM3B + CLB_GLOBAL_IN_MUX_EPWM3B_OE = 35, //!< EPWM3B trip output + CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO = 36, //!< EPWM3 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD = 37, //!< EPWM3 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR = 38, //!< EPWM3 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM3_TBCLK = 39, //!< EPWM3 TBCLK + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA = 40, //!< EPWM3 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB = 41, //!< EPWM3 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC = 42, //!< EPWM3 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD = 43, //!< EPWM3 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM3A_AQ = 44, //!< EPWM3A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_AQ = 45, //!< EPWM3B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3A_DB = 46, //!< EPWM3A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_DB = 47, //!< EPWM3B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM4A = 48, //!< EPWM4A + CLB_GLOBAL_IN_MUX_EPWM4A_OE = 49, //!< EPWM4A trip output + CLB_GLOBAL_IN_MUX_EPWM4B = 50, //!< EPWM4B + CLB_GLOBAL_IN_MUX_EPWM4B_OE = 51, //!< EPWM4B trip output + CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO = 52, //!< EPWM4 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD = 53, //!< EPWM4 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR = 54, //!< EPWM4 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM4_TBCLK = 55, //!< EPWM4 TBCLK + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA = 56, //!< EPWM4 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB = 57, //!< EPWM4 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC = 58, //!< EPWM4 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD = 59, //!< EPWM4 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM4A_AQ = 60, //!< EPWM4A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_AQ = 61, //!< EPWM4B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4A_DB = 62, //!< EPWM4A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_DB = 63, //!< EPWM4B DB submodule output + + CLB_GLOBAL_IN_MUX_CLB_AUXSIG0 = 64, //!< CLB X-BAR AUXSIG0 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG1 = 65, //!< CLB X-BAR AUXSIG1 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG2 = 66, //!< CLB X-BAR AUXSIG2 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG3 = 67, //!< CLB X-BAR AUXSIG3 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG4 = 68, //!< CLB X-BAR AUXSIG4 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG5 = 69, //!< CLB X-BAR AUXSIG5 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG6 = 70, //!< CLB X-BAR AUXSIG6 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG7 = 71, //!< CLB X-BAR AUXSIG7 + +} CLB_GlobalInputMux; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +// +//! +//! Checks the CLB base address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CLB_isBaseValid(uint32_t base) +{ + return( + (base == CLB1_BASE) || + (base == CLB2_BASE) || + (base == CLB3_BASE) || + (base == CLB4_BASE) + ); +} + +//***************************************************************************** +// +//! +//! Checks the CLB internal memory address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the address is valid and \b false otherwise. +// +//***************************************************************************** +static inline bool CLB_isAddressValid(uint32_t address) +{ + return(address <= (CLB_ADDR_HLC_BASE + CLB_NUM_HLC_INSTR)); +} +#endif + +//***************************************************************************** +// +//! Set global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Clear global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function disables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) &= ~CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enable CLB lock. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the lock bit of the lock register. The lock can only +//! be set once and can only be cleared by a device reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableLock(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Setting the lock bit requires key 0x5A5A to be written at the same time + // + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOCK) = + (uint32_t)CLB_LOCK_LOCK | ((uint32_t)CLB_LOCK_KEY << CLB_LOCK_KEY_S); + EDIS; +} + +//***************************************************************************** +// +//! Write value to address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param address is the address of CLB internal memory. +//! \param value is the value to write to specified address. +//! +//! This function writes the specified value to CLB internal memory. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_writeInterface(uint32_t base, uint32_t address, + uint32_t value) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(CLB_isAddressValid(address)); + + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_ADDR) = address; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_DATA) = value; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_LOAD_EN; + EDIS; +} + +//***************************************************************************** +// +//! Select input filter type. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param filterType is the selected type of filter applied to the input. +//! +//! This function configures the filter selection for the specified input. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e filterType parameter can have one enumeration value from +//! CLB_FilterType. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectInputFilter(uint32_t base, CLB_Inputs inID, + CLB_FilterType filterType) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 2-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID << 1; + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) & + ~(CLB_INPUT_FILTER_FIN0_M << shiftVal)) | + ((uint16_t)filterType << shiftVal); +} + +//***************************************************************************** +// +//! Enables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function enables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) |= + (1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Disables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function disables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) &= + ~(1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Configures the general purpose input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param gpMuxCfg is the mux selection for the general purpose input mux. +//! +//! This function configures the general purpose input mux. The \e gpMuxCfg +//! parameter can select either the use of an external input signal +//! (\b CLB_GP_IN_MUX_EXTERNAL) or the use of the corresponding CLB_GP_REG bit +//! as an input (\b CLB_GP_IN_MUX_GP_REG). +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \sa CLB_setGPREG() to write to the CLB_GP_REG. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGPInputMux(uint32_t base, CLB_Inputs inID, + CLB_GPInputMux gpMuxCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) & + ~(CLB_IN_MUX_SEL_0_SEL_GP_IN_0 << (uint16_t)inID)) | + ((uint16_t)gpMuxCfg << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Sets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param gpRegVal is the value to be written to CLB_GP_REG. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setGPREG(uint32_t base, uint32_t gpRegVal) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG) = gpRegVal; +} + +//***************************************************************************** +// +//! Gets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return CLB_GP_REG value. +// +//***************************************************************************** +static inline uint32_t CLB_getGPREG(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG)); +} + +//***************************************************************************** +// +//! Configures the local input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param localMuxCfg is the mux selection for the local input mux. +//! +//! This function configures the local input mux for the specified input +//! signal. +//! +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e localMuxCfg parameter can have one enumeration value from +//! CLB_LocalInputMux. +//! +//! \note The local input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLocalInputMux(uint32_t base, CLB_Inputs inID, + CLB_LocalInputMux localMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each local input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } + else + { + // + // Calculating shift amount for inputs > input3 + // + shiftVal -= 4U * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Configures the global input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param globalMuxCfg is the mux selection for the global input mux. +//! +//! This function configures the global input mux for the specified input +//! signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e globalMuxCfg parameter can have one enumeration value from +//! CLB_GlobalInputMux. +//! +//! \note The global input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGlobalInputMux(uint32_t base, CLB_Inputs inID, + CLB_GlobalInputMux globalMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } + else + { + shiftVal -= 4U * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Controls the output enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outputMask is a mask of the outputs to be enabled. +//! \param enable is a switch to decide if the CLB outputs need to be enabled +//! or not. +//! +//! This function is used to enable and disable CLB outputs by writing a mask +//! to CLB_OUT_EN. Each bit corresponds to a CLB output. When a bit is 1, the +//! corresponding output is enabled; when a bit is 0, the output is disabled. +//! +//! The \e outputMask parameter takes a logical OR of any of the CLB_OUTPUT_0x +//! values that correspond to the CLB OUTPUT ENABLE for the respective outputs. +//! The \e enable parameter can have one of the values from: +//! false: Disable the respective CLB outputs +//! true: Enable the respective CLB outputs +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setOutputMask(uint32_t base, uint32_t outputMask , + bool enable) +{ + ASSERT(CLB_isBaseValid(base)); + + if(enable == true) + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) |= outputMask; + } + else + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) &= ~outputMask; + } +} + +//***************************************************************************** +// +//! Reads the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the value in the interrupt tag register which is a 6-bit +//! constant set by the HLC. +// +//***************************************************************************** +static inline uint16_t CLB_getInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG)); +} + +//***************************************************************************** +// +//! Clears the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the interrupt tag register, setting it to 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_clearInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG) = 0U; +} + +//***************************************************************************** +// +//! Selects LUT4 inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4In0 is the value for LUT4 input signal 0. Generated by tool as +//! \b TILEx_CFG_LUT4_IN0. +//! \param lut4In1 is the value for LUT4 input signal 1. Generated by tool as +//! \b TILEx_CFG_LUT4_IN1. +//! \param lut4In2 is the value for LUT4 input signal 2. Generated by tool as +//! \b TILEx_CFG_LUT4_IN2. +//! \param lut4In3 is the value for LUT4 input signal 3. Generated by tool as +//! \b TILEx_CFG_LUT4_IN3. +//! +//! This function configures the LUT4 block's input signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectLUT4Inputs(uint32_t base, uint32_t lut4In0, + uint32_t lut4In1, uint32_t lut4In2, + uint32_t lut4In3) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_IN0) = lut4In0; + HWREG(base + CLB_O_LUT4_IN1) = lut4In1; + HWREG(base + CLB_O_LUT4_IN2) = lut4In2; + HWREG(base + CLB_O_LUT4_IN3) = lut4In3; + EDIS; +} + +//***************************************************************************** +// +//! Configures LUT4 functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4Fn10 is the equation value for LUT4 blocks 0 and 1. Generated by +//! tool as \b TILEx_CFG_LUT4_FN10. +//! \param lut4Fn2 is the equation value for LUT4 block2. Generated by tool as +//! \b TILEx_CFG_LUT4_FN2. +//! +//! This function configures the LUT4 block's equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLUT4Function(uint32_t base, uint32_t lut4Fn10, + uint32_t lut4Fn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_FN1_0) = lut4Fn10; + HWREG(base + CLB_O_LUT4_FN2) = lut4Fn2; + EDIS; +} + +//***************************************************************************** +// +//! Selects FSM inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param external0 is the value for FSM external 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN0. +//! \param external1 is the value for FSM external 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN1. +//! \param extra0 is the value for FSM extra 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN0. +//! \param extra1 is the value for FSM extra 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN1. +//! +//! This function configures the FSM block's external inputs and extra external +//! inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectFSMInputs(uint32_t base, uint32_t external0, + uint32_t external1, uint32_t extra0, + uint32_t extra1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_EXTERNAL_IN0) = external0; + HWREG(base + CLB_O_FSM_EXTERNAL_IN1) = external1; + HWREG(base + CLB_O_FSM_EXTRA_IN0) = extra0; + HWREG(base + CLB_O_FSM_EXTRA_IN1) = extra1; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM LUT function. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param fsmLutFn10 is the value for FSM 0 & FSM 1 LUT function. Generated +//! by tool as \b TILEx_CFG_FSM_LUT_FN10. +//! \param fsmLutFn2 is the value for FSM 2 LUT function. Generated by tool as +//! \b TILEx_CFG_FSM_LUT_FN2. +//! +//! This function configures the FSM block's LUT equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMLUTFunction(uint32_t base, uint32_t fsmLutFn10, + uint32_t fsmLutFn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_LUT_FN1_0) = fsmLutFn10; + HWREG(base + CLB_O_FSM_LUT_FN2) = fsmLutFn2; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM next state. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param nextState0 is the value for FSM 0's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_0. +//! \param nextState1 is the value for FSM 1's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_1. +//! \param nextState2 is the value for FSM 2's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_2. +//! +//! This function configures the FSM's next state equation. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMNextState(uint32_t base, uint32_t nextState0, + uint32_t nextState1, + uint32_t nextState2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_NEXT_STATE_0) = nextState0; + HWREG(base + CLB_O_FSM_NEXT_STATE_1) = nextState1; + HWREG(base + CLB_O_FSM_NEXT_STATE_2) = nextState2; + EDIS; +} + +//***************************************************************************** +// +//! Selects Counter inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param reset is the value for counter's reset inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_RESET. +//! \param event is the value for counter's event inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_EVENT. +//! \param mode0 is the value for counter's mode 0 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_0. +//! \param mode1 is the value for counter's mode 1 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_1. +//! +//! This function selects the input signals to the counter block. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectCounterInputs(uint32_t base, uint32_t reset, + uint32_t event, uint32_t mode0, + uint32_t mode1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_COUNT_RESET) = reset; + HWREG(base + CLB_O_COUNT_EVENT) = event; + HWREG(base + CLB_O_COUNT_MODE_0) = mode0; + HWREG(base + CLB_O_COUNT_MODE_1) = mode1; + EDIS; +} + +//***************************************************************************** +// +//! Configures Counter and FSM modes. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param miscCtrl is the value to represent counter and FSM modes. +//! Generated by tool as \b TILEx_CFG_MISC_CONTROL. +//! +//! This function configures the counter mode, particularly add/shift, load +//! modes. The function also configures whether the FSM should use state inputs +//! or an extra external input. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configMiscCtrlModes(uint32_t base, uint32_t miscCtrl) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_MISC_CONTROL) = miscCtrl; + EDIS; +} + +//***************************************************************************** +// +//! Configures Output LUT functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outID is the specified CLB tile output signal. +//! \param outputCfg is the value for the output LUT signal function and input +//! signal selections. Generated by tool as \b TILEx_CFG_OUTLUT_n where +//! n is the output number. +//! +//! This function configures the input signals and equations of the output LUT +//! corresponding to the /e outID parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configOutputLUT(uint32_t base, CLB_Outputs outID, + uint32_t outputCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_OUTPUT_LUT_0 + (sizeof(uint32_t) * outID)) = outputCfg; + EDIS; +} + +//***************************************************************************** +// +//! Configures HLC event selection. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param eventSel is the value for HLC event selection. Generated by tool as +//! \b TILEx_HLC_EVENT_SEL. +//! +//! This function configures the event selection for the High Level Controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configHLCEventSelect(uint32_t base, uint32_t eventSel) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_HLC_EVENT_SEL) = eventSel; + EDIS; +} + +//***************************************************************************** +// +//! Program HLC instruction. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param instructionNum is the index into the HLC instruction memory. For +//! example, a value of 0 corresponds to instruction 0 of event 0, +//! a value of 1 corresponds to instruction 1 of event 0, and so on up +//! to a value of 31 which corresponds to instruction 7 of event 3. +//! \param instruction is the instruction to be programmed. Generated by tool +//! as \b TILEx_HLCINSTR_n where n is the instruction number. +//! +//! This function configures the CLB internal memory corresponding to the +//! specified HLC instruction number with the given instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_programHLCInstruction(uint32_t base, + uint32_t instructionNum, + uint32_t instruction) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(instructionNum < 32U); + + CLB_writeInterface(base, CLB_ADDR_HLC_BASE + instructionNum, instruction); +} + +//***************************************************************************** +// +//! Set HLC registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param r0Init is the value to write to HLC register R0. Generated by tool +//! as \b TILEx_HLC_R0_INIT. +//! \param r1Init is the value to write to HLC register R1. Generated by tool +//! as \b TILEx_HLC_R1_INIT. +//! \param r2Init is the value to write to HLC register R2. Generated by tool +//! as \b TILEx_HLC_R2_INIT. +//! \param r3Init is the value to write to HLC register R3. Generated by tool +//! as \b TILEx_HLC_R3_INIT. +//! +//! This function configures the CLB internal memory corresponding to the HLC +//! registers R0-R3 with the specified values. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setHLCRegisters(uint32_t base, uint32_t r0Init, + uint32_t r1Init, uint32_t r2Init, + uint32_t r3Init) +{ + ASSERT(CLB_isBaseValid(base)); + + CLB_writeInterface(base, CLB_ADDR_HLC_R0, r0Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R1, r1Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R2, r2Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R3, r3Init); +} + +//***************************************************************************** +// +//! Get HLC or counter register values. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param registerID is the internal register from which to read. Can be +//! either an HLC register (\b CLB_REG_HLC_Rn) or a counter value +//! (\b CLB_REG_CTR_Cn). +//! +//! \return Returns the value in the specified HLC register or counter. +// +//***************************************************************************** +static inline uint32_t CLB_getRegister(uint32_t base, CLB_Register registerID) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + (uint32_t)registerID)); +} + +//***************************************************************************** +// +//! Get output status. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the output status of various components within the CLB tile +//! such as a counter match or LUT output. Use the \b CLB_DBG_OUT_* +//! masks from hw_clb.h to decode the bits. +// +//***************************************************************************** +static inline uint32_t CLB_getOutputStatus(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_DBG_OUT)); +} + +//***************************************************************************** +// +//! Configures Counter load and match. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param counterID is the specified counter unit. +//! \param load is the value for counter's load mode. Generated by tool as +//! \b TILEx_COUNTER_n_LOAD_VAL where n is the counter number. +//! \param match1 is the value for counter's match 1. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH1_VAL where n is the counter number. +//! \param match2 is the value for counter's match 2. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH2_VAL where n is the counter number. +//! +//! This function configures the CLB internal memory corresponding to the +//! counter block's load and match values. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, + uint32_t match2); + +//***************************************************************************** +// +//! Clear FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the PUSH/PULL FIFOs as well as its pointers. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_clearFIFOs(uint32_t base); + +//***************************************************************************** +// +//! Configure the FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pullData[] is a pointer to an array of bytes which needs to be +//! written into the FIFO. The 0th FIFO data is in the 0th index. +//! +//! This function writes to the PULL FIFO. This also clears the FIFOs and +//! its pointer using the CLB_clearFIFOs() API prior to writing to +//! the FIFO. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_writeFIFOs(uint32_t base, const uint32_t pullData[]); + +//***************************************************************************** +// +//! Read FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pushData[] is a pointer to an array of bytes which needs to be +//! read from the FIFO. +//! +//! This function reads from the PUSH FIFO. The 0th FIFO data would be in +//! the 0th index. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_readFIFOs(uint32_t base , uint32_t pushData[]); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLB_H diff --git a/gpio_bitfield_cpu1/device/driverlib/cmpss.c b/gpio_bitfield_cpu1/device/driverlib/cmpss.c new file mode 100644 index 0000000..88f9e5f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cmpss.c @@ -0,0 +1,223 @@ +//########################################################################### +// +// FILE: cmpss.c +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cmpss.h" + +//***************************************************************************** +// +// CMPSS_configFilterHigh +// +//***************************************************************************** +void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPHFILCTL) & + ~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the high comparator. + // + HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configFilterLow +// +//***************************************************************************** +void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPLFILCTL) & + ~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the low comparator. + // + HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configLatchOnPWMSYNC +// +//***************************************************************************** +void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // If the highEnable is true, set the bit that will enable PWMSYNC to reset + // the high comparator digital filter latch. If not, clear the bit. + // + EALLOW; + + if(highEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + } + + // + // If the lowEnable is true, set the bit that will enable PWMSYNC to reset + // the low comparator digital filter latch. If not, clear the bit. + // + if(lowEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + } + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configRamp +// +//***************************************************************************** +void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M); + ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 12U)); + + EALLOW; + + // + // Write the ramp generator source to the register + // + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S); + + // + // Set or clear the bit that determines from where the max ramp value + // should be loaded. + // + if(useRampValShdw) + { + HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL; + } + else + { + HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL; + } + + EDIS; + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal; + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal; + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal; +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/cmpss.h b/gpio_bitfield_cpu1/device/driverlib/cmpss.h new file mode 100644 index 0000000..25625c3 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cmpss.h @@ -0,0 +1,1325 @@ +//########################################################################### +// +// FILE: cmpss.h +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CMPSS_H +#define CMPSS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cmpss_api CMPSS +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_cmpss.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CMPSS_HICMP_CTL_M (CMPSS_COMPCTL_COMPHSOURCE | \ + CMPSS_COMPCTL_COMPHINV | \ + CMPSS_COMPCTL_ASYNCHEN) + +#define CMPSS_LOCMP_CTL_M (CMPSS_COMPCTL_COMPLSOURCE | \ + CMPSS_COMPCTL_COMPLINV | \ + CMPSS_COMPCTL_ASYNCLEN) + +#ifndef DOXYGEN_PDF_IGNORE + + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configLowComparator() and +// CMPSS_configHighComparator() as the config parameter. +// +//***************************************************************************** +// +// Comparator negative input source +// +//! Input driven by internal DAC +#define CMPSS_INSRC_DAC 0x0000U +//! Input driven by external pin +#define CMPSS_INSRC_PIN 0x0001U + +// +// Extra options +// +//! Comparator output is inverted +#define CMPSS_INV_INVERTED 0x0002U +//! Asynch comparator output feeds into OR with latched digital filter output +#define CMPSS_OR_ASYNC_OUT_W_FILT 0x0040U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configOutputsLow() and +// CMPSS_configOutputsHigh() as the config parameter. +// +//***************************************************************************** +// +// Signal driving CTRIPOUT +// +//! Asynchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_SYNC_COMP 0x0010U +//! Filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_FILTER 0x0020U +//! Latched filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_LATCH 0x0030U + +// +// Signal driving CTRIP +// +//! Asynchronous comparator output drives CTRIP +#define CMPSS_TRIP_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIP +#define CMPSS_TRIP_SYNC_COMP 0x0004U +//! Filter output drives CTRIP +#define CMPSS_TRIP_FILTER 0x0008U +//! Latched filter output drives CTRIP +#define CMPSS_TRIP_LATCH 0x000CU + +//***************************************************************************** +// +// Values that can be returned by CMPSS_getStatus(). +// +//***************************************************************************** +//! High digital filter output +#define CMPSS_STS_HI_FILTOUT 0x0001U +//! Latched value of high digital filter output +#define CMPSS_STS_HI_LATCHFILTOUT 0x0002U +//! Low digital filter output +#define CMPSS_STS_LO_FILTOUT 0x0100U +//! Latched value of low digital filter output +#define CMPSS_STS_LO_LATCHFILTOUT 0x0200U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configDAC() the config parameter. +// +//***************************************************************************** +// +// When is DAC value loaded from shadow register +// +//! DAC value updated from SYSCLK +#define CMPSS_DACVAL_SYSCLK 0x0000U +//! DAC value updated from PWMSYNC +#define CMPSS_DACVAL_PWMSYNC 0x0080U + +// +// DAC reference voltage +// +//! VDDA is the voltage reference +#define CMPSS_DACREF_VDDA 0x0000U +//! VDAC is the voltage reference +#define CMPSS_DACREF_VDAC 0x0020U + +// +// DAC value source +// +//! DAC value updated from shadow register +#define CMPSS_DACSRC_SHDW 0x0000U +//! DAC value is updated from the ramp register +#define CMPSS_DACSRC_RAMP 0x0001U +#endif + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configRamp() +// as the pwmSyncSrc parameter. +// +//***************************************************************************** +#define CMPSS_PWMSYNC1 1U //!< PWMSYNC1 +#define CMPSS_PWMSYNC2 2U //!< PWMSYNC2 +#define CMPSS_PWMSYNC3 3U //!< PWMSYNC3 +#define CMPSS_PWMSYNC4 4U //!< PWMSYNC4 +#define CMPSS_PWMSYNC5 5U //!< PWMSYNC5 +#define CMPSS_PWMSYNC6 6U //!< PWMSYNC6 +#define CMPSS_PWMSYNC7 7U //!< PWMSYNC7 +#define CMPSS_PWMSYNC8 8U //!< PWMSYNC8 +#define CMPSS_PWMSYNC9 9U //!< PWMSYNC9 +#define CMPSS_PWMSYNC10 10U //!< PWMSYNC10 +#define CMPSS_PWMSYNC11 11U //!< PWMSYNC11 +#define CMPSS_PWMSYNC12 12U //!< PWMSYNC12 + + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks the CMPSS base address. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function determines if a CMPSS base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CMPSS_isBaseValid(uint32_t base) +{ + return( + (base == CMPSS1_BASE) || + (base == CMPSS2_BASE) || + (base == CMPSS3_BASE) || + (base == CMPSS4_BASE) || + (base == CMPSS5_BASE) || + (base == CMPSS6_BASE) || + (base == CMPSS7_BASE) || + (base == CMPSS8_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function enables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) |= CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function disables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Clear the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) &= ~CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the high comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPH or +//! CTRIPOUTH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configHighComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_HICMP_CTL_M) | config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the low comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPL or +//! CTRIPOUTL. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configLowComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_LOCMP_CTL_M) | (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTH: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPH: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsHigh(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTHSEL_M | + CMPSS_COMPCTL_CTRIPHSEL_M)) | + config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTL: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPL: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsLow(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTLSEL_M | + CMPSS_COMPCTL_CTRIPLSEL_M)) | + (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current comparator status. +//! +//! \param base is the base address of the comparator module. +//! +//! This function returns the current status for the comparator, specifically +//! the digital filter output and latched digital filter output. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b CMPSS_STS_HI_FILTOUT - High digital filter output +//! - \b CMPSS_STS_HI_LATCHFILTOUT - Latched value of high digital filter +//! output +//! - \b CMPSS_STS_LO_FILTOUT - Low digital filter output +//! - \b CMPSS_STS_LO_LATCHFILTOUT - Latched value of low digital filter output +// +//***************************************************************************** +static inline uint16_t +CMPSS_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Return contents of the status register. + // + return(HWREGH(base + CMPSS_O_COMPSTS)); +} + +//***************************************************************************** +// +//! Sets the configuration for the internal comparator DACs. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the internal DAC. +//! +//! This function configures the comparator's internal DAC. The \e config +//! parameter is the result of a logical OR operation between the +//! \b CMPSS_DACVAL_xxx, \b CMPSS_DACREF_xxx, and \b CMPSS_DACSRC_xxx. +//! +//! The \b CMPSS_DACVAL_xxx term can take on the following values to specify +//! when the DAC value is loaded from its shadow register: +//! - \b CMPSS_DACVAL_SYSCLK - Value register updated on system clock. +//! - \b CMPSS_DACVAL_PWMSYNC - Value register updated on PWM sync. +//! +//! The \b CMPSS_DACREF_xxx term can take on the following values to specify +//! which voltage supply is used as reference for the DACs: +//! - \b CMPSS_DACREF_VDDA - VDDA is the voltage reference for the DAC. +//! - \b CMPSS_DACREF_VDAC - VDAC is the voltage reference for the DAC. +//! +//! The \b CMPSS_DACSRC_xxx term can take on the following values to specify +//! the DAC value source for the high comparator's internal DAC: +//! - \b CMPSS_DACSRC_SHDW - The user-programmed DACVALS register. +//! - \b CMPSS_DACSRC_RAMP - The ramp generator RAMPSTS register +//! +//! \note The \b CMPSS_DACVAL_xxx and \b CMPSS_DACREF_xxx terms apply to +//! both the high and low comparators. \b CMPSS_DACSRC_xxx will only affect +//! the high comparator's internal DAC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configDAC(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~(CMPSS_COMPDACCTL_SWLOADSEL | CMPSS_COMPDACCTL_SELREF | + CMPSS_COMPDACCTL_DACSOURCE)) | config; + EDIS; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the high +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueHigh(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACHVALS) = value; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the low +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueLow(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACLVALS) = value; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the high comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterHigh() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the high comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) |= CMPSS_CTRIPHFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the low comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterLow() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the low comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) |= CMPSS_CTRIPLFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the high comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueHigh() writes. +//! +//! \return Returns the value driven by the internal DAC of the high comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACHVALA)); +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the low comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueLow() writes. +//! +//! \return Returns the value driven by the internal DAC of the low comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACLVALA)); +} + +//***************************************************************************** +// +//! Causes a software reset of the high comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the high comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Causes a software reset of the low comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the low comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! \param value the ramp maximum reference value. +//! +//! This function sets the ramp maximum reference value that will be loaded +//! into the ramp generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setMaxRampValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp maximum reference value that will be +//! loaded into the ramp generator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getMaxRampValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the maximum ramp value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPMAXREFA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the ramp decrement value. +//! +//! This function sets the value that is subtracted from the ramp value on +//! every system clock cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDecValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp decrement value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDecValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp decrement value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDECVALA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the 13-bit ramp delay value. +//! +//! This function sets the value that configures the number of system clock +//! cycles to delay the start of the ramp generator decrementer after a PWMSYNC +//! event is received. Delay value can be no greater than 8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDelayValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 8192U); + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp delay value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDelayValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp delay value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDLYA)); +} + +//***************************************************************************** +// +//! Configures sync source for comparator +//! +//! \param base is the base address of the comparator module. +//! \param syncSource is the desired EPWMxSYNCPER source +//! +//! This function configures desired EPWMxSYNCPER source for comparator +//! blocks. Configured EPWMxSYNCPER signal can be used to synchronize loading +//! of DAC input value from shadow to active register. It can also be used to +//! synchronize Ramp generator, if applicable. Refer to device manual to check +//! if Ramp generator is available in the desired CMPSS instance. +//! +//! Valid values for \e syncSource parameter can be 1 to n, where n represents +//! the maximum number of EPWMSYNCPER signals available on the device. For +//! instance, passing 2 into \e syncSource will select EPWM2SYNCPER. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configureSyncSource(uint32_t base, uint16_t syncSource) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp delay value to the shadow register. + // + EALLOW; + HWREGH(base + CMPSS_O_COMPDACCTL) = (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(syncSource - 1U) << + CMPSS_COMPDACCTL_RAMPSOURCE_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the comparator hysteresis settings. +//! +//! \param base is the base address of the comparator module. +//! \param value is the amount of hysteresis on the comparator inputs. +//! +//! This function sets the amount of hysteresis on the comparator inputs. The +//! \e value parameter indicates the amount of hysteresis desired. Passing in 0 +//! results in none, passing in 1 results in typical hysteresis, passing in 2 +//! results in 2x of typical hysteresis, and so on where \e value x of typical +//! hysteresis is the amount configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setHysteresis(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value <= 4U); + + // + // Read the ramp delay value from the register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPHYSCTL) = value; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the high +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configHighComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterHigh() +//! -# Initialize the sample values using CMPSS_initFilterHigh() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsHigh() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the low +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configLowComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterLow() +//! -# Initialize the sample values using CMPSS_initFilterLow() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsLow() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures whether or not the digital filter latches are reset by PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! \param highEnable indicates filter latch settings in the high comparator. +//! \param lowEnable indicates filter latch settings in the low comparator. +//! +//! This function configures whether or not the digital filter latches in both +//! the high and low comparators should be reset by PWMSYNC. If the +//! \e highEnable parameter is \b true, the PWMSYNC will be allowed to reset +//! the high comparator's digital filter latch. If it is false, the ability of +//! the PWMSYNC to reset the latch will be disabled. The \e lowEnable parameter +//! has the same effect on the low comparator's digital filter latch. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable); + +//***************************************************************************** +// +//! Configures the comparator subsystem's ramp generator. +//! +//! \param base is the base address of the comparator module. +//! \param maxRampVal is the ramp maximum reference value. +//! \param decrementVal value is the ramp decrement value. +//! \param delayVal is the ramp delay value. +//! \param pwmSyncSrc is the number of the PWMSYNC source. +//! \param useRampValShdw indicates if the max ramp shadow should be used. +//! +//! This function configures many of the main settings of the comparator +//! subsystem's ramp generator. The \e maxRampVal parameter should be passed +//! the ramp maximum reference value that will be loaded into the ramp +//! generator. The \e decrementVal parameter should be passed the decrement +//! value that will be subtracted from the ramp generator on each system clock +//! cycle. The \e delayVal parameter should be passed the 13-bit number of +//! system clock cycles the ramp generator should delay before beginning to +//! decrement the ramp generator after a PWMSYNC signal is received. +//! +//! These three values may be be set individually using the +//! CMPSS_setMaxRampValue(), CMPSS_setRampDecValue(), and +//! CMPSS_setRampDelayValue() APIs. +//! +//! The number of the PWMSYNC signal to be used to reset the ramp generator +//! should be specified by passing it into the \e pwmSyncSrc parameter. For +//! instance, passing a CMPSS_PWMSYNCx into \e pwmSyncSrc will select PWMSYNCx. +//! +//! To indicate whether the ramp generator should reset with the value from the +//! ramp max reference value shadow register or with the latched ramp max +//! reference value, use the \e useRampValShdw parameter. Passing it \b true +//! will result in the latched value being bypassed. The ramp generator will be +//! loaded right from the shadow register. A value of \b false will load the +//! ramp generator from the latched value. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CMPSS_H diff --git a/gpio_bitfield_cpu1/device/driverlib/cpu.h b/gpio_bitfield_cpu1/device/driverlib/cpu.h new file mode 100644 index 0000000..3e7385b --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cpu.h @@ -0,0 +1,172 @@ +//########################################################################### +// +// FILE: cpu.h +// +// TITLE: Useful C28x CPU defines. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CPU_H +#define CPU_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +// +// External reference to the interrupt flag register (IFR) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IFR; +#endif + +// +// External reference to the interrupt enable register (IER) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IER; +#endif + +// +// Define to enable interrupts +// +#ifndef EINT +#define EINT __asm(" clrc INTM") +#endif + +// +// Define to disable interrupts +// +#ifndef DINT +#define DINT __asm(" setc INTM") +#endif + +// +// Define to enable debug events +// +#ifndef ERTM +#define ERTM __asm(" clrc DBGM") +#endif + +// +// Define to disable debug events +// +#ifndef DRTM +#define DRTM __asm(" setc DBGM") +#endif + +// +// Define to allow writes to protected registers +// +#ifndef EALLOW +#ifndef __TMS320C28XX_CLA__ +#define EALLOW __eallow() +#else +#define EALLOW __meallow() +#endif // __TMS320C28XX_CLA__ +#endif // EALLOW + +// +// Define to disable writes to protected registers +// +#ifndef EDIS +#ifndef __TMS320C28XX_CLA__ +#define EDIS __edis() +#else +#define EDIS __medis() +#endif // __TMS320C28XX_CLA__ +#endif // EDIS + +// +// Define for emulation stop +// +#ifndef ESTOP0 +#define ESTOP0 __asm(" ESTOP0") +#endif + +// +// Define for emulation stop +// +#ifndef ESTOP1 +#define ESTOP1 __asm(" ESTOP1") +#endif + +// +// Define for no operation +// +#ifndef NOP +#define NOP __asm(" NOP") +#endif + +// +// Define for putting processor into a low-power mode +// +#ifndef _DUAL_HEADERS +#ifndef IDLE +#define IDLE __asm(" IDLE") +#endif +#else +#define IDLE_ASM __asm(" IDLE"); +#endif + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// +//***************************************************************************** +extern void __eallow(void); +extern void __edis(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CPU_H diff --git a/gpio_bitfield_cpu1/device/driverlib/cputimer.c b/gpio_bitfield_cpu1/device/driverlib/cputimer.c new file mode 100644 index 0000000..5d12934 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cputimer.c @@ -0,0 +1,61 @@ +//############################################################################# +// +// FILE: cputimer.c +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "cputimer.h" + +//***************************************************************************** +// +// CPUTimer_setEmulationMode +// +//***************************************************************************** +void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode) +{ + ASSERT(CPUTimer_isBaseValid(base)); + // + // Write to FREE_SOFT bits of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) = + (HWREGH(base + CPUTIMER_O_TCR) & + ~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) | + (uint16_t)mode; +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/cputimer.h b/gpio_bitfield_cpu1/device/driverlib/cputimer.h new file mode 100644 index 0000000..71a7501 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/cputimer.h @@ -0,0 +1,509 @@ +//############################################################################# +// +// FILE: cputimer.h +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef CPUTIMER_H +#define CPUTIMER_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup cputimer_api CPUTimer +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_cputimer.h" +#include "debug.h" +#include "sysctl.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +//! Values that can be passed to CPUTimer_setEmulationMode() as the +//! \e mode parameter. +// +//**************************************************************************** +typedef enum +{ + //! Denotes that the timer will stop after the next decrement + CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000, + //! Denotes that the timer will stop when it reaches zero + CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400, + //! Denotes that the timer will run free + CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800 +}CPUTimer_EmulationMode; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e source parameter. +// +//***************************************************************************** +typedef enum +{ + //! System Clock Source + CPUTIMER_CLOCK_SOURCE_SYS = 0x0, + //! Internal Oscillator 1 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1, + //! Internal Oscillator 2 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2, + //! External Clock Source + CPUTIMER_CLOCK_SOURCE_XTAL = 0x3, + //! Auxiliary PLL Clock Source + CPUTIMER_CLOCK_SOURCE_AUX = 0x6 +} CPUTimer_ClockSource; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1 + CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2 + CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4 + CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8 + CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16 +} CPUTimer_Prescaler; + +//***************************************************************************** +// +//! \internal +//! Checks CPU timer base address. +//! +//! \param base specifies the Timer module base address. +//! +//! This function determines if a CPU timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CPUTimer_isBaseValid(uint32_t base) +{ + return((base == CPUTIMER0_BASE) || (base == CPUTIMER1_BASE) || + (base == CPUTIMER2_BASE)); +} +#endif + +//***************************************************************************** +// +//! Clears CPU timer overflow flag. +//! +//! \param base is the base address of the timer module. +//! +//! This function clears the CPU timer overflow flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_clearOverflowFlag(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIF bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; +} + +//***************************************************************************** +// +//! Disables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function disables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_disableInterrupt(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TIE bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Enables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function enables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_enableInterrupt(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIE bit of TCR register + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Reloads CPU timer counter. +//! +//! \param base is the base address of the timer module. +//! +//! This function reloads the CPU timer counter with the values contained in +//! the CPU timer period register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_reloadTimerCounter(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TRB bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; +} + +//***************************************************************************** +// +//! Stops CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function stops the CPU timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_stopTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TSS bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function doesn't reset the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_resumeTimer(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function reloads the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_startTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Reload the timer counter + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Sets CPU timer period. +//! +//! \param base is the base address of the timer module. +//! \param periodCount is the CPU timer period count. +//! +//! This function sets the CPU timer period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Load the MSB period Count + // + HWREG(base + CPUTIMER_O_PRD) = periodCount; +} + +//***************************************************************************** +// +//! Returns the current CPU timer counter value. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the current CPU timer counter value. +//! +//! \return Returns the current CPU timer count value. +// +//***************************************************************************** +static inline uint32_t CPUTimer_getTimerCount(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Get the TIMH:TIM registers value + // + return(HWREG(base + CPUTIMER_O_TIM)); +} + +//***************************************************************************** +// +//! Set CPU timer pre-scaler value. +//! +//! \param base is the base address of the timer module. +//! \param prescaler is the CPU timer pre-scaler value. +//! +//! This function sets the pre-scaler value for the CPU timer. For every value +//! of (prescaler + 1), the CPU timer counter decrements by 1. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Writes to TPR.TDDR and TPRH.TDDRH bits + // + HWREGH(base + CPUTIMER_O_TPRH) = prescaler >> 8U; + HWREGH(base + CPUTIMER_O_TPR) = (prescaler & CPUTIMER_TPR_TDDR_M) ; +} + +//***************************************************************************** +// +//! Return the CPU timer overflow status. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the CPU timer overflow status. +//! +//! \return Returns true if the CPU timer has overflowed, false if not. +// +//***************************************************************************** +static inline bool CPUTimer_getTimerOverflowStatus(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Check if TIF bits of register TCR are set + // + return(((HWREGH(base + CPUTIMER_O_TCR) & CPUTIMER_TCR_TIF) == + CPUTIMER_TCR_TIF) ? true : false); +} + +//***************************************************************************** +// +//! Select CPU Timer 2 Clock Source and Prescaler +//! +//! \param base is the base address of the timer module. +//! \param source is the clock source to use for CPU Timer 2 +//! \param prescaler is the value that configures the selected clock source +//! relative to the system clock +//! +//! This function selects the specified clock source and prescaler value +//! for the CPU timer (CPU timer 2 only). +//! +//! The \e source parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock +//! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock +//! +//! The \e prescaler parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1 +//! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2 +//! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4 +//! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8 +//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16 +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_selectClockSource(uint32_t base, + CPUTimer_ClockSource source, + CPUTimer_Prescaler prescaler) +{ + ASSERT(base == CPUTIMER2_BASE); + + // + // Set source and prescaler for CPU Timer 2 + // + if(base == CPUTIMER2_BASE) + { + EALLOW; + + // + // Set Clock Source + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | (uint16_t)source; + SYSCTL_REGWRITE_DELAY; + + // + // Set Clock Prescaler + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M) | + ((uint16_t)prescaler < 0.0F); + + // + // Get the sign-extended offset trim value + // + oldOffsetTrim = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + oldOffsetTrim = ((oldOffsetTrim & (uint16_t)DAC_REG_BYTE_MASK) ^ + (uint16_t)0x80) - (uint16_t)0x80; + + // + // Calculate new offset trim value if DAC is operating at a reference + // voltage other than 2.5v. + // + newOffsetTrim = ((float32_t)(2.5 / referenceVoltage) * + (int16_t)oldOffsetTrim); + + // + // Check if the new offset trim value is valid + // + ASSERT(((int16_t)newOffsetTrim > -129) && ((int16_t)newOffsetTrim < 128)); + + // + // Set the new offset trim value + // + EALLOW; + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | + (int16_t)newOffsetTrim; + + EDIS; + +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/dac.h b/gpio_bitfield_cpu1/device/driverlib/dac.h new file mode 100644 index 0000000..fcd866a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/dac.h @@ -0,0 +1,604 @@ +//########################################################################### +// +// FILE: dac.h +// +// TITLE: C28x DAC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DAC_H +#define DAC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dac_api DAC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dac.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +// +// A 8-bit register mask +// +#define DAC_REG_BYTE_MASK (0xFFU) //!< Register Byte Mask + +// +// Lock Key +// +#define DAC_LOCK_KEY (0xA000U) //!< DAC Lock Key + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are defines for the reg parameter of the +// DAC_lockRegister() and DAC_isRegisterLocked() functions. +// +//***************************************************************************** +#define DAC_LOCK_CONTROL (0x1U) //!< Lock the control register +#define DAC_LOCK_SHADOW (0x2U) //!< Lock the shadow value register +#define DAC_LOCK_OUTPUT (0x4U) //!< Lock the output enable register + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! Values that can be passed to DAC_setReferenceVoltage() as the \e source +//! parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_REF_VDAC = 0, //!< VDAC reference voltage + DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage +}DAC_ReferenceVoltage; + +//***************************************************************************** +// +//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK + DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL +}DAC_LoadMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks DAC base address. +//! +//! \param base specifies the DAC module base address. +//! +//! This function determines if an DAC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DAC_isBaseValid(uint32_t base) +{ + return( + (base == DACA_BASE) || + (base == DACB_BASE) || + (base == DACC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Get the DAC Revision value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC revision value. +//! +//! \return Returns the DAC revision value. +// +//***************************************************************************** +static inline uint16_t +DAC_getRevision(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the revision value. + // + return(HWREGH(base + DAC_O_REV) & DAC_REV_REV_M); +} + +//***************************************************************************** +// +//! Sets the DAC Reference Voltage +//! +//! \param base is the DAC module base address +//! \param source is the selected reference voltage +//! +//! This function sets the DAC reference voltage. +//! +//! The \e source parameter can have the following value: +//! - \b DAC_REF_VDAC - The VDAC reference voltage +//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the reference voltage + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_DACREFSEL) | (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC Load Mode +//! +//! \param base is the DAC module base address +//! \param mode is the selected load mode +//! +//! This function sets the DAC load mode. +//! +//! The \e mode parameter can have one of two values: +//! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK +//! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setLoadMode(uint32_t base, DAC_LoadMode mode) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the load mode + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_LOADMODE) | (uint16_t)mode; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC PWMSYNC Signal +//! +//! \param base is the DAC module base address +//! \param signal is the selected PWM signal +//! +//! This function sets the DAC PWMSYNC signal. +//! +//! The \e signal parameter must be set to a number that represents the PWM +//! signal that will be set. For instance, passing 2 into \e signal will +//! select PWM sync signal 2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setPWMSyncSignal(uint32_t base, uint16_t pwmSignal) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((pwmSignal > 0U) && (pwmSignal < 17U)); + + // + // Set the PWM sync signal + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_SYNCSEL_M) | + ((uint16_t)(pwmSignal - 1U) << + DAC_CTL_SYNCSEL_S); + + EDIS; +} + +//***************************************************************************** +// +//! Get the DAC Active Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC active output value. +//! +//! \return Returns the DAC active output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getActiveValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the active value + // + return(HWREGH(base + DAC_O_VALA) & DAC_VALA_DACVALA_M); +} + +//***************************************************************************** +// +//! Set the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! \param value is the 12-bit code to be loaded into the active value register +//! +//! This function sets the DAC shadow output value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setShadowValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT(value <= DAC_VALS_DACVALS_M); + + // + // Set the shadow value + // + HWREGH(base + DAC_O_VALS) = (HWREGH(base + DAC_O_VALS) & + ~DAC_VALS_DACVALS_M) | + (uint16_t)(value & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Get the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC shadow output value. +//! +//! \return Returns the DAC shadow output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getShadowValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the shadow value + // + return(HWREGH(base + DAC_O_VALS) & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Enable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function enables the DAC output. +//! +//! \note A delay is required after enabling the DAC. Further details +//! regarding the exact delay time length can be found in the device datasheet. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_enableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Enable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) |= DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function disables the DAC output. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_disableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Disable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) &= ~DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Set DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param offset is the specified value for the offset trim +//! +//! This function sets the DAC offset trim. The \e offset value should be a +//! signed number in the range of -128 to 127. +//! +//! \note The offset should not be modified unless specifically indicated by +//! TI Errata or other documentation. Modifying the offset value could cause +//! this module to operate outside of the datasheet specifications. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setOffsetTrim(uint32_t base, int16_t offset) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((offset > -129) && (offset < 128)); + + // + // Set the offset trim value + // + EALLOW; + + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | (int16_t)offset; + + EDIS; +} + +//***************************************************************************** +// +//! Get DAC Offset Trim +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC offset trim value. +//! +//! \return None. +// +//***************************************************************************** +static inline int16_t +DAC_getOffsetTrim(uint32_t base) +{ + uint16_t value; + + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the sign-extended offset trim value + // + value = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + value = ((value & (uint16_t)DAC_REG_BYTE_MASK) ^ (uint16_t)0x80) - + (uint16_t)0x80; + + return((int16_t)value); +} + +//***************************************************************************** +// +//! Lock write-access to DAC Register +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC registers +//! +//! This function locks the write-access to the specified DAC register. Only a +//! system reset can unlock the register once locked. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_lockRegister(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Lock the specified registers + // + EALLOW; + + HWREGH(base + DAC_O_LOCK) |= (DAC_LOCK_KEY | reg); + + EDIS; +} + +//***************************************************************************** +// +//! Check if DAC Register is locked +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC register locks to check +//! +//! This function checks if write-access has been locked on the specified DAC +//! register. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return Returns \b true if any of the registers specified are locked, and +//! \b false if all specified registers aren't locked. +// +//***************************************************************************** +static inline bool +DAC_isRegisterLocked(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Return the lock status on the specified registers + // + return((bool)((HWREGH(base + DAC_O_LOCK) & reg) != 0U)); +} + +//***************************************************************************** +// +//! Tune DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param referenceVoltage is the reference voltage the DAC +//! module is operating at. +//! +//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage +//! value should be a floating point number in the range specified in the +//! device data manual. +//! +//! \note Use this function to adjust the DAC offset trim if operating +//! at a reference voltage other than 2.5v. Since this function modifies +//! the DAC offset trim register, it should only be called once after +//! Device_cal. If it is called multiple times after Device_cal, the offset +//! value scaled would be the wrong value. +//! +//! \return None. +// +//***************************************************************************** +extern void +DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DAC_H diff --git a/gpio_bitfield_cpu1/device/driverlib/dcsm.c b/gpio_bitfield_cpu1/device/driverlib/dcsm.c new file mode 100644 index 0000000..808027a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/dcsm.c @@ -0,0 +1,377 @@ +//############################################################################# +// +// FILE: dcsm.c +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "dcsm.h" + +//***************************************************************************** +// +// DCSM_unlockZone1CSM +// +//***************************************************************************** +void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3; + } +} + +//***************************************************************************** +// +// DCSM_unlockZone2CSM +// +//***************************************************************************** +void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3; + } +} +//***************************************************************************** +// +// DCSM_getZone1FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t) + ((regValue >> (uint16_t)sector) & + 0x01U)); + } + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone1RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >> + (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_getZone2FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >> + (uint16_t)sector) & 0x01U)); + } + + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone2RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z2_BASE + + DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_claimZoneSemaphore +// +//***************************************************************************** +bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S) | + (uint16_t)zone; + EDIS; + + // + // If the calling function was unable to claim the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == (uint16_t)zone) ? + true : false); +} + +//***************************************************************************** +// +// DCSM_releaseZoneSemaphore +// +//***************************************************************************** +bool +DCSM_releaseZoneSemaphore(void) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S); + EDIS; + + // + // If the calling function was unable to release the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == 0x0U) ? true : false); +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/dcsm.h b/gpio_bitfield_cpu1/device/driverlib/dcsm.h new file mode 100644 index 0000000..d181fa7 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/dcsm.h @@ -0,0 +1,669 @@ +//############################################################################# +// +// FILE: dcsm.h +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef DCSM_H +#define DCSM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dcsm_api DCSM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dcsm.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the unlockZone1CSM() and unlockZone2CSM(). +// These are not parameters for any function. +// These are not intended for application code. +// +//***************************************************************************** + +#define DCSM_O_Z1_CSMPSWD0 0x08U //!< Z1 CSMPSWD0 offset +#define DCSM_O_Z1_CSMPSWD1 0x0AU //!< Z1 CSMPSWD1 offset +#define DCSM_O_Z1_CSMPSWD2 0x0CU //!< Z1 CSMPSWD2 offset +#define DCSM_O_Z1_CSMPSWD3 0x0EU //!< Z1 CSMPSWD3 offset +#define DCSM_O_Z2_CSMPSWD0 0x08U //!< Z2 CSMPSWD0 offset +#define DCSM_O_Z2_CSMPSWD1 0x0AU //!< Z2 CSMPSWD1 offset +#define DCSM_O_Z2_CSMPSWD2 0x0CU //!< Z2 CSMPSWD2 offset +#define DCSM_O_Z2_CSMPSWD3 0x0EU //!< Z2 CSMPSWD3 offset + +//***************************************************************************** +// +// Register key defines. +// +//***************************************************************************** +#define FLSEM_KEY 0xA5U //!< Zone semaphore key + +//***************************************************************************** +// +//! Data structures to hold password keys. +// +//***************************************************************************** +typedef struct +{ + uint32_t csmKey0; + uint32_t csmKey1; + uint32_t csmKey2; + uint32_t csmKey3; +} DCSM_CSMPasswordKey; + +//***************************************************************************** +// +//! Values to distinguish the status of RAM or FLASH sectors. These values +//! describe which zone the memory location belongs too. +//! These values can be returned from DCSM_getRAMZone(), +//! DCSM_getFlashSectorZone(). +// +//***************************************************************************** +typedef enum +{ + DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible + DCSM_MEMORY_ZONE1, //!< Zone 1 + DCSM_MEMORY_ZONE2, //!< Zone 2 + DCSM_MEMORY_FULL_ACCESS //!< Full access +} DCSM_MemoryStatus; + +//***************************************************************************** +// +//! Values to pass to DCSM_claimZoneSemaphore(). These values are used +//! to describe the zone that can write to Flash Wrapper registers. +// +//***************************************************************************** +typedef enum +{ + DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1 + DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2 +} DCSM_SemaphoreZone; + +//***************************************************************************** +// +//! Values to distinguish the security status of the zones. +//! These values can be returned from DCSM_getZone1CSMSecurityStatus(), +//! DCSM_getZone2CSMSecurityStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_STATUS_SECURE, //!< Secure + DCSM_STATUS_UNSECURE, //!< Unsecure + DCSM_STATUS_LOCKED, //!< Locked +} DCSM_SecurityStatus; + +//***************************************************************************** +// +// Values to distinguish the status of the Control Registers. These values +// describe can be used with the return values of +// DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus(). +// +//***************************************************************************** +#define DCSM_ALLZERO 0x08U //!< CSM Passwords all zeros +#define DCSM_ALLONE 0x10U //!< CSM Passwords all ones +#define DCSM_UNSECURE 0x20U //!< Zone is secure/unsecure +#define DCSM_ARMED 0x40U //!< CSM is armed + +//***************************************************************************** +// +//! Values to decribe the EXEONLY Status. +//! These values are returned from to DCSM_getZone1RAMEXEStatus(), +//! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(), +//! DCSM_getZone2FlashEXEStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_PROTECTED, //!< Protected + DCSM_UNPROTECTED, //!< Unprotected + DCSM_INCORRECT_ZONE //!< Incorrect Zone +}DCSM_EXEOnlyStatus; + +//***************************************************************************** +// +//! Values to distinguish RAM Module. +//! These values can be passed to DCSM_getZone1RAMEXEStatus() +//! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone(). +// +//***************************************************************************** +typedef enum +{ + // + //C28x RAMs + // + DCSM_RAMLS0, //!< RAMLS0 + DCSM_RAMLS1, //!< RAMLS1 + DCSM_RAMLS2, //!< RAMLS2 + DCSM_RAMLS3, //!< RAMLS3 + DCSM_RAMLS4, //!< RAMLS4 + DCSM_RAMLS5, //!< RAMLS5 + DCSM_RAMD0, //!< RAMD0 + DCSM_RAMD1, //!< RAMD1 + DCSM_CLA = 14U //!> + shift) & 0x03U); + return((DCSM_MemoryStatus)ramStatus); +} + +//***************************************************************************** +// +//! Returns the security zone a flash sector belongs to +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function returns the security zone a flash sector belongs to. +//! +//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible , +//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if +//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section +//! doesn't belong to any zone (or if the section is unsecure).. +// +//***************************************************************************** +static inline DCSM_MemoryStatus +DCSM_getFlashSectorZone(DCSM_Sector sector) +{ + uint32_t sectStat; + uint16_t shift; + + // + // Get the Sector status register for the specific bank + // + sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT); + shift = (uint16_t)sector * 2U; + + // + //Read the SECTSTAT register for the specific Flash Sector. + // + return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U))); +} + +//***************************************************************************** +// +//! Read Zone 1 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 1 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone1LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Read Zone 2 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 2 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone2LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Unlocks Zone 1 CSM. +//! +//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the +//! CSM password for zone 1. +//! +//! This function unlocks the CSM password. It first reads the +//! four password locations in the User OTP. If any of the password values is +//! different from 0xFFFFFFFF, it unlocks the device by writing the provided +//! passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey); + +//***************************************************************************** +// +//! Unlocks Zone 2 CSM. +//! +//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM +//! password for zone 2. +//! +//! This function unlocks the CSM password. It first reads +//! the four password locations in the User OTP. If any of the password values +//! is different from 0xFFFFFFFF, it unlocks the device by writing the +//! provided passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey); +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Claims the zone semaphore which allows access to the Flash Wrapper register +//! for that zone. +//! +//! \param zone is the zone which is trying to claim the semaphore which allows +//! access to the Flash Wrapper registers. +//! +//! \return Returns true for a successful semaphore capture, false if it was +//! unable to capture the semaphore. +// +//***************************************************************************** +extern bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone); + +//***************************************************************************** +// +//! Releases the zone semaphore. +//! +//! \return Returns true if it was successful in releasing the zone semaphore +//! and false if it was unsuccessful in releasing the zone semaphore. +//! +//! \note If the calling function is not in the right zone to be able +//! to access this register, it will return a false. +// +//***************************************************************************** +extern bool +DCSM_releaseZoneSemaphore(void); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DCSM_H diff --git a/gpio_bitfield_cpu1/device/driverlib/debug.h b/gpio_bitfield_cpu1/device/driverlib/debug.h new file mode 100644 index 0000000..5a2f93a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/debug.h @@ -0,0 +1,91 @@ +//########################################################################### +// +// FILE: debug.h +// +// TITLE: Assert definition macro for debug. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DEBUG_H +#define DEBUG_H + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. It is the +// application's responsibility to define the __error__ function. +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#ifdef __TMS320C28XX__ +// +// When called from C28x application +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } \ + while((_Bool)0) +#else +// +// When called from CLA application. Update as needed. +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __mdebugstop(); \ + } \ + } \ + while((_Bool)0) +#endif +#else +#define ASSERT(expr) +#endif + +#endif // DEBUG_H diff --git a/gpio_bitfield_cpu1/device/driverlib/dma.c b/gpio_bitfield_cpu1/device/driverlib/dma.c new file mode 100644 index 0000000..ea591b1 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/dma.c @@ -0,0 +1,370 @@ +//########################################################################### +// +// FILE: dma.c +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "dma.h" + +//***************************************************************************** +// +// DMA_configAddresses +// +//***************************************************************************** +void DMA_configAddresses(uint32_t base, const void *destAddr, + const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configBurst +// +//***************************************************************************** +void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((size >= 1U) && (size <= 32U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up BURST registers. + // + HWREGH(base + DMA_O_BURST_SIZE) = size - 1U; + HWREGH(base + DMA_O_SRC_BURST_STEP) = srcStep; + HWREGH(base + DMA_O_DST_BURST_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configTransfer +// +//***************************************************************************** +void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(transferSize <= 0x10000U); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up TRANSFER registers. + // + HWREGH(base + DMA_O_TRANSFER_SIZE) = (uint16_t)(transferSize - 1U); + HWREGH(base + DMA_O_SRC_TRANSFER_STEP) = srcStep; + HWREGH(base + DMA_O_DST_TRANSFER_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configWrap +// +//***************************************************************************** +void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((srcWrapSize <= 0x10000U) || (destWrapSize <= 0x10000U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up WRAP registers. + // + HWREGH(base + DMA_O_SRC_WRAP_SIZE) = (uint16_t)(srcWrapSize - 1U); + HWREGH(base + DMA_O_SRC_WRAP_STEP) = srcStep; + + HWREGH(base + DMA_O_DST_WRAP_SIZE) = (uint16_t)(destWrapSize - 1U); + HWREGH(base + DMA_O_DST_WRAP_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configMode +// +//***************************************************************************** +void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up trigger selection in the CMA/CLA trigger source selection + // registers. These are considered part of system control. + // + switch(base) + { + case DMA_CH1_BASE: + // + // Channel 1 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH1_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH1_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH1_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH1_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 1U; + break; + + case DMA_CH2_BASE: + // + // Channel 2 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH2_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH2_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH2_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH2_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 2U; + break; + + case DMA_CH3_BASE: + // + // Channel 3 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH3_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH3_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH3_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH3_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 3U; + break; + + case DMA_CH4_BASE: + // + // Channel 4 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH4_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH4_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH4_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH4_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 4U; + break; + + case DMA_CH5_BASE: + // + // Channel 5 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH5_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH5_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH5_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH5_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 5U; + break; + + case DMA_CH6_BASE: + // + // Channel 6 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH6_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH6_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH6_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH6_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 6U; + break; + + default: + // + // Invalid base. + // + break; + } + + // + // Write the configuration to the mode register. + // + HWREGH(base + DMA_O_MODE) &= ~(DMA_MODE_DATASIZE | DMA_MODE_CONTINUOUS | + DMA_MODE_ONESHOT); + HWREGH(base + DMA_O_MODE) |= config; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configChannel +// +//***************************************************************************** +void DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(((transfParams->configSize == DMA_CFG_SIZE_16BIT) || + (transfParams->configSize == DMA_CFG_SIZE_32BIT)) && + ((transfParams->transferMode == DMA_CFG_ONESHOT_DISABLE) || + (transfParams->transferMode == DMA_CFG_ONESHOT_ENABLE)) && + ((transfParams->reinitMode == DMA_CFG_CONTINUOUS_DISABLE) || + (transfParams->reinitMode == DMA_CFG_CONTINUOUS_ENABLE))); + + // + // Configure DMA Channel + // + DMA_configAddresses(base, (const void *)transfParams->destAddr, + (const void *)transfParams->srcAddr); + + // + // Configure the size of each burst and the address step size + // + DMA_configBurst(base, transfParams->burstSize, transfParams->srcBurstStep, + transfParams->destBurstStep); + + // + // Configure the transfer size and the address step that is + // made after each burst. + // + DMA_configTransfer(base, transfParams->transferSize, + transfParams->srcTransferStep, + transfParams->destTransferStep); + + // + // Configure the DMA channel's wrap settings + // + DMA_configWrap(base, transfParams->srcWrapSize, transfParams->srcWrapStep, + transfParams->destWrapSize, transfParams->destWrapStep); + + // + // Configure the DMA channel's trigger and mode + // + DMA_configMode(base, transfParams->transferTrigger, + transfParams->transferMode | transfParams->reinitMode | + transfParams->configSize); + + // + // Enable the selected peripheral trigger to start a DMA transfer + // + DMA_enableTrigger(base); + + if(transfParams->enableInterrupt) + { + // + // Set the channel interrupt mode + // + DMA_setInterruptMode(base, transfParams->interruptMode); + + // + // Enable the indicated DMA channel interrupt source + // + DMA_enableInterrupt(base); + } + else + { + // + // Disable the indicated DMA channel interrupt source + // + DMA_disableInterrupt(base); + } +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/dma.h b/gpio_bitfield_cpu1/device/driverlib/dma.h new file mode 100644 index 0000000..ae57689 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/dma.h @@ -0,0 +1,1171 @@ +//########################################################################### +// +// FILE: dma.h +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DMA_H +#define DMA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dma_api DMA +//! \brief This module is used for DMA configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dma.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to DMA_configMode() as the config parameter. +// +//***************************************************************************** +//! Only one burst transfer performed per trigger. +#define DMA_CFG_ONESHOT_DISABLE 0U +//! Burst transfers occur without additional event triggers after the first. +#define DMA_CFG_ONESHOT_ENABLE DMA_MODE_ONESHOT + +//! DMA channel will be disabled at the end of a transfer. +#define DMA_CFG_CONTINUOUS_DISABLE 0U +//! DMA reinitializes when the transfer count is zero and waits for a trigger. +#define DMA_CFG_CONTINUOUS_ENABLE DMA_MODE_CONTINUOUS + +//! DMA transfers 16 bits at a time. +#define DMA_CFG_SIZE_16BIT 0U +//! DMA transfers 32 bits at a time. +#define DMA_CFG_SIZE_32BIT DMA_MODE_DATASIZE + +//***************************************************************************** +// +//! Values that can be passed to DMA_configMode() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + DMA_TRIGGER_SOFTWARE = 0, + + DMA_TRIGGER_ADCA1 = 1, + DMA_TRIGGER_ADCA2 = 2, + DMA_TRIGGER_ADCA3 = 3, + DMA_TRIGGER_ADCA4 = 4, + DMA_TRIGGER_ADCAEVT = 5, + DMA_TRIGGER_ADCB1 = 6, + DMA_TRIGGER_ADCB2 = 7, + DMA_TRIGGER_ADCB3 = 8, + DMA_TRIGGER_ADCB4 = 9, + DMA_TRIGGER_ADCBEVT = 10, + DMA_TRIGGER_ADCC1 = 11, + DMA_TRIGGER_ADCC2 = 12, + DMA_TRIGGER_ADCC3 = 13, + DMA_TRIGGER_ADCC4 = 14, + DMA_TRIGGER_ADCCEVT = 15, + DMA_TRIGGER_ADCD1 = 16, + DMA_TRIGGER_ADCD2 = 17, + DMA_TRIGGER_ADCD3 = 18, + DMA_TRIGGER_ADCD4 = 19, + DMA_TRIGGER_ADCDEVT = 20, + + DMA_TRIGGER_XINT1 = 29, + DMA_TRIGGER_XINT2 = 30, + DMA_TRIGGER_XINT3 = 31, + DMA_TRIGGER_XINT4 = 32, + DMA_TRIGGER_XINT5 = 33, + + DMA_TRIGGER_EPWM1SOCA = 36, + DMA_TRIGGER_EPWM1SOCB = 37, + DMA_TRIGGER_EPWM2SOCA = 38, + DMA_TRIGGER_EPWM2SOCB = 39, + DMA_TRIGGER_EPWM3SOCA = 40, + DMA_TRIGGER_EPWM3SOCB = 41, + DMA_TRIGGER_EPWM4SOCA = 42, + DMA_TRIGGER_EPWM4SOCB = 43, + DMA_TRIGGER_EPWM5SOCA = 44, + DMA_TRIGGER_EPWM5SOCB = 45, + DMA_TRIGGER_EPWM6SOCA = 46, + DMA_TRIGGER_EPWM6SOCB = 47, + DMA_TRIGGER_EPWM7SOCA = 48, + DMA_TRIGGER_EPWM7SOCB = 49, + DMA_TRIGGER_EPWM8SOCA = 50, + DMA_TRIGGER_EPWM8SOCB = 51, + DMA_TRIGGER_EPWM9SOCA = 52, + DMA_TRIGGER_EPWM9SOCB = 53, + DMA_TRIGGER_EPWM10SOCA = 54, + DMA_TRIGGER_EPWM10SOCB = 55, + DMA_TRIGGER_EPWM11SOCA = 56, + DMA_TRIGGER_EPWM11SOCB = 57, + DMA_TRIGGER_EPWM12SOCA = 58, + DMA_TRIGGER_EPWM12SOCB = 59, + + DMA_TRIGGER_TINT0 = 68, + DMA_TRIGGER_TINT1 = 69, + DMA_TRIGGER_TINT2 = 70, + + DMA_TRIGGER_MCBSPAMXEVT = 71, + DMA_TRIGGER_MCBSPAMREVT = 72, + DMA_TRIGGER_MCBSPBMXEVT = 73, + DMA_TRIGGER_MCBSPBMREVT = 74, + + + DMA_TRIGGER_SDFM1FLT1 = 95, + DMA_TRIGGER_SDFM1FLT2 = 96, + DMA_TRIGGER_SDFM1FLT3 = 97, + DMA_TRIGGER_SDFM1FLT4 = 98, + + DMA_TRIGGER_SDFM2FLT1 = 99, + DMA_TRIGGER_SDFM2FLT2 = 100, + DMA_TRIGGER_SDFM2FLT3 = 101, + DMA_TRIGGER_SDFM2FLT4 = 102, + + + DMA_TRIGGER_SPIATX = 109, + DMA_TRIGGER_SPIARX = 110, + DMA_TRIGGER_SPIBTX = 111, + DMA_TRIGGER_SPIBRX = 112, + DMA_TRIGGER_SPICTX = 113, + DMA_TRIGGER_SPICRX = 114, + + DMA_TRIGGER_CLB1INT = 127, + DMA_TRIGGER_CLB2INT = 128, + DMA_TRIGGER_CLB3INT = 129, + DMA_TRIGGER_CLB4INT = 130, + +} DMA_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setInterruptMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! DMA interrupt is generated at the beginning of a transfer + DMA_INT_AT_BEGINNING, + //! DMA interrupt is generated at the end of a transfer + DMA_INT_AT_END +} DMA_InterruptMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after current read-write access is completed + DMA_EMULATION_STOP, + //! Continue DMA operation regardless of emulation suspend + DMA_EMULATION_FREE_RUN +} DMA_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_configChannel() as the +//! configure parameter. +// +//***************************************************************************** +typedef struct +{ + DMA_Trigger transferTrigger; //DMA transfer triggers + DMA_InterruptMode interruptMode; //Channel interrupt mode + //! enableInterrupt can have a value 1(Enable) or 0(Disable) + bool enableInterrupt; //Enable/Disable interrupt mode + //! configSize can have a value DMA_CFG_SIZE_16BIT/32BIT + uint32_t configSize; //Data bus width (16 or 32 bits) + //! transferMode can have a value DMA_CFG_ONESHOT_DISABLE/ENABLE + uint32_t transferMode; //Burst transfer mode + //! reinitMode can have a value DMA_CFG_CONTINUOUS_DISABLE/ENABLE + uint32_t reinitMode; //DMA reinitialization mode + //! burstSize value range from 1 word to 32 sixteen-bit words. + uint32_t burstSize; //Number of words transferred per burst + //! transferSize value range from 1 to 65536 + uint32_t transferSize; //Number of bursts per transfer + //! Number of bursts to be transferred before a wrap of the source address + //! occurs. srcWrapSize value range from 1 to 65536 + uint32_t srcWrapSize; + //! Number of bursts to be transferred before a wrap of the destination + //! address occurs. destWrapSize value range from 1 to 65536 + uint32_t destWrapSize; + uint32_t destAddr; //destination address + uint32_t srcAddr; //source address + //! Amount to inc or dec the source address after each word of a burst. + //! srcBurstStep can have only signed values from -4096 to 4095 + int16_t srcBurstStep; + //! Amount to inc or dec the destination address after each word of a burst. + //! destBurstStep can have only signed values from -4096 to 4095 + int16_t destBurstStep; + //! Amount to inc or dec the source address after each burst of a transfer. + //! srcTransferStep can have only signed values from -4096 to 4095 + int16_t srcTransferStep; + //! Amount to inc or dec the destination address after each burst of a + //! transfer. destTransferStep can have only signed values from -4096 to 4095 + int16_t destTransferStep; + //! Amount to inc or dec the source address when the wrap occurs. + //! srcWrapStep can have only signed values from -4096 to 4095 + int16_t srcWrapStep; + //! Amount to inc or dec the destination address when the wrap occurs. + //! destWrapStep can have only signed values from -4096 to 4095 + int16_t destWrapStep; + +} DMA_ConfigParams; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an DMA channel base address. +//! +//! \param base specifies the DMA channel base address. +//! +//! This function determines if a DMA channel base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DMA_isBaseValid(uint32_t base) +{ + return((base == DMA_CH1_BASE) || (base == DMA_CH2_BASE) || + (base == DMA_CH3_BASE) || (base == DMA_CH4_BASE) || + (base == DMA_CH5_BASE) || (base == DMA_CH6_BASE)); +} +#endif + +//***************************************************************************** +// +//! Initializes the DMA controller to a known state. +//! +//! This function configures does a hard reset of the DMA controller in order +//! to put it into a known state. The function also sets the DMA to run free +//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_initController(void) +{ + EALLOW; + + // + // Set the hard reset bit. One NOP is required after HARDRESET. + // + HWREGH(DMA_BASE + DMA_O_CTRL) |= DMA_CTRL_HARDRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Channel Soft Reset +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function does a soft reset to place the channel into its default state +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_triggerSoftReset(uint32_t base) +{ + EALLOW; + + // + // Set the soft reset bit. One NOP is required after SOFTRESET. + // + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_SOFTRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Sets DMA emulation mode. +//! +//! \param mode is the emulation mode to be selected. +//! +//! This function sets the behavior of the DMA operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is +//! completed. +//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setEmulationMode(DMA_EmulationMode mode) +{ + EALLOW; + + // + // Set emulation mode + // + if(mode == DMA_EMULATION_STOP) + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) &= ~DMA_DEBUGCTRL_FREE; + } + else + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) |= DMA_DEBUGCTRL_FREE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables peripherals to trigger a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the selected peripheral trigger to start a DMA +//! transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables peripherals from triggering a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the selected peripheral trigger from starting a DMA +//! transfer on the specified channel. This also disables the use of the +//! software force using the DMA_forceTrigger() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Clear the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Force a peripheral trigger to a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function sets the peripheral trigger flag and if triggering a DMA +//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be +//! forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_forceTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger force bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTFRC; + EDIS; +} + +//***************************************************************************** +// +//! Clears a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears the peripheral trigger flag. Normally, you would use +//! this function when initializing the DMA for the first time. The flag is +//! cleared automatically when the DMA starts the first burst of a transfer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearTriggerFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write a one to the clear bit to clear the peripheral trigger flag. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Transfer Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Transfer Status Flag is set, which +//! means a DMA transfer has begun. +//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTransferStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Transfer Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_TRANSFERSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Burst Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Burst Status Flag is set, which +//! means a DMA burst has begun. +//! This flag is cleared when BURST_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Burst Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getBurstStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Burst Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_BURSTSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Run Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Run Status Flag is set, which +//! means the DMA channel is enabled. +//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and +//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit +//! is set. +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getRunStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Run Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_RUNSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Overflow Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Overflow Flag is set, which +//! means peripheral event trigger was received while Peripheral Event Trigger +//! Flag was already set. +//! This flag can be cleared by writing to ERRCLR bit, using the function +//! DMA_clearErrorFlag(). +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getOverflowFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Overflow Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_OVRFLG) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if a peripheral trigger event has occurred +//! The flag is automatically cleared when the first burst transfer begins, but +//! if needed, it can be cleared using DMA_clearTriggerFlag(). +//! +//! \return Returns \b true if a peripheral trigger event has occurred and its +//! flag is set. Returns \b false otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTriggerFlagStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the peripheral trigger flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_PERINTFLG) != 0U); +} + +//***************************************************************************** +// +//! Starts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function starts the DMA running, typically after you have configured +//! it. It will wait for the first trigger event to start operation. To halt +//! the channel use DMA_stopChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_startChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the run bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_RUN; + EDIS; +} + +//***************************************************************************** +// +//! Halts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function halts the DMA at its current state and any current read-write +//! access is completed. To start the channel again use DMA_startChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_stopChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the halt bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_HALT; + EDIS; +} + +//***************************************************************************** +// +//! Enables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Enables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. An overrun is when a peripheral +//! event trigger is received by the DMA before a previous trigger on that +//! channel had been serviced and its flag had been cleared. +//! +//! Note that this is the same interrupt signal as the interrupt that gets +//! generated at the beginning/end of a transfer. That interrupt must first be +//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to +//! be generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Clears the DMA channel error flags. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears both the DMA channel's sync error flag and its +//! overrun error flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearErrorFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write to the error clear bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_ERRCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the interrupt generation mode of a DMA channel interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param mode is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e mode parameter +//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the +//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be +//! generated at the beginning of a new transfer. Generating at the beginning +//! of a new transfer is the default behavior. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Write the selected interrupt generation mode to the register. + // + if(mode == DMA_INT_AT_END) + { + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTMODE; + } + else + { + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTMODE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DMA channel priority mode. +//! +//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e ch1IsHighPri +//! parameter is \b false, the DMA channels are serviced in round-robin mode. +//! This is the default behavior. +//! +//! If \b true, channel 1 will be given higher priority than the other +//! channels. This means that if a channel 1 trigger occurs, the current word +//! transfer on any other channel is completed and channel 1 is serviced for +//! the complete burst count. The lower-priority channel's interrupted transfer +//! will then resume. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setPriorityMode(bool ch1IsHighPri) +{ + EALLOW; + + // + // Write the selected priority mode to the register. + // + if(ch1IsHighPri) + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) |= + DMA_PRIORITYCTRL1_CH1PRIORITY; + } + else + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) &= + ~DMA_PRIORITYCTRL1_CH1PRIORITY; + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the source address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *srcAddr is a source address. +//! +//! This function configures the source address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configSourceAddress(uint32_t base, const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the destination address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! +//! This function configures the destinaton address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configDestAddress(uint32_t base, const void *destAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Setup DMA to transfer data on the specified channel. +//! +//! \param base is Base address of the DMA channel control register +//! \param *transfParams configuration parameter +//! Refer struct #DMA_ConfigParams +//! +//! This function configures the DMA transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams); + +//***************************************************************************** +// +//! Configures the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! \param *srcAddr is a source address. +//! +//! This function configures the source and destination addresses of a DMA +//! channel. The parameters are pointers to the data to be transferred. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr); + +//***************************************************************************** +// +//! Configures the DMA channel's burst settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param size is the number of words transferred per burst. +//! \param srcStep is the amount to increment or decrement the source address +//! after each word of a burst. +//! \param destStep is the amount to increment or decrement the destination +//! address after each word of a burst. +//! +//! This function configures the size of each burst and the address step size. +//! +//! The \e size parameter is the number of words that will be transferred +//! during a single burst. Possible amounts range from 1 word to 32 words. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred word of a burst. Only signed values from -4096 to 4095 are +//! valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's transfer settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param transferSize is the number of bursts per transfer. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the transfer size and the address step that is +//! made after each burst. +//! +//! The \e transferSize parameter is the number of bursts per transfer. If DMA +//! channel interrupts are enabled, they will occur after this number of bursts +//! have completed. The maximum number of bursts is 65536. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred burst of a transfer. Only signed values from -4096 to 4095 are +//! valid. If a wrap occurs, these step values will be ignored. Wrapping is +//! configured with DMA_configWrap(). +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's wrap settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param srcWrapSize is the number of bursts to be transferred before a wrap +//! of the source address occurs. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destWrapSize is the number of bursts to be transferred before a wrap +//! of the destination address occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the DMA channel's wrap settings. +//! +//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts +//! that are to be transferred before their respective addresses are wrapped. +//! The maximum wrap size is 65536 bursts. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses when the wrap +//! occurs. Only signed values from -4096 to 4095 are valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel trigger and mode. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param trigger is the interrupt source that triggers a DMA transfer. +//! \param config is a bit field of several configuration selections. +//! +//! This function configures the DMA channel's trigger and mode. +//! +//! The \e trigger parameter is the interrupt source that will trigger the +//! start of a DMA transfer. +//! +//! The \e config parameter is the logical OR of the following values: +//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled, +//! the subsequent burst transfers occur without additional event triggers +//! after the first event trigger. If disabled, only one burst transfer is +//! performed per event trigger. +//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled +//! the DMA reinitializes when the transfer count is zero and waits for the +//! next interrupt event trigger. If disabled, the DMA stops and clears the +//! run status bit. +//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects +//! whether the databus width is 16 or 32 bits. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DMA_H diff --git a/gpio_bitfield_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h b/gpio_bitfield_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h new file mode 100644 index 0000000..00e9ac6 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h @@ -0,0 +1,109 @@ +#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ +#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ + + +//***************************************************************************** +// CLB +//***************************************************************************** +#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL +#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL +#define SPI_MODE_MASTER SPI_MODE_CONTROLLER +#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD +#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD + +#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW +#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH + +#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity + + +//***************************************************************************** +// Interrupt +//***************************************************************************** +#define Interrupt_enableMaster Interrupt_enableGlobal +#define Interrupt_disableMaster Interrupt_disableGlobal + + +//***************************************************************************** +// SysCtrl +//***************************************************************************** +#define SysCtl_AccessMaster SysCtl_AccessController +#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA +#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA +#define SysCtl_selectSecMaster SysCtl_selectSecController + + +//***************************************************************************** +// GPIO +//***************************************************************************** +#define GPIO_setMasterCore GPIO_setControllerCore + + + +//***************************************************************************** +// Memcfg +//***************************************************************************** +#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel +#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY +#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1 +#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel + +#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel +#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1 +#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2 +#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel + +//***************************************************************************** +// EMIF +//***************************************************************************** +#define EMIF_MasterSelect EMIF_ControllerSelect +#define EMIF_selectMaster EMIF_selectController +#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG +#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G +#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G +#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2 + + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE +#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE +#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE +#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE +#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET +#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET +#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR +#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET + +#define I2C_initMaster I2C_initController +#define I2C_setSlaveAddress I2C_setTargetAddress +#define I2C_setOwnSlaveAddress I2C_setOwnAddress + + +//***************************************************************************** +// SDFM +//***************************************************************************** +#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt +#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt +#define SDFM_enableMasterFilter SDFM_enableMainFilter +#define SDFM_disableMasterFilter SDFM_disableMainFilter + +#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG + +#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */ diff --git a/gpio_bitfield_cpu1/device/driverlib/ecap.c b/gpio_bitfield_cpu1/device/driverlib/ecap.c new file mode 100644 index 0000000..4a48441 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/ecap.c @@ -0,0 +1,61 @@ +//########################################################################### +// +// FILE: ecap.c +// +// TITLE: C28x ECAP driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ecap.h" + +//***************************************************************************** +// +// ECAP_setEmulationMode +// +//***************************************************************************** +void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to FREE/SOFT bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) | + ((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S)); +} diff --git a/gpio_bitfield_cpu1/device/driverlib/ecap.h b/gpio_bitfield_cpu1/device/driverlib/ecap.h new file mode 100644 index 0000000..577d7a8 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/ecap.h @@ -0,0 +1,1164 @@ +//########################################################################### +// +// FILE: ecap.h +// +// TITLE: C28x ECAP driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef ECAP_H +#define ECAP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ecap_api eCAP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Includes +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ecap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// eCAP minimum and maximum values +// +//***************************************************************************** +#define ECAP_MAX_PRESCALER_VALUE 32U // Maximum Pre-scaler value + +//***************************************************************************** +// +// Values that can be passed to ECAP_enableInterrupt(), +// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as +// the intFlags parameter and returned by ECAP_getInterruptSource(). +// +//***************************************************************************** +//! Event 1 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_1 0x2U +//! Event 2 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_2 0x4U +//! Event 3 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_3 0x8U +//! Event 4 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_4 0x10U +//! Counter overflow ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_OVERFLOW 0x20U +//! Counter equals period ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_PERIOD 0x40U +//! Counter equals compare ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_COMPARE 0x80U + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEmulationMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! TSCTR is stopped on emulation suspension + ECAP_EMULATION_STOP = 0x0U, + //! TSCTR runs until 0 before stopping on emulation suspension + ECAP_EMULATION_RUN_TO_ZERO = 0x1U, + //! TSCTR is not affected by emulation suspension + ECAP_EMULATION_FREE_RUN = 0x2U +}ECAP_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setCaptureMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! eCAP operates in continuous capture mode + ECAP_CONTINUOUS_CAPTURE_MODE = 0U, + //! eCAP operates in one shot capture mode + ECAP_ONE_SHOT_CAPTURE_MODE = 1U +}ECAP_CaptureMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(), +//! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(), +//! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVENT_1 = 0U, //!< eCAP event 1 + ECAP_EVENT_2 = 1U, //!< eCAP event 2 + ECAP_EVENT_3 = 2U, //!< eCAP event 3 + ECAP_EVENT_4 = 3U //!< eCAP event 4 +}ECAP_Events; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setSyncOutMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! sync out on the sync in signal and software force + ECAP_SYNC_OUT_SYNCI = 0x00U, + //! sync out on counter equals period + ECAP_SYNC_OUT_COUNTER_PRD = 0x40U, + //! Disable sync out signal + ECAP_SYNC_OUT_DISABLED = 0x80U +}ECAP_SyncOutMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_APWM_ACTIVE_HIGH = 0x000, //!< APWM is active high + ECAP_APWM_ACTIVE_LOW = 0x400 //!< APWM is active low +}ECAP_APWMPolarity; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVNT_RISING_EDGE = 0U, //!< Rising edge polarity + ECAP_EVNT_FALLING_EDGE = 1U //!< Falling edge polarity +}ECAP_EventPolarity; + +//***************************************************************************** +// +//! \internal +//! Checks eCAP base address. +//! +//! \param base specifies the eCAP module base address. +//! +//! This function determines if an eCAP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool ECAP_isBaseValid(uint32_t base) +{ + return( + (base == ECAP1_BASE) || + (base == ECAP2_BASE) || + (base == ECAP3_BASE) || + (base == ECAP4_BASE) || + (base == ECAP5_BASE) || + (base == ECAP6_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the input prescaler. +//! +//! \param base is the base address of the ECAP module. +//! \param preScalerValue is the pre scaler value for ECAP input +//! +//! This function divides the ECAP input scaler. The pre scale value is +//! doubled inside the module. For example a preScalerValue of 5 will divide +//! the scaler by 10. Use a value of 1 to divide the pre scaler by 1. +//! The \e preScalerValue should be less than \b ECAP_MAX_PRESCALER_VALUE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPrescaler(uint32_t base, + uint16_t preScalerValue) +{ + ASSERT(ECAP_isBaseValid(base)); + + ASSERT(preScalerValue < ECAP_MAX_PRESCALER_VALUE); + + + // + // Write to PRESCALE bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_PRESCALE_M)) | + (preScalerValue << ECAP_ECCTL1_PRESCALE_S)); +} + +//***************************************************************************** +// +//! Sets the Capture event polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! \param polarity is the polarity of the event. +//! +//! This function sets the polarity of a given event. The value of event +//! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to +//! the four available events.For each event the polarity value determines the +//! edge on which the capture is activated. For a rising edge use a polarity +//! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of +//! \b ECAP_EVNT_FALLING_EDGE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPolarity(uint32_t base, + ECAP_Events event, + ECAP_EventPolarity polarity) +{ + + uint16_t shift; + + ASSERT(ECAP_isBaseValid(base)); + + shift = ((uint16_t)event) << 1U; + + + // + // Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL + // + HWREGH(base + ECAP_O_ECCTL1) = + (HWREGH(base + ECAP_O_ECCTL1) & ~(1U << shift)) | + ((uint16_t)polarity << shift); +} + +//***************************************************************************** +// +//! Sets the capture mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the capture mode. +//! \param event is the event number at which the counter stops or wraps. +//! +//! This function sets the eCAP module to a continuous or one-shot mode. +//! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or +//! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode +//! respectively. +//! +//! The value of event determines the event number at which the counter stops +//! (in one-shot mode) or the counter wraps (in continuous mode). The value of +//! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding +//! to the valid event numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setCaptureMode(uint32_t base, + ECAP_CaptureMode mode, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to CONT/ONESHT + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_CONT_ONESHT)) | + (uint16_t)mode); + + // + // Write to STOP_WRAP + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_STOP_WRAP_M)) | + (((uint16_t)event) << ECAP_ECCTL2_STOP_WRAP_S )); +} + +//***************************************************************************** +// +//! Re-arms the eCAP module. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function re-arms the eCAP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_reArm(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to RE-ARM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_REARM; +} + +//***************************************************************************** +// +//! Enables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be enabled. +//! +//! This function sets and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + + // + // Set bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be disabled. +//! +//! This function clears and disables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableInterrupt(uint32_t base, + uint16_t intFlags) +{ + + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Clear bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) &= ~intFlags; +} + +//***************************************************************************** +// +//! Returns the interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP interrupt flag. The following are valid +//! interrupt sources corresponding to the eCAP interrupt flag. +//! +//! \return Returns the eCAP interrupt that has occurred. The following are +//! valid return values. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \note - User can check if a combination of various interrupts have occurred +//! by ORing the above return values. +// +//***************************************************************************** +static inline uint16_t ECAP_getInterruptSource(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of ECFLG register + // + return(HWREGH(base + ECAP_O_ECFLG) & 0xFEU); +} + +//***************************************************************************** +// +//! Returns the Global interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP Global interrupt flag. +//! +//! \return Returns true if there is a global eCAP interrupt, false otherwise. +// +//***************************************************************************** +static inline bool ECAP_getGlobalInterruptStatus(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of Global interrupt bit + // + return((HWREGH(base + ECAP_O_ECFLG) & 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Clears interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function clears eCAP interrupt flags. The following are valid +//! interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + // + // Write to ECCLR register + // + HWREGH(base + ECAP_O_ECCLR) = intFlags; +} + +//***************************************************************************** +// +//! Clears global interrupt flag +//! +//! \param base is the base address of the ECAP module. +//! +//! This function clears the global interrupt bit. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearGlobalInterrupt(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to INT bit + // + HWREGH(base + ECAP_O_ECCLR) = ECAP_ECCLR_INT; +} + +//***************************************************************************** +// +//! Forces interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function forces and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_forceInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Write to ECFRC register + // + HWREGH(base + ECAP_O_ECFRC) = intFlags; +} + +//***************************************************************************** +// +//! Sets eCAP in Capture mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCaptureMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Sets eCAP in APWM mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in APWM mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableAPWMMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Enables counter reset on an event. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function enables the base timer, TSCTR, to be reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) |= 1U << ((2U * (uint16_t)event) + 1U); +} + +//***************************************************************************** +// +//! Disables counter reset on events. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function disables the base timer, TSCTR, from being reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) &= ~(1U << ((2U * (uint16_t)event) + 1U)); +} + +//***************************************************************************** +// +//! Enables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) |= ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Disables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Sets a phase shift value count. +//! +//! \param base is the base address of the ECAP module. +//! \param shiftCount is the phase shift value. +//! +//! This function writes a phase shift value to be loaded into the main time +//! stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CTRPHS + // + HWREG(base + ECAP_O_CTRPHS) = shiftCount; +} + +//***************************************************************************** +// +//! Enable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Disable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Load time stamp counter +//! +//! \param base is the base address of the ECAP module. +//! +//! This function forces the value in the phase shift counter register to be +//! loaded into Time stamp counter register. +//! Make sure to enable loading of Time stamp counter by calling +//! ECAP_enableLoadCounter() function before calling this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_loadCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SWSYNC + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SWSYNC; +} + +//***************************************************************************** +// +//! Configures Sync out signal mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the sync out mode. +//! +//! This function sets the sync out mode. Valid parameters for mode are: +//! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event. +//! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period. +//! - ECAP_SYNC_OUT_DISABLED - Disable sync out. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setSyncOutMode(uint32_t base, + ECAP_SyncOutMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCO_SEL + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_SYNCO_SEL_M)) | + (uint16_t)mode); +} + +//***************************************************************************** +// +//! Stops Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function stops the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_stopCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Starts Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function starts the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_startCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Set eCAP APWM polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param polarity is the polarity of APWM +//! +//! This function sets the polarity of the eCAP in APWM mode. Valid inputs for +//! polarity are: +//! - ECAP_APWM_ACTIVE_HIGH - For active high. +//! - ECAP_APWM_ACTIVE_LOW - For active low. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPolarity(uint32_t base, + ECAP_APWMPolarity polarity) +{ + ASSERT(ECAP_isBaseValid(base)); + + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & ~ECAP_ECCTL2_APWMPOL) | + (uint16_t)polarity); +} + +//***************************************************************************** +// +//! Set eCAP APWM period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the period count for APWM. +//! +//! This function sets the period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP1 + // + HWREG(base + ECAP_O_CAP1) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the on or off time count of the APWM waveform depending +//! on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity(), is active high then compareCount determines the on +//! time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP2 + // + HWREG(base + ECAP_O_CAP2) = compareCount; +} + +//***************************************************************************** +// +//! Load eCAP APWM shadow period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the shadow period count for APWM. +//! +//! This function sets the shadow period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowPeriod(uint32_t base, + uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP3 + // + HWREG(base + ECAP_O_CAP3) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM shadow on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the shadow on or off time count of the APWM waveform +//! depending on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity() , is active high then compareCount determines the +//! on time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowCompare(uint32_t base, + uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP4 + // + HWREG(base + ECAP_O_CAP4) = compareCount; +} + +//***************************************************************************** +// +//! Returns the time base counter value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the time base counter value. +//! +//! \return Returns the time base counter value. +// +//***************************************************************************** +static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Read the Time base counter value + // + return(HWREG(base + ECAP_O_TSCTR)); +} + +//***************************************************************************** +// +//! Returns event time stamp. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! +//! This function returns the current time stamp count of the given event. +//! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return Event time stamp value or 0 if \e event is invalid. +// +//***************************************************************************** +static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event) +{ + uint32_t count; + + ASSERT(ECAP_isBaseValid(base)); + + + switch(event) + { + case ECAP_EVENT_1: + + // + // Read CAP1 register + // + count = HWREG(base + ECAP_O_CAP1); + break; + + case ECAP_EVENT_2: + // + // Read CAP2 register + // + count = HWREG(base + ECAP_O_CAP2); + break; + + case ECAP_EVENT_3: + + // + // Read CAP3 register + // + count = HWREG(base + ECAP_O_CAP3); + break; + + case ECAP_EVENT_4: + + // + // Read CAP4 register + // + count = HWREG(base + ECAP_O_CAP4); + break; + + default: + + // + // Invalid event parameter + // + count = 0U; + break; + } + + return(count); +} + +//***************************************************************************** +// +//! Configures emulation mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the emulation mode. +//! +//! This function configures the eCAP counter, TSCTR, to the desired emulation +//! mode when emulation suspension occurs. Valid inputs for mode are: +//! - ECAP_EMULATION_STOP - Counter is stopped immediately. +//! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0. +//! - ECAP_EMULATION_FREE_RUN - Counter is not affected. +//! +//! \return None. +// +//***************************************************************************** +extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ECAP_H diff --git a/gpio_bitfield_cpu1/device/driverlib/emif.c b/gpio_bitfield_cpu1/device/driverlib/emif.c new file mode 100644 index 0000000..a862104 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/emif.c @@ -0,0 +1,46 @@ +//########################################################################### +// +// FILE: emif.c +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "emif.h" + diff --git a/gpio_bitfield_cpu1/device/driverlib/emif.h b/gpio_bitfield_cpu1/device/driverlib/emif.h new file mode 100644 index 0000000..7177421 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/emif.h @@ -0,0 +1,1369 @@ +//########################################################################### +// +// FILE: emif.h +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EMIF_H +#define EMIF_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup emif_api EMIF +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_emif.h" +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines to specify access protection to EMIF_setAccessProtection(). +// +//***************************************************************************** +//! This flag is used to specify whether CPU fetches are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_FETCHPROT MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 + +//! This flag is used to specify whether CPU writes are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_CPUWRPROT MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 + +//! This flag is used to specify whether DMA writes are allowed/blocked +//! for EMIF. It is valid only for EMIF1 instance. +#define EMIF_ACCPROT0_DMAWRPROT MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF1ACCPROT0 register that aren't +// associated with EMIF1 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF1 \ + ((uint16_t)MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1) + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF2ACCPROT0 register that aren't +// associated with EMIF2 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF2 \ + ((uint16_t)MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 |\ + (uint16_t)MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2) + +//***************************************************************************** +// +// Define to mask out the bits in the ASYNC_CSx_CR register that +// aren't associated with async configuration. +// +//***************************************************************************** +#define EMIF_ASYNC_CS_CR_MASK ((uint32_t)EMIF_ASYNC_CS2_CR_R_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_TA_M) + +//***************************************************************************** +// +// Define to mask out the bits in the INT_MSK register that aren't associated +// with interrupts. +// +//***************************************************************************** +#define EMIF_ASYNC_INT_MASK ((uint16_t)EMIF_INT_MSK_SET_AT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_LT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_WR_MASK_SET_M) + +//***************************************************************************** +// +// Defines to specify interrupt sources to EMIF_enableAsyncInterrupt() and +// EMIF_disableAsyncInterrupt().Three interrupts are available for asynchronous +// memory interface: Masked Asyncronous Timeout(AT) to indicate EMxWAIT signal +// remains active even after maximum wait cycles are reached. Masked Line Trap +// (LT) to indicate illegal memory access or invalid cache line size. +// Masked Wait Rise(WR) to indicate rising edge on EMxWAIT is detected. +// +//***************************************************************************** +//! This flag is used to allow/block EMIF to generate Masked Asynchronous +//! Timeout interrupt. +#define EMIF_ASYNC_INT_AT EMIF_INT_MSK_SET_AT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Line Trap +//! interrupt. +#define EMIF_ASYNC_INT_LT EMIF_INT_MSK_SET_LT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Wait Rise +//! interrupt. +#define EMIF_ASYNC_INT_WR EMIF_INT_MSK_SET_WR_MASK_SET_M + +//***************************************************************************** +// +// Define for key for EMIF1MSEL register that enables the register write. +// +//***************************************************************************** +#define EMIF_MSEL_KEY 0x93A5CE70U + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_CR register that aren't +// associated with SDRAM configuration parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_CR_MASK ((uint32_t)EMIF_SDRAM_CR_PAGESIGE_M | \ + (uint32_t)EMIF_SDRAM_CR_IBANK_M | \ + (uint32_t)EMIF_SDRAM_CR_BIT_11_9_LOCK | \ + (uint32_t)EMIF_SDRAM_CR_CL_M | \ + (uint32_t)EMIF_SDRAM_CR_NM | \ + (uint32_t)EMIF_SDRAM_CR_SR) + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_TR register that aren't +// associated with SDRAM timings parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_TR_MASK ((uint32_t)EMIF_SDRAM_TR_T_RRD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RC_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RAS_M | \ + (uint32_t)EMIF_SDRAM_TR_T_WR_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RCD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RP_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RFC_M) + +//***************************************************************************** +// +//! Values that can be passed to EMIF_setAsyncMode(), +//! EMIF_setAsyncTimingParams(), EMIF_setAsyncDataBusWidth(), +//! EMIF_enableAsyncExtendedWait() and EMIF_disableAsyncExtendedWait() +//! as the \e offset parameter. Three chip selects are available in +//! asynchronous memory interface so there are three configuration registers +//! available for each EMIF instance. All the three chip select offsets are +//! valid for EMIF1 while only EMIF_ASYNC_CS2_OFFSET is valid for EMIF2. +// +//***************************************************************************** +typedef enum +{ + EMIF_ASYNC_CS2_OFFSET = EMIF_O_ASYNC_CS2_CR, //! It is valid only for EMIF1 instance and not for EMIF2 instance. +//! Valid value for configBase parameter is EMIF1CONFIG_BASE. Valid +//! values for select parameter can be \e EMIF_CONTROLLER_CPU1_NG, +//! \e EMIF_CONTROLLER_CPU1_G, \e EMIF_CONTROLLER_CPU2_G or +//! \e EMIF_CONTROLLER_CPU1_NG2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_selectController(uint32_t configBase, EMIF_ControllerSelect select) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase)); + + // + // Sets the bits that enables EMIF1 controller selection. + // + EALLOW; + HWREG(configBase + MEMCFG_O_EMIF1MSEL) = (EMIF_MSEL_KEY | (uint32_t)select); + EDIS; +} + +//***************************************************************************** +// +//! Sets the access protection. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! \param access is the required access protection configuration. +//! +//! This function sets the access protection for an EMIF instance from CPU +//! and DMA. The \e access parameter can be any of \b EMIF_ACCPROT0_FETCHPROT, +//! \b EMIF_ACCPROT0_CPUWRPROT \b EMIF_ACCPROT0_DMAWRPROT values or their +//! combination. EMIF_ACCPROT0_DMAWRPROT value is valid as access parameter +//! for EMIF1 instance only . +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAccessProtection(uint32_t configBase, uint16_t access) +{ + uint16_t temp; + // + // Check the arguments. + // + + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + if(configBase == EMIF1CONFIG_BASE) + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF1); + temp = EMIF_ACCPROT0_MASK_EMIF1; + } + else + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF2); + temp = EMIF_ACCPROT0_MASK_EMIF2; + } + + // + // Sets the bits that enables access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) = + (HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) & ~(temp)) | access; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function commits the access protection for an EMIF instance from +//! CPU & DMA. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_commitAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that commits access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1COMMIT) |= + MEMCFG_EMIF1COMMIT_COMMIT_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Locks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function locks the write to access configuration fields i.e +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_lockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that locks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) |= MEMCFG_EMIF1LOCK_LOCK_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function unlocks the write to access configuration fields such as +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_unlockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that unlocks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) &= + ~((uint16_t)MEMCFG_EMIF1LOCK_LOCK_EMIF1); + EDIS; +} + +//***************************************************************************** +// +// Prototypes for Asynchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Selects the asynchronous mode of operation. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param mode is the desired mode of operation for external memory. +//! +//! +//! This function sets the mode of operation for asynchronous memory +//! between Normal or Strobe mode. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values for param \e mode can be \e EMIF_ASYNC_STROBE_MODE or +//! \e EMIF_ASYNC_NORMAL_MODE. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMode(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncMode mode) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async mode of operation. + // + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) + & ~((uint32_t)EMIF_ASYNC_CS2_CR_SS)) + | (uint32_t)mode; +} + +//***************************************************************************** +// +//! Enables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of the +//! EMIF instance +//! +//! This function enables the extended wait mode for an asynchronous +//! external memory.Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that enables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) | + EMIF_ASYNC_CS2_CR_EW; +} + +//***************************************************************************** +// +//! Disables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! This function disables the extended wait mode for an asynchronous external +//! memory.Valid values for param \e offset can be \e EMIF_ASYNC_CS2_OFFSET, +//! \e EMIF_ASYNC_CS3_OFFSET & \e EMIF_ASYNC_C43_OFFSET for EMIF1 and +//! \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) + { + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that disables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) & + ~((uint32_t)EMIF_ASYNC_CS2_CR_EW); +} + +//***************************************************************************** +// +//! Sets the wait polarity. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param polarity is desired wait polarity. +//! +//! This function sets the wait polarity for an asynchronous external memory. +//! Valid values for param \e polarity can be \e EMIF_ASYNC_WAIT_POLARITY_LOW +//! or \e EMIF_ASYNC_WAIT_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncWaitPolarity(uint32_t base, EMIF_AsyncWaitPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the polarity for async extended wait mode. + // + HWREG(base + EMIF_O_ASYNC_WCCR) = (HWREG(base + EMIF_O_ASYNC_WCCR) + & ~((uint32_t)EMIF_ASYNC_WCCR_WP0)) + | (uint32_t)polarity; +} + +//***************************************************************************** +// +//! Sets the Maximum Wait Cycles. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param value is the desired maximum wait cycles. +//! +//! This function sets the maximum wait cycles for extended asynchronous cycle. +//! Valid values for parameter \e value lies b/w 0x0U-0xFFU or 0-255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMaximumWaitCycles(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(value <= (EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)); + + // + // Sets the bit that enables extended wait mode. + // + HWREGH(base + EMIF_O_ASYNC_WCCR) = (HWREGH(base + EMIF_O_ASYNC_WCCR) + & ~((uint16_t)EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)) + | value; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Memory Timing Characteristics. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param tParam is the desired timing parameters. +//! +//! This function sets timing characteristics for an external asynchronous +//! memory to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET and +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 & EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncTimingParams(uint32_t base, EMIF_AsyncCSOffset offset, + const EMIF_AsyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory timing parameters. + // + temp = (tParam->turnArnd << EMIF_ASYNC_CS2_CR_TA_S) | + (tParam->rHold << EMIF_ASYNC_CS2_CR_R_HOLD_S) | + (tParam->rStrobe << EMIF_ASYNC_CS2_CR_R_STROBE_S) | + (tParam->rSetup << EMIF_ASYNC_CS2_CR_R_SETUP_S) | + (tParam->wHold << EMIF_ASYNC_CS2_CR_W_HOLD_S) | + (tParam->wStrobe << EMIF_ASYNC_CS2_CR_W_STROBE_S) | + (tParam->wSetup << EMIF_ASYNC_CS2_CR_W_SETUP_S); + + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) & + ~EMIF_ASYNC_CS_CR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Data Bus Width. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param width is the data bus width of the memory. +//! +//! This function sets the data bus size for an external asynchronous memory +//! to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values of param \e width can be \e EMIF_ASYNC_DATA_WIDTH_8, +//! \e EMIF_ASYNC_DATA_WIDTH_16 or \e EMIF_ASYNC_DATA_WIDTH_32. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncDataBusWidth(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncDataWidth width) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory data bus width. + // + HWREGH(base + (uint32_t)offset) = (HWREGH(base + (uint32_t)offset) + & ~((uint16_t)EMIF_ASYNC_CS2_CR_ASIZE_M)) + | (uint32_t)width; +} + +//***************************************************************************** +// +// Prototypes for Interrupt Handling +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for desired interrupts. +//! +//! This function enables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or their +//! combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that enables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_SET) = intFlags; +} + +//***************************************************************************** +// +//! Disables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for interrupts to be disabled. +//! +//! This function disables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or +//! their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that disables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_CLR) = intFlags; + +} + +//***************************************************************************** +// +//! Gets the interrupt status. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function gets the interrupt status for an EMIF instance. +//! +//! \return Returns the current interrupt status. +// +//***************************************************************************** +static inline uint16_t +EMIF_getAsyncInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets the async memory interrupt status. + // + return(HWREGH(base + EMIF_O_INT_MSK) & EMIF_ASYNC_INT_MASK); +} + +//***************************************************************************** +// +//! Clears the interrupt status for an EMIF instance. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for the interrupt status to be cleared. +//! +//! This function clears the interrupt status for an EMIF instance. +//! The \e intFlags parameter can be any of \b EMIF_INT_MSK_SET_AT_MASK_SET, +//! \b EMIF_INT_MSK_SET_LT_MASK_SET, or \b EMIF_INT_MSK_SET_WR_MASK_SET_M +//! values or their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_clearAsyncInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bit that clears desired async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK) = intFlags; +} + +//***************************************************************************** +// +// Prototypes for Synchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Sets the Synchronous Memory Timing Parameters. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tParam is parameters from memory datasheet in \e ns. +//! +//! This function sets the timing characteristics for an external +//! synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncTimingParams(uint32_t base, const EMIF_SyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets sync memory timing parameters. + // + temp = ((tParam->tRrd << EMIF_SDRAM_TR_T_RRD_S) + & EMIF_SDRAM_TR_T_RRD_M) + | ((tParam->tRc << EMIF_SDRAM_TR_T_RC_S) + & EMIF_SDRAM_TR_T_RC_M) + | ((tParam->tRas << EMIF_SDRAM_TR_T_RAS_S) + & EMIF_SDRAM_TR_T_RAS_M) + | ((tParam->tWr << EMIF_SDRAM_TR_T_WR_S) + & EMIF_SDRAM_TR_T_WR_M) + | ((tParam->tRcd << EMIF_SDRAM_TR_T_RCD_S) + & EMIF_SDRAM_TR_T_RCD_M) + | ((tParam->tRp << EMIF_SDRAM_TR_T_RP_S) + & EMIF_SDRAM_TR_T_RP_M) + | ((tParam->tRfc << EMIF_SDRAM_TR_T_RFC_S) + & EMIF_SDRAM_TR_T_RFC_M); + + HWREG(base + EMIF_O_SDRAM_TR) = (HWREG(base + EMIF_O_SDRAM_TR) & + ~EMIF_SYNC_SDRAM_TR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the SDRAM Self Refresh Exit Timing. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tXs is the desired timing value. +//! +//! This function sets the self refresh exit timing for an external +//! synchronous memory to be interfaced. tXs values must lie between +//! 0x0U-0x1FU or 0-31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncSelfRefreshExitTmng(uint32_t base, uint16_t tXs) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(tXs <= EMIF_SDR_EXT_TMNG_T_XS_M); + + // + // Sets the self refresh exit timing for sync memory. + // + HWREGH(base + EMIF_O_SDR_EXT_TMNG) = (HWREGH(base + EMIF_O_SDR_EXT_TMNG) + & ~((uint16_t)EMIF_SDR_EXT_TMNG_T_XS_M)) + | tXs; +} + +//***************************************************************************** +// +//! Sets the SDR Refresh Rate. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param refRate is the refresh rate. +//! +//! This function sets the refresh rate for an external synchronous memory +//! to be interfaced. Valid values for refRate lies b/w 0x0U-0x1FFFU or +//! 0-8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncRefreshRate(uint32_t base, uint16_t refRate) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(refRate <= EMIF_SDRAM_RCR_REFRESH_RATE_M); + + // + // Sets the sync memory refresh rate. + // + HWREGH(base + EMIF_O_SDRAM_RCR) = (HWREGH(base + EMIF_O_SDRAM_RCR) + & (~(uint16_t)EMIF_SDRAM_RCR_REFRESH_RATE_M)) + | refRate; +} + +//***************************************************************************** +// +//! Sets the Synchronous Memory configuration parameters. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param config is the desired configuration parameters. +//! +//! This function sets configuration parameters like CL, NM, IBANK +//! and PAGESIZE for an external synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncMemoryConfig(uint32_t base, const EMIF_SyncConfig *config) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the sync memory configuration bits. + // + temp = ((uint32_t)config->casLatency | (uint32_t)config->iBank | + (uint32_t)config->narrowMode | (uint32_t)config->pageSize); + + HWREG(base + EMIF_O_SDRAM_CR) = (HWREG(base + EMIF_O_SDRAM_CR) & + ~EMIF_SYNC_SDRAM_CR_MASK) | temp; +} + +//***************************************************************************** +// +// Prototypes for EMIF Low Power Modes +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_SR; +} + +//***************************************************************************** +// +//! Disables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_SR); +} + +//***************************************************************************** +// +//! Enables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function Enables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PD; +} + +//***************************************************************************** +// +//! Disables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PD); +} + +//***************************************************************************** +// +//! Enables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PDWR; +} + +//***************************************************************************** +// +//! Disables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PDWR); +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of SDRAM accesses +//! from a controller(CPUx/CPUx.DMA). +//! +//! \return \e Returns total number of accesses to SDRAM. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_AR)); + +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses which require activate command. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of accesses to SDRAM which +//! require activate command. +//! +//!\return \e Returns total number of accesses to SDRAM which require activate. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalActivateAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory which requires activate command. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_ACTR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EMIF_H diff --git a/gpio_bitfield_cpu1/device/driverlib/epwm.c b/gpio_bitfield_cpu1/device/driverlib/epwm.c new file mode 100644 index 0000000..76e09bb --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/epwm.c @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: epwm.c +// +// TITLE: C28x EPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "epwm.h" + +//***************************************************************************** +// +// EPWM_setEmulationMode +// +//***************************************************************************** +void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode) +{ + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to FREE_SOFT bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & (~EPWM_TBCTL_FREE_SOFT_M)) | + ((uint16_t)emulationMode << EPWM_TBCTL_FREE_SOFT_S)); +} + +//***************************************************************************** +// +// EPWM_configureSignal +// +//***************************************************************************** +void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams) +{ + float32_t tbClkInHz = 0.0F; + uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U; + + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Valid values in the function for TBCTR Mode are UP, DOWN + // and UP-DOWN count. + // + ASSERT((uint16_t)signalParams->tbCtrMode <= 2U); + + // + // Configure EPWM clock Divider + // + SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv); + + // + // Configure Time Base counter Clock + // + EPWM_setClockPrescaler(base, signalParams->tbClkDiv, + signalParams->tbHSClkDiv); + + // + // Configure Time Base Counter Mode + // + EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode); + + // + // Calculate TBCLK, TBPRD and CMPx values to be configured for + // achieving desired signal + // + tbClkInHz = ((float32_t)signalParams->sysClkInHz / + (float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv + + (uint16_t)signalParams->tbClkDiv))); + + if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4) + { + tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv); + } + else + { + tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv); + } + + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)(signalParams->dutyValA * + (float32_t)(tbPrdVal + 1U)); + cmpBVal = (uint16_t)(signalParams->dutyValB * + (float32_t)(tbPrdVal + 1U)); + } + else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValA * (float32_t)(tbPrdVal + 1U))); + cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValB * (float32_t)(tbPrdVal + 1U))); + } + else + { + tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz)); + cmpAVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValA * + (float32_t)tbPrdVal))) + 0.5f); + cmpBVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValB * + (float32_t)tbPrdVal))) + 0.5f); + } + + // + // Configure TBPRD value + // + EPWM_setTimeBasePeriod(base, tbPrdVal); + + // + // Default Configurations. + // + EPWM_disablePhaseShiftLoad(base); + EPWM_setPhaseShift(base, 0U); + EPWM_setTimeBaseCounter(base, 0U); + + // + // Setup shadow register load on ZERO + // + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_A, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_B, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + // + // Set Compare values + // + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, + cmpAVal); + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, + cmpBVal); + + // + // Set actions for ePWMxA & ePWMxB + // + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + + } + } + else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } + else + { + // + // Clear PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/epwm.h b/gpio_bitfield_cpu1/device/driverlib/epwm.h new file mode 100644 index 0000000..ada9b80 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/epwm.h @@ -0,0 +1,7496 @@ +//############################################################################# +// +// FILE: epwm.h +// +// TITLE: C28x EPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef EPWM_H +#define EPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup epwm_api ePWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_epwm.h" +#include "cpu.h" +#include "debug.h" +#include "sysctl.h" + + +// +// Time Base Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setEmulationMode() as the +//! \e emulationMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Stop after next Time Base counter increment or decrement + EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0, + //! Stop when counter completes whole cycle + EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1, + //! Free run + EPWM_EMULATION_FREE_RUN = 2 +} EPWM_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCountModeAfterSync() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0, //!< Count down after sync event + EPWM_COUNT_MODE_UP_AFTER_SYNC = 1 //!< Count up after sync event +} EPWM_SyncCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_CLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_CLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_CLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_CLOCK_DIVIDER_8 = 3, //!< Divide clock by 8 + EPWM_CLOCK_DIVIDER_16 = 4, //!< Divide clock by 16 + EPWM_CLOCK_DIVIDER_32 = 5, //!< Divide clock by 32 + EPWM_CLOCK_DIVIDER_64 = 6, //!< Divide clock by 64 + EPWM_CLOCK_DIVIDER_128 = 7 //!< Divide clock by 128 +} EPWM_ClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e highSpeedPrescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_HSCLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_HSCLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_HSCLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_HSCLOCK_DIVIDER_6 = 3, //!< Divide clock by 6 + EPWM_HSCLOCK_DIVIDER_8 = 4, //!< Divide clock by 8 + EPWM_HSCLOCK_DIVIDER_10 = 5, //!< Divide clock by 10 + EPWM_HSCLOCK_DIVIDER_12 = 6, //!< Divide clock by 12 + EPWM_HSCLOCK_DIVIDER_14 = 7 //!< Divide clock by 14 +} EPWM_HSClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setSyncOutPulseMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Sync pulse is generated by software + EPWM_SYNC_OUT_PULSE_ON_SOFTWARE = 0, + //! Sync pulse is passed from EPWMxSYNCIN + EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN = 0, + //! Sync pulse is generated when time base counter equals zero + EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO = 1, + //! Sync pulse is generated when time base counter equals compare B value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B = 2, + //! Sync pulse is disabled + EPWM_SYNC_OUT_PULSE_DISABLED = 4, + //! Sync pulse is generated when time base counter equals compare C value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C = 5, + //! Sync pulse is generated when time base counter equals compare D value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D = 6 +} EPWM_SyncOutPulseMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setPeriodLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! PWM Period register access is through shadow register + EPWM_PERIOD_SHADOW_LOAD = 0, + //! PWM Period register access is directly + EPWM_PERIOD_DIRECT_LOAD = 1 +} EPWM_PeriodLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTimeBaseCounterMode() as the +//! \e counterMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_MODE_UP = 0, //!< Up - count mode + EPWM_COUNTER_MODE_DOWN = 1, //!< Down - count mode + EPWM_COUNTER_MODE_UP_DOWN = 2, //!< Up - down - count mode + EPWM_COUNTER_MODE_STOP_FREEZE = 3 //!< Stop - Freeze counter +} EPWM_TimeBaseCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectPeriodLoadEvent() as the +//! \e shadowLoadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow to active load occurs when time base counter reaches 0 + EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0, + //! Shadow to active load occurs when time base counter reaches 0 and a + //! SYNC occurs + EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1, + //! Shadow to active load occurs only when a SYNC occurs + EPWM_SHADOW_LOAD_MODE_SYNC = 2 +} EPWM_PeriodShadowLoadMode; + +//***************************************************************************** +// +// Values that can be returned by the EPWM_getTimeBaseCounterDirection() +// +//***************************************************************************** +//! Time base counter is counting up +//! +#define EPWM_TIME_BASE_STATUS_COUNT_UP 1U +//! Time base counter is counting down +//! +#define EPWM_TIME_BASE_STATUS_COUNT_DOWN 0U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e epwmLink +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_WITH_EPWM_1 = 0, //!< link current ePWM with ePWM1 + EPWM_LINK_WITH_EPWM_2 = 1, //!< link current ePWM with ePWM2 + EPWM_LINK_WITH_EPWM_3 = 2, //!< link current ePWM with ePWM3 + EPWM_LINK_WITH_EPWM_4 = 3, //!< link current ePWM with ePWM4 + EPWM_LINK_WITH_EPWM_5 = 4, //!< link current ePWM with ePWM5 + EPWM_LINK_WITH_EPWM_6 = 5, //!< link current ePWM with ePWM6 + EPWM_LINK_WITH_EPWM_7 = 6, //!< link current ePWM with ePWM7 + EPWM_LINK_WITH_EPWM_8 = 7, //!< link current ePWM with ePWM8 + EPWM_LINK_WITH_EPWM_9 = 8, //!< link current ePWM with ePWM9 + EPWM_LINK_WITH_EPWM_10 = 9, //!< link current ePWM with ePWM10 + EPWM_LINK_WITH_EPWM_11 = 10, //!< link current ePWM with ePWM11 + EPWM_LINK_WITH_EPWM_12 = 11 //!< link current ePWM with ePWM12 +} EPWM_CurrentLink; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e linkComp +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_TBPRD = 0U, //!< link TBPRD registers + EPWM_LINK_COMP_A = 4U, //!< link COMPA registers + EPWM_LINK_COMP_B = 8U, //!< link COMPB registers + EPWM_LINK_COMP_C = 12U, //!< link COMPC registers + EPWM_LINK_COMP_D = 16U, //!< link COMPD registers + EPWM_LINK_GLDCTL2 = 28U //!< link GLDCTL2 registers +} EPWM_LinkComponent; + +// +// Counter Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to the EPWM_getCounterCompareShadowStatus(), +//! EPWM_setCounterCompareValue(), EPWM_setCounterCompareShadowLoadMode(), +//! EPWM_disableCounterCompareShadowLoadMode() +//! as the \e compModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_COMPARE_A = 0, //!< Counter compare A + EPWM_COUNTER_COMPARE_B = 2, //!< Counter compare B + EPWM_COUNTER_COMPARE_C = 5, //!< Counter compare C + EPWM_COUNTER_COMPARE_D = 7 //!< Counter compare D +} EPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCounterCompareShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_COMP_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_COMP_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_COMP_LOAD_ON_SYNC_ONLY = 8 +} EPWM_CounterCompareLoadMode; + +// +// Action Qualifier Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() and +//! EPWM_disableActionQualifierShadowLoadMode() as the \e aqModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_ACTION_QUALIFIER_A = 0, //!< Action Qualifier A + EPWM_ACTION_QUALIFIER_B = 2 //!< Action Qualifier B +} EPWM_ActionQualifierModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_AQ_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_AQ_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_AQ_LOAD_ON_SYNC_ONLY = 8 +} EPWM_ActionQualifierLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierT1TriggerSource() and +//! EPWM_setActionQualifierT2TriggerSource() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0, //!< Digital compare event A 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1, //!< Digital compare event A 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2, //!< Digital compare event B 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3, //!< Digital compare event B 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4, //!< Trip zone 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5, //!< Trip zone 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6, //!< Trip zone 3 + EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7 //!< ePWM sync +} EPWM_ActionQualifierTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierAction() as the \e +//! event parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0, + //! Time base counter equals period + EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2, + //! Time base counter up equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4, + //! Time base counter down equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6, + //! Time base counter up equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8, + //! Time base counter down equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10, + //! T1 event on count up + EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1, + //! T1 event on count down + EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3, + //! T2 event on count up + EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5, + //! T2 event on count down + EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7 +} EPWM_ActionQualifierOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierSWAction(), +//! EPWM_setActionQualifierAction() as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_NO_CHANGE = 0, //!< No change in the output pins + EPWM_AQ_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_OUTPUT_HIGH = 2, //!< Set output pins to High + EPWM_AQ_OUTPUT_TOGGLE = 3 //!< Toggle the output pins +} EPWM_ActionQualifierOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceAction() +//! as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_SW_DISABLED = 0, //!< Software forcing disabled + EPWM_AQ_SW_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_SW_OUTPUT_HIGH = 2 //!< Set output pins to High +} EPWM_ActionQualifierSWOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierActionComplete() +//! as the \e action parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0, + //! Time base counter equals zero and set output pins to low + EPWM_AQ_OUTPUT_LOW_ZERO = 0x1, + //! Time base counter equals zero and set output pins to high + EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2, + //! Time base counter equals zero and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3, + //! Time base counter equals period and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0, + //! Time base counter equals period and set output pins to low + EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4, + //! Time base counter equals period and set output pins to high + EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8, + //! Time base counter equals period and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC, + //! Time base counter up equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00, + //! Time base counter up equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10, + //! Time base counter up equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20, + //! Time base counter up equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30, + //! Time base counter down equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00, + //! Time base counter down equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40, + //! Time base counter down equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80, + //! Time base counter down equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0, + //! Time base counter up equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000, + //! Time base counter up equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100, + //! Time base counter up equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200, + //! Time base counter up equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300, + //! Time base counter down equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000, + //! Time base counter down equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400, + //! Time base counter down equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800, + //! Time base counter down equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00 +} EPWM_ActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to +//! EPWM_setAdditionalActionQualifierActionComplete() as the \e action +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! T1 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0, + //! T1 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1, + //! T1 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2, + //! T1 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3, + //! T1 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0, + //! T1 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4, + //! T1 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8, + //! T1 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC, + //! T2 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00, + //! T2 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10, + //! T2 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20, + //! T2 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30, + //! T2 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00, + //! T2 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40, + //! T2 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80, + //! T2 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0 +} EPWM_AdditionalActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_forceActionQualifierSWAction(), +//! EPWM_setActionQualifierSWAction(), EPWM_setActionQualifierAction() +//! EPWM_setActionQualifierContSWForceAction() as the \e epwmOutput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_A = 0, //!< ePWMxA output + EPWM_AQ_OUTPUT_B = 2 //!< ePWMxB output +} EPWM_ActionQualifierOutputModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceShadowMode() +//! as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow mode load when counter equals zero + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0, + //! Shadow mode load when counter equals period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1, + //! Shadow mode load when counter equals zero or period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! No shadow load mode. Immediate mode only. + EPWM_AQ_SW_IMMEDIATE_LOAD = 3 +} EPWM_ActionQualifierContForce; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandOutputSwapMode() +//! as the \e output parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_OUTPUT_A = 1, //!< DB output is ePWMA + EPWM_DB_OUTPUT_B = 0 //!< DB output is ePWMB +} EPWM_DeadBandOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity(), +//! EPWM_setDeadBandDelayMode() as the \e delayMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_RED = 1, //!< DB RED (Rising Edge Delay) mode + EPWM_DB_FED = 0 //!< DB FED (Falling Edge Delay) mode +} EPWM_DeadBandDelayMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity as the +//! \e polarity parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_POLARITY_ACTIVE_HIGH = 0, //!< DB polarity is not inverted + EPWM_DB_POLARITY_ACTIVE_LOW = 1 //!< DB polarity is inverted +} EPWM_DeadBandPolarity; + +//***************************************************************************** +// +// Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(), +// EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter. +// +//***************************************************************************** +//! Input signal is ePWMA +//! +#define EPWM_DB_INPUT_EPWMA 0U +//! Input signal is ePWMB +//! +#define EPWM_DB_INPUT_EPWMB 1U +//! Input signal is the output of Rising Edge delay +//! +#define EPWM_DB_INPUT_DB_RED 2U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandControlShadowLoadMode() as +//! the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_DB_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_DB_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_DB_LOAD_FREEZE = 3 +} EPWM_DeadBandControlLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setRisingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_RED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_RED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_RED_LOAD_FREEZE = 3 +} EPWM_RisingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setFallingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_FED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_FED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_FED_LOAD_FREEZE = 3 +} EPWM_FallingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandCounterClock() as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Dead band counter runs at TBCLK rate + EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0, + //! Dead band counter runs at 2*TBCLK rate + EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1 +} EPWM_DeadBandClockMode; + +// +// Trip Zone +// +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneSignals() and +// EPWM_disableTripZoneSignals() as the tzSignal parameter. +// +//***************************************************************************** +//! TZ1 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC1 0x1U +//! TZ2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC2 0x2U +//! TZ3 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC3 0x4U +//! TZ4 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC4 0x8U +//! TZ5 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC5 0x10U +//! TZ6 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC6 0x20U +//! DCAEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCAEVT2 0x40U +//! DCBEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCBEVT2 0x80U +//! One-shot TZ1 +//! +#define EPWM_TZ_SIGNAL_OSHT1 0x100U +//! One-shot TZ2 +//! +#define EPWM_TZ_SIGNAL_OSHT2 0x200U +//! One-shot TZ3 +//! +#define EPWM_TZ_SIGNAL_OSHT3 0x400U +//! One-shot TZ4 +//! +#define EPWM_TZ_SIGNAL_OSHT4 0x800U +//! One-shot TZ5 +//! +#define EPWM_TZ_SIGNAL_OSHT5 0x1000U +//! One-shot TZ6 +//! +#define EPWM_TZ_SIGNAL_OSHT6 0x2000U +//! One-shot DCAEVT1 +//! +#define EPWM_TZ_SIGNAL_DCAEVT1 0x4000U +//! One-shot DCBEVT1 +//! +#define EPWM_TZ_SIGNAL_DCBEVT1 0x8000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcType parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_DC_OUTPUT_A1 = 0, //!< Digital Compare output 1 A + EPWM_TZ_DC_OUTPUT_A2 = 3, //!< Digital Compare output 2 A + EPWM_TZ_DC_OUTPUT_B1 = 6, //!< Digital Compare output 1 B + EPWM_TZ_DC_OUTPUT_B2 = 9 //!< Digital Compare output 2 B +} EPWM_TripZoneDigitalCompareOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_EVENT_DC_DISABLED = 0, //!< Event is disabled + EPWM_TZ_EVENT_DCXH_LOW = 1, //!< Event when DCxH low + EPWM_TZ_EVENT_DCXH_HIGH = 2, //!< Event when DCxH high + EPWM_TZ_EVENT_DCXL_LOW = 3, //!< Event when DCxL low + EPWM_TZ_EVENT_DCXL_HIGH = 4, //!< Event when DCxL high + EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5 //!< Event when DCxL high DCxH low +} EPWM_TripZoneDigitalCompareOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the \e tzEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_EVENT_TZA = 0, //!< TZ1 - TZ6, DCAEVT2, DCAEVT1 + EPWM_TZ_ACTION_EVENT_TZB = 2, //!< TZ1 - TZ6, DCBEVT2, DCBEVT1 + EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, //!< DCAEVT1 (Digital Compare A event 1) + EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, //!< DCAEVT2 (Digital Compare A event 2) + EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, //!< DCBEVT1 (Digital Compare B event 1) + EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 //!< DCBEVT2 (Digital Compare B event 2) +} EPWM_TripZoneEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the +//! \e tzAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ACTION_DISABLE = 3 //!< Disable action +} EPWM_TripZoneAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvAction() as the +//! \e tzAdvEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9, + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0 +} EPWM_TripZoneAdvancedEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA(), +//! EPWM_setTripZoneAdvDigitalCompareActionB(),EPWM_setTripZoneAdvAction() +//! as the \e tzAdvDCAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ADV_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ADV_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ADV_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ADV_ACTION_TOGGLE = 3, //!< Toggle the output + EPWM_TZ_ADV_ACTION_DISABLE = 7 //!< Disable action +} EPWM_TripZoneAdvancedAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA() and +//! EPWM_setTripZoneAdvDigitalCompareActionB() as the \e tzAdvDCEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital Compare event A/B 1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0, + //! Digital Compare event A/B 1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3, + //! Digital Compare event A/B 2 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6, + //! Digital Compare event A/B 2 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9 +} EPWM_TripZoneAdvDigitalCompareEvent; + + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneInterrupt()and +// EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle interrupt +//! +#define EPWM_TZ_INTERRUPT_CBC 0x2U +//! Trip Zones One Shot interrupt +//! +#define EPWM_TZ_INTERRUPT_OST 0x4U +//! Digital Compare A Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT1 0x8U +//! Digital Compare A Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT2 0x10U +//! Digital Compare B Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT1 0x20U +//! Digital Compare B Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be returned by EPWM_getTripZoneFlagStatus() . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle flag +//! +#define EPWM_TZ_FLAG_CBC 0x2U +//! Trip Zones One Shot flag +//! +#define EPWM_TZ_FLAG_OST 0x4U +//! Digital Compare A Event 1 flag +//! +#define EPWM_TZ_FLAG_DCAEVT1 0x8U +//! Digital Compare A Event 2 flag +//! +#define EPWM_TZ_FLAG_DCAEVT2 0x10U +//! Digital Compare B Event 1 flag +//! +#define EPWM_TZ_FLAG_DCBEVT1 0x20U +//! Digital Compare B Event 2 flag +//! +#define EPWM_TZ_FLAG_DCBEVT2 0x40U + +//***************************************************************************** +// +// Value can be passed to EPWM_clearTripZoneFlag() as the +// tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus(). +// +//***************************************************************************** +//! Trip Zone interrupt +//! +#define EPWM_TZ_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag() +// as the tzCbcFlag parameter and returned by +// EPWM_getCycleByCycleTripZoneFlagStatus(). +// +//***************************************************************************** +//! CBC flag 1 +//! +#define EPWM_TZ_CBC_FLAG_1 0x1U +//! CBC flag 2 +//! +#define EPWM_TZ_CBC_FLAG_2 0x2U +//! CBC flag 3 +//! +#define EPWM_TZ_CBC_FLAG_3 0x4U +//! CBC flag 4 +//! +#define EPWM_TZ_CBC_FLAG_4 0x8U +//! CBC flag 5 +//! +#define EPWM_TZ_CBC_FLAG_5 0x10U +//! CBC flag 6 +//! +#define EPWM_TZ_CBC_FLAG_6 0x20U +//! CBC flag Digital compare event A2 +//! +#define EPWM_TZ_CBC_FLAG_DCAEVT2 0x40U +//! CBC flag Digital compare event B2 +//! +#define EPWM_TZ_CBC_FLAG_DCBEVT2 0x80U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearOneShotTripZoneFlag() as +// the tzCbcFlag parameter and returned by the +// EPWM_getOneShotTripZoneFlagStatus() . +// +//***************************************************************************** +//! OST flag OST1 +//! +#define EPWM_TZ_OST_FLAG_OST1 0x1U +//! OST flag OST2 +//! +#define EPWM_TZ_OST_FLAG_OST2 0x2U +//! OST flag OST3 +//! +#define EPWM_TZ_OST_FLAG_OST3 0x4U +//! OST flag OST4 +//! +#define EPWM_TZ_OST_FLAG_OST4 0x8U +//! OST flag OST5 +//! +#define EPWM_TZ_OST_FLAG_OST5 0x10U +//! OST flag OST6 +//! +#define EPWM_TZ_OST_FLAG_OST6 0x20U +//! OST flag Digital compare event A1 +//! +#define EPWM_TZ_OST_FLAG_DCAEVT1 0x40U +//! OST flag Digital compare event B1 +//! +#define EPWM_TZ_OST_FLAG_DCBEVT1 0x80U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectCycleByCycleTripZoneClearEvent() as +//! the \e clearMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Clear CBC pulse when counter equals zero + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0, + //! Clear CBC pulse when counter equals period + EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1, + //! Clear CBC pulse when counter equals zero or period + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2 +} EPWM_CycleByCycleTripZoneClearMode; + +//***************************************************************************** +// +// Values that can be passed to EPWM_forceTripZoneEvent() as the +// tzForceEvent parameter. +// +//***************************************************************************** +//! Force Cycle By Cycle trip event +//! +#define EPWM_TZ_FORCE_EVENT_CBC 0x2U +//! Force a One-Shot Trip Event +//! +#define EPWM_TZ_FORCE_EVENT_OST 0x4U +//! Force Digital Compare Output A Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT1 0x8U +//! Force Digital Compare Output A Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT2 0x10U +//! Force Digital Compare Output B Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT1 0x20U +//! Force Digital Compare Output B Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be passed to EPWM_setInterruptSource() as the +// interruptSource parameter. +// +//***************************************************************************** +//! Time-base counter is disabled +//! +#define EPWM_INT_TBCTR_DISABLED 0U +//! Time-base counter equal to zero +//! +#define EPWM_INT_TBCTR_ZERO 1U +//! Time-base counter equal to period +//! +#define EPWM_INT_TBCTR_PERIOD 2U +//! Time-base counter equal to zero or period +//! +#define EPWM_INT_TBCTR_ZERO_OR_PERIOD 3U +//! time-base counter equal to CMPA when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPA 4U +//! time-base counter equal to CMPC when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPC 8U +//! time-base counter equal to CMPA when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPA 5U +//! time-base counter equal to CMPC when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPC 10U +//! time-base counter equal to CMPB when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPB 6U +//! time-base counter equal to CMPD when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPD 12U +//! time-base counter equal to CMPB when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPB 7U +//! time-base counter equal to CMPD when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPD 14U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_enableADCTrigger(), +//! EPWM_disableADCTrigger(),EPWM_setADCTriggerSource(), +//! EPWM_setADCTriggerEventPrescale(),EPWM_getADCTriggerFlagStatus(), +//! EPWM_clearADCTriggerFlag(),EPWM_enableADCTriggerEventCountInit(), +//! EPWM_disableADCTriggerEventCountInit(),EPWM_forceADCTriggerEventCountInit(), +//! EPWM_setADCTriggerEventCountInitValue(),EPWM_getADCTriggerEventCount(), +//! EPWM_forceADCTrigger() as the \e adcSOCType parameter +// +//***************************************************************************** +typedef enum +{ + EPWM_SOC_A = 0, //!< SOC A + EPWM_SOC_B = 1 //!< SOC B +} EPWM_ADCStartOfConversionType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setADCTriggerSource() as the +//! \e socSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Event is based on DCxEVT1 + EPWM_SOC_DCxEVT1 = 0, + //! Time-base counter equal to zero + EPWM_SOC_TBCTR_ZERO = 1, + //! Time-base counter equal to period + EPWM_SOC_TBCTR_PERIOD = 2, + //! Time-base counter equal to zero or period + EPWM_SOC_TBCTR_ZERO_OR_PERIOD = 3, + //! Time-base counter equal to CMPA when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPA = 4, + //! Time-base counter equal to CMPC when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPC = 8, + //! Time-base counter equal to CMPA when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPA = 5, + //! Time-base counter equal to CMPC when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPC = 10, + //! Time-base counter equal to CMPB when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPB = 6, + //! Time-base counter equal to CMPD when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPD = 12, + //! Time-base counter equal to CMPB when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPB = 7, + //! Time-base counter equal to CMPD when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPD = 14 +} EPWM_ADCStartOfConversionSource; + +// +// Digital Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput(), +//! EPWM_enableDigitalCompareTripCombinationInput(), +//! EPWM_disableDigitalCompareTripCombinationInput() as the \e dcType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TYPE_DCAH = 0, //!< Digital Compare A High + EPWM_DC_TYPE_DCAL = 1, //!< Digital Compare A Low + EPWM_DC_TYPE_DCBH = 2, //!< Digital Compare B High + EPWM_DC_TYPE_DCBL = 3 //!< Digital Compare B Low +} EPWM_DigitalCompareType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput() +//! as the \e tripSource parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TRIP_TRIPIN1 = 0, //!< Trip 1 + EPWM_DC_TRIP_TRIPIN2 = 1, //!< Trip 2 + EPWM_DC_TRIP_TRIPIN3 = 2, //!< Trip 3 + EPWM_DC_TRIP_TRIPIN4 = 3, //!< Trip 4 + EPWM_DC_TRIP_TRIPIN5 = 4, //!< Trip 5 + EPWM_DC_TRIP_TRIPIN6 = 5, //!< Trip 6 + EPWM_DC_TRIP_TRIPIN7 = 6, //!< Trip 7 + EPWM_DC_TRIP_TRIPIN8 = 7, //!< Trip 8 + EPWM_DC_TRIP_TRIPIN9 = 8, //!< Trip 9 + EPWM_DC_TRIP_TRIPIN10 = 9, //!< Trip 10 + EPWM_DC_TRIP_TRIPIN11 = 10, //!< Trip 11 + EPWM_DC_TRIP_TRIPIN12 = 11, //!< Trip 12 + EPWM_DC_TRIP_TRIPIN14 = 13, //!< Trip 14 + EPWM_DC_TRIP_TRIPIN15 = 14, //!< Trip 15 + EPWM_DC_TRIP_COMBINATION = 15 //!< All Trips (Trip1 - Trip 15) are selected +} EPWM_DigitalCompareTripInput; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput(), +// EPWM_disableDigitalCompareTripCombinationInput() as the tripInput +// parameter. +// +//***************************************************************************** +//! Combinational Trip 1 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN1 0x1U +//! Combinational Trip 2 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN2 0x2U +//! Combinational Trip 3 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN3 0x4U +//! Combinational Trip 4 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN4 0x8U +//! Combinational Trip 5 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN5 0x10U +//! Combinational Trip 6 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN6 0x20U +//! Combinational Trip 7 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN7 0x40U +//! Combinational Trip 8 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN8 0x80U +//! Combinational Trip 9 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN9 0x100U +//! Combinational Trip 10 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN10 0x200U +//! Combinational Trip 11 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN11 0x400U +//! Combinational Trip 12 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN12 0x800U +//! Combinational Trip 14 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN14 0x2000U +//! Combinational Trip 15 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN15 0x4000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareBlankingEvent() as the +//! the \e blankingPulse parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals period + EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0, + //! Time base counter equals zero + EPWM_DC_WINDOW_START_TBCTR_ZERO = 1, + //! Time base counter equals zero or period + EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2 +} EPWM_DigitalCompareBlankingPulse; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareFilterInput() +//! as the \e filterInput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, //!< DC filter signal source is DCAEVT1 + EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, //!< DC filter signal source is DCAEVT2 + EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, //!< DC filter signal source is DCBEVT1 + EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3 //!< DC filter signal source is DCBEVT2 +} EPWM_DigitalCompareFilterInput; + +//***************************************************************************** +// +//! Values that can be assigned to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode(),EPWM_enableDigitalCompareSyncEvent() +//! EPWM_enableDigitalCompareADCTrigger(),EPWM_disableDigitalCompareSyncEvent() +//! EPWM_disableDigitalCompareADCTrigger() as the \e dcModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_MODULE_A = 0, //!< Digital Compare Module A + EPWM_DC_MODULE_B = 1 //!< Digital Compare Module B +} EPWM_DigitalCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EVENT_1 = 0, //!< Digital Compare Event number 1 + EPWM_DC_EVENT_2 = 1 //!< Digital Compare Event number 2 +} EPWM_DigitalCompareEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource() as the +//! \e dcEventSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Signal source is unfiltered (DCAEVT1/2) + EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0, + //! Signal source is filtered (DCEVTFILT) + EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1 +} EPWM_DigitalCompareEventSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSyncMode() as the +//! \e syncMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! DC input signal is synced with TBCLK + EPWM_DC_EVENT_INPUT_SYNCED = 0, + //! DC input signal is not synced with TBCLK + EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1 +} EPWM_DigitalCompareSyncMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setGlobalLoadTrigger() as the +//! \e loadTrigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter is equal to zero + EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0, + //! Load when counter is equal to period + EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1, + //! Load when counter is equal to zero or period + EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2, + //! Load on sync event + EPWM_GL_LOAD_PULSE_SYNC = 0x3, + //! Load on sync event or when counter is equal to zero + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4, + //! Load on sync event or when counter is equal to period + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5, + //! Load on sync event or when counter is equal to period or zero + EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6, + //! Load on global force + EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF +} EPWM_GlobalLoadTrigger; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableGlobalLoadRegisters(), +// EPWM_disableGlobalLoadRegisters() as theloadRegister parameter. +// +//***************************************************************************** +//! Global load TBPRD:TBPRDHR +//! +#define EPWM_GL_REGISTER_TBPRD_TBPRDHR 0x1U +//! Global load CMPA:CMPAHR +//! +#define EPWM_GL_REGISTER_CMPA_CMPAHR 0x2U +//! Global load CMPB:CMPBHR +//! +#define EPWM_GL_REGISTER_CMPB_CMPBHR 0x4U +//! Global load CMPC +//! +#define EPWM_GL_REGISTER_CMPC 0x8U +//! Global load CMPD +//! +#define EPWM_GL_REGISTER_CMPD 0x10U +//! Global load DBRED:DBREDHR +//! +#define EPWM_GL_REGISTER_DBRED_DBREDHR 0x20U +//! Global load DBFED:DBFEDHR +//! +#define EPWM_GL_REGISTER_DBFED_DBFEDHR 0x40U +//! Global load DBCTL +//! +#define EPWM_GL_REGISTER_DBCTL 0x80U +//! Global load AQCTLA/A2 +//! +#define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 0x100U +//! Global load AQCTLB/B2 +//! +#define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 0x200U +//! Global load AQCSFRC +//! +#define EPWM_GL_REGISTER_AQCSFRC 0x400U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyTriggerSource() as the \e +//! trigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Valley capture trigged by software + EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U, + //! Valley capture trigged by when counter is equal to zero + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U, + //! Valley capture trigged by when counter is equal period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U, + //! Valley capture trigged when counter is equal to zero or period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U, + //! Valley capture trigged by DCAEVT1 (Digital Compare A event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U, + //! Valley capture trigged by DCAEVT2 (Digital Compare A event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U, + //! Valley capture trigged by DCBEVT1 (Digital Compare B event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U, + //! Valley capture trigged by DCBEVT2 (Digital Compare B event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U +} EPWM_ValleyTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_getValleyCountEdgeStatus() as the \e edge +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_VALLEY_COUNT_START_EDGE = 0, //!< Valley count start edge + EPWM_VALLEY_COUNT_STOP_EDGE = 1 //!< Valley count stop edge +} EPWM_ValleyCounterEdge; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyDelayValue() as the \e delayMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Delay value equals the offset value defines by software + EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U, + //! Delay value equals the sum of the Hardware counter value and the offset + //! value defines by software + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U, + //! Delay value equals the the Hardware counter shifted by + //! (1 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U, + //! Delay value equals the the Hardware counter shifted by + //! (2 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U, + //! Delay value equals the the Hardware counter shifted by + //! (4 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U +} EPWM_ValleyDelayMode; + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterMode() +//! as the \e edgeMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_MODE_RISING = 0, //!< Digital Compare Edge filter low + //!< to high edge mode + EPWM_DC_EDGEFILT_MODE_FALLING = 1, //!< Digital Compare Edge filter high + //!< to low edge mode + EPWM_DC_EDGEFILT_MODE_BOTH = 2 //!< Digital Compare Edge filter both + //!< edges mode +} EPWM_DigitalCompareEdgeFilterMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterEdgeCount() +//! as the \e edgeCount parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_EDGECNT_0 = 0, //!< Digital Compare Edge filter edge + //!< count = 0 + EPWM_DC_EDGEFILT_EDGECNT_1 = 1, //!< Digital Compare Edge filter edge + //!< count = 1 + EPWM_DC_EDGEFILT_EDGECNT_2 = 2, //!< Digital Compare Edge filter edge + //!< count = 2 + EPWM_DC_EDGEFILT_EDGECNT_3 = 3, //!< Digital Compare Edge filter edge + //!< count = 3 + EPWM_DC_EDGEFILT_EDGECNT_4 = 4, //!< Digital Compare Edge filter edge + //!< count = 4 + EPWM_DC_EDGEFILT_EDGECNT_5 = 5, //!< Digital Compare Edge filter edge + //!< count = 5 + EPWM_DC_EDGEFILT_EDGECNT_6 = 6, //!< Digital Compare Edge filter edge + //!< count = 6 + EPWM_DC_EDGEFILT_EDGECNT_7 = 7 //!< Digital Compare Edge filter edge + //!< count = 7 +} EPWM_DigitalCompareEdgeFilterEdgeCount; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_configureSignal() as the +//! \e signalParams parameter. +// +//***************************************************************************** +typedef struct +{ + float32_t freqInHz; //!< Desired Signal Frequency(in Hz) + float32_t dutyValA; //!< Desired ePWMxA Signal Duty + float32_t dutyValB; //!< Desired ePWMxB Signal Duty + bool invertSignalB; //!< Invert ePWMxB Signal if true + float32_t sysClkInHz; //!< SYSCLK Frequency(in Hz) + SysCtl_EPWMCLKDivider epwmClkDiv; //!< EPWM Clock Divider + EPWM_TimeBaseCountMode tbCtrMode; //!< Time Base Counter Mode + EPWM_ClockDivider tbClkDiv; //!< Time Base Counter Clock Divider + EPWM_HSClockDivider tbHSClkDiv; //!< Time Base Counter HS Clock Divider +} EPWM_SignalParams; + +//***************************************************************************** +// +// Functions APIs shared with HRPWM module +// +//***************************************************************************** + +// +// Period Control related API +// +#define EPWM_setSyncPulseSource HRPWM_setSyncPulseSource + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks ePWM base address. +//! +//! \param base specifies the ePWM module base address. +//! +//! This function determines if an ePWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool EPWM_isBaseValid(uint32_t base) +{ + return( + (base == EPWM1_BASE) || + (base == EPWM2_BASE) || + (base == EPWM3_BASE) || + (base == EPWM4_BASE) || + (base == EPWM5_BASE) || + (base == EPWM6_BASE) || + (base == EPWM7_BASE) || + (base == EPWM8_BASE) || + (base == EPWM9_BASE) || + (base == EPWM10_BASE) || + (base == EPWM11_BASE) || + (base == EPWM12_BASE) + ); +} +#endif + +// +// Time Base Sub Module related APIs +// +//***************************************************************************** +// +//! Set the time base count +//! +//! \param base is the base address of the EPWM module. +//! \param count is the time base count value. +//! +//! This function sets the 16 bit counter value of the time base counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounter(uint32_t base, uint16_t count) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBCTR register + // + HWREGH(base + EPWM_O_TBCTR) = count; +} + +//***************************************************************************** +// +//! Set count mode after phase shift sync +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the count mode. +//! +//! This function sets the time base count to count up or down after a new +//! phase value set by the EPWM_setPhaseShift(). The count direction is +//! determined by the variable mode. Valid inputs for mode are: +//! - EPWM_COUNT_MODE_UP_AFTER_SYNC - Count up after sync +//! - EPWM_COUNT_MODE_DOWN_AFTER_SYNC - Count down after sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC) + { + // + // Set PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSDIR; + } + else + { + // + // Clear PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSDIR; + } +} + +//***************************************************************************** +// +//! Set the time base clock and the high speed time base clock count pre-scaler +//! +//! \param base is the base address of the EPWM module. +//! \param prescaler is the time base count pre scale value. +//! \param highSpeedPrescaler is the high speed time base count pre scale +//! value. +//! +//! This function sets the pre scaler(divider)value for the time base clock +//! counter and the high speed time base clock counter. +//! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X, +//! where X is 1,2,4,8,16, 32,64 or 128. +//! The actual numerical values for these macros represent values 0,1...7. +//! The equation for the output clock is: +//! TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler) +//! +//! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half +//! SYSCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, + EPWM_HSClockDivider highSpeedPrescaler) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CLKDIV and HSPCLKDIV bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & + ~(EPWM_TBCTL_CLKDIV_M | EPWM_TBCTL_HSPCLKDIV_M)) | + (((uint16_t)prescaler << EPWM_TBCTL_CLKDIV_S) | + ((uint16_t)highSpeedPrescaler << EPWM_TBCTL_HSPCLKDIV_S))); +} + +//***************************************************************************** +// +//! Force a software sync pulse +//! +//! \param base is the base address of the EPWM module. +//! +//! This function causes a single software initiated sync pulse. Make sure the +//! appropriate mode is selected using EPWM_setupSyncOutputMode() before using +//! this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceSyncPulse(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SWFSYNC bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_SWFSYNC; +} + +//***************************************************************************** +// +//! Set up the sync out pulse event +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the sync out mode. +//! +//! This function set the sync out pulse mode. +//! Valid values for mode are: +//! - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - sync pulse is generated by software +//! when EPWM_forceSyncPulse() +//! function is called or by EPWMxSYNCI +//! signal. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO - sync pulse is generated when +//! time base counter equals zero. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B - sync pulse is generated when +//! time base counter equals compare +//! B value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C - sync pulse is generated when +//! time base counter equals compare +//! C value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D - sync pulse is generated when +//! time base counter equals compare +//! D value. +//! - EPWM_SYNC_OUT_PULSE_DISABLED - sync pulse is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setSyncOutPulseMode(uint32_t base, EPWM_SyncOutPulseMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // No extended mode support + // + if(mode < EPWM_SYNC_OUT_PULSE_DISABLED) + { + // + // Write to SYNCOSEL bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_SYNCOSEL_M)) | + ((uint16_t)mode << EPWM_TBCTL_SYNCOSEL_S)); + } + // + // Extended modes and sync out disable mode + // + else + { + // + // Write 0x3 to SYNCOSEL to enable selection from SYNCOSELX + // + HWREGH(base + EPWM_O_TBCTL) = HWREGH(base + EPWM_O_TBCTL) | + EPWM_TBCTL_SYNCOSEL_M; + + // + // Write to SYNCOSELX bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_SYNCOSELX_M)) | + (((uint16_t)mode & 0x3U) << EPWM_TBCTL2_SYNCOSELX_S)); + } +} + +//***************************************************************************** +// +//! Set PWM period load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the PWM period load mode. +//! +//! This function sets the load mode for the PWM period. If loadMode is set to +//! EPWM_PERIOD_SHADOW_LOAD, a write or read to the TBPRD (PWM Period count +//! register) accesses the shadow register. If loadMode is set to +//! EPWM_PERIOD_DIRECT_LOAD, a write or read to the TBPRD register accesses the +//! register directly. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(loadMode == EPWM_PERIOD_SHADOW_LOAD) + { + // + // Clear PRDLD + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PRDLD; + } + else + { + // + // Set PRDLD + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PRDLD; + } +} + +//***************************************************************************** +// +//! Enable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of phase shift when the appropriate sync +//! event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Disable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of phase shift. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Set time base counter mode +//! +//! \param base is the base address of the EPWM module. +//! \param counterMode is the time base counter mode. +//! +//! This function sets up the time base counter mode. +//! Valid values for counterMode are: +//! - EPWM_COUNTER_MODE_UP - Up - count mode. +//! - EPWM_COUNTER_MODE_DOWN - Down - count mode. +//! - EPWM_COUNTER_MODE_UP_DOWN - Up - down - count mode. +//! - EPWM_COUNTER_MODE_STOP_FREEZE - Stop - Freeze counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CTRMODE bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_CTRMODE_M)) | + ((uint16_t)counterMode)); +} + +//***************************************************************************** +// +//! Set shadow to active period load on sync mode +//! +//! \param base is the base address of the EPWM module. +//! \param shadowLoadMode is the shadow to active load mode. +//! +//! This function sets up the shadow to active Period register load mode with +//! respect to a sync event. Valid values for shadowLoadMode are: +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO - shadow to active load occurs when +//! time base counter reaches 0. +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC - shadow to active load occurs when +//! time base counter reaches 0 and a +//! SYNC occurs. +//! - EPWM_SHADOW_LOAD_MODE_SYNC - shadow to active load occurs only +//! when a SYNC occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_selectPeriodLoadEvent(uint32_t base, + EPWM_PeriodShadowLoadMode shadowLoadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to PRDLDSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_PRDLDSYNC_M)) | + ((uint16_t)shadowLoadMode << EPWM_TBCTL2_PRDLDSYNC_S)); +} +//***************************************************************************** +// +//! Enable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Disable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) &= ~EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Start one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function propagates a one shot sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNC; +} + +//***************************************************************************** +// +//! Returns time base counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the current value of the time base counter. +//! +//! \return returns time base counter value +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterValue(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Returns TBCTR value + // + return(HWREGH(base + EPWM_O_TBCTR)); +} + +//***************************************************************************** +// +//! Return time base counter maximum status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the status of the time base max counter. +//! +//! \return Returns true if the counter has reached 0xFFFF. +//! Returns false if the counter hasn't reached 0xFFFF. +// +//***************************************************************************** +static inline bool +EPWM_getTimeBaseCounterOverflowStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if CTRMAX bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRMAX) == + EPWM_TBSTS_CTRMAX) ? true : false); +} + +//***************************************************************************** +// +//! Clear max time base counter event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the max time base counter latch event. The latch event +//! occurs when the time base counter reaches its maximum value of 0xFFFF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CTRMAX bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_CTRMAX; +} + +//***************************************************************************** +// +//! Return external sync signal status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the external sync signal status. +//! +//! \return Returns true if if an external sync signal event +//! Returns false if there is no event. +// +//***************************************************************************** +static inline bool +EPWM_getSyncStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if SYNCI bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_SYNCI) == + EPWM_TBSTS_SYNCI) ? true : false); +} + +//***************************************************************************** +// +//! Clear external sync signal event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the external sync signal latch event. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearSyncEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SYNCI bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_SYNCI; +} + +//***************************************************************************** +// +//! Return time base counter direction. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the direction of the time base counter. +//! +//! \return returns EPWM_TIME_BASE_STATUS_COUNT_UP if the counter is counting +//! up or EPWM_TIME_BASE_STATUS_COUNT_DOWN if the counter is +//! counting down. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterDirection(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return CTRDIR bit + // + return(HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRDIR); +} + +//***************************************************************************** +// +//! Sets the phase shift offset counter value. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the phase shift count value. +//! +//! This function sets the 16 bit time-base counter phase of the ePWM relative +//! to the time-base that is supplying the synchronization input signal. Call +//! the EPWM_enablePhaseShiftLoad() function to enable loading of the +//! phaseCount phase shift value when a sync event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPHS bit + // + HWREG(base + EPWM_O_TBPHS) = + ((HWREG(base + EPWM_O_TBPHS) & + ~((uint32_t)EPWM_TBPHS_TBPHS_M)) | + ((uint32_t)phaseCount << EPWM_TBPHS_TBPHS_S)); +} + +//***************************************************************************** +// +//! Sets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is period count value. +//! +//! This function sets the period of the PWM count. The value of periodCount is +//! the value written to the register. User should map the desired period or +//! frequency of the waveform into the correct periodCount. +//! Invoke the function EPWM_selectPeriodLoadEvent() with the appropriate +//! parameter to set the load mode of the Period count. periodCount has a +//! maximum valid value of 0xFFFF +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPRD bit + // + HWREGH(base + EPWM_O_TBPRD) = periodCount; +} + +//***************************************************************************** +// +//! Gets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the period of the PWM count. +//! +//! \return The period count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read from TBPRD bit + // + return(HWREGH(base + EPWM_O_TBPRD)); +} + +//***************************************************************************** +// +//! Sets the EPWM links. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmLink is the ePWM instance to link with. +//! \param linkComp is the ePWM component to link. +//! +//! This function links the component defined in linkComp in the current ePWM +//! instance with the linkComp component of the ePWM instance defined by +//! epwmLink. A change (a write) in the value of linkComp component of epwmLink +//! instance, causes a change in the current ePWM linkComp component. +//! For example if the current ePWM is ePWM3 and the values of epwmLink and +//! linkComp are EPWM_LINK_WITH_EPWM_1 and EPWM_LINK_COMP_C respectively, +//! then a write to COMPC register in ePWM1, will result in a simultaneous +//! write to COMPC register in ePWM3. +//! Valid values for epwmLink are: +//! - EPWM_LINK_WITH_EPWM_1 - link current ePWM with ePWM1 +//! - EPWM_LINK_WITH_EPWM_2 - link current ePWM with ePWM2 +//! - EPWM_LINK_WITH_EPWM_3 - link current ePWM with ePWM3 +//! - EPWM_LINK_WITH_EPWM_4 - link current ePWM with ePWM4 +//! - EPWM_LINK_WITH_EPWM_5 - link current ePWM with ePWM5 +//! - EPWM_LINK_WITH_EPWM_6 - link current ePWM with ePWM6 +//! - EPWM_LINK_WITH_EPWM_7 - link current ePWM with ePWM7 +//! - EPWM_LINK_WITH_EPWM_8 - link current ePWM with ePWM8 +//! - EPWM_LINK_WITH_EPWM_9 - link current ePWM with ePWM9 +//! - EPWM_LINK_WITH_EPWM_10 - link current ePWM with ePWM10 +//! - EPWM_LINK_WITH_EPWM_11 - link current ePWM with ePWM11 +//! - EPWM_LINK_WITH_EPWM_12 - link current ePWM with ePWM12 +//! +//! Valid values for linkComp are: +//! - EPWM_LINK_TBPRD - link TBPRD:TBPRDHR registers +//! - EPWM_LINK_COMP_A - link COMPA registers +//! - EPWM_LINK_COMP_B - link COMPB registers +//! - EPWM_LINK_COMP_C - link COMPC registers +//! - EPWM_LINK_COMP_D - link COMPD registers +//! - EPWM_LINK_GLDCTL2 - link GLDCTL2 registers +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, + EPWM_LinkComponent linkComp) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + uint32_t registerOffset; + registerOffset = base + EPWM_O_XLINK; + + // + // Configure EPWM links + // + HWREG(registerOffset) = + ((HWREG(registerOffset) & ~((uint32_t)EPWM_XLINK_TBPRDLINK_M << (uint32_t)linkComp)) | + ((uint32_t)epwmLink << (uint32_t)linkComp)); +} + + +//***************************************************************************** +// +//! Sets up the Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets up the counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! - loadMode +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD -load when counter equals period +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule, + EPWM_CounterCompareLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t loadModeOffset; + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + syncModeOffset = 10U; + loadModeOffset = 0U; + shadowModeOffset = 4U; + } + else + { + syncModeOffset = 12U; + loadModeOffset = 2U; + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(registerOffset) = ((HWREGH(registerOffset) & + ~((0x3U << syncModeOffset) | // Clear sync mode + (0x3U << loadModeOffset) | // Clear load mode + (0x1U << shadowModeOffset))) | // shadow mode + ((((uint16_t)loadMode >> 2U) << syncModeOffset) | + (((uint16_t)loadMode & 0x3U) << loadModeOffset))); +} + +//***************************************************************************** +// +//! Disable Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! +//! This function disables counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + shadowModeOffset = 4U; + } + else + { + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Disable shadow load mode. + // + HWREGH(registerOffset) = (HWREGH(registerOffset) | + (0x1U << shadowModeOffset)); +} + +//***************************************************************************** +// +//! Set counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! \param compCount is the counter compare count value. +//! +//! This function sets the counter compare value for counter compare registers. +//! The maximum value for compCount is 0xFFFF. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, + uint16_t compCount) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Write to the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Write to COMPA or COMPB bits + // + HWREGH(base + registerOffset + 0x1U) = compCount; + } + else + { + // + // Write to COMPC or COMPD bits + // + HWREGH(base + registerOffset) = compCount; + } +} + +//***************************************************************************** +// +//! Get counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function gets the counter compare value for counter compare registers. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return The counter compare count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule) +{ + uint32_t registerOffset; + uint16_t compCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Read from the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Read COMPA or COMPB bits + // + compCount = (uint16_t)((HWREG(base + registerOffset) & + 0xFFFF0000UL) >> 16U); + } + else + { + // + // Read COMPC or COMPD bits + // + compCount = HWREGH(base + registerOffset); + } + return(compCount); +} + +//***************************************************************************** +// +//! Return the counter compare shadow register full status. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function returns the counter Compare shadow register full status flag. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return Returns true if the shadow register is full. +//! Returns false if the shadow register is not full. +// +//***************************************************************************** +static inline bool +EPWM_getCounterCompareShadowStatus(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Check the validity of input. + // COMPA and COMPB are valid input arguments. + // + ASSERT((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)); + + // + // Read the value of SHDWAFULL or SHDWBFULL bit + // + return((((HWREG(base + EPWM_O_CMPCTL) >> + ((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) & + 0x1U) == 0x1U) ? true:false); +} + +// +// Action Qualifier module related APIs +// +//***************************************************************************** +// +//! Sets the Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! - loadMode +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_AQ_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter +//! equals zero +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter +//! equals period +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when +//! counter equals zero or period +//! - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule, + EPWM_ActionQualifierLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + syncModeOffset = 8U + (uint16_t)aqModule; + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(base + EPWM_O_AQCTL) = ((HWREGH(base + EPWM_O_AQCTL) & + (~((0x3U << (uint16_t)aqModule) | + (0x3U << (uint16_t)syncModeOffset))) | + (0x1U << shadowModeOffset)) | + ((((uint16_t)loadMode >> 2U) << + syncModeOffset) | (((uint16_t)loadMode & + 0x3U) << (uint16_t)aqModule))); +} + +//***************************************************************************** +// +//! Disable Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! +//! This function disables the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule) +{ + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Disable shadow load mode. Action qualifier is loaded on + // immediate mode only. + // + HWREGH(base + EPWM_O_AQCTL) &= ~(1U << shadowModeOffset); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T1 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T1. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT1TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T1 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T1SEL_M)) | + ((uint16_t)trigger)); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T2 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T2. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT2TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T2 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T2SEL_M)) | + ((uint16_t)trigger << EPWM_AQTSRCSEL_T2SEL_S)); +} + +//***************************************************************************** +// +//! Set up Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! \param event is the event that causes a change in output. +//! +//! This function sets up the Action Qualifier output on ePWM A or ePWMB, +//! depending on the value of epwmOutput, to a value specified by outPut based +//! on the input events - specified by event. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! - event +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO - Time base counter equals +//! zero +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD - Time base counter equals +//! period +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA - Time base counter up equals +//! COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA - Time base counter down +//! equals COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB - Time base counter up equals +//! COMPB +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB - Time base counter down +//! equals COMPB +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP - T1 event on count up +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN - T1 event on count down +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP - T2 event on count up +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN - T2 event on count down +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output, + EPWM_ActionQualifierOutputEvent event) +{ + uint32_t registerOffset; + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // If the event occurs on T1 or T2 events + // + if(((uint16_t)event & 0x1U) == 1U) + { + // + // Write to T1U,T1D,T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = + ((HWREGH(base + registerTOffset) & ~(3U << ((uint16_t)event - 1U))) | + ((uint16_t)output << ((uint16_t)event - 1U))); + } + else + { + // + // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~(3U << (uint16_t)event)) | + ((uint16_t)output << (uint16_t)event)); + } +} + +//***************************************************************************** +// +//! Set up Action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Action Qualifier output on ePWMA or ePWMB, +//! depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different time base counter scenarios +//! should be OR'd together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! - action +//! - When time base counter equals zero +//! - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO - Time base counter equals zero +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_ZERO - Time base counter equals zero +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_ZERO - Time base counter equals zero +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_ZERO - Time base counter equals zero +//! and toggle the output pins +//! - When time base counter equals period +//! - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_PERIOD - Time base counter equals period +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_PERIOD - Time base counter equals period +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_PERIOD - Time base counter equals period +//! and toggle the output pins +//! - When time base counter equals CMPA during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA - Time base counter up equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPA - Time base counter up equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPA - Time base counter up equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA - Time base counter up equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPA during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA - Time base counter down equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA - Time base counter down equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPB during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB - Time base counter up equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPB - Time base counter up equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPB - Time base counter up equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB - Time base counter up equals +//! COMPB and toggle output pins +//! - When time base counter equals CMPB during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB - Time base counter down equals +//! COMPB and toggle output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each time base +//! counter scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + + // + // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Set up Additional action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Additional Action Qualifier output on ePWMA or +//! ePWMB depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different event scenarios should be OR'd +//! together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - action +//! - When T1 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 - T1 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T1 - T1 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T1 - T1 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T1 - T1 event on count up +//! and toggle the output pins +//! - When T1 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1- T1 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T1 - T1 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T1 - T1 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 - T1 event on count down +//! and toggle the output pins +//! - When T2 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 - T2 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T2 - T2 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T2 - T2 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T2 - T2 event on count up +//! and toggle the output pins +//! - When T2 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 - T2 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T2 - T2 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T2 - T2 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 - T2 event on count down +//! and toggle the output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each event +//! scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // Write to T1U, T1D, T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Sets up Action qualifier continuous software load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the mode for shadow to active load mode. +//! +//! This function sets up the AQCFRSC register load mode for continuous +//! software force reload mode. The software force actions are determined by +//! the EPWM_setActionQualifierContSWForceAction() function. +//! Valid values for mode are: +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO - shadow mode load when counter +//! equals zero +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD - shadow mode load when counter +//! equals period +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter +//! equals zero or period +//! - EPWM_AQ_SW_IMMEDIATE_LOAD - immediate mode load only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, + EPWM_ActionQualifierContForce mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action qualifier software action reload mode. + // Write to RLDCSF bit + // + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_RLDCSF_M) | + ((uint16_t)mode << EPWM_AQSFRC_RLDCSF_S)); +} + +//***************************************************************************** +// +//! Triggers a continuous software forced event. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function triggers a continuous software forced Action Qualifier output +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for the parameters are: +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_SW_DISABLED - Software forcing disabled. +//! - EPWM_AQ_SW_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_SW_OUTPUT_HIGH - Set output pins to High +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierSWOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a continuous software forced output + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFB_M) | + ((uint16_t)output << EPWM_AQCSFRC_CSFB_S)) ; + } +} + +//***************************************************************************** +// +//! Set up one time software forced Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function sets up the one time software forced Action Qualifier output +//! on ePWM A or ePWMB, depending on the value of epwmOutput to a value +//! specified by outPut. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the one time software forced action + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFB_M) | + ((uint16_t)output << EPWM_AQSFRC_ACTSFB_S)); + } +} + +//***************************************************************************** +// +//! Triggers a one time software forced event on Action qualifier +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! +//! This function triggers a one time software forced Action Qualifier event +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for epwmOutput are: +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a software forced event + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFA; + } + else + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFB; + } +} + +// +// Dead Band Module related APIs +// +//***************************************************************************** +// +//! Sets Dead Band signal output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param output is the ePWM Dead Band output. +//! \param enableSwapMode is the output swap mode. +//! +//! This function sets up the output signal swap mode. For example if the +//! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then +//! the ePWM A output gets its signal from the ePWM B signal path. Valid values +//! for the input variables are: +//! - output +//! - EPWM_DB_OUTPUT_A - ePWM output A +//! - EPWM_DB_OUTPUT_B - ePWM output B +//! - enableSwapMode +//! - true - the output is swapped +//! - false - the output and the signal path are the same. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, + bool enableSwapMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)output + EPWM_DBCTL_OUTSWAP_S); + + if(enableSwapMode) + { + // + // Set the appropriate outswap bit to swap output + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band signal output mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param enableDelayMode is the dead band delay mode. +//! +//! This function sets up the dead band delay mode. The delayMode variable +//! determines if the applied delay is Rising Edge or Falling Edge. The +//! enableDelayMode determines if a dead band delay should be applied. +//! Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - enableDelayMode +//! - true - Falling edge or Rising edge delay is applied. +//! - false - Dead Band delay is bypassed. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, + bool enableDelayMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)delayMode + EPWM_DBCTL_OUT_MODE_S); + + if(enableDelayMode) + { + // + // Set the appropriate outmode bit to enable Dead Band delay + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~ mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band delay polarity. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param polarity is the polarity of the delayed signal. +//! +//! This function sets up the polarity as determined by the variable polarity +//! of the Falling Edge or Rising Edge delay depending on the value of +//! delayMode. Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - polarity +//! - EPWM_DB_POLARITY_ACTIVE_HIGH - polarity is not inverted. +//! - EPWM_DB_POLARITY_ACTIVE_LOW - polarity is inverted. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayPolarity(uint32_t base, + EPWM_DeadBandDelayMode delayMode, + EPWM_DeadBandPolarity polarity) +{ + uint16_t shift; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shift = (((uint16_t)delayMode ^ 0x1U) + EPWM_DBCTL_POLSEL_S); + + // + // Set the appropriate polsel bits for dead band polarity + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~ (1U << shift)) | + ((uint16_t)polarity << shift)); +} + +//***************************************************************************** +// +//! Sets Rising Edge Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA( Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB( Valid for both Falling +//! Edge and Rising Edge) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB)); + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S))) | + (input << EPWM_DBCTL_IN_MODE_S)); +} + +//***************************************************************************** +// +//! Sets Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_DB_RED - Input signal is the output of Rising +//! Edge delay. +//! (Valid only for Falling Edge delay) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB) || + (input == EPWM_DB_INPUT_DB_RED)); + + if(input == EPWM_DB_INPUT_DB_RED) + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) |= EPWM_DBCTL_DEDB_MODE; + } + else + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) &= ~EPWM_DBCTL_DEDB_MODE; + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S + 1U))) | + (input << (EPWM_DBCTL_IN_MODE_S + 1U))); + } +} + +//***************************************************************************** +// +//! Set the Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Dead Band control register shadow +//! load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_DB_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_DB_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_DB_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandControlShadowLoadMode(uint32_t base, + EPWM_DeadBandControlLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode and setup the load event + // + HWREGH(base + EPWM_O_DBCTL2) = + ((HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_LOADDBCTLMODE_M) | + (EPWM_DBCTL2_SHDWDBCTLMODE | (uint16_t)loadMode)); +} + +//***************************************************************************** +// +//! Disable Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Dead Band control register shadow +//! load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDeadBandControlShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow load mode. Only immediate load mode only. + // + HWREGH(base + EPWM_O_DBCTL2) = + (HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_SHDWDBCTLMODE); +} + +//***************************************************************************** +// +//! Set the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function sets the Rising Edge Delay register shadow load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_RED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_RED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_RED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_RisingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Set-up the load mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADREDMODE_M) | + ((uint16_t)EPWM_DBCTL_SHDWDBREDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADREDMODE_S))); + +} + +//***************************************************************************** +// +//! Disable the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Rising Edge Delay register shadow load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBREDMODE); + +} + +//***************************************************************************** +// +//! Set the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function enables and sets the Falling Edge Delay register shadow load +//! mode. Valid values for the \e loadMode parameters are: +//! - EPWM_FED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_FED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_FED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_FallingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Setup the load mode. + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADFEDMODE_M) | + (EPWM_DBCTL_SHDWDBFEDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADFEDMODE_S))); + +} + +//***************************************************************************** +// +//! Disables the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Falling Edge Delay register shadow load mode. +//! Valid values for the parameters are: +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBFEDMODE); +} + +//***************************************************************************** +// +//! Sets Dead Band Counter clock rate. +//! +//! \param base is the base address of the EPWM module. +//! \param clockMode is the Dead Band counter clock mode. +//! +//! This function sets up the Dead Band counter clock rate with respect to +//! TBCLK (ePWM time base counter). +//! Valid values for clockMode are: +//! - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE -Dead band counter runs at TBCLK +//! (ePWM Time Base Counter) rate. +//! - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE -Dead band counter runs at 2*TBCLK +//! (twice ePWM Time Base Counter)rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandCounterClock(uint32_t base, + EPWM_DeadBandClockMode clockMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DB clock mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_HALFCYCLE) | + ((uint16_t)clockMode << 15U)); +} + +//***************************************************************************** +// +//! Set ePWM RED count +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the RED(Rising Edge Delay) count. +//! +//! This function sets the RED (Rising Edge Delay) count value. +//! The value of redCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(redCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBRED) = redCount; +} + +//***************************************************************************** +// +//! Set ePWM FED count +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the FED(Falling Edge Delay) count. +//! +//! This function sets the FED (Falling Edge Delay) count value. +//! The value of fedCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(fedCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBFED) = fedCount; +} + +// +// Chopper module related APIs +// +//***************************************************************************** +// +//! Enable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CHPEN bit. Enable Chopper + // + HWREGH(base + EPWM_O_PCCTL) |= EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Disable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear CHPEN bit. Disable Chopper + // + HWREGH(base + EPWM_O_PCCTL) &= ~EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Set chopper duty cycle. +//! +//! \param base is the base address of the EPWM module. +//! \param dutyCycleCount is the chopping clock duty cycle count. +//! +//! This function sets the chopping clock duty cycle. The value of +//! dutyCycleCount should be less than 7. The dutyCycleCount value is converted +//! to the actual chopper duty cycle value base on the following equation: +//! chopper duty cycle = (dutyCycleCount + 1) / 8 +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(dutyCycleCount < 7U); + + // + // Set the chopper duty cycle + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & ~EPWM_PCCTL_CHPDUTY_M) | + (dutyCycleCount << EPWM_PCCTL_CHPDUTY_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param freqDiv is the chopping clock frequency divider. +//! +//! This function sets the scaler for the chopping clock frequency. The value +//! of freqDiv should be less than 8. The chopping clock frequency is altered +//! based on the following equation. +//! chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(freqDiv < 8U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_CHPFREQ_M) | + (freqDiv << EPWM_PCCTL_CHPFREQ_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param firstPulseWidth is the width of the first pulse. +//! +//! This function sets the first pulse width of chopper output waveform. The +//! value of firstPulseWidth should be less than 0x10. The value of the first +//! pulse width in seconds is given using the following equation: +//! first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(firstPulseWidth < 16U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_OSHTWTH_M) | + (firstPulseWidth << EPWM_PCCTL_OSHTWTH_S)); +} + +// +// Trip Zone module related APIs +// +//***************************************************************************** +// +//! Enables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function enables the Trip Zone signals specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) |= tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Disables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function disables the Trip Zone signal specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) &= ~tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Set Digital compare conditions that cause Trip Zone event. +//! +//! \param base is the base address of the EPWM module. +//! \param dcType is the Digital compare output type. +//! \param dcEvent is the Digital Compare output event. +//! +//! This function sets up the Digital Compare output Trip Zone event sources. +//! The dcType variable specifies the event source to be whether Digital +//! Compare output A or Digital Compare output B. The dcEvent parameter +//! specifies the event that causes Trip Zone. +//! Valid values for the parameters are: +//! - dcType +//! - EPWM_TZ_DC_OUTPUT_A1 - Digital Compare output 1 A +//! - EPWM_TZ_DC_OUTPUT_A2 - Digital Compare output 2 A +//! - EPWM_TZ_DC_OUTPUT_B1 - Digital Compare output 1 B +//! - EPWM_TZ_DC_OUTPUT_B2 - Digital Compare output 2 B +//! - dcEvent +//! - EPWM_TZ_EVENT_DC_DISABLED - Event Trigger is disabled +//! - EPWM_TZ_EVENT_DCXH_LOW - Trigger event when DCxH low +//! - EPWM_TZ_EVENT_DCXH_HIGH - Trigger event when DCxH high +//! - EPWM_TZ_EVENT_DCXL_LOW - Trigger event when DCxL low +//! - EPWM_TZ_EVENT_DCXL_HIGH - Trigger event when DCxL high +//! - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW - Trigger event when DCxL high +//! DCxH low +//! +//! \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, + EPWM_TripZoneDigitalCompareOutput dcType, + EPWM_TripZoneDigitalCompareOutputEvent dcEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set Digital Compare Events conditions that cause a Digital Compare trip + // + EALLOW; + HWREGH(base + EPWM_O_TZDCSEL) = + ((HWREGH(base + EPWM_O_TZDCSEL) & ~(0x7U << (uint16_t)dcType)) | + ((uint16_t)dcEvent << (uint16_t)dcType)); + EDIS; +} + +//***************************************************************************** +// +//! Enable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the advanced actions of the Trip Zone events. The +//! advanced features combine the trip zone events with the direction of the +//! counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Advanced feature. Set ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Disable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the advanced actions of the Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Advanced feature. clear ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) &= ~EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzEvent is the Trip Zone event type. +//! \param tzAction is the Trip zone Action. +//! +//! This function sets the Trip Zone Action to be taken when a Trip Zone event +//! occurs. +//! Valid values for the parameters are: +//! - tzEvent +//! - EPWM_TZ_ACTION_EVENT_DCBEVT2 - DCBEVT2 (Digital Compare B event 2) +//! - EPWM_TZ_ACTION_EVENT_DCBEVT1 - DCBEVT1 (Digital Compare B event 1) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT2 - DCAEVT2 (Digital Compare A event 2) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT1 - DCAEVT1 (Digital Compare A event 1) +//! - EPWM_TZ_ACTION_EVENT_TZB - TZ1 - TZ6, DCBEVT2, DCBEVT1 +//! - EPWM_TZ_ACTION_EVENT_TZA - TZ1 - TZ6, DCAEVT2, DCAEVT1 +//! - tzAction +//! - EPWM_TZ_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ACTION_HIGH - high output +//! - EPWM_TZ_ACTION_LOW - low low +//! - EPWM_TZ_ACTION_DISABLE - disable action +//! +//! \note Disable the advanced Trip Zone event using +//! EPWM_disableTripZoneAdvAction() before calling this function. +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzEvent parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, + EPWM_TripZoneAction tzAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL) = + ((HWREGH(base + EPWM_O_TZCTL) & ~(0x3U << (uint16_t)tzEvent)) | + ((uint16_t)tzAction << (uint16_t)tzEvent)) ; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvEvent is the Trip Zone event type. +//! \param tzAdvAction is the Trip zone Action. +//! +//! This function sets the Advanced Trip Zone Action to be taken when an +//! advanced Trip Zone event occurs. +//! +//! Valid values for the parameters are: +//! - tzAdvEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_D - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_U - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_D - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_U - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting up +//! - tzAdvAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzAdvEvent parameter. +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, + EPWM_TripZoneAdvancedAction tzAdvAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) = + ((HWREGH(base + EPWM_O_TZCTL2) & ~(0x7U << (uint16_t)tzAdvEvent)) | + ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMA. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event A2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event A2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event A1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event A1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCA) = + ((HWREGH(base + EPWM_O_TZCTLDCA) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMB. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event B2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event B2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event B1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event B1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCB) = + ((HWREGH(base + EPWM_O_TZCTLDCB) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function enables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Enable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) |= tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Disable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function disables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Disable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) &= ~tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Gets the Trip Zone status flag +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the Trip Zone status flag. +//! +//! \return The function returns the following or the bitwise OR value +//! of the following values. +//! - EPWM_TZ_INTERRUPT - Trip Zone interrupt was generated +//! due to the following TZ events. +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle event status flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot event status flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag +// +//*************************************************************************** +static inline uint16_t +EPWM_getTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZFLG) & 0x7FU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone Cycle by Cycle flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific Cycle by Cycle Trip Zone flag +//! status. +//! +//! \return The function returns the following values. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 status flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 status flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 status flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 status flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 status flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 status flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC status flag for Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC status flag for Digital compare +//! event B2 +// +//*************************************************************************** +static inline uint16_t +EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Cycle By Cycle Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZCBCFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone One Shot flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific One Shot Trip Zone flag status. +//! +//! \return The function returns the bitwise OR of the following flags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST status flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST status flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST status flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST status flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST status flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST status flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST status flag for Digital +//! compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST status flag for Digital +//! compare event B1 +// +//*************************************************************************** +static inline uint16_t +EPWM_getOneShotTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the One Shot Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZOSTFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Set the Trip Zone CBC pulse clear event. +//! +//! \param base is the base address of the EPWM module. +//! \param clearEvent is the CBC trip zone clear event. +//! +//! This function set the event which automatically clears the +//! CBC (Cycle by Cycle) latch. +//! Valid values for clearEvent are: +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO - Clear CBC pulse when counter +//! equals zero +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD - Clear CBC pulse when counter +//! equals period +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD - Clear CBC pulse when counter +//! equals zero or period +//! +//! \return None. +// +//************************************************************************** +static inline void +EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, + EPWM_CycleByCycleTripZoneClearMode clearEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Cycle by Cycle Trip Latch mode + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) = + ((HWREGH(base + EPWM_O_TZCLR) & ~EPWM_TZCLR_CBCPULSE_M) | + ((uint16_t)clearEvent << EPWM_TZCLR_CBCPULSE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Clear Trip Zone flag +//! +//! \param base is the base address of the EPWM module. +//! \param tzFlags is the Trip Zone flags. +//! +//! This function clears the Trip Zone flags +//! Valid values for tzFlags are: +//! - EPWM_TZ_INTERRUPT - Global Trip Zone interrupt flag +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag +//! +//! \b note: A bitwise OR of the valid values can be passed as the tzFlags +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzFlags <= 0x80U); + + // + // Clear Trip zone event flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) |= tzFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone Cycle by Cycle flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzCBCFlags is the CBC flag to be cleared. +//! +//! This function clears the specific Cycle by Cycle Trip Zone flag. +//! The following are valid values for tzCBCFlags. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC flag Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC flag Digital compare +//! event B2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzCBCFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCBCCLR) |= tzCBCFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone One Shot flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzOSTFlags is the OST flags to be cleared. +//! +//! This function clears the specific One Shot (OST) Trip Zone flag. +//! The following are valid values for tzOSTFlags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST flag for Digital compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST flag for Digital compare event B1 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzOSTFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZOSTCLR) |= tzOSTFlags; + EDIS; +} + +//***************************************************************************** +// +//! Force Trip Zone events. +//! +//! \param base is the base address of the EPWM module. +//! \param tzForceEvent is the forced Trip Zone event. +//! +//! This function forces a Trip Zone event. +//! Valid values for tzForceEvent are: +//! - EPWM_TZ_FORCE_EVENT_CBC - Force Trip Zones Cycle By Cycle event +//! - EPWM_TZ_FORCE_EVENT_OST - Force Trip Zones One Shot Event +//! - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzForceEvent & 0xFF81U)== 0U); + + // + // Force a Trip Zone event + // + EALLOW; + HWREGH(base + EPWM_O_TZFRC) |= tzForceEvent; + EDIS; +} + +// +// Event Trigger related APIs +// +//***************************************************************************** +// +//! Enable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! disable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt source. +//! +//! \param base is the base address of the EPWM module. +//! \param interruptSource is the ePWM interrupt source. +//! +//! This function sets the ePWM interrupt source. +//! Valid values for interruptSource are: +//! - EPWM_INT_TBCTR_DISABLED - Time-base counter is disabled +//! - EPWM_INT_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_INT_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is incrementing +//! - EPWM_INT_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource) +{ + uint16_t intSource; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(((interruptSource > 0U) && (interruptSource < 9U)) || + (interruptSource == 10U) || (interruptSource == 12U) || + (interruptSource == 14U)); + + if((interruptSource == EPWM_INT_TBCTR_U_CMPC) || + (interruptSource == EPWM_INT_TBCTR_U_CMPD) || + (interruptSource == EPWM_INT_TBCTR_D_CMPC) || + (interruptSource == EPWM_INT_TBCTR_D_CMPD)) + { + // + // Shift the interrupt source by 1 + // + intSource = interruptSource >> 1U; + + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTSELCMP; + } + else if((interruptSource == EPWM_INT_TBCTR_U_CMPA) || + (interruptSource == EPWM_INT_TBCTR_U_CMPB) || + (interruptSource == EPWM_INT_TBCTR_D_CMPA) || + (interruptSource == EPWM_INT_TBCTR_D_CMPB)) + { + intSource = interruptSource; + + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTSELCMP; + } + else + { + intSource = interruptSource; + } + + // + // Set the interrupt source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_INTSEL_M) | intSource); +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the event count for interrupt scale +//! +//! This function sets the interrupt event count that determines the number of +//! events that have to occur before an interrupt is issued. +//! Maximum value for eventCount is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Enable advanced feature of interrupt every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_INTPSSEL; + HWREGH(base + EPWM_O_ETINTPS) = + ((HWREGH(base + EPWM_O_ETINTPS) & ~EPWM_ETINTPS_INTPRD2_M) | + eventCount); +} + +//***************************************************************************** +// +//! Return the interrupt status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt status. +//! \b Note This function doesn't return the Trip Zone status. +//! +//! \return Returns true if ePWM interrupt was generated. +//! Returns false if no interrupt was generated +// +//***************************************************************************** +static inline bool +EPWM_getEventTriggerInterruptStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return INT bit of ETFLG register + // + return(((HWREGH(base + EPWM_O_ETFLG) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear interrupt flag. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the ePWM interrupt flag. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearEventTriggerInterruptFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear INT bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= EPWM_ETCLR_INT; +} + +//***************************************************************************** +// +//! Enable Pre-interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt counter to be pre-interrupt loaded +//! with a count value. +//! +//! \note This is valid only for advanced/expanded interrupt mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Disable interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt counter from being loaded with +//! pre-interrupt count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= ~EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Force a software pre interrupt event counter load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces the ePWM interrupt counter to be loaded with the +//! contents set by EPWM_setPreInterruptEventCount(). +//! +//! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is +//! is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITFRC; +} + +//***************************************************************************** +// +//! Set interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM interrupt count. eventCount is the value of the +//! pre-interrupt value that is to be loaded. The maximum value of eventCount +//! is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the Pre-interrupt event count + // + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_INTINIT_M) | + (uint16_t)(eventCount & 0xFU)); +} + +//***************************************************************************** +// +//! Get the interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt event count. +//! +//! \return The interrupt event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getInterruptEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the interrupt event count + // + return(((HWREGH(base + EPWM_O_ETINTPS) & EPWM_ETINTPS_INTCNT2_M) >> + EPWM_ETINTPS_INTCNT2_S)); +} + +//***************************************************************************** +// +//! Force ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces an ePWM interrupt. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceEventTriggerInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set INT bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= EPWM_ETFRC_INT; +} + +// +// ADC SOC configuration related APIs +// +//***************************************************************************** +// +//! Enable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM module to trigger an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Disable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM module from triggering an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC source. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param socSource is the SOC source. +//! +//! This function sets the ePWM ADC SOC source. +//! Valid values for socSource are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - socSource +//! - EPWM_SOC_DCxEVT1 - Event is based on DCxEVT1 +//! - EPWM_SOC_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_SOC_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_SOC_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is incrementing +//! - EPWM_SOC_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerSource(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + EPWM_ADCStartOfConversionSource socSource) +{ + uint16_t source; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + source = (uint16_t)socSource >> 1U; + } + else + { + source = (uint16_t)socSource; + } + + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the SOC source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCASEL_M) | + (source << EPWM_ETSEL_SOCASEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCASELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCASELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } + else + { + // + // Enable the comparator selection + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCBSEL_M) | + (source << EPWM_ETSEL_SOCBSEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBSELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBSELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param preScaleCount is the event count number. +//! +//! This function sets the SOC event count that determines the number of +//! events that have to occur before an SOC is issued. +//! Valid values for the parameters are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - preScaleCount +//! - [1 - 15] - Generate SOC pulse every preScaleCount +//! up to 15 events. +//! +//! \note A preScaleCount value of 0 disables the prescale. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventPrescale(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t preScaleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(preScaleCount < 16U); + + // + // Enable advanced feature of SOC every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_SOCPSSEL; + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the count for SOC A + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCAPRD2_M) | + preScaleCount); + } + else + { + // + // Set the count for SOC B + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCBPRD2_M) | + (preScaleCount << EPWM_ETSOCPS_SOCBPRD2_S)); + } +} + +//***************************************************************************** +// +//! Return the SOC event status. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC status. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return Returns true if the selected adcSOCType SOC was generated. +//! Returns false if the selected adcSOCType SOC was not generated. +// +//***************************************************************************** +static inline bool +EPWM_getADCTriggerFlagStatus(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC A/ B status + // + return((((HWREGH(base + EPWM_O_ETFLG) >> + ((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear SOC flag. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function clears the ePWM SOC flag. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearADCTriggerFlag(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear SOC A/B bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +//***************************************************************************** +// +//! Enable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM SOC event counter which is set by the +//! EPWM_setADCTriggerEventCountInitValue() function to be loaded before +//! an SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 14U); +} + +//***************************************************************************** +// +//! Disable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM SOC event counter from being loaded before +//! an SOC event (only an SOC event causes an increment of the counter value). +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= + ~(1U << ((uint16_t)adcSOCType + 14U)); +} + +//***************************************************************************** +// +//! Force a software pre SOC event counter load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type +//! +//! This function forces the ePWM SOC counter to be loaded with the +//! contents set by EPWM_setPreADCStartOfConversionEventCount(). +//! +//! \note make sure the EPWM_enableADCTriggerEventCountInit() +//! function is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 11U); +} + +//***************************************************************************** +// +//! Set ADC Trigger count values. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM ADC Trigger count values. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! The eventCount has a maximum value of 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventCountInitValue(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the ADC Trigger event count + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCAINIT_M) | + (uint16_t)(eventCount << EPWM_ETCNTINIT_SOCAINIT_S)); + } + else + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCBINIT_M) | + (eventCount << EPWM_ETCNTINIT_SOCBINIT_S)); + } +} + +//***************************************************************************** +// +//! Get the SOC event count. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC event count. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return The SOC event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getADCTriggerEventCount(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + uint16_t eventCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC event count + // + if(adcSOCType == EPWM_SOC_A) + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCACNT2_S) & 0xFU; + } + else + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCBCNT2_S) & 0xFU; + } + return(eventCount); +} + +//***************************************************************************** +// +//! Force SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function forces an ePWM SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SOC A/B bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +// +// Digital Compare module related APIs +// +//***************************************************************************** +// +//! Set the DC trip input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripSource is the tripSource. +//! \param dcType is the Digital Compare type. +//! +//! This function sets the trip input to the Digital Compare (DC). For a given +//! dcType the function sets the tripSource to be the input to the DC. +//! Valid values for the parameter are: +//! - tripSource +//! - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13 +//! - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input +//! is enabled by the following function +//! EPWM_enableDigitalCompareTripCombinationInput() +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_selectDigitalCompareTripInput(uint32_t base, + EPWM_DigitalCompareTripInput tripSource, + EPWM_DigitalCompareType dcType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + EPWM_O_DCTRIPSEL) = + ((HWREGH(base + EPWM_O_DCTRIPSEL) & ~(0xFU << ((uint16_t)dcType << 2U))) | + ((uint16_t)tripSource << ((uint16_t)dcType << 2U))); + EDIS; +} + +// +// DCFILT +// +//***************************************************************************** +// +//! Enable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Disable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Window inverse mode. This will +//! invert the blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Window inverse mode. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare filter blanking pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param blankingPulse is Pulse that starts blanking window. +//! +//! This function sets the input pulse that starts the Digital Compare blanking +//! window. +//! Valid values for blankingPulse are: +//! - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO - Time base counter equals zero +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero +//! or period. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareBlankingEvent(uint32_t base, + EPWM_DigitalCompareBlankingPulse blankingPulse) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC blanking event + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_PULSESEL_M) | + ((uint16_t)((uint32_t)blankingPulse << EPWM_DCFCTL_PULSESEL_S))); + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter input. +//! +//! \param base is the base address of the EPWM module. +//! \param filterInput is Digital Compare signal source. +//! +//! This function sets the signal input source that will be filtered by the +//! Digital Compare module. +//! Valid values for filterInput are: +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT1 - DC filter signal source is DCAEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT2 - DC filter signal source is DCAEVT2 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT1 - DC filter signal source is DCBEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT2 - DC filter signal source is DCBEVT2 +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareFilterInput(uint32_t base, + EPWM_DigitalCompareFilterInput filterInput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the signal source that will be filtered + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_SRCSEL_M) | + ((uint16_t)filterInput)); + EDIS; +} + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Enable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Edge filter to generate event +//! after configured number of edges. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Edge filter. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Mode. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeMode is Digital Compare Edge filter mode. +//! +//! This function sets the Digital Compare Event filter mode. Valid values +//! for edgeMode are: +//! - EPWM_DC_EDGEFILT_MODE_RISING - DC edge filter mode is rising edge +//! - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge +//! - EPWM_DC_EDGEFILT_MODE_BOTH - DC edge filter mode is both edges +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, + EPWM_DigitalCompareEdgeFilterMode edgeMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter mode + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + (HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_EDGEMODE_M) | + ((uint16_t)edgeMode << EPWM_DCFCTL_EDGEMODE_S); + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeCount is Digital Compare event filter count +//! +//! This function sets the Digital Compare Event filter Edge Count to generate +//! events. Valid values for edgeCount can be: +//! - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event +//! - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter edge count + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = (HWREGH(base + EPWM_O_DCFCTL) & + ~EPWM_DCFCTL_EDGECOUNT_M) | + (edgeCount << EPWM_DCFCTL_EDGECOUNT_S); + EDIS; +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the configured Digital Compare Edge filter edge +//! count required to generate events. It can return values from 0-7. +//! +//! \return Returns the configured DigitalCompare Edge filter edge count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return configured DC edge filter edge count + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGECOUNT_M) >> + EPWM_DCFCTL_EDGECOUNT_S); +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge filter captured edge count status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the count of edges captured by Digital Compare Edge +//! filter. It can return values from 0-7. +//! +//! \return Returns the count of captured edges +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return captured edge count by DC Edge filter + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGESTATUS_M) >> + EPWM_DCFCTL_EDGESTATUS_S); +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window offset +//! +//! \param base is the base address of the EPWM module. +//! \param windowOffsetCount is blanking window offset length. +//! +//! This function sets the offset between window start pulse and blanking +//! window in TBCLK count. +//! The function take a 16bit count value for the offset value. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window offset in TBCLK counts + // + HWREGH(base + EPWM_O_DCFOFFSET) = windowOffsetCount; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window length +//! +//! \param base is the base address of the EPWM module. +//! \param windowLengthCount is blanking window length. +//! +//! This function sets up the Digital Compare filter blanking window length in +//! TBCLK count.The function takes a 16bit count value for the window length. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window length in TBCLK counts + // + HWREGH(base + EPWM_O_DCFWINDOW) = windowLengthCount; +} + +//***************************************************************************** +// +//! Return DC filter blanking window offset count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window offset count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Offset count + // + return(HWREGH(base + EPWM_O_DCFOFFSETCNT)); +} + +//***************************************************************************** +// +//! Return DC filter blanking window length count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window length count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Length count + // + return(HWREGH(base + EPWM_O_DCFWINDOWCNT)); +} + +//***************************************************************************** +// +//! Set up the Digital Compare Event source. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param dcEventSource is the - Digital Compare Event source. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - dcEventSource +//! - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL - signal source is filtered +//! \note The signal source for this option is DCxEVTy, where the +//! value of x is dependent on dcModule and the value of y is +//! dependent on dcEvent. Possible signal sources are DCAEVT1, +//! DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both +//! dcModule and dcEvent. +//! - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL - signal source is unfiltered +//! The signal source for this option is DCxEVTy. +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSource(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareEventSource dcEventSource) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event 1 source source + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SRCSEL) | + (uint16_t)dcEventSource); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2SRCSEL) | + ((uint16_t)dcEventSource << 8U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare input sync mode. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param syncMode is the Digital Compare Event sync mode. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - syncMode +//! - EPWM_DC_EVENT_INPUT_SYNCED - DC input signal is synced with +//! TBCLK +//! - EPWM_DC_EVENT_INPUT_NOT SYNCED - DC input signal is not synced with +//! TBCLK +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSyncMode(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareSyncMode syncMode) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event sync mode + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1FRCSYNCSEL) | + ((uint16_t)syncMode << 1U)); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2FRCSYNCSEL) | + ((uint16_t)syncMode << 9U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate sync out pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate sync out +//! pulse +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating synch +//! out pulse. +//! The following are valid values for the \e dcModule parameters. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +// +// DC capture mode +// +//***************************************************************************** +// +//! Enables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disable the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Set the Time Base Counter Capture mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableShadowMode is the shadow read mode flag. +//! +//! This function sets the mode the Time Base Counter value is read from. If +//! enableShadowMode is true, CPU reads of the DCCAP register will return the +//! shadow register contents.If enableShadowMode is false, CPU reads of the +//! DCCAP register will return the active register contents. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(enableShadowMode) + { + // + // Enable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_SHDWMODE; + } + else + { + // + // Disable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_SHDWMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Capture event status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC capture event status. +//! +//! \return Returns true if a DC capture event has occurs. +//! Returns false if no DC Capture event has occurred. +//! +//! \return None. +// +//***************************************************************************** +static inline bool +EPWM_getDigitalCompareCaptureStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC compare status + // + return((HWREGH(base + EPWM_O_DCCAPCTL) & EPWM_DCCAPCTL_CAPSTS) == + EPWM_DCCAPCTL_CAPSTS); +} + +//***************************************************************************** +// +//! Clears DC capture latched status flag +//! +//! \param base is the base address of the EPWM module. +//! This function is used to clear the CAPSTS (set) condition. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_clearDigitalCompareCaptureStatusFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear digital compare capture status flag + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPCLR; + EDIS; +} + +//***************************************************************************** +// +//! Configures DC capture operating mode +//! +//! \param base is the base address of the EPWM module. +//! \param disableClearMode is the clear mode bit. +//! +//! This function is used to configure the DC capture operating mode. If +//! \e disableClearMode is false, the TBCNT value is captured in active register +//! on occurance of DCEVTFILT event. The trip events are ignored until next +//! PRD or ZRO event re-triggers the capture mechanism. +//! If \e disableClearMode is true, the TBCNT value is captured, CAPSTS flag is +//! set and further trips are ignored until CAPSTS bit is cleared. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_configureDigitalCompareCounterCaptureMode(uint32_t base, + bool disableClearMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(disableClearMode) + { + // + // Disable DC counter auto-clear on PULSESEL event + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPMODE; + } + else + { + // + // Enable DC counter clear on PULSESEL events + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Time Base Counter capture value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC Time Base Counter capture value. The value +//! read is determined by the mode as set in the +//! EPWM_setTimeBaseCounterReadMode() function. +//! +//! \return Returns the DC Time Base Counter Capture count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareCaptureCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC Time Base Counter Capture count value + // + return(HWREGH(base + EPWM_O_DCCAP)); +} + +//***************************************************************************** +// +//! Enable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function enables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | tripInput); + + // + // Enable the combination input + // + HWREGH(base + EPWM_O_DCTRIPSEL) = + (HWREGH(base + EPWM_O_DCTRIPSEL) | (0xFU << ((uint16_t)dcType << 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Disable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function disables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~tripInput); + EDIS; +} + +// +// Valley switching +// +//***************************************************************************** +// +//! Enable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Start valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function starts Valley Capture sequence. +//! +//! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger +//! variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPSTART bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPSTART; + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger. +//! +//! \param base is the base address of the EPWM module. +//! \param trigger is the Valley counter trigger. +//! +//! This function sets the trigger value that initiates Valley Capture sequence +//! +//! \b Set the number of Trigger source events for starting and stopping the +//! valley capture using EPWM_setValleyTriggerEdgeCounts(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TRIGSEL bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_TRIGSEL_M) | + ((uint16_t)trigger << 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger source count. +//! +//! \param base is the base address of the EPWM module. +//! \param startCount +//! \param stopCount +//! +//! This function sets the number of trigger events required to start and stop +//! the valley capture count. +//! Maximum values for both startCount and stopCount is 15 corresponding to the +//! 15th edge of the trigger event. +//! +//! \b Note: +//! A startCount value of 0 prevents starting the valley counter. +//! A stopCount value of 0 prevents the valley counter from stopping. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, + uint16_t stopCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((startCount < 16U) && (stopCount < 16U)); + + // + // Write to STARTEDGE and STOPEDGE bits + // + EALLOW; + HWREGH(base + EPWM_O_VCNTCFG) = + ((HWREGH(base + EPWM_O_VCNTCFG) & + ~(EPWM_VCNTCFG_STARTEDGE_M | EPWM_VCNTCFG_STOPEDGE_M)) | + (startCount | (stopCount << 8U))); + EDIS; +} + +//***************************************************************************** +// +//! Enable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set Valley delay values. +//! +//! \param base is the base address of the EPWM module. +//! \param delayOffsetValue is the software defined delay offset value. +//! +//! This function sets the Valley delay value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to SWVDELVAL bits + // + HWREGH(base + EPWM_O_SWVDELVAL) = delayOffsetValue; +} + +//***************************************************************************** +// +//! Set Valley delay mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Valley delay mode. +//! +//! This function sets the Valley delay mode values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to VDELAYDIV bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_VDELAYDIV_M) | + ((uint16_t)delayMode << 7U)); + EDIS; +} + +//***************************************************************************** +// +//! Get the valley edge status bit. +//! +//! \param base is the base address of the EPWM module. +//! \param edge is the start or stop edge. +//! +//! This function returns the status of the start or stop valley status +//! depending on the value of edge. +//! If a start or stop edge has occurred, the function returns true, if not it +//! returns false. +//! +//! \return Returns true if the specified edge has occurred, +//! Returns false if the specified edge has not occurred. +// +//***************************************************************************** +static inline bool +EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(edge == EPWM_VALLEY_COUNT_START_EDGE) + { + // + // Returns STARTEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STARTEDGESTS) == + EPWM_VCNTCFG_STARTEDGESTS ) ? true : false); + } + else + { + // + // Returns STOPEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STOPEDGESTS) == + EPWM_VCNTCFG_STOPEDGESTS) ? true : false); + } +} + +//***************************************************************************** +// +//! Get the Valley Counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the valley time base count value which is captured +//! upon occurrence of the stop edge condition selected by +//! EPWM_setValleyTriggerSource() and by the stopCount variable of the +//! EPWM_setValleyTriggerEdgeCounts() function. +//! +//! \return Returns the valley base time count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read VCNTVAL register + // + return(HWREGH(base + EPWM_O_VCNTVAL)); +} + +//***************************************************************************** +// +//! Get the Valley delay value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the hardware valley delay count. +//! +//! \return Returns the valley delay count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read HWVDELVAL register + // + return(HWREGH(base + EPWM_O_HWVDELVAL)); +} + +//***************************************************************************** +// +//! Enable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Global shadow to active load mode of registers. +//! The trigger source for loading shadow to active is determined by +//! EPWM_setGlobalLoadTrigger() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Disable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Global shadow to active load mode of registers. +//! Loading shadow to active is determined individually. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled individually + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Set the Global shadow load pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param loadTrigger is the pulse that causes global shadow load. +//! +//! This function sets the pulse that causes Global shadow to active load. +//! Valid values for the loadTrigger parameter are: +//! +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO - load when counter is equal +//! to zero +//! - EPWM_GL_LOAD_PULSE_CNTR_PERIOD - load when counter is equal +//! to period +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD - load when counter is equal +//! to zero or period +//! - EPWM_GL_LOAD_PULSE_SYNC - load on sync event +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO - load on sync event or when +//! counter is equal to zero +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD - load on sync event or when +//! counter is equal to period +//! - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD - load on sync event or when +//! counter is equal to period +//! or zero +//! - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE - load on global force +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Global shadow to active load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDMODE_M) | + ((uint16_t)loadTrigger << EPWM_GLDCTL_GLDMODE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! \param prescalePulseCount is the pulse event counts. +//! +//! This function sets the number of Global Load pulse events that have to +//! occurred before a global load pulse is issued. Valid values for +//! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7 +//! representing 7 events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(prescalePulseCount < 8U); + + // + // Set the number of counts that have to occur before + // a load strobe is issued + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDPRD_M) | + (prescalePulseCount << EPWM_GLDCTL_GLDPRD_S)); + EDIS; +} + +//***************************************************************************** +// +//! Return the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the number of Global Load pulse events that have +//! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +EPWM_getGlobalLoadEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the number of events that have occurred + // + return((HWREGH(base + EPWM_O_GLDCTL) >> EPWM_GLDCTL_GLDCNT_S) & 0x7U); +} + +//***************************************************************************** +// +//! Enable continuous global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables global continuous shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Enable One shot global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables a one time global shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Set One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function sets a one time global shadow to active load pulse. The pulse +//! propagates to generate a load signal if any of the events set by +//! EPWM_setGlobalLoadTrigger() occur. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadOneShotLatch(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set a one shot Global shadow load pulse. + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_OSHTLD; + EDIS; +} + +//***************************************************************************** +// +//! Force a software One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces a software a one time global shadow to active load +//! pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceGlobalLoadOneShotEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Force a Software Global shadow load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_GFRCLD; + EDIS; +} + +//***************************************************************************** +// +//! Enable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function enables the register specified by loadRegister to be globally +//! loaded. +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) |= loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Disable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function disables the register specified by loadRegister from being +//! loaded globally. The shadow to active load happens as specified by the +//! register control +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded by individual + // register configuration setting + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) &= ~loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Set emulation mode +//! +//! \param base is the base address of the EPWM module. +//! \param emulationMode is the emulation mode. +//! +//! This function sets the emulation behaviours of the time base counter. Valid +//! values for emulationMode are: +//! - EPWM_EMULATION_STOP_AFTER_NEXT_TB - Stop after next Time Base counter +//! increment or decrement. +//! - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole +//! cycle. +//! - EPWM_EMULATION_FREE_RUN - Free run. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode); + +//***************************************************************************** +// +//! Configures ePWM signal with desired frequency & duty +//! +//! \param base is the base address of the EPWM module. +//! \param signalParams is the desired signal parameters. +//! +//! This function configures the ePWM module to generate a signal with +//! desired frequency & duty. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EPWM_H diff --git a/gpio_bitfield_cpu1/device/driverlib/eqep.c b/gpio_bitfield_cpu1/device/driverlib/eqep.c new file mode 100644 index 0000000..64caf47 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/eqep.c @@ -0,0 +1,149 @@ +//########################################################################### +// +// FILE: eqep.c +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "eqep.h" + +//***************************************************************************** +// +// EQEP_setCompareConfig +// +//***************************************************************************** +void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the compare match value + // + HWREG(base + EQEP_O_QPOSCMP) = compareValue; + + // + // Set the shadow register settings and pulse width. + // + regValue = (config & (uint16_t)(EQEP_QPOSCTL_PCSHDW | + EQEP_QPOSCTL_PCLOAD)) | (cycles - 1U); + + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(EQEP_QPOSCTL_PCSPW_M | + EQEP_QPOSCTL_PCLOAD | + EQEP_QPOSCTL_PCSHDW)) | regValue; + + // + // Set position compare sync-output mode. + // + regValue = config & (uint16_t)(EQEP_QDECCTL_SOEN | EQEP_QDECCTL_SPSEL); + + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SOEN | + EQEP_QDECCTL_SPSEL)) | regValue; +} + +//***************************************************************************** +// +// EQEP_setInputPolarity +// +//***************************************************************************** +void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Configure QEPA signal + // + if(invertQEPA) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QAP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QAP; + } + + // + // Configure QEPB signal + // + if(invertQEPB) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QBP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QBP; + } + + // + // Configure index signal + // + if(invertIndex) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QIP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QIP; + } + + // + // Configure strobe signal + // + if(invertStrobe) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QSP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QSP; + } +} diff --git a/gpio_bitfield_cpu1/device/driverlib/eqep.h b/gpio_bitfield_cpu1/device/driverlib/eqep.h new file mode 100644 index 0000000..4f1eaa2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/eqep.h @@ -0,0 +1,1691 @@ +//########################################################################### +// +// FILE: eqep.h +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EQEP_H +#define EQEP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eqep_api eQEP +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_eqep.h" +#include "inc/hw_types.h" +#include "debug.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to EQEP_setDecoderConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Operation Mode +// +#define EQEP_CONFIG_QUADRATURE 0x0000U //!< Quadrature-clock mode +#define EQEP_CONFIG_CLOCK_DIR 0x4000U //!< Direction-count mode +#define EQEP_CONFIG_UP_COUNT 0x8000U //!< Up-count mode, QDIR = 1 +#define EQEP_CONFIG_DOWN_COUNT 0xC000U //!< Down-count mode, QDIR = 0 + +// +// Resolution +// +#define EQEP_CONFIG_2X_RESOLUTION 0x0000U //!< Count rising and falling edge +#define EQEP_CONFIG_1X_RESOLUTION 0x0800U //!< Count rising edge only + +// +// Swap QEPA and QEPB +// +#define EQEP_CONFIG_NO_SWAP 0x0000U //!< Do not swap QEPA and QEPB +#define EQEP_CONFIG_SWAP 0x0400U //!< Swap QEPA and QEPB + +// +// Index pulse gating option +// +#define EQEP_CONFIG_IGATE_DISABLE 0x0000U //!< Disable gating of Index pulse +#define EQEP_CONFIG_IGATE_ENABLE 0x0200U //!< Gate the index pin with strobe + +//***************************************************************************** + +// +// Values that can be passed to EQEP_setCompareConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Sync pulse pin +// +#define EQEP_COMPARE_NO_SYNC_OUT 0x0000U //!< Disable sync output +#define EQEP_COMPARE_IDX_SYNC_OUT 0x2000U //!< Sync output on index pin +#define EQEP_COMPARE_STROBE_SYNC_OUT 0x3000U //!< Sync output on strobe pin + +// +// Shadow register use +// +#define EQEP_COMPARE_NO_SHADOW 0x0000U //!< Disable shadow of QPOSCMP +#define EQEP_COMPARE_LOAD_ON_ZERO 0x8000U //!< Load on QPOSCNT = 0 +#define EQEP_COMPARE_LOAD_ON_MATCH 0xC000U //!< Load on QPOSCNT = QPOSCMP + +//***************************************************************************** +// +// Values that can be passed to EQEP_enableInterrupt(), +// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the +// intFlags parameter and returned by EQEP_clearInterruptStatus(). +// +//***************************************************************************** +#define EQEP_INT_GLOBAL 0x0001U //!< Global interrupt flag +#define EQEP_INT_POS_CNT_ERROR 0x0002U //!< Position counter error +#define EQEP_INT_PHASE_ERROR 0x0004U //!< Quadrature phase error +#define EQEP_INT_DIR_CHANGE 0x0008U //!< Quadrature direction change +#define EQEP_INT_WATCHDOG 0x0010U //!< Watchdog time-out +#define EQEP_INT_UNDERFLOW 0x0020U //!< Position counter underflow +#define EQEP_INT_OVERFLOW 0x0040U //!< Position counter overflow +#define EQEP_INT_POS_COMP_READY 0x0080U //!< Position-compare ready +#define EQEP_INT_POS_COMP_MATCH 0x0100U //!< Position-compare match +#define EQEP_INT_STROBE_EVNT_LATCH 0x0200U //!< Strobe event latch +#define EQEP_INT_INDEX_EVNT_LATCH 0x0400U //!< Index event latch +#define EQEP_INT_UNIT_TIME_OUT 0x0800U //!< Unit time-out + +//***************************************************************************** +// +// Values that can be returned by EQEP_getStatus(). +// +//***************************************************************************** +//! Unit position event detected +#define EQEP_STS_UNIT_POS_EVNT 0x0080U +//! Direction was clockwise on first index event +#define EQEP_STS_DIR_ON_1ST_IDX 0x0040U +//! Direction is CW (forward) +#define EQEP_STS_DIR_FLAG 0x0020U +//! Direction was CW on index +#define EQEP_STS_DIR_LATCH 0x0010U +//! Capture timer overflow +#define EQEP_STS_CAP_OVRFLW_ERROR 0x0008U +//! Direction changed between position capture events +#define EQEP_STS_CAP_DIR_ERROR 0x0004U +//! First index pulse occurred +#define EQEP_STS_1ST_IDX_FLAG 0x0002U +//! Position counter error +#define EQEP_STS_POS_CNT_ERROR 0x0001U + +//***************************************************************************** +// +// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter. +// +//***************************************************************************** + +// +// Position counter latch event +// +#define EQEP_LATCH_CNT_READ_BY_CPU 0x0000U //!< On position counter read +#define EQEP_LATCH_UNIT_TIME_OUT 0x0004U //!< On unit time-out event + +// +// Strobe position counter latch event +// +//! On rising edge of strobe +#define EQEP_LATCH_RISING_STROBE 0x0000U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_LATCH_EDGE_DIR_STROBE 0x0040U + +// +// Index position counter latch event +// +#define EQEP_LATCH_RISING_INDEX 0x0010U //!< On rising edge of index +#define EQEP_LATCH_FALLING_INDEX 0x0020U //!< On falling edge of index + +#define EQEP_LATCH_SW_INDEX_MARKER 0x0030U //!< On software index marker + +//***************************************************************************** +// +// Values that can be passed to EQEP_setPositionInitMode() as the initMode +// parameter. +// +//***************************************************************************** +#define EQEP_INIT_DO_NOTHING 0x0000U //!< Action is disabled + +// +// Strobe events +// +//! On rising edge of strobe +#define EQEP_INIT_RISING_STROBE 0x0800U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_INIT_EDGE_DIR_STROBE 0x0C00U + +// +// Index events +// +#define EQEP_INIT_RISING_INDEX 0x0200U //!< On rising edge of index +#define EQEP_INIT_FALLING_INDEX 0x0300U //!< On falling edge of index +#endif + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Reset position on index pulse + EQEP_POSITION_RESET_IDX = 0x0000, + //! Reset position on maximum position + EQEP_POSITION_RESET_MAX_POS = 0x1000, + //! Reset position on the first index pulse + EQEP_POSITION_RESET_1ST_IDX = 0x2000, + //! Reset position on a unit time event + EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000 +} EQEP_PositionResetMode; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale +//! parameter. CAPCLK is the capture timer clock frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_CAPTURE_CLK_DIV_1 = 0x00, //!< CAPCLK = SYSCLKOUT/1 + EQEP_CAPTURE_CLK_DIV_2 = 0x10, //!< CAPCLK = SYSCLKOUT/2 + EQEP_CAPTURE_CLK_DIV_4 = 0x20, //!< CAPCLK = SYSCLKOUT/4 + EQEP_CAPTURE_CLK_DIV_8 = 0x30, //!< CAPCLK = SYSCLKOUT/8 + EQEP_CAPTURE_CLK_DIV_16 = 0x40, //!< CAPCLK = SYSCLKOUT/16 + EQEP_CAPTURE_CLK_DIV_32 = 0x50, //!< CAPCLK = SYSCLKOUT/32 + EQEP_CAPTURE_CLK_DIV_64 = 0x60, //!< CAPCLK = SYSCLKOUT/64 + EQEP_CAPTURE_CLK_DIV_128 = 0x70 //!< CAPCLK = SYSCLKOUT/128 +} EQEP_CAPCLKPrescale; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale +//! parameter. UPEVNT is the unit position event frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_UNIT_POS_EVNT_DIV_1, //!< UPEVNT = QCLK/1 + EQEP_UNIT_POS_EVNT_DIV_2, //!< UPEVNT = QCLK/2 + EQEP_UNIT_POS_EVNT_DIV_4, //!< UPEVNT = QCLK/4 + EQEP_UNIT_POS_EVNT_DIV_8, //!< UPEVNT = QCLK/8 + EQEP_UNIT_POS_EVNT_DIV_16, //!< UPEVNT = QCLK/16 + EQEP_UNIT_POS_EVNT_DIV_32, //!< UPEVNT = QCLK/32 + EQEP_UNIT_POS_EVNT_DIV_64, //!< UPEVNT = QCLK/64 + EQEP_UNIT_POS_EVNT_DIV_128, //!< UPEVNT = QCLK/128 + EQEP_UNIT_POS_EVNT_DIV_256, //!< UPEVNT = QCLK/256 + EQEP_UNIT_POS_EVNT_DIV_512, //!< UPEVNT = QCLK/512 + EQEP_UNIT_POS_EVNT_DIV_1024, //!< UPEVNT = QCLK/1024 + EQEP_UNIT_POS_EVNT_DIV_2048 //!< UPEVNT = QCLK/2048 +} EQEP_UPEVNTPrescale; + + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EQEP_EMULATIONMODE_STOPIMMEDIATELY, //!< Counters stop immediately + EQEP_EMULATIONMODE_STOPATROLLOVER, //!< Counters stop at period rollover + EQEP_EMULATIONMODE_RUNFREE //!< Counter unaffected by suspend +}EQEP_EmulationMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an eQEP base address. +//! +//! \param base specifies the eQEP module base address. +//! +//! This function determines if a eQEP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +EQEP_isBaseValid(uint32_t base) +{ + return( + (base == EQEP1_BASE) || + (base == EQEP2_BASE) || + (base == EQEP3_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the enhanced quadrature encoder pulse +//! (eQEP) module. The module must be configured before it is enabled. +//! +//! \sa EQEP_setConfig() +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_QPEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module. +//! +//! \param base is the base address of the enhanced quadrature encoder pulse +//! (eQEP) module +//! +//! This function disables operation of the eQEP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_QPEN); +} + +//***************************************************************************** +// +//! Configures eQEP module's quadrature decoder unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module decoder unit. +//! +//! This function configures the operation of the eQEP module's quadrature +//! decoder unit. The \e config parameter provides the configuration +//! of the decoder and is the logical OR of several values: +//! +//! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify +//! if both rising and falling edges should be counted or just rising edges. +//! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR, +//! \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if +//! quadrature signals are being provided on QEPA and QEPB, if a direction +//! signal and a clock are being provided, or if the direction should be +//! hard-wired for a single direction with QEPA used for input. +//! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the +//! signals provided on QEPA and QEPB should be swapped before being +//! processed. +//! - \b EQEP_CONFIG_IGATE_DISABLE or \b EQEP_CONFIG_IGATE_ENABLE to specify +//! if the gating of the index pulse should be enabled or disabled +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setDecoderConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the new decoder configuration to the hardware. + // + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SWAP | + EQEP_QDECCTL_XCR | + EQEP_QDECCTL_QSRC_M | + EQEP_QDECCTL_IGATE)) | config; +} + +//***************************************************************************** +// +//! Configures eQEP module position counter unit. +//! +//! \param base is the base address of the eQEP module. +//! \param mode is the configuration for the eQEP module position counter. +//! \param maxPosition specifies the maximum position value. +//! +//! This function configures the operation of the eQEP module position +//! counter. The \e mode parameter determines the event on which the position +//! counter gets reset. It should be passed one of the following values: +//! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS, +//! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT. +//! +//! \e maxPosition is the maximum value of the position counter and is +//! the value used to reset the position capture when moving in the reverse +//! (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode, + uint32_t maxPosition) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the position counter reset configuration to the hardware. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~EQEP_QEPCTL_PCRM_M) | (uint16_t)mode; + + // + // Set the maximum position. + // + HWREG(base + EQEP_O_QPOSMAX) = maxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter is not yet aligned with the index pulse). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPosition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSCNT)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the new position for the encoder. +//! +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the position counter. + // + HWREG(base + EQEP_O_QPOSCNT) = position; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +static inline int16_t +EQEP_getDirection(uint32_t base) +{ + int16_t direction; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the direction of rotation. + // + if((HWREGH(base + EQEP_O_QEPSTS) & EQEP_QEPSTS_QDF) != 0U) + { + direction = 1; + } + else + { + direction = -1; + } + + return(direction); +} + +//***************************************************************************** +// +//! Enables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the interrupt status for the eQEP module +//! module. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +// +//***************************************************************************** +static inline uint16_t +EQEP_getInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + return(HWREGH(base + EQEP_O_QFLG)); +} + +//***************************************************************************** +// +//! Clears eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In +//! order to get any further eQEP interrupts, this flag must be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QCLR) = intFlags; +} + +//***************************************************************************** +// +//! Forces individual eQEP module interrupts. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be forced. +//! +//! This function forces eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR +//! - \b EQEP_INT_PHASE_ERROR +//! - \b EQEP_INT_DIR_CHANGE +//! - \b EQEP_INT_WATCHDOG +//! - \b EQEP_INT_UNDERFLOW +//! - \b EQEP_INT_OVERFLOW +//! - \b EQEP_INT_POS_COMP_READY +//! - \b EQEP_INT_POS_COMP_MATCH +//! - \b EQEP_INT_STROBE_EVNT_LATCH +//! - \b EQEP_INT_INDEX_EVNT_LATCH +//! - \b EQEP_INT_UNIT_TIME_OUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_forceInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Force the specified interrupts. + // + HWREGH(base + EQEP_O_QFRC) |= intFlags; +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the error indicator for the eQEP module. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +static inline bool +EQEP_getError(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the error indicator. + // + return((HWREGH(base + EQEP_O_QFLG) & EQEP_QFLG_PHE) != 0U); +} + +//***************************************************************************** +// +//! Returns content of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the contents of the status register. The value it +//! returns is an OR of the following values: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward +//! movement) occurred on the first index event +//! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation +//! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last +//! index event marker +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred +//! +//! \return Returns the value of the QEP status register. +// +//***************************************************************************** +static inline uint16_t +EQEP_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the status register. + // + return(HWREGH(base + EQEP_O_QEPSTS) & 0x00FFU); +} + +//***************************************************************************** +// +//! Clears selected fields of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! \param statusFlags is the bit mask of the status flags to be cleared. +//! +//! This function clears the status register fields indicated by +//! \e statusFlags. The \e statusFlags parameter is the logical OR of any of +//! the following: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! +//! \note Only the above status fields can be cleared. All others are +//! read-only, non-sticky fields. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearStatus(uint32_t base, uint16_t statusFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QEPSTS) = statusFlags; +} + +//***************************************************************************** +// +//! Configures eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! \param capPrescale is the prescaler setting of the eQEP capture timer clk. +//! \param evntPrescale is the prescaler setting of the unit position event +//! frequency. +//! +//! This function configures the operation of the eQEP module edge-capture +//! unit. The \e capPrescale parameter provides the configuration of the eQEP +//! capture timer clock rate. It determines by which power of 2 between 1 and +//! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in +//! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For +//! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock +//! frequency that is SYSCLKOUT/32. +//! +//! The \e evntPrescale parameter determines how frequently a unit position +//! event occurs. The macro that can be passed this parameter is in the format +//! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock +//! periods between unit position events. For example, +//! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event +//! frequency of QCLK/16. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale, + EQEP_UPEVNTPrescale evntPrescale) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write new prescaler configurations to the appropriate registers. + // + HWREGH(base + EQEP_O_QCAPCTL) = + (HWREGH(base + EQEP_O_QCAPCTL) & + ~(EQEP_QCAPCTL_UPPS_M | EQEP_QCAPCTL_CCPS_M)) | + ((uint16_t)evntPrescale | (uint16_t)capPrescale); +} + +//***************************************************************************** +// +//! Enables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) |= EQEP_QCAPCTL_CEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) &= ~(EQEP_QCAPCTL_CEN); +} + +//***************************************************************************** +// +//! Gets the encoder capture period. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the period count value between the last successive +//! eQEP position events. +//! +//! \return The period count value between the last successive position events. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriod(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture period. + // + return(HWREGH(base + EQEP_O_QCPRD)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the time base for the edge capture unit. +//! +//! \return The capture timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture timer value. + // + return(HWREGH(base + EQEP_O_QCTMR)); +} + +//***************************************************************************** +// +//! Enables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's position-compare unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) |= EQEP_QPOSCTL_PCE; +} + +//***************************************************************************** +// +//! Disables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's position-compare +//! unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) &= ~(EQEP_QPOSCTL_PCE); +} + +//***************************************************************************** +// +//! Configures the position-compare unit's sync output pulse width. +//! +//! \param base is the base address of the eQEP module. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the width of the sync output pulse. The width of +//! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle. The +//! maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the pulse width. + // + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(uint16_t)EQEP_QPOSCTL_PCSPW_M) | + (cycles - 1U); +} + +//***************************************************************************** +// +//! Loads the eQEP module unit timer period as number of SYSCLK cycles. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function sets the unit time-out interrupt when it matches the value +//! specified by \e period +//! The unit timer is clocked by SYSCLKOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_loadUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; +} + +//***************************************************************************** +// +//! Enables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function enables operation of the eQEP module's peripheral unit timer. +//! The unit timer is clocked by SYSCLKOUT and will set the unit time-out +//! interrupt when it matches the value specified by \e period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; + + // + // Enable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_UTE; +} + +//***************************************************************************** +// +//! Disables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral +//! unit timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableUnitTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_UTE); +} + +//***************************************************************************** +// +//! Enables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is watchdog period value at which a time-out will occur if +//! no quadrature-clock event is detected. +//! +//! This function enables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \note When selecting \e period, note that the watchdog timer is clocked +//! from SYSCLKOUT/64. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableWatchdog(uint32_t base, uint16_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the timeout count for the eQEP peripheral watchdog timer. + // + HWREGH(base + EQEP_O_QWDPRD) = period; + + // + // Enable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_WDE; +} + +//***************************************************************************** +// +//! Disables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableWatchdog(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_WDE); +} + +//***************************************************************************** +// +//! Sets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! \param value is the value to be written to the watchdog timer. +//! +//! This function sets the eQEP module's watchdog timer value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the value to the watchdog timer register. + // + HWREGH(base + EQEP_O_QWDTMR) = value; +} + +//***************************************************************************** +// +//! Gets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! \return Returns the current watchdog timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getWatchdogTimerValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Read the value from the watchdog timer register. + // + return(HWREGH(base + EQEP_O_QWDTMR)); +} + +//***************************************************************************** +// +//! Configures the mode in which the position counter is initialized. +//! +//! \param base is the base address of the eQEP module. +//! \param initMode is the configuration for initializing the position count. +//! See below for a description of this parameter. +//! +//! This function configures the events on which the position count can be +//! initialized. The \e initMode parameter provides the mode as either +//! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following +//! strobe events, index events, or a logical OR of both a strobe event and an +//! index event. +//! +//! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify +//! which strobe event will initialize the position counter. +//! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify +//! which index event will initialize the position counter. +//! +//! Use EQEP_setSWPositionInit() to cause a software initialization and +//! EQEP_setInitialPosition() to set the value that gets loaded into the +//! position counter upon initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionInitMode(uint32_t base, uint16_t initMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the init mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_IEI_M | EQEP_QEPCTL_SEI_M)) | + initMode; +} + +//***************************************************************************** +// +//! Sets the software initialization of the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param initialize is a flag to specify if software initialization of the +//! position counter is enabled. +//! +//! This function does a software initialization of the position counter when +//! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit +//! is cleared and no action is taken. +//! +//! The init value to be loaded into the position counter can be set with +//! EQEP_setInitialPosition(). Additional initialization causes can be +//! configured with EQEP_setPositionInitMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setSWPositionInit(uint32_t base, bool initialize) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set or clear the software initialization bit. + // + if(initialize) + { + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_SWI; + } + else + { + HWREGH(base + EQEP_O_QEPCTL) &= ~EQEP_QEPCTL_SWI; + } +} + +//***************************************************************************** +// +//! Sets the init value for the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the value to be written to the position counter upon. +//! initialization. +//! +//! This function sets the init value for position of the encoder. See +//! EQEP_setPositionInitMode() to set the initialization cause or +//! EQEP_setSWPositionInit() to cause a software initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setInitialPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write position to position counter init register + // + HWREG(base + EQEP_O_QPOSINIT) = position; +} + +//***************************************************************************** +// +//! Configures the quadrature modes in which the position count can be latched. +//! +//! \param base is the base address of the eQEP module. +//! \param latchMode is the configuration for latching of the position count +//! and several other registers. See below for a description of this +//! parameter. +//! +//! This function configures the events on which the position count and several +//! other registers can be latched. The \e latchMode parameter provides the +//! mode as the logical OR of several values. +//! +//! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify +//! the event that latches the position counter. This latch register can be +//! read using EQEP_getPositionLatch(). The capture timer and capture +//! period are also latched based on this setting, and can be read using +//! EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch(). +//! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE +//! specify which strobe event will latch the position counter into the +//! strobe position latch register. This register can be read with +//! EQEP_getStrobePositionLatch(). +//! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or +//! \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the +//! position counter into the index position latch register. This register +//! can be read with EQEP_getIndexPositionLatch(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setLatchMode(uint32_t base, uint32_t latchMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the latch mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_QCLM | EQEP_QEPCTL_IEL_M | + EQEP_QEPCTL_SEL)) | latchMode; +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on an index event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the index position latch register. The +//! position counter is latched into this register on either a rising index +//! edge, a falling index edge, or a software index marker. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on an index event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getIndexPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSILAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a strobe event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the strobe position latch register. The +//! position counter can be configured to be latched into this register on +//! rising strobe edges only or on rising strobe edges while moving clockwise +//! and falling strobe edges while moving counter-clockwise. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on a strobe event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getStrobePositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a unit time-out event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the position latch register. The +//! position counter is latched into this register either on a unit time-out +//! event. +//! +//! \return The position count latch register value. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture timer latch register. The +//! capture timer value is latched into this register either on a unit time-out +//! event or upon the CPU reading the eQEP position counter. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The edge-capture timer latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimerLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCTMRLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture period latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture period latch register. The +//! capture period value is latched into this register either on a unit +//! time-out event or upon the CPU reading the eQEP position counter. This is +//! configured using EQEP_setLatchMode(). +//! +//! \return The edge-capture period latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriodLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCPRDLAT)); +} + +//***************************************************************************** +// +//! Set the emulation mode of the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! \param emuMode is the mode operation upon an emulation suspend. +//! +//! This function sets the eQEP module's emulation mode. This mode determines +//! how the timers are affected by an emulation suspend. Valid values for the +//! \e emuMode parameter are the following: +//! +//! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog +//! counter, unit timer, and capture timer all stop immediately. +//! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog +//! counter, unit timer all count until period rollover. The capture timer +//! counts until the next unit period event. +//! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter, +//! unit timer, and capture timer are all unaffected by an emulation suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the emulation mode to the FREE_SOFT bits. + // + HWREGH(base + EQEP_O_QEPCTL) = + (HWREGH(base + EQEP_O_QEPCTL) & ~EQEP_QEPCTL_FREE_SOFT_M) | + ((uint16_t)emuMode << EQEP_QEPCTL_FREE_SOFT_S); +} + +//***************************************************************************** +// +//! Configures eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module +//! position-compare unit. See below for a description of this parameter. +//! \param compareValue is the value to which the position count value is +//! compared for a position-compare event. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the operation of the eQEP module position-compare +//! unit. The \e config parameter provides the configuration of the +//! position-compare unit and is the logical OR of several values: +//! +//! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or +//! \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse +//! and which pin should be used. +//! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or +//! \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when +//! should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP. +//! +//! The \e cycles is used to select the width of the sync output pulse. The +//! width of the resulting pulse will be \e cycles * 4 * the width of a +//! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \note You can set the sync pulse width independently using the +//! EQEP_setComparePulseWidth() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles); + +//***************************************************************************** +// +//! Sets the polarity of the eQEP module's input signals. +//! +//! \param base is the base address of the eQEP module. +//! \param invertQEPA is the flag to negate the QEPA input. +//! \param invertQEPB is the flag to negate the QEPA input. +//! \param invertIndex is the flag to negate the index input. +//! \param invertStrobe is the flag to negate the strobe input. +//! +//! This function configures the polarity of the inputs to the eQEP module. To +//! negate the polarity of any of the input signals, pass \b true into its +//! corresponding parameter in this function. Pass \b false to leave it as-is. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EQEP_H diff --git a/gpio_bitfield_cpu1/device/driverlib/flash.c b/gpio_bitfield_cpu1/device/driverlib/flash.c new file mode 100644 index 0000000..372b77b --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/flash.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: flash.c +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "flash.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_powerDown, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_wakeFromLPM, ".TI.ramfunc"); +#endif + +//***************************************************************************** +// +// Flash_initModule +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT(waitstates <= 0xFU); + + // + // Set the bank power up delay so that the bank will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Set the bank fallback power mode to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Power up flash bank and pump and this also sets the fall back mode of + // flash and pump as active + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); + + // + // Disable cache and prefetch mechanism before changing wait states + // + Flash_disableCache(ctrlBase); + Flash_disablePrefetch(ctrlBase); + + // + // Set waitstates according to frequency. + // + Flash_setWaitstates(ctrlBase, waitstates); + + + // + // Enable cache and prefetch mechanism to improve performance of code + // executed from flash. + // + Flash_enableCache(ctrlBase); + Flash_enablePrefetch(ctrlBase); + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash_enableECC(eccBase); + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + + FLASH_DELAY_CONFIG; +} + +//***************************************************************************** +// +// Flash_powerDown +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_powerDown(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank power up delay so that it will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Power down the flash bank. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_SLEEP); + + // + // Power down the flash pump. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_SLEEP); +} + +//***************************************************************************** +// +// Flash_wakeFromLPM +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_wakeFromLPM(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank fallback power modes to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Set the flash pump power mode to active. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); +} diff --git a/gpio_bitfield_cpu1/device/driverlib/flash.h b/gpio_bitfield_cpu1/device/driverlib/flash.h new file mode 100644 index 0000000..a60a2f2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/flash.h @@ -0,0 +1,1671 @@ +//########################################################################### +// +// FILE: flash.h +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH_H +#define FLASH_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif +#ifndef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +//! \addtogroup flash_api Flash +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_flash.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc"); +#endif + + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the bank parameter +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK = 0x0 //!< Bank +} Flash_BankNumber; + +//***************************************************************************** +// +//! Values that can be passed to Flash_claimPumpSemaphore() in order to claim +//! the pump semaphore. +// +//***************************************************************************** +typedef enum +{ + FLASH_CPU1_WRAPPER = 0x2, //!< CPU1 Wrapper + FLASH_CPU2_WRAPPER = 0x1 //!< CPU2 Wrapper +}Flash_PumpOwnership; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_BANK_PWR_STANDBY = 0x1, //!< Standby fallback mode + FLASH_BANK_PWR_ACTIVE = 0x3 //!< Active fallback mode +} Flash_BankPowerMode; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setPumpPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_PUMP_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_PUMP_PWR_ACTIVE = 0x1 //!< Active fallback mode +} Flash_PumpPowerMode; + +//***************************************************************************** +// +//! Type that correspond to values returned from Flash_getLowErrorStatus() and +//! Flash_getHighErrorStatus() determining the error status code. +// +//***************************************************************************** +typedef enum +{ + FLASH_NO_ERR = 0x0, //!< No error + FLASH_FAIL_0 = 0x1, //!< Fail on 0 + FLASH_FAIL_1 = 0x2, //!< Fail on 1 + FLASH_UNC_ERR = 0x4 //!< Uncorrectable error +} Flash_ErrorStatus; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getLowErrorType() and +//! Flash_getHighErrorType() determining the error type. +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_ERR = 0x0, //!< Data error + FLASH_ECC_ERR = 0x1 //!< ECC error +} Flash_ErrorType; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getECCTestSingleBitErrorType(). +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_BITS = 0x0, //!< Data bits + FLASH_CHECK_BITS = 0x1 //!< ECC bits +} Flash_SingleBitErrorIndicator; + +//***************************************************************************** +// +// Values that can be passed to Flash_clearLowErrorStatus and +// Flash_clearHighErrorStatus. +// +//***************************************************************************** +#define FLASH_FAIL_0_CLR 0x1 //!< Fail-0 clear +#define FLASH_FAIL_1_CLR 0x2 //!< Fail-1 clear +#define FLASH_UNC_ERR_CLR 0x4 //!< Uncorrectable error Clear + +//***************************************************************************** +// +// Values that can be returned from Flash_getInterruptFlag and +// Flash_getECCTestStatus. +// +//***************************************************************************** +#define FLASH_NO_ERROR 0x0 //!< No error +#define FLASH_SINGLE_ERROR 0x1 //!< Single bit error +#define FLASH_UNC_ERROR 0x2 //!< Uncorrectable error + +//***************************************************************************** +// +// Delay instruction that allows for register configuration to complete. +// +//***************************************************************************** +#define FLASH_DELAY_CONFIG __asm(" RPT #7 || NOP") + +//***************************************************************************** +// +// Key value for claiming the pump semaphore. +// +//***************************************************************************** +#define FLASH_PUMP_KEY 0x5A5A0000UL //!< Pump semaphore key + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function determines if a flash wrapper control base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isCtrlBaseValid(uint32_t ctrlBase) +{ + return((ctrlBase == FLASH0CTRL_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the ECC registers. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function determines if a flash wrapper ECC base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isECCBaseValid(uint32_t eccBase) +{ + return((eccBase == FLASH0ECC_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash pump semaphore base address. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! This function determines if a flash pump semaphore base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isPumpSemBaseValid(uint32_t pumpSemBase) +{ + return((pumpSemBase == FLASHPUMPSEMAPHORE_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the random read wait state amount. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param waitstates is the wait-state value. +//! +//! This function sets the number of wait states for a flash read access. The +//! \e waitstates parameter is a number between 0 and 15. It is \b important +//! to look at your device's datasheet for information about what the required +//! minimum flash wait-state is for your selected SYSCLK frequency. +//! +//! By default the wait state amount is configured to the maximum 15. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // waitstates is 4 bits wide. + // + ASSERT(waitstates <= 0xFU); + + EALLOW; + // + // Write flash read wait-state amount to appropriate register. + // + HWREG(ctrlBase + FLASH_O_FRDCNTL) = + (HWREG(ctrlBase + FLASH_O_FRDCNTL) & + ~(uint32_t)FLASH_FRDCNTL_RWAIT_M) | + ((uint32_t)waitstates << FLASH_FRDCNTL_RWAIT_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of a flash bank. +//! +//! \param ctrlBase is the base address of the flash wrapper registers. +//! \param bank is the flash bank that is being configured. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode of the flash bank specified by +//! them \e bank parameter. The power mode is specified by the \e powerMode +//! parameter with one of the following values: +//! +//! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled. +//! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference +//! enabled. +//! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled. +//! +//! +//! Note: There is only one Flash_BankNumber value on this device (FLASH_BANK). +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank, + Flash_BankPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FBFALLBACK) = + (HWREG(ctrlBase + FLASH_O_FBFALLBACK) & + ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t)bank * 2U))) | + ((uint32_t)powerMode << ((uint32_t)bank * 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of the charge pump. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode flash charge pump. +//! +//! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled. +//! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PMPPWR) | (uint32_t)powerMode; + EDIS; +} + +//***************************************************************************** +// +//! Enables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Write the key value 0xA to ECC_ENABLE register. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0xAU; + EDIS; +} + +//***************************************************************************** +// +//! Disables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Clear ECC enable field with the one's complement of the key. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0x5U; + EDIS; +} + + +//***************************************************************************** +// +//! Sets the bank power up delay. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param delay is the number of HCLK cycles. +//! +//! This function sets the VREADST delay to ensure that the requisite delay is +//! introduced for the flash pump/bank to come out of low-power mode, so that +//! the flash/OTP is ready for CPU access. +//! +//! Note: Refer to TRM before configuring VREADST. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setBankPowerUpDelay(uint32_t ctrlBase, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(delay <= 0xFF); + + EALLOW; + + // + // Write period to the BAGP of the FBAC register. + // + HWREG(ctrlBase + FLASH_O_FBAC) = (HWREG(ctrlBase + FLASH_O_FBAC) & + ~(uint32_t)FLASH_FBAC_VREADST_M) | delay; + EDIS; +} + +//***************************************************************************** +// +//! Sets the pump wake up time. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump +//! to wakeup. +//! +//! This function sets the wakeup time with \e sysclkCycles parameter. +//! The \e sysclkCycles is a value between 0 and 8190. When the charge pump +//! exits sleep power mode, it will take sysclkCycles to wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // PSLEEP = sysclkCycles/2. PSLEEP maximum value is 4095(12 bits wide) + // + ASSERT( sysclkCycles <= 8190U ); + + EALLOW; + + // + // Write sysclkCycles/2 to PSLEEP of the FPAC1 register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PSLEEP_M) | + (((uint32_t)sysclkCycles / (uint32_t)2) << + (uint32_t)FLASH_FPAC1_PSLEEP_S); + EDIS; +} + +//***************************************************************************** +// +//! Reads the bank active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param bank is the flash bank that is being used. +//! +//! \return Returns \b true if the Bank is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + uint32_t bitMask = (uint32_t)FLASH_FBPRDY_BANKRDY << (uint32_t)bank; + // + // Return the BANKXRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & bitMask) == bitMask) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + +//***************************************************************************** +// +//! Reads the pump active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return Returns \b true if the Pump is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isPumpReady(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + + // + // Return the PUMPRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & + (uint32_t)FLASH_FBPRDY_PUMPRDY) == FLASH_FBPRDY_PUMPRDY) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + + +//***************************************************************************** +// +//! Gets the single error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the single error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC base. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the error status of the Lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the lower 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the low error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getLowErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the Low Error Status bits + // + errorStatus = (HWREG(eccBase + FLASH_O_ERR_STATUS) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error status of the Upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the upper 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the high error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getHighErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the High Error Status bits + // + errorStatus = ((HWREG(eccBase + FLASH_O_ERR_STATUS) >> 16U) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error position of the lower 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the lower 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the lower error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getLowErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_L_M) >> + FLASH_ERR_POS_ERR_POS_L_S); +} + +//***************************************************************************** +// +//! Gets the error position of the upper 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the upper 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the upper error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getHighErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_H_M) >> + FLASH_ERR_POS_ERR_POS_H_S); +} + +//***************************************************************************** +// +//! Gets the error type of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the lower 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the lower 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getLowErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_L) + == FLASH_ERR_POS_ERR_TYPE_L) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} + +//***************************************************************************** +// +//! Gets the error type of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the upper 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the upper 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getHighErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_H) + == FLASH_ERR_POS_ERR_TYPE_H) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} +//***************************************************************************** +// +//! Clears the errors status of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus); + EDIS; +} + +//***************************************************************************** +// +//! Clears the errors status of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus << 16U); + EDIS; +} + +//***************************************************************************** +// +//! Gets the single bit error count. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error count. +// +//***************************************************************************** +static inline uint32_t +Flash_getErrorCount(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_ERR_CNT) & + (uint32_t)FLASH_ERR_CNT_ERR_CNT_M); +} + +//***************************************************************************** +// +//! Sets the single bit error threshold. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param threshold is the single bit error threshold. Valid ranges are from +//! 0-65535. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_THRESHOLD) = ((uint32_t)threshold & + (uint32_t)FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M); + EDIS; +} + +//***************************************************************************** +// +//! Gets the error interrupt. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the type of error interrupt that occurred. The +//! values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the interrupt flag. +// +//***************************************************************************** +static inline uint32_t +Flash_getInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_ERR_INTFLG) & (uint32_t)0x3U)); +} + +//***************************************************************************** +// +//! Clears the single error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearSingleErrorInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Clears the uncorrectable error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearUncorrectableInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_UNC_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data Low Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the low double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAL_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data High Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the high double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAH_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the test address register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param address is a 32-bit value containing an address. Bits 21-3 will be +//! used as the flash word (128-bit) address. +//! +//! This function left shifts the address 1 bit to convert it to a byte address +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestAddress(uint32_t eccBase, uint32_t address) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Left shift the address 1 bit to make it byte-addressable + // + uint32_t byteAddress = address << 1; + + EALLOW; + + // + // Write bits 21-3 to the register. + // + HWREG(eccBase + FLASH_O_FADDR_TEST) = byteAddress; + + EDIS; + +} + +//***************************************************************************** +// +//! Sets the ECC test bits for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param ecc is a 32-bit value. The least significant 8 bits are used as +//! the ECC Control Bits in the ECC Test. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + ASSERT( ecc <= 255U ); + EALLOW; + + // + // Write the 8 ECC Control Bits. + // + HWREG(eccBase + FLASH_O_FECC_TEST) = + ((uint32_t)ecc & (uint32_t)FLASH_FECC_TEST_ECC_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_enableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [63:0] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectLowECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [127:64] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectHighECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Performs the ECC calculation on the test block. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_performECCCalculation(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_DO_ECC_CALC; + EDIS; +} + +//***************************************************************************** +// +//! Gets the ECC Test data out high 63:32 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC TEst data out High. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTH_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test data out low 31:0 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test data out Low. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTL_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test status. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the ECC test status. The values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the ECC test status. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestStatus(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS)) & (uint32_t)0x3U); +} + +//***************************************************************************** +// +//! Gets the ECC Test single bit error position. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test single bit error position. If the error type +//! is check bits than the position can range from 0 to 7. If the error type +//! is data bits than the position can range from 0 to 63. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the position bits and shift it to the right. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_DATA_ERR_POS_M) >> + FLASH_FECC_STATUS_DATA_ERR_POS_S); +} + +//***************************************************************************** +// +//! Gets the single bit error type. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error type as a +//! Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS +//! indicate where the single bit error occurred. +// +//***************************************************************************** +static inline Flash_SingleBitErrorIndicator +Flash_getECCTestSingleBitErrorType(uint32_t eccBase) +{ + uint32_t errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the ERR_TYPE bit to see where the single bit error was. + // + errorType = ((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_ERR_TYPE) >> 8U); + return((Flash_SingleBitErrorIndicator)errorType); +} + +//***************************************************************************** +// +//! Claim the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! \param wrapper is the Flash_PumpOwnership wrapper claiming the pump +//! semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_claimPumpSemaphore(uint32_t pumpSemBase, Flash_PumpOwnership wrapper) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Block until the pump semaphore is claimed. + // + EALLOW; + while((HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) + & FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M) != wrapper) + { + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = + FLASH_PUMP_KEY | (uint32_t)wrapper; + } + EDIS; +} + +//***************************************************************************** +// +//! Release the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_releasePumpSemaphore(uint32_t pumpSemBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Relinquish the pump semaphore. + // + EALLOW; + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = FLASH_PUMP_KEY; + EDIS; +} + +//***************************************************************************** +// +//! Initializes the flash control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param waitstates is the wait-state value. +//! +//! This function initializes the flash control registers. At reset bank and +//! pump are in sleep. A flash access will power up the bank and pump +//! automatically. This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! This function also sets the number of wait-states for a flash access +//! (see Flash_setWaitstates() for more details), and enables cache, the +//! prefetch mechanism, and ECC. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates); + + +//***************************************************************************** +// +//! Powers down the flash. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function powers down the flash bank(s) and the flash pump. +//! +//! Note: For this device, you must claim the flash pump semaphore before +//! calling this function and powering down the pump. Afterwards, you may want +//! to relinquish the flash pump. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_powerDown(uint32_t ctrlBase); + +//***************************************************************************** +// +//! Wakes the flash from low power mode. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_wakeFromLPM(uint32_t ctrlBase); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +#endif // #ifdef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // FLASH_H diff --git a/gpio_bitfield_cpu1/device/driverlib/gpio.c b/gpio_bitfield_cpu1/device/driverlib/gpio.c new file mode 100644 index 0000000..be20285 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/gpio.c @@ -0,0 +1,489 @@ +//########################################################################### +// +// FILE: gpio.c +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "gpio.h" + +//***************************************************************************** +// +// GPIO_setDirectionMode +// +//***************************************************************************** +void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Set the data direction + // + if(pinIO == GPIO_DIR_MODE_OUT) + { + // + // Output + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask; + } + else + { + // + // Input + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getDirectionMode +// +//***************************************************************************** +GPIO_Direction +GPIO_getDirectionMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >> + (pin % 32U)) & 1U))); + +} + +//***************************************************************************** +// +// GPIO_setInterruptPin +// +//***************************************************************************** +void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum) +{ + XBAR_InputNum input; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + // + // Pick the X-BAR input that corresponds to the requested XINT. + // + switch(extIntNum) + { + case GPIO_INT_XINT1: + input = XBAR_INPUT4; + break; + + case GPIO_INT_XINT2: + input = XBAR_INPUT5; + break; + + case GPIO_INT_XINT3: + input = XBAR_INPUT6; + break; + + case GPIO_INT_XINT4: + input = XBAR_INPUT13; + break; + + case GPIO_INT_XINT5: + input = XBAR_INPUT14; + break; + + default: + // + // Invalid interrupt. Shouldn't happen if enum value is used. + // XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for + // a bad value. + // + input = XBAR_INPUT1; + break; + } + + if(input != XBAR_INPUT1) + { + XBAR_setInputPin(input, (uint16_t)pin); + } +} + +//***************************************************************************** +// +// GPIO_setPadConfig +// +//***************************************************************************** +void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Enable open drain if necessary + // + if((pinType & GPIO_PIN_TYPE_OD) != 0U) + { + gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask; + } + + // + // Enable pull-up if necessary + // + if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U) + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask; + } + + // + // Invert polarity if necessary + // + if((pinType & GPIO_PIN_TYPE_INVERT) != 0U) + { + gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getPadConfig +// +//***************************************************************************** +uint32_t +GPIO_getPadConfig(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + uint32_t pinTypeRes; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + pinTypeRes = GPIO_PIN_TYPE_STD; + + // + // Get open drain value + // + if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_OD; + } + + // + // Get pull-up value + // + if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_PULLUP; + } + + // + // Get polarity value + // + if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_INVERT; + } + + return(pinTypeRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationMode +// +//***************************************************************************** +void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Write the input qualification mode to the register. + // + EALLOW; + + gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt; + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getQualificationMode +// +//***************************************************************************** +GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t qualRes; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Read the qualification mode register and shift and mask to get the + // value for the specified pin. + // + qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) & + (uint32_t)GPIO_GPAQSEL1_GPIO0_M; + return((GPIO_QualificationMode)qualRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationPeriod +// +//***************************************************************************** +void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask, regVal, shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + ASSERT((divider >= 1U) && (divider <= 510U)); + + shiftAmt = (pin % 32U) & ~((uint32_t)0x7U); + pinMask = (uint32_t)0xFFU << shiftAmt; + + // + // Divide divider by two to get the value that needs to go into the field. + // Then shift it into the right place. + // + regVal = (divider / 2U) << shiftAmt; + + // + // Write the divider parameter into the register. + // + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setControllerCore +// +//***************************************************************************** +void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t cSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U); + cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U); + + // + // Write the core parameter into the register. + // + EALLOW; + gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setAnalogMode +// +//***************************************************************************** +void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT((pin == 42U) || (pin == 43U)); + + pinMask = (uint32_t)1U << (pin % 32U); + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + + // + // Set the analog mode selection. + // + if(mode == GPIO_ANALOG_ENABLED) + { + // + // Enable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask; + } + else + { + // + // Disable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_setPinConfig +// +//***************************************************************************** +void +GPIO_setPinConfig(uint32_t pinConfig) +{ + uint32_t muxRegAddr; + uint32_t pinMask, shiftAmt; + + muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16); + shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU); + pinMask = (uint32_t)0x3U << shiftAmt; + + EALLOW; + + // + // Clear fields in MUX register first to avoid glitches + // + HWREG(muxRegAddr) &= ~pinMask; + + // + // Write value into GMUX register + // + HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) = + (HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) | + (((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt); + + // + // Write value into MUX register + // + HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt); + EDIS; +} diff --git a/gpio_bitfield_cpu1/device/driverlib/gpio.h b/gpio_bitfield_cpu1/device/driverlib/gpio.h new file mode 100644 index 0000000..05ae80a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/gpio.h @@ -0,0 +1,1047 @@ +//########################################################################### +// +// FILE: gpio.h +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef GPIO_H +#define GPIO_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup gpio_api GPIO +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_gpio.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_xint.h" +#include "cpu.h" +#include "xbar.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions to access gpio registers. +// Not intended for use by application code. +// +// Divide by 2 is for C28x which has word access +// +//***************************************************************************** +#define GPIO_CTRL_REGS_STEP ((GPIO_O_GPBCTRL - GPIO_O_GPACTRL) / 2U) +#define GPIO_DATA_REGS_STEP ((GPIO_O_GPBDAT - GPIO_O_GPADAT) / 2U) + +#define GPIO_GPxCTRL_INDEX (GPIO_O_GPACTRL / 2U) +#define GPIO_GPxQSEL_INDEX (GPIO_O_GPAQSEL1 / 2U) +#define GPIO_GPxMUX_INDEX (GPIO_O_GPAMUX1 / 2U) +#define GPIO_GPxDIR_INDEX (GPIO_O_GPADIR / 2U) +#define GPIO_GPxAMSEL_INDEX (0x00000014U / 2U) // Address rsvd for GPAAMSEL +#define GPIO_GPxPUD_INDEX (GPIO_O_GPAPUD / 2U) +#define GPIO_GPxINV_INDEX (GPIO_O_GPAINV / 2U) +#define GPIO_GPxODR_INDEX (GPIO_O_GPAODR / 2U) +#define GPIO_GPxGMUX_INDEX (GPIO_O_GPAGMUX1 / 2U) +#define GPIO_GPxCSEL_INDEX (GPIO_O_GPACSEL1 / 2U) +#define GPIO_GPxLOCK_INDEX (GPIO_O_GPALOCK / 2U) +#define GPIO_GPxCR_INDEX (GPIO_O_GPACR / 2U) + +#define GPIO_GPxDAT_INDEX (GPIO_O_GPADAT / 2U) +#define GPIO_GPxSET_INDEX (GPIO_O_GPASET / 2U) +#define GPIO_GPxCLEAR_INDEX (GPIO_O_GPACLEAR / 2U) +#define GPIO_GPxTOGGLE_INDEX (GPIO_O_GPATOGGLE / 2U) + +#define GPIO_MUX_TO_GMUX (GPIO_O_GPAGMUX1 - GPIO_O_GPAMUX1) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to GPIO_setPadConfig() as the pinType parameter +// and returned by GPIO_getPadConfig(). +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x0000U //!< Push-pull output or floating input +#define GPIO_PIN_TYPE_PULLUP 0x0001U //!< Pull-up enable for input +#define GPIO_PIN_TYPE_INVERT 0x0002U //!< Invert polarity on input +#define GPIO_PIN_TYPE_OD 0x0004U //!< Open-drain on output +#endif + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO +//! parameter and returned from GPIO_getDirectionMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_DIR_MODE_IN, //!< Pin is a GPIO input + GPIO_DIR_MODE_OUT //!< Pin is a GPIO output +} GPIO_Direction; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptType() as the \e intType +//! parameter and returned from GPIO_getInterruptType(). +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_TYPE_FALLING_EDGE = 0x00, //!< Interrupt on falling edge + GPIO_INT_TYPE_RISING_EDGE = 0x04, //!< Interrupt on rising edge + GPIO_INT_TYPE_BOTH_EDGES = 0x0C //!< Interrupt on both edges +} GPIO_IntType; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setQualificationMode() as the +//! \e qualification parameter and returned by GPIO_getQualificationMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_QUAL_SYNC, //!< Synchronization to SYSCLK + GPIO_QUAL_3SAMPLE, //!< Qualified with 3 samples + GPIO_QUAL_6SAMPLE, //!< Qualified with 6 samples + GPIO_QUAL_ASYNC //!< No synchronization +} GPIO_QualificationMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_ANALOG_DISABLED, //!< Pin is in digital mode + GPIO_ANALOG_ENABLED //!< Pin is in analog mode +} GPIO_AnalogMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setControllerCore() as the \e core +//! parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_CORE_CPU1, //!< CPU1 selected as controller core + GPIO_CORE_CPU1_CLA1, //!< CPU1's CLA1 selected as controller core + GPIO_CORE_CPU2, //!< CPU2 selected as controller core + GPIO_CORE_CPU2_CLA1 //!< CPU2's CLA1 selected as controller core +} GPIO_CoreSelect; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(), +//! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_PORT_A = 0, //!< GPIO port A + GPIO_PORT_B = 1, //!< GPIO port B + GPIO_PORT_C = 2, //!< GPIO port C + GPIO_PORT_D = 3, //!< GPIO port D + GPIO_PORT_E = 4, //!< GPIO port E + GPIO_PORT_F = 5 //!< GPIO port F +} GPIO_Port; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptPin(), +//! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(), +//! GPIO_disableInterrupt(), as the \e extIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_XINT1, //!< External Interrupt 1 + GPIO_INT_XINT2, //!< External Interrupt 2 + GPIO_INT_XINT3, //!< External Interrupt 3 + GPIO_INT_XINT4, //!< External Interrupt 4 + GPIO_INT_XINT5 //!< External Interrupt 5 +} GPIO_ExternalIntNum; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks that a pin number is valid for a device. +//! +//! Note that this function reflects the highest possible GPIO number of a +//! device on its biggest package. Check the datasheet to see what the actual +//! range of valid pin numbers is for a specific package. +//! +//! \return None. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +GPIO_isPinValid(uint32_t pin) +{ + return(pin <= 168U); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin. +//! +//! \param extIntNum specifies the external interrupt. +//! \param intType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin on the selected GPIO port. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! One of the following flags can be used to define the \e intType +//! parameter: +//! +//! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to +//! falling +//! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising +//! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType) +{ + // + // Write the selected polarity to the appropriate register. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) = + (HWREGH(XINT_BASE + (uint16_t)extIntNum) & ~XINT_1CR_POLARITY_M) | + (uint16_t)intType; +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function gets the interrupt type for a interrupt. The interrupt can be +//! configured as a falling-edge, rising-edge, or both-edges detected +//! interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return Returns one of the flags described for GPIO_setInterruptType(). +// +//***************************************************************************** +static inline GPIO_IntType +GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum) +{ + // + // Read the selected polarity from the appropriate register. + // + return((GPIO_IntType)((uint16_t)(HWREGH(XINT_BASE + (uint16_t)extIntNum) & + XINT_1CR_POLARITY_M))); +} + +//***************************************************************************** +// +//! Enables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function enables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Set the enable bit for the specified interrupt. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) |= XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Disables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function disables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Clear the enable bit for the specified interrupt + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) &= ~XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Gets the value of the external interrupt counter. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns external interrupt counter value. +// +//***************************************************************************** +static inline uint16_t +GPIO_getInterruptCounter(GPIO_ExternalIntNum extIntNum) +{ + ASSERT(extIntNum <= GPIO_INT_XINT3); + + // + // Read the counter value from the appropriate register. + // + return((HWREGH(XINT_BASE + XINT_O_1CTR + (uint16_t)extIntNum))); +} + +//***************************************************************************** +// +//! Reads the value present on the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! The value at the specified pin are read, as specified by \e pin. The value +//! is returned for both input and output pins. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return Returns the value in the data register for the specified pin. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + return((gpioDataReg[GPIO_GPxDAT_INDEX] >> (pin % 32U)) & (uint32_t)0x1U); +} + + +//***************************************************************************** +// +//! Writes a value to the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param outVal is the value to write to the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePin(uint32_t pin, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + pinMask = (uint32_t)1U << (pin % 32U); + + if(outVal == 0U) + { + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; + } + else + { + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; + } +} + +//***************************************************************************** +// +//! Toggles the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = (uint32_t)1U << (pin % 32U); +} + +//***************************************************************************** +// +//! Reads the data on the specified port. +//! +//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X +//! where X is the port letter. +//! +//! \return Returns the value available on pin for the specified port. Each +//! bit of the the return value represents a pin on the port, where bit 0 +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPortData(GPIO_Port port) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and return DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + return(gpioDataReg[GPIO_GPxDAT_INDEX]); +} + + +//***************************************************************************** +// +//! Writes a value to the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param outVal is the value to write to the port. +//! +//! This function writes the value \e outVal to the port specified by the +//! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X +//! is the port letter. For example, use \b GPIO_PORT_A to affect port A +//! (GPIOs 0-31). +//! +//! The \e outVal is a bit-packed value, where each bit represents a bit on a +//! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port +//! pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePortData(GPIO_Port port, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxDAT_INDEX] = outVal; +} + +//***************************************************************************** +// +//! Sets all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function sets all of the pins specified by the \e pinMask parameter on +//! the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO +//! port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to SET. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Clears all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function clears all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is \b set +//! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1 +//! represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to CLEAR. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Toggles all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function toggles all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to TOGGLE. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Locks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function locks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that this function is for locking the configuration of a pin such as +//! the pin muxing, direction, open drain mode, and other settings. It does not +//! affect the ability to change the value of the pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function unlocks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] &= ~pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function commits the lock configuration registers of the pins +//! specified by the \e pinMask parameter on the port specified by the \e port +//! parameter which takes a value in the form of \b GPIO_PORT_X where X is the +//! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that once this function is called, GPIO_lockPortConfig() and +//! GPIO_unlockPortConfig() will no longer have any effect on the specified +//! pins. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxCR_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinIO is the pin direction mode. +//! +//! This function configures the specified pin on the selected GPIO port as +//! either input or output. +//! +//! The parameter \e pinIO is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input +//! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO); + +//***************************************************************************** +// +//! Gets the direction mode of a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function gets the direction mode for a specified pin. The pin can be +//! configured as either an input or output The type of direction is returned +//! as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIO_setDirectionMode(). +// +//***************************************************************************** +extern GPIO_Direction +GPIO_getDirectionMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the pin for the specified external interrupt. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param extIntNum specifies the external interrupt. +//! +//! This function sets which pin triggers the selected external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \sa XBAR_setInputPin() +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum); + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinType specifies the pin type. +//! +//! This function sets the pin type for the specified pin. The parameter +//! \e pinType can be the following values: +//! +//! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input +//! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input +//! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin +//! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input +//! +//! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or +//! \b GPIO_PIN_TYPE_PULLUP. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType); + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function returns the pin type for the specified pin. The value +//! returned corresponds to the values used in GPIO_setPadConfig(). +//! +//! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD, +//! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT. +// +//***************************************************************************** +extern uint32_t +GPIO_getPadConfig(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification mode for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param qualification specifies the qualification mode of the pin. +//! +//! This function sets the qualification mode for the specified pin. The +//! parameter \e qualification can be one of the following values: +//! - \b GPIO_QUAL_SYNC +//! - \b GPIO_QUAL_3SAMPLE +//! - \b GPIO_QUAL_6SAMPLE +//! - \b GPIO_QUAL_ASYNC +//! +//! To set the qualification sampling period, use +//! GPIO_setQualificationPeriod(). +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification); + +//***************************************************************************** +// +//! Gets the qualification type for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! \return Returns the qualification mode in the form of one of the values +//! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or +//! \b GPIO_QUAL_ASYNC. +// +//***************************************************************************** +extern GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification period for a set of pins +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param divider specifies the output drive strength. +//! +//! This function sets the qualification period for a set of \b 8 \b pins, +//! specified by the \e pin parameter. For instance, passing in 3 as the value +//! of \e pin will set the qualification period for GPIO0 through GPIO7, and a +//! value of 98 will set the qualification period for GPIO96 through GPIO103. +//! This is because the register field that configures the divider is shared. +//! +//! To think of this in terms of an equation, configuring \e pin as \b n will +//! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7). +//! +//! \e divider is the value by which the frequency of SYSCLKOUT is divided. It +//! can be 1 or an even value between 2 and 510 inclusive. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider); + +//***************************************************************************** +// +//! Selects the controller core of a specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param core is the core that is controller of the specified pin. +//! +//! This function configures which core owns the specified pin's data registers +//! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data +//! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's +//! CLA1 controller of the pin. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core); + +//***************************************************************************** +// +//! Sets the analog mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param mode is the selected analog mode. +//! +//! This function configures the specified pin for either analog or digital +//! mode. Not all GPIO pins have the ability to be switched to analog mode, +//! so refer to the technical reference manual for details. This setting should +//! be thought of as another level of muxing. +//! +//! The parameter \e mode is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode +//! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \b Note: The pin parameter is applicable for both AIO and GPIO because +//! the GPAxMSEL.GPIOy register configures for both +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode); + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param pinConfig is the pin configuration value, specified as only one +//! of the \b GPIO_#_???? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). +//! +//! The available mappings are supplied in pin_map.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPinConfig(uint32_t pinConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // GPIO_H diff --git a/gpio_bitfield_cpu1/device/driverlib/hrpwm.c b/gpio_bitfield_cpu1/device/driverlib/hrpwm.c new file mode 100644 index 0000000..04aa22c --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/hrpwm.c @@ -0,0 +1,47 @@ +//########################################################################### +// +// FILE: hrpwm.c +// +// TITLE: C28x HRPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "hrpwm.h" + +// +// All the API functions are in-lined in hrpwm.h +// diff --git a/gpio_bitfield_cpu1/device/driverlib/hrpwm.h b/gpio_bitfield_cpu1/device/driverlib/hrpwm.h new file mode 100644 index 0000000..2561d67 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/hrpwm.h @@ -0,0 +1,1657 @@ +//############################################################################# +// +// FILE: hrpwm.h +// +// TITLE: C28x HRPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef HRPWM_H +#define HRPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup hrpwm_api HRPWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_hrpwm.h" +#include "cpu.h" +#include "debug.h" +#include "epwm.h" +#include "hrpwm.h" + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect(), +//! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent() +//! as the \e channel parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_CHANNEL_A = 0, //!< HRPWM A + HRPWM_CHANNEL_B = 8 //!< HRPWM B +} HRPWM_Channel; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_MEP_CTRL_DISABLE = 0, + //! MEP controls rising edge + HRPWM_MEP_CTRL_RISING_EDGE = 1, + //! MEP controls falling edge + HRPWM_MEP_CTRL_FALLING_EDGE = 2, + //! MEP controls both rising and falling edge + HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3 +} HRPWM_MEPEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! CMPAHR/CMPBHR or TBPRDHR controls MEP edge + HRPWM_MEP_DUTY_PERIOD_CTRL = 0, + //! TBPHSHR controls MEP edge + HRPWM_MEP_PHASE_CTRL = 1 +} HRPWM_MEPCtrlMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(), +//! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode +//! as the \e loadEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! load when counter equals zero + HRPWM_LOAD_ON_CNTR_ZERO = 0, + //! load when counter equals period + HRPWM_LOAD_ON_CNTR_PERIOD = 1, + //! load when counter equals zero or period + HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2, +} HRPWM_LoadMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e +//! outputOnB parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal. + HRPWM_OUTPUT_ON_B_INV_A = 1 //!< ePWMxB output is inverted + //!< version of ePWMxA signal +} HRPWM_ChannelBOutput; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setSyncPulseSource() as the \e +//! syncPulseSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Counter equals Period + HRPWM_PWMSYNC_SOURCE_PERIOD = 0, + //! Counter equals zero + HRPWM_PWMSYNC_SOURCE_ZERO = 1, + //! Counter equals COMPC when counting up + HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4, + //! Counter equals COMPC when counting down + HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5, + //! Counter equals COMPD when counting up + HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6, + //! Counter equals COMPD when counting down + HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7 +} HRPWM_SyncPulseSource; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareValue() as the \e +//! compModule parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A + HRPWM_COUNTER_COMPARE_B = 4 //!< counter compare B +} HRPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e +//! mepDBEdge. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_DB_MEP_CTRL_DISABLE = 0, + //! MEP controls Rising Edge Delay + HRPWM_DB_MEP_CTRL_RED = 1, + //! MEP controls Falling Edge Delay + HRPWM_DB_MEP_CTRL_FED = 2, + //! MEP controls both Falling and Rising edge delay + HRPWM_DB_MEP_CTRL_RED_FED = 3 +} HRPWM_MEPDeadBandEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup +//! parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_REGISTER_GROUP_HRPWM = 0x1, //!< HRPWM register group + HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group + HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group + HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group + HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group +} HRPWM_LockRegisterGroup; + +//***************************************************************************** +// +// Functions APIs shared with ePWM module +// +//***************************************************************************** + +// +// Time Base Sub Module related APIs +// +#define HRPWM_setTimeBaseCounter EPWM_setTimeBaseCounter +#define HRPWM_setCountModeAfterSync EPWM_setCountModeAfterSync +#define HRPWM_setClockPrescaler EPWM_setClockPrescaler +#define HRPWM_swForceSyncPulse EPWM_forceSyncPulse +#define HRPWM_setSyncOutPulseMode EPWM_setSyncOutPulseMode +#define HRPWM_setPeriodLoadMode EPWM_setPeriodLoadMode +#define HRPWM_setTimeBaseCounterMode EPWM_setTimeBaseCounterMode +#define HRPWM_selectPeriodLoadEvent EPWM_selectPeriodLoadEvent +#define HRPWM_enableOneShotSync EPWM_enableOneShotSync +#define HRPWM_disableOneShotSync EPWM_disableOneShotSync +#define HRPWM_startOneShotSync EPWM_startOneShotSync +#define HRPWM_getTimeBaseCounterOverflowStatus \ + EPWM_getTimeBaseCounterOverflowStatus +#define HRPWM_clearTimeBaseCounterOverflowEvent \ + EPWM_clearTimeBaseCounterOverflowEvent +#define HRPWM_getSyncStatus EPWM_getSyncStatus +#define HRPWM_clearSyncEvent EPWM_clearSyncEvent +#define HRPWM_getTimeBaseCounterDirection EPWM_getTimeBaseCounterDirection +#define HRPWM_setupEPWMLinks EPWM_setupEPWMLinks +#define HRPWM_setCounterCompareShadowLoadMode \ + EPWM_setCounterCompareShadowLoadMode +#define HRPWM_disableCounterCompareShadowLoadMode \ + EPWM_disableCounterCompareShadowLoadMode +#define HRPWM_getCounterCompareShadowStatus \ + EPWM_getCounterCompareShadowStatus + +// +// Action Qualifier module related APIs +// +#define HRPWM_setActionQualifierShadowLoadMode \ + EPWM_setActionQualifierShadowLoadMode +#define HRPWM_disableActionQualifierShadowLoadMode \ + EPWM_disableActionQualifierShadowLoadMode +#define HRPWM_setActionQualifierT1TriggerSource \ + EPWM_setActionQualifierT1TriggerSource +#define HRPWM_setActionQualifierT2TriggerSource \ + EPWM_setActionQualifierT2TriggerSource +#define HRPWM_setActionQualifierAction EPWM_setActionQualifierAction +#define HRPWM_setActionQualifierContSWForceShadowMode \ + EPWM_setActionQualifierContSWForceShadowMode +#define HRPWM_setActionQualifierContSWForceAction \ + EPWM_setActionQualifierContSWForceAction +/* HRPWM_setActionQualifierSwAction is kept for compatibility, +use HRPWM_setActionQualifierSWAction*/ +#define HRPWM_setActionQualifierSwAction EPWM_setActionQualifierSwAction +#define HRPWM_setActionQualifierSWAction EPWM_setActionQualifierSWAction +/* HRPWM_forceActionQualifierSwAction is kept for compatibility, +use HRPWM_forceActionQualifierSWAction*/ +#define HRPWM_forceActionQualifierSwAction EPWM_forceActionQualifierSwAction +#define HRPWM_forceActionQualifierSWAction EPWM_forceActionQualifierSWAction +// +// Dead Band Module related APIs +// +#define HRPWM_setDeadBandOutputSwapMode EPWM_setDeadBandOutputSwapMode +#define HRPWM_setDeadBandDelayMode EPWM_setDeadBandDelayMode +#define HRPWM_setDeadBandDelayPolarity EPWM_setDeadBandDelayPolarity +#define HRPWM_setRisingEdgeDeadBandDelayInput \ + EPWM_setRisingEdgeDeadBandDelayInput +#define HRPWM_setFallingEdgeDeadBandDelayInput \ + EPWM_setFallingEdgeDeadBandDelayInput +#define HRPWM_setDeadBandControlShadowLoadMode \ + EPWM_setDeadBandControlShadowLoadMode +#define HRPWM_disableDeadBandControlShadowLoadMode \ + EPWM_disableDeadBandControlShadowLoadMode +#define HRPWM_setRisingEdgeDelayCountShadowLoadMode \ + EPWM_setRisingEdgeDelayCountShadowLoadMode +#define HRPWM_disableRisingEdgeDelayCountShadowLoadMode \ + EPWM_disableRisingEdgeDelayCountShadowLoadMode +#define HRPWM_setFallingEdgeDelayCountShadowLoadMode \ + EPWM_setFallingEdgeDelayCountShadowLoadMode +#define HRPWM_disableFallingEdgeDelayCountShadowLoadMode \ + EPWM_disableFallingEdgeDelayCountShadowLoadMode +#define HRPWM_setDeadBandCounterClock EPWM_setDeadBandCounterClock +#define HRPWM_setRisingEdgeDelayCount EPWM_setRisingEdgeDelayCount +#define HRPWM_setFallingEdgeDelayCount EPWM_setFallingEdgeDelayCount + +// +// Chopper module related APIs +// +#define HRPWM_enableChopper EPWM_enableChopper +#define HRPWM_disableChopper EPWM_disableChopper +#define HRPWM_setChopperDutyCycle EPWM_setChopperDutyCycle +#define HRPWM_setChopperFreq EPWM_setChopperFreq +#define HRPWM_setChopperFirstPulseWidt EPWM_setChopperFirstPulseWidth + +// +// Trip Zone module related APIs +// +#define HRPWM_enableTripZoneSignals EPWM_enableTripZoneSignals +#define HRPWM_disableTripZoneSignals EPWM_disableTripZoneSignals +#define HRPWM_setTripZoneDigitalCompareEventCondition \ + EPWM_setTripZoneDigitalCompareEventCondition +#define HRPWM_enableTripZoneAdvAction EPWM_enableTripZoneAdvAction +#define HRPWM_disableTripZoneAdvAction EPWM_disableTripZoneAdvAction +#define HRPWM_setTripZoneAction EPWM_setTripZoneAction +#define HRPWM_setTripZoneAdvAction EPWM_setTripZoneAdvAction +#define HRPWM_setTripZoneAdvDigitalCompareActionA \ + EPWM_setTripZoneAdvDigitalCompareActionA +#define HRPWM_setTripZoneAdvDigitalCompareActionB \ + EPWM_setTripZoneAdvDigitalCompareActionB +#define HRPWM_enableTripZoneInterrupt EPWM_enableTripZoneInterrupt +#define HRPWM_disableTripZoneInterrupt EPWM_disableTripZoneInterrupt + +// +// HRPWM_getTripZoneInterruptStatus API define is obsolete please use +// HRPWM_getTripZoneFlagStatus going forward. +// +#define HRPWM_getTripZoneInterruptStatus EPWM_getTripZoneFlagStatus +#define HRPWM_getTripZoneFlagStatus EPWM_getTripZoneFlagStatus + +// +// HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete +// please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward. +// +#define HRPWM_getCycleByCycleTripZoneInterruptStatus \ + HRPWM_getCycleByCycleTripZoneFlagStatus +#define HRPWM_getCycleByCycleTripZoneFlagStatus \ + EPWM_getCycleByCycleTripZoneFlagStatus + +// +// HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use +// HRPWM_getOneShotTripZoneFlagStatus going forward. +// +#define HRPWM_getOneShotTripZoneInterruptStatus \ + HRPWM_getOneShotTripZoneFlagStatus +#define HRPWM_getOneShotTripZoneFlagStatus \ + EPWM_getOneShotTripZoneFlagStatus +#define HRPWM_selectCycleByCycleTripZoneClearEvent \ + EPWM_selectCycleByCycleTripZoneClearEvent + +// +// HRPWM_clearTripZoneInterruptFlag is obsolete please use +// HRPWM_clearTripZoneFlag going forward. +// +#define HRPWM_clearTripZoneInterruptFlag HRPWM_clearTripZoneFlag +#define HRPWM_clearTripZoneFlag EPWM_clearTripZoneFlag + +// +// HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use +// HRPWM_clearCycleByCycleTripZoneFlag going forward. +// +#define HRPWM_clearCycleByCycleTripZoneInterruptFlag \ + HRPWM_clearCycleByCycleTripZoneFlag +#define HRPWM_clearCycleByCycleTripZoneFlag \ + EPWM_clearCycleByCycleTripZoneFlag + +// +// HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use +// HRPWM_clearOneShotTripZoneFlag going forward. +// +#define HRPWM_clearOneShotTripZoneInterruptFlag \ + HRPWM_clearOneShotTripZoneFlag +#define HRPWM_clearOneShotTripZoneFlag \ + EPWM_clearOneShotTripZoneFlag +#define HRPWM_forceTripZoneEvent EPWM_forceTripZoneEvent + +// +// Event Trigger related APIs +// +#define HRPWM_enableInterrupt EPWM_enableInterrupt +#define HRPWM_disableInterrupt EPWM_disableInterrupt +#define HRPWM_setInterruptSource EPWM_setInterruptSource +#define HRPWM_setInterruptEventCount EPWM_setInterruptEventCount +#define HRPWM_getEventTriggerInterruptStatus \ + EPWM_getEventTriggerInterruptStatus +#define HRPWM_clearEventTriggerInterruptFlag \ + EPWM_clearEventTriggerInterruptFlag +#define HRPWM_enableInterruptEventCountInit \ + EPWM_enableInterruptEventCountInit +#define HRPWM_disableInterruptEventCountInit \ + EPWM_disableInterruptEventCountInit +#define HRPWM_forceInterruptEventCountInit \ + EPWM_forceInterruptEventCountInit +#define HRPWM_setInterruptEventCountInitValue \ + EPWM_setInterruptEventCountInitValue +#define HRPWM_getInterruptEventCount EPWM_getInterruptEventCount +#define HRPWM_forceEventTriggerInterrupt EPWM_forceEventTriggerInterrupt + +// +// ADC SOC configuration related APIs +// +#define HRPWM_enableADCTrigger EPWM_enableADCTrigger +#define HRPWM_disableADCTrigger EPWM_disableADCTrigger +#define HRPWM_setADCTriggerSource EPWM_setADCTriggerSource +#define HRPWM_setADCTriggerEventPrescale EPWM_setADCTriggerEventPrescale +#define HRPWM_getADCTriggerFlagStatus EPWM_getADCTriggerFlagStatus +#define HRPWM_clearADCTriggerFlag EPWM_clearADCTriggerFlag +#define HRPWM_enableADCTriggerEventCountInit \ + EPWM_enableADCTriggerEventCountInit +#define HRPWM_disableADCTriggerEventCountInit \ + EPWM_disableADCTriggerEventCountInit +#define HRPWM_forceADCTriggerEventCountInit \ + EPWM_forceADCTriggerEventCountInit +#define HRPWM_setADCTriggerEventCountInitValue \ + EPWM_setADCTriggerEventCountInitValue +#define HRPWM_getADCTriggerEventCount EPWM_getADCTriggerEventCount +#define HRPWM_forceADCTrigger EPWM_forceADCTrigger + +// +// Digital Compare Module related APIs +// +#define HRPWM_selectDigitalCompareTripInput \ + EPWM_selectDigitalCompareTripInput +#define HRPWM_enableDigitalCompareBlankingWindow \ + EPWM_enableDigitalCompareBlankingWindow +#define HRPWM_disableDigitalCompareBlankingWindow \ + EPWM_disableDigitalCompareBlankingWindow +#define HRPWM_enableDigitalCompareWindowInverseMode \ + EPWM_enableDigitalCompareWindowInverseMode +#define HRPWM_disableDigitalCompareWindowInverseMode \ + EPWM_disableDigitalCompareWindowInverseMode +#define HRPWM_setDigitalCompareBlankingEvent \ + EPWM_setDigitalCompareBlankingEvent +#define HRPWM_setDigitalCompareFilterInput \ + EPWM_setDigitalCompareFilterInput +#define HRPWM_setDigitalCompareWindowOffset \ + EPWM_setDigitalCompareWindowOffset +#define HRPWM_setDigitalCompareWindowLength \ + EPWM_setDigitalCompareWindowLength +#define HRPWM_getDigitalCompareBlankingWindowOffsetCount \ + EPWM_getDigitalCompareBlankingWindowOffsetCount +#define HRPWM_getDigitalCompareBlankingWindowLengthCount \ + EPWM_getDigitalCompareBlankingWindowLengthCount +#define HRPWM_setDigitalCompareEventSource \ + EPWM_setDigitalCompareEventSource +#define HRPWM_setDigitalCompareEventSyncMode \ + EPWM_setDigitalCompareEventSyncMode +#define HRPWM_enableDigitalCompareADCTrigger \ + EPWM_enableDigitalCompareADCTrigger +#define HRPWM_disableDigitalCompareADCTrigger \ + EPWM_disableDigitalCompareADCTrigger +#define HRPWM_enableDigitalCompareSyncEvent \ + EPWM_enableDigitalCompareSyncEvent +#define HRPWM_disableDigitalCompareSyncEvent \ + EPWM_disableDigitalCompareSyncEvent +#define HRPWM_enableDigitalCompareCounterCapture \ + EPWM_enableDigitalCompareCounterCapture +#define HRPWM_disableDigitalCompareCounterCapture \ + EPWM_disableDigitalCompareCounterCapture +#define HRPWM_setDigitalCompareCounterShadowMode \ + EPWM_setDigitalCompareCounterShadowMode +#define HRPWM_getDigitalCompareCaptureStatus \ + EPWM_getDigitalCompareCaptureStatus +#define HRPWM_getDigitalCompareCaptureCount \ + EPWM_getDigitalCompareCaptureCount +#define HRPWM_enableDigitalCompareTripCombinationInput \ + EPWM_enableDigitalCompareTripCombinationInput +#define HRPWM_disableDigitalCompareTripCombinationInput \ + EPWM_disableDigitalCompareTripCombinationInput + +// +// Valley switching related APIs +// +#define HRPWM_enableValleyCapture EPWM_enableValleyCapture +#define HRPWM_disableValleyCapture EPWM_disableValleyCapture +#define HRPWM_startValleyCapture EPWM_startValleyCapture +#define HRPWM_setValleyTriggerSource EPWM_setValleyTriggerSource +#define HRPWM_setValleyTriggerEdgeCounts EPWM_setValleyTriggerEdgeCounts +#define HRPWM_enableValleyHWDelay EPWM_enableValleyHWDelay +#define HRPWM_disableValleyHWDelay EPWM_disableValleyHWDelay +#define HRPWM_setValleySWDelayValue EPWM_setValleySWDelayValue +#define HRPWM_setValleyDelayDivider EPWM_setValleyDelayDivider +#define HRPWM_getValleyEdgeStatus EPWM_getValleyEdgeStatus +#define HRPWM_getValleyCount EPWM_getValleyCount +#define HRPWM_getValleyHWDelay EPWM_getValleyHWDelay + +// +// Global Load feature related APIs +// +#define HRPWM_enableGlobalLoad EPWM_enableGlobalLoad +#define HRPWM_disableGlobalLoad EPWM_disableGlobalLoad +#define HRPWM_setGlobalLoadTrigger EPWM_setGlobalLoadTrigger +#define HRPWM_setGlobalLoadEventPrescale EPWM_setGlobalLoadEventPrescale +#define HRPWM_getGlobalLoadEventCount EPWM_getGlobalLoadEventCount +#define HRPWM_disableGlobalLoadOneShotMode EPWM_disableGlobalLoadOneShotMode +#define HRPWM_enableGlobalLoadOneShotMode EPWM_enableGlobalLoadOneShotMode +#define HRPWM_setGlobalLoadOneShotLatch EPWM_setGlobalLoadOneShotLatch +#define HRPWM_forceGlobalLoadOneShotEvent EPWM_forceGlobalLoadOneShotEvent +#define HRPWM_enableGlobalLoadRegisters EPWM_enableGlobalLoadRegisters +#define HRPWM_disableGlobalLoadRegisters EPWM_disableGlobalLoadRegisters +#define HRPWM_setEmulationMode EPWM_setEmulationMode + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks HRPWM base address. +//! +//! \param base specifies the HRPWM module base address. +//! +//! This function determines if an HRPWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool HRPWM_isBaseValid(uint32_t base) +{ + return((base == EPWM1_BASE) || (base == EPWM2_BASE) || + (base == EPWM3_BASE) || (base == EPWM4_BASE) || + (base == EPWM5_BASE) || (base == EPWM6_BASE) || + (base == EPWM7_BASE) || (base == EPWM8_BASE)); +} +#endif +//***************************************************************************** +// +//! Sets the consolidated phase shift value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the consolidated phase shift count value. +//! +//! This function sets the consolidated phase shift value, that is, both TBPHS +//! and TBPHSHR values are configured together. +//! +//! Call EPWM_enablePhaseShiftLoad & HRPWM_enableHRPhaseShiftLoad() functions +//! to enable loading of the phaseCount in high resolution mode. +//! +//! \b Note: phaseCount is a 24-bit value. +//! \b Note: For configuring TBPHS = 0x3C, TBPHSHR = 0x2; +//! phaseCount = 0x3C02 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(phaseCount < 0x1000000U); + + // + // Write to TBPHS:TBPHSHR bits + // + HWREG(base + HRPWM_O_TBPHS) = phaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution phase shift value. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPhaseCount is the high resolution phase shift count value. +//! +//! This function sets only the high resolution phase shift(TBPHSHR) value. +//! Call the HRPWM_enableHRPhaseShiftLoad() function to enable loading of +//! the hrPhaseCount. +//! +//! \b Note: hrPhaseCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResPhaseShiftOnly(uint32_t base, uint16_t hrPhaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPhaseCount < 256U); + + // + // Write to TBPHSHR bits + // + HWREGH(base + HRPWM_O_TBPHS) = hrPhaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets the consolidated period of time base counter used in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is the consolidated period count value. +//! +//! This function sets the consolidated period of time base counter value +//! (TBPRD:TBPRDHR) required in high resolution mode. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct periodCount. +//! +//! \b Note: periodCount is a 24 bit value. +//! \b Note: For configuring TBPRD = 0x3C, TBPRDHR = 0xA; +//! periodCount = 0x3C0A +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(periodCount < 0x1000000U); + + // + // Write to TBPRD:TBPRDHR bits + // + HWREG(base + HRPWM_O_TBPRDHR) = periodCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution time base counter. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPeriodCount is the high resolution period count value. +//! +//! This function sets only the high resolution time base counter(TBPRDHR) +//! value. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct hrPeriodCount. +//! +//! \b Note: hrPeriodCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResTimeBasePeriodOnly(uint32_t base, uint16_t hrPeriodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPeriodCount < 256U); + + // + // Write to TBPRDHR bits + // + HWREGH(base + HRPWM_O_TBPRDHR) = hrPeriodCount << 8U; +} + +//***************************************************************************** +// +//! Gets the consolidated time base period count used in HR mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the consolidated time base period(TBPRD:TBPRDHR) value +//! used in high resolution mode. +//! +//! \return The consolidated time base period count value. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRD:TBPRDHR bit + // + return(HWREG(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Gets the only the high resolution time base period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets only the high resolution time base period(TBPRDHR) value. +//! +//! \return The high resolution time base period count value. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResTimeBasePeriodOnly(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRDHR bit + // + return(HWREGH(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Sets the high resolution edge controlled by MEP (Micro Edge Positioner). +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge +//! Positioner). +//! +//! This function sets the edge of the PWM that is controlled by MEP (Micro +//! Edge Positioner). Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepEdgeMode +//! - HRPWM_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_MEP_CTRL_RISING_EDGE - MEP (Micro Edge Positioner) +//! controls rising edge. +//! - HRPWM_MEP_CTRL_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls falling edge. +//! - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls both edges. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPEdgeMode mepEdgeMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << (uint16_t)channel )) | + ((uint16_t)mepEdgeMode << (uint16_t)channel)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the MEP (Micro Edge Positioner) control mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the mode (register type) the MEP (Micro Edge Positioner) +//! will control. Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepCtrlMode +//! - HRPWM_MEP_DUTY_PERIOD_CTRL - MEP (Micro Edge Positioner) is +//! controlled by value of CMPAHR/ +//! CMPBHR(depending on the value of +//! channel) or TBPRDHR. +//! - HRPWM_MEP_PHASE_CTRL - MEP (Micro Edge Positioner) is +//! controlled by TBPHSHR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPCtrlMode mepCtrlMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the MEP control + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x1U << ((uint16_t)channel + 2U))) | + ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution comparator load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param loadEvent is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the shadow load mode of the high resolution comparator. +//! The function sets the COMPA or COMPB register depending on the channel +//! variable. +//! Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - loadEvent +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the CMPAHR or CMPBHR load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << ((uint16_t)channel + 3U))) | + ((uint16_t)loadEvent << ((uint16_t)channel + 3U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableOutputSwap is the output swap flag. +//! +//! This function sets the HRPWM output swap mode. If enableOutputSwap is true, +//! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA +//! output. If it is false ePWMxA and ePWMxB outputs are unchanged. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set output swap mode + // + EALLOW; + if(enableOutputSwap) + { + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_SWAPAB; + } + else + { + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_SWAPAB; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output on ePWMxB +//! +//! \param base is the base address of the EPWM module. +//! \param outputOnB is the output signal on ePWMxB. +//! +//! This function sets the HRPWM output signal on ePWMxB. If outputOnB is +//! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of +//! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is +//! ePWMxB. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the output on ePWM B + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(HRPWM_HRCNFG_SELOUTB)) | + ((uint16_t)outputOnB << 5U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables MEP (Micro Edge Positioner) automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the MEP (Micro Edge Positioner) to automatically +//! scale HRMSTEP. +//! +//! The SFO library will calculate required MEP steps per coarse steps and +//! feed it to HRMSTEP register. The MEP calibration module will use the value +//! in HRMSTEP to determine appropriate number of MEP steps represented by +//! fractional duty cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Enable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Disables MEP automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the MEP (Micro Edge Positioner) from automatically +//! scaling HRMSTEP. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Disable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of high resolution phase shift value which is +//! set by the function HRPWM_setPhaseShift(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of high resolution phase shift value. +//! +//! \return +// +//***************************************************************************** +static inline void +HRPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution PWMSYNC source. +//! +//! \param base is the base address of the EPWM module. +//! \param syncPulseSource is the PWMSYNC source. +//! +//! This function sets the high resolution PWMSYNC pulse source. +//! Valid values for syncPulseSource are: +//! - HRPWM_PWMSYNC_SOURCE_PERIOD - Counter equals Period. +//! - HRPWM_PWMSYNC_SOURCE_ZERO - Counter equals zero. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_UP - Counter equals COMPC when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN - Counter equals COMPC when +//! counting down. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_UP - Counter equals COMPD when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN - Counter equals COMPD when +//! counting down. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource) +{ + // + // Set the PWMSYNC source + // + EALLOW; + + // + // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD + // or HRPWM_PWMSYNC_SOURCE_ZERO + // + if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP) + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & + ~(HRPWM_HRPCTL_PWMSYNCSELX_M | HRPWM_HRPCTL_PWMSYNCSEL)) | + ((uint16_t)syncPulseSource << 1U)); + } + else + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & ~HRPWM_HRPCTL_PWMSYNCSELX_M) | + ((uint16_t)syncPulseSource << HRPWM_HRPCTL_PWMSYNCSELX_S)); + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the Translator Remainder value. +//! +//! \param base is the base address of the EPWM module. +//! \param trremVal is the translator remainder value. +//! +//! This function sets the Translator Remainder value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(trremVal < 2048U); + + // + // Set Translator Remainder value + // + EALLOW; + HWREGH(base + HRPWM_O_TRREM) = (trremVal & HRPWM_TRREM_TRREM_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the consolidated counter compare values in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param compCount is the consolidated counter compare count value. +//! +//! This function sets the consolidated counter compare(CMPx:CMPxHR) value +//! required in high resolution mode for counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: compCount is a 24 bit value. +//! \b Note: For configuring CMPA = 0xB4, CMPAHR = 0x64; value of +//! compCount = 0xB464 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint32_t compCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(compCount < 0x1000000U); + + // + // Write to counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPA:CMPAHR + // + HWREG(base + HRPWM_O_CMPA) = compCount << 8U; + } + else + { + // + // Write to CMPB:CMPBHR + // + HWREG(base + HRPWM_O_CMPB) = compCount << 8U; + } +} + +//***************************************************************************** +// +//! Sets only the high resolution counter compare value. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param hrCompCount is the high resolution counter compare count value. +//! +//! This function sets the high resolution counter compare value(CMPxHR) for +//! counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: hrCompCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint16_t hrCompCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrCompCount < 256U); + + // + // Write to the high resolution counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPAHR + // + HWREGH(base + HRPWM_O_CMPA) = hrCompCount << 8U; + } + else + { + // + // Write to CMPBHR + // + HWREGH(base + HRPWM_O_CMPB) = hrCompCount << 8U; + } +} + +//***************************************************************************** +// +//! Gets the consolidated counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets the consolidated counter compare(CMPx:CMPxHR) value +//! used in high resolution for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! +//! \return None. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint32_t compCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + compCount = HWREG(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + compCount = HWREG(base + HRPWM_O_CMPB) >> 8U; + } + return(compCount); +} + +//***************************************************************************** +// +//! Gets only the high resolution counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets only the high resolution counter compare(CMPxHR) value +//! for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint16_t hrCompCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPB) >> 8U; + } + return(hrCompCount); +} + +//***************************************************************************** +// +//! Sets the consolidated RED count in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the high resolution RED count. +//! +//! This function sets the consolidated RED (Rising Edge Delay) count +//! (DBRED:DBREDHR) value used in high resolution mode. The value of +//! redCount should be less than 0x200000. +//! +//! \b Note: redCount is a 21 bit value. +//! \b Note: For configuring DBRED = 0x4, DBREDHR = 0x1; value of +//! redCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(redCount < 0x200000U); + + // + // Set the consolidated RED (Rising Edge Delay) count + // + HWREG(base + HRPWM_O_DBREDHR) = redCount << 9U; +} + +//***************************************************************************** +// +//! Sets the high resolution RED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrRedCount is the high resolution RED count. +//! +//! This function sets only the high resolution RED (Rising Edge Delay) +//! count(DBREDHR) value. +//! The value of hrRedCount should be less than 128. +//! +//! \b Note: hrRedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResRisingEdgeDelayOnly(uint32_t base, uint16_t hrRedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrRedCount < 128U); + + // + // Set the High Resolution RED (Rising Edge Delay) count only + // + HWREGH(base + HRPWM_O_DBREDHR) = hrRedCount << 9U; +} + +//***************************************************************************** +// +//! Sets the consolidated FED value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the high resolution FED count. +//! +//! This function sets the consolidated FED (Falling Edge Delay) count +//! (DBFED: DBFEDHR) value used in high resolution mode. The value of fedCount +//! should be less than 0x200000. +//! +//! \b Note: fedCount is a 21 bit value. +//! \b Note: For configuring DBFED = 0x4, DBFEDHR = 0x1; value of +//! fedCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(fedCount < 0x200000U); + + // + // Set the High Resolution FED (Falling Edge Delay) count + // + HWREG(base + HRPWM_O_DBFEDHR) = fedCount << 9U; +} + +//***************************************************************************** +// +//! Sets high resolution FED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrFedCount is the high resolution FED count. +//! +//! This function sets only the high resolution FED (Falling Edge Delay) count +//! (DBFEDHR)value. The value of hrFedCount should be less than 128. +//! +//! \b Note: hrFedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrFedCount < 128U); + + // + // Set the high resolution FED (Falling Edge Delay) count + // + HWREGH(base + HRPWM_O_DBFEDHR) = hrFedCount << 9U; +} + +//***************************************************************************** +// +//! Set high resolution MEP (Micro Edge Positioner) step. +//! +//! \param base is the base address of the EPWM module. +//! \param mepCount is the high resolution MEP (Micro Edge Positioner) step +//! count. +//! +//! This function sets the high resolution MEP (Micro Edge Positioner) step +//! count. The maximum value for the MEP count step is 255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPStep(uint32_t base, uint16_t mepCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(mepCount < 256U); + + // + // Set HRPWM MEP count + // + EALLOW; + HWREGH(base + HRPWM_O_HRMSTEP) = + ((HWREGH(base + HRPWM_O_HRMSTEP) & ~HRPWM_HRMSTEP_HRMSTEP_M) | + mepCount); + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution Dead Band MEP (Micro Edge Positioner) control. +//! +//! \param base is the base address of the EPWM module. +//! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control +//! edge. +//! +//! This function sets the high resolution Dead Band edge that the MEP (Micro +//! Edge Positioner) controls Valid values for mepDBEdge are: +//! - HRPWM_DB_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_DB_MEP_CTRL_RED - MEP (Micro Edge Positioner) controls +//! Rising Edge Delay +//! - HRPWM_DB_MEP_CTRL_FED - MEP (Micro Edge Positioner) controls +//! Falling Edge Delay +//! - HRPWM_DB_MEP_CTRL_RED_FED - MEP (Micro Edge Positioner) controls both +//! Falling and Rising edge delays +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, + HRPWM_MEPDeadBandEdgeMode mepDBEdge) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM DB edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_EDGMODEDB_M) | + ((uint16_t)mepDBEdge)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band RED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Rising Edge Delay(RED)Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM RED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBRED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBRED_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band FED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Falling Edge Delay(FED) Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM FED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBFED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBFED_S)); + EDIS; +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // HRPWM_H + diff --git a/gpio_bitfield_cpu1/device/driverlib/hw_reg_inclusive_terminology.h b/gpio_bitfield_cpu1/device/driverlib/hw_reg_inclusive_terminology.h new file mode 100644 index 0000000..d3dc018 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/hw_reg_inclusive_terminology.h @@ -0,0 +1,29 @@ +#ifndef HW_REG_INCLUSIVE_TERMINOLOGY_H +#define HW_REG_INCLUSIVE_TERMINOLOGY_H + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_CTL_CONTROLLER_PERIPHERAL SPI_CTL_MASTER_SLAVE +#define SPI_PRI_PTEINV SPI_PRI_STEINV + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_O_TAR I2C_O_SAR + +#define I2C_TAR_TAR_S I2C_SAR_SAR_S +#define I2C_TAR_TAR_M I2C_SAR_SAR_M + +#define I2C_IER_AAT I2C_IER_AAS + +#define I2C_STR_AAT I2C_STR_AAS +#define I2C_STR_TDIR I2C_STR_SDIR + +#define I2C_MDR_CNT I2C_MDR_MST + + + +#endif // HW_REG_INCLUSIVE_TERMINOLOGY_H diff --git a/gpio_bitfield_cpu1/device/driverlib/i2c.c b/gpio_bitfield_cpu1/device/driverlib/i2c.c new file mode 100644 index 0000000..692f7a2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/i2c.c @@ -0,0 +1,351 @@ +//########################################################################### +// +// FILE: i2c.c +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "i2c.h" + +//***************************************************************************** +// +// I2C_initController +// +//***************************************************************************** +void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((10000000U / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (10000000U / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_initControllerModuleFrequency +// +//***************************************************************************** +void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((moduleFrequency / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (moduleFrequency / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_enableInterrupt +// +//***************************************************************************** +void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the desired basic interrupts + // + HWREGH(base + I2C_O_IER) |= (intFlags & 0xFFFFU); + + // + // Enabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) |= I2C_IER_AAT; + } + + // + // Enable desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFIENA; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// I2C_disableInterrupt +// +//***************************************************************************** +void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the desired basic interrupts. + // + HWREGH(base + I2C_O_IER) &= ~(intFlags & 0xFFFFU); + + // + // Disabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) &= ~I2C_IER_AAT; + } + + // + // Disable the desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_TXFFIENA); + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) &= ~(I2C_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// I2C_getInterruptStatus +// +//***************************************************************************** +uint32_t +I2C_getInterruptStatus(uint32_t base) +{ + uint32_t temp; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return only the status bits associated with interrupts. + // + temp = (uint32_t)HWREGH(base + I2C_O_STR) & (uint32_t)I2C_STR_INTMASK; + + // + // Read FIFO interrupt flags. + // + if((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFINT) != 0U) + { + temp |= I2C_INT_TXFF; + } + + if((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFINT) != 0U) + { + temp |= I2C_INT_RXFF; + } + + return(temp); +} + +//***************************************************************************** +// +// I2C_clearInterruptStatus +// +//***************************************************************************** +void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the interrupt flags that are located in STR. + // + HWREGH(base + I2C_O_STR) = ((uint16_t)intFlags & I2C_STR_INTMASK); + + // + // Clear the FIFO interrupt flags if needed. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFINTCLR; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFINTCLR; + } +} +//***************************************************************************** +// +// I2C_configureModuleFrequency +// +//***************************************************************************** +void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} +//***************************************************************************** +// +// I2C_configureModuleClockFrequency +// +//***************************************************************************** +void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} diff --git a/gpio_bitfield_cpu1/device/driverlib/i2c.h b/gpio_bitfield_cpu1/device/driverlib/i2c.h new file mode 100644 index 0000000..634c4c8 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/i2c.h @@ -0,0 +1,1386 @@ +//########################################################################### +// +// FILE: i2c.h +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef I2C_H +#define I2C_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup i2c_api I2C +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2c.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// I2C Controller commands. +// +//***************************************************************************** +#define I2C_CONTROLLER_SEND_MODE 0x0600U //!< Controller-transmitter mode +#define I2C_CONTROLLER_RECEIVE_MODE 0x0400U //!< Controller-receiver mode +#define I2C_TARGET_SEND_MODE 0x0200U //!< Target-transmitter mode +#define I2C_TARGET_RECEIVE_MODE 0x0000U //!< Target-receiver mode + +#define I2C_REPEAT_MODE 0x0080U //!< Only applies to Controller mode +#define I2C_START_BYTE_MODE 0x0010U //!< Enable start byte mode +#define I2C_FREE_DATA_FORMAT 0x0008U //!< Enable free data (no addr) format + +//***************************************************************************** +// +// I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(), +// I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by +// I2C_getInterruptStatus(). +// +//***************************************************************************** +#define I2C_INT_ARB_LOST 0x00001U //!< Arbitration-lost interrupt +#define I2C_INT_NO_ACK 0x00002U //!< NACK interrupt +#define I2C_INT_REG_ACCESS_RDY 0x00004U //!< Register-access-ready interrupt +#define I2C_INT_RX_DATA_RDY 0x00008U //!< Receive-data-ready interrupt +#define I2C_INT_TX_DATA_RDY 0x00010U //!< Transmit-data-ready interrupt +#define I2C_INT_STOP_CONDITION 0x00020U //!< Stop condition detected +#define I2C_INT_ADDR_TARGET 0x00200U //!< Addressed as target interrupt +#define I2C_INT_RXFF 0x10000U //!< RX FIFO level interrupt +#define I2C_INT_TXFF 0x20000U //!< TX FIFO level interrupt + + +// +// Helpful define to mask out the bits in the I2CSTR register that aren't +// associated with interrupts. +// +#define I2C_STR_INTMASK ((uint16_t)I2C_INT_ARB_LOST | \ + (uint16_t)I2C_INT_NO_ACK | \ + (uint16_t)I2C_INT_REG_ACCESS_RDY | \ + (uint16_t)I2C_INT_RX_DATA_RDY | \ + (uint16_t)I2C_INT_TX_DATA_RDY | \ + (uint16_t)I2C_INT_STOP_CONDITION | \ + (uint16_t)I2C_INT_ADDR_TARGET) + + + + +//***************************************************************************** +// +// Flags for use as the stsFlags parameter of I2C_clearStatus() and to be +// returned by I2C_getStatus(). +// +//***************************************************************************** +#define I2C_STS_ARB_LOST 0x0001U //!< Arbitration-lost +#define I2C_STS_NO_ACK 0x0002U //!< No-acknowledgment (NACK) +#define I2C_STS_REG_ACCESS_RDY 0x0004U //!< Register-access-ready (ARDY) +#define I2C_STS_RX_DATA_RDY 0x0008U //!< Receive-data-ready +#define I2C_STS_TX_DATA_RDY 0x0010U //!< Transmit-data-ready +#define I2C_STS_STOP_CONDITION 0x0020U //!< Stop condition detected +#define I2C_STS_ADDR_ZERO 0x0100U //!< Address of all zeros detected +#define I2C_STS_ADDR_TARGET 0x0200U //!< Addressed as target +#define I2C_STS_TX_EMPTY 0x0400U //!< Transmit shift register empty +#define I2C_STS_RX_FULL 0x0800U //!< Receive shift register full +#define I2C_STS_BUS_BUSY 0x1000U //!< Bus busy, wait for STOP or reset +#define I2C_STS_NACK_SENT 0x2000U //!< NACK was sent +#define I2C_STS_TARGET_DIR 0x4000U //!< Addressed as target transmitter + +#endif + + +//***************************************************************************** +// +//! I2C interrupts to be returned by I2C_getInterruptSource(). +// +//***************************************************************************** +typedef enum +{ + I2C_INTSRC_NONE, //!< No interrupt pending + I2C_INTSRC_ARB_LOST, //!< Arbitration-lost interrupt + I2C_INTSRC_NO_ACK, //!< NACK interrupt + I2C_INTSRC_REG_ACCESS_RDY, //!< Register-access-ready interrupt + I2C_INTSRC_RX_DATA_RDY, //!< Receive-data-ready interrupt + I2C_INTSRC_TX_DATA_RDY, //!< Transmit-data-ready interrupt + I2C_INTSRC_STOP_CONDITION, //!< Stop condition detected + I2C_INTSRC_ADDR_TARGET, //!< Addressed as target interrupt +} I2C_InterruptSource; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by I2C_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + I2C_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + I2C_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + I2C_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + I2C_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + I2C_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + I2C_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + I2C_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + I2C_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + I2C_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + I2C_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + I2C_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + I2C_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + I2C_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + I2C_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + I2C_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + I2C_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} I2C_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by I2C_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + I2C_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + I2C_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + I2C_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + I2C_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + I2C_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + I2C_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + I2C_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + I2C_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + I2C_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + I2C_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + I2C_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + I2C_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + I2C_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + I2C_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + I2C_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + I2C_FIFO_RXFULL = 0x0010U //!< Receive FIFO full +} I2C_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setBitCount() as the \e size parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_BITCOUNT_1 = 1U, //!< 1 bit per data byte + I2C_BITCOUNT_2 = 2U, //!< 2 bits per data byte + I2C_BITCOUNT_3 = 3U, //!< 3 bits per data byte + I2C_BITCOUNT_4 = 4U, //!< 4 bits per data byte + I2C_BITCOUNT_5 = 5U, //!< 5 bits per data byte + I2C_BITCOUNT_6 = 6U, //!< 6 bits per data byte + I2C_BITCOUNT_7 = 7U, //!< 7 bits per data byte + I2C_BITCOUNT_8 = 0U //!< 8 bits per data byte +} I2C_BitCount; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setAddressMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_ADDR_MODE_7BITS = 0x0000U, //!< 7-bit address + I2C_ADDR_MODE_10BITS = 0x0100U //!< 10-bit address +} I2C_AddressMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! If SCL is low, keep it low. If high, stop when it goes low again. + I2C_EMULATION_STOP_SCL_LOW = 0x0000U, + //! Continue I2C operation regardless + I2C_EMULATION_FREE_RUN = 0x4000U +} I2C_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_initController() as the \e dutyCycle +//! parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_DUTYCYCLE_33, //!< Clock duty cycle is 33% + I2C_DUTYCYCLE_50 //!< Clock duty cycle is 55% +} I2C_DutyCycle; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an I2C base address. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function determines if a I2C module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +I2C_isBaseValid(uint32_t base) +{ + return( + (base == I2CA_BASE) || + (base == I2CB_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) |= I2C_MDR_IRS; +} + +//***************************************************************************** +// +//! Disables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) &= ~(I2C_MDR_IRS); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions enables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST; + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions disables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST); + HWREGH(base + I2C_O_FFRX) &= ~I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or +//! \b I2C_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or +//! \b I2C_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel, + I2C_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + I2C_O_FFTX) = (HWREGH(base + I2C_O_FFTX) & + (~I2C_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + I2C_O_FFRX) = (HWREGH(base + I2C_O_FFRX) & + (~I2C_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, +//! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, +//! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel, + I2C_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (I2C_TxFIFOLevel)(HWREGH(base + I2C_O_FFTX) & + I2C_FFTX_TXFFIL_M); + *rxLevel = (I2C_RxFIFOLevel)(HWREGH(base + I2C_O_FFRX) & + I2C_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3, +//! ..., or \b I2C_FIFO_TX16 +// +//***************************************************************************** +static inline I2C_TxFIFOLevel +I2C_getTxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFST_M) >> + I2C_FFTX_TXFFST_S); + + return((I2C_TxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3, +//! ..., or \b I2C_FIFO_RX16 +// +//***************************************************************************** +static inline I2C_RxFIFOLevel +I2C_getRxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFST_M) >> + I2C_FFRX_RXFFST_S); + + return((I2C_RxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Reads I2C Module clock prescaler value. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads the I2C prescaler value which configures the I2C module +//! clock by dividing down the SYSCLK. I2C_MODULE_CLK = SYSCLK / (I2CPSC + ) +//! +//! \return Returns the I2C prescaler(I2CPSC) cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getPreScaler(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the Prescaler register. + // + return(HWREGH(base + I2C_O_PSC)); +} + +//***************************************************************************** +// +//! Sets the address that the I2C Controller places on the bus. +//! +//! \param base is the base address of the I2C instance used. +//! \param targetAddr 7-bit or 10-bit target address +//! +//! This function configures the address that the I2C Controller places on the bus +//! when initiating a transaction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setTargetAddress(uint32_t base, uint16_t targetAddr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(targetAddr <= I2C_TAR_TAR_M); + + HWREGH(base + I2C_O_TAR) = targetAddr; +} + +//***************************************************************************** +// +//! Sets the own address for this I2C module. +//! +//! \param base is the base address of the I2C Target module. +//! \param Addr is the 7-bit or 10-bit address +//! +//! This function writes the specified address. +//! +//! The parameter \e Addr is the value that is compared against the +//! target address sent by an I2C controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setOwnAddress(uint32_t base, uint16_t Addr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(Addr <= I2C_OAR_OAR_M); + + HWREGH(base + I2C_O_OAR) = Addr; +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-controller environment to determine if the +//! bus is free for another data transfer. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +static inline bool +I2C_isBusBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + return((HWREGH(base + I2C_O_STR) & I2C_STR_BB) == I2C_STR_BB); +} + +//***************************************************************************** +// +//! Gets the current I2C module status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the status for the I2C module. +//! +//! \return The current module status, enumerated as a bit field of +//! - \b I2C_STS_ARB_LOST - Arbitration-lost +//! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK) +//! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY) +//! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready +//! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready +//! - \b I2C_STS_STOP_CONDITION - Stop condition detected +//! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected +//! - \b I2C_STS_ADDR_TARGET - Addressed as Target +//! - \b I2C_STS_TX_EMPTY - Transmit shift register empty +//! - \b I2C_STS_RX_FULL - Receive shift register full +//! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset +//! - \b I2C_STS_NACK_SENT - NACK was sent +//! - \b I2C_STS_TARGET_DIR- Addressed as Target transmitter +// +//***************************************************************************** +static inline uint16_t +I2C_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return contents of the status register + // + return(HWREGH(base + I2C_O_STR)); +} + +//***************************************************************************** +// +//! Clears I2C status flags. +//! +//! \param base is the base address of the I2C instance used. +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! +//! This function clears the specified I2C status flags. The \e stsFlags +//! parameter is the logical OR of the following values: +//! - \b I2C_STS_ARB_LOST +//! - \b I2C_STS_NO_ACK, +//! - \b I2C_STS_REG_ACCESS_RDY +//! - \b I2C_STS_RX_DATA_RDY +//! - \b I2C_STS_STOP_CONDITION +//! - \b I2C_STS_NACK_SENT +//! - \b I2C_STS_TARGET_DIR +//! +//! \note Note that some of the status flags returned by I2C_getStatus() cannot +//! be cleared by this function. Some may only be cleared by hardware or a +//! reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_clearStatus(uint32_t base, uint16_t stsFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write to the status registers to clear them. + // + HWREGH(base + I2C_O_STR) = stsFlags; +} + +//***************************************************************************** +// +//! Controls the state of the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param config is the command to be issued to the I2C module. +//! +//! This function is used to control the state of the controller and target send and +//! receive operations. The \e config is a logical OR of the following options. +//! +//! One of the following four options: +//! - \b I2C_CONTROLLER_SEND_MODE - Controller-transmitter mode +//! - \b I2C_CONTROLLER_RECEIVE_MODE - Controller-receiver mode +//! - \b I2C_TARGET_SEND_MODE - Target-transmitter mode +//! - \b I2C_TARGET_RECEIVE_MODE - Target-receiver mode +//! +//! Any of the following: +//! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count +//! - \b I2C_START_BYTE_MODE - Use start byte mode +//! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & + ~(I2C_MDR_CNT | I2C_MDR_TRX | I2C_MDR_RM | + I2C_MDR_STB | I2C_MDR_FDF)) | config; +} + +//***************************************************************************** +// +//! Sets the data byte bit count the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param size is the number of bits per data byte. +//! +//! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of +//! bits per data byte. The default and maximum size is 8 bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setBitCount(uint32_t base, I2C_BitCount size) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_BC_M) | + (uint16_t)size; +} + +//***************************************************************************** +// +//! Issues an I2C START condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a start condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStartCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the START condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STT; +} + +//***************************************************************************** +// +//! Issues an I2C STOP condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a stop condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! To check on the status of the STOP condition, I2C_getStopConditionStatus() +//! can be used. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStopCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the STOP condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STP; +} + +//***************************************************************************** +// +//! Issues a no-acknowledge (NACK) bit. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a NACK bit. This is only +//! applicable when the I2C module is acting as a receiver. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendNACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the NACK mode bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_NACKMOD; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads a byte of data from the I2C Data Receive Register. +//! +//! \return Returns the byte received from by the I2C cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the receive register. + // + return(HWREGH(base + I2C_O_DRR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! \param data is the data to be transmitted from the I2C Controller. +//! +//! This function places the supplied data into I2C Data Transmit Register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_putData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Place the data into the transmit register. + // + HWREGH(base + I2C_O_DXR) = data; +} + +//***************************************************************************** +// +//! Get stop condition status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads and returns the stop condition bit status. +//! +//! \return Returns \b true if the STP bit has been set by the device to +//! generate a stop condition when the internal data counter of the I2C module +//! has reached 0. Returns \b false when the STP bit is zero. This bit is +//! automatically cleared after the stop condition has been generated. +// +//***************************************************************************** +static inline bool +I2C_getStopConditionStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Check the stop condition bit and return appropriately. + // + return((HWREGH(base + I2C_O_MDR) & I2C_MDR_STP) != 0U); +} + +//***************************************************************************** +// +//! Set number of bytes to be to transfer or receive when repeat mode is off. +//! +//! \param base is the base address of the I2C instance used. +//! \param count is the value to be put in the I2C data count register. +//! +//! This function sets the number of bytes to transfer or receive when repeat +//! mode is off. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setDataCount(uint32_t base, uint16_t count) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the count value to the appropriate register. + // + HWREGH(base + I2C_O_CNT) = count; +} + +//***************************************************************************** +// +//! Sets the addressing mode to either 7-bit or 10-bit. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the address mode, 7-bit or 10-bit. +//! +//! This function configures the I2C module for either a 7-bit address +//! (default) or a 10-bit address. The \e mode parameter configures the address +//! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when +//! \b I2C_ADDR_MODE_7BITS. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setAddressMode(uint32_t base, I2C_AddressMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the appropriate value to the address expansion bit. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_XA) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Sets I2C emulation mode. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the I2C operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs, +//! the I2C module stops immediately. If SCL is high, the I2C module waits +//! until SCL becomes low and then stops. +//! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_FREE) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Enables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables loopback mode. This mode is only valid during controller +//! mode and is helpful during device testing as it causes data transmitted out +//! of the data transmit register to be received in data receive register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Disables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) &= ~I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Returns the current I2C interrupt source. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the event that generated an I2C basic (non-FIFO) +//! interrupt. The possible sources are the following: +//! - \b I2C_INTSRC_NONE +//! - \b I2C_INTSRC_ARB_LOST +//! - \b I2C_INTSRC_NO_ACK +//! - \b I2C_INTSRC_REG_ACCESS_RDY +//! - \b I2C_INTSRC_RX_DATA_RDY +//! - \b I2C_INTSRC_TX_DATA_RDY +//! - \b I2C_INTSRC_STOP_CONDITION +//! - \b I2C_INTSRC_ADDR_TARGET +//! +//! Calling this function will result in hardware automatically clearing the +//! current interrupt code and if ready, loading the next pending enabled +//! interrupt. It will also clear the corresponding interrupt flag if the +//! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or +//! \b I2C_INTSRC_STOP_CONDITION. +//! +//! \note Note that this function differs from I2C_getInterruptStatus() in that +//! it returns a single interrupt source. I2C_getInterruptSource() will return +//! the status of all interrupt flags possible, including the flags that aren't +//! necessarily enabled to generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline I2C_InterruptSource +I2C_getInterruptSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the interrupt source value + // + return((I2C_InterruptSource)(HWREGH(base + I2C_O_ISRC) & + I2C_ISRC_INTCODE_M)); +} + + + + + + + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle); + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! \param moduleFrequency is the module clock used by I2C module +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency); + +//***************************************************************************** +// +//! Enables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt +//! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt +//! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt +//! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt +//! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt +//! - \b I2C_INT_STOP_CONDITION - Stop condition detected +//! - \b I2C_INT_ADDR_TARGET - Addressed as target interrupt +//! - \b I2C_INT_RXFF - RX FIFO level interrupt +//! - \b I2C_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Target interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current I2C interrupt status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the interrupt status for the I2C module. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! - \b I2C_INT_ARB_LOST +//! - \b I2C_INT_NO_ACK +//! - \b I2C_INT_REG_ACCESS_RDY +//! - \b I2C_INT_RX_DATA_RDY +//! - \b I2C_INT_TX_DATA_RDY +//! - \b I2C_INT_STOP_CONDITION +//! - \b I2C_INT_ADDR_TARGET +//! - \b I2C_INT_RXFF +//! - \b I2C_INT_TXFF +//! +//! \note This function will only return the status flags associated with +//! interrupts. However, a flag may be set even if its corresponding interrupt +//! is disabled. +// +//***************************************************************************** +extern uint32_t +I2C_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \note Also note that some of the status flags returned by +//! I2C_getInterruptStatus() cannot be cleared by this function. Some may only +//! be cleared by hardware or a reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency with a given module clock +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param moduleFrequency is the rate of the module clock used by I2C module +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // I2C_H diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_adc.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_adc.h new file mode 100644 index 0000000..89bd529 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_adc.h @@ -0,0 +1,911 @@ +//########################################################################### +// +// FILE: hw_adc.h +// +// TITLE: Definitions for the ADC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ADC_H +#define HW_ADC_H + +//************************************************************************************************* +// +// The following are defines for the ADC register offsets +// +//************************************************************************************************* +#define ADC_O_CTL1 0x0U // ADC Control 1 Register +#define ADC_O_CTL2 0x1U // ADC Control 2 Register +#define ADC_O_BURSTCTL 0x2U // ADC Burst Control Register +#define ADC_O_INTFLG 0x3U // ADC Interrupt Flag Register +#define ADC_O_INTFLGCLR 0x4U // ADC Interrupt Flag Clear Register +#define ADC_O_INTOVF 0x5U // ADC Interrupt Overflow Register +#define ADC_O_INTOVFCLR 0x6U // ADC Interrupt Overflow Clear Register +#define ADC_O_INTSEL1N2 0x7U // ADC Interrupt 1 and 2 Selection Register +#define ADC_O_INTSEL3N4 0x8U // ADC Interrupt 3 and 4 Selection Register +#define ADC_O_SOCPRICTL 0x9U // ADC SOC Priority Control Register +#define ADC_O_INTSOCSEL1 0xAU // ADC Interrupt SOC Selection 1 Register +#define ADC_O_INTSOCSEL2 0xBU // ADC Interrupt SOC Selection 2 Register +#define ADC_O_SOCFLG1 0xCU // ADC SOC Flag 1 Register +#define ADC_O_SOCFRC1 0xDU // ADC SOC Force 1 Register +#define ADC_O_SOCOVF1 0xEU // ADC SOC Overflow 1 Register +#define ADC_O_SOCOVFCLR1 0xFU // ADC SOC Overflow Clear 1 Register +#define ADC_O_SOC0CTL 0x10U // ADC SOC0 Control Register +#define ADC_O_SOC1CTL 0x12U // ADC SOC1 Control Register +#define ADC_O_SOC2CTL 0x14U // ADC SOC2 Control Register +#define ADC_O_SOC3CTL 0x16U // ADC SOC3 Control Register +#define ADC_O_SOC4CTL 0x18U // ADC SOC4 Control Register +#define ADC_O_SOC5CTL 0x1AU // ADC SOC5 Control Register +#define ADC_O_SOC6CTL 0x1CU // ADC SOC6 Control Register +#define ADC_O_SOC7CTL 0x1EU // ADC SOC7 Control Register +#define ADC_O_SOC8CTL 0x20U // ADC SOC8 Control Register +#define ADC_O_SOC9CTL 0x22U // ADC SOC9 Control Register +#define ADC_O_SOC10CTL 0x24U // ADC SOC10 Control Register +#define ADC_O_SOC11CTL 0x26U // ADC SOC11 Control Register +#define ADC_O_SOC12CTL 0x28U // ADC SOC12 Control Register +#define ADC_O_SOC13CTL 0x2AU // ADC SOC13 Control Register +#define ADC_O_SOC14CTL 0x2CU // ADC SOC14 Control Register +#define ADC_O_SOC15CTL 0x2EU // ADC SOC15 Control Register +#define ADC_O_EVTSTAT 0x30U // ADC Event Status Register +#define ADC_O_EVTCLR 0x32U // ADC Event Clear Register +#define ADC_O_EVTSEL 0x34U // ADC Event Selection Register +#define ADC_O_EVTINTSEL 0x36U // ADC Event Interrupt Selection Register +#define ADC_O_OSDETECT 0x38U // ADC Open and Shorts Detect Register +#define ADC_O_COUNTER 0x39U // ADC Counter Register +#define ADC_O_REV 0x3AU // ADC Revision Register +#define ADC_O_OFFTRIM 0x3BU // ADC Offset Trim Register +#define ADC_O_PPB1CONFIG 0x40U // ADC PPB1 Config Register +#define ADC_O_PPB1STAMP 0x41U // ADC PPB1 Sample Delay Time Stamp Register +#define ADC_O_PPB1OFFCAL 0x42U // ADC PPB1 Offset Calibration Register +#define ADC_O_PPB1OFFREF 0x43U // ADC PPB1 Offset Reference Register +#define ADC_O_PPB1TRIPHI 0x44U // ADC PPB1 Trip High Register +#define ADC_O_PPB1TRIPLO 0x46U // ADC PPB1 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB2CONFIG 0x48U // ADC PPB2 Config Register +#define ADC_O_PPB2STAMP 0x49U // ADC PPB2 Sample Delay Time Stamp Register +#define ADC_O_PPB2OFFCAL 0x4AU // ADC PPB2 Offset Calibration Register +#define ADC_O_PPB2OFFREF 0x4BU // ADC PPB2 Offset Reference Register +#define ADC_O_PPB2TRIPHI 0x4CU // ADC PPB2 Trip High Register +#define ADC_O_PPB2TRIPLO 0x4EU // ADC PPB2 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB3CONFIG 0x50U // ADC PPB3 Config Register +#define ADC_O_PPB3STAMP 0x51U // ADC PPB3 Sample Delay Time Stamp Register +#define ADC_O_PPB3OFFCAL 0x52U // ADC PPB3 Offset Calibration Register +#define ADC_O_PPB3OFFREF 0x53U // ADC PPB3 Offset Reference Register +#define ADC_O_PPB3TRIPHI 0x54U // ADC PPB3 Trip High Register +#define ADC_O_PPB3TRIPLO 0x56U // ADC PPB3 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB4CONFIG 0x58U // ADC PPB4 Config Register +#define ADC_O_PPB4STAMP 0x59U // ADC PPB4 Sample Delay Time Stamp Register +#define ADC_O_PPB4OFFCAL 0x5AU // ADC PPB4 Offset Calibration Register +#define ADC_O_PPB4OFFREF 0x5BU // ADC PPB4 Offset Reference Register +#define ADC_O_PPB4TRIPHI 0x5CU // ADC PPB4 Trip High Register +#define ADC_O_PPB4TRIPLO 0x5EU // ADC PPB4 Trip Low/Trigger Time Stamp Register +#define ADC_O_INLTRIM1 0x70U // ADC Linearity Trim 1 Register +#define ADC_O_INLTRIM2 0x72U // ADC Linearity Trim 2 Register +#define ADC_O_INLTRIM3 0x74U // ADC Linearity Trim 3 Register +#define ADC_O_INLTRIM4 0x76U // ADC Linearity Trim 4 Register +#define ADC_O_INLTRIM5 0x78U // ADC Linearity Trim 5 Register +#define ADC_O_INLTRIM6 0x7AU // ADC Linearity Trim 6 Register + +#define ADC_O_RESULT0 0x0U // ADC Result 0 Register +#define ADC_O_RESULT1 0x1U // ADC Result 1 Register +#define ADC_O_RESULT2 0x2U // ADC Result 2 Register +#define ADC_O_RESULT3 0x3U // ADC Result 3 Register +#define ADC_O_RESULT4 0x4U // ADC Result 4 Register +#define ADC_O_RESULT5 0x5U // ADC Result 5 Register +#define ADC_O_RESULT6 0x6U // ADC Result 6 Register +#define ADC_O_RESULT7 0x7U // ADC Result 7 Register +#define ADC_O_RESULT8 0x8U // ADC Result 8 Register +#define ADC_O_RESULT9 0x9U // ADC Result 9 Register +#define ADC_O_RESULT10 0xAU // ADC Result 10 Register +#define ADC_O_RESULT11 0xBU // ADC Result 11 Register +#define ADC_O_RESULT12 0xCU // ADC Result 12 Register +#define ADC_O_RESULT13 0xDU // ADC Result 13 Register +#define ADC_O_RESULT14 0xEU // ADC Result 14 Register +#define ADC_O_RESULT15 0xFU // ADC Result 15 Register +#define ADC_O_PPB1RESULT 0x10U // ADC Post Processing Block 1 Result Register +#define ADC_O_PPB2RESULT 0x12U // ADC Post Processing Block 2 Result Register +#define ADC_O_PPB3RESULT 0x14U // ADC Post Processing Block 3 Result Register +#define ADC_O_PPB4RESULT 0x16U // ADC Post Processing Block 4 Result Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL1 register +// +//************************************************************************************************* +#define ADC_CTL1_INTPULSEPOS 0x4U // ADC Interrupt Pulse Position +#define ADC_CTL1_ADCPWDNZ 0x80U // ADC Power Down +#define ADC_CTL1_ADCBSYCHN_S 8U +#define ADC_CTL1_ADCBSYCHN_M 0xF00U // ADC Busy Channel +#define ADC_CTL1_ADCBSY 0x2000U // ADC Busy + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL2 register +// +//************************************************************************************************* +#define ADC_CTL2_PRESCALE_S 0U +#define ADC_CTL2_PRESCALE_M 0xFU // ADC Clock Prescaler +#define ADC_CTL2_RESOLUTION 0x40U // SOC Conversion Resolution +#define ADC_CTL2_SIGNALMODE 0x80U // SOC Signaling Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCBURSTCTL register +// +//************************************************************************************************* +#define ADC_BURSTCTL_BURSTTRIGSEL_S 0U +#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3FU // SOC Burst Trigger Source Select +#define ADC_BURSTCTL_BURSTSIZE_S 8U +#define ADC_BURSTCTL_BURSTSIZE_M 0xF00U // SOC Burst Size Select +#define ADC_BURSTCTL_BURSTEN 0x8000U // SOC Burst Mode Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLG register +// +//************************************************************************************************* +#define ADC_INTFLG_ADCINT1 0x1U // ADC Interrupt 1 Flag +#define ADC_INTFLG_ADCINT2 0x2U // ADC Interrupt 2 Flag +#define ADC_INTFLG_ADCINT3 0x4U // ADC Interrupt 3 Flag +#define ADC_INTFLG_ADCINT4 0x8U // ADC Interrupt 4 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLGCLR register +// +//************************************************************************************************* +#define ADC_INTFLGCLR_ADCINT1 0x1U // ADC Interrupt 1 Flag Clear +#define ADC_INTFLGCLR_ADCINT2 0x2U // ADC Interrupt 2 Flag Clear +#define ADC_INTFLGCLR_ADCINT3 0x4U // ADC Interrupt 3 Flag Clear +#define ADC_INTFLGCLR_ADCINT4 0x8U // ADC Interrupt 4 Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVF register +// +//************************************************************************************************* +#define ADC_INTOVF_ADCINT1 0x1U // ADC Interrupt 1 Overflow Flags +#define ADC_INTOVF_ADCINT2 0x2U // ADC Interrupt 2 Overflow Flags +#define ADC_INTOVF_ADCINT3 0x4U // ADC Interrupt 3 Overflow Flags +#define ADC_INTOVF_ADCINT4 0x8U // ADC Interrupt 4 Overflow Flags + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVFCLR register +// +//************************************************************************************************* +#define ADC_INTOVFCLR_ADCINT1 0x1U // ADC Interrupt 1 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT2 0x2U // ADC Interrupt 2 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT3 0x4U // ADC Interrupt 3 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT4 0x8U // ADC Interrupt 4 Overflow Clear Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL1N2 register +// +//************************************************************************************************* +#define ADC_INTSEL1N2_INT1SEL_S 0U +#define ADC_INTSEL1N2_INT1SEL_M 0xFU // ADCINT1 EOC Source Select +#define ADC_INTSEL1N2_INT1E 0x20U // ADCINT1 Interrupt Enable +#define ADC_INTSEL1N2_INT1CONT 0x40U // ADCINT1 Continue to Interrupt Mode +#define ADC_INTSEL1N2_INT2SEL_S 8U +#define ADC_INTSEL1N2_INT2SEL_M 0xF00U // ADCINT2 EOC Source Select +#define ADC_INTSEL1N2_INT2E 0x2000U // ADCINT2 Interrupt Enable +#define ADC_INTSEL1N2_INT2CONT 0x4000U // ADCINT2 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL3N4 register +// +//************************************************************************************************* +#define ADC_INTSEL3N4_INT3SEL_S 0U +#define ADC_INTSEL3N4_INT3SEL_M 0xFU // ADCINT3 EOC Source Select +#define ADC_INTSEL3N4_INT3E 0x20U // ADCINT3 Interrupt Enable +#define ADC_INTSEL3N4_INT3CONT 0x40U // ADCINT3 Continue to Interrupt Mode +#define ADC_INTSEL3N4_INT4SEL_S 8U +#define ADC_INTSEL3N4_INT4SEL_M 0xF00U // ADCINT4 EOC Source Select +#define ADC_INTSEL3N4_INT4E 0x2000U // ADCINT4 Interrupt Enable +#define ADC_INTSEL3N4_INT4CONT 0x4000U // ADCINT4 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCPRICTL register +// +//************************************************************************************************* +#define ADC_SOCPRICTL_SOCPRIORITY_S 0U +#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1FU // SOC Priority +#define ADC_SOCPRICTL_RRPOINTER_S 5U +#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0U // Round Robin Pointer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL1 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL1_SOC0_S 0U +#define ADC_INTSOCSEL1_SOC0_M 0x3U // SOC0 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC1_S 2U +#define ADC_INTSOCSEL1_SOC1_M 0xCU // SOC1 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC2_S 4U +#define ADC_INTSOCSEL1_SOC2_M 0x30U // SOC2 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC3_S 6U +#define ADC_INTSOCSEL1_SOC3_M 0xC0U // SOC3 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC4_S 8U +#define ADC_INTSOCSEL1_SOC4_M 0x300U // SOC4 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC5_S 10U +#define ADC_INTSOCSEL1_SOC5_M 0xC00U // SOC5 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC6_S 12U +#define ADC_INTSOCSEL1_SOC6_M 0x3000U // SOC6 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC7_S 14U +#define ADC_INTSOCSEL1_SOC7_M 0xC000U // SOC7 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL2 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL2_SOC8_S 0U +#define ADC_INTSOCSEL2_SOC8_M 0x3U // SOC8 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC9_S 2U +#define ADC_INTSOCSEL2_SOC9_M 0xCU // SOC9 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC10_S 4U +#define ADC_INTSOCSEL2_SOC10_M 0x30U // SOC10 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC11_S 6U +#define ADC_INTSOCSEL2_SOC11_M 0xC0U // SOC11 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC12_S 8U +#define ADC_INTSOCSEL2_SOC12_M 0x300U // SOC12 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC13_S 10U +#define ADC_INTSOCSEL2_SOC13_M 0xC00U // SOC13 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC14_S 12U +#define ADC_INTSOCSEL2_SOC14_M 0x3000U // SOC14 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC15_S 14U +#define ADC_INTSOCSEL2_SOC15_M 0xC000U // SOC15 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFLG1 register +// +//************************************************************************************************* +#define ADC_SOCFLG1_SOC0 0x1U // SOC0 Start of Conversion Flag +#define ADC_SOCFLG1_SOC1 0x2U // SOC1 Start of Conversion Flag +#define ADC_SOCFLG1_SOC2 0x4U // SOC2 Start of Conversion Flag +#define ADC_SOCFLG1_SOC3 0x8U // SOC3 Start of Conversion Flag +#define ADC_SOCFLG1_SOC4 0x10U // SOC4 Start of Conversion Flag +#define ADC_SOCFLG1_SOC5 0x20U // SOC5 Start of Conversion Flag +#define ADC_SOCFLG1_SOC6 0x40U // SOC6 Start of Conversion Flag +#define ADC_SOCFLG1_SOC7 0x80U // SOC7 Start of Conversion Flag +#define ADC_SOCFLG1_SOC8 0x100U // SOC8 Start of Conversion Flag +#define ADC_SOCFLG1_SOC9 0x200U // SOC9 Start of Conversion Flag +#define ADC_SOCFLG1_SOC10 0x400U // SOC10 Start of Conversion Flag +#define ADC_SOCFLG1_SOC11 0x800U // SOC11 Start of Conversion Flag +#define ADC_SOCFLG1_SOC12 0x1000U // SOC12 Start of Conversion Flag +#define ADC_SOCFLG1_SOC13 0x2000U // SOC13 Start of Conversion Flag +#define ADC_SOCFLG1_SOC14 0x4000U // SOC14 Start of Conversion Flag +#define ADC_SOCFLG1_SOC15 0x8000U // SOC15 Start of Conversion Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFRC1 register +// +//************************************************************************************************* +#define ADC_SOCFRC1_SOC0 0x1U // SOC0 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC1 0x2U // SOC1 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC2 0x4U // SOC2 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC3 0x8U // SOC3 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC4 0x10U // SOC4 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC5 0x20U // SOC5 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC6 0x40U // SOC6 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC7 0x80U // SOC7 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC8 0x100U // SOC8 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC9 0x200U // SOC9 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC10 0x400U // SOC10 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC11 0x800U // SOC11 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC12 0x1000U // SOC12 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC13 0x2000U // SOC13 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC14 0x4000U // SOC14 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC15 0x8000U // SOC15 Force Start of Conversion Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVF1 register +// +//************************************************************************************************* +#define ADC_SOCOVF1_SOC0 0x1U // SOC0 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC1 0x2U // SOC1 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC2 0x4U // SOC2 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC3 0x8U // SOC3 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC4 0x10U // SOC4 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC5 0x20U // SOC5 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC6 0x40U // SOC6 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC7 0x80U // SOC7 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC8 0x100U // SOC8 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC9 0x200U // SOC9 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC10 0x400U // SOC10 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC11 0x800U // SOC11 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC12 0x1000U // SOC12 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC13 0x2000U // SOC13 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC14 0x4000U // SOC14 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC15 0x8000U // SOC15 Start of Conversion Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVFCLR1 register +// +//************************************************************************************************* +#define ADC_SOCOVFCLR1_SOC0 0x1U // SOC0 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC1 0x2U // SOC1 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC2 0x4U // SOC2 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC3 0x8U // SOC3 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC4 0x10U // SOC4 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC5 0x20U // SOC5 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC6 0x40U // SOC6 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC7 0x80U // SOC7 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC8 0x100U // SOC8 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC9 0x200U // SOC9 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC10 0x400U // SOC10 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC11 0x800U // SOC11 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC12 0x1000U // SOC12 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC13 0x2000U // SOC13 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC14 0x4000U // SOC14 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC15 0x8000U // SOC15 Clear Start of Conversion Overflow Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC0CTL register +// +//************************************************************************************************* +#define ADC_SOC0CTL_ACQPS_S 0U +#define ADC_SOC0CTL_ACQPS_M 0x1FFU // SOC0 Acquisition Prescale +#define ADC_SOC0CTL_CHSEL_S 15U +#define ADC_SOC0CTL_CHSEL_M 0x78000U // SOC0 Channel Select +#define ADC_SOC0CTL_TRIGSEL_S 20U +#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000U // SOC0 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC1CTL register +// +//************************************************************************************************* +#define ADC_SOC1CTL_ACQPS_S 0U +#define ADC_SOC1CTL_ACQPS_M 0x1FFU // SOC1 Acquisition Prescale +#define ADC_SOC1CTL_CHSEL_S 15U +#define ADC_SOC1CTL_CHSEL_M 0x78000U // SOC1 Channel Select +#define ADC_SOC1CTL_TRIGSEL_S 20U +#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000U // SOC1 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC2CTL register +// +//************************************************************************************************* +#define ADC_SOC2CTL_ACQPS_S 0U +#define ADC_SOC2CTL_ACQPS_M 0x1FFU // SOC2 Acquisition Prescale +#define ADC_SOC2CTL_CHSEL_S 15U +#define ADC_SOC2CTL_CHSEL_M 0x78000U // SOC2 Channel Select +#define ADC_SOC2CTL_TRIGSEL_S 20U +#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000U // SOC2 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC3CTL register +// +//************************************************************************************************* +#define ADC_SOC3CTL_ACQPS_S 0U +#define ADC_SOC3CTL_ACQPS_M 0x1FFU // SOC3 Acquisition Prescale +#define ADC_SOC3CTL_CHSEL_S 15U +#define ADC_SOC3CTL_CHSEL_M 0x78000U // SOC3 Channel Select +#define ADC_SOC3CTL_TRIGSEL_S 20U +#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000U // SOC3 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC4CTL register +// +//************************************************************************************************* +#define ADC_SOC4CTL_ACQPS_S 0U +#define ADC_SOC4CTL_ACQPS_M 0x1FFU // SOC4 Acquisition Prescale +#define ADC_SOC4CTL_CHSEL_S 15U +#define ADC_SOC4CTL_CHSEL_M 0x78000U // SOC4 Channel Select +#define ADC_SOC4CTL_TRIGSEL_S 20U +#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000U // SOC4 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC5CTL register +// +//************************************************************************************************* +#define ADC_SOC5CTL_ACQPS_S 0U +#define ADC_SOC5CTL_ACQPS_M 0x1FFU // SOC5 Acquisition Prescale +#define ADC_SOC5CTL_CHSEL_S 15U +#define ADC_SOC5CTL_CHSEL_M 0x78000U // SOC5 Channel Select +#define ADC_SOC5CTL_TRIGSEL_S 20U +#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000U // SOC5 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC6CTL register +// +//************************************************************************************************* +#define ADC_SOC6CTL_ACQPS_S 0U +#define ADC_SOC6CTL_ACQPS_M 0x1FFU // SOC6 Acquisition Prescale +#define ADC_SOC6CTL_CHSEL_S 15U +#define ADC_SOC6CTL_CHSEL_M 0x78000U // SOC6 Channel Select +#define ADC_SOC6CTL_TRIGSEL_S 20U +#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000U // SOC6 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC7CTL register +// +//************************************************************************************************* +#define ADC_SOC7CTL_ACQPS_S 0U +#define ADC_SOC7CTL_ACQPS_M 0x1FFU // SOC7 Acquisition Prescale +#define ADC_SOC7CTL_CHSEL_S 15U +#define ADC_SOC7CTL_CHSEL_M 0x78000U // SOC7 Channel Select +#define ADC_SOC7CTL_TRIGSEL_S 20U +#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000U // SOC7 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC8CTL register +// +//************************************************************************************************* +#define ADC_SOC8CTL_ACQPS_S 0U +#define ADC_SOC8CTL_ACQPS_M 0x1FFU // SOC8 Acquisition Prescale +#define ADC_SOC8CTL_CHSEL_S 15U +#define ADC_SOC8CTL_CHSEL_M 0x78000U // SOC8 Channel Select +#define ADC_SOC8CTL_TRIGSEL_S 20U +#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000U // SOC8 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC9CTL register +// +//************************************************************************************************* +#define ADC_SOC9CTL_ACQPS_S 0U +#define ADC_SOC9CTL_ACQPS_M 0x1FFU // SOC9 Acquisition Prescale +#define ADC_SOC9CTL_CHSEL_S 15U +#define ADC_SOC9CTL_CHSEL_M 0x78000U // SOC9 Channel Select +#define ADC_SOC9CTL_TRIGSEL_S 20U +#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000U // SOC9 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC10CTL register +// +//************************************************************************************************* +#define ADC_SOC10CTL_ACQPS_S 0U +#define ADC_SOC10CTL_ACQPS_M 0x1FFU // SOC10 Acquisition Prescale +#define ADC_SOC10CTL_CHSEL_S 15U +#define ADC_SOC10CTL_CHSEL_M 0x78000U // SOC10 Channel Select +#define ADC_SOC10CTL_TRIGSEL_S 20U +#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000U // SOC10 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC11CTL register +// +//************************************************************************************************* +#define ADC_SOC11CTL_ACQPS_S 0U +#define ADC_SOC11CTL_ACQPS_M 0x1FFU // SOC11 Acquisition Prescale +#define ADC_SOC11CTL_CHSEL_S 15U +#define ADC_SOC11CTL_CHSEL_M 0x78000U // SOC11 Channel Select +#define ADC_SOC11CTL_TRIGSEL_S 20U +#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000U // SOC11 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC12CTL register +// +//************************************************************************************************* +#define ADC_SOC12CTL_ACQPS_S 0U +#define ADC_SOC12CTL_ACQPS_M 0x1FFU // SOC12 Acquisition Prescale +#define ADC_SOC12CTL_CHSEL_S 15U +#define ADC_SOC12CTL_CHSEL_M 0x78000U // SOC12 Channel Select +#define ADC_SOC12CTL_TRIGSEL_S 20U +#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000U // SOC12 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC13CTL register +// +//************************************************************************************************* +#define ADC_SOC13CTL_ACQPS_S 0U +#define ADC_SOC13CTL_ACQPS_M 0x1FFU // SOC13 Acquisition Prescale +#define ADC_SOC13CTL_CHSEL_S 15U +#define ADC_SOC13CTL_CHSEL_M 0x78000U // SOC13 Channel Select +#define ADC_SOC13CTL_TRIGSEL_S 20U +#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000U // SOC13 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC14CTL register +// +//************************************************************************************************* +#define ADC_SOC14CTL_ACQPS_S 0U +#define ADC_SOC14CTL_ACQPS_M 0x1FFU // SOC14 Acquisition Prescale +#define ADC_SOC14CTL_CHSEL_S 15U +#define ADC_SOC14CTL_CHSEL_M 0x78000U // SOC14 Channel Select +#define ADC_SOC14CTL_TRIGSEL_S 20U +#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000U // SOC14 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC15CTL register +// +//************************************************************************************************* +#define ADC_SOC15CTL_ACQPS_S 0U +#define ADC_SOC15CTL_ACQPS_M 0x1FFU // SOC15 Acquisition Prescale +#define ADC_SOC15CTL_CHSEL_S 15U +#define ADC_SOC15CTL_CHSEL_M 0x78000U // SOC15 Channel Select +#define ADC_SOC15CTL_TRIGSEL_S 20U +#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000U // SOC15 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSTAT register +// +//************************************************************************************************* +#define ADC_EVTSTAT_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Flag +#define ADC_EVTSTAT_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Flag +#define ADC_EVTSTAT_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Flag +#define ADC_EVTSTAT_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Flag +#define ADC_EVTSTAT_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Flag +#define ADC_EVTSTAT_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Flag +#define ADC_EVTSTAT_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Flag +#define ADC_EVTSTAT_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Flag +#define ADC_EVTSTAT_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Flag +#define ADC_EVTSTAT_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Flag +#define ADC_EVTSTAT_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Flag +#define ADC_EVTSTAT_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTCLR register +// +//************************************************************************************************* +#define ADC_EVTCLR_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Clear +#define ADC_EVTCLR_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Clear +#define ADC_EVTCLR_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Clear +#define ADC_EVTCLR_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Clear +#define ADC_EVTCLR_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Clear +#define ADC_EVTCLR_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Clear +#define ADC_EVTCLR_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Clear +#define ADC_EVTCLR_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Clear +#define ADC_EVTCLR_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Clear +#define ADC_EVTCLR_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Clear +#define ADC_EVTCLR_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Clear +#define ADC_EVTCLR_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSEL register +// +//************************************************************************************************* +#define ADC_EVTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Event Enable +#define ADC_EVTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Event Enable +#define ADC_EVTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Event Enable +#define ADC_EVTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Event Enable +#define ADC_EVTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Event Enable +#define ADC_EVTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Event Enable +#define ADC_EVTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Event Enable +#define ADC_EVTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Event Enable +#define ADC_EVTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Event Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTINTSEL register +// +//************************************************************************************************* +#define ADC_EVTINTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOSDETECT register +// +//************************************************************************************************* +#define ADC_OSDETECT_DETECTCFG_S 0U +#define ADC_OSDETECT_DETECTCFG_M 0x7U // ADC Opens and Shorts Detect Configuration + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCOUNTER register +// +//************************************************************************************************* +#define ADC_COUNTER_FREECOUNT_S 0U +#define ADC_COUNTER_FREECOUNT_M 0xFFFU // ADC Free Running Counter Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCREV register +// +//************************************************************************************************* +#define ADC_REV_TYPE_S 0U +#define ADC_REV_TYPE_M 0xFFU // ADC Type +#define ADC_REV_REV_S 8U +#define ADC_REV_REV_M 0xFF00U // ADC Revision + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOFFTRIM register +// +//************************************************************************************************* +#define ADC_OFFTRIM_OFFTRIM_S 0U +#define ADC_OFFTRIM_OFFTRIM_M 0xFFU // ADC Offset Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1CONFIG register +// +//************************************************************************************************* +#define ADC_PPB1CONFIG_CONFIG_S 0U +#define ADC_PPB1CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 1 Configuration +#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 1 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1STAMP register +// +//************************************************************************************************* +#define ADC_PPB1STAMP_DLYSTAMP_S 0U +#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 1 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB1OFFCAL_OFFCAL_S 0U +#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB1TRIPHI_LIMITHI_S 0U +#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 1 Trip High Limit +#define ADC_PPB1TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB1TRIPLO_LIMITLO_S 0U +#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 1 Trip Low Limit +#define ADC_PPB1TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB1TRIPLO_REQSTAMP_S 20U +#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 1 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2CONFIG register +// +//************************************************************************************************* +#define ADC_PPB2CONFIG_CONFIG_S 0U +#define ADC_PPB2CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 2 Configuration +#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 2 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2STAMP register +// +//************************************************************************************************* +#define ADC_PPB2STAMP_DLYSTAMP_S 0U +#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 2 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB2OFFCAL_OFFCAL_S 0U +#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB2TRIPHI_LIMITHI_S 0U +#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 2 Trip High Limit +#define ADC_PPB2TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB2TRIPLO_LIMITLO_S 0U +#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 2 Trip Low Limit +#define ADC_PPB2TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB2TRIPLO_REQSTAMP_S 20U +#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 2 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3CONFIG register +// +//************************************************************************************************* +#define ADC_PPB3CONFIG_CONFIG_S 0U +#define ADC_PPB3CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 3 Configuration +#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 3 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3STAMP register +// +//************************************************************************************************* +#define ADC_PPB3STAMP_DLYSTAMP_S 0U +#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 3 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB3OFFCAL_OFFCAL_S 0U +#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB3TRIPHI_LIMITHI_S 0U +#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 3 Trip High Limit +#define ADC_PPB3TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB3TRIPLO_LIMITLO_S 0U +#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 3 Trip Low Limit +#define ADC_PPB3TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB3TRIPLO_REQSTAMP_S 20U +#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 3 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4CONFIG register +// +//************************************************************************************************* +#define ADC_PPB4CONFIG_CONFIG_S 0U +#define ADC_PPB4CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 4 Configuration +#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 4 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4STAMP register +// +//************************************************************************************************* +#define ADC_PPB4STAMP_DLYSTAMP_S 0U +#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 4 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB4OFFCAL_OFFCAL_S 0U +#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB4TRIPHI_LIMITHI_S 0U +#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 4 Trip High Limit +#define ADC_PPB4TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB4TRIPLO_LIMITLO_S 0U +#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 4 Trip Low Limit +#define ADC_PPB4TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB4TRIPLO_REQSTAMP_S 20U +#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 4 Request Time Stamp + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1RESULT register +// +//************************************************************************************************* +#define ADC_PPB1RESULT_PPBRESULT_S 0U +#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB1RESULT_SIGN_S 16U +#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2RESULT register +// +//************************************************************************************************* +#define ADC_PPB2RESULT_PPBRESULT_S 0U +#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB2RESULT_SIGN_S 16U +#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3RESULT register +// +//************************************************************************************************* +#define ADC_PPB3RESULT_PPBRESULT_S 0U +#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB3RESULT_SIGN_S 16U +#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4RESULT register +// +//************************************************************************************************* +#define ADC_PPB4RESULT_PPBRESULT_S 0U +#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB4RESULT_SIGN_S 16U +#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_asysctl.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_asysctl.h new file mode 100644 index 0000000..4ee1c62 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_asysctl.h @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: hw_asysctl.h +// +// TITLE: Definitions for the ASYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ASYSCTL_H +#define HW_ASYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the ASYSCTL register offsets +// +//************************************************************************************************* +#define ASYSCTL_O_INTOSC1TRIM 0x20U // Internal Oscillator 1 Trim Register +#define ASYSCTL_O_INTOSC2TRIM 0x22U // Internal Oscillator 2 Trim Register +#define ASYSCTL_O_TSNSCTL 0x26U // Temperature Sensor Control Register +#define ASYSCTL_O_LOCK 0x2EU // Lock Register +#define ASYSCTL_O_ANAREFTRIMA 0x36U // Analog Reference Trim A Register +#define ASYSCTL_O_ANAREFTRIMB 0x38U // Analog Reference Trim B Register +#define ASYSCTL_O_ANAREFTRIMC 0x3AU // Analog Reference Trim C Register +#define ASYSCTL_O_ANAREFTRIMD 0x3CU // Analog Reference Trim D Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC1TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC2TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TSNSCTL register +// +//************************************************************************************************* +#define ASYSCTL_TSNSCTL_ENABLE 0x1U // Temperature Sensor Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOCK register +// +//************************************************************************************************* +#define ASYSCTL_LOCK_TSNSCTL 0x8U // Temperature Sensor Control Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMA 0x800000U // Analog Reference A Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMB 0x1000000U // Analog Reference B Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMC 0x2000000U // Analog Reference C Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMD 0x4000000U // Analog Reference D Trim Register Lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMA register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMB register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMC register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMD register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_M 0xF800U // Reference Current Trim + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_can.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_can.h new file mode 100644 index 0000000..05bc58b --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_can.h @@ -0,0 +1,514 @@ +//########################################################################### +// +// FILE: hw_can.h +// +// TITLE: Definitions for the CAN registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CAN_H +#define HW_CAN_H + +//************************************************************************************************* +// +// The following are defines for the CAN register offsets +// +//************************************************************************************************* +#define CAN_O_CTL 0x0U // CAN Control Register +#define CAN_O_ES 0x4U // Error and Status Register +#define CAN_O_ERRC 0x8U // Error Counter Register +#define CAN_O_BTR 0xCU // Bit Timing Register +#define CAN_O_INT 0x10U // Interrupt Register +#define CAN_O_TEST 0x14U // Test Register +#define CAN_O_PERR 0x1CU // CAN Parity Error Code Register +#define CAN_O_RAM_INIT 0x40U // CAN RAM Initialization Register +#define CAN_O_GLB_INT_EN 0x50U // CAN Global Interrupt Enable Register +#define CAN_O_GLB_INT_FLG 0x54U // CAN Global Interrupt Flag Register +#define CAN_O_GLB_INT_CLR 0x58U // CAN Global Interrupt Clear Register +#define CAN_O_ABOTR 0x80U // Auto-Bus-On Time Register +#define CAN_O_TXRQ_X 0x84U // CAN Transmission Request Register +#define CAN_O_TXRQ_21 0x88U // CAN Transmission Request 2_1 Register +#define CAN_O_NDAT_X 0x98U // CAN New Data Register +#define CAN_O_NDAT_21 0x9CU // CAN New Data 2_1 Register +#define CAN_O_IPEN_X 0xACU // CAN Interrupt Pending Register +#define CAN_O_IPEN_21 0xB0U // CAN Interrupt Pending 2_1 Register +#define CAN_O_MVAL_X 0xC0U // CAN Message Valid Register +#define CAN_O_MVAL_21 0xC4U // CAN Message Valid 2_1 Register +#define CAN_O_IP_MUX21 0xD8U // CAN Interrupt Multiplexer 2_1 Register +#define CAN_O_IF1CMD 0x100U // IF1 Command Register +#define CAN_O_IF1MSK 0x104U // IF1 Mask Register +#define CAN_O_IF1ARB 0x108U // IF1 Arbitration Register +#define CAN_O_IF1MCTL 0x10CU // IF1 Message Control Register +#define CAN_O_IF1DATA 0x110U // IF1 Data A Register +#define CAN_O_IF1DATB 0x114U // IF1 Data B Register +#define CAN_O_IF2CMD 0x120U // IF2 Command Register +#define CAN_O_IF2MSK 0x124U // IF2 Mask Register +#define CAN_O_IF2ARB 0x128U // IF2 Arbitration Register +#define CAN_O_IF2MCTL 0x12CU // IF2 Message Control Register +#define CAN_O_IF2DATA 0x130U // IF2 Data A Register +#define CAN_O_IF2DATB 0x134U // IF2 Data B Register +#define CAN_O_IF3OBS 0x140U // IF3 Observation Register +#define CAN_O_IF3MSK 0x144U // IF3 Mask Register +#define CAN_O_IF3ARB 0x148U // IF3 Arbitration Register +#define CAN_O_IF3MCTL 0x14CU // IF3 Message Control Register +#define CAN_O_IF3DATA 0x150U // IF3 Data A Register +#define CAN_O_IF3DATB 0x154U // IF3 Data B Register +#define CAN_O_IF3UPD 0x160U // IF3 Update Enable Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_CTL register +// +//************************************************************************************************* +#define CAN_CTL_INIT 0x1U // Initialization +#define CAN_CTL_IE0 0x2U // Interrupt line 0 Enable +#define CAN_CTL_SIE 0x4U // Status Change Interrupt Enable +#define CAN_CTL_EIE 0x8U // Error Interrupt Enable +#define CAN_CTL_DAR 0x20U // Disable Automatic Retransmission +#define CAN_CTL_CCE 0x40U // Configuration Change Enable +#define CAN_CTL_TEST 0x80U // Test Mode Enable +#define CAN_CTL_IDS 0x100U // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x200U // Auto-Bus-On Enable +#define CAN_CTL_PMD_S 10U +#define CAN_CTL_PMD_M 0x3C00U // Parity on/off +#define CAN_CTL_SWR 0x8000U // SW Reset Enable +#define CAN_CTL_INITDBG 0x10000U // Debug Mode Status +#define CAN_CTL_IE1 0x20000U // Interrupt line 1 Enable Disabled + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ES register +// +//************************************************************************************************* +#define CAN_ES_LEC_S 0U +#define CAN_ES_LEC_M 0x7U // Last Error Code +#define CAN_ES_TXOK 0x8U // Transmission status +#define CAN_ES_RXOK 0x10U // Reception status +#define CAN_ES_EPASS 0x20U // Error Passive State +#define CAN_ES_EWARN 0x40U // Warning State +#define CAN_ES_BOFF 0x80U // Bus-Off State +#define CAN_ES_PER 0x100U // Parity Error Detected + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ERRC register +// +//************************************************************************************************* +#define CAN_ERRC_TEC_S 0U +#define CAN_ERRC_TEC_M 0xFFU // Transmit Error Counter +#define CAN_ERRC_REC_S 8U +#define CAN_ERRC_REC_M 0x7F00U // Receive Error Counter +#define CAN_ERRC_RP 0x8000U // Receive Error Passive + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_BTR register +// +//************************************************************************************************* +#define CAN_BTR_BRP_S 0U +#define CAN_BTR_BRP_M 0x3FU // Baud Rate Prescaler +#define CAN_BTR_SJW_S 6U +#define CAN_BTR_SJW_M 0xC0U // Synchronization Jump Width +#define CAN_BTR_TSEG1_S 8U +#define CAN_BTR_TSEG1_M 0xF00U // Time segment +#define CAN_BTR_TSEG2_S 12U +#define CAN_BTR_TSEG2_M 0x7000U // Time segment +#define CAN_BTR_BRPE_S 16U +#define CAN_BTR_BRPE_M 0xF0000U // Baud Rate Prescaler Extension + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_INT register +// +//************************************************************************************************* +#define CAN_INT_INT0ID_S 0U +#define CAN_INT_INT0ID_M 0xFFFFU // Interrupt Identifier +#define CAN_INT_INT1ID_S 16U +#define CAN_INT_INT1ID_M 0xFF0000U // Interrupt 1 Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TEST register +// +//************************************************************************************************* +#define CAN_TEST_SILENT 0x8U // Silent Mode +#define CAN_TEST_LBACK 0x10U // Loopback Mode +#define CAN_TEST_TX_S 5U +#define CAN_TEST_TX_M 0x60U // CANTX Pin Control +#define CAN_TEST_RX 0x80U // CANRX Pin Status +#define CAN_TEST_EXL 0x100U // External Loopback Mode +#define CAN_TEST_RDA 0x200U // RAM Direct Access Enable: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_PERR register +// +//************************************************************************************************* +#define CAN_PERR_MSG_NUM_S 0U +#define CAN_PERR_MSG_NUM_M 0xFFU // Message Number +#define CAN_PERR_WORD_NUM_S 8U +#define CAN_PERR_WORD_NUM_M 0x700U // Word Number + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_RAM_INIT register +// +//************************************************************************************************* +#define CAN_RAM_INIT_KEY0 0x1U // KEY0 +#define CAN_RAM_INIT_KEY1 0x2U // KEY1 +#define CAN_RAM_INIT_KEY2 0x4U // KEY2 +#define CAN_RAM_INIT_KEY3 0x8U // KEY3 +#define CAN_RAM_INIT_CAN_RAM_INIT 0x10U // Initialize CAN Mailbox RAM +#define CAN_RAM_INIT_RAM_INIT_DONE 0x20U // CAN RAM initialization complete + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_EN register +// +//************************************************************************************************* +#define CAN_GLB_INT_EN_GLBINT0_EN 0x1U // Global Interrupt Enable for CANINT0 +#define CAN_GLB_INT_EN_GLBINT1_EN 0x2U // Global Interrupt Enable for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_FLG register +// +//************************************************************************************************* +#define CAN_GLB_INT_FLG_INT0_FLG 0x1U // Global Interrupt Flag for CANINT0 +#define CAN_GLB_INT_FLG_INT1_FLG 0x2U // Global Interrupt Flag for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_CLR register +// +//************************************************************************************************* +#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1U // Global Interrupt flag clear for CANINT0 +#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2U // Global Interrupt flag clear for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TXRQ_X register +// +//************************************************************************************************* +#define CAN_TXRQ_X_TXRQSTREG1_S 0U +#define CAN_TXRQ_X_TXRQSTREG1_M 0x3U // Transmit Request Register 1 +#define CAN_TXRQ_X_TXRQSTREG2_S 2U +#define CAN_TXRQ_X_TXRQSTREG2_M 0xCU // Transmit Request Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_NDAT_X register +// +//************************************************************************************************* +#define CAN_NDAT_X_NEWDATREG1_S 0U +#define CAN_NDAT_X_NEWDATREG1_M 0x3U // New Data Register 1 +#define CAN_NDAT_X_NEWDATREG2_S 2U +#define CAN_NDAT_X_NEWDATREG2_M 0xCU // New Data Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IPEN_X register +// +//************************************************************************************************* +#define CAN_IPEN_X_INTPNDREG1_S 0U +#define CAN_IPEN_X_INTPNDREG1_M 0x3U // Interrupt Pending Register 1 +#define CAN_IPEN_X_INTPNDREG2_S 2U +#define CAN_IPEN_X_INTPNDREG2_M 0xCU // Interrupt Pending Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_MVAL_X register +// +//************************************************************************************************* +#define CAN_MVAL_X_MSGVALREG1_S 0U +#define CAN_MVAL_X_MSGVALREG1_M 0x3U // Message Valid Register 1 +#define CAN_MVAL_X_MSGVALREG2_S 2U +#define CAN_MVAL_X_MSGVALREG2_M 0xCU // Message Valid Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1CMD register +// +//************************************************************************************************* +#define CAN_IF1CMD_MSG_NUM_S 0U +#define CAN_IF1CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF1CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF1CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF1CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF1CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF1CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF1CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF1CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF1CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF1CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MSK register +// +//************************************************************************************************* +#define CAN_IF1MSK_MSK_S 0U +#define CAN_IF1MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF1MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF1MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1ARB register +// +//************************************************************************************************* +#define CAN_IF1ARB_ID_S 0U +#define CAN_IF1ARB_ID_M 0x1FFFFFFFU // ` +#define CAN_IF1ARB_DIR 0x20000000U // Message Direction +#define CAN_IF1ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF1ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MCTL register +// +//************************************************************************************************* +#define CAN_IF1MCTL_DLC_S 0U +#define CAN_IF1MCTL_DLC_M 0xFU // Data length code +#define CAN_IF1MCTL_EOB 0x80U // End of Block +#define CAN_IF1MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF1MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF1MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF1MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF1MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF1MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF1MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF1MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATA register +// +//************************************************************************************************* +#define CAN_IF1DATA_DATA_0_S 0U +#define CAN_IF1DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF1DATA_DATA_1_S 8U +#define CAN_IF1DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF1DATA_DATA_2_S 16U +#define CAN_IF1DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF1DATA_DATA_3_S 24U +#define CAN_IF1DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATB register +// +//************************************************************************************************* +#define CAN_IF1DATB_DATA_4_S 0U +#define CAN_IF1DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF1DATB_DATA_5_S 8U +#define CAN_IF1DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF1DATB_DATA_6_S 16U +#define CAN_IF1DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF1DATB_DATA_7_S 24U +#define CAN_IF1DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2CMD register +// +//************************************************************************************************* +#define CAN_IF2CMD_MSG_NUM_S 0U +#define CAN_IF2CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF2CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF2CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF2CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF2CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF2CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF2CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF2CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF2CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF2CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MSK register +// +//************************************************************************************************* +#define CAN_IF2MSK_MSK_S 0U +#define CAN_IF2MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF2MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF2MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2ARB register +// +//************************************************************************************************* +#define CAN_IF2ARB_ID_S 0U +#define CAN_IF2ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF2ARB_DIR 0x20000000U // Message Direction +#define CAN_IF2ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF2ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MCTL register +// +//************************************************************************************************* +#define CAN_IF2MCTL_DLC_S 0U +#define CAN_IF2MCTL_DLC_M 0xFU // Data length code +#define CAN_IF2MCTL_EOB 0x80U // End of Block +#define CAN_IF2MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF2MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF2MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF2MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF2MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF2MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF2MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF2MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATA register +// +//************************************************************************************************* +#define CAN_IF2DATA_DATA_0_S 0U +#define CAN_IF2DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF2DATA_DATA_1_S 8U +#define CAN_IF2DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF2DATA_DATA_2_S 16U +#define CAN_IF2DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF2DATA_DATA_3_S 24U +#define CAN_IF2DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATB register +// +//************************************************************************************************* +#define CAN_IF2DATB_DATA_4_S 0U +#define CAN_IF2DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF2DATB_DATA_5_S 8U +#define CAN_IF2DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF2DATB_DATA_6_S 16U +#define CAN_IF2DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF2DATB_DATA_7_S 24U +#define CAN_IF2DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3OBS register +// +//************************************************************************************************* +#define CAN_IF3OBS_MASK 0x1U // Mask data read observation +#define CAN_IF3OBS_ARB 0x2U // Arbitration data read observation +#define CAN_IF3OBS_CTRL 0x4U // Ctrl read observation +#define CAN_IF3OBS_DATA_A 0x8U // Data A read observation +#define CAN_IF3OBS_DATA_B 0x10U // Data B read observation +#define CAN_IF3OBS_IF3SM 0x100U // IF3 Status of Mask data read access +#define CAN_IF3OBS_IF3SA 0x200U // IF3 Status of Arbitration data read access +#define CAN_IF3OBS_IF3SC 0x400U // IF3 Status of Control bits read access +#define CAN_IF3OBS_IF3SDA 0x800U // IF3 Status of Data A read access +#define CAN_IF3OBS_IF3SDB 0x1000U // IF3 Status of Data B read access +#define CAN_IF3OBS_IF3UPD 0x8000U // IF3 Update Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MSK register +// +//************************************************************************************************* +#define CAN_IF3MSK_MSK_S 0U +#define CAN_IF3MSK_MSK_M 0x1FFFFFFFU // Mask +#define CAN_IF3MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF3MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3ARB register +// +//************************************************************************************************* +#define CAN_IF3ARB_ID_S 0U +#define CAN_IF3ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF3ARB_DIR 0x20000000U // Message Direction +#define CAN_IF3ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF3ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MCTL register +// +//************************************************************************************************* +#define CAN_IF3MCTL_DLC_S 0U +#define CAN_IF3MCTL_DLC_M 0xFU // Data length code +#define CAN_IF3MCTL_EOB 0x80U // End of Block +#define CAN_IF3MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF3MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF3MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF3MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF3MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF3MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF3MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF3MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATA register +// +//************************************************************************************************* +#define CAN_IF3DATA_DATA_0_S 0U +#define CAN_IF3DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF3DATA_DATA_1_S 8U +#define CAN_IF3DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF3DATA_DATA_2_S 16U +#define CAN_IF3DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF3DATA_DATA_3_S 24U +#define CAN_IF3DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATB register +// +//************************************************************************************************* +#define CAN_IF3DATB_DATA_4_S 0U +#define CAN_IF3DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF3DATB_DATA_5_S 8U +#define CAN_IF3DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF3DATB_DATA_6_S 16U +#define CAN_IF3DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF3DATB_DATA_7_S 24U +#define CAN_IF3DATB_DATA_7_M 0xFF000000U // Data Byte 7 + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_cla.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_cla.h new file mode 100644 index 0000000..0206de7 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_cla.h @@ -0,0 +1,241 @@ +//########################################################################### +// +// FILE: hw_cla.h +// +// TITLE: Definitions for the CLA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLA_H +#define HW_CLA_H + +//************************************************************************************************* +// +// The following are defines for the CLA register offsets +// +//************************************************************************************************* +#ifndef __TMS320C28XX_CLA__ +#define CLA_O_MVECT1 0x0U // Task Interrupt Vector +#define CLA_O_MVECT2 0x1U // Task Interrupt Vector +#define CLA_O_MVECT3 0x2U // Task Interrupt Vector +#define CLA_O_MVECT4 0x3U // Task Interrupt Vector +#define CLA_O_MVECT5 0x4U // Task Interrupt Vector +#define CLA_O_MVECT6 0x5U // Task Interrupt Vector +#define CLA_O_MVECT7 0x6U // Task Interrupt Vector +#define CLA_O_MVECT8 0x7U // Task Interrupt Vector +#define CLA_O_MCTL 0x10U // Control Register +#define CLA_O_MIFR 0x20U // Interrupt Flag Register +#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register +#define CLA_O_MIFRC 0x22U // Interrupt Force Register +#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register +#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register +#define CLA_O_MIER 0x25U // Interrupt Enable Register +#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register +#define CLA_O_MPC 0x28U // CLA Program Counter +#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0 +#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1 +#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register +#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0 +#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1 +#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2 +#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3 +#endif + +#ifdef __TMS320C28XX_CLA__ +#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register +#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register +#endif + + +#ifndef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCTL register +// +//************************************************************************************************* +#define CLA_MCTL_HARDRESET 0x1U // Hard Reset +#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset +#define CLA_MCTL_IACKE 0x4U // IACK enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFR register +// +//************************************************************************************************* +#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag +#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag +#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag +#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag +#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag +#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag +#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag +#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIOVF register +// +//************************************************************************************************* +#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag +#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag +#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag +#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag +#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag +#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag +#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag +#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFRC register +// +//************************************************************************************************* +#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force +#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force +#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force +#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force +#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force +#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force +#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force +#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLR register +// +//************************************************************************************************* +#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear +#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear +#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear +#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear +#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear +#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear +#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear +#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLROVF register +// +//************************************************************************************************* +#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIER register +// +//************************************************************************************************* +#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable +#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable +#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable +#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable +#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable +#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable +#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable +#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIRUN register +// +//************************************************************************************************* +#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status +#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status +#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status +#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status +#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status +#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status +#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status +#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the _MSTF register +// +//************************************************************************************************* +#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag +#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag +#define CLA_MSTF_NF 0x4U // Negative Float Flag +#define CLA_MSTF_ZF 0x8U // Zero Float Flag +#define CLA_MSTF_TF 0x40U // Test Flag +#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode +#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status +#define CLA_MSTF_RPC_S 12U +#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC + +#endif + +#ifdef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTEN register +// +//************************************************************************************************* +#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTFRC register +// +//************************************************************************************************* +#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task. + +#endif + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_clb.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_clb.h new file mode 100644 index 0000000..4390004 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_clb.h @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: hw_clb.h +// +// TITLE: Definitions for the CLB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLB_H +#define HW_CLB_H + +//************************************************************************************************* +// +// The following are defines for the CLB register offsets +// +//************************************************************************************************* +#define CLB_O_COUNT_RESET 0x2U // Counter Block RESET +#define CLB_O_COUNT_MODE_1 0x4U // Counter Block MODE_1 +#define CLB_O_COUNT_MODE_0 0x6U // Counter Block MODE_0 +#define CLB_O_COUNT_EVENT 0x8U // Counter Block EVENT +#define CLB_O_FSM_EXTRA_IN0 0xAU // FSM Extra EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN0 0xCU // FSM EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN1 0xEU // FSM_EXT_IN1 +#define CLB_O_FSM_EXTRA_IN1 0x10U // FSM Extra_EXT_IN1 +#define CLB_O_LUT4_IN0 0x12U // LUT4_0/1/2 IN0 input source +#define CLB_O_LUT4_IN1 0x14U // LUT4_0/1/2 IN1 input source +#define CLB_O_LUT4_IN2 0x16U // LUT4_0/1/2 IN2 input source +#define CLB_O_LUT4_IN3 0x18U // LUT4_0/1/2 IN3 input source +#define CLB_O_FSM_LUT_FN1_0 0x1CU // LUT function for FSM Unit 1 and Unit 0 +#define CLB_O_FSM_LUT_FN2 0x1EU // LUT function for FSM Unit 2 +#define CLB_O_LUT4_FN1_0 0x20U // LUT function for LUT4 block of Unit 1 and 0 +#define CLB_O_LUT4_FN2 0x22U // LUT function for LUT4 block of Unit 2 +#define CLB_O_FSM_NEXT_STATE_0 0x24U // FSM Next state equations for Unit 0 +#define CLB_O_FSM_NEXT_STATE_1 0x26U // FSM Next state equations for Unit 1 +#define CLB_O_FSM_NEXT_STATE_2 0x28U // FSM Next state equations for Unit 2 +#define CLB_O_MISC_CONTROL 0x2AU // Static controls for Ctr,FSM +#define CLB_O_OUTPUT_LUT_0 0x2CU // Inp Sel, LUT fns for Out0 +#define CLB_O_OUTPUT_LUT_1 0x2EU // Inp Sel, LUT fns for Out1 +#define CLB_O_OUTPUT_LUT_2 0x30U // Inp Sel, LUT fns for Out2 +#define CLB_O_OUTPUT_LUT_3 0x32U // Inp Sel, LUT fns for Out3 +#define CLB_O_OUTPUT_LUT_4 0x34U // Inp Sel, LUT fns for Out4 +#define CLB_O_OUTPUT_LUT_5 0x36U // Inp Sel, LUT fns for Out5 +#define CLB_O_OUTPUT_LUT_6 0x38U // Inp Sel, LUT fns for Out6 +#define CLB_O_OUTPUT_LUT_7 0x3AU // Inp Sel, LUT fns for Out7 +#define CLB_O_HLC_EVENT_SEL 0x3CU // Event Selector register for the High Level controller + +#define CLB_O_LOAD_EN 0x0U // Global enable & indirect load enable control +#define CLB_O_LOAD_ADDR 0x2U // Indirect address +#define CLB_O_LOAD_DATA 0x4U // Data for indirect loads +#define CLB_O_INPUT_FILTER 0x6U // Input filter selection for both edge detection and + // synchronizers +#define CLB_O_IN_MUX_SEL_0 0x8U // Input selection to decide between Signals and GP register +#define CLB_O_LCL_MUX_SEL_1 0xAU // Input Mux selection for local mux +#define CLB_O_LCL_MUX_SEL_2 0xCU // Input Mux selection for local mux +#define CLB_O_BUF_PTR 0xEU // PUSH and PULL pointers +#define CLB_O_GP_REG 0x10U // General purpose register for CELL inputs +#define CLB_O_OUT_EN 0x12U // CELL output enable register +#define CLB_O_GLBL_MUX_SEL_1 0x14U // Global Mux select for CELL inputs +#define CLB_O_GLBL_MUX_SEL_2 0x16U // Global Mux select for CELL inputs +#define CLB_O_INTR_TAG_REG 0x20U // Interrupt Tag register +#define CLB_O_LOCK 0x22U // Lock control register +#define CLB_O_DBG_R0 0x30U // R0 of High level Controller +#define CLB_O_DBG_R1 0x32U // R1 of High level Controller +#define CLB_O_DBG_R2 0x34U // R2 of High level Controller +#define CLB_O_DBG_R3 0x36U // R3 of High level Controller +#define CLB_O_DBG_C0 0x38U // Count of Unit 0 +#define CLB_O_DBG_C1 0x3AU // Count of Unit 1 +#define CLB_O_DBG_C2 0x3CU // Count of Unit 2 +#define CLB_O_DBG_OUT 0x3EU // Outputs of various units in the Cell + +#define CLB_O_PUSH(i) (0x0U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PUSH FIFO Registers (from + // HLC) +#define CLB_O_PULL(i) (0x100U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PULL FIFO Registers (TO HLC) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_RESET register +// +//************************************************************************************************* +#define CLB_COUNT_RESET_SEL_0_S 0U +#define CLB_COUNT_RESET_SEL_0_M 0x1FU // Count Reset Select 0 +#define CLB_COUNT_RESET_SEL_1_S 5U +#define CLB_COUNT_RESET_SEL_1_M 0x3E0U // Count Reset Select 1 +#define CLB_COUNT_RESET_SEL_2_S 10U +#define CLB_COUNT_RESET_SEL_2_M 0x7C00U // Count Reset Select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_1_SEL_0_S 0U +#define CLB_COUNT_MODE_1_SEL_0_M 0x1FU // Counter mode 1 select 0 +#define CLB_COUNT_MODE_1_SEL_1_S 5U +#define CLB_COUNT_MODE_1_SEL_1_M 0x3E0U // Counter mode 1 select 1 +#define CLB_COUNT_MODE_1_SEL_2_S 10U +#define CLB_COUNT_MODE_1_SEL_2_M 0x7C00U // Counter mode 1 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_0_SEL_0_S 0U +#define CLB_COUNT_MODE_0_SEL_0_M 0x1FU // Counter mode 0 select 0 +#define CLB_COUNT_MODE_0_SEL_1_S 5U +#define CLB_COUNT_MODE_0_SEL_1_M 0x3E0U // Counter mode 0 select 1 +#define CLB_COUNT_MODE_0_SEL_2_S 10U +#define CLB_COUNT_MODE_0_SEL_2_M 0x7C00U // Counter mode 0 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_EVENT register +// +//************************************************************************************************* +#define CLB_COUNT_EVENT_SEL_0_S 0U +#define CLB_COUNT_EVENT_SEL_0_M 0x1FU // Counter event select 0 +#define CLB_COUNT_EVENT_SEL_1_S 5U +#define CLB_COUNT_EVENT_SEL_1_M 0x3E0U // Counter event select 1 +#define CLB_COUNT_EVENT_SEL_2_S 10U +#define CLB_COUNT_EVENT_SEL_2_M 0x7C00U // Counter event select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN0_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN0_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN0_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN0_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN0_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN0_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN0_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN0_SEL_0_M 0x1FU // FSM EXT_IN0 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN0_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN0_SEL_1_M 0x3E0U // FSM EXT_IN0 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN0_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN0_SEL_2_M 0x7C00U // FSM EXT_IN0 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN1_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN1_SEL_0_M 0x1FU // FSM EXT_IN1 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN1_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN1_SEL_1_M 0x3E0U // FSM EXT_IN1 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN1_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN1_SEL_2_M 0x7C00U // FSM EXT_IN1 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN1_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN1_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN1_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN1_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN1_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN1_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN0 register +// +//************************************************************************************************* +#define CLB_LUT4_IN0_SEL_0_S 0U +#define CLB_LUT4_IN0_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN0_SEL_1_S 5U +#define CLB_LUT4_IN0_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN0_SEL_2_S 10U +#define CLB_LUT4_IN0_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN1 register +// +//************************************************************************************************* +#define CLB_LUT4_IN1_SEL_0_S 0U +#define CLB_LUT4_IN1_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN1_SEL_1_S 5U +#define CLB_LUT4_IN1_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN1_SEL_2_S 10U +#define CLB_LUT4_IN1_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN2 register +// +//************************************************************************************************* +#define CLB_LUT4_IN2_SEL_0_S 0U +#define CLB_LUT4_IN2_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN2_SEL_1_S 5U +#define CLB_LUT4_IN2_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN2_SEL_2_S 10U +#define CLB_LUT4_IN2_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN3 register +// +//************************************************************************************************* +#define CLB_LUT4_IN3_SEL_0_S 0U +#define CLB_LUT4_IN3_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN3_SEL_1_S 5U +#define CLB_LUT4_IN3_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN3_SEL_2_S 10U +#define CLB_LUT4_IN3_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN1_0_FN0_S 0U +#define CLB_FSM_LUT_FN1_0_FN0_M 0xFFFFU // FSM LUT output function for unit 0 +#define CLB_FSM_LUT_FN1_0_FN1_S 16U +#define CLB_FSM_LUT_FN1_0_FN1_M 0xFFFF0000U // FSM LUT output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN2_FN1_S 0U +#define CLB_FSM_LUT_FN2_FN1_M 0xFFFFU // FSM LUT output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register +// +//************************************************************************************************* +#define CLB_LUT4_FN1_0_FN0_S 0U +#define CLB_LUT4_FN1_0_FN0_M 0xFFFFU // LUT4 output function for unit 0 +#define CLB_LUT4_FN1_0_FN1_S 16U +#define CLB_LUT4_FN1_0_FN1_M 0xFFFF0000U // LUT4 output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN2 register +// +//************************************************************************************************* +#define CLB_LUT4_FN2_FN1_S 0U +#define CLB_LUT4_FN2_FN1_M 0xFFFFU // LUT4 output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_0_S0_S 0U +#define CLB_FSM_NEXT_STATE_0_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_0_S1_S 16U +#define CLB_FSM_NEXT_STATE_0_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_1_S0_S 0U +#define CLB_FSM_NEXT_STATE_1_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_1_S1_S 16U +#define CLB_FSM_NEXT_STATE_1_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_2_S0_S 0U +#define CLB_FSM_NEXT_STATE_2_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_2_S1_S 16U +#define CLB_FSM_NEXT_STATE_2_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_MISC_CONTROL register +// +//************************************************************************************************* +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_0 0x1U // Add/Shift for counter 0 +#define CLB_MISC_CONTROL_COUNT_DIR_0 0x2U // Direction for counter 0 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_0 0x4U // Event control for counter 0 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_1 0x8U // Add/Shift for counter 1 +#define CLB_MISC_CONTROL_COUNT_DIR_1 0x10U // Direction for counter 1 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_1 0x20U // Event control for counter 1 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_2 0x40U // Add/Shift for counter 2 +#define CLB_MISC_CONTROL_COUNT_DIR_2 0x80U // Direction for counter 2 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_2 0x100U // Event control for counter 2 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_0 0x200U // Serializer enable 0 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_1 0x400U // Serializer enable 1 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_2 0x800U // Serializer enable 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_0 0x1000U // FSM extra_sel0 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_0 0x2000U // FSM extra_sel1 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_1 0x4000U // FSM extra_sel0 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_1 0x8000U // FSM extra_sel1 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_2 0x10000U // FSM extra_sel0 for 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_2 0x20000U // FSM extra_sel1 for 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_0_IN0_S 0U +#define CLB_OUTPUT_LUT_0_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_0_IN1_S 5U +#define CLB_OUTPUT_LUT_0_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_0_IN2_S 10U +#define CLB_OUTPUT_LUT_0_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_0_FN_S 15U +#define CLB_OUTPUT_LUT_0_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_1_IN0_S 0U +#define CLB_OUTPUT_LUT_1_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_1_IN1_S 5U +#define CLB_OUTPUT_LUT_1_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_1_IN2_S 10U +#define CLB_OUTPUT_LUT_1_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_1_FN_S 15U +#define CLB_OUTPUT_LUT_1_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_2_IN0_S 0U +#define CLB_OUTPUT_LUT_2_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_2_IN1_S 5U +#define CLB_OUTPUT_LUT_2_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_2_IN2_S 10U +#define CLB_OUTPUT_LUT_2_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_2_FN_S 15U +#define CLB_OUTPUT_LUT_2_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_3_IN0_S 0U +#define CLB_OUTPUT_LUT_3_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_3_IN1_S 5U +#define CLB_OUTPUT_LUT_3_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_3_IN2_S 10U +#define CLB_OUTPUT_LUT_3_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_3_FN_S 15U +#define CLB_OUTPUT_LUT_3_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_4_IN0_S 0U +#define CLB_OUTPUT_LUT_4_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_4_IN1_S 5U +#define CLB_OUTPUT_LUT_4_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_4_IN2_S 10U +#define CLB_OUTPUT_LUT_4_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_4_FN_S 15U +#define CLB_OUTPUT_LUT_4_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_5_IN0_S 0U +#define CLB_OUTPUT_LUT_5_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_5_IN1_S 5U +#define CLB_OUTPUT_LUT_5_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_5_IN2_S 10U +#define CLB_OUTPUT_LUT_5_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_5_FN_S 15U +#define CLB_OUTPUT_LUT_5_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_6_IN0_S 0U +#define CLB_OUTPUT_LUT_6_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_6_IN1_S 5U +#define CLB_OUTPUT_LUT_6_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_6_IN2_S 10U +#define CLB_OUTPUT_LUT_6_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_6_FN_S 15U +#define CLB_OUTPUT_LUT_6_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_7_IN0_S 0U +#define CLB_OUTPUT_LUT_7_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_7_IN1_S 5U +#define CLB_OUTPUT_LUT_7_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_7_IN2_S 10U +#define CLB_OUTPUT_LUT_7_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_7_FN_S 15U +#define CLB_OUTPUT_LUT_7_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register +// +//************************************************************************************************* +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_S 0U +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_M 0x1FU // Event Select 0 +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_S 5U +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_M 0x3E0U // Event Select 1 +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_S 10U +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_M 0x7C00U // Event Select 2 +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_S 15U +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_M 0xF8000U // Event Select 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_EN register +// +//************************************************************************************************* +#define CLB_LOAD_EN_LOAD_EN 0x1U // Load Enable +#define CLB_LOAD_EN_GLOBAL_EN 0x2U // Global Enable +#define CLB_LOAD_EN_STOP 0x4U // Debug stop control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_ADDR register +// +//************************************************************************************************* +#define CLB_LOAD_ADDR_ADDR_S 0U +#define CLB_LOAD_ADDR_ADDR_M 0x3FU // Indirect Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INPUT_FILTER register +// +//************************************************************************************************* +#define CLB_INPUT_FILTER_FIN0_S 0U +#define CLB_INPUT_FILTER_FIN0_M 0x3U // Input filter control 0 +#define CLB_INPUT_FILTER_FIN1_S 2U +#define CLB_INPUT_FILTER_FIN1_M 0xCU // Input filter control 1 +#define CLB_INPUT_FILTER_FIN2_S 4U +#define CLB_INPUT_FILTER_FIN2_M 0x30U // Input filter control 2 +#define CLB_INPUT_FILTER_FIN3_S 6U +#define CLB_INPUT_FILTER_FIN3_M 0xC0U // Input filter control 3 +#define CLB_INPUT_FILTER_FIN4_S 8U +#define CLB_INPUT_FILTER_FIN4_M 0x300U // Input filter control 4 +#define CLB_INPUT_FILTER_FIN5_S 10U +#define CLB_INPUT_FILTER_FIN5_M 0xC00U // Input filter control 5 +#define CLB_INPUT_FILTER_FIN6_S 12U +#define CLB_INPUT_FILTER_FIN6_M 0x3000U // Input filter control 6 +#define CLB_INPUT_FILTER_FIN7_S 14U +#define CLB_INPUT_FILTER_FIN7_M 0xC000U // Input filter control 7 +#define CLB_INPUT_FILTER_SYNC0 0x10000U // Synchronizer control 0 +#define CLB_INPUT_FILTER_SYNC1 0x20000U // Synchronizer control 1 +#define CLB_INPUT_FILTER_SYNC2 0x40000U // Synchronizer control 2 +#define CLB_INPUT_FILTER_SYNC3 0x80000U // Synchronizer control 3 +#define CLB_INPUT_FILTER_SYNC4 0x100000U // Synchronizer control 4 +#define CLB_INPUT_FILTER_SYNC5 0x200000U // Synchronizer control 5 +#define CLB_INPUT_FILTER_SYNC6 0x400000U // Synchronizer control 6 +#define CLB_INPUT_FILTER_SYNC7 0x800000U // Synchronizer control 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register +// +//************************************************************************************************* +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_0 0x1U // Select GP register 0 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_1 0x2U // Select GP register 1 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_2 0x4U // Select GP register 2 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_3 0x8U // Select GP register 3 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_4 0x10U // Select GP register 4 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_5 0x20U // Select GP register 5 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_6 0x40U // Select GP register 6 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_7 0x80U // Select GP register 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_S 0U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M 0x1FU // Local Mux select 0 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S 5U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_M 0x3E0U // Local Mux select 1 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_S 10U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_M 0x7C00U // Local Mux select 2 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_S 15U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_M 0xF8000U // Local Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_S 0U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_M 0x1FU // Local Mux select 4 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_S 5U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_M 0x3E0U // Local Mux select 5 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_S 10U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_M 0x7C00U // Local Mux select 6 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_S 15U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_M 0xF8000U // Local Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_BUF_PTR register +// +//************************************************************************************************* +#define CLB_BUF_PTR_PULL_S 0U +#define CLB_BUF_PTR_PULL_M 0xFFU // Data pointer for pull +#define CLB_BUF_PTR_PUSH_S 16U +#define CLB_BUF_PTR_PUSH_M 0xFF0000U // Data pointer for pull + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GP_REG register +// +//************************************************************************************************* +#define CLB_GP_REG_REG_S 0U +#define CLB_GP_REG_REG_M 0xFFU // General Purpose bit register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_S 0U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M 0x7FU // Global Mux select 0 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S 7U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_M 0x3F80U // Global Mux select 1 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_S 14U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_M 0x1FC000U // Global Mux select 2 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_S 21U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_M 0xFE00000U // Global Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_S 0U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_M 0x7FU // Global Mux select 4 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_S 7U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_M 0x3F80U // Global Mux select 5 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_S 14U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_M 0x1FC000U // Global Mux select 6 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_S 21U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_M 0xFE00000U // Global Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INTR_TAG_REG register +// +//************************************************************************************************* +#define CLB_INTR_TAG_REG_TAG_S 0U +#define CLB_INTR_TAG_REG_TAG_M 0x3FU // Interrupt tag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOCK register +// +//************************************************************************************************* +#define CLB_LOCK_LOCK 0x1U // LOCK enable +#define CLB_LOCK_KEY_S 16U +#define CLB_LOCK_KEY_M 0xFFFF0000U // Key for enabling write + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_DBG_OUT register +// +//************************************************************************************************* +#define CLB_DBG_OUT_COUNT0_MATCH2 0x2U // COUNT_MATCH2 UNIT 0 +#define CLB_DBG_OUT_COUNT0_ZERO 0x4U // COUNT_ZERO UNIT 0 +#define CLB_DBG_OUT_COUNT0_MATCH1 0x8U // COUNT_MATCH1 UNIT 0 +#define CLB_DBG_OUT_FSM0_S0 0x10U // FSM_S0 UNIT 0 +#define CLB_DBG_OUT_FSM0_S1 0x20U // FSM_S1 UNIT 0 +#define CLB_DBG_OUT_FSM0_LUTOUT 0x40U // FSM_LUT_OUT UNIT 0 +#define CLB_DBG_OUT_LUT40_OUT 0x80U // LUT4_OUT UNIT 0 +#define CLB_DBG_OUT_COUNT1_MATCH2 0x200U // COUNT_MATCH2 UNIT 1 +#define CLB_DBG_OUT_COUNT1_ZERO 0x400U // COUNT_ZERO UNIT 1 +#define CLB_DBG_OUT_COUNT1_MATCH1 0x800U // COUNT_MATCH1 UNIT 1 +#define CLB_DBG_OUT_FSM1_S0 0x1000U // FSM_S0 UNIT 1 +#define CLB_DBG_OUT_FSM1_S1 0x2000U // FSM_S1 UNIT 1 +#define CLB_DBG_OUT_FSM1_LUTOUT 0x4000U // FSM_LUT_OUT UNIT 1 +#define CLB_DBG_OUT_LUT41_OUT 0x8000U // LUT4_OUT UNIT 1 +#define CLB_DBG_OUT_COUNT2_MATCH2 0x20000U // COUNT_MATCH2 UNIT 2 +#define CLB_DBG_OUT_COUNT2_ZERO 0x40000U // COUNT_ZERO UNIT 2 +#define CLB_DBG_OUT_COUNT2_MATCH1 0x80000U // COUNT_MATCH1 UNIT 2 +#define CLB_DBG_OUT_FSM2_S0 0x100000U // FSM_S0 UNIT 2 +#define CLB_DBG_OUT_FSM2_S1 0x200000U // FSM_S1 UNIT 2 +#define CLB_DBG_OUT_FSM2_LUTOUT 0x400000U // FSM_LUT_OUT UNIT 2 +#define CLB_DBG_OUT_LUT42_OUT 0x800000U // LUT4_OUT UNIT 2 +#define CLB_DBG_OUT_OUT0 0x1000000U // CELL Output 0 +#define CLB_DBG_OUT_OUT1 0x2000000U // CELL Output 1 +#define CLB_DBG_OUT_OUT2 0x4000000U // CELL Output 2 +#define CLB_DBG_OUT_OUT3 0x8000000U // CELL Output 3 +#define CLB_DBG_OUT_OUT4 0x10000000U // CELL Output 4 +#define CLB_DBG_OUT_OUT5 0x20000000U // CELL Output 5 +#define CLB_DBG_OUT_OUT6 0x40000000U // CELL Output 6 +#define CLB_DBG_OUT_OUT7 0x80000000U // CELL Output 7 + + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_clbxbar.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_clbxbar.h new file mode 100644 index 0000000..64072e2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_clbxbar.h @@ -0,0 +1,1272 @@ +//########################################################################### +// +// FILE: hw_clbxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLBXBAR_H +#define HW_CLBXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_AUXSIG0MUX0TO15CFG 0x0U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG0MUX16TO31CFG 0x2U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG1MUX0TO15CFG 0x4U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG1MUX16TO31CFG 0x6U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG2MUX0TO15CFG 0x8U // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG2MUX16TO31CFG 0xAU // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG3MUX0TO15CFG 0xCU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG3MUX16TO31CFG 0xEU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG4MUX0TO15CFG 0x10U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG4MUX16TO31CFG 0x12U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG5MUX0TO15CFG 0x14U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG5MUX16TO31CFG 0x16U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG6MUX0TO15CFG 0x18U // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG6MUX16TO31CFG 0x1AU // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG7MUX0TO15CFG 0x1CU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG7MUX16TO31CFG 0x1EU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG0MUXENABLE 0x20U // CLB XBAR Mux Enable Register for Output-0 +#define XBAR_O_AUXSIG1MUXENABLE 0x22U // CLB XBAR Mux Enable Register for Output-1 +#define XBAR_O_AUXSIG2MUXENABLE 0x24U // CLB XBAR Mux Enable Register for Output-2 +#define XBAR_O_AUXSIG3MUXENABLE 0x26U // CLB XBAR Mux Enable Register for Output-3 +#define XBAR_O_AUXSIG4MUXENABLE 0x28U // CLB XBAR Mux Enable Register for Output-4 +#define XBAR_O_AUXSIG5MUXENABLE 0x2AU // CLB XBAR Mux Enable Register for Output-5 +#define XBAR_O_AUXSIG6MUXENABLE 0x2CU // CLB XBAR Mux Enable Register for Output-6 +#define XBAR_O_AUXSIG7MUXENABLE 0x2EU // CLB XBAR Mux Enable Register for Output-7 +#define XBAR_O_AUXSIGOUTINV 0x38U // CLB XBAR Output Inversion Register +#define XBAR_O_AUXSIGLOCK 0x3EU // ClbXbar Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG0 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG1 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG2 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG3 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG4 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG5 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG6 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGOUTINV register +// +//************************************************************************************************* +#define XBAR_AUXSIGOUTINV_OUT0 0x1U // Selects polarity for AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT1 0x2U // Selects polarity for AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT2 0x4U // Selects polarity for AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT3 0x8U // Selects polarity for AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT4 0x10U // Selects polarity for AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT5 0x20U // Selects polarity for AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT6 0x40U // Selects polarity for AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT7 0x80U // Selects polarity for AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGLOCK register +// +//************************************************************************************************* +#define XBAR_AUXSIGLOCK_LOCK 0x1U // Locks the configuration for CLB-XBAR +#define XBAR_AUXSIGLOCK_KEY_S 16U +#define XBAR_AUXSIGLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_cmpss.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_cmpss.h new file mode 100644 index 0000000..67d32e3 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_cmpss.h @@ -0,0 +1,235 @@ +//########################################################################### +// +// FILE: hw_cmpss.h +// +// TITLE: Definitions for the CMPSS registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CMPSS_H +#define HW_CMPSS_H + +//************************************************************************************************* +// +// The following are defines for the CMPSS register offsets +// +//************************************************************************************************* +#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register +#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register +#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register +#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register +#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register +#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register +#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register +#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register +#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register +#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register +#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register +#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register +#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register +#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register +#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register +#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register +#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register +#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register +#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register +#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register +#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPCTL register +// +//************************************************************************************************* +#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select +#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPHSEL_S 2U +#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U +#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select +#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPLSEL_S 10U +#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U +#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPHYSCTL register +// +//************************************************************************************************* +#define CMPSS_COMPHYSCTL_COMPHYS_S 0U +#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTS register +// +//************************************************************************************************* +#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status +#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status +#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status +#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTSCLR register +// +//************************************************************************************************* +#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable +#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPDACCTL register +// +//************************************************************************************************* +#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control +#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U +#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control +#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select +#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select +#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select +#define CMPSS_COMPDACCTL_FREESOFT_S 14U +#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALS register +// +//************************************************************************************************* +#define CMPSS_DACHVALS_DACVAL_S 0U +#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALA register +// +//************************************************************************************************* +#define CMPSS_DACHVALA_DACVAL_S 0U +#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALS register +// +//************************************************************************************************* +#define CMPSS_DACLVALS_DACVAL_S 0U +#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALA register +// +//************************************************************************************************* +#define CMPSS_DACLVALA_DACVAL_S 0U +#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYA register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYA_DELAY_S 0U +#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYS register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYS_DELAY_S 0U +#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPLFILCTL_THRESH_S 9U +#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPHFILCTL_THRESH_S 9U +#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPLOCK register +// +//************************************************************************************************* +#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock +#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock +#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock +#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_cputimer.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_cputimer.h new file mode 100644 index 0000000..f7613fb --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_cputimer.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: hw_cputimer.h +// +// TITLE: Definitions for the CPUTIMER registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CPUTIMER_H +#define HW_CPUTIMER_H + +//************************************************************************************************* +// +// The following are defines for the CPUTIMER register offsets +// +//************************************************************************************************* +#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register +#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register +#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register +#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register +#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TIM register +// +//************************************************************************************************* +#define CPUTIMER_TIM_LSW_S 0U +#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers +#define CPUTIMER_TIM_MSW_S 16U +#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRD register +// +//************************************************************************************************* +#define CPUTIMER_PRD_LSW_S 0U +#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers +#define CPUTIMER_PRD_MSW_S 16U +#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TCR register +// +//************************************************************************************************* +#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit. +#define CPUTIMER_TCR_TRB 0x20U // Timer reload +#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes +#define CPUTIMER_TCR_FREE 0x800U // Emulation modes +#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable. +#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPR register +// +//************************************************************************************************* +#define CPUTIMER_TPR_TDDR_S 0U +#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPR_PSC_S 8U +#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPRH register +// +//************************************************************************************************* +#define CPUTIMER_TPRH_TDDRH_S 0U +#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPRH_PSCH_S 8U +#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter. + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_dac.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_dac.h new file mode 100644 index 0000000..3e3d3a2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_dac.h @@ -0,0 +1,122 @@ +//########################################################################### +// +// FILE: hw_dac.h +// +// TITLE: Definitions for the DAC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DAC_H +#define HW_DAC_H + +//************************************************************************************************* +// +// The following are defines for the DAC register offsets +// +//************************************************************************************************* +#define DAC_O_REV 0x0U // DAC Revision Register +#define DAC_O_CTL 0x1U // DAC Control Register +#define DAC_O_VALA 0x2U // DAC Value Register - Active +#define DAC_O_VALS 0x3U // DAC Value Register - Shadow +#define DAC_O_OUTEN 0x4U // DAC Output Enable Register +#define DAC_O_LOCK 0x5U // DAC Lock Register +#define DAC_O_TRIM 0x6U // DAC Trim Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACREV register +// +//************************************************************************************************* +#define DAC_REV_REV_S 0U +#define DAC_REV_REV_M 0xFFU // DAC Revision Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACCTL register +// +//************************************************************************************************* +#define DAC_CTL_DACREFSEL 0x1U // DAC Reference Select +#define DAC_CTL_LOADMODE 0x4U // DACVALA Load Mode +#define DAC_CTL_SYNCSEL_S 4U +#define DAC_CTL_SYNCSEL_M 0xF0U // DAC EPWMSYNCPER Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALA register +// +//************************************************************************************************* +#define DAC_VALA_DACVALA_S 0U +#define DAC_VALA_DACVALA_M 0xFFFU // DAC Active Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALS register +// +//************************************************************************************************* +#define DAC_VALS_DACVALS_S 0U +#define DAC_VALS_DACVALS_M 0xFFFU // DAC Shadow Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACOUTEN register +// +//************************************************************************************************* +#define DAC_OUTEN_DACOUTEN 0x1U // DAC Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLOCK register +// +//************************************************************************************************* +#define DAC_LOCK_DACCTL 0x1U // DAC Control Register Lock +#define DAC_LOCK_DACVAL 0x2U // DAC Value Register Lock +#define DAC_LOCK_DACOUTEN 0x4U // DAC Output Enable Register Lock +#define DAC_LOCK_KEY_S 12U +#define DAC_LOCK_KEY_M 0xF000U // DAC Register Lock Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACTRIM register +// +//************************************************************************************************* +#define DAC_TRIM_OFFSET_TRIM_S 0U +#define DAC_TRIM_OFFSET_TRIM_M 0xFFU // DAC Offset Trim + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_dcsm.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_dcsm.h new file mode 100644 index 0000000..c81bcb1 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_dcsm.h @@ -0,0 +1,442 @@ +//########################################################################### +// +// FILE: hw_dcsm.h +// +// TITLE: Definitions for the DCSM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DCSM_H +#define HW_DCSM_H + +//************************************************************************************************* +// +// The following are defines for the DCSM register offsets +// +//************************************************************************************************* +#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP +#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP +#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP +#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP + +#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP +#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP +#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP +#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP + +#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer +#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock +#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0 +#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1 +#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2 +#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3 +#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register +#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register +#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register +#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register +#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register + +#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer +#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock +#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0 +#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1 +#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2 +#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3 +#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register +#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register +#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register +#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register +#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register + +#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register +#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register +#define DCSM_O_RAMSTAT 0x4U // RAM Status Register + + + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock. +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z1_BOOTCTRL_KEY_S 0U +#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z1_BOOTCTRL_BMODE_S 8U +#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_CR register +// +//************************************************************************************************* +#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock. +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z2_BOOTCTRL_KEY_S 0U +#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z2_BOOTCTRL_BMODE_S 8U +#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_CR register +// +//************************************************************************************************* +#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FLSEM register +// +//************************************************************************************************* +#define DCSM_FLSEM_SEM_S 0U +#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit +#define DCSM_FLSEM_KEY_S 8U +#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECTSTAT register +// +//************************************************************************************************* +#define DCSM_SECTSTAT_STATUS_SECTA_S 0U +#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A +#define DCSM_SECTSTAT_STATUS_SECTB_S 2U +#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B +#define DCSM_SECTSTAT_STATUS_SECTC_S 4U +#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C +#define DCSM_SECTSTAT_STATUS_SECTD_S 6U +#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D +#define DCSM_SECTSTAT_STATUS_SECTE_S 8U +#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E +#define DCSM_SECTSTAT_STATUS_SECTF_S 10U +#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F +#define DCSM_SECTSTAT_STATUS_SECTG_S 12U +#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G +#define DCSM_SECTSTAT_STATUS_SECTH_S 14U +#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H +#define DCSM_SECTSTAT_STATUS_SECTI_S 16U +#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I +#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U +#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J +#define DCSM_SECTSTAT_STATUS_SECTK_S 20U +#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K +#define DCSM_SECTSTAT_STATUS_SECTL_S 22U +#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L +#define DCSM_SECTSTAT_STATUS_SECTM_S 24U +#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M +#define DCSM_SECTSTAT_STATUS_SECTN_S 26U +#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMSTAT register +// +//************************************************************************************************* +#define DCSM_RAMSTAT_STATUS_RAM0_S 0U +#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0 +#define DCSM_RAMSTAT_STATUS_RAM1_S 2U +#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1 +#define DCSM_RAMSTAT_STATUS_RAM2_S 4U +#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2 +#define DCSM_RAMSTAT_STATUS_RAM3_S 6U +#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3 +#define DCSM_RAMSTAT_STATUS_RAM4_S 8U +#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4 +#define DCSM_RAMSTAT_STATUS_RAM5_S 10U +#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5 +#define DCSM_RAMSTAT_STATUS_RAM6_S 12U +#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0 +#define DCSM_RAMSTAT_STATUS_RAM7_S 14U +#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1 +#define DCSM_RAMSTAT_STATUS_CLA1_S 28U +#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1 + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_dma.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_dma.h new file mode 100644 index 0000000..1ecd1d7 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_dma.h @@ -0,0 +1,165 @@ +//########################################################################### +// +// FILE: hw_dma.h +// +// TITLE: Definitions for the DMA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DMA_H +#define HW_DMA_H + +//************************************************************************************************* +// +// The following are defines for the DMA register offsets +// +//************************************************************************************************* +#define DMA_O_CTRL 0x0U // DMA Control Register +#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register +#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register +#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register + +#define DMA_O_MODE 0x0U // Mode Register +#define DMA_O_CONTROL 0x1U // Control Register +#define DMA_O_BURST_SIZE 0x2U // Burst Size Register +#define DMA_O_BURST_COUNT 0x3U // Burst Count Register +#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register +#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register +#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register +#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register +#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register +#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register +#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register +#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register +#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register +#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register +#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register +#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register +#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register +#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register +#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register +#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register +#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register +#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register +#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register +#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACTRL register +// +//************************************************************************************************* +#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit +#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEBUGCTRL register +// +//************************************************************************************************* +#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYCTRL1 register +// +//************************************************************************************************* +#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYSTAT register +// +//************************************************************************************************* +#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U +#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MODE register +// +//************************************************************************************************* +#define DMA_MODE_PERINTSEL_S 0U +#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select +#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable +#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable +#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode +#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit +#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit +#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit +#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CONTROL register +// +//************************************************************************************************* +#define DMA_CONTROL_RUN 0x1U // Run Bit +#define DMA_CONTROL_HALT 0x2U // Halt Bit +#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit +#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit +#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit +#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit +#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit +#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit +#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit +#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit +#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_SIZE register +// +//************************************************************************************************* +#define DMA_BURST_SIZE_BURSTSIZE_S 0U +#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_COUNT register +// +//************************************************************************************************* +#define DMA_BURST_COUNT_BURSTCOUNT_S 0U +#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_ecap.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_ecap.h new file mode 100644 index 0000000..48981d6 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_ecap.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_ecap.h +// +// TITLE: Definitions for the ECAP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ECAP_H +#define HW_ECAP_H + +//************************************************************************************************* +// +// The following are defines for the ECAP register offsets +// +//************************************************************************************************* +#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter +#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register +#define ECAP_O_CAP1 0x4U // Capture 1 Register +#define ECAP_O_CAP2 0x6U // Capture 2 Register +#define ECAP_O_CAP3 0x8U // Capture 3 Register +#define ECAP_O_CAP4 0xAU // Capture 4 Register +#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1 +#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2 +#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register +#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register +#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register +#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL1 register +// +//************************************************************************************************* +#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select +#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1 +#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select +#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2 +#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select +#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3 +#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select +#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4 +#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event +#define ECAP_ECCTL1_PRESCALE_S 9U +#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select +#define ECAP_ECCTL1_FREE_SOFT_S 14U +#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL2 register +// +//************************************************************************************************* +#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot +#define ECAP_ECCTL2_STOP_WRAP_S 1U +#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous +#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm +#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop +#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select +#define ECAP_ECCTL2_SYNCO_SEL_S 6U +#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode +#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync +#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select +#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECEINT register +// +//************************************************************************************************* +#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable +#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable +#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable +#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable +#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFLG register +// +//************************************************************************************************* +#define ECAP_ECFLG_INT 0x1U // Global Flag +#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag +#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag +#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag +#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag +#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag +#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag +#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCLR register +// +//************************************************************************************************* +#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear +#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear +#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear +#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear +#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear +#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear +#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear +#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFRC register +// +//************************************************************************************************* +#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt +#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt +#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt +#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt +#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt +#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt +#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_emif.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_emif.h new file mode 100644 index 0000000..9f1401e --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_emif.h @@ -0,0 +1,259 @@ +//########################################################################### +// +// FILE: hw_emif.h +// +// TITLE: Definitions for the EMIF registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EMIF_H +#define HW_EMIF_H + +//************************************************************************************************* +// +// The following are defines for the EMIF register offsets +// +//************************************************************************************************* +#define EMIF_O_RCSR 0x0U // Revision Code and Status Register +#define EMIF_O_ASYNC_WCCR 0x2U // Async Wait Cycle Config Register +#define EMIF_O_SDRAM_CR 0x4U // SDRAM (EMxCS0n) Config Register +#define EMIF_O_SDRAM_RCR 0x6U // SDRAM Refresh Control Register +#define EMIF_O_ASYNC_CS2_CR 0x8U // Async 1 (EMxCS2n) Config Register +#define EMIF_O_ASYNC_CS3_CR 0xAU // Async 2 (EMxCS3n) Config Register +#define EMIF_O_ASYNC_CS4_CR 0xCU // Async 3 (EMxCS4n) Config Register +#define EMIF_O_SDRAM_TR 0x10U // SDRAM Timing Register +#define EMIF_O_TOTAL_SDRAM_AR 0x18U // Total SDRAM Accesses Register +#define EMIF_O_TOTAL_SDRAM_ACTR 0x1AU // Total SDRAM Activate Register +#define EMIF_O_SDR_EXT_TMNG 0x1EU // SDRAM SR/PD Exit Timing Register +#define EMIF_O_INT_RAW 0x20U // Interrupt Raw Register +#define EMIF_O_INT_MSK 0x22U // Interrupt Masked Register +#define EMIF_O_INT_MSK_SET 0x24U // Interrupt Mask Set Register +#define EMIF_O_INT_MSK_CLR 0x26U // Interrupt Mask Clear Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCSR register +// +//************************************************************************************************* +#define EMIF_RCSR_MINOR_REVISION_S 0U +#define EMIF_RCSR_MINOR_REVISION_M 0xFFU // Minor Revision. +#define EMIF_RCSR_MAJOR_REVISION_S 8U +#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00U // Major Revision. +#define EMIF_RCSR_MODULE_ID_S 16U +#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000U // EMIF module ID. +#define EMIF_RCSR_FR 0x40000000U // EMIF is running in full rate or half rate. +#define EMIF_RCSR_BE 0x80000000U // EMIF endian mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_WCCR register +// +//************************************************************************************************* +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0U +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFFU // Maximum Extended Wait cycles. +#define EMIF_ASYNC_WCCR_WP0 0x10000000U // Polarity for EMxWAIT. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_CR register +// +//************************************************************************************************* +#define EMIF_SDRAM_CR_PAGESIGE_S 0U +#define EMIF_SDRAM_CR_PAGESIGE_M 0x7U // Page Size. +#define EMIF_SDRAM_CR_IBANK_S 4U +#define EMIF_SDRAM_CR_IBANK_M 0x70U // Internal Bank setup of SDRAM devices. +#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100U // Bits 11 to 9 are writable only if this bit + // is set. +#define EMIF_SDRAM_CR_CL_S 9U +#define EMIF_SDRAM_CR_CL_M 0xE00U // CAS Latency. +#define EMIF_SDRAM_CR_NM 0x4000U // Narrow Mode. +#define EMIF_SDRAM_CR_PDWR 0x20000000U // Perform refreshes during Power Down. +#define EMIF_SDRAM_CR_PD 0x40000000U // Power Down. +#define EMIF_SDRAM_CR_SR 0x80000000U // Self Refresh. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_RCR register +// +//************************************************************************************************* +#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0U +#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFFU // Refresh Rate. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS2_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS2_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS2_CR_TA_S 2U +#define EMIF_ASYNC_CS2_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS2_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS3_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS3_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS3_CR_TA_S 2U +#define EMIF_ASYNC_CS3_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS3_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS4_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS4_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS4_CR_TA_S 2U +#define EMIF_ASYNC_CS4_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS4_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_TR register +// +//************************************************************************************************* +#define EMIF_SDRAM_TR_T_RRD_S 4U +#define EMIF_SDRAM_TR_T_RRD_M 0x70U // Activate to Activate timing for different bank. +#define EMIF_SDRAM_TR_T_RC_S 8U +#define EMIF_SDRAM_TR_T_RC_M 0xF00U // Activate to Activate timing . +#define EMIF_SDRAM_TR_T_RAS_S 12U +#define EMIF_SDRAM_TR_T_RAS_M 0xF000U // Activate to Precharge timing. +#define EMIF_SDRAM_TR_T_WR_S 16U +#define EMIF_SDRAM_TR_T_WR_M 0x70000U // Last Write to Precharge timing. +#define EMIF_SDRAM_TR_T_RCD_S 20U +#define EMIF_SDRAM_TR_T_RCD_M 0x700000U // Activate to Read/Write timing. +#define EMIF_SDRAM_TR_T_RP_S 24U +#define EMIF_SDRAM_TR_T_RP_M 0x7000000U // Precharge to Activate/Refresh timing. +#define EMIF_SDRAM_TR_T_RFC_S 27U +#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000U // Refresh/Load Mode to Refresh/Activate timing + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDR_EXT_TMNG register +// +//************************************************************************************************* +#define EMIF_SDR_EXT_TMNG_T_XS_S 0U +#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1FU // Self Refresh exit to new command timing. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_RAW register +// +//************************************************************************************************* +#define EMIF_INT_RAW_AT 0x1U // Asynchronous Timeout. +#define EMIF_INT_RAW_LT 0x2U // Line Trap. +#define EMIF_INT_RAW_WR_S 2U +#define EMIF_INT_RAW_WR_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK register +// +//************************************************************************************************* +#define EMIF_INT_MSK_AT_MASKED 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_LT_MASKED 0x2U // Line Trap. +#define EMIF_INT_MSK_WR_MASKED_S 2U +#define EMIF_INT_MSK_WR_MASKED_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_SET register +// +//************************************************************************************************* +#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2U // Line Trap. +#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2U +#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_CLR register +// +//************************************************************************************************* +#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2U // Line Trap. +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2U +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3CU // Wait Rise. + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_epwm.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_epwm.h new file mode 100644 index 0000000..6f7bf2d --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_epwm.h @@ -0,0 +1,1050 @@ +//########################################################################### +// +// FILE: hw_epwm.h +// +// TITLE: Definitions for the EPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWM_H +#define HW_EPWM_H + +//************************************************************************************************* +// +// The following are defines for the EPWM register offsets +// +//************************************************************************************************* +#define EPWM_O_TBCTL 0x0U // Time Base Control Register +#define EPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define EPWM_O_TBCTR 0x4U // Time Base Counter Register +#define EPWM_O_TBSTS 0x5U // Time Base Status Register +#define EPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define EPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define EPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define EPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define EPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define EPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define EPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define EPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define EPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define EPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define EPWM_O_HRPWR 0x21U // HRPWM Power Register +#define EPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define EPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define EPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define EPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define EPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define EPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define EPWM_O_XLINK 0x38U // EPWMx Link Register +#define EPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define EPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define EPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define EPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define EPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define EPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define EPWM_O_TBPHS 0x60U // Time Base Phase High +#define EPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define EPWM_O_TBPRD 0x63U // Time Base Period Register +#define EPWM_O_CMPA 0x6AU // Counter Compare A Register +#define EPWM_O_CMPB 0x6CU // Compare B Register +#define EPWM_O_CMPC 0x6FU // Counter Compare C Register +#define EPWM_O_CMPD 0x71U // Counter Compare D Register +#define EPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define EPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define EPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define EPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define EPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define EPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define EPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define EPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define EPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define EPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define EPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define EPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define EPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define EPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define EPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define EPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define EPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define EPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define EPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define EPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define EPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define EPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define EPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define EPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define EPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define EPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define EPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define EPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define EPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define EPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define EPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define EPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define EPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define EPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define EPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define EPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define EPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define EPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define EPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define EPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define EPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define EPWM_TBCTL_CTRMODE_S 0U +#define EPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define EPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define EPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define EPWM_TBCTL_SYNCOSEL_S 4U +#define EPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define EPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define EPWM_TBCTL_HSPCLKDIV_S 7U +#define EPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define EPWM_TBCTL_CLKDIV_S 10U +#define EPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define EPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define EPWM_TBCTL_FREE_SOFT_S 14U +#define EPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define EPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define EPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define EPWM_TBCTL2_SYNCOSELX_S 12U +#define EPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define EPWM_TBCTL2_PRDLDSYNC_S 14U +#define EPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define EPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define EPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define EPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define EPWM_CMPCTL_LOADAMODE_S 0U +#define EPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define EPWM_CMPCTL_LOADBMODE_S 2U +#define EPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define EPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define EPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define EPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define EPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define EPWM_CMPCTL_LOADASYNC_S 10U +#define EPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define EPWM_CMPCTL_LOADBSYNC_S 12U +#define EPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define EPWM_CMPCTL2_LOADCMODE_S 0U +#define EPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define EPWM_CMPCTL2_LOADDMODE_S 2U +#define EPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define EPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define EPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define EPWM_CMPCTL2_LOADCSYNC_S 10U +#define EPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define EPWM_CMPCTL2_LOADDSYNC_S 12U +#define EPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define EPWM_DBCTL_OUT_MODE_S 0U +#define EPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define EPWM_DBCTL_POLSEL_S 2U +#define EPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define EPWM_DBCTL_IN_MODE_S 4U +#define EPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define EPWM_DBCTL_LOADREDMODE_S 6U +#define EPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define EPWM_DBCTL_LOADFEDMODE_S 8U +#define EPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define EPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define EPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define EPWM_DBCTL_OUTSWAP_S 12U +#define EPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define EPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define EPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define EPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define EPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define EPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define EPWM_AQCTL_LDAQAMODE_S 0U +#define EPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define EPWM_AQCTL_LDAQBMODE_S 2U +#define EPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define EPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define EPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define EPWM_AQCTL_LDAQASYNC_S 8U +#define EPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define EPWM_AQCTL_LDAQBSYNC_S 10U +#define EPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define EPWM_AQTSRCSEL_T1SEL_S 0U +#define EPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define EPWM_AQTSRCSEL_T2SEL_S 4U +#define EPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define EPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define EPWM_PCCTL_OSHTWTH_S 1U +#define EPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define EPWM_PCCTL_CHPFREQ_S 5U +#define EPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define EPWM_PCCTL_CHPDUTY_S 8U +#define EPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define EPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define EPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define EPWM_VCAPCTL_TRIGSEL_S 2U +#define EPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define EPWM_VCAPCTL_VDELAYDIV_S 7U +#define EPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define EPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define EPWM_VCNTCFG_STARTEDGE_S 0U +#define EPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define EPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define EPWM_VCNTCFG_STOPEDGE_S 8U +#define EPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define EPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define EPWM_HRCNFG_EDGMODE_S 0U +#define EPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define EPWM_HRCNFG_HRLOAD_S 3U +#define EPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define EPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define EPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define EPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define EPWM_HRCNFG_EDGMODEB_S 8U +#define EPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define EPWM_HRCNFG_HRLOADB_S 11U +#define EPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define EPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define EPWM_HRMSTEP_HRMSTEP_S 0U +#define EPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define EPWM_HRCNFG2_EDGMODEDB_S 0U +#define EPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define EPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define EPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define EPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define EPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define EPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define EPWM_HRPCTL_PWMSYNCSELX_S 4U +#define EPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define EPWM_TRREM_TRREM_S 0U +#define EPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define EPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define EPWM_GLDCTL_GLDMODE_S 1U +#define EPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define EPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define EPWM_GLDCTL_GLDPRD_S 7U +#define EPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define EPWM_GLDCTL_GLDCNT_S 10U +#define EPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define EPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define EPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define EPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define EPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define EPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define EPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define EPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define EPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define EPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define EPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define EPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define EPWM_XLINK_TBPRDLINK_S 0U +#define EPWM_XLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define EPWM_XLINK_CMPALINK_S 4U +#define EPWM_XLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define EPWM_XLINK_CMPBLINK_S 8U +#define EPWM_XLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define EPWM_XLINK_CMPCLINK_S 12U +#define EPWM_XLINK_CMPCLINK_M 0xF000U // CMPC Link +#define EPWM_XLINK_CMPDLINK_S 16U +#define EPWM_XLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define EPWM_XLINK_GLDCTL2LINK_S 28U +#define EPWM_XLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define EPWM_AQCTLA_ZRO_S 0U +#define EPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLA_PRD_S 2U +#define EPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLA_CAU_S 4U +#define EPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLA_CAD_S 6U +#define EPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLA_CBU_S 8U +#define EPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLA_CBD_S 10U +#define EPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define EPWM_AQCTLA2_T1U_S 0U +#define EPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLA2_T1D_S 2U +#define EPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLA2_T2U_S 4U +#define EPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLA2_T2D_S 6U +#define EPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define EPWM_AQCTLB_ZRO_S 0U +#define EPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLB_PRD_S 2U +#define EPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLB_CAU_S 4U +#define EPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLB_CAD_S 6U +#define EPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLB_CBU_S 8U +#define EPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLB_CBD_S 10U +#define EPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define EPWM_AQCTLB2_T1U_S 0U +#define EPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLB2_T1D_S 2U +#define EPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLB2_T2U_S 4U +#define EPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLB2_T2D_S 6U +#define EPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define EPWM_AQSFRC_ACTSFA_S 0U +#define EPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define EPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define EPWM_AQSFRC_ACTSFB_S 3U +#define EPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define EPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define EPWM_AQSFRC_RLDCSF_S 6U +#define EPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define EPWM_AQCSFRC_CSFA_S 0U +#define EPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define EPWM_AQCSFRC_CSFB_S 2U +#define EPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define EPWM_DBREDHR_DBREDHR_S 9U +#define EPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define EPWM_DBRED_DBRED_S 0U +#define EPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define EPWM_DBFEDHR_DBFEDHR_S 9U +#define EPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define EPWM_DBFED_DBFED_S 0U +#define EPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define EPWM_TBPHS_TBPHSHR_S 0U +#define EPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define EPWM_TBPHS_TBPHS_S 16U +#define EPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define EPWM_CMPA_CMPAHR_S 0U +#define EPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define EPWM_CMPA_CMPA_S 16U +#define EPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define EPWM_CMPB_CMPBHR_S 0U +#define EPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define EPWM_CMPB_CMPB_S 16U +#define EPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define EPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define EPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define EPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define EPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define EPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define EPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define EPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define EPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define EPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define EPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define EPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define EPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define EPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define EPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define EPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define EPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define EPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define EPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define EPWM_TZDCSEL_DCAEVT1_S 0U +#define EPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define EPWM_TZDCSEL_DCAEVT2_S 3U +#define EPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define EPWM_TZDCSEL_DCBEVT1_S 6U +#define EPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define EPWM_TZDCSEL_DCBEVT2_S 9U +#define EPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define EPWM_TZCTL_TZA_S 0U +#define EPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define EPWM_TZCTL_TZB_S 2U +#define EPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define EPWM_TZCTL_DCAEVT1_S 4U +#define EPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define EPWM_TZCTL_DCAEVT2_S 6U +#define EPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define EPWM_TZCTL_DCBEVT1_S 8U +#define EPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define EPWM_TZCTL_DCBEVT2_S 10U +#define EPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define EPWM_TZCTL2_TZAU_S 0U +#define EPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define EPWM_TZCTL2_TZAD_S 3U +#define EPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define EPWM_TZCTL2_TZBU_S 6U +#define EPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define EPWM_TZCTL2_TZBD_S 9U +#define EPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define EPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define EPWM_TZCTLDCA_DCAEVT1U_S 0U +#define EPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT1D_S 3U +#define EPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCA_DCAEVT2U_S 6U +#define EPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT2D_S 9U +#define EPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define EPWM_TZCTLDCB_DCBEVT1U_S 0U +#define EPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT1D_S 3U +#define EPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCB_DCBEVT2U_S 6U +#define EPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT2D_S 9U +#define EPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define EPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define EPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define EPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define EPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define EPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define EPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define EPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define EPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define EPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define EPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define EPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define EPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define EPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define EPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define EPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define EPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define EPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define EPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define EPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define EPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event 2 +#define EPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define EPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define EPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define EPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define EPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define EPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define EPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define EPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event 1 +#define EPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define EPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define EPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define EPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define EPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define EPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define EPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define EPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define EPWM_TZCLR_CBCPULSE_S 14U +#define EPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define EPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define EPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define EPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define EPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define EPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define EPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define EPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define EPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define EPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define EPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define EPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define EPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define EPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define EPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define EPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define EPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define EPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define EPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define EPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define EPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define EPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define EPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define EPWM_ETSEL_INTSEL_S 0U +#define EPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define EPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define EPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define EPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define EPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define EPWM_ETSEL_SOCASEL_S 8U +#define EPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define EPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define EPWM_ETSEL_SOCBSEL_S 12U +#define EPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define EPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define EPWM_ETPS_INTPRD_S 0U +#define EPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define EPWM_ETPS_INTCNT_S 2U +#define EPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define EPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define EPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define EPWM_ETPS_SOCAPRD_S 8U +#define EPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define EPWM_ETPS_SOCACNT_S 10U +#define EPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define EPWM_ETPS_SOCBPRD_S 12U +#define EPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define EPWM_ETPS_SOCBCNT_S 14U +#define EPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define EPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define EPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define EPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define EPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define EPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define EPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define EPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define EPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define EPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define EPWM_ETINTPS_INTPRD2_S 0U +#define EPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define EPWM_ETINTPS_INTCNT2_S 4U +#define EPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define EPWM_ETSOCPS_SOCAPRD2_S 0U +#define EPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define EPWM_ETSOCPS_SOCACNT2_S 4U +#define EPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define EPWM_ETSOCPS_SOCBPRD2_S 8U +#define EPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define EPWM_ETSOCPS_SOCBCNT2_S 12U +#define EPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define EPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define EPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define EPWM_ETCNTINIT_INTINIT_S 0U +#define EPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCAINIT_S 4U +#define EPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCBINIT_S 8U +#define EPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define EPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define EPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define EPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define EPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define EPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define EPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define EPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define EPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define EPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define EPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define EPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define EPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define EPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define EPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define EPWM_DCFCTL_SRCSEL_S 0U +#define EPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define EPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define EPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define EPWM_DCFCTL_PULSESEL_S 4U +#define EPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define EPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define EPWM_DCFCTL_EDGEMODE_S 8U +#define EPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define EPWM_DCFCTL_EDGECOUNT_S 10U +#define EPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define EPWM_DCFCTL_EDGESTATUS_S 13U +#define EPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define EPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define EPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define EPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define EPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define EPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_epwmxbar.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_epwmxbar.h new file mode 100644 index 0000000..5fb6058 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_epwmxbar.h @@ -0,0 +1,1192 @@ +//########################################################################### +// +// FILE: hw_epwmxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWMXBAR_H +#define HW_EPWMXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_TRIP4MUX0TO15CFG 0x0U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP4MUX16TO31CFG 0x2U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP5MUX0TO15CFG 0x4U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP5MUX16TO31CFG 0x6U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP7MUX0TO15CFG 0x8U // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP7MUX16TO31CFG 0xAU // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP8MUX0TO15CFG 0xCU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP8MUX16TO31CFG 0xEU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP9MUX0TO15CFG 0x10U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP9MUX16TO31CFG 0x12U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP10MUX0TO15CFG 0x14U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP10MUX16TO31CFG 0x16U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP11MUX0TO15CFG 0x18U // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP11MUX16TO31CFG 0x1AU // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP12MUX0TO15CFG 0x1CU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP12MUX16TO31CFG 0x1EU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP4MUXENABLE 0x20U // ePWM XBAR Mux Enable for TRIP4 +#define XBAR_O_TRIP5MUXENABLE 0x22U // ePWM XBAR Mux Enable for TRIP5 +#define XBAR_O_TRIP7MUXENABLE 0x24U // ePWM XBAR Mux Enable for TRIP7 +#define XBAR_O_TRIP8MUXENABLE 0x26U // ePWM XBAR Mux Enable for TRIP8 +#define XBAR_O_TRIP9MUXENABLE 0x28U // ePWM XBAR Mux Enable for TRIP9 +#define XBAR_O_TRIP10MUXENABLE 0x2AU // ePWM XBAR Mux Enable for TRIP10 +#define XBAR_O_TRIP11MUXENABLE 0x2CU // ePWM XBAR Mux Enable for TRIP11 +#define XBAR_O_TRIP12MUXENABLE 0x2EU // ePWM XBAR Mux Enable for TRIP12 +#define XBAR_O_TRIPOUTINV 0x38U // ePWM XBAR Output Inversion Register +#define XBAR_O_TRIPLOCK 0x3EU // ePWM XBAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP4 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP5 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP7 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP8 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP9MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP9MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP9MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP9MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP9MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP9MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP9MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP9MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP9MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP9MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP9MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP9MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP9MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP9MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP9MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP9MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP9MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP9MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP9MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP9MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP9MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP9MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP9MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP9MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP9MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP9MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP9MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP9MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP9MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP9MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP9MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP9MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP9 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP10MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP10MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP10MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP10MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP10MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP10MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP10MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP10MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP10MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP10MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP10MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP10MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP10MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP10MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP10MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP10MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP10MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP10MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP10MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP10MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP10MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP10MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP10MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP10MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP10MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP10MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP10MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP10MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP10MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP10MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP10MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP10MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP11MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP11MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP11MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP11MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP11MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP11MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP11MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP11MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP11MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP11MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP11MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP11MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP11MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP11MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP11MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP11MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP11MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP11MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP11MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP11MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP11MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP11MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP11MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP11MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP11MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP11MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP11MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP11MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP11MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP11MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP11MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP11MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP12MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP12MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP12MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP12MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP12MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP12MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP12MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP12MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP12MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP12MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP12MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP12MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP12MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP12MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP12MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP12MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP12MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP12MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP12MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP12MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP12MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP12MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP12MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP12MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP12MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP12MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP12MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP12MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP12MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP12MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP12MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP12MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP4MUXENABLE_MUX0 0x1U // mux0 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP5MUXENABLE_MUX0 0x1U // mux0 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP7MUXENABLE_MUX0 0x1U // mux0 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP8MUXENABLE_MUX0 0x1U // mux0 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP9MUXENABLE_MUX0 0x1U // mux0 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP10MUXENABLE_MUX0 0x1U // mux0 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP10 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP11MUXENABLE_MUX0 0x1U // mux0 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP11 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP12MUXENABLE_MUX0 0x1U // mux0 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPOUTINV register +// +//************************************************************************************************* +#define XBAR_TRIPOUTINV_TRIP4 0x1U // Selects polarity for TRIP4 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP5 0x2U // Selects polarity for TRIP5 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP7 0x4U // Selects polarity for TRIP7 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP8 0x8U // Selects polarity for TRIP8 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP9 0x10U // Selects polarity for TRIP9 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP10 0x20U // Selects polarity for TRIP10 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP11 0x40U // Selects polarity for TRIP11 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP12 0x80U // Selects polarity for TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPLOCK register +// +//************************************************************************************************* +#define XBAR_TRIPLOCK_LOCK 0x1U // Locks the configuration for EPWM-XBAR +#define XBAR_TRIPLOCK_KEY_S 16U +#define XBAR_TRIPLOCK_KEY_M 0xFFFF0000U // Write protection KEY + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_eqep.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_eqep.h new file mode 100644 index 0000000..7dbb33a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_eqep.h @@ -0,0 +1,225 @@ +//########################################################################### +// +// FILE: hw_eqep.h +// +// TITLE: Definitions for the EQEP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EQEP_H +#define HW_EQEP_H + +//************************************************************************************************* +// +// The following are defines for the EQEP register offsets +// +//************************************************************************************************* +#define EQEP_O_QPOSCNT 0x0U // Position Counter +#define EQEP_O_QPOSINIT 0x2U // Position Counter Init +#define EQEP_O_QPOSMAX 0x4U // Maximum Position Count +#define EQEP_O_QPOSCMP 0x6U // Position Compare +#define EQEP_O_QPOSILAT 0x8U // Index Position Latch +#define EQEP_O_QPOSSLAT 0xAU // Strobe Position Latch +#define EQEP_O_QPOSLAT 0xCU // Position Latch +#define EQEP_O_QUTMR 0xEU // QEP Unit Timer +#define EQEP_O_QUPRD 0x10U // QEP Unit Period +#define EQEP_O_QWDTMR 0x12U // QEP Watchdog Timer +#define EQEP_O_QWDPRD 0x13U // QEP Watchdog Period +#define EQEP_O_QDECCTL 0x14U // Quadrature Decoder Control +#define EQEP_O_QEPCTL 0x15U // QEP Control +#define EQEP_O_QCAPCTL 0x16U // Qaudrature Capture Control +#define EQEP_O_QPOSCTL 0x17U // Position Compare Control +#define EQEP_O_QEINT 0x18U // QEP Interrupt Control +#define EQEP_O_QFLG 0x19U // QEP Interrupt Flag +#define EQEP_O_QCLR 0x1AU // QEP Interrupt Clear +#define EQEP_O_QFRC 0x1BU // QEP Interrupt Force +#define EQEP_O_QEPSTS 0x1CU // QEP Status +#define EQEP_O_QCTMR 0x1DU // QEP Capture Timer +#define EQEP_O_QCPRD 0x1EU // QEP Capture Period +#define EQEP_O_QCTMRLAT 0x1FU // QEP Capture Latch +#define EQEP_O_QCPRDLAT 0x20U // QEP Capture Period Latch + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QDECCTL register +// +//************************************************************************************************* +#define EQEP_QDECCTL_QSP 0x20U // QEPS input polarity +#define EQEP_QDECCTL_QIP 0x40U // QEPI input polarity +#define EQEP_QDECCTL_QBP 0x80U // QEPB input polarity +#define EQEP_QDECCTL_QAP 0x100U // QEPA input polarity +#define EQEP_QDECCTL_IGATE 0x200U // Index pulse gating option +#define EQEP_QDECCTL_SWAP 0x400U // CLK/DIR Signal Source for Position Counter +#define EQEP_QDECCTL_XCR 0x800U // External Clock Rate +#define EQEP_QDECCTL_SPSEL 0x1000U // Sync output pin selection +#define EQEP_QDECCTL_SOEN 0x2000U // Sync output-enable +#define EQEP_QDECCTL_QSRC_S 14U +#define EQEP_QDECCTL_QSRC_M 0xC000U // Position-counter source selection + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPCTL register +// +//************************************************************************************************* +#define EQEP_QEPCTL_WDE 0x1U // QEP watchdog enable +#define EQEP_QEPCTL_UTE 0x2U // QEP unit timer enable +#define EQEP_QEPCTL_QCLM 0x4U // QEP capture latch mode +#define EQEP_QEPCTL_QPEN 0x8U // Quadrature postotion counter enable +#define EQEP_QEPCTL_IEL_S 4U +#define EQEP_QEPCTL_IEL_M 0x30U // Index event latch +#define EQEP_QEPCTL_SEL 0x40U // Strobe event latch +#define EQEP_QEPCTL_SWI 0x80U // Software init position counter +#define EQEP_QEPCTL_IEI_S 8U +#define EQEP_QEPCTL_IEI_M 0x300U // Index event init of position count +#define EQEP_QEPCTL_SEI_S 10U +#define EQEP_QEPCTL_SEI_M 0xC00U // Strobe event init +#define EQEP_QEPCTL_PCRM_S 12U +#define EQEP_QEPCTL_PCRM_M 0x3000U // Postion counter reset +#define EQEP_QEPCTL_FREE_SOFT_S 14U +#define EQEP_QEPCTL_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCAPCTL register +// +//************************************************************************************************* +#define EQEP_QCAPCTL_UPPS_S 0U +#define EQEP_QCAPCTL_UPPS_M 0xFU // Unit position event prescaler +#define EQEP_QCAPCTL_CCPS_S 4U +#define EQEP_QCAPCTL_CCPS_M 0x70U // eQEP capture timer clock prescaler +#define EQEP_QCAPCTL_CEN 0x8000U // Enable eQEP capture + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QPOSCTL register +// +//************************************************************************************************* +#define EQEP_QPOSCTL_PCSPW_S 0U +#define EQEP_QPOSCTL_PCSPW_M 0xFFFU // Position compare sync pulse width +#define EQEP_QPOSCTL_PCE 0x1000U // Position compare enable/disable +#define EQEP_QPOSCTL_PCPOL 0x2000U // Polarity of sync output +#define EQEP_QPOSCTL_PCLOAD 0x4000U // Position compare of shadow load +#define EQEP_QPOSCTL_PCSHDW 0x8000U // Position compare of shadow enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEINT register +// +//************************************************************************************************* +#define EQEP_QEINT_PCE 0x2U // Position counter error interrupt enable +#define EQEP_QEINT_QPE 0x4U // Quadrature phase error interrupt enable +#define EQEP_QEINT_QDC 0x8U // Quadrature direction change interrupt enable +#define EQEP_QEINT_WTO 0x10U // Watchdog time out interrupt enable +#define EQEP_QEINT_PCU 0x20U // Position counter underflow interrupt enable +#define EQEP_QEINT_PCO 0x40U // Position counter overflow interrupt enable +#define EQEP_QEINT_PCR 0x80U // Position-compare ready interrupt enable +#define EQEP_QEINT_PCM 0x100U // Position-compare match interrupt enable +#define EQEP_QEINT_SEL 0x200U // Strobe event latch interrupt enable +#define EQEP_QEINT_IEL 0x400U // Index event latch interrupt enable +#define EQEP_QEINT_UTO 0x800U // Unit time out interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFLG register +// +//************************************************************************************************* +#define EQEP_QFLG_INT 0x1U // Global interrupt status flag +#define EQEP_QFLG_PCE 0x2U // Position counter error interrupt flag +#define EQEP_QFLG_PHE 0x4U // Quadrature phase error interrupt flag +#define EQEP_QFLG_QDC 0x8U // Quadrature direction change interrupt flag +#define EQEP_QFLG_WTO 0x10U // Watchdog timeout interrupt flag +#define EQEP_QFLG_PCU 0x20U // Position counter underflow interrupt flag +#define EQEP_QFLG_PCO 0x40U // Position counter overflow interrupt flag +#define EQEP_QFLG_PCR 0x80U // Position-compare ready interrupt flag +#define EQEP_QFLG_PCM 0x100U // eQEP compare match event interrupt flag +#define EQEP_QFLG_SEL 0x200U // Strobe event latch interrupt flag +#define EQEP_QFLG_IEL 0x400U // Index event latch interrupt flag +#define EQEP_QFLG_UTO 0x800U // Unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCLR register +// +//************************************************************************************************* +#define EQEP_QCLR_INT 0x1U // Global interrupt clear flag +#define EQEP_QCLR_PCE 0x2U // Clear position counter error interrupt flag +#define EQEP_QCLR_PHE 0x4U // Clear quadrature phase error interrupt flag +#define EQEP_QCLR_QDC 0x8U // Clear quadrature direction change interrupt flag +#define EQEP_QCLR_WTO 0x10U // Clear watchdog timeout interrupt flag +#define EQEP_QCLR_PCU 0x20U // Clear position counter underflow interrupt flag +#define EQEP_QCLR_PCO 0x40U // Clear position counter overflow interrupt flag +#define EQEP_QCLR_PCR 0x80U // Clear position-compare ready interrupt flag +#define EQEP_QCLR_PCM 0x100U // Clear eQEP compare match event interrupt flag +#define EQEP_QCLR_SEL 0x200U // Clear strobe event latch interrupt flag +#define EQEP_QCLR_IEL 0x400U // Clear index event latch interrupt flag +#define EQEP_QCLR_UTO 0x800U // Clear unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFRC register +// +//************************************************************************************************* +#define EQEP_QFRC_PCE 0x2U // Force position counter error interrupt +#define EQEP_QFRC_PHE 0x4U // Force quadrature phase error interrupt +#define EQEP_QFRC_QDC 0x8U // Force quadrature direction change interrupt +#define EQEP_QFRC_WTO 0x10U // Force watchdog time out interrupt +#define EQEP_QFRC_PCU 0x20U // Force position counter underflow interrupt +#define EQEP_QFRC_PCO 0x40U // Force position counter overflow interrupt +#define EQEP_QFRC_PCR 0x80U // Force position-compare ready interrupt +#define EQEP_QFRC_PCM 0x100U // Force position-compare match interrupt +#define EQEP_QFRC_SEL 0x200U // Force strobe event latch interrupt +#define EQEP_QFRC_IEL 0x400U // Force index event latch interrupt +#define EQEP_QFRC_UTO 0x800U // Force unit time out interrupt + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPSTS register +// +//************************************************************************************************* +#define EQEP_QEPSTS_PCEF 0x1U // Position counter error flag. +#define EQEP_QEPSTS_FIMF 0x2U // First index marker flag +#define EQEP_QEPSTS_CDEF 0x4U // Capture direction error flag +#define EQEP_QEPSTS_COEF 0x8U // Capture overflow error flag +#define EQEP_QEPSTS_QDLF 0x10U // eQEP direction latch flag +#define EQEP_QEPSTS_QDF 0x20U // Quadrature direction flag +#define EQEP_QEPSTS_FIDF 0x40U // The first index marker +#define EQEP_QEPSTS_UPEVNT 0x80U // Unit position event flag + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_flash.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_flash.h new file mode 100644 index 0000000..73319f1 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_flash.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_flash.h +// +// TITLE: Definitions for the FLASH registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_FLASH_H +#define HW_FLASH_H + +//************************************************************************************************* +// +// The following are defines for the FLASH register offsets +// +//************************************************************************************************* +#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register +#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register +#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register +#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register +#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1 +#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register +#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register + +#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable +#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low +#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High +#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low +#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High +#define FLASH_O_ERR_STATUS 0xAU // Error Status +#define FLASH_O_ERR_POS 0xCU // Error Position +#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear +#define FLASH_O_ERR_CNT 0x10U // Error Control +#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold +#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag +#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear +#define FLASH_O_FDATAH_TEST 0x18U // Data High Test +#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test +#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address +#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address +#define FLASH_O_FECC_CTRL 0x20U // ECC Control +#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High +#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low +#define FLASH_O_FECC_STATUS 0x26U // ECC Status + +#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRDCNTL register +// +//************************************************************************************************* +#define FLASH_FRDCNTL_RWAIT_S 8U +#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBAC register +// +//************************************************************************************************* +#define FLASH_FBAC_VREADST_S 0U +#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBFALLBACK register +// +//************************************************************************************************* +#define FLASH_FBFALLBACK_BNKPWR0_S 0U +#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBPRDY register +// +//************************************************************************************************* +#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State +#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FPAC1 register +// +//************************************************************************************************* +#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode +#define FLASH_FPAC1_PSLEEP_S 16U +#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FMSTAT register +// +//************************************************************************************************* +#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend. +#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend. +#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status +#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status +#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data +#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status +#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status +#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit +#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status +#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRD_INTF_CTRL register +// +//************************************************************************************************* +#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable +#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECC_ENABLE register +// +//************************************************************************************************* +#define FLASH_ECC_ENABLE_ENABLE_S 0U +#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred +#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_POS register +// +//************************************************************************************************* +#define FLASH_ERR_POS_ERR_POS_L_S 0U +#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits +#define FLASH_ERR_POS_ERR_POS_H_S 16U +#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS_CLR register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error + // occurred Clear +#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error + // occurred Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_CNT register +// +//************************************************************************************************* +#define FLASH_ERR_CNT_ERR_CNT_S 0U +#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_THRESHOLD register +// +//************************************************************************************************* +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTFLG register +// +//************************************************************************************************* +#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag +#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTCLR register +// +//************************************************************************************************* +#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear +#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FADDR_TEST register +// +//************************************************************************************************* +#define FLASH_FADDR_TEST_ADDRL_S 3U +#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low +#define FLASH_FADDR_TEST_ADDRH_S 16U +#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_TEST register +// +//************************************************************************************************* +#define FLASH_FECC_TEST_ECC_S 0U +#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_CTRL register +// +//************************************************************************************************* +#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic +#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select +#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_STATUS register +// +//************************************************************************************************* +#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error +#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error +#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U +#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error +#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PUMPREQUEST register +// +//************************************************************************************************* +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between + // CPU1 and CPU2 +#define FLASH_PUMPREQUEST_KEY_S 16U +#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this + // register + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_gpio.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_gpio.h new file mode 100644 index 0000000..0be426d --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_gpio.h @@ -0,0 +1,4018 @@ +//########################################################################### +// +// FILE: hw_gpio.h +// +// TITLE: Definitions for the GPIO registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_GPIO_H +#define HW_GPIO_H + +//************************************************************************************************* +// +// The following are defines for the GPIO register offsets +// +//************************************************************************************************* +#define GPIO_O_GPACTRL 0x0U // GPIO A Qualification Sampling Period Control (GPIO0 to 31) +#define GPIO_O_GPAQSEL1 0x2U // GPIO A Qualifier Select 1 Register (GPIO0 to 15) +#define GPIO_O_GPAQSEL2 0x4U // GPIO A Qualifier Select 2 Register (GPIO16 to 31) +#define GPIO_O_GPAMUX1 0x6U // GPIO A Mux 1 Register (GPIO0 to 15) +#define GPIO_O_GPAMUX2 0x8U // GPIO A Mux 2 Register (GPIO16 to 31) +#define GPIO_O_GPADIR 0xAU // GPIO A Direction Register (GPIO0 to 31) +#define GPIO_O_GPAPUD 0xCU // GPIO A Pull Up Disable Register (GPIO0 to 31) +#define GPIO_O_GPAINV 0x10U // GPIO A Input Polarity Invert Registers (GPIO0 to 31) +#define GPIO_O_GPAODR 0x12U // GPIO A Open Drain Output Register (GPIO0 to GPIO31) +#define GPIO_O_GPAGMUX1 0x20U // GPIO A Peripheral Group Mux (GPIO0 to 15) +#define GPIO_O_GPAGMUX2 0x22U // GPIO A Peripheral Group Mux (GPIO16 to 31) +#define GPIO_O_GPACSEL1 0x28U // GPIO A Core Select Register (GPIO0 to 7) +#define GPIO_O_GPACSEL2 0x2AU // GPIO A Core Select Register (GPIO8 to 15) +#define GPIO_O_GPACSEL3 0x2CU // GPIO A Core Select Register (GPIO16 to 23) +#define GPIO_O_GPACSEL4 0x2EU // GPIO A Core Select Register (GPIO24 to 31) +#define GPIO_O_GPALOCK 0x3CU // GPIO A Lock Configuration Register (GPIO0 to 31) +#define GPIO_O_GPACR 0x3EU // GPIO A Lock Commit Register (GPIO0 to 31) +#define GPIO_O_GPBCTRL 0x40U // GPIO B Qualification Sampling Period Control (GPIO32 to 63) +#define GPIO_O_GPBQSEL1 0x42U // GPIO B Qualifier Select 1 Register (GPIO32 to 47) +#define GPIO_O_GPBQSEL2 0x44U // GPIO B Qualifier Select 2 Register (GPIO48 to 63) +#define GPIO_O_GPBMUX1 0x46U // GPIO B Mux 1 Register (GPIO32 to 47) +#define GPIO_O_GPBMUX2 0x48U // GPIO B Mux 2 Register (GPIO48 to 63) +#define GPIO_O_GPBDIR 0x4AU // GPIO B Direction Register (GPIO32 to 63) +#define GPIO_O_GPBPUD 0x4CU // GPIO B Pull Up Disable Register (GPIO32 to 63) +#define GPIO_O_GPBINV 0x50U // GPIO B Input Polarity Invert Registers (GPIO32 to 63) +#define GPIO_O_GPBODR 0x52U // GPIO B Open Drain Output Register (GPIO32 to GPIO63) +#define GPIO_O_GPBAMSEL 0x54U // GPIO B Analog Mode Select register (GPIO32 to GPIO63) +#define GPIO_O_GPBGMUX1 0x60U // GPIO B Peripheral Group Mux (GPIO32 to 47) +#define GPIO_O_GPBGMUX2 0x62U // GPIO B Peripheral Group Mux (GPIO48 to 63) +#define GPIO_O_GPBCSEL1 0x68U // GPIO B Core Select Register (GPIO32 to 39) +#define GPIO_O_GPBCSEL2 0x6AU // GPIO B Core Select Register (GPIO40 to 47) +#define GPIO_O_GPBCSEL3 0x6CU // GPIO B Core Select Register (GPIO48 to 55) +#define GPIO_O_GPBCSEL4 0x6EU // GPIO B Core Select Register (GPIO56 to 63) +#define GPIO_O_GPBLOCK 0x7CU // GPIO B Lock Configuration Register (GPIO32 to 63) +#define GPIO_O_GPBCR 0x7EU // GPIO B Lock Commit Register (GPIO32 to 63) +#define GPIO_O_GPCCTRL 0x80U // GPIO C Qualification Sampling Period Control (GPIO64 to 95) +#define GPIO_O_GPCQSEL1 0x82U // GPIO C Qualifier Select 1 Register (GPIO64 to 79) +#define GPIO_O_GPCQSEL2 0x84U // GPIO C Qualifier Select 2 Register (GPIO80 to 95) +#define GPIO_O_GPCMUX1 0x86U // GPIO C Mux 1 Register (GPIO64 to 79) +#define GPIO_O_GPCMUX2 0x88U // GPIO C Mux 2 Register (GPIO80 to 95) +#define GPIO_O_GPCDIR 0x8AU // GPIO C Direction Register (GPIO64 to 95) +#define GPIO_O_GPCPUD 0x8CU // GPIO C Pull Up Disable Register (GPIO64 to 95) +#define GPIO_O_GPCINV 0x90U // GPIO C Input Polarity Invert Registers (GPIO64 to 95) +#define GPIO_O_GPCODR 0x92U // GPIO C Open Drain Output Register (GPIO64 to GPIO95) +#define GPIO_O_GPCGMUX1 0xA0U // GPIO C Peripheral Group Mux (GPIO64 to 79) +#define GPIO_O_GPCGMUX2 0xA2U // GPIO C Peripheral Group Mux (GPIO80 to 95) +#define GPIO_O_GPCCSEL1 0xA8U // GPIO C Core Select Register (GPIO64 to 71) +#define GPIO_O_GPCCSEL2 0xAAU // GPIO C Core Select Register (GPIO72 to 79) +#define GPIO_O_GPCCSEL3 0xACU // GPIO C Core Select Register (GPIO80 to 87) +#define GPIO_O_GPCCSEL4 0xAEU // GPIO C Core Select Register (GPIO88 to 95) +#define GPIO_O_GPCLOCK 0xBCU // GPIO C Lock Configuration Register (GPIO64 to 95) +#define GPIO_O_GPCCR 0xBEU // GPIO C Lock Commit Register (GPIO64 to 95) +#define GPIO_O_GPDCTRL 0xC0U // GPIO D Qualification Sampling Period Control (GPIO96 to 127) +#define GPIO_O_GPDQSEL1 0xC2U // GPIO D Qualifier Select 1 Register (GPIO96 to 111) +#define GPIO_O_GPDQSEL2 0xC4U // GPIO D Qualifier Select 2 Register (GPIO112 to 127) +#define GPIO_O_GPDMUX1 0xC6U // GPIO D Mux 1 Register (GPIO96 to 111) +#define GPIO_O_GPDMUX2 0xC8U // GPIO D Mux 2 Register (GPIO112 to 127) +#define GPIO_O_GPDDIR 0xCAU // GPIO D Direction Register (GPIO96 to 127) +#define GPIO_O_GPDPUD 0xCCU // GPIO D Pull Up Disable Register (GPIO96 to 127) +#define GPIO_O_GPDINV 0xD0U // GPIO D Input Polarity Invert Registers (GPIO96 to 127) +#define GPIO_O_GPDODR 0xD2U // GPIO D Open Drain Output Register (GPIO96 to GPIO127) +#define GPIO_O_GPDGMUX1 0xE0U // GPIO D Peripheral Group Mux (GPIO96 to 111) +#define GPIO_O_GPDGMUX2 0xE2U // GPIO D Peripheral Group Mux (GPIO112 to 127) +#define GPIO_O_GPDCSEL1 0xE8U // GPIO D Core Select Register (GPIO96 to 103) +#define GPIO_O_GPDCSEL2 0xEAU // GPIO D Core Select Register (GPIO104 to 111) +#define GPIO_O_GPDCSEL3 0xECU // GPIO D Core Select Register (GPIO112 to 119) +#define GPIO_O_GPDCSEL4 0xEEU // GPIO D Core Select Register (GPIO120 to 127) +#define GPIO_O_GPDLOCK 0xFCU // GPIO D Lock Configuration Register (GPIO96 to 127) +#define GPIO_O_GPDCR 0xFEU // GPIO D Lock Commit Register (GPIO96 to 127) +#define GPIO_O_GPECTRL 0x100U // GPIO E Qualification Sampling Period Control (GPIO128 to 159) +#define GPIO_O_GPEQSEL1 0x102U // GPIO E Qualifier Select 1 Register (GPIO128 to 143) +#define GPIO_O_GPEQSEL2 0x104U // GPIO E Qualifier Select 2 Register (GPIO144 to 159) +#define GPIO_O_GPEMUX1 0x106U // GPIO E Mux 1 Register (GPIO128 to 143) +#define GPIO_O_GPEMUX2 0x108U // GPIO E Mux 2 Register (GPIO144 to 159) +#define GPIO_O_GPEDIR 0x10AU // GPIO E Direction Register (GPIO128 to 159) +#define GPIO_O_GPEPUD 0x10CU // GPIO E Pull Up Disable Register (GPIO128 to 159) +#define GPIO_O_GPEINV 0x110U // GPIO E Input Polarity Invert Registers (GPIO128 to 159) +#define GPIO_O_GPEODR 0x112U // GPIO E Open Drain Output Register (GPIO128 to GPIO159) +#define GPIO_O_GPEGMUX1 0x120U // GPIO E Peripheral Group Mux (GPIO128 to 143) +#define GPIO_O_GPEGMUX2 0x122U // GPIO E Peripheral Group Mux (GPIO144 to 159) +#define GPIO_O_GPECSEL1 0x128U // GPIO E Core Select Register (GPIO128 to 135) +#define GPIO_O_GPECSEL2 0x12AU // GPIO E Core Select Register (GPIO136 to 143) +#define GPIO_O_GPECSEL3 0x12CU // GPIO E Core Select Register (GPIO144 to 151) +#define GPIO_O_GPECSEL4 0x12EU // GPIO E Core Select Register (GPIO152 to 159) +#define GPIO_O_GPELOCK 0x13CU // GPIO E Lock Configuration Register (GPIO128 to 159) +#define GPIO_O_GPECR 0x13EU // GPIO E Lock Commit Register (GPIO128 to 159) +#define GPIO_O_GPFCTRL 0x140U // GPIO F Qualification Sampling Period Control (GPIO160 to 168) +#define GPIO_O_GPFQSEL1 0x142U // GPIO F Qualifier Select 1 Register (GPIO160 to 168) +#define GPIO_O_GPFMUX1 0x146U // GPIO F Mux 1 Register (GPIO160 to 168) +#define GPIO_O_GPFDIR 0x14AU // GPIO F Direction Register (GPIO160 to 168) +#define GPIO_O_GPFPUD 0x14CU // GPIO F Pull Up Disable Register (GPIO160 to 168) +#define GPIO_O_GPFINV 0x150U // GPIO F Input Polarity Invert Registers (GPIO160 to 168) +#define GPIO_O_GPFODR 0x152U // GPIO F Open Drain Output Register (GPIO160 to GPIO168) +#define GPIO_O_GPFGMUX1 0x160U // GPIO F Peripheral Group Mux (GPIO160 to 168) +#define GPIO_O_GPFCSEL1 0x168U // GPIO F Core Select Register (GPIO160 to 167) +#define GPIO_O_GPFCSEL2 0x16AU // GPIO F Core Select Register (GPIO168) +#define GPIO_O_GPFLOCK 0x17CU // GPIO F Lock Configuration Register (GPIO160 to 168) +#define GPIO_O_GPFCR 0x17EU // GPIO F Lock Commit Register (GPIO160 to 168) + +#define GPIO_O_GPADAT 0x0U // GPIO A Data Register (GPIO0 to 31) +#define GPIO_O_GPASET 0x2U // GPIO A Data Set Register (GPIO0 to 31) +#define GPIO_O_GPACLEAR 0x4U // GPIO A Data Clear Register (GPIO0 to 31) +#define GPIO_O_GPATOGGLE 0x6U // GPIO A Data Toggle Register (GPIO0 to 31) +#define GPIO_O_GPBDAT 0x8U // GPIO B Data Register (GPIO32 to 63) +#define GPIO_O_GPBSET 0xAU // GPIO B Data Set Register (GPIO32 to 63) +#define GPIO_O_GPBCLEAR 0xCU // GPIO B Data Clear Register (GPIO32 to 63) +#define GPIO_O_GPBTOGGLE 0xEU // GPIO B Data Toggle Register (GPIO32 to 63) +#define GPIO_O_GPCDAT 0x10U // GPIO C Data Register (GPIO64 to 95) +#define GPIO_O_GPCSET 0x12U // GPIO C Data Set Register (GPIO64 to 95) +#define GPIO_O_GPCCLEAR 0x14U // GPIO C Data Clear Register (GPIO64 to 95) +#define GPIO_O_GPCTOGGLE 0x16U // GPIO C Data Toggle Register (GPIO64 to 95) +#define GPIO_O_GPDDAT 0x18U // GPIO D Data Register (GPIO96 to 127) +#define GPIO_O_GPDSET 0x1AU // GPIO D Data Set Register (GPIO96 to 127) +#define GPIO_O_GPDCLEAR 0x1CU // GPIO D Data Clear Register (GPIO96 to 127) +#define GPIO_O_GPDTOGGLE 0x1EU // GPIO D Data Toggle Register (GPIO96 to 127) +#define GPIO_O_GPEDAT 0x20U // GPIO E Data Register (GPIO128 to 159) +#define GPIO_O_GPESET 0x22U // GPIO E Data Set Register (GPIO128 to 159) +#define GPIO_O_GPECLEAR 0x24U // GPIO E Data Clear Register (GPIO128 to 159) +#define GPIO_O_GPETOGGLE 0x26U // GPIO E Data Toggle Register (GPIO128 to 159) +#define GPIO_O_GPFDAT 0x28U // GPIO F Data Register (GPIO160 to 168) +#define GPIO_O_GPFSET 0x2AU // GPIO F Data Set Register (GPIO160 to 168) +#define GPIO_O_GPFCLEAR 0x2CU // GPIO F Data Clear Register (GPIO160 to 168) +#define GPIO_O_GPFTOGGLE 0x2EU // GPIO F Data Toggle Register (GPIO160 to 168) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACTRL register +// +//************************************************************************************************* +#define GPIO_GPACTRL_QUALPRD0_S 0U +#define GPIO_GPACTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO0 to GPIO7 +#define GPIO_GPACTRL_QUALPRD1_S 8U +#define GPIO_GPACTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO8 to + // GPIO15 +#define GPIO_GPACTRL_QUALPRD2_S 16U +#define GPIO_GPACTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO16 to + // GPIO23 +#define GPIO_GPACTRL_QUALPRD3_S 24U +#define GPIO_GPACTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO24 to + // GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL1_GPIO0_S 0U +#define GPIO_GPAQSEL1_GPIO0_M 0x3U // Select input qualification type for GPIO0 +#define GPIO_GPAQSEL1_GPIO1_S 2U +#define GPIO_GPAQSEL1_GPIO1_M 0xCU // Select input qualification type for GPIO1 +#define GPIO_GPAQSEL1_GPIO2_S 4U +#define GPIO_GPAQSEL1_GPIO2_M 0x30U // Select input qualification type for GPIO2 +#define GPIO_GPAQSEL1_GPIO3_S 6U +#define GPIO_GPAQSEL1_GPIO3_M 0xC0U // Select input qualification type for GPIO3 +#define GPIO_GPAQSEL1_GPIO4_S 8U +#define GPIO_GPAQSEL1_GPIO4_M 0x300U // Select input qualification type for GPIO4 +#define GPIO_GPAQSEL1_GPIO5_S 10U +#define GPIO_GPAQSEL1_GPIO5_M 0xC00U // Select input qualification type for GPIO5 +#define GPIO_GPAQSEL1_GPIO6_S 12U +#define GPIO_GPAQSEL1_GPIO6_M 0x3000U // Select input qualification type for GPIO6 +#define GPIO_GPAQSEL1_GPIO7_S 14U +#define GPIO_GPAQSEL1_GPIO7_M 0xC000U // Select input qualification type for GPIO7 +#define GPIO_GPAQSEL1_GPIO8_S 16U +#define GPIO_GPAQSEL1_GPIO8_M 0x30000U // Select input qualification type for GPIO8 +#define GPIO_GPAQSEL1_GPIO9_S 18U +#define GPIO_GPAQSEL1_GPIO9_M 0xC0000U // Select input qualification type for GPIO9 +#define GPIO_GPAQSEL1_GPIO10_S 20U +#define GPIO_GPAQSEL1_GPIO10_M 0x300000U // Select input qualification type for GPIO10 +#define GPIO_GPAQSEL1_GPIO11_S 22U +#define GPIO_GPAQSEL1_GPIO11_M 0xC00000U // Select input qualification type for GPIO11 +#define GPIO_GPAQSEL1_GPIO12_S 24U +#define GPIO_GPAQSEL1_GPIO12_M 0x3000000U // Select input qualification type for GPIO12 +#define GPIO_GPAQSEL1_GPIO13_S 26U +#define GPIO_GPAQSEL1_GPIO13_M 0xC000000U // Select input qualification type for GPIO13 +#define GPIO_GPAQSEL1_GPIO14_S 28U +#define GPIO_GPAQSEL1_GPIO14_M 0x30000000U // Select input qualification type for GPIO14 +#define GPIO_GPAQSEL1_GPIO15_S 30U +#define GPIO_GPAQSEL1_GPIO15_M 0xC0000000U // Select input qualification type for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL2_GPIO16_S 0U +#define GPIO_GPAQSEL2_GPIO16_M 0x3U // Select input qualification type for GPIO16 +#define GPIO_GPAQSEL2_GPIO17_S 2U +#define GPIO_GPAQSEL2_GPIO17_M 0xCU // Select input qualification type for GPIO17 +#define GPIO_GPAQSEL2_GPIO18_S 4U +#define GPIO_GPAQSEL2_GPIO18_M 0x30U // Select input qualification type for GPIO18 +#define GPIO_GPAQSEL2_GPIO19_S 6U +#define GPIO_GPAQSEL2_GPIO19_M 0xC0U // Select input qualification type for GPIO19 +#define GPIO_GPAQSEL2_GPIO20_S 8U +#define GPIO_GPAQSEL2_GPIO20_M 0x300U // Select input qualification type for GPIO20 +#define GPIO_GPAQSEL2_GPIO21_S 10U +#define GPIO_GPAQSEL2_GPIO21_M 0xC00U // Select input qualification type for GPIO21 +#define GPIO_GPAQSEL2_GPIO22_S 12U +#define GPIO_GPAQSEL2_GPIO22_M 0x3000U // Select input qualification type for GPIO22 +#define GPIO_GPAQSEL2_GPIO23_S 14U +#define GPIO_GPAQSEL2_GPIO23_M 0xC000U // Select input qualification type for GPIO23 +#define GPIO_GPAQSEL2_GPIO24_S 16U +#define GPIO_GPAQSEL2_GPIO24_M 0x30000U // Select input qualification type for GPIO24 +#define GPIO_GPAQSEL2_GPIO25_S 18U +#define GPIO_GPAQSEL2_GPIO25_M 0xC0000U // Select input qualification type for GPIO25 +#define GPIO_GPAQSEL2_GPIO26_S 20U +#define GPIO_GPAQSEL2_GPIO26_M 0x300000U // Select input qualification type for GPIO26 +#define GPIO_GPAQSEL2_GPIO27_S 22U +#define GPIO_GPAQSEL2_GPIO27_M 0xC00000U // Select input qualification type for GPIO27 +#define GPIO_GPAQSEL2_GPIO28_S 24U +#define GPIO_GPAQSEL2_GPIO28_M 0x3000000U // Select input qualification type for GPIO28 +#define GPIO_GPAQSEL2_GPIO29_S 26U +#define GPIO_GPAQSEL2_GPIO29_M 0xC000000U // Select input qualification type for GPIO29 +#define GPIO_GPAQSEL2_GPIO30_S 28U +#define GPIO_GPAQSEL2_GPIO30_M 0x30000000U // Select input qualification type for GPIO30 +#define GPIO_GPAQSEL2_GPIO31_S 30U +#define GPIO_GPAQSEL2_GPIO31_M 0xC0000000U // Select input qualification type for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAMUX1_GPIO0_S 0U +#define GPIO_GPAMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAMUX1_GPIO1_S 2U +#define GPIO_GPAMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAMUX1_GPIO2_S 4U +#define GPIO_GPAMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAMUX1_GPIO3_S 6U +#define GPIO_GPAMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAMUX1_GPIO4_S 8U +#define GPIO_GPAMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAMUX1_GPIO5_S 10U +#define GPIO_GPAMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAMUX1_GPIO6_S 12U +#define GPIO_GPAMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAMUX1_GPIO7_S 14U +#define GPIO_GPAMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAMUX1_GPIO8_S 16U +#define GPIO_GPAMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAMUX1_GPIO9_S 18U +#define GPIO_GPAMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAMUX1_GPIO10_S 20U +#define GPIO_GPAMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAMUX1_GPIO11_S 22U +#define GPIO_GPAMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAMUX1_GPIO12_S 24U +#define GPIO_GPAMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAMUX1_GPIO13_S 26U +#define GPIO_GPAMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAMUX1_GPIO14_S 28U +#define GPIO_GPAMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAMUX1_GPIO15_S 30U +#define GPIO_GPAMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAMUX2_GPIO16_S 0U +#define GPIO_GPAMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAMUX2_GPIO17_S 2U +#define GPIO_GPAMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAMUX2_GPIO18_S 4U +#define GPIO_GPAMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAMUX2_GPIO19_S 6U +#define GPIO_GPAMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAMUX2_GPIO20_S 8U +#define GPIO_GPAMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAMUX2_GPIO21_S 10U +#define GPIO_GPAMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAMUX2_GPIO22_S 12U +#define GPIO_GPAMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAMUX2_GPIO23_S 14U +#define GPIO_GPAMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAMUX2_GPIO24_S 16U +#define GPIO_GPAMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAMUX2_GPIO25_S 18U +#define GPIO_GPAMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAMUX2_GPIO26_S 20U +#define GPIO_GPAMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAMUX2_GPIO27_S 22U +#define GPIO_GPAMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAMUX2_GPIO28_S 24U +#define GPIO_GPAMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAMUX2_GPIO29_S 26U +#define GPIO_GPAMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAMUX2_GPIO30_S 28U +#define GPIO_GPAMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAMUX2_GPIO31_S 30U +#define GPIO_GPAMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADIR register +// +//************************************************************************************************* +#define GPIO_GPADIR_GPIO0 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO1 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO2 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO3 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO4 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO5 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO6 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO7 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO8 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO9 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO10 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO11 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO12 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO13 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO14 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO15 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO16 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO17 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO18 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO19 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO20 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO21 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO22 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO23 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO24 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO25 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO26 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO27 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO28 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO29 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO30 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO31 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAPUD register +// +//************************************************************************************************* +#define GPIO_GPAPUD_GPIO0 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO1 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO2 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO3 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO4 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO5 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO6 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO7 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO8 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO9 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO10 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO11 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO12 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO13 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO14 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO15 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO16 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO17 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO18 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO19 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO20 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO21 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO22 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO23 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO24 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO25 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO26 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO27 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO28 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO29 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO30 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO31 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAINV register +// +//************************************************************************************************* +#define GPIO_GPAINV_GPIO0 0x1U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO1 0x2U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO2 0x4U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO3 0x8U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO4 0x10U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO5 0x20U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO6 0x40U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO7 0x80U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO8 0x100U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO9 0x200U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO10 0x400U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO11 0x800U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO12 0x1000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO13 0x2000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO14 0x4000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO15 0x8000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO16 0x10000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO17 0x20000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO18 0x40000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO19 0x80000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO20 0x100000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO21 0x200000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO22 0x400000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO23 0x800000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO24 0x1000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO25 0x2000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO26 0x4000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO27 0x8000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO28 0x10000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO29 0x20000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO30 0x40000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO31 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAODR register +// +//************************************************************************************************* +#define GPIO_GPAODR_GPIO0 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO1 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO2 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO3 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO4 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO5 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO6 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO7 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO8 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO9 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO10 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO11 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO12 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO13 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO14 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO15 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO16 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO17 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO18 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO19 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO20 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO21 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO22 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO23 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO24 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO25 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO26 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO27 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO28 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO29 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO30 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO31 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX1_GPIO0_S 0U +#define GPIO_GPAGMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAGMUX1_GPIO1_S 2U +#define GPIO_GPAGMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAGMUX1_GPIO2_S 4U +#define GPIO_GPAGMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAGMUX1_GPIO3_S 6U +#define GPIO_GPAGMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAGMUX1_GPIO4_S 8U +#define GPIO_GPAGMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAGMUX1_GPIO5_S 10U +#define GPIO_GPAGMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAGMUX1_GPIO6_S 12U +#define GPIO_GPAGMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAGMUX1_GPIO7_S 14U +#define GPIO_GPAGMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAGMUX1_GPIO8_S 16U +#define GPIO_GPAGMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAGMUX1_GPIO9_S 18U +#define GPIO_GPAGMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAGMUX1_GPIO10_S 20U +#define GPIO_GPAGMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAGMUX1_GPIO11_S 22U +#define GPIO_GPAGMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAGMUX1_GPIO12_S 24U +#define GPIO_GPAGMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAGMUX1_GPIO13_S 26U +#define GPIO_GPAGMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAGMUX1_GPIO14_S 28U +#define GPIO_GPAGMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAGMUX1_GPIO15_S 30U +#define GPIO_GPAGMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX2_GPIO16_S 0U +#define GPIO_GPAGMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAGMUX2_GPIO17_S 2U +#define GPIO_GPAGMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAGMUX2_GPIO18_S 4U +#define GPIO_GPAGMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAGMUX2_GPIO19_S 6U +#define GPIO_GPAGMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAGMUX2_GPIO20_S 8U +#define GPIO_GPAGMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAGMUX2_GPIO21_S 10U +#define GPIO_GPAGMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAGMUX2_GPIO22_S 12U +#define GPIO_GPAGMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAGMUX2_GPIO23_S 14U +#define GPIO_GPAGMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAGMUX2_GPIO24_S 16U +#define GPIO_GPAGMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAGMUX2_GPIO25_S 18U +#define GPIO_GPAGMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAGMUX2_GPIO26_S 20U +#define GPIO_GPAGMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAGMUX2_GPIO27_S 22U +#define GPIO_GPAGMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAGMUX2_GPIO28_S 24U +#define GPIO_GPAGMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAGMUX2_GPIO29_S 26U +#define GPIO_GPAGMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAGMUX2_GPIO30_S 28U +#define GPIO_GPAGMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAGMUX2_GPIO31_S 30U +#define GPIO_GPAGMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL1 register +// +//************************************************************************************************* +#define GPIO_GPACSEL1_GPIO0_S 0U +#define GPIO_GPACSEL1_GPIO0_M 0xFU // GPIO0 Master CPU Select +#define GPIO_GPACSEL1_GPIO1_S 4U +#define GPIO_GPACSEL1_GPIO1_M 0xF0U // GPIO1 Master CPU Select +#define GPIO_GPACSEL1_GPIO2_S 8U +#define GPIO_GPACSEL1_GPIO2_M 0xF00U // GPIO2 Master CPU Select +#define GPIO_GPACSEL1_GPIO3_S 12U +#define GPIO_GPACSEL1_GPIO3_M 0xF000U // GPIO3 Master CPU Select +#define GPIO_GPACSEL1_GPIO4_S 16U +#define GPIO_GPACSEL1_GPIO4_M 0xF0000U // GPIO4 Master CPU Select +#define GPIO_GPACSEL1_GPIO5_S 20U +#define GPIO_GPACSEL1_GPIO5_M 0xF00000U // GPIO5 Master CPU Select +#define GPIO_GPACSEL1_GPIO6_S 24U +#define GPIO_GPACSEL1_GPIO6_M 0xF000000U // GPIO6 Master CPU Select +#define GPIO_GPACSEL1_GPIO7_S 28U +#define GPIO_GPACSEL1_GPIO7_M 0xF0000000U // GPIO7 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL2 register +// +//************************************************************************************************* +#define GPIO_GPACSEL2_GPIO8_S 0U +#define GPIO_GPACSEL2_GPIO8_M 0xFU // GPIO8 Master CPU Select +#define GPIO_GPACSEL2_GPIO9_S 4U +#define GPIO_GPACSEL2_GPIO9_M 0xF0U // GPIO9 Master CPU Select +#define GPIO_GPACSEL2_GPIO10_S 8U +#define GPIO_GPACSEL2_GPIO10_M 0xF00U // GPIO10 Master CPU Select +#define GPIO_GPACSEL2_GPIO11_S 12U +#define GPIO_GPACSEL2_GPIO11_M 0xF000U // GPIO11 Master CPU Select +#define GPIO_GPACSEL2_GPIO12_S 16U +#define GPIO_GPACSEL2_GPIO12_M 0xF0000U // GPIO12 Master CPU Select +#define GPIO_GPACSEL2_GPIO13_S 20U +#define GPIO_GPACSEL2_GPIO13_M 0xF00000U // GPIO13 Master CPU Select +#define GPIO_GPACSEL2_GPIO14_S 24U +#define GPIO_GPACSEL2_GPIO14_M 0xF000000U // GPIO14 Master CPU Select +#define GPIO_GPACSEL2_GPIO15_S 28U +#define GPIO_GPACSEL2_GPIO15_M 0xF0000000U // GPIO15 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL3 register +// +//************************************************************************************************* +#define GPIO_GPACSEL3_GPIO16_S 0U +#define GPIO_GPACSEL3_GPIO16_M 0xFU // GPIO16 Master CPU Select +#define GPIO_GPACSEL3_GPIO17_S 4U +#define GPIO_GPACSEL3_GPIO17_M 0xF0U // GPIO17 Master CPU Select +#define GPIO_GPACSEL3_GPIO18_S 8U +#define GPIO_GPACSEL3_GPIO18_M 0xF00U // GPIO18 Master CPU Select +#define GPIO_GPACSEL3_GPIO19_S 12U +#define GPIO_GPACSEL3_GPIO19_M 0xF000U // GPIO19 Master CPU Select +#define GPIO_GPACSEL3_GPIO20_S 16U +#define GPIO_GPACSEL3_GPIO20_M 0xF0000U // GPIO20 Master CPU Select +#define GPIO_GPACSEL3_GPIO21_S 20U +#define GPIO_GPACSEL3_GPIO21_M 0xF00000U // GPIO21 Master CPU Select +#define GPIO_GPACSEL3_GPIO22_S 24U +#define GPIO_GPACSEL3_GPIO22_M 0xF000000U // GPIO22 Master CPU Select +#define GPIO_GPACSEL3_GPIO23_S 28U +#define GPIO_GPACSEL3_GPIO23_M 0xF0000000U // GPIO23 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL4 register +// +//************************************************************************************************* +#define GPIO_GPACSEL4_GPIO24_S 0U +#define GPIO_GPACSEL4_GPIO24_M 0xFU // GPIO24 Master CPU Select +#define GPIO_GPACSEL4_GPIO25_S 4U +#define GPIO_GPACSEL4_GPIO25_M 0xF0U // GPIO25 Master CPU Select +#define GPIO_GPACSEL4_GPIO26_S 8U +#define GPIO_GPACSEL4_GPIO26_M 0xF00U // GPIO26 Master CPU Select +#define GPIO_GPACSEL4_GPIO27_S 12U +#define GPIO_GPACSEL4_GPIO27_M 0xF000U // GPIO27 Master CPU Select +#define GPIO_GPACSEL4_GPIO28_S 16U +#define GPIO_GPACSEL4_GPIO28_M 0xF0000U // GPIO28 Master CPU Select +#define GPIO_GPACSEL4_GPIO29_S 20U +#define GPIO_GPACSEL4_GPIO29_M 0xF00000U // GPIO29 Master CPU Select +#define GPIO_GPACSEL4_GPIO30_S 24U +#define GPIO_GPACSEL4_GPIO30_M 0xF000000U // GPIO30 Master CPU Select +#define GPIO_GPACSEL4_GPIO31_S 28U +#define GPIO_GPACSEL4_GPIO31_M 0xF0000000U // GPIO31 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPALOCK register +// +//************************************************************************************************* +#define GPIO_GPALOCK_GPIO0 0x1U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO1 0x2U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO2 0x4U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO3 0x8U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO4 0x10U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO5 0x20U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO6 0x40U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO7 0x80U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO8 0x100U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO9 0x200U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO10 0x400U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO11 0x800U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO12 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO13 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO14 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO15 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO16 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO17 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO18 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO19 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO20 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO21 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO22 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO23 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO24 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO25 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO26 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO27 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO28 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO29 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO30 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO31 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACR register +// +//************************************************************************************************* +#define GPIO_GPACR_GPIO0 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO1 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO2 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO3 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO4 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO5 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO6 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO7 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO8 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO9 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO10 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO11 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO12 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO13 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO14 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO15 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO16 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO17 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO18 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO19 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO20 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO21 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO22 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO23 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO24 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO25 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO26 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO27 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO28 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO29 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO30 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO31 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCTRL register +// +//************************************************************************************************* +#define GPIO_GPBCTRL_QUALPRD0_S 0U +#define GPIO_GPBCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO32 to + // GPIO39 +#define GPIO_GPBCTRL_QUALPRD1_S 8U +#define GPIO_GPBCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO40 to + // GPIO47 +#define GPIO_GPBCTRL_QUALPRD2_S 16U +#define GPIO_GPBCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO48 to + // GPIO55 +#define GPIO_GPBCTRL_QUALPRD3_S 24U +#define GPIO_GPBCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO56 to + // GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL1_GPIO32_S 0U +#define GPIO_GPBQSEL1_GPIO32_M 0x3U // Select input qualification type for GPIO32 +#define GPIO_GPBQSEL1_GPIO33_S 2U +#define GPIO_GPBQSEL1_GPIO33_M 0xCU // Select input qualification type for GPIO33 +#define GPIO_GPBQSEL1_GPIO34_S 4U +#define GPIO_GPBQSEL1_GPIO34_M 0x30U // Select input qualification type for GPIO34 +#define GPIO_GPBQSEL1_GPIO35_S 6U +#define GPIO_GPBQSEL1_GPIO35_M 0xC0U // Select input qualification type for GPIO35 +#define GPIO_GPBQSEL1_GPIO36_S 8U +#define GPIO_GPBQSEL1_GPIO36_M 0x300U // Select input qualification type for GPIO36 +#define GPIO_GPBQSEL1_GPIO37_S 10U +#define GPIO_GPBQSEL1_GPIO37_M 0xC00U // Select input qualification type for GPIO37 +#define GPIO_GPBQSEL1_GPIO38_S 12U +#define GPIO_GPBQSEL1_GPIO38_M 0x3000U // Select input qualification type for GPIO38 +#define GPIO_GPBQSEL1_GPIO39_S 14U +#define GPIO_GPBQSEL1_GPIO39_M 0xC000U // Select input qualification type for GPIO39 +#define GPIO_GPBQSEL1_GPIO40_S 16U +#define GPIO_GPBQSEL1_GPIO40_M 0x30000U // Select input qualification type for GPIO40 +#define GPIO_GPBQSEL1_GPIO41_S 18U +#define GPIO_GPBQSEL1_GPIO41_M 0xC0000U // Select input qualification type for GPIO41 +#define GPIO_GPBQSEL1_GPIO42_S 20U +#define GPIO_GPBQSEL1_GPIO42_M 0x300000U // Select input qualification type for GPIO42 +#define GPIO_GPBQSEL1_GPIO43_S 22U +#define GPIO_GPBQSEL1_GPIO43_M 0xC00000U // Select input qualification type for GPIO43 +#define GPIO_GPBQSEL1_GPIO44_S 24U +#define GPIO_GPBQSEL1_GPIO44_M 0x3000000U // Select input qualification type for GPIO44 +#define GPIO_GPBQSEL1_GPIO45_S 26U +#define GPIO_GPBQSEL1_GPIO45_M 0xC000000U // Select input qualification type for GPIO45 +#define GPIO_GPBQSEL1_GPIO46_S 28U +#define GPIO_GPBQSEL1_GPIO46_M 0x30000000U // Select input qualification type for GPIO46 +#define GPIO_GPBQSEL1_GPIO47_S 30U +#define GPIO_GPBQSEL1_GPIO47_M 0xC0000000U // Select input qualification type for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL2_GPIO48_S 0U +#define GPIO_GPBQSEL2_GPIO48_M 0x3U // Select input qualification type for GPIO48 +#define GPIO_GPBQSEL2_GPIO49_S 2U +#define GPIO_GPBQSEL2_GPIO49_M 0xCU // Select input qualification type for GPIO49 +#define GPIO_GPBQSEL2_GPIO50_S 4U +#define GPIO_GPBQSEL2_GPIO50_M 0x30U // Select input qualification type for GPIO50 +#define GPIO_GPBQSEL2_GPIO51_S 6U +#define GPIO_GPBQSEL2_GPIO51_M 0xC0U // Select input qualification type for GPIO51 +#define GPIO_GPBQSEL2_GPIO52_S 8U +#define GPIO_GPBQSEL2_GPIO52_M 0x300U // Select input qualification type for GPIO52 +#define GPIO_GPBQSEL2_GPIO53_S 10U +#define GPIO_GPBQSEL2_GPIO53_M 0xC00U // Select input qualification type for GPIO53 +#define GPIO_GPBQSEL2_GPIO54_S 12U +#define GPIO_GPBQSEL2_GPIO54_M 0x3000U // Select input qualification type for GPIO54 +#define GPIO_GPBQSEL2_GPIO55_S 14U +#define GPIO_GPBQSEL2_GPIO55_M 0xC000U // Select input qualification type for GPIO55 +#define GPIO_GPBQSEL2_GPIO56_S 16U +#define GPIO_GPBQSEL2_GPIO56_M 0x30000U // Select input qualification type for GPIO56 +#define GPIO_GPBQSEL2_GPIO57_S 18U +#define GPIO_GPBQSEL2_GPIO57_M 0xC0000U // Select input qualification type for GPIO57 +#define GPIO_GPBQSEL2_GPIO58_S 20U +#define GPIO_GPBQSEL2_GPIO58_M 0x300000U // Select input qualification type for GPIO58 +#define GPIO_GPBQSEL2_GPIO59_S 22U +#define GPIO_GPBQSEL2_GPIO59_M 0xC00000U // Select input qualification type for GPIO59 +#define GPIO_GPBQSEL2_GPIO60_S 24U +#define GPIO_GPBQSEL2_GPIO60_M 0x3000000U // Select input qualification type for GPIO60 +#define GPIO_GPBQSEL2_GPIO61_S 26U +#define GPIO_GPBQSEL2_GPIO61_M 0xC000000U // Select input qualification type for GPIO61 +#define GPIO_GPBQSEL2_GPIO62_S 28U +#define GPIO_GPBQSEL2_GPIO62_M 0x30000000U // Select input qualification type for GPIO62 +#define GPIO_GPBQSEL2_GPIO63_S 30U +#define GPIO_GPBQSEL2_GPIO63_M 0xC0000000U // Select input qualification type for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBMUX1_GPIO32_S 0U +#define GPIO_GPBMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBMUX1_GPIO33_S 2U +#define GPIO_GPBMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBMUX1_GPIO34_S 4U +#define GPIO_GPBMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBMUX1_GPIO35_S 6U +#define GPIO_GPBMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBMUX1_GPIO36_S 8U +#define GPIO_GPBMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBMUX1_GPIO37_S 10U +#define GPIO_GPBMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBMUX1_GPIO38_S 12U +#define GPIO_GPBMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBMUX1_GPIO39_S 14U +#define GPIO_GPBMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBMUX1_GPIO40_S 16U +#define GPIO_GPBMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBMUX1_GPIO41_S 18U +#define GPIO_GPBMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBMUX1_GPIO42_S 20U +#define GPIO_GPBMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBMUX1_GPIO43_S 22U +#define GPIO_GPBMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBMUX1_GPIO44_S 24U +#define GPIO_GPBMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBMUX1_GPIO45_S 26U +#define GPIO_GPBMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBMUX1_GPIO46_S 28U +#define GPIO_GPBMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBMUX1_GPIO47_S 30U +#define GPIO_GPBMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBMUX2_GPIO48_S 0U +#define GPIO_GPBMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBMUX2_GPIO49_S 2U +#define GPIO_GPBMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBMUX2_GPIO50_S 4U +#define GPIO_GPBMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBMUX2_GPIO51_S 6U +#define GPIO_GPBMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBMUX2_GPIO52_S 8U +#define GPIO_GPBMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBMUX2_GPIO53_S 10U +#define GPIO_GPBMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBMUX2_GPIO54_S 12U +#define GPIO_GPBMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBMUX2_GPIO55_S 14U +#define GPIO_GPBMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBMUX2_GPIO56_S 16U +#define GPIO_GPBMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBMUX2_GPIO57_S 18U +#define GPIO_GPBMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBMUX2_GPIO58_S 20U +#define GPIO_GPBMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBMUX2_GPIO59_S 22U +#define GPIO_GPBMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBMUX2_GPIO60_S 24U +#define GPIO_GPBMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBMUX2_GPIO61_S 26U +#define GPIO_GPBMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBMUX2_GPIO62_S 28U +#define GPIO_GPBMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBMUX2_GPIO63_S 30U +#define GPIO_GPBMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDIR register +// +//************************************************************************************************* +#define GPIO_GPBDIR_GPIO32 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO33 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO34 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO35 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO36 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO37 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO38 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO39 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO40 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO41 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO42 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO43 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO44 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO45 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO46 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO47 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO48 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO49 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO50 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO51 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO52 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO53 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO54 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO55 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO56 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO57 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO58 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO59 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO60 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO61 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO62 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO63 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBPUD register +// +//************************************************************************************************* +#define GPIO_GPBPUD_GPIO32 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO33 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO34 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO35 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO36 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO37 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO38 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO39 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO40 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO41 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO42 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO43 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO44 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO45 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO46 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO47 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO48 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO49 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO50 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO51 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO52 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO53 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO54 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO55 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO56 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO57 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO58 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO59 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO60 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO61 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO62 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO63 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBINV register +// +//************************************************************************************************* +#define GPIO_GPBINV_GPIO32 0x1U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO33 0x2U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO34 0x4U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO35 0x8U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO36 0x10U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO37 0x20U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO38 0x40U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO39 0x80U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO40 0x100U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO41 0x200U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO42 0x400U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO43 0x800U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO44 0x1000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO45 0x2000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO46 0x4000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO47 0x8000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO48 0x10000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO49 0x20000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO50 0x40000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO51 0x80000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO52 0x100000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO53 0x200000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO54 0x400000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO55 0x800000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO56 0x1000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO57 0x2000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO58 0x4000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO59 0x8000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO60 0x10000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO61 0x20000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO62 0x40000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO63 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBODR register +// +//************************************************************************************************* +#define GPIO_GPBODR_GPIO32 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO33 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO34 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO35 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO36 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO37 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO38 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO39 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO40 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO41 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO42 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO43 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO44 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO45 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO46 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO47 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO48 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO49 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO50 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO51 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO52 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO53 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO54 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO55 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO56 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO57 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO58 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO59 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO60 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO61 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO62 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO63 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBAMSEL register +// +//************************************************************************************************* +#define GPIO_GPBAMSEL_GPIO42 0x400U // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO43 0x800U // Analog Mode select for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX1_GPIO32_S 0U +#define GPIO_GPBGMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBGMUX1_GPIO33_S 2U +#define GPIO_GPBGMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBGMUX1_GPIO34_S 4U +#define GPIO_GPBGMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBGMUX1_GPIO35_S 6U +#define GPIO_GPBGMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBGMUX1_GPIO36_S 8U +#define GPIO_GPBGMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBGMUX1_GPIO37_S 10U +#define GPIO_GPBGMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBGMUX1_GPIO38_S 12U +#define GPIO_GPBGMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBGMUX1_GPIO39_S 14U +#define GPIO_GPBGMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBGMUX1_GPIO40_S 16U +#define GPIO_GPBGMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBGMUX1_GPIO41_S 18U +#define GPIO_GPBGMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBGMUX1_GPIO42_S 20U +#define GPIO_GPBGMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBGMUX1_GPIO43_S 22U +#define GPIO_GPBGMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBGMUX1_GPIO44_S 24U +#define GPIO_GPBGMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBGMUX1_GPIO45_S 26U +#define GPIO_GPBGMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBGMUX1_GPIO46_S 28U +#define GPIO_GPBGMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBGMUX1_GPIO47_S 30U +#define GPIO_GPBGMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX2_GPIO48_S 0U +#define GPIO_GPBGMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBGMUX2_GPIO49_S 2U +#define GPIO_GPBGMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBGMUX2_GPIO50_S 4U +#define GPIO_GPBGMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBGMUX2_GPIO51_S 6U +#define GPIO_GPBGMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBGMUX2_GPIO52_S 8U +#define GPIO_GPBGMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBGMUX2_GPIO53_S 10U +#define GPIO_GPBGMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBGMUX2_GPIO54_S 12U +#define GPIO_GPBGMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBGMUX2_GPIO55_S 14U +#define GPIO_GPBGMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBGMUX2_GPIO56_S 16U +#define GPIO_GPBGMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBGMUX2_GPIO57_S 18U +#define GPIO_GPBGMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBGMUX2_GPIO58_S 20U +#define GPIO_GPBGMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBGMUX2_GPIO59_S 22U +#define GPIO_GPBGMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBGMUX2_GPIO60_S 24U +#define GPIO_GPBGMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBGMUX2_GPIO61_S 26U +#define GPIO_GPBGMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBGMUX2_GPIO62_S 28U +#define GPIO_GPBGMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBGMUX2_GPIO63_S 30U +#define GPIO_GPBGMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL1_GPIO32_S 0U +#define GPIO_GPBCSEL1_GPIO32_M 0xFU // GPIO32 Master CPU Select +#define GPIO_GPBCSEL1_GPIO33_S 4U +#define GPIO_GPBCSEL1_GPIO33_M 0xF0U // GPIO33 Master CPU Select +#define GPIO_GPBCSEL1_GPIO34_S 8U +#define GPIO_GPBCSEL1_GPIO34_M 0xF00U // GPIO34 Master CPU Select +#define GPIO_GPBCSEL1_GPIO35_S 12U +#define GPIO_GPBCSEL1_GPIO35_M 0xF000U // GPIO35 Master CPU Select +#define GPIO_GPBCSEL1_GPIO36_S 16U +#define GPIO_GPBCSEL1_GPIO36_M 0xF0000U // GPIO36 Master CPU Select +#define GPIO_GPBCSEL1_GPIO37_S 20U +#define GPIO_GPBCSEL1_GPIO37_M 0xF00000U // GPIO37 Master CPU Select +#define GPIO_GPBCSEL1_GPIO38_S 24U +#define GPIO_GPBCSEL1_GPIO38_M 0xF000000U // GPIO38 Master CPU Select +#define GPIO_GPBCSEL1_GPIO39_S 28U +#define GPIO_GPBCSEL1_GPIO39_M 0xF0000000U // GPIO39 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL2_GPIO40_S 0U +#define GPIO_GPBCSEL2_GPIO40_M 0xFU // GPIO40 Master CPU Select +#define GPIO_GPBCSEL2_GPIO41_S 4U +#define GPIO_GPBCSEL2_GPIO41_M 0xF0U // GPIO41 Master CPU Select +#define GPIO_GPBCSEL2_GPIO42_S 8U +#define GPIO_GPBCSEL2_GPIO42_M 0xF00U // GPIO42 Master CPU Select +#define GPIO_GPBCSEL2_GPIO43_S 12U +#define GPIO_GPBCSEL2_GPIO43_M 0xF000U // GPIO43 Master CPU Select +#define GPIO_GPBCSEL2_GPIO44_S 16U +#define GPIO_GPBCSEL2_GPIO44_M 0xF0000U // GPIO44 Master CPU Select +#define GPIO_GPBCSEL2_GPIO45_S 20U +#define GPIO_GPBCSEL2_GPIO45_M 0xF00000U // GPIO45 Master CPU Select +#define GPIO_GPBCSEL2_GPIO46_S 24U +#define GPIO_GPBCSEL2_GPIO46_M 0xF000000U // GPIO46 Master CPU Select +#define GPIO_GPBCSEL2_GPIO47_S 28U +#define GPIO_GPBCSEL2_GPIO47_M 0xF0000000U // GPIO47 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL3_GPIO48_S 0U +#define GPIO_GPBCSEL3_GPIO48_M 0xFU // GPIO48 Master CPU Select +#define GPIO_GPBCSEL3_GPIO49_S 4U +#define GPIO_GPBCSEL3_GPIO49_M 0xF0U // GPIO49 Master CPU Select +#define GPIO_GPBCSEL3_GPIO50_S 8U +#define GPIO_GPBCSEL3_GPIO50_M 0xF00U // GPIO50 Master CPU Select +#define GPIO_GPBCSEL3_GPIO51_S 12U +#define GPIO_GPBCSEL3_GPIO51_M 0xF000U // GPIO51 Master CPU Select +#define GPIO_GPBCSEL3_GPIO52_S 16U +#define GPIO_GPBCSEL3_GPIO52_M 0xF0000U // GPIO52 Master CPU Select +#define GPIO_GPBCSEL3_GPIO53_S 20U +#define GPIO_GPBCSEL3_GPIO53_M 0xF00000U // GPIO53 Master CPU Select +#define GPIO_GPBCSEL3_GPIO54_S 24U +#define GPIO_GPBCSEL3_GPIO54_M 0xF000000U // GPIO54 Master CPU Select +#define GPIO_GPBCSEL3_GPIO55_S 28U +#define GPIO_GPBCSEL3_GPIO55_M 0xF0000000U // GPIO55 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL4_GPIO56_S 0U +#define GPIO_GPBCSEL4_GPIO56_M 0xFU // GPIO56 Master CPU Select +#define GPIO_GPBCSEL4_GPIO57_S 4U +#define GPIO_GPBCSEL4_GPIO57_M 0xF0U // GPIO57 Master CPU Select +#define GPIO_GPBCSEL4_GPIO58_S 8U +#define GPIO_GPBCSEL4_GPIO58_M 0xF00U // GPIO58 Master CPU Select +#define GPIO_GPBCSEL4_GPIO59_S 12U +#define GPIO_GPBCSEL4_GPIO59_M 0xF000U // GPIO59 Master CPU Select +#define GPIO_GPBCSEL4_GPIO60_S 16U +#define GPIO_GPBCSEL4_GPIO60_M 0xF0000U // GPIO60 Master CPU Select +#define GPIO_GPBCSEL4_GPIO61_S 20U +#define GPIO_GPBCSEL4_GPIO61_M 0xF00000U // GPIO61 Master CPU Select +#define GPIO_GPBCSEL4_GPIO62_S 24U +#define GPIO_GPBCSEL4_GPIO62_M 0xF000000U // GPIO62 Master CPU Select +#define GPIO_GPBCSEL4_GPIO63_S 28U +#define GPIO_GPBCSEL4_GPIO63_M 0xF0000000U // GPIO63 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBLOCK register +// +//************************************************************************************************* +#define GPIO_GPBLOCK_GPIO32 0x1U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO33 0x2U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO34 0x4U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO35 0x8U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO36 0x10U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO37 0x20U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO38 0x40U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO39 0x80U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO40 0x100U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO41 0x200U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO42 0x400U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO43 0x800U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO44 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO45 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO46 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO47 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO48 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO49 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO50 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO51 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO52 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO53 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO54 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO55 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO56 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO57 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO58 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO59 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO60 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO61 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO62 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO63 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCR register +// +//************************************************************************************************* +#define GPIO_GPBCR_GPIO32 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO33 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO34 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO35 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO36 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO37 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO38 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO39 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO40 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO41 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO42 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO43 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO44 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO45 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO46 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO47 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO48 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO49 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO50 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO51 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO52 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO53 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO54 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO55 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO56 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO57 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO58 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO59 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO60 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO61 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO62 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO63 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCTRL register +// +//************************************************************************************************* +#define GPIO_GPCCTRL_QUALPRD0_S 0U +#define GPIO_GPCCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO64 to + // GPIO71 +#define GPIO_GPCCTRL_QUALPRD1_S 8U +#define GPIO_GPCCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO72 to + // GPIO79 +#define GPIO_GPCCTRL_QUALPRD2_S 16U +#define GPIO_GPCCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO80 to + // GPIO87 +#define GPIO_GPCCTRL_QUALPRD3_S 24U +#define GPIO_GPCCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO88 to + // GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL1_GPIO64_S 0U +#define GPIO_GPCQSEL1_GPIO64_M 0x3U // Select input qualification type for GPIO64 +#define GPIO_GPCQSEL1_GPIO65_S 2U +#define GPIO_GPCQSEL1_GPIO65_M 0xCU // Select input qualification type for GPIO65 +#define GPIO_GPCQSEL1_GPIO66_S 4U +#define GPIO_GPCQSEL1_GPIO66_M 0x30U // Select input qualification type for GPIO66 +#define GPIO_GPCQSEL1_GPIO67_S 6U +#define GPIO_GPCQSEL1_GPIO67_M 0xC0U // Select input qualification type for GPIO67 +#define GPIO_GPCQSEL1_GPIO68_S 8U +#define GPIO_GPCQSEL1_GPIO68_M 0x300U // Select input qualification type for GPIO68 +#define GPIO_GPCQSEL1_GPIO69_S 10U +#define GPIO_GPCQSEL1_GPIO69_M 0xC00U // Select input qualification type for GPIO69 +#define GPIO_GPCQSEL1_GPIO70_S 12U +#define GPIO_GPCQSEL1_GPIO70_M 0x3000U // Select input qualification type for GPIO70 +#define GPIO_GPCQSEL1_GPIO71_S 14U +#define GPIO_GPCQSEL1_GPIO71_M 0xC000U // Select input qualification type for GPIO71 +#define GPIO_GPCQSEL1_GPIO72_S 16U +#define GPIO_GPCQSEL1_GPIO72_M 0x30000U // Select input qualification type for GPIO72 +#define GPIO_GPCQSEL1_GPIO73_S 18U +#define GPIO_GPCQSEL1_GPIO73_M 0xC0000U // Select input qualification type for GPIO73 +#define GPIO_GPCQSEL1_GPIO74_S 20U +#define GPIO_GPCQSEL1_GPIO74_M 0x300000U // Select input qualification type for GPIO74 +#define GPIO_GPCQSEL1_GPIO75_S 22U +#define GPIO_GPCQSEL1_GPIO75_M 0xC00000U // Select input qualification type for GPIO75 +#define GPIO_GPCQSEL1_GPIO76_S 24U +#define GPIO_GPCQSEL1_GPIO76_M 0x3000000U // Select input qualification type for GPIO76 +#define GPIO_GPCQSEL1_GPIO77_S 26U +#define GPIO_GPCQSEL1_GPIO77_M 0xC000000U // Select input qualification type for GPIO77 +#define GPIO_GPCQSEL1_GPIO78_S 28U +#define GPIO_GPCQSEL1_GPIO78_M 0x30000000U // Select input qualification type for GPIO78 +#define GPIO_GPCQSEL1_GPIO79_S 30U +#define GPIO_GPCQSEL1_GPIO79_M 0xC0000000U // Select input qualification type for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL2_GPIO80_S 0U +#define GPIO_GPCQSEL2_GPIO80_M 0x3U // Select input qualification type for GPIO80 +#define GPIO_GPCQSEL2_GPIO81_S 2U +#define GPIO_GPCQSEL2_GPIO81_M 0xCU // Select input qualification type for GPIO81 +#define GPIO_GPCQSEL2_GPIO82_S 4U +#define GPIO_GPCQSEL2_GPIO82_M 0x30U // Select input qualification type for GPIO82 +#define GPIO_GPCQSEL2_GPIO83_S 6U +#define GPIO_GPCQSEL2_GPIO83_M 0xC0U // Select input qualification type for GPIO83 +#define GPIO_GPCQSEL2_GPIO84_S 8U +#define GPIO_GPCQSEL2_GPIO84_M 0x300U // Select input qualification type for GPIO84 +#define GPIO_GPCQSEL2_GPIO85_S 10U +#define GPIO_GPCQSEL2_GPIO85_M 0xC00U // Select input qualification type for GPIO85 +#define GPIO_GPCQSEL2_GPIO86_S 12U +#define GPIO_GPCQSEL2_GPIO86_M 0x3000U // Select input qualification type for GPIO86 +#define GPIO_GPCQSEL2_GPIO87_S 14U +#define GPIO_GPCQSEL2_GPIO87_M 0xC000U // Select input qualification type for GPIO87 +#define GPIO_GPCQSEL2_GPIO88_S 16U +#define GPIO_GPCQSEL2_GPIO88_M 0x30000U // Select input qualification type for GPIO88 +#define GPIO_GPCQSEL2_GPIO89_S 18U +#define GPIO_GPCQSEL2_GPIO89_M 0xC0000U // Select input qualification type for GPIO89 +#define GPIO_GPCQSEL2_GPIO90_S 20U +#define GPIO_GPCQSEL2_GPIO90_M 0x300000U // Select input qualification type for GPIO90 +#define GPIO_GPCQSEL2_GPIO91_S 22U +#define GPIO_GPCQSEL2_GPIO91_M 0xC00000U // Select input qualification type for GPIO91 +#define GPIO_GPCQSEL2_GPIO92_S 24U +#define GPIO_GPCQSEL2_GPIO92_M 0x3000000U // Select input qualification type for GPIO92 +#define GPIO_GPCQSEL2_GPIO93_S 26U +#define GPIO_GPCQSEL2_GPIO93_M 0xC000000U // Select input qualification type for GPIO93 +#define GPIO_GPCQSEL2_GPIO94_S 28U +#define GPIO_GPCQSEL2_GPIO94_M 0x30000000U // Select input qualification type for GPIO94 +#define GPIO_GPCQSEL2_GPIO95_S 30U +#define GPIO_GPCQSEL2_GPIO95_M 0xC0000000U // Select input qualification type for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCMUX1_GPIO64_S 0U +#define GPIO_GPCMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCMUX1_GPIO65_S 2U +#define GPIO_GPCMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCMUX1_GPIO66_S 4U +#define GPIO_GPCMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCMUX1_GPIO67_S 6U +#define GPIO_GPCMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCMUX1_GPIO68_S 8U +#define GPIO_GPCMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCMUX1_GPIO69_S 10U +#define GPIO_GPCMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCMUX1_GPIO70_S 12U +#define GPIO_GPCMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCMUX1_GPIO71_S 14U +#define GPIO_GPCMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCMUX1_GPIO72_S 16U +#define GPIO_GPCMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCMUX1_GPIO73_S 18U +#define GPIO_GPCMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCMUX1_GPIO74_S 20U +#define GPIO_GPCMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCMUX1_GPIO75_S 22U +#define GPIO_GPCMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCMUX1_GPIO76_S 24U +#define GPIO_GPCMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCMUX1_GPIO77_S 26U +#define GPIO_GPCMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCMUX1_GPIO78_S 28U +#define GPIO_GPCMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCMUX1_GPIO79_S 30U +#define GPIO_GPCMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCMUX2_GPIO80_S 0U +#define GPIO_GPCMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCMUX2_GPIO81_S 2U +#define GPIO_GPCMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCMUX2_GPIO82_S 4U +#define GPIO_GPCMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCMUX2_GPIO83_S 6U +#define GPIO_GPCMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCMUX2_GPIO84_S 8U +#define GPIO_GPCMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCMUX2_GPIO85_S 10U +#define GPIO_GPCMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCMUX2_GPIO86_S 12U +#define GPIO_GPCMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCMUX2_GPIO87_S 14U +#define GPIO_GPCMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCMUX2_GPIO88_S 16U +#define GPIO_GPCMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCMUX2_GPIO89_S 18U +#define GPIO_GPCMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCMUX2_GPIO90_S 20U +#define GPIO_GPCMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCMUX2_GPIO91_S 22U +#define GPIO_GPCMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCMUX2_GPIO92_S 24U +#define GPIO_GPCMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCMUX2_GPIO93_S 26U +#define GPIO_GPCMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCMUX2_GPIO94_S 28U +#define GPIO_GPCMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCMUX2_GPIO95_S 30U +#define GPIO_GPCMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDIR register +// +//************************************************************************************************* +#define GPIO_GPCDIR_GPIO64 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO65 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO66 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO67 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO68 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO69 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO70 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO71 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO72 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO73 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO74 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO75 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO76 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO77 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO78 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO79 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO80 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO81 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO82 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO83 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO84 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO85 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO86 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO87 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO88 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO89 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO90 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO91 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO92 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO93 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO94 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO95 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCPUD register +// +//************************************************************************************************* +#define GPIO_GPCPUD_GPIO64 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO65 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO66 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO67 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO68 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO69 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO70 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO71 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO72 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO73 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO74 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO75 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO76 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO77 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO78 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO79 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO80 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO81 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO82 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO83 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO84 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO85 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO86 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO87 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO88 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO89 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO90 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO91 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO92 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO93 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO94 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO95 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCINV register +// +//************************************************************************************************* +#define GPIO_GPCINV_GPIO64 0x1U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO65 0x2U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO66 0x4U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO67 0x8U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO68 0x10U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO69 0x20U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO70 0x40U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO71 0x80U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO72 0x100U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO73 0x200U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO74 0x400U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO75 0x800U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO76 0x1000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO77 0x2000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO78 0x4000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO79 0x8000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO80 0x10000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO81 0x20000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO82 0x40000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO83 0x80000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO84 0x100000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO85 0x200000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO86 0x400000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO87 0x800000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO88 0x1000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO89 0x2000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO90 0x4000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO91 0x8000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO92 0x10000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO93 0x20000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO94 0x40000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO95 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCODR register +// +//************************************************************************************************* +#define GPIO_GPCODR_GPIO64 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO65 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO66 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO67 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO68 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO69 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO70 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO71 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO72 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO73 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO74 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO75 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO76 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO77 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO78 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO79 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO80 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO81 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO82 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO83 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO84 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO85 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO86 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO87 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO88 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO89 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO90 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO91 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO92 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO93 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO94 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO95 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX1_GPIO64_S 0U +#define GPIO_GPCGMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCGMUX1_GPIO65_S 2U +#define GPIO_GPCGMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCGMUX1_GPIO66_S 4U +#define GPIO_GPCGMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCGMUX1_GPIO67_S 6U +#define GPIO_GPCGMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCGMUX1_GPIO68_S 8U +#define GPIO_GPCGMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCGMUX1_GPIO69_S 10U +#define GPIO_GPCGMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCGMUX1_GPIO70_S 12U +#define GPIO_GPCGMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCGMUX1_GPIO71_S 14U +#define GPIO_GPCGMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCGMUX1_GPIO72_S 16U +#define GPIO_GPCGMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCGMUX1_GPIO73_S 18U +#define GPIO_GPCGMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCGMUX1_GPIO74_S 20U +#define GPIO_GPCGMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCGMUX1_GPIO75_S 22U +#define GPIO_GPCGMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCGMUX1_GPIO76_S 24U +#define GPIO_GPCGMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCGMUX1_GPIO77_S 26U +#define GPIO_GPCGMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCGMUX1_GPIO78_S 28U +#define GPIO_GPCGMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCGMUX1_GPIO79_S 30U +#define GPIO_GPCGMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX2_GPIO80_S 0U +#define GPIO_GPCGMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCGMUX2_GPIO81_S 2U +#define GPIO_GPCGMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCGMUX2_GPIO82_S 4U +#define GPIO_GPCGMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCGMUX2_GPIO83_S 6U +#define GPIO_GPCGMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCGMUX2_GPIO84_S 8U +#define GPIO_GPCGMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCGMUX2_GPIO85_S 10U +#define GPIO_GPCGMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCGMUX2_GPIO86_S 12U +#define GPIO_GPCGMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCGMUX2_GPIO87_S 14U +#define GPIO_GPCGMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCGMUX2_GPIO88_S 16U +#define GPIO_GPCGMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCGMUX2_GPIO89_S 18U +#define GPIO_GPCGMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCGMUX2_GPIO90_S 20U +#define GPIO_GPCGMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCGMUX2_GPIO91_S 22U +#define GPIO_GPCGMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCGMUX2_GPIO92_S 24U +#define GPIO_GPCGMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCGMUX2_GPIO93_S 26U +#define GPIO_GPCGMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCGMUX2_GPIO94_S 28U +#define GPIO_GPCGMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCGMUX2_GPIO95_S 30U +#define GPIO_GPCGMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL1_GPIO64_S 0U +#define GPIO_GPCCSEL1_GPIO64_M 0xFU // GPIO64 Master CPU Select +#define GPIO_GPCCSEL1_GPIO65_S 4U +#define GPIO_GPCCSEL1_GPIO65_M 0xF0U // GPIO65 Master CPU Select +#define GPIO_GPCCSEL1_GPIO66_S 8U +#define GPIO_GPCCSEL1_GPIO66_M 0xF00U // GPIO66 Master CPU Select +#define GPIO_GPCCSEL1_GPIO67_S 12U +#define GPIO_GPCCSEL1_GPIO67_M 0xF000U // GPIO67 Master CPU Select +#define GPIO_GPCCSEL1_GPIO68_S 16U +#define GPIO_GPCCSEL1_GPIO68_M 0xF0000U // GPIO68 Master CPU Select +#define GPIO_GPCCSEL1_GPIO69_S 20U +#define GPIO_GPCCSEL1_GPIO69_M 0xF00000U // GPIO69 Master CPU Select +#define GPIO_GPCCSEL1_GPIO70_S 24U +#define GPIO_GPCCSEL1_GPIO70_M 0xF000000U // GPIO70 Master CPU Select +#define GPIO_GPCCSEL1_GPIO71_S 28U +#define GPIO_GPCCSEL1_GPIO71_M 0xF0000000U // GPIO71 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL2_GPIO72_S 0U +#define GPIO_GPCCSEL2_GPIO72_M 0xFU // GPIO72 Master CPU Select +#define GPIO_GPCCSEL2_GPIO73_S 4U +#define GPIO_GPCCSEL2_GPIO73_M 0xF0U // GPIO73 Master CPU Select +#define GPIO_GPCCSEL2_GPIO74_S 8U +#define GPIO_GPCCSEL2_GPIO74_M 0xF00U // GPIO74 Master CPU Select +#define GPIO_GPCCSEL2_GPIO75_S 12U +#define GPIO_GPCCSEL2_GPIO75_M 0xF000U // GPIO75 Master CPU Select +#define GPIO_GPCCSEL2_GPIO76_S 16U +#define GPIO_GPCCSEL2_GPIO76_M 0xF0000U // GPIO76 Master CPU Select +#define GPIO_GPCCSEL2_GPIO77_S 20U +#define GPIO_GPCCSEL2_GPIO77_M 0xF00000U // GPIO77 Master CPU Select +#define GPIO_GPCCSEL2_GPIO78_S 24U +#define GPIO_GPCCSEL2_GPIO78_M 0xF000000U // GPIO78 Master CPU Select +#define GPIO_GPCCSEL2_GPIO79_S 28U +#define GPIO_GPCCSEL2_GPIO79_M 0xF0000000U // GPIO79 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL3_GPIO80_S 0U +#define GPIO_GPCCSEL3_GPIO80_M 0xFU // GPIO80 Master CPU Select +#define GPIO_GPCCSEL3_GPIO81_S 4U +#define GPIO_GPCCSEL3_GPIO81_M 0xF0U // GPIO81 Master CPU Select +#define GPIO_GPCCSEL3_GPIO82_S 8U +#define GPIO_GPCCSEL3_GPIO82_M 0xF00U // GPIO82 Master CPU Select +#define GPIO_GPCCSEL3_GPIO83_S 12U +#define GPIO_GPCCSEL3_GPIO83_M 0xF000U // GPIO83 Master CPU Select +#define GPIO_GPCCSEL3_GPIO84_S 16U +#define GPIO_GPCCSEL3_GPIO84_M 0xF0000U // GPIO84 Master CPU Select +#define GPIO_GPCCSEL3_GPIO85_S 20U +#define GPIO_GPCCSEL3_GPIO85_M 0xF00000U // GPIO85 Master CPU Select +#define GPIO_GPCCSEL3_GPIO86_S 24U +#define GPIO_GPCCSEL3_GPIO86_M 0xF000000U // GPIO86 Master CPU Select +#define GPIO_GPCCSEL3_GPIO87_S 28U +#define GPIO_GPCCSEL3_GPIO87_M 0xF0000000U // GPIO87 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL4_GPIO88_S 0U +#define GPIO_GPCCSEL4_GPIO88_M 0xFU // GPIO88 Master CPU Select +#define GPIO_GPCCSEL4_GPIO89_S 4U +#define GPIO_GPCCSEL4_GPIO89_M 0xF0U // GPIO89 Master CPU Select +#define GPIO_GPCCSEL4_GPIO90_S 8U +#define GPIO_GPCCSEL4_GPIO90_M 0xF00U // GPIO90 Master CPU Select +#define GPIO_GPCCSEL4_GPIO91_S 12U +#define GPIO_GPCCSEL4_GPIO91_M 0xF000U // GPIO91 Master CPU Select +#define GPIO_GPCCSEL4_GPIO92_S 16U +#define GPIO_GPCCSEL4_GPIO92_M 0xF0000U // GPIO92 Master CPU Select +#define GPIO_GPCCSEL4_GPIO93_S 20U +#define GPIO_GPCCSEL4_GPIO93_M 0xF00000U // GPIO93 Master CPU Select +#define GPIO_GPCCSEL4_GPIO94_S 24U +#define GPIO_GPCCSEL4_GPIO94_M 0xF000000U // GPIO94 Master CPU Select +#define GPIO_GPCCSEL4_GPIO95_S 28U +#define GPIO_GPCCSEL4_GPIO95_M 0xF0000000U // GPIO95 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCLOCK register +// +//************************************************************************************************* +#define GPIO_GPCLOCK_GPIO64 0x1U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO65 0x2U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO66 0x4U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO67 0x8U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO68 0x10U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO69 0x20U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO70 0x40U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO71 0x80U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO72 0x100U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO73 0x200U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO74 0x400U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO75 0x800U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO76 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO77 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO78 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO79 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO80 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO81 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO82 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO83 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO84 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO85 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO86 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO87 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO88 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO89 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO90 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO91 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO92 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO93 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO94 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO95 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCR register +// +//************************************************************************************************* +#define GPIO_GPCCR_GPIO64 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO65 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO66 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO67 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO68 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO69 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO70 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO71 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO72 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO73 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO74 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO75 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO76 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO77 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO78 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO79 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO80 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO81 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO82 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO83 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO84 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO85 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO86 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO87 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO88 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO89 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO90 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO91 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO92 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO93 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO94 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO95 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCTRL register +// +//************************************************************************************************* +#define GPIO_GPDCTRL_QUALPRD0_S 0U +#define GPIO_GPDCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO96 to + // GPIO103 +#define GPIO_GPDCTRL_QUALPRD1_S 8U +#define GPIO_GPDCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO104 to + // GPIO111 +#define GPIO_GPDCTRL_QUALPRD2_S 16U +#define GPIO_GPDCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO112 to + // GPIO119 +#define GPIO_GPDCTRL_QUALPRD3_S 24U +#define GPIO_GPDCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO120 to + // GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL1_GPIO96_S 0U +#define GPIO_GPDQSEL1_GPIO96_M 0x3U // Select input qualification type for GPIO96 +#define GPIO_GPDQSEL1_GPIO97_S 2U +#define GPIO_GPDQSEL1_GPIO97_M 0xCU // Select input qualification type for GPIO97 +#define GPIO_GPDQSEL1_GPIO98_S 4U +#define GPIO_GPDQSEL1_GPIO98_M 0x30U // Select input qualification type for GPIO98 +#define GPIO_GPDQSEL1_GPIO99_S 6U +#define GPIO_GPDQSEL1_GPIO99_M 0xC0U // Select input qualification type for GPIO99 +#define GPIO_GPDQSEL1_GPIO100_S 8U +#define GPIO_GPDQSEL1_GPIO100_M 0x300U // Select input qualification type for GPIO100 +#define GPIO_GPDQSEL1_GPIO101_S 10U +#define GPIO_GPDQSEL1_GPIO101_M 0xC00U // Select input qualification type for GPIO101 +#define GPIO_GPDQSEL1_GPIO102_S 12U +#define GPIO_GPDQSEL1_GPIO102_M 0x3000U // Select input qualification type for GPIO102 +#define GPIO_GPDQSEL1_GPIO103_S 14U +#define GPIO_GPDQSEL1_GPIO103_M 0xC000U // Select input qualification type for GPIO103 +#define GPIO_GPDQSEL1_GPIO104_S 16U +#define GPIO_GPDQSEL1_GPIO104_M 0x30000U // Select input qualification type for GPIO104 +#define GPIO_GPDQSEL1_GPIO105_S 18U +#define GPIO_GPDQSEL1_GPIO105_M 0xC0000U // Select input qualification type for GPIO105 +#define GPIO_GPDQSEL1_GPIO106_S 20U +#define GPIO_GPDQSEL1_GPIO106_M 0x300000U // Select input qualification type for GPIO106 +#define GPIO_GPDQSEL1_GPIO107_S 22U +#define GPIO_GPDQSEL1_GPIO107_M 0xC00000U // Select input qualification type for GPIO107 +#define GPIO_GPDQSEL1_GPIO108_S 24U +#define GPIO_GPDQSEL1_GPIO108_M 0x3000000U // Select input qualification type for GPIO108 +#define GPIO_GPDQSEL1_GPIO109_S 26U +#define GPIO_GPDQSEL1_GPIO109_M 0xC000000U // Select input qualification type for GPIO109 +#define GPIO_GPDQSEL1_GPIO110_S 28U +#define GPIO_GPDQSEL1_GPIO110_M 0x30000000U // Select input qualification type for GPIO110 +#define GPIO_GPDQSEL1_GPIO111_S 30U +#define GPIO_GPDQSEL1_GPIO111_M 0xC0000000U // Select input qualification type for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL2_GPIO112_S 0U +#define GPIO_GPDQSEL2_GPIO112_M 0x3U // Select input qualification type for GPIO112 +#define GPIO_GPDQSEL2_GPIO113_S 2U +#define GPIO_GPDQSEL2_GPIO113_M 0xCU // Select input qualification type for GPIO113 +#define GPIO_GPDQSEL2_GPIO114_S 4U +#define GPIO_GPDQSEL2_GPIO114_M 0x30U // Select input qualification type for GPIO114 +#define GPIO_GPDQSEL2_GPIO115_S 6U +#define GPIO_GPDQSEL2_GPIO115_M 0xC0U // Select input qualification type for GPIO115 +#define GPIO_GPDQSEL2_GPIO116_S 8U +#define GPIO_GPDQSEL2_GPIO116_M 0x300U // Select input qualification type for GPIO116 +#define GPIO_GPDQSEL2_GPIO117_S 10U +#define GPIO_GPDQSEL2_GPIO117_M 0xC00U // Select input qualification type for GPIO117 +#define GPIO_GPDQSEL2_GPIO118_S 12U +#define GPIO_GPDQSEL2_GPIO118_M 0x3000U // Select input qualification type for GPIO118 +#define GPIO_GPDQSEL2_GPIO119_S 14U +#define GPIO_GPDQSEL2_GPIO119_M 0xC000U // Select input qualification type for GPIO119 +#define GPIO_GPDQSEL2_GPIO120_S 16U +#define GPIO_GPDQSEL2_GPIO120_M 0x30000U // Select input qualification type for GPIO120 +#define GPIO_GPDQSEL2_GPIO121_S 18U +#define GPIO_GPDQSEL2_GPIO121_M 0xC0000U // Select input qualification type for GPIO121 +#define GPIO_GPDQSEL2_GPIO122_S 20U +#define GPIO_GPDQSEL2_GPIO122_M 0x300000U // Select input qualification type for GPIO122 +#define GPIO_GPDQSEL2_GPIO123_S 22U +#define GPIO_GPDQSEL2_GPIO123_M 0xC00000U // Select input qualification type for GPIO123 +#define GPIO_GPDQSEL2_GPIO124_S 24U +#define GPIO_GPDQSEL2_GPIO124_M 0x3000000U // Select input qualification type for GPIO124 +#define GPIO_GPDQSEL2_GPIO125_S 26U +#define GPIO_GPDQSEL2_GPIO125_M 0xC000000U // Select input qualification type for GPIO125 +#define GPIO_GPDQSEL2_GPIO126_S 28U +#define GPIO_GPDQSEL2_GPIO126_M 0x30000000U // Select input qualification type for GPIO126 +#define GPIO_GPDQSEL2_GPIO127_S 30U +#define GPIO_GPDQSEL2_GPIO127_M 0xC0000000U // Select input qualification type for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDMUX1_GPIO96_S 0U +#define GPIO_GPDMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDMUX1_GPIO97_S 2U +#define GPIO_GPDMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDMUX1_GPIO98_S 4U +#define GPIO_GPDMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDMUX1_GPIO99_S 6U +#define GPIO_GPDMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDMUX1_GPIO100_S 8U +#define GPIO_GPDMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDMUX1_GPIO101_S 10U +#define GPIO_GPDMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDMUX1_GPIO102_S 12U +#define GPIO_GPDMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDMUX1_GPIO103_S 14U +#define GPIO_GPDMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDMUX1_GPIO104_S 16U +#define GPIO_GPDMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDMUX1_GPIO105_S 18U +#define GPIO_GPDMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDMUX1_GPIO106_S 20U +#define GPIO_GPDMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDMUX1_GPIO107_S 22U +#define GPIO_GPDMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDMUX1_GPIO108_S 24U +#define GPIO_GPDMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDMUX1_GPIO109_S 26U +#define GPIO_GPDMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDMUX1_GPIO110_S 28U +#define GPIO_GPDMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDMUX1_GPIO111_S 30U +#define GPIO_GPDMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDMUX2_GPIO112_S 0U +#define GPIO_GPDMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDMUX2_GPIO113_S 2U +#define GPIO_GPDMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDMUX2_GPIO114_S 4U +#define GPIO_GPDMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDMUX2_GPIO115_S 6U +#define GPIO_GPDMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDMUX2_GPIO116_S 8U +#define GPIO_GPDMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDMUX2_GPIO117_S 10U +#define GPIO_GPDMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDMUX2_GPIO118_S 12U +#define GPIO_GPDMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDMUX2_GPIO119_S 14U +#define GPIO_GPDMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDMUX2_GPIO120_S 16U +#define GPIO_GPDMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDMUX2_GPIO121_S 18U +#define GPIO_GPDMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDMUX2_GPIO122_S 20U +#define GPIO_GPDMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDMUX2_GPIO123_S 22U +#define GPIO_GPDMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDMUX2_GPIO124_S 24U +#define GPIO_GPDMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDMUX2_GPIO125_S 26U +#define GPIO_GPDMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDMUX2_GPIO126_S 28U +#define GPIO_GPDMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDMUX2_GPIO127_S 30U +#define GPIO_GPDMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDIR register +// +//************************************************************************************************* +#define GPIO_GPDDIR_GPIO96 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO97 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO98 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO99 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO100 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO101 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO102 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO103 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO104 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO105 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO106 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO107 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO108 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO109 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO110 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO111 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO112 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO113 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO114 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO115 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO116 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO117 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO118 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO119 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO120 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO121 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO122 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO123 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO124 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO125 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO126 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO127 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDPUD register +// +//************************************************************************************************* +#define GPIO_GPDPUD_GPIO96 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO97 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO98 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO99 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO100 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO101 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO102 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO103 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO104 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO105 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO106 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO107 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO108 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO109 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO110 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO111 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO112 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO113 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO114 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO115 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO116 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO117 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO118 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO119 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO120 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO121 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO122 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO123 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO124 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO125 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO126 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO127 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDINV register +// +//************************************************************************************************* +#define GPIO_GPDINV_GPIO96 0x1U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO97 0x2U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO98 0x4U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO99 0x8U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO100 0x10U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO101 0x20U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO102 0x40U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO103 0x80U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO104 0x100U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO105 0x200U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO106 0x400U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO107 0x800U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO108 0x1000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO109 0x2000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO110 0x4000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO111 0x8000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO112 0x10000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO113 0x20000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO114 0x40000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO115 0x80000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO116 0x100000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO117 0x200000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO118 0x400000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO119 0x800000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO120 0x1000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO121 0x2000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO122 0x4000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO123 0x8000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO124 0x10000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO125 0x20000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO126 0x40000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO127 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDODR register +// +//************************************************************************************************* +#define GPIO_GPDODR_GPIO96 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO97 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO98 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO99 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO100 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO101 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO102 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO103 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO104 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO105 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO106 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO107 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO108 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO109 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO110 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO111 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO112 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO113 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO114 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO115 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO116 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO117 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO118 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO119 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO120 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO121 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO122 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO123 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO124 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO125 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO126 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO127 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX1_GPIO96_S 0U +#define GPIO_GPDGMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDGMUX1_GPIO97_S 2U +#define GPIO_GPDGMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDGMUX1_GPIO98_S 4U +#define GPIO_GPDGMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDGMUX1_GPIO99_S 6U +#define GPIO_GPDGMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDGMUX1_GPIO100_S 8U +#define GPIO_GPDGMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDGMUX1_GPIO101_S 10U +#define GPIO_GPDGMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDGMUX1_GPIO102_S 12U +#define GPIO_GPDGMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDGMUX1_GPIO103_S 14U +#define GPIO_GPDGMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDGMUX1_GPIO104_S 16U +#define GPIO_GPDGMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDGMUX1_GPIO105_S 18U +#define GPIO_GPDGMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDGMUX1_GPIO106_S 20U +#define GPIO_GPDGMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDGMUX1_GPIO107_S 22U +#define GPIO_GPDGMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDGMUX1_GPIO108_S 24U +#define GPIO_GPDGMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDGMUX1_GPIO109_S 26U +#define GPIO_GPDGMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDGMUX1_GPIO110_S 28U +#define GPIO_GPDGMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDGMUX1_GPIO111_S 30U +#define GPIO_GPDGMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX2_GPIO112_S 0U +#define GPIO_GPDGMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDGMUX2_GPIO113_S 2U +#define GPIO_GPDGMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDGMUX2_GPIO114_S 4U +#define GPIO_GPDGMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDGMUX2_GPIO115_S 6U +#define GPIO_GPDGMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDGMUX2_GPIO116_S 8U +#define GPIO_GPDGMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDGMUX2_GPIO117_S 10U +#define GPIO_GPDGMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDGMUX2_GPIO118_S 12U +#define GPIO_GPDGMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDGMUX2_GPIO119_S 14U +#define GPIO_GPDGMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDGMUX2_GPIO120_S 16U +#define GPIO_GPDGMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDGMUX2_GPIO121_S 18U +#define GPIO_GPDGMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDGMUX2_GPIO122_S 20U +#define GPIO_GPDGMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDGMUX2_GPIO123_S 22U +#define GPIO_GPDGMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDGMUX2_GPIO124_S 24U +#define GPIO_GPDGMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDGMUX2_GPIO125_S 26U +#define GPIO_GPDGMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDGMUX2_GPIO126_S 28U +#define GPIO_GPDGMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDGMUX2_GPIO127_S 30U +#define GPIO_GPDGMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL1_GPIO96_S 0U +#define GPIO_GPDCSEL1_GPIO96_M 0xFU // GPIO96 Master CPU Select +#define GPIO_GPDCSEL1_GPIO97_S 4U +#define GPIO_GPDCSEL1_GPIO97_M 0xF0U // GPIO97 Master CPU Select +#define GPIO_GPDCSEL1_GPIO98_S 8U +#define GPIO_GPDCSEL1_GPIO98_M 0xF00U // GPIO98 Master CPU Select +#define GPIO_GPDCSEL1_GPIO99_S 12U +#define GPIO_GPDCSEL1_GPIO99_M 0xF000U // GPIO99 Master CPU Select +#define GPIO_GPDCSEL1_GPIO100_S 16U +#define GPIO_GPDCSEL1_GPIO100_M 0xF0000U // GPIO100 Master CPU Select +#define GPIO_GPDCSEL1_GPIO101_S 20U +#define GPIO_GPDCSEL1_GPIO101_M 0xF00000U // GPIO101 Master CPU Select +#define GPIO_GPDCSEL1_GPIO102_S 24U +#define GPIO_GPDCSEL1_GPIO102_M 0xF000000U // GPIO102 Master CPU Select +#define GPIO_GPDCSEL1_GPIO103_S 28U +#define GPIO_GPDCSEL1_GPIO103_M 0xF0000000U // GPIO103 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL2_GPIO104_S 0U +#define GPIO_GPDCSEL2_GPIO104_M 0xFU // GPIO104 Master CPU Select +#define GPIO_GPDCSEL2_GPIO105_S 4U +#define GPIO_GPDCSEL2_GPIO105_M 0xF0U // GPIO105 Master CPU Select +#define GPIO_GPDCSEL2_GPIO106_S 8U +#define GPIO_GPDCSEL2_GPIO106_M 0xF00U // GPIO106 Master CPU Select +#define GPIO_GPDCSEL2_GPIO107_S 12U +#define GPIO_GPDCSEL2_GPIO107_M 0xF000U // GPIO107 Master CPU Select +#define GPIO_GPDCSEL2_GPIO108_S 16U +#define GPIO_GPDCSEL2_GPIO108_M 0xF0000U // GPIO108 Master CPU Select +#define GPIO_GPDCSEL2_GPIO109_S 20U +#define GPIO_GPDCSEL2_GPIO109_M 0xF00000U // GPIO109 Master CPU Select +#define GPIO_GPDCSEL2_GPIO110_S 24U +#define GPIO_GPDCSEL2_GPIO110_M 0xF000000U // GPIO110 Master CPU Select +#define GPIO_GPDCSEL2_GPIO111_S 28U +#define GPIO_GPDCSEL2_GPIO111_M 0xF0000000U // GPIO111 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL3_GPIO112_S 0U +#define GPIO_GPDCSEL3_GPIO112_M 0xFU // GPIO112 Master CPU Select +#define GPIO_GPDCSEL3_GPIO113_S 4U +#define GPIO_GPDCSEL3_GPIO113_M 0xF0U // GPIO113 Master CPU Select +#define GPIO_GPDCSEL3_GPIO114_S 8U +#define GPIO_GPDCSEL3_GPIO114_M 0xF00U // GPIO114 Master CPU Select +#define GPIO_GPDCSEL3_GPIO115_S 12U +#define GPIO_GPDCSEL3_GPIO115_M 0xF000U // GPIO115 Master CPU Select +#define GPIO_GPDCSEL3_GPIO116_S 16U +#define GPIO_GPDCSEL3_GPIO116_M 0xF0000U // GPIO116 Master CPU Select +#define GPIO_GPDCSEL3_GPIO117_S 20U +#define GPIO_GPDCSEL3_GPIO117_M 0xF00000U // GPIO117 Master CPU Select +#define GPIO_GPDCSEL3_GPIO118_S 24U +#define GPIO_GPDCSEL3_GPIO118_M 0xF000000U // GPIO118 Master CPU Select +#define GPIO_GPDCSEL3_GPIO119_S 28U +#define GPIO_GPDCSEL3_GPIO119_M 0xF0000000U // GPIO119 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL4_GPIO120_S 0U +#define GPIO_GPDCSEL4_GPIO120_M 0xFU // GPIO120 Master CPU Select +#define GPIO_GPDCSEL4_GPIO121_S 4U +#define GPIO_GPDCSEL4_GPIO121_M 0xF0U // GPIO121 Master CPU Select +#define GPIO_GPDCSEL4_GPIO122_S 8U +#define GPIO_GPDCSEL4_GPIO122_M 0xF00U // GPIO122 Master CPU Select +#define GPIO_GPDCSEL4_GPIO123_S 12U +#define GPIO_GPDCSEL4_GPIO123_M 0xF000U // GPIO123 Master CPU Select +#define GPIO_GPDCSEL4_GPIO124_S 16U +#define GPIO_GPDCSEL4_GPIO124_M 0xF0000U // GPIO124 Master CPU Select +#define GPIO_GPDCSEL4_GPIO125_S 20U +#define GPIO_GPDCSEL4_GPIO125_M 0xF00000U // GPIO125 Master CPU Select +#define GPIO_GPDCSEL4_GPIO126_S 24U +#define GPIO_GPDCSEL4_GPIO126_M 0xF000000U // GPIO126 Master CPU Select +#define GPIO_GPDCSEL4_GPIO127_S 28U +#define GPIO_GPDCSEL4_GPIO127_M 0xF0000000U // GPIO127 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDLOCK register +// +//************************************************************************************************* +#define GPIO_GPDLOCK_GPIO96 0x1U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO97 0x2U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO98 0x4U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO99 0x8U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO100 0x10U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO101 0x20U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO102 0x40U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO103 0x80U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO104 0x100U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO105 0x200U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO106 0x400U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO107 0x800U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO108 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO109 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO110 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO111 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO112 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO113 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO114 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO115 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO116 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO117 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO118 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO119 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO120 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO121 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO122 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO123 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO124 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO125 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO126 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO127 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCR register +// +//************************************************************************************************* +#define GPIO_GPDCR_GPIO96 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO97 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO98 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO99 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO100 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO101 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO102 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO103 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO104 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO105 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO106 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO107 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO108 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO109 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO110 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO111 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO112 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO113 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO114 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO115 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO116 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO117 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO118 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO119 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO120 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO121 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO122 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO123 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO124 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO125 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO126 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO127 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECTRL register +// +//************************************************************************************************* +#define GPIO_GPECTRL_QUALPRD0_S 0U +#define GPIO_GPECTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO128 to + // GPIO135 +#define GPIO_GPECTRL_QUALPRD1_S 8U +#define GPIO_GPECTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO136 to + // GPIO143 +#define GPIO_GPECTRL_QUALPRD2_S 16U +#define GPIO_GPECTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO144 to + // GPIO151 +#define GPIO_GPECTRL_QUALPRD3_S 24U +#define GPIO_GPECTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO152 to + // GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL1_GPIO128_S 0U +#define GPIO_GPEQSEL1_GPIO128_M 0x3U // Select input qualification type for GPIO128 +#define GPIO_GPEQSEL1_GPIO129_S 2U +#define GPIO_GPEQSEL1_GPIO129_M 0xCU // Select input qualification type for GPIO129 +#define GPIO_GPEQSEL1_GPIO130_S 4U +#define GPIO_GPEQSEL1_GPIO130_M 0x30U // Select input qualification type for GPIO130 +#define GPIO_GPEQSEL1_GPIO131_S 6U +#define GPIO_GPEQSEL1_GPIO131_M 0xC0U // Select input qualification type for GPIO131 +#define GPIO_GPEQSEL1_GPIO132_S 8U +#define GPIO_GPEQSEL1_GPIO132_M 0x300U // Select input qualification type for GPIO132 +#define GPIO_GPEQSEL1_GPIO133_S 10U +#define GPIO_GPEQSEL1_GPIO133_M 0xC00U // Select input qualification type for GPIO133 +#define GPIO_GPEQSEL1_GPIO134_S 12U +#define GPIO_GPEQSEL1_GPIO134_M 0x3000U // Select input qualification type for GPIO134 +#define GPIO_GPEQSEL1_GPIO135_S 14U +#define GPIO_GPEQSEL1_GPIO135_M 0xC000U // Select input qualification type for GPIO135 +#define GPIO_GPEQSEL1_GPIO136_S 16U +#define GPIO_GPEQSEL1_GPIO136_M 0x30000U // Select input qualification type for GPIO136 +#define GPIO_GPEQSEL1_GPIO137_S 18U +#define GPIO_GPEQSEL1_GPIO137_M 0xC0000U // Select input qualification type for GPIO137 +#define GPIO_GPEQSEL1_GPIO138_S 20U +#define GPIO_GPEQSEL1_GPIO138_M 0x300000U // Select input qualification type for GPIO138 +#define GPIO_GPEQSEL1_GPIO139_S 22U +#define GPIO_GPEQSEL1_GPIO139_M 0xC00000U // Select input qualification type for GPIO139 +#define GPIO_GPEQSEL1_GPIO140_S 24U +#define GPIO_GPEQSEL1_GPIO140_M 0x3000000U // Select input qualification type for GPIO140 +#define GPIO_GPEQSEL1_GPIO141_S 26U +#define GPIO_GPEQSEL1_GPIO141_M 0xC000000U // Select input qualification type for GPIO141 +#define GPIO_GPEQSEL1_GPIO142_S 28U +#define GPIO_GPEQSEL1_GPIO142_M 0x30000000U // Select input qualification type for GPIO142 +#define GPIO_GPEQSEL1_GPIO143_S 30U +#define GPIO_GPEQSEL1_GPIO143_M 0xC0000000U // Select input qualification type for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL2_GPIO144_S 0U +#define GPIO_GPEQSEL2_GPIO144_M 0x3U // Select input qualification type for GPIO144 +#define GPIO_GPEQSEL2_GPIO145_S 2U +#define GPIO_GPEQSEL2_GPIO145_M 0xCU // Select input qualification type for GPIO145 +#define GPIO_GPEQSEL2_GPIO146_S 4U +#define GPIO_GPEQSEL2_GPIO146_M 0x30U // Select input qualification type for GPIO146 +#define GPIO_GPEQSEL2_GPIO147_S 6U +#define GPIO_GPEQSEL2_GPIO147_M 0xC0U // Select input qualification type for GPIO147 +#define GPIO_GPEQSEL2_GPIO148_S 8U +#define GPIO_GPEQSEL2_GPIO148_M 0x300U // Select input qualification type for GPIO148 +#define GPIO_GPEQSEL2_GPIO149_S 10U +#define GPIO_GPEQSEL2_GPIO149_M 0xC00U // Select input qualification type for GPIO149 +#define GPIO_GPEQSEL2_GPIO150_S 12U +#define GPIO_GPEQSEL2_GPIO150_M 0x3000U // Select input qualification type for GPIO150 +#define GPIO_GPEQSEL2_GPIO151_S 14U +#define GPIO_GPEQSEL2_GPIO151_M 0xC000U // Select input qualification type for GPIO151 +#define GPIO_GPEQSEL2_GPIO152_S 16U +#define GPIO_GPEQSEL2_GPIO152_M 0x30000U // Select input qualification type for GPIO152 +#define GPIO_GPEQSEL2_GPIO153_S 18U +#define GPIO_GPEQSEL2_GPIO153_M 0xC0000U // Select input qualification type for GPIO153 +#define GPIO_GPEQSEL2_GPIO154_S 20U +#define GPIO_GPEQSEL2_GPIO154_M 0x300000U // Select input qualification type for GPIO154 +#define GPIO_GPEQSEL2_GPIO155_S 22U +#define GPIO_GPEQSEL2_GPIO155_M 0xC00000U // Select input qualification type for GPIO155 +#define GPIO_GPEQSEL2_GPIO156_S 24U +#define GPIO_GPEQSEL2_GPIO156_M 0x3000000U // Select input qualification type for GPIO156 +#define GPIO_GPEQSEL2_GPIO157_S 26U +#define GPIO_GPEQSEL2_GPIO157_M 0xC000000U // Select input qualification type for GPIO157 +#define GPIO_GPEQSEL2_GPIO158_S 28U +#define GPIO_GPEQSEL2_GPIO158_M 0x30000000U // Select input qualification type for GPIO158 +#define GPIO_GPEQSEL2_GPIO159_S 30U +#define GPIO_GPEQSEL2_GPIO159_M 0xC0000000U // Select input qualification type for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEMUX1_GPIO128_S 0U +#define GPIO_GPEMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEMUX1_GPIO129_S 2U +#define GPIO_GPEMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEMUX1_GPIO130_S 4U +#define GPIO_GPEMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEMUX1_GPIO131_S 6U +#define GPIO_GPEMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEMUX1_GPIO132_S 8U +#define GPIO_GPEMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEMUX1_GPIO133_S 10U +#define GPIO_GPEMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEMUX1_GPIO134_S 12U +#define GPIO_GPEMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEMUX1_GPIO135_S 14U +#define GPIO_GPEMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEMUX1_GPIO136_S 16U +#define GPIO_GPEMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEMUX1_GPIO137_S 18U +#define GPIO_GPEMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEMUX1_GPIO138_S 20U +#define GPIO_GPEMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEMUX1_GPIO139_S 22U +#define GPIO_GPEMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEMUX1_GPIO140_S 24U +#define GPIO_GPEMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEMUX1_GPIO141_S 26U +#define GPIO_GPEMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEMUX1_GPIO142_S 28U +#define GPIO_GPEMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEMUX1_GPIO143_S 30U +#define GPIO_GPEMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEMUX2_GPIO144_S 0U +#define GPIO_GPEMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEMUX2_GPIO145_S 2U +#define GPIO_GPEMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEMUX2_GPIO146_S 4U +#define GPIO_GPEMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEMUX2_GPIO147_S 6U +#define GPIO_GPEMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEMUX2_GPIO148_S 8U +#define GPIO_GPEMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEMUX2_GPIO149_S 10U +#define GPIO_GPEMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEMUX2_GPIO150_S 12U +#define GPIO_GPEMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEMUX2_GPIO151_S 14U +#define GPIO_GPEMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEMUX2_GPIO152_S 16U +#define GPIO_GPEMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEMUX2_GPIO153_S 18U +#define GPIO_GPEMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEMUX2_GPIO154_S 20U +#define GPIO_GPEMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEMUX2_GPIO155_S 22U +#define GPIO_GPEMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEMUX2_GPIO156_S 24U +#define GPIO_GPEMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEMUX2_GPIO157_S 26U +#define GPIO_GPEMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEMUX2_GPIO158_S 28U +#define GPIO_GPEMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEMUX2_GPIO159_S 30U +#define GPIO_GPEMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDIR register +// +//************************************************************************************************* +#define GPIO_GPEDIR_GPIO128 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO129 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO130 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO131 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO132 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO133 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO134 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO135 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO136 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO137 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO138 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO139 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO140 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO141 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO142 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO143 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO144 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO145 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO146 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO147 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO148 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO149 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO150 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO151 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO152 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO153 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO154 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO155 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO156 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO157 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO158 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO159 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEPUD register +// +//************************************************************************************************* +#define GPIO_GPEPUD_GPIO128 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO129 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO130 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO131 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO132 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO133 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO134 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO135 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO136 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO137 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO138 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO139 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO140 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO141 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO142 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO143 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO144 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO145 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO146 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO147 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO148 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO149 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO150 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO151 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO152 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO153 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO154 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO155 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO156 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO157 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO158 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO159 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEINV register +// +//************************************************************************************************* +#define GPIO_GPEINV_GPIO128 0x1U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO129 0x2U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO130 0x4U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO131 0x8U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO132 0x10U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO133 0x20U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO134 0x40U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO135 0x80U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO136 0x100U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO137 0x200U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO138 0x400U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO139 0x800U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO140 0x1000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO141 0x2000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO142 0x4000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO143 0x8000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO144 0x10000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO145 0x20000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO146 0x40000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO147 0x80000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO148 0x100000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO149 0x200000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO150 0x400000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO151 0x800000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO152 0x1000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO153 0x2000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO154 0x4000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO155 0x8000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO156 0x10000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO157 0x20000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO158 0x40000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO159 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEODR register +// +//************************************************************************************************* +#define GPIO_GPEODR_GPIO128 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO129 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO130 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO131 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO132 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO133 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO134 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO135 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO136 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO137 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO138 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO139 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO140 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO141 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO142 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO143 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO144 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO145 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO146 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO147 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO148 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO149 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO150 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO151 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO152 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO153 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO154 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO155 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO156 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO157 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO158 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO159 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX1_GPIO128_S 0U +#define GPIO_GPEGMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEGMUX1_GPIO129_S 2U +#define GPIO_GPEGMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEGMUX1_GPIO130_S 4U +#define GPIO_GPEGMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEGMUX1_GPIO131_S 6U +#define GPIO_GPEGMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEGMUX1_GPIO132_S 8U +#define GPIO_GPEGMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEGMUX1_GPIO133_S 10U +#define GPIO_GPEGMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEGMUX1_GPIO134_S 12U +#define GPIO_GPEGMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEGMUX1_GPIO135_S 14U +#define GPIO_GPEGMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEGMUX1_GPIO136_S 16U +#define GPIO_GPEGMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEGMUX1_GPIO137_S 18U +#define GPIO_GPEGMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEGMUX1_GPIO138_S 20U +#define GPIO_GPEGMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEGMUX1_GPIO139_S 22U +#define GPIO_GPEGMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEGMUX1_GPIO140_S 24U +#define GPIO_GPEGMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEGMUX1_GPIO141_S 26U +#define GPIO_GPEGMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEGMUX1_GPIO142_S 28U +#define GPIO_GPEGMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEGMUX1_GPIO143_S 30U +#define GPIO_GPEGMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX2_GPIO144_S 0U +#define GPIO_GPEGMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEGMUX2_GPIO145_S 2U +#define GPIO_GPEGMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEGMUX2_GPIO146_S 4U +#define GPIO_GPEGMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEGMUX2_GPIO147_S 6U +#define GPIO_GPEGMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEGMUX2_GPIO148_S 8U +#define GPIO_GPEGMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEGMUX2_GPIO149_S 10U +#define GPIO_GPEGMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEGMUX2_GPIO150_S 12U +#define GPIO_GPEGMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEGMUX2_GPIO151_S 14U +#define GPIO_GPEGMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEGMUX2_GPIO152_S 16U +#define GPIO_GPEGMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEGMUX2_GPIO153_S 18U +#define GPIO_GPEGMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEGMUX2_GPIO154_S 20U +#define GPIO_GPEGMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEGMUX2_GPIO155_S 22U +#define GPIO_GPEGMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEGMUX2_GPIO156_S 24U +#define GPIO_GPEGMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEGMUX2_GPIO157_S 26U +#define GPIO_GPEGMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEGMUX2_GPIO158_S 28U +#define GPIO_GPEGMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEGMUX2_GPIO159_S 30U +#define GPIO_GPEGMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL1 register +// +//************************************************************************************************* +#define GPIO_GPECSEL1_GPIO128_S 0U +#define GPIO_GPECSEL1_GPIO128_M 0xFU // GPIO128 Master CPU Select +#define GPIO_GPECSEL1_GPIO129_S 4U +#define GPIO_GPECSEL1_GPIO129_M 0xF0U // GPIO129 Master CPU Select +#define GPIO_GPECSEL1_GPIO130_S 8U +#define GPIO_GPECSEL1_GPIO130_M 0xF00U // GPIO130 Master CPU Select +#define GPIO_GPECSEL1_GPIO131_S 12U +#define GPIO_GPECSEL1_GPIO131_M 0xF000U // GPIO131 Master CPU Select +#define GPIO_GPECSEL1_GPIO132_S 16U +#define GPIO_GPECSEL1_GPIO132_M 0xF0000U // GPIO132 Master CPU Select +#define GPIO_GPECSEL1_GPIO133_S 20U +#define GPIO_GPECSEL1_GPIO133_M 0xF00000U // GPIO133 Master CPU Select +#define GPIO_GPECSEL1_GPIO134_S 24U +#define GPIO_GPECSEL1_GPIO134_M 0xF000000U // GPIO134 Master CPU Select +#define GPIO_GPECSEL1_GPIO135_S 28U +#define GPIO_GPECSEL1_GPIO135_M 0xF0000000U // GPIO135 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL2 register +// +//************************************************************************************************* +#define GPIO_GPECSEL2_GPIO136_S 0U +#define GPIO_GPECSEL2_GPIO136_M 0xFU // GPIO136 Master CPU Select +#define GPIO_GPECSEL2_GPIO137_S 4U +#define GPIO_GPECSEL2_GPIO137_M 0xF0U // GPIO137 Master CPU Select +#define GPIO_GPECSEL2_GPIO138_S 8U +#define GPIO_GPECSEL2_GPIO138_M 0xF00U // GPIO138 Master CPU Select +#define GPIO_GPECSEL2_GPIO139_S 12U +#define GPIO_GPECSEL2_GPIO139_M 0xF000U // GPIO139 Master CPU Select +#define GPIO_GPECSEL2_GPIO140_S 16U +#define GPIO_GPECSEL2_GPIO140_M 0xF0000U // GPIO140 Master CPU Select +#define GPIO_GPECSEL2_GPIO141_S 20U +#define GPIO_GPECSEL2_GPIO141_M 0xF00000U // GPIO141 Master CPU Select +#define GPIO_GPECSEL2_GPIO142_S 24U +#define GPIO_GPECSEL2_GPIO142_M 0xF000000U // GPIO142 Master CPU Select +#define GPIO_GPECSEL2_GPIO143_S 28U +#define GPIO_GPECSEL2_GPIO143_M 0xF0000000U // GPIO143 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL3 register +// +//************************************************************************************************* +#define GPIO_GPECSEL3_GPIO144_S 0U +#define GPIO_GPECSEL3_GPIO144_M 0xFU // GPIO144 Master CPU Select +#define GPIO_GPECSEL3_GPIO145_S 4U +#define GPIO_GPECSEL3_GPIO145_M 0xF0U // GPIO145 Master CPU Select +#define GPIO_GPECSEL3_GPIO146_S 8U +#define GPIO_GPECSEL3_GPIO146_M 0xF00U // GPIO146 Master CPU Select +#define GPIO_GPECSEL3_GPIO147_S 12U +#define GPIO_GPECSEL3_GPIO147_M 0xF000U // GPIO147 Master CPU Select +#define GPIO_GPECSEL3_GPIO148_S 16U +#define GPIO_GPECSEL3_GPIO148_M 0xF0000U // GPIO148 Master CPU Select +#define GPIO_GPECSEL3_GPIO149_S 20U +#define GPIO_GPECSEL3_GPIO149_M 0xF00000U // GPIO149 Master CPU Select +#define GPIO_GPECSEL3_GPIO150_S 24U +#define GPIO_GPECSEL3_GPIO150_M 0xF000000U // GPIO150 Master CPU Select +#define GPIO_GPECSEL3_GPIO151_S 28U +#define GPIO_GPECSEL3_GPIO151_M 0xF0000000U // GPIO151 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL4 register +// +//************************************************************************************************* +#define GPIO_GPECSEL4_GPIO152_S 0U +#define GPIO_GPECSEL4_GPIO152_M 0xFU // GPIO152 Master CPU Select +#define GPIO_GPECSEL4_GPIO153_S 4U +#define GPIO_GPECSEL4_GPIO153_M 0xF0U // GPIO153 Master CPU Select +#define GPIO_GPECSEL4_GPIO154_S 8U +#define GPIO_GPECSEL4_GPIO154_M 0xF00U // GPIO154 Master CPU Select +#define GPIO_GPECSEL4_GPIO155_S 12U +#define GPIO_GPECSEL4_GPIO155_M 0xF000U // GPIO155 Master CPU Select +#define GPIO_GPECSEL4_GPIO156_S 16U +#define GPIO_GPECSEL4_GPIO156_M 0xF0000U // GPIO156 Master CPU Select +#define GPIO_GPECSEL4_GPIO157_S 20U +#define GPIO_GPECSEL4_GPIO157_M 0xF00000U // GPIO157 Master CPU Select +#define GPIO_GPECSEL4_GPIO158_S 24U +#define GPIO_GPECSEL4_GPIO158_M 0xF000000U // GPIO158 Master CPU Select +#define GPIO_GPECSEL4_GPIO159_S 28U +#define GPIO_GPECSEL4_GPIO159_M 0xF0000000U // GPIO159 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPELOCK register +// +//************************************************************************************************* +#define GPIO_GPELOCK_GPIO128 0x1U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO129 0x2U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO130 0x4U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO131 0x8U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO132 0x10U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO133 0x20U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO134 0x40U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO135 0x80U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO136 0x100U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO137 0x200U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO138 0x400U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO139 0x800U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO140 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO141 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO142 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO143 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO144 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO145 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO146 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO147 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO148 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO149 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO150 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO151 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO152 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO153 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO154 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO155 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO156 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO157 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO158 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO159 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECR register +// +//************************************************************************************************* +#define GPIO_GPECR_GPIO128 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO129 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO130 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO131 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO132 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO133 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO134 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO135 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO136 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO137 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO138 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO139 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO140 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO141 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO142 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO143 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO144 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO145 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO146 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO147 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO148 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO149 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO150 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO151 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO152 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO153 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO154 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO155 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO156 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO157 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO158 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO159 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCTRL register +// +//************************************************************************************************* +#define GPIO_GPFCTRL_QUALPRD0_S 0U +#define GPIO_GPFCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO160 to GPIO167 +#define GPIO_GPFCTRL_QUALPRD1_S 8U +#define GPIO_GPFCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFQSEL1_GPIO160_S 0U +#define GPIO_GPFQSEL1_GPIO160_M 0x3U // Select input qualification type for GPIO160 +#define GPIO_GPFQSEL1_GPIO161_S 2U +#define GPIO_GPFQSEL1_GPIO161_M 0xCU // Select input qualification type for GPIO161 +#define GPIO_GPFQSEL1_GPIO162_S 4U +#define GPIO_GPFQSEL1_GPIO162_M 0x30U // Select input qualification type for GPIO162 +#define GPIO_GPFQSEL1_GPIO163_S 6U +#define GPIO_GPFQSEL1_GPIO163_M 0xC0U // Select input qualification type for GPIO163 +#define GPIO_GPFQSEL1_GPIO164_S 8U +#define GPIO_GPFQSEL1_GPIO164_M 0x300U // Select input qualification type for GPIO164 +#define GPIO_GPFQSEL1_GPIO165_S 10U +#define GPIO_GPFQSEL1_GPIO165_M 0xC00U // Select input qualification type for GPIO165 +#define GPIO_GPFQSEL1_GPIO166_S 12U +#define GPIO_GPFQSEL1_GPIO166_M 0x3000U // Select input qualification type for GPIO166 +#define GPIO_GPFQSEL1_GPIO167_S 14U +#define GPIO_GPFQSEL1_GPIO167_M 0xC000U // Select input qualification type for GPIO167 +#define GPIO_GPFQSEL1_GPIO168_S 16U +#define GPIO_GPFQSEL1_GPIO168_M 0x30000U // Select input qualification type for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFMUX1_GPIO160_S 0U +#define GPIO_GPFMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFMUX1_GPIO161_S 2U +#define GPIO_GPFMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFMUX1_GPIO162_S 4U +#define GPIO_GPFMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFMUX1_GPIO163_S 6U +#define GPIO_GPFMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFMUX1_GPIO164_S 8U +#define GPIO_GPFMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFMUX1_GPIO165_S 10U +#define GPIO_GPFMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFMUX1_GPIO166_S 12U +#define GPIO_GPFMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFMUX1_GPIO167_S 14U +#define GPIO_GPFMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFMUX1_GPIO168_S 16U +#define GPIO_GPFMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDIR register +// +//************************************************************************************************* +#define GPIO_GPFDIR_GPIO160 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO161 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO162 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO163 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO164 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO165 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO166 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO167 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO168 0x100U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFPUD register +// +//************************************************************************************************* +#define GPIO_GPFPUD_GPIO160 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO161 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO162 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO163 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO164 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO165 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO166 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO167 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO168 0x100U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFINV register +// +//************************************************************************************************* +#define GPIO_GPFINV_GPIO160 0x1U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO161 0x2U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO162 0x4U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO163 0x8U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO164 0x10U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO165 0x20U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO166 0x40U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO167 0x80U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO168 0x100U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFODR register +// +//************************************************************************************************* +#define GPIO_GPFODR_GPIO160 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO161 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO162 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO163 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO164 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO165 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO166 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO167 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO168 0x100U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFGMUX1_GPIO160_S 0U +#define GPIO_GPFGMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFGMUX1_GPIO161_S 2U +#define GPIO_GPFGMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFGMUX1_GPIO162_S 4U +#define GPIO_GPFGMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFGMUX1_GPIO163_S 6U +#define GPIO_GPFGMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFGMUX1_GPIO164_S 8U +#define GPIO_GPFGMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFGMUX1_GPIO165_S 10U +#define GPIO_GPFGMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFGMUX1_GPIO166_S 12U +#define GPIO_GPFGMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFGMUX1_GPIO167_S 14U +#define GPIO_GPFGMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFGMUX1_GPIO168_S 16U +#define GPIO_GPFGMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL1_GPIO160_S 0U +#define GPIO_GPFCSEL1_GPIO160_M 0xFU // GPIO160 Master CPU Select +#define GPIO_GPFCSEL1_GPIO161_S 4U +#define GPIO_GPFCSEL1_GPIO161_M 0xF0U // GPIO161 Master CPU Select +#define GPIO_GPFCSEL1_GPIO162_S 8U +#define GPIO_GPFCSEL1_GPIO162_M 0xF00U // GPIO162 Master CPU Select +#define GPIO_GPFCSEL1_GPIO163_S 12U +#define GPIO_GPFCSEL1_GPIO163_M 0xF000U // GPIO163 Master CPU Select +#define GPIO_GPFCSEL1_GPIO164_S 16U +#define GPIO_GPFCSEL1_GPIO164_M 0xF0000U // GPIO164 Master CPU Select +#define GPIO_GPFCSEL1_GPIO165_S 20U +#define GPIO_GPFCSEL1_GPIO165_M 0xF00000U // GPIO165 Master CPU Select +#define GPIO_GPFCSEL1_GPIO166_S 24U +#define GPIO_GPFCSEL1_GPIO166_M 0xF000000U // GPIO166 Master CPU Select +#define GPIO_GPFCSEL1_GPIO167_S 28U +#define GPIO_GPFCSEL1_GPIO167_M 0xF0000000U // GPIO167 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL2_GPIO168_S 0U +#define GPIO_GPFCSEL2_GPIO168_M 0xFU // GPIO168 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFLOCK register +// +//************************************************************************************************* +#define GPIO_GPFLOCK_GPIO160 0x1U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO161 0x2U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO162 0x4U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO163 0x8U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO164 0x10U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO165 0x20U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO166 0x40U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO167 0x80U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO168 0x100U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCR register +// +//************************************************************************************************* +#define GPIO_GPFCR_GPIO160 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO161 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO162 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO163 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO164 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO165 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO166 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO167 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO168 0x100U // Configuration lock commit bit for this pin + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADAT register +// +//************************************************************************************************* +#define GPIO_GPADAT_GPIO0 0x1U // Data Register for this pin +#define GPIO_GPADAT_GPIO1 0x2U // Data Register for this pin +#define GPIO_GPADAT_GPIO2 0x4U // Data Register for this pin +#define GPIO_GPADAT_GPIO3 0x8U // Data Register for this pin +#define GPIO_GPADAT_GPIO4 0x10U // Data Register for this pin +#define GPIO_GPADAT_GPIO5 0x20U // Data Register for this pin +#define GPIO_GPADAT_GPIO6 0x40U // Data Register for this pin +#define GPIO_GPADAT_GPIO7 0x80U // Data Register for this pin +#define GPIO_GPADAT_GPIO8 0x100U // Data Register for this pin +#define GPIO_GPADAT_GPIO9 0x200U // Data Register for this pin +#define GPIO_GPADAT_GPIO10 0x400U // Data Register for this pin +#define GPIO_GPADAT_GPIO11 0x800U // Data Register for this pin +#define GPIO_GPADAT_GPIO12 0x1000U // Data Register for this pin +#define GPIO_GPADAT_GPIO13 0x2000U // Data Register for this pin +#define GPIO_GPADAT_GPIO14 0x4000U // Data Register for this pin +#define GPIO_GPADAT_GPIO15 0x8000U // Data Register for this pin +#define GPIO_GPADAT_GPIO16 0x10000U // Data Register for this pin +#define GPIO_GPADAT_GPIO17 0x20000U // Data Register for this pin +#define GPIO_GPADAT_GPIO18 0x40000U // Data Register for this pin +#define GPIO_GPADAT_GPIO19 0x80000U // Data Register for this pin +#define GPIO_GPADAT_GPIO20 0x100000U // Data Register for this pin +#define GPIO_GPADAT_GPIO21 0x200000U // Data Register for this pin +#define GPIO_GPADAT_GPIO22 0x400000U // Data Register for this pin +#define GPIO_GPADAT_GPIO23 0x800000U // Data Register for this pin +#define GPIO_GPADAT_GPIO24 0x1000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO25 0x2000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO26 0x4000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO27 0x8000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO28 0x10000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO29 0x20000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO30 0x40000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO31 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPASET register +// +//************************************************************************************************* +#define GPIO_GPASET_GPIO0 0x1U // Output Set bit for this pin +#define GPIO_GPASET_GPIO1 0x2U // Output Set bit for this pin +#define GPIO_GPASET_GPIO2 0x4U // Output Set bit for this pin +#define GPIO_GPASET_GPIO3 0x8U // Output Set bit for this pin +#define GPIO_GPASET_GPIO4 0x10U // Output Set bit for this pin +#define GPIO_GPASET_GPIO5 0x20U // Output Set bit for this pin +#define GPIO_GPASET_GPIO6 0x40U // Output Set bit for this pin +#define GPIO_GPASET_GPIO7 0x80U // Output Set bit for this pin +#define GPIO_GPASET_GPIO8 0x100U // Output Set bit for this pin +#define GPIO_GPASET_GPIO9 0x200U // Output Set bit for this pin +#define GPIO_GPASET_GPIO10 0x400U // Output Set bit for this pin +#define GPIO_GPASET_GPIO11 0x800U // Output Set bit for this pin +#define GPIO_GPASET_GPIO12 0x1000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO13 0x2000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO14 0x4000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO15 0x8000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO16 0x10000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO17 0x20000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO18 0x40000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO19 0x80000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO20 0x100000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO21 0x200000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO22 0x400000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO23 0x800000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO24 0x1000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO25 0x2000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO26 0x4000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO27 0x8000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO28 0x10000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO29 0x20000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO30 0x40000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO31 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACLEAR register +// +//************************************************************************************************* +#define GPIO_GPACLEAR_GPIO0 0x1U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO1 0x2U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO2 0x4U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO3 0x8U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO4 0x10U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO5 0x20U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO6 0x40U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO7 0x80U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO8 0x100U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO9 0x200U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO10 0x400U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO11 0x800U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO12 0x1000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO13 0x2000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO14 0x4000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO15 0x8000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO16 0x10000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO17 0x20000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO18 0x40000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO19 0x80000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO20 0x100000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO21 0x200000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO22 0x400000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO23 0x800000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO24 0x1000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO25 0x2000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO26 0x4000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO27 0x8000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO28 0x10000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO29 0x20000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO30 0x40000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO31 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPATOGGLE register +// +//************************************************************************************************* +#define GPIO_GPATOGGLE_GPIO0 0x1U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO1 0x2U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO2 0x4U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO3 0x8U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO4 0x10U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO5 0x20U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO6 0x40U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO7 0x80U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO8 0x100U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO9 0x200U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO10 0x400U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO11 0x800U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO12 0x1000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO13 0x2000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO14 0x4000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO15 0x8000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO16 0x10000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO17 0x20000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO18 0x40000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO19 0x80000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO20 0x100000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO21 0x200000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO22 0x400000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO23 0x800000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO24 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO25 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO26 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO27 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO28 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO29 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO30 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO31 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDAT register +// +//************************************************************************************************* +#define GPIO_GPBDAT_GPIO32 0x1U // Data Register for this pin +#define GPIO_GPBDAT_GPIO33 0x2U // Data Register for this pin +#define GPIO_GPBDAT_GPIO34 0x4U // Data Register for this pin +#define GPIO_GPBDAT_GPIO35 0x8U // Data Register for this pin +#define GPIO_GPBDAT_GPIO36 0x10U // Data Register for this pin +#define GPIO_GPBDAT_GPIO37 0x20U // Data Register for this pin +#define GPIO_GPBDAT_GPIO38 0x40U // Data Register for this pin +#define GPIO_GPBDAT_GPIO39 0x80U // Data Register for this pin +#define GPIO_GPBDAT_GPIO40 0x100U // Data Register for this pin +#define GPIO_GPBDAT_GPIO41 0x200U // Data Register for this pin +#define GPIO_GPBDAT_GPIO42 0x400U // Data Register for this pin +#define GPIO_GPBDAT_GPIO43 0x800U // Data Register for this pin +#define GPIO_GPBDAT_GPIO44 0x1000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO45 0x2000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO46 0x4000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO47 0x8000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO48 0x10000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO49 0x20000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO50 0x40000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO51 0x80000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO52 0x100000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO53 0x200000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO54 0x400000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO55 0x800000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO56 0x1000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO57 0x2000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO58 0x4000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO59 0x8000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO60 0x10000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO61 0x20000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO62 0x40000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO63 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBSET register +// +//************************************************************************************************* +#define GPIO_GPBSET_GPIO32 0x1U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO33 0x2U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO34 0x4U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO35 0x8U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO36 0x10U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO37 0x20U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO38 0x40U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO39 0x80U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO40 0x100U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO41 0x200U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO42 0x400U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO43 0x800U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO44 0x1000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO45 0x2000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO46 0x4000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO47 0x8000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO48 0x10000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO49 0x20000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO50 0x40000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO51 0x80000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO52 0x100000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO53 0x200000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO54 0x400000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO55 0x800000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO56 0x1000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO57 0x2000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO58 0x4000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO59 0x8000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO60 0x10000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO61 0x20000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO62 0x40000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO63 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCLEAR register +// +//************************************************************************************************* +#define GPIO_GPBCLEAR_GPIO32 0x1U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO33 0x2U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO34 0x4U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO35 0x8U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO36 0x10U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO37 0x20U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO38 0x40U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO39 0x80U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO40 0x100U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO41 0x200U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO42 0x400U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO43 0x800U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO44 0x1000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO45 0x2000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO46 0x4000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO47 0x8000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO48 0x10000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO49 0x20000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO50 0x40000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO51 0x80000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO52 0x100000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO53 0x200000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO54 0x400000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO55 0x800000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO56 0x1000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO57 0x2000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO58 0x4000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO59 0x8000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO60 0x10000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO61 0x20000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO62 0x40000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO63 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPBTOGGLE_GPIO32 0x1U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO33 0x2U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO34 0x4U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO35 0x8U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO36 0x10U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO37 0x20U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO38 0x40U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO39 0x80U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO40 0x100U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO41 0x200U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO42 0x400U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO43 0x800U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO44 0x1000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO45 0x2000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO46 0x4000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO47 0x8000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO48 0x10000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO49 0x20000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO50 0x40000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO51 0x80000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO52 0x100000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO53 0x200000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO54 0x400000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO55 0x800000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO56 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO57 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO58 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO59 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO60 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO61 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO62 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO63 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDAT register +// +//************************************************************************************************* +#define GPIO_GPCDAT_GPIO64 0x1U // Data Register for this pin +#define GPIO_GPCDAT_GPIO65 0x2U // Data Register for this pin +#define GPIO_GPCDAT_GPIO66 0x4U // Data Register for this pin +#define GPIO_GPCDAT_GPIO67 0x8U // Data Register for this pin +#define GPIO_GPCDAT_GPIO68 0x10U // Data Register for this pin +#define GPIO_GPCDAT_GPIO69 0x20U // Data Register for this pin +#define GPIO_GPCDAT_GPIO70 0x40U // Data Register for this pin +#define GPIO_GPCDAT_GPIO71 0x80U // Data Register for this pin +#define GPIO_GPCDAT_GPIO72 0x100U // Data Register for this pin +#define GPIO_GPCDAT_GPIO73 0x200U // Data Register for this pin +#define GPIO_GPCDAT_GPIO74 0x400U // Data Register for this pin +#define GPIO_GPCDAT_GPIO75 0x800U // Data Register for this pin +#define GPIO_GPCDAT_GPIO76 0x1000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO77 0x2000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO78 0x4000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO79 0x8000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO80 0x10000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO81 0x20000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO82 0x40000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO83 0x80000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO84 0x100000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO85 0x200000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO86 0x400000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO87 0x800000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO88 0x1000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO89 0x2000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO90 0x4000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO91 0x8000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO92 0x10000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO93 0x20000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO94 0x40000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO95 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCSET register +// +//************************************************************************************************* +#define GPIO_GPCSET_GPIO64 0x1U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO65 0x2U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO66 0x4U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO67 0x8U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO68 0x10U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO69 0x20U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO70 0x40U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO71 0x80U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO72 0x100U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO73 0x200U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO74 0x400U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO75 0x800U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO76 0x1000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO77 0x2000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO78 0x4000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO79 0x8000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO80 0x10000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO81 0x20000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO82 0x40000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO83 0x80000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO84 0x100000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO85 0x200000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO86 0x400000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO87 0x800000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO88 0x1000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO89 0x2000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO90 0x4000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO91 0x8000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO92 0x10000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO93 0x20000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO94 0x40000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO95 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCLEAR register +// +//************************************************************************************************* +#define GPIO_GPCCLEAR_GPIO64 0x1U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO65 0x2U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO66 0x4U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO67 0x8U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO68 0x10U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO69 0x20U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO70 0x40U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO71 0x80U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO72 0x100U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO73 0x200U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO74 0x400U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO75 0x800U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO76 0x1000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO77 0x2000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO78 0x4000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO79 0x8000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO80 0x10000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO81 0x20000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO82 0x40000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO83 0x80000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO84 0x100000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO85 0x200000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO86 0x400000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO87 0x800000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO88 0x1000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO89 0x2000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO90 0x4000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO91 0x8000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO92 0x10000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO93 0x20000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO94 0x40000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO95 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPCTOGGLE_GPIO64 0x1U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO65 0x2U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO66 0x4U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO67 0x8U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO68 0x10U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO69 0x20U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO70 0x40U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO71 0x80U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO72 0x100U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO73 0x200U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO74 0x400U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO75 0x800U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO76 0x1000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO77 0x2000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO78 0x4000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO79 0x8000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO80 0x10000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO81 0x20000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO82 0x40000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO83 0x80000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO84 0x100000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO85 0x200000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO86 0x400000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO87 0x800000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO88 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO89 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO90 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO91 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO92 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO93 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO94 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO95 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDAT register +// +//************************************************************************************************* +#define GPIO_GPDDAT_GPIO96 0x1U // Data Register for this pin +#define GPIO_GPDDAT_GPIO97 0x2U // Data Register for this pin +#define GPIO_GPDDAT_GPIO98 0x4U // Data Register for this pin +#define GPIO_GPDDAT_GPIO99 0x8U // Data Register for this pin +#define GPIO_GPDDAT_GPIO100 0x10U // Data Register for this pin +#define GPIO_GPDDAT_GPIO101 0x20U // Data Register for this pin +#define GPIO_GPDDAT_GPIO102 0x40U // Data Register for this pin +#define GPIO_GPDDAT_GPIO103 0x80U // Data Register for this pin +#define GPIO_GPDDAT_GPIO104 0x100U // Data Register for this pin +#define GPIO_GPDDAT_GPIO105 0x200U // Data Register for this pin +#define GPIO_GPDDAT_GPIO106 0x400U // Data Register for this pin +#define GPIO_GPDDAT_GPIO107 0x800U // Data Register for this pin +#define GPIO_GPDDAT_GPIO108 0x1000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO109 0x2000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO110 0x4000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO111 0x8000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO112 0x10000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO113 0x20000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO114 0x40000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO115 0x80000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO116 0x100000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO117 0x200000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO118 0x400000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO119 0x800000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO120 0x1000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO121 0x2000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO122 0x4000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO123 0x8000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO124 0x10000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO125 0x20000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO126 0x40000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO127 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDSET register +// +//************************************************************************************************* +#define GPIO_GPDSET_GPIO96 0x1U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO97 0x2U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO98 0x4U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO99 0x8U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO100 0x10U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO101 0x20U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO102 0x40U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO103 0x80U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO104 0x100U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO105 0x200U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO106 0x400U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO107 0x800U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO108 0x1000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO109 0x2000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO110 0x4000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO111 0x8000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO112 0x10000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO113 0x20000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO114 0x40000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO115 0x80000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO116 0x100000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO117 0x200000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO118 0x400000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO119 0x800000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO120 0x1000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO121 0x2000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO122 0x4000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO123 0x8000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO124 0x10000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO125 0x20000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO126 0x40000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO127 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCLEAR register +// +//************************************************************************************************* +#define GPIO_GPDCLEAR_GPIO96 0x1U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO97 0x2U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO98 0x4U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO99 0x8U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO100 0x10U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO101 0x20U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO102 0x40U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO103 0x80U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO104 0x100U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO105 0x200U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO106 0x400U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO107 0x800U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO108 0x1000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO109 0x2000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO110 0x4000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO111 0x8000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO112 0x10000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO113 0x20000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO114 0x40000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO115 0x80000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO116 0x100000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO117 0x200000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO118 0x400000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO119 0x800000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO120 0x1000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO121 0x2000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO122 0x4000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO123 0x8000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO124 0x10000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO125 0x20000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO126 0x40000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO127 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPDTOGGLE_GPIO96 0x1U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO97 0x2U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO98 0x4U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO99 0x8U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO100 0x10U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO101 0x20U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO102 0x40U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO103 0x80U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO104 0x100U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO105 0x200U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO106 0x400U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO107 0x800U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO108 0x1000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO109 0x2000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO110 0x4000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO111 0x8000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO112 0x10000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO113 0x20000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO114 0x40000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO115 0x80000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO116 0x100000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO117 0x200000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO118 0x400000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO119 0x800000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO120 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO121 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO122 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO123 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO124 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO125 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO126 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO127 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDAT register +// +//************************************************************************************************* +#define GPIO_GPEDAT_GPIO128 0x1U // Data Register for this pin +#define GPIO_GPEDAT_GPIO129 0x2U // Data Register for this pin +#define GPIO_GPEDAT_GPIO130 0x4U // Data Register for this pin +#define GPIO_GPEDAT_GPIO131 0x8U // Data Register for this pin +#define GPIO_GPEDAT_GPIO132 0x10U // Data Register for this pin +#define GPIO_GPEDAT_GPIO133 0x20U // Data Register for this pin +#define GPIO_GPEDAT_GPIO134 0x40U // Data Register for this pin +#define GPIO_GPEDAT_GPIO135 0x80U // Data Register for this pin +#define GPIO_GPEDAT_GPIO136 0x100U // Data Register for this pin +#define GPIO_GPEDAT_GPIO137 0x200U // Data Register for this pin +#define GPIO_GPEDAT_GPIO138 0x400U // Data Register for this pin +#define GPIO_GPEDAT_GPIO139 0x800U // Data Register for this pin +#define GPIO_GPEDAT_GPIO140 0x1000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO141 0x2000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO142 0x4000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO143 0x8000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO144 0x10000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO145 0x20000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO146 0x40000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO147 0x80000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO148 0x100000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO149 0x200000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO150 0x400000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO151 0x800000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO152 0x1000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO153 0x2000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO154 0x4000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO155 0x8000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO156 0x10000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO157 0x20000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO158 0x40000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO159 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPESET register +// +//************************************************************************************************* +#define GPIO_GPESET_GPIO128 0x1U // Output Set bit for this pin +#define GPIO_GPESET_GPIO129 0x2U // Output Set bit for this pin +#define GPIO_GPESET_GPIO130 0x4U // Output Set bit for this pin +#define GPIO_GPESET_GPIO131 0x8U // Output Set bit for this pin +#define GPIO_GPESET_GPIO132 0x10U // Output Set bit for this pin +#define GPIO_GPESET_GPIO133 0x20U // Output Set bit for this pin +#define GPIO_GPESET_GPIO134 0x40U // Output Set bit for this pin +#define GPIO_GPESET_GPIO135 0x80U // Output Set bit for this pin +#define GPIO_GPESET_GPIO136 0x100U // Output Set bit for this pin +#define GPIO_GPESET_GPIO137 0x200U // Output Set bit for this pin +#define GPIO_GPESET_GPIO138 0x400U // Output Set bit for this pin +#define GPIO_GPESET_GPIO139 0x800U // Output Set bit for this pin +#define GPIO_GPESET_GPIO140 0x1000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO141 0x2000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO142 0x4000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO143 0x8000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO144 0x10000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO145 0x20000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO146 0x40000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO147 0x80000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO148 0x100000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO149 0x200000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO150 0x400000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO151 0x800000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO152 0x1000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO153 0x2000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO154 0x4000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO155 0x8000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO156 0x10000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO157 0x20000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO158 0x40000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO159 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECLEAR register +// +//************************************************************************************************* +#define GPIO_GPECLEAR_GPIO128 0x1U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO129 0x2U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO130 0x4U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO131 0x8U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO132 0x10U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO133 0x20U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO134 0x40U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO135 0x80U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO136 0x100U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO137 0x200U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO138 0x400U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO139 0x800U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO140 0x1000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO141 0x2000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO142 0x4000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO143 0x8000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO144 0x10000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO145 0x20000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO146 0x40000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO147 0x80000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO148 0x100000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO149 0x200000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO150 0x400000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO151 0x800000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO152 0x1000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO153 0x2000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO154 0x4000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO155 0x8000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO156 0x10000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO157 0x20000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO158 0x40000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO159 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPETOGGLE register +// +//************************************************************************************************* +#define GPIO_GPETOGGLE_GPIO128 0x1U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO129 0x2U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO130 0x4U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO131 0x8U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO132 0x10U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO133 0x20U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO134 0x40U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO135 0x80U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO136 0x100U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO137 0x200U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO138 0x400U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO139 0x800U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO140 0x1000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO141 0x2000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO142 0x4000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO143 0x8000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO144 0x10000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO145 0x20000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO146 0x40000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO147 0x80000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO148 0x100000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO149 0x200000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO150 0x400000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO151 0x800000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO152 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO153 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO154 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO155 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO156 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO157 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO158 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO159 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDAT register +// +//************************************************************************************************* +#define GPIO_GPFDAT_GPIO160 0x1U // Data Register for this pin +#define GPIO_GPFDAT_GPIO161 0x2U // Data Register for this pin +#define GPIO_GPFDAT_GPIO162 0x4U // Data Register for this pin +#define GPIO_GPFDAT_GPIO163 0x8U // Data Register for this pin +#define GPIO_GPFDAT_GPIO164 0x10U // Data Register for this pin +#define GPIO_GPFDAT_GPIO165 0x20U // Data Register for this pin +#define GPIO_GPFDAT_GPIO166 0x40U // Data Register for this pin +#define GPIO_GPFDAT_GPIO167 0x80U // Data Register for this pin +#define GPIO_GPFDAT_GPIO168 0x100U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFSET register +// +//************************************************************************************************* +#define GPIO_GPFSET_GPIO160 0x1U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO161 0x2U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO162 0x4U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO163 0x8U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO164 0x10U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO165 0x20U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO166 0x40U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO167 0x80U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO168 0x100U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCLEAR register +// +//************************************************************************************************* +#define GPIO_GPFCLEAR_GPIO160 0x1U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO161 0x2U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO162 0x4U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO163 0x8U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO164 0x10U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO165 0x20U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO166 0x40U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO167 0x80U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO168 0x100U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPFTOGGLE_GPIO160 0x1U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO161 0x2U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO162 0x4U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO163 0x8U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO164 0x10U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO165 0x20U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO166 0x40U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO167 0x80U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO168 0x100U // Output Toggle bit for this pin + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_hic.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_hic.h new file mode 100644 index 0000000..07d544f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_hic.h @@ -0,0 +1,344 @@ +//########################################################################### +// +// FILE: hw_hic.h +// +// TITLE: Definitions for the HIC registers. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HIC_H +#define HW_HIC_H + +//************************************************************************************************* +// +// The following are defines for the HIC register offsets +// +//************************************************************************************************* +#define HIC_O_REV 0x0U // Module Revision Register +#define HIC_O_GCR 0x2U // Global Control Register +#define HIC_O_LOCK 0x4U // Lock Register +#define HIC_O_MODECR 0x6U // Mode Control Register +#define HIC_O_PINPOLCR 0x8U // Pin Polarity Control Register +#define HIC_O_BASESEL 0xAU // Base Select Register +#define HIC_O_HOSTCR 0xCU // Host Control Register +#define HIC_O_ERRADDR 0xEU // Host Error Address register +#define HIC_O_H2DTOKEN 0x10U // Host to Device Token Register +#define HIC_O_D2HTOKEN 0x12U // Devie to Host Token Register +#define HIC_O_DBADDR0 0x14U // Device Base Address Register 0 +#define HIC_O_DBADDR1 0x16U // Device Base Address Register 1 +#define HIC_O_DBADDR2 0x18U // Device Base Address Register 2 +#define HIC_O_DBADDR3 0x1AU // Device Base Address Register 3 +#define HIC_O_DBADDR4 0x1CU // Device Base Address Register 4 +#define HIC_O_DBADDR5 0x1EU // Device Base Address Register 5 +#define HIC_O_DBADDR6 0x20U // Device Base Address Register 6 +#define HIC_O_DBADDR7 0x22U // Device Base Address Register 7 +#define HIC_O_H2DINTEN 0x28U // H2D Interrupt Enable +#define HIC_O_H2DINTFLG 0x2AU // H2D Interrupt status Flag +#define HIC_O_H2DINTCLR 0x2CU // H2D Interrupt status Clear +#define HIC_O_H2DINTFRC 0x2EU // H2D Interrupt Set Force +#define HIC_O_D2HINTEN 0x30U // D2H Interrupt Enable +#define HIC_O_D2HINTFLG 0x32U // D2H Interrupt status Flag +#define HIC_O_D2HINTCLR 0x34U // D2H Interrupt status Clear +#define HIC_O_D2HINTFRC 0x36U // D2H Interrupt Set Force +#define HIC_O_ACCVIOADDR 0x38U // Access Violation Address +#define HIC_O_H2D_BUF0 0x40U // Host to Device Buffer 0 +#define HIC_O_H2D_BUF1 0x42U // Host to Device Buffer 1 +#define HIC_O_H2D_BUF2 0x44U // Host to Device Buffer 2 +#define HIC_O_H2D_BUF3 0x46U // Host to Device Buffer 3 +#define HIC_O_H2D_BUF4 0x48U // Host to Device Buffer 4 +#define HIC_O_H2D_BUF5 0x4AU // Host to Device Buffer 5 +#define HIC_O_H2D_BUF6 0x4CU // Host to Device Buffer 6 +#define HIC_O_H2D_BUF7 0x4EU // Host to Device Buffer 7 +#define HIC_O_H2D_BUF8 0x50U // Host to Device Buffer 8 +#define HIC_O_H2D_BUF9 0x52U // Host to Device Buffer 9 +#define HIC_O_H2D_BUF10 0x54U // Host to Device Buffer 10 +#define HIC_O_H2D_BUF11 0x56U // Host to Device Buffer 11 +#define HIC_O_H2D_BUF12 0x58U // Host to Device Buffer 12 +#define HIC_O_H2D_BUF13 0x5AU // Host to Device Buffer 13 +#define HIC_O_H2D_BUF14 0x5CU // Host to Device Buffer 14 +#define HIC_O_H2D_BUF15 0x5EU // Host to Device Buffer 15 +#define HIC_O_D2H_BUF0 0x60U // Device to Host Buffer 0 +#define HIC_O_D2H_BUF1 0x62U // Device to Host Buffer 1 +#define HIC_O_D2H_BUF2 0x64U // Device to Host Buffer 2 +#define HIC_O_D2H_BUF3 0x66U // Device to Host Buffer 3 +#define HIC_O_D2H_BUF4 0x68U // Device to Host Buffer 4 +#define HIC_O_D2H_BUF5 0x6AU // Device to Host Buffer 5 +#define HIC_O_D2H_BUF6 0x6CU // Device to Host Buffer 6 +#define HIC_O_D2H_BUF7 0x6EU // Device to Host Buffer 7 +#define HIC_O_D2H_BUF8 0x70U // Device to Host Buffer 8 +#define HIC_O_D2H_BUF9 0x72U // Device to Host Buffer 9 +#define HIC_O_D2H_BUF10 0x74U // Device to Host Buffer 10 +#define HIC_O_D2H_BUF11 0x76U // Device to Host Buffer 11 +#define HIC_O_D2H_BUF12 0x78U // Device to Host Buffer 12 +#define HIC_O_D2H_BUF13 0x7AU // Device to Host Buffer 13 +#define HIC_O_D2H_BUF14 0x7CU // Device to Host Buffer 14 +#define HIC_O_D2H_BUF15 0x7EU // Device to Host Buffer 15 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICREV register +// +//************************************************************************************************* +#define HIC_REV_MINOR_S 0U +#define HIC_REV_MINOR_M 0x3FU // Minor Revision Number +#define HIC_REV_CUSTOM_S 6U +#define HIC_REV_CUSTOM_M 0xC0U // Custom Module Number +#define HIC_REV_MAJOR_S 8U +#define HIC_REV_MAJOR_M 0x700U // Major Revision Number +#define HIC_REV_RTL_S 11U +#define HIC_REV_RTL_M 0xF800U // Design Release Number +#define HIC_REV_FUNC_S 16U +#define HIC_REV_FUNC_M 0xFFF0000U // Functional Release Number +#define HIC_REV_SCHEME_S 30U +#define HIC_REV_SCHEME_M 0xC0000000U // Defines Scheme for Module +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICGCR register +// +//************************************************************************************************* +#define HIC_GCR_HICEN_S 0U +#define HIC_GCR_HICEN_M 0xFU // Host Interface Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICLOCK register +// +//************************************************************************************************* +#define HIC_LOCK_LOCK 0x1U // LOCK enable +#define HIC_LOCK_WRITE_ENABLE_KEY_S 16U +#define HIC_LOCK_WRITE_ENABLE_KEY_M 0xFFFF0000U // Key for enabling write +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICMODECR register +// +//************************************************************************************************* +#define HIC_MODECR_DW_MODE_S 0U +#define HIC_MODECR_DW_MODE_M 0x3U // Data Width Mode +#define HIC_MODECR_RW_MODE 0x10U // Read-Write Mode +#define HIC_MODECR_BEN_PRESENT 0x20U // Byte Enable Pins are present +#define HIC_MODECR_RDY_PRESENT 0x40U // Ready pin present +#define HIC_MODECR_H2DBUF_DEVWREN 0x100U // Write Enable for Device to H2D Buffer +#define HIC_MODECR_D2HBUF_HOSTWREN 0x200U // Write Enable for Host to D2H Buffer +#define HIC_MODECR_EN_DEVACC 0x400U // Enable Host access to Device region +#define HIC_MODECR_EN_HOSTWREALLOW 0x800U // Enable Host Write to EALLOWCTL register +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICPINPOLCR register +// +//************************************************************************************************* +#define HIC_PINPOLCR_CS_POL 0x1U // Chip Select Polarity +#define HIC_PINPOLCR_BEN_POL 0x2U // Byte Enable Polarity +#define HIC_PINPOLCR_OE_POL 0x4U // Output Enable Polarity +#define HIC_PINPOLCR_WE_POL 0x8U // Write Enable Polarity +#define HIC_PINPOLCR_RDY_POL 0x10U // Ready Polarity +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICBASESEL register +// +//************************************************************************************************* +#define HIC_BASESEL_BASE_SELECT_S 0U +#define HIC_BASESEL_BASE_SELECT_M 0x7U // Base Select +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICHOSTCR register +// +//************************************************************************************************* +#define HIC_HOSTCR_EALLOW_EN 0x1U // EALLOW Enable +#define HIC_HOSTCR_ACCSIZE 0x2U // Access Size +#define HIC_HOSTCR_PAGESEL 0x4U // Page Select +#define HIC_HOSTCR_HKEY_S 8U +#define HIC_HOSTCR_HKEY_M 0xFF00U // Host Key +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICERRADDR register +// +//************************************************************************************************* +#define HIC_ERRADDR_H2D_ERR_ADDR_S 0U +#define HIC_ERRADDR_H2D_ERR_ADDR_M 0xFFU // Address of the Host bus captured upon an + // error for Device +#define HIC_ERRADDR_H2D_BASE_SEL_S 12U +#define HIC_ERRADDR_H2D_BASE_SEL_M 0x7000U // Base Select corresponding to H2D error event +#define HIC_ERRADDR_D2H_ERR_ADDR_S 16U +#define HIC_ERRADDR_D2H_ERR_ADDR_M 0xFF0000U // Address of the Host bus captured upon an + // error for Host +#define HIC_ERRADDR_D2H_BASE_SEL_S 28U +#define HIC_ERRADDR_D2H_BASE_SEL_M 0x70000000U // Base Select corresponding to D2H error event +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR0 register +// +//************************************************************************************************* +#define HIC_DBADDR0_BASE_ADDR_S 7U +#define HIC_DBADDR0_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR1 register +// +//************************************************************************************************* +#define HIC_DBADDR1_BASE_ADDR_S 7U +#define HIC_DBADDR1_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR2 register +// +//************************************************************************************************* +#define HIC_DBADDR2_BASE_ADDR_S 7U +#define HIC_DBADDR2_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR3 register +// +//************************************************************************************************* +#define HIC_DBADDR3_BASE_ADDR_S 7U +#define HIC_DBADDR3_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR4 register +// +//************************************************************************************************* +#define HIC_DBADDR4_BASE_ADDR_S 7U +#define HIC_DBADDR4_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR5 register +// +//************************************************************************************************* +#define HIC_DBADDR5_BASE_ADDR_S 7U +#define HIC_DBADDR5_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR6 register +// +//************************************************************************************************* +#define HIC_DBADDR6_BASE_ADDR_S 7U +#define HIC_DBADDR6_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR7 register +// +//************************************************************************************************* +#define HIC_DBADDR7_BASE_ADDR_S 7U +#define HIC_DBADDR7_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTEN register +// +//************************************************************************************************* +#define HIC_H2DINTEN_H2D_INTEN 0x1U // Host To Device Interrupt Enable +#define HIC_H2DINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_H2DINTEN_ILLWR_INTEN 0x4U // Illegal Write event interrupt enable +#define HIC_H2DINTEN_ILLRD_INTEN 0x8U // Illegal Read event interrupt enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFLG register +// +//************************************************************************************************* +#define HIC_H2DINTFLG_H2D_FLG 0x1U // Host To Device Interrupt Flag +#define HIC_H2DINTFLG_BUSERR_FLG 0x2U // BusError Interrupt Flag +#define HIC_H2DINTFLG_ILLWR_FLG 0x4U // Illegal write event interrupt flag +#define HIC_H2DINTFLG_ILLRD_FLG 0x8U // Illegal read event interrupt flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTCLR register +// +//************************************************************************************************* +#define HIC_H2DINTCLR_H2D_CLR 0x1U // Host To Device Interrupt Clear +#define HIC_H2DINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_H2DINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_H2DINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFRC register +// +//************************************************************************************************* +#define HIC_H2DINTFRC_H2D_INTFRC 0x1U // Host To Device Force Set +#define HIC_H2DINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_H2DINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_H2DINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTEN register +// +//************************************************************************************************* +#define HIC_D2HINTEN_D2H_INTEN 0x1U // Device to Host Data Ready Interrupt Enable +#define HIC_D2HINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_D2HINTEN_ILLWR_INTEN 0x4U // Illegal Write event Interrupt Enable +#define HIC_D2HINTEN_ILLRD_INTEN 0x8U // Illegal Read event Interrupt Enable +#define HIC_D2HINTEN_ACCVIO_INTEN 0x10U // Access Violation Interrupt Enable +#define HIC_D2HINTEN_EVTRIG_INTEN_S 16U +#define HIC_D2HINTEN_EVTRIG_INTEN_M 0xFFFF0000U // Event Trigger Interrupt Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFLG register +// +//************************************************************************************************* +#define HIC_D2HINTFLG_D2H_FLG 0x1U // Device to Host Data Ready Flag +#define HIC_D2HINTFLG_BUSERR_FLG 0x2U // BusError Flag +#define HIC_D2HINTFLG_ILLWR_FLG 0x4U // Illegal Write event Flag +#define HIC_D2HINTFLG_ILLRD_FLG 0x8U // Illegal Read event Flag +#define HIC_D2HINTFLG_ACCVIO_FLG 0x10U // Access Violation Flag +#define HIC_D2HINTFLG_EVTRIG_FLG_S 16U +#define HIC_D2HINTFLG_EVTRIG_FLG_M 0xFFFF0000U // Event Trigger Flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTCLR register +// +//************************************************************************************************* +#define HIC_D2HINTCLR_D2H_CLR 0x1U // Device to Host Interrupt Clear +#define HIC_D2HINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_D2HINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_D2HINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +#define HIC_D2HINTCLR_ACCVIO_CLR 0x10U // Access Violation Interrupt Clear +#define HIC_D2HINTCLR_EVTRIG_CLR_S 16U +#define HIC_D2HINTCLR_EVTRIG_CLR_M 0xFFFF0000U // Event Trigger Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFRC register +// +//************************************************************************************************* +#define HIC_D2HINTFRC_D2H_INTFRC 0x1U // Device to Host Force Set +#define HIC_D2HINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_D2HINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_D2HINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +#define HIC_D2HINTFRC_ACCVIO_INTFRC 0x10U // Access Violation Interrupt Force Set +#define HIC_D2HINTFRC_EVTRIG_INTFRC_S 16U +#define HIC_D2HINTFRC_EVTRIG_INTFRC_M 0xFFFF0000U // Event Trigger Interrupt Force Set + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_hrpwm.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_hrpwm.h new file mode 100644 index 0000000..a6c899f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_hrpwm.h @@ -0,0 +1,1058 @@ +//########################################################################### +// +// FILE: hw_hrpwm.h +// +// TITLE: Definitions for the HRPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HRPWM_H +#define HW_HRPWM_H + +//************************************************************************************************* +// +// The following are defines for the HRPWM register offsets +// +//************************************************************************************************* +#define HRPWM_O_TBCTL 0x0U // Time Base Control Register +#define HRPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define HRPWM_O_TBCTR 0x4U // Time Base Counter Register +#define HRPWM_O_TBSTS 0x5U // Time Base Status Register +#define HRPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define HRPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define HRPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define HRPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define HRPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define HRPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define HRPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define HRPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define HRPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define HRPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define HRPWM_O_HRPWR 0x21U // HRPWM Power Register +#define HRPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define HRPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define HRPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define HRPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define HRPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define HRPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define HRPWM_O_EPWMXLINK 0x38U // EPWMx Link Register +#define HRPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define HRPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define HRPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define HRPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define HRPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define HRPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define HRPWM_O_TBPHS 0x60U // Time Base Phase High +#define HRPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define HRPWM_O_TBPRD 0x63U // Time Base Period Register +#define HRPWM_O_CMPA 0x6AU // Counter Compare A Register +#define HRPWM_O_CMPB 0x6CU // Compare B Register +#define HRPWM_O_CMPC 0x6FU // Counter Compare C Register +#define HRPWM_O_CMPD 0x71U // Counter Compare D Register +#define HRPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define HRPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define HRPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define HRPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define HRPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define HRPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define HRPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define HRPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define HRPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define HRPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define HRPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define HRPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define HRPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define HRPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define HRPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define HRPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define HRPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define HRPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define HRPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define HRPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define HRPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define HRPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define HRPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define HRPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define HRPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define HRPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define HRPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define HRPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define HRPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define HRPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define HRPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define HRPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define HRPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define HRPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define HRPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define HRPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define HRPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define HRPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define HRPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define HRPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define HRPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define HRPWM_TBCTL_CTRMODE_S 0U +#define HRPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define HRPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define HRPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define HRPWM_TBCTL_SYNCOSEL_S 4U +#define HRPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define HRPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define HRPWM_TBCTL_HSPCLKDIV_S 7U +#define HRPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define HRPWM_TBCTL_CLKDIV_S 10U +#define HRPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define HRPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define HRPWM_TBCTL_FREE_SOFT_S 14U +#define HRPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define HRPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define HRPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define HRPWM_TBCTL2_SYNCOSELX_S 12U +#define HRPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define HRPWM_TBCTL2_PRDLDSYNC_S 14U +#define HRPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define HRPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define HRPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define HRPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define HRPWM_CMPCTL_LOADAMODE_S 0U +#define HRPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define HRPWM_CMPCTL_LOADBMODE_S 2U +#define HRPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define HRPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define HRPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define HRPWM_CMPCTL_LOADASYNC_S 10U +#define HRPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define HRPWM_CMPCTL_LOADBSYNC_S 12U +#define HRPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define HRPWM_CMPCTL2_LOADCMODE_S 0U +#define HRPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define HRPWM_CMPCTL2_LOADDMODE_S 2U +#define HRPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define HRPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define HRPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define HRPWM_CMPCTL2_LOADCSYNC_S 10U +#define HRPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define HRPWM_CMPCTL2_LOADDSYNC_S 12U +#define HRPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define HRPWM_DBCTL_OUT_MODE_S 0U +#define HRPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define HRPWM_DBCTL_POLSEL_S 2U +#define HRPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define HRPWM_DBCTL_IN_MODE_S 4U +#define HRPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define HRPWM_DBCTL_LOADREDMODE_S 6U +#define HRPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define HRPWM_DBCTL_LOADFEDMODE_S 8U +#define HRPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define HRPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define HRPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define HRPWM_DBCTL_OUTSWAP_S 12U +#define HRPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define HRPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define HRPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define HRPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define HRPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define HRPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define HRPWM_AQCTL_LDAQAMODE_S 0U +#define HRPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define HRPWM_AQCTL_LDAQBMODE_S 2U +#define HRPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define HRPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define HRPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define HRPWM_AQCTL_LDAQASYNC_S 8U +#define HRPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define HRPWM_AQCTL_LDAQBSYNC_S 10U +#define HRPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define HRPWM_AQTSRCSEL_T1SEL_S 0U +#define HRPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define HRPWM_AQTSRCSEL_T2SEL_S 4U +#define HRPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define HRPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define HRPWM_PCCTL_OSHTWTH_S 1U +#define HRPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define HRPWM_PCCTL_CHPFREQ_S 5U +#define HRPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define HRPWM_PCCTL_CHPDUTY_S 8U +#define HRPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define HRPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define HRPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define HRPWM_VCAPCTL_TRIGSEL_S 2U +#define HRPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define HRPWM_VCAPCTL_VDELAYDIV_S 7U +#define HRPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define HRPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define HRPWM_VCNTCFG_STARTEDGE_S 0U +#define HRPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define HRPWM_VCNTCFG_STOPEDGE_S 8U +#define HRPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define HRPWM_HRCNFG_EDGMODE_S 0U +#define HRPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOAD_S 3U +#define HRPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define HRPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define HRPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define HRPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define HRPWM_HRCNFG_EDGMODEB_S 8U +#define HRPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOADB_S 11U +#define HRPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define HRPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define HRPWM_HRMSTEP_HRMSTEP_S 0U +#define HRPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define HRPWM_HRCNFG2_EDGMODEDB_S 0U +#define HRPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define HRPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define HRPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define HRPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define HRPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define HRPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define HRPWM_HRPCTL_PWMSYNCSELX_S 4U +#define HRPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define HRPWM_TRREM_TRREM_S 0U +#define HRPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define HRPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define HRPWM_GLDCTL_GLDMODE_S 1U +#define HRPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define HRPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define HRPWM_GLDCTL_GLDPRD_S 7U +#define HRPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define HRPWM_GLDCTL_GLDCNT_S 10U +#define HRPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define HRPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define HRPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define HRPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define HRPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define HRPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define HRPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define HRPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define HRPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define HRPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define HRPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define HRPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define HRPWM_EPWMXLINK_TBPRDLINK_S 0U +#define HRPWM_EPWMXLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define HRPWM_EPWMXLINK_CMPALINK_S 4U +#define HRPWM_EPWMXLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define HRPWM_EPWMXLINK_CMPBLINK_S 8U +#define HRPWM_EPWMXLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define HRPWM_EPWMXLINK_CMPCLINK_S 12U +#define HRPWM_EPWMXLINK_CMPCLINK_M 0xF000U // CMPC Link +#define HRPWM_EPWMXLINK_CMPDLINK_S 16U +#define HRPWM_EPWMXLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define HRPWM_EPWMXLINK_GLDCTL2LINK_S 28U +#define HRPWM_EPWMXLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define HRPWM_AQCTLA_ZRO_S 0U +#define HRPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLA_PRD_S 2U +#define HRPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLA_CAU_S 4U +#define HRPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLA_CAD_S 6U +#define HRPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLA_CBU_S 8U +#define HRPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLA_CBD_S 10U +#define HRPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLA2_T1U_S 0U +#define HRPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLA2_T1D_S 2U +#define HRPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLA2_T2U_S 4U +#define HRPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLA2_T2D_S 6U +#define HRPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define HRPWM_AQCTLB_ZRO_S 0U +#define HRPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLB_PRD_S 2U +#define HRPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLB_CAU_S 4U +#define HRPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLB_CAD_S 6U +#define HRPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLB_CBU_S 8U +#define HRPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLB_CBD_S 10U +#define HRPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLB2_T1U_S 0U +#define HRPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLB2_T1D_S 2U +#define HRPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLB2_T2U_S 4U +#define HRPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLB2_T2D_S 6U +#define HRPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define HRPWM_AQSFRC_ACTSFA_S 0U +#define HRPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define HRPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define HRPWM_AQSFRC_ACTSFB_S 3U +#define HRPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define HRPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define HRPWM_AQSFRC_RLDCSF_S 6U +#define HRPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define HRPWM_AQCSFRC_CSFA_S 0U +#define HRPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define HRPWM_AQCSFRC_CSFB_S 2U +#define HRPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define HRPWM_DBREDHR_DBREDHR_S 9U +#define HRPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define HRPWM_DBRED_DBRED_S 0U +#define HRPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define HRPWM_DBFEDHR_DBFEDHR_S 9U +#define HRPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define HRPWM_DBFED_DBFED_S 0U +#define HRPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define HRPWM_TBPHS_TBPHSHR_S 0U +#define HRPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define HRPWM_TBPHS_TBPHS_S 16U +#define HRPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define HRPWM_CMPA_CMPAHR_S 0U +#define HRPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define HRPWM_CMPA_CMPA_S 16U +#define HRPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define HRPWM_CMPB_CMPBHR_S 0U +#define HRPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define HRPWM_CMPB_CMPB_S 16U +#define HRPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define HRPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define HRPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define HRPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define HRPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define HRPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define HRPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define HRPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define HRPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define HRPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define HRPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define HRPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define HRPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define HRPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define HRPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define HRPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define HRPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define HRPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define HRPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define HRPWM_TZDCSEL_DCAEVT1_S 0U +#define HRPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define HRPWM_TZDCSEL_DCAEVT2_S 3U +#define HRPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define HRPWM_TZDCSEL_DCBEVT1_S 6U +#define HRPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define HRPWM_TZDCSEL_DCBEVT2_S 9U +#define HRPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define HRPWM_TZCTL_TZA_S 0U +#define HRPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define HRPWM_TZCTL_TZB_S 2U +#define HRPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define HRPWM_TZCTL_DCAEVT1_S 4U +#define HRPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define HRPWM_TZCTL_DCAEVT2_S 6U +#define HRPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define HRPWM_TZCTL_DCBEVT1_S 8U +#define HRPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define HRPWM_TZCTL_DCBEVT2_S 10U +#define HRPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define HRPWM_TZCTL2_TZAU_S 0U +#define HRPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define HRPWM_TZCTL2_TZAD_S 3U +#define HRPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define HRPWM_TZCTL2_TZBU_S 6U +#define HRPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define HRPWM_TZCTL2_TZBD_S 9U +#define HRPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define HRPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCA_DCAEVT1U_S 0U +#define HRPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT1D_S 3U +#define HRPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCA_DCAEVT2U_S 6U +#define HRPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT2D_S 9U +#define HRPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCB_DCBEVT1U_S 0U +#define HRPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT1D_S 3U +#define HRPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCB_DCBEVT2U_S 6U +#define HRPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT2D_S 9U +#define HRPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define HRPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define HRPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define HRPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define HRPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define HRPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define HRPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define HRPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define HRPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define HRPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define HRPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define HRPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define HRPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define HRPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define HRPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define HRPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define HRPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define HRPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define HRPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define HRPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define HRPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event + // 2 +#define HRPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event + // 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define HRPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define HRPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define HRPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define HRPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define HRPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define HRPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define HRPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event + // 1 +#define HRPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event + // 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define HRPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define HRPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define HRPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define HRPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define HRPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define HRPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define HRPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define HRPWM_TZCLR_CBCPULSE_S 14U +#define HRPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define HRPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define HRPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define HRPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define HRPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define HRPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define HRPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define HRPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define HRPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define HRPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define HRPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define HRPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define HRPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define HRPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define HRPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define HRPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define HRPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define HRPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define HRPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define HRPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define HRPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define HRPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define HRPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define HRPWM_ETSEL_INTSEL_S 0U +#define HRPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define HRPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define HRPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define HRPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define HRPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define HRPWM_ETSEL_SOCASEL_S 8U +#define HRPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define HRPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define HRPWM_ETSEL_SOCBSEL_S 12U +#define HRPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define HRPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define HRPWM_ETPS_INTPRD_S 0U +#define HRPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define HRPWM_ETPS_INTCNT_S 2U +#define HRPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define HRPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCAPRD_S 8U +#define HRPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define HRPWM_ETPS_SOCACNT_S 10U +#define HRPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define HRPWM_ETPS_SOCBPRD_S 12U +#define HRPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define HRPWM_ETPS_SOCBCNT_S 14U +#define HRPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define HRPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define HRPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define HRPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define HRPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define HRPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define HRPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define HRPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define HRPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define HRPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define HRPWM_ETINTPS_INTPRD2_S 0U +#define HRPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define HRPWM_ETINTPS_INTCNT2_S 4U +#define HRPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define HRPWM_ETSOCPS_SOCAPRD2_S 0U +#define HRPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define HRPWM_ETSOCPS_SOCACNT2_S 4U +#define HRPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define HRPWM_ETSOCPS_SOCBPRD2_S 8U +#define HRPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define HRPWM_ETSOCPS_SOCBCNT2_S 12U +#define HRPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define HRPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define HRPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define HRPWM_ETCNTINIT_INTINIT_S 0U +#define HRPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCAINIT_S 4U +#define HRPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCBINIT_S 8U +#define HRPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define HRPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define HRPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define HRPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define HRPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define HRPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define HRPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define HRPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define HRPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define HRPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define HRPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define HRPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define HRPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define HRPWM_DCFCTL_SRCSEL_S 0U +#define HRPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define HRPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define HRPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define HRPWM_DCFCTL_PULSESEL_S 4U +#define HRPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define HRPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define HRPWM_DCFCTL_EDGEMODE_S 8U +#define HRPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define HRPWM_DCFCTL_EDGECOUNT_S 10U +#define HRPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define HRPWM_DCFCTL_EDGESTATUS_S 13U +#define HRPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define HRPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define HRPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define HRPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define HRPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define HRPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_i2c.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_i2c.h new file mode 100644 index 0000000..e37ef50 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_i2c.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_i2c.h +// +// TITLE: Definitions for the I2C registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_I2C_H +#define HW_I2C_H + +//************************************************************************************************* +// +// The following are defines for the I2C register offsets +// +//************************************************************************************************* +#define I2C_O_OAR 0x0U // I2C Own address +#define I2C_O_IER 0x1U // I2C Interrupt Enable +#define I2C_O_STR 0x2U // I2C Status +#define I2C_O_CLKL 0x3U // I2C Clock low-time divider +#define I2C_O_CLKH 0x4U // I2C Clock high-time divider +#define I2C_O_CNT 0x5U // I2C Data count +#define I2C_O_DRR 0x6U // I2C Data receive +#define I2C_O_SAR 0x7U // I2C Slave address +#define I2C_O_DXR 0x8U // I2C Data Transmit +#define I2C_O_MDR 0x9U // I2C Mode +#define I2C_O_ISRC 0xAU // I2C Interrupt Source +#define I2C_O_EMDR 0xBU // I2C Extended Mode +#define I2C_O_PSC 0xCU // I2C Prescaler +#define I2C_O_FFTX 0x20U // I2C FIFO Transmit +#define I2C_O_FFRX 0x21U // I2C FIFO Receive + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2COAR register +// +//************************************************************************************************* +#define I2C_OAR_OAR_S 0U +#define I2C_OAR_OAR_M 0x3FFU // I2C Own address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CIER register +// +//************************************************************************************************* +#define I2C_IER_ARBL 0x1U // Arbitration-lost interrupt enable +#define I2C_IER_NACK 0x2U // No-acknowledgment interrupt enable +#define I2C_IER_ARDY 0x4U // Register-access-ready interrupt enable +#define I2C_IER_RRDY 0x8U // Receive-data-ready interrupt enable +#define I2C_IER_XRDY 0x10U // Transmit-data-ready interrupt enable +#define I2C_IER_SCD 0x20U // Stop condition detected interrupt enable +#define I2C_IER_AAS 0x40U // Addressed as slave interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSTR register +// +//************************************************************************************************* +#define I2C_STR_ARBL 0x1U // Arbitration-lost interrupt flag bit +#define I2C_STR_NACK 0x2U // No-acknowledgment interrupt flag bit. +#define I2C_STR_ARDY 0x4U // Register-access-ready interrupt flag bit +#define I2C_STR_RRDY 0x8U // Receive-data-ready interrupt flag bit. +#define I2C_STR_XRDY 0x10U // Transmit-data-ready interrupt flag bit. +#define I2C_STR_SCD 0x20U // Stop condition detected bit. +#define I2C_STR_AD0 0x100U // Address 0 bits +#define I2C_STR_AAS 0x200U // Addressed-as-slave bit +#define I2C_STR_XSMT 0x400U // Transmit shift register empty bit. +#define I2C_STR_RSFULL 0x800U // Receive shift register full bit. +#define I2C_STR_BB 0x1000U // Bus busy bit. +#define I2C_STR_NACKSNT 0x2000U // NACK sent bit. +#define I2C_STR_SDIR 0x4000U // Slave direction bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDRR register +// +//************************************************************************************************* +#define I2C_DRR_DATA_S 0U +#define I2C_DRR_DATA_M 0xFFU // Receive data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSAR register +// +//************************************************************************************************* +#define I2C_SAR_SAR_S 0U +#define I2C_SAR_SAR_M 0x3FFU // Slave Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDXR register +// +//************************************************************************************************* +#define I2C_DXR_DATA_S 0U +#define I2C_DXR_DATA_M 0xFFU // Transmit data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CMDR register +// +//************************************************************************************************* +#define I2C_MDR_BC_S 0U +#define I2C_MDR_BC_M 0x7U // Bit count bits. +#define I2C_MDR_FDF 0x8U // Free Data Format +#define I2C_MDR_STB 0x10U // START Byte Mode +#define I2C_MDR_IRS 0x20U // I2C Module Reset +#define I2C_MDR_DLB 0x40U // Digital Loopback Mode +#define I2C_MDR_RM 0x80U // Repeat Mode +#define I2C_MDR_XA 0x100U // Expanded Address Mode +#define I2C_MDR_TRX 0x200U // Transmitter Mode +#define I2C_MDR_MST 0x400U // Master Mode +#define I2C_MDR_STP 0x800U // STOP Condition +#define I2C_MDR_STT 0x2000U // START condition bit +#define I2C_MDR_FREE 0x4000U // Debug Action +#define I2C_MDR_NACKMOD 0x8000U // NACK mode bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CISRC register +// +//************************************************************************************************* +#define I2C_ISRC_INTCODE_S 0U +#define I2C_ISRC_INTCODE_M 0x7U // Interrupt code bits. +#define I2C_ISRC_WRITE_ZEROS_S 8U +#define I2C_ISRC_WRITE_ZEROS_M 0xF00U // Always write all 0s to this field + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CEMDR register +// +//************************************************************************************************* +#define I2C_EMDR_BC 0x1U // Backwards compatibility mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CPSC register +// +//************************************************************************************************* +#define I2C_PSC_IPSC_S 0U +#define I2C_PSC_IPSC_M 0xFFU // I2C Prescaler Divide Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFTX register +// +//************************************************************************************************* +#define I2C_FFTX_TXFFIL_S 0U +#define I2C_FFTX_TXFFIL_M 0x1FU // Transmit FIFO Interrupt Level +#define I2C_FFTX_TXFFIENA 0x20U // Transmit FIFO Interrupt Enable +#define I2C_FFTX_TXFFINTCLR 0x40U // Transmit FIFO Interrupt Flag Clear +#define I2C_FFTX_TXFFINT 0x80U // Transmit FIFO Interrupt Flag +#define I2C_FFTX_TXFFST_S 8U +#define I2C_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define I2C_FFTX_TXFFRST 0x2000U // Transmit FIFO Reset +#define I2C_FFTX_I2CFFEN 0x4000U // Transmit FIFO Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFRX register +// +//************************************************************************************************* +#define I2C_FFRX_RXFFIL_S 0U +#define I2C_FFRX_RXFFIL_M 0x1FU // Receive FIFO Interrupt Level +#define I2C_FFRX_RXFFIENA 0x20U // Receive FIFO Interrupt Enable +#define I2C_FFRX_RXFFINTCLR 0x40U // Receive FIFO Interrupt Flag Clear +#define I2C_FFRX_RXFFINT 0x80U // Receive FIFO Interrupt Flag +#define I2C_FFRX_RXFFST_S 8U +#define I2C_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define I2C_FFRX_RXFFRST 0x2000U // Receive FIFO Reset + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_inputxbar.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_inputxbar.h new file mode 100644 index 0000000..a2567f2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_inputxbar.h @@ -0,0 +1,92 @@ +//########################################################################### +// +// FILE: hw_inputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_INPUTXBAR_H +#define HW_INPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INPUTSELECTLOCK register +// +//************************************************************************************************* +#define XBAR_INPUTSELECTLOCK_INPUT1SELECT 0x1U // Lock bit for INPUT1SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT2SELECT 0x2U // Lock bit for INPUT2SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT3SELECT 0x4U // Lock bit for INPUT3SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT4SELECT 0x8U // Lock bit for INPUT4SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT5SELECT 0x10U // Lock bit for INPUT5SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT6SELECT 0x20U // Lock bit for INPUT6SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT7SELECT 0x40U // Lock bit for INPUT7SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT8SELECT 0x80U // Lock bit for INPUT8SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT9SELECT 0x100U // Lock bit for INPUT9SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT10SELECT 0x200U // Lock bit for INPUT10SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT11SELECT 0x400U // Lock bit for INPUT11SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT12SELECT 0x800U // Lock bit for INPUT12SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT13SELECT 0x1000U // Lock bit for INPUT13SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT14SELECT 0x2000U // Lock bit for INPUT14SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT15SELECT 0x4000U // Lock bit for INPUT15SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT16SELECT 0x8000U // Lock bit for INPUT16SELECT Register + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_ints.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_ints.h new file mode 100644 index 0000000..d49c58d --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_ints.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: hw_ints.h +// +// TITLE: Definitions of interrupt numbers for use with interrupt.c. +// +//########################################################################### +// +// +//########################################################################### + +#ifndef HW_INTS_H +#define HW_INTS_H + +//***************************************************************************** +// +// PIE Interrupt Numbers +// +// 0x00FF = PIE Table Row # +// 0xFF00 = PIE Table Column # +// 0xFFFF0000 = PIE Vector ID +// +//***************************************************************************** + +// Lower PIE Group 1 +#define INT_ADCA1 0x00200101U // 1.1 - ADCA Interrupt 1 +#define INT_ADCB1 0x00210102U // 1.2 - ADCB Interrupt 1 +#define INT_ADCC1 0x00220103U // 1.3 - ADCC Interrupt 1 +#define INT_XINT1 0x00230104U // 1.4 - XINT1 Interrupt +#define INT_XINT2 0x00240105U // 1.5 - XINT2 Interrupt +#define INT_ADCD1 0x00250106U // 1.6 - ADCD Interrupt 1 +#define INT_TIMER0 0x00260107U // 1.7 - Timer 0 Interrupt +#define INT_WAKE 0x00270108U // 1.8 - Standby and Halt Wakeup Interrupt + +// Lower PIE Group 2 +#define INT_EPWM1_TZ 0x00280201U // 2.1 - ePWM1 Trip Zone Interrupt +#define INT_EPWM2_TZ 0x00290202U // 2.2 - ePWM2 Trip Zone Interrupt +#define INT_EPWM3_TZ 0x002A0203U // 2.3 - ePWM3 Trip Zone Interrupt +#define INT_EPWM4_TZ 0x002B0204U // 2.4 - ePWM4 Trip Zone Interrupt +#define INT_EPWM5_TZ 0x002C0205U // 2.5 - ePWM5 Trip Zone Interrupt +#define INT_EPWM6_TZ 0x002D0206U // 2.6 - ePWM6 Trip Zone Interrupt +#define INT_EPWM7_TZ 0x002E0207U // 2.7 - ePWM7 Trip Zone Interrupt +#define INT_EPWM8_TZ 0x002F0208U // 2.8 - ePWM8 Trip Zone Interrupt + +// Lower PIE Group 3 +#define INT_EPWM1 0x00300301U // 3.1 - ePWM1 Interrupt +#define INT_EPWM2 0x00310302U // 3.2 - ePWM2 Interrupt +#define INT_EPWM3 0x00320303U // 3.3 - ePWM3 Interrupt +#define INT_EPWM4 0x00330304U // 3.4 - ePWM4 Interrupt +#define INT_EPWM5 0x00340305U // 3.5 - ePWM5 Interrupt +#define INT_EPWM6 0x00350306U // 3.6 - ePWM6 Interrupt +#define INT_EPWM7 0x00360307U // 3.7 - ePWM7 Interrupt +#define INT_EPWM8 0x00370308U // 3.8 - ePWM8 Interrupt + +// Lower PIE Group 4 +#define INT_ECAP1 0x00380401U // 4.1 - eCAP1 Interrupt +#define INT_ECAP2 0x00390402U // 4.2 - eCAP2 Interrupt +#define INT_ECAP3 0x003A0403U // 4.3 - eCAP3 Interrupt +#define INT_ECAP4 0x003B0404U // 4.4 - eCAP4 Interrupt +#define INT_ECAP5 0x003C0405U // 4.5 - eCAP5 Interrupt +#define INT_ECAP6 0x003D0406U // 4.6 - eCAP6 Interrupt +// Lower PIE Group 5 +#define INT_EQEP1 0x00400501U // 5.1 - eQEP1 Interrupt +#define INT_EQEP2 0x00410502U // 5.2 - eQEP2 Interrupt +#define INT_EQEP3 0x00420503U // 5.3 - eQEP3 Interrupt +#define INT_CLB1 0x00440505U // 5.5 - CLB1 (Reconfigurable Logic) Interrupt +#define INT_CLB2 0x00450506U // 5.6 - CLB2 (Reconfigurable Logic) Interrupt +#define INT_CLB3 0x00460507U // 5.7 - CLB3 (Reconfigurable Logic) Interrupt +#define INT_CLB4 0x00470508U // 5.8 - CLB4 (Reconfigurable Logic) Interrupt + +// Lower PIE Group 6 +#define INT_SPIA_RX 0x00480601U // 6.1 - SPIA Receive Interrupt +#define INT_SPIA_TX 0x00490602U // 6.2 - SPIA Transmit Interrupt +#define INT_SPIB_RX 0x004A0603U // 6.3 - SPIB Receive Interrupt +#define INT_SPIB_TX 0x004B0604U // 6.4 - SPIB Transmit Interrupt +#define INT_MCBSPA_RX 0x004C0605U // 6.5 - McBSPA Receive Interrupt +#define INT_MCBSPA_TX 0x004D0606U // 6.6 - McBSPA Transmit Interrupt +#define INT_MCBSPB_RX 0x004E0607U // 6.7 - McBSPB Receive Interrupt +#define INT_MCBSPB_TX 0x004F0608U // 6.8 - McBSPB Transmit Interrupt + +// Lower PIE Group 7 +#define INT_DMA_CH1 0x00500701U // 7.1 - DMA Channel 1 Interrupt +#define INT_DMA_CH2 0x00510702U // 7.2 - DMA Channel 2 Interrupt +#define INT_DMA_CH3 0x00520703U // 7.3 - DMA Channel 3 Interrupt +#define INT_DMA_CH4 0x00530704U // 7.4 - DMA Channel 4 Interrupt +#define INT_DMA_CH5 0x00540705U // 7.5 - DMA Channel 5 Interrupt +#define INT_DMA_CH6 0x00550706U // 7.6 - DMA Channel 6 Interrupt + +// Lower PIE Group 8 +#define INT_I2CA 0x00580801U // 8.1 - I2CA Interrupt 1 +#define INT_I2CA_FIFO 0x00590802U // 8.2 - I2CA Interrupt 2 +#define INT_I2CB 0x005A0803U // 8.3 - I2CB Interrupt 1 +#define INT_I2CB_FIFO 0x005B0804U // 8.4 - I2CB Interrupt 2 +#define INT_SCIC_RX 0x005C0805U // 8.5 - SCIC Receive Interrupt +#define INT_SCIC_TX 0x005D0806U // 8.6 - SCIC Transmit Interrupt +#define INT_SCID_RX 0x005E0807U // 8.7 - SCID Receive Interrupt +#define INT_SCID_TX 0x005F0808U // 8.8 - SCID Transmit Interrupt + +// Lower PIE Group 9 +#define INT_SCIA_RX 0x00600901U // 9.1 - SCIA Receive Interrupt +#define INT_SCIA_TX 0x00610902U // 9.2 - SCIA Transmit Interrupt +#define INT_SCIB_RX 0x00620903U // 9.3 - SCIB Receive Interrupt +#define INT_SCIB_TX 0x00630904U // 9.4 - SCIB Transmit Interrupt +#define INT_CANA0 0x00640905U // 9.5 - CANA Interrupt 0 +#define INT_CANA1 0x00650906U // 9.6 - CANA Interrupt 1 +#define INT_CANB0 0x00660907U // 9.7 - CANB Interrupt 0 +#define INT_CANB1 0x00670908U // 9.8 - CANB Interrupt 1 + +// Lower PIE Group 10 +#define INT_ADCA_EVT 0x00680A01U // 10.1 - ADCA Event Interrupt +#define INT_ADCA2 0x00690A02U // 10.2 - ADCA Interrupt 2 +#define INT_ADCA3 0x006A0A03U // 10.3 - ADCA Interrupt 3 +#define INT_ADCA4 0x006B0A04U // 10.4 - ADCA Interrupt 4 +#define INT_ADCB_EVT 0x006C0A05U // 10.5 - ADCB Event Interrupt +#define INT_ADCB2 0x006D0A06U // 10.6 - ADCB Interrupt 2 +#define INT_ADCB3 0x006E0A07U // 10.7 - ADCB Interrupt 3 +#define INT_ADCB4 0x006F0A08U // 10.8 - ADCB Interrupt 4 + +// Lower PIE Group 11 +#define INT_CLA1_1 0x00700B01U // 11.1 - CLA1 Interrupt 1 +#define INT_CLA1_2 0x00710B02U // 11.2 - CLA1 Interrupt 2 +#define INT_CLA1_3 0x00720B03U // 11.3 - CLA1 Interrupt 3 +#define INT_CLA1_4 0x00730B04U // 11.4 - CLA1 Interrupt 4 +#define INT_CLA1_5 0x00740B05U // 11.5 - CLA1 Interrupt 5 +#define INT_CLA1_6 0x00750B06U // 11.6 - CLA1 Interrupt 6 +#define INT_CLA1_7 0x00760B07U // 11.7 - CLA1 Interrupt 7 +#define INT_CLA1_8 0x00770B08U // 11.8 - CLA1 Interrupt 8 + +// Lower PIE Group 12 +#define INT_XINT3 0x00780C01U // 12.1 - XINT3 Interrupt +#define INT_XINT4 0x00790C02U // 12.2 - XINT4 Interrupt +#define INT_XINT5 0x007A0C03U // 12.3 - XINT5 Interrupt +#define INT_PBIST 0x007B0C04U // 12.4 - PBIST Interrupt +#define INT_FMC 0x007C0C05U // 12.5 - Flash Wrapper Operation Done Interrupt +#define INT_VCU 0x007D0C06U // 12.6 - VCU Interrupt +#define INT_FPU_OVERFLOW 0x007E0C07U // 12.7 - FPU Overflow Interrupt +#define INT_FPU_UNDERFLOW 0x007F0C08U // 12.8 - FPU Underflow Interrupt + +// Upper PIE Group 1 +#define INT_IPC_0 0x0084010DU // 1.13 - IPC Interrupt 1 +#define INT_IPC_1 0x0085010EU // 1.14 - IPC Interrupt 2 +#define INT_IPC_2 0x0086010FU // 1.15 - IPC Interrupt 3 +#define INT_IPC_3 0x00870110U // 1.16 - IPC Interrupt 4 + +// Upper PIE Group 2 +#define INT_EPWM9_TZ 0x00880209U // 2.9 - ePWM9 Trip Zone Interrupt +#define INT_EPWM10_TZ 0x0089020AU // 2.10 - ePWM10 Trip Zone Interrupt +#define INT_EPWM11_TZ 0x008A020BU // 2.11 - ePWM11 Trip Zone Interrupt +#define INT_EPWM12_TZ 0x008B020CU // 2.12 - ePWM12 Trip Zone Interrupt + +// Upper PIE Group 3 +#define INT_EPWM9 0x00900309U // 3.9 - ePWM9 Interrupt +#define INT_EPWM10 0x0091030AU // 3.10 - ePWM10 Interrupt +#define INT_EPWM11 0x0092030BU // 3.11 - ePWM11 Interrupt +#define INT_EPWM12 0x0093030CU // 3.12 - ePWM12 Interrupt + +// Upper PIE Group 5 +#define INT_SD1 0x00A00509U // 5.9 - SD1 Interrupt +#define INT_SD2 0x00A1050AU // 5.10 - SD2 Interrupt + +// Upper PIE Group 6 +#define INT_SPIC_RX 0x00A80609U // 6.9 - SPIC Receive Interrupt +#define INT_SPIC_TX 0x00A9060AU // 6.10 - SPIC Transmit Interrupt + +// Upper PIE Group 8 +#define INT_UPPA 0x00BE080FU // 8.15 - uPPA Interrupt + +// Upper PIE Group 9 +#define INT_USBA 0x00C6090FU // 9.15 - USBA Interrupt + +// Upper PIE Group 10 +#define INT_ADCC_EVT 0x00C80A09U // 10.9 - ADCC Event Interrupt +#define INT_ADCC2 0x00C90A0AU // 10.10 - ADCC Interrupt 2 +#define INT_ADCC3 0x00CA0A0BU // 10.11 - ADCC Interrupt 3 +#define INT_ADCC4 0x00CB0A0CU // 10.12 - ADCC Interrupt 4 +#define INT_ADCD_EVT 0x00CC0A0DU // 10.13 - ADCD Event Interrupt +#define INT_ADCD2 0x00CD0A0EU // 10.14 - ADCD Interrupt 2 +#define INT_ADCD3 0x00CE0A0FU // 10.15 - ADCD Interrupt 3 +#define INT_ADCD4 0x00CF0A10U // 10.16 - ADCD Interrupt 4 + +// Upper PIE Group 12 +#define INT_EMIF_ERROR 0x00D80C09U // 12.9 - EMIF Error Interrupt +#define INT_RAM_CORR_ERR 0x00D90C0AU // 12.10 - RAM Correctable Error Interrupt +#define INT_FLASH_CORR_ERR 0x00DA0C0BU // 12.11 - Flash Correctable Error Interrupt +#define INT_RAM_ACC_VIOL 0x00DB0C0CU // 12.12 - RAM Access Violation Interrupt +#define INT_SYS_PLL_SLIP 0x00DC0C0DU // 12.13 - System PLL Slip Interrupt +#define INT_AUX_PLL_SLIP 0x00DD0C0EU // 12.14 - Auxiliary PLL Slip Interrupt +#define INT_CLA_OVERFLOW 0x00DE0C0FU // 12.15 - CLA Overflow Interrupt +#define INT_CLA_UNDERFLOW 0x00DF0C10U // 12.16 - CLA Underflow Interrupt + +// Other interrupts +#define INT_TIMER1 0x000D0000U // CPU Timer 1 Interrupt +#define INT_TIMER2 0x000E0000U // CPU Timer 2 Interrupt +#define INT_DATALOG 0x000F0000U // Datalogging Interrupt +#define INT_RTOS 0x00100000U // RTOS Interrupt +#define INT_EMU 0x00110000U // Emulation Interrupt +#define INT_NMI 0x00120000U // Non-Maskable Interrupt +#define INT_ILLEGAL 0x00130000U // Illegal Operation Trap +#define INT_USER1 0x00140000U // User Defined Trap 1 +#define INT_USER2 0x00150000U // User Defined Trap 2 +#define INT_USER3 0x00160000U // User Defined Trap 3 +#define INT_USER4 0x00170000U // User Defined Trap 4 +#define INT_USER5 0x00180000U // User Defined Trap 5 +#define INT_USER6 0x00190000U // User Defined Trap 6 +#define INT_USER7 0x001A0000U // User Defined Trap 7 +#define INT_USER8 0x001B0000U // User Defined Trap 8 +#define INT_USER9 0x001C0000U // User Defined Trap 9 +#define INT_USER10 0x001D0000U // User Defined Trap 10 +#define INT_USER11 0x001E0000U // User Defined Trap 11 +#define INT_USER12 0x001F0000U // User Defined Trap 12 + +#endif // HW_INTS_H diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_ipc.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_ipc.h new file mode 100644 index 0000000..e99715f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_ipc.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: hw_ipc.h +// +// TITLE: Definitions for the IPC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_IPC_H +#define HW_IPC_H + +//***************************************************************************** +// +// The following are defines for the IPC register offsets +// +//***************************************************************************** +#define IPC_O_ACK 0x0U // IPC incoming flag clear + // (acknowledge) register +#define IPC_O_STS 0x2U // IPC incoming flag status + // register +#define IPC_O_SET 0x4U // IPC remote flag set register +#define IPC_O_CLR 0x6U // IPC remote flag clear + // register +#define IPC_O_FLG 0x8U // IPC remote flag status + // register +#define IPC_O_COUNTERL 0xCU // IPC Counter Low Register +#define IPC_O_COUNTERH 0xEU // IPC Counter High Register +#ifndef CPU2 +#define IPC_O_SENDCOM 0x10U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x12U // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x14U // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x16U // Remote to Local IPC Reply + // Data Register +#define IPC_O_RECVCOM 0x18U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x1AU // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x1CU // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x1EU // Local to Remote IPC Reply + // Data Register +#else +#define IPC_O_RECVCOM 0x10U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x12U // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x14U // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x16U // Local to Remote IPC Reply + // Data Register +#define IPC_O_SENDCOM 0x18U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x1AU // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x1CU // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x1EU // Remote to Local IPC Reply + // Data Register +#endif +#define IPC_O_BOOTSTS 0x20U // CPU2 to CPU1 IPC Boot Status + // Register +#define IPC_O_BOOTMODE 0x22U // CPU1 to CPU2 IPC Boot Mode + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCACK register +// +//***************************************************************************** +#define IPC_ACK_IPC0 0x1U // Local IPC Flag 0 + // Acknowledgement +#define IPC_ACK_IPC1 0x2U // Local IPC Flag 1 + // Acknowledgement +#define IPC_ACK_IPC2 0x4U // Local IPC Flag 2 + // Acknowledgement +#define IPC_ACK_IPC3 0x8U // Local IPC Flag 3 + // Acknowledgement +#define IPC_ACK_IPC4 0x10U // Local IPC Flag 4 + // Acknowledgement +#define IPC_ACK_IPC5 0x20U // Local IPC Flag 5 + // Acknowledgement +#define IPC_ACK_IPC6 0x40U // Local IPC Flag 6 + // Acknowledgement +#define IPC_ACK_IPC7 0x80U // Local IPC Flag 7 + // Acknowledgement +#define IPC_ACK_IPC8 0x100U // Local IPC Flag 8 + // Acknowledgement +#define IPC_ACK_IPC9 0x200U // Local IPC Flag 9 + // Acknowledgement +#define IPC_ACK_IPC10 0x400U // Local IPC Flag 10 + // Acknowledgement +#define IPC_ACK_IPC11 0x800U // Local IPC Flag 11 + // Acknowledgement +#define IPC_ACK_IPC12 0x1000U // Local IPC Flag 12 + // Acknowledgement +#define IPC_ACK_IPC13 0x2000U // Local IPC Flag 13 + // Acknowledgement +#define IPC_ACK_IPC14 0x4000U // Local IPC Flag 14 + // Acknowledgement +#define IPC_ACK_IPC15 0x8000U // Local IPC Flag 15 + // Acknowledgement +#define IPC_ACK_IPC16 0x10000U // Local IPC Flag 16 + // Acknowledgement +#define IPC_ACK_IPC17 0x20000U // Local IPC Flag 17 + // Acknowledgement +#define IPC_ACK_IPC18 0x40000U // Local IPC Flag 18 + // Acknowledgement +#define IPC_ACK_IPC19 0x80000U // Local IPC Flag 19 + // Acknowledgement +#define IPC_ACK_IPC20 0x100000U // Local IPC Flag 20 + // Acknowledgement +#define IPC_ACK_IPC21 0x200000U // Local IPC Flag 21 + // Acknowledgement +#define IPC_ACK_IPC22 0x400000U // Local IPC Flag 22 + // Acknowledgement +#define IPC_ACK_IPC23 0x800000U // Local IPC Flag 23 + // Acknowledgement +#define IPC_ACK_IPC24 0x1000000U // Local IPC Flag 24 + // Acknowledgement +#define IPC_ACK_IPC25 0x2000000U // Local IPC Flag 25 + // Acknowledgement +#define IPC_ACK_IPC26 0x4000000U // Local IPC Flag 26 + // Acknowledgement +#define IPC_ACK_IPC27 0x8000000U // Local IPC Flag 27 + // Acknowledgement +#define IPC_ACK_IPC28 0x10000000U // Local IPC Flag 28 + // Acknowledgement +#define IPC_ACK_IPC29 0x20000000U // Local IPC Flag 29 + // Acknowledgement +#define IPC_ACK_IPC30 0x40000000U // Local IPC Flag 30 + // Acknowledgement +#define IPC_ACK_IPC31 0x80000000U // Local IPC Flag 31 + // Acknowledgement + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSTS register +// +//***************************************************************************** +#define IPC_STS_IPC0 0x1U // Local IPC Flag 0 Status +#define IPC_STS_IPC1 0x2U // Local IPC Flag 1 Status +#define IPC_STS_IPC2 0x4U // Local IPC Flag 2 Status +#define IPC_STS_IPC3 0x8U // Local IPC Flag 3 Status +#define IPC_STS_IPC4 0x10U // Local IPC Flag 4 Status +#define IPC_STS_IPC5 0x20U // Local IPC Flag 5 Status +#define IPC_STS_IPC6 0x40U // Local IPC Flag 6 Status +#define IPC_STS_IPC7 0x80U // Local IPC Flag 7 Status +#define IPC_STS_IPC8 0x100U // Local IPC Flag 8 Status +#define IPC_STS_IPC9 0x200U // Local IPC Flag 9 Status +#define IPC_STS_IPC10 0x400U // Local IPC Flag 10 Status +#define IPC_STS_IPC11 0x800U // Local IPC Flag 11 Status +#define IPC_STS_IPC12 0x1000U // Local IPC Flag 12 Status +#define IPC_STS_IPC13 0x2000U // Local IPC Flag 13 Status +#define IPC_STS_IPC14 0x4000U // Local IPC Flag 14 Status +#define IPC_STS_IPC15 0x8000U // Local IPC Flag 15 Status +#define IPC_STS_IPC16 0x10000U // Local IPC Flag 16 Status +#define IPC_STS_IPC17 0x20000U // Local IPC Flag 17 Status +#define IPC_STS_IPC18 0x40000U // Local IPC Flag 18 Status +#define IPC_STS_IPC19 0x80000U // Local IPC Flag 19 Status +#define IPC_STS_IPC20 0x100000U // Local IPC Flag 20 Status +#define IPC_STS_IPC21 0x200000U // Local IPC Flag 21 Status +#define IPC_STS_IPC22 0x400000U // Local IPC Flag 22 Status +#define IPC_STS_IPC23 0x800000U // Local IPC Flag 23 Status +#define IPC_STS_IPC24 0x1000000U // Local IPC Flag 24 Status +#define IPC_STS_IPC25 0x2000000U // Local IPC Flag 25 Status +#define IPC_STS_IPC26 0x4000000U // Local IPC Flag 26 Status +#define IPC_STS_IPC27 0x8000000U // Local IPC Flag 27 Status +#define IPC_STS_IPC28 0x10000000U // Local IPC Flag 28 Status +#define IPC_STS_IPC29 0x20000000U // Local IPC Flag 29 Status +#define IPC_STS_IPC30 0x40000000U // Local IPC Flag 30 Status +#define IPC_STS_IPC31 0x80000000U // Local IPC Flag 31 Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSET register +// +//***************************************************************************** +#define IPC_SET_IPC0 0x1U // Set Remote IPC0 Flag +#define IPC_SET_IPC1 0x2U // Set Remote IPC1 Flag +#define IPC_SET_IPC2 0x4U // Set Remote IPC2 Flag +#define IPC_SET_IPC3 0x8U // Set Remote IPC3 Flag +#define IPC_SET_IPC4 0x10U // Set Remote IPC4 Flag +#define IPC_SET_IPC5 0x20U // Set Remote IPC5 Flag +#define IPC_SET_IPC6 0x40U // Set Remote IPC6 Flag +#define IPC_SET_IPC7 0x80U // Set Remote IPC7 Flag +#define IPC_SET_IPC8 0x100U // Set Remote IPC8 Flag +#define IPC_SET_IPC9 0x200U // Set Remote IPC9 Flag +#define IPC_SET_IPC10 0x400U // Set Remote IPC10 Flag +#define IPC_SET_IPC11 0x800U // Set Remote IPC11 Flag +#define IPC_SET_IPC12 0x1000U // Set Remote IPC12 Flag +#define IPC_SET_IPC13 0x2000U // Set Remote IPC13 Flag +#define IPC_SET_IPC14 0x4000U // Set Remote IPC14 Flag +#define IPC_SET_IPC15 0x8000U // Set Remote IPC15 Flag +#define IPC_SET_IPC16 0x10000U // Set Remote IPC16 Flag +#define IPC_SET_IPC17 0x20000U // Set Remote IPC17 Flag +#define IPC_SET_IPC18 0x40000U // Set Remote IPC18 Flag +#define IPC_SET_IPC19 0x80000U // Set Remote IPC19 Flag +#define IPC_SET_IPC20 0x100000U // Set Remote IPC20 Flag +#define IPC_SET_IPC21 0x200000U // Set Remote IPC21 Flag +#define IPC_SET_IPC22 0x400000U // Set Remote IPC22 Flag +#define IPC_SET_IPC23 0x800000U // Set Remote IPC23 Flag +#define IPC_SET_IPC24 0x1000000U // Set Remote IPC24 Flag +#define IPC_SET_IPC25 0x2000000U // Set Remote IPC25 Flag +#define IPC_SET_IPC26 0x4000000U // Set Remote IPC26 Flag +#define IPC_SET_IPC27 0x8000000U // Set Remote IPC27 Flag +#define IPC_SET_IPC28 0x10000000U // Set Remote IPC28 Flag +#define IPC_SET_IPC29 0x20000000U // Set Remote IPC29 Flag +#define IPC_SET_IPC30 0x40000000U // Set Remote IPC30 Flag +#define IPC_SET_IPC31 0x80000000U // Set Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCCLR register +// +//***************************************************************************** +#define IPC_CLR_IPC0 0x1U // Clear Remote IPC0 Flag +#define IPC_CLR_IPC1 0x2U // Clear Remote IPC1 Flag +#define IPC_CLR_IPC2 0x4U // Clear Remote IPC2 Flag +#define IPC_CLR_IPC3 0x8U // Clear Remote IPC3 Flag +#define IPC_CLR_IPC4 0x10U // Clear Remote IPC4 Flag +#define IPC_CLR_IPC5 0x20U // Clear Remote IPC5 Flag +#define IPC_CLR_IPC6 0x40U // Clear Remote IPC6 Flag +#define IPC_CLR_IPC7 0x80U // Clear Remote IPC7 Flag +#define IPC_CLR_IPC8 0x100U // Clear Remote IPC8 Flag +#define IPC_CLR_IPC9 0x200U // Clear Remote IPC9 Flag +#define IPC_CLR_IPC10 0x400U // Clear Remote IPC10 Flag +#define IPC_CLR_IPC11 0x800U // Clear Remote IPC11 Flag +#define IPC_CLR_IPC12 0x1000U // Clear Remote IPC12 Flag +#define IPC_CLR_IPC13 0x2000U // Clear Remote IPC13 Flag +#define IPC_CLR_IPC14 0x4000U // Clear Remote IPC14 Flag +#define IPC_CLR_IPC15 0x8000U // Clear Remote IPC15 Flag +#define IPC_CLR_IPC16 0x10000U // Clear Remote IPC16 Flag +#define IPC_CLR_IPC17 0x20000U // Clear Remote IPC17 Flag +#define IPC_CLR_IPC18 0x40000U // Clear Remote IPC18 Flag +#define IPC_CLR_IPC19 0x80000U // Clear Remote IPC19 Flag +#define IPC_CLR_IPC20 0x100000U // Clear Remote IPC20 Flag +#define IPC_CLR_IPC21 0x200000U // Clear Remote IPC21 Flag +#define IPC_CLR_IPC22 0x400000U // Clear Remote IPC22 Flag +#define IPC_CLR_IPC23 0x800000U // Clear Remote IPC23 Flag +#define IPC_CLR_IPC24 0x1000000U // Clear Remote IPC24 Flag +#define IPC_CLR_IPC25 0x2000000U // Clear Remote IPC25 Flag +#define IPC_CLR_IPC26 0x4000000U // Clear Remote IPC26 Flag +#define IPC_CLR_IPC27 0x8000000U // Clear Remote IPC27 Flag +#define IPC_CLR_IPC28 0x10000000U // Clear Remote IPC28 Flag +#define IPC_CLR_IPC29 0x20000000U // Clear Remote IPC29 Flag +#define IPC_CLR_IPC30 0x40000000U // Clear Remote IPC30 Flag +#define IPC_CLR_IPC31 0x80000000U // Clear Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCFLG register +// +//***************************************************************************** +#define IPC_FLG_IPC0 0x1U // Remote IPC0 Flag Status +#define IPC_FLG_IPC1 0x2U // Remote IPC1 Flag Status +#define IPC_FLG_IPC2 0x4U // Remote IPC2 Flag Status +#define IPC_FLG_IPC3 0x8U // Remote IPC3 Flag Status +#define IPC_FLG_IPC4 0x10U // Remote IPC4 Flag Status +#define IPC_FLG_IPC5 0x20U // Remote IPC5 Flag Status +#define IPC_FLG_IPC6 0x40U // Remote IPC6 Flag Status +#define IPC_FLG_IPC7 0x80U // Remote IPC7 Flag Status +#define IPC_FLG_IPC8 0x100U // Remote IPC8 Flag Status +#define IPC_FLG_IPC9 0x200U // Remote IPC9 Flag Status +#define IPC_FLG_IPC10 0x400U // Remote IPC10 Flag Status +#define IPC_FLG_IPC11 0x800U // Remote IPC11 Flag Status +#define IPC_FLG_IPC12 0x1000U // Remote IPC12 Flag Status +#define IPC_FLG_IPC13 0x2000U // Remote IPC13 Flag Status +#define IPC_FLG_IPC14 0x4000U // Remote IPC14 Flag Status +#define IPC_FLG_IPC15 0x8000U // Remote IPC15 Flag Status +#define IPC_FLG_IPC16 0x10000U // Remote IPC16 Flag Status +#define IPC_FLG_IPC17 0x20000U // Remote IPC17 Flag Status +#define IPC_FLG_IPC18 0x40000U // Remote IPC18 Flag Status +#define IPC_FLG_IPC19 0x80000U // Remote IPC19 Flag Status +#define IPC_FLG_IPC20 0x100000U // Remote IPC20 Flag Status +#define IPC_FLG_IPC21 0x200000U // Remote IPC21 Flag Status +#define IPC_FLG_IPC22 0x400000U // Remote IPC22 Flag Status +#define IPC_FLG_IPC23 0x800000U // Remote IPC23 Flag Status +#define IPC_FLG_IPC24 0x1000000U // Remote IPC24 Flag Status +#define IPC_FLG_IPC25 0x2000000U // Remote IPC25 Flag Status +#define IPC_FLG_IPC26 0x4000000U // Remote IPC26 Flag Status +#define IPC_FLG_IPC27 0x8000000U // Remote IPC27 Flag Status +#define IPC_FLG_IPC28 0x10000000U // Remote IPC28 Flag Status +#define IPC_FLG_IPC29 0x20000000U // Remote IPC29 Flag Status +#define IPC_FLG_IPC30 0x40000000U // Remote IPC30 Flag Status +#define IPC_FLG_IPC31 0x80000000U // Remote IPC31 Flag Status +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_mcbsp.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_mcbsp.h new file mode 100644 index 0000000..814055f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_mcbsp.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_mcbsp.h +// +// TITLE: Definitions for the MCBSP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MCBSP_H +#define HW_MCBSP_H + +//************************************************************************************************* +// +// The following are defines for the MCBSP register offsets +// +//************************************************************************************************* +#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16 +#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0 +#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16 +#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0 +#define MCBSP_O_SPCR2 0x4U // Serial port control register 2 +#define MCBSP_O_SPCR1 0x5U // Serial port control register 1 +#define MCBSP_O_RCR2 0x6U // Receive Control register 2 +#define MCBSP_O_RCR1 0x7U // Receive Control register 1 +#define MCBSP_O_XCR2 0x8U // Transmit Control register 2 +#define MCBSP_O_XCR1 0x9U // Transmit Control register 1 +#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2 +#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1 +#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2 +#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1 +#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A +#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B +#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A +#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B +#define MCBSP_O_PCR 0x12U // Pin Control register +#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C +#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D +#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C +#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D +#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E +#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F +#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E +#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F +#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G +#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H +#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G +#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H +#define MCBSP_O_MFFINT 0x23U // Interrupt enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR2 register +// +//************************************************************************************************* +#define MCBSP_DRR2_HWLB_S 0U +#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DRR2_HWHB_S 8U +#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR1 register +// +//************************************************************************************************* +#define MCBSP_DRR1_LWLB_S 0U +#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DRR1_LWHB_S 8U +#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR2 register +// +//************************************************************************************************* +#define MCBSP_DXR2_HWLB_S 0U +#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DXR2_HWHB_S 8U +#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR1 register +// +//************************************************************************************************* +#define MCBSP_DXR1_LWLB_S 0U +#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DXR1_LWHB_S 8U +#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR2 register +// +//************************************************************************************************* +#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset +#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready +#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty +#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag +#define MCBSP_SPCR2_XINTM_S 4U +#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits +#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset +#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset +#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit +#define MCBSP_SPCR2_FREE 0x200U // FREE bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR1 register +// +//************************************************************************************************* +#define MCBSP_SPCR1_RRST 0x1U // Receiver reset +#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready +#define MCBSP_SPCR1_RFULL 0x4U // Receiver full +#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag +#define MCBSP_SPCR1_RINTM_S 4U +#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits +#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable +#define MCBSP_SPCR1_CLKSTP_S 11U +#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode +#define MCBSP_SPCR1_RJUST_S 13U +#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode +#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR2 register +// +//************************************************************************************************* +#define MCBSP_RCR2_RDATDLY_S 0U +#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay +#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore +#define MCBSP_RCR2_RCOMPAND_S 3U +#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects +#define MCBSP_RCR2_RWDLEN2_S 5U +#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2 +#define MCBSP_RCR2_RFRLEN2_S 8U +#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2 +#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR1 register +// +//************************************************************************************************* +#define MCBSP_RCR1_RWDLEN1_S 5U +#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1 +#define MCBSP_RCR1_RFRLEN1_S 8U +#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR2 register +// +//************************************************************************************************* +#define MCBSP_XCR2_XDATDLY_S 0U +#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay +#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore +#define MCBSP_XCR2_XCOMPAND_S 3U +#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects +#define MCBSP_XCR2_XWDLEN2_S 5U +#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2 +#define MCBSP_XCR2_XFRLEN2_S 8U +#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2 +#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR1 register +// +//************************************************************************************************* +#define MCBSP_XCR1_XWDLEN1_S 5U +#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1 +#define MCBSP_XCR1_XFRLEN1_S 8U +#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR2 register +// +//************************************************************************************************* +#define MCBSP_SRGR2_FPER_S 0U +#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period +#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode +#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode +#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR1 register +// +//************************************************************************************************* +#define MCBSP_SRGR1_CLKGDV_S 0U +#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider +#define MCBSP_SRGR1_FWID_S 8U +#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR2 register +// +//************************************************************************************************* +#define MCBSP_MCR2_XMCM_S 0U +#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay +#define MCBSP_MCR2_XCBLK_S 2U +#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore +#define MCBSP_MCR2_XPABLK_S 5U +#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects +#define MCBSP_MCR2_XPBBLK_S 7U +#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2 +#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR1 register +// +//************************************************************************************************* +#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode +#define MCBSP_MCR1_RCBLK_S 2U +#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block +#define MCBSP_MCR1_RPABLK_S 5U +#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block +#define MCBSP_MCR1_RPBBLK_S 7U +#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block +#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCR register +// +//************************************************************************************************* +#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity +#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity +#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity +#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity +#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection +#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode +#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode. +#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode +#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MFFINT register +// +//************************************************************************************************* +#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt +#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_memcfg.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_memcfg.h new file mode 100644 index 0000000..d5d7e8c --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_memcfg.h @@ -0,0 +1,870 @@ +//########################################################################### +// +// FILE: hw_memcfg.h +// +// TITLE: Definitions for the MEMCFG registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMCFG_H +#define HW_MEMCFG_H + +//************************************************************************************************* +// +// The following are defines for the MEMCFG register offsets +// +//************************************************************************************************* +#define MEMCFG_O_DXLOCK 0x0U // Dedicated RAM Config Lock Register +#define MEMCFG_O_DXCOMMIT 0x2U // Dedicated RAM Config Lock Commit Register +#define MEMCFG_O_DXACCPROT0 0x8U // Dedicated RAM Config Register +#define MEMCFG_O_DXTEST 0x10U // Dedicated RAM TEST Register +#define MEMCFG_O_DXINIT 0x12U // Dedicated RAM Init Register +#define MEMCFG_O_DXINITDONE 0x14U // Dedicated RAM InitDone Status Register +#define MEMCFG_O_LSXLOCK 0x20U // Local Shared RAM Config Lock Register +#define MEMCFG_O_LSXCOMMIT 0x22U // Local Shared RAM Config Lock Commit Register +#define MEMCFG_O_LSXMSEL 0x24U // Local Shared RAM Master Sel Register +#define MEMCFG_O_LSXCLAPGM 0x26U // Local Shared RAM Prog/Exe control Register +#define MEMCFG_O_LSXACCPROT0 0x28U // Local Shared RAM Config Register 0 +#define MEMCFG_O_LSXACCPROT1 0x2AU // Local Shared RAM Config Register 1 +#define MEMCFG_O_LSXTEST 0x30U // Local Shared RAM TEST Register +#define MEMCFG_O_LSXINIT 0x32U // Local Shared RAM Init Register +#define MEMCFG_O_LSXINITDONE 0x34U // Local Shared RAM InitDone Status Register +#define MEMCFG_O_GSXLOCK 0x40U // Global Shared RAM Config Lock Register +#define MEMCFG_O_GSXCOMMIT 0x42U // Global Shared RAM Config Lock Commit Register +#define MEMCFG_O_GSXMSEL 0x44U // Global Shared RAM Master Sel Register +#define MEMCFG_O_GSXACCPROT0 0x48U // Global Shared RAM Config Register 0 +#define MEMCFG_O_GSXACCPROT1 0x4AU // Global Shared RAM Config Register 1 +#define MEMCFG_O_GSXACCPROT2 0x4CU // Global Shared RAM Config Register 2 +#define MEMCFG_O_GSXACCPROT3 0x4EU // Global Shared RAM Config Register 3 +#define MEMCFG_O_GSXTEST 0x50U // Global Shared RAM TEST Register +#define MEMCFG_O_GSXINIT 0x52U // Global Shared RAM Init Register +#define MEMCFG_O_GSXINITDONE 0x54U // Global Shared RAM InitDone Status Register +#define MEMCFG_O_MSGXTEST 0x70U // Message RAM TEST Register +#define MEMCFG_O_MSGXINIT 0x72U // Message RAM Init Register +#define MEMCFG_O_MSGXINITDONE 0x74U // Message RAM InitDone Status Register + +#define MEMCFG_O_EMIF1LOCK 0x0U // EMIF1 Config Lock Register +#define MEMCFG_O_EMIF1COMMIT 0x2U // EMIF1 Config Lock Commit Register +#define MEMCFG_O_EMIF1MSEL 0x4U // EMIF1 Master Sel Register +#define MEMCFG_O_EMIF1ACCPROT0 0x8U // EMIF1 Config Register 0 + +#define MEMCFG_O_EMIF2LOCK 0x0U // EMIF2 Config Lock Register +#define MEMCFG_O_EMIF2COMMIT 0x2U // EMIF2 Config Lock Commit Register +#define MEMCFG_O_EMIF2ACCPROT0 0x8U // EMIF2 Config Register 0 + +#define MEMCFG_O_NMAVFLG 0x0U // Non-Master Access Violation Flag Register +#define MEMCFG_O_NMAVSET 0x2U // Non-Master Access Violation Flag Set Register +#define MEMCFG_O_NMAVCLR 0x4U // Non-Master Access Violation Flag Clear Register +#define MEMCFG_O_NMAVINTEN 0x6U // Non-Master Access Violation Interrupt Enable Register +#define MEMCFG_O_NMCPURDAVADDR 0x8U // Non-Master CPU Read Access Violation Address +#define MEMCFG_O_NMCPUWRAVADDR 0xAU // Non-Master CPU Write Access Violation Address +#define MEMCFG_O_NMCPUFAVADDR 0xCU // Non-Master CPU Fetch Access Violation Address +#define MEMCFG_O_NMDMAWRAVADDR 0xEU // Non-Master DMA Write Access Violation Address +#define MEMCFG_O_NMCLA1RDAVADDR 0x10U // Non-Master CLA1 Read Access Violation Address +#define MEMCFG_O_NMCLA1WRAVADDR 0x12U // Non-Master CLA1 Write Access Violation Address +#define MEMCFG_O_NMCLA1FAVADDR 0x14U // Non-Master CLA1 Fetch Access Violation Address +#define MEMCFG_O_MAVFLG 0x20U // Master Access Violation Flag Register +#define MEMCFG_O_MAVSET 0x22U // Master Access Violation Flag Set Register +#define MEMCFG_O_MAVCLR 0x24U // Master Access Violation Flag Clear Register +#define MEMCFG_O_MAVINTEN 0x26U // Master Access Violation Interrupt Enable Register +#define MEMCFG_O_MCPUFAVADDR 0x28U // Master CPU Fetch Access Violation Address +#define MEMCFG_O_MCPUWRAVADDR 0x2AU // Master CPU Write Access Violation Address +#define MEMCFG_O_MDMAWRAVADDR 0x2CU // Master DMA Write Access Violation Address + +#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register +#define MEMCFG_O_UCERRSET 0x2U // Uncorrectable Error Flag Set Register +#define MEMCFG_O_UCERRCLR 0x4U // Uncorrectable Error Flag Clear Register +#define MEMCFG_O_UCCPUREADDR 0x6U // Uncorrectable CPU Read Error Address +#define MEMCFG_O_UCDMAREADDR 0x8U // Uncorrectable DMA Read Error Address +#define MEMCFG_O_UCCLA1READDR 0xAU // Uncorrectable CLA1 Read Error Address +#define MEMCFG_O_CERRFLG 0x20U // Correctable Error Flag Register +#define MEMCFG_O_CERRSET 0x22U // Correctable Error Flag Set Register +#define MEMCFG_O_CERRCLR 0x24U // Correctable Error Flag Clear Register +#define MEMCFG_O_CCPUREADDR 0x26U // Correctable CPU Read Error Address +#define MEMCFG_O_CERRCNT 0x2EU // Correctable Error Count Register +#define MEMCFG_O_CERRTHRES 0x30U // Correctable Error Threshold Value Register +#define MEMCFG_O_CEINTFLG 0x32U // Correctable Error Interrupt Flag Status Register +#define MEMCFG_O_CEINTCLR 0x34U // Correctable Error Interrupt Flag Clear Register +#define MEMCFG_O_CEINTSET 0x36U // Correctable Error Interrupt Flag Set Register +#define MEMCFG_O_CEINTEN 0x38U // Correctable Error Interrupt Enable Register + +#define MEMCFG_O_ROMWAITSTATE 0x0U // ROM Wait State Configuration Register + +#define MEMCFG_O_ROMPREFETCH 0x0U // ROM Prefetch Configuration Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxLOCK register +// +//************************************************************************************************* +#define MEMCFG_DXLOCK_LOCK_D0 0x4U // D0 RAM access protection and master select fields lock + // bit +#define MEMCFG_DXLOCK_LOCK_D1 0x8U // D1 RAM access protection and master select fields lock + // bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_DXCOMMIT_COMMIT_D0 0x4U // D0 RAM access protection and master select permanent + // lock +#define MEMCFG_DXCOMMIT_COMMIT_D1 0x8U // D1 RAM access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_DXACCPROT0_FETCHPROT_D0 0x10000U // Fetch Protection For D0 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D0 0x20000U // CPU WR Protection For D0 RAM +#define MEMCFG_DXACCPROT0_FETCHPROT_D1 0x1000000U // Fetch Protection For D1 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D1 0x2000000U // CPU WR Protection For D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxTEST register +// +//************************************************************************************************* +#define MEMCFG_DXTEST_TEST_M0_S 0U +#define MEMCFG_DXTEST_TEST_M0_M 0x3U // Selects the different modes for M0 RAM +#define MEMCFG_DXTEST_TEST_M1_S 2U +#define MEMCFG_DXTEST_TEST_M1_M 0xCU // Selects the different modes for M1 RAM +#define MEMCFG_DXTEST_TEST_D0_S 4U +#define MEMCFG_DXTEST_TEST_D0_M 0x30U // Selects the different modes for D0 RAM +#define MEMCFG_DXTEST_TEST_D1_S 6U +#define MEMCFG_DXTEST_TEST_D1_M 0xC0U // Selects the different modes for D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINIT register +// +//************************************************************************************************* +#define MEMCFG_DXINIT_INIT_M0 0x1U // RAM Initialization control for M0 RAM. +#define MEMCFG_DXINIT_INIT_M1 0x2U // RAM Initialization control for M1 RAM. +#define MEMCFG_DXINIT_INIT_D0 0x4U // RAM Initialization control for D0 RAM. +#define MEMCFG_DXINIT_INIT_D1 0x8U // RAM Initialization control for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_DXINITDONE_INITDONE_M0 0x1U // RAM Initialization status for M0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_M1 0x2U // RAM Initialization status for M1 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D0 0x4U // RAM Initialization status for D0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D1 0x8U // RAM Initialization status for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_LSXLOCK_LOCK_LS0 0x1U // LS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS1 0x2U // LS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS2 0x4U // LS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS3 0x8U // LS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS4 0x10U // LS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS5 0x20U // LS5 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_LSXCOMMIT_COMMIT_LS0 0x1U // LS0 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS1 0x2U // LS1 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS2 0x4U // LS2 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS3 0x8U // LS3 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS4 0x10U // LS4 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS5 0x20U // LS5 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_LSXMSEL_MSEL_LS0_S 0U +#define MEMCFG_LSXMSEL_MSEL_LS0_M 0x3U // Master Select for LS0 RAM +#define MEMCFG_LSXMSEL_MSEL_LS1_S 2U +#define MEMCFG_LSXMSEL_MSEL_LS1_M 0xCU // Master Select for LS1 RAM +#define MEMCFG_LSXMSEL_MSEL_LS2_S 4U +#define MEMCFG_LSXMSEL_MSEL_LS2_M 0x30U // Master Select for LS2 RAM +#define MEMCFG_LSXMSEL_MSEL_LS3_S 6U +#define MEMCFG_LSXMSEL_MSEL_LS3_M 0xC0U // Master Select for LS3 RAM +#define MEMCFG_LSXMSEL_MSEL_LS4_S 8U +#define MEMCFG_LSXMSEL_MSEL_LS4_M 0x300U // Master Select for LS4 RAM +#define MEMCFG_LSXMSEL_MSEL_LS5_S 10U +#define MEMCFG_LSXMSEL_MSEL_LS5_M 0xC00U // Master Select for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCLAPGM register +// +//************************************************************************************************* +#define MEMCFG_LSXCLAPGM_CLAPGM_LS0 0x1U // Selects LS0 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS1 0x2U // Selects LS1 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS2 0x4U // Selects LS2 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS3 0x8U // Selects LS3 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS4 0x10U // Selects LS4 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS5 0x20U // Selects LS5 RAM as program vs data memory for CLA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS0 0x1U // Fetch Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS0 0x2U // CPU WR Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS1 0x100U // Fetch Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS1 0x200U // CPU WR Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS2 0x10000U // Fetch Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS2 0x20000U // CPU WR Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS3 0x1000000U // Fetch Protection For LS3 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS3 0x2000000U // CPU WR Protection For LS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS4 0x1U // Fetch Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS4 0x2U // CPU WR Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS5 0x100U // Fetch Protection For LS5 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS5 0x200U // CPU WR Protection For LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxTEST register +// +//************************************************************************************************* +#define MEMCFG_LSXTEST_TEST_LS0_S 0U +#define MEMCFG_LSXTEST_TEST_LS0_M 0x3U // Selects the different modes for LS0 RAM +#define MEMCFG_LSXTEST_TEST_LS1_S 2U +#define MEMCFG_LSXTEST_TEST_LS1_M 0xCU // Selects the different modes for LS1 RAM +#define MEMCFG_LSXTEST_TEST_LS2_S 4U +#define MEMCFG_LSXTEST_TEST_LS2_M 0x30U // Selects the different modes for LS2 RAM +#define MEMCFG_LSXTEST_TEST_LS3_S 6U +#define MEMCFG_LSXTEST_TEST_LS3_M 0xC0U // Selects the different modes for LS3 RAM +#define MEMCFG_LSXTEST_TEST_LS4_S 8U +#define MEMCFG_LSXTEST_TEST_LS4_M 0x300U // Selects the different modes for LS4 RAM +#define MEMCFG_LSXTEST_TEST_LS5_S 10U +#define MEMCFG_LSXTEST_TEST_LS5_M 0xC00U // Selects the different modes for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINIT register +// +//************************************************************************************************* +#define MEMCFG_LSXINIT_INIT_LS0 0x1U // RAM Initialization control for LS0 RAM. +#define MEMCFG_LSXINIT_INIT_LS1 0x2U // RAM Initialization control for LS1 RAM. +#define MEMCFG_LSXINIT_INIT_LS2 0x4U // RAM Initialization control for LS2 RAM. +#define MEMCFG_LSXINIT_INIT_LS3 0x8U // RAM Initialization control for LS3 RAM. +#define MEMCFG_LSXINIT_INIT_LS4 0x10U // RAM Initialization control for LS4 RAM. +#define MEMCFG_LSXINIT_INIT_LS5 0x20U // RAM Initialization control for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_LSXINITDONE_INITDONE_LS0 0x1U // RAM Initialization status for LS0 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS1 0x2U // RAM Initialization status for LS1 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS2 0x4U // RAM Initialization status for LS2 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS3 0x8U // RAM Initialization status for LS3 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS4 0x10U // RAM Initialization status for LS4 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS5 0x20U // RAM Initialization status for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_GSXLOCK_LOCK_GS0 0x1U // GS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS1 0x2U // GS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS2 0x4U // GS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS3 0x8U // GS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS4 0x10U // GS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS5 0x20U // GS5 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS6 0x40U // GS6 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS7 0x80U // GS7 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS8 0x100U // GS8 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS9 0x200U // GS9 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS10 0x400U // GS10 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS11 0x800U // GS11 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS12 0x1000U // GS12 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS13 0x2000U // GS13 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS14 0x4000U // GS14 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS15 0x8000U // GS15 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_GSXCOMMIT_COMMIT_GS0 0x1U // GS0 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS1 0x2U // GS1 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS2 0x4U // GS2 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS3 0x8U // GS3 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS4 0x10U // GS4 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS5 0x20U // GS5 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS6 0x40U // GS6 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS7 0x80U // GS7 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS8 0x100U // GS8 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS9 0x200U // GS9 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS10 0x400U // GS10 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS11 0x800U // GS11 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS12 0x1000U // GS12 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS13 0x2000U // GS13 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS14 0x4000U // GS14 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS15 0x8000U // GS15 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_GSXMSEL_MSEL_GS0 0x1U // Master Select for GS0 RAM +#define MEMCFG_GSXMSEL_MSEL_GS1 0x2U // Master Select for GS1 RAM +#define MEMCFG_GSXMSEL_MSEL_GS2 0x4U // Master Select for GS2 RAM +#define MEMCFG_GSXMSEL_MSEL_GS3 0x8U // Master Select for GS3 RAM +#define MEMCFG_GSXMSEL_MSEL_GS4 0x10U // Master Select for GS4 RAM +#define MEMCFG_GSXMSEL_MSEL_GS5 0x20U // Master Select for GS5 RAM +#define MEMCFG_GSXMSEL_MSEL_GS6 0x40U // Master Select for GS6 RAM +#define MEMCFG_GSXMSEL_MSEL_GS7 0x80U // Master Select for GS7 RAM +#define MEMCFG_GSXMSEL_MSEL_GS8 0x100U // Master Select for GS8 RAM +#define MEMCFG_GSXMSEL_MSEL_GS9 0x200U // Master Select for GS9 RAM +#define MEMCFG_GSXMSEL_MSEL_GS10 0x400U // Master Select for GS10 RAM +#define MEMCFG_GSXMSEL_MSEL_GS11 0x800U // Master Select for GS11 RAM +#define MEMCFG_GSXMSEL_MSEL_GS12 0x1000U // Master Select for GS12 RAM +#define MEMCFG_GSXMSEL_MSEL_GS13 0x2000U // Master Select for GS13 RAM +#define MEMCFG_GSXMSEL_MSEL_GS14 0x4000U // Master Select for GS14 RAM +#define MEMCFG_GSXMSEL_MSEL_GS15 0x8000U // Master Select for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS0 0x1U // Fetch Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 0x2U // CPU WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS0 0x4U // DMA WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS1 0x100U // Fetch Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS1 0x200U // CPU WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS1 0x400U // DMA WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS2 0x10000U // Fetch Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS2 0x20000U // CPU WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS2 0x40000U // DMA WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS3 0x1000000U // Fetch Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS3 0x2000000U // CPU WR Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS3 0x4000000U // DMA WR Protection For GS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS4 0x1U // Fetch Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS4 0x2U // CPU WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS4 0x4U // DMA WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS5 0x100U // Fetch Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS5 0x200U // CPU WR Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS5 0x400U // DMA WR Protection For GS5RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS6 0x10000U // Fetch Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS6 0x20000U // CPU WR Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS6 0x40000U // DMA WR Protection For GS6RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS7 0x1000000U // Fetch Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS7 0x2000000U // CPU WR Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS7 0x4000000U // DMA WR Protection For GS7RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT2 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS8 0x1U // Fetch Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS8 0x2U // CPU WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS8 0x4U // DMA WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS9 0x100U // Fetch Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS9 0x200U // CPU WR Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS9 0x400U // DMA WR Protection For GS9RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS10 0x10000U // Fetch Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS10 0x20000U // CPU WR Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS10 0x40000U // DMA WR Protection For GS10RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS11 0x1000000U // Fetch Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS11 0x2000000U // CPU WR Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS11 0x4000000U // DMA WR Protection For GS11RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT3 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS12 0x1U // Fetch Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS12 0x2U // CPU WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS12 0x4U // DMA WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS13 0x100U // Fetch Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS13 0x200U // CPU WR Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS13 0x400U // DMA WR Protection For GS13RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS14 0x10000U // Fetch Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS14 0x20000U // CPU WR Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS14 0x40000U // DMA WR Protection For GS14RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS15 0x1000000U // Fetch Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS15 0x2000000U // CPU WR Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS15 0x4000000U // DMA WR Protection For GS15RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxTEST register +// +//************************************************************************************************* +#define MEMCFG_GSXTEST_TEST_GS0_S 0U +#define MEMCFG_GSXTEST_TEST_GS0_M 0x3U // Selects the different modes for GS0 RAM +#define MEMCFG_GSXTEST_TEST_GS1_S 2U +#define MEMCFG_GSXTEST_TEST_GS1_M 0xCU // Selects the different modes for GS1 RAM +#define MEMCFG_GSXTEST_TEST_GS2_S 4U +#define MEMCFG_GSXTEST_TEST_GS2_M 0x30U // Selects the different modes for GS2 RAM +#define MEMCFG_GSXTEST_TEST_GS3_S 6U +#define MEMCFG_GSXTEST_TEST_GS3_M 0xC0U // Selects the different modes for GS3 RAM +#define MEMCFG_GSXTEST_TEST_GS4_S 8U +#define MEMCFG_GSXTEST_TEST_GS4_M 0x300U // Selects the different modes for GS4 RAM +#define MEMCFG_GSXTEST_TEST_GS5_S 10U +#define MEMCFG_GSXTEST_TEST_GS5_M 0xC00U // Selects the different modes for GS5 RAM +#define MEMCFG_GSXTEST_TEST_GS6_S 12U +#define MEMCFG_GSXTEST_TEST_GS6_M 0x3000U // Selects the different modes for GS6 RAM +#define MEMCFG_GSXTEST_TEST_GS7_S 14U +#define MEMCFG_GSXTEST_TEST_GS7_M 0xC000U // Selects the different modes for GS7 RAM +#define MEMCFG_GSXTEST_TEST_GS8_S 16U +#define MEMCFG_GSXTEST_TEST_GS8_M 0x30000U // Selects the different modes for GS8 RAM +#define MEMCFG_GSXTEST_TEST_GS9_S 18U +#define MEMCFG_GSXTEST_TEST_GS9_M 0xC0000U // Selects the different modes for GS9 RAM +#define MEMCFG_GSXTEST_TEST_GS10_S 20U +#define MEMCFG_GSXTEST_TEST_GS10_M 0x300000U // Selects the different modes for GS10 RAM +#define MEMCFG_GSXTEST_TEST_GS11_S 22U +#define MEMCFG_GSXTEST_TEST_GS11_M 0xC00000U // Selects the different modes for GS11 RAM +#define MEMCFG_GSXTEST_TEST_GS12_S 24U +#define MEMCFG_GSXTEST_TEST_GS12_M 0x3000000U // Selects the different modes for GS12 RAM +#define MEMCFG_GSXTEST_TEST_GS13_S 26U +#define MEMCFG_GSXTEST_TEST_GS13_M 0xC000000U // Selects the different modes for GS13 RAM +#define MEMCFG_GSXTEST_TEST_GS14_S 28U +#define MEMCFG_GSXTEST_TEST_GS14_M 0x30000000U // Selects the different modes for GS14 RAM +#define MEMCFG_GSXTEST_TEST_GS15_S 30U +#define MEMCFG_GSXTEST_TEST_GS15_M 0xC0000000U // Selects the different modes for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINIT register +// +//************************************************************************************************* +#define MEMCFG_GSXINIT_INIT_GS0 0x1U // RAM Initialization control for GS0 RAM. +#define MEMCFG_GSXINIT_INIT_GS1 0x2U // RAM Initialization control for GS1 RAM. +#define MEMCFG_GSXINIT_INIT_GS2 0x4U // RAM Initialization control for GS2 RAM. +#define MEMCFG_GSXINIT_INIT_GS3 0x8U // RAM Initialization control for GS3 RAM. +#define MEMCFG_GSXINIT_INIT_GS4 0x10U // RAM Initialization control for GS4 RAM. +#define MEMCFG_GSXINIT_INIT_GS5 0x20U // RAM Initialization control for GS5 RAM. +#define MEMCFG_GSXINIT_INIT_GS6 0x40U // RAM Initialization control for GS6 RAM. +#define MEMCFG_GSXINIT_INIT_GS7 0x80U // RAM Initialization control for GS7 RAM. +#define MEMCFG_GSXINIT_INIT_GS8 0x100U // RAM Initialization control for GS8 RAM. +#define MEMCFG_GSXINIT_INIT_GS9 0x200U // RAM Initialization control for GS9 RAM. +#define MEMCFG_GSXINIT_INIT_GS10 0x400U // RAM Initialization control for GS10 RAM. +#define MEMCFG_GSXINIT_INIT_GS11 0x800U // RAM Initialization control for GS11 RAM. +#define MEMCFG_GSXINIT_INIT_GS12 0x1000U // RAM Initialization control for GS12 RAM. +#define MEMCFG_GSXINIT_INIT_GS13 0x2000U // RAM Initialization control for GS13 RAM. +#define MEMCFG_GSXINIT_INIT_GS14 0x4000U // RAM Initialization control for GS14 RAM. +#define MEMCFG_GSXINIT_INIT_GS15 0x8000U // RAM Initialization control for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_GSXINITDONE_INITDONE_GS0 0x1U // RAM Initialization status for GS0 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS1 0x2U // RAM Initialization status for GS1 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS2 0x4U // RAM Initialization status for GS2 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS3 0x8U // RAM Initialization status for GS3 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS4 0x10U // RAM Initialization status for GS4 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS5 0x20U // RAM Initialization status for GS5 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS6 0x40U // RAM Initialization status for GS6 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS7 0x80U // RAM Initialization status for GS7 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS8 0x100U // RAM Initialization status for GS8 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS9 0x200U // RAM Initialization status for GS9 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS10 0x400U // RAM Initialization status for GS10 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS11 0x800U // RAM Initialization status for GS11 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS12 0x1000U // RAM Initialization status for GS12 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS13 0x2000U // RAM Initialization status for GS13 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS14 0x4000U // RAM Initialization status for GS14 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS15 0x8000U // RAM Initialization status for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxTEST register +// +//************************************************************************************************* +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_S 0U +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_M 0x3U // CPU to CPU Mode Select +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_S 2U +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_M 0xCU // CPU to CLA1 MSG RAM Mode Select +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_S 4U +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_M 0x30U // CLA1 to CPU MSG RAM Mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINIT register +// +//************************************************************************************************* +#define MEMCFG_MSGXINIT_INIT_CPUTOCPU 0x1U // Initialization control for CPU to CPU MSG RAM +#define MEMCFG_MSGXINIT_INIT_CPUTOCLA1 0x2U // Initialization control for CPUTOCLA1 MSG RAM +#define MEMCFG_MSGXINIT_INIT_CLA1TOCPU 0x4U // Initialization control for CLA1TOCPU MSG RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCPU 0x1U // Initialization status for CPU to CPU MSG + // RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCLA1 0x2U // Initialization status for CPU to CLA1 + // MSG RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CLA1TOCPU 0x4U // Initialization status for CLA1 to CPU + // MSG RAM + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF1LOCK_LOCK_EMIF1 0x1U // EMIF1 access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF1COMMIT_COMMIT_EMIF1 0x1U // EMIF1 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1MSEL register +// +//************************************************************************************************* +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_S 0U +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_M 0x3U // Master Select for EMIF1. +#define MEMCFG_EMIF1MSEL_KEY_S 4U +#define MEMCFG_EMIF1MSEL_KEY_M 0xFFFFFFF0U // KEY to enable the write into MSEL_EMIF1 + // bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 0x1U // Fetch Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 0x2U // CPU WR Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 0x4U // DMA WR Protection For EMIF1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF2LOCK_LOCK_EMIF2 0x1U // EMIF2 access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF2COMMIT_COMMIT_EMIF2 0x1U // EMIF2 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 0x1U // Fetch Protection For EMIF2 +#define MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2 0x2U // CPU WR Protection For EMIF2 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVFLG register +// +//************************************************************************************************* +#define MEMCFG_NMAVFLG_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag +#define MEMCFG_NMAVFLG_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag +#define MEMCFG_NMAVFLG_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag +#define MEMCFG_NMAVFLG_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVSET register +// +//************************************************************************************************* +#define MEMCFG_NMAVSET_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Set +#define MEMCFG_NMAVSET_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVCLR register +// +//************************************************************************************************* +#define MEMCFG_NMAVCLR_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_NMAVCLR_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_NMAVINTEN_CPUREAD 0x1U // Non Master CPU Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUWRITE 0x2U // Non Master CPU Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_DMAWRITE 0x8U // Non Master DMA Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVFLG register +// +//************************************************************************************************* +#define MEMCFG_MAVFLG_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag +#define MEMCFG_MAVFLG_CPUWRITE 0x2U // Master CPU Write Access Violation Flag +#define MEMCFG_MAVFLG_DMAWRITE 0x4U // Master DMA Write Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVSET register +// +//************************************************************************************************* +#define MEMCFG_MAVSET_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Set +#define MEMCFG_MAVSET_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Set +#define MEMCFG_MAVSET_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVCLR register +// +//************************************************************************************************* +#define MEMCFG_MAVCLR_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_MAVCLR_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Clear +#define MEMCFG_MAVCLR_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_MAVINTEN_CPUFETCH 0x1U // Master CPU Fetch Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_CPUWRITE 0x2U // Master CPU Write Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_DMAWRITE 0x4U // Master DMA Write Access Violation Interrupt Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRFLG register +// +//************************************************************************************************* +#define MEMCFG_UCERRFLG_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRSET register +// +//************************************************************************************************* +#define MEMCFG_UCERRSET_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRCLR register +// +//************************************************************************************************* +#define MEMCFG_UCERRCLR_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRFLG register +// +//************************************************************************************************* +#define MEMCFG_CERRFLG_CPURDERR 0x1U // CPU Correctable Read Error Flag +#define MEMCFG_CERRFLG_DMARDERR 0x2U // DMA Correctable Read Error Flag +#define MEMCFG_CERRFLG_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRSET register +// +//************************************************************************************************* +#define MEMCFG_CERRSET_CPURDERR 0x1U // CPU Correctable Read Error Flag Set +#define MEMCFG_CERRSET_DMARDERR 0x2U // DMA Correctable Read Error Flag Set +#define MEMCFG_CERRSET_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRCLR register +// +//************************************************************************************************* +#define MEMCFG_CERRCLR_CPURDERR 0x1U // CPU Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_DMARDERR 0x2U // DMA Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTFLG register +// +//************************************************************************************************* +#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTCLR register +// +//************************************************************************************************* +#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // CPU Corrected Error Threshold Exceeded Error Clear. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTSET register +// +//************************************************************************************************* +#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTEN register +// +//************************************************************************************************* +#define MEMCFG_CEINTEN_CEINTEN 0x1U // CPU/DMA Correctable Error Interrupt Enable. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMWAITSTATE register +// +//************************************************************************************************* +#define MEMCFG_ROMWAITSTATE_WSDISABLE 0x1U // C28x ROM Wait State Enable/Disable Control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMPREFETCH register +// +//************************************************************************************************* +#define MEMCFG_ROMPREFETCH_PFENABLE 0x1U // ROM Prefetch Enable/Disable Control + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_memmap.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_memmap.h new file mode 100644 index 0000000..ba0b5e5 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_memmap.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_memmap.h +// +// TITLE: Macros defining the memory map of the C28x. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMMAP_H +#define HW_MEMMAP_H + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define M0_RAM_BASE 0x00000000U +#define M1_RAM_BASE 0x00000400U +#define ADCARESULT_BASE 0x00000B00U +#define ADCBRESULT_BASE 0x00000B20U +#define ADCCRESULT_BASE 0x00000B40U +#define ADCDRESULT_BASE 0x00000B60U +#define CPUTIMER0_BASE 0x00000C00U +#define CPUTIMER1_BASE 0x00000C08U +#define CPUTIMER2_BASE 0x00000C10U +#define CLA1_SOFTINT_BASE 0x00000CE0U +#define PIECTRL_BASE 0x00000CE0U +#define PIEVECTTABLE_BASE 0x00000D00U +#define DMA_BASE 0x00001000U +#define DMA_CH1_BASE 0x00001020U +#define DMA_CH2_BASE 0x00001040U +#define DMA_CH3_BASE 0x00001060U +#define DMA_CH4_BASE 0x00001080U +#define DMA_CH5_BASE 0x000010A0U +#define DMA_CH6_BASE 0x000010C0U +#define CLA1_BASE 0x00001400U +#define CLATOCPU_RAM_BASE 0x00001480U +#define CPUTOCLA_RAM_BASE 0x00001500U +#define CLB1_BASE 0x00003000U +#define CLB1_LOGICCFG_BASE 0x00003000U +#define CLB1_LOGICCTL_BASE 0x00003100U +#define CLB1_DATAEXCH_BASE 0x00003200U +#define CLB2_BASE 0x00003400U +#define CLB2_LOGICCFG_BASE 0x00003400U +#define CLB2_LOGICCTL_BASE 0x00003500U +#define CLB2_DATAEXCH_BASE 0x00003600U +#define CLB3_BASE 0x00003800U +#define CLB3_LOGICCFG_BASE 0x00003800U +#define CLB3_LOGICCTL_BASE 0x00003900U +#define CLB3_DATAEXCH_BASE 0x00003A00U +#define CLB4_BASE 0x00003C00U +#define CLB4_LOGICCFG_BASE 0x00003C00U +#define CLB4_LOGICCTL_BASE 0x00003D00U +#define CLB4_DATAEXCH_BASE 0x00003E00U +#define EPWM1_BASE 0x00004000U +#define EPWM2_BASE 0x00004100U +#define EPWM3_BASE 0x00004200U +#define EPWM4_BASE 0x00004300U +#define EPWM5_BASE 0x00004400U +#define EPWM6_BASE 0x00004500U +#define EPWM7_BASE 0x00004600U +#define EPWM8_BASE 0x00004700U +#define EPWM9_BASE 0x00004800U +#define EPWM10_BASE 0x00004900U +#define EPWM11_BASE 0x00004A00U +#define EPWM12_BASE 0x00004B00U +#define ECAP1_BASE 0x00005000U +#define ECAP2_BASE 0x00005020U +#define ECAP3_BASE 0x00005040U +#define ECAP4_BASE 0x00005060U +#define ECAP5_BASE 0x00005080U +#define ECAP6_BASE 0x000050A0U +#define EQEP1_BASE 0x00005100U +#define EQEP2_BASE 0x00005140U +#define EQEP3_BASE 0x00005180U +#define DACA_BASE 0x00005C00U +#define DACB_BASE 0x00005C10U +#define DACC_BASE 0x00005C20U +#define CMPSS1_BASE 0x00005C80U +#define CMPSS2_BASE 0x00005CA0U +#define CMPSS3_BASE 0x00005CC0U +#define CMPSS4_BASE 0x00005CE0U +#define CMPSS5_BASE 0x00005D00U +#define CMPSS6_BASE 0x00005D20U +#define CMPSS7_BASE 0x00005D40U +#define CMPSS8_BASE 0x00005D60U +#define SDFM1_BASE 0x00005E00U +#define SDFM2_BASE 0x00005E80U +#define MCBSPA_BASE 0x00006000U +#define MCBSPB_BASE 0x00006040U +#define SPIA_BASE 0x00006100U +#define SPIB_BASE 0x00006110U +#define SPIC_BASE 0x00006120U +#define UPP_BASE 0x00006200U +#define UPP_TX_MSG_RAM_BASE 0x00006C00U +#define UPP_RX_MSG_RAM_BASE 0x00006E00U +#define WD_BASE 0x00007000U +#define NMI_BASE 0x00007060U +#define XINT_BASE 0x00007070U +#define SCIA_BASE 0x00007200U +#define SCIB_BASE 0x00007210U +#define SCIC_BASE 0x00007220U +#define SCID_BASE 0x00007230U +#define I2CA_BASE 0x00007300U +#define I2CB_BASE 0x00007340U +#define ADCA_BASE 0x00007400U +#define ADCB_BASE 0x00007480U +#define ADCC_BASE 0x00007500U +#define ADCD_BASE 0x00007580U +#define INPUTXBAR_BASE 0x00007900U +#define XBAR_BASE 0x00007920U +#define SYNCSOC_BASE 0x00007940U +#define DMACLASRCSEL_BASE 0x00007980U +#define EPWMXBAR_BASE 0x00007A00U +#define CLBXBAR_BASE 0x00007A40U +#define OUTPUTXBAR_BASE 0x00007A80U +#define GPIOCTRL_BASE 0x00007C00U +#define GPIODATA_BASE 0x00007F00U +#define LS0_RAM_BASE 0x00008000U +#define LS1_RAM_BASE 0x00008800U +#define LS2_RAM_BASE 0x00009000U +#define LS3_RAM_BASE 0x00009800U +#define LS4_RAM_BASE 0x0000A000U +#define LS5_RAM_BASE 0x0000A800U +#define D0_RAM_BASE 0x0000B000U +#define D1_RAM_BASE 0x0000B800U +#define GS0_RAM_BASE 0x0000C000U +#define GS1_RAM_BASE 0x0000D000U +#define GS2_RAM_BASE 0x0000E000U +#define GS3_RAM_BASE 0x0000F000U +#define GS4_RAM_BASE 0x00010000U +#define GS5_RAM_BASE 0x00011000U +#define GS6_RAM_BASE 0x00012000U +#define GS7_RAM_BASE 0x00013000U +#define GS8_RAM_BASE 0x00014000U +#define GS9_RAM_BASE 0x00015000U +#define GS10_RAM_BASE 0x00016000U +#define GS11_RAM_BASE 0x00017000U +#define GS12_RAM_BASE 0x00018000U +#define GS13_RAM_BASE 0x00019000U +#define GS14_RAM_BASE 0x0001A000U +#define GS15_RAM_BASE 0x0001B000U +#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U +#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U +#define USBA_BASE 0x00040000U +#define EMIF1_BASE 0x00047000U +#define EMIF2_BASE 0x00047800U +#define CANA_BASE 0x00048000U +#define CANA_MSG_RAM_BASE 0x00049000U +#define CANB_BASE 0x0004A000U +#define CANB_MSG_RAM_BASE 0x0004B000U +#define IPC_BASE 0x00050000U +#define FLASHPUMPSEMAPHORE_BASE 0x00050024U +#define DEVCFG_BASE 0x0005D000U +#define ANALOGSUBSYS_BASE 0x0005D180U +#define CLKCFG_BASE 0x0005D200U +#define CPUSYS_BASE 0x0005D300U +#define ROMPREFETCH_BASE 0x0005E608U +#define DCSM_Z1_BASE 0x0005F000U +#define DCSM_Z2_BASE 0x0005F040U +#define DCSMCOMMON_BASE 0x0005F070U +#define MEMCFG_BASE 0x0005F400U +#define EMIF1CONFIG_BASE 0x0005F480U +#define EMIF2CONFIG_BASE 0x0005F4A0U +#define ACCESSPROTECTION_BASE 0x0005F4C0U +#define MEMORYERROR_BASE 0x0005F500U +#define ROMWAITSTATE_BASE 0x0005F540U +#define FLASH0CTRL_BASE 0x0005F800U +#define FLASH0ECC_BASE 0x0005FB00U +#define DCSM_Z1OTP_BASE 0x00078000U +#define DCSM_Z2OTP_BASE 0x00078200U +#define UID_BASE 0x000703C0U +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_nmi.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_nmi.h new file mode 100644 index 0000000..efd8157 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_nmi.h @@ -0,0 +1,134 @@ +//########################################################################### +// +// FILE: hw_nmi.h +// +// TITLE: Definitions for the NMI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_NMI_H +#define HW_NMI_H + +//************************************************************************************************* +// +// The following are defines for the NMI register offsets +// +//************************************************************************************************* +#define NMI_O_CFG 0x0U // NMI Configuration Register +#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear) +#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register +#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register +#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register +#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register +#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMICFG register +// +//************************************************************************************************* +#define NMI_CFG_NMIE 0x1U // Global NMI Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLG register +// +//************************************************************************************************* +#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag +#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag +#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag +#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag +#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag +#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag +#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag +#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag +#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag +#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGCLR register +// +//************************************************************************************************* +#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear +#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear +#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear +#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear +#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear +#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear +#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear +#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear +#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear +#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear +#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGFRC register +// +//************************************************************************************************* +#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force +#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force +#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force +#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force +#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force +#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force +#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force +#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force +#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force +#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMISHDFLG register +// +//************************************************************************************************* +#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag +#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag +#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag +#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag +#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag +#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag +#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag +#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag +#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag +#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_otp.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_otp.h new file mode 100644 index 0000000..d074499 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_otp.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: hw_otp.h +// +// TITLE: Definitions for the OTP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OTP_H +#define HW_OTP_H + +//************************************************************************************************* +// +// The following are defines for the OTP register offsets +// +//************************************************************************************************* +#define OTP_O_UID_PSRAND0 0x0U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND1 0x2U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND2 0x4U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND3 0x6U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND4 0x8U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND5 0xAU // UID Psuedo-random 160 bit number +#define OTP_O_UID_UNIQUE 0xCU // UID UID Unique 32 bit number +#define OTP_O_UID_CHECKSUM 0xEU // UID Checksum + + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_outputxbar.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_outputxbar.h new file mode 100644 index 0000000..30a10e9 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_outputxbar.h @@ -0,0 +1,1340 @@ +//########################################################################### +// +// FILE: hw_outputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OUTPUTXBAR_H +#define HW_OUTPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_OUTPUT1MUX0TO15CFG 0x0U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT1MUX16TO31CFG 0x2U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT2MUX0TO15CFG 0x4U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT2MUX16TO31CFG 0x6U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT3MUX0TO15CFG 0x8U // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT3MUX16TO31CFG 0xAU // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT4MUX0TO15CFG 0xCU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT4MUX16TO31CFG 0xEU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT5MUX0TO15CFG 0x10U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT5MUX16TO31CFG 0x12U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT6MUX0TO15CFG 0x14U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT6MUX16TO31CFG 0x16U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT7MUX0TO15CFG 0x18U // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT7MUX16TO31CFG 0x1AU // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT8MUX0TO15CFG 0x1CU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT8MUX16TO31CFG 0x1EU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT1MUXENABLE 0x20U // Output X-BAR Mux Enable for Output 1 +#define XBAR_O_OUTPUT2MUXENABLE 0x22U // Output X-BAR Mux Enable for Output 2 +#define XBAR_O_OUTPUT3MUXENABLE 0x24U // Output X-BAR Mux Enable for Output 3 +#define XBAR_O_OUTPUT4MUXENABLE 0x26U // Output X-BAR Mux Enable for Output 4 +#define XBAR_O_OUTPUT5MUXENABLE 0x28U // Output X-BAR Mux Enable for Output 5 +#define XBAR_O_OUTPUT6MUXENABLE 0x2AU // Output X-BAR Mux Enable for Output 6 +#define XBAR_O_OUTPUT7MUXENABLE 0x2CU // Output X-BAR Mux Enable for Output 7 +#define XBAR_O_OUTPUT8MUXENABLE 0x2EU // Output X-BAR Mux Enable for Output 8 +#define XBAR_O_OUTPUTLATCH 0x30U // Output X-BAR Output Latch +#define XBAR_O_OUTPUTLATCHCLR 0x32U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHFRC 0x34U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHENABLE 0x36U // Output X-BAR Output Latch Enable +#define XBAR_O_OUTPUTINV 0x38U // Output X-BAR Output Inversion +#define XBAR_O_OUTPUTLOCK 0x3EU // Output X-BAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT1 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT2 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT3 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT4 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT5 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT6 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT7 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCH register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCH_OUTPUT1 0x1U // Records the OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT2 0x2U // Records the OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT3 0x4U // Records the OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT4 0x8U // Records the OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT5 0x10U // Records the OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT6 0x20U // Records the OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT7 0x40U // Records the OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT8 0x80U // Records the OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHCLR register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHCLR_OUTPUT1 0x1U // Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT2 0x2U // Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT3 0x4U // Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT4 0x8U // Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT5 0x10U // Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT6 0x20U // Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT7 0x40U // Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT8 0x80U // Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHFRC register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHFRC_OUTPUT1 0x1U // Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT2 0x2U // Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT3 0x4U // Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT4 0x8U // Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT5 0x10U // Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT6 0x20U // Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT7 0x40U // Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT8 0x80U // Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHENABLE_OUTPUT1 0x1U // Selects the output latch to drive OUTPUT1 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT2 0x2U // Selects the output latch to drive OUTPUT2 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT3 0x4U // Selects the output latch to drive OUTPUT3 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT4 0x8U // Selects the output latch to drive OUTPUT4 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT5 0x10U // Selects the output latch to drive OUTPUT5 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT6 0x20U // Selects the output latch to drive OUTPUT6 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT7 0x40U // Selects the output latch to drive OUTPUT7 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT8 0x80U // Selects the output latch to drive OUTPUT8 for + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTINV register +// +//************************************************************************************************* +#define XBAR_OUTPUTINV_OUTPUT1 0x1U // Selects polarity for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT2 0x2U // Selects polarity for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT3 0x4U // Selects polarity for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT4 0x8U // Selects polarity for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT5 0x10U // Selects polarity for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT6 0x20U // Selects polarity for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT7 0x40U // Selects polarity for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT8 0x80U // Selects polarity for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLOCK register +// +//************************************************************************************************* +#define XBAR_OUTPUTLOCK_LOCK 0x1U // Locks the configuration for OUTPUT-XBAR +#define XBAR_OUTPUTLOCK_KEY_S 16U +#define XBAR_OUTPUTLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_pie.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_pie.h new file mode 100644 index 0000000..9a4f09f --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_pie.h @@ -0,0 +1,636 @@ +//########################################################################### +// +// FILE: hw_pie.h +// +// TITLE: Definitions for the PIE registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_PIE_H +#define HW_PIE_H + +//************************************************************************************************* +// +// The following are defines for the PIE register offsets +// +//************************************************************************************************* +#define PIE_O_CTRL 0x0U // ePIE Control Register +#define PIE_O_ACK 0x1U // Interrupt Acknowledge Register +#define PIE_O_IER1 0x2U // Interrupt Group 1 Enable Register +#define PIE_O_IFR1 0x3U // Interrupt Group 1 Flag Register +#define PIE_O_IER2 0x4U // Interrupt Group 2 Enable Register +#define PIE_O_IFR2 0x5U // Interrupt Group 2 Flag Register +#define PIE_O_IER3 0x6U // Interrupt Group 3 Enable Register +#define PIE_O_IFR3 0x7U // Interrupt Group 3 Flag Register +#define PIE_O_IER4 0x8U // Interrupt Group 4 Enable Register +#define PIE_O_IFR4 0x9U // Interrupt Group 4 Flag Register +#define PIE_O_IER5 0xAU // Interrupt Group 5 Enable Register +#define PIE_O_IFR5 0xBU // Interrupt Group 5 Flag Register +#define PIE_O_IER6 0xCU // Interrupt Group 6 Enable Register +#define PIE_O_IFR6 0xDU // Interrupt Group 6 Flag Register +#define PIE_O_IER7 0xEU // Interrupt Group 7 Enable Register +#define PIE_O_IFR7 0xFU // Interrupt Group 7 Flag Register +#define PIE_O_IER8 0x10U // Interrupt Group 8 Enable Register +#define PIE_O_IFR8 0x11U // Interrupt Group 8 Flag Register +#define PIE_O_IER9 0x12U // Interrupt Group 9 Enable Register +#define PIE_O_IFR9 0x13U // Interrupt Group 9 Flag Register +#define PIE_O_IER10 0x14U // Interrupt Group 10 Enable Register +#define PIE_O_IFR10 0x15U // Interrupt Group 10 Flag Register +#define PIE_O_IER11 0x16U // Interrupt Group 11 Enable Register +#define PIE_O_IFR11 0x17U // Interrupt Group 11 Flag Register +#define PIE_O_IER12 0x18U // Interrupt Group 12 Enable Register +#define PIE_O_IFR12 0x19U // Interrupt Group 12 Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIECTRL register +// +//************************************************************************************************* +#define PIE_CTRL_ENPIE 0x1U // PIE Enable +#define PIE_CTRL_PIEVECT_S 1U +#define PIE_CTRL_PIEVECT_M 0xFFFEU // PIE Vector Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEACK register +// +//************************************************************************************************* +#define PIE_ACK_ACK1 0x1U // Acknowledge PIE Interrupt Group 1 +#define PIE_ACK_ACK2 0x2U // Acknowledge PIE Interrupt Group 2 +#define PIE_ACK_ACK3 0x4U // Acknowledge PIE Interrupt Group 3 +#define PIE_ACK_ACK4 0x8U // Acknowledge PIE Interrupt Group 4 +#define PIE_ACK_ACK5 0x10U // Acknowledge PIE Interrupt Group 5 +#define PIE_ACK_ACK6 0x20U // Acknowledge PIE Interrupt Group 6 +#define PIE_ACK_ACK7 0x40U // Acknowledge PIE Interrupt Group 7 +#define PIE_ACK_ACK8 0x80U // Acknowledge PIE Interrupt Group 8 +#define PIE_ACK_ACK9 0x100U // Acknowledge PIE Interrupt Group 9 +#define PIE_ACK_ACK10 0x200U // Acknowledge PIE Interrupt Group 10 +#define PIE_ACK_ACK11 0x400U // Acknowledge PIE Interrupt Group 11 +#define PIE_ACK_ACK12 0x800U // Acknowledge PIE Interrupt Group 12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER1 register +// +//************************************************************************************************* +#define PIE_IER1_INTX1 0x1U // Enable for Interrupt 1.1 +#define PIE_IER1_INTX2 0x2U // Enable for Interrupt 1.2 +#define PIE_IER1_INTX3 0x4U // Enable for Interrupt 1.3 +#define PIE_IER1_INTX4 0x8U // Enable for Interrupt 1.4 +#define PIE_IER1_INTX5 0x10U // Enable for Interrupt 1.5 +#define PIE_IER1_INTX6 0x20U // Enable for Interrupt 1.6 +#define PIE_IER1_INTX7 0x40U // Enable for Interrupt 1.7 +#define PIE_IER1_INTX8 0x80U // Enable for Interrupt 1.8 +#define PIE_IER1_INTX9 0x100U // Enable for Interrupt 1.9 +#define PIE_IER1_INTX10 0x200U // Enable for Interrupt 1.10 +#define PIE_IER1_INTX11 0x400U // Enable for Interrupt 1.11 +#define PIE_IER1_INTX12 0x800U // Enable for Interrupt 1.12 +#define PIE_IER1_INTX13 0x1000U // Enable for Interrupt 1.13 +#define PIE_IER1_INTX14 0x2000U // Enable for Interrupt 1.14 +#define PIE_IER1_INTX15 0x4000U // Enable for Interrupt 1.15 +#define PIE_IER1_INTX16 0x8000U // Enable for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR1 register +// +//************************************************************************************************* +#define PIE_IFR1_INTX1 0x1U // Flag for Interrupt 1.1 +#define PIE_IFR1_INTX2 0x2U // Flag for Interrupt 1.2 +#define PIE_IFR1_INTX3 0x4U // Flag for Interrupt 1.3 +#define PIE_IFR1_INTX4 0x8U // Flag for Interrupt 1.4 +#define PIE_IFR1_INTX5 0x10U // Flag for Interrupt 1.5 +#define PIE_IFR1_INTX6 0x20U // Flag for Interrupt 1.6 +#define PIE_IFR1_INTX7 0x40U // Flag for Interrupt 1.7 +#define PIE_IFR1_INTX8 0x80U // Flag for Interrupt 1.8 +#define PIE_IFR1_INTX9 0x100U // Flag for Interrupt 1.9 +#define PIE_IFR1_INTX10 0x200U // Flag for Interrupt 1.10 +#define PIE_IFR1_INTX11 0x400U // Flag for Interrupt 1.11 +#define PIE_IFR1_INTX12 0x800U // Flag for Interrupt 1.12 +#define PIE_IFR1_INTX13 0x1000U // Flag for Interrupt 1.13 +#define PIE_IFR1_INTX14 0x2000U // Flag for Interrupt 1.14 +#define PIE_IFR1_INTX15 0x4000U // Flag for Interrupt 1.15 +#define PIE_IFR1_INTX16 0x8000U // Flag for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER2 register +// +//************************************************************************************************* +#define PIE_IER2_INTX1 0x1U // Enable for Interrupt 2.1 +#define PIE_IER2_INTX2 0x2U // Enable for Interrupt 2.2 +#define PIE_IER2_INTX3 0x4U // Enable for Interrupt 2.3 +#define PIE_IER2_INTX4 0x8U // Enable for Interrupt 2.4 +#define PIE_IER2_INTX5 0x10U // Enable for Interrupt 2.5 +#define PIE_IER2_INTX6 0x20U // Enable for Interrupt 2.6 +#define PIE_IER2_INTX7 0x40U // Enable for Interrupt 2.7 +#define PIE_IER2_INTX8 0x80U // Enable for Interrupt 2.8 +#define PIE_IER2_INTX9 0x100U // Enable for Interrupt 2.9 +#define PIE_IER2_INTX10 0x200U // Enable for Interrupt 2.10 +#define PIE_IER2_INTX11 0x400U // Enable for Interrupt 2.11 +#define PIE_IER2_INTX12 0x800U // Enable for Interrupt 2.12 +#define PIE_IER2_INTX13 0x1000U // Enable for Interrupt 2.13 +#define PIE_IER2_INTX14 0x2000U // Enable for Interrupt 2.14 +#define PIE_IER2_INTX15 0x4000U // Enable for Interrupt 2.15 +#define PIE_IER2_INTX16 0x8000U // Enable for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR2 register +// +//************************************************************************************************* +#define PIE_IFR2_INTX1 0x1U // Flag for Interrupt 2.1 +#define PIE_IFR2_INTX2 0x2U // Flag for Interrupt 2.2 +#define PIE_IFR2_INTX3 0x4U // Flag for Interrupt 2.3 +#define PIE_IFR2_INTX4 0x8U // Flag for Interrupt 2.4 +#define PIE_IFR2_INTX5 0x10U // Flag for Interrupt 2.5 +#define PIE_IFR2_INTX6 0x20U // Flag for Interrupt 2.6 +#define PIE_IFR2_INTX7 0x40U // Flag for Interrupt 2.7 +#define PIE_IFR2_INTX8 0x80U // Flag for Interrupt 2.8 +#define PIE_IFR2_INTX9 0x100U // Flag for Interrupt 2.9 +#define PIE_IFR2_INTX10 0x200U // Flag for Interrupt 2.10 +#define PIE_IFR2_INTX11 0x400U // Flag for Interrupt 2.11 +#define PIE_IFR2_INTX12 0x800U // Flag for Interrupt 2.12 +#define PIE_IFR2_INTX13 0x1000U // Flag for Interrupt 2.13 +#define PIE_IFR2_INTX14 0x2000U // Flag for Interrupt 2.14 +#define PIE_IFR2_INTX15 0x4000U // Flag for Interrupt 2.15 +#define PIE_IFR2_INTX16 0x8000U // Flag for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER3 register +// +//************************************************************************************************* +#define PIE_IER3_INTX1 0x1U // Enable for Interrupt 3.1 +#define PIE_IER3_INTX2 0x2U // Enable for Interrupt 3.2 +#define PIE_IER3_INTX3 0x4U // Enable for Interrupt 3.3 +#define PIE_IER3_INTX4 0x8U // Enable for Interrupt 3.4 +#define PIE_IER3_INTX5 0x10U // Enable for Interrupt 3.5 +#define PIE_IER3_INTX6 0x20U // Enable for Interrupt 3.6 +#define PIE_IER3_INTX7 0x40U // Enable for Interrupt 3.7 +#define PIE_IER3_INTX8 0x80U // Enable for Interrupt 3.8 +#define PIE_IER3_INTX9 0x100U // Enable for Interrupt 3.9 +#define PIE_IER3_INTX10 0x200U // Enable for Interrupt 3.10 +#define PIE_IER3_INTX11 0x400U // Enable for Interrupt 3.11 +#define PIE_IER3_INTX12 0x800U // Enable for Interrupt 3.12 +#define PIE_IER3_INTX13 0x1000U // Enable for Interrupt 3.13 +#define PIE_IER3_INTX14 0x2000U // Enable for Interrupt 3.14 +#define PIE_IER3_INTX15 0x4000U // Enable for Interrupt 3.15 +#define PIE_IER3_INTX16 0x8000U // Enable for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR3 register +// +//************************************************************************************************* +#define PIE_IFR3_INTX1 0x1U // Flag for Interrupt 3.1 +#define PIE_IFR3_INTX2 0x2U // Flag for Interrupt 3.2 +#define PIE_IFR3_INTX3 0x4U // Flag for Interrupt 3.3 +#define PIE_IFR3_INTX4 0x8U // Flag for Interrupt 3.4 +#define PIE_IFR3_INTX5 0x10U // Flag for Interrupt 3.5 +#define PIE_IFR3_INTX6 0x20U // Flag for Interrupt 3.6 +#define PIE_IFR3_INTX7 0x40U // Flag for Interrupt 3.7 +#define PIE_IFR3_INTX8 0x80U // Flag for Interrupt 3.8 +#define PIE_IFR3_INTX9 0x100U // Flag for Interrupt 3.9 +#define PIE_IFR3_INTX10 0x200U // Flag for Interrupt 3.10 +#define PIE_IFR3_INTX11 0x400U // Flag for Interrupt 3.11 +#define PIE_IFR3_INTX12 0x800U // Flag for Interrupt 3.12 +#define PIE_IFR3_INTX13 0x1000U // Flag for Interrupt 3.13 +#define PIE_IFR3_INTX14 0x2000U // Flag for Interrupt 3.14 +#define PIE_IFR3_INTX15 0x4000U // Flag for Interrupt 3.15 +#define PIE_IFR3_INTX16 0x8000U // Flag for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER4 register +// +//************************************************************************************************* +#define PIE_IER4_INTX1 0x1U // Enable for Interrupt 4.1 +#define PIE_IER4_INTX2 0x2U // Enable for Interrupt 4.2 +#define PIE_IER4_INTX3 0x4U // Enable for Interrupt 4.3 +#define PIE_IER4_INTX4 0x8U // Enable for Interrupt 4.4 +#define PIE_IER4_INTX5 0x10U // Enable for Interrupt 4.5 +#define PIE_IER4_INTX6 0x20U // Enable for Interrupt 4.6 +#define PIE_IER4_INTX7 0x40U // Enable for Interrupt 4.7 +#define PIE_IER4_INTX8 0x80U // Enable for Interrupt 4.8 +#define PIE_IER4_INTX9 0x100U // Enable for Interrupt 4.9 +#define PIE_IER4_INTX10 0x200U // Enable for Interrupt 4.10 +#define PIE_IER4_INTX11 0x400U // Enable for Interrupt 4.11 +#define PIE_IER4_INTX12 0x800U // Enable for Interrupt 4.12 +#define PIE_IER4_INTX13 0x1000U // Enable for Interrupt 4.13 +#define PIE_IER4_INTX14 0x2000U // Enable for Interrupt 4.14 +#define PIE_IER4_INTX15 0x4000U // Enable for Interrupt 4.15 +#define PIE_IER4_INTX16 0x8000U // Enable for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR4 register +// +//************************************************************************************************* +#define PIE_IFR4_INTX1 0x1U // Flag for Interrupt 4.1 +#define PIE_IFR4_INTX2 0x2U // Flag for Interrupt 4.2 +#define PIE_IFR4_INTX3 0x4U // Flag for Interrupt 4.3 +#define PIE_IFR4_INTX4 0x8U // Flag for Interrupt 4.4 +#define PIE_IFR4_INTX5 0x10U // Flag for Interrupt 4.5 +#define PIE_IFR4_INTX6 0x20U // Flag for Interrupt 4.6 +#define PIE_IFR4_INTX7 0x40U // Flag for Interrupt 4.7 +#define PIE_IFR4_INTX8 0x80U // Flag for Interrupt 4.8 +#define PIE_IFR4_INTX9 0x100U // Flag for Interrupt 4.9 +#define PIE_IFR4_INTX10 0x200U // Flag for Interrupt 4.10 +#define PIE_IFR4_INTX11 0x400U // Flag for Interrupt 4.11 +#define PIE_IFR4_INTX12 0x800U // Flag for Interrupt 4.12 +#define PIE_IFR4_INTX13 0x1000U // Flag for Interrupt 4.13 +#define PIE_IFR4_INTX14 0x2000U // Flag for Interrupt 4.14 +#define PIE_IFR4_INTX15 0x4000U // Flag for Interrupt 4.15 +#define PIE_IFR4_INTX16 0x8000U // Flag for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER5 register +// +//************************************************************************************************* +#define PIE_IER5_INTX1 0x1U // Enable for Interrupt 5.1 +#define PIE_IER5_INTX2 0x2U // Enable for Interrupt 5.2 +#define PIE_IER5_INTX3 0x4U // Enable for Interrupt 5.3 +#define PIE_IER5_INTX4 0x8U // Enable for Interrupt 5.4 +#define PIE_IER5_INTX5 0x10U // Enable for Interrupt 5.5 +#define PIE_IER5_INTX6 0x20U // Enable for Interrupt 5.6 +#define PIE_IER5_INTX7 0x40U // Enable for Interrupt 5.7 +#define PIE_IER5_INTX8 0x80U // Enable for Interrupt 5.8 +#define PIE_IER5_INTX9 0x100U // Enable for Interrupt 5.9 +#define PIE_IER5_INTX10 0x200U // Enable for Interrupt 5.10 +#define PIE_IER5_INTX11 0x400U // Enable for Interrupt 5.11 +#define PIE_IER5_INTX12 0x800U // Enable for Interrupt 5.12 +#define PIE_IER5_INTX13 0x1000U // Enable for Interrupt 5.13 +#define PIE_IER5_INTX14 0x2000U // Enable for Interrupt 5.14 +#define PIE_IER5_INTX15 0x4000U // Enable for Interrupt 5.15 +#define PIE_IER5_INTX16 0x8000U // Enable for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR5 register +// +//************************************************************************************************* +#define PIE_IFR5_INTX1 0x1U // Flag for Interrupt 5.1 +#define PIE_IFR5_INTX2 0x2U // Flag for Interrupt 5.2 +#define PIE_IFR5_INTX3 0x4U // Flag for Interrupt 5.3 +#define PIE_IFR5_INTX4 0x8U // Flag for Interrupt 5.4 +#define PIE_IFR5_INTX5 0x10U // Flag for Interrupt 5.5 +#define PIE_IFR5_INTX6 0x20U // Flag for Interrupt 5.6 +#define PIE_IFR5_INTX7 0x40U // Flag for Interrupt 5.7 +#define PIE_IFR5_INTX8 0x80U // Flag for Interrupt 5.8 +#define PIE_IFR5_INTX9 0x100U // Flag for Interrupt 5.9 +#define PIE_IFR5_INTX10 0x200U // Flag for Interrupt 5.10 +#define PIE_IFR5_INTX11 0x400U // Flag for Interrupt 5.11 +#define PIE_IFR5_INTX12 0x800U // Flag for Interrupt 5.12 +#define PIE_IFR5_INTX13 0x1000U // Flag for Interrupt 5.13 +#define PIE_IFR5_INTX14 0x2000U // Flag for Interrupt 5.14 +#define PIE_IFR5_INTX15 0x4000U // Flag for Interrupt 5.15 +#define PIE_IFR5_INTX16 0x8000U // Flag for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER6 register +// +//************************************************************************************************* +#define PIE_IER6_INTX1 0x1U // Enable for Interrupt 6.1 +#define PIE_IER6_INTX2 0x2U // Enable for Interrupt 6.2 +#define PIE_IER6_INTX3 0x4U // Enable for Interrupt 6.3 +#define PIE_IER6_INTX4 0x8U // Enable for Interrupt 6.4 +#define PIE_IER6_INTX5 0x10U // Enable for Interrupt 6.5 +#define PIE_IER6_INTX6 0x20U // Enable for Interrupt 6.6 +#define PIE_IER6_INTX7 0x40U // Enable for Interrupt 6.7 +#define PIE_IER6_INTX8 0x80U // Enable for Interrupt 6.8 +#define PIE_IER6_INTX9 0x100U // Enable for Interrupt 6.9 +#define PIE_IER6_INTX10 0x200U // Enable for Interrupt 6.10 +#define PIE_IER6_INTX11 0x400U // Enable for Interrupt 6.11 +#define PIE_IER6_INTX12 0x800U // Enable for Interrupt 6.12 +#define PIE_IER6_INTX13 0x1000U // Enable for Interrupt 6.13 +#define PIE_IER6_INTX14 0x2000U // Enable for Interrupt 6.14 +#define PIE_IER6_INTX15 0x4000U // Enable for Interrupt 6.15 +#define PIE_IER6_INTX16 0x8000U // Enable for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR6 register +// +//************************************************************************************************* +#define PIE_IFR6_INTX1 0x1U // Flag for Interrupt 6.1 +#define PIE_IFR6_INTX2 0x2U // Flag for Interrupt 6.2 +#define PIE_IFR6_INTX3 0x4U // Flag for Interrupt 6.3 +#define PIE_IFR6_INTX4 0x8U // Flag for Interrupt 6.4 +#define PIE_IFR6_INTX5 0x10U // Flag for Interrupt 6.5 +#define PIE_IFR6_INTX6 0x20U // Flag for Interrupt 6.6 +#define PIE_IFR6_INTX7 0x40U // Flag for Interrupt 6.7 +#define PIE_IFR6_INTX8 0x80U // Flag for Interrupt 6.8 +#define PIE_IFR6_INTX9 0x100U // Flag for Interrupt 6.9 +#define PIE_IFR6_INTX10 0x200U // Flag for Interrupt 6.10 +#define PIE_IFR6_INTX11 0x400U // Flag for Interrupt 6.11 +#define PIE_IFR6_INTX12 0x800U // Flag for Interrupt 6.12 +#define PIE_IFR6_INTX13 0x1000U // Flag for Interrupt 6.13 +#define PIE_IFR6_INTX14 0x2000U // Flag for Interrupt 6.14 +#define PIE_IFR6_INTX15 0x4000U // Flag for Interrupt 6.15 +#define PIE_IFR6_INTX16 0x8000U // Flag for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER7 register +// +//************************************************************************************************* +#define PIE_IER7_INTX1 0x1U // Enable for Interrupt 7.1 +#define PIE_IER7_INTX2 0x2U // Enable for Interrupt 7.2 +#define PIE_IER7_INTX3 0x4U // Enable for Interrupt 7.3 +#define PIE_IER7_INTX4 0x8U // Enable for Interrupt 7.4 +#define PIE_IER7_INTX5 0x10U // Enable for Interrupt 7.5 +#define PIE_IER7_INTX6 0x20U // Enable for Interrupt 7.6 +#define PIE_IER7_INTX7 0x40U // Enable for Interrupt 7.7 +#define PIE_IER7_INTX8 0x80U // Enable for Interrupt 7.8 +#define PIE_IER7_INTX9 0x100U // Enable for Interrupt 7.9 +#define PIE_IER7_INTX10 0x200U // Enable for Interrupt 7.10 +#define PIE_IER7_INTX11 0x400U // Enable for Interrupt 7.11 +#define PIE_IER7_INTX12 0x800U // Enable for Interrupt 7.12 +#define PIE_IER7_INTX13 0x1000U // Enable for Interrupt 7.13 +#define PIE_IER7_INTX14 0x2000U // Enable for Interrupt 7.14 +#define PIE_IER7_INTX15 0x4000U // Enable for Interrupt 7.15 +#define PIE_IER7_INTX16 0x8000U // Enable for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR7 register +// +//************************************************************************************************* +#define PIE_IFR7_INTX1 0x1U // Flag for Interrupt 7.1 +#define PIE_IFR7_INTX2 0x2U // Flag for Interrupt 7.2 +#define PIE_IFR7_INTX3 0x4U // Flag for Interrupt 7.3 +#define PIE_IFR7_INTX4 0x8U // Flag for Interrupt 7.4 +#define PIE_IFR7_INTX5 0x10U // Flag for Interrupt 7.5 +#define PIE_IFR7_INTX6 0x20U // Flag for Interrupt 7.6 +#define PIE_IFR7_INTX7 0x40U // Flag for Interrupt 7.7 +#define PIE_IFR7_INTX8 0x80U // Flag for Interrupt 7.8 +#define PIE_IFR7_INTX9 0x100U // Flag for Interrupt 7.9 +#define PIE_IFR7_INTX10 0x200U // Flag for Interrupt 7.10 +#define PIE_IFR7_INTX11 0x400U // Flag for Interrupt 7.11 +#define PIE_IFR7_INTX12 0x800U // Flag for Interrupt 7.12 +#define PIE_IFR7_INTX13 0x1000U // Flag for Interrupt 7.13 +#define PIE_IFR7_INTX14 0x2000U // Flag for Interrupt 7.14 +#define PIE_IFR7_INTX15 0x4000U // Flag for Interrupt 7.15 +#define PIE_IFR7_INTX16 0x8000U // Flag for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER8 register +// +//************************************************************************************************* +#define PIE_IER8_INTX1 0x1U // Enable for Interrupt 8.1 +#define PIE_IER8_INTX2 0x2U // Enable for Interrupt 8.2 +#define PIE_IER8_INTX3 0x4U // Enable for Interrupt 8.3 +#define PIE_IER8_INTX4 0x8U // Enable for Interrupt 8.4 +#define PIE_IER8_INTX5 0x10U // Enable for Interrupt 8.5 +#define PIE_IER8_INTX6 0x20U // Enable for Interrupt 8.6 +#define PIE_IER8_INTX7 0x40U // Enable for Interrupt 8.7 +#define PIE_IER8_INTX8 0x80U // Enable for Interrupt 8.8 +#define PIE_IER8_INTX9 0x100U // Enable for Interrupt 8.9 +#define PIE_IER8_INTX10 0x200U // Enable for Interrupt 8.10 +#define PIE_IER8_INTX11 0x400U // Enable for Interrupt 8.11 +#define PIE_IER8_INTX12 0x800U // Enable for Interrupt 8.12 +#define PIE_IER8_INTX13 0x1000U // Enable for Interrupt 8.13 +#define PIE_IER8_INTX14 0x2000U // Enable for Interrupt 8.14 +#define PIE_IER8_INTX15 0x4000U // Enable for Interrupt 8.15 +#define PIE_IER8_INTX16 0x8000U // Enable for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR8 register +// +//************************************************************************************************* +#define PIE_IFR8_INTX1 0x1U // Flag for Interrupt 8.1 +#define PIE_IFR8_INTX2 0x2U // Flag for Interrupt 8.2 +#define PIE_IFR8_INTX3 0x4U // Flag for Interrupt 8.3 +#define PIE_IFR8_INTX4 0x8U // Flag for Interrupt 8.4 +#define PIE_IFR8_INTX5 0x10U // Flag for Interrupt 8.5 +#define PIE_IFR8_INTX6 0x20U // Flag for Interrupt 8.6 +#define PIE_IFR8_INTX7 0x40U // Flag for Interrupt 8.7 +#define PIE_IFR8_INTX8 0x80U // Flag for Interrupt 8.8 +#define PIE_IFR8_INTX9 0x100U // Flag for Interrupt 8.9 +#define PIE_IFR8_INTX10 0x200U // Flag for Interrupt 8.10 +#define PIE_IFR8_INTX11 0x400U // Flag for Interrupt 8.11 +#define PIE_IFR8_INTX12 0x800U // Flag for Interrupt 8.12 +#define PIE_IFR8_INTX13 0x1000U // Flag for Interrupt 8.13 +#define PIE_IFR8_INTX14 0x2000U // Flag for Interrupt 8.14 +#define PIE_IFR8_INTX15 0x4000U // Flag for Interrupt 8.15 +#define PIE_IFR8_INTX16 0x8000U // Flag for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER9 register +// +//************************************************************************************************* +#define PIE_IER9_INTX1 0x1U // Enable for Interrupt 9.1 +#define PIE_IER9_INTX2 0x2U // Enable for Interrupt 9.2 +#define PIE_IER9_INTX3 0x4U // Enable for Interrupt 9.3 +#define PIE_IER9_INTX4 0x8U // Enable for Interrupt 9.4 +#define PIE_IER9_INTX5 0x10U // Enable for Interrupt 9.5 +#define PIE_IER9_INTX6 0x20U // Enable for Interrupt 9.6 +#define PIE_IER9_INTX7 0x40U // Enable for Interrupt 9.7 +#define PIE_IER9_INTX8 0x80U // Enable for Interrupt 9.8 +#define PIE_IER9_INTX9 0x100U // Enable for Interrupt 9.9 +#define PIE_IER9_INTX10 0x200U // Enable for Interrupt 9.10 +#define PIE_IER9_INTX11 0x400U // Enable for Interrupt 9.11 +#define PIE_IER9_INTX12 0x800U // Enable for Interrupt 9.12 +#define PIE_IER9_INTX13 0x1000U // Enable for Interrupt 9.13 +#define PIE_IER9_INTX14 0x2000U // Enable for Interrupt 9.14 +#define PIE_IER9_INTX15 0x4000U // Enable for Interrupt 9.15 +#define PIE_IER9_INTX16 0x8000U // Enable for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR9 register +// +//************************************************************************************************* +#define PIE_IFR9_INTX1 0x1U // Flag for Interrupt 9.1 +#define PIE_IFR9_INTX2 0x2U // Flag for Interrupt 9.2 +#define PIE_IFR9_INTX3 0x4U // Flag for Interrupt 9.3 +#define PIE_IFR9_INTX4 0x8U // Flag for Interrupt 9.4 +#define PIE_IFR9_INTX5 0x10U // Flag for Interrupt 9.5 +#define PIE_IFR9_INTX6 0x20U // Flag for Interrupt 9.6 +#define PIE_IFR9_INTX7 0x40U // Flag for Interrupt 9.7 +#define PIE_IFR9_INTX8 0x80U // Flag for Interrupt 9.8 +#define PIE_IFR9_INTX9 0x100U // Flag for Interrupt 9.9 +#define PIE_IFR9_INTX10 0x200U // Flag for Interrupt 9.10 +#define PIE_IFR9_INTX11 0x400U // Flag for Interrupt 9.11 +#define PIE_IFR9_INTX12 0x800U // Flag for Interrupt 9.12 +#define PIE_IFR9_INTX13 0x1000U // Flag for Interrupt 9.13 +#define PIE_IFR9_INTX14 0x2000U // Flag for Interrupt 9.14 +#define PIE_IFR9_INTX15 0x4000U // Flag for Interrupt 9.15 +#define PIE_IFR9_INTX16 0x8000U // Flag for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER10 register +// +//************************************************************************************************* +#define PIE_IER10_INTX1 0x1U // Enable for Interrupt 10.1 +#define PIE_IER10_INTX2 0x2U // Enable for Interrupt 10.2 +#define PIE_IER10_INTX3 0x4U // Enable for Interrupt 10.3 +#define PIE_IER10_INTX4 0x8U // Enable for Interrupt 10.4 +#define PIE_IER10_INTX5 0x10U // Enable for Interrupt 10.5 +#define PIE_IER10_INTX6 0x20U // Enable for Interrupt 10.6 +#define PIE_IER10_INTX7 0x40U // Enable for Interrupt 10.7 +#define PIE_IER10_INTX8 0x80U // Enable for Interrupt 10.8 +#define PIE_IER10_INTX9 0x100U // Enable for Interrupt 10.9 +#define PIE_IER10_INTX10 0x200U // Enable for Interrupt 10.10 +#define PIE_IER10_INTX11 0x400U // Enable for Interrupt 10.11 +#define PIE_IER10_INTX12 0x800U // Enable for Interrupt 10.12 +#define PIE_IER10_INTX13 0x1000U // Enable for Interrupt 10.13 +#define PIE_IER10_INTX14 0x2000U // Enable for Interrupt 10.14 +#define PIE_IER10_INTX15 0x4000U // Enable for Interrupt 10.15 +#define PIE_IER10_INTX16 0x8000U // Enable for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR10 register +// +//************************************************************************************************* +#define PIE_IFR10_INTX1 0x1U // Flag for Interrupt 10.1 +#define PIE_IFR10_INTX2 0x2U // Flag for Interrupt 10.2 +#define PIE_IFR10_INTX3 0x4U // Flag for Interrupt 10.3 +#define PIE_IFR10_INTX4 0x8U // Flag for Interrupt 10.4 +#define PIE_IFR10_INTX5 0x10U // Flag for Interrupt 10.5 +#define PIE_IFR10_INTX6 0x20U // Flag for Interrupt 10.6 +#define PIE_IFR10_INTX7 0x40U // Flag for Interrupt 10.7 +#define PIE_IFR10_INTX8 0x80U // Flag for Interrupt 10.8 +#define PIE_IFR10_INTX9 0x100U // Flag for Interrupt 10.9 +#define PIE_IFR10_INTX10 0x200U // Flag for Interrupt 10.10 +#define PIE_IFR10_INTX11 0x400U // Flag for Interrupt 10.11 +#define PIE_IFR10_INTX12 0x800U // Flag for Interrupt 10.12 +#define PIE_IFR10_INTX13 0x1000U // Flag for Interrupt 10.13 +#define PIE_IFR10_INTX14 0x2000U // Flag for Interrupt 10.14 +#define PIE_IFR10_INTX15 0x4000U // Flag for Interrupt 10.15 +#define PIE_IFR10_INTX16 0x8000U // Flag for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER11 register +// +//************************************************************************************************* +#define PIE_IER11_INTX1 0x1U // Enable for Interrupt 11.1 +#define PIE_IER11_INTX2 0x2U // Enable for Interrupt 11.2 +#define PIE_IER11_INTX3 0x4U // Enable for Interrupt 11.3 +#define PIE_IER11_INTX4 0x8U // Enable for Interrupt 11.4 +#define PIE_IER11_INTX5 0x10U // Enable for Interrupt 11.5 +#define PIE_IER11_INTX6 0x20U // Enable for Interrupt 11.6 +#define PIE_IER11_INTX7 0x40U // Enable for Interrupt 11.7 +#define PIE_IER11_INTX8 0x80U // Enable for Interrupt 11.8 +#define PIE_IER11_INTX9 0x100U // Enable for Interrupt 11.9 +#define PIE_IER11_INTX10 0x200U // Enable for Interrupt 11.10 +#define PIE_IER11_INTX11 0x400U // Enable for Interrupt 11.11 +#define PIE_IER11_INTX12 0x800U // Enable for Interrupt 11.12 +#define PIE_IER11_INTX13 0x1000U // Enable for Interrupt 11.13 +#define PIE_IER11_INTX14 0x2000U // Enable for Interrupt 11.14 +#define PIE_IER11_INTX15 0x4000U // Enable for Interrupt 11.15 +#define PIE_IER11_INTX16 0x8000U // Enable for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR11 register +// +//************************************************************************************************* +#define PIE_IFR11_INTX1 0x1U // Flag for Interrupt 11.1 +#define PIE_IFR11_INTX2 0x2U // Flag for Interrupt 11.2 +#define PIE_IFR11_INTX3 0x4U // Flag for Interrupt 11.3 +#define PIE_IFR11_INTX4 0x8U // Flag for Interrupt 11.4 +#define PIE_IFR11_INTX5 0x10U // Flag for Interrupt 11.5 +#define PIE_IFR11_INTX6 0x20U // Flag for Interrupt 11.6 +#define PIE_IFR11_INTX7 0x40U // Flag for Interrupt 11.7 +#define PIE_IFR11_INTX8 0x80U // Flag for Interrupt 11.8 +#define PIE_IFR11_INTX9 0x100U // Flag for Interrupt 11.9 +#define PIE_IFR11_INTX10 0x200U // Flag for Interrupt 11.10 +#define PIE_IFR11_INTX11 0x400U // Flag for Interrupt 11.11 +#define PIE_IFR11_INTX12 0x800U // Flag for Interrupt 11.12 +#define PIE_IFR11_INTX13 0x1000U // Flag for Interrupt 11.13 +#define PIE_IFR11_INTX14 0x2000U // Flag for Interrupt 11.14 +#define PIE_IFR11_INTX15 0x4000U // Flag for Interrupt 11.15 +#define PIE_IFR11_INTX16 0x8000U // Flag for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER12 register +// +//************************************************************************************************* +#define PIE_IER12_INTX1 0x1U // Enable for Interrupt 12.1 +#define PIE_IER12_INTX2 0x2U // Enable for Interrupt 12.2 +#define PIE_IER12_INTX3 0x4U // Enable for Interrupt 12.3 +#define PIE_IER12_INTX4 0x8U // Enable for Interrupt 12.4 +#define PIE_IER12_INTX5 0x10U // Enable for Interrupt 12.5 +#define PIE_IER12_INTX6 0x20U // Enable for Interrupt 12.6 +#define PIE_IER12_INTX7 0x40U // Enable for Interrupt 12.7 +#define PIE_IER12_INTX8 0x80U // Enable for Interrupt 12.8 +#define PIE_IER12_INTX9 0x100U // Enable for Interrupt 12.9 +#define PIE_IER12_INTX10 0x200U // Enable for Interrupt 12.10 +#define PIE_IER12_INTX11 0x400U // Enable for Interrupt 12.11 +#define PIE_IER12_INTX12 0x800U // Enable for Interrupt 12.12 +#define PIE_IER12_INTX13 0x1000U // Enable for Interrupt 12.13 +#define PIE_IER12_INTX14 0x2000U // Enable for Interrupt 12.14 +#define PIE_IER12_INTX15 0x4000U // Enable for Interrupt 12.15 +#define PIE_IER12_INTX16 0x8000U // Enable for Interrupt 12.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR12 register +// +//************************************************************************************************* +#define PIE_IFR12_INTX1 0x1U // Flag for Interrupt 12.1 +#define PIE_IFR12_INTX2 0x2U // Flag for Interrupt 12.2 +#define PIE_IFR12_INTX3 0x4U // Flag for Interrupt 12.3 +#define PIE_IFR12_INTX4 0x8U // Flag for Interrupt 12.4 +#define PIE_IFR12_INTX5 0x10U // Flag for Interrupt 12.5 +#define PIE_IFR12_INTX6 0x20U // Flag for Interrupt 12.6 +#define PIE_IFR12_INTX7 0x40U // Flag for Interrupt 12.7 +#define PIE_IFR12_INTX8 0x80U // Flag for Interrupt 12.8 +#define PIE_IFR12_INTX9 0x100U // Flag for Interrupt 12.9 +#define PIE_IFR12_INTX10 0x200U // Flag for Interrupt 12.10 +#define PIE_IFR12_INTX11 0x400U // Flag for Interrupt 12.11 +#define PIE_IFR12_INTX12 0x800U // Flag for Interrupt 12.12 +#define PIE_IFR12_INTX13 0x1000U // Flag for Interrupt 12.13 +#define PIE_IFR12_INTX14 0x2000U // Flag for Interrupt 12.14 +#define PIE_IFR12_INTX15 0x4000U // Flag for Interrupt 12.15 +#define PIE_IFR12_INTX16 0x8000U // Flag for Interrupt 12.16 + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_sci.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_sci.h new file mode 100644 index 0000000..2fc9680 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_sci.h @@ -0,0 +1,209 @@ +//########################################################################### +// +// FILE: hw_sci.h +// +// TITLE: Definitions for the SCI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SCI_H +#define HW_SCI_H + +//************************************************************************************************* +// +// The following are defines for the SCI register offsets +// +//************************************************************************************************* +#define SCI_O_CCR 0x0U // Communications control register +#define SCI_O_CTL1 0x1U // Control register 1 +#define SCI_O_HBAUD 0x2U // Baud rate (high) register +#define SCI_O_LBAUD 0x3U // Baud rate (low) register +#define SCI_O_CTL2 0x4U // Control register 2 +#define SCI_O_RXST 0x5U // Receive status register +#define SCI_O_RXEMU 0x6U // Receive emulation buffer register +#define SCI_O_RXBUF 0x7U // Receive data buffer +#define SCI_O_TXBUF 0x9U // Transmit data buffer +#define SCI_O_FFTX 0xAU // FIFO transmit register +#define SCI_O_FFRX 0xBU // FIFO receive register +#define SCI_O_FFCT 0xCU // FIFO control register +#define SCI_O_PRI 0xFU // SCI priority control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICCR register +// +//************************************************************************************************* +#define SCI_CCR_SCICHAR_S 0U +#define SCI_CCR_SCICHAR_M 0x7U // Character length control +#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control +#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable +#define SCI_CCR_PARITYENA 0x20U // Parity enable +#define SCI_CCR_PARITY 0x40U // Even or Odd Parity +#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL1 register +// +//************************************************************************************************* +#define SCI_CTL1_RXENA 0x1U // SCI receiver enable +#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable +#define SCI_CTL1_SLEEP 0x4U // SCI sleep +#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method +#define SCI_CTL1_SWRESET 0x20U // Software reset +#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIHBAUD register +// +//************************************************************************************************* +#define SCI_HBAUD_BAUD_S 0U +#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCILBAUD register +// +//************************************************************************************************* +#define SCI_LBAUD_BAUD_S 0U +#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL2 register +// +//************************************************************************************************* +#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable +#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable +#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag +#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXST register +// +//************************************************************************************************* +#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag +#define SCI_RXST_PE 0x4U // Parity error flag +#define SCI_RXST_OE 0x8U // Overrun error flag +#define SCI_RXST_FE 0x10U // Framing error flag +#define SCI_RXST_BRKDT 0x20U // Break-detect flag +#define SCI_RXST_RXRDY 0x40U // Receiver ready flag +#define SCI_RXST_RXERROR 0x80U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXEMU register +// +//************************************************************************************************* +#define SCI_RXEMU_ERXDT_S 0U +#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXBUF register +// +//************************************************************************************************* +#define SCI_RXBUF_SAR_S 0U +#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits +#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag +#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCITXBUF register +// +//************************************************************************************************* +#define SCI_TXBUF_TXDT_S 0U +#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFTX register +// +//************************************************************************************************* +#define SCI_FFTX_TXFFIL_S 0U +#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level +#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable +#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFTX_TXFFINT 0x80U // INT flag +#define SCI_FFTX_TXFFST_S 8U +#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status +#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset +#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable +#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFRX register +// +//************************************************************************************************* +#define SCI_FFRX_RXFFIL_S 0U +#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level +#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable +#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFRX_RXFFINT 0x80U // INT flag +#define SCI_FFRX_RXFFST_S 8U +#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status +#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset +#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow +#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFCT register +// +//************************************************************************************************* +#define SCI_FFCT_FFTXDLY_S 0U +#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay +#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable +#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear +#define SCI_FFCT_ABD 0x8000U // Auto baud detect + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIPRI register +// +//************************************************************************************************* +#define SCI_PRI_FREESOFT_S 3U +#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_sdfm.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_sdfm.h new file mode 100644 index 0000000..d2ba146 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_sdfm.h @@ -0,0 +1,431 @@ +//########################################################################### +// +// FILE: hw_sdfm.h +// +// TITLE: Definitions for the SDFM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SDFM_H +#define HW_SDFM_H + +//************************************************************************************************* +// +// The following are defines for the SDFM register offsets +// +//************************************************************************************************* +#define SDFM_O_SDIFLG 0x0U // Interrupt Flag Register +#define SDFM_O_SDIFLGCLR 0x2U // Interrupt Flag Clear Register +#define SDFM_O_SDCTL 0x4U // SD Control Register +#define SDFM_O_SDMFILEN 0x6U // SD Master Filter Enable +#define SDFM_O_SDCTLPARM1 0x10U // Control Parameter Register for Ch1 +#define SDFM_O_SDDFPARM1 0x11U // Data Filter Parameter Register for Ch1 +#define SDFM_O_SDDPARM1 0x12U // Integer Parameter Register for Ch1 +#define SDFM_O_SDCMPH1 0x13U // High-level Threshold Register for Ch1 +#define SDFM_O_SDCMPL1 0x14U // Low-level Threshold Register for Ch1 +#define SDFM_O_SDCPARM1 0x15U // Comparator Parameter Register for Ch1 +#define SDFM_O_SDDATA1 0x16U // Filter Data Register (16 or 32bit) for Ch1 +#define SDFM_O_SDCTLPARM2 0x20U // Control Parameter Register for Ch2 +#define SDFM_O_SDDFPARM2 0x21U // Data Filter Parameter Register for Ch2 +#define SDFM_O_SDDPARM2 0x22U // Integer Parameter Register for Ch2 +#define SDFM_O_SDCMPH2 0x23U // High-level Threshold Register for Ch2 +#define SDFM_O_SDCMPL2 0x24U // Low-level Threshold Register for Ch2 +#define SDFM_O_SDCPARM2 0x25U // Comparator Parameter Register for Ch2 +#define SDFM_O_SDDATA2 0x26U // Filter Data Register (16 or 32bit) for Ch2 +#define SDFM_O_SDCTLPARM3 0x30U // Control Parameter Register for Ch3 +#define SDFM_O_SDDFPARM3 0x31U // Data Filter Parameter Register for Ch3 +#define SDFM_O_SDDPARM3 0x32U // Integer Parameter Register for Ch3 +#define SDFM_O_SDCMPH3 0x33U // High-level Threshold Register for Ch3 +#define SDFM_O_SDCMPL3 0x34U // Low-level Threshold Register for Ch3 +#define SDFM_O_SDCPARM3 0x35U // Comparator Parameter Register for Ch3 +#define SDFM_O_SDDATA3 0x36U // Filter Data Register (16 or 32bit) for Ch3 +#define SDFM_O_SDCTLPARM4 0x40U // Control Parameter Register for Ch4 +#define SDFM_O_SDDFPARM4 0x41U // Data Filter Parameter Register for Ch4 +#define SDFM_O_SDDPARM4 0x42U // Integer Parameter Register for Ch4 +#define SDFM_O_SDCMPH4 0x43U // High-level Threshold Register for Ch4 +#define SDFM_O_SDCMPL4 0x44U // Low-level Threshold Register for Ch4 +#define SDFM_O_SDCPARM4 0x45U // Comparator Parameter Register for Ch4 +#define SDFM_O_SDDATA4 0x46U // Filter Data Register (16 or 32bit) for Ch4 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLG register +// +//************************************************************************************************* +#define SDFM_SDIFLG_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLG_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLG_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLG_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLG_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLG_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLG_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLG_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLG_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLG_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLG_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLGCLR register +// +//************************************************************************************************* +#define SDFM_SDIFLGCLR_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLGCLR_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLGCLR_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLGCLR_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLGCLR_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLGCLR_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLGCLR_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLGCLR_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLGCLR_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTL register +// +//************************************************************************************************* +#define SDFM_SDCTL_MIE 0x2000U // Master Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDMFILEN register +// +//************************************************************************************************* +#define SDFM_SDMFILEN_MFE 0x800U // Master Filter Enable. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM1_MOD_S 0U +#define SDFM_SDCTLPARM1_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM1_DOSR_S 0U +#define SDFM_SDDFPARM1_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM1_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM1_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM1_SST_S 10U +#define SDFM_SDDFPARM1_SST_M 0xC00U // Data Filter Structure (DataFast/1/2/3) +#define SDFM_SDDFPARM1_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDPARM1_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM1_SH_S 11U +#define SDFM_SDDPARM1_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH1 register +// +//************************************************************************************************* +#define SDFM_SDCMPH1_HLT_S 0U +#define SDFM_SDCMPH1_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL1 register +// +//************************************************************************************************* +#define SDFM_SDCMPL1_LLT_S 0U +#define SDFM_SDCMPL1_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCPARM1_COSR_S 0U +#define SDFM_SDCPARM1_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM1_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM1_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM1_CS1_CS0_S 7U +#define SDFM_SDCPARM1_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM1_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA1 register +// +//************************************************************************************************* +#define SDFM_SDDATA1_DATA16_S 0U +#define SDFM_SDDATA1_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA1_DATA32HI_S 16U +#define SDFM_SDDATA1_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM2_MOD_S 0U +#define SDFM_SDCTLPARM2_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM2_DOSR_S 0U +#define SDFM_SDDFPARM2_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM2_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM2_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM2_SST_S 10U +#define SDFM_SDDFPARM2_SST_M 0xC00U // Data Filter Structure (SincFast/1/2/3) +#define SDFM_SDDFPARM2_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDPARM2_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM2_SH_S 11U +#define SDFM_SDDPARM2_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH2 register +// +//************************************************************************************************* +#define SDFM_SDCMPH2_HLT_S 0U +#define SDFM_SDCMPH2_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL2 register +// +//************************************************************************************************* +#define SDFM_SDCMPL2_LLT_S 0U +#define SDFM_SDCMPL2_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCPARM2_COSR_S 0U +#define SDFM_SDCPARM2_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM2_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM2_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM2_CS1_CS0_S 7U +#define SDFM_SDCPARM2_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM2_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA2 register +// +//************************************************************************************************* +#define SDFM_SDDATA2_DATA16_S 0U +#define SDFM_SDDATA2_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA2_DATA32HI_S 16U +#define SDFM_SDDATA2_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM3_MOD_S 0U +#define SDFM_SDCTLPARM3_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM3_DOSR_S 0U +#define SDFM_SDDFPARM3_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM3_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM3_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM3_SST_S 10U +#define SDFM_SDDFPARM3_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM3_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDPARM3_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM3_SH_S 11U +#define SDFM_SDDPARM3_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH3 register +// +//************************************************************************************************* +#define SDFM_SDCMPH3_HLT_S 0U +#define SDFM_SDCMPH3_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL3 register +// +//************************************************************************************************* +#define SDFM_SDCMPL3_LLT_S 0U +#define SDFM_SDCMPL3_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCPARM3_COSR_S 0U +#define SDFM_SDCPARM3_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM3_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM3_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM3_CS1_CS0_S 7U +#define SDFM_SDCPARM3_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM3_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA3 register +// +//************************************************************************************************* +#define SDFM_SDDATA3_DATA16_S 0U +#define SDFM_SDDATA3_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA3_DATA32HI_S 16U +#define SDFM_SDDATA3_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM4_MOD_S 0U +#define SDFM_SDCTLPARM4_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM4_DOSR_S 0U +#define SDFM_SDDFPARM4_DOSR_M 0xFFU // SINC Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM4_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM4_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM4_SST_S 10U +#define SDFM_SDDFPARM4_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM4_SDSYNCEN 0x1000U // SINC FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDPARM4_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM4_SH_S 11U +#define SDFM_SDDPARM4_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH4 register +// +//************************************************************************************************* +#define SDFM_SDCMPH4_HLT_S 0U +#define SDFM_SDCMPH4_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL4 register +// +//************************************************************************************************* +#define SDFM_SDCMPL4_LLT_S 0U +#define SDFM_SDCMPL4_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCPARM4_COSR_S 0U +#define SDFM_SDCPARM4_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM4_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM4_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM4_CS1_CS0_S 7U +#define SDFM_SDCPARM4_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM4_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA4 register +// +//************************************************************************************************* +#define SDFM_SDDATA4_DATA16_S 0U +#define SDFM_SDDATA4_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA4_DATA32HI_S 16U +#define SDFM_SDDATA4_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_spi.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_spi.h new file mode 100644 index 0000000..c4907aa --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_spi.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_spi.h +// +// TITLE: Definitions for the SPI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SPI_H +#define HW_SPI_H + +//************************************************************************************************* +// +// The following are defines for the SPI register offsets +// +//************************************************************************************************* +#define SPI_O_CCR 0x0U // SPI Configuration Control Register +#define SPI_O_CTL 0x1U // SPI Operation Control Register +#define SPI_O_STS 0x2U // SPI Status Register +#define SPI_O_BRR 0x4U // SPI Baud Rate Register +#define SPI_O_RXEMU 0x6U // SPI Emulation Buffer Register +#define SPI_O_RXBUF 0x7U // SPI Serial Input Buffer Register +#define SPI_O_TXBUF 0x8U // SPI Serial Output Buffer Register +#define SPI_O_DAT 0x9U // SPI Serial Data Register +#define SPI_O_FFTX 0xAU // SPI FIFO Transmit Register +#define SPI_O_FFRX 0xBU // SPI FIFO Receive Register +#define SPI_O_FFCT 0xCU // SPI FIFO Control Register +#define SPI_O_PRI 0xFU // SPI Priority Control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICCR register +// +//************************************************************************************************* +#define SPI_CCR_SPICHAR_S 0U +#define SPI_CCR_SPICHAR_M 0xFU // Character Length Control +#define SPI_CCR_SPILBK 0x10U // SPI Loopback +#define SPI_CCR_HS_MODE 0x20U // High Speed mode control +#define SPI_CCR_CLKPOLARITY 0x40U // Shift Clock Polarity +#define SPI_CCR_SPISWRESET 0x80U // SPI Software Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICTL register +// +//************************************************************************************************* +#define SPI_CTL_SPIINTENA 0x1U // SPI Interupt Enable +#define SPI_CTL_TALK 0x2U // Master/Slave Transmit Enable +#define SPI_CTL_MASTER_SLAVE 0x4U // SPI Network Mode Control +#define SPI_CTL_CLK_PHASE 0x8U // SPI Clock Phase +#define SPI_CTL_OVERRUNINTENA 0x10U // Overrun Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPISTS register +// +//************************************************************************************************* +#define SPI_STS_BUFFULL_FLAG 0x20U // SPI Transmit Buffer Full Flag +#define SPI_STS_INT_FLAG 0x40U // SPI Interrupt Flag +#define SPI_STS_OVERRUN_FLAG 0x80U // SPI Receiver Overrun Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIBRR register +// +//************************************************************************************************* +#define SPI_BRR_SPI_BIT_RATE_S 0U +#define SPI_BRR_SPI_BIT_RATE_M 0x7FU // SPI Bit Rate Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFTX register +// +//************************************************************************************************* +#define SPI_FFTX_TXFFIL_S 0U +#define SPI_FFTX_TXFFIL_M 0x1FU // TXFIFO Interrupt Level +#define SPI_FFTX_TXFFIENA 0x20U // TXFIFO Interrupt Enable +#define SPI_FFTX_TXFFINTCLR 0x40U // TXFIFO Interrupt Clear +#define SPI_FFTX_TXFFINT 0x80U // TXFIFO Interrupt Flag +#define SPI_FFTX_TXFFST_S 8U +#define SPI_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define SPI_FFTX_TXFIFO 0x2000U // TXFIFO Reset +#define SPI_FFTX_SPIFFENA 0x4000U // FIFO Enhancements Enable +#define SPI_FFTX_SPIRST 0x8000U // SPI Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFRX register +// +//************************************************************************************************* +#define SPI_FFRX_RXFFIL_S 0U +#define SPI_FFRX_RXFFIL_M 0x1FU // RXFIFO Interrupt Level +#define SPI_FFRX_RXFFIENA 0x20U // RXFIFO Interrupt Enable +#define SPI_FFRX_RXFFINTCLR 0x40U // RXFIFO Interupt Clear +#define SPI_FFRX_RXFFINT 0x80U // RXFIFO Interrupt Flag +#define SPI_FFRX_RXFFST_S 8U +#define SPI_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define SPI_FFRX_RXFIFORESET 0x2000U // RXFIFO Reset +#define SPI_FFRX_RXFFOVFCLR 0x4000U // Receive FIFO Overflow Clear +#define SPI_FFRX_RXFFOVF 0x8000U // Receive FIFO Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFCT register +// +//************************************************************************************************* +#define SPI_FFCT_TXDLY_S 0U +#define SPI_FFCT_TXDLY_M 0xFFU // FIFO Transmit Delay Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIPRI register +// +//************************************************************************************************* +#define SPI_PRI_TRIWIRE 0x1U // 3-wire mode select bit +#define SPI_PRI_STEINV 0x2U // SPISTE inversion bit +#define SPI_PRI_FREE 0x10U // Free emulation mode +#define SPI_PRI_SOFT 0x20U // Soft emulation mode + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_sysctl.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_sysctl.h new file mode 100644 index 0000000..11df8d3 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_sysctl.h @@ -0,0 +1,1428 @@ +//########################################################################### +// +// FILE: hw_sysctl.h +// +// TITLE: Definitions for the SYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SYSCTL_H +#define HW_SYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the SYSCTL register offsets +// +//************************************************************************************************* +#define SYSCTL_O_DEVCFGLOCK1 0x0U // Lock bit for CPUSELx registers +#define SYSCTL_O_PARTIDL 0x8U // Lower 32-bit of Device PART Identification Number +#define SYSCTL_O_PARTIDH 0xAU // Upper 32-bit of Device PART Identification Number +#define SYSCTL_O_REVID 0xCU // Device Revision Number +#define SYSCTL_O_DC0 0x10U // Device Capability: Device Information +#define SYSCTL_O_DC1 0x12U // Device Capability: Processing Block Customization +#define SYSCTL_O_DC2 0x14U // Device Capability: EMIF Customization +#define SYSCTL_O_DC3 0x16U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC4 0x18U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC5 0x1AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC6 0x1CU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC7 0x1EU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC8 0x20U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC9 0x22U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC10 0x24U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC11 0x26U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC12 0x28U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC13 0x2AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC14 0x2CU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC15 0x2EU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC17 0x32U // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC18 0x34U // Device Capability: CPU1 Lx SRAM Customization +#define SYSCTL_O_DC19 0x36U // Device Capability: CPU2 Lx SRAM Customization +#define SYSCTL_O_DC20 0x38U // Device Capability: GSx SRAM Customization +#define SYSCTL_O_PERCNF1 0x60U // Peripheral Configuration register +#define SYSCTL_O_FUSEERR 0x74U // e-Fuse error Status register +#define SYSCTL_O_SOFTPRES0 0x82U // Processing Block Software Reset register +#define SYSCTL_O_SOFTPRES1 0x84U // EMIF Software Reset register +#define SYSCTL_O_SOFTPRES2 0x86U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES3 0x88U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES4 0x8AU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES6 0x8EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES7 0x90U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES8 0x92U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES9 0x94U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES11 0x98U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES13 0x9CU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES14 0x9EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES16 0xA2U // Peripheral Software Reset register +#define SYSCTL_O_CPUSEL0 0xD6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL1 0xD8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL2 0xDAU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL4 0xDEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL5 0xE0U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL6 0xE2U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL7 0xE4U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL8 0xE6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL9 0xE8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL11 0xECU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL12 0xEEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL14 0xF2U // CPU Select register for common peripherals +#define SYSCTL_O_CPU2RESCTL 0x122U // CPU2 Reset Control Register +#define SYSCTL_O_RSTSTAT 0x124U // Reset Status register for secondary C28x CPUs +#define SYSCTL_O_LPMSTAT 0x125U // LPM Status Register for secondary C28x CPUs +#define SYSCTL_O_SYSDBGCTL 0x12CU // System Debug Control register + +#define SYSCTL_O_CLKSEM 0x0U // Clock Control Semaphore Register +#define SYSCTL_O_CLKCFGLOCK1 0x2U // Lock bit for CLKCFG registers +#define SYSCTL_O_CLKSRCCTL1 0x8U // Clock Source Control register-1 +#define SYSCTL_O_CLKSRCCTL2 0xAU // Clock Source Control register-2 +#define SYSCTL_O_CLKSRCCTL3 0xCU // Clock Source Control register-3 +#define SYSCTL_O_SYSPLLCTL1 0xEU // SYSPLL Control register-1 +#define SYSCTL_O_SYSPLLMULT 0x14U // SYSPLL Multiplier register +#define SYSCTL_O_SYSPLLSTS 0x16U // SYSPLL Status register +#define SYSCTL_O_AUXPLLCTL1 0x18U // AUXPLL Control register-1 +#define SYSCTL_O_AUXPLLMULT 0x1EU // AUXPLL Multiplier register +#define SYSCTL_O_AUXPLLSTS 0x20U // AUXPLL Status register +#define SYSCTL_O_SYSCLKDIVSEL 0x22U // System Clock Divider Select register +#define SYSCTL_O_AUXCLKDIVSEL 0x24U // Auxillary Clock Divider Select register +#define SYSCTL_O_PERCLKDIVSEL 0x26U // Peripheral Clock Divider Selet register +#define SYSCTL_O_XCLKOUTDIVSEL 0x28U // XCLKOUT Divider Select register +#define SYSCTL_O_LOSPCP 0x2CU // Low Speed Clock Source Prescalar +#define SYSCTL_O_MCDCR 0x2EU // Missing Clock Detect Control Register +#define SYSCTL_O_X1CNT 0x30U // 10-bit Counter on X1 Clock + +#define SYSCTL_O_CPUSYSLOCK1 0x0U // Lock bit for CPUSYS registers +#define SYSCTL_O_HIBBOOTMODE 0x6U // HIB Boot Mode Register +#define SYSCTL_O_IORESTOREADDR 0x8U // IORestore() routine Address Register +#define SYSCTL_O_PIEVERRADDR 0xAU // PIE Vector Fetch Error Address register +#define SYSCTL_O_PCLKCR0 0x22U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR1 0x24U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR2 0x26U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR3 0x28U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR4 0x2AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR6 0x2EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR7 0x30U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR8 0x32U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR9 0x34U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR10 0x36U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR11 0x38U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR12 0x3AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR13 0x3CU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR14 0x3EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR16 0x42U // Peripheral Clock Gating Registers +#define SYSCTL_O_SECMSEL 0x74U // Secondary Master Select register for common + // peripherals: Selects between CLA & DMA +#define SYSCTL_O_LPMCR 0x76U // LPM Control Register +#define SYSCTL_O_GPIOLPMSEL0 0x78U // GPIO LPM Wakeup select registers +#define SYSCTL_O_GPIOLPMSEL1 0x7AU // GPIO LPM Wakeup select registers +#define SYSCTL_O_TMR2CLKCTL 0x7CU // Timer2 Clock Measurement functionality control register +#define SYSCTL_O_RESC 0x80U // Reset Cause register + +#define SYSCTL_O_SCSR 0x22U // System Control & Status Register +#define SYSCTL_O_WDCNTR 0x23U // Watchdog Counter Register +#define SYSCTL_O_WDKEY 0x25U // Watchdog Reset Key Register +#define SYSCTL_O_WDCR 0x29U // Watchdog Control Register +#define SYSCTL_O_WDWCR 0x2AU // Watchdog Windowed Control Register + +#define SYSCTL_O_CLA1TASKSRCSELLOCK 0x0U // CLA1 Task Trigger Source Select Lock Register +#define SYSCTL_O_DMACHSRCSELLOCK 0x4U // DMA Channel Triger Source Select Lock Register +#define SYSCTL_O_CLA1TASKSRCSEL1 0x6U // CLA1 Task Trigger Source Select Register-1 +#define SYSCTL_O_CLA1TASKSRCSEL2 0x8U // CLA1 Task Trigger Source Select Register-2 +#define SYSCTL_O_DMACHSRCSEL1 0x16U // DMA Channel Trigger Source Select Register-1 +#define SYSCTL_O_DMACHSRCSEL2 0x18U // DMA Channel Trigger Source Select Register-2 + +#define SYSCTL_O_SYNCSELECT 0x0U // Sync Input and Output Select Register +#define SYSCTL_O_ADCSOCOUTSELECT 0x2U // External ADC (Off Chip) SOC Select Register +#define SYSCTL_O_SYNCSOCLOCK 0x4U // SYNCSEL and EXTADCSOC Select Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEVCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_DEVCFGLOCK1_CPUSEL0 0x1U // Lock bit for CPUSEL0 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL1 0x2U // Lock bit for CPUSEL1 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL2 0x4U // Lock bit for CPUSEL2 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL3 0x8U // Lock bit for CPUSEL3 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL4 0x10U // Lock bit for CPUSEL4 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL5 0x20U // Lock bit for CPUSEL5 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL6 0x40U // Lock bit for CPUSEL6 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL7 0x80U // Lock bit for CPUSEL7 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL8 0x100U // Lock bit for CPUSEL8 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL9 0x200U // Lock bit for CPUSEL9 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL10 0x400U // Lock bit for CPUSEL10 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL11 0x800U // Lock bit for CPUSEL11 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL12 0x1000U // Lock bit for CPUSEL12 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL13 0x2000U // Lock bit for CPUSEL13 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL14 0x4000U // Lock bit for CPUSEL14 register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDL register +// +//************************************************************************************************* +#define SYSCTL_PARTIDL_QUAL_S 6U +#define SYSCTL_PARTIDL_QUAL_M 0xC0U // Qualification Status +#define SYSCTL_PARTIDL_PIN_COUNT_S 8U +#define SYSCTL_PARTIDL_PIN_COUNT_M 0x700U // Device Pin Count +#define SYSCTL_PARTIDL_INSTASPIN_S 13U +#define SYSCTL_PARTIDL_INSTASPIN_M 0x6000U // Motorware feature set +#define SYSCTL_PARTIDL_FLASH_SIZE_S 16U +#define SYSCTL_PARTIDL_FLASH_SIZE_M 0xFF0000U // Flash size in KB +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S 28U +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M 0xF0000000U // Revision of the PARTID format + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDH register +// +//************************************************************************************************* +#define SYSCTL_PARTIDH_FAMILY_S 8U +#define SYSCTL_PARTIDH_FAMILY_M 0xFF00U // Device family +#define SYSCTL_PARTIDH_PARTNO_S 16U +#define SYSCTL_PARTIDH_PARTNO_M 0xFF0000U // Device part number +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_S 24U +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_M 0xFF000000U // Device class ID + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC0 register +// +//************************************************************************************************* +#define SYSCTL_DC0_SINGLE_CORE 0x1U // Single Core vs Dual Core + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC1 register +// +//************************************************************************************************* +#define SYSCTL_DC1_CPU1_FPU_TMU 0x1U // CPU1's FPU1+TMU1 +#define SYSCTL_DC1_CPU2_FPU_TMU 0x2U // CPU2's FPU2+TMU2 +#define SYSCTL_DC1_CPU1_VCU 0x4U // CPU1's VCU +#define SYSCTL_DC1_CPU2_VCU 0x8U // CPU2's VCU +#define SYSCTL_DC1_CPU1_CLA1 0x40U // CPU1.CLA1 +#define SYSCTL_DC1_CPU2_CLA1 0x100U // CPU2.CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC2 register +// +//************************************************************************************************* +#define SYSCTL_DC2_EMIF1 0x1U // EMIF1 +#define SYSCTL_DC2_EMIF2 0x2U // EMIF2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC3 register +// +//************************************************************************************************* +#define SYSCTL_DC3_EPWM1 0x1U // EPWM1 +#define SYSCTL_DC3_EPWM2 0x2U // EPWM2 +#define SYSCTL_DC3_EPWM3 0x4U // EPWM3 +#define SYSCTL_DC3_EPWM4 0x8U // EPWM4 +#define SYSCTL_DC3_EPWM5 0x10U // EPWM5 +#define SYSCTL_DC3_EPWM6 0x20U // EPWM6 +#define SYSCTL_DC3_EPWM7 0x40U // EPWM7 +#define SYSCTL_DC3_EPWM8 0x80U // EPWM8 +#define SYSCTL_DC3_EPWM9 0x100U // EPWM9 +#define SYSCTL_DC3_EPWM10 0x200U // EPWM10 +#define SYSCTL_DC3_EPWM11 0x400U // EPWM11 +#define SYSCTL_DC3_EPWM12 0x800U // EPWM12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC4 register +// +//************************************************************************************************* +#define SYSCTL_DC4_ECAP1 0x1U // ECAP1 +#define SYSCTL_DC4_ECAP2 0x2U // ECAP2 +#define SYSCTL_DC4_ECAP3 0x4U // ECAP3 +#define SYSCTL_DC4_ECAP4 0x8U // ECAP4 +#define SYSCTL_DC4_ECAP5 0x10U // ECAP5 +#define SYSCTL_DC4_ECAP6 0x20U // ECAP6 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC5 register +// +//************************************************************************************************* +#define SYSCTL_DC5_EQEP1 0x1U // EQEP1 +#define SYSCTL_DC5_EQEP2 0x2U // EQEP2 +#define SYSCTL_DC5_EQEP3 0x4U // EQEP3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC6 register +// +//************************************************************************************************* +#define SYSCTL_DC6_CLB1 0x1U // CLB1 +#define SYSCTL_DC6_CLB2 0x2U // CLB2 +#define SYSCTL_DC6_CLB3 0x4U // CLB3 +#define SYSCTL_DC6_CLB4 0x8U // CLB4 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC7 register +// +//************************************************************************************************* +#define SYSCTL_DC7_SD1 0x1U // SD1 +#define SYSCTL_DC7_SD2 0x2U // SD2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC8 register +// +//************************************************************************************************* +#define SYSCTL_DC8_SCI_A 0x1U // SCI_A +#define SYSCTL_DC8_SCI_B 0x2U // SCI_B +#define SYSCTL_DC8_SCI_C 0x4U // SCI_C +#define SYSCTL_DC8_SCI_D 0x8U // SCI_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC9 register +// +//************************************************************************************************* +#define SYSCTL_DC9_SPI_A 0x1U // SPI_A +#define SYSCTL_DC9_SPI_B 0x2U // SPI_B +#define SYSCTL_DC9_SPI_C 0x4U // SPI_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC10 register +// +//************************************************************************************************* +#define SYSCTL_DC10_I2C_A 0x1U // I2C_A +#define SYSCTL_DC10_I2C_B 0x2U // I2C_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC11 register +// +//************************************************************************************************* +#define SYSCTL_DC11_CAN_A 0x1U // CAN_A +#define SYSCTL_DC11_CAN_B 0x2U // CAN_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC12 register +// +//************************************************************************************************* +#define SYSCTL_DC12_MCBSP_A 0x1U // McBSP_A +#define SYSCTL_DC12_MCBSP_B 0x2U // McBSP_B +#define SYSCTL_DC12_USB_A_S 16U +#define SYSCTL_DC12_USB_A_M 0x30000U // Decides the capability of the USB_A Module + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC13 register +// +//************************************************************************************************* +#define SYSCTL_DC13_UPP_A 0x1U // uPP_A + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC14 register +// +//************************************************************************************************* +#define SYSCTL_DC14_ADC_A 0x1U // ADC_A +#define SYSCTL_DC14_ADC_B 0x2U // ADC_B +#define SYSCTL_DC14_ADC_C 0x4U // ADC_C +#define SYSCTL_DC14_ADC_D 0x8U // ADC_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC15 register +// +//************************************************************************************************* +#define SYSCTL_DC15_CMPSS1 0x1U // CMPSS1 +#define SYSCTL_DC15_CMPSS2 0x2U // CMPSS2 +#define SYSCTL_DC15_CMPSS3 0x4U // CMPSS3 +#define SYSCTL_DC15_CMPSS4 0x8U // CMPSS4 +#define SYSCTL_DC15_CMPSS5 0x10U // CMPSS5 +#define SYSCTL_DC15_CMPSS6 0x20U // CMPSS6 +#define SYSCTL_DC15_CMPSS7 0x40U // CMPSS7 +#define SYSCTL_DC15_CMPSS8 0x80U // CMPSS8 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC17 register +// +//************************************************************************************************* +#define SYSCTL_DC17_DAC_A 0x10000U // Buffered-DAC_A +#define SYSCTL_DC17_DAC_B 0x20000U // Buffered-DAC_B +#define SYSCTL_DC17_DAC_C 0x40000U // Buffered-DAC_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC18 register +// +//************************************************************************************************* +#define SYSCTL_DC18_LS0_1 0x1U // LS0_1 +#define SYSCTL_DC18_LS1_1 0x2U // LS1_1 +#define SYSCTL_DC18_LS2_1 0x4U // LS2_1 +#define SYSCTL_DC18_LS3_1 0x8U // LS3_1 +#define SYSCTL_DC18_LS4_1 0x10U // LS4_1 +#define SYSCTL_DC18_LS5_1 0x20U // LS5_1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC19 register +// +//************************************************************************************************* +#define SYSCTL_DC19_LS0_2 0x1U // LS0_2 +#define SYSCTL_DC19_LS1_2 0x2U // LS1_2 +#define SYSCTL_DC19_LS2_2 0x4U // LS2_2 +#define SYSCTL_DC19_LS3_2 0x8U // LS3_2 +#define SYSCTL_DC19_LS4_2 0x10U // LS4_2 +#define SYSCTL_DC19_LS5_2 0x20U // LS5_2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC20 register +// +//************************************************************************************************* +#define SYSCTL_DC20_GS0 0x1U // GS0 +#define SYSCTL_DC20_GS1 0x2U // GS1 +#define SYSCTL_DC20_GS2 0x4U // GS2 +#define SYSCTL_DC20_GS3 0x8U // GS3 +#define SYSCTL_DC20_GS4 0x10U // GS4 +#define SYSCTL_DC20_GS5 0x20U // GS5 +#define SYSCTL_DC20_GS6 0x40U // GS6 +#define SYSCTL_DC20_GS7 0x80U // GS7 +#define SYSCTL_DC20_GS8 0x100U // GS8 +#define SYSCTL_DC20_GS9 0x200U // GS9 +#define SYSCTL_DC20_GS10 0x400U // GS10 +#define SYSCTL_DC20_GS11 0x800U // GS11 +#define SYSCTL_DC20_GS12 0x1000U // GS12 +#define SYSCTL_DC20_GS13 0x2000U // GS13 +#define SYSCTL_DC20_GS14 0x4000U // GS14 +#define SYSCTL_DC20_GS15 0x8000U // GS15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCNF1 register +// +//************************************************************************************************* +#define SYSCTL_PERCNF1_ADC_A_MODE 0x1U // ADC_A mode setting bit +#define SYSCTL_PERCNF1_ADC_B_MODE 0x2U // ADC_B mode setting bit +#define SYSCTL_PERCNF1_ADC_C_MODE 0x4U // ADC_C mode setting bit +#define SYSCTL_PERCNF1_ADC_D_MODE 0x8U // ADC_D mode setting bit +#define SYSCTL_PERCNF1_USB_A_PHY 0x10000U // USB_A_PHY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FUSEERR register +// +//************************************************************************************************* +#define SYSCTL_FUSEERR_ALERR_S 0U +#define SYSCTL_FUSEERR_ALERR_M 0x1FU // Efuse Autoload Error Status +#define SYSCTL_FUSEERR_ERR 0x20U // Efuse Self Test Error Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES0 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES0_CPU1_CLA1 0x1U // CPU1_CLA1 software reset bit +#define SYSCTL_SOFTPRES0_CPU2_CLA1 0x4U // CPU2_CLA1 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES1 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES1_EMIF1 0x1U // EMIF1 software reset bit +#define SYSCTL_SOFTPRES1_EMIF2 0x2U // EMIF2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES2 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES2_EPWM1 0x1U // EPWM1 software reset bit +#define SYSCTL_SOFTPRES2_EPWM2 0x2U // EPWM2 software reset bit +#define SYSCTL_SOFTPRES2_EPWM3 0x4U // EPWM3 software reset bit +#define SYSCTL_SOFTPRES2_EPWM4 0x8U // EPWM4 software reset bit +#define SYSCTL_SOFTPRES2_EPWM5 0x10U // EPWM5 software reset bit +#define SYSCTL_SOFTPRES2_EPWM6 0x20U // EPWM6 software reset bit +#define SYSCTL_SOFTPRES2_EPWM7 0x40U // EPWM7 software reset bit +#define SYSCTL_SOFTPRES2_EPWM8 0x80U // EPWM8 software reset bit +#define SYSCTL_SOFTPRES2_EPWM9 0x100U // EPWM9 software reset bit +#define SYSCTL_SOFTPRES2_EPWM10 0x200U // EPWM10 software reset bit +#define SYSCTL_SOFTPRES2_EPWM11 0x400U // EPWM11 software reset bit +#define SYSCTL_SOFTPRES2_EPWM12 0x800U // EPWM12 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES3 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES3_ECAP1 0x1U // ECAP1 software reset bit +#define SYSCTL_SOFTPRES3_ECAP2 0x2U // ECAP2 software reset bit +#define SYSCTL_SOFTPRES3_ECAP3 0x4U // ECAP3 software reset bit +#define SYSCTL_SOFTPRES3_ECAP4 0x8U // ECAP4 software reset bit +#define SYSCTL_SOFTPRES3_ECAP5 0x10U // ECAP5 software reset bit +#define SYSCTL_SOFTPRES3_ECAP6 0x20U // ECAP6 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES4 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES4_EQEP1 0x1U // EQEP1 software reset bit +#define SYSCTL_SOFTPRES4_EQEP2 0x2U // EQEP2 software reset bit +#define SYSCTL_SOFTPRES4_EQEP3 0x4U // EQEP3 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES6 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES6_SD1 0x1U // SD1 software reset bit +#define SYSCTL_SOFTPRES6_SD2 0x2U // SD2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES7 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES7_SCI_A 0x1U // SCI_A software reset bit +#define SYSCTL_SOFTPRES7_SCI_B 0x2U // SCI_B software reset bit +#define SYSCTL_SOFTPRES7_SCI_C 0x4U // SCI_C software reset bit +#define SYSCTL_SOFTPRES7_SCI_D 0x8U // SCI_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES8 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES8_SPI_A 0x1U // SPI_A software reset bit +#define SYSCTL_SOFTPRES8_SPI_B 0x2U // SPI_B software reset bit +#define SYSCTL_SOFTPRES8_SPI_C 0x4U // SPI_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES9 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES9_I2C_A 0x1U // I2C_A software reset bit +#define SYSCTL_SOFTPRES9_I2C_B 0x2U // I2C_B software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES11 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES11_MCBSP_A 0x1U // McBSP_A software reset bit +#define SYSCTL_SOFTPRES11_MCBSP_B 0x2U // McBSP_B software reset bit +#define SYSCTL_SOFTPRES11_USB_A 0x10000U // USB_A software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES13 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES13_ADC_A 0x1U // ADC_A software reset bit +#define SYSCTL_SOFTPRES13_ADC_B 0x2U // ADC_B software reset bit +#define SYSCTL_SOFTPRES13_ADC_C 0x4U // ADC_C software reset bit +#define SYSCTL_SOFTPRES13_ADC_D 0x8U // ADC_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES14 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES14_CMPSS1 0x1U // CMPSS1 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS2 0x2U // CMPSS2 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS3 0x4U // CMPSS3 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS4 0x8U // CMPSS4 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS5 0x10U // CMPSS5 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS6 0x20U // CMPSS6 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS7 0x40U // CMPSS7 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS8 0x80U // CMPSS8 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES16 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES16_DAC_A 0x10000U // Buffered_DAC_A software reset bit +#define SYSCTL_SOFTPRES16_DAC_B 0x20000U // Buffered_DAC_B software reset bit +#define SYSCTL_SOFTPRES16_DAC_C 0x40000U // Buffered_DAC_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL0 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL0_EPWM1 0x1U // EPWM1 CPU select bit +#define SYSCTL_CPUSEL0_EPWM2 0x2U // EPWM2 CPU select bit +#define SYSCTL_CPUSEL0_EPWM3 0x4U // EPWM3 CPU select bit +#define SYSCTL_CPUSEL0_EPWM4 0x8U // EPWM4 CPU select bit +#define SYSCTL_CPUSEL0_EPWM5 0x10U // EPWM5 CPU select bit +#define SYSCTL_CPUSEL0_EPWM6 0x20U // EPWM6 CPU select bit +#define SYSCTL_CPUSEL0_EPWM7 0x40U // EPWM7 CPU select bit +#define SYSCTL_CPUSEL0_EPWM8 0x80U // EPWM8 CPU select bit +#define SYSCTL_CPUSEL0_EPWM9 0x100U // EPWM9 CPU select bit +#define SYSCTL_CPUSEL0_EPWM10 0x200U // EPWM10 CPU select bit +#define SYSCTL_CPUSEL0_EPWM11 0x400U // EPWM11 CPU select bit +#define SYSCTL_CPUSEL0_EPWM12 0x800U // EPWM12 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL1_ECAP1 0x1U // ECAP1 CPU select bit +#define SYSCTL_CPUSEL1_ECAP2 0x2U // ECAP2 CPU select bit +#define SYSCTL_CPUSEL1_ECAP3 0x4U // ECAP3 CPU select bit +#define SYSCTL_CPUSEL1_ECAP4 0x8U // ECAP4 CPU select bit +#define SYSCTL_CPUSEL1_ECAP5 0x10U // ECAP5 CPU select bit +#define SYSCTL_CPUSEL1_ECAP6 0x20U // ECAP6 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL2_EQEP1 0x1U // EQEP1 CPU select bit +#define SYSCTL_CPUSEL2_EQEP2 0x2U // EQEP2 CPU select bit +#define SYSCTL_CPUSEL2_EQEP3 0x4U // EQEP3 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL4 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL4_SD1 0x1U // SD1 CPU select bit +#define SYSCTL_CPUSEL4_SD2 0x2U // SD2 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL5 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL5_SCI_A 0x1U // SCI_A CPU select bit +#define SYSCTL_CPUSEL5_SCI_B 0x2U // SCI_B CPU select bit +#define SYSCTL_CPUSEL5_SCI_C 0x4U // SCI_C CPU select bit +#define SYSCTL_CPUSEL5_SCI_D 0x8U // SCI_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL6 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL6_SPI_A 0x1U // SPI_A CPU select bit +#define SYSCTL_CPUSEL6_SPI_B 0x2U // SPI_B CPU select bit +#define SYSCTL_CPUSEL6_SPI_C 0x4U // SPI_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL7 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL7_I2C_A 0x1U // I2C_A CPU select bit +#define SYSCTL_CPUSEL7_I2C_B 0x2U // I2C_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL8 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL8_CAN_A 0x1U // CAN_A CPU select bit +#define SYSCTL_CPUSEL8_CAN_B 0x2U // CAN_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL9 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL9_MCBSP_A 0x1U // McBSP_A CPU select bit +#define SYSCTL_CPUSEL9_MCBSP_B 0x2U // McBSP_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL11 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL11_ADC_A 0x1U // ADC_A CPU select bit +#define SYSCTL_CPUSEL11_ADC_B 0x2U // ADC_B CPU select bit +#define SYSCTL_CPUSEL11_ADC_C 0x4U // ADC_C CPU select bit +#define SYSCTL_CPUSEL11_ADC_D 0x8U // ADC_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL12 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL12_CMPSS1 0x1U // CMPSS1 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS2 0x2U // CMPSS2 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS3 0x4U // CMPSS3 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS4 0x8U // CMPSS4 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS5 0x10U // CMPSS5 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS6 0x20U // CMPSS6 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS7 0x40U // CMPSS7 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS8 0x80U // CMPSS8 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL14 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL14_DAC_A 0x10000U // Buffered_DAC_A CPU select bit +#define SYSCTL_CPUSEL14_DAC_B 0x20000U // Buffered_DAC_B CPU select bit +#define SYSCTL_CPUSEL14_DAC_C 0x40000U // Buffered_DAC_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPU2RESCTL register +// +//************************************************************************************************* +#define SYSCTL_CPU2RESCTL_RESET 0x1U // CPU2 Reset Control bit +#define SYSCTL_CPU2RESCTL_KEY_S 16U +#define SYSCTL_CPU2RESCTL_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RSTSTAT register +// +//************************************************************************************************* +#define SYSCTL_RSTSTAT_CPU2RES 0x1U // CPU2 Reset Status bit +#define SYSCTL_RSTSTAT_CPU2NMIWDRST 0x2U // Indicates whether a CPU2.NMIWD reset was issued + // to CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST0 0x4U // Indicates whether a HWBIST reset was issued to + // CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST1 0x8U // Indicates whether a HWBIST reset was issued to + // CPU2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMSTAT register +// +//************************************************************************************************* +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_S 0U +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_M 0x3U // CPU2 LPM Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSDBGCTL register +// +//************************************************************************************************* +#define SYSCTL_SYSDBGCTL_BIT_0 0x1U // Used in PLL startup. Only reset by POR. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSEM register +// +//************************************************************************************************* +#define SYSCTL_CLKSEM_SEM_S 0U +#define SYSCTL_CLKSEM_SEM_M 0x3U // Semaphore for CLKCFG Ownership by CPU1 or CPU2 +#define SYSCTL_CLKSEM_KEY_S 16U +#define SYSCTL_CLKSEM_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL1 0x1U // Lock bit for CLKSRCCTL1 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL2 0x2U // Lock bit for CLKSRCCTL2 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL3 0x4U // Lock bit for CLKSRCCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL1 0x8U // Lock bit for SYSPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL2 0x10U // Lock bit for SYSPLLCTL2 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL3 0x20U // Lock bit for SYSPLLCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLMULT 0x40U // Lock bit for SYSPLLMULT register +#define SYSCTL_CLKCFGLOCK1_AUXPLLCTL1 0x80U // Lock bit for AUXPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_AUXPLLMULT 0x400U // Lock bit for AUXPLLMULT register +#define SYSCTL_CLKCFGLOCK1_SYSCLKDIVSEL 0x800U // Lock bit for SYSCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_AUXCLKDIVSEL 0x1000U // Lock bit for AUXCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_PERCLKDIVSEL 0x2000U // Lock bit for PERCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_LOSPCP 0x8000U // Lock bit for LOSPCP register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL1 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M 0x3U // OSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL1_INTOSC2OFF 0x8U // Internal Oscillator 2 Off Bit +#define SYSCTL_CLKSRCCTL1_XTALOFF 0x10U // Crystal (External) Oscillator Off Bit +#define SYSCTL_CLKSRCCTL1_WDHALTI 0x20U // Watchdog HALT Mode Ignore Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL2 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M 0x3U // AUXOSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_S 2U +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_M 0xCU // CANA Bit Clock Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S 4U +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M 0x30U // CANB Bit Clock Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL3 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_S 0U +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M 0x7U // XCLKOUT Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLCTL1_PLLEN 0x1U // SYSPLL enable/disable bit +#define SYSCTL_SYSPLLCTL1_PLLCLKEN 0x2U // SYSPLL bypassed or included in the PLLSYSCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLMULT_IMULT_S 0U +#define SYSCTL_SYSPLLMULT_IMULT_M 0x7FU // SYSPLL Integer Multiplier +#define SYSCTL_SYSPLLMULT_FMULT_S 8U +#define SYSCTL_SYSPLLMULT_FMULT_M 0x300U // SYSPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLSTS_LOCKS 0x1U // SYSPLL Lock Status Bit +#define SYSCTL_SYSPLLSTS_SLIPS 0x2U // SYSPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLCTL1_PLLEN 0x1U // AUXPLL enable/disable bit +#define SYSCTL_AUXPLLCTL1_PLLCLKEN 0x2U // AUXPLL bypassed or included in the AUXPLLCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLMULT_IMULT_S 0U +#define SYSCTL_AUXPLLMULT_IMULT_M 0x7FU // AUXPLL Integer Multiplier +#define SYSCTL_AUXPLLMULT_FMULT_S 8U +#define SYSCTL_AUXPLLMULT_FMULT_M 0x300U // AUXPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLSTS_LOCKS 0x1U // AUXPLL Lock Status Bit +#define SYSCTL_AUXPLLSTS_SLIPS 0x2U // AUXPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_S 0U +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M 0x3FU // PLLSYSCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_S 0U +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M 0x3U // AUXPLLCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_S 0U +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M 0x3U // EPWM Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV 0x10U // EMIF1 Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV 0x40U // EMIF2 Clock Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCLKOUTDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_S 0U +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M 0x3U // XCLKOUT Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOSPCP register +// +//************************************************************************************************* +#define SYSCTL_LOSPCP_LSPCLKDIV_S 0U +#define SYSCTL_LOSPCP_LSPCLKDIV_M 0x7U // LSPCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCDCR register +// +//************************************************************************************************* +#define SYSCTL_MCDCR_MCLKSTS 0x1U // Missing Clock Status Bit +#define SYSCTL_MCDCR_MCLKCLR 0x2U // Missing Clock Clear Bit +#define SYSCTL_MCDCR_MCLKOFF 0x4U // Missing Clock Detect Off Bit +#define SYSCTL_MCDCR_OSCOFF 0x8U // Oscillator Clock Off Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the X1CNT register +// +//************************************************************************************************* +#define SYSCTL_X1CNT_X1CNT_S 0U +#define SYSCTL_X1CNT_X1CNT_M 0x3FFU // X1 Counter + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSYSLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSYSLOCK1_HIBBOOTMODE 0x1U // Lock bit for HIBBOOTMODE register +#define SYSCTL_CPUSYSLOCK1_IORESTOREADDR 0x2U // Lock bit for IORESTOREADDR Register +#define SYSCTL_CPUSYSLOCK1_PIEVERRADDR 0x4U // Lock bit for PIEVERRADDR Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR0 0x8U // Lock bit for PCLKCR0 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR1 0x10U // Lock bit for PCLKCR1 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR2 0x20U // Lock bit for PCLKCR2 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR3 0x40U // Lock bit for PCLKCR3 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR4 0x80U // Lock bit for PCLKCR4 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR5 0x100U // Lock bit for PCLKCR5 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR6 0x200U // Lock bit for PCLKCR6 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR7 0x400U // Lock bit for PCLKCR7 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR8 0x800U // Lock bit for PCLKCR8 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR9 0x1000U // Lock bit for PCLKCR9 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR10 0x2000U // Lock bit for PCLKCR10 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR11 0x4000U // Lock bit for PCLKCR11 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR12 0x8000U // Lock bit for PCLKCR12 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR13 0x10000U // Lock bit for PCLKCR13 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR14 0x20000U // Lock bit for PCLKCR14 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR15 0x40000U // Lock bit for PCLKCR15 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR16 0x80000U // Lock bit for PCLKCR16 Register +#define SYSCTL_CPUSYSLOCK1_SECMSEL 0x100000U // Lock bit for SECMSEL Register +#define SYSCTL_CPUSYSLOCK1_LPMCR 0x200000U // Lock bit for LPMCR Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL0 0x400000U // Lock bit for GPIOLPMSEL0 Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL1 0x800000U // Lock bit for GPIOLPMSEL1 Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IORESTOREADDR register +// +//************************************************************************************************* +#define SYSCTL_IORESTOREADDR_ADDR_S 0U +#define SYSCTL_IORESTOREADDR_ADDR_M 0x3FFFFFU // restoreIO() routine address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEVERRADDR register +// +//************************************************************************************************* +#define SYSCTL_PIEVERRADDR_ADDR_S 0U +#define SYSCTL_PIEVERRADDR_ADDR_M 0x3FFFFFU // PIE Vector Fetch Error Handler Routine Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR0 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR0_CLA1 0x1U // CLA1 Clock Enable Bit +#define SYSCTL_PCLKCR0_DMA 0x4U // DMA Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER0 0x8U // CPUTIMER0 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER1 0x10U // CPUTIMER1 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER2 0x20U // CPUTIMER2 Clock Enable bit +#define SYSCTL_PCLKCR0_HRPWM 0x10000U // HRPWM Clock Enable Bit +#define SYSCTL_PCLKCR0_TBCLKSYNC 0x40000U // EPWM Time Base Clock sync +#define SYSCTL_PCLKCR0_GTBCLKSYNC 0x80000U // EPWM Time Base Clock Global sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR1 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR1_EMIF1 0x1U // EMIF1 Clock Enable bit +#define SYSCTL_PCLKCR1_EMIF2 0x2U // EMIF2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR2 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR2_EPWM1 0x1U // EPWM1 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM2 0x2U // EPWM2 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM3 0x4U // EPWM3 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM4 0x8U // EPWM4 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM5 0x10U // EPWM5 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM6 0x20U // EPWM6 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM7 0x40U // EPWM7 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM8 0x80U // EPWM8 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM9 0x100U // EPWM9 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM10 0x200U // EPWM10 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM11 0x400U // EPWM11 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM12 0x800U // EPWM12 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR3 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR3_ECAP1 0x1U // ECAP1 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP2 0x2U // ECAP2 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP3 0x4U // ECAP3 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP4 0x8U // ECAP4 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP5 0x10U // ECAP5 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP6 0x20U // ECAP6 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR4 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR4_EQEP1 0x1U // EQEP1 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP2 0x2U // EQEP2 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP3 0x4U // EQEP3 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR6 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR6_SD1 0x1U // SD1 Clock Enable bit +#define SYSCTL_PCLKCR6_SD2 0x2U // SD2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR7 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR7_SCI_A 0x1U // SCI_A Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_B 0x2U // SCI_B Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_C 0x4U // SCI_C Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_D 0x8U // SCI_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR8 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR8_SPI_A 0x1U // SPI_A Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_B 0x2U // SPI_B Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_C 0x4U // SPI_C Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR9 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR9_I2C_A 0x1U // I2C_A Clock Enable bit +#define SYSCTL_PCLKCR9_I2C_B 0x2U // I2C_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR10 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR10_CAN_A 0x1U // CAN_A Clock Enable bit +#define SYSCTL_PCLKCR10_CAN_B 0x2U // CAN_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR11 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR11_MCBSP_A 0x1U // McBSP_A Clock Enable bit +#define SYSCTL_PCLKCR11_MCBSP_B 0x2U // McBSP_B Clock Enable bit +#define SYSCTL_PCLKCR11_USB_A 0x10000U // USB_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR12 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR12_UPP_A 0x1U // uPP_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR13 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR13_ADC_A 0x1U // ADC_A Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_B 0x2U // ADC_B Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_C 0x4U // ADC_C Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_D 0x8U // ADC_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR14 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR14_CMPSS1 0x1U // CMPSS1 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS2 0x2U // CMPSS2 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS3 0x4U // CMPSS3 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS4 0x8U // CMPSS4 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS5 0x10U // CMPSS5 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS6 0x20U // CMPSS6 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS7 0x40U // CMPSS7 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS8 0x80U // CMPSS8 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR16 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR16_DAC_A 0x10000U // Buffered_DAC_A Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_B 0x20000U // Buffered_DAC_B Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_C 0x40000U // Buffered_DAC_C Clock Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECMSEL register +// +//************************************************************************************************* +#define SYSCTL_SECMSEL_PF1SEL_S 0U +#define SYSCTL_SECMSEL_PF1SEL_M 0x3U // Secondary Master Select for VBUS32_1 Bridge +#define SYSCTL_SECMSEL_PF2SEL_S 2U +#define SYSCTL_SECMSEL_PF2SEL_M 0xCU // Secondary Master Select for VBUS32_2 Bridge + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMCR register +// +//************************************************************************************************* +#define SYSCTL_LPMCR_LPM_S 0U +#define SYSCTL_LPMCR_LPM_M 0x3U // Low Power Mode setting +#define SYSCTL_LPMCR_QUALSTDBY_S 2U +#define SYSCTL_LPMCR_QUALSTDBY_M 0xFCU // STANDBY Wakeup Pin Qualification Setting +#define SYSCTL_LPMCR_WDINTE 0x8000U // Enable for WDINT wakeup from STANDBY +#define SYSCTL_LPMCR_M0M1MODE_S 16U +#define SYSCTL_LPMCR_M0M1MODE_M 0x30000U // Configuration for M0 and M1 mode during HIB +#define SYSCTL_LPMCR_IOISODIS 0x80000000U // IO Isolation Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL0 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL0_GPIO0 0x1U // GPIO0 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO1 0x2U // GPIO1 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO2 0x4U // GPIO2 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO3 0x8U // GPIO3 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO4 0x10U // GPIO4 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO5 0x20U // GPIO5 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO6 0x40U // GPIO6 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO7 0x80U // GPIO7 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO8 0x100U // GPIO8 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO9 0x200U // GPIO9 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO10 0x400U // GPIO10 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO11 0x800U // GPIO11 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO12 0x1000U // GPIO12 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO13 0x2000U // GPIO13 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO14 0x4000U // GPIO14 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO15 0x8000U // GPIO15 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO16 0x10000U // GPIO16 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO17 0x20000U // GPIO17 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO18 0x40000U // GPIO18 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO19 0x80000U // GPIO19 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO20 0x100000U // GPIO20 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO21 0x200000U // GPIO21 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO22 0x400000U // GPIO22 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO23 0x800000U // GPIO23 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO24 0x1000000U // GPIO24 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO25 0x2000000U // GPIO25 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO26 0x4000000U // GPIO26 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO27 0x8000000U // GPIO27 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO28 0x10000000U // GPIO28 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO29 0x20000000U // GPIO29 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO30 0x40000000U // GPIO30 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO31 0x80000000U // GPIO31 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL1 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL1_GPIO32 0x1U // GPIO32 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO33 0x2U // GPIO33 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO34 0x4U // GPIO34 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO35 0x8U // GPIO35 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO36 0x10U // GPIO36 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO37 0x20U // GPIO37 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO38 0x40U // GPIO38 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO39 0x80U // GPIO39 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO40 0x100U // GPIO40 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO41 0x200U // GPIO41 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO42 0x400U // GPIO42 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO43 0x800U // GPIO43 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO44 0x1000U // GPIO44 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO45 0x2000U // GPIO45 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO46 0x4000U // GPIO46 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO47 0x8000U // GPIO47 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO48 0x10000U // GPIO48 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO49 0x20000U // GPIO49 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO50 0x40000U // GPIO50 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO51 0x80000U // GPIO51 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO52 0x100000U // GPIO52 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO53 0x200000U // GPIO53 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO54 0x400000U // GPIO54 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO55 0x800000U // GPIO55 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO56 0x1000000U // GPIO56 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO57 0x2000000U // GPIO57 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO58 0x4000000U // GPIO58 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO59 0x8000000U // GPIO59 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO60 0x10000000U // GPIO60 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO61 0x20000000U // GPIO61 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO62 0x40000000U // GPIO62 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO63 0x80000000U // GPIO63 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TMR2CLKCTL register +// +//************************************************************************************************* +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S 0U +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M 0x7U // CPU Timer 2 Clock Source Select Bit +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S 3U +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M 0x38U // CPU Timer 2 Clock Pre-Scale Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RESC register +// +//************************************************************************************************* +#define SYSCTL_RESC_POR 0x1U // POR Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN 0x2U // XRSn Reset Cause Indication Bit +#define SYSCTL_RESC_WDRSN 0x4U // WDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_NMIWDRSN 0x8U // NMIWDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_HWBISTN 0x20U // HWBISTn Reset Cause Indication Bit +#define SYSCTL_RESC_HIBRESETN 0x40U // HIBRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_SCCRESETN 0x100U // SCCRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN_PIN_STATUS 0x40000000U // XRSN Pin Status +#define SYSCTL_RESC_TRSTN_PIN_STATUS 0x80000000U // TRSTn Status + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCSR register +// +//************************************************************************************************* +#define SYSCTL_SCSR_WDOVERRIDE 0x1U // WD Override for WDDIS bit +#define SYSCTL_SCSR_WDENINT 0x2U // WD Interrupt Enable +#define SYSCTL_SCSR_WDINTS 0x4U // WD Interrupt Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCNTR register +// +//************************************************************************************************* +#define SYSCTL_WDCNTR_WDCNTR_S 0U +#define SYSCTL_WDCNTR_WDCNTR_M 0xFFU // WD Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDKEY register +// +//************************************************************************************************* +#define SYSCTL_WDKEY_WDKEY_S 0U +#define SYSCTL_WDKEY_WDKEY_M 0xFFU // WD KEY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCR register +// +//************************************************************************************************* +#define SYSCTL_WDCR_WDPS_S 0U +#define SYSCTL_WDCR_WDPS_M 0x7U // WD Clock Prescalar +#define SYSCTL_WDCR_WDCHK_S 3U +#define SYSCTL_WDCR_WDCHK_M 0x38U // WD Check Bits +#define SYSCTL_WDCR_WDDIS 0x40U // WD Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDWCR register +// +//************************************************************************************************* +#define SYSCTL_WDWCR_MIN_S 0U +#define SYSCTL_WDWCR_MIN_M 0xFFU // WD Min Threshold setting for Windowed Watchdog + // functionality +#define SYSCTL_WDWCR_FIRSTKEY 0x100U // First Key Detect Flag + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL1 0x1U // CLA1TASKSRCSEL1 Register Lock bit +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL2 0x2U // CLA1TASKSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL1 0x1U // DMACHSRCSEL1 Register Lock bit +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL2 0x2U // DMACHSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_S 0U +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_M 0xFFU // Selects the Trigger Source for TASK1 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_S 8U +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_M 0xFF00U // Selects the Trigger Source for TASK2 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_S 16U +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_M 0xFF0000U // Selects the Trigger Source for TASK3 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_S 24U +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_M 0xFF000000U // Selects the Trigger Source for TASK4 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_S 0U +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_M 0xFFU // Selects the Trigger Source for TASK5 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_S 8U +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_M 0xFF00U // Selects the Trigger Source for TASK6 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_S 16U +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_M 0xFF0000U // Selects the Trigger Source for TASK7 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_S 24U +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_M 0xFF000000U // Selects the Trigger Source for TASK8 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL1_CH1_S 0U +#define SYSCTL_DMACHSRCSEL1_CH1_M 0xFFU // Selects the Trigger and Sync Source CH1 of DMA +#define SYSCTL_DMACHSRCSEL1_CH2_S 8U +#define SYSCTL_DMACHSRCSEL1_CH2_M 0xFF00U // Selects the Trigger and Sync Source CH2 of DMA +#define SYSCTL_DMACHSRCSEL1_CH3_S 16U +#define SYSCTL_DMACHSRCSEL1_CH3_M 0xFF0000U // Selects the Trigger and Sync Source CH3 of DMA +#define SYSCTL_DMACHSRCSEL1_CH4_S 24U +#define SYSCTL_DMACHSRCSEL1_CH4_M 0xFF000000U // Selects the Trigger and Sync Source CH4 of DMA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL2_CH5_S 0U +#define SYSCTL_DMACHSRCSEL2_CH5_M 0xFFU // Selects the Trigger and Sync Source CH5 of DMA +#define SYSCTL_DMACHSRCSEL2_CH6_S 8U +#define SYSCTL_DMACHSRCSEL2_CH6_M 0xFF00U // Selects the Trigger and Sync Source CH6 of DMA + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSELECT register +// +//************************************************************************************************* +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_S 0U +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_M 0x7U // Selects Sync Input Source for EPWM4 +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_S 3U +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_M 0x38U // Selects Sync Input Source for EPWM7 +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_S 6U +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_M 0x1C0U // Selects Sync Input Source for EPWM10 +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_S 9U +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_M 0xE00U // Selects Sync Input Source for ECAP1 +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_S 12U +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_M 0x7000U // Selects Sync Input Source for ECAP4 +#define SYSCTL_SYNCSELECT_SYNCOUT_S 27U +#define SYSCTL_SYNCSELECT_SYNCOUT_M 0x18000000U // Select Syncout Source + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOUTSELECT register +// +//************************************************************************************************* +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCAEN 0x1U // PWM1SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCAEN 0x2U // PWM2SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCAEN 0x4U // PWM3SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCAEN 0x8U // PWM4SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCAEN 0x10U // PWM5SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCAEN 0x20U // PWM6SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCAEN 0x40U // PWM7SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCAEN 0x80U // PWM8SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCAEN 0x100U // PWM9SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCAEN 0x200U // PWM10SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCAEN 0x400U // PWM11SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCAEN 0x800U // PWM12SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCBEN 0x10000U // PWM1SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCBEN 0x20000U // PWM2SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCBEN 0x40000U // PWM3SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCBEN 0x80000U // PWM4SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCBEN 0x100000U // PWM5SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCBEN 0x200000U // PWM6SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCBEN 0x400000U // PWM7SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCBEN 0x800000U // PWM8SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCBEN 0x1000000U // PWM9SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCBEN 0x2000000U // PWM10SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCBEN 0x4000000U // PWM11SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCBEN 0x8000000U // PWM12SOCBEN Enable for ADCSOCBO + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSOCLOCK register +// +//************************************************************************************************* +#define SYSCTL_SYNCSOCLOCK_SYNCSELECT 0x1U // SYNCSEL Register Lock bit +#define SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT 0x2U // ADCSOCOUTSELECT Register Lock bit + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_types.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_types.h new file mode 100644 index 0000000..8c1b32d --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_types.h @@ -0,0 +1,166 @@ +//########################################################################### +// +// FILE: hw_types.h +// +// TITLE: Type definitions used in driverlib functions. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_TYPES_H +#define HW_TYPES_H + +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#if defined(__TMS320C28XX_CLA__) + #define HWREG(x) \ + (*((volatile uint32_t *)((uintptr_t)(x)))) + #define HWREGH(x) \ + (*((volatile uint16_t *)((uintptr_t)(x)))) +#else + #define HWREG(x) \ + (*((volatile uint32_t *)(x))) + #define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#endif + +#define HWREG_BP(x) \ + __byte_peripheral_32((uint32_t *)(x)) +#define HWREGB(x) \ + __byte((int *)(x),0) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_S_SUCCESS (0) +#define STATUS_E_FAILURE (-1) + +//***************************************************************************** +// +// Definition of 8 bit types for USB Driver code to maintain portability +// between byte and word addressable cores of C2000 Devices. +// +//***************************************************************************** +typedef uint16_t uint8_t; +typedef int16_t int8_t; + +//**************************************************************************** +// +// For checking NULL pointers +// +//**************************************************************************** +#ifndef NULL +#define NULL ((void *)0x0) +#endif + +//***************************************************************************** +// +// 32-bit & 64-bit float type +// +//***************************************************************************** +#ifndef C2000_IEEE754_TYPES +#define C2000_IEEE754_TYPES +#ifdef __TI_EABI__ +typedef float float32_t; +typedef double float64_t; +#else // TI COFF +typedef float float32_t; +typedef long double float64_t; +#endif // __TI_EABI__ +#endif // C2000_IEEE754_TYPES + + +//***************************************************************************** +// +// Emulated Bitbanded write +// +//***************************************************************************** +#define HWREGBITW(address, mask, value) \ + (*(volatile uint32_t *)(address)) = \ + ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \ + | ((uint32_t)value << mask) + +#define HWREGBITHW(address, mask, value) \ + (*(volatile uint16_t *)(address)) = \ + ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \ + | ((uint16_t)value << mask) + +//***************************************************************************** +// +// Emulated Bitbanded read +// +//***************************************************************************** +#define HWREGBITR(address, mask) \ + (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask) + +#define HWREGBITHR(address, mask) \ + (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask) + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// These are provided to satisfy static analysis tools. The #ifndef is required +// because the '&' is for a C++-style reference, and although it is the correct +// prototype, it will not build in C code. +// +//***************************************************************************** +#if(defined(__TMS320C28XX__) || defined(__TMS320C28XX_CLA__)) +#else +extern int16_t &__byte(int16_t *array, uint16_t byte_index); +extern uint32_t &__byte_peripheral_32(uint32_t *x); +#endif + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +/* To fix Misra-C errors */ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif // HW_TYPES_H diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_upp.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_upp.h new file mode 100644 index 0000000..9f73e9b --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_upp.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: hw_upp.h +// +// TITLE: Definitions for the UPP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_UPP_H +#define HW_UPP_H + +//************************************************************************************************* +// +// The following are defines for the UPP register offsets +// +//************************************************************************************************* +#define UPP_O_PID 0x0U // Peripheral ID Register +#define UPP_O_PERCTL 0x2U // Peripheral Control Register +#define UPP_O_CHCTL 0x8U // General Control Register +#define UPP_O_IFCFG 0xAU // Interface Configuration Register +#define UPP_O_IFIVAL 0xCU // Interface Idle Value Register +#define UPP_O_THCFG 0xEU // Threshold Configuration Register +#define UPP_O_RAWINTST 0x10U // Raw Interrupt Status Register +#define UPP_O_ENINTST 0x12U // Enable Interrupt Status Register +#define UPP_O_INTENSET 0x14U // Interrupt Enable Set Register +#define UPP_O_INTENCLR 0x16U // Interrupt Enable Clear Register +#define UPP_O_CHIDESC0 0x20U // DMA Channel I Descriptor 0 Register +#define UPP_O_CHIDESC1 0x22U // DMA Channel I Descriptor 1 Register +#define UPP_O_CHIDESC2 0x24U // DMA Channel I Descriptor 2 Register +#define UPP_O_CHIST0 0x28U // DMA Channel I Status 0 Register +#define UPP_O_CHIST1 0x2AU // DMA Channel I Status 1 Register +#define UPP_O_CHIST2 0x2CU // DMA Channel I Status 2 Register +#define UPP_O_CHQDESC0 0x30U // DMA Channel Q Descriptor 0 Register +#define UPP_O_CHQDESC1 0x32U // DMA Channel Q Descriptor 1 Register +#define UPP_O_CHQDESC2 0x34U // DMA Channel Q Descriptor 2 Register +#define UPP_O_CHQST0 0x38U // DMA Channel Q Status 0 Register +#define UPP_O_CHQST1 0x3AU // DMA Channel Q Status 1 Register +#define UPP_O_CHQST2 0x3CU // DMA Channel Q Status 2 Register +#define UPP_O_GINTEN 0x40U // Global Peripheral Interrupt Enable Register +#define UPP_O_GINTFLG 0x42U // Global Peripheral Interrupt Flag Register +#define UPP_O_GINTCLR 0x44U // Global Peripheral Interrupt Clear Register +#define UPP_O_DLYCTL 0x46U // IO clock data skew control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCTL register +// +//************************************************************************************************* +#define UPP_PERCTL_FREE 0x1U // Emulation control. +#define UPP_PERCTL_SOFT 0x2U // Emulation control. +#define UPP_PERCTL_RTEMU 0x4U // Realtime emulation control. +#define UPP_PERCTL_PEREN 0x8U // Peripheral Enable +#define UPP_PERCTL_SOFTRST 0x10U // Software Reset +#define UPP_PERCTL_DMAST 0x80U // DMA Burst transaction status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHCTL register +// +//************************************************************************************************* +#define UPP_CHCTL_MODE_S 0U +#define UPP_CHCTL_MODE_M 0x3U // Operating mode +#define UPP_CHCTL_SDRTXILA 0x8U // SDR TX Interleve mode +#define UPP_CHCTL_DEMUXA 0x10U // DDR de-multiplexing mode +#define UPP_CHCTL_DRA 0x10000U // Data rate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFCFG register +// +//************************************************************************************************* +#define UPP_IFCFG_STARTPOLA 0x1U // Polarity of START(SELECT) signal +#define UPP_IFCFG_ENAPOLA 0x2U // Polarity of ENABLE(WRITE) signal +#define UPP_IFCFG_WAITPOLA 0x4U // Polarity of WAIT signal. +#define UPP_IFCFG_STARTA 0x8U // Enable Usage of START (SELECT) signal +#define UPP_IFCFG_ENAA 0x10U // Enable Usage of ENABLE (WRITE) signal +#define UPP_IFCFG_WAITA 0x20U // Enable Usage of WAIT signal +#define UPP_IFCFG_CLKDIVA_S 8U +#define UPP_IFCFG_CLKDIVA_M 0xF00U // Clock divider for tx mode +#define UPP_IFCFG_CLKINVA 0x1000U // Clock inversion +#define UPP_IFCFG_TRISENA 0x2000U // Pin Tri-state Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFIVAL register +// +//************************************************************************************************* +#define UPP_IFIVAL_VALA_S 0U +#define UPP_IFIVAL_VALA_M 0x1FFU // Idle Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the THCFG register +// +//************************************************************************************************* +#define UPP_THCFG_RDSIZEI_S 0U +#define UPP_THCFG_RDSIZEI_M 0x3U // DMA Read Threshold for DMA Channel I +#define UPP_THCFG_RDSIZEQ_S 8U +#define UPP_THCFG_RDSIZEQ_M 0x300U // DMA Read Threshold for DMA Channel Q +#define UPP_THCFG_TXSIZEA_S 16U +#define UPP_THCFG_TXSIZEA_M 0x30000U // I/O Transmit Threshold Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAWINTST register +// +//************************************************************************************************* +#define UPP_RAWINTST_DPEI 0x1U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEI 0x2U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWI 0x8U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLI 0x10U // Interrupt raw status for end-of-line condition +#define UPP_RAWINTST_DPEQ 0x100U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEQ 0x200U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWQ 0x800U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLQ 0x1000U // Interrupt raw status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ENINTST register +// +//************************************************************************************************* +#define UPP_ENINTST_DPEI 0x1U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEI 0x2U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWI 0x8U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLI 0x10U // Interrupt enable status for end-of-line condition +#define UPP_ENINTST_DPEQ 0x100U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEQ 0x200U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWQ 0x800U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLQ 0x1000U // Interrupt enable status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENSET register +// +//************************************************************************************************* +#define UPP_INTENSET_DPEI 0x1U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEI 0x2U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWI 0x8U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLI 0x10U // Interrupt enable for end-of-line condition +#define UPP_INTENSET_DPEQ 0x100U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEQ 0x200U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWQ 0x800U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLQ 0x1000U // Interrupt enable for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENCLR register +// +//************************************************************************************************* +#define UPP_INTENCLR_DPEI 0x1U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEI 0x2U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWI 0x8U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLI 0x10U // Interrupt clear for end-of-line condition +#define UPP_INTENCLR_DPEQ 0x100U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEQ 0x200U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWQ 0x800U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLQ 0x1000U // Interrupt clear for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC1 register +// +//************************************************************************************************* +#define UPP_CHIDESC1_BCNT_S 0U +#define UPP_CHIDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel I + // transfer. +#define UPP_CHIDESC1_LCNT_S 16U +#define UPP_CHIDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel I + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC2 register +// +//************************************************************************************************* +#define UPP_CHIDESC2_LOFFSET_S 0U +#define UPP_CHIDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST1 register +// +//************************************************************************************************* +#define UPP_CHIST1_BCNT_S 0U +#define UPP_CHIST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHIST1_LCNT_S 16U +#define UPP_CHIST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST2 register +// +//************************************************************************************************* +#define UPP_CHIST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHIST2_PEND 0x2U // Status of DMA. +#define UPP_CHIST2_WM_S 4U +#define UPP_CHIST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel I tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC1 register +// +//************************************************************************************************* +#define UPP_CHQDESC1_BCNT_S 0U +#define UPP_CHQDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel Q + // transfer. +#define UPP_CHQDESC1_LCNT_S 16U +#define UPP_CHQDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel Q + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC2 register +// +//************************************************************************************************* +#define UPP_CHQDESC2_LOFFSET_S 0U +#define UPP_CHQDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST1 register +// +//************************************************************************************************* +#define UPP_CHQST1_BCNT_S 0U +#define UPP_CHQST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHQST1_LCNT_S 16U +#define UPP_CHQST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST2 register +// +//************************************************************************************************* +#define UPP_CHQST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHQST2_PEND 0x2U // Status of DMA. +#define UPP_CHQST2_WM_S 4U +#define UPP_CHQST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel Q tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTEN register +// +//************************************************************************************************* +#define UPP_GINTEN_GINTEN 0x1U // Global Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTFLG register +// +//************************************************************************************************* +#define UPP_GINTFLG_GINTFLG 0x1U // Global Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTCLR register +// +//************************************************************************************************* +#define UPP_GINTCLR_GINTCLR 0x1U // Global Interrupt Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DLYCTL register +// +//************************************************************************************************* +#define UPP_DLYCTL_DLYDIS 0x1U // IO dealy control disable. +#define UPP_DLYCTL_DLYCTL_S 1U +#define UPP_DLYCTL_DLYCTL_M 0x6U // IO delay control. + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_usb.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_usb.h new file mode 100644 index 0000000..27907eb --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_usb.h @@ -0,0 +1,4614 @@ +//########################################################################### +// +// FILE: hw_usb.h +// +// TITLE: Definitions for the USB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_USB_H +#define HW_USB_H + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST +#define USB_IS_DISCON 0x00000020 // Session Disconnect +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt +#define USB_IE_SESREQ 0x00000040 // Enable Session Request +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO15_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. +// +//***************************************************************************** +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. +// +//***************************************************************************** +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL8_STALL 0x00000010 // Send STALL +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL8_ERROR 0x00000004 // Error +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. +// +//***************************************************************************** +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH8_MODE 0x00000020 // Mode +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL8_STALL 0x00000020 // Send STALL +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL8_OVER 0x00000004 // Overrun +#define USB_RXCSRL8_ERROR 0x00000004 // Error +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. +// +//***************************************************************************** +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. +// +//***************************************************************************** +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. +// +//***************************************************************************** +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL9_STALL 0x00000010 // Send STALL +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL9_ERROR 0x00000004 // Error +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH9_MODE 0x00000020 // Mode +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL9_STALL 0x00000020 // Send STALL +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL9_ERROR 0x00000004 // Error +#define USB_RXCSRL9_OVER 0x00000004 // Overrun +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. +// +//***************************************************************************** +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. +// +//***************************************************************************** +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. +// +//***************************************************************************** +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL10_STALL 0x00000010 // Send STALL +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL10_ERROR 0x00000004 // Error +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH10_MODE 0x00000020 // Mode +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL10_STALL 0x00000020 // Send STALL +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL10_OVER 0x00000004 // Overrun +#define USB_RXCSRL10_ERROR 0x00000004 // Error +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT10_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. +// +//***************************************************************************** +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. +// +//***************************************************************************** +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. +// +//***************************************************************************** +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. +// +//***************************************************************************** +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL11_STALL 0x00000010 // Send STALL +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL11_ERROR 0x00000004 // Error +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH11_MODE 0x00000020 // Mode +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL11_STALL 0x00000020 // Send STALL +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL11_OVER 0x00000004 // Overrun +#define USB_RXCSRL11_ERROR 0x00000004 // Error +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL12_STALL 0x00000010 // Send STALL +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL12_ERROR 0x00000004 // Error +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH12_MODE 0x00000020 // Mode +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL12_STALL 0x00000020 // Send STALL +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL12_ERROR 0x00000004 // Error +#define USB_RXCSRL12_OVER 0x00000004 // Overrun +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL13_STALL 0x00000010 // Send STALL +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL13_ERROR 0x00000004 // Error +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH13_MODE 0x00000020 // Mode +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL13_STALL 0x00000020 // Send STALL +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL13_OVER 0x00000004 // Overrun +#define USB_RXCSRL13_ERROR 0x00000004 // Error +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL14_STALL 0x00000010 // Send STALL +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL14_ERROR 0x00000004 // Error +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH14_MODE 0x00000020 // Mode +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL14_STALL 0x00000020 // Send STALL +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL14_OVER 0x00000004 // Overrun +#define USB_RXCSRL14_ERROR 0x00000004 // Error +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL15_STALL 0x00000010 // Send STALL +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL15_ERROR 0x00000004 // Error +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH15_MODE 0x00000020 // Mode +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL15_STALL 0x00000020 // Send STALL +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL15_ERROR 0x00000004 // Error +#define USB_RXCSRL15_OVER 0x00000004 // Overrun +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_TXFIFOADD register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_RXFIFOADD register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 + +#endif + +#endif // __HW_USB_H__ diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_xbar.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_xbar.h new file mode 100644 index 0000000..7869257 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_xbar.h @@ -0,0 +1,271 @@ +//########################################################################### +// +// FILE: hw_xbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XBAR_H +#define HW_XBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_FLG1 0x0U // X-Bar Input Flag Register 1 +#define XBAR_O_FLG2 0x2U // X-Bar Input Flag Register 2 +#define XBAR_O_FLG3 0x4U // X-Bar Input Flag Register 3 +#define XBAR_O_CLR1 0x8U // X-Bar Input Flag Clear Register 1 +#define XBAR_O_CLR2 0xAU // X-Bar Input Flag Clear Register 2 +#define XBAR_O_CLR3 0xCU // X-Bar Input Flag Clear Register 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG1 register +// +//************************************************************************************************* +#define XBAR_FLG1_CMPSS1_CTRIPL 0x1U // Input Flag for CMPSS1.CTRIPL Signal +#define XBAR_FLG1_CMPSS1_CTRIPH 0x2U // Input Flag for CMPSS1.CTRIPH Signal +#define XBAR_FLG1_CMPSS2_CTRIPL 0x4U // Input Flag for CMPSS2.CTRIPL Signal +#define XBAR_FLG1_CMPSS2_CTRIPH 0x8U // Input Flag for CMPSS2.CTRIPH Signal +#define XBAR_FLG1_CMPSS3_CTRIPL 0x10U // Input Flag for CMPSS3.CTRIPL Signal +#define XBAR_FLG1_CMPSS3_CTRIPH 0x20U // Input Flag for CMPSS3.CTRIPH Signal +#define XBAR_FLG1_CMPSS4_CTRIPL 0x40U // Input Flag for CMPSS4.CTRIPL Signal +#define XBAR_FLG1_CMPSS4_CTRIPH 0x80U // Input Flag for CMPSS4.CTRIPH Signal +#define XBAR_FLG1_CMPSS5_CTRIPL 0x100U // Input Flag for CMPSS5.CTRIPL Signal +#define XBAR_FLG1_CMPSS5_CTRIPH 0x200U // Input Flag for CMPSS5.CTRIPH Signal +#define XBAR_FLG1_CMPSS6_CTRIPL 0x400U // Input Flag for CMPSS6.CTRIPL Signal +#define XBAR_FLG1_CMPSS6_CTRIPH 0x800U // Input Flag for CMPSS6.CTRIPH Signal +#define XBAR_FLG1_CMPSS7_CTRIPL 0x1000U // Input Flag for CMPSS7.CTRIPL Signal +#define XBAR_FLG1_CMPSS7_CTRIPH 0x2000U // Input Flag for CMPSS7.CTRIPH Signal +#define XBAR_FLG1_CMPSS8_CTRIPL 0x4000U // Input Flag for CMPSS8.CTRIPL Signal +#define XBAR_FLG1_CMPSS8_CTRIPH 0x8000U // Input Flag for CMPSS8.CTRIPH Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag for CMPSS1.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag for CMPSS1.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag for CMPSS2.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag for CMPSS2.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag for CMPSS3.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag for CMPSS3.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag for CMPSS4.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag for CMPSS4.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag for CMPSS5.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag for CMPSS5.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag for CMPSS6.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag for CMPSS6.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag for CMPSS7.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag for CMPSS7.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag for CMPSS8.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG2 register +// +//************************************************************************************************* +#define XBAR_FLG2_INPUT1 0x1U // Input Flag for INPUT1 Signal +#define XBAR_FLG2_INPUT2 0x2U // Input Flag for INPUT2 Signal +#define XBAR_FLG2_INPUT3 0x4U // Input Flag for INPUT3 Signal +#define XBAR_FLG2_INPUT4 0x8U // Input Flag for INPUT4 Signal +#define XBAR_FLG2_INPUT5 0x10U // Input Flag for INPUT5 Signal +#define XBAR_FLG2_INPUT6 0x20U // Input Flag for INPUT6 Signal +#define XBAR_FLG2_ADCSOCAO 0x40U // Input Flag for ADCSOCAO Signal +#define XBAR_FLG2_ADCSOCBO 0x80U // Input Flag for ADCSOCBO Signal +#define XBAR_FLG2_CLB1_OUT4 0x100U // Input Flag for CLB1_OUT4 Signal +#define XBAR_FLG2_CLB1_OUT5 0x200U // Input Flag for CLB1_OUT5 Signal +#define XBAR_FLG2_CLB2_OUT4 0x400U // Input Flag for CLB2_OUT4 Signal +#define XBAR_FLG2_CLB2_OUT5 0x800U // Input Flag for CLB2_OUT5 Signal +#define XBAR_FLG2_CLB3_OUT4 0x1000U // Input Flag for CLB3_OUT4 Signal +#define XBAR_FLG2_CLB3_OUT5 0x2000U // Input Flag for CLB3_OUT5 Signal +#define XBAR_FLG2_CLB4_OUT4 0x4000U // Input Flag for CLB4_OUT4 Signal +#define XBAR_FLG2_CLB4_OUT5 0x8000U // Input Flag for CLB4_OUT5 Signal +#define XBAR_FLG2_ECAP1_OUT 0x10000U // Input Flag for ECAP1.OUT Signal +#define XBAR_FLG2_ECAP2_OUT 0x20000U // Input Flag for ECAP2.OUT Signal +#define XBAR_FLG2_ECAP3_OUT 0x40000U // Input Flag for ECAP3.OUT Signal +#define XBAR_FLG2_ECAP4_OUT 0x80000U // Input Flag for ECAP4.OUT Signal +#define XBAR_FLG2_ECAP5_OUT 0x100000U // Input Flag for ECAP5.OUT Signal +#define XBAR_FLG2_ECAP6_OUT 0x200000U // Input Flag for ECAP6.OUT Signal +#define XBAR_FLG2_EXTSYNCOUT 0x400000U // Input Flag for EXTSYNCOUT Signal +#define XBAR_FLG2_ADCAEVT1 0x800000U // Input Flag for ADCAEVT1 Signal +#define XBAR_FLG2_ADCAEVT2 0x1000000U // Input Flag for ADCAEVT2 Signal +#define XBAR_FLG2_ADCAEVT3 0x2000000U // Input Flag for ADCAEVT3 Signal +#define XBAR_FLG2_ADCAEVT4 0x4000000U // Input Flag for ADCAEVT4 Signal +#define XBAR_FLG2_ADCBEVT1 0x8000000U // Input Flag for ADCBEVT1 Signal +#define XBAR_FLG2_ADCBEVT2 0x10000000U // Input Flag for ADCBEVT2 Signal +#define XBAR_FLG2_ADCBEVT3 0x20000000U // Input Flag for ADCBEVT3 Signal +#define XBAR_FLG2_ADCBEVT4 0x40000000U // Input Flag for ADCBEVT4 Signal +#define XBAR_FLG2_ADCCEVT1 0x80000000U // Input Flag for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG3 register +// +//************************************************************************************************* +#define XBAR_FLG3_ADCCEVT2 0x1U // Input Flag for ADCCEVT2 Signal +#define XBAR_FLG3_ADCCEVT3 0x2U // Input Flag for ADCCEVT3 Signal +#define XBAR_FLG3_ADCCEVT4 0x4U // Input Flag for ADCCEVT4 Signal +#define XBAR_FLG3_ADCDEVT1 0x8U // Input Flag for ADCDEVT1 Signal +#define XBAR_FLG3_ADCDEVT2 0x10U // Input Flag for ADCDEVT2 Signal +#define XBAR_FLG3_ADCDEVT3 0x20U // Input Flag for ADCDEVT3 Signal +#define XBAR_FLG3_ADCDEVT4 0x40U // Input Flag for ADCDEVT4 Signal +#define XBAR_FLG3_SD1FLT1_COMPL 0x80U // Input Flag for SD1FLT1.COMPL Signal +#define XBAR_FLG3_SD1FLT1_COMPH 0x100U // Input Flag for SD1FLT1.COMPH Signal +#define XBAR_FLG3_SD1FLT2_COMPL 0x200U // Input Flag for SD1FLT2.COMPL Signal +#define XBAR_FLG3_SD1FLT2_COMPH 0x400U // Input Flag for SD1FLT2.COMPH Signal +#define XBAR_FLG3_SD1FLT3_COMPL 0x800U // Input Flag for SD1FLT3.COMPL Signal +#define XBAR_FLG3_SD1FLT3_COMPH 0x1000U // Input Flag for SD1FLT3.COMPH Signal +#define XBAR_FLG3_SD1FLT4_COMPL 0x2000U // Input Flag for SD1FLT4.COMPL Signal +#define XBAR_FLG3_SD1FLT4_COMPH 0x4000U // Input Flag for SD1FLT4.COMPH Signal +#define XBAR_FLG3_SD2FLT1_COMPL 0x8000U // Input Flag for SD2FLT1.COMPL Signal +#define XBAR_FLG3_SD2FLT1_COMPH 0x10000U // Input Flag for SD2FLT1.COMPH Signal +#define XBAR_FLG3_SD2FLT2_COMPL 0x20000U // Input Flag for SD2FLT2.COMPL Signal +#define XBAR_FLG3_SD2FLT2_COMPH 0x40000U // Input Flag for SD2FLT2.COMPH Signal +#define XBAR_FLG3_SD2FLT3_COMPL 0x80000U // Input Flag for SD2FLT3.COMPL Signal +#define XBAR_FLG3_SD2FLT3_COMPH 0x100000U // Input Flag for SD2FLT3.COMPH Signal +#define XBAR_FLG3_SD2FLT4_COMPL 0x200000U // Input Flag for SD2FLT4.COMPL Signal +#define XBAR_FLG3_SD2FLT4_COMPH 0x400000U // Input Flag for SD2FLT4.COMPH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR1 register +// +//************************************************************************************************* +#define XBAR_CLR1_CMPSS1_CTRIPL 0x1U // Input Flag Clear for CMPSS1.CTRIPL Signal +#define XBAR_CLR1_CMPSS1_CTRIPH 0x2U // Input Flag Clear for CMPSS1.CTRIPH Signal +#define XBAR_CLR1_CMPSS2_CTRIPL 0x4U // Input Flag Clear for CMPSS2.CTRIPL Signal +#define XBAR_CLR1_CMPSS2_CTRIPH 0x8U // Input Flag Clear for CMPSS2.CTRIPH Signal +#define XBAR_CLR1_CMPSS3_CTRIPL 0x10U // Input Flag Clear for CMPSS3.CTRIPL Signal +#define XBAR_CLR1_CMPSS3_CTRIPH 0x20U // Input Flag Clear for CMPSS3.CTRIPH Signal +#define XBAR_CLR1_CMPSS4_CTRIPL 0x40U // Input Flag Clear for CMPSS4.CTRIPL Signal +#define XBAR_CLR1_CMPSS4_CTRIPH 0x80U // Input Flag Clear for CMPSS4.CTRIPH Signal +#define XBAR_CLR1_CMPSS5_CTRIPL 0x100U // Input Flag Clear for CMPSS5.CTRIPL Signal +#define XBAR_CLR1_CMPSS5_CTRIPH 0x200U // Input Flag Clear for CMPSS5.CTRIPH Signal +#define XBAR_CLR1_CMPSS6_CTRIPL 0x400U // Input Flag Clear for CMPSS6.CTRIPL Signal +#define XBAR_CLR1_CMPSS6_CTRIPH 0x800U // Input Flag Clear for CMPSS6.CTRIPH Signal +#define XBAR_CLR1_CMPSS7_CTRIPL 0x1000U // Input Flag Clear for CMPSS7.CTRIPL Signal +#define XBAR_CLR1_CMPSS7_CTRIPH 0x2000U // Input Flag Clear for CMPSS7.CTRIPH Signal +#define XBAR_CLR1_CMPSS8_CTRIPL 0x4000U // Input Flag Clear for CMPSS8.CTRIPL Signal +#define XBAR_CLR1_CMPSS8_CTRIPH 0x8000U // Input Flag Clear for CMPSS8.CTRIPH Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag Clear for CMPSS1.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag Clear for CMPSS1.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag Clear for CMPSS2.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag Clear for CMPSS2.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag Clear for CMPSS3.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag Clear for CMPSS3.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag Clear for CMPSS4.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag Clear for CMPSS4.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag Clear for CMPSS5.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag Clear for CMPSS5.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag Clear for CMPSS6.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag Clear for CMPSS6.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag Clear for CMPSS7.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag Clear for CMPSS7.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag Clear for CMPSS8.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag Clear for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR2 register +// +//************************************************************************************************* +#define XBAR_CLR2_INPUT1 0x1U // Input Flag Clear for INPUT1 Signal +#define XBAR_CLR2_INPUT2 0x2U // Input Flag Clear for INPUT2 Signal +#define XBAR_CLR2_INPUT3 0x4U // Input Flag Clear for INPUT3 Signal +#define XBAR_CLR2_INPUT4 0x8U // Input Flag Clear for INPUT4 Signal +#define XBAR_CLR2_INPUT5 0x10U // Input Flag Clear for INPUT5 Signal +#define XBAR_CLR2_INPUT7 0x20U // Input Flag Clear for INPUT7 Signal +#define XBAR_CLR2_ADCSOCAO 0x40U // Input Flag Clear for ADCSOCAO Signal +#define XBAR_CLR2_ADCSOCBO 0x80U // Input Flag Clear for ADCSOCBO Signal +#define XBAR_CLR2_CLB1_OUT4 0x100U // Input Flag Clear for CLB1_OUT4 Signal +#define XBAR_CLR2_CLB1_OUT5 0x200U // Input Flag Clear for CLB1_OUT5 Signal +#define XBAR_CLR2_CLB2_OUT4 0x400U // Input Flag Clear for CLB2_OUT4 Signal +#define XBAR_CLR2_CLB2_OUT5 0x800U // Input Flag Clear for CLB2_OUT5 Signal +#define XBAR_CLR2_CLB3_OUT4 0x1000U // Input Flag Clear for CLB3_OUT4 Signal +#define XBAR_CLR2_CLB3_OUT5 0x2000U // Input Flag Clear for CLB3_OUT5 Signal +#define XBAR_CLR2_CLB4_OUT4 0x4000U // Input Flag Clear for CLB4_OUT4 Signal +#define XBAR_CLR2_CLB4_OUT5 0x8000U // Input Flag Clear for CLB4_OUT5 Signal +#define XBAR_CLR2_ECAP1_OUT 0x10000U // Input Flag Clear for ECAP1.OUT Signal +#define XBAR_CLR2_ECAP2_OUT 0x20000U // Input Flag Clear for ECAP2.OUT Signal +#define XBAR_CLR2_ECAP3_OUT 0x40000U // Input Flag Clear for ECAP3.OUT Signal +#define XBAR_CLR2_ECAP4_OUT 0x80000U // Input Flag Clear for ECAP4.OUT Signal +#define XBAR_CLR2_ECAP5_OUT 0x100000U // Input Flag Clear for ECAP5.OUT Signal +#define XBAR_CLR2_ECAP6_OUT 0x200000U // Input Flag Clear for ECAP6.OUT Signal +#define XBAR_CLR2_EXTSYNCOUT 0x400000U // Input Flag Clear for EXTSYNCOUT Signal +#define XBAR_CLR2_ADCAEVT1 0x800000U // Input Flag Clear for ADCAEVT1 Signal +#define XBAR_CLR2_ADCAEVT2 0x1000000U // Input Flag Clear for ADCAEVT2 Signal +#define XBAR_CLR2_ADCAEVT3 0x2000000U // Input Flag Clear for ADCAEVT3 Signal +#define XBAR_CLR2_ADCAEVT4 0x4000000U // Input Flag Clear for ADCAEVT4 Signal +#define XBAR_CLR2_ADCBEVT1 0x8000000U // Input Flag Clear for ADCBEVT1 Signal +#define XBAR_CLR2_ADCBEVT2 0x10000000U // Input Flag Clear for ADCBEVT2 Signal +#define XBAR_CLR2_ADCBEVT3 0x20000000U // Input Flag Clear for ADCBEVT3 Signal +#define XBAR_CLR2_ADCBEVT4 0x40000000U // Input Flag Clear for ADCBEVT4 Signal +#define XBAR_CLR2_ADCCEVT1 0x80000000U // Input Flag Clear for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR3 register +// +//************************************************************************************************* +#define XBAR_CLR3_ADCCEVT2 0x1U // Input Flag Clear for ADCCEVT2 Signal +#define XBAR_CLR3_ADCCEVT3 0x2U // Input Flag Clear for ADCCEVT3 Signal +#define XBAR_CLR3_ADCCEVT4 0x4U // Input Flag Clear for ADCCEVT4 Signal +#define XBAR_CLR3_ADCDEVT1 0x8U // Input Flag Clear for ADCDEVT1 Signal +#define XBAR_CLR3_ADCDEVT2 0x10U // Input Flag Clear for ADCDEVT2 Signal +#define XBAR_CLR3_ADCDEVT3 0x20U // Input Flag Clear for ADCDEVT3 Signal +#define XBAR_CLR3_ADCDEVT4 0x40U // Input Flag Clear for ADCDEVT4 Signal +#define XBAR_CLR3_SD1FLT1_COMPL 0x80U // Input Flag Clear for SD1FLT1.COMPL Signal +#define XBAR_CLR3_SD1FLT1_COMPH 0x100U // Input Flag Clear for SD1FLT1.COMPH Signal +#define XBAR_CLR3_SD1FLT2_COMPL 0x200U // Input Flag Clear for SD1FLT2.COMPL Signal +#define XBAR_CLR3_SD1FLT2_COMPH 0x400U // Input Flag Clear for SD1FLT2.COMPH Signal +#define XBAR_CLR3_SD1FLT3_COMPL 0x800U // Input Flag Clear for SD1FLT3.COMPL Signal +#define XBAR_CLR3_SD1FLT3_COMPH 0x1000U // Input Flag Clear for SD1FLT3.COMPH Signal +#define XBAR_CLR3_SD1FLT4_COMPL 0x2000U // Input Flag Clear for SD1FLT4.COMPL Signal +#define XBAR_CLR3_SD1FLT4_COMPH 0x4000U // Input Flag Clear for SD1FLT4.COMPH Signal +#define XBAR_CLR3_SD2FLT1_COMPL 0x8000U // Input Flag Clear for SD2FLT1.COMPL Signal +#define XBAR_CLR3_SD2FLT1_COMPH 0x10000U // Input Flag Clear for SD2FLT1.COMPH Signal +#define XBAR_CLR3_SD2FLT2_COMPL 0x20000U // Input Flag Clear for SD2FLT2.COMPL Signal +#define XBAR_CLR3_SD2FLT2_COMPH 0x40000U // Input Flag Clear for SD2FLT2.COMPH Signal +#define XBAR_CLR3_SD2FLT3_COMPL 0x80000U // Input Flag Clear for SD2FLT3.COMPL Signal +#define XBAR_CLR3_SD2FLT3_COMPH 0x100000U // Input Flag Clear for SD2FLT3.COMPH Signal +#define XBAR_CLR3_SD2FLT4_COMPL 0x200000U // Input Flag Clear for SD2FLT4.COMPL Signal +#define XBAR_CLR3_SD2FLT4_COMPH 0x400000U // Input Flag Clear for SD2FLT4.COMPH Signal + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/inc/hw_xint.h b/gpio_bitfield_cpu1/device/driverlib/inc/hw_xint.h new file mode 100644 index 0000000..677c2f9 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/inc/hw_xint.h @@ -0,0 +1,108 @@ +//########################################################################### +// +// FILE: hw_xint.h +// +// TITLE: Definitions for the XINT registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XINT_H +#define HW_XINT_H + +//************************************************************************************************* +// +// The following are defines for the XINT register offsets +// +//************************************************************************************************* +#define XINT_O_1CR 0x0U // XINT1 configuration register +#define XINT_O_2CR 0x1U // XINT2 configuration register +#define XINT_O_3CR 0x2U // XINT3 configuration register +#define XINT_O_4CR 0x3U // XINT4 configuration register +#define XINT_O_5CR 0x4U // XINT5 configuration register +#define XINT_O_1CTR 0x8U // XINT1 counter register +#define XINT_O_2CTR 0x9U // XINT2 counter register +#define XINT_O_3CTR 0xAU // XINT3 counter register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT1CR register +// +//************************************************************************************************* +#define XINT_1CR_ENABLE 0x1U // XINT1 Enable +#define XINT_1CR_POLARITY_S 2U +#define XINT_1CR_POLARITY_M 0xCU // XINT1 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT2CR register +// +//************************************************************************************************* +#define XINT_2CR_ENABLE 0x1U // XINT2 Enable +#define XINT_2CR_POLARITY_S 2U +#define XINT_2CR_POLARITY_M 0xCU // XINT2 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT3CR register +// +//************************************************************************************************* +#define XINT_3CR_ENABLE 0x1U // XINT3 Enable +#define XINT_3CR_POLARITY_S 2U +#define XINT_3CR_POLARITY_M 0xCU // XINT3 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT4CR register +// +//************************************************************************************************* +#define XINT_4CR_ENABLE 0x1U // XINT4 Enable +#define XINT_4CR_POLARITY_S 2U +#define XINT_4CR_POLARITY_M 0xCU // XINT4 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT5CR register +// +//************************************************************************************************* +#define XINT_5CR_ENABLE 0x1U // XINT5 Enable +#define XINT_5CR_POLARITY_S 2U +#define XINT_5CR_POLARITY_M 0xCU // XINT5 Polarity + + + +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/interrupt.c b/gpio_bitfield_cpu1/device/driverlib/interrupt.c new file mode 100644 index 0000000..4d628ce --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/interrupt.c @@ -0,0 +1,425 @@ +//########################################################################### +// +// FILE: interrupt.c +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Clears the IFR flag in the CPU. +//! +//! \param group specifies the interrupt group to be cleared. +//! +//! This function clears the IFR flag. This switch is needed because the +//! clearing of the IFR can only be done with a constant. +// +//***************************************************************************** +static void Interrupt_clearIFR(uint16_t group) +{ + switch(group) + { + case 0x0001U: + IFR &= ~(uint16_t)0x0001U; + break; + case 0x0002U: + IFR &= ~(uint16_t)0x0002U; + break; + case 0x0004U: + IFR &= ~(uint16_t)0x0004U; + break; + case 0x0008U: + IFR &= ~(uint16_t)0x0008U; + break; + case 0x0010U: + IFR &= ~(uint16_t)0x0010U; + break; + case 0x0020U: + IFR &= ~(uint16_t)0x0020U; + break; + case 0x0040U: + IFR &= ~(uint16_t)0x0040U; + break; + case 0x0080U: + IFR &= ~(uint16_t)0x0080U; + break; + case 0x0100U: + IFR &= ~(uint16_t)0x0100U; + break; + case 0x0200U: + IFR &= ~(uint16_t)0x0200U; + break; + case 0x0400U: + IFR &= ~(uint16_t)0x0400U; + break; + case 0x0800U: + IFR &= ~(uint16_t)0x0800U; + break; + case 0x1000U: + IFR &= ~(uint16_t)0x1000U; + break; + case 0x2000U: + IFR &= ~(uint16_t)0x2000U; + break; + case 0x4000U: + IFR &= ~(uint16_t)0x4000U; + break; + case 0x8000U: + IFR &= ~(uint16_t)0x8000U; + break; + default: + // + // Invalid group mask. + // + ASSERT((bool)false); + break; + } +} + +//***************************************************************************** +// +// Interrupt_initModule +// +//***************************************************************************** +void +Interrupt_initModule(void) +{ + // + // Disable and clear all interrupts at the CPU + // + (void)Interrupt_disableGlobal(); + IER = 0x0000U; + IFR = 0x0000U; + + // + // Clear all PIEIER registers + // + HWREGH(PIECTRL_BASE + PIE_O_IER1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER12) = 0U; + + // + // Clear all PIEIFR registers + // + HWREGH(PIECTRL_BASE + PIE_O_IFR1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR12) = 0U; + + // + // Enable vector fetching from PIE block + // + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; + +} + +//***************************************************************************** +// +//! The default interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_defaultHandler(void) +{ + uint16_t pieVect; + uint16_t vectID; + + // + // Calculate the vector ID. If the vector is in the lower PIE, it's the + // offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT) + // divided by two. + // + pieVect = HWREGH(PIECTRL_BASE + PIE_O_CTRL); + vectID = (pieVect & 0xFEU) >> 1U; + + // + // If the vector is in the upper PIE, the vector ID is 128 or higher. + // + if(pieVect >= 0x0E00U) + { + vectID += 128U; + } + + // + // Something has gone wrong. An interrupt without a proper registered + // handler function has occurred. To help you debug the issue, local + // variable vectID contains the vector ID of the interrupt that occurred. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default illegal instruction trap interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_illegalOperationHandler(void) +{ + // + // Something has gone wrong. The CPU has tried to execute an illegal + // instruction, generating an illegal instruction trap (ITRAP). + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default non-maskable interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_nmiHandler(void) +{ + // + // A non-maskable interrupt has occurred, indicating that a hardware error + // has occurred in the system. You can use SysCtl_getNMIFlagStatus() to + // to read the NMIFLG register and determine what caused the NMI. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +// Interrupt_initVectorTable +// +//***************************************************************************** +void +Interrupt_initVectorTable(void) +{ + uint16_t i; + + EALLOW; + + // + // We skip the first three locations because they are initialized by Boot + // ROM with boot variables. + // + for(i = 3U; i < 224U; i++) + { + HWREG(PIEVECTTABLE_BASE + (2U * i)) = + (uint32_t)Interrupt_defaultHandler; + } + + // + // NMI and ITRAP get their own handlers. + // + HWREG(PIEVECTTABLE_BASE + ((INT_NMI >> 16U) * 2U)) = + (uint32_t)Interrupt_nmiHandler; + HWREG(PIEVECTTABLE_BASE + ((INT_ILLEGAL >> 16U) * 2U)) = + (uint32_t)Interrupt_illegalOperationHandler; + + EDIS; +} + +//***************************************************************************** +// +//Interrupt_enable +// +//***************************************************************************** +void +Interrupt_enable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + // + // Globally disable interrupts but save status + // + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) |= + (uint16_t)1U << ((interruptNumber & 0xFFU) - 1U); + + // + // Enable PIE Group Interrupt + // + IER |= groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER |= (uint16_t)1U << (vectID - 1U); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} + +//***************************************************************************** +// +// Interrupt_disable +// +//***************************************************************************** +void +Interrupt_disable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + // + // Disable individual PIE interrupt + // + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) &= + ~(1U << ((interruptNumber & 0xFFUL) - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR(groupMask); + + // + // Acknowledge any interrupts + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER &= ~((uint16_t)1U << (vectID - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR((uint16_t)1U << (vectID - 1U)); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} diff --git a/gpio_bitfield_cpu1/device/driverlib/interrupt.h b/gpio_bitfield_cpu1/device/driverlib/interrupt.h new file mode 100644 index 0000000..05a555a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/interrupt.h @@ -0,0 +1,497 @@ +//########################################################################### +// +// FILE: interrupt.h +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef INTERRUPT_H +#define INTERRUPT_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup interrupt_api Interrupt +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pie.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_enableInCPU() +// and Interrupt_disableInCPU() functions as the cpuInterrupt parameter. +// +//***************************************************************************** +#define INTERRUPT_CPU_INT1 0x1U //!< CPU Interrupt Number 1 +#define INTERRUPT_CPU_INT2 0x2U //!< CPU Interrupt Number 2 +#define INTERRUPT_CPU_INT3 0x4U //!< CPU Interrupt Number 3 +#define INTERRUPT_CPU_INT4 0x8U //!< CPU Interrupt Number 4 +#define INTERRUPT_CPU_INT5 0x10U //!< CPU Interrupt Number 5 +#define INTERRUPT_CPU_INT6 0x20U //!< CPU Interrupt Number 6 +#define INTERRUPT_CPU_INT7 0x40U //!< CPU Interrupt Number 7 +#define INTERRUPT_CPU_INT8 0x80U //!< CPU Interrupt Number 8 +#define INTERRUPT_CPU_INT9 0x100U //!< CPU Interrupt Number 9 +#define INTERRUPT_CPU_INT10 0x200U //!< CPU Interrupt Number 10 +#define INTERRUPT_CPU_INT11 0x400U //!< CPU Interrupt Number 11 +#define INTERRUPT_CPU_INT12 0x800U //!< CPU Interrupt Number 12 +#define INTERRUPT_CPU_INT13 0x1000U //!< CPU Interrupt Number 13 +#define INTERRUPT_CPU_INT14 0x2000U //!< CPU Interrupt Number 14 +#define INTERRUPT_CPU_DLOGINT 0x4000U //!< CPU Data Log Interrupt +#define INTERRUPT_CPU_RTOSINT 0x8000U //!< CPU RTOS Interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_clearACKGroup() +// function as the group parameter. +// +//***************************************************************************** +#define INTERRUPT_ACK_GROUP1 0x1U //!< Acknowledge PIE Interrupt Group 1 +#define INTERRUPT_ACK_GROUP2 0x2U //!< Acknowledge PIE Interrupt Group 2 +#define INTERRUPT_ACK_GROUP3 0x4U //!< Acknowledge PIE Interrupt Group 3 +#define INTERRUPT_ACK_GROUP4 0x8U //!< Acknowledge PIE Interrupt Group 4 +#define INTERRUPT_ACK_GROUP5 0x10U //!< Acknowledge PIE Interrupt Group 5 +#define INTERRUPT_ACK_GROUP6 0x20U //!< Acknowledge PIE Interrupt Group 6 +#define INTERRUPT_ACK_GROUP7 0x40U //!< Acknowledge PIE Interrupt Group 7 +#define INTERRUPT_ACK_GROUP8 0x80U //!< Acknowledge PIE Interrupt Group 8 +#define INTERRUPT_ACK_GROUP9 0x100U //!< Acknowledge PIE Interrupt Group 9 +#define INTERRUPT_ACK_GROUP10 0x200U //!< Acknowledge PIE Interrupt Group 10 +#define INTERRUPT_ACK_GROUP11 0x400U //!< Acknowledge PIE Interrupt Group 11 +#define INTERRUPT_ACK_GROUP12 0x800U //!< Acknowledge PIE Interrupt Group 12 +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler. The Interrupt_initVectorTable() +//! function sets all vectors to this function. Also, when an interrupt is +//! unregistered using the Interrupt_unregister() function, this handler takes +//! its place. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_defaultHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default illegal instruction trap interrupt handler. +//! +//! This is the default interrupt handler for an illegal instruction trap +//! (ITRAP). The Interrupt_initVectorTable() function sets the appropriate +//! vector to this function. This should never be called during normal +//! operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with +//! an appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_illegalOperationHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default non-maskable interrupt handler. +//! +//! This is the default interrupt handler for a non-maskable interrupt (NMI). +//! The Interrupt_initVectorTable() function sets the appropriate vector to +//! this function. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_nmiHandler(void); + +//***************************************************************************** +// +//! Allows the CPU to process interrupts. +//! +//! This function clears the global interrupt mask bit (INTM) in the CPU, +//! allowing the processor to respond to interrupts. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_enableGlobal(void) +{ + // + // Enable processor interrupts. + // + return(((__enable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Stops the CPU from processing interrupts. +//! +//! This function sets the global interrupt mask bit (INTM) in the CPU, +//! preventing the processor from receiving maskable interrupts. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_disableGlobal(void) +{ + // + // Disable processor interrupts. + // + return(((__disable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! \param handler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via Interrupt_enable()), the handler function will be +//! called in interrupt context. Since the handler function can preempt other +//! code, care must be taken to protect memory or peripherals that are accessed +//! by the handler and other non-handler code. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \note This function assumes that the PIE has been enabled. See +//! Interrupt_initModule(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_register(uint32_t interruptNumber, void (*handler)(void)) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)handler; + EDIS; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! +//! This function is used to indicate that a default handler +//! Interrupt_defaultHandler() should be called when the given interrupt is +//! asserted to the processor. Call Interrupt_disable() to disable +//! the interrupt before calling this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \sa Interrupt_register() for important information about registering +//! interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_unregister(uint32_t interruptNumber) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy default ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)Interrupt_defaultHandler; + EDIS; +} + +//***************************************************************************** +// +//! Enables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be enabled. +//! +//! This function enables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enableInCPU(uint16_t cpuInterrupt) +{ + // + // Set the interrupt bits in the CPU. + // + IER |= cpuInterrupt; +} + +//***************************************************************************** +// +//! Disables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be disabled. +//! +//! This function disables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disableInCPU(uint16_t cpuInterrupt) +{ + // + // Clear the interrupt bits in the CPU. + // + IER &= ~cpuInterrupt; +} + +//***************************************************************************** +// +//! Acknowledges PIE Interrupt Group +//! +//! \param group specifies the interrupt group to be acknowledged. +//! +//! The specified interrupt group is acknowledged and clears any interrupt +//! flag within that respective group. +//! +//! The \e group parameter must be a logical OR of the following: +//! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3 +//! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6 +//! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9 +//! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11, +//! \b INTERRUPT_ACK_GROUP12. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_clearACKGroup(uint16_t group) +{ + // + // Set interrupt group acknowledge bits + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = group; +} + +//***************************************************************************** +// +//! Enables the PIE block. +//! +//! This function enables the vector fetching for the peripheral interrupts by +//! enabling the PIE block. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Disables the PIE block. +//! +//! This function disables the vector fetching for the peripheral interrupts by +//! disabling the PIE block. PIEACK, PIEIFR, and PIEIER registers can be +//! accessed even when the PIE block is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) &= ~PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Initializes the PIE control registers by setting them to a known state. +//! +//! This function initializes the PIE control registers. After globally +//! disabling interrupts and enabling the PIE, it clears all of the PIE +//! interrupt enable bits and interrupt flags. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initModule(void); + +//***************************************************************************** +// +//! Initializes the PIE vector table by setting all vectors to a default +//! handler function. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initVectorTable(void); + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_enable(uint32_t interruptNumber); + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_disable(uint32_t interruptNumber); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // INTERRUPT_H diff --git a/gpio_bitfield_cpu1/device/driverlib/ipc.c b/gpio_bitfield_cpu1/device/driverlib/ipc.c new file mode 100644 index 0000000..8d6982e --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/ipc.c @@ -0,0 +1,445 @@ +//########################################################################### +// +// FILE: ipc.c +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ipc.h" + +// +// Macros internal to the IPC driver +// + +#define IPC_ADDR_OFFSET_NOCHANGE 2U +#define IPC_ADDR_OFFSET_MUL2 4U +#define IPC_ADDR_OFFSET_DIV2 1U + +#define IPC_ADDR_OFFSET_CORR(addr, corr) (((addr) * (corr)) / 2U) + +#if IPC_MSGQ_SUPPORT == 1U + +// +// Global Circular Buffer Definitions +// + + +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_PutBuffer, "MSGRAM_CPU1_TO_CPU2") +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_GetBuffer, "MSGRAM_CPU2_TO_CPU1") + +// +// IPC_CPU1_To_CPU2_PutBuffer acts as IPC_CPU2_To_CPU1_GetBuffer and +// IPC_CPU1_To_CPU2_GetBuffer acts as IPC_CPU2_To_CPU1_PutBuffer +// +IPC_PutBuffer_t IPC_CPU1_To_CPU2_PutBuffer; +IPC_GetBuffer_t IPC_CPU1_To_CPU2_GetBuffer; +#endif + +const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM] = { + + /* IPC_CPU1_L_CPU2_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = &IPC_CPU1_To_CPU2_PutBuffer, + .IPC_GetBuffer = &IPC_CPU1_To_CPU2_GetBuffer +#endif + }, + + /* IPC_CPU2_L_CPU1_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = (IPC_PutBuffer_t *)&IPC_CPU1_To_CPU2_GetBuffer, + .IPC_GetBuffer = (IPC_GetBuffer_t *)&IPC_CPU1_To_CPU2_PutBuffer +#endif + } +}; + +//***************************************************************************** +// +// IPC_sendCommand +// +//***************************************************************************** +bool IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data) +{ + bool ret; + + // + // Check whether the flags are not busy + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) == 0U) + { + ret = true; + + if(addrCorrEnable) + { + // + // Update the command registers. ADDR register holds the offset + // from the base address of the MSG RAM + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = + addr - IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + else + { + // + // Update the command registers. addr param remains as is. + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = addr; + } + + // + // Set the flags to indicate the remote core + // + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; + } + else + { + ret = false; + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readCommand +// +//***************************************************************************** +bool IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data) +{ + bool ret; + uint32_t addrReg; + + // + // Check whether the flags are not empty + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U) + { + ret = true; + + // + // Read the command registers + // + *command = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVCOM; + addrReg = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVADDR; + *data = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVDATA; + + if(addrCorrEnable) + { + // + // Calculate the address form the offset + // + *addr = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(addrReg, + IPC_Instance[ipcType].IPC_Offset_Corr); + + } + else + { + *addr = addrReg; + } + + } + else + { + ret = false; + } + + return(ret); +} + + +//***************************************************************************** +// +// IPC_registerInterrupt +// +//***************************************************************************** +void IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Register the interrupt handler + // + + Interrupt_register(intNum, pfnHandler); + + // + // Enable the interrupt + // + Interrupt_enable(intNum); +} + +//***************************************************************************** +// +// IPC_unregisterInterrupt +// +//***************************************************************************** +void IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Disable the interrupt. + // + Interrupt_disable(intNum); + + // + // Unregister the interrupt handler. + // + + Interrupt_unregister(intNum); +} + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// IPCinitMessageQueue +// +//***************************************************************************** +void IPC_initMessageQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(ipcInt_L < IPC_NUM_OF_INTERRUPTS); + ASSERT(ipcInt_R < IPC_NUM_OF_INTERRUPTS); + + IPC_PutBuffer_t *putBuffer = IPC_Instance[ipcType].IPC_PutBuffer; + IPC_GetBuffer_t *getBuffer = IPC_Instance[ipcType].IPC_GetBuffer; + + // + // L->R Put Buffer and Index Initialization + // + msgQueue->PutBuffer = putBuffer->Buffer[ipcInt_R]; + msgQueue->PutWriteIndex = &(putBuffer->PutWriteIndex[ipcInt_R]); + msgQueue->GetReadIndex = &(putBuffer->GetReadIndex[ipcInt_L]); + msgQueue->PutFlag = (uint32_t)1U << ipcInt_R; + + // + // L->R Get Buffer and Index Initialization + // + msgQueue->GetBuffer = getBuffer->Buffer[ipcInt_L]; + msgQueue->GetWriteIndex = &(getBuffer->GetWriteIndex[ipcInt_L]); + msgQueue->PutReadIndex = &(getBuffer->PutReadIndex[ipcInt_R]); + + // + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + // + *(msgQueue->PutWriteIndex) = 0U; + *(msgQueue->GetReadIndex) = 0U; +} + +//***************************************************************************** +// +// IPC_sendMessageToQueue +// +//***************************************************************************** +bool IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->PutWriteIndex); + readIndex = *(msgQueue->PutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while(((writeIndex + 1U) & IPC_MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + readIndex = *(msgQueue->PutReadIndex); + } + + if(ret != false) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + msgQueue->PutBuffer[writeIndex] = *msg; + + if(addrCorrEnable) + { + msgQueue->PutBuffer[writeIndex].address -= + IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + + writeIndex = (writeIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->PutWriteIndex) = writeIndex; + + IPC_setFlagLtoR(ipcType, msgQueue->PutFlag); + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readMessageFromQueue +// +//***************************************************************************** +bool IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->GetWriteIndex); + readIndex = *(msgQueue->GetReadIndex); + + // + // Loop while GetBuffer is empty + // + while(writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + writeIndex = *(msgQueue->GetWriteIndex); + } + + if(ret != false) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *msg = msgQueue->GetBuffer[readIndex]; + if(addrCorrEnable) + { + msg->address = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(msg->address, + IPC_Instance[ipcType].IPC_Offset_Corr); + } + + readIndex = (readIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->GetReadIndex) = readIndex; + } + + return(ret); +} +#endif diff --git a/gpio_bitfield_cpu1/device/driverlib/ipc.h b/gpio_bitfield_cpu1/device/driverlib/ipc.h new file mode 100644 index 0000000..8da7688 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/ipc.h @@ -0,0 +1,880 @@ +//########################################################################### +// +// FILE: ipc.h +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef IPC_H +#define IPC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ipc_api IPC +//! \brief This module is used for inter-processor communications. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "debug.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ipc.h" +#include "inc/hw_ints.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the APIs +// +//***************************************************************************** +//***************************************************************************** +// +// Driver configuration macros +// +//***************************************************************************** +#define IPC_MSGQ_SUPPORT 1U + +// +// Number of IPC messages in circular buffer (must be interval of 2) +// +#define IPC_BUFFER_SIZE 4U + +// +// Number of IPC interrupts using circular buffer (must be same number on both +// CPUs) +// +#define IPC_NUM_OF_INTERRUPTS 4U + +//***************************************************************************** +// +// Values that can be passed as parameter flags in all the IPC API functions. +// +//***************************************************************************** +#ifndef IPC_FLAGS_DEFINED +#define IPC_FLAGS_DEFINED +#define IPC_NO_FLAG 0x00000000U //!< NO FLAG +#define IPC_FLAG0 0x00000001U //!< IPC FLAG 0 +#define IPC_FLAG1 0x00000002U //!< IPC FLAG 1 +#define IPC_FLAG2 0x00000004U //!< IPC FLAG 2 +#define IPC_FLAG3 0x00000008U //!< IPC FLAG 3 +#define IPC_FLAG4 0x00000010U //!< IPC FLAG 4 +#define IPC_FLAG5 0x00000020U //!< IPC FLAG 5 +#define IPC_FLAG6 0x00000040U //!< IPC FLAG 6 +#define IPC_FLAG7 0x00000080U //!< IPC FLAG 7 +#define IPC_FLAG8 0x00000100U //!< IPC FLAG 8 +#define IPC_FLAG9 0x00000200U //!< IPC FLAG 9 +#define IPC_FLAG10 0x00000400U //!< IPC FLAG 10 +#define IPC_FLAG11 0x00000800U //!< IPC FLAG 11 +#define IPC_FLAG12 0x00001000U //!< IPC FLAG 12 +#define IPC_FLAG13 0x00002000U //!< IPC FLAG 13 +#define IPC_FLAG14 0x00004000U //!< IPC FLAG 14 +#define IPC_FLAG15 0x00008000U //!< IPC FLAG 15 +#define IPC_FLAG16 0x00010000U //!< IPC FLAG 16 +#define IPC_FLAG17 0x00020000U //!< IPC FLAG 17 +#define IPC_FLAG18 0x00040000U //!< IPC FLAG 18 +#define IPC_FLAG19 0x00080000U //!< IPC FLAG 19 +#define IPC_FLAG20 0x00100000U //!< IPC FLAG 20 +#define IPC_FLAG21 0x00200000U //!< IPC FLAG 21 +#define IPC_FLAG22 0x00400000U //!< IPC FLAG 22 +#define IPC_FLAG23 0x00800000U //!< IPC FLAG 23 +#define IPC_FLAG24 0x01000000U //!< IPC FLAG 24 +#define IPC_FLAG25 0x02000000U //!< IPC FLAG 25 +#define IPC_FLAG26 0x04000000U //!< IPC FLAG 26 +#define IPC_FLAG27 0x08000000U //!< IPC FLAG 27 +#define IPC_FLAG28 0x10000000U //!< IPC FLAG 28 +#define IPC_FLAG29 0x20000000U //!< IPC FLAG 29 +#define IPC_FLAG30 0x40000000U //!< IPC FLAG 30 +#define IPC_FLAG31 0x80000000U //!< IPC FLAG 31 +#define IPC_FLAG_ALL 0xFFFFFFFFU //!< All IPC flags +#endif + +//***************************************************************************** +// +// Values that can be passed as parameter ipcInt in +// IPC_registerInterrupt and IPC_unregisterInterrupt functions. +// Please refer to the datasheet for the actual number of interrupts available +// for each IPC instance +// +//***************************************************************************** +#define IPC_INT0 0x0U //!< IPC Interrupt 0 +#define IPC_INT1 0x1U //!< IPC Interrupt 1 +#define IPC_INT2 0x2U //!< IPC Interrupt 2 +#define IPC_INT3 0x3U //!< IPC Interrupt 3 +#define IPC_INT4 0x4U //!< IPC Interrupt 4 +#define IPC_INT5 0x5U //!< IPC Interrupt 5 +#define IPC_INT6 0x6U //!< IPC Interrupt 6 +#define IPC_INT7 0x7U //!< IPC Interrupt 7 + +//***************************************************************************** +// +// Values that can be passed as parameter addrCorrEnable in +// IPC_sendCommand, IPC_readCommand, IPC_sendMessageToQueue and +// IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_ADDR_CORRECTION_ENABLE true +#define IPC_ADDR_CORRECTION_DISABLE false + +//***************************************************************************** +// +// Values that can be passed as parameter block in +// IPC_sendMessageToQueue and IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_BLOCKING_CALL true +#define IPC_NONBLOCKING_CALL false + + + +//***************************************************************************** +// +// Internal macros used for message queue implementation +// +//***************************************************************************** +#define IPC_MAX_BUFFER_INDEX (IPC_BUFFER_SIZE - 1U) + +//***************************************************************************** +// +// Enums for the APIs +// +//***************************************************************************** + +//***************************************************************************** +// +//! Values that can be passed as parameter \e ipcType in all the driver +//! functions +// +//***************************************************************************** +typedef enum +{ + IPC_CPU1_L_CPU2_R, //!< CPU1 - Local core, CPU2 - Remote core + IPC_CPU2_L_CPU1_R, //!< CPU2 - Local core, CPU1 - Remote core + IPC_TOTAL_NUM +}IPC_Type_t; + +//***************************************************************************** +// +// Internal structs for register and messaage queue accesses +// +//***************************************************************************** +typedef struct +{ + uint32_t IPC_ACK; + uint32_t IPC_STS; + uint32_t IPC_SET; + uint32_t IPC_CLR; + uint32_t IPC_FLG; + uint32_t IPC_RSVDREG; + uint32_t IPC_COUNTERL; + uint32_t IPC_COUNTERH; +}IPC_Flag_Ctr_Reg_t; + +typedef struct +{ + uint32_t IPC_SENDCOM; + uint32_t IPC_SENDADDR; + uint32_t IPC_SENDDATA; + uint32_t IPC_REMOTEREPLY; +}IPC_SendCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_RECVCOM; + uint32_t IPC_RECVADDR; + uint32_t IPC_RECVDATA; + uint32_t IPC_LOCALREPLY; +}IPC_RecvCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_BOOTSTS; + uint32_t IPC_BOOTMODE; +}IPC_Boot_Pump_Reg_t; + +#if IPC_MSGQ_SUPPORT == 1U +typedef struct +{ + uint32_t command; + uint32_t address; + uint32_t dataw1; + uint32_t dataw2; +}IPC_Message_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t PutWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t GetReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_PutBuffer_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t GetWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t PutReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_GetBuffer_t; +#endif + +//***************************************************************************** +// +// Internal struct used to store the required information regarding an IPC +// instance +// +//***************************************************************************** +typedef struct +{ + volatile IPC_Flag_Ctr_Reg_t *IPC_Flag_Ctr_Reg; + volatile IPC_SendCmd_Reg_t *IPC_SendCmd_Reg; + volatile IPC_RecvCmd_Reg_t *IPC_RecvCmd_Reg; + volatile IPC_Boot_Pump_Reg_t *IPC_Boot_Pump_Reg; + uint32_t IPC_IntNum[8U]; + uint32_t IPC_MsgRam_LtoR; + uint32_t IPC_MsgRam_RtoL; + uint32_t IPC_Offset_Corr; +#if IPC_MSGQ_SUPPORT == 1U + IPC_PutBuffer_t *IPC_PutBuffer; + IPC_GetBuffer_t *IPC_GetBuffer; +#endif +}IPC_Instance_t; + +extern const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM]; + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// A structure that defines an IPC message queue. These +// fields are used by the IPC drivers, and normally it is not necessary for +// user software to directly read or write fields in the table. +// +//***************************************************************************** + +typedef struct +{ + IPC_Message_t * PutBuffer; + uint32_t PutFlag; + uint16_t * PutWriteIndex; + uint16_t * PutReadIndex; + IPC_Message_t * GetBuffer; + uint16_t * GetWriteIndex; + uint16_t * GetReadIndex; +} IPC_MessageQueue_t; +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! Local core sets Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being set +//! +//! This function will allow the Local core system to set the designated IPC +//! flags to send to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; +} + +//***************************************************************************** +// +//! Local core clears Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being cleared +//! +//! This function will allow the Local core system to clear the designated IPC +//! flags sent to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_clearFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_CLR = flags; +} + +//***************************************************************************** +// +//! Local core acknowledges Remote to Local IPC Flag. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being acknowledged. +//! +//! This function will allow the Local core system to acknowledge/clear the IPC +//! flag set by the Remote core system. The \e flags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_ackFlagRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_ACK = flags; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Local to Remote IPC flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Local to Remote +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) != 0U); +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Remote to Local IPC Flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Remote to Local +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U); +} + +//***************************************************************************** +// +//! Wait for the remote core to send a flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the Remote to Local IPC flag mask to wait for +//! +//! Allows the caller to wait for the Remote to Local flag to be send by +//! the remote core. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForFlag(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flag) == 0U) + { + } +} + +//***************************************************************************** +// +//! Wait for the IPC flag to be acknowledged +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask for which ack is pending +//! +//! Allows the caller to wait for the IPC flag to be acknowledged by the +//! remote core. The \e flagsparameter can be any of the IPC flag values: +//! \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForAck(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flag) != 0U) + { + } +} + +//***************************************************************************** +// +//! Synchronises the two cores +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask with which synchronisation is done +//! +//! Allows the local and remote cores to synchronise. Neither core will return +//! from this function call before the other core enters it. +//! +//! \note Must be called with same flag mask on both the cores +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_sync(IPC_Type_t ipcType, uint32_t flag) +{ + IPC_setFlagLtoR(ipcType, flag); + IPC_waitForFlag(ipcType, flag); + IPC_ackFlagRtoL(ipcType, flag); + IPC_waitForAck(ipcType, flag); +} + +//***************************************************************************** +// +//! Initialize IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +// +//! This function initializes IPC by clearing all the flags +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_init(IPC_Type_t ipcType) +{ + IPC_clearFlagLtoR(ipcType, IPC_FLAG_ALL); +} + +//***************************************************************************** +// +//! Sends a command to the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags to be set +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit command value +//! \param addr is the 32-bit address to be sent as part of command +//! \param data is the 32-bit data to be sent as part of command +//! +//! Allows the caller to send a command to the remote core. A command consists +//! of a unique command value, a 32-bit address and a 32-bit data. The function +//! also sends the designated flags to the remote core. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! The application shall use the function IPC_getResponse to read the response +//! sent by the remote core. +//! +//! \note The application is expected to wait until the the response is +//! received before sending another command. +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is sent properly and \b false if +//! the designated flags were busy and hence command was not sent. +// +//***************************************************************************** +extern bool +IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data); + +//***************************************************************************** +// +//! Reads a command sent by the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags sent by the remote core +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit pointer at which the command value is read to +//! \param addr is the 32-bit pointer at which address value is read to +//! \param data is the 32-bit pointer at which the data is read to +//! +//! Allows the caller to read a command sent by the remote core. A command +//! consists of a unique command value, a 32-bit address and a 32-bit data. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! \note The application is expected to acknowledge the flag and send a +//! response (if needed) after reading the command +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is read properly and \b false if +//! the designated flags were empty and hence command was not read. +// +//***************************************************************************** +extern bool +IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data); + +//***************************************************************************** +// +//! Sends the response to the command sent by remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param data is the 32-bit value of the response to be sent +//! +//! Allows the caller to send a response to the command previously sent by the +//! remote core +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_sendResponse(IPC_Type_t ipcType, uint32_t data) +{ + IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_LOCALREPLY = data; +} + +//***************************************************************************** +// +//! Reads the response from the remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the response sent by the remote core to the +//! command previously sent by the local core +//! +//! \return the 32-bit value of the response. +// +//***************************************************************************** +static inline uint32_t +IPC_getResponse(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_REMOTEREPLY); +} + +//***************************************************************************** +// +//! Sets the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param mode is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! \note This function shall be called by CPU1 only. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_setBootMode(IPC_Type_t ipcType, uint32_t mode) +{ + ASSERT(ipcType == IPC_CPU1_L_CPU2_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE = mode; +} + +//***************************************************************************** +// +//! Reads the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTMODE register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootMode(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE); +} + +//***************************************************************************** +// +//! Sets the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param status is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTSTS register. +//! +//! \note This function shall be called by CPU2 and CM only +//! +//! \note This function shall be called by CPU2 only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setBootStatus(IPC_Type_t ipcType, uint32_t status) +{ + ASSERT(ipcType == IPC_CPU2_L_CPU1_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS = status; +} + +//***************************************************************************** +// +//! Reads the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTSTS register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootStatus(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS); +} + +//***************************************************************************** +// +//! Reads the timestamp counter value. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the IPC timestamp counter value. +//! +//! \return 64-bit counter value. +// +//***************************************************************************** +static inline uint64_t +IPC_getCounter(IPC_Type_t ipcType) +{ + // + // Get the Counter High and Low values. Read to the Counter low register + // saves the value of Counter High register. + // + uint32_t ctrL = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERL; + uint32_t ctrH = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERH; + + // + // Return the 64-bit value of the counter + // + return(((uint64_t)ctrH << 32) | ((uint64_t)ctrL)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being registered +//! \param pfnHandler is the pointer to ISR function +//! +//! This function registers the handler to be called when an IPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! Unregisters an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being unregistered +//! +//! This function clears the handler to be called when an IPC interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt); + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +//! Initializes the IPC message queue +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param ipcInt_L specifies the interrupt number on the local core used by +//! the message queue . +//! \param ipcInt_R specifies the interrupt number on the remote core used by +//! the message queue. +//! +//! This function initializes the IPC message queue with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e ipcInt_L and \e ipcInt_R parameters can be one of the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e IPC_MessageQueue_t +//! instance, that particular interrupt should not be tied to a second +//! \e IPC_MessageQueue_t instance. +//! +//! \note For a particular ipcInt_L - ipcInt_R pair, there must be an instance +//! of IPC_MessageQueue_t defined and initialized on both the locakl and remote +//! systems. +//! +//! \return None. +// +//***************************************************************************** +extern void +IPC_initMessageQueue(IPC_Type_t ipcType, volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R); + +//***************************************************************************** +// +//! Sends a message into the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to be +//! sent to message queue. +//! \param block specifies whether to allow function to block until the buffer +//! has a free slot +//! +//! This function checks if there is a free slot in the message queue. If so, it +//! puts the message pointed to by \e msg into the free and sets the +//! appropriate IPC interrupt flag +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is full. \b true if the message is +//! successfully sent. +// +//***************************************************************************** +extern bool +IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); + +//***************************************************************************** +// +//! Reads a message from the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to which +//! the message needs to be read +//! \param block specifies whether to allow function to block until a message +//! is available in the message queue +//! +//! This function checks if there is a message in the message queue. If so, it +//! reads the message and writes to the address pointed to by \e msg into. +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is empty. \b true if the message successfully +//! read. +// +//***************************************************************************** +extern bool +IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); +#endif +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // IPC_H diff --git a/gpio_bitfield_cpu1/device/driverlib/mcbsp.c b/gpio_bitfield_cpu1/device/driverlib/mcbsp.c new file mode 100644 index 0000000..4b23940 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/mcbsp.c @@ -0,0 +1,1621 @@ +//########################################################################### +// +// FILE: mcbsp.c +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "mcbsp.h" + +//***************************************************************************** +// +// McBSP_transmit16BitdataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit16BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_setRxDataSize +// +//***************************************************************************** +void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word , write to RWDLEN1 and words per frame , write to + // RFRLEN1. + // + HWREGH(base + MCBSP_O_RCR1) = + ((HWREGH(base + MCBSP_O_RCR1) & ~MCBSP_RCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR1_RFRLEN1_S))); + } + else + { + // + // Set bits per word , write to RWDLEN2 and words per frame, write to + // RFRLEN2. + // + HWREGH(base + MCBSP_O_RCR2) = + ((HWREGH(base + MCBSP_O_RCR2) & ~MCBSP_RCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR2_RFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_setTxDataSize +// +//***************************************************************************** +void +McBSP_setTxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word XWDLEN1 and words per frame XFRLEN1. + // + HWREGH(base + MCBSP_O_XCR1) = + ((HWREGH(base + MCBSP_O_XCR1) & ~MCBSP_XCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR1_XFRLEN1_S))); + } + else + { + // + // Set bits per word XWDLEN2 and words per frame XFRLEN2. + // + HWREGH(base + MCBSP_O_XCR2) = + ((HWREGH(base + MCBSP_O_XCR2) & ~MCBSP_XCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR2_XFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_disableRxChannel +// +//***************************************************************************** +void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableRxChannel +// +//***************************************************************************** +void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_disableTxChannel +// +//***************************************************************************** +void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableTxChannel +// +//***************************************************************************** +void McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine wheter it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_configureTxClock +// +//***************************************************************************** +void +McBSP_configureTxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select TX clock source as SRG or External. + // + McBSP_setTxClockSource(base, + (McBSP_TxClockSource)ptrClockParams->clockSourceTx); + + // + // Check if using SRG to drive Transmitter clock. + // + if((McBSP_TxClockSource)ptrClockParams->clockSourceTx == + MCBSP_INTERNAL_TX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setTxSRGClockSource(base, + (McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource); + + // + // Check if SRG is clocked from MCLKR pin. GSYNC feature can be enabled + // in this case as SRG input clock source is MCLKR pin. + // + if((McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource == + MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); + + // + // Check if SRG is to be synced with FSR that is GSYNC is to be + // enabled or not. + // + if(ptrClockParams->clockSRGSyncFlag) + { + McBSP_enableSRGSyncFSR(base); + } + else + { + McBSP_disableSRGSyncFSR(base); + } + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKX. + // Output polarity if using SRG as clock source. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); +} + +//***************************************************************************** +// +// McBSP_configureRxClock +// +//***************************************************************************** +void +McBSP_configureRxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select RX clock source as SRG or External. + // + McBSP_setRxClockSource(base, + (McBSP_RxClockSource)ptrClockParams->clockSourceRx); + + // + // Check if using SRG to drive Receiver clock. + // + if((McBSP_RxClockSource)ptrClockParams->clockSourceRx == + MCBSP_INTERNAL_RX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setRxSRGClockSource(base, + (McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource); + + // + // Check if SRG is clocked from MCLKX pin. GSYNC cannot be enabled in + // this case as GSYNC feature can be used only when SRG clock source is + // MCLKR pin. + // + if((McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource == + MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKR. + // Output polarity if using SRG as clock source. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); +} + +//***************************************************************************** +// +// McBSP_configureTxFrameSync +// +//***************************************************************************** +void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setTxFrameSyncSource(base, + (McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx); + + // + // Check if using internal frame-sync source. + // + if((McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx == + MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Select the internal frame-sync trigger source. + // + McBSP_setTxInternalFrameSyncSource(base, + (McBSP_TxInternalFrameSyncSource)ptrFsyncParams->syncIntSource); + + // + // Check if using SRG FSG to trigger frame-sync pulse and GSYNC feature + // is disabled that is FSG is not derived from external MCLKR pin. + // + if((ptrFsyncParams->syncIntSource == + MCBSP_TX_INTERNAL_FRAME_SYNC_SRG) && + (ptrFsyncParams->syncSRGSyncFSRFlag == false)) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setTxFrameSyncPolarity(base, + (McBSP_TxFrameSyncPolarity)ptrFsyncParams->syncFSXPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableTxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureRxFrameSync +// +//***************************************************************************** +void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setRxFrameSyncSource(base, + (McBSP_RxFrameSyncSource)ptrFsyncParams->syncSourceRx); + + // + // If using internal frame-sync source. + // + if(ptrFsyncParams->syncSourceRx == MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Check if GSYNC feature is disabled that is FSG is not derived + // from external MCLKR pin. + // + if(ptrFsyncParams->syncSRGSyncFSRFlag == false) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setRxFrameSyncPolarity(base, + (McBSP_RxFrameSyncPolarity)ptrFsyncParams->syncFSRPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableRxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureTxDataFormat +// +//***************************************************************************** +void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - a TX must at least has a single phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseTx(base); + + // + // Check if second phase is being used. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseTx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the Tx companding mode. + // + McBSP_setTxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set Tx data delay in bits. + // + McBSP_setTxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set DX pin delay. + // + if(ptrDataParams->pinDelayEnableFlag) + { + McBSP_enableDxPinDelay(base); + } + else + { + McBSP_disableDxPinDelay(base); + } + + // + // Set the transmitter interrupt source. + // + McBSP_setTxInterruptSource(base, + (McBSP_TxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureRxDataFormat +// +//***************************************************************************** +void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP mode. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - an RX must at least have a single phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseRx(base); + + // + // Check if second phase is to be enabled. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseRx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the receiver companding mode. + // + McBSP_setRxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set receiver data delay in bits. + // + McBSP_setRxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set receiver sign-extension and justification mode. + // + McBSP_setRxSignExtension(base, + (McBSP_RxSignExtensionMode)ptrDataParams->signExtMode); + + // + // Set the receiver interrupt source. + // + McBSP_setRxInterruptSource(base, + (McBSP_RxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureTxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorTx; + + errorTx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setTxChannelMode(base, + (McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx); + + // + // Configuration for multichannel selections that is for + // MCBSP_TX_CHANNEL_SELECTION_ENABLED, + // MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or + // MCBSP_SYMMERTIC_RX_TX_SELECTION. + // + if(((McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx) != + MCBSP_ALL_TX_CHANNELS_ENABLED) + { + // + // Select 2 partition or 8 partition. + // + McBSP_setTxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionTx); + + // + // Disable dual phase transmission mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionTx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if(((uint16_t)ptrMchnParams->channelCountTx) > 32U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*(ptrMchnParams->ptrChannelsListTx) + + index)); + } + else + { + errorTx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition B. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + else + { + errorTx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if((uint16_t)ptrMchnParams->channelCountTx > 128U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Enable the Tx channels. + // + McBSP_enableTxChannel(base, MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + } + } + return(errorTx); +} + +//***************************************************************************** +// +// McBSP_configureRxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorRx; + + errorRx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setRxChannelMode(base, + (McBSP_RxChannelMode)ptrMchnParams->multichannelModeRx); + + // + // Select 2 partition or 8 partition. + // + McBSP_setRxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionRx); + + // + // Configuration for multichannel selections that is for + // MCBSP_RX_CHANNEL_SELECTION_ENABLED. + // + if((ptrMchnParams->multichannelModeRx) == + MCBSP_RX_CHANNEL_SELECTION_ENABLED) + { + // + // Disable dual phase reception mode. + // + McBSP_disableTwoPhaseRx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionRx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if((uint16_t)ptrMchnParams->channelCountRx > 32U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (*((ptrMchnParams->ptrChannelsListRx) + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the Rx channel belonging to the block + // assigned to partition B. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if(ptrMchnParams->channelCountRx > 128U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Enable the Rx channels. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + index))); + } + } + } + return(errorRx); +} + +//***************************************************************************** +// +// McBSP_configureSPIMasterMode +// +//***************************************************************************** +void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams *ptrSPIMasterMode) +{ + // + // Configure clock stop mode. + // + if(((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPIMasterMode->clockStopMode); + + // + // Set loop back mode. + // + if(ptrSPIMasterMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as master. Use SRG as clock source for driving + // master clock. MCLKX pin will be the master clock out pin. + // + McBSP_setTxClockSource(base, MCBSP_INTERNAL_TX_CLOCK_SOURCE); + + // + // Set internal clock (LSPCLK) as SRG clock source. + // + McBSP_setTxSRGClockSource(base, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK); + + // + // Set SRG clock divider for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrSPIMasterMode->clockSRGDivider); + + // + // Set the output master clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPIMasterMode->spiMode); + + // + // Set FSX as an output driven by SRG. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE); + + // + // FSX is triggered when data is written to DXR registers. + // + McBSP_setTxInternalFrameSyncSource(base, + MCBSP_TX_INTERNAL_FRAME_SYNC_DATA); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + + // + // Set one bit data delay for transmission & reception to set correct + // setup time on FSX signal. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + } +} + +//***************************************************************************** +// +// McBSP_configureSPISlaveMode +// +//***************************************************************************** +void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams *ptrSPISlaveMode) +{ + + // + // Configure clock stop mode. + // + if(((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPISlaveMode->clockStopMode); + // + // Set loop back mode. + // + if(ptrSPISlaveMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as Slave. MCLKX pin acts as input slave + // clock and is driven externally by SPI master. + // + McBSP_setTxClockSource(base, MCBSP_EXTERNAL_TX_CLOCK_SOURCE); + + // + // Set the input slave clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPISlaveMode->spiMode); + + // + // Set internal clock (LSPCLK) as SRG clock source. SRG is used to + // synchronize McBSP logic with externally generated master clock. + // + McBSP_setRxSRGClockSource(base, MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK); + + // + // Assign a clock divider value of 1 for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, 1U); + + // + // Set FSX as an input which is driven by slave-enable signal + // from SPI master. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception.. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + + // + // Set zero bit data delay for transmission & reception. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + } +} diff --git a/gpio_bitfield_cpu1/device/driverlib/mcbsp.h b/gpio_bitfield_cpu1/device/driverlib/mcbsp.h new file mode 100644 index 0000000..949987d --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/mcbsp.h @@ -0,0 +1,3340 @@ +//########################################################################### +// +// FILE: mcbsp.h +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MCBSP_H +#define MCBSP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup mcbsp_api McBSP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "inc/hw_mcbsp.h" +#include "inc/hw_memmap.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Define to specify mask for setting the word and frame length in +// McBSP_setTxDataSize() anf McBSP_setRxDataSize(). +// +//***************************************************************************** +#define MCBSP_XCR1_M (MCBSP_XCR1_XWDLEN1_M | \ + MCBSP_XCR1_XFRLEN1_M) +#define MCBSP_RCR1_M (MCBSP_RCR1_RWDLEN1_M | \ + MCBSP_RCR1_RFRLEN1_M) +#define MCBSP_XCR2_M (MCBSP_XCR2_XWDLEN2_M | \ + MCBSP_XCR2_XFRLEN2_M) +#define MCBSP_RCR2_M (MCBSP_RCR2_RWDLEN2_M | \ + MCBSP_RCR2_RFRLEN2_M) + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getRxErrorStatus() when +// there is an error in Rx. +// +//***************************************************************************** +#define MCBSP_RX_NO_ERROR 0x0U //!< No error. +#define MCBSP_RX_BUFFER_ERROR 0x4U //!< Buffer Full. +#define MCBSP_RX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_RX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getTxErrorStatus() when +// there is an error in Tx. +// +//***************************************************************************** +#define MCBSP_TX_NO_ERROR 0x0U //!< No error. +#define MCBSP_TX_BUFFER_ERROR 0x4U //!< Buffer overrun. +#define MCBSP_TX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_TX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Values that can be returned by McBSP_configureTxMultichannel() and +// McBSP_configureRxMultichannel(). +// +//***************************************************************************** +#define MCBSP_ERROR_EXCEEDED_CHANNELS 0x1U //!< Exceeded number of channels. +#define MCBSP_ERROR_2_PARTITION_A 0x2U //!< Error in 2 partition A setup. +#define MCBSP_ERROR_2_PARTITION_B 0x4U //!< Error in 2 partition B setup. +#define MCBSP_ERROR_INVALID_MODE 0x8U //!< Invalid mode. + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxSignExtension() as the \e +//! mode parameters. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RIGHT_JUSTIFY_FILL_ZERO = 0x0000U, //!< Right justify and + //!< zero fill MSB. + MCBSP_RIGHT_JUSTIFY_FILL_SIGN = 0x2000U, //!< Right justified sign + //!< extended into MSBs. + MCBSP_LEFT_JUSTIFY_FILL_ZER0 = 0x4000U //!< Left justifies LBS + //!< filled with zero. +}McBSP_RxSignExtensionMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setClockStopMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_CLOCK_MCBSP_MODE = 0x0000U, //!< Disables clock stop mode. + MCBSP_CLOCK_SPI_MODE_NO_DELAY = 0x1000U, //!< Enables clock stop mode. + MCBSP_CLOCK_SPI_MODE_DELAY = 0x1800U //!< Enables clock stop mode + //!< with half cycle delay. +}McBSP_ClockStopMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxInterruptSource() as the +//! \e interruptSource parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RX_ISR_SOURCE_SERIAL_WORD = 0x0000U, //!> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Configures transmitter input clock source for sample generator. +//! +//! \param base is the base address of the McBSP module. +//! \param srgClockSource is clock source for the sample generator. +//! +//! This functions sets the clock source for the sample rate generator. +//! Valid values for \e clockSource are +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK for LSPCLK. +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN for external clock at MCLKR pin. +//! MCLKX pin will be an output driven by sample rate generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxSRGClockSource(uint32_t base, + const McBSP_SRGTxClockSource srgClockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKSM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_CLKSM) | + ((uint16_t)((uint16_t)srgClockSource & 0x1U) << 13U)); + // + // Set or clear SCLKME bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_SCLKME) | + (uint16_t)(((uint16_t)srgClockSource >> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Sets the mode for transmitter internal frame sync signal. +//! +//! \param base is the base address of the McBSP module. +//! \param syncMode is the frame sync mode. +//! +//! This function sets the frame sync signal generation mode. The signal can be +//! generated based on clock divider as set in McBSP_setFrameSyncPulsePeriod() +//! function or when data is transferred from DXR registers to XSR registers. +//! Valid input for syncMode are: +//! +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_DATA - frame sync signal is +//! generated when data is transferred from +//! DXR registers to XSR registers. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SRG - frame sync signal is +//! generated based on the clock counter +//! value as defined in +//! McBSP_setFrameSyncPulsePeriod() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxInternalFrameSyncSource(uint32_t base, + const McBSP_TxInternalFrameSyncSource syncMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSGM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_FSGM) | (uint16_t)syncMode); +} + +//***************************************************************************** +// +//! Set Multichannel receiver partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel receiver. Valid values +//! for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or Clear RMCME bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to receiver in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! receiver partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Check the block value if it is 0,2,4,6 or 1,3,5,7. + // + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to RPABLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPABLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to RPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPBBLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active receiver block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active receiver block involved in McBSP +//! reception. +//! +//! \return Active block in McBSP reception. Returned values range from 0 to 7 +//! representing the respective active block number . +// +//***************************************************************************** +static inline uint16_t +McBSP_getRxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return RCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR1) & MCBSP_MCR1_RCBLK_M) >> + MCBSP_MCR1_RCBLK_S); +} + +//***************************************************************************** +// +//! Configure channel selection mode for receiver. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_RX_CHANNELS_ENABLED - enables all channels. +//! - \b MCBSP_RX_CHANNEL_SELECTION_ENABLED - lets the user enable desired +//! channels by using McBSP_enableRxChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxChannelMode(uint32_t base, const McBSP_RxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear RMCM bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCM) | (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Set Multichannel transmitter partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel transmitter. Valid +//! values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear XMCME bit. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to transmitter in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! transmitter partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to XPABLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPABLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to XPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPBBLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active transmitter block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active transmitter block involved in +//! McBSP transmission. +//! +//! \return Active block in McBSP transmission. Returned values range from +//! 0 to 7 representing the respective active block number. +// +//***************************************************************************** +static inline uint16_t +McBSP_getTxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return XCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR2) & MCBSP_MCR2_XCBLK_M) >> + MCBSP_MCR2_XCBLK_S); + +} + +//***************************************************************************** +// +//! Configure channel selection mode for transmitter. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_TX_CHANNELS_ENABLED - enables and unmasks all channels +//! - \b MCBSP_TX_CHANNEL_SELECTION_ENABLED - lets the user enable and unmask +//! desired channels by using McBSP_enableTxChannel() +//! - \b MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION - All channels enables but +//! until enabled by McBSP_enableTxChannel() +//! - \b MCBSP_SYMMERTIC_RX_TX_SELECTION - Symmetric transmission and +//! reception. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxChannelMode(uint32_t base, const McBSP_TxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set values to the XMCM bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCM_M) | + (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Select the transmitter frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the transmitter frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSX. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! internally. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncSource(uint32_t base, + const McBSP_TxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Set or Clear the FSXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Select receiver frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the receiver frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSR. +//! - \b MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! by SRG. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncSource(uint32_t base, + const McBSP_RxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Configures the Transmit clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the transmission pin. +//! +//! This function configures the clock source for the transmitter. Valid input +//! for rxClockSource are: +//! - \b MCBSP_INTERNAL_TX_CLOCK_SOURCE - internal clock source. SRG is the +//! source. +//! - \b MCBSP_EXTERNAL_TX_CLOCK_SOURCE - external clock source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockSource(uint32_t base, const McBSP_TxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXM ) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Configures the Receive clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the reception pin. +//! +//! This function configures the clock source for the receiver. Valid input +//! for base are: +//! - \b MCBSP_INTERNAL_RX_CLOCK_SOURCE - internal clock source. Sample Rate +//! Generator will be used. +//! - \b MCBSP_EXTERNAL_RX_CLOCK_SOURCE - external clock will drive the data. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockSource(uint32_t base, const McBSP_RxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRM) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Sets transmitter frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSX pin. Use \b MCBSP_TX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_TX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncPolarity(uint32_t base, + const McBSP_TxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets receiver frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSR pin. Use \b MCBSP_RX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_RX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncPolarity(uint32_t base, + const McBSP_RxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets transmitter clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the transmitter +//! clock on MCLKX pin. +//! Valid values for clockPolarity are: +//! - \b MCBSP_TX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_TX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockPolarity(uint32_t base, + const McBSP_TxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKXP bit first , then set or clear CLKXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +//! Sets receiver clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the receiver +//! clock on MCLKR pin. If external clock is used, the polarity will affect +//! CLKG signal. +//! Valid values for clockPolarity are: +//! - \b MCBSP_RX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_RX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockPolarity(uint32_t base, + const McBSP_RxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKRP bit first , then set or clear CLKRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data value in data receive register. +//! +//! \return received data. +// +//***************************************************************************** +static inline +uint16_t McBSP_read16bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DRR1 register. + // + return(HWREGH(base + MCBSP_O_DRR1)); +} + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data values in data receive registers. +//! +//! \return received data. +// +//***************************************************************************** +static inline uint32_t +McBSP_read32bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DDR1 register and return DDR2:DDR1. + // + return((((uint32_t)HWREGH(base + MCBSP_O_DRR2) << 16U) | + HWREGH(base + MCBSP_O_DRR1))); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 8,12 or 16 bit data to data transmit register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write16bitData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data; +} + +//***************************************************************************** +// +//! Write 20, 24 or 32 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 20, 24 or 32 bit data to data transmit registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write32bitData(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR2 register first. + // + HWREGH(base + MCBSP_O_DXR2) = data >> 16U; + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data & 0xFFFFU; +} + +//***************************************************************************** +// +//! Return left justified for data for U Law or A Law companding. +//! +//! \param data is the 14 bit word. +//! \param compandingType specifies the type comapnding desired. +//! +//! This functions returns U law or A law adjusted word. +//! +//! \return U law or A law left justified word. +// +//***************************************************************************** +static inline uint16_t +McBSP_getLeftJustifyData(uint16_t data, + const McBSP_CompandingType compandingType) +{ + return(data << (uint16_t)compandingType); +} + + +//***************************************************************************** +// +//! Enable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_RINT; +} + +//***************************************************************************** +// +//! Disable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_RINT); +} + +//***************************************************************************** +// +//! Enable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_XINT; +} + +//***************************************************************************** +// +//! Disable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_XINT); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. +//! +//! \return None. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written to +//! the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! the transmitter buffer is empty the data will be written to the data +//! registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written +//! to the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData); + + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Reception. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing the first or second frame phase +//! respectively. Valid value for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Transmission. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing single or dual phase respectively. +//! Valid values for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setTxDataSize(uint32_t base, + const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Disables a channel in an eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function disables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function enables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Disables a channel in an eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function disables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function enables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Configures transmitter clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the transmitter clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFSR - true to sync with signal on FSR pin, +//! false to ignore signal on FSR pin. +//! the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_TX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_TX_CLOCK_SOURCE +//! - \b clockTxSRGSource - MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN +//! - \b clockMCLKXPolarity - Output polarity on MCLKX pin. +//! - MCBSP_TX_POLARITY_RISING_EDGE +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockMCLKRPolarity - Input polarity on MCLKR pin (if SRG is +//! sourced from MCLKR pin). +//! - MCBSP_RX_POLARITY_FALLING_EDGE +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures receiver clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the receiver clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_RX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_RX_CLOCK_SOURCE +//! - \b clockRxSRGSource - MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN +//! - \b clockMCLKRPolarity- output polarity on MCLKR pin. +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! - \b clockMCLKXPolarity- Input polarity on MCLKX pin (if SRG is sourced +//! from MCLKX pin). +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures transmitter frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSPTxFsyncParams. +//! This function sets up the transmitter frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin.This value has to +//! be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. false +//! to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceTx - MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncIntSource - MCBSP_TX_INTERNAL_FRAME_SYNC_DATA or +//! MCBSP_TX_INTERNAL_FRAME_SYNC_SRG +//! - \b syncFSXPolarity - MCBSP_TX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_TX_FRAME_SYNC_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures receiver frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSP_RxFsyncParams. +//! This function sets up the receiver frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, +//! false to ignore the pulse on FSR pin. +//! This value has to be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. +//! false to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceRx - MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncFSRPolarity - MCBSP_RX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_RX_FRAME_SYNC_POLARITY_HIGH +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures transmitter data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing \e data format +//! parameters McBSPTxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSPTxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for no loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b pinDelayEnableFlag - true to enable DX pin delay. +//! false to disable DX pin delay. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b interruptMode - MCBSP_TX_ISR_SOURCE_TX_READY, +//! MCBSP_TX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_TX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_TX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures receiver data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing data format +//! parameters McBSP_RxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSP_RxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for non loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b signExtMode - MCBSP_RIGHT_JUSTIFY_FILL_ZERO, +//! MCBSP_RIGHT_JUSTIFY_FILL_SIGN or +//! MCBSP_LEFT_JUSTIFY_FILL_ZER0 +//! - \b interruptMode - MCBSP_RX_ISR_SOURCE_SERIAL_WORD, +//! MCBSP_RX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_RX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_RX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures transmitter multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_TxMultichannelParams. +//! +//! This function sets up the transmitter multichannel mode. The following are +//! valid values and ranges for the parameters of the +//! McBSP_TxMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_TX_CHANNELS_ENABLED, +//! MCBSP_TX_CHANNEL_SELECTION_ENABLED, +//! MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or +//! MCBSP_SYMMERTIC_RX_TX_SELECTION +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even and +//! odd channels. For example you can have channels [48 -63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63] and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures receiver multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_RxMultiChannelParams. +//! +//! This function sets up the receiver multichannel mode. The following are +//! valid values and ranges for the parameters of the McBSPMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_RX_CHANNELS_ENABLED, +//! MCBSP_RX_CHANNEL_SELECTION_ENABLED, +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even +//! and odd channels. For example you can have channels [48 - 63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63]and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures McBSP in SPI master mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPIMasterMode is a pointer to a structure containing SPI +//! parameters McBSP_SPIMasterModeParams. +//! This function sets up the McBSP module in SPI master mode.The following are +//! valid values and ranges for the parameters of the +//! McBSP_SPIMasterModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity can take values: +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockSRGDivider - Maximum valid value is 255. +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams * ptrSPIMasterMode); + +//***************************************************************************** +// +//! Configures McBSP in SPI slave mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPISlaveMode is a pointer to a structure containing SPI +//! parameters McBSP_SPISlaveModeParams. +//! This function sets up the McBSP module in SPI slave mode.The following are +//! valid values and ranges for the parameters of the McBSP_SPISlaveModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity and can take +//! values: +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams * ptrSPISlaveMode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MCBSP_H diff --git a/gpio_bitfield_cpu1/device/driverlib/memcfg.c b/gpio_bitfield_cpu1/device/driverlib/memcfg.c new file mode 100644 index 0000000..c9a4dc7 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/memcfg.c @@ -0,0 +1,701 @@ +//########################################################################### +// +// FILE: memcfg.c +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "memcfg.h" + + +//***************************************************************************** +// +// MemCfg_lockConfig +// +//***************************************************************************** +void +MemCfg_lockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that blocks writes to the sections' configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Lock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_unlockConfig +// +//***************************************************************************** +void +MemCfg_unlockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Clear the bit that blocks writes to the sections' configuration + // registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Unlock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL)); + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_commitConfig +// +//***************************************************************************** +void +MemCfg_commitConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that permanently blocks writes to the sections' + // configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Commit configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setProtection +// +//***************************************************************************** +void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + uint32_t regOffset; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 8 bits in the corresponding ACCPROT register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 8U; + } + + // + // Calculate register offset. Also, make sure the shift value is no greater + // than 31. + // + regOffset = (shiftVal & ~(0x1FU)) >> 4U; + shiftVal &= 0x0001FU; + maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal; + regVal = protectMode << shiftVal; + + // + // Write the access protection mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal; + break; + + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setLSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel) +{ + uint32_t shiftVal; + uint32_t temp; + + // + // Check the arguments. + // + ASSERT((ramSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Calculate how far the controller select value needs to be shifted. Each + // section number is represented by a bit in the lower word of ramSection + // and 2 bits in the corresponding MSEL register. + // + shiftVal = 0U; + temp = MEMCFG_SECT_NUM_MASK & ramSection; + + while(temp != 1U) + { + temp = temp >> 1U; + shiftVal += 2U; + } + + // + // Write the controller select setting into the appropriate field + // + EALLOW; + + HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) = + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) & + ~((uint32_t)MEMCFG_LSXMSEL_MSEL_LS0_M << shiftVal)) | + ((uint32_t)controllerSel << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setGSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel) +{ + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS); + + // + // We only need the section number bits for this function. + // + sectionNum = ramSections & MEMCFG_SECT_NUM_MASK; + + // + // Write the controller select setting into the appropriate field. + // + EALLOW; + if(controllerSel == MEMCFG_GSRAMCONTROLLER_CPU1) + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &= ~sectionNum; + } + else + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) |= sectionNum; + } + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setTestMode +// +//***************************************************************************** +void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 2 bits in the corresponding TEST register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 2U; + } + + maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal; + regVal = (uint32_t)testMode << shiftVal; + + // + // Write the test mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal; + break; + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_initSections +// +//***************************************************************************** +void +MemCfg_initSections(uint32_t ramSections) +{ + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Set the bit in the various initialization registers that starts + // initialization. + // + EALLOW; + + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Initialize all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_MSGX_ALL; + break; + + default: + // + // Do nothing. Invalid ramSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_getInitStatus +// +//***************************************************************************** +bool +MemCfg_getInitStatus(uint32_t ramSections) +{ + uint32_t status; + + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Read registers containing the initialization complete status. + // + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE); + break; + + case MEMCFG_SECT_TYPE_LS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_GS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MSG: + status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Return the overall status. + // + if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) == + (MEMCFG_SECT_DX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) == + (MEMCFG_SECT_LSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) == + (MEMCFG_SECT_GSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) == + (MEMCFG_SECT_MSGX_ALL & MEMCFG_SECT_NUM_MASK))) + { + status = MEMCFG_SECT_NUM_MASK; + } + else + { + status = 0U; + } + break; + + default: + // + // Invalid ramSections. Make sure you aren't OR-ing values for two + // different types of RAM. + // + status = 0U; + break; + } + + return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK)); +} + +//***************************************************************************** +// +// MemCfg_getViolationAddress +// +//***************************************************************************** +uint32_t +MemCfg_getViolationAddress(uint32_t intFlag) +{ + uint32_t address; + uint32_t stsNumber; + + // + // Calculate the the address of the desired violation address register. + // + if((intFlag & MEMCFG_MVIOL_MASK) != 0U) + { + stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT; + address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR; + } + else + { + stsNumber = intFlag; + address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR; + } + + while(stsNumber > 1U) + { + stsNumber = stsNumber >> 1U; + address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR); + } + + // + // Read and return the access violation address at the calculated location. + // + return(HWREG(address)); +} + +//***************************************************************************** +// +// MemCfg_getCorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag) +{ + // + // Check the arguments. + // + if(stsFlag != MEMCFG_CERR_CPUREAD) + { + // + // Currently, the only correctable error address that can be read + // from a register is one for a CPU read error (MEMCFG_CERR_CPUREAD). + // For the sake of keeping this function portable to possible future + // devices with other error types, it still takes a stsFlag parameter. + // + ASSERT((bool)false); + } + + // + // Read and return the error address. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CCPUREADDR)); +} + +//***************************************************************************** +// +// MemCfg_getUncorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag) +{ + uint32_t address; + uint32_t temp; + + // + // Calculate the the address of the desired error address register. + // + address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR; + + temp = stsFlag; + + while(temp > 1U) + { + temp = temp >> 1U; + address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR); + } + + // + // Read and return the error address at the calculated location. + // + return(HWREG(address)); +} + + diff --git a/gpio_bitfield_cpu1/device/driverlib/memcfg.h b/gpio_bitfield_cpu1/device/driverlib/memcfg.h new file mode 100644 index 0000000..8a9b6fc --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/memcfg.h @@ -0,0 +1,1266 @@ +//########################################################################### +// +// FILE: memcfg.h +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MEMCFG_H +#define MEMCFG_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup memcfg_api MemCfg +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +// +// Masks to decode memory section defines. +// +#define MEMCFG_SECT_TYPE_MASK 0xFF000000U +#define MEMCFG_SECT_TYPE_D 0x00000000U +#define MEMCFG_SECT_TYPE_LS 0x01000000U +#define MEMCFG_SECT_TYPE_GS 0x02000000U +#define MEMCFG_SECT_TYPE_MSG 0x03000000U +#define MEMCFG_SECT_NUM_MASK 0x00FFFFFFU +#define MEMCFG_XACCPROTX_M ((uint32_t)MEMCFG_GSXACCPROT0_FETCHPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_DMAWRPROT_GS0) +#define MEMCFG_XTEST_M MEMCFG_DXTEST_TEST_M0_M + +// +// Used for access violation functions. +// +#define MEMCFG_NMVIOL_MASK 0x0000FFFFU +#define MEMCFG_MVIOL_MASK 0x000F0000U +#define MEMCFG_MVIOL_SHIFT 16U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(), +// MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(), +// MemCfg_setCLAMemType(), MemCfg_setLSRAMControllerSel(), +// MemCfg_getInitStatus() as the memSection(s) or ramSection(s) parameter. +// +//***************************************************************************** +// +// DxRAM - Dedicated RAM config +// +#define MEMCFG_SECT_M0 0x00000001U //!< M0 RAM +#define MEMCFG_SECT_M1 0x00000002U //!< M1 RAM +#define MEMCFG_SECT_D0 0x00000004U //!< D0 RAM +#define MEMCFG_SECT_D1 0x00000008U //!< D1 RAM +#define MEMCFG_SECT_DX_ALL 0x0000000FU //!< All M and D RAM + +// +// LSxRAM - Local shared RAM config +// +#define MEMCFG_SECT_LS0 0x01000001U //!< LS0 RAM +#define MEMCFG_SECT_LS1 0x01000002U //!< LS1 RAM +#define MEMCFG_SECT_LS2 0x01000004U //!< LS2 RAM +#define MEMCFG_SECT_LS3 0x01000008U //!< LS3 RAM +#define MEMCFG_SECT_LS4 0x01000010U //!< LS4 RAM +#define MEMCFG_SECT_LS5 0x01000020U //!< LS5 RAM +#define MEMCFG_SECT_LSX_ALL 0x0100003FU //!< All LS RAM + +// +// GSxRAM - Global shared RAM config +// +#define MEMCFG_SECT_GS0 0x02000001U //!< GS0 RAM +#define MEMCFG_SECT_GS1 0x02000002U //!< GS1 RAM +#define MEMCFG_SECT_GS2 0x02000004U //!< GS2 RAM +#define MEMCFG_SECT_GS3 0x02000008U //!< GS3 RAM +#define MEMCFG_SECT_GS4 0x02000010U //!< GS4 RAM +#define MEMCFG_SECT_GS5 0x02000020U //!< GS5 RAM +#define MEMCFG_SECT_GS6 0x02000040U //!< GS6 RAM +#define MEMCFG_SECT_GS7 0x02000080U //!< GS7 RAM +#define MEMCFG_SECT_GS8 0x02000100U //!< GS8 RAM +#define MEMCFG_SECT_GS9 0x02000200U //!< GS9 RAM +#define MEMCFG_SECT_GS10 0x02000400U //!< GS10 RAM +#define MEMCFG_SECT_GS11 0x02000800U //!< GS11 RAM +#define MEMCFG_SECT_GS12 0x02001000U //!< GS12 RAM +#define MEMCFG_SECT_GS13 0x02002000U //!< GS13 RAM +#define MEMCFG_SECT_GS14 0x02004000U //!< GS14 RAM +#define MEMCFG_SECT_GS15 0x02008000U //!< GS15 RAM +#define MEMCFG_SECT_GSX_ALL 0x0200FFFFU //!< All GS RAM + +// +// MSGxRAM - Message RAM config +// +#define MEMCFG_SECT_MSGCPUTOCPU 0x03000001U //!< CPU-to-CPU message RAM +#define MEMCFG_SECT_MSGCPUTOCLA1 0x03000002U //!< CPU-to-CLA1 message RAM +#define MEMCFG_SECT_MSGCLA1TOCPU 0x03000004U //!< CLA1-to-CPU message RAM +#define MEMCFG_SECT_MSGX_ALL 0x03000007U //!< All message RAM + + +// +// All sections +// +#define MEMCFG_SECT_ALL 0xFFFFFFFFU //!< All configurable RAM + +//***************************************************************************** +// +// Values that can be passed to MemCfg_setProtection() as the protectMode +// parameter. +// +//***************************************************************************** +#define MEMCFG_PROT_ALLOWCPUFETCH 0x00000000U //!< CPU fetch allowed +#define MEMCFG_PROT_BLOCKCPUFETCH 0x00000001U //!< CPU fetch blocked + +#define MEMCFG_PROT_ALLOWCPUWRITE 0x00000000U //!< CPU write allowed +#define MEMCFG_PROT_BLOCKCPUWRITE 0x00000002U //!< CPU write blocked + +#define MEMCFG_PROT_ALLOWDMAWRITE 0x00000000U //!< DMA write allowed (GSxRAM) +#define MEMCFG_PROT_BLOCKDMAWRITE 0x00000004U //!< DMA write blocked (GSxRAM) + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_NMVIOL_CPUREAD 0x00000001U //!< Non-controller CPU read access +#define MEMCFG_NMVIOL_CPUWRITE 0x00000002U //!< Non-controller CPU write access +#define MEMCFG_NMVIOL_CPUFETCH 0x00000004U //!< Non-controller CPU fetch access +#define MEMCFG_NMVIOL_DMAWRITE 0x00000008U //!< Non-controller DMA write access +#define MEMCFG_NMVIOL_CLA1READ 0x00000010U //!< Non-controller CLA1 read access +#define MEMCFG_NMVIOL_CLA1WRITE 0x00000020U //!< Non-controller CLA1 write access +#define MEMCFG_NMVIOL_CLA1FETCH 0x00000040U //!< Non-controller CLA1 fetch access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_MVIOL_CPUFETCH 0x00010000U //!< Controller CPU fetch access +#define MEMCFG_MVIOL_CPUWRITE 0x00020000U //!< Controller CPU write access +#define MEMCFG_MVIOL_DMAWRITE 0x00040000U //!< Controller DMA write access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceCorrErrorStatus(), +// MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus(). +// +// Note that MEMCFG_CERR_CPUREAD is the only value below that has a +// corresponding interrupt and may be used with the error functions that take +// an intFlag(s) parameter. +// +//***************************************************************************** +#define MEMCFG_CERR_CPUREAD 0x0001U //!< Correctable CPU read error +#define MEMCFG_CERR_DMAREAD 0x0002U //!< Correctable DMA read error +#define MEMCFG_CERR_CLA1READ 0x0004U //!< Correctable CLA1 read error +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceUncorrErrorStatus(), +// MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus(). +// +//***************************************************************************** +#define MEMCFG_UCERR_CPUREAD 0x0001U //!< Uncorrectable CPU read error +#define MEMCFG_UCERR_DMAREAD 0x0002U //!< Uncorrectable DMA read error +#define MEMCFG_UCERR_CLA1READ 0x0004U //!< Uncorrectable CLA1 read error + +#endif + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_CLA_MEM_DATA, //!< Section is CLA data memory + MEMCFG_CLA_MEM_PROGRAM //!< Section is CLA program memory +} MemCfg_CLAMemoryType; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setLSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_LSRAMCONTROLLER_CPU_ONLY, //!< CPU is the owner of the section + MEMCFG_LSRAMCONTROLLER_CPU_CLA1 //!< CPU and CLA1 share this section +} MemCfg_LSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setGSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_GSRAMCONTROLLER_CPU1, //!< CPU1 is controller of the section + MEMCFG_GSRAMCONTROLLER_CPU2 //!< CPU2 is controller of the section +} MemCfg_GSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setTestMode() as the \e testMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Functional mode. Test mode is disabled. + MEMCFG_TEST_FUNCTIONAL = 0, + //! Writes allowed to data only + MEMCFG_TEST_WRITE_DATA = 1, + //! Writes allowed to ECC only (for DxRAM/MxRAM) + MEMCFG_TEST_WRITE_ECC = 2, + //! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM) + MEMCFG_TEST_WRITE_PARITY = 2 +} MemCfg_TestMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sets the CLA memory type of the specified RAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param claMemType indicates data memory or program memory. +//! +//! This function sets the CLA memory type configuration of the RAM section. If +//! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will +//! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM +//! section will be configured as CLA program memory. +//! +//! The \e ramSections parameter is an OR of the following indicators: +//! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx. +//! +//! \note This API only applies to LSx RAM and has no effect if the CLA isn't +//! controller of the memory section. +//! +//! \sa MemCfg_setLSRAControllerSel() +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType) +{ + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Write the CLA memory configuration to the appropriate register. Either + // set or clear the bit that determines the function of the RAM section as + // it relates to the CLA. + // + EALLOW; + + if(claMemType == MEMCFG_CLA_MEM_PROGRAM) + { + // + // Program memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) |= ramSections; + } + else + { + // + // Data memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) &= ~ramSections; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! This function enables the indicated RAM access violation interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableViolationInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function disables the indicated RAM access violation interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only non-controller violations may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableViolationInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) &= + ~(intFlags & MEMCFG_NMVIOL_MASK); + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) &= + ~((intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM access violation status. +//! +//! This function returns the RAM access violation status. This function will +//! return flags for both controller and non-controller access violations +//! although only the non-controller flags have the ability to cause the +//! generation of an interrupt. +//! +//! \return Returns the current violation status, enumerated as a bit field of +//! the values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//***************************************************************************** +static inline uint32_t +MemCfg_getViolationInterruptStatus(void) +{ + uint32_t status; + + // + // Read and return RAM access status flags. + // + status = (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVFLG)) | + (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVFLG) << + MEMCFG_MVIOL_SHIFT); + + return(status); +} + +//***************************************************************************** +// +//! Sets the RAM access violation status. +//! +//! \param intFlags is a bit mask of the access violation flags to be set. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function sets the RAM access violation status. This function will +//! set flags for both controller and non-controller access violations, and an +//! interrupt will be generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceViolationInterrupt(uint32_t intFlags) +{ + // + // Shift and mask the flags appropriately and write them to the + // corresponding SET register. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVSET) = + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVSET) = + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Clears RAM access violation flags. +//! +//! \param intFlags is a bit mask of the access violation flags to be cleared. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearViolationInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested access violation flags. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVCLR) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVCLR) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the correctable error threshold value. +//! +//! \param threshold is the correctable error threshold. +//! +//! This value sets the error-count threshold at which a correctable error +//! interrupt is generated. That is when the error count register reaches the +//! value specified by the \e threshold parameter, an interrupt is +//! generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCorrErrorThreshold(uint32_t threshold) +{ + // + // Write the threshold value to the appropriate register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRTHRES) = threshold; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the correctable error count. +//! +//! \return Returns the number of correctable error have occurred. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorCount(void) +{ + // + // Read and return the number of errors that have occurred. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCNT)); +} + +//***************************************************************************** +// +//! Enables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function enables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function disables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) &= ~(intFlags); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM correctable error interrupt status. +//! +//! \return Returns the current error interrupt status. Will return a value of +//! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the +//! function will return 0. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorInterruptStatus(void) +{ + // + // Read and return correctable error interrupt flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTFLG)); +} + +//***************************************************************************** +// +//! Sets the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be set. Can take +//! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function sets the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTSET) = intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function clears the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTCLR) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current correctable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRFLG)); +} + +//***************************************************************************** +// +//! Gets the current uncorrectable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getUncorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRFLG)); +} + +//***************************************************************************** +// +//! Sets the specified correctable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function sets the specified correctable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the specified uncorrectable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function sets the specified uncorrectable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears correctable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function clears the specified correctable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears uncorrectable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function clears the specified uncorrectable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 1-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMWaitState(void) +{ + // + // Clear the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) &= + ~((uint32_t)MEMCFG_ROMWAITSTATE_WSDISABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 0-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMWaitState(void) +{ + // + // Set the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) |= + MEMCFG_ROMWAITSTATE_WSDISABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMPrefetch(void) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) |= + MEMCFG_ROMPREFETCH_PFENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMPrefetch(void) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) &= + ~((uint32_t)MEMCFG_ROMPREFETCH_PFENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the writes to the configuration of specified memory sections. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function locks writes to the access protection and controller select +//! configuration of a memory section.That means calling MemCfg_setProtection() +//! or MemCfg_setLSRAMControllerSel() for a locked memory section will have no +//! effect until MemCfg_unlockConfig() is called. +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_lockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Unlocks the writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function unlocks writes to the access protection and controller select +//! configuration of a memory section that has been locked using +//! MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_unlockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Permanently locks writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function permanently locks writes to the access protection and +//! controller select configuration of a memory section. That means calling +//! MemCfg_setProtection() or MemCfg_setLSRAMControllerSel() for a locked memory +//! section will have no effect. To lock the configuration in a nonpermanent +//! way, use MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_commitConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Sets the access protection mode of a single memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param protectMode is the logical OR of the settings to be applied. +//! +//! This function sets the access protection mode of a specified memory section. +//! The mode is passed into the \e protectMode parameter as the logical OR of +//! the following values: +//! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch +//! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write +//! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_D0 or \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory +//! is configured as CLA program memory. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode); + +//***************************************************************************** +// +//! Sets the controller of the specified LSxRAM section. +//! +//! \param ramSection is the LSxRAM section to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the LSxRAM +//! section. +//! If the \e controllerSel parameter is \b MEMCFG_LSRAMCONTROLLER_CPU_ONLY, +//! the LSxRAM section passed into the \e ramSection parameter will be dedicated +//! to the CPU. If \b MEMCFG_LSRAMCONTROLLER_CPU_CLA1, the memory section will +//! be shared between the CPU and the CLA. +//! +//! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0 +//! through \b MEMCFG_SECT_LSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to LSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the controller of the specified GSxRAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the GSxRAM +//! section.If the \e controllerSel parameter is \b MEMCFG_GSRAMCONTROLLER_CPU1, +//! the GSRAM sections passed into the \e ramSections parameter will be +//! dedicated to CPU1. If \b MEMCFG_GSRAMCONTROLLER_CPU2, the memory section +//! will be dedicated to CPU2. +//! +//! The \e ramSections parameter should be a logical OR of values from +//! \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to GSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the test mode of the specified memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param testMode is the test mode selected. +//! +//! This function sets the test mode configuration of the RAM section. The +//! \e testMode parameter can take one of the following values: +//! - \b MEMCFG_TEST_FUNCTIONAL +//! - \b MEMCFG_TEST_WRITE_DATA +//! - \b MEMCFG_TEST_WRITE_ECC +//! - \b MEMCFG_TEST_WRITE_PARITY +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1 +//! - \b MEMCFG_SECT_D0, \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode); + +//***************************************************************************** +// +//! Starts the initialization the specified RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be initialized. +//! +//! This function starts the initialization of the specified RAM sections. Use +//! MemCfg_getInitStatus() to check if the initialization is done. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_initSections(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the status of initialized RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be checked. +//! +//! This function gets the initialization status of the RAM sections specified +//! by the \e ramSections parameter. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections. +//! +//! \note Use MemCfg_initSections() to start the initialization. +//! +//! \return Returns \b true if all the sections specified by \e ramSections +//! have been initialized and \b false if not. +// +//***************************************************************************** +extern bool +MemCfg_getInitStatus(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the violation address associated with a intFlag. +//! +//! \param intFlag is the type of access violation as indicated by ONE of +//! these values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return Returns the violation address associated with the \e intFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getViolationAddress(uint32_t intFlag); + +//***************************************************************************** +// +//! Get the correctable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. Can currently take the value \b MEMCFG_CERR_CPUREAD only. +//! Other values are reserved. +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag); + +//***************************************************************************** +// +//! Get the uncorrectable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. It may be passed one of these values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or +//! \b MEMCFG_UCERR_CLA1READ values +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MEMCFG_H diff --git a/gpio_bitfield_cpu1/device/driverlib/pin_map.h b/gpio_bitfield_cpu1/device/driverlib/pin_map.h new file mode 100644 index 0000000..95c6fa3 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/pin_map.h @@ -0,0 +1,894 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// 0x00000003 = MUX register value +// 0x0000000C = GMUX register value +// 0x0000FF00 = Shift amount within mux registers +// 0xFFFF0000 = Offset of MUX register +//***************************************************************************** + + +#define GPIO_0_GPIO0 0x00060000U +#define GPIO_0_EPWM1A 0x00060001U +#define GPIO_0_SDAA 0x00060006U + +#define GPIO_1_GPIO1 0x00060200U +#define GPIO_1_EPWM1B 0x00060201U +#define GPIO_1_MFSRB 0x00060203U +#define GPIO_1_SCLA 0x00060206U + +#define GPIO_2_GPIO2 0x00060400U +#define GPIO_2_EPWM2A 0x00060401U +#define GPIO_2_OUTPUTXBAR1 0x00060405U +#define GPIO_2_SDAB 0x00060406U + +#define GPIO_3_GPIO3 0x00060600U +#define GPIO_3_EPWM2B 0x00060601U +#define GPIO_3_OUTPUTXBAR2 0x00060602U +#define GPIO_3_MCLKRB 0x00060603U +#define GPIO_3_SCLB 0x00060606U + +#define GPIO_4_GPIO4 0x00060800U +#define GPIO_4_EPWM3A 0x00060801U +#define GPIO_4_OUTPUTXBAR3 0x00060805U +#define GPIO_4_CANTXA 0x00060806U + +#define GPIO_5_GPIO5 0x00060A00U +#define GPIO_5_EPWM3B 0x00060A01U +#define GPIO_5_MFSRA 0x00060A02U +#define GPIO_5_OUTPUTXBAR3 0x00060A03U +#define GPIO_5_CANRXA 0x00060A06U + +#define GPIO_6_GPIO6 0x00060C00U +#define GPIO_6_EPWM4A 0x00060C01U +#define GPIO_6_OUTPUTXBAR4 0x00060C02U +#define GPIO_6_EPWMSYNCO 0x00060C03U +#define GPIO_6_EQEP3A 0x00060C05U +#define GPIO_6_CANTXB 0x00060C06U + +#define GPIO_7_GPIO7 0x00060E00U +#define GPIO_7_EPWM4B 0x00060E01U +#define GPIO_7_MCLKRA 0x00060E02U +#define GPIO_7_OUTPUTXBAR5 0x00060E03U +#define GPIO_7_EQEP3B 0x00060E05U +#define GPIO_7_CANRXB 0x00060E06U + +#define GPIO_8_GPIO8 0x00061000U +#define GPIO_8_EPWM5A 0x00061001U +#define GPIO_8_CANTXB 0x00061002U +#define GPIO_8_ADCSOCAO 0x00061003U +#define GPIO_8_EQEP3S 0x00061005U +#define GPIO_8_SCITXDA 0x00061006U + +#define GPIO_9_GPIO9 0x00061200U +#define GPIO_9_EPWM5B 0x00061201U +#define GPIO_9_SCITXDB 0x00061202U +#define GPIO_9_OUTPUTXBAR6 0x00061203U +#define GPIO_9_EQEP3I 0x00061205U +#define GPIO_9_SCIRXDA 0x00061206U + +#define GPIO_10_GPIO10 0x00061400U +#define GPIO_10_EPWM6A 0x00061401U +#define GPIO_10_CANRXB 0x00061402U +#define GPIO_10_ADCSOCBO 0x00061403U +#define GPIO_10_EQEP1A 0x00061405U +#define GPIO_10_SCITXDB 0x00061406U +#define GPIO_10_UPP_WAIT 0x0006140FU + +#define GPIO_11_GPIO11 0x00061600U +#define GPIO_11_EPWM6B 0x00061601U +#define GPIO_11_SCIRXDB 0x00061602U +#define GPIO_11_OUTPUTXBAR7 0x00061603U +#define GPIO_11_EQEP1B 0x00061605U +#define GPIO_11_UPP_STRT 0x0006160FU + +#define GPIO_12_GPIO12 0x00061800U +#define GPIO_12_EPWM7A 0x00061801U +#define GPIO_12_CANTXB 0x00061802U +#define GPIO_12_MDXB 0x00061803U +#define GPIO_12_EQEP1S 0x00061805U +#define GPIO_12_SCITXDC 0x00061806U +#define GPIO_12_UPP_ENA 0x0006180FU + +#define GPIO_13_GPIO13 0x00061A00U +#define GPIO_13_EPWM7B 0x00061A01U +#define GPIO_13_CANRXB 0x00061A02U +#define GPIO_13_MDRB 0x00061A03U +#define GPIO_13_EQEP1I 0x00061A05U +#define GPIO_13_SCIRXDC 0x00061A06U +#define GPIO_13_UPP_D7 0x00061A0FU + +#define GPIO_14_GPIO14 0x00061C00U +#define GPIO_14_EPWM8A 0x00061C01U +#define GPIO_14_SCITXDB 0x00061C02U +#define GPIO_14_MCLKXB 0x00061C03U +#define GPIO_14_OUTPUTXBAR3 0x00061C06U +#define GPIO_14_UPP_D6 0x00061C0FU + +#define GPIO_15_GPIO15 0x00061E00U +#define GPIO_15_EPWM8B 0x00061E01U +#define GPIO_15_SCIRXDB 0x00061E02U +#define GPIO_15_MFSXB 0x00061E03U +#define GPIO_15_OUTPUTXBAR4 0x00061E06U +#define GPIO_15_UPP_D5 0x00061E0FU + +#define GPIO_16_GPIO16 0x00080000U +#define GPIO_16_SPISIMOA 0x00080001U +#define GPIO_16_CANTXB 0x00080002U +#define GPIO_16_OUTPUTXBAR7 0x00080003U +#define GPIO_16_EPWM9A 0x00080005U +#define GPIO_16_SD1_D1 0x00080007U +#define GPIO_16_UPP_D4 0x0008000FU + +#define GPIO_17_GPIO17 0x00080200U +#define GPIO_17_SPISOMIA 0x00080201U +#define GPIO_17_CANRXB 0x00080202U +#define GPIO_17_OUTPUTXBAR8 0x00080203U +#define GPIO_17_EPWM9B 0x00080205U +#define GPIO_17_SD1_C1 0x00080207U +#define GPIO_17_UPP_D3 0x0008020FU + +#define GPIO_18_GPIO18 0x00080400U +#define GPIO_18_SPICLKA 0x00080401U +#define GPIO_18_SCITXDB 0x00080402U +#define GPIO_18_CANRXA 0x00080403U +#define GPIO_18_EPWM10A 0x00080405U +#define GPIO_18_SD1_D2 0x00080407U +#define GPIO_18_UPP_D2 0x0008040FU + +#define GPIO_19_GPIO19 0x00080600U +#define GPIO_19_SPISTEA 0x00080601U +#define GPIO_19_SCIRXDB 0x00080602U +#define GPIO_19_CANTXA 0x00080603U +#define GPIO_19_EPWM10B 0x00080605U +#define GPIO_19_SD1_C2 0x00080607U +#define GPIO_19_UPP_D1 0x0008060FU + +#define GPIO_20_GPIO20 0x00080800U +#define GPIO_20_EQEP1A 0x00080801U +#define GPIO_20_MDXA 0x00080802U +#define GPIO_20_CANTXB 0x00080803U +#define GPIO_20_EPWM11A 0x00080805U +#define GPIO_20_SD1_D3 0x00080807U +#define GPIO_20_UPP_D0 0x0008080FU + +#define GPIO_21_GPIO21 0x00080A00U +#define GPIO_21_EQEP1B 0x00080A01U +#define GPIO_21_MDRA 0x00080A02U +#define GPIO_21_CANRXB 0x00080A03U +#define GPIO_21_EPWM11B 0x00080A05U +#define GPIO_21_SD1_C3 0x00080A07U +#define GPIO_21_UPP_CLK 0x00080A0FU + +#define GPIO_22_GPIO22 0x00080C00U +#define GPIO_22_EQEP1S 0x00080C01U +#define GPIO_22_MCLKXA 0x00080C02U +#define GPIO_22_SCITXDB 0x00080C03U +#define GPIO_22_EPWM12A 0x00080C05U +#define GPIO_22_SPICLKB 0x00080C06U +#define GPIO_22_SD1_D4 0x00080C07U + +#define GPIO_23_GPIO23 0x00080E00U +#define GPIO_23_EQEP1I 0x00080E01U +#define GPIO_23_MFSXA 0x00080E02U +#define GPIO_23_SCIRXDB 0x00080E03U +#define GPIO_23_EPWM12B 0x00080E05U +#define GPIO_23_SPISTEB 0x00080E06U +#define GPIO_23_SD1_C4 0x00080E07U + +#define GPIO_24_GPIO24 0x00081000U +#define GPIO_24_OUTPUTXBAR1 0x00081001U +#define GPIO_24_EQEP2A 0x00081002U +#define GPIO_24_MDXB 0x00081003U +#define GPIO_24_SPISIMOB 0x00081006U +#define GPIO_24_SD2_D1 0x00081007U + +#define GPIO_25_GPIO25 0x00081200U +#define GPIO_25_OUTPUTXBAR2 0x00081201U +#define GPIO_25_EQEP2B 0x00081202U +#define GPIO_25_MDRB 0x00081203U +#define GPIO_25_SPISOMIB 0x00081206U +#define GPIO_25_SD2_C1 0x00081207U + +#define GPIO_26_GPIO26 0x00081400U +#define GPIO_26_OUTPUTXBAR3 0x00081401U +#define GPIO_26_EQEP2I 0x00081402U +#define GPIO_26_MCLKXB 0x00081403U +#define GPIO_26_SPICLKB 0x00081406U +#define GPIO_26_SD2_D2 0x00081407U + +#define GPIO_27_GPIO27 0x00081600U +#define GPIO_27_OUTPUTXBAR4 0x00081601U +#define GPIO_27_EQEP2S 0x00081602U +#define GPIO_27_MFSXB 0x00081603U +#define GPIO_27_SPISTEB 0x00081606U +#define GPIO_27_SD2_C2 0x00081607U + +#define GPIO_28_GPIO28 0x00081800U +#define GPIO_28_SCIRXDA 0x00081801U +#define GPIO_28_EM1CS4N 0x00081802U +#define GPIO_28_OUTPUTXBAR5 0x00081805U +#define GPIO_28_EQEP3A 0x00081806U +#define GPIO_28_SD2_D3 0x00081807U + +#define GPIO_29_GPIO29 0x00081A00U +#define GPIO_29_SCITXDA 0x00081A01U +#define GPIO_29_EM1SDCKE 0x00081A02U +#define GPIO_29_OUTPUTXBAR6 0x00081A05U +#define GPIO_29_EQEP3B 0x00081A06U +#define GPIO_29_SD2_C3 0x00081A07U + +#define GPIO_30_GPIO30 0x00081C00U +#define GPIO_30_CANRXA 0x00081C01U +#define GPIO_30_EM1CLK 0x00081C02U +#define GPIO_30_OUTPUTXBAR7 0x00081C05U +#define GPIO_30_EQEP3S 0x00081C06U +#define GPIO_30_SD2_D4 0x00081C07U + +#define GPIO_31_GPIO31 0x00081E00U +#define GPIO_31_CANTXA 0x00081E01U +#define GPIO_31_EM1WEN 0x00081E02U +#define GPIO_31_OUTPUTXBAR8 0x00081E05U +#define GPIO_31_EQEP3I 0x00081E06U +#define GPIO_31_SD2_C4 0x00081E07U + +#define GPIO_32_GPIO32 0x00460000U +#define GPIO_32_SDAA 0x00460001U +#define GPIO_32_EM1CS0N 0x00460002U + +#define GPIO_33_GPIO33 0x00460200U +#define GPIO_33_SCLA 0x00460201U +#define GPIO_33_EM1RNW 0x00460202U + +#define GPIO_34_GPIO34 0x00460400U +#define GPIO_34_OUTPUTXBAR1 0x00460401U +#define GPIO_34_EM1CS2N 0x00460402U +#define GPIO_34_SDAB 0x00460406U +#define GPIO_34_OFSD_2_N 0x0046040FU + +#define GPIO_35_GPIO35 0x00460600U +#define GPIO_35_SCIRXDA 0x00460601U +#define GPIO_35_EM1CS3N 0x00460602U +#define GPIO_35_SCLB 0x00460606U +#define GPIO_35_IID 0x0046060FU + +#define GPIO_36_GPIO36 0x00460800U +#define GPIO_36_SCITXDA 0x00460801U +#define GPIO_36_EM1WAIT 0x00460802U +#define GPIO_36_CANRXA 0x00460806U +#define GPIO_36_ISESSEND 0x0046080FU + +#define GPIO_37_GPIO37 0x00460A00U +#define GPIO_37_OUTPUTXBAR2 0x00460A01U +#define GPIO_37_EM1OEN 0x00460A02U +#define GPIO_37_CANTXA 0x00460A06U +#define GPIO_37_IAVALID 0x00460A0FU + +#define GPIO_38_GPIO38 0x00460C00U +#define GPIO_38_EM1A0 0x00460C02U +#define GPIO_38_SCITXDC 0x00460C05U +#define GPIO_38_CANTXB 0x00460C06U + +#define GPIO_39_GPIO39 0x00460E00U +#define GPIO_39_EM1A1 0x00460E02U +#define GPIO_39_SCIRXDC 0x00460E05U +#define GPIO_39_CANRXB 0x00460E06U + +#define GPIO_40_GPIO40 0x00461000U +#define GPIO_40_EM1A2 0x00461002U +#define GPIO_40_SDAB 0x00461006U + +#define GPIO_41_GPIO41 0x00461200U +#define GPIO_41_EM1A3 0x00461202U +#define GPIO_41_EMU1 0x00461203U +#define GPIO_41_SCLB 0x00461206U + +#define GPIO_42_GPIO42 0x00461400U +#define GPIO_42_SDAA 0x00461406U +#define GPIO_42_SCITXDA 0x0046140FU + +#define GPIO_43_GPIO43 0x00461600U +#define GPIO_43_SCLA 0x00461606U +#define GPIO_43_SCIRXDA 0x0046160FU + +#define GPIO_44_GPIO44 0x00461800U +#define GPIO_44_EM1A4 0x00461802U +#define GPIO_44_IXRCV 0x0046180FU + +#define GPIO_45_GPIO45 0x00461A00U +#define GPIO_45_EM1A5 0x00461A02U +#define GPIO_45_IDM 0x00461A0FU + +#define GPIO_46_GPIO46 0x00461C00U +#define GPIO_46_EM1A6 0x00461C02U +#define GPIO_46_SCIRXDD 0x00461C06U +#define GPIO_46_IDP 0x00461C0FU + +#define GPIO_47_GPIO47 0x00461E00U +#define GPIO_47_EM1A7 0x00461E02U +#define GPIO_47_SCITXDD 0x00461E06U +#define GPIO_47_OFSD_1_N 0x00461E0FU + +#define GPIO_48_GPIO48 0x00480000U +#define GPIO_48_OUTPUTXBAR3 0x00480001U +#define GPIO_48_EM1A8 0x00480002U +#define GPIO_48_SCITXDA 0x00480006U +#define GPIO_48_SD1_D1 0x00480007U + +#define GPIO_49_GPIO49 0x00480200U +#define GPIO_49_OUTPUTXBAR4 0x00480201U +#define GPIO_49_EM1A9 0x00480202U +#define GPIO_49_SCIRXDA 0x00480206U +#define GPIO_49_SD1_C1 0x00480207U + +#define GPIO_50_GPIO50 0x00480400U +#define GPIO_50_EQEP1A 0x00480401U +#define GPIO_50_EM1A10 0x00480402U +#define GPIO_50_SPISIMOC 0x00480406U +#define GPIO_50_SD1_D2 0x00480407U + +#define GPIO_51_GPIO51 0x00480600U +#define GPIO_51_EQEP1B 0x00480601U +#define GPIO_51_EM1A11 0x00480602U +#define GPIO_51_SPISOMIC 0x00480606U +#define GPIO_51_SD1_C2 0x00480607U + +#define GPIO_52_GPIO52 0x00480800U +#define GPIO_52_EQEP1S 0x00480801U +#define GPIO_52_EM1A12 0x00480802U +#define GPIO_52_SPICLKC 0x00480806U +#define GPIO_52_SD1_D3 0x00480807U + +#define GPIO_53_GPIO53 0x00480A00U +#define GPIO_53_EQEP1I 0x00480A01U +#define GPIO_53_EM1D31 0x00480A02U +#define GPIO_53_EM2D15 0x00480A03U +#define GPIO_53_SPISTEC 0x00480A06U +#define GPIO_53_SD1_C3 0x00480A07U + +#define GPIO_54_GPIO54 0x00480C00U +#define GPIO_54_SPISIMOA 0x00480C01U +#define GPIO_54_EM1D30 0x00480C02U +#define GPIO_54_EM2D14 0x00480C03U +#define GPIO_54_EQEP2A 0x00480C05U +#define GPIO_54_SCITXDB 0x00480C06U +#define GPIO_54_SD1_D4 0x00480C07U + +#define GPIO_55_GPIO55 0x00480E00U +#define GPIO_55_SPISOMIA 0x00480E01U +#define GPIO_55_EM1D29 0x00480E02U +#define GPIO_55_EM2D13 0x00480E03U +#define GPIO_55_EQEP2B 0x00480E05U +#define GPIO_55_SCIRXDB 0x00480E06U +#define GPIO_55_SD1_C4 0x00480E07U + +#define GPIO_56_GPIO56 0x00481000U +#define GPIO_56_SPICLKA 0x00481001U +#define GPIO_56_EM1D28 0x00481002U +#define GPIO_56_EM2D12 0x00481003U +#define GPIO_56_EQEP2S 0x00481005U +#define GPIO_56_SCITXDC 0x00481006U +#define GPIO_56_SD2_D1 0x00481007U + +#define GPIO_57_GPIO57 0x00481200U +#define GPIO_57_SPISTEA 0x00481201U +#define GPIO_57_EM1D27 0x00481202U +#define GPIO_57_EM2D11 0x00481203U +#define GPIO_57_EQEP2I 0x00481205U +#define GPIO_57_SCIRXDC 0x00481206U +#define GPIO_57_SD2_C1 0x00481207U + +#define GPIO_58_GPIO58 0x00481400U +#define GPIO_58_MCLKRA 0x00481401U +#define GPIO_58_EM1D26 0x00481402U +#define GPIO_58_EM2D10 0x00481403U +#define GPIO_58_OUTPUTXBAR1 0x00481405U +#define GPIO_58_SPICLKB 0x00481406U +#define GPIO_58_SD2_D2 0x00481407U +#define GPIO_58_SPISIMOA 0x0048140FU + +#define GPIO_59_GPIO59 0x00481600U +#define GPIO_59_MFSRA 0x00481601U +#define GPIO_59_EM1D25 0x00481602U +#define GPIO_59_EM2D9 0x00481603U +#define GPIO_59_OUTPUTXBAR2 0x00481605U +#define GPIO_59_SPISTEB 0x00481606U +#define GPIO_59_SD2_C2 0x00481607U +#define GPIO_59_SPISOMIA 0x0048160FU + +#define GPIO_60_GPIO60 0x00481800U +#define GPIO_60_MCLKRB 0x00481801U +#define GPIO_60_EM1D24 0x00481802U +#define GPIO_60_EM2D8 0x00481803U +#define GPIO_60_OUTPUTXBAR3 0x00481805U +#define GPIO_60_SPISIMOB 0x00481806U +#define GPIO_60_SD2_D3 0x00481807U +#define GPIO_60_SPICLKA 0x0048180FU + +#define GPIO_61_GPIO61 0x00481A00U +#define GPIO_61_MFSRB 0x00481A01U +#define GPIO_61_EM1D23 0x00481A02U +#define GPIO_61_EM2D7 0x00481A03U +#define GPIO_61_OUTPUTXBAR4 0x00481A05U +#define GPIO_61_SPISOMIB 0x00481A06U +#define GPIO_61_SD2_C3 0x00481A07U +#define GPIO_61_SPISTEA 0x00481A0FU + +#define GPIO_62_GPIO62 0x00481C00U +#define GPIO_62_SCIRXDC 0x00481C01U +#define GPIO_62_EM1D22 0x00481C02U +#define GPIO_62_EM2D6 0x00481C03U +#define GPIO_62_EQEP3A 0x00481C05U +#define GPIO_62_CANRXA 0x00481C06U +#define GPIO_62_SD2_D4 0x00481C07U + +#define GPIO_63_GPIO63 0x00481E00U +#define GPIO_63_SCITXDC 0x00481E01U +#define GPIO_63_EM1D21 0x00481E02U +#define GPIO_63_EM2D5 0x00481E03U +#define GPIO_63_EQEP3B 0x00481E05U +#define GPIO_63_CANTXA 0x00481E06U +#define GPIO_63_SD2_C4 0x00481E07U +#define GPIO_63_SPISIMOB 0x00481E0FU + +#define GPIO_64_GPIO64 0x00860000U +#define GPIO_64_EM1D20 0x00860002U +#define GPIO_64_EM2D4 0x00860003U +#define GPIO_64_EQEP3S 0x00860005U +#define GPIO_64_SCIRXDA 0x00860006U +#define GPIO_64_SPISOMIB 0x0086000FU + +#define GPIO_65_GPIO65 0x00860200U +#define GPIO_65_EM1D19 0x00860202U +#define GPIO_65_EM2D3 0x00860203U +#define GPIO_65_EQEP3I 0x00860205U +#define GPIO_65_SCITXDA 0x00860206U +#define GPIO_65_SPICLKB 0x0086020FU + +#define GPIO_66_GPIO66 0x00860400U +#define GPIO_66_EM1D18 0x00860402U +#define GPIO_66_EM2D2 0x00860403U +#define GPIO_66_SDAB 0x00860406U +#define GPIO_66_SPISTEB 0x0086040FU + +#define GPIO_67_GPIO67 0x00860600U +#define GPIO_67_EM1D17 0x00860602U +#define GPIO_67_EM2D1 0x00860603U + +#define GPIO_68_GPIO68 0x00860800U +#define GPIO_68_EM1D16 0x00860802U +#define GPIO_68_EM2D0 0x00860803U + +#define GPIO_69_GPIO69 0x00860A00U +#define GPIO_69_EM1D15 0x00860A02U +#define GPIO_69_EMU0 0x00860A03U +#define GPIO_69_SCLB 0x00860A06U +#define GPIO_69_SPISIMOC 0x00860A0FU + +#define GPIO_70_GPIO70 0x00860C00U +#define GPIO_70_EM1D14 0x00860C02U +#define GPIO_70_EMU0 0x00860C03U +#define GPIO_70_CANRXA 0x00860C05U +#define GPIO_70_SCITXDB 0x00860C06U +#define GPIO_70_SPISOMIC 0x00860C0FU + +#define GPIO_71_GPIO71 0x00860E00U +#define GPIO_71_EM1D13 0x00860E02U +#define GPIO_71_EMU1 0x00860E03U +#define GPIO_71_CANTXA 0x00860E05U +#define GPIO_71_SCIRXDB 0x00860E06U +#define GPIO_71_SPICLKC 0x00860E0FU + +#define GPIO_72_GPIO72 0x00861000U +#define GPIO_72_EM1D12 0x00861002U +#define GPIO_72_CANTXB 0x00861005U +#define GPIO_72_SCITXDC 0x00861006U +#define GPIO_72_SPISTEC 0x0086100FU + +#define GPIO_73_GPIO73 0x00861200U +#define GPIO_73_EM1D11 0x00861202U +#define GPIO_73_XCLKOUT 0x00861203U +#define GPIO_73_CANRXB 0x00861205U +#define GPIO_73_SCIRXDC 0x00861206U + +#define GPIO_74_GPIO74 0x00861400U +#define GPIO_74_EM1D10 0x00861402U + +#define GPIO_75_GPIO75 0x00861600U +#define GPIO_75_EM1D9 0x00861602U + +#define GPIO_76_GPIO76 0x00861800U +#define GPIO_76_EM1D8 0x00861802U +#define GPIO_76_SCITXDD 0x00861806U + +#define GPIO_77_GPIO77 0x00861A00U +#define GPIO_77_EM1D7 0x00861A02U +#define GPIO_77_SCIRXDD 0x00861A06U + +#define GPIO_78_GPIO78 0x00861C00U +#define GPIO_78_EM1D6 0x00861C02U +#define GPIO_78_EQEP2A 0x00861C06U + +#define GPIO_79_GPIO79 0x00861E00U +#define GPIO_79_EM1D5 0x00861E02U +#define GPIO_79_EQEP2B 0x00861E06U + +#define GPIO_80_GPIO80 0x00880000U +#define GPIO_80_EM1D4 0x00880002U +#define GPIO_80_EQEP2S 0x00880006U + +#define GPIO_81_GPIO81 0x00880200U +#define GPIO_81_EM1D3 0x00880202U +#define GPIO_81_EQEP2I 0x00880206U + +#define GPIO_82_GPIO82 0x00880400U +#define GPIO_82_EM1D2 0x00880402U + +#define GPIO_83_GPIO83 0x00880600U +#define GPIO_83_EM1D1 0x00880602U + +#define GPIO_84_GPIO84 0x00880800U +#define GPIO_84_SCITXDA 0x00880805U +#define GPIO_84_MDXB 0x00880806U +#define GPIO_84_MDXA 0x0088080FU + +#define GPIO_85_GPIO85 0x00880A00U +#define GPIO_85_EM1D0 0x00880A02U +#define GPIO_85_SCIRXDA 0x00880A05U +#define GPIO_85_MDRB 0x00880A06U +#define GPIO_85_MDRA 0x00880A0FU + +#define GPIO_86_GPIO86 0x00880C00U +#define GPIO_86_EM1A13 0x00880C02U +#define GPIO_86_EM1CAS 0x00880C03U +#define GPIO_86_SCITXDB 0x00880C05U +#define GPIO_86_MCLKXB 0x00880C06U +#define GPIO_86_MCLKXA 0x00880C0FU + +#define GPIO_87_GPIO87 0x00880E00U +#define GPIO_87_EM1A14 0x00880E02U +#define GPIO_87_EM1RAS 0x00880E03U +#define GPIO_87_SCIRXDB 0x00880E05U +#define GPIO_87_MFSXB 0x00880E06U +#define GPIO_87_MFSXA 0x00880E0FU + +#define GPIO_88_GPIO88 0x00881000U +#define GPIO_88_EM1A15 0x00881002U +#define GPIO_88_EM1DQM0 0x00881003U + +#define GPIO_89_GPIO89 0x00881200U +#define GPIO_89_EM1A16 0x00881202U +#define GPIO_89_EM1DQM1 0x00881203U +#define GPIO_89_SCITXDC 0x00881206U + +#define GPIO_90_GPIO90 0x00881400U +#define GPIO_90_EM1A17 0x00881402U +#define GPIO_90_EM1DQM2 0x00881403U +#define GPIO_90_SCIRXDC 0x00881406U + +#define GPIO_91_GPIO91 0x00881600U +#define GPIO_91_EM1A18 0x00881602U +#define GPIO_91_EM1DQM3 0x00881603U +#define GPIO_91_SDAA 0x00881606U + +#define GPIO_92_GPIO92 0x00881800U +#define GPIO_92_EM1A19 0x00881802U +#define GPIO_92_EM1BA1 0x00881803U +#define GPIO_92_SCLA 0x00881806U + +#define GPIO_93_GPIO93 0x00881A00U +#define GPIO_93_EM1A20 0x00881A02U +#define GPIO_93_EM1BA0 0x00881A03U +#define GPIO_93_SCITXDD 0x00881A06U + +#define GPIO_94_GPIO94 0x00881C00U +#define GPIO_94_EM1A21 0x00881C02U +#define GPIO_94_SCIRXDD 0x00881C06U + +#define GPIO_95_GPIO95 0x00881E00U + +#define GPIO_96_GPIO96 0x00C60000U +#define GPIO_96_EM2DQM1 0x00C60003U +#define GPIO_96_EQEP1A 0x00C60005U + +#define GPIO_97_GPIO97 0x00C60200U +#define GPIO_97_EM2DQM0 0x00C60203U +#define GPIO_97_EQEP1B 0x00C60205U + +#define GPIO_98_GPIO98 0x00C60400U +#define GPIO_98_EM2A0 0x00C60403U +#define GPIO_98_EQEP1S 0x00C60405U + +#define GPIO_99_GPIO99 0x00C60600U +#define GPIO_99_EM2A1 0x00C60603U +#define GPIO_99_EQEP1I 0x00C60605U + +#define GPIO_100_GPIO100 0x00C60800U +#define GPIO_100_EM2A2 0x00C60803U +#define GPIO_100_EQEP2A 0x00C60805U +#define GPIO_100_SPISIMOC 0x00C60806U + +#define GPIO_101_GPIO101 0x00C60A00U +#define GPIO_101_EM2A3 0x00C60A03U +#define GPIO_101_EQEP2B 0x00C60A05U +#define GPIO_101_SPISOMIC 0x00C60A06U + +#define GPIO_102_GPIO102 0x00C60C00U +#define GPIO_102_EM2A4 0x00C60C03U +#define GPIO_102_EQEP2S 0x00C60C05U +#define GPIO_102_SPICLKC 0x00C60C06U + +#define GPIO_103_GPIO103 0x00C60E00U +#define GPIO_103_EM2A5 0x00C60E03U +#define GPIO_103_EQEP2I 0x00C60E05U +#define GPIO_103_SPISTEC 0x00C60E06U + +#define GPIO_104_GPIO104 0x00C61000U +#define GPIO_104_SDAA 0x00C61001U +#define GPIO_104_EM2A6 0x00C61003U +#define GPIO_104_EQEP3A 0x00C61005U +#define GPIO_104_SCITXDD 0x00C61006U + +#define GPIO_105_GPIO105 0x00C61200U +#define GPIO_105_SCLA 0x00C61201U +#define GPIO_105_EM2A7 0x00C61203U +#define GPIO_105_EQEP3B 0x00C61205U +#define GPIO_105_SCIRXDD 0x00C61206U + +#define GPIO_106_GPIO106 0x00C61400U +#define GPIO_106_EM2A8 0x00C61403U +#define GPIO_106_EQEP3S 0x00C61405U +#define GPIO_106_SCITXDC 0x00C61406U + +#define GPIO_107_GPIO107 0x00C61600U +#define GPIO_107_EM2A9 0x00C61603U +#define GPIO_107_EQEP3I 0x00C61605U +#define GPIO_107_SCIRXDC 0x00C61606U + +#define GPIO_108_GPIO108 0x00C61800U +#define GPIO_108_EM2A10 0x00C61803U + +#define GPIO_109_GPIO109 0x00C61A00U +#define GPIO_109_EM2A11 0x00C61A03U + +#define GPIO_110_GPIO110 0x00C61C00U +#define GPIO_110_EM2WAIT 0x00C61C03U + +#define GPIO_111_GPIO111 0x00C61E00U +#define GPIO_111_EM2BA0 0x00C61E03U + +#define GPIO_112_GPIO112 0x00C80000U +#define GPIO_112_EM2BA1 0x00C80003U + +#define GPIO_113_GPIO113 0x00C80200U +#define GPIO_113_EM2CAS 0x00C80203U + +#define GPIO_114_GPIO114 0x00C80400U +#define GPIO_114_EM2RAS 0x00C80403U + +#define GPIO_115_GPIO115 0x00C80600U +#define GPIO_115_EM2CS0N 0x00C80603U + +#define GPIO_116_GPIO116 0x00C80800U +#define GPIO_116_EM2CS2N 0x00C80803U + +#define GPIO_117_GPIO117 0x00C80A00U +#define GPIO_117_EM2SDCKE 0x00C80A03U + +#define GPIO_118_GPIO118 0x00C80C00U +#define GPIO_118_EM2CLK 0x00C80C03U + +#define GPIO_119_GPIO119 0x00C80E00U +#define GPIO_119_EM2RNW 0x00C80E03U + +#define GPIO_120_GPIO120 0x00C81000U +#define GPIO_120_EM2WEN 0x00C81003U +#define GPIO_120_USB0PFLT 0x00C8100FU + +#define GPIO_121_GPIO121 0x00C81200U +#define GPIO_121_EM2OEN 0x00C81203U +#define GPIO_121_USB0EPEN 0x00C8120FU + +#define GPIO_122_GPIO122 0x00C81400U +#define GPIO_122_SPISIMOC 0x00C81406U +#define GPIO_122_SD1_D1 0x00C81407U +#define GPIO_122_ODISCHRGVBUS 0x00C8140FU + +#define GPIO_123_GPIO123 0x00C81600U +#define GPIO_123_SPISOMIC 0x00C81606U +#define GPIO_123_SD1_C1 0x00C81607U +#define GPIO_123_OCHRGVBUS 0x00C8160FU + +#define GPIO_124_GPIO124 0x00C81800U +#define GPIO_124_SPICLKC 0x00C81806U +#define GPIO_124_SD1_D2 0x00C81807U +#define GPIO_124_ODMPULLDN 0x00C8180FU + +#define GPIO_125_GPIO125 0x00C81A00U +#define GPIO_125_SPISTEC 0x00C81A06U +#define GPIO_125_SD1_C2 0x00C81A07U +#define GPIO_125_ODPPULLDN 0x00C81A0FU + +#define GPIO_126_GPIO126 0x00C81C00U +#define GPIO_126_SD1_D3 0x00C81C07U +#define GPIO_126_OLSD_2_N 0x00C81C0FU + +#define GPIO_127_GPIO127 0x00C81E00U +#define GPIO_127_SD1_C3 0x00C81E07U +#define GPIO_127_OLSD_1_N 0x00C81E0FU + +#define GPIO_128_GPIO128 0x01060000U +#define GPIO_128_SD1_D4 0x01060007U +#define GPIO_128_OIDPULLUP 0x0106000FU + +#define GPIO_129_GPIO129 0x01060200U +#define GPIO_129_SD1_C4 0x01060207U +#define GPIO_129_OSPEED 0x0106020FU + +#define GPIO_130_GPIO130 0x01060400U +#define GPIO_130_SD2_D1 0x01060407U +#define GPIO_130_OSUSPEND 0x0106040FU + +#define GPIO_131_GPIO131 0x01060600U +#define GPIO_131_SD2_C1 0x01060607U +#define GPIO_131_OOE 0x0106060FU + +#define GPIO_132_GPIO132 0x01060800U +#define GPIO_132_SD2_D2 0x01060807U +#define GPIO_132_ODMSE1 0x0106080FU + +#define GPIO_133_GPIO133 0x01060A00U +#define GPIO_133_SD2_C2 0x01060A07U +#define GPIO_133_ODPDAT 0x01060A0FU + +#define GPIO_134_GPIO134 0x01060C00U +#define GPIO_134_SD2_D3 0x01060C07U +#define GPIO_134_IVBUSVALID 0x01060C0FU + +#define GPIO_135_GPIO135 0x01060E00U +#define GPIO_135_SCITXDA 0x01060E06U +#define GPIO_135_SD2_C3 0x01060E07U + +#define GPIO_136_GPIO136 0x01061000U +#define GPIO_136_SCIRXDA 0x01061006U +#define GPIO_136_SD2_D4 0x01061007U + +#define GPIO_137_GPIO137 0x01061200U +#define GPIO_137_SCITXDB 0x01061206U +#define GPIO_137_SD2_C4 0x01061207U + +#define GPIO_138_GPIO138 0x01061400U +#define GPIO_138_SCIRXDB 0x01061406U + +#define GPIO_139_GPIO139 0x01061600U +#define GPIO_139_SCIRXDC 0x01061606U + +#define GPIO_140_GPIO140 0x01061800U +#define GPIO_140_SCITXDC 0x01061806U + +#define GPIO_141_GPIO141 0x01061A00U +#define GPIO_141_SCIRXDD 0x01061A06U + +#define GPIO_142_GPIO142 0x01061C00U +#define GPIO_142_SCITXDD 0x01061C06U + +#define GPIO_143_GPIO143 0x01061E00U + +#define GPIO_144_GPIO144 0x01080000U + +#define GPIO_145_GPIO145 0x01080200U +#define GPIO_145_EPWM1A 0x01080201U + +#define GPIO_146_GPIO146 0x01080400U +#define GPIO_146_EPWM1B 0x01080401U + +#define GPIO_147_GPIO147 0x01080600U +#define GPIO_147_EPWM2A 0x01080601U + +#define GPIO_148_GPIO148 0x01080800U +#define GPIO_148_EPWM2B 0x01080801U + +#define GPIO_149_GPIO149 0x01080A00U +#define GPIO_149_EPWM3A 0x01080A01U + +#define GPIO_150_GPIO150 0x01080C00U +#define GPIO_150_EPWM3B 0x01080C01U + +#define GPIO_151_GPIO151 0x01080E00U +#define GPIO_151_EPWM4A 0x01080E01U + +#define GPIO_152_GPIO152 0x01081000U +#define GPIO_152_EPWM4B 0x01081001U + +#define GPIO_153_GPIO153 0x01081200U +#define GPIO_153_EPWM5A 0x01081201U + +#define GPIO_154_GPIO154 0x01081400U +#define GPIO_154_EPWM5B 0x01081401U + +#define GPIO_155_GPIO155 0x01081600U +#define GPIO_155_EPWM6A 0x01081601U + +#define GPIO_156_GPIO156 0x01081800U +#define GPIO_156_EPWM6B 0x01081801U + +#define GPIO_157_GPIO157 0x01081A00U +#define GPIO_157_EPWM7A 0x01081A01U + +#define GPIO_158_GPIO158 0x01081C00U +#define GPIO_158_EPWM7B 0x01081C01U + +#define GPIO_159_GPIO159 0x01081E00U +#define GPIO_159_EPWM8A 0x01081E01U + +#define GPIO_160_GPIO160 0x01460000U +#define GPIO_160_EPWM8B 0x01460001U + +#define GPIO_161_GPIO161 0x01460200U +#define GPIO_161_EPWM9A 0x01460201U + +#define GPIO_162_GPIO162 0x01460400U +#define GPIO_162_EPWM9B 0x01460401U + +#define GPIO_163_GPIO163 0x01460600U +#define GPIO_163_EPWM10A 0x01460601U + +#define GPIO_164_GPIO164 0x01460800U +#define GPIO_164_EPWM10B 0x01460801U + +#define GPIO_165_GPIO165 0x01460A00U +#define GPIO_165_EPWM11A 0x01460A01U + +#define GPIO_166_GPIO166 0x01460C00U +#define GPIO_166_EPWM11B 0x01460C01U + +#define GPIO_167_GPIO167 0x01460E00U +#define GPIO_167_EPWM12A 0x01460E01U + +#define GPIO_168_GPIO168 0x01461000U +#define GPIO_168_EPWM12B 0x01461001U + +#endif // PIN_MAP_H diff --git a/gpio_bitfield_cpu1/device/driverlib/pin_map_legacy.h b/gpio_bitfield_cpu1/device/driverlib/pin_map_legacy.h new file mode 100644 index 0000000..c503ad4 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/pin_map_legacy.h @@ -0,0 +1,95 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Legacy definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_LEGACY_H__ +#define __PIN_MAP_LEGACY_H__ + + +#include "pin_map.h" + +//***************************************************************************** +// Legacy pinmuxing MACROS - Retained for portability across devices ONLY +// Not recommended for new users +//***************************************************************************** +#define GPIO_16_SD_D1 GPIO_16_SD1_D1 + +#define GPIO_17_SD_C1 GPIO_17_SD1_C1 + +#define GPIO_18_SD_D2 GPIO_18_SD1_D2 + +#define GPIO_19_SD_C2 GPIO_19_SD1_C2 + +#define GPIO_20_SD_D3 GPIO_20_SD1_D3 + +#define GPIO_21_SD_C3 GPIO_21_SD1_C3 + +#define GPIO_22_SD_D4 GPIO_22_SD1_D4 + +#define GPIO_23_SD_C4 GPIO_23_SD1_C4 + +#define GPIO_24_SD_D5 GPIO_24_SD2_D1 + +#define GPIO_25_SD_C5 GPIO_25_SD2_C1 + +#define GPIO_26_SD_D6 GPIO_26_SD2_D2 + +#define GPIO_27_SD_C6 GPIO_27_SD2_C2 + +#define GPIO_28_SD_D7 GPIO_28_SD2_D3 + +#define GPIO_29_SD_C7 GPIO_29_SD2_C3 + +#define GPIO_30_SD_D8 GPIO_30_SD2_D4 + +#define GPIO_31_SD_C8 GPIO_31_SD2_C4 + +#define GPIO_36_EM1WAIT1 GPIO_36_EM1WAIT + +#define GPIO_110_EM2WAIT1 GPIO_110_EM2WAIT + +#define GPIO_115_EM2CS0 GPIO_115_EM2CS0N + +#define GPIO_116_EM2CS2 GPIO_116_EM2CS2N + +#define GPIO_132_ODMSE0 GPIO_132_ODMSE1 + +#endif // __PIN_MAP_LEGACY_H__ diff --git a/gpio_bitfield_cpu1/device/driverlib/sci.c b/gpio_bitfield_cpu1/device/driverlib/sci.c new file mode 100644 index 0000000..dfd8e30 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/sci.c @@ -0,0 +1,421 @@ +//########################################################################### +// +// FILE: sci.c +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sci.h" + +//***************************************************************************** +// +// SCI_setConfig +// +//***************************************************************************** +void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, uint32_t config) +{ + uint32_t divider; + + // + // Check the arguments. + // Is the required baud rate greater than the maximum rate supported? + // + ASSERT(SCI_isBaseValid(base)); + ASSERT(baud != 0U); + ASSERT((baud * 16U) <= lspclkHz); + + // + // Stop the SCI. + // + SCI_disableModule(base); + + // + // Compute the baud rate divider. + // + divider = ((lspclkHz / (baud * 8U)) - 1U); + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; + + // + // Set parity, data length, and number of stop bits. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK)) | config); + + // + // Start the SCI. + // + SCI_enableModule(base); +} + +//***************************************************************************** +// +// SCI_writeCharArray +// +//***************************************************************************** +void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } + else + { + // + // FIFO is not enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } +} + +//***************************************************************************** +// +// SCI_readCharArray +// +//***************************************************************************** +void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } + else + { + // + // FIFO is not enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive buffer. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } +} + +//***************************************************************************** +// +// SCI_enableInterrupt +// +//***************************************************************************** +void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_disableInterrupt +// +//***************************************************************************** +void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SCI_getInterruptStatus(uint32_t base) +{ + uint32_t interruptStatus = 0; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the interrupt status. + // + if((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == SCI_CTL2_TXRDY) + { + interruptStatus |= SCI_INT_TXRDY; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXERROR) == SCI_RXST_RXERROR) + { + interruptStatus |= SCI_INT_RXERR; + } + if(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == SCI_RXST_RXRDY) || + ((HWREGH(base + SCI_O_RXST) & SCI_RXST_BRKDT) == SCI_RXST_BRKDT)) + { + interruptStatus |= SCI_INT_RXRDY_BRKDT; + } + if((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFINT) == SCI_FFTX_TXFFINT) + { + interruptStatus |= SCI_INT_TXFF; + } + if((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFINT) == SCI_FFRX_RXFFINT) + { + interruptStatus |= SCI_INT_RXFF; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_FE) == SCI_RXST_FE) + { + interruptStatus |= SCI_INT_FE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_OE) == SCI_RXST_OE) + { + interruptStatus |= SCI_INT_OE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_PE) == SCI_RXST_PE) + { + interruptStatus |= SCI_INT_PE; + } + + return(interruptStatus); +} + +//***************************************************************************** +// +// SCI_clearInterruptStatus +// +//***************************************************************************** +void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + if(((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) || + ((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) || + ((intFlags & SCI_INT_FE) == SCI_INT_FE) || + ((intFlags & SCI_INT_OE) == SCI_INT_OE) || + ((intFlags & SCI_INT_PE) == SCI_INT_PE)) + { + SCI_performSoftwareReset(base); + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFINTCLR; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR; + } +} + +//***************************************************************************** +// +// SCI_setBaud +// +//***************************************************************************** +void SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud) +{ + uint32_t divider; + + // + // Compute the baud rate divider {ROUND TO NEAREST INTEGER} + // + divider = ((float)((float)lspclkHz / ((float)baud * 8.0F)) - 1.0F) + 0.5F; + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; +} + +//***************************************************************************** +// +// SCI_setWakeFlag +// +//***************************************************************************** +void SCI_setWakeFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the TX wake flag bit to indicate + // that the next frame is an address frame. + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_TXWAKE; +} diff --git a/gpio_bitfield_cpu1/device/driverlib/sci.h b/gpio_bitfield_cpu1/device/driverlib/sci.h new file mode 100644 index 0000000..454ee12 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/sci.h @@ -0,0 +1,1646 @@ +//########################################################################### +// +// FILE: sci.h +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SCI_H +#define SCI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sci_api SCI +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_sci.h" +#include "inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and +// SCI_clearInterruptStatus as the intFlags parameter, and returned from +// SCI_getInterruptStatus. +// +//***************************************************************************** +#define SCI_INT_RXERR 0x01U //!< RXERR interrupt +#define SCI_INT_RXRDY_BRKDT 0x02U //!< RXRDY interrupt +#define SCI_INT_TXRDY 0x04U //!< TXRDY interrupt +#define SCI_INT_TXFF 0x08U //!< TX FIFO level interrupt +#define SCI_INT_RXFF 0x10U //!< RX FIFO level interrupt +#define SCI_INT_FE 0x20U //!< Frame Error +#define SCI_INT_OE 0x40U //!< Overrun Error +#define SCI_INT_PE 0x80U //!< Parity Error + +//***************************************************************************** +// +// Values that can be passed to SCI_setConfig as the config parameter +// and returned by SCI_getConfig in the config parameter. +// Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to +// SCI_setParityMode as the parity parameter, and are returned by +// SCI_getParityMode. +// +//***************************************************************************** +#define SCI_CONFIG_WLEN_MASK 0x0007U //!< Mask for extracting word length +#define SCI_CONFIG_WLEN_8 0x0007U //!< 8 bit data +#define SCI_CONFIG_WLEN_7 0x0006U //!< 7 bit data +#define SCI_CONFIG_WLEN_6 0x0005U //!< 6 bit data +#define SCI_CONFIG_WLEN_5 0x0004U //!< 5 bit data +#define SCI_CONFIG_WLEN_4 0x0003U //!< 4 bit data +#define SCI_CONFIG_WLEN_3 0x0002U //!< 3 bit data +#define SCI_CONFIG_WLEN_2 0x0001U //!< 2 bit data +#define SCI_CONFIG_WLEN_1 0x0000U //!< 1 bit data +#define SCI_CONFIG_STOP_MASK 0x0080U //!< Mask for extracting stop bits +#define SCI_CONFIG_STOP_ONE 0x0000U //!< One stop bit +#define SCI_CONFIG_STOP_TWO 0x0080U //!< Two stop bits +#define SCI_CONFIG_PAR_MASK 0x0060U //!< Parity Mask + +//***************************************************************************** +// +//! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to +//! describe the parity of the SCI communication. +// +//***************************************************************************** +typedef enum +{ + SCI_CONFIG_PAR_NONE = 0x0000U, //!< No parity + SCI_CONFIG_PAR_EVEN = 0x0060U, //!< Even parity + SCI_CONFIG_PAR_ODD = 0x0020U //!< Odd parity +} SCI_ParityType; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel +//! parameter and returned by SCI_getFIFOInteruptLevel() and +//! SCI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_TX0 = 0x0000U, //!< Transmit interrupt empty + SCI_FIFO_TX1 = 0x0001U, //!< Transmit interrupt 1/16 full + SCI_FIFO_TX2 = 0x0002U, //!< Transmit interrupt 2/16 full + SCI_FIFO_TX3 = 0x0003U, //!< Transmit interrupt 3/16 full + SCI_FIFO_TX4 = 0x0004U, //!< Transmit interrupt 4/16 full + SCI_FIFO_TX5 = 0x0005U, //!< Transmit interrupt 5/16 full + SCI_FIFO_TX6 = 0x0006U, //!< Transmit interrupt 6/16 full + SCI_FIFO_TX7 = 0x0007U, //!< Transmit interrupt 7/16 full + SCI_FIFO_TX8 = 0x0008U, //!< Transmit interrupt 8/16 full + SCI_FIFO_TX9 = 0x0009U, //!< Transmit interrupt 9/16 full + SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full + SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full + SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full + SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full + SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full + SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full + SCI_FIFO_TX16 = 0x0010U //!< Transmit interrupt full +} SCI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel +//! parameter and returned by SCI_getFIFOInterruptLevel() and +//! SCI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_RX0 = 0x0000U, //!< Receive interrupt empty + SCI_FIFO_RX1 = 0x0001U, //!< Receive interrupt 1/16 full + SCI_FIFO_RX2 = 0x0002U, //!< Receive interrupt 2/16 full + SCI_FIFO_RX3 = 0x0003U, //!< Receive interrupt 3/16 full + SCI_FIFO_RX4 = 0x0004U, //!< Receive interrupt 4/16 full + SCI_FIFO_RX5 = 0x0005U, //!< Receive interrupt 5/16 full + SCI_FIFO_RX6 = 0x0006U, //!< Receive interrupt 6/16 full + SCI_FIFO_RX7 = 0x0007U, //!< Receive interrupt 7/16 full + SCI_FIFO_RX8 = 0x0008U, //!< Receive interrupt 8/16 full + SCI_FIFO_RX9 = 0x0009U, //!< Receive interrupt 9/16 full + SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full + SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full + SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full + SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full + SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full + SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full + SCI_FIFO_RX16 = 0x0010U //!< Receive interrupt full +} SCI_RxFIFOLevel; + +//***************************************************************************** +// +// Values returned from SCI_getRxStatus(). These correspond to the different +// bits and flags of the SCIRXST register. +// +//***************************************************************************** +#define SCI_RXSTATUS_WAKE 0x0002U //!< Receiver wake up detect +#define SCI_RXSTATUS_PARITY 0x0004U //!< Parity error +#define SCI_RXSTATUS_OVERRUN 0x0008U //!< Overrun error +#define SCI_RXSTATUS_FRAMING 0x0010U //!< Framing error +#define SCI_RXSTATUS_BREAK 0x0020U //!< Break detect +#define SCI_RXSTATUS_READY 0x0040U //!< Receiver ready +#define SCI_RXSTATUS_ERROR 0x0080U //!< Receiver error + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a SCI base address. +//! +//! \param base is the base address of the SCI port. +//! +//! This function determines if a SCI port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SCI_isBaseValid(uint32_t base) +{ + return( + (base == SCIA_BASE) || + (base == SCIB_BASE) || + (base == SCIC_BASE) || + (base == SCID_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param base is the base address of the SCI port. +//! \param parity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e parity parameter must be one of the following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setParityMode(uint32_t base, SCI_ParityType parity) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the parity mode. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK)) | (uint16_t)parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param base is the base address of the SCI port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of the +//! following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +// +//***************************************************************************** +static inline SCI_ParityType +SCI_getParityMode(uint32_t base) +{ + uint16_t parity; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current parity setting. + // + parity = (HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK)); + + return((SCI_ParityType)parity); +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to address-bit mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to address-bit mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setAddrMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to idle-line mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to idle-line protocol. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setIdleMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Locks Autobaud. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs an autobaud lock for the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_lockAutobaud(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Prime the baud register + // + HWREGH(base + SCI_O_HBAUD) = 0x0U; + HWREGH(base + SCI_O_LBAUD) = 0x1U; + + // + // Prepare for autobaud detection. + // Set the CDC bit to enable autobaud detection and clear the ABD bit. + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_CDC; + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + + // + // Wait until we correctly read an 'A' or 'a' and lock + // + while((HWREGH(base + SCI_O_FFCT) & SCI_FFCT_ABD) != SCI_FFCT_ABD) + { + } + + // + // After autobaud lock, clear the ABD and CDC bits + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + HWREGH(base + SCI_O_FFCT) &= ~SCI_FFCT_CDC; +} + +//***************************************************************************** +// +//! Sets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as one of +//! the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or +//! \b SCI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as one of +//! the following +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel, + SCI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SCI_O_FFTX) = (HWREGH(base + SCI_O_FFTX) & + (~SCI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SCI_O_FFRX) = (HWREGH(base + SCI_O_FFRX) & + (~SCI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is a pointer to storage for the transmit FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel, + SCI_RxFIFOLevel *rxLevel) +{ + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SCI_TxFIFOLevel)(HWREGH(base + SCI_O_FFTX) & + SCI_FFTX_TXFFIL_M); + *rxLevel = (SCI_RxFIFOLevel)(HWREGH(base + SCI_O_FFRX) & + SCI_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Gets the current configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is a pointer to storage for the baud rate. +//! \param config is a pointer to storage for the data format. +//! +//! The baud rate and data format for the SCI is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e config is enumerated the same as the \e config parameter of +//! SCI_setConfig(). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud, + uint32_t *config) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Compute the baud rate. + // + *baud = lspclkHz / + ((1U + (((uint32_t)HWREGH(base + SCI_O_HBAUD) << 8U) | + HWREGH(base + SCI_O_LBAUD))) * 8U); + + // + // Get the parity, data length, and number of stop bits. + // + *config = (uint32_t)HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and +//! RXENA bits which enables transmit and receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX, TX, and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_RXENA | + SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the +//! data has been sent before disable the module during transmission. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~(SCI_FFTX_SCIFFENA); + + // + // Disable the SCI. + // + HWREGH(base + SCI_O_CTL1) &= ~(SCI_CTL1_TXENA | SCI_CTL1_RXENA); +} + +//***************************************************************************** +// +//! Enables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA bit +//! which enables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable TX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the TXENA bit +//! which disables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable TX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_TXENA; +} + +//***************************************************************************** +// +//! Enables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the RXENA bit +//! which enables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_RXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the RXENA bit +//! which disables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable RX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXENA; +} + +//***************************************************************************** +// +//! Enables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the sleep mode in SCI by setting the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set sleep bit + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Disables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the sleep mode in SCI by clearing the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear sleep bit + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions enables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIFFENA | SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions disables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Determines if the FIFO enhancement is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not the FIFO enhancement +//! is enabled. +//! +//! \return Returns \b true if the FIFO enhancement is enabled or \b false +//! if the FIFO enhancement is disabled. +// +//***************************************************************************** +static inline bool +SCI_isFIFOEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return true if the FIFO is enabled and false if it is disabled. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_SCIFFENA) == + SCI_FFTX_SCIFFENA) ? true : false); +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the receive FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the transmit FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the SCI Transmit and Receive Channels +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets transmit and receive channels in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetChannels(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the Tx and Rx Channels + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive buffer when the +//! FIFO enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive buffer. +//! +//! \return Returns \b true if there is data in the receive buffer or \b false +//! if there is no data in the receive buffer. +// +//***************************************************************************** +static inline bool +SCI_isDataAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of characters with FIFO disabled. + // + return(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == + SCI_RXST_RXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit buffer when the FIFO +//! enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit buffer when not using the FIFO enhancement. +//! +//! \return Returns \b true if there is space available in the transmit buffer +//! or \b false if there is no space available in the transmit buffer. +// +//***************************************************************************** +static inline bool +SCI_isSpaceAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of space. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == + SCI_CTL2_TXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3 +//! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16 +// +//***************************************************************************** +static inline SCI_TxFIFOLevel +SCI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_TxFIFOLevel)((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) >> + SCI_FFTX_TXFFST_S)); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3 +//! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16 +// +//***************************************************************************** +static inline SCI_RxFIFOLevel +SCI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_RxFIFOLevel)((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFST_M) >> + SCI_FFRX_RXFFST_S)); +} + +//***************************************************************************** +// +//! Determines whether the SCI transmitter is busy or not. +//! +//! \param base is the base address of the SCI port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware when the FIFO is not enabled. When the FIFO is +//! enabled, this function allows the caller to determine whether there is any +//! data in the FIFO. +//! +//! Without the FIFO enabled, if \b false is returned, the transmit buffer and +//! shift registers are empty and the transmitter is not busy. With the FIFO +//! enabled, if \b false is returned, the FIFO is empty. This does not +//! necessarily mean that the transmitter is not busy. The empty FIFO does not +//! reflect the status of the transmitter shift register. The FIFO may be empty +//! while the transmitter is still transmitting data. +//! +//! \return Returns \b true if the SCI is transmitting or \b false if +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SCI_isTransmitterBusy(uint32_t base) +{ + // + // Check the argument. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // With FIFO enhancement, determine if the SCI is busy. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) != + 0U) ? true : false); + } + else + { + // + // Without FIFO enhancement, determine if the SCI is busy. + // Check if the transmit buffer and shift register empty. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXEMPTY) == + SCI_CTL2_TXEMPTY) ? false : true); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. \e data is a uint16_t but +//! only 8 bits are written to the SCI port. SCI only transmits 8 bit +//! characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! before returning. \e data is a uint16_t but only 8 bits are written to the +//! SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Writes the character \e data to the transmit buffer for the specified port. +//! This function does not block and only writes to the transmit buffer. +//! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus() +//! to determine if the transmit buffer or FIFO have space available. +//! \e data is a uint16_t but only 8 bits are written to the SCI port. SCI +//! only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets current receiver status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns the current receiver status flags. The returned +//! error flags are equivalent to the error bits returned via the previous +//! reading or receiving of a character with the exception that the overrun +//! error is set immediately the overrun occurs rather than when a character +//! is next read. +//! +//! \return Returns a bitwise OR combination of the receiver status flags, +//! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN, +//! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY, +//! and \b SCI_RXSTATUS_ERROR. +// +//***************************************************************************** +static inline uint16_t +SCI_getRxStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current value of the receive status register. + // + return(HWREGH(base + SCI_O_RXST)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. Returns immediately in case of Error. +//! +//! \return Returns the character read from the specified port as \e uint16_t +//! or 0x0 in case of Error. The application must use +//! SCI_getRxStatus() API to check if some error occurred before +//! consuming the data +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + // + //If there is any error return + // + if((SCI_getRxStatus(base) & SCI_RXSTATUS_ERROR) != 0U) + { + return(0U); + } + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. If there +//! is no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port as \e uint16_t. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. This +//! function does not block and only reads the receive buffer. The user should +//! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if +//! the receive buffer or FIFO have data available. +//! +//! \return Returns \e uin16_t which is read from the receive buffer. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Performs a software reset of the SCI and Clears all reported receiver +//! status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs a software reset of the SCI port. It affects the +//! operating flags of the SCI, but it neither affects the configuration bits +//! nor restores the reset values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_performSoftwareReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // To clear all errors a sw reset of the module is required + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SWRESET; + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SWRESET; +} + +//***************************************************************************** +// +//! Enables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the loop back test mode where the Tx pin is internally connected +//! to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the loop back mode. + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Disables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the loop back test mode where the Tx pin is no longer internally +//! connected to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the loop back mode. + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Get the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the receive FIFO overflow flag status. +//! +//! \return Returns \b true if overflow has occurred, else returned \b false if +//! an overflow hasn't occurred. +// +//***************************************************************************** +static inline bool +SCI_getOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current FIFO overflow status + // + return((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFOVF) == SCI_FFRX_RXFFOVF); +} + +//***************************************************************************** +// +//! Clear the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions clears the receive FIFO overflow flag status. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_clearOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the current FIFO overflow status + // + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFOVRCLR; +} + +//***************************************************************************** +// +//! Sets the configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! \param config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the SCI for operation in the specified data +//! format. The baud rate is provided in the \e baud parameter and the data +//! format in the \e config parameter. +//! +//! The \e config parameter is the bitwise OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b SCI_CONFIG_WLEN_8, +//! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5, +//! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and +//! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte +//! (respectively). +//! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, +//! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity +//! bit, odd parity bit respectively). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! A baud rate divider (BRR) is used in this function to calculate the +//! baud rate. The value of BRR is calculated in float and type casted as int +//! to be fed in the \b SCIHBAUD and \b SCILBAUD registers. This conversion +//! brings an error in the calculated baud rate and the requested. Error will +//! be significant when operating at higher baud rates. The error is due to +//! lower BRR integer value granularity at higher baud rates. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, + uint32_t config); + +//***************************************************************************** +// +//! Waits to send an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be transmitted. +//! It is pointer to the array of characters to be transmitted. +//! \param length is the length of the array, or number of characters in the +//! array to be transmitted. +//! +//! Sends the number of characters specified by \e length, starting at the +//! address \e array, out of the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! and \e length number of characters are transmitted before returning. +//! \e array is a pointer to uint16_ts but only the least significant 8 bits +//! are written to the SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length); + +//***************************************************************************** +// +//! Waits to receive an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be received. +//! It is a pointer to the array of characters to be received. +//! \param length is the length of the array, or number of characters in the +//! array to be received. +//! +//! Receives an array of characters from the receive buffer for the specified +//! port, and stores them as an array of characters starting at address +//! \e array. This function waits until the \e length number of characters are +//! received before returning. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length); + +//***************************************************************************** +// +//! Enables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter is the bitwise OR of any of the following: +//! +//! - \b SCI_INT_RXERR - RXERR Interrupt +//! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt +//! - \b SCI_INT_TXRDY - TXRDY Interrupt +//! - \b SCI_INT_TXFF - TX FIFO Level Interrupt +//! - \b SCI_INT_RXFF - RX FIFO Level Interrupt +//! - \b SCI_INT_FE - Frame Error +//! - \b SCI_INT_OE - Overrun Error +//! - \b SCI_INT_PE - Parity Error +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the SCI port. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SCI_enableInterrupt(). +// +//***************************************************************************** +extern uint32_t +SCI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SCI interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Sets SCI Baud rate. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! +//! This function configures the SCI for operation in the specified baud rate +//! The baud rate is provided in the \e baud parameter. +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock() +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud); + +//***************************************************************************** +// +//! Sets the SCI TXWAKE flag +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the TXWAKE flag bit to indicate that the next frame +//! is an address frame. +//! TXWAKE bit controls selection of data-transmit feature based on +//! which mode is selected from idle-line and address-bit. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setWakeFlag(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SCI_H diff --git a/gpio_bitfield_cpu1/device/driverlib/sdfm.c b/gpio_bitfield_cpu1/device/driverlib/sdfm.c new file mode 100644 index 0000000..41bc605 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/sdfm.c @@ -0,0 +1,188 @@ +//########################################################################### +// +// FILE: sdfm.c +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sdfm.h" + +//***************************************************************************** +// +// Defines for filter configurations. Not intended for use by application code. +// +//***************************************************************************** +// +// Get filter oversampling ratio +// +#define SDFM_GET_OSR(C) ((C) >> 8U) + +// +// Maximum acceptable comparator filter oversampling ratio +// +#define SDFM_MAX_COMP_FILTER_OSR 31U + +// +// Maximum acceptable data filter oversampling ratio +// +#define SDFM_MAX_DATA_FILTER_OSR 255U + +// +// Get the filter type +// +#define SDFM_GET_FILTER_TYPE(C) ((C) & 0x30U) + +// +// Get the filter number +// +#define SDFM_GET_FILTER_NUMBER(C) ((C) & 0x3U) + + +// +// Get data shift value +// +#define SDFM_GET_SHIFT_VALUE(C) (((C) >> 2U) & 0x1FU) + +//***************************************************************************** +// +// SDFM_configComparator +// +//***************************************************************************** +void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_COMP_FILTER_OSR) + { + ratio = SDFM_MAX_COMP_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setComparatorFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setCompFilterOverSamplingRatio(base, filter, ratio); + + // + // Set the comparator high threshold value + // + SDFM_setCompFilterHighThreshold(base, filter, + SDFM_GET_HIGH_THRESHOLD(config2)); + + // + // Set the comparator low threshold value + // + SDFM_setCompFilterLowThreshold(base, filter, + SDFM_GET_LOW_THRESHOLD(config2)); + +} + +//***************************************************************************** +// +// SDFM_configDataFilter +// +//***************************************************************************** +void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_DATA_FILTER_OSR) + { + ratio = SDFM_MAX_DATA_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setFilterOverSamplingRatio(base, filter, ratio); + + // + // If filter switch on + // + if((config2 & SDFM_FILTER_ENABLE) == SDFM_FILTER_ENABLE) + { + SDFM_enableFilter(base, filter); + } + else + { + SDFM_disableFilter(base, filter); + } + + // + // Set output data format + // + SDFM_setOutputDataFormat(base, filter, + (SDFM_OutputDataFormat)(config2 & 0x1U)); + + // + // Set the shift value if data is in 16-bit 2's complement format + // + if((config2 & 0x1U) == (uint16_t)(SDFM_DATA_FORMAT_16_BIT)) + { + SDFM_setDataShiftValue(base, filter, SDFM_GET_SHIFT_VALUE(config2)); + } +} + + diff --git a/gpio_bitfield_cpu1/device/driverlib/sdfm.h b/gpio_bitfield_cpu1/device/driverlib/sdfm.h new file mode 100644 index 0000000..afbdfb7 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/sdfm.h @@ -0,0 +1,1178 @@ +//########################################################################### +// +// FILE: sdfm.h +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef SDFM_H +#define SDFM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sdfm_api SDFM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_types.h" +#include "inc/hw_sdfm.h" +#include "inc/hw_memmap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//! Macro to get the low threshold +//! +#define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C)) + +//! Macro to get the high threshold +//! +#define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U)) + + +//! Macro to convert comparator over sampling ratio to acceptable bit location +//! +#define SDFM_SET_OSR(X) (((X) - 1U) << 8U) +//! Macro to convert the data shift bit values to acceptable bit location +//! +#define SDFM_SHIFT_VALUE(X) ((X) << 2U) + +//! Macro to combine high threshold and low threshold values +//! +#define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L)) + +//! Macro to set the FIFO level to acceptable bit location +//! +#define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U) + +//! Macro to set and enable the zero cross threshold value. +//! +#define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X)) + +//! Macros to enable or disable filter. +//! +#define SDFM_FILTER_DISABLE 0x0U +#define SDFM_FILTER_ENABLE 0x2U + +//***************************************************************************** +// +//! Values that can be returned from SDFM_getThresholdStatus() +// +//***************************************************************************** +typedef enum +{ + SDFM_OUTPUT_WITHIN_THRESHOLD = 0, //!< SDFM output is within threshold + SDFM_OUTPUT_ABOVE_THRESHOLD = 1, //!< SDFM output is above threshold + SDFM_OUTPUT_BELOW_THRESHOLD = 2 //!< SDFM output is below threshold +} SDFM_OutputThresholdStatus; + +//***************************************************************************** +// +//! Values that can be passed to all functions as the \e filterNumber +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SDFM_FILTER_1 = 0, //!< Digital filter 1 + SDFM_FILTER_2 = 1, //!< Digital filter 2 + SDFM_FILTER_3 = 2, //!< Digital filter 3 + SDFM_FILTER_4 = 3 //!< Digital filter 4 +} SDFM_FilterNumber; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setFilterType(), +//! SDFM_setComparatorFilterType() as the \e filterType parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital filter with SincFast structure. + SDFM_FILTER_SINC_FAST = 0x00, + //! Digital filter with Sinc1 structure + SDFM_FILTER_SINC_1 = 0x10, + //! Digital filter with Sinc3 structure. + SDFM_FILTER_SINC_2 = 0x20, + //! Digital filter with Sinc4 structure. + SDFM_FILTER_SINC_3 = 0x30 +} SDFM_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setupModulatorClock(),as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Modulator clock is identical to the data rate + SDFM_MODULATOR_CLK_EQUAL_DATA_RATE = 0, + //! Modulator clock is half the data rate + SDFM_MODULATOR_CLK_HALF_DATA_RATE = 1, + //! Modulator clock is off. Data is Manchester coded. + SDFM_MODULATOR_CLK_OFF = 2, + //! Modulator clock is double the data rate. + SDFM_MODULATOR_CLK_DOUBLE_DATA_RATE = 3 +} SDFM_ModulatorClockMode; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setOutputDataFormat(),as the +//! \e dataFormat parameter. +// +//***************************************************************************** +typedef enum +{ + //! Filter output is in 16 bits 2's complement format. + SDFM_DATA_FORMAT_16_BIT = 0, + //! Filter output is in 32 bits 2's complement format. + SDFM_DATA_FORMAT_32_BIT = 1 +} SDFM_OutputDataFormat; + +//***************************************************************************** +// +// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt +// as intFlags parameter +// +//***************************************************************************** +//! Interrupt is generated if Modulator fails. +//! +#define SDFM_MODULATOR_FAILURE_INTERRUPT 0x200U +//! Interrupt on Comparator low-level threshold. +//! +#define SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT 0x40U +//! Interrupt on Comparator high-level threshold. +//! +#define SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT 0x20U +//! Interrupt on Acknowledge flag +//! +#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to SDFM_clearInterruptFlag flags parameter +// +//***************************************************************************** +//! Main interrupt flag +//! +#define SDFM_MAIN_INTERRUPT_FLAG 0x80000000U +//! Filter 1 high -level threshold flag +//! +#define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG 0x1U +//! Filter 1 low -level threshold flag +//! +#define SDFM_FILTER_1_LOW_THRESHOLD_FLAG 0x2U +//! Filter 2 high -level threshold flag +//! +#define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG 0x4U +//! Filter 2 low -level threshold flag +//! +#define SDFM_FILTER_2_LOW_THRESHOLD_FLAG 0x8U +//! Filter 3 high -level threshold flag +//! +#define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG 0x10U +//! Filter 3 low -level threshold flag +//! +#define SDFM_FILTER_3_LOW_THRESHOLD_FLAG 0x20U +//! Filter 4 high -level threshold flag +//! +#define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG 0x40U +//! Filter 4 low -level threshold flag +//! +#define SDFM_FILTER_4_LOW_THRESHOLD_FLAG 0x80U +//! Filter 1 modulator failed flag +//! +#define SDFM_FILTER_1_MOD_FAILED_FLAG 0x100U +//! Filter 2 modulator failed flag +//! +#define SDFM_FILTER_2_MOD_FAILED_FLAG 0x200U +//! Filter 3 modulator failed flag +//! +#define SDFM_FILTER_3_MOD_FAILED_FLAG 0x400U +//! Filter 4 modulator failed flag +//! +#define SDFM_FILTER_4_MOD_FAILED_FLAG 0x800U +//! Filter 1 new data flag +//! +#define SDFM_FILTER_1_NEW_DATA_FLAG 0x1000U +//! Filter 2 new data flag +//! +#define SDFM_FILTER_2_NEW_DATA_FLAG 0x2000U +//! Filter 3 new data flag +//! +#define SDFM_FILTER_3_NEW_DATA_FLAG 0x4000U +//! Filter 4 new data flag +//! +#define SDFM_FILTER_4_NEW_DATA_FLAG 0x8000U + +//***************************************************************************** +// +//! \internal +//! Checks SDFM base address. +//! +//! \param base specifies the SDFM module base address. +//! +//! This function determines if SDFM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SDFM_isBaseValid(uint32_t base) +{ + return( + (base == SDFM1_BASE) || + (base == SDFM2_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables data filter to be reset by an external source (PWM +//! compare output). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables data filter from being reset by an external source +//! (PWM compare output). +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Enable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables the filter specified by the \e filterNumber variable. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables the filter specified by the \e filterNumber +//! variable. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Set filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the filter type or structure. +//! +//! This function sets the filter type or structure to be used as specified by +//! filterType for the selected filter number as specified by filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SST bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_SST_M)) | + ((uint16_t)filterType << 6U); + EDIS; +} + +//***************************************************************************** +// +//! Set data filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the data filter over sampling ratio. +//! +//! This function sets the filter oversampling ratio for the filter specified +//! by the filterNumber variable.Valid values for the variable +//! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio +//! will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 256U); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DOSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_DOSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Set modulator clock mode. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param clockMode is the modulator clock mode. +//! +//! This function sets the modulator clock mode specified by clockMode +//! for the filter specified by filterNumber. +//! +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_ModulatorClockMode clockMode) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCTLPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to MOD bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCTLPARM1_MOD_M)) | + (uint16_t)clockMode; + + EDIS; +} + +//***************************************************************************** +// +//! Set the output data format +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param dataFormat is the output data format. +//! +//! This function sets the output data format for the filter specified by +//! filterNumber. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_OutputDataFormat dataFormat) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DR bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_DR)) | + ((uint16_t)dataFormat << 10U); + EDIS; +} + +//***************************************************************************** +// +//! Set data shift value. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param shiftValue is the data shift value. +//! +//! This function sets the shift value for the 16 bit 2's complement data +//! format. The valid maximum value for shiftValue is 31. +//! +//! \b Note: Use this function with 16 bit 2's complement data format only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t shiftValue) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(shiftValue < 32U); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SH bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_SH_M)) | + (shiftValue << SDFM_SDDPARM1_SH_S); + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output high-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param highThreshold is the high-level threshold. +//! +//! This function sets the unsigned high-level threshold value for the +//! Comparator filter output. If the output value of the filter exceeds +//! highThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t highThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(highThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPH1 + ((uint32_t)filterNumber * 16U); + + // + // Write to HLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPH1_HLT_M) | highThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output low-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param lowThreshold is the low-level threshold. +//! +//! This function sets the unsigned low-level threshold value for the +//! Comparator filter output. If the output value of the filter gets below +//! lowThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t lowThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(lowThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPL1 + ((uint32_t)filterNumber * 16U); + + // + // Write to LLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPL1_LLT_M) | lowThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Enable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function enables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter specified +//! by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, Modulator failure + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) |= + (intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) |= SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Disable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function disables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter +//! specified by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, modulator failure interrupts + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) &= + ~(intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) &= ~SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Set the comparator filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the comparator filter type or structure. +//! +//! This function sets the Comparator filter type or structure to be used as +//! specified by filterType for the selected filter number as specified by +//! filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to CS1_CS0 bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_CS1_CS0_M)) | + ((uint16_t)filterType << 3U); + EDIS; +} + +//***************************************************************************** +// +//! Set Comparator filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the comparator filter over sampling ration. +//! +//! This function sets the comparator filter oversampling ratio for the filter +//! specified by the filterNumber.Valid values for the variable +//! overSamplingRatio are 0 to 31 inclusive. +//! The actual oversampling ratio will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setCompFilterOverSamplingRatio(uint32_t base, + SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 32U); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to COSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_COSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Get the filter data output. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the latest data filter output. Depending on the +//! filter data output format selected, the valid value will be the lower 16 +//! bits or the whole 32 bits of the returned value. +//! +//! \return Returns the latest data filter output. +//***************************************************************************** +static inline uint32_t +SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDDATA bits + // + return(HWREG(base + SDFM_O_SDDATA1 + ((uint32_t)filterNumber * 16U))); +} + +//***************************************************************************** +// +//! Get the Comparator threshold status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Comparator output threshold status for the given +//! filterNumber. +//! +//! \return Returns the following status flags. +//! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the +//! specified threshold. +//! - \b SDFM_OUTPUT_ABOVE_THRESHOLD if the output is above the high +//! threshold +//! - \b SDFM_OUTPUT_BELOW_THRESHOLD if the output is below the low +//! threshold. +//! +//***************************************************************************** +static inline SDFM_OutputThresholdStatus +SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG high/low threshold bits + // + return((SDFM_OutputThresholdStatus)((HWREG(base + SDFM_O_SDIFLG) >> + (2U * (uint16_t)filterNumber)) & 0x3U)); +} + +//***************************************************************************** +// +//! Get the Modulator status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Modulator status. +//! +//! \return Returns true if the Modulator is operating normally +//! Returns false if the Modulator has failed +//! +//***************************************************************************** +static inline bool +SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MF1, MF2, MF3 OR MF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 8U)) & + 0x1U) != 0x1U); +} + +//***************************************************************************** +// +//! Check if new Filter data is available. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns new filter data status. +//! +//! \return Returns \b true if new filter data is available +//! Returns \b false if no new filter data is available +//! +//***************************************************************************** +static inline bool +SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG AF1, AF2, AF3 OR AF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 12U)) & + 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Get pending interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function returns any pending interrupt status. +//! +//! \return Returns \b true if there is a pending interrupt. +//! Returns \b false if no interrupt is pending. +//! +//***************************************************************************** +static inline bool +SDFM_getIsrStatus(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MIF + // + return((HWREG(base + SDFM_O_SDIFLG) >> 31U) == 0x1U); +} + +//***************************************************************************** +// +//! Clear pending flags. +//! +//! \param base is the base address of the SDFM module +//! \param flag is the SDFM status +//! +//! This function clears the specified pending interrupt flag. +//! Valid values are +//! SDFM_MAIN_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG, +//! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG, +//! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG, +//! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG, +//! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_4_LOW_THRESHOLD_FLAG or any combination of the above +//! flags. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_clearInterruptFlag(uint32_t base, uint32_t flag) +{ + ASSERT(SDFM_isBaseValid(base)); + ASSERT((flag & 0x8000FFFFU) == flag); + + // + // Write to SDIFLGCLR register + // + HWREG(base + SDFM_O_SDIFLGCLR) |= flag; +} + +//***************************************************************************** +// +//! Enable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) |= SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) &= ~SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Enable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) |= SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) &= ~SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Configures SDFM comparator for filter config & threshold values +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio. +//! \param config2 is high-level and low-level threshold values. +//! +//! This function configures the comparator filter for filter config and +//! threshold values based on provided inputs. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] filter number +//! - config1.[7:4] filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location. +//! For example the value +//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16)) +//! will select Filter 1, SINC 2 type with an oversampling ratio of 16. +//! +//! The config2 parameter is the logical OR of the filter high and low +//! threshold values. +//! The bit definitions for config2 are as follow: +//! - config2.[15:0] low threshold +//! - config2.[31:16] high threshold +//! The upper 16 bits define the high threshold and the lower +//! 16 bits define the low threshold. +//! SDFM_THRESHOLD(H,L) can be used to combine the high and low thresholds. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2); + +//***************************************************************************** +// +//! Configure SDFM data filter +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio +//! configuration. +//! \param config2 is filter switch, data representation and data shift values +//! configuration. +//! +//! This function configures the data filter based on configurations +//! config1 and config2. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] Filter number +//! - config1.[7:4] Filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio , which ranges [1,256] inclusive , in the appropriate bit location +//! for config1. For example the value +//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64)) +//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64. +//! +//! The config2 parameter is the logical OR of data representation, filter +//! switch, and data shift values +//! The bit definitions for config2 are as follow: +//! - config2.[0] Data representation +//! - config2.[1] Filter switch +//! - config2.[15:2] Shift values +//! Valid values for data representation are given in SDFM_OutputDataFormat +//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the +//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value +//! of the data shift value,which ranges [0,31] inclusive, in the appropriate +//! bit location for config2. +//! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data +//! representation format. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif +#endif // SDFM_H diff --git a/gpio_bitfield_cpu1/device/driverlib/spi.c b/gpio_bitfield_cpu1/device/driverlib/spi.c new file mode 100644 index 0000000..b077369 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/spi.c @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: spi.c +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "spi.h" + +//***************************************************************************** +// +// SPI_setConfig +// +//***************************************************************************** +void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth) +{ + uint16_t regValue; + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + ASSERT((dataWidth >= 1U) && (dataWidth <= 16U)); + ASSERT((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPISWRESET) == 0U); + + // + // Set polarity and data width. + // + regValue = (((uint16_t)protocol << 6U) & SPI_CCR_CLKPOLARITY) | + (dataWidth - 1U); + + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & + ~(SPI_CCR_CLKPOLARITY | SPI_CCR_SPICHAR_M)) | + regValue; + + // + // Set the mode and phase. + // + regValue = (uint16_t)mode | (((uint16_t)protocol << 2U) & + SPI_CTL_CLK_PHASE); + + HWREGH(base + SPI_O_CTL) = (HWREGH(base + SPI_O_CTL) & + ~(SPI_CTL_TALK | SPI_CTL_CONTROLLER_PERIPHERAL | + SPI_CTL_CLK_PHASE)) | regValue; + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_setBaudRate +// +//***************************************************************************** +void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate) +{ + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_enableInterrupt +// +//***************************************************************************** +void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_SPIINTENA; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_OVERRUNINTENA; + } + + // + // Enable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFIENA; + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SPI_disableInterrupt +// +//***************************************************************************** +void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_SPIINTENA); + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_OVERRUNINTENA); + } + + // + // Disable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_TXFFIENA); + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) &= ~(SPI_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// SPI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SPI_getInterruptStatus(uint32_t base) +{ + uint32_t temp = 0; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + if((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) != 0U) + { + temp |= SPI_INT_RX_DATA_TX_EMPTY; + } + + if((HWREGH(base + SPI_O_STS) & SPI_STS_OVERRUN_FLAG) != 0U) + { + temp |= SPI_INT_RX_OVERRUN; + } + + if((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFINT) != 0U) + { + temp |= SPI_INT_TXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFINT) != 0U) + { + temp |= SPI_INT_RXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFOVF) != 0U) + { + temp |= SPI_INT_RXFF_OVERFLOW; + } + + return(temp); +} + +//***************************************************************************** +// +// SPI_clearInterruptStatus +// +//***************************************************************************** +void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the specified non-FIFO interrupt sources. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_STS) |= SPI_STS_OVERRUN_FLAG; + } + + // + // Clear the specified FIFO-mode interrupt sources. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF_OVERFLOW) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFOVFCLR; + } +} +//***************************************************************************** +// +// SPI_pollingNonFIFOTransaction +// +//***************************************************************************** +uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, uint16_t data) +{ + uint16_t rxData; + + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + ASSERT(data < ((uint32_t)1U << charLength)); + + // + // Write to SPI Transmit buffer + // + SPI_writeDataBlockingNonFIFO(base, data << (16U - charLength)); + + // + // Read SPI Receive buffer + // + rxData = SPI_readDataBlockingNonFIFO(base); + + return(rxData); +} +//***************************************************************************** +// +// SPI_pollingFIFOTransaction +// +//***************************************************************************** + +void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay) +{ + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + + // + // Reset the TX / RX FIFO buffers to default state + // + SPI_disableFIFO(base); // Disable FIFO register + SPI_enableFIFO(base); // Enable FIFO register + + // + // Configure the FIFO Transmit Delay + // + SPI_setTxFifoTransmitDelay(base, txDelay); + + // + // Determine the number of 16-level words from number of words to be + // transmitted / received + // + uint16_t numOfSixteenWords = numOfWords / (uint16_t)SPI_FIFO_TXFULL; + + // + // Determine the number of remaining words from number of words to be + // transmitted / received + // + uint16_t remainingWords = numOfWords % (uint16_t)SPI_FIFO_TXFULL; + + uint16_t count = 0; + uint16_t i = 0; + uint16_t txBuffer_pos = 0; + uint16_t rxBuffer_pos = 0; + + // + // Number of transactions is based on numOfSixteenWords + // Each transaction will transmit and receive 16 words. + // + while(count < numOfSixteenWords) + { + // + // Fill-up the SPI Transmit FIFO buffers + // + for(i = 1; i <= (uint16_t)SPI_FIFO_TXFULL; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer is full + // + while(SPI_getRxFIFOStatus(base) < SPI_FIFO_RXFULL) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 1U; i <= (uint16_t)SPI_FIFO_RXFULL; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + count++; + } + + // + // Number of transactions is based on remainingWords + // + for(i = 0U; i < remainingWords; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer remaining words + // + while((uint16_t)SPI_getRxFIFOStatus(base) < remainingWords) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 0; i < remainingWords; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + // + // Disable SPI FIFO + // + SPI_disableFIFO(base); +} + +//***************************************************************************** +// +// SPI_transmit24Bits +// +//***************************************************************************** +void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t rxBuffer[3]; + uint16_t txBuffer[3]; + + ASSERT(data < ((uint32_t)1U << 24U)); + + // + // Empty Receive buffer + // + for(i = 0U; i < 3U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[23:16] + txBuffer[1] = (uint16_t)(data) >> 8U; // data[15:8] + txBuffer[2] = (uint16_t)(data) & 0x00FFU; // data[7:0] + + // + // Three 8-bits make a 24-bit + // Character length = 8 + // number of bytes = 3 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); +} +//***************************************************************************** +// +// SPI_receive16Bits +// +//***************************************************************************** + +uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + uint16_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 2U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 2U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = (rxBuffer[1] << 8) | rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = (rxBuffer[0] << 8) | rxBuffer[1]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_receive24Bits +// +//***************************************************************************** + +uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[3]; + uint16_t rxBuffer[3]; + uint32_t rxData = 0; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 3U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Two 8-bits make a 16-bit + // Character length = 8 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[2] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[2]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_transmit32Bits +// +//***************************************************************************** + +void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + + // + // Empty Receive buffer + // + for(i = 0U; i < 2U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[31:16] + txBuffer[1] = (uint16_t)(data); // data[15:0] + + // + // Two 16-bits make a 32-bit + // Character length = 16 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 16U, txBuffer, rxBuffer, 2U, txDelay); +} +//***************************************************************************** +// +// SPI_receive32Bits +// +//***************************************************************************** + +uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[4]; + uint16_t rxBuffer[4]; + uint32_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 4U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Four 8-bits make a 32-bit + // Character length = 8 + // number of bytes = 4 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 4U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[3] << 24U) | + ((uint32_t)rxBuffer[2] << 16U) | + ((uint32_t)rxBuffer[1] << 8U) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 24U) | + ((uint32_t)rxBuffer[1] << 16U) | + ((uint32_t)rxBuffer[2] << 8U) | + (uint32_t)rxBuffer[3]; + } + + return(rxData); +} diff --git a/gpio_bitfield_cpu1/device/driverlib/spi.h b/gpio_bitfield_cpu1/device/driverlib/spi.h new file mode 100644 index 0000000..b9e0d38 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/spi.h @@ -0,0 +1,1743 @@ +//########################################################################### +// +// FILE: spi.h +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SPI_H +#define SPI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup spi_api SPI +//! \brief This module is used for SPI configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_spi.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(), +// and SPI_clearInterruptStatus() as the intFlags parameter, and returned by +// SPI_getInterruptStatus(). +// +//***************************************************************************** +#define SPI_INT_RX_OVERRUN 0x0001U //!< Receive overrun interrupt +#define SPI_INT_RX_DATA_TX_EMPTY 0x0002U //!< Data received, transmit empty +#define SPI_INT_RXFF 0x0004U //!< RX FIFO level interrupt +#define SPI_INT_TXFF 0x0008U //!< TX FIFO level interrupt +#define SPI_INT_RXFF_OVERFLOW 0x0010U //!< RX FIFO overflow +#endif + + +//***************************************************************************** +// +//! This macro definition is used to transmit a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitByte(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 8U, txData) + +//***************************************************************************** +// +//! This macro definition is used to transmit a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a 16-bit word of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmit16Bits(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 16U, txData) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of bytes to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' bytes of data. +//! This macro definition uses SPI_pollingFIFOTransaction function. +//! +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNBytes(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' 16-bit words of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit 'N' 16-bit words of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitN16BitWord(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' with previously +//! configured SPI character length +//! +//! \param base specifies the SPI module base address +//! \param charLength specifies the SPI character length +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' with configurable +//! SPI character length. +//! +//! This macro uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNWordsWithCharLength(base, charLength, txBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, txBuffer, NULL, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition is used to receive a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! +//! This macro definition is to receive a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received byte. +// +//***************************************************************************** +#define SPI_receiveByte(base, dummyData) \ + SPI_pollingNonFIFOTransaction(base, 8U, dummyData) + +//***************************************************************************** +// +//! This macro is used to receive 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of bytes to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' bytes of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNBytes(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' 16-bits words of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of 16-bit words to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' 16-bit words of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveN16BitWord(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' words with previously configured character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of words with specified character +//! length +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' words with specified character length +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNWordsWithcharLength(base, charLength, rxBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, NULL, rxBuffer, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e protocol parameter. +// +//***************************************************************************** +typedef enum +{ + //! Mode 0. Polarity 0, phase 0. Rising edge without delay. + SPI_PROT_POL0PHA0 = 0x0000U, + //! Mode 1. Polarity 0, phase 1. Rising edge with delay. + SPI_PROT_POL0PHA1 = 0x0002U, + //! Mode 2. Polarity 1, phase 0. Falling edge without delay. + SPI_PROT_POL1PHA0 = 0x0001U, + //! Mode 3. Polarity 1, phase 1. Falling edge with delay. + SPI_PROT_POL1PHA1 = 0x0003U +} SPI_TransferProtocol; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_MODE_PERIPHERAL = 0x0002U, //!< SPI peripheral + SPI_MODE_CONTROLLER = 0x0006U, //!< SPI controller + SPI_MODE_PERIPHERAL_OD = 0x0000U, //!< SPI peripheral w/ output disabled + SPI_MODE_CONTROLLER_OD = 0x0004U //!< SPI controller w/ output disabled +} SPI_Mode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by SPI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + SPI_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + SPI_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + SPI_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + SPI_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + SPI_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + SPI_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + SPI_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + SPI_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + SPI_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + SPI_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + SPI_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + SPI_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + SPI_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + SPI_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + SPI_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + SPI_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} SPI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by SPI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + SPI_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + SPI_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + SPI_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + SPI_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + SPI_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + SPI_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + SPI_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + SPI_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + SPI_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + SPI_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + SPI_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + SPI_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + SPI_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + SPI_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + SPI_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXFULL = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXDEFAULT = 0x001FU //!< To prevent interrupt at reset +} SPI_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after midway in the bit stream + SPI_EMULATION_STOP_MIDWAY = 0x0000U, + //! Continue SPI operation regardless + SPI_EMULATION_FREE_RUN = 0x0010U, + //! Transmission will stop after a started transmission completes + SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U +} SPI_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setPTESignalPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_PTE_ACTIVE_LOW = 0x0000U, //!< SPIPTE is active low (normal) + SPI_PTE_ACTIVE_HIGH = SPI_PRI_PTEINV //!< SPIPTE is active high (inverted) +} SPI_PTEPolarity; + +//***************************************************************************** +// +//! Values that can be passed to SPI_receive16Bits(), SPI_receive24Bits(), +//! SPI_receive32Bits() +// +//***************************************************************************** +typedef enum +{ + SPI_DATA_LITTLE_ENDIAN = 0U, //!< LITTLE ENDIAN + SPI_DATA_BIG_ENDIAN = 1U, //!< BIG ENDIAN +} SPI_endianess; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an SPI base address. +//! +//! \param base specifies the SPI module base address. +//! +//! This function determines if a SPI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SPI_isBaseValid(uint32_t base) +{ + return( + (base == SPIA_BASE) || + (base == SPIB_BASE) || + (base == SPIC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function enables operation of the serial peripheral interface. The +//! serial peripheral interface must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; +} + +//***************************************************************************** +// +//! Disables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function disables operation of the serial peripheral interface. Call +//! this function before doing any configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); +} + +//***************************************************************************** +// +//! Sets the character length of SPI transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the character length of SPI transaction +//! +//! This function configures the character length of SPI transaction. +//! SPI character length can be from anywhere between 1-bit word to 16 bit word +//! of character length +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setcharLength(uint32_t base, uint16_t charLength) +{ + // + // Check the arguments. + // + ASSERT((charLength >= 1U) && (charLength <= 16U)); + + bool originalStatus = ((HWREGH(base + SPI_O_CCR) & (SPI_CCR_SPISWRESET)) + == SPI_CCR_SPISWRESET ); + + SPI_disableModule(base); + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & ~SPI_CCR_SPICHAR_M) | + (charLength - 1U); + // + // Restore original status + // + if(originalStatus){ + SPI_enableModule(base); + } +} + + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions enables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions disables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO); + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the transmit FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFIFO; +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the receive FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the RX FIFO. + // + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or +//! \b SPI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or +//! \b SPI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel, + SPI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SPI_O_FFTX) = (HWREGH(base + SPI_O_FFTX) & + (~SPI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SPI_O_FFRX) = (HWREGH(base + SPI_O_FFRX) & + (~SPI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, +//! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, +//! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel, + SPI_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SPI_TxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFTX) & + SPI_FFTX_TXFFIL_M)); + *rxLevel = (SPI_RxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFRX) & + SPI_FFRX_RXFFIL_M)); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3, +//! ..., or \b SPI_FIFO_TX16 +// +//***************************************************************************** +static inline SPI_TxFIFOLevel +SPI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_TxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) >> + SPI_FFTX_TXFFST_S))); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3, +//! ..., or \b SPI_FIFO_RX16 +// +//***************************************************************************** +static inline SPI_RxFIFOLevel +SPI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_RxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFST_M) >> + SPI_FFRX_RXFFST_S))); +} + +//***************************************************************************** +// +//! Determines whether the SPI transmitter is busy or not. +//! +//! \param base is the base address of the SPI port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. This function is only valid when operating in +//! FIFO mode. +//! +//! \return Returns \b true if the SPI is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SPI_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Determine if the SPI is busy. + // + return((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) != 0U); +} + +//***************************************************************************** +// +//! Puts a data element into the SPI transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets a data element from the SPI receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function gets received data from the receive buffer of the specified +//! SPI module and returns it. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for space in the FIFO and then puts data into the transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once space is available in the transmit FIFO. This +//! function should only be used when the FIFO is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until space is available in the receive FIFO. + // + while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data in the FIFO and then reads it from the receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits until there is data in the receive FIFO and then reads +//! received data from the receive buffer. This function should only be used +//! when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data is available in the receive FIFO. + // + while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for the transmit buffer to empty and then writes data to it. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once it is empty. This function should not be used +//! when FIFO mode is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until the transmit buffer is not full. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_BUFFULL_FLAG) != 0U) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data to be received and then reads it from the buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits for data to be received and then reads it from the +//! receive buffer of the specified SPI module. This function should not be +//! used when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data has been received. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) == 0U) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Enables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables 3-wire mode. When in controller mode, this allows +//! SPIPICO to become SPICOCI and SPIPOCI to become free for non-SPI use. +//! When in peripheral mode, SPIPOCI because the SPIPIPO pin and SPIPICO is +//! free for non-SPI use. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the tri-wire bit to enable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) |= SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Disables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables 3-wire mode. SPI will operate in normal 4-wire mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the tri-wire bit to disable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) &= ~SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Enables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables loopback mode. This mode is only valid during +//! controller mode and is helpful during device testing as it internally +//! connects PICO and POCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Disables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Set the peripheral select (SPIPTE) signal polarity. +//! +//! \param base is the base address of the SPI port. +//! \param polarity is the SPIPTE signal polarity. +//! +//! This function sets the polarity of the peripheral select (SPIPTE) signal. +//! The two modes to choose from for the \e polarity parameter are +//! \b SPI_PTE_ACTIVE_LOW for active-low polarity (typical) and +//! \b SPI_PTE_ACTIVE_HIGH for active-high polarity (considered inverted). +//! +//! \note This has no effect on the PTE signal when in controller mode. It is +//! only applicable to peripheral mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setPTESignalPolarity(uint32_t base, SPI_PTEPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the polarity of the SPIPTE signal to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & ~SPI_PRI_PTEINV) | + (uint16_t)polarity; +} + +//***************************************************************************** +// +//! Enables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables high speed mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Disables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables high speed mode. High speed mode is disabled by +//! default after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Sets SPI emulation mode. +//! +//! \param base is the base address of the SPI port. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the SPI operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit +//! stream. The rest of the bits will be transmitting after the suspend is +//! deasserted. +//! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the +//! first SPICLK pulse, the transmission will not start. If it occurs later, +//! the transmission will be completed. +//! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & + ~(SPI_PRI_FREE | SPI_PRI_SOFT)) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Configures the FIFO Transmit Delay +//! +//! \param base is the base address of the SPI port. +//! \param delay Tx FIFO delay to be configured in cycles (0..0xFF) +//! +//! This function sets the delay between every transfer from FIFO +//! transmit buffer to transmit shift register. The delay is defined in +//! number SPI serial clock cycles. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_setTxFifoTransmitDelay(uint32_t base, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(delay <= 0xFFU); + + // + // Configure the FIFO Transmit Delay Bits + // + HWREGH(base + SPI_O_FFCT) = delay; +} + +//***************************************************************************** +// +//! Returns the Emulation Buffer Received Data +//! +//! \param base is the base address of the SPI port. +//! +//! This function returns the Emulation Buffer Received Data +//! +//! \return Rx emulation buffer data +// +//***************************************************************************** +static inline uint16_t +SPI_readRxEmulationBuffer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Return Emulation Buffer Received Data + // + return(HWREGH(base + SPI_O_RXEMU)); +} + +//***************************************************************************** +// +//! Enable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function sets the TALK bit enabling the data trasnmission. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_enableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) |= SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Disable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function clears the TALK bit disabling the data trasnmission. The +//! output pin will be put in high-impedance state. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_disableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) &= ~SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Reset SPI transmit and receive channels +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the SPI transmit and receive channels. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_reset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write to SPRST bit the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_SPIRST; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIRST; +} + +//***************************************************************************** +// +//! Configures the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param protocol specifies the data transfer protocol. +//! \param mode specifies the mode of operation. +//! \param bitRate specifies the clock rate in Hz. +//! \param dataWidth specifies number of bits transferred per frame. +//! +//! This function configures the serial peripheral interface. It sets the SPI +//! protocol, mode of operation, bit rate, and data width. +//! +//! The \e protocol parameter defines the data frame format. The \e protocol +//! parameter can be one of the following values: \b SPI_PROT_POL0PHA0, +//! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or +//! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity +//! and phase configurations: +//! +//! 

    +//! Polarity Phase       Mode
+//!   0       0   SPI_PROT_POL0PHA0
+//!   0       1   SPI_PROT_POL0PHA1
+//!   1       0   SPI_PROT_POL1PHA0
+//!   1       1   SPI_PROT_POL1PHA1
+//!
    +//! +//! The \e mode parameter defines the operating mode of the SPI module. The +//! SPI module can operate as a controller or peripheral; the SPI can also be be +//! configured to disable output on its serial output line. The \e mode +//! parameter can be one of the following values: \b SPI_MODE_CONTROLLER, +//! \b SPI_MODE_PERIPHERAL, \b SPI_MODE_CONTROLLER_OD or +//! \b SPI_MODE_PERIPHERAL_OD ("OD" indicates "output disabled"). +//! +//! The \e bitRate parameter defines the bit rate for the SPI. This bit rate +//! must satisfy the following clock ratio criteria: +//! +//! - \e bitRate can be no greater than lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The \e dataWidth parameter defines the width of the data transfers and +//! can be a value between 1 and 16, inclusive. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI operation should be disabled via SPI_disableModule() before any +//! changes to its configuration. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth); + +//***************************************************************************** +// +//! Configures the baud rate of the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param bitRate specifies the clock rate in Hz. +//! +//! This function configures the SPI baud rate. The \e bitRate parameter +//! defines the bit rate for the SPI. This bit rate must satisfy the following +//! clock ratio criteria: +//! +//! - \e bitRate can be no greater than \e lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate() +//! if you wish to configure it separately from protocol and mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate); + +//***************************************************************************** +// +//! Enables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SPI interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. The \e intFlags parameter can be +//! any of the following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level +//! interrupt (and RX FIFO overflow) +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SPI interrupt sources. The +//! \e intFlags parameter can be any of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW) +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base specifies the SPI module base address. +//! +//! This function returns the interrupt status for the SPI module. +//! +//! \return The current interrupt status, enumerated as a bit field of the +//! following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF - RX FIFO level interrupt +//! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +// +//***************************************************************************** +extern uint32_t +SPI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified SPI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e intFlags parameter can consist of a bit field of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF +//! - \b SPI_INT_RXFF_OVERFLOW +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive +//! receive buffer, so it usually doesn't need to be cleared using this +//! function. +//! +//! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + + +//***************************************************************************** +// +//! This function can be used to transmit a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 24-bit word of data. +//! 24-bit word data is divided into three bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay); + +//***************************************************************************** +// +//! This function can be used to transmit a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 32-bit word of data. +//! 32-bit word data is divided into four bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to receive a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 16-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 16-bit word. +// +//***************************************************************************** +extern uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 24-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 24-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 32-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 32-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param data specified the data to be transmitted +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return . +// +//***************************************************************************** +extern uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t data); + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length and 'N' words of transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param pTxBuffer specifies the pointer to transmit buffer +//! \param pRxBuffer specifies the pointer to receive buffer +//! \param numOfWords specified the number of data to be transmitted / received +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return none +// +//***************************************************************************** +extern void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SPI_H diff --git a/gpio_bitfield_cpu1/device/driverlib/sysctl.c b/gpio_bitfield_cpu1/device/driverlib/sysctl.c new file mode 100644 index 0000000..f4708f2 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/sysctl.c @@ -0,0 +1,1469 @@ +//########################################################################### +// +// FILE: sysctl.c +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cputimer.h" +#include "sysctl.h" + +// +// Define to isolate inline assembly +// +#define SYSCTL_DELAY __asm(" .if __TI_EABI__\n" \ + " .asg SysCtl_delay , _SysCtl_delay\n" \ + " .endif\n" \ + " .def _SysCtl_delay\n" \ + " .sect \".TI.ramfunc\"\n" \ + " .global _SysCtl_delay\n" \ + "_SysCtl_delay:\n" \ + " SUB ACC,#1\n" \ + " BF _SysCtl_delay, GEQ\n" \ + " LRETR\n") +#define SYSCTL_CLRC_DBGM __asm(" CLRC DBGM") + +// +// Define Timer1 and Timer2 seed values +// +#define TMR1SYSCLKCTR 0xF0000000U +#define TMR2INPCLKCTR 0x800U + +#define XTAL_CPUTIMER_PERIOD 1023U + +//***************************************************************************** +// +// SysCtl_delay() +// +//***************************************************************************** +SYSCTL_DELAY; + + +static void +SysCtl_pollCpuTimer(void) +{ + // + // Delay for 1 ms while the XTAL powers up + // + // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles + // + SysCtl_delay(2000); + + // + // Wait for cpu timer 2 to overflow + // + while(CPUTimer_getTimerOverflowStatus(CPUTIMER2_BASE) == false); + { + // + // If your application is stuck in this loop, please check if the + // input clock source is valid. + // + } + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); +} + +//***************************************************************************** +// +// SysCtl_getClock() +// +//***************************************************************************** +uint32_t +SysCtl_getClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + // + // Don't proceed if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning the INTOSC1 rate. You need + // to handle the MCD and clear the failure. + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (uint32_t)SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + if((oscSource == (SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) || + (oscSource == (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S))) + { + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) & + (SYSCTL_SYSPLLCTL1_PLLEN | SYSCTL_SYSPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_FMULT_M) >> + SYSCTL_SYSPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier and fixed divide by 2 + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_IMULT_M) >> + SYSCTL_SYSPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)); + } + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getAuxClock() +// +//***************************************************************************** +uint32_t SysCtl_getAuxClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + (uint32_t)SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M; + + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + if(oscSource == (SYSCTL_AUXPLL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) + { + // + // 10MHz Internal Clock + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) & + (SYSCTL_AUXPLLCTL1_PLLEN | SYSCTL_AUXPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M) >> + SYSCTL_AUXPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_IMULT_M) >> + SYSCTL_AUXPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + clockOut /= (1U << (HWREG(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)); + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_setClock() +// +//***************************************************************************** +bool +SysCtl_setClock(uint32_t config) +{ + uint16_t divSel; + uint16_t iMult = 0U, fMult = 0U, pllMult = 0U, div; + bool status, sysclkInvalidFreq = true; + uint16_t i, tempSCSR, tempWDCR, tempWDWCR, intStatus; + uint16_t t1TCR, t1TPR, t1TPRH, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t1PRD, t2PRD, ctr1; + float32_t sysclkToInClkError, mult; + + // + // Check the arguments. + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Don't proceed to the PLL initialization if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning false. You'll need to clear + // the MCD error. + // + status = false; + } + else + { + // + // Configure oscillator source + // + SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M); + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure PLL if enabled + // + EALLOW; + if((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) + { + if((HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) & + SYSCTL_SYSDBGCTL_BIT_0) != 0U) + { + // + // The user can optionally insert handler code here. This will + // only be executed if a watchdog reset occurred after a failed + // system PLL initialization. See your device user's guide for + // more information. + // + // If the application has a watchdog reset handler, this bit + // should be checked to determine if the watchdog reset + // occurred because of the PLL. + // + // No action here will continue with retrying the PLL as + // normal. + // + } + + // + // Set dividers to /1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = 0U; + + // + // Get the PLL multiplier settings from config + // + iMult |= (uint16_t)(config & SYSCTL_IMULT_M); + fMult |= (uint16_t)((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S); + pllMult |= (iMult << SYSCTL_SYSPLLMULT_IMULT_S) | + (fMult << SYSCTL_SYSPLLMULT_FMULT_S); + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase + // this number according to allotted system initialization time. + // + for(i = 0U; i < 5U; i++) + { + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + asm(" RPT #60 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + } + } + + // + // Configure Dividers. Set divider to produce slower output frequency + // to limit current increase. + // + divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + + if(divSel != (126U / 2U)) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | (divSel + 1U); + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the + // PLLstartup sequence. If your application has already cleared the + // watchdog SCRS[WDOVERRIDE] bit this cannot be done. It is recommended + // not to clear this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + tempSCSR = HWREGH(WD_BASE + SYSCTL_O_SCSR); + tempWDCR = HWREGH(WD_BASE + SYSCTL_O_WDCR); + tempWDWCR = HWREGH(WD_BASE + SYSCTL_O_WDWCR); + + // + // Disable windowed functionality, reset counter + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = 0x0U; + SysCtl_serviceWatchdog(); + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = 0x0U; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + + // + // This bit is reset only by power-on-reset (POR) and will not be + // cleared by a WD reset + // + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) |= SYSCTL_SYSDBGCTL_BIT_0; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_SYSPLLCTL1) |= SYSCTL_SYSPLLCTL1_PLLCLKEN; + + EDIS; + + // + // Delay to ensure system is clocking from PLL prior to clearing + // status bit + // + SysCtl_delay(3U); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer + // counts are off by +/- 10%. At a minimum, SYSCLK check is performed. + // Re-lock attempt is carried out if SLIPS bit is set. + // This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will + // be aborted by watchdog reset. + // + while(((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) && + (sysclkInvalidFreq == true)) + { + EALLOW; + + // + // Perform PLL re-lock only if SLIPS bit is set, otherwise monitor + // SYSCLK frequency with timers + // + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_SLIPS) == 1U) + { + // + // Bypass PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + SysCtl_delay(12U); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) |= pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + ; + } + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |= + SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay to ensure system is clocking from PLL prior to + // clearing status bit + // + SysCtl_delay(12U); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR); + t1PRD = HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD); + t1TPR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR); + t1TPRH = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH); + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + + // + // Stop timer 1 + // Seed timer1 counter + // Set sysclock divider + // Reload timer with value in PRD + // Clear interrupt flag + // Enable interrupt + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR1SYSCLKCTR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + + // + // Configure timer2 to count Input clock cycles + // + switch (config & SYSCTL_OSCSRC_M) + { + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INT_OSC1 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 1U; + break; + + case SYSCTL_OSCSRC_OSC2: + // + // Clk Src = INT_OSC2 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 2U; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Clk Src = XTAL + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 3U; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + + // + // Clear interrupt flag + // Enable interrupt + // Stop timer 2 + // Seed timer2 counter + // Set sysclock divider + // Reload timer with value in PRD + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR2INPCLKCTR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Stop/Start timer counters + // + + // + // Stop timer 1 + // Stop timer 2 + // Reload timer1 with value in PRD + // Reload timer2 with value in PRD + // Clear timer2 interrupt flag + // Start timer2 + // Start timer1 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Wait for Timers - Stop if either timer overflows + // + while(((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U) && + ((HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U)) + { + ; + } + + // + // Stop timer 1 and 2 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + // + // Calculate elapsed counts on timer1 + // + ctr1 = (uint32_t)TMR1SYSCLKCTR - HWREG(CPUTIMER1_BASE + + CPUTIMER_O_TIM); + + // + // Restore timer settings + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) = t1TCR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = t1PRD; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR) = t1TPR; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH) = t1TPRH; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float32_t)iMult + ((float32_t)fMult / 4.0F); + + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & 0x3FU) == 0U) + { + div = 1U; + } + else + { + div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + 0x3FU) << 1; + } + + sysclkToInClkError = (mult / (float32_t)div) - + ((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is + // off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) || + (sysclkToInClkError < -0.10F)); + + EDIS; + } + + // + // Clear bit + // + EALLOW; + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &= ~SYSCTL_SYSDBGCTL_BIT_0; + EDIS; + + // + // Restore user watchdog, first resetting counter + // + SysCtl_serviceWatchdog(); + + // + // Set the KEY bits and make sure not to set the WDOVERRIDE bit + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = tempWDCR | SYSCTL_WD_CHKBITS; + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = tempWDWCR; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = tempSCSR & ~SYSCTL_SCSR_WDOVERRIDE; + EDIS; + + // + // Restore state of ST1[INTM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x1U) == 0U) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x2U) == 0U) + { + SYSCTL_CLRC_DBGM; + } + + // + // ~200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + SysCtl_delay(40U); + + // + // Set the divider to user value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + status = true; + } + + return(status); +} +//***************************************************************************** +// +// SysCtl_setAuxClock() +// +//***************************************************************************** +void SysCtl_setAuxClock(uint32_t config) +{ + uint16_t pllMult = 0U; + uint16_t counter = 0U, started = 0U, attempts = 0U; + uint16_t mult; + uint16_t i, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Check the arguments + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure oscillator source + // + SysCtl_selectOscSourceAuxPLL(config & SYSCTL_OSCSRC_M); + + // + // Get the PLL multiplier settings from config + // + pllMult |= (uint16_t)((config & SYSCTL_IMULT_M) << + SYSCTL_AUXPLLMULT_IMULT_S); + pllMult |= (uint16_t)(((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << + SYSCTL_AUXPLLMULT_FMULT_S); + + // + // Get the PLL multipliers currently programmed + // + mult = (uint16_t)((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_M) >> + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_S); + mult |= (uint16_t)(HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M); + + // + // Lock PLL only if the multipliers need update + // + if(mult != pllMult) + { + + // + // Configure PLL if enabled + // + if((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE) + { + // + // Backup Timer 2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // - Clock source to AUXPLL + // - Clock divider to divide by 1 + // - Small period to detect overflow + // - Interrupt disabled + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = 6U; + + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = 10U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK / 2 + // while using Timer 2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = 0x3U; + SYSCTL_REGWRITE_DELAY; + EDIS; + + // + // Lock the PLL up to five times. + //CPU Timer 2 will monitor a successful + // lock and break out of the loop earlier if detected. + // + while((counter < 5U) && (started == 0U)) + { + EALLOW; + + // + // Turn off AUXPLL and delay for it to power down. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= + ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically + // turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + SYSCTL_REGWRITE_DELAY; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLEN; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. + // This is used to test that the PLL has successfully started. + // + // Reload and start the timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Check to see timer is counting properly + // + for(i = 0U; i < 1000U; i++) + { + // + // Check overflow flag + // + if((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) != 0U) + { + // + // Clear overflow flag + // + HWREGH(CPUTIMER2_BASE + + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + + // + // Set flag to indicate PLL started and break out of + // for-loop + // + started = 1U; + break; + } + } + + // + // Stop timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + counter++; + EDIS; + } + + if(started == 0U) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass + // PLL). + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) = 0U; + EDIS; + + // + // The user should put some handler code here based on how + // this condition should be handled in their application. + // + ESTOP0; + } + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Reload period value + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + EDIS; + } + } + else + { + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + EDIS; + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + while(((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_SLIPS) != 0U) && (attempts < 10U) && + ((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE)) + { + EALLOW; + + // + // Bypass AUXPLL + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLEN; + + // + // Wait for the AUXPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + + SysCtl_delay(3U); + + attempts++; + + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + SYSCTL_REGWRITE_DELAY; + EDIS; + +} + + +//***************************************************************************** +// +// SysCtl_selectXTAL() +// +//***************************************************************************** +void +SysCtl_selectXTAL(void) +{ + uint16_t t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Backup CPU timer2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Backup AUX clock settings + // + uint16_t clksrcctl2 = HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2); + uint16_t auxpllctl1 = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1); + uint16_t auxclkdivsel = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL); + + // + // Set AUX clock source to XTAL, bypass mode. + // AUXCLK is used as the CPUTimer Clock source. SYSCLK frequency must be + // atleast twice the frequency of AUXCLK. SYSCLK = INTOSC2(10MHz) + // Set the AUX divider to 8. The above condition will be met for XTAL + // frequencies up to 40MHz + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = 0x0U; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = SYSCTL_AUXPLLCLK_DIV_8; + SYSCTL_REGWRITE_DELAY; + + + // + // Disable cpu timer 2 interrupt + // + CPUTimer_disableInterrupt(CPUTIMER2_BASE); + + // + // Stop cpu timer 2 if running + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Initialize cpu timer 2 period + // + CPUTimer_setPeriod(CPUTIMER2_BASE, XTAL_CPUTIMER_PERIOD); + + // + // Set cpu timer 2 clock source to XTAL + // + CPUTimer_selectClockSource(CPUTIMER2_BASE, CPUTIMER_CLOCK_SOURCE_AUX, + CPUTIMER_CLOCK_PRESCALER_1); + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); + + // + // Start cpu timer 2 + // + CPUTimer_startTimer(CPUTIMER2_BASE); + + EALLOW; + // + // Turn on XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_XTALOFF; + EDIS; + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + + // + // If a missing clock failure was detected, try waiting for the cpu timer 2 + // to overflow again. + // + while(SysCtl_isMCDClockFailureDetected()) + { + // + // Clear the MCD failure + // + SysCtl_resetMCD(); + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + } + + // + // Stop cpu timer 2 + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Restore AUX clock settings + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = clksrcctl2; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = auxpllctl1; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = auxclkdivsel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSource() +// +//***************************************************************************** +void +SysCtl_selectOscSource(uint32_t oscSource) +{ + ASSERT((oscSource == SYSCTL_OSCSRC_OSC1) || + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL)); + + // + // Select the specified source. + // + EALLOW; + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Select XTAL in crystal mode and wait for it to power up + // + SysCtl_selectXTAL(); + break; + + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INTOSC1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M) | + (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S); + + SYSCTL_CLKSRCCTL_DELAY; + + // + //Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSourceAuxPLL() +// +//***************************************************************************** +void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource) +{ + bool status = false; + + EALLOW; + + switch(oscSource) + { + case SYSCTL_AUXPLL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_INTOSC2OFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M); + break; + + case SYSCTL_AUXPLL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_XTALOFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + break; + + case SYSCTL_AUXPLL_OSCSRC_AUXCLKIN: + // + // Clk Src = AUXCLKIN + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (2U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + SYSCTL_CLKSRCCTL_DELAY; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_getLowSpeedClock() +// +//***************************************************************************** +uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz) +{ + uint32_t clockOut; + + // + // Get the main system clock + // + clockOut = SysCtl_getClock(clockInHz); + + // + // Apply the divider to the main clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M)); + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getDeviceParametric() +// +//***************************************************************************** +uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric) +{ + uint32_t value; + + // + // Get requested parametric value + // + switch(parametric) + { + case SYSCTL_DEVICE_QUAL: + // + // Qualification Status + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_QUAL_M) >> SYSCTL_PARTIDL_QUAL_S); + break; + + case SYSCTL_DEVICE_PINCOUNT: + // + // Pin Count + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + break; + + case SYSCTL_DEVICE_INSTASPIN: + // + // InstaSPIN Feature Set + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_INSTASPIN_M) >> + SYSCTL_PARTIDL_INSTASPIN_S); + break; + + case SYSCTL_DEVICE_FLASH: + // + // Flash Size (KB) + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_FLASH_SIZE_M) >> + SYSCTL_PARTIDL_FLASH_SIZE_S); + break; + + case SYSCTL_DEVICE_PARTID: + // + // PARTID Format Revision + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M) >> + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S); + break; + + case SYSCTL_DEVICE_FAMILY: + // + // Device Family + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_FAMILY_M) >> SYSCTL_PARTIDH_FAMILY_S); + break; + + case SYSCTL_DEVICE_PARTNO: + // + // Part Number + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_PARTNO_M) >> SYSCTL_PARTIDH_PARTNO_S); + break; + + case SYSCTL_DEVICE_CLASSID: + // + // Class ID + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_DEVICE_CLASS_ID_M) >> + SYSCTL_PARTIDH_DEVICE_CLASS_ID_S); + break; + + default: + // + // Not a valid value for PARTID register + // + value = 0U; + break; + } + + return((uint16_t)value); +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/sysctl.h b/gpio_bitfield_cpu1/device/driverlib/sysctl.h new file mode 100644 index 0000000..8b263eb --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/sysctl.h @@ -0,0 +1,3531 @@ +//########################################################################### +// +// FILE: sysctl.h +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SYSCTL_H +#define SYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sysctl_api SysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_nmi.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_otp.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + + +// +// Macro used for adding delay between 2 consecutive writes to CLKSRCCTL1 +// register. +// Delay = 300 NOPs +// +#define SYSCTL_CLKSRCCTL_DELAY asm(" RPT #250 || NOP \n RPT #50 || NOP") + +// +// Macro used for adding delay between 2 consecutive writes to memory mapped +// register in System control +// Total delay = 3 * (DEVICE_SYSCLK_FREQ / INTOSC1 Freq) + 9 +// +#define SYSCTL_REGWRITE_DELAY asm(" RPT #69 || NOP") + +//***************************************************************************** +// +// Defines for system control functions. Not intended for use by application +// code. +// +//***************************************************************************** + +// +// Shifted pattern for WDCR register's WDCHK field. +// +#define SYSCTL_WD_CHKBITS 0x0028U + +// +// Keys for WDKEY field. The first enables resets and the second resets. +// +#define SYSCTL_WD_ENRSTKEY 0x0055U +#define SYSCTL_WD_RSTKEY 0x00AAU + +// +// Values to help decode peripheral parameter +// +#define SYSCTL_PERIPH_REG_M 0x001FU +#define SYSCTL_PERIPH_REG_S 0x0000U +#define SYSCTL_PERIPH_BIT_M 0x1F00U +#define SYSCTL_PERIPH_BIT_S 0x0008U + +// +//Keys for the System control registers write protection +// +#define SYSCTL_REG_KEY 0xA5A50000U +#define SYSCTL_PLL_KEY 0XCAFE0000U + +// +//Values to help access shifting of bits +// +#define SYSCTL_TYPE_LOCK_S 0xFU + + +// +// LPM defines for LPMCR.LPM +// +#define SYSCTL_LPM_IDLE 0x0000U +#define SYSCTL_LPM_STANDBY 0x0001U +#define SYSCTL_LPM_HALT 0x0002U +#define SYSCTL_LPM_HIB 0x0003U + +// +// Bit shift for DAC to configure the CPUSEL register +// +#define SYSCTL_CPUSEL_DAC_S 0x10U + +// +// Default internal oscillator frequency, 10 MHz +// +#define SYSCTL_DEFAULT_OSC_FREQ 10000000U + +// +// Mask for SYNCSELECT.SYNCIN +// +#define SYSCTL_SYNCSELECT_SYNCIN_M SYSCTL_SYNCSELECT_EPWM4SYNCIN_M + +// +// Boot ROM Booting and Reset Status +// +#if defined(CPU2) +#define SYSCTL_BOOT_ROM_STATUS 0x0002U +#else +#define SYSCTL_BOOT_ROM_STATUS 0x002CU +#endif +#define SYSCTL_BOOT_ROM_POR 0x8000U +#define SYSCTL_BOOT_ROM_XRS 0x4000U + +#define SYSCTL_DEVICECAL_CONTEXT_SAVE asm(" PUSH ACC \n\ + PUSH DP \n\ + PUSH XAR0 \n\ + PUSH XAR2 \n\ + PUSH XAR3 \n\ + PUSH XAR4 \n\ + PUSH XAR5 \n\ + ") + +#define SYSCTL_DEVICECAL_CONTEXT_RESTORE asm(" POP XAR5 \n\ + POP XAR4 \n\ + POP XAR3 \n\ + POP XAR2 \n\ + POP XAR0 \n\ + POP DP \n\ + POP ACC \n\ + ") + +// +// Device_cal function which is available in OTP memory +// This function is called in SysCtl_resetPeripheral after resetting +// analog peripherals +// +#define Device_cal ((void (*)(void))((uintptr_t)0x070282)) + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setClock() API as +// the config parameter. +// +//***************************************************************************** +// +// System clock divider (SYSDIV) +// + + + +#define SYSCTL_SYSDIV_M 0x00001F80UL // Mask for SYSDIV value in config +#define SYSCTL_SYSDIV_S 7U // Shift for SYSDIV value in config + +//! Macro to format system clock divider value. x must be 1 or even values up +//! to 126. +#define SYSCTL_SYSDIV(x) ((((x) / 2U) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M) + +// +// Integer multiplier (IMULT) +// +#define SYSCTL_IMULT_M 0x0000007FUL // Mask for IMULT value in config +#define SYSCTL_IMULT_S 0U // Shift for IMULT value in config +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M) + +#ifndef DOXYGEN_PDF_IGNORE +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_FMULT_M 0x00006000UL // Mask for FMULT value in config +#define SYSCTL_FMULT_S 13U // Shift for FMULT value in config +#define SYSCTL_FMULT_NONE 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_0 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_1_4 0x00002000UL //!< Fractional multiplier of 0.25 +#define SYSCTL_FMULT_1_2 0x00004000UL //!< Fractional multiplier of 0.50 +#define SYSCTL_FMULT_3_4 0x00006000UL //!< Fractional multiplier of 0.75 + +// +// Oscillator source +// +// Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(), +// and SysCtl_turnOffOsc() functions as the oscSource parameter. +// +#define SYSCTL_OSCSRC_M 0x00030000UL // Mask for OSCSRC value in config +#define SYSCTL_OSCSRC_S 16U // Shift for OSCSRC value in config +//! Internal oscillator INTOSC2 +#define SYSCTL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) in crystal mode +#define SYSCTL_OSCSRC_XTAL 0x00010000U +//! Internal oscillator INTOSC1 +#define SYSCTL_OSCSRC_OSC1 0x00020000UL + +// +// Enable/disable PLL +// +#define SYSCTL_PLL_ENABLE 0x80000000U //!< Enable PLL +#define SYSCTL_PLL_DISABLE 0x00000000U //!< Disable PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setAuxClock() API +// as the config parameter. +// +//***************************************************************************** +// +// Auxiliary clock divider (AUXCLKDIV) +// +#define SYSCTL_AUXPLL_DIV_1 0x00000000UL //!< Auxiliary PLL divide by 1 +#define SYSCTL_AUXPLL_DIV_2 0x00000080UL //!< Auxiliary PLL divide by 2 +#define SYSCTL_AUXPLL_DIV_4 0x00000100UL //!< Auxiliary PLL divide by 4 +#define SYSCTL_AUXPLL_DIV_8 0x00000180UL //!< Auxiliary PLL divide by 8 + +// +// Integer multiplier (IMULT) +// +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_AUXPLL_IMULT(x) SYSCTL_IMULT((x)) + +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_AUXPLL_FMULT_NONE 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_0 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_1_4 0x00002000UL //!< Fractional multiplier - 0.25 +#define SYSCTL_AUXPLL_FMULT_1_2 0x00004000UL //!< Fractional multiplier - 0.50 +#define SYSCTL_AUXPLL_FMULT_3_4 0x00006000UL //!< Fractional multiplier - 0.75 + +// +// Oscillator source +// +//! Internal oscillator INTOSC2 as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_XTAL 0x00010000UL +//! AUXCLKIN (from GPIO) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_AUXCLKIN 0x00020000U + +// +// Enable/disable PLL +// +#define SYSCTL_AUXPLL_ENABLE 0x80000000U //!< Enable AUXPLL +#define SYSCTL_AUXPLL_DISABLE 0x00000000U //!< Disable AUXPLL + +//***************************************************************************** +// +// Values that can be passed to SysCtl_selectSecController() as the +// periFrame1Config and periFrame2Config parameters. +// +//***************************************************************************** +//! Configure CLA as the secondary controller +#define SYSCTL_SEC_CONTROLLER_CLA 0x0U +//! Configure DMA a secondary controller +#define SYSCTL_SEC_CONTROLLER_DMA 0x1U + +//***************************************************************************** +// +// Values that can be passed to SysCtl_clearNMIStatus(), +// SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and +// SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by +// SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus(). +// +//***************************************************************************** +#define SYSCTL_NMI_NMIINT 0x1U //!< NMI Interrupt Flag +#define SYSCTL_NMI_CLOCKFAIL 0x2U //!< Clock Fail Interrupt Flag +#define SYSCTL_NMI_RAMUNCERR 0x4U //!< RAM Uncorrectable Error NMI Flag +#define SYSCTL_NMI_FLUNCERR 0x8U //!< Flash Uncorrectable Error NMI Flag +#define SYSCTL_NMI_CPU1HWBISTERR 0x10U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_CPU2HWBISTERR 0x20U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_PIEVECTERR 0x40U //!< PIE Vector Fetch Error Flag +#define SYSCTL_NMI_CLBNMI 0x100U //!< Configurable Logic Block NMI Flag +#define SYSCTL_NMI_CPU2WDRSN 0x200U //!< CPU2 WDRSn Reset Indication Flag +#define SYSCTL_NMI_CPU2NMIWDRSN 0x400U //!< CPU2 NMIWDRSn Reset Indication Flag + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_clearResetCause() +// API as rstCauses or returned by the SysCtl_getResetCause() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_POR 0x00000001U //!< Power-on reset +#define SYSCTL_CAUSE_XRS 0x00000002U //!< External reset pin +#define SYSCTL_CAUSE_WDRS 0x00000004U //!< Watchdog reset +#define SYSCTL_CAUSE_NMIWDRS 0x00000008U //!< NMI watchdog reset +#define SYSCTL_CAUSE_SCCRESET 0x00000100U //!< SCCRESETn by DCSM +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_enablePeripheral() +//! and SysCtl_disablePeripheral() as the \e peripheral parameter. +//! The EPWM Clock enable bit is also used to enable clocking for CLB. +//! The EPWM and CLB clock enable bits are mapped to same value, +// +//***************************************************************************** +#define SYSCTL_PERIPH_CLK_CLB1 SYSCTL_PERIPH_CLK_EPWM1 //!< CLB1 clock +#define SYSCTL_PERIPH_CLK_CLB2 SYSCTL_PERIPH_CLK_EPWM2 //!< CLB2 clock +#define SYSCTL_PERIPH_CLK_CLB3 SYSCTL_PERIPH_CLK_EPWM3 //!< CLB3 clock +#define SYSCTL_PERIPH_CLK_CLB4 SYSCTL_PERIPH_CLK_EPWM4 //!< CLB4 clock +//***************************************************************************** +// +// The following values define the adcsocSrc parameter for +// SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource(). +// +//***************************************************************************** +#define SYSCTL_ADCSOC_SRC_PWM1SOCA 0x1U //! EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT, //!< EPWM4SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT, //!< EPWM7SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT //!< EPWM10SYNCOUT --> EXTSYNCOUT + +} SysCtl_SyncOutputSource; + +//***************************************************************************** +// +//! The following values define the \e parametric parameter for +//! SysCtl_getDeviceParametric(). +// +//***************************************************************************** +typedef enum +{ + SYSCTL_DEVICE_QUAL, //!< Device Qualification Status + SYSCTL_DEVICE_PINCOUNT, //!< Device Pin Count + SYSCTL_DEVICE_INSTASPIN, //!< Device InstaSPIN Feature Set + SYSCTL_DEVICE_FLASH, //!< Device Flash size (KB) + SYSCTL_DEVICE_PARTID, //!< Device Part ID Format Revision + SYSCTL_DEVICE_FAMILY, //!< Device Family + SYSCTL_DEVICE_PARTNO, //!< Device Part Number + SYSCTL_DEVICE_CLASSID //!< Device Class ID +} SysCtl_DeviceParametric; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setXClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_XCLKOUT_DIV_1 = 0, //!< XCLKOUT = XCLKOUT / 1 + SYSCTL_XCLKOUT_DIV_2 = 1, //!< XCLKOUT = XCLKOUT / 2 + SYSCTL_XCLKOUT_DIV_4 = 2, //!< XCLKOUT = XCLKOUT / 4 + SYSCTL_XCLKOUT_DIV_8 = 3 //!< XCLKOUT = XCLKOUT / 8 + +}SysCtl_XClkDivider; + + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setAuxPLLClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_AUXPLLCLK_DIV_1, //!< AUXPLL clock = AUXPLL clock / 1 + SYSCTL_AUXPLLCLK_DIV_2, //!< AUXPLL clock = AUXPLL clock / 2 + SYSCTL_AUXPLLCLK_DIV_4, //!< AUXPLL clock = AUXPLL clock / 4 + SYSCTL_AUXPLLCLK_DIV_8, //!< AUXPLL clock = AUXPLL clock / 8 + SYSCTL_AUXPLLCLK_DIV_3, //!< AUXPLL clock = AUXPLL clock / 3 + SYSCTL_AUXPLLCLK_DIV_5, //!< AUXPLL clock = AUXPLL clock / 5 + SYSCTL_AUXPLLCLK_DIV_6, //!< AUXPLL clock = AUXPLL clock / 6 + SYSCTL_AUXPLLCLK_DIV_7 //!< AUXPLL clock = AUXPLL clock / 7 + +}SysCtl_AuxPLLClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setCputimer2Clk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKPRESCALE_1, //!< Cputimer2 clock = Cputimer2 clock / 1 + SYSCTL_TMR2CLKPRESCALE_2, //!< Cputimer2 clock = Cputimer2 clock / 2 + SYSCTL_TMR2CLKPRESCALE_4, //!< Cputimer2 clock = Cputimer2 clock / 4 + SYSCTL_TMR2CLKPRESCALE_8, //!< Cputimer2 clock = Cputimer2 clock / 8 + SYSCTL_TMR2CLKPRESCALE_16 //!< Cputimer2 clock = Cputimer2 clock / 16 + +}SysCtl_Cputimer2ClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_setCputimer2Clk() +//! as \e source parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKSRCSEL_SYSCLK = 0U, //!< System Clock + SYSCTL_TMR2CLKSRCSEL_INTOSC1 = 1U, //!< Internal Oscillator 1 + SYSCTL_TMR2CLKSRCSEL_INTOSC2 = 2U, //!< Internal Oscillator 2 + SYSCTL_TMR2CLKSRCSEL_XTAL = 3U, //!< Crystal oscillator + SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK = 6U //!< Aux PLL CLock + +}SysCtl_Cputimer2ClkSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Wrapper function for Device_cal function +//! +//! \param None +//! +//! This is a wrapper function for the Device_cal function available in the OTP +//! memory. +//! The function saves and restores the core registers which are being +//! used by the Device_cal function +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_deviceCal(void) +{ + // + // Save the core registers used by Device_cal function in the stack + // + SYSCTL_DEVICECAL_CONTEXT_SAVE; + + // + // Call the Device_cal function + // + Device_cal(); + + // + // Restore the core registers + // + SYSCTL_DEVICECAL_CONTEXT_RESTORE; +} + +//***************************************************************************** +// +//! Resets a peripheral +//! +//! \param peripheral is the peripheral to reset. +//! +//! This function uses the SOFTPRESx registers to reset a specified peripheral. +//! Module registers will be returned to their reset states. +//! +//! \note This includes registers containing trim values.The peripheral +//! software reset needed by CPU2 can be communicated to CPU1 via +//! IPC for all shared peripherals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Sets the appropriate reset bit and then clears it. + // + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) |= (1UL << bitIndex); + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) &= ~(1UL << bitIndex); + + // + // Call Device_cal function + // + if((((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0xDU) || // ADCx + (((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0x10U) // DACx + ) + { + SysCtl_deviceCal(); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param peripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note Note that there should be atleast 5 cycles delay between enabling the +//! peripheral clock and accessing the peripheral registers. The delay should be +//! added by the user if the peripheral is accessed immediately after this +//! function call. +//! Use asm(" RPT #5 || NOP"); to add 5 cycle delay post this function call. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn on the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) |= (1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param peripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn off the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) &= ~(1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a watchdog reset of the device. +//! +//! \return This function does not return. +// +//***************************************************************************** +static inline void +SysCtl_resetDevice(void) +{ + // + // Write an incorrect check value to the watchdog control register + // This will cause a device reset + // + EALLOW; + + // + // Enable the watchdog + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + // + // Write a bad check value + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = 0U; + SYSCTL_REGWRITE_DELAY; + + EDIS; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while((bool)1) + { + } +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! \note If you re-purpose the reserved boot ROM RAM, the POR and XRS reset +//! statuses won't be accurate. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getResetCause(void) +{ + uint32_t resetCauses; + + // + // Read CPU reset register + // + resetCauses = HWREG(CPUSYS_BASE + SYSCTL_O_RESC) & + ((uint32_t)SYSCTL_RESC_POR | (uint32_t)SYSCTL_RESC_XRSN | + (uint32_t)SYSCTL_RESC_WDRSN | + (uint32_t)SYSCTL_RESC_NMIWDRSN | + (uint32_t)SYSCTL_RESC_SCCRESETN + ); + + // + // Set POR and XRS Causes from boot ROM Status + // + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_POR) == + (uint32_t)SYSCTL_BOOT_ROM_POR) + { + resetCauses |= SYSCTL_RESC_POR; + } + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_XRS) == + (uint32_t)SYSCTL_BOOT_ROM_XRS) + { + resetCauses |= SYSCTL_RESC_XRSN; + } + + // + // Return the reset reasons. + // + return(resetCauses); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param rstCauses are the reset causes to be cleared; must be a logical +//! OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtl_getResetCause(). +//! +//! \note Some reset causes are cleared by the boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearResetCause(uint32_t rstCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(CPUSYS_BASE + SYSCTL_O_RESC) = rstCauses; +} + +//***************************************************************************** +// +//! Sets the low speed peripheral clock rate prescaler. +//! +//! \param prescaler is the LSPCLK rate relative to SYSCLK +//! +//! This function configures the clock rate of the low speed peripherals. The +//! \e prescaler parameter is the value by which the SYSCLK rate is divided to +//! get the LSPCLK rate. For example, a \e prescaler of +//! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter +//! of the SYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = + (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + ~(uint32_t)SYSCTL_LOSPCP_LSPCLKDIV_M) | (uint32_t)prescaler; + EDIS; +} + +//***************************************************************************** +// +//! Sets the ePWM clock divider. +//! +//! \param divider is the value by which PLLSYSCLK is divided +//! +//! This function configures the clock rate of the EPWMCLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an +//! EPWMCLK rate that is half the PLLSYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) & + ~SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF1 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF1CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF1CLK rate. For example, \b SYSCTL_EMIF1CLK_DIV_2 will select an +//! EMIF1CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF1ClockDivider(SysCtl_EMIF1CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF1CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF2 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF2CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF2CLK rate. For example, \b SYSCTL_EMIF2CLK_DIV_2 will select an +//! EMIF2CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF2ClockDivider(SysCtl_EMIF2CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF2CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Selects a clock source to mux to an external GPIO pin (XCLKOUT). +//! +//! \param source is the internal clock source to be configured. +//! +//! This function configures the specified clock source to be muxed to an +//! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a +//! value of one of the following values: +//! - \b SYSCTL_CLOCKOUT_PLLSYS +//! - \b SYSCTL_CLOCKOUT_PLLRAW +//! - \b SYSCTL_CLOCKOUT_SYSCLK +//! - \b SYSCTL_CLOCKOUT_INTOSC1 +//! - \b SYSCTL_CLOCKOUT_INTOSC2 +//! - \b SYSCTL_CLOCKOUT_XTALOSC +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectClockOutSource(SysCtl_ClockOut source) +{ + EALLOW; + + // + // Clear clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) &= + ~SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M; + SYSCTL_CLKSRCCTL_DELAY; + + // + // Set clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) |= (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the external oscillator counter value. +//! +//! This function returns the X1 clock counter value. When the return value +//! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external +//! oscillator (XTAL), an application should call this function to make sure +//! the counter is saturated. +//! +//! \return Returns the value of the 10-bit X1 clock counter. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getExternalOscCounterValue(void) +{ + return(HWREGH(CLKCFG_BASE + SYSCTL_O_X1CNT) & SYSCTL_X1CNT_X1CNT_M); +} + +//***************************************************************************** +// +//! Turns on the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns on the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOnOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Turns off the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns off the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOffOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn off INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enters IDLE mode. +//! +//! This function puts the device into IDLE mode. The CPU clock is gated while +//! all peripheral clocks are left running. Any enabled interrupt will wake the +//! CPU up from IDLE mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterIdleMode(void) +{ + EALLOW; + + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters STANDBY mode. +//! +//! This function puts the device into STANDBY mode. This will gate both the +//! CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is +//! left active, and an NMI or an optional watchdog interrupt will wake the +//! CPU subsystem from STANDBY mode. +//! +//! GPIOs may be configured to wake the CPU subsystem. See +//! SysCtl_enableLPMWakeupPin(). +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterStandbyMode(void) +{ + EALLOW; + + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters HALT mode. +//! +//! This function puts the device into HALT mode. This will gate almost all +//! systems and clocks and allows for the power-down of oscillators and analog +//! blocks. The watchdog may be left clocked to produce a reset. See +//! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be +//! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin(). +//! +//! Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHaltMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + asm(" IDLE"); + +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into HALT mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HALT; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +// +//! Enters Hibernate mode. +//! +//! This function puts the device into Hibernate mode. Hibernate (HIB) is a +//! global low-power mode that gates the supply voltages to most of the system. +//! This mode affects both CPU subsystems. HIB is essentially a controlled +//! power-down with remote wakeup capability, and can be used to save power +//! during long periods of inactivity. +//! +//! To wake the device from HIB mode: +//! 1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the +//! power-up of the device clock sources. +//! 2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the +//! rest of the device. +//! +//! To enter Hibernate mode in dual CPU put CPU2 in STANDBY mode first. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHibernateMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + asm(" IDLE"); +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into Hibernate mode when IDLE is executed + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HIB; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +//! Enables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function connects a pin to the LPM circuit, allowing an event on the +//! pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of +//! being connected to the LPM circuit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) |= pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) |= pinMask; + } + + EDIS; +} + +//***************************************************************************** +//! Disables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function disconnects a pin to the LPM circuit, disallowing an event on +//! the pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) &= ~pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the number of cycles to qualify an input on waking from STANDBY mode. +//! +//! \param cycles is the number of OSCCLK cycles. +//! +//! This function sets the number of OSCCLK clock cycles used to qualify the +//! selected inputs when waking from STANDBY mode. The \e cycles parameter +//! should be passed a cycle count between 2 and 65 cycles inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setStandbyQualificationPeriod(uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT((cycles >= 2U) && (cycles <= 65U)); + + EALLOW; + + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint16_t)SYSCTL_LPMCR_QUALSTDBY_M) | + ((cycles - 2U) << SYSCTL_LPMCR_QUALSTDBY_S); + + EDIS; +} + +//***************************************************************************** +// +//! Enable the device to wake from STANDBY mode upon a watchdog interrupt. +//! +//! \note In order to use this option, you must configure the watchdog to +//! generate an interrupt using SysCtl_setWatchdogMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Set the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) |= SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the device from waking from STANDBY mode upon a watchdog interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Clear the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) &= ~SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the watchdog to run while in HALT mode. +//! +//! This function configures the watchdog to continue to run while in HALT +//! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the +//! system enters HALT mode. By default the watchdog is gated when the system +//! enters HALT. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogInHalt(void) +{ + EALLOW; + + // + // Set the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the watchdog from running while in HALT mode. +//! +//! This function gates the watchdog when the system enters HALT mode. INTOSC1 +//! and INTOSC2 will be powered down. This is the default behavior of the +//! device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogInHalt(void) +{ + EALLOW; + + // + // Clear the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the watchdog generates a reset or an interrupt signal. +//! +//! \param mode is a flag to select the watchdog mode. +//! +//! This function configures the action taken when the watchdog counter reaches +//! its maximum value. When the \e mode parameter is +//! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog +//! interrupt signal and disables the generation of a reset signal. This will +//! allow the watchdog module to wake up the device from IDLE +//! or STANDBY if desired (see SysCtl_enableWatchdogStandbyWakeup()). +//! +//! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will +//! be put into reset mode and generation of a watchdog interrupt signal will +//! be disabled. This is how the watchdog is configured by default. +//! +//! \note Check the status of the watchdog interrupt using +//! SysCtl_isWatchdogInterruptActive() before calling this function. If the +//! interrupt is still active, switching from interrupt mode to reset mode will +//! immediately reset the device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogMode(SysCtl_WDMode mode) +{ + EALLOW; + + // + // Either set or clear the WDENINT bit to that will determine whether the + // watchdog will generate a reset signal or an interrupt signal. Take care + // not to write a 1 to WDOVERRIDE. + // + if(mode == SYSCTL_WD_MODE_INTERRUPT) + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) = + (HWREGH(WD_BASE + SYSCTL_O_SCSR) & ~SYSCTL_SCSR_WDOVERRIDE) | + SYSCTL_SCSR_WDENINT; + } + else + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) &= ~(SYSCTL_SCSR_WDENINT | + SYSCTL_SCSR_WDOVERRIDE); + } + + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of the watchdog interrupt signal. +//! +//! This function returns the status of the watchdog interrupt signal. If the +//! interrupt is active, this function will return \b true. If \b false, the +//! interrupt is NOT active. +//! +//! \note Make sure to call this function to ensure that the interrupt is not +//! active before making any changes to the configuration of the watchdog to +//! prevent any unexpected behavior. For instance, switching from interrupt +//! mode to reset mode while the interrupt is active will immediately reset the +//! device. +//! +//! \return \b true if the interrupt is active and \b false if it is not. +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogInterruptActive(void) +{ + // + // If the status bit is cleared, the WDINTn signal is active. + // + return((HWREGH(WD_BASE + SYSCTL_O_SCSR) & SYSCTL_SCSR_WDINTS) == 0U); +} + +//***************************************************************************** +// +//! Disables the watchdog. +//! +//! This function disables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdog(void) +{ + EALLOW; + + // + // Set the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) |= SYSCTL_WD_CHKBITS | SYSCTL_WDCR_WDDIS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Enables the watchdog. +//! +//! This function enables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdog(void) +{ + EALLOW; + + // + // Clear the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~SYSCTL_WDCR_WDDIS) | SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Checks if the watchdog is enabled or not +//! +//! This function returns the watchdog status whether it is enabled or disabled +//! +//! \return \b true if the watchdog is enabled & \b false if the watchdog is +//! disabled +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogEnabled(void) +{ + + // + // Get the watchdog enable status + // + return ((HWREGH(WD_BASE + SYSCTL_O_WDCR) & SYSCTL_WDCR_WDDIS) == 0U); +} + +//***************************************************************************** +// +//! Services the watchdog. +//! +//! This function resets the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_serviceWatchdog(void) +{ + EALLOW; + + // + // Enable the counter to be reset and then reset it. + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the first key to enter the watchdog reset. +//! +//! This function writes the first key to enter the watchdog reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogReset(void) +{ + EALLOW; + + // + // Enable the counter to be reset + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the second key to reset the watchdog. +//! +//! This function writes the second key to reset the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetWatchdog(void) +{ + EALLOW; + + // + // Reset the watchdog counter + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up watchdog clock (WDCLK) prescaler. +//! +//! \param prescaler is the value that configures the watchdog clock relative +//! to the value from the pre-divider. +//! +//! This function sets up the watchdog clock (WDCLK) prescaler. The +//! \e prescaler parameter divides INTOSC1 down to WDCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler) +{ + uint16_t regVal; + + regVal = (uint16_t)prescaler | (uint16_t)SYSCTL_WD_CHKBITS; + + EALLOW; + + // + // Write the prescaler to the appropriate register. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~(SYSCTL_WDCR_WDPS_M)) | regVal; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the watchdog counter value. +//! +//! \return Returns the current value of the 8-bit watchdog counter. If this +//! count value overflows, a watchdog output pulse is generated. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getWatchdogCounterValue(void) +{ + // + // Read and return the value of the watchdog counter. + // + return(HWREGH(WD_BASE + SYSCTL_O_WDCNTR)); +} + +//***************************************************************************** +// +//! Gets the watchdog reset status. +//! +//! This function returns the watchdog reset status. If this function returns +//! \b true, that indicates that a watchdog reset generated the last reset +//! condition. Otherwise, it was an external device or power-up reset +//! condition. +//! +//! \return Returns \b true if the watchdog generated the last reset condition. +// +//***************************************************************************** +static inline bool +SysCtl_getWatchdogResetStatus(void) +{ + // + // Read and return the status of the watchdog reset status flag. + // + return((HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) & SYSCTL_RESC_WDRSN) != 0U); +} + +//***************************************************************************** +// +//! Clears the watchdog reset status. +//! +//! This function clears the watchdog reset status. To check if it was set +//! first, see SysCtl_getWatchdogResetStatus(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogResetStatus(void) +{ + EALLOW; + + // + // Read and return the status of the watchdog reset status flag. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) = SYSCTL_RESC_WDRSN; + + EDIS; +} + +//***************************************************************************** +// +//! Set the minimum threshold value for windowed watchdog +//! +//! \param value is the value to set the window threshold +//! +//! This function sets the minimum threshold value used to define the lower +//! limit of the windowed watchdog functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogWindowValue(uint16_t value) +{ + EALLOW; + + // + // Clear the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) &= ~SYSCTL_WDWCR_MIN_M; + + // + // Set the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) |= (value & SYSCTL_WDWCR_MIN_M); + + EDIS; +} + +//***************************************************************************** +// +//! Clears the watchdog override. +//! +//! This function clears the watchdog override and locks the watchdog timer +//! module to remain in its prior state which could be either enable /disable. +//! The watchdog timer will remain in this state until the next system reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogOverride(void) +{ + EALLOW; + + HWREGH(WD_BASE + SYSCTL_O_SCSR) |= SYSCTL_SCSR_WDOVERRIDE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the NMI Global interrupt bit +//! +//! \b Note: This bit should be set after the device security related +//! initialization is complete. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableNMIGlobalInterrupt(void) +{ + EALLOW; + + HWREGH(NMI_BASE + NMI_O_CFG) |= NMI_CFG_NMIE; + + EDIS; +} + +//***************************************************************************** +// +//! Read NMI interrupts. +//! +//! Read the current state of NMI interrupt. +//! +//! \return \b true if NMI interrupt is triggered, \b false if not. +// +//***************************************************************************** +static inline bool +SysCtl_getNMIStatus(void) +{ + // + // Read and return the current value of the NMI flag register, masking out + // all but the NMI bit. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & NMI_FLG_NMIINT) != 0U); +} + +//***************************************************************************** +// +//! Read NMI Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMIFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIFlagStatus(void) +{ + // + // Read and return the current value of the NMI flag register. + // + return(HWREGH(NMI_BASE + NMI_O_FLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI interrupts are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Function to clear individual NMI interrupts. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Clear NMI interrupt flags that correspond with the passed in bit mask. +//! +//! \b Note: The NMI Interrupt flag is always cleared by default and +//! therefore doesn't have to be included in the bit mask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearNMIStatus(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Clear the individual flags as well as NMI Interrupt flag + // + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Clear all the NMI Flags that are currently set. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearAllNMIFlags(void) +{ + uint16_t nmiFlags; + + // + // Read the flag status register and then write to the clear register, + // clearing all the flags that were returned plus the NMI flag. + // + EALLOW; + + nmiFlags = SysCtl_getNMIFlagStatus(); + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Function to force individual NMI interrupt fail flags +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_forceNMIFlags(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Set the Flags for the individual interrupts in the NMI flag + // force register + // + HWREGH(NMI_BASE + NMI_O_FLGFRC) |= nmiFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog counter value. +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns the NMI watchdog counter register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogCounter(void) +{ + // + // Read and return the NMI watchdog counter register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDCNT)); +} + +//***************************************************************************** +// +//! Sets the NMI watchdog period value. +//! +//! \param wdPeriod is the 16-bit value at which a reset is generated. +//! +//! This function writes to the NMI watchdog period register that holds the +//! value to which the NMI watchdog counter is compared. When the two registers +//! match, a reset is generated. By default, the period is 0xFFFF. +//! +//! \note If a value smaller than the current counter value is passed into the +//! \e wdPeriod parameter, a NMIRSn will be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod) +{ + EALLOW; + + // + // Write to the period register. + // + HWREGH(NMI_BASE + NMI_O_WDPRD) = wdPeriod; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog period value. +//! +//! \return Returns the NMI watchdog period register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogPeriod(void) +{ + // + // Read and return the NMI watchdog period register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDPRD)); +} + +//***************************************************************************** +// +//! Read NMI Shadow Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMISHDFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint32_t +SysCtl_getNMIShadowFlagStatus(void) +{ + // + // Read and return the current value of the NMI shadow flag register. + // + return(HWREGH(NMI_BASE + NMI_O_SHDFLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI shadow flags are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIShadowFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_SHDFLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Enable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_MCLKOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Get the missing clock detection Failure Status +//! +//! \note A failure means the oscillator clock is missing +//! +//! \return Returns \b true if a failure is detected or \b false if a +//! failure isn't detected +// +//***************************************************************************** +static inline bool +SysCtl_isMCDClockFailureDetected(void) +{ + // + // Check the status bit to determine failure + // + return((HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) & SYSCTL_MCDCR_MCLKSTS) != 0U); +} + +//***************************************************************************** +// +//! Reset the missing clock detection logic after clock failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Re-connect missing clock detection clock source to stop simulating clock +//! failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_connectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_OSCOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disconnect missing clock detection clock source to simulate clock failure. +//! This is for testing the MCD functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disconnectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_OSCOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the sync input source for the ePWM and eCAP signals. +//! +//! \param syncInput is the sync input being configured +//! \param syncSrc is sync input source selection. +//! +//! This function configures the sync input source for the ePWM and eCAP +//! modules. The \e syncInput parameter is the sync input being configured. It +//! should be passed a value of \b SYSCTL_SYNC_IN_XXXX, where XXXX is the ePWM +//! or eCAP instance the sync signal is entering. +//! +//! The \e syncSrc parameter is the sync signal selected as the source of the +//! sync input. It should be passed a value of \b SYSCTL_SYNC_IN_SRC_XXXX, +//! XXXX is a sync signal coming from an ePWM, eCAP or external sync output. +//! where For example, a \e syncInput value of \b SYSCTL_SYNC_IN_ECAP1 and a +//! \e syncSrc value of \b SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT will make the +//! EPWM1SYNCOUT signal drive eCAP1's SYNCIN signal. +//! +//! Note that some \e syncSrc values are only valid for certain values of +//! \e syncInput. See device technical reference manual for details on +//! time-base counter synchronization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncInputConfig(SysCtl_SyncInput syncInput, + SysCtl_SyncInputSource syncSrc) +{ + uint32_t clearMask; + + // + // Write the input sync source selection to the appropriate register. + // + EALLOW; + clearMask = (uint32_t)SYSCTL_SYNCSELECT_SYNCIN_M << (uint32_t)syncInput; + + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & ~clearMask) | + ((uint32_t)syncSrc << (uint32_t)syncInput); + + EDIS; +} +//***************************************************************************** +// +//! Configures the sync output source. +//! +//! \param syncSrc is sync output source selection. +//! +//! This function configures the sync output source from the ePWM modules. The +//! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is +//! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc) +{ + // + // Write the sync output source selection to the appropriate register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & + ~((uint32_t)SYSCTL_SYNCSELECT_SYNCOUT_M)) | + ((uint32_t)syncSrc << SYSCTL_SYNCSELECT_SYNCOUT_S); + EDIS; + +} +//***************************************************************************** +// +//! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be enabled +//! +//! This function configures which ePWM SOC signals are enabled as a source for +//! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR +//! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Set the bits that correspond to signal to be enabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) |= adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Disables ePWM SOC signals from driving an external ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be disabled +//! +//! This function configures which ePWM SOC signals are disabled as a source +//! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical +//! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Clear the bits that correspond to signal to be disabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) &= ~adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Locks the SOC Select of the Trig X-BAR. +//! +//! This function locks the external ADC SOC select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockExtADCSOCSelect(void) +{ + // + // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = + SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT; + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the dual ported bridge is connected with DMA or +//! CLA as the secondary controller. +//! +//! \param periFrame1Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 1. +//! \param periFrame2Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 2. +//! +//! One of the following values can be passed as parameter. +//! \b SYSCTL_SEC_CONTROLLER_CLA +//! \b SYSCTL_SEC_CONTROLLER_DMA +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectSecController(uint16_t periFrame1Config, uint16_t periFrame2Config) +{ + EALLOW; + + HWREG(CPUSYS_BASE + SYSCTL_O_SECMSEL) = + (((periFrame1Config << SYSCTL_SECMSEL_PF1SEL_S) & + SYSCTL_SECMSEL_PF1SEL_M) | + ((periFrame2Config << SYSCTL_SECMSEL_PF2SEL_S) & + SYSCTL_SECMSEL_PF2SEL_M)); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the Sync Select of the Trig X-BAR. +//! +//! This function locks Sync Input and Output Select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockSyncSelect(void) +{ + // + // Lock the SYNCSELECT register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = SYSCTL_SYNCSOCLOCK_SYNCSELECT; + EDIS; +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeriphInstance +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheralInstance(SysCtl_CPUSelPeriphInstance peripheral, + SysCtl_CPUSel cpuInst) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Identify the register index and bit position + // + regIndex = 2U * ((uint16_t)peripheral & SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Configure the CPU owner for the specified peripheral instance + // + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) = + (HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) & ~(1UL << bitIndex)) | + ((uint32_t)cpuInst << bitIndex); + + EDIS; + +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param peripheralInst is the instance for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! The \e peripheralInst parameter is the instance number for example +//! 1 for EPWM1, 2 for EPWM2 so on.For instances which are named with alphabets +//! (instead of numbers) the following convention needs to be followed. +//! 1 for A (SPI_A), 2 for B (SPI_B), 3 for C (SPI_C) so on... +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \note This function is retained for compatibility puposes. Recommended to +//! to use the function \e SysCtl_selectCPUForPeripheralInstance() +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheral(SysCtl_CPUSelPeripheral peripheral, + uint16_t peripheralInst, SysCtl_CPUSel cpuInst) +{ + uint32_t tempValue; + uint16_t shift; + + if(SYSCTL_CPUSEL14_DAC == peripheral) + { + shift = peripheralInst + SYSCTL_CPUSEL_DAC_S - 1U; + } + else + { + shift = peripheralInst - 1U; + } + + tempValue = + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) & + (~(1UL << shift)); + + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) = + tempValue | ((uint32_t)cpuInst << shift); + EDIS; +} +//***************************************************************************** +// +//! Get the Device Silicon Revision ID +//! +//! This function returns the silicon revision ID for the device. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the silicon revision ID value. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceRevision(void) +{ + // + // Returns the device silicon revision ID + // + return(HWREG(DEVCFG_BASE + SYSCTL_O_REVID)); +} + +//***************************************************************************** +// +//! Locks the CPU select registers for the peripherals +//! +//! \param peripheral is the peripheral for which CPU needs to be selected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockCPUSelectRegs(SysCtl_CPUSelPeripheral peripheral) +{ + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_DEVCFGLOCK1) |= (1UL << (uint32_t)peripheral); + EDIS; +} + + +//***************************************************************************** +// +//! Gets the error status of the Efuse +//! +//! The function provides both the Efuse Autoload & the Efuse Self Test +//! Error Status. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Fuse Error status. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getEfuseError(void) +{ + return(HWREGH(DEVCFG_BASE + SYSCTL_O_FUSEERR)); +} + +//***************************************************************************** +// +//! Sets up XCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the XCLK divider. There is only one +//! divider that scales INTOSC1 to XCLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_XClkDivider +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setXClk(SysCtl_XClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) & + ~(SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M)) | + (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up PLLSYSCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the PLLSYSCLK divider. There is only one +//! divider that scales PLLSYSCLK to generate the system clock. +//! +//! The \e divider parameter can have one value from the set below: +//! 0x0 = /1 +//! 0x1 = /2 +//! 0x2 = /4 (default on reset) +//! 0x3 = /6 +//! 0x4 = /8 +//! ...... +//! 0x3F =/126 +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setPLLSysClk(uint16_t divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)) | divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up AUXPLLCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the AUXPLLCLK divider. There is only one +//! divider that scales AUXPLLCLK to generate the system clock. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_AuxPLLClkDivider +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setAuxPLLClk(SysCtl_AuxPLLClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + ~(SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up CPU Timer 2 CLK source & divider. +//! +//! \param divider is the value that configures the divider. +//! \param source is the source for the clock divider +//! +//! This function sets up the CPU Timer 2 CLK divider based on the source that +//! is selected. There is only one divider that scales the "source" to +//! CPU Timer 2 CLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkDivider +//! The \e source parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkSource +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setCputimer2Clk(SysCtl_Cputimer2ClkDivider divider, + SysCtl_Cputimer2ClkSource source) +{ + // + // Clears the divider & the source, then configures it. + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~(SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M | + SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M)); + SYSCTL_REGWRITE_DELAY; + + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= + ((uint16_t)divider << SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S) | + ((uint16_t)source << SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S); + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Gets the PIE Vector Fetch Error Handler Routine Address. +//! +//! The function indicates the address of the PIE Vector Fetch Error +//! handler routine. +//! +//! \return Error Handler Address. +//! +//! \note Its the responsibility of user to initialize this register. If this +//! register is not initialized, a default error handler at address +//! 0x3fffbe will get executed. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getPIEVErrAddr(void) +{ + return(HWREG(CPUSYS_BASE + SYSCTL_O_PIEVERRADDR)); +} + +//***************************************************************************** +// +//! Check if the Internal PHY is present or not for the USB module +//! +//! Provides the USB module Internal PHY presence +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return \b true if Internal USB PHY Module is present \b false if +//! Internal USB PHY Module is not present +// +//***************************************************************************** +static inline bool +SysCtl_isPresentUSBPHY(void) +{ + return((HWREG(DEVCFG_BASE + SYSCTL_O_PERCNF1) & + SYSCTL_PERCNF1_USB_A_PHY) != 0U); +} + +//***************************************************************************** +// +//! Get the device UID_UNIQUE value +//! +//! This function returns the device UID_UNIQUE value +//! +//! \return Returns the device UID_UNIQUE value +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceUID(void) +{ + // + // Returns the device UID_UNIQUE value + // + return(HWREG(UID_BASE + OTP_O_UID_UNIQUE)); +} + +//***************************************************************************** +// +//! Delays for a fixed number of cycles. +//! +//! \param count is the number of delay loop iterations to perform. +//! +//! This function generates a constant length delay using assembly code. The +//! loop takes 5 cycles per iteration plus 9 cycles of overhead. +//! +//! \note If count is equal to zero, the loop will underflow and run for a +//! very long time. +//! +//! \note Refer to the macro DEVICE_DELAY_US(x) in device.h which can be used to +//! insert a delay in microseconds. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_delay(uint32_t count); + +//***************************************************************************** +// +//! Calculates the system clock frequency (SYSCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the system clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the PLL +//! and clock divider configuration registers. +//! +//! \return Returns the system clock frequency. If a missing clock is detected, +//! the function will return the INTOSC1 frequency. This needs to be +//! corrected and cleared (see SysCtl_resetMCD()) before trying to call this +//! function again. +// +//***************************************************************************** +extern uint32_t +SysCtl_getClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Calculates the system auxiliary clock frequency (AUXPLLCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source +//! (AUXOSCCLK). +//! +//! This function determines the frequency of the auxiliary clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the AUXPLL +//! and clock divider configuration registers. +//! +//! \return Returns the auxiliary clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getAuxClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Configures the clocking of the device. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x) +//! where x is either 1 or an even value up to 126. +//! +//! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or +//! \b SYSCTL_PLL_DISABLE. +//! +//! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value +//! from 1 to 127. +//! +//! - The fractional multiplier is chosen with either \b SYSCTL_FMULT_0, +//! \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or \b SYSCTL_FMULT_3_4. +//! +//! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2, +//! \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! This function uses the watchdog as a monitor for the PLL. The user +//! watchdog settings will be modified and restored upon completion. Make sure +//! that the WDOVERRIDE bit isn't set before calling this function. Re-lock +//! attempt is carried out if either SLIP condition occurs or SYSCLK to input +//! clock ratio is off by 10%. +//! +//! This function uses the following resources to support PLL initialization: +//! - Watchdog +//! - CPU Timer 1 +//! - CPU Timer 2 +//! +//! +//! \note See your device errata for more details about locking the PLL. +//! +//! \return Returns \b false if a missing clock error is detected. This needs +//! to be cleared (see SysCtl_resetMCD()) before trying to call this function +//! again. Otherwise, returns \b true. +// +//***************************************************************************** +extern bool +SysCtl_setClock(uint32_t config); + +//***************************************************************************** +// +//! Configures the external oscillator for the clocking of the device. +//! +//! This function configures the external oscillator (XTAL) to be used for the +//! clocking of the device in crystal mode. It follows the procedure to turn on +//! the oscillator, wait for it to power up, and select it as the source of the +//! system clock. +//! +//! Please note that this function blocks while it waits for the XTAL to power +//! up. If the XTAL does not manage to power up properly, the function will +//! loop for a long time. It is recommended that you modify this function to +//! add an appropriate timeout and error-handling procedure. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectXTAL(void); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the clocking of the device. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! device. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSource(uint32_t oscSource); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the AUXPLL. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! AUXPLL. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource); + +//***************************************************************************** +// +//! Calculates the low-speed peripheral clock frequency (LSPCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the low-speed peripheral clock +//! based on the frequency of the oscillator clock source (from \e clockInHz) +//! and the PLL and clock divider configuration registers. +//! +//! \return Returns the low-speed peripheral clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Get the device part parametric value +//! +//! \param parametric is the requested device parametric value +//! +//! This function gets the device part parametric value. +//! +//! The \e parametric parameter can have one the following enumerated values: +//! - \b SYSCTL_DEVICE_QUAL - Device Qualification Status +//! - \b SYSCTL_DEVICE_PINCOUNT - Device Pin Count +//! - \b SYSCTL_DEVICE_INSTASPIN - Device InstaSPIN Feature Set +//! - \b SYSCTL_DEVICE_FLASH - Device Flash size (KB) +//! - \b SYSCTL_DEVICE_PARTID - Device Part ID Format Revision +//! - \b SYSCTL_DEVICE_FAMILY - Device Family +//! - \b SYSCTL_DEVICE_PARTNO - Device Part Number +//! - \b SYSCTL_DEVICE_CLASSID - Device Class ID +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the specified parametric value. +// +//***************************************************************************** +extern uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric); + +//***************************************************************************** +// +//! Configures the auxiliary PLL for clocking USB. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clock source for auxiliary PLL, the integer +//! multiplier, fractional multiplier and divider. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with one of the following macros: +//! \b SYSCTL_AUXPLL_DIV_1, +//! \b SYSCTL_AUXPLL_DIV_2, +//! \b SYSCTL_AUXPLL_DIV_4, +//! \b SYSCTL_AUXPLL_DIV_8 +//! +//! - The use of the PLL is chosen with either \b SYSCTL_AUXPLL_ENABLE or +//! \b SYSCTL_AUXPLL_DISABLE. +//! +//! - The integer multiplier is chosen with \b SYSCTL_AUXPLL_IMULT(x) where x +//! is a value from 1 to 127. +//! +//! - The oscillator source chosen with one of +//! \b SYSCTL_AUXPLL_OSCSRC_OSC2, +//! \b SYSCTL_AUXPLL_OSCSRC_XTAL, +//! \b SYSCTL_AUXPLL_OSCSRC_AUXCLKIN, +//! +//! \note This function uses CPU Timer 2 to monitor a successful lock of the +//! AUXPLL. For this function to properly detect the PLL startup +//! SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +//! User configuration of CPU Timer 2 will be backed up and restored. +//! \note See your device errata for more details about locking the PLL. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_setAuxClock(uint32_t config); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//**************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SYSCTL_H diff --git a/gpio_bitfield_cpu1/device/driverlib/upp.c b/gpio_bitfield_cpu1/device/driverlib/upp.c new file mode 100644 index 0000000..a3fb8da --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/upp.c @@ -0,0 +1,298 @@ +//########################################################################### +// +// FILE: upp.c +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "upp.h" + +//***************************************************************************** +// +// UPP_setDMAReadThreshold +// +//***************************************************************************** +void +UPP_setDMAReadThreshold(uint32_t base, UPP_DMAChannel channel, + UPP_ThresholdSize size) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Set DMA read threshold for channel I. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEI_M) | + (uint16_t)size; + } + else + { + // + // Set DMA read threshold for channel Q. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEQ_M) | + ((uint16_t)size << UPP_THCFG_RDSIZEQ_S); + } +} + +//***************************************************************************** +// +// UPP_setDMADescriptor +// +//***************************************************************************** +void +UPP_setDMADescriptor(uint32_t base, UPP_DMAChannel channel, + const UPP_DMADescriptor * const desc) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Sets DMA descriptors for channel I. + // + HWREG(base + UPP_O_CHIDESC0) = desc->addr; + HWREG(base + UPP_O_CHIDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHIDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHIDESC2) = desc->lineOffset; + } + else + { + // + // Sets DMA descriptors for channel Q. + // + HWREG(base + UPP_O_CHQDESC0) = desc->addr; + HWREG(base + UPP_O_CHQDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHQDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHQDESC2) = desc->lineOffset; + } +} + +//***************************************************************************** +// +// UPP_getDMAChannelStatus +// +//***************************************************************************** +void +UPP_getDMAChannelStatus(uint32_t base, UPP_DMAChannel channel, + UPP_DMAChannelStatus * const status) +{ + uint32_t cntStatus; + + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the current status for channel I. + // + cntStatus = HWREG(base + UPP_O_CHIST1); + status->curAddr = HWREG(base + UPP_O_CHIST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHIDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHIDESC1_LCNT_S); + } + else + { + // + // Return the current status for channel Q. + // + cntStatus = HWREG(base + UPP_O_CHQST1); + status->curAddr = HWREG(base + UPP_O_CHQST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHQDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHQDESC1_LCNT_S); + } +} + +//***************************************************************************** +// +// UPP_isDescriptorPending +// +//***************************************************************************** +bool +UPP_isDescriptorPending(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the pend status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_PEND) == UPP_CHIST2_PEND); + } + else + { + // + // Return the pend status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_PEND) == UPP_CHQST2_PEND); + } + return(status); +} + +//***************************************************************************** +// +// UPP_isDescriptorActive +// +//***************************************************************************** +bool +UPP_isDescriptorActive(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Returns active status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_ACT) == UPP_CHIST2_ACT); + } + else + { + // + // Returns active status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_ACT) == UPP_CHQST2_ACT); + } + return(status); +} + +//***************************************************************************** +// +// UPP_getDMAFIFOWatermark +// +//***************************************************************************** +uint16_t +UPP_getDMAFIFOWatermark(uint32_t base, UPP_DMAChannel channel) +{ + uint16_t status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_WM_M) >> UPP_CHIST2_WM_S); + } + else + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_WM_M) >> UPP_CHQST2_WM_S); + } + return(status); +} + +//***************************************************************************** +// +// UPP_readRxMsgRAM +// +//***************************************************************************** +void +UPP_readRxMsgRAM(uint32_t rxBase, uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isRxBaseValid(rxBase)); + ASSERT((length + offset) < UPP_RX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Read one 16-bit word. + // + array[i] = HWREGH(rxBase + offset + i); + } +} + +//***************************************************************************** +// +// UPP_writeTxMsgRAM +// +//***************************************************************************** +void +UPP_writeTxMsgRAM(uint32_t txBase, const uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isTxBaseValid(txBase)); + ASSERT((length + offset) < UPP_TX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Write one 16-bit word. + // + HWREGH(txBase + offset + i) = array[i]; + } +} diff --git a/gpio_bitfield_cpu1/device/driverlib/upp.h b/gpio_bitfield_cpu1/device/driverlib/upp.h new file mode 100644 index 0000000..128d077 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/upp.h @@ -0,0 +1,1574 @@ +//########################################################################### +// +// FILE: upp.h +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef UPP_H +#define UPP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup upp_api UPP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_upp.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines that can be passed as addr field of UPP_DMADescriptor to +// UPP_setDMADescriptor(). Since the addresses for Tx & Rx MSG RAMs are +// different for CPU & DMA views, these defines can be used as DMA descriptor +// addresses. +// +//***************************************************************************** +#define UPP_DMA_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_DMA_RX_MSGRAM_STARTADDR 0x00007000U + +//***************************************************************************** +// +// Defines that can be used in user program as start address for CPU/CLA write +// to TX MSG RAM for transmitting data & for CPU/CLA read from RX MSG RAM for +// receiving data. Since the addresses for Tx & Rx MSG RAMs are different for +// CPU & DMA views, these defines can be used for CPU read/writes. +// +//***************************************************************************** +#define UPP_CPU_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_CPU_RX_MSGRAM_STARTADDR UPP_RX_MSG_RAM_BASE + +//***************************************************************************** +// +// Defines to specify the size of the uPP Tx and Rx MSG RAMs. +// +//***************************************************************************** +#define UPP_TX_MSGRAM_MAX_SIZE 0x200U +#define UPP_RX_MSGRAM_MAX_SIZE 0x200U + +//***************************************************************************** +// +// Define to specify 32 cycle delay between software reset issue & release in +// UPP_performSoftReset(). +// +//***************************************************************************** +#ifndef UPP_32_CYCLE_NOP +#define UPP_32_CYCLE_NOP __asm(" RPT #31 || NOP") +#endif + +//***************************************************************************** +// +// Define to specify mask for setting emulation mode in UPP_setEmulationMode(). +// +//***************************************************************************** +#define UPP_SOFT_FREE_M ((uint16_t)UPP_PERCTL_SOFT | \ + (uint16_t)UPP_PERCTL_FREE) + +//***************************************************************************** +// +// Defines to specify masks for enabling/disabling uPP Tx/Rx control signals in +// UPP_setTxControlSignalMode() & UPP_setRxControlSignalMode() respectively. +// +//***************************************************************************** +#define UPP_TX_SIGNAL_MODE_M UPP_IFCFG_WAITA +#define UPP_RX_SIGNAL_MODE_M ((uint16_t)UPP_IFCFG_STARTA | \ + (uint16_t)UPP_IFCFG_ENAA) + +//***************************************************************************** +// +// Define to specify mask for configuring polarities for uPP control signals +// in UPP_setControlSignalPolarity(). +// +//***************************************************************************** +#define UPP_SIGNAL_POLARITY_M ((uint16_t)UPP_IFCFG_WAITPOLA | \ + (uint16_t)UPP_IFCFG_ENAPOLA | \ + (uint16_t)UPP_IFCFG_STARTPOLA) + +//***************************************************************************** +// +// Define to specify masks for returning interrupt status in +// UPP_getInterruptStatus() & UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_M ((uint16_t)UPP_ENINTST_DPEI | (uint16_t)UPP_ENINTST_UOEI | \ + (uint16_t)UPP_ENINTST_EOWI | (uint16_t)UPP_ENINTST_EOLI | \ + (uint16_t)UPP_ENINTST_DPEQ | (uint16_t)UPP_ENINTST_UOEQ | \ + (uint16_t)UPP_ENINTST_EOWQ | (uint16_t)UPP_ENINTST_EOLQ) + +//***************************************************************************** +// +// Values that can be passed to UPP_enableInterrupt(), +// UPP_disableInterrupt() and UPP_clearInterruptStatus() as the +// intFlags parameter and returned by UPP_getInterruptStatus() & +// UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_CHI_DMA_PROG_ERR 0x0001U //! +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "debug.h" +#include "sysctl.h" +#include "usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16U + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16U + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10U) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0U) || (ui32Endpoint == 1U) || (ui32Endpoint == 2U) || + (ui32Endpoint == 3U)); + ASSERT((ui32Size == 1U) || (ui32Size == 2U)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint8_t ui8Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1U) + { + // + // Get the value. + // + ui8Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui8Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui8Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USBA_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0U; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = 0U; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0U); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0U; + *pui32IntStatusEP = 0U; + uint32_t usbis = 0U; + uint32_t rxis = 0U; + uint32_t txis = 0U; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Do-While to make sure that all status registers are cleared before + // continuing. This eliminates the race condition which can cause the USB + // interrupt to stay high and never get triggered again. + // + do + { + // + // Get the general interrupt status. + // + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + + // + // Get the transmit interrupt status. + // + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + + // + // Get the receive interrupt status. + // + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // + // Get the general interrupt status, these bits go into the lower 8 bits + // of the returned value. + // + ui32Status |= usbis; + + // + // Get the transmit interrupt status. + // + *pui32IntStatusEP |= txis; + + // + // Get the receive interrupt status, these bits go into the second byte + // of the returned value. + // + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while((usbis != 0x0000U) || (txis != 0x0000U) || (rxis != 0x0000U)); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << + USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) + << USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0U); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + if((pui32Flags != NULL) && (pui32MaxPacketSize != NULL)) + { + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size + // has been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change. If they decode the returned mode, however, they + // may be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size + // max packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change.If they decode the returned mode, however, they may + // be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOSZ, 1U); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOSZ, 1U); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a given endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0U); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0U; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xFFU; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8U) & 0xFFU; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0U); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0U) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0U); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16U; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2U)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = (uint32_t)0xFU << (ui32Channel * 4U); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4U); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0U; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4U * (USBEPToIndex(ui32Endpoint) - 1U))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(15U); +} + diff --git a/gpio_bitfield_cpu1/device/driverlib/usb.h b/gpio_bitfield_cpu1/device/driverlib/usb.h new file mode 100644 index 0000000..ae3c7ad --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/usb.h @@ -0,0 +1,560 @@ +//########################################################################### +// +// FILE: usb.h +// +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef USB_H +#define USB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup usb_api USB +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001U +#define USB_ID_HOST 0x0002U +#define USB_ID_DEVICE 0x0000U +#define USB_PFLT_ACTIVE 0x0004U + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FFUL // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FFUL // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080UL // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040UL // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040UL // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020UL // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010UL // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008UL // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004UL // Babble signaled +#define USB_INTCTRL_RESET 0x00000004UL // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002UL // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001UL // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200UL // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100UL // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFFUL // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000UL // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000UL // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000UL // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000UL // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000UL // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000UL // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000UL // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000UL // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000UL // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000UL // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000UL // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000UL // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000UL // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000UL // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000UL // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000UL // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000UL // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000UL // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000UL // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000UL // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000UL // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000UL // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000UL // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000UL // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000UL // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000UL // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000UL // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000UL // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000UL // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000UL // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000UL // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000UL // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFEUL // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000UL // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000UL // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000UL // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000UL // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800UL // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400UL // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200UL // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100UL // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080UL // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040UL // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020UL // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010UL // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008UL // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004UL // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002UL // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFEUL // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000UL // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000UL // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000UL // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000UL // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800UL // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400UL // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200UL // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100UL // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080UL // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040UL // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020UL // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010UL // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008UL // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004UL // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002UL // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000UL // Current speed is undefined +#define USB_FULL_SPEED 0x00000001UL // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000UL // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000UL // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000UL // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000UL // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000UL // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000UL // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000UL // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000UL // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000UL // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFFUL // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080UL // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020UL // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004UL // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002UL // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001UL // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040UL // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010UL // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004UL // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001UL // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000UL // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000UL // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000UL // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000UL // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000UL // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080UL // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020UL // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004UL // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002UL // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001UL // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010UL // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004UL // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002UL // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001UL // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001UL // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002UL // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004UL // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008UL // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010UL // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000UL // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100UL // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200UL // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300UL // Control endpoint +#define USB_EP_MODE_MASK 0x00000300UL // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000UL // Low Speed +#define USB_EP_SPEED_FULL 0x00001000UL // Full Speed +#define USB_EP_HOST_IN 0x00000000UL // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000UL // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000UL // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000UL // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010UL +#define USB_HOST_PWRFLT_HIGH 0x00000030UL +#define USB_HOST_PWRFLT_EP_NONE 0x00000000UL +#define USB_HOST_PWRFLT_EP_TRI 0x00000140UL +#define USB_HOST_PWRFLT_EP_LOW 0x00000240UL +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340UL +#define USB_HOST_PWREN_MAN_LOW 0x00000000UL +#define USB_HOST_PWREN_MAN_HIGH 0x00000001UL +#define USB_HOST_PWREN_AUTOLOW 0x00000002UL +#define USB_HOST_PWREN_AUTOHIGH 0x00000003UL +#define USB_HOST_PWREN_FILTER 0x00010000UL + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64U + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000UL // Endpoint 0 +#define USB_EP_1 0x00000010UL // Endpoint 1 +#define USB_EP_2 0x00000020UL // Endpoint 2 +#define USB_EP_3 0x00000030UL // Endpoint 3 +#define USB_EP_4 0x00000040UL // Endpoint 4 +#define USB_EP_5 0x00000050UL // Endpoint 5 +#define USB_EP_6 0x00000060UL // Endpoint 6 +#define USB_EP_7 0x00000070UL // Endpoint 7 +#define USB_EP_8 0x00000080UL // Endpoint 8 +#define USB_EP_9 0x00000090UL // Endpoint 9 +#define USB_EP_10 0x000000A0UL // Endpoint 10 +#define USB_EP_11 0x000000B0UL // Endpoint 11 +#define USB_EP_12 0x000000C0UL // Endpoint 12 +#define USB_EP_13 0x000000D0UL // Endpoint 13 +#define USB_EP_14 0x000000E0UL // Endpoint 14 +#define USB_EP_15 0x000000F0UL // Endpoint 15 +#define NUM_USB_EP 16U // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) (((uint32_t)(x) << 4U) & 0xFFU) +#define USBEPToIndex(x) ((x) >> 4U) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000UL // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001UL // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002UL // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003UL // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004UL // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005UL // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006UL // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007UL // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008UL // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009UL // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010UL // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011UL // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012UL // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013UL // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014UL // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015UL // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016UL // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017UL // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018UL // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010UL +#define USBFIFOSizeToBytes(x) ((uint32_t)8U << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102UL // Normal OUT transaction +#define USB_TRANS_IN 0x00000102UL // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010AUL // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110AUL // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142UL // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001UL // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081UL // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080UL // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001DUL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009UL // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011UL // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009DUL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080UL // OTG controller mode is not set. + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +// +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0FUL // All Interrupt sources +#define USB_INT_STATUS 0xFF000000UL // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000UL // VBUS Error +#define USB_INT_SESSION_START 0x40000000UL // Session Start Detected +#define USB_INT_SESSION_END 0x20000000UL // Session End Detected +#define USB_INT_DISCONNECT 0x20000000UL // Disconnect Detected +#define USB_INT_CONNECT 0x10000000UL // Device Connect Detected +#define USB_INT_SOF 0x08000000UL // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000UL // Babble signaled +#define USB_INT_RESET 0x04000000UL // Reset signaled +#define USB_INT_RESUME 0x02000000UL // Resume detected +#define USB_INT_SUSPEND 0x01000000UL // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000UL // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000UL // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00UL // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00UL // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800UL // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400UL // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200UL // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800UL // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400UL // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200UL // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000EUL // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000EUL // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008UL // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004UL // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002UL // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008UL // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004UL // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002UL // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // USB_H diff --git a/gpio_bitfield_cpu1/device/driverlib/version.c b/gpio_bitfield_cpu1/device/driverlib/version.c new file mode 100644 index 0000000..ced29c1 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/version.c @@ -0,0 +1,54 @@ +//########################################################################### +// +// FILE: version.c +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "version.h" + +//***************************************************************************** +// +// Version_getLibVersion +// +//***************************************************************************** +uint32_t +Version_getLibVersion(void) +{ + return(VERSION_NUMBER); +} diff --git a/gpio_bitfield_cpu1/device/driverlib/version.h b/gpio_bitfield_cpu1/device/driverlib/version.h new file mode 100644 index 0000000..8a3b431 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/version.h @@ -0,0 +1,101 @@ +//########################################################################### +// +// FILE: version.h +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef VERSION_H +#define VERSION_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup version_api Version +//! @{ +// +//***************************************************************************** +#include + +//! Version number to be returned by Version_getLibVersion() +//! +#define VERSION_NUMBER 26000000U + +//***************************************************************************** +// +//! Returns the driverlib version number +//! +//! This function can be used to check the version number of the driverlib.lib +//! that is in use. The version number will take the format yy.mm.pp.bb, so for +//! yy-Year, mm-Major Release version, pp-Patch Release Version, bb- Build Number. +//! example, if the function returns 26000000, the driverlib version being used +//! is 26.00.00.00. +//! +//! \return Returns an integer value indicating the driverlib version. +// +//***************************************************************************** +extern uint32_t +Version_getLibVersion(void); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // VERSION_H diff --git a/gpio_bitfield_cpu1/device/driverlib/xbar.c b/gpio_bitfield_cpu1/device/driverlib/xbar.c new file mode 100644 index 0000000..008145a --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/xbar.c @@ -0,0 +1,255 @@ +//########################################################################### +// +// FILE: xbar.c +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "xbar.h" + +//***************************************************************************** +// +// XBAR_setOutputMuxConfig +// +//***************************************************************************** +void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)output << 1U) + 2U; + } + else + { + offset = (uint16_t)output << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR output. + // + EALLOW; + + HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) = + (HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) & + ~((uint32_t)0x3U << shift)) | + (((uint32_t)muxConfig & 0x3U) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setEPWMMuxConfig +// +//***************************************************************************** +void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)trip << 1U) + 2U; + } + else + { + offset = (uint16_t)trip << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR trip. + // + EALLOW; + + HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setCLBMuxConfig +// +//***************************************************************************** +void +XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, XBAR_CLBMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)auxSignal << 1U) + 2U; + } + else + { + offset = (uint16_t)auxSignal << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR auxSignal. + // + EALLOW; + + + HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_getInputFlagStatus +// +//***************************************************************************** +bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_FLG1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_FLG2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_FLG3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Get the status of the X-BAR input latch. + // + inputMask = (uint32_t)1U << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + + return((HWREG(XBAR_BASE + offset) & inputMask) != 0U); +} + +//***************************************************************************** +// +// XBAR_clearInputFlag +// +//***************************************************************************** +void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag clear register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_CLR1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_CLR2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_CLR3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Set the bit that clears the X-BAR input latch. + // + inputMask = 1UL << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + HWREG(XBAR_BASE + offset) = inputMask; +} diff --git a/gpio_bitfield_cpu1/device/driverlib/xbar.h b/gpio_bitfield_cpu1/device/driverlib/xbar.h new file mode 100644 index 0000000..02e4e68 --- /dev/null +++ b/gpio_bitfield_cpu1/device/driverlib/xbar.h @@ -0,0 +1,1294 @@ +//########################################################################### +// +// FILE: xbar.h +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef XBAR_H +#define XBAR_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup xbar_api XBAR +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clbxbar.h" +#include "inc/hw_epwmxbar.h" +#include "inc/hw_inputxbar.h" +#include "inc/hw_outputxbar.h" +#include "inc/hw_xbar.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. +// Not intended for use by application code. +// +//***************************************************************************** +#define XBAR_OUTPUT_CFG_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUX0TO15CFG) +#define XBAR_OUTPUT_EN_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUXENABLE) +#define XBAR_EPWM_CFG_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUX0TO15CFG) +#define XBAR_EPWM_EN_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUXENABLE) +#define XBAR_CLB_CFG_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUX0TO15CFG) +#define XBAR_CLB_EN_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUXENABLE) +#define XBAR_INPUT_BASE (INPUTXBAR_BASE + XBAR_O_INPUT1SELECT) + +#define XBAR_INPUT_FLG_INPUT_M 0x00FFU +#define XBAR_INPUT_FLG_REG_M 0xFF00U +#define XBAR_INPUT_FLG_REG_1 0x0000U +#define XBAR_INPUT_FLG_REG_2 0x0100U +#define XBAR_INPUT_FLG_REG_3 0x0200U + +#define XBAR_GPIO_MAX_CNT 168U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following values define the muxes parameter for XBAR_enableEPWMMux(), +// XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and +// XBAR_disableOutputMux(). +// +//***************************************************************************** +#define XBAR_MUX00 0x00000001U //!< Mask for X-BAR mux 0 +#define XBAR_MUX01 0x00000002U //!< Mask for X-BAR mux 1 +#define XBAR_MUX02 0x00000004U //!< Mask for X-BAR mux 2 +#define XBAR_MUX03 0x00000008U //!< Mask for X-BAR mux 3 +#define XBAR_MUX04 0x00000010U //!< Mask for X-BAR mux 4 +#define XBAR_MUX05 0x00000020U //!< Mask for X-BAR mux 5 +#define XBAR_MUX06 0x00000040U //!< Mask for X-BAR mux 6 +#define XBAR_MUX07 0x00000080U //!< Mask for X-BAR mux 7 +#define XBAR_MUX08 0x00000100U //!< Mask for X-BAR mux 8 +#define XBAR_MUX09 0x00000200U //!< Mask for X-BAR mux 9 +#define XBAR_MUX10 0x00000400U //!< Mask for X-BAR mux 10 +#define XBAR_MUX11 0x00000800U //!< Mask for X-BAR mux 11 +#define XBAR_MUX12 0x00001000U //!< Mask for X-BAR mux 12 +#define XBAR_MUX13 0x00002000U //!< Mask for X-BAR mux 13 +#define XBAR_MUX14 0x00004000U //!< Mask for X-BAR mux 14 +#define XBAR_MUX15 0x00008000U //!< Mask for X-BAR mux 15 +#define XBAR_MUX16 0x00010000U //!< Mask for X-BAR mux 16 +#define XBAR_MUX17 0x00020000U //!< Mask for X-BAR mux 17 +#define XBAR_MUX18 0x00040000U //!< Mask for X-BAR mux 18 +#define XBAR_MUX19 0x00080000U //!< Mask for X-BAR mux 19 +#define XBAR_MUX20 0x00100000U //!< Mask for X-BAR mux 20 +#define XBAR_MUX21 0x00200000U //!< Mask for X-BAR mux 21 +#define XBAR_MUX22 0x00400000U //!< Mask for X-BAR mux 22 +#define XBAR_MUX23 0x00800000U //!< Mask for X-BAR mux 23 +#define XBAR_MUX24 0x01000000U //!< Mask for X-BAR mux 24 +#define XBAR_MUX25 0x02000000U //!< Mask for X-BAR mux 25 +#define XBAR_MUX26 0x04000000U //!< Mask for X-BAR mux 26 +#define XBAR_MUX27 0x08000000U //!< Mask for X-BAR mux 27 +#define XBAR_MUX28 0x10000000U //!< Mask for X-BAR mux 28 +#define XBAR_MUX29 0x20000000U //!< Mask for X-BAR mux 29 +#define XBAR_MUX30 0x40000000U //!< Mask for X-BAR mux 30 +#define XBAR_MUX31 0x80000000U //!< Mask for X-BAR mux 31 +#endif + +//***************************************************************************** +// +//! The following values define the \e output parameter for +//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and +//! XBAR_disableOutputMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR + XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR + XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR + XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR + XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR + XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR + XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR + XBAR_OUTPUT8 = 14, //!< OUTPUT8 of the Output X-BAR +} XBAR_OutputNum; + +//***************************************************************************** +// +//! The following values define the \e trip parameter for +//! XBAR_setEPWMMuxConfig(), XBAR_invertEPWMSignal(), XBAR_enableEPWMMux(), +//! and XBAR_disableEPWMMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR + XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR + XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR + XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR + XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR + XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR + XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR + XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR +} XBAR_TripNum; + +//***************************************************************************** +// +// The following values define the trip parameter for XBAR_setCLBMuxConfig(), +// XBAR_enableCLBMux(), and XBAR_disableCLBMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_AUXSIG0 = 0, + XBAR_AUXSIG1 = 2, + XBAR_AUXSIG2 = 4, + XBAR_AUXSIG3 = 6, + XBAR_AUXSIG4 = 8, + XBAR_AUXSIG5 = 10, + XBAR_AUXSIG6 = 12, + XBAR_AUXSIG7 = 14 +} XBAR_AuxSigNum; + +//***************************************************************************** +// +//! The following values define the \e input parameter for XBAR_setInputPin(). +// +//***************************************************************************** +typedef enum +{ + XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs + XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs + XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs + XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1 + XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2 + XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3 + XBAR_INPUT7, //!< eCAP1, X-BARs + XBAR_INPUT8, //!< eCAP2, X-BARs + XBAR_INPUT9, //!< eCAP3, X-BARs + XBAR_INPUT10, //!< eCAP4, X-BARs + XBAR_INPUT11, //!< eCAP5, X-BARs + XBAR_INPUT12, //!< eCAP6, X-BARs + XBAR_INPUT13, //!< XINT4, X-BARs + XBAR_INPUT14 //!< XINT5, X-BARs +} XBAR_InputNum; + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setOutputMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + // + //OUTPUTXBAR + // + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000, + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001, + XBAR_OUT_MUX00_ADCAEVT1 = 0x0002, + XBAR_OUT_MUX00_ECAP1_OUT = 0x0003, + XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200, + XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201, + XBAR_OUT_MUX01_CLB1_OUT4 = 0x0202, + XBAR_OUT_MUX01_ADCCEVT1 = 0x0203, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401, + XBAR_OUT_MUX02_ADCAEVT2 = 0x0402, + XBAR_OUT_MUX02_ECAP2_OUT = 0x0403, + XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600, + XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601, + XBAR_OUT_MUX03_CLB1_OUT5 = 0x0602, + XBAR_OUT_MUX03_ADCCEVT2 = 0x0603, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801, + XBAR_OUT_MUX04_ADCAEVT3 = 0x0802, + XBAR_OUT_MUX04_ECAP3_OUT = 0x0803, + XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00, + XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_OUT_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01, + XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02, + XBAR_OUT_MUX06_ECAP4_OUT = 0x0C03, + XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00, + XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_OUT_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH = 0x1000, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L = 0x1001, + XBAR_OUT_MUX08_ADCBEVT1 = 0x1002, + XBAR_OUT_MUX08_ECAP5_OUT = 0x1003, + XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL = 0x1200, + XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201, + XBAR_OUT_MUX09_CLB3_OUT4 = 0x1202, + XBAR_OUT_MUX09_ADCDEVT1 = 0x1203, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH = 0x1400, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L = 0x1401, + XBAR_OUT_MUX10_ADCBEVT2 = 0x1402, + XBAR_OUT_MUX10_ECAP6_OUT = 0x1403, + XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL = 0x1600, + XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601, + XBAR_OUT_MUX11_CLB3_OUT5 = 0x1602, + XBAR_OUT_MUX11_ADCDEVT2 = 0x1603, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH = 0x1800, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L = 0x1801, + XBAR_OUT_MUX12_ADCBEVT3 = 0x1802, + XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL = 0x1A00, + XBAR_OUT_MUX13_ADCSOCA = 0x1A01, + XBAR_OUT_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_OUT_MUX13_ADCDEVT3 = 0x1A03, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH = 0x1C00, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH_OR_L = 0x1C01, + XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02, + XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_OUT_MUX15_CMPSS8_CTRIPOUTL = 0x1E00, + XBAR_OUT_MUX15_ADCSOCB = 0x1E01, + XBAR_OUT_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_OUT_MUX15_ADCDEVT4 = 0x1E03, + XBAR_OUT_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_OUT_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_OUT_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_OUT_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_OUT_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_OUT_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_OUT_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_OUT_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_OUT_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_OUT_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_OUT_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_OUT_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_OUT_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_OUT_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_OUT_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_OUT_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_OUT_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_OUT_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_OUT_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_OUT_MUX31_SD2FLT4_COMPL = 0x3E00, + +} XBAR_OutputMuxConfig; + +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setEPWMMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_EPWM_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_EPWM_MUX00_ADCAEVT1 = 0x0002, + XBAR_EPWM_MUX00_ECAP1_OUT = 0x0003, + XBAR_EPWM_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_EPWM_MUX01_INPUTXBAR1 = 0x0201, + XBAR_EPWM_MUX01_CLB1_OUT4 = 0x0202, + XBAR_EPWM_MUX01_ADCCEVT1 = 0x0203, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_EPWM_MUX02_ADCAEVT2 = 0x0402, + XBAR_EPWM_MUX02_ECAP2_OUT = 0x0403, + XBAR_EPWM_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_EPWM_MUX03_INPUTXBAR2 = 0x0601, + XBAR_EPWM_MUX03_CLB1_OUT5 = 0x0602, + XBAR_EPWM_MUX03_ADCCEVT2 = 0x0603, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_EPWM_MUX04_ADCAEVT3 = 0x0802, + XBAR_EPWM_MUX04_ECAP3_OUT = 0x0803, + XBAR_EPWM_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_EPWM_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_EPWM_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_EPWM_MUX05_ADCCEVT3 = 0x0A03, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_EPWM_MUX06_ADCAEVT4 = 0x0C02, + XBAR_EPWM_MUX06_ECAP4_OUT = 0x0C03, + XBAR_EPWM_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_EPWM_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_EPWM_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_EPWM_MUX07_ADCCEVT4 = 0x0E03, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_EPWM_MUX08_ADCBEVT1 = 0x1002, + XBAR_EPWM_MUX08_ECAP5_OUT = 0x1003, + XBAR_EPWM_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_EPWM_MUX09_INPUTXBAR5 = 0x1201, + XBAR_EPWM_MUX09_CLB3_OUT4 = 0x1202, + XBAR_EPWM_MUX09_ADCDEVT1 = 0x1203, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_EPWM_MUX10_ADCBEVT2 = 0x1402, + XBAR_EPWM_MUX10_ECAP6_OUT = 0x1403, + XBAR_EPWM_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_EPWM_MUX11_INPUTXBAR6 = 0x1601, + XBAR_EPWM_MUX11_CLB3_OUT5 = 0x1602, + XBAR_EPWM_MUX11_ADCDEVT2 = 0x1603, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_EPWM_MUX12_ADCBEVT3 = 0x1802, + XBAR_EPWM_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_EPWM_MUX13_ADCSOCA = 0x1A01, + XBAR_EPWM_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_EPWM_MUX13_ADCDEVT3 = 0x1A03, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_EPWM_MUX14_ADCBEVT4 = 0x1C02, + XBAR_EPWM_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_EPWM_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_EPWM_MUX15_ADCSOCB = 0x1E01, + XBAR_EPWM_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_EPWM_MUX15_ADCDEVT4 = 0x1E03, + XBAR_EPWM_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_EPWM_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_EPWM_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_EPWM_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_EPWM_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_EPWM_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_EPWM_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_EPWM_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_EPWM_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_EPWM_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_EPWM_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_EPWM_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_EPWM_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_EPWM_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_EPWM_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_EPWM_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_EPWM_MUX31_SD2FLT4_COMPL = 0x3E00 +} XBAR_EPWMMuxConfig; + +//***************************************************************************** +// +// The following values define the muxConfig parameter for +// XBAR_setCLBMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_CLB_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_CLB_MUX00_ADCAEVT1 = 0x0002, + XBAR_CLB_MUX00_ECAP1_OUT = 0x0003, + XBAR_CLB_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_CLB_MUX01_INPUTXBAR1 = 0x0201, + XBAR_CLB_MUX01_CLB1_OUT4 = 0x0202, + XBAR_CLB_MUX01_ADCCEVT1 = 0x0203, + XBAR_CLB_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_CLB_MUX02_ADCAEVT2 = 0x0402, + XBAR_CLB_MUX02_ECAP2_OUT = 0x0403, + XBAR_CLB_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_CLB_MUX03_INPUTXBAR2 = 0x0601, + XBAR_CLB_MUX03_CLB1_OUT5 = 0x0602, + XBAR_CLB_MUX03_ADCCEVT2 = 0x0603, + XBAR_CLB_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_CLB_MUX04_ADCAEVT3 = 0x0802, + XBAR_CLB_MUX04_ECAP3_OUT = 0x0803, + XBAR_CLB_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_CLB_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_CLB_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_CLB_MUX05_ADCCEVT3 = 0x0A03, + XBAR_CLB_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_CLB_MUX06_ADCAEVT4 = 0x0C02, + XBAR_CLB_MUX06_ECAP4_OUT = 0x0C03, + XBAR_CLB_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_CLB_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_CLB_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_CLB_MUX07_ADCCEVT4 = 0x0E03, + XBAR_CLB_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_CLB_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_CLB_MUX08_ADCBEVT1 = 0x1002, + XBAR_CLB_MUX08_ECAP5_OUT = 0x1003, + XBAR_CLB_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_CLB_MUX09_INPUTXBAR5 = 0x1201, + XBAR_CLB_MUX09_CLB3_OUT4 = 0x1202, + XBAR_CLB_MUX09_ADCDEVT1 = 0x1203, + XBAR_CLB_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_CLB_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_CLB_MUX10_ADCBEVT2 = 0x1402, + XBAR_CLB_MUX10_ECAP6_OUT = 0x1403, + XBAR_CLB_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_CLB_MUX11_INPUTXBAR6 = 0x1601, + XBAR_CLB_MUX11_CLB3_OUT5 = 0x1602, + XBAR_CLB_MUX11_ADCDEVT2 = 0x1603, + XBAR_CLB_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_CLB_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_CLB_MUX12_ADCBEVT3 = 0x1802, + XBAR_CLB_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_CLB_MUX13_ADCSOCA = 0x1A01, + XBAR_CLB_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_CLB_MUX13_ADCDEVT3 = 0x1A03, + XBAR_CLB_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_CLB_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_CLB_MUX14_ADCBEVT4 = 0x1C02, + XBAR_CLB_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_CLB_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_CLB_MUX15_ADCSOCB = 0x1E01, + XBAR_CLB_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_CLB_MUX15_ADCDEVT4 = 0x1E03, + XBAR_CLB_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_CLB_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_CLB_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_CLB_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_CLB_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_CLB_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_CLB_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_CLB_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_CLB_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_CLB_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_CLB_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_CLB_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_CLB_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_CLB_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_CLB_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_CLB_MUX31_SD2FLT4_COMPL = 0x3E00, +} XBAR_CLBMuxConfig; + + +//***************************************************************************** +// +//! The following values define the \e inputFlag parameter for +//! XBAR_getInputFlagStatus() and XBAR_clearInputFlag(). +// +//***************************************************************************** +typedef enum +{ + // + // XBARFLG1 + // + XBAR_INPUT_FLG_CMPSS1_CTRIPL = 0x0000, + XBAR_INPUT_FLG_CMPSS1_CTRIPH = 0x0001, + XBAR_INPUT_FLG_CMPSS2_CTRIPL = 0x0002, + XBAR_INPUT_FLG_CMPSS2_CTRIPH = 0x0003, + XBAR_INPUT_FLG_CMPSS3_CTRIPL = 0x0004, + XBAR_INPUT_FLG_CMPSS3_CTRIPH = 0x0005, + XBAR_INPUT_FLG_CMPSS4_CTRIPL = 0x0006, + XBAR_INPUT_FLG_CMPSS4_CTRIPH = 0x0007, + XBAR_INPUT_FLG_CMPSS5_CTRIPL = 0x0008, + XBAR_INPUT_FLG_CMPSS5_CTRIPH = 0x0009, + XBAR_INPUT_FLG_CMPSS6_CTRIPL = 0x000A, + XBAR_INPUT_FLG_CMPSS6_CTRIPH = 0x000B, + XBAR_INPUT_FLG_CMPSS7_CTRIPL = 0x000C, + XBAR_INPUT_FLG_CMPSS7_CTRIPH = 0x000D, + XBAR_INPUT_FLG_CMPSS8_CTRIPL = 0x000E, + XBAR_INPUT_FLG_CMPSS8_CTRIPH = 0x000F, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTL = 0x0018, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTH = 0x0019, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTL = 0x001A, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTH = 0x001B, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTL = 0x001C, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTH = 0x001D, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTL = 0x001E, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTH = 0x001F, + // + // XBARFLG2 + // + XBAR_INPUT_FLG_INPUT1 = 0x0100, + XBAR_INPUT_FLG_INPUT2 = 0x0101, + XBAR_INPUT_FLG_INPUT3 = 0x0102, + XBAR_INPUT_FLG_INPUT4 = 0x0103, + XBAR_INPUT_FLG_INPUT5 = 0x0104, + XBAR_INPUT_FLG_INPUT6 = 0x0105, + XBAR_INPUT_FLG_ADCSOCA = 0x0106, + XBAR_INPUT_FLG_ADCSOCB = 0x0107, + XBAR_INPUT_FLG_CLB1_OUT4 = 0x0108, + XBAR_INPUT_FLG_CLB1_OUT5 = 0x0109, + XBAR_INPUT_FLG_CLB2_OUT4 = 0x010A, + XBAR_INPUT_FLG_CLB2_OUT5 = 0x010B, + XBAR_INPUT_FLG_CLB3_OUT4 = 0x010C, + XBAR_INPUT_FLG_CLB3_OUT5 = 0x010D, + XBAR_INPUT_FLG_CLB4_OUT4 = 0x010E, + XBAR_INPUT_FLG_CLB4_OUT5 = 0x010F, + XBAR_INPUT_FLG_ECAP1_OUT = 0x0110, + XBAR_INPUT_FLG_ECAP2_OUT = 0x0111, + XBAR_INPUT_FLG_ECAP3_OUT = 0x0112, + XBAR_INPUT_FLG_ECAP4_OUT = 0x0113, + XBAR_INPUT_FLG_ECAP5_OUT = 0x0114, + XBAR_INPUT_FLG_ECAP6_OUT = 0x0115, + XBAR_INPUT_FLG_EXTSYNCOUT = 0x0116, + XBAR_INPUT_FLG_ADCAEVT1 = 0x0117, + XBAR_INPUT_FLG_ADCAEVT2 = 0x0118, + XBAR_INPUT_FLG_ADCAEVT3 = 0x0119, + XBAR_INPUT_FLG_ADCAEVT4 = 0x011A, + XBAR_INPUT_FLG_ADCBEVT1 = 0x011B, + XBAR_INPUT_FLG_ADCBEVT2 = 0x011C, + XBAR_INPUT_FLG_ADCBEVT3 = 0x011D, + XBAR_INPUT_FLG_ADCBEVT4 = 0x011E, + XBAR_INPUT_FLG_ADCCEVT1 = 0x011F, + // + // XBARFLG3 + // + XBAR_INPUT_FLG_ADCCEVT2 = 0x0200, + XBAR_INPUT_FLG_ADCCEVT3 = 0x0201, + XBAR_INPUT_FLG_ADCCEVT4 = 0x0202, + XBAR_INPUT_FLG_ADCDEVT1 = 0x0203, + XBAR_INPUT_FLG_ADCDEVT2 = 0x0204, + XBAR_INPUT_FLG_ADCDEVT3 = 0x0205, + XBAR_INPUT_FLG_ADCDEVT4 = 0x0206, + XBAR_INPUT_FLG_SD1FLT1_COMPL = 0x0207, + XBAR_INPUT_FLG_SD1FLT1_COMPH = 0x0208, + XBAR_INPUT_FLG_SD1FLT2_COMPL = 0x0209, + XBAR_INPUT_FLG_SD1FLT2_COMPH = 0x020A, + XBAR_INPUT_FLG_SD1FLT3_COMPL = 0x020B, + XBAR_INPUT_FLG_SD1FLT3_COMPH = 0x020C, + XBAR_INPUT_FLG_SD1FLT4_COMPL = 0x020D, + XBAR_INPUT_FLG_SD1FLT4_COMPH = 0x020E, + XBAR_INPUT_FLG_SD2FLT1_COMPL = 0x020F, + XBAR_INPUT_FLG_SD2FLT1_COMPH = 0x0210, + XBAR_INPUT_FLG_SD2FLT2_COMPL = 0x0211, + XBAR_INPUT_FLG_SD2FLT2_COMPH = 0x0212, + XBAR_INPUT_FLG_SD2FLT3_COMPL = 0x0213, + XBAR_INPUT_FLG_SD2FLT3_COMPH = 0x0214, + XBAR_INPUT_FLG_SD2FLT4_COMPL = 0x0215, + XBAR_INPUT_FLG_SD2FLT4_COMPH = 0x0216 +} XBAR_InputFlag; +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Output X-BAR mux values to be passed to the output signal. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) |= muxes; + + EDIS; + + +} + +//***************************************************************************** +// +//! Disables the Output X-BAR mux values from being passed to the output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values from being passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to disable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Enables or disables the output latch to drive the selected output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param enable is a flag that determines whether or not the latch is +//! selected to drive the X-BAR output. +//! +//! This function sets the Output X-BAR output signal latch mode. If the +//! \e enable parameter is \b true, the output specified by \e output will be +//! driven by the output latch. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setOutputLatchMode(XBAR_OutputNum output, bool enable) +{ + EALLOW; + + // + // Set or clear the latch setting bit based on the enable parameter. + // + if(enable) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Returns the status of the output latch +//! +//! \param output is the X-BAR output being checked. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! \return Returns \b true if the output corresponding to \e output was +//! triggered. If not, it will return \b false. +// +//***************************************************************************** +static inline bool +XBAR_getOutputLatchStatus(XBAR_OutputNum output) +{ + // + // Get the status of the Output X-BAR output latch. + // + return((HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCH) & + (0x1U << ((uint16_t)output / 2U))) != 0U); +} + +//***************************************************************************** +// +//! Clears the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function clears the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_clearOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that clears the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHCLR) |= + 0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Forces the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function forces the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_forceOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that forces the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHFRC) = + (uint16_t)0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Configures the polarity of an Output X-BAR output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the Output X-BAR signal if the \e invert parameter is +//! \b true. If \e invert is \b false, the signal will be passed as is. The +//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output +//! number between 1 and 8 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertOutputSignal(XBAR_OutputNum output, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) |= muxes; + EDIS; +} + +//***************************************************************************** +// +//! Disables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an ePWM X-BAR output. +//! +//! \param trip is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the ePWM X-BAR trip signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertEPWMSignal(XBAR_TripNum trip, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) |= + 0x1U << ((uint16_t)trip / 2U); + } + else + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) &= + ~(0x1U << ((uint16_t)trip / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the GPIO pin for an Input X-BAR input. +//! +//! \param input is the X-BAR input being configured. +//! \param pin is the identifying number of the pin. +//! +//! This function configures which GPIO is assigned to an Input X-BAR input. +//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy +//! where y is a the input number for the Input X-BAR. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setInputPin(XBAR_InputNum input, uint16_t pin) +{ + // + // Check the argument. + // + ASSERT(pin <= XBAR_GPIO_MAX_CNT); + + // + // Write the requested pin to the appropriate input select register. + // + EALLOW; + + HWREGH(XBAR_INPUT_BASE + (uint16_t)input) = pin; + + EDIS; +} + +//***************************************************************************** +// +//! Locks an input to the Input X-BAR. +//! +//! \param input is an input to the Input X-BAR. +//! +//! This function locks the specific input on the Input X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockInput(XBAR_InputNum input) +{ + // + // lock the input in the INPUTSELECTLOCK register. + // + EALLOW; + HWREG(INPUTXBAR_BASE + XBAR_O_INPUTSELECTLOCK) = + 1UL << (uint16_t)input; + EDIS; +} + +//***************************************************************************** +// +//! Locks the Output X-BAR. +//! +//! This function locks the Output X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockOutput(void) +{ + // + // Lock the Output X-BAR with the OUTPUTLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLOCK) = + ((uint32_t)0x5A5A << XBAR_OUTPUTLOCK_KEY_S) | + (uint32_t)XBAR_OUTPUTLOCK_LOCK; + + EDIS; +} + +//***************************************************************************** +// +//! Locks the ePWM X-BAR. +//! +//! This function locks the ePWM X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockEPWM(void) +{ + // + // Lock the ePWM X-BAR with the TRIPLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(EPWMXBAR_BASE + XBAR_O_TRIPLOCK) = + ((uint32_t)0x5A5A << XBAR_TRIPLOCK_KEY_S) | + (uint32_t)XBAR_TRIPLOCK_LOCK; + EDIS; +} + +//***************************************************************************** +// +//! Enables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) |= muxes; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an CLB X-BAR output. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the CLB X-BAR auxSignal signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertCLBSignal(XBAR_AuxSigNum auxSignal, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) |= + 0x1U << ((uint16_t)auxSignal / 2U); + } + else + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) &= + ~(0x1U << ((uint16_t)auxSignal / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the Output X-BAR mux that determines the signals passed to an +//! output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an Output X-BAR mux. This determines which +//! signal(s) should be passed through the X-BAR to a GPIO. The \e output +//! parameter is a value \b XBAR_OUTPUTy where y is a the output number +//! between 1 and 8 inclusive. +//! +//! The \e muxConfig parameter for OUTPUT XBAR is the mux configuration +//! value that specifies which signal will be passed from the mux. The +//! values have the format of \b XBAR_OUT_MUXnn_xx where the 'xx' is +//! the signal and nn is the mux number. +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the output signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig); + +//***************************************************************************** +// +//! Configures the ePWM X-BAR mux that determines the signals passed to an +//! ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an ePWM X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an ePWM module. The \e trip +//! parameter is a value \b XBAR_TRIPy where y is a the number of the trip +//! signal on the ePWM. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the trip signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig); + +//***************************************************************************** +// +//! Returns the status of the input latch. +//! +//! \param inputFlag is the X-BAR input latch being checked. Values are in the +//! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal. +//! +//! \return Returns \b true if the X-BAR input corresponding to the +//! \e inputFlag has been triggered. If not, it will return \b false. +// +//***************************************************************************** +extern bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Clears the input latch for the specified input latch. +//! +//! \param inputFlag is the X-BAR input latch being cleared. +//! +//! This function clears the Input X-BAR input latch. The input latch to be +//! cleared is specified by the \e inputFlag parameter. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Configures the CLB X-BAR mux that determines the signals passed to a +//! CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an CLB X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an CLB module. The \e auxSignal +//! parameter is a value \b XBAR_AUXSIGy where y is a the number of the +//! signal on the CLB. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_CLB_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_CLB_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_CLB_MUX03_INPUTXBAR2, resulting in the values of MUX00 and MUX03 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, + XBAR_CLBMuxConfig muxConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // XBAR_H diff --git a/gpio_bitfield_cpu1/gpio_bitfield_main_cpu1.c b/gpio_bitfield_cpu1/gpio_bitfield_main_cpu1.c new file mode 100644 index 0000000..d4094a0 --- /dev/null +++ b/gpio_bitfield_cpu1/gpio_bitfield_main_cpu1.c @@ -0,0 +1,57 @@ +// comment inline +/*This is a multipleline comments +Line 2 +Line 3*/ +/*Gerardo Marx +30th June 2026 +GPIOs management with dual CPUs +---------------- +CPU1: GPIO22 and GPIO97 using bitfield approach +CPU2: GPIO52 using driverlib approach + + |-----------| + | | + |GPIO22 | + | | + | ---- | + |GPIO97 | + | | + |GPIO52 | + |-----------| +*/ + +// Libraries and includes +#include "F28x_Project.h" +#include "driverlib.h" //??? +#include "device.h" + + +// Variables and definitions + +// main +void main(void){ + // 1: Init system + InitSysCtrl(); + // 2: Configure GPIOs + EALLOW; //enable GPIO config + // 2.1 GPIO22 + GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 0; //pin as gpio + GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; // configure as output + GpioCtrlRegs.GPACSEL3.bit.GPIO22 = 0; // cpu1 + + // 2.2 GPIO97 + GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 0; //pin as gpio + GpioCtrlRegs.GPDDIR.bit.GPIO97 = 1; // configure as output + GpioCtrlRegs.GPDCSEL1.bit.GPIO97 = 0; //cpu1 + + // 2.3 GPIO52 + GpioCtrlRegs.GPBGMUX2.bit.GPIO52 = 0; //pin as gpio + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1; // configure as output + GpioCtrlRegs.GPBCSEL3.bit.GPIO52 = 2; //cpu2 + + // 3: Change state of the GPIOs + GpioDataRegs.GPASET.bit.GPIO22 = 1; // set logical 1 + GpioDataRegs.GPDSET.bit.GPIO97 = 1; // set logical 1 + // 4: Enter into the infinite loop + +} diff --git a/gpio_bitfield_cpu1/targetConfigs/TMS320F28377D.ccxml b/gpio_bitfield_cpu1/targetConfigs/TMS320F28377D.ccxml new file mode 100644 index 0000000..79dd5cc --- /dev/null +++ b/gpio_bitfield_cpu1/targetConfigs/TMS320F28377D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu1/targetConfigs/readme.txt b/gpio_bitfield_cpu1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/gpio_bitfield_cpu1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/gpio_driverlib_cpu2/.ccsproject b/gpio_driverlib_cpu2/.ccsproject new file mode 100644 index 0000000..e089904 --- /dev/null +++ b/gpio_driverlib_cpu2/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu2/.clangd b/gpio_driverlib_cpu2/.clangd new file mode 100644 index 0000000..657a761 --- /dev/null +++ b/gpio_driverlib_cpu2/.clangd @@ -0,0 +1,8 @@ +# This is an auto-generated file - do not add it to source-control + +CompileFlags: + CompilationDatabase: CPU2_RAM/.clangd + +Diagnostics: + Suppress: '*' + diff --git a/gpio_driverlib_cpu2/.cproject b/gpio_driverlib_cpu2/.cproject new file mode 100644 index 0000000..1ad0ab8 --- /dev/null +++ b/gpio_driverlib_cpu2/.cproject @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu2/.project b/gpio_driverlib_cpu2/.project new file mode 100644 index 0000000..7098144 --- /dev/null +++ b/gpio_driverlib_cpu2/.project @@ -0,0 +1,33 @@ + + + gpio_driverlib_cpu2 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + + + + driverlib.lib + 1 + COM_TI_C2000WARE_INSTALL_DIR/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_INSTALL_DIR%7D/driverlib/f2837xd/driverlib + + + diff --git a/gpio_driverlib_cpu2/.settings/org.eclipse.cdt.codan.core.prefs b/gpio_driverlib_cpu2/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/gpio_driverlib_cpu2/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/gpio_driverlib_cpu2/.settings/org.eclipse.core.resources.prefs b/gpio_driverlib_cpu2/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..6bef3e5 --- /dev/null +++ b/gpio_driverlib_cpu2/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,9 @@ +eclipse.preferences.version=1 +encoding//CPU2_RAM/device/subdir_rules.mk=UTF-8 +encoding//CPU2_RAM/device/subdir_vars.mk=UTF-8 +encoding//CPU2_RAM/makefile=UTF-8 +encoding//CPU2_RAM/objects.mk=UTF-8 +encoding//CPU2_RAM/sources.mk=UTF-8 +encoding//CPU2_RAM/subdir_rules.mk=UTF-8 +encoding//CPU2_RAM/subdir_vars.mk=UTF-8 +encoding/=UTF-8 diff --git a/gpio_driverlib_cpu2/2837xD_FLASH_lnk_cpu2.cmd b/gpio_driverlib_cpu2/2837xD_FLASH_lnk_cpu2.cmd new file mode 100644 index 0000000..8c6a609 --- /dev/null +++ b/gpio_driverlib_cpu2/2837xD_FLASH_lnk_cpu2.cmd @@ -0,0 +1,148 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x0000A2, length = 0x00035E + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(8) + .text : > FLASHB PAGE = 0, ALIGN(8) + codestart : > BEGIN PAGE = 0, ALIGN(8) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + .switch : > FLASHB PAGE = 0, ALIGN(8) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + +#if defined(__TI_EABI__) + .init_array : > FLASHB, PAGE = 0, ALIGN(8) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : > FLASHF, PAGE = 0, ALIGN(8) +#else + .pinit : > FLASHB, PAGE = 0, ALIGN(8) + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .econst : >> FLASHF PAGE = 0, ALIGN(8) +#endif + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #if defined(__TI_EABI__) + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #else + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/gpio_driverlib_cpu2/2837xD_RAM_lnk_cpu2.cmd b/gpio_driverlib_cpu2/2837xD_RAM_lnk_cpu2.cmd new file mode 100644 index 0000000..bca4726 --- /dev/null +++ b/gpio_driverlib_cpu2/2837xD_RAM_lnk_cpu2.cmd @@ -0,0 +1,104 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x0000A2, length = 0x00035E + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .stack : > RAMM1, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .init_array : > RAMM0, PAGE = 0 + .const : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 +#endif + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.12FC8C33CB659405.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.12FC8C33CB659405.idx new file mode 100644 index 0000000000000000000000000000000000000000..893ae2583b7b60a7756ce724b8efd3e64fddad3f GIT binary patch literal 1016 zcmWIYbaVT_%)sEB;#rZKT9U}Zz`!63#Kk2=nQIss7>t1e6?2XTU(8Zg6!{wbD{hYU z%%yj87xH_anf6X?Nr}`YbHgmPpmdS-lT-fJnPz%(FWtbO=(y*_#m5ilXfK=+u&U|i zD~IUiUwn(}{4}KR>#qvAk+Nln>KDGYd(q0SChMF#*iu5LsrG!{BjWh^)uic93lB^@ zJ4_?loA@YtFawRqImD#ywB+xpsc3 zEmevNsLD9_o|>dgMSv(IvzruE#tn)z%ckNaiLlkXDtIZx?mT5~yl2iuSM zti{UKN2fY&+%)SC>&?6}`Qpmlq#wYzOHbAAoAhay7%zhm1B0jog98_s0Lp*?_vbHt z9qpc$ybNL>X&DDOFaeX+&c2>ARWGrVmq7$5og|y22qs|C>33yio^1;4<7MCnN+&8L zs(}fZ^u#?PvtLg?GKH5x94MX1n#m6)VA9)LZRT2?zO|Z{K>#S7Ae*29CScNPfiwM9 zeV@LK7nBA?Ls>)lzywU1XTh@V7hZh6#>*fGlunjSRss_+>7vxM;txO$%>Rto{mlXt z26`H%i%T>>B|r_q3sMO};-xC2D#7GnApz>% literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint.h.269335DDD01ACAF0.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint.h.269335DDD01ACAF0.idx new file mode 100644 index 0000000000000000000000000000000000000000..8d258bf2d0dc831960fbb7323fbcd04f28135a3e GIT binary patch literal 1424 zcmYL|e@v8h9LGO*9Q2h3n)f`1!Eqr@?m{p)+Zha`&dy_SH1F!fyEtx1dFeTjb$3os z3#YOmWneM#M@XT8;wDoOjU0(hnDHd7eM+bK7gL=kxvX z{(N69E-Y+_2C%IzuBi${Dl`Bf;4d5r1$X2B82)NLENB{vJ#U`9?2&EQG&)DC-89`b z?dmU$3iA8>BcJCOyFRFm`m8ya)oA*)_-ya+)qw|bVB7W8RME5dHLF#Ng5O?hvd%lB zNo?EG@%5IfKkQGhTky$fyUS7Z=H|(vO_3$TErYXOY+oDd`F`Zf?ODGy*LQCV%(U{s z;rgRPrPqJC{p!?rQ~pP)_^6^&5U#CyZI=pQm1nPJWc)-T2eANZyUuQq3e3VC1E^Hd z=XO~3Ro4zAa}b9@o{*=PiXybNCg1CH_s!>kq2Sax4N_4ANX`A}hWYM74jxCro#0N9 ziXwPZgj?Snit}*r7z!Sp#~>9&IR3+qd%0;jDB!l#R-M%#6-5XfPk(pf&$$&G;LWSE zg>1c46k#mqPEx4x{V)d{3J#saAQeTp&~t3%{kJbPa1f7zFTs~06-9`YS1!4gxu}Z+ z%vo&_EPAOZg2~v>^pxj?vm8XBkRfE~rJ@LbPbB#Fywq@wgBTRj__Rc+C_*UkM%aiS zca*(V_Dug@po&x5nVqMI>{-9}u3vRVgE*UIYw66DTh~VFdRa7L2XpXr((#1B(e#Va z9AXdi@N~!2OcncI&Qi<(lrmy5;{Pd7wur@G2~(no#W)E+9NTN@?pw1Qm$Wh~PpLh> z{AZuuysi}O#cXjB*|a0XV&sJBE5u^ZgwwV24^%hid$G5hxdqz6hVDa-kt5Syw2jP| zNH*OKVsRJvI7| zE!q}l(b8N5Zu&V>zjHI%UgnjTJiM`*D;V8bhj;~BkxWfKy;JEr?_aqcaUm;|ZJI*F z;s}yG;eJr#zkP8(Vly+#H@Kl_>rATtbUW_E$9w{PeD}%y1KVztcA}liQlFqEv{A(3 z^b($Hi?u<$?=<3kmM{0FOF%4+GTAqKO4?%hzCpz0tXw{hec|qR4t{*)9O9*Hsce6A zKxjU4z4HsiC9Fio%l_#YiW$Fp8F41dl$WIUfmnPTv}Ep&2P4Ydf zw1B{PHpqBwLSa%7iAx}2+qhRH12Txfa7=JQWCDV0|J~AiZgO*z?>pyzod4vW^!4_( zG-jA1vA(h-u{3Hk!!Ue&Q>BvAV*GxLudGI(ecLqK&YX8*-|no}m8x#FzOGV`#@}o| z_hLByqHx^B$&|ShR=Uu3Qj%*@S?%DTrEI!t>=OLq;hMhA?D43@iBBd%67C+=ZP(P) zIZuVHmhH6oDp@gHGrn!*cY8l3H6tk+6EPC;snpXvhKXnjSeu&&HXVM2I>t17P!W8)y6lDa;h_yjn(Yo5+t379fLI$#z4fvA(Vaq{r z%Pz$A1nP;vAg(s$ENvBMyoREKKnKn6>}+0_qh`VmMI(VmDy*Zr1~T^+I-@8eP(*eZ zLOGp%I?Edy*^lBDfm?)2KIS!gKIc6THxx<&N*d~bJzw+J_d`MyIs!Vv&f&jDKmGOU zf}+?R#Uz1Ax??)MM=>3s^F)yXDHewH&y9-?zG>~}g;)ww4hz1C+uM7?#Sd{FfjnC3 z`wDn9vtGxFNQmUtS9RInu!ssjj<}ydKdq;K&3M^*vMCTnAOxBj(pGgmIxwWzAwrx1 z8C<_pY5M*aku8f=1XMKbnMHkd_=owdC?`-(rK7(C)Wy;;(2D@M^tpp#}O9+Vy}FzsSR5+refWT6g@aeSLZ#6b|m)n95mn=j5O zOh!CUV4iUIZa`n1o;`5?42pIF?KH7utDDAs!9NX!9OPWb7up>jHeOiFLflHAm9D@1 z&iEIO8_wA%iU}0cLN5o}++NCxV?{23T)JcG+N%7sn3#MNS^`>ni=q?%7OIPuzeLeY zpqXCbo|v$U#n!$hD15-@6~l1MV{7JBPyVSu91Ou+&$0UR$E-|^st|`k7}qf`Znyde zHz|u-2(-|8K3}rreZ;?1i=vM}AFb!OdF1^7cc(TK;SkORDtY&|_P1H}w}?jwjL|teP?QiTp*uz$9d(P%=F=!<2+Yvb&YGn^0~?lS zQB)A9p!Zbp*wtIu*YF612t-`ZhYq*?6t4bt9&tB;Zkl0N(k8gJzx*kRc!=kEj+dE; z_Y4lLARZ+!O3x@H_m5uJY5sE*`2_N5peLvN@7zr3Sx3=8pn;CZ2R4-V_6asn1VDhP sVff!Egbn9J3Ko|VD5Zh$kDD09u1b}}q;A8n5eYHNEMFh4eT!lK1x#{rb^rhX literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint40.h.867E57579EB83AFB.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_stdint40.h.867E57579EB83AFB.idx new file mode 100644 index 0000000000000000000000000000000000000000..c93cf4414aca56554c47227bbab775eed1d3cf5d GIT binary patch literal 248 zcmWIYbaVT_z`)>~;#rZKT9U{DWD5gvaY<2T5|B;=;)*$yxJ6a-uY%~|qQF5S3! zJ2U^xkJ&7ZCwA0t+;w#4S;fTnj69a?4?|UtGKm_9yU+XQ6wJjs=UvS6<*ObB^I9uK z&DoxteX{Q}OQ+1e+~YwdlUK;zT>Xui*MGQr$X~kYZT5xg8Lz!CvhKyW{ zsvN4KASn>ov`uDC{GnO%n0Xl08Pvrff(#5ij2a9YNIZWAe>krwH3#H;hT@{+Vs0SK R#JKnPiIv`mI<7M?001&-N!9=W literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_ti_config.h.B258754A245C49A8.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_ti_config.h.B258754A245C49A8.idx new file mode 100644 index 0000000000000000000000000000000000000000..102afe6f2743e856a83c925abbb84b8acf3d063e GIT binary patch literal 436 zcmWIYbaPw7$iU#7;#rZKT9U}Zz`!63#Kk2=nfXBa01#Kq+1hK!cgR41<@3S{{b`q$ zEMDGxuZ!>a9E%#UeShRXbF9)$GqILkRLNYB>DyW^zFJl<;oZcrU%GdEtZ&@QJu%-g zUC*vqWs%7B4LXg7zScE|T>Ct6VvJCHYd9!7>9MmV2AK4(e`%albxd(}A9;I0Jv iIVTZhS8-8tu{e-sVhl6yKm6uK&{Rey1}2y*7#INl9cmx| literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_types.h.CAEEFA4995D439EF.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_types.h.CAEEFA4995D439EF.idx new file mode 100644 index 0000000000000000000000000000000000000000..ac50c61ac38644234e3ff77dc564b3501acb117d GIT binary patch literal 3434 zcmYL~3se->8OQH{$do$^*%=)kWz=^v^BmqPu z8Xxi4#)625AyQK{njTj~0~(*yYCIT@s35jc>jN81(qJ2DwBMcO>+Csv!};Ie-r2cx z@AsRXm61`PA>@@sSu2aJrTJqBArkyKO6^N>IYP|tgsj|g_~TCd8d>Oyzc*3WAEvYQ zJhVRC89h+B`HNq#OPgTIy5Dm(FY~_pq9@OO%FpV(-dJq^@l;*Q3sRcXG_m#NjUi2~ zrHw@kYFCuW2lmufTwSv&)zEwC=Gu#wyN(k1z}6d{=7(eVFWmC|q+_4>=RRHDbtJr{ ztUFJC^t;0ynVq_bUySz8wS%^mH;0q_qyJ%@-Rk^oLio+TYq^(~`cCy4E_mHBFm->U z^LM9rKk2)qHI~e`?Jqi>wBfM!UzhHDP~YscX~-INH>&s0_D|~z!<}E>ab#C^#3nrW zrnAQuuFEfvy6y3(KI-Hj2 zAMdm2&j;JC@CEPrTr|4x3h!V1sp-*<$g!84VMpoZ;Mc1>r`B0JuI(w`S@__Gku%*j zLzeTKssle?R8e8u+B;*(%kHTsxY~uL-e>NI)*J5=M|p8UqX!}FN5gCP=56u!COS7F zSI~+8r4Sz81bp1*Bxcs_K4YLnBt(vv;zN}}ex;0ZvPXBx(8cHY)e|W30$_$_hF&Qu z@X&bvLVuAMOUa7>O!J!-rW6&}b?f}De2)$jB?17`HPiJ$uApW)PeN}^zn3^5~ADe4?zxt?FX6VvocQGs{p9=i3odrYoPr07Ti$7+WGu`PBgOm%cD+OPFJ5#`tO-&%E?l5qf}NGS%T zsK8_Af-y0-_n)NXIRI)nsfII*UR3D$;2#>6HqZQ;lJNjFa=Jz?V)UXyZMKH?9|x=Y zDe(trlJ_J(rKrH~SC^3Sd&vMLo&ebOcB4{MV1CHz*%KrCzNN$$fJ8A-rxXDusKEOT8(&?<#Q_iqK$TmSk5W|N=aA0VzO#(nqr@A4YEG)=0!J?@ zv@bH?z^j_<`;>$LWbv~Yl%fJX4L>bx)0+n=(E?zSOrc6qfmq%0cUu?d{*#hu07`sI z3`$Xfdyi+WJxvAy2ml~iOb$|t3cSBP-F$hy_9I#`m|K4y#{$M7*)JRyQC^RgCOq#!5r$y$6mK~Ce-w0NS6s%@pK4)PxG zLruI%#6=Y3cs^c4l?ZYYpCsZL7vvN^MZ`@kz?uY9)x7l15YV zx8az(Rd0z#cq|9+&|xz~MFGwHgfxl?VrC_bmtE{H>pu4z6T~eX-@?JMbA8ZLFu){* zG1>`YrY4NhNf0w3VT|twVx}RCad9DL^1=8?Z$rW!=i=$`K$H2&B6e1k5zx#;NaNdv znE3}|6c5BM>)-(D1_qdGFuwKWyi&34^xJS#i;qRZqk@|RXeJ({agiZry1^Jd12K~f z#)tSRTg}$&a@ZiTe5@89M358tL@hQ4K{oSdEp`GyPUq9LxSRrXaju^8!Uo?IT6nf@ z}4n;n2DJPXR@5$FmGh;whs77cHXYTCXa0hXr?8k@hC&gWP~xc z9*A8E!hzh*75k*$t~v*^r}C-Zc%1ODfp^&md6WWr1 znPV_Uxj@X!f-!a@h+RIx0X!Qpz#M`x_C1K1IWWd$hM4&RV{D}mGfQBMeH~)v28`|2 jqI~wh!~VAGw8i2GA#wlz*G&#CSn65V@$E*pxLEQ(mw<2R literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_types.h.DA467FFD6DBAEA91.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/_types.h.DA467FFD6DBAEA91.idx new file mode 100644 index 0000000000000000000000000000000000000000..38436ad887ec89f7beb336980186394266fb5d5a GIT binary patch literal 3554 zcmYM13s6+o8OP5hpeLNGa_@zLJa-pCR77*5)L;{phY4ZW?K2O>Q5slV><7MTaQlOdGPGf(`B|EQ*-@! zrFu?$$EIq@UhuB518sD~eJF1YN@U=E_L3S1SY3kNnfmTs|s zNIe)a0+1Y#9Hxr~z<$FchJ3Dl9Wmg+82J?d*>ZNEE_{ZJ+NWo1R~G^>8-P-|G*}l7 ztoie(SM%Z&iIGqM>XmwvE*yB$VW*vse^MBM@2s{8vs;Bw*TA8#Zk*nHX>7ock!b*> zDQSVaXn>pkqIV{u#%yoNp^VH0pixj7VHW4WXEE(vx-hwBWf&s?0G0cd8+747-{h^L zV<%IVG7murgp}m@XW!^j5CvcsL`KkthI~ z1f@wZxCRcztWH{D?K+piNH9PSL2(F1*TA9S9S6QPo?V>9v>UEkWQ$Q34n#3kR$b?CHFH^<|9s0+8pIXVQfO!?WLQ-B0f` zXC8;D``2z^WIg~@N>zw195_#7I$krcsbxe2AW=yS)I|fF*WuF0Df|7YT>y9kP%IZ4 zbm24f{xB~r{K(4iAXLublW0+y?p3dxg{$MM$%6OARwShLs`066`bh=%TvE5_J!B^5E&NTzU zYy(>hHnede!PepoZOk#Sogsz=+%PC;!G$)iKiICEa#b*;prAz*^7yh~yAsJ&iF|Zm z?EC7UmO^2tKz9n-UupUWcMuBBl)?gr6BM*$LK{~bY%Pz_#vq#J=?oy3FRFF4PR2tm zs@v!`87CH18@0)J=|t5|?K1WY5#onB1R0YF&mBC~nPK=`1fbx|Ei7PMK|#wZwDGuu zttAxN7)@Ynxr85Y%V6&p=zf0EajBu8B^B~`p{axcOjfse(4f3D{be zp#39lNa*O;{a>)dY54PFi`NirEm)9-MA=xV{bH>uw!;4a#7+I~dSS`&miR_O{tvRZ BkB$HU literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/adc.h.E519F935EB5F4CE6.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/adc.h.E519F935EB5F4CE6.idx new file mode 100644 index 0000000000000000000000000000000000000000..168f82a80419f6169fd854412d21a017e2821ce7 GIT binary patch literal 32078 zcmZ5n2|N|u8=iabaQ8b%;ig0iZPKEsXwjykRhutMi}rm}O13PCEZHMV3vKqILh#G2@=6GD`zeB)4{2X?Xj9`VZ=1>|CC=C7pUuWT%71aK#^$Umo*(o|v7~mk z+}L`lWS*PXq$jG&63+dt(^Tp;$vr!-hu3m<_c`~kUN^Vgym>S5=FOzI{-?tShUXi{ z$6T8E@b#3?q8W`RLrsQ{I@$gWEAsT2;~8_58Q*d3eD{w>{4Jp}$0BC^Qajn(cupF0l%8Zp8gw7KO`{EA{KGY2}KGvY(o;`8sx8Ib2kMG7g)_qe+NxOb+Z-(U79}QE+ zZ%J=zoFDSqR&RM*ysn(wF$sFYd;W0m^eysM1!=+%mzr5hi$>p8bg-GF(fD=s@%u}+ zs3wH@BcD_bZgzj>ELofD^1jDsYvz5O(qHwOw&hN^ zT)IK?kED2sxZ0;?#p_>;9@|os`DJH#VdHWQr}V$I9J!fiY%MUeT`A^MdpeKW9#P8q z<=?~mmM5W;Is2sb`+VF$LZ6A3{g>vociQA35*S5?OcVNXnSFld_*wx6F64yLnR~ ze^!`WWUf&h9G&}gj zL8+F=(vX8epYQ&RkN6caM`Cfw`~ffh&n~LlCK#q%$UQF+yWhfm#TA9mqn(Fc&Q#sM zrp~kCshkMF{$f$u;X|)0TyL2ydUQzYfl=*B(?-qNA*mB=o~>DNEF0d&hmPws;qw3fSViV<&g} zQN-4$+didv&o1P=&)QYLY4b}b{`_&~_L1TjX_7mN5>}sF;QYziVS7mXuG(ga(>J%s zhE(}P$roB!tyKQ`&1L7Nq>__+`cIfno@rv?!S}2Aylw7$8NShS2f=|uHm)aTNLVN* zzVsQ@zc=pqC^YKP`q@tUTgGoLdy=mGoxMEimT|I$j76BbMa{d1T`y}@DZu2$iL3buE*W-W8VA>y7x_Z*LD8Fgf_xHK- zZw&U_-lpiZLHTW7AkB4ydJ`*$``JEAG08OvPFTz^ehE~+Y*K*qgT*I z8^~Mx>FNHyZR#tx_;A9)NKMrJ?Xs~OwoNLRNBd=ejW?M5Iaz6aw>A1gUTuA>%z8%L z=-VDIjvvp^tUl-+tfCTc(QA6eZN)pq=CJ^c%gSr5H(1?`^MAr5CW2_uIuDdKDVzP&vD`$@=Qf71;+@ES4!{ygfGGwPZi) zq+}kE!q4DL7+BBgsR~|V?RV}O+o8|>d)rQV_lG-IN7BZ~8fuh|^UhKa^4Hocz18cC zdaH|6HR%B7zir)A%$-LYrpv)=>U zOy!%38>e~6@2Sm``tqg|J!xujz&P-j3ysk}bT7eXMzK-Q@D@&DWH@G#1Tf>|k zekRoIIQl0yE9Y0IFseLlN2Rgc;F1TDUu1RPW#=x)*7Mj9>VMiGQbS`~u-5kzH~SAZ zT)97`=G`BK0@;FN!ecq_!X3CduAO~)5q%X*$yq|<;&fd z4&bgj9AluTYNEP-d-QlqBw=MOBC~0%R)dU(PcCY{WbU4rr8MieaZ}70*O7JZUcCLv zekkf=b^onNU$nx$2s`x3f}iX;^;QFKv8cuj*p6?Y_-> zc?R=#E!z}O82Go<>TSwh!_8iXf}ir{A14^vd~9j$U>_KNy?sT#)1$|KOIF0*X?gl_ z%gaSZM}0Uwt8(vhG}?>ayxP@e(Eob=MBgoO)h-o+2VPDe6D0?iY4~~OdS71=R2{#q z!qf8HI~mDvnF%KwoAeYC9xl3m*>i7Z^_T~$`xfwwx5f5Kx;Lyb-;t=M^C8zuGbiJL zQ(^PU!loiUUR|#~|KqYW{oF*4d5>~J;w9^)PK6{+bi93Jj&4d{(CTeUKe{B1RHEW9 zFSHBbXGGlfQu%sdjIoy(IHTyO!O`TA+tTZ-jh3bt*9f7A8hq)e` zI1u&j4C8y0o2^0A>cnw5eYvcXBvmu5vLIf-v%LPpevz??j$f7DFE!tf9+6Lsa;Xw3 zN*+P>A2x8%>$KZ-P7qxzx&EGy?gZi5SqHvcq@88-4Me@Sk98bYxU!Iwc35U_)7FRO z-(@Mc6=+hJ?=0ycTh{RRv|mc z{~+7j*h6La8+#+cxR=u{16)Tfdhy}F#@tJ#jO%aXCLZ*fG`8MS`Qc)yCXY~Q7QLb5?KajbLgtr>-^fy*DdyI)@&QkZ{!0o&!jvCH3h%{=V(J$+fp z)H(Hyl{y~W>K3Q#$qD6uqb|lyoL|mAH*?C-*4OH<9vWEYaRc9st&9w@7PKJb(ZWyz`D#YGuQl8wB2BjhW z8^4{?SJ_OG8SZRYt@xk1+W~J{{Dg~M4ELHE^V>&TnkUBCZ{Kz4(bnbdZxowDH-@_0 ztu`_$lB!5O7&3PDah5#0V)gpSz3Vu7r>4yK-t@Ac9u&g~`QiG0VvO;?rUE1ZA;CCfz`!@HV3X4D0a6C2t98#MQ?RuiP({aZy zm5|PgISDblb>~)f@tOB)zeOIf`1rb6#)`FX+9RWkf-IWg*2}M<*e-P%Xyq~*-)!A)fD`e>5oN=t)`qg?*I^8#(URxcX-@k5)K@Iza?d0e$C9*CrOO76%5JmHn z`(kf+ZFzNy+iz_R_N&X2?+++zX7627WHe#T!L9p4nO+6md9qClsuU+n$FP)2&E{1F0A2_zfZn5xO zMapyC>jjz4>Vvfn$L~5_DUdv^YZ7a#|LKtL<359QN#T{~&*jteuiUngI5s}`FmvN^ z|Gw;1g2h%l*9fFm@J3}WK0m`|+HSVrpX+)U5_D9G#lGnrRB|&Q?p{H9<&VQFy{pzF zo366_@73`x8H4;Yn_eY0zn1c-^mZ|OS*x<^N?StUbeqZC>1$D=iRX*iOjCF&F|Xzx8)X}) zT)Cxor(vn4okv(HCobS>@O3Fwzj@n~Z?8V!;4(PI#ihpTly^f`R^noh4Zr;tMRbKN zxqWDlhfDDK%SMMB%j$&JrHvDo#!md*m$3BrI{ww^udQM_cd8_I*$DOIKII{GmoksCd-df6Q?|ojI zYR=udH`P`6<;H5$kGv0WJfsU&=KjcS9Pg0Pw88wd<6M^&kpX*x4oq{|IYHmMq{`zC zM|YF7T+``NqhC4e$7VPBynAc%=A(9L$+q_JljHqMKK#x1N&d2!@#^N?v)O`gbl00- z);(7kH7)9)|C00d_te*Amsv^8-B6q0Wa&7juR6Q$@^R~vZbKbrsx!;J@9mFbG5z)3 zPk5%Ro~3Ob5i;X~hK9!NuF@qdAD@wSk1l;Z+h@Z*t3T86SN8*lgKE;VJZUZaagV&8~ zx4vP~TzgDR_Ql`crxsZnKmC&J**z&c1%`>Q&%4YNc6<)LmUZGq@0B@ew|H@eH|H$d z6z)5H%+-^XdoQXin4~{-$#7|YW7ZS5z29dY|J|G)QGat)m2KD|4K2+`i*>JG1(kP7 zT%}LVJTVlzIa{0A+4l6yzE4;8*1VywQ{OwwpA*z$ZVHp?SpmVNMI4^Do0D^kzlzi{sQgrwlV`SQoy+;&c{+0=7+apl}waSyij zSRQt48DDxOzC=Uk{lTdj*?BqfZue9+Uw0W)by&K()*Gwoxg^~bB70VAN&2^s>YIX# z?1OjAeNpKk<#>3%8Gla8uACmT6*SX$n_Z^@S0lY+-EH)DSwHjd-pt#;ll92%N^&`) za?x?rbk_`xJL`_v9^Y@LWcYr;=-tS%0fiR&!nEq@04$aO{n|7nM z)$3Yk-!#A59zVLX?5%{4SGs)7{c}U(YJlC0(>f}Jf27;Dm@X<+_&IfA#>r*bi*I)6 zw>B6i9X8RMy-98VEcUml`Hj}fU#{FfxPA@&O-1dvGr@|Zb7WQ|=6~^7w1Sbjw`chU z_g}Mb_pO>Ut!2Xl*L{8NZ)bn_bG?vhncAFazPYMe-eNXq)F=5H$7D_C(e_?9U3JWG ztmo#~*;YJR)!HcOmP4zL7yq)8t~ga2)jjn<@{+qsl}n#r%QS2FG*LmO-}uxV>1vml z_C+4u*#o{-D?)EZHYyzrc5%?#_T)+T#+&?`h&QiOzuV8OQ?j!) z{&`U^+oIlf!Sx@Fn=NkDo*0lg68SZ3&7wK6M!)0~zgG!*CF=9ee>0i6^9H|`<~3^K zLcaQarP*q`W#jfp9o=2AwD+KP&-_b*%wT7kf(VWX_n?Zl6p(B^ z-gNz*Y;Sk%n##T1N0mpvY6!H-on{=l^s0%0OslM}=hpG763g6gFO*?s`Kzwp!JD?N zB}mnGee)q+j_~_bmLu2}O+sP&_i;d5>=C+=j@i((EA)&tcb7TL4-#w7jov_wbGrP+>U$RaDYra- zRc<_P{$SMfE=%dt{#Vye)s}y^vbdl)DKz*}%i{aIyzvt&_ZRFBTADDbWXXPd+>J(! z#s^2|tDn&I`nr0It=7BRafLsEBDcxD_XzhK@AgXo;aD|lm_ zn!}F2U6lV$^K-dA=h9%+-q_~hmvyNRy`#^6=cZd$UvB?Wbh`eBYo5b}6{eeIjW$dv zd3OInhun;$d6lI#3$wP~`F%FxWe`g>@3r)j#+pBqR)tHs+!C6var|mriw3I(8D1Xh z`tBA{iZOpU=coACQ-}#i5Z8kZh?eEJ-eqX;Pzhds*;RD6{B%2~%AAA~XR(QD~$)_>@9g6Qc ze0f;r-m}{N6UM=X=f{^8HfX=z*0e$)^ZdT~DmPU0-&W^@nMJ7YEZb-}N~7h{TFj~; zDWxoqFl3X9tw5vyMRX{q$9jWlqMn*1@WtNWTlW89KG*3)O3>hIa?@iXa!VhHQf zzEf)otA(D7f_Z1X+KwF0^7OivvG~H3HxC+;3%j>_4KzM4aQ=GGa^BM~_YbPCeY;Qh zn00{lp^f$~YYy^!D(PmW^8+hvm7R{hYtQh`GTWYh=-c9Sv^U1j{>g(s+Y_rQxAbq^ zZP8nG{&iQ<8Tnrixfb?Gsna~>?%H|o&QDLRr%BE(y``Kn8$7GS3)ky24u%8>f6Vo1 zpy$onVYaL7Jlp#1X`NT|*1U<#+`}n5=IA4H_eJa41zMF$qW!~88l2IVm>zs=Ph+Xu z*lRb;o_|oaUF-J(teXiBnF;>5VW+uJ{KGFZsE4gKaX!H%v?U#6aSxv zpx+Iq_oIY2ExqFBx5@_I+R;@M(NMdi>(YYd>9$90UF8ZN8MGcM?w3tB(r8U+v~jC@ zeCxYS$AYl#lrsz74<(NE_I$R}^_PFG%l^!(2W-bxn+=@WKk0+n%3pHBFXCjf{4bw+ z|EHtk<;BW#Rk=TO`~MmZz4WO&)qT-u$j-<1bCZ&8zq8ShmyfOLPiwQL^rV4=`VbSH zx^b<~zuEkFaIAQNC%0So(?T0P@7b#oQeCLr)}cMwxPjvp=j;xOLb4 z=%(z;n^r8lu!*~lKj+ntxlu}UqLj3wl;%dIYn3l*z1YiJxT$e-xbpr#Hw+hDO7T2Y zC4+5_n55YD^K}2DxBH6wk3O$Uq9@6Wn-~6V^7rTLMQX1k>X#m;J?q6nek^PK`?kO3 zQj1|*Wsk=8TJnvf{O3^ply>8eXSw6_Z+IxJ%3(D1H2lEz|$6hiUTqU2Fa4 zf$#H-W+(6eYjMxcCF=Fn&BnBOj9(#}Di##>1l0z4J4tUn;J2^A)on*(t_3z@cB$Wo zb*_*ZVO|D&vFyg6!B-kwp3*C*YxzOh+B(!+!QaaF?1L?5Bs#m-3cW9cr3_)Amj z4f-vFZx;RB{?tEz&;HJFpN^&*-R&Cv>BziUHLI^y92(r$=Bn1txHDz0Bu}^h+rgRuhZn zba#@sHKw(eeSKDxz>Kx0X>J9KMwnoZY&;_Drh;77rwLmhC$nMiTD5cp(l>TWlm}z_xQsn)Nnf8ajV)MJ>78M zsVUBL{ombva{bk`qO(srPTCx|Uc1(RVU4%tf{gs5!S2Oltevm9)Q^?Z+Zq{Ld*joA zRX?<&ejGCu3aY#FrfpZq#nji$yRoa(Lg<>(tb6s;@)-%WyB<}zWtcctZhy4xT$1JA z82Kr47THF>3o?C_HF(po*JR3>*p1PdHx0)<+WfV!d*kzaZgoxmnqpyRnPZfkX%t+p_RL?0vb?Ws!CnkD+f4wU4>&A5#8XaIUVX_UWmMXO9*aEs8ybeXm)zps%E8QT!>-?=|zzc8tBXV0GE= zoZ8yj-7hXIP}%;V=8<>p2CHMoj`g9#e-+fvR_n-jw08}k%~?(#tMYc=bDyFOeVzH$ zt6Z}qZ#}ni)(t95XH=Z9nVmi;IPP;e@nYZ10lj6)SBx9m<^)~R|J}S>C#LKNGyOtH zRt1+O4w}t&X*R|8vma)FG$q==SSg zPcQ3#S#3f){`=Tp^KJFVo-)!4dY&#hX`p#vU){?$$@5ChD$J4_*R@~R)Rz{$$Sg+g zp5Hk6Jbku(JH zW!#~mcW9%aMc4>(_71I!PV;3*ynF67{bT(G28O&Rq*-({i;hc43#6auRg~6J`OD-9 z2b?7^#Dxyr=F!kRnjEx1`-AREC;e{o%y#i{_QJKDgx>}l+CUrY%OEY#4vVyvdTEt& zpUW_Lh%ezci-%WdNuUABxFm#o<)m!7-9>C>lY3EMU#dW zIK9n)ebwI=fA_=gMm~nTBs!2xN0Y&AAT7`q&{L`F8g=ryi_ls}3PTzQ?OQtf7HCNe zw5_6BcJ**4dvVPJT$@E``{`&u9UofK0&O|HjPiR-mR;~v*dWbAVu>sJ#YKK`@$n)p z!dB&Pfmc?wHb+p|VlBf%!U<_22TA0N_GOS3+_5!J8018lFEf!f{4HV>hFl|h@SBGI z2BSb)(1ZJ;QOG=6@7VZalROW3K)6jqku(&)yQD?f8Zz@?4?44#bnUj{2r(p$aGOL& zlfWR57P!q94cL=8PwqbaQ8x}lk_qiq26~k--j_jIpnXeEp$4Jut4+=Bm##_}GE8XS z)6n-cybGiST6YGV;|aDE#uFaXCu2w*p)IGQ<#btJ25Et|NpvIb%v=?$+x!RDdJ)tef8!V%7Al>7p3$zZR{#L}tJc{`+2iH0i!&^i{i)eU%Nei@TqBXhAD`Dr+kVstXN%;LsL;r&Q zk``zmi2Cch?0T|YcJ|9BjpET=&3msLp~AOGCEoYhL^NJ+b9~|nU>ReQw?))ts~KePc-xsxNW2b zS}&2`M$2fGBY$R2!;o6SZz&xu1%62jv<)J^{ktA__YDf}cMDBUtSj`?bqC(po&ki}>{rJ`%#mub;FaF6u$A^B=y52smson}_%lQg;c& zT>|$?TF?PwC|z|fC|%i>J{Lpo6CJomNAH0JNm|f>i;t)^HtG13S3RfB&%+QOLh4FK zUFq_^_zeOUNdJn0xbofAYGGa%acvNx4WXeS;JQc)v`64|Juq=AeXKoYK88FeqzQC1 z0rY^hK$cy(*f9GHPj8ZWm|cZW9Q%uUN<{ zmW(fhvo20IfAqj+AZwBhkQ1fMw7Px&S3JBic2e&Xg)fZ#P6~gTY z8u|frfwVw-UDSmwZ~Qu6yAChIkUxaq3L07gw4?=EXOVWX+ooswx7QkA$O}T7NJkUF z=#my_^F*V2PxtZ#$u1{cdxg*r)6iiWercoy+Hle6Zna+?z0R(EIfmF1{jH&)HJ}fq z1zJy09|B)Go=lkbd<72)BD7s>q>GJ557Hv+iM$nX$WA{|IDX0F%1R8mNp!)VhWdkf zLt5Z=Kb$vTBFn0!dl{>E$bG_VF%v0f;%l6=2z#pRCg}C|oeuuF`=fAa03q$*Assy2 zD`~;fF@Vyhs_hHt`b$<}h!fEPdpc@Q$H#!QpaW5&F<74ZX>U{id0hLN(Eg&MzrZd{ zTA(cv?b03gAzRy)e8;spgtncIw$t%3AT7`qi?qDdzed|Q!qpg3LugCrXbFgPqy^e~ zQKY-kpuaM7#ii9e#E-Z%I{{)Rz!xQH!KE#Smlh^aH*glz8Dhvs!fi1fEe38$3*3Gd zxlQ)g*(9?vVhx5|CER|dp`XF+B`whUh;FZRRomGY3e(nNNC4qCh=vA%dq!HIJp}LB z%~<>QftDIZ7~()k?dYf-7+ul=X{2a$WlLCo><=rAc}P6bg?t8*&yezEkQQMJ8QSp5 z3>9{*yRvu5MjjGHNFOnfM-0rDL0S;+kWP9xaT1N3x2f(^(8-M$5<~Q$j*iyRm3$eb z1wAHZf8p9bLR(5hOTjH8EzmlOZrSKNfzrxPn|ENyS3+ArLkobGv_Shzbfj1! z&E99$^bObEBeZwv=v@#&NDH*qaEI8~%Q*S_YsO9*Z94yPkrcwKAA|14z-Iz!f!F^K1U%^!J$)S5qB-3HLk0<96%DNdT_r6Lx`{4} zb*tOF^}>Ia7~)1~uhP-0V22_t(Eb+fP)EClGud6HdoU!7(1z2{a4>603$!QUtfkj* z4bv1#aA_kU&84HcU<61Dq+dh}=f<@)XBkx;xb_>NEu^7^pu406+7!{qN)&oBbL+MC za*;|x8&9Lh)9@KiTA(#2$Dq@uarWehg;p5ymk_?Aq3?iG(gLB2Xbk38sP(G*?K*-X zeuOrFh6aG^A}!D!fY&u8&U<_7>^&#&7*0s9(9tVkHIf!cBSfol+}i95QyyF4+9pDq zM@RF(7?2id+eBkf>Gb}*W9Xz)JS2pe25k~Zn*<(cNQ-9aJz>b*@E}>AG=bbE@4PCA-qpV?}N)CEfCtk$^Aw%)Mw*)%gY#& zM@T#AXeWr^qy^F{(YlR1kZHKoqxv!zNhP#T>GY>`JRp%4Xm^mmzs**#azjkP6%4ry zPM=P6)Co*j(gIzNXu^Itv_^M@N0c2GsUmz<(CHPxCuxCpC+Ty^BPA`#qHp#X;!6mJ zXy_0)B#{;fAB%1)ZPq-QVw#x~hIkX&K^i&;w4?>vMlgS5<|`a6lp{8XVNypBJ9c7HYkmY_C_l6BAqd$fapOt z9qk6gN?Oo^_o897tVwtMFJ#{}3~3>>1$49k+%3`q?KjaRv}?gsPB7+rU`Rco&7q?? zKucPnZ4qg?+<{A9@h@)}@`KRU)6jbGctcvC9TLsLhHo|RxMKvK7!pEgLuqIzSYMnFlGJ_7HDHc zQ$}-7)VrPf4!E|L&=%9sVz9hP3$z2GfxT=lQ@Y3GeE<*fAx6QMgZOgrK9Cli5*Nc! zNHJbN`q`07w=krFa2rcQV`=!ZAuVvbuaertJJ|z|C9O|{a*;cP^e&Bl7xb32Kx#>@ znx@5Hc}vXJ-{v81#Ls_|M7~MlTPhmPI>H;lBv z?Kv2WPJP{yI<9QveGG{pq){|93QPmi0_hnz4ctp=CL7wcMDvh1yaUuEyd{O)l9EN( z%AD=+*FAKeD6VRsAA=#Sgv&xYS_pofw7}(e(RBG4RdD0)xXO48=^(UiG_(y20BM2t zg=he5o;N+*9Nma(n+a_`9nA-RNei@JMSiQW)c=Z;7bRjyFrmFgLvMl0A}!D!g_pH< zF*5T#<8&eq2_weURT6QP#K)Di;C8KpN4}^vi(j%|?0AMDc7#_qI_d^qK9UxA?G**t zsY~nvny&o!0z(Q3?N2)T6GS7@0__LULa@@z;<)W;pu)a%9`fklM5xEZBgRG8YEtuHUx&Wx++KLA zFO!EP5tn6;BK9c0&5{;jPZ>1_N^M>o?|(Ljm4hMi#LwSgpf|u9FVcda&k!9?o9iA) z9rD@umWz}V+F&|87;Imp1zIz5A=29tX+j^lJPfHOgm38R8!%x=3xu_z36mkY_jq@n zegTFQ5!xO)+5>JEX@T~m=yr8Ue#yz1wi?$4k{zI-!C-O)6BcL>!^ySsO+wg`X-2rT zn~*lq&?c}SkQPYoMCYyVWgQi@Pt$O1I-&hbNB`3CcdDcX+GJ4|>>nIy`rX@uYwd`k z{YXPUf^|b$p!E>>-MhoXTW*O_A%^4AK=nR3$&FYzfOt5BMo^waBUZ%ZKR=% zpueOA+AAWzDlV$gQX1vB_8p;(qoHvic9Irotzhh&w)wxmF>9lWG2}NPEu*1jpu406 zQYVqycuVKPq|<2?T*Q^Qw68S!R~mleA}!GFC2wz~Z+^5#Ug|pxi6xxAprJ2l_|bs0 zK-fY5LIv+N_9pY}-b|_DB4vbjfKDF(OM$dNyPI^{cVh*wCDo}KL!J^sHwNm)085;( zK=?*95x2E;@a}Ebf6qm}5ZaeC`b%)?CN0ofkWOc5S`EL9j(g8Tf{9DIg?~HX;iF1g z@HDduE`;-2(~^}|biT(Bf5K-V4Gjcyi?qP!K{&U*<;2g9PQCsCL*fXjI|FqGk94F3 z(sWT*)@q7RSR$YVA>Wk?IoQY+!5 zMIM=&ClUOmk&8Sc+(y&s(I6s`7P#F-PJ|qxR+|3Sbp=9imWI{>Eop)FhNuHmGtFNG#0=ruV#04P9qk1Zk+eWtBbtcZcVkn! zo~iX<$P+@FMnls;oFgsJwu|E2q5saUSQf9)iy_YltqTKn0pW|ZK$|6s38u>jB{B@6 zeql%^q3xriePErF7HCUFeTYsD?{Yp=-;W`;2yGY*4Fh3`v_N|thNT~NF5X8BP7Lyp z2yz$%NUZ>u))E%nGF^Df&?3!oG|hoQ40%X+{X|DUfgX?+czsESFS~9WaZ66VqB_Jw zJP5abEX0q6&l=K#$+!qk#*2m}CsZeG9m0^egxd}}+5rZaw7~5<(S>b(z43jwnH~N? zrH#<$)6jfy(?|=nPenKQG|)UY9i?<&TL_A84GdTxffg7i>)dKMDwJhdE!7RPrCFUU{zkmGjHyogC9A`IynZm zg!usg&mwXIAOo`j07GU1Kn8yM2MqPSpQ7NGe!?61b)RD3hkd|YBR=XwZ<@#S+NqlWobix>ANWBV>Z3kI_2&u-3|eB?;1)gMO?bl7fo*W0ilBlzLh_rl|K(MFew1IrxF1us=#=_lY{=^0{1tW!kZ&*>kvmc^zXL9bOGRmN)e!( z!0Z6Pkf{OihhZ`RV5kHDidw5&zG-F3eT;+uaIHY2RxnGn-0)Y#0`#+hF9z6Q0y|7@ z1TfDITPz0HV?29ov=|VGX#`@kL}3^I&W52O7+(xX!vtxV+z4P^8n##rc!}{|Vxu7d zvlYO_yd^Rf;AO(x1i(=F2o%-V{8)K==o)FjTw+}kO-7iZ0B|ZRfocI05&%ObAy7>F zZ{x6UrRt*q<3?k-{aaTsGXXHaiL3a0)6j|Vs&J>JC|ZiL zM*x#c(Wwx?otB{*WvG@IP=TsdpqgSp8!Bu=RYb4uz~^FFcL_z&$7FCm9DPq>oapoj zmIgmtVl-SV_^-4{jBb+{Cwc)4p2y`}C6z=^>)`2F;l8A@=-C;ZjFj>u)kNne@Ww^? zo1}*5eGJ|YCg#qR6QwKQ1H_yV#8ejpf|;X&nPbI(hfMB6<|xsr34i0nlq+T`iM|>a(o+$=AW{-Nz9xFPff|q=<#cV~Z{omJci_$x101=0NA74b zz>llo$5j@6(!rl3xM%>ECk8}t)gri>Vn7yGF^j7zdQXf;4leqZ%M%02xawuxnPR{% zuJ9LE1x5(GWBpvTpUV>i9C+#uyqRLaEuP{no~r2S3_s5B&@diP42b5bNAqTi0a?6p zS-eSb8^eDkhll3ycw#^)PrZ~kQw-?f$#(D*MPH8b_xwDxlgASS26);7JUuZWgg-ij zKTedVfxi>xqoI7B7!bqPj^XQx0Y!YdBEFI+T?Jpre6*C$69Yc+wLkIo!~i>if}KEF z^xYS~l>*d3z!L*J1=^khJux6oAdC~JzqL^fu0ypkMZg;S%nbt!l@CTSFmM8f%KoAlnD_-4D%p!-V44?TsMIcsxtle6u5p;{RB-3xC1v6z zl_>&&>0Y4CCnD7gGBCLdFjPVpMZuX57%F{>VqoSLV5oF0ih)s#V94YwihKbKsr9fhIoM#OJ`tf&(`N=uH6!20|S6<^~ulwT+@+QX4T5h=exS2IjB&dHDR7Y#2XZ9^xg&rFOu+-DNCC6qh@T-c;h-}(RRBZfyHONObps5Q-bOJnu?;X( zG8@IfG&aCcscRGilhy!3C8|*jOi=^OFp-`{5eQ630}PdfMp1As0)|RCqZpWN1{f;C zjAGzA0t}TDafT5DaCqnj8&MmI5l zjBa888QmZdEqPG3V6C(fc+=s?7drB%Lk0)p`HJy;O$fl0JYvoe>3EQVI~HK5q&tfG zV!QjQjFG1?aNjIYY!*y`ZEzqQQw+yM0Jg1N^YOkSW8yHtkd0@IgHrgMJrQ?LCF)TW z?xcjlEnx^@4{*Q@<+`ClxM$)(7Rt>+g>cWrfesX}vK7KT69>E`xLy)MxM$+PLkaFf z2_f7waUfrUn=c_0dwlJX;C4s|#U5WhB)J}vLb1o!N0Qt}l0vb^*J4R-v7}J!@wHQu z+bJm&dwh*!a^sjnv1idrCbyC)gdqm+#}Jb{#1z7<8V7<|++davZq+!D&EjUWgfRZ% zfIFM(&KAO*83z*B+yu4|?#wt)!RA)5g>Yxafj&03k1d4J5C?)d+#rq+?#wul!r`WH zgklet?>XG}93k9yaK$Yy_ZC+u_Q+Sr2w}X#ffNBZMIeN` zJIwL~QdZ$Mx{Tw$=!`oCc&`Jge&PM`Ju4IT}GY<5iXb&o`=s}fxP;rI7 z1nMs#u85aF<3|7`5@^W?;HL!oa|GZm$@3nuAID3g@si?BD|WF{~9-=2YdknPTD^9ed}i&f98^AF9bE1miRTfF%S0eB7%T zx>by&Vn7CpW}rN=z@3Lm<)QKrzUC3Q1iE;0ki}i)}Hzl9PKSXN&-}dnNV6 zfNM;_HM}~4D*3{FkO4ysAOnWjHdV}AP|RE=woR2X(NZQ)45(uAtC*ul028a2Q^kNf zrc@nM9s>B!l2K>`0HP2C@O#_HRBvR?gaF=z3`=l#!~rra!QBxD$gl)=M*;w02?Ds& z0@maL)(i;X3NlWKJ?fHi3IceO7S`kz)(i;XO~}9nw_E}MfeQk7lR&m|AX`HWc+6h# zn7s^c%6Jnpv_SxGlFHUfW$TCm#q5Q}Yy-G$<4wrm2LZgvNA~QG>;+;#H(Rm$-y37R z2^k*6cKRXqoFVo?G2kX=+|7UQl<_8H02Mn6L~y1=aAt`C2^>KJXAC?X;7!O73jw@i zFF7+_a@qw%SfvX_~^l^oK|6VfVO~^nF4=Ff626A{v!2vRmiyczBcxcy%*S~{2=|P?X zJhk9W$WRXfydPnFG;GA{-v@l@2Ydy1uECp-n*jvyCdGWY;t}tI%lK&7i1)#DeCayA z0z3-gKFIw;3?TOp2;fe?@Ht=jGGc(E0CgPk#`uOn`i4LO9;a}pg+()7SO&syY zI71+vAy9w^F1!i3DM0{lQY(T2r67PS0x{V@Oc8!^#1-VW1p!$70=6Kk z;)U9Rlmc{2d@WyX15XuI43#RzT)3gZDj3j)s(hg+Sn~oHs?LRCV1)}{?h@54&>Ng~ zfT4<5C<@lE&;di#uD~{Ump-v3e`0CF&{5>Dz+haZ&>TpOS;k6YLT^;w8x=i@?Tu4+ z``Dvof#EKCID#II_~#f0F3*8G3clII6%LrZ1EwT4nhuz{1EwhkIARKp*n|;)y5k6i z6DH?`jTcimVN;wiEioV+lS{|O!#jfiY&xcvj?EYW=%!;!#DENJOa?Y?1TZB7(-H$h zrACKJDZ(!WxYJOnDWOtY5P&5=VAQEHA8O1ZQ!Zy8Ojv0N?t3y*J((%`>JLkQKpU#u zhiaqWmQ-zd(voNs!Ce%=T?=mjECB*-sIni5y8rz^V8X`WJ>UgLH3O|?uwWa|SriRL z#esJy`fdd93q^m800Jb?015FX2@+_+2%v?DwlKvNPAt@kB@RTe(1;O05eqFE0kpEv z))7Du8x3NM`*_YqpN{})*l5iNV3>^#j{qV$Xe3A6$44&ukt+_w^3YhGI8e<)t49D= z`RG-?xFV5{CXN8U^3ks&fItBnC=hRwD?oGq0k9+s+&ZcZi@HOw01Gfw(G|tOax1V7 zsS+!S!Eb6kHntwqfZx0LbrFg0{$%b2^DLjGmj5p`2$o_2_f+{6<>Z;|G}ZZ&rT2q2 zLFkMibO}Wu>lwF;XBYi<2r$=C-RtN&$lU(nyXE}=;|O4yS!&HJ(MK{^#sz+dD&3+Q zU3?y)bi1?mIC%L|ib|KFqR%S?FuN382HnE~FW`hK>Y^xE&IK5%go|R}=@u|l!4}29 zS}nj(^;r}Xyv8Fd|JjF(V}mzWI!csK%1sKPCZf;C&<_E2?N z6oWf)K=}@+JbeAr7-_7x{G2iGf*AFq|D2}y(4RqBTM{yWH@VbI7^hE1WUj$+zD0o z_3v_=*osd7cTiM$%+?%n44hcZo+)<7>tavsV$T;l!ufKh`Eqo`4rqy-Nr{|UV#lv? zj#@cqj@aR~W{R`%>!i~7$M0p!E3% z00+AW2LdounHxpHXHURTRc#al3)%of6|qsw1OMdy14$p;z_g8J$j1JA7uw`=bpH5s z-D{xD6&mZxzi&YmPs4{!PuX`3wCP1vdQolIH&_e@+E4{>6csdX&&K7KCb@%In#YpK zV~IzIJl32%mMB8NDmmaJhp3Q)?qN+FV5mAcih>nzfT611DCT@=mE}bb9Z&H6o=kIs z-UtAsIf(&e&e8|~x8fctgiz&RZ~Y%dE-{EDH^xv zCSXiirlODbu*weLRAn92;?wNRPN$riWj41c45farMf$MihbY zc@?jW`!C!ApBfvOG7ZcLkRgEC4NTF#hXal*8OITcw&5(9@P7a-#ps0?1P(><|u+r%D*`aDY5j!hnYZECO67p0DA7=2MB~O(wtl|K9s)U;t4v?oxxGHggJXONY z3kS$kC7gdaK%OdLyu|_XR0;PP93W4XaG${e@>B_*w{d_xRl=uf93W4X@WB@c$WtYJ zti=KHR0$ti;YETQM-^yNcOTYf0*0!`q?iS98ZSbU58MSS#et{iz!R+$SfmNsP=%RP znYhOLs9}TAJcGhvPaRMjO#6)arl-of!n z2A8*kwL=s!@eW0Br6af#p^HuOttxfc2>0dZ`*z>aySqW57@qrxXK=O#wp{m{JTZ zEd>l!PD(MbkQ6Xf@hHW>Mj6{TRBQB|ZAgLkM6 z)o4StVX%ZXrN9YQM@mUy1u0;ts!@u8^`d~GYD6gpmWKj{DhZ_+SPTjnssNN?VCg4d zsB%w=frXxcp^7^x29|XKhAQQx7+Ay!7^-lSV(RJ!O3VJ}6a(fI>y#`7Be0ee;8gu4 zMa}E~Zu(>Ue$vfk3u)AY1e->|e02O(TA5>2#baVW1@= zzRbFzsN0ASvDZ-a+6W*EMYBc#9Vpr{0`QVRy+(X@eJFuG90BA@p!p+!4hghl1mGcw zdW`t)`bZLeGy*7=M2klNos#JPsy4UKII1v?XFDHr+nEUsf=jdyX-bHm(p60bt$U_MVE?NP;#lH1)DByYQcD%#v6iS1(i5ev|!SsNp0`;nn%~P zV9ld7EtvFaQro-D`;^y$f=>l47zk)U+q=yMlnn#%s0}r<;7()4sA+MWlE>*a`5&r+ zn^x0Jt4-=VQLA~5L#IaD=|>YiLmNS!r{RcIKcYSH%5Hr*eBz07%~Knmb$9_+?44Ka zJyIN+xqnmtSlxLZuRmt@hrW&Y*i7JHqZ6^OxqBGbVfTx*-ePUNJaMG<<4)jQ<5bbD znLx1y5xbfRjA{^ZshPl^1`%_b32bQ)sic{}jRp}dnh8{B5RssnKzs%f<(WzUmhKEt zBZ4y%NXC#YKLva=<VT zVbzb}f}gnHM}xb5;;t5)3KFM+=oy!T#N{v$iP}|zL7YbSs`ml2X~1lkLQw_h&F1rF zQc4#U%$Y57<}0$bt%3(;>jU#uS)i$4*=t<(TBXWY!I-~m%x{w_Uj;Y(rW<~{RQW3C z3!3|aq*VDTmnO8tCj`)`MrnDoW$zObS>^xeU4 z?hk%(pQlza-cXE3pKzskdnx{o-0!FFD^6Ojt093eMd_|3;&2bB*5a z!o|Os494ui@CP6}^-Q3Fqm3-@n85lL0^yqpBySMWyO}`g29Z*f2?TBsakrVk*9MvY z_TKvIpBEqUH$83EpAHLnakzQ@!`nt1b?PO0<`TUqOWyYmfAC9ZtmP4RGEaNv>1~`@ zBYrmz45u4NY;GohY?<8B<^{OhOyFw+iK)#5b~eb~XZNQ!-dy>QuVB@zTMbPHF}Ar4 zEN!&;B)_ook-faiq|@%Ku4%;E<{YjzS{%vj-*<2Jhc*5MRh+tt6P>XWZry}i4Q6+Y z9DTR-t93p#XVm44sQ!{OcIS-h3u$q`c|7>u81LnszfQkzu5L2vwR@|T_L1@JzxVFC z^O(QwN%BrowXBl`47Y#~j=sbNX9E8lL|!Q{f$a?^jf{EH-qP7}z ze|+>q9H$TXQx%uVyTA UoQ@oiMvl)!j#cyOClwz55BrvMa{vGU literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/asysctl.h.738EE6FD4747F368.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/asysctl.h.738EE6FD4747F368.idx new file mode 100644 index 0000000000000000000000000000000000000000..81563c7c0a5af3559d6b382c43c4cdb83ea995c3 GIT binary patch literal 1178 zcmWIYbaR`;!oc91;#rZKT9OE4G6(~4aY<38Gb00oI~xN-#hkm7eEpdf1=_yfi9ZdYt%ONl{=%x!kknH;;^Vzbfu= z%UQT_6|X_lHRlx?YzZ7%-pxpvouQhUKGP~|V&Lb=%*7LHRNUSv%+P%%`^eJa zQpC3xI!lVzfBYWT%l`X$Qp4ZpTO+J~7Ma<;)L~7JXjtpkWKdDI`KsLWlv9`GW9r+s zSh;*rwD|UP&)p?k_C-G}nV!3)QS*7tv%MELz1r0?$7Fh|K-2l%UsrMkh;3ggaQtNG z1#1qs>ovi5?%&zFQr}$kUErjXv+td}bewSo*Q*_}4Xf8aIh$=6W9i4g<-)e9@_qi* z{6D1Qk`&bz-L|w$pWuD{mkQs>D&6fRwHym{)P7dX>8{xsSDGO#TA&iDKKmE=A2bp1r$9ZOehUuGV#CYV_~U`+@fL=%jEe16zP*ZEulj69s}jPmV_x-g0L4_nt3 zO=}4Pnij_r#|0DS;VfY(LE^PDva~b8`5Pa%e6>(94+pv%qzU0}kS2t?A(~+BUhyV# z=H{T;DL|VNSQ0o8HkGlIA@MpHSvncve5JDsrYhXj%wz&OPd?57p{Yc^1kU3%*m3$` zRB#^Hb4KlqZZKsqrvQT;6vr@On2UhIkeG!@2y(3pz0SUSG0aw5zy7EXv0 zVWzy3n_pz%*mVjNg4}U3FtdOm$X$ZOYiHzcXN2>&FEc#z?C~;#rZKT9U{DWD5gvaY<2TFpv%h;)*%R9;eTEZoPE8Urb-?(Mtm!&z9 z?h!sV#Bkv2KMb5#ba{JCbLv%Am-J852Hn`ao&5W+t2^wMkih+- zkJYp4BtW<$z#U<%1VxSCm)XCF)Sg^8mtsSzRxL=s~O+y-;c-rB!( zI6@K+N&F}YX8d^GgD<_Sk5Irv0Y6!SuFUTCe207kga{rYczp@9`Um1mzbPJzkSRc> zFh&B-(ycjVL)&7Ed1cT{l8FMd1`>`!FV})^;mynIMEiINOC)gQNbB z&r{4Wyqmyo!qybS$K9*(_{jnxSp~@|Luu;V*zxv@s;DJG3WXHP))dl|bjB|Iz!wP7 zN{CjnH5C?IEa^IxHyyzhT-glk{bx;BTa#~v;UNM;^4UdyVw16@&1)vYB>^r8#?sVX z2On)n9cr0{aF~a~{5T0VT+VlD+_-K&LJ@@`$`%{vT&WEG&(TE)9RxZETkK1(rZqPo zZniP4j6tXz&l}*1bI&uym?=+#Sx*2LK9_$|0M6$&&hP$3WOmZhUDsd;P|lp%AvrI zz`>Bb&=!=pIgIyqBYUb;pUE zDv@I)sOI`Pqke9hv7ed7nbKscvz}b4%$1AlaY=V@c%g|araGC2WPYNwu_)fS zM%6faEy76(C*?<^ydcCpT%F;8P(z`HvQOyEZi@W9u~~$>0^Ai?d1>|z+c;|3^34eC z9JF%=(j5MzqQb$;Z3{xS0NDaNwb3?T2F_aO?The=hgWg|I6O)oRa3QW8^S7B#b)Tx z8-BvSdcY6E5h{pKu^B83(}tNB-3ma^P|#2Yj{V^#<{cJ62xSDy(G>COJTd+n9A6CL)B|FQv%>!0v zEPoNf7Hru=`?q0LzT2N?h~WwX74p`~cTD>HswWqLkgbGlB}+!3kG6aHrp!2mXadn> ziZr$Lw%y(#KJ6lSffrlRRR;_A{1B^s7#<`rD0lAT6X*86@p2F$mWNomxpnSO|7z>{ zaft|80kpydX$IkT*4RH>hovKgLa3<}u2egvRE#hb!vz!yYH2Eqjj7wCBDRz*Jrua4`vB0?O2IAS3IKkM`R2IuTE5#CdHFSj2*DAb0Y zF8mE4i-#(#`*SaDswzMj;9!7boi)}tjkbQbun@r<%-Q>EM|QpprP;+8uA@*# z*{&BChNVyNbtyrJArM1YXI(a@HR97(X=e}`C^X1Vo%`&+Kh^lhRUoW`b!-n|+qb&} zP3im{!z~nAC|gml>3d3afx}!wzG2^s3kVt| zXq2qwt)9Fxsx5MPEkX%_68Tnby>nZ9o*%D6SPiRL;pf>bey~h)Qw sFe3GRMi?0 zrnl%aLJ$P8WT;g?L92t7RX z$YplDclo{J$rnXPQbLlFJ#+PbF^@B@ylFrC)>68Wm_%Y*luaV+UVI7{HH z+$Q|3U3M;VNPW&>D>lFB+2=JumV=FLuhohU9n|KE;CKr}m_k_*s&lxEjRC?!9bs(p4zJmToqOvkC+XLd-}&V`&H4U45#aBy zW&_|G7m$@K&5+;#0898$WXNTeECBl8SyowVNl@@J53?f0PYv@Id@q&m3+OtY%AN^K zFc*s5`udxyYg(^Z4nLEcYrA5v=TG$1TwGjOD_^+1kWdnru^7I)d~n}uuFiW~<~>FJ zQHAO9oF83-G=eJo)Af4j$w}%tJh;5C+M8=DE7>X z;ETGy9jT^)%G~Oq{wKrd$8yH{t5_|wWfSug(u&V`D&3&=eY>_uS(j&hU*k1d(}4Wn z&hJYa(=3F4E!z$K7Oj(TlT_7lvYf&3o%bCrjD>z`Ppz|dk9N2Apmv8gyF0N(yixz@ zCsK8QTBZ(DXRH0x1#?GZSB}Ztb;sAui+9v?igtdGJ^A(i;XwAW!0Fn#YkzX3)oy+P z**B)%y2qX4#8>Q^I{8)CSO|Zb^N!}rlt)V%ZP(hZwBF{ig@{~lI(0SJ=l8kicioo49PeBG*DZe7*|w^AaC9K6;Oq;mR$glD zS9*5nW@h6l5omq2=Q1@l`{CfY&U$F5X9_5?lVe11QmJ0if&}B&O({SDV3UTYkxT(b z0C23fv256!JNa+?GBe|20<55riDjBGg%-8|0EJ&Gn^z8ae0+optf8R9fD)r#egPwl z1$cZYIhuV8jRsqQzGx_e}OtfP_LSo=P%> z7PjhtgLQ8O@Cq8IfEg6h@pO_Yv_LSz&t(UF*JHgWD8Pk6GM-E_g%)r|kW1qg9@yrq zvW)ew3I7`O^164(y(sQoQx?}IAG6HI?DZIc=+GPZlaXdVJWyh0N{o*l_37bRc75gN zPOwop5za$C8VbbpL=f&UUGa`PQvEh;v%w-aSnw(JYgG5oqVz8BF!UvagpV+~1!Dc& z(80x!-n3nHga{s-AB9wD+dPbWnMYP%$eT?tn>9{uWm(5}4o{KQ8PM-q{S zCaO~%#owB{T!uJ`h%(^s#JLjX$qVHWhY?{09J0TovNm|20%9>CHeeJNi0Q1LE8Frc zaxVSR(*SWa5pA$hb|9vMgKU%-i0QZ>ynJrfM8z*}hd6?WFf>8&ftbz?vagC%5378P z1|SY5f*lcdewihR=^!DD5(F_FAB5%7a}s*5kjE;L=#2wi^vlo^00CkEY~S1pH@CK% eTSK-0X5&(l*y&z4e3RHNw6(K$a1;Q$P4R!yl(MG) literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/clb.h.0A665CC508A5A036.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/clb.h.0A665CC508A5A036.idx new file mode 100644 index 0000000000000000000000000000000000000000..8ba1f916b94d26f097a3d65cf4dbc0280ddfc7b1 GIT binary patch literal 26596 zcmZ8q30w_d8=gCJ?!9wc+*TA(q$FfXvSds4{K=Yq&6ZvErP8KSs6@C`~qG*?P zBD5eyQK`sMeRF2!%)R&f|N6Xnp69&hoip1xbKciyHFwsmciS+`e9PRUySERV%X8ZZ)Up=zBRqn9kJd)ygD(@H>dZ&xlspBtQe9P8#dAU=bQsJ zhxbM;^#!XV7KM9>bE+b{nq9N60a2cp@uYc{JN0nQX-C3RTXz~?@fm;Sk84{D`SIPs zZ4=}!KUdrKW@>eiZ*80QvySv7?YGY)4LtGedxXE*ey=ix5i2+Cn=WtmQhT1`5a-`= z4}1N{$`2_%qJAg!{0HqSwPP+%uUt4jeOb2pG^1y3qb8oJ+HlCoC)(W3Zhmb=mg@1> z7oME>C61n{Hl$74DtG(O)k?j5oL!6@-|cDG;~w~7zWclKtuy40q>srKZ=5yL!z$>3 z;jW9B)?Qok#McJ7k93^;AfaT}w)@w2$#0HsZyN0;cVBr<-_x1>h_3Lx0wl!|NxIWu!`V!xju2-DQY~56*3R64A>i(JUVKG3j z_0Gx_qFpy9ZS-(|7u|@RZO)!ju9cZER1l+MCpdh6)3yzJ^&J~Wt#1EuX#BCPnIS%t zb7L}Y3?F^ecSx$p{`|{E?Y~dw7WnASFzxlZWRFYGL*f1_D}K+{61_Y+f34_crvGuZ z6xGpz8_)LE+L>K>ad^z=DcBs>*>-`A+Ba6e2oC+TtZC_sSr6=YSU)_xjJL;Z)9wRR zs~mVcSKQWm`)c^?)Q7g~&K%AxPO2$SG#W8BU{syllIjSXwWAG9BK2%64=To#*Y>_S zy&-ht4xP(#tJPzsm8S=e@f7H-T)H^UPOJDXQF%Pn=JS$p%lyl|ZHK+$EmW^r&O7uyq1H(wac4xz znhimbpUyq%dQdbqa=CoR@}sRo%zw*0BlUY{dJc?ioj5l*>&~RXyzh&r?f9+d@PRSJ!N|r0af1grbGRb28g7n5w*;^*6_MLZh z?$$A-&xX|LWF5Phy?w!%G3|~0mCxoBt90HqnLa(uY2vTxGnMqh=lvO1Fe)Q{#f0yx z4e#`+)wb|I`@Ek)lKH(2yia{o-lpc=ZhMz`(S?v`Q}>$jx{XQ zjhW*+BI0EFz|vdK6o%f}*wI(8^~25V9R0bk#_p8g5tFxgfN$3RqvnyfPr2tt1h}>m zG0T1R@0>dM;pUj3RtruXdtflFM)_J?&+ql=z1?`dV&ylfh3{xl7+PO6A?9=R{e3Zm zJch5cS+vn>b;B;r&l9|+Yn}Vl>3K&n?C|4F|BOVZ(+6b73(}t*Jr}&73pZJ?KQ7tr zKl5!7npZPb--AvCb)(gP-Z{A|v=_~;@_coBTy>ho^|!pr@QpM63NyFA2)}7Mb=AQ< zrKuJrp!m6{f?R;>5Py4l89t6E{#E#Au=8>THHhTV1>b=B2lkX)(Tp7n)s%Z~nc zc=pudSb2$)(rovovf+p6hs8d)HZ|L1&U&?h?ZA z-+(3(%o;c6zt_T1y2mQ}4i_9y#w_3N_B_Z-@G!KB34+~?KU(!+-*9H`WLueli<*rPfjb=>9L zO6*UZ9Wh-vN~3P;j!_zpGd9;ar}XPMbG1;ftT2A+u8QJ_ zt8?!j`|fdTiFsV!tX~!f_02~p`&>R=;PPk3>&=D352$&xgy@;pz8z<`a`u_oLoVHl z>#py1+y3CmskhcTGtLqJmUKRtVQ!`Au=0oTxzNp%Ki@CBG@;zz$~5!b4AXG_$k7VM zkyZm5!hCuKShSeA~%?VK`s?$g$>`2Y;RS2~9ZFY4~sE%<8N`Sy6uTJpSo4 zIajT^>MC%sKhe3k_mm4SZ0>5Lz8j;jm^;M%*ek0^Iw~i^>L=dazs}sNJECev{^k7# z$2*%XD0o<^;{VR-V6VgP7B6uz9bB#$YDvQ+jyqpCx{scp(v*2;wpb4nFO^rW zRQsZr=j8h;tBlvA6t#YY%^kxz<5X5W3)R^eX`>u-_}R|hFGk$0__$*DgzW~AVHQdU zM=JHY`HNUHK-(wjLsiZ7ogw2hAHR9|%XU=2+Ul+`gZ~D1A1&8-Y%y0PoHXXEUhdoT ze^+cDaOtADz4F0-dh3?AeY2k5?kM- zV*=N|S9!O$N-kQv_cQaDqwUWe*G~D@J?m`muMf7)EN@SrqBKlVS1+r7aM_S0e@Bm) zP}u(X5xMrh-Y}<~!xy^kU)VU&-?pKkXIp&6jwI_61MT_lho*Y3l zkHGP$j!ZGmAs&(A3pw-M;&*6ogQlAF{RQt~l6mC3J zo~nDn^nCH}F2&g+_T^5|+|`-bD|=qox6S*j&n|9$W0<|k;PJi5YWLUv-K_iFuBrbf z-KQaG@pV-vW={KEz{{A`blOhwZt3^H^*0anz8v6jmM>Rq^QJ=SWOexGOP>BW6^`;| z0nH@;5g!NXD}?HAy7Re3cSr2#u#O2@rqf!IoK;pGxS~A%re{}g)!v(#p;s@w_50u;X zM)hOwkY}40-&`glji@UVVL|JP@pC^&>#>>Bdc(8N!kgxMD z%nmtGYfyAH?e$)#{nxSi<=D&37hL8}_cqva!g+J-d)uvn1MjWZhPV4q?umX`@n%p!aAfy^g=0?oUmvca z5^K68=f->uo56wi>Ksm{cf|Kkuztp?{#SAI_Ug*y2?f4o_TS?(4n{nioV7 zPG*H}J7uaIzq4ZAlu_|6Gp3(NaDVjn_3nVl_P^6l-ZnFynENOC$zCguOqHp3r+t*` zH~E(5#JS}vI)OuY!D*tw-|i(h%&A;-c5PGQe?v4Q6E^Sq))4vS^94<{VJ4N|;=NuR z?9|*g{m*orj-3|apTedUC_dPzx!UJr%&|##kNf)#(iVh?tOXx;CIx$)YSuYZmsPH7 zv4U@M=E6r?+bh+hcPD3WF=|_#*%2r7i$34zs?}%pz=I=&KI&n{`!nPHb%{p(m?m(U@{gI8>5U$1md?`daF*W5F!&Rvf$ z`KZ3m(mQ+6&LY(sgSZYmJTRfMdRoh$&!K8777U!f_h!RMLyMgL2^!-y$4>L`{#n}S z5~ii9H1yPiR_&?ziw52pVSX_wt0^T>U8hnh#H??E<#EO74VQx2Mzja2JTl(?eU0Wx z^P+66u)RBq-;JKp*zqVderL9Q-Go^aJUwTRxLj3~a42Cx~{sqs_# zhdinuQt@m0;aTm^471HQYlK-Jc;wxv@Hp@J=zfXko(d{QI-e@rx?+``UiE_KcS{ef zpK-si;o6SmWvi;@Z-069)YuW;WtBdI$)h_A&JNP-+TUbQ?LF~J|1bR(^&Ru%rT(1u z`QMwH8)P+r2% z{H!Mt|J7|vc)PTy3il!Q&aMBvtL)KFo95WxR|oifvf0}c{7mg={C_L(VT$u#e3?7$ z;}Hi-*GYC;N=>7y{Q`u;r<7dH6sJvS%q${}29D}7ZWuI`H{kT|n70~Xh3}1gGM2ry zHx*=#(+=XbD&|fiepK0?Gz|%k2=aP6sMgKtMCh3p0X8Fr=1C(PJi8}0u3yt(_j>C# z)Bc`O3Y`r$OY^;jJ_p7n#}+reY`OJT!+l#URuW#m^6Sd^Yj@qyT-j`kxwiWyG`Ezq1x;%fq!`%wfalkhc{pSrwrTh`P1g~ zOKq->f-sXFyUyt6XUw`A+p3TJ`(@U%_5M_kg`s)1mjAsS@~&z^+<(_=<3rqjZu?QO zIQrqc-Fv=P2K+p6{jGI$&#|v7^ViJ3y3L@iUw%z=My?ghV861vOOMRi1YN@tY&+gLSyJzP2P;OE#$2#1!-E=vx zHP`*n)IrWlT?rOXl|?IbCtqx__;7trS|5?g<<6v@~v0cywTb@q0u+a zFW+-?txmW`$NoKjT5k5QcC@75NC?u6Y&dYhEbZF5AH?qD4Z4qi-f=J-yXtz_DnsqG zU%zt%zc(&5J$lY$& z(5;ODW-ZZL=R9@x;G2hAHjEv?GyF25U}C}b7L9H{#a>?p8q1G$|HKBU-Pv$z6~6J~ zy!wJCnF;q_d{^|0%IH%u>Z zjTp4e*3aJe;m`}?X7o-v&hu{Hb>FxB@0<%^RyHB`t?nt^YSGW^t>t$(A^!HwQ$e3S zT=I)8LIa&G98T#uHSb&LvYWr<_{3Q~=Nh`RF+0meMPTjHX=NjumgYZrQfoY+cH4=c zXD3b#iMSH&vsLFwi@y8Fl=BwHH22KYF5H}`v7Y*=NU#4IdtjV(@~wz9OO{6&7*_cD ztsV^je4c0gJb(9Pzg_wHb(2lduVq{7cEtWzV14XX#N;K*gA5F#XTd+ceRf>-s~B!r zz6&L)f;#uaN43*D_4))UUm1=`*~GMjtxl9IHT3w_+!0y&!2z4w0cezotYZwsdCz3 z?$If=>+N=XI1N^bnsanetw-jhi${%A1}@CrxLiGBt-&E@munC1yV|?XF4gq&{%?=t zNjtpfz}vhJAMO85)$f@aq;$G9r>(86S6Y&x4NryOpQacMYGa+@o2Ow|U0HH$CE$;9xp-@YwE61GO+LEp4vBC0lb` zj0N*B%!{bNK?SahEGELROgx$ALGZi?zR%2xF&!(8QrfSywu%R;cq(25W1;p3{+-nx zuUU9^@m>`m#*Ra`(Kv|4`y&gbQJmZTr;RL1Vlyb|C)#Zm4`lHaya>iZtuyhNbvwId z%C!r*dq^?nMQby0kckiSA{Yy`v7BG+1sAOh<~2~-+qAX`2Tk}uFM_d9`@BEtvt}m>xV3qw&1&&LAV+8G9c_fKq+fzuNgd$0i$Islsa(Ho;&dG+ltI! zO8cDF`r^PB*Y+Y93$?-cd-llAdylSqDOw>X#(Ze)GaNj_2YV5Wh1w)8+RUt!?J3HuDX=2*zR}ZQ-;l#CiIhEp!vkZhCfIL5!8sQg0l1;{&`1#zMEBxe%hG z-9dwfwxSqwp|y{3@ED#n#zJih7ec+CMT*1xdCFp}n%1WCKsp=-#zL(bJsMWt$ z+9)evKWS|~shUqx;W8Ez>Gzt9!u6|lp0-!rPECwC($XXxB*Dv(vC!>pE`%&1^1!%d zxoQfS6An*WIH4L&3_%tXY4XOp6Q1-a?0!_7RhpfmF2>4ex1Kog#C5y~#zMFC+$aof zEH0UmnA}^8y`#0~aBvQe7-ONfmD9e7n0(R(<_JtBUR%_Jt|t-VxmE!Dd=+C_N@2n9;Y$-V(bMi zy^Mp)ICY6J7P<}L&Tn1ua+}&Mh6Z9Rl-5?_pc0;6#zJil7w&i6*+tPm_`?*iE?S#F zs3s89gMqP_s2{!83fOPjX8@@hKo0XF7>kKUs+%Hd(SWVxg_rWj%VQ5| zX%7$Y;VF3$jD_7V!7%v7*}7ML;KPR@rV5xneTxV1`vmZ*hazKP_jCLS=DDn~ZQ@&R zr`uD+SQYK_2@gDhhs0Ruvj<0Sk&!*?E+p;ppC-nRz>!MEK{6aE#zN_RZlp#mQEIB0 zt7f5q{iEIH1J!&mf_iq*787X!b97YQBmd!7y|-D2F@IY676)&kTgF1S&pEd>&SO-= zO#jUiW6`v>0S686Vqq-QmUG%(b{&hm6^-YMu}oSUjDukKW?(GTUg9o7mzkB52CkZK zDaNkR+IKj32V-C?)E04mjkn*t^`LFWLIvy`^ZXR5h6}0tAe^?CXsCE0I<&xcwK>+f z`hQ~VJnc3E2N}>UW1-s&&h5jFJi&+7$VCcRE2U+xmmHBojz|v^^(Q7EpBi(@j#Lw$ z7m2YF+NT!|yx?<|vCwB7cUb%So|GRJa(}TH3!$}daPS5W7h|C|o9ll=oPF0XS9vQj zmQQN~a1a1vWh~SNaeiH9yCsi$VZTg_U8c1~I4FW|JjOz8KIeDo{KfnsHEqijFi(28 z9Qmq_e9A9lG0`w(D|BeTeO?u_6eum=e%f^Rk!zAF?N>L#^N9rUI~na+B=-~(eeJH0v9(^+QaY~kHkSF z41uvwdXJMXI^%+EXth``k8Ow2avomJ>xC?ou4L}UuivkpCPRYPi?IN@`w|?KK%b0- z!a~kx@BZz&i!qapVyubQ*6=_LoGUUGYTLQF;^0k(;w&fJptKihZ7vRS;n`&@)IQ|= zE*{_OP)tfBrFEsX`8ddj!^K#rP35$GrghEl&UwB`j9sF&c{s>}ei;k3iJW#fKQl{# z&)Y1hb!BX`yOiMOBi^Xqd;TS;rLHSSPJb;;Sa{ zsi!z&F_8{A9bM($?C-29nYqqZ0du2oh%TXOmynV&788xputd_W%f2OjB+l51F&lV= zmGVF-41lpP0DpWt^BBM5f2?wIWiI8^g?3s;s@9Riy$Hr)B14tA$mz7QXBtJ_3wA4D z&a~8vpymfnvTSQx--ZnQMXIPI5FR+Ki9 z)_%mnM|gG_3$?YJRy+OiVE3hodlWDSI)pSqpELnA1dN3t%)iXOpHen^PP=|^#eM~> zg?3vgP%RV;^&%Jxr6%aWQZp)VH(Brwim?n@8qWjqa5BSK7(o{|naTd0ZuNQ2pd(`J z6dc(HICubqWh|7&aKZZByZB#2#xhEpO1q8Xfhg#fu~7Sqb9?sw=mrHV$D;~Z8?AjW zRDCZr@FEzCiHv$rLeVyO?NG|7tUV#d?$Xj)9Mr-P7z^FL=R(M_`g6jks`iu^dq8Wy z;NT0qY8eZ)FFEa=u90WgA7$-62Nqc>PgBLIY#zJX2 z7wtj6Q8q^-t10bkT6+x#*PxcMP}{^s;J7DsQ)Q;WRg8tx+AJj*F__U22+@=^@6BL1h#UqF?}wg~~|IY3-3<`DtU0 zdy27JbO1FtsDV#9#zJi+r|p&Iv+Z@S97=nR);__(6X=(*Q2U6}PTst!(*DqIN_!B7 z@Dm3=;m|S`N;jdQ_1=FsO=sPHZw0J}_L=}x69Dz>U@V-gS)hw{L&9lm!f*6Nc`TWh z{=xA-xSAKiSm<>r^UiBow5CCG>VLjs>?1AAjle4~|qD4%*;IF&0YKqmfekuRS68RI?&og93(<5W1;pIrwwR!KewqdgVM&++D|z61htHX z+Bck5+oo&cGIw5(Jhq#TmWQ{&H9#9}p>zdv1{4p~HVzD(6r_N8(a+d0fohn5^2u0C zG^)=GG+0xo@Mq7}a0n7(b#(XHJdh1f7Gt4L7w%-q?bl3DU4-2bV|!rttvG0fgT+`V zU5f_mG_hYM*ff zu*2+iO@|wPR{=XqAJ{cfpKBs&{>@lSG+1sHTHLIWA0aX?3Xc$DTVb#zJWv9Ui?PtF zAG%>@2dwLQI4vPcjQP<4WZ@tS2EbS-jpG8C>ucYVv!pp%jO~YB+i}nirHqBr4QL1) zv%dse=_Wsr$KKOk!*Dzdr{1=Vh0Yv()aR%KaAW_N0ih zY+8E*2RGmxg0WER%lWl@kNc~9J(DWNoM>$f4r1UqFcxa>a`9q?zYkyiWSu6)5@>Bb z4(egNjD^}VPFtOY6I+~|A1Pqnw6=;+ts*EbW8oxXCb}2y%v`bTT-mL31xA^hXX%2IbkexdxHyML*S72%W%08G1f?Ht9hUrUX6@}+BWWL zJbtBk*r3R@rD80P)?UTIRTwT~q4qlGw_0OU+lzB2C~Xw2{fvXpFb2j#Z7FwX3unye z(YO>xX#;6(6%MMPU&cahF{iC4@^N{&{wbw>OKXF05CpZ1h1zB=hM?it@zH}y%fwh1 ztu4nvIlOxq3$?kN-;!%P-ir_UmW#0y@M=iGK?-!sSSXF=q-zYKYixaWUx~3NwA)x7 zh=p@n#zO61Zch7CPSNYJL1%>+YoN6sdEg@)UdBT06>fNKt&$UVJ~VzU#*%1lHxG34 z`g#$Jg<3c618lrt%A>RSPu?kD7w9{!lThu1-=P_ciS!g#qpRUQsrax$KJmR6OQGFH z@<1dEm$A_8PcB^Nbn_MA3hS%H*bQ3y8V9f8{li$O&EkgPwdy}aZMycGlAfne+F6n6S@`m0EG8P=cM+0ye417<+w)eV0_I3dBSn28MbsjX zvGAcg8@;DJUi+>dFu$}(jO~S2?hhRNfJ4Aocv$PulQg4nz~Itp7ru)zTc~W|ffo3I zpRrKsO0dft{Mf`9Yn-k$D`4JK_v}ouUZhYDzrX6rk4ItNG1g2PKkmX01k>pAfLk39C2mL~A< z1UN}zEc9v3_{<)zW4LP9fF3bcPYXZrzz2A%1Kp zPtJ>Q;gK#pb@p6f3vc{#>KH7-VP7A4>K}PJh(UX+uuTQMuZkG7lL{Gj_mrhdGt(wH z-EASDw^o62t6(5%gLYJ5n`nAF6)|W76*BCmDN7x{zCY-P$qfPYc9BrKNKiYz%ztPj z6}DkFPgw?Sn?k0E-ZDjP&?YHlTIn59#Gp-4$gmrsEQPi}A>&JLf1);M!xJ*>CMQdw z?M=wATbe9`b~7R4P48qPZ)oolGLPwfOT_s8^1j;oz)umU#^4!W`x$>GVkn@5uTjD` zLjc;;gihFvOqN1hn2=$&Em>x))3xkHm;NbhQOp8zfg18fIZq)}QiuUkKp~-0CR`V6arT$v`DpMo|b<3T1$= zK;^3p&SKzq{A3A+!? zYTw)qFnC;1s}Aql9|Gkcl4k(gn}%)9(fiWKy@`eS!RnT}-jLZ%?&h9OXoni&KJ@N1 zYO!I(RZv_R+xIlpix)vn#SFO*sxWrFaAG7n8cLBs=p+yZ+`c7z0uRa~hH=klxCR+i zMGQkL6hKWc3GkT^A%OBxPl)OXWf?%Xo)|6#bP{@<#7HzkRFh6(Tqj{B1^g!TeoGWo zFFge4Aw)<)0rmjc18Kkk00#*`IrReueqc1WK%x!~j7R|ExX(v$cW-1qFyZ$8;0$7D z9T>&UFW|0^wj+Niw)v2$q1l&xhEj+2^6J(C;=HI0Vp470>d=HSnk_C{6=q3C>YIs!H09Ip$&pj+>8qX z;~NB1rGPJjpjYD8khR|FJcq$zJRHC4I$q|Aap$I7`AXf--B>?60y>Qrj;TUcM1OgM@ z3#Ur~Rl;FaGKy;9uxbfFIsGIApM)aRgaYb>piTz(ECin=0M%`m(6CE5mfKTbdW42O5(U+*6A7G15mHcqGYOn!02dOt$N;V+aFqa5U;(6I z06CV+?ts9=0CENbD5t?B2qr}cpqj*y`f;QYmuEw*0ZILM2|zVTCP6YOl2Rm-Ba=xJ zDIlL5o=+O1c^Bn0pPZCWnj?VnQAC0wQiK3XQAdubBgb(&h}0X19PwEOs3%9%%K&FZ z`e#K(++q-}|4hz`rbq!!B7G+rg_FqCNiw2h zzo0H{k$&#~0VcVkDN>3&k$#?x;+3f1E74#s<%fD_i~7}z26Jmr2#l&1nMwh_M4G=u zgSh<+>bs$6*e}r-1faAxI00#-Q{K=7MCD7@6vJ?LaFAg$-&h9ayb%<`=DD#9 z>scw*A)7w}I-93F zl@Vlod8DsoY|!P&6LE=XY#a0pf^FEmGnOfGbzKt>KH69jK70s}Ovs_*pnw+yctOaa zxhw_L5ulEcLlaX9=q5lnAtyD<{4N0B1#(g^Yj+`V7s^S!M(+v1J)xY`3ocs-vW0R| zubz)W@KGoy^_DnGg0rNY)Z;pc1VN-6Iw~rTBoZW%a_B@;Kp_bVNjdZoOj|g&_)*)c z@$mSs^T_LxF+(YLaACrx*|8%-UC5uo(9ggG&2G{BlO9Am;f_^et!ev9ZIr@H0o5iH z=!Al?h@pTmpce*ArGR9hlPses1UiKh;QkRZ=xklc1bF*@5-NWZa<~72Z4Rdu=EY5b zv2GwY^pWy;PNa2CG#mkQgiD5u$9uz~F`}NBfP^WEKgVyGd3y>$_2orS zU!+tJLjmDLuW(sFFd|$q8Yxg>Ash}inUJMW8X;to=^R4TMq!4Jl2z#68IbYkk^YkN z;HW>W`-#y4b9mG-BK;VVF=~TW8?X(VUC2@>u@EwBG9k;PD8JNABRgh6#+^sHOZq_x zhLB;C3fVSW%O?Blt7XoH%w-;VS<+^!trON69yS-o)*?`Dk*qsC+{|2$Pv1Nb4)kVn zv-BD96lr-%&Irm?gwEOgM7Gg*42Z&j zSgJ`f0Le0nLI4V7fUf|2l>r)os8Pm8xPrPoqT>td_uoapsZE zk`XEPu#!u@_-84+d2)ryxxzun2}&}BZHnjwQ^cT;1CU|UNLgxw@~QMKb%R$xZyrKr z4i;NjG^dh6$UIE|=P>}l6aRVsb0DTca`Cx`s3Sfp6 z0hEuMK<*|`K>*c+8E2`_B`IKX3Ydui_*S9^9zD@0A4R~d2v{J1QZQ!%y>cjkITHw= znlypoO~68}!Lf?jEY-e~bp1;$(vQUG&BpsxWa*B73{bUM!$on3*EazD@WuUElycweY|U-E)O zIlr(Co9D|m%F4;|9Fp~O4PmU&ut#X}*Y=xFvQh{%7<$ z7=bIP>`HQ9g;B~ce4sP=zNif)%@LX8h-RQi3Cj9~?n~&5UnE62zK~(_dRYo(^g@Qs z;$<0>zYCdsI(HX&8~ZH$l-qMgcy{^3)`@{yDWvWb|G_#&e%n5P>wES z*t}epnz2PK=FQKETOi}cBi$rJe5Yy0)i|qbTi`1yl>n&(iM&xj5dn&1fCd6I$N-K2 zI0ES=Z356HkOs~R!Fi!H5G@4JGC-aXz(l0244g@ zeBB)Wc*IaZF5e)RKN$h_5nUsvUVTnWUHIBAd~O~`NrU+ML40mHIpP;_qw2lxb{J!w zP`OTW>!7@67|BCA=NY+INqP4ne^Kyu$gCn)aSu%Wt#cMzrkd=8zMM&AXOep`qr7O? zg3X0youNkvWZ2ASmZ^%k?`-}!co$^WkZZVJPENUSDtUvpEyOSK$cvJz3QgxB!=^^F zzJB)zGgbc`v4vxIPoR5GFbW+D1w;vSqa*-IpoUJ^tZ7z@K6gNdO_FAr+ar%?PxJd} z3lBUT$cF>&z|n_(xM#&?OS5e#X(Az?NNA#$3I#kTwV8@9^Fa8805`CAmp{28e(BR*j{- z`4Vcrl0DE-PHS^xUH2V;ZGw1YkfaStlZOnO8qaq0E6x1b%~ZibxZF!2bW(_sC;|#7 zBy5{Ixio!K$-ZEVYBa93SBdhVRP+S=78z<&HLwGKMI+1Jo20*uD9IaYK7^W&Wb8hGj(oe`gHFIUhNPh)>c8ux+Is4rsG)H`9_c6Xg_8MUi&{F7 zAGPW4w{B0Jpg2C=vn~O24(+4hRyhADU|CEnV)o`KWcNdq+-(vuL<5m zsR)>jWyDYbvj;2%FnhpK0J8@y1u(m_QUJ5}Dg`iGtx^E9)hY!r8>vzNvymzVFuS5s z0JAG91u%P_QUJ5(DFrb5l~Mq+UnvDJ8;4Q=vvDW|FdK(b0JCu@1u(mSQUJ3HCRb0JDW91uz>_QUJ5tBn2>gI8p$!A%g%k*MXNZTY$n+wi%PR46N0=2ydnuo_dYs zv4N^m;Hr$RL}A-d(iZ;k7XB18x!Hg3)t$|WikIMnGF>n0-00fDMN(sSyH|8afAC+h@a@#Afsnb%Bdt3+qjU*E|L?hEElz`LYNu`_d}Sq zE}HRE0JGLbGkywS*1BlMPXWwY7tQ!7fLZIJX)^^dYh5&LrT}KGi>A#Kz^rxAw3z~! zwJw?hQ2?{nMbl;qVAi^5+Drk=S{F^5DS%n)qG|Ih^+)q|_i+!0Cuw4HRL=`=dVXJspM(6dfXVLYGZb9Y(kGvo`RcHzh8Mc~-ZId}_!nR7& zN%!Ch`7BiaELqsDm|HyHyT`G6u#GE^bd`9E{irbULs>N4<`Yl-ljM1Erhey<*0i@WCD3) zpyUA2Ee#pAh=^^29%7JTYlc_`l?y@U7hNmF5*R8Ef(%;{#8Rjj2r_H|5X+#_AIPxv zJ}iSOeIUbD_pl7A>w%0vUDLx7*bn)v8%vMw%!8v7OezOU9(bs}2ex5rde}w-%c>SW zGq8OQ+kD`ue~_GH^lXA{*xDYp&1l?VZbq@^3)m)7s2nL-NT7lr*oH0gVcVec9>}mI zJuKs2VDrTwc16hm%3C4<5@q&1o)h4?3{XRW8X4d(0shJW{|N9;1_%HkKxW?~5r9M) zpa6gZ8K41x1{uJK51jbiMhF#YARh$E0FU_Kkqpqz2kkPzEdjVC*-W8)JQje*GC;8a z6w3fj0?;G_xCw!qP&$q~LU2b0$P|K18K71OYGnWi5;&03J_1P)C<8ns!9y9KfCL3H zz!wsHkpaGv;HwPaDgv$|>0Yjjz;ziQS_Gmc0IKPN7YJL&#aFO<(z)-yw zWY`)lmO|B8kYOvbSO(Q%L8hFp!$RKXJNK zu;p89cc^d+GOy{PEtbGs=g&6tGU{Cm-^kssBY9+>VD7iBlPAeRQ42dFYq0Ah+m5w9BC#(s2m}g)1Zqci}lw2p{p=kRgzyr0gXVfQIe9gprd$@ z_4aig(1|5!$z{u+YA}ei6=1A$yD`-Ne@Uq5CuG)=Yq_-^stJQQTL;FrKowx{3TLan zScVGcn#kmuXa<@bPjrmcb6L~!3r1eb*DaOVIV$5Dlu34uP`McN%9e;pyvC6xapZKg z1VD=x7#dq7hC*ZO!-N#W)`Ur%_yJQtFaynbsE884vU09RW-1+F-+kDm2Z+|z$y?La!#5JmQgA7~W#vU|P z*=D;D{(kVl=7ZEffq>y&gpyY7iIbMS<_P@=U#ed067@ORo47z=7YWpe`j-Zze)pC7 T-AC$oZ>is@=G=dmB)|U;Oq2N- literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cmpss.h.44349D1312E625EE.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cmpss.h.44349D1312E625EE.idx new file mode 100644 index 0000000000000000000000000000000000000000..b1599cee41172bffffe38b1e3698439b80ec0072 GIT binary patch literal 12618 zcmY*e2|N_Nar)kotAaBcAbCxux%-0n>cD-8{ zoJudzX`ZBH@ocBf6rVXyT+bU_PPni-a!N&n%jB7sZfia@IiGsaWM!dsWo1Rd!L@vhOW9A{?V}v+#-&N=jY`Q?d@>_)>QF5<_GZER zp&?V><9=7%*ZMp%GsxVV+nBp~Zo00$DXWTUC7oar-4k=k{>61K{-v2)TFmq;USuZ6 z*lAmPso3NrKeWQ5WxpC4qx8Q~i)Hg{L6B1RW6KD&s2Ybrio_1+;!v`tfL%tpZ z&eu>E>)Og(=XK|Hn=Z-h>c778Vtve_Rg4c-^_JIy!q-O0-m0Ey-7;t89xrfR+C3og zsg9w|%H_{iXYRfFDDS4=y@^fB+;5|jKa4Y;d&@FRX43MIa{6eqE|YOCv&w!-g+4v? z@{5(g@%OjPW6J(DNSEdNCmDq*%MCP@Rf}$+zS8dZdGy?}Jzg=Ih-U4UzS8`%CK=Vx zh{Q1}vM1urBHHzWkBkm5(vP?@x6F3tjQQ_fgN$y{ml_7tym*CFWumCu!V0f76>Ha3 zEOP1G>X=iuC%SN{TyR-?X14CsWt-TQN-kchY&XB!8(~ZD%A7>4=U1&>t8qux^i)#P zqGJAe*I!2-c`PoM_PpwoT;Jk?oUq`TEdC*<$+@NJeD%SoRVABWrsu!wX`Ow`L{&9f ztKyf{>8Yv#zN?qqz&@6H9<;w^DjT_q6BG7y-5l*T+p;tECP!FCC+egs*Zci2nmVY$ zE~6K0I)1=MSv~cfV6#lpbH$#pC>5U-{TA}?^%Rr~ZSSjE`7#4-K40I?(r66_cJX#4 zw@O&EPi0h1Vt-`&myUVUt9l6>mKV&w(Teh38L$mE1hzHrIDUS|`+4QBQvR;opz4MS zlK3u7TJz_fduz&XY%knUXqTwxqug7z$Zb~jfU;HdqHd=)#G%wex3Jsb6K%VtxkucU zZ>K6{6F0~DalPdhH$FM1og|368Zy`C^G@aN|K5Zwx$jkPqF(2tUzF#cxU%y51;Zyt z4;=R1s2j2-DtyB{SGLZ*XxH>P83`-PEtF4hjhwjdjqwcQu&QHbMnh@Lys8JD_oOW9 z-G2Nq(#^`QZE-nb@7Ah(9y#)G(V&NSXiiL(ra|~Q`MX!{?ON*1Q-7y2H}zPhsZ3;? z4!fdWz4brmrH|*?m*-B2`D5m|Z6j^o-5r{FOO~jYO`Ty?XW4lE)v9&DcW;(dU5I17 zo!07}p%<2BdhyM+r`#z?yh@YLIW5}CW*?i+JzDYD!{yNTy*b|dx;1#&azP)oe9fB& zHoUhy&l|I9YPJjgoa=GZr0g$yCiDuX{8stCz*XJH=Za0G=k`AZ_8OP0Q`lCMG>i0> z>s+(cu4{aYhE!%w*B^C2H!IcIv$F9{i2NvL`|kMzH%8?sWlS+hdsehpYK2>rmSeQR zxZK{;jUB45i_XU*UXiO;ES=SAwR-d8)CI!Qp2ss^YNE)(7U5~-GZxV<#y>W^FY=g} z{AS@@uWL@b+^QTlDtQ&Hz#N|4Uc#Vj&G~1pyVC7Z#B7~HgHdO@$IPF3$4q;B^r|{x z^V9kldIbgw^Tt;Fwws_or#h09}hYYwdrq zM-~}py*t6wTz}J{`HqQq_%mosXO~lpt4-Vkd!H;+y0PVed#@q(UHZ6|eu<#8YEji~ zByLXDmlw&$g-dRhx1W-5Td+6Br z;p;d`+-JT*`L?b$W&f*B+^_yQH@ATGWXN~2jlwj;xvVRLsvRpj{985Va(`px!wDK) z&D#na*|cZ#_~qt5uh)HT>^8e#dOZ8}F_+hWJeS?i*p~Lo{nz0Q+jeG!I^-Qp+b~#p z$YZKm!THd_ISzk3w418l?s{wNvN5i3PO;`U=a#Em+jcwZx(`f0F*~U8i_GA%z{;ap zzcE?)jQ4Z=E|=y9$MOeTM#avErd3%iZT!-? zTYvIR_geqt&emxGuN$;dPo0eR7lB;Ze{ESVSvJ_%Nu@V_S{~2?6AD)!BYpB zeA{0)Tb$nQ(`{^1N!_r%aqGMOfP=IX>T+%YOUo>=!}2<9vrLqBY~7dX9r5&Xu&(i$ z?@2Ens(yWKz^Oa0^!EIii{Vcreaa3O*;{mMo&0ch>BXWA>akab4`(&)H_dcb%c_0d zV=1?7Q-TV8PTZ2F?$CJO?xvKBi+p?Z{TCZxPUr70Hl6wQOhJXK!P<9%Z|{a>y>_CbaypK>xDOudD@#l5evrAX+wzqW8FltzDyV3m1p|JMo&jZhAJXG)T zJ-6gu;risy@@Bg)EX&`Tcdqf~X8&!rYYp#*Mx1qiedT>Dw&dUIn&{ldHO$ewd{z6( zhlXZkzcCCfQae>VCGdm0LpaOjmdvt-EtwV?mws+6N;Ho+q08QN%jVCXlBa3UdwDya znRYJdOxIkdKimK4itwY>-(ER3ulba_|Hs6B?bx*Uskc;bThKRJL>-E@9XPyf+qF{R z!}T9OT~5~uUR8-c3Y?#6_#kOH>)V=&2gAvoCG^3E&ErG0OsyQ3e43NjQs?}$;f7A# z-1q-pCTJMDxqkT=o)Oen|8AmZh?=#G%I-xq4z&mLH^oR#{B4-BYKffv@7HNzOn)c4 zyZaL=Pxz_|Fok_OHz#~=Z_gOa+@rmsZ*PPxawYTeT-#aaoNsD+tTvJwwfMlE+?cJ3 zkLX`d{g{5uC;Q2Ym-6M48J(eV%c@$OOHGW>%m0canoL&XLahN$Q=zsOZ+@__mVtsvE zj#S$Uskl%2*tJ8yx%R$jd}T+w!-?l*l`AJ0hkoAsqEC%G+?CyAH9V(sUg8YT-jvU> zH|qCp-}0#@Z?ePdTP7M^)KqwU zr&?M+8ClSCr0(zX!Vu@e^?Czw1Ha3s`MUqW*y~8(>Z-pr8q?G+d{N7ncmHwlP3l2^^Y<@~WS{3AHGi=sXs@N4 zlH>CGoefr;^AWuP)2ni>F3^g|^72?2)YljIrjPDgl*2}Q8GBee9`a-Q{q=|U>Bp|P zb1y7CsCmnutlW+*1CIy(u5g}nqPpL)r+R<*CZ9un-&M0)REJ*v*X^0VNV+W6p=HgL z`i>1P#=L?1wJ!e-mal2Jn3gtmGP3`cea3%pzTXOVvFxfTiduUZglM6lZ_cS-Mh~|Z|_l@V}{hUIv$CqP&GyIms}xTYVsd%r2H@ckuUvaoBzg~%qBathaOU*DbL zjs8o&blx<4RsBBZ`@`j*_Q__33N4OimmQ6G{Pp(L!$0p$d)2~=uwgvgy|&;~s?Y2G zy9-|;1?s6MGb>XyoZOR5e%?MaYv}Kpz6`r?lWRY=TMDb6q-pHQzFaTYpDV21QE=hy zu9`gwmw$~pqL}sNP(w%W_Q&Fvch z)Z`8|wR`@adVJHgL+-6|>C#eC;h#L4+g646PnwM$3JMBh>--*;o~cy(V05~)^e10- z>z$wDG}KQWn)6`ri<{HE6L-8x7M)!|3;z7Q28#8iCN6!{DDdfjY?ZqlZ0JAQrlG!HI{$CVnBz9dmIC>0 zC-QR4+hiEDoPT!KzcN;Mbq@Px?sG#tz1WR?>vb^HXa+7qyuh0h$d2L#7O`6;`YBk1#>ZE4m7Gkks5TYxDgqt zju`EdUh|)Z@g6G-nG22n(2zegzPJ$?sf`#t-+aqte~|M!3|S0~PBM{`OnGr5G8#K# zl)3J-d)6~l^uyETHMd}hDKzS(BfWGLaU+^-N22I*;zl%%@`#b?psCeM zeL*aSm_wsH6v;!!i5roT;)u~|Z+j3{?HP|D7SJf4jpVbH#Er;EW8{v;zHuAgn0M|! z3|S71uCtNr&Oo5sjoiGSc1AN*X@=-U1An z4UJ+^Bo=A_Z$w5aBO_g1Z}IP=Q)D5AOeH3ulY?|}R1pq`t}tTqK)PhOvGiC8hRlcK zv@(%a_;T?^G|m`&A}2fyf466_4nrnDqkl}~A5&G_h>WC1MyfArIhS9i_7y{{pivVI zX`;!B8<7#RVik-5AyM*8dxx8$(GqA>0gwuyAZ|nxU^Ft4rbk-oM3vFsFvJoXB{Pv^ zrkuDDjifbVv`STF_a(v2P7HzDd%|RZBm-%2Bhu3N5hKK7o3m$?06`QE$4+#}8%v{M z!Yn2~i#c9AABe@yi67wR0*%HM?m~BsAx;xf51z(D9zkf)1^54&r?Vh&kA~i(sSrf= zV1~l5f(i!`j;Ny&aeABZm)H4}jiS@VG_;teNDwnF3NVvyKMtKMT#2rf41)=eF$|6| zpkw35VrIuP_f!2`*#8j?eMI(`^_VwWMQ$t)K2bYOzMVFj=t0C{*aHv51ab1$vOVpo zYBG>0rJLa{xmLyWcaG}~uA1jF@FzhSGGc+X`0Y01r#Oo2qAFfu8YGBqSY3;K>iD^p$KR?tn< z{xP+@2@ir3sT#u?OUx_=gS%orOG6U(VGvWSW@$*`8_YC{9V`t=5`uw1F_5hxi4ib* zC|_r5N&*WEIm-ELO-VF@Nl5hrd#ofs!I&)XhYBR&8pe!qv8bUWoWQuIorfApLLN*R zS~aMFB%8oIGp-9Yl%ybGGDj(yGg=aAVMbG|=V(Y$ov@Rm*2&S5L?W1jWh1#NL~t00Q?{X1W)7j1VIpYO5+gagP0*C z347p`1JQ$cSCGJ~1%h}P6tv-Tg2@zFAPl5~KsuLDJrKszK|GyHs2&I_>7bI%B`yJk z|LEW!olB@52-6rKjlm^u8VDO0pn<_9R1buA0k{jegvx>N921;latRefo(b+UxrB;= zFqj2`SzJP;KzNe{ZnC(9N`deT8+>7N2^9fhC<;PRE}`;N*)dB{9Qx*OO&fpPvThae>LdK*n>z zk>F6`vPs;7xE3VviixOa<}gApLzht^bT!?e znl6dZnr;pr?cA{0uzwCv$^kGP;YZ%6U(=ixCe8+!u#qO!NaGU(2Ax8`lVeQ9=A9f^ zr{M=CjN(p@;=+mqKZt3Aw~p6w1VQKr5_s)K5b{%f)>`kfv4;25!BpvB>Jdckv)%8f zTbM7C#l#XM2uv(N65|piF)l$8;}Rq>E zEL99yV~segXb3FqR-f)t^MYy4$@1&T%0PEhH0gohj#r zLsH;M*y9^b{u`Nq)0+a)JT9JCH5L;F(?KwuOALhxZ_vRFDz2h~Dk`p~bE@f*n1l)a z7{HG~>3@vDImV#y=?sug<%(#rwdbjQ5)bepC4~Y~C3*g->IHG&W`YVm7as%D1sW8$S0A&5IwHFboA@ zD5ZZA3X-V!F$x}2aRUk(sCWPc10>#jaLC^GiNYEvtza4&OxBV=G@_Uwf@cS%^_#{2 zO_o=;TTb+ujhkjS2S)4>X%P_sh^0kj5Dexd{Sx{lGK1h!BQY*D0%NeQ((9$0kQoM- z9*J@35g3LGhE6OJEGvdD<1gh^X^`5SKE6VG#|+wF5(<9sw{4h@?$oT-sy? z#idPTP)zuYDfNu0NYsHqh)bQon6QN@)xuOH>OuhHvPk+Q#-&eYU|jk{1{T$ccNYsr$h`R=XVIE*Pi4t z0wUKTFb3;Po$KrgM4bsMkP%lRFec1nOXaZ@iMkWs--v4w7=wvj?*rR}$n-#nyBZaX zT#djmrm_vbu_u$*57qKR4akZEcSRE8u1HoOxGRzs2=0nRDg{E^6^W_<>WMQxnPW`W zu_+v-6lz_Y!ZA+an38-wN4uV5L=-5P@GVF2Ew%1_%Q1S(nM(4JT+K+XE>TTlu$Y`0 z$(=>wD6VW2Sr>~+fN@b=LxPw7JM?D$4a6Qsgikd2Ph_%Dx&7zNx_w-Gt|-~?gXxkL ztSH&=Z%}a+onJ-8)pVt5x?~|NN;Z5y2BrTohSD(xg->Vj)2VzqV@f&$Zod%0v5~=V zr1Fi7DUBpQI?uoU%8#?6C-_X0|4crC(^!q1rf|J=kf>&=RFky|;cGBF;+syyrA|6r zUjOG`(|Xt=0H_22U4j_D1DVj=H`f97cuYedlewCZ2_*2XDWb<;sq5v-Dkg7+#9{O> z+$g{gBFw?l_%0PebO&WD(g-Ww3W)+5T0mYQ>AP#xomJ6Ju&@fDgAh7O^uUCPbdX5J zHFQuz#r_Q7&!E`fWq`X>{D}cRQE?ssd4OVni3u(-DL97-a;W$e3!Gw6_+%DHrsD5x z@SRQJPov;8O2Nq}NT%Xq6ckf&BMKU+cnAeUB+h9*zW!$Ab7weXku)@tCJ|VGx0B!L z+m<`vTMS|8g|H+_T2!p)Gl-__ggqY8(1+w4yE#bJzIZBdgFWg1zmBZYh$stt;QNKd zWUY~Kgn8{oPt9I($GMfM21APfy*E9#-;cgCA+u0;m=-k77lfrp?jNL9dA9O^v-Md z{&R4s8#MF=IaC6D_Xe!`=LJYa(9j5yASwn(;M0jv%l*%`mYp9DSH!s2ko64iHN@Qk zA?`Iqy#j=|*AR{hSF|HuL)05Uh>B zQP^$e$(B>RZ^5a2Mnj*Gn|MSfhJ<)SSv<+TA4B$U57oT`iFg_sPm`4M>zY#M@~=3F zh%_3SM!sMo=|ckFeI{Pl^srltj*ThEf_Ie*lyb?XZukq+Uo#@>a$%2)H1r~=F5>wi zA>N!8k40<)S zg^zoIX>fsb*vKu{rVlv2EQKrkEWpnK5)Z(H*+45B5WDRN2Fo0N8=Jznv8T1M;RZQ= z=#NF7^$#eN!3&qr&=T@tJ>mudG(6K)gJ!7=L6@hTl$ zrQ$L=D5K&5IvAkhBnC*LE)DA$pq`5T0Pv$O?a~2Ar{XFAs;IacfNCo40-%eEy8-B? z;&3Jir!EcCnIN5tUogQ7D*nm@U#Zxi1^lT?y*L(#qvApqD5T;#7O11*9v0}K;!rjS zr7ryv*&vaMlh`1MiVNAGkcykxpqYvTP!K>a_27033IeG(0R;(ET!4ZCDt?QCw^ZDR zf<6-GDzF=8p1o29rP;*LZ6Y_V5R3Ou)vZ-tLn4jMPh(5=F{1u*xHIMaMMN7-zKx71 zGylf_n_i(<1EuzqhCU@D3K9Dtfq(KLRGZ^4k#l&lM?D-WiKUlBX6}w(ti^|ReR~Iq zcD8;y8-6duj|)%tF4Atj_5l)KY4Tsmi!XmO`b^z6nMQbx9q0~K!anrN^=_X4L(%E; zH1s@KG!&M72(o*3vk4CLfu-_+CE4pJ3Qhi+8Gh#rByzx%900!_;|KAjL7hu{j1m(f z7vdeG3y74139r(5SE-*K%ILf@x`0SIm~ep38=wn_lmj20!AoKYh?Ii~>lwUyhJZ*p zu%HG!KOi8Ntm%N44g^FBf=f2Qs{#UY3EBmCT|huAIWb{4lNZhu5Ge{1rZaiz)K3pD zn7kKE0a5(Gsb%uMG6h8V!-W1Uo!M`ICZ=A^Ckifqk z5(F{xB4XrwAwdkc8haNw?iqwc5e+RO!?4w}!>d5#l|hki*#=+PmPC)BjQh45xBeVr ziHcW#2#XTolUV$u|HCLhiL8-CUn%&Hski~*+_9T1Vdb_puwrh}e5)xTY{feh literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cpu.h.F8701109AD01AD40.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/cpu.h.F8701109AD01AD40.idx new file mode 100644 index 0000000000000000000000000000000000000000..43741525740b624c5206d9463b9848265aeea417 GIT binary patch literal 824 zcmWIYbaOLcW?*nm@vO*AElFfyU|wzWABu zl8?552XrzuX0oZN2luH?JKwVA3ERi*Pg)JW(tx%f@;G&yhg#?Z?$qH}jVd!#M5 zb+_QPByp!dGi3dB?)=(#O66Bq1~0>QP1d5=g%$=POzB&$6_~%iuD94!d-YfT=JO_r zd|%l1?%cKG&To6c>26zp?_Zs~czV^gfFvHC_QhA;9LhcYsCu2L_tkA)tCv6Lz3|}B z3qii!9UEtrrFPFy`nk&Kt$aY#>_YFD{ei*piA9~-48@hXN$EiUpKouEnYF~wgognX zG9bV)pOI%iqX+{hBO?+HK1^DwYNR4{NXVB}fAC}2dz7&w7E9yUg1R)(U~wBmYTScg{rSzEVPmz#-&!;alf2&R#R!@jwlQyOxm?=1Qo{9tTO2tpSA&Kpj3DK5+G`u5Hwgo7w3C z6mDe%B0iWw*H7f#v2?Ze1xjRcWWt44yvdxoIcRnYP`HGn1a8b_(dpKjo@Z--!igM- zaN*=?M&s9ZZ4E%-D2^z&@T+CD%Xfb}*#{J^~;#rZKT9U{DWD5gvaY<2T1dxsa;)*%R9;eTEZoPEUEp0&=}d$0XnYp>n1C7zxf0}OLt zza%OwWP1?AFiZ#iMQrD9da8_Jm#1J@)QR^i!?w2AYrO~^Q~zyR(ay!cK3upqZEIFW zq1&_Df;Ntly8cyR6O`Uj9+$RJP)Z@Mho^;zNMA{<_2F#B-%!+(x!4Xogsnd~(8^9fC! z7TD9^TWp&7T>V4#u(hSuNf(uLZ}$BW>-vfU>tC7#kDtf3th|@rxcc@V zb0Hp5QsaWzXAbVam{+3l%ZFV$XAI|Ib*bl+Q_agSeH&GCw>?(;hSjOI&Lg}j*|MHr zp}QnxB=LUk@GiHA?5u&@)sM3pl!OP51lpu@pRl;rkhu6x{yK|;b_Y{@2FA`tL|HFM zsCS>z?fAw#QDAqp!b|tl=FEtC-%Xs@-L~hFybW{;w?aD~9hTm3LW_Nc&lJP%-_sx0 zjXWGl4(is{?bvs(Z%8lMB+KVk?w>(fd!tguZ$D9OmuYFe;q=0_C-?Up*>kG-$OO%H zZ{^C!?v_psd{|>-6X9!`_$cId|4(hc*K*%K2bMeHJkWmv?LV=wwgda{N!- z#-|gLt7bMgm2VW!+3}C7wzc7!N%g1QKIHVqxEyNJKi{miV|wtgullD;5C8HK8*-2T zaj{x8&)}Ak%}@Q@w!g%Ww$-s+ zDabwI((oisY5KoEk2{i-`irxjZcF1o-0$t>cHSEgT7i-a{N~D8O=d%>&2es}4jP3k zm-*Xr`m>*;ouAVhT)bk#w%F+&ZynqBx%~9%@R6%;V-B}?@ei$=!yOZEe!ruwLhQFA zBSf#q<1f!Ofn^hR6$}LSIl10FQ5U^DB2ai)G;8t7S4|66ovHrwX5>}x>F3t%^XwV9 z@PqyA$Auqfgpu7>93JTk8Vup4-I@mueRz<_E;l2pa|N9f9+mfVzsC3!{yp&+H+D!E zve$OHt=ZKjBbvJoK6-IVC0t1>%X7-gX?hiY^DD|(E}1Ol@cNY(qUuJyo6;(-_`OP= zH&4^9xv!#oht&n&FBf9w_5OTsXt6SOa^0;nHtyN))lZ*wx@J-|+v09vXrbC^XSF@zwK~CFf_pi}oEB@ME8Q%zfN3XJk^{2i>K9p=1mHz`@w3oHsRU zS93YPbd_DiL!NEaxh?qBd5iX!{bSvyI*+@DcBQ7p{CBASUps<_9QvNEzcpMoMTPse z(XPnqYTb9M)Qzn9JHEeOQ<~j+I`Uh@=85gs>;sB#-<;?@&{6wtOQ;g)f??@~{(8x* z@=ulGw=<3J{F^Wtv>F+h-(YJnac;g-ia2+8@~kHR0QbF`r~Rtn^G;^`I{D;xR;@M%lC!xcO8ocX4U8-pUKbYr2-2j+M5(J>t1~Oj&9Cz%KE?SYShn<0_j4 z&Kriia(_?#UiQLn&!XhL_g7SmZ=HR6&6>gSzjr6qszmhUChk^w|I@ZvnYJ2dK5Y4X zyyCU(;;5QOC2a%u*QI|=2@CiT{(SIbbQ}KLZ$ii8BRNZ>UB0!XMCd0t_dW}M8uMl3 z{>z&t2lN((mPKB&Nzv@g^f}msk5<$?J$cD&fB)5pQ@e0TQ!E=bfbSL=Y1}Hl{|xNsC=@p3;f+ zlU2reeKsU!jid)~>;OJa-eGELI5y82DgAd*%KqiIy?sb*8dAz2una<5-bs|$QcD9% z*G4=kKkP?hHb|)h$2yQDS%;~qg9%b4v+J$wq^4Q^EX*7!ZNxX~N*|aSh8bZP8tR^n zW6$NOsw+usHd2TOSUlj!J4{Ved7{*cU_rClIF5KViCH40MgnU@^O1Fu`EWd)kfrQ` zu=_tgmFy-lTcmWIz^)@DS%;}cmCbzOgZnyb7amW7!jr3gGiL;8@+XR>rY&Y1lr zj~xyPBsK#ny9=u4LzM&j|#m}B)gY${R; zg`s-Vhs27p)C%@B=(C>H!a5SOLkguhR*H|8cbFQBFqB#`*b(}N*V?s>BsK>rl>w{_ zO<2}pYFesXsgk~1xVx8;b1R9>L`p)42_Z+`N#>(1CD;E&&*$GrP3<8u3#9Z3V4r}N zypt?lM{23?d*5Wc*i%C!W`&fR0oII$lXViM@lyX_{E!V1w=`+q<7yP&rR2vjZ{ufv zi*B7Chm%NPB7&Awgt$El8I8_bt4)x+N`hTUOq73sN$|`{!jZ@(I)7Z;zo-7LD8kvf$J**55P)=I|2<(DTN1LYJY1VHg|Y_@MQB&# zO@fU?ILgYhM)Jfs6f@;w+(^unrvaD-7~iJ>qcp(yz7Vhq0dqV6MNEAWFctxHgi_=6 z09FrEKaPNL1jBv~0dttRl7N-}9~)N^411k~MkgV;Bukrw3@`~Y>=i+sB8cwPvPQ8H zxmJGQ%LRUGzDz21ZCx(SjwW#gI#6Uyk{zey5a{fXHL5NE>au!3{+dK7&%6|OqUe9Q zJK^J8Q-=U!l6MN%Jca8~0T1OnL}U35$Q+D61JMVo?JifxJMJOU{coWfdYFIvm#Fs?--GZxDxr zOq>Z|CSb@D2$(=H@M!{`X5t3~e89xX5GF%~zNopbO7uav1!YbVV2c1F#frd85nz-W zJ;0y`ppsJ7w!a$L77}m09p$NXV4MyV$0D^UXpQpvR{jN5-J++A^Fn$CR5T&O@{(6>Lcdj`j6cBHj|7&gmI}jAd8jnEibz4@d8v9S z(u0HyMqLED7RZ`!SK5EvT>Uc$b>0fq75da`R6#*b97Kh(#`kpGf(Q8S?O}(Z<484}s*_5DBm}GXZ-szOo4F-j@n-oJFUxoGOZ}BBKiBNXU~>g<>P*$*4j{nT#rQl*y<X1baxSq&_yqbx5pFHQ9cV1Z*`64;iWgoGRu4TLVmL0OL5S1+#0xLTUyiN|)w6bRbZ7CbS~Sg^5z5P7m~2c1@xL zpiKbh%$@oKQ7Ho$WdH^BkJfGIx406}fJzD>4u#ATp#p~$Ox%mZUM3a*C}5TV2LL?4 z#CZVbF>xh;l}ua(U=yYG`7}QKHSxCK(4MErgL$}F9*+JSAZyeKhkP!-ZpsDqcA-J}i?=qR zTBC|EsUqf5Uy$f*vgjmu6sFD$WI=W%r36VsPFXQAk2=wq?{VYzxMJ6+_(fmH?x)lj z)NzUg^2?}Pvi0$khcSt>zo5tsR1IWAZX7g^gVcXx(CsoGn&;CP-C%zWl9-6#2S=<$ vJ>cyucw#cUyTMAuW1-such~utf}|McAs-EOZuC!g`ll=Xb3XlZ0sZrTRNLCK literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dcsm.h.095A7773A0730C87.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dcsm.h.095A7773A0730C87.idx new file mode 100644 index 0000000000000000000000000000000000000000..37ed74f561823bb214566b42954bd8927ec6ef92 GIT binary patch literal 8958 zcmY*d3p`az7oYu**KrQ=mXJt9l9H>}RZ3DqrBaC~gcM4l>w1J-?^K8irIg$r^b+!_ z6c39Z4hZOJe_3l2C7}dNo(Q-=iyl+WwuFZbe-Ee)9>7ox`p137! zwcy((xty6EuBnjqup%^2+^k~Fd<(M$@hcRxnjZXa(G^-8)8kR)EPc&Xf1;eR1(f#fg1w&T`+ZW`D&Iz4R zsryoIX?Jpp)U5u*{4V>_Bcj<0Z7iGAmrM?x`Yd$$-_LVY?@u{QY#}%K_sho!-O5$> zoEsnXp@Cj+rBUu9BbC^C$Heo!rA4OCQ*c$xR(oUUrJg1+9&pc@vL@v>vnCng%H@N* zI&smgeGd)dh@}C`Mn`wj*TNOe zy36|Rnn`5jCBEV;YM+`OsQ@)fRXAly9q`i|DD6AG@z#|?QK z<_kYcu-x{EvX*m^jS2j)q;@9}-(q~Py*>1{M7PP!m@r;i#qh{i>uURo!F9S9cE5eS zNikPvP}#5jAeS!^oamOc$n8P!79!*Riv#C+QgbKh#|=H2Mj!k4((kJuociKf>C<}o zx}T1o_t~!Njs13KyS^=Z#DBZ?-MXi%x|eSdxleuFs+WIrv%jMD^M`*Wmc5wJ@VKx@ z(nZrrY1i8nch6PM^J|^tO~jL`vpYQ{9&J&JtFm&G?0=sy`*Q{91uKn)vZ(FRZ zjfY>Z8kw})z{0;ISJ85b?ia^7M)mKXat(^}J%#Vy{9o*}i6A3b!SS0^>*61w?ky(b z5&KM@YF6LO3zQumxj03rW>)i=sLd&U?RmC)tcu!i7%tMhqLOlfe?U>snICCb!?}8Y zrCrITX)Elw18dz46J8Y?-I}?BUp1rjM3>5`X*!L^)4Jp@{#4o287 zPBR9F3Lg}9gk}`C>J(@Ha+`mEXZZB}w;xY>s?wcGwd1vxR%@ty@7(5;ub^ac^j@8o z#lkDMPTtKcy9u7Oi2kcnrB^QD9a)j8<+r{1u=KBPN73mbi()zUaclB*Vk|YPO!o!V z-?lMK^RKybHE48i_>=+Nd0ydpk~I`C)(lhBjR#%QFqzi<-3D za-#odtmAYpYr|HR@{SFy!h_d_UYGQR{pbr;^_DfxSrr-@t)0VvuPfA5nvn9aCp9Rz zy>~)JYV+3mP|J$!o~VCCJ&Hp;x-Pc9X_DOjL_$tvz(AddcO?UV4-PYybU*n<$l{1a z-^Sl^hR^Kgy@!hv&+Xh zNuJd)+M6{(#AXZY-0HnhsVW%|X?moRw0@AJXI|``bZF{lsqlq;L2309tlsJ!&HBDM zYov!NUtF43pIV(`(UW+vXx8lQfg(fSUM;jV`?%1&+va8N$GVwAA6J@PmZts9J{-E0 z(5n%=$n0hP5I;V=I5AguYxqwP{*&kRGGyk$FU|{h&doa$5i1MrQ1dGRtgu-Dm!y8KJLA2^Vi$TcU{+1RjHJv4@XuyO9n}%9}NrdiS)Fa=sbP) zhId2?=``7)Z%6&k@5$HfzjZ6_`S;#c?v`Mc;sB*LHO_+;so?`*JDQK>$`1V6WaC{? ze)Z7t7Ll(0up@bK%^VY#0oTn-9)@MR81$`vrBvWJcjeD8hbhUe3I97;a%gSDEMNaR zmq_1x!*bTGVODD5R*PI}m$}xiUAI8ETGOTAyp!J3C&IjMhZkOVIpm?Zz9K?gG3vOq z|Lfg<7#2S>H<>%s+4Oz>ZHf4GH;=ic)UOKbxW1_I_l(*J&n}1tnmTmOt}FVKWG6a# z-KNJ&H8f9~cV1m{H+i}H7w2iZ+}!tOw^}~P)#OI>TSxTwUb+-}`*Nt`AG0$b-#*)# zZkunPmvP)<*w$-J-thXoyLwOcEel_*EPQ0^wIMIovQXFVPS4A>)jKQpd~EEmH@bK8 z#fs79I&iTOgXv=82xz6M37l-u~TU69-V_G~7T2E(aKWeR= zyZQ8NgFUW8rDDH*vVGO}TbL22cH)+IS(2uQk4)=SDB2k7cUUK<>#s1dWSvi@Q?tqI z8Ed(+Kg)izQR<+Z^e27a_b|-ovX@R>gVy3*r8Ys?UzWAUo>SH|{^3>LyTu`3yZ8c! zc{d_T^f;a!#ts3y#N~@V-O=0JT3#==tjMRUTP@31*;Ub8yLZ(dj-!O?JG1b({R0&R z!ygLfOt{lxXLzhCPU893I{nxCxut_~(~kSdT(8}KKj_Zep(fFQ2X&kB*BcM+bk*(9 z`^W3Xi~PyIf`xNmJsv*L?A?3nnCh26xyYcGVr`DAM}{BHydH4z`mGkz^{Nkoxz{~2 zUoN1wPCk%dRneDver`*Lx3CUB=zG_ugDbuVeV_GNbN`vaoEL}Mt3S%M*)MtCU%6K( zYcd1gQ=VpH>o`T^!YQv1B(ENCt3))g^2t6#g=vk_9 zQiKQeAn*WvK$d+%P$;3#qC`Eqn|3u@bH#xrM7<`+*MtO?5UC0P^fouBJKQMcupAGV zL)=S(ehI^}65@hTSSfwGP2zSOd2zs$c=5!2g1k>iVhMq2ti%3&{JXt(rB!*r1mYSA zx)C~LCB*q4hZAPaZr$VjRh+!&12z*Y^&tYs< zLg0QBdxQOV#rwO3Ot|0(A<7_kO6-(jpFo5udzm&*Pc75^^XA`pU@CM~P0-Z@2TSN` z2a0K;GF7AAVbNj^uw#2N=(999ODh9WVNzBrd~|hh+O^K=jM`?-1Jj|q0)j3eeuKa#1pNdKl9dp+2MzK>+uohU+L4apU?l{m5M&C$d?>7hKy`M%_Oxj&zB=ct z6A#RSxGI9Kf{|GXaqcMc%lPo%)s&qJ7sQTk1rG@iW-Gua-U>9|t3b&o+m#2VL01t3 z9YHV;_iCZKJ3kF`DR)ra|Wh4jXy%zzPUVCg@~B0ZZsHgg}}8qvv#be~ir@abN|JkpvkD z2gyo^)L`>cY%ctk|Fg=U2j)UtIYF1hZ;6!<=Z*5Rx6LdfVQq^)2dozC>meEp(egl4 zgc1)UqDDvfXy~I@EceI(4%jMyjZk2Ong~S2=t+3T_^nR6o$35NhztH2&9b|MJ2N`? z#98*5VlrUr=^D%dYv91rDUePv17jr+oj@p{oP18tEx2*RDTD`RKwtnJz^p%f!qNYU z56bDrat`i&Mxh*F3sLV#@D83Xtc06c8lNsN$`tf=IA(?OfDS|+qz@{yPw3AXox2q~ zW(fPG?u+IDV+g7s=n9xNRzl!zl(v7<+hdBN4B|MzQIL-m8l=#p`B1_6aIWzmaoq7W zfd}S5fAo@jMk~Uc$e`n8*PM_$ysWO%Jg@}1 zYa{43xbs*E-5o?bFXo8dGxemAEDo@Nz%&x1k(056X^~uccywKB^K;7dYZJ41;CBdY zCFoY@k(JP60P+~n^+@Ae@W6QG>SsAec$C5Qr9H zW+EiS!yD@IekngK_wFk^pbP!&r}s}{pU~HKv>dP3wkqx3P&RkZ)i74Y8Q*yc1rLFc{l{nCZ$X(PuVAPj=aKjaOUelQGM z_l*maPD!RylLdz|lLA_)jMf$$NAW}-t<*-H4Op1f!((yzVC7ngdV+Dh_Nzpec4o(1rD4}>I zlnhodh;?0yKRxpT8irY!a;eEy+x+(E)N)jt5DPQx0asG<1;%lbV znkl9>X4{7ljwe;vtwJ%DSW+pLWVRFA7)2$iQAsk@m_QLisfSQZInOp+Lc^6nbu+Ty zni*P9p^PlJNQM@+LPiFFi(+VDD`ITHRWP)m(ifTVqCg8Qd2tV1>_R0*oNuN*6J zZy8gVi7ZMdYb+DDB?gRLmgX)b8Osk^_y;YH`!I?qA>k+?fx_XiW8I!YnZ+<^d_sv& zj89r7sge1gr1g>NeWW01cwZBug0dRL!6h{uG+R&O0pJ=MT2SGPOt@%<7Pex>eI9Wf z&8q|Btl@O>NVzts+2JJEf*tq0@+SP-ys5_aJm!Pp6L1oE!i<8Qgy24l zCr*;|Ns@!ZFbH;5Si#JyoTST14vxzp*lA(~gLq4F-;#2;mSYg?ys?5o{2;kMNICqO zFbFmgSivANC^}>8L>X1cW&G!8yG7Br#!eIlQA$aaQnKStluAmilG4TsOjclq5JN#J z!t6wdu^>u#tBQTR2M*v2A##S0 z#$hl)f)>PzkO}vNM-gH|$bv}_v>@_>Ecl{>-bUFD(&PIK>Ji03mNo8e6R3W>LojKv zq)sf!a7ngd;sg7P@*SkdUjx)5euFH>gY|zr0q?@-QD5S*q&zafQ>T)YsU+3LDMBde z5Q?dT*v25bDXDHs1uHO5f?*&@!upJ4pQp*?M$u5OE27KAdQ6$19`Ph(!W;>v3vnZ4 z321oc92jR34+qR%{MZ|#VDI^H3ietbr(kb!tiT)#4ge7=WWrSp8~`Fy$a328WS0zQ zYBKC&BVr@?V3t&Qzq~XvE*Y*$H>K7+b`Lr>{_}RG)2^e?l0!=8kW6LIHfP#f&qmof z65X=5Zgm0%=DlI z(K}>$(LAz#Pi)OaIG=N*)VZhrb7hy9g-#m5^VxkAVB6f%RF1{i5 zL25v*3|iKUtQYJO%=qB(59uBrITI_5;-*om__JpeITR;{QW>Wxq_~BYDn1z*L?y+k zq*SnCy7@FIYp2W#7;~M-Izdc)<3c^6jVLT;jBxIwL~(59Bb3qzrH79#CRPfqltSy_ z4>RWQRPf6D$ph$fjmR27EL`lv)kM4!`NW(O_CQ1uSulx&7Q`HprL}3*lzB@#8=z&a z$XY=Ze4Il)qL8Qu<}@%qqK(LcD|grj@kC@%-k9Z|cE|l0JW}|CIG-4Q24<2nng2Nh z`$*|Na{L+COi4A5oq?Ed!Z3(rqA*c&3%&>b&U+0lb|Q9y$zb9Mw*+FFs0Z8wv~Uis zh)Y~XQA!J!(u(+aVifhXa6PSv=gla3Y2jX45ibP)Niok-ui`EIB+io3XUFbqOk_us z$g)=ycelFNuGeC`0a)qQlXCU{sdVc}z520Ax0!2T2b5F?pc7jWTfw9-n}hmM%8Oht z(D8DceaH3(be%;hWKqlyrfg#rC6sIl#r&Agw!N;NPVmil?{?oH_>xS(C)?u2-pP1^ wcip$O_wVk1L{f-jL?TnqCNY&k9FahPV`DgwGVVQb-22gS?@Sj#OB#FsKie)7lK=n! literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/debug.h.D983B7242F0626AB.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/debug.h.D983B7242F0626AB.idx new file mode 100644 index 0000000000000000000000000000000000000000..11212ada3f75a49f763a7f7e608a8700ae0834a0 GIT binary patch literal 556 zcmWIYbaPW-VqkDi@vO*AElFfyU|oyhPgnwiaBcoPx~D<5IAEQzmZ)< zF6*($)QT@*a!z{-849<^RL@>hkbAo9QkdxfzROOGoyylvt^RuMT+g+eH&5mnO}^H` zu}M@;Z`zWJ9isdCAEbnzwK6J<`p7YhXW#tv^!h~i58P$*V*flpSzPhS?ADG_4)52B z+ceAF+%~C+DlxH6aLNwZkaw}cz+svAED?_TCE6y{9m0wWPAT4EG^~#jVK|?gwPb@^ z{zC3}o>P-D9S;0G{Pwi+71_+t14-v6T`3kgmpLh^pg`(CazUnU$mC@^WPgb2T~_+$ zXX*Za?ejk`cAofL9~)3M<;0UU=iB0E8XkLgUyix^NJ{85)!owX!XHiypT0+j|KOD6 za(kD}(p~-fxDRUR(OmpnCBPv9A*5Nl#7K z%p}eGawJy!y(oOOVc`?^D!tfn)!un3b<3R6_Nq>;W%#=9WClZVWp0u(FubS4n@?O{ zGA)XS0T=`9t65oBv+}W-@R*1)a56D6bFeb9u`(2;rWMBk)h2|`WVvu_lLR9Vn~9Ez z2}~=DX5@ru1gZpqS<&sv8=3N(7`fQAIkfp9f(#7P&!oN7+!THhDD2DO%LfxKO3g_G Yv5Sk6i@AX`6C0<6hdA3`Z9fJE02+SQJOBUy literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.c.A7AA6765925BA603.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.c.A7AA6765925BA603.idx new file mode 100644 index 0000000000000000000000000000000000000000..4f05af88d4a29f36b73527102a8dd9172d22aeca GIT binary patch literal 5964 zcmY+I2|QKX9>@1u)(NN0Q{9wfBc-Hsh*DIBiZpl2P0Fn_Q5saZ&2BeiR7&bLXuuIl zy6KrYrX&;&C5ezGDPyK4-a7BJ-`a0~KF;TS&+otf>%abM*#E_Tp`D%WD2lS#vhctz z7q5+oqNox0&(q7pEgHj|;S_b?%G=eub~l-;mA(JYKf2nj;j+2%a(?Ba>bbu=e6vqV z%8)!+6q=~AdfMJ+`y$pR5B?}rMrYC_mO-o5tvhFWz(V`$VlDGZezN(4K z96eVp&$Ty93)trB|7z!9(UjjD76jNGIW_Cs`4#nw9zo-0FJG|c&5%>)_bEa3apz5D ziD~L^TR*V*G8Bn)zD6@PUn&`Oq#V)eP4&!KlhET+0`HS zl77+Z^ov=B3GKe$C#=x!`G-Pd&)8uFRn7I=-<9<~{;_EEu195kMMlrG2gYc8_bqJy z;&Q*Nus_hNImst2bZ6s$#_jNBznEQ)pPkTXU9UJeIZIMQZT#5zC(C(n4T^cW108ji4PhV0j##B;Fwo>O-SMNcu3(d0(wRqwyote!<6@?w zb4A<7zueO#&Rk+RWsB%o*G#87B{$+L%IbYq&ve=D;YX)FTL?_6O}=k_{;gx+YwwU# z(*{>{oHRQ9{a!@%wECMB!5>yud1ubfMuKSr1bkENq> z|7^UwX2}e-NV>^5aH6qocl5>1+bfHMKz-ANV@1*rjgxGfUHMx1TED7goqcvr{i4U2 z;ZLotGbOg-xeL^z;wu-eX;^q|@tmN~jW@udEgp@MO?uIHAD#8?GBJKx`NZ_ClkjRx za=BvQETu+Qr^o54uECxA!%}xkA{sR7CUi`yZsa-kd%aG|Teab`?FzrcZSC#0pG{{h z6USxjby*rbOj}?7RIg?2*-y#ymJUxI+gG^Cz|Gj<-;5Py+C9W;ldngLshj^^#_m;M zxURa!dEV=?x&-hdNdIn7TjJW~SW_f`NQZl)3ajtz4RR_?o_IOJA90m&UkgB`%lVa zb#xvc8u_707`;B{*7}hRGtPV5o#DLyo4e!FhkL{4%sVmQ@M^Bx!*la`f4iI;HU09P zcRL67Wz-)`e%kG$w8m`69@x7ww8ja384?;FPT!jI@-M;4KiZ$i-6*^0c->vQb$#B{ zzBiqs7Wb9h$c^@rrtR{s;p5*ouGD$u?Px-t_Ao1Exh(Gk5aaU4yJ!zS50UN&!-$X|i>R~XHjT)h}#uw(xd zBbpLm6EWb4!5GmcNMC~bG7}#55-Kt*u%FekkfyY;$$Z{?HPJ~(pM;}i2FlproU>Wz zKVE-3(bNQN5YOYq^HdE?Y15IEvI5{wo(K$h8`EH#djAYCNyMiF<@bD6Q;7MAu?3GNVuoaJN|OpT7MoZoTa5be z2W~HaJX~BoH>pun=&h?I2hFxpfEJblrWBa4*&fKdE3x+3hpp(EHrU$0-zuOj%OFa3-#Wl z5l+*zuuue;B9gSL$wj%&=P7M0WB?|E2<(Q(`Iql@Hva=RV?$;h$(?{(v;d}s%-B4| z*leFbkvD@P598wY|6Iub&N>&BCZ174911JpWu;&B+=kdYznbj9u?QtI% zV-E#@DIl&pC#0|1==`e*7Py17{JhXQ{xk;gXg@43OYv;UGsm`|h4Rd?Y+`%A{Iz$KJ@ya_m{<}@;%mPi zb3HT1|AvC3kY?90G}$xrrO06o7AgQ!LHhLURQ6e>Gr|cAp8@lkxGH@Zn>H$Uf=md6 zf(j024=CiF*_)`tq->$HEQ3+#sF1>SZa_?9|?X z2OI$f5#(URvjqj&gnwJT(`|(L;SJbB0$>t=8N0CAwFUVPCY}Dum&}3t#g)soda5)yBST4r_6vyS80Nvzr0ze5|P68;2 z%gF#Gb2$Z|6fUO%l*;8afYP{}4p2ImGXToqawb5TT+RY0i^~##BwWr0D4WYU0OfEw z51>3Q=L3|_<@*5L=W+o+1zdgr&;u?P0#wN5B7lmxTntb#mrDRD;qqgE9&@=Api(ZE z160msDL_&#R{&JOb#i2QIe&)WYRY0DaRPVUsK3FIROgRx!|I9ysvQ*0#3t3Q*MNTrd zFvf?4yeejo3+F`eeT?2Ve|!!_LO~>Hfun?i9K!c@+g3_TJ_lge&jItC^toEiQM2yw zlOQbMO1y^%+RM&u8QHEKjD=>vG!x+f)2beNMCB9~ssK|(1W$vynC>~2Ay~)+OeQ(& zT4KCoGkc3=LLv_(^7w4{2P&#J9S)gsdZ_FumsNbMARCUX;v+1t_z24@KEm>fkFdPr zBP_4@2+J!z!t#obu)N|UEU)-jj?7HlYig(#F@zTSLF5ND*osb87$AQx2S60S}3P*BH68w z9i6Y&8WiLaZZT*RW=}Jy!(Fujrj49N?7a)||L-PC3oin65e#QT#Z@&ArSOKc z_dL9nc_@=NoIQbFCzU9jy}kPl_WubmpNRi&MzwSM-d%Z*g>=BAlQGVoW#L|W#I~I; z+vEHQ{7;3Sk8F?gBe@&}`B7XJL%x{HS&*N_WeMat9i)YMgve~x z-TtpwI1UBJ$pYEa(D%iEXvzQ4A%7;ZUnm8k!V&k&OX|+qDu@gxQKJ6|)aG4VcFHahqg6-I!-oG$O;u&& KFC)~4YWxS7XGy65 literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.h.7B29A1EE1F525C86.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.h.7B29A1EE1F525C86.idx new file mode 100644 index 0000000000000000000000000000000000000000..bc698a15abf14b43ff93776d741f585d84f379c1 GIT binary patch literal 2576 zcmYLKc|4U_82-+8-5m7^;gXmZ=@QA3&?SkXYmyeSG!bPda;@EzvBZQijAR*%F5QaA zk|m9%63RAXDakS|mMILPLDSD1&G%j3?|1)sp67ku_nh~A&ppgGGlMHJ%;Xe1)Ymo8 zSqQ^0N%Z3c26(>3G0dF6u+X1}j`sWYYKV{MUwHiMxQXaS5vdgZZ2ZmMuB&&#d#pt= zdLnF2x>wR%KaGSO*pPp?Y8Kesa(iMiF~S-g3X#b@_P0^R?g>t4j&Sal%yJcCRfc`> zW;=T7IxPtzK;8KI*Z}r=gcq;c8N5ROk5k}^g_hKg@|d*CZ^w12W#+rILeDAf-P5+C zePq9+^Xdq8enj(H53}oFlSj;Bm$Tf@a+l6}#+{7~U-Um1$<(X$95cTE{+~}eQVpJQ4WH}R*RwR( zCNn?RpSQEm^)X;tw)3TXJYC$aPCW9BzM!(guVkJZ-aR?mIA@~2+0ZC~r_kU2>hAkr zG$u~3xs$gzsj@IQ*>3k?cgNGMwQU(MI8EGv)+pBA8#davF3Bq&n@&h%wUWZj)*qBQ zBdr?j9ZijGBC^a`Tw|vXGE;ZH{^R(Af<#`a?>1@vt-)Wm%b9V)d|kKz!|Kut$KF}U z(+Nxz!=x7heGy18csRks*I^<6;A^EY?cyYvwm;W12y6|KRM6=abU8*8jfkRcT#{f& z5I^od-5BGH@aTXD&%- z$R$~ATm50yJ2ru#1(Y_Yn~O6Na3TShSrP~%fpaxpZR_#MnZQ;dK{ig$#?={RI8lb{ zEJ;=%iR0W;tNTe0+(fa}NU~dGw=`oGh|dCfOayJXtR(hTv5{S~W_UD#NgzQDonC`Z z6HOzcmrtX=nBw)TN;Qwb&?6yTgVSqJnkJlR`acaFrJ2o?H}d$Yx=|DpLlQ#~LpjC_ z5T60)M*dH8Z*WlI$%naaVhNCL#_7$t5~BkrI&ih6QiYHQ7U1f}v87|!(QJQO@S8dz zu#({eedLkBmyc=<5TP1E5?-7=3Re{lu0;B006qgu634#7v|Gk~uZSYz34l+4GDY-t z*7Hqc45bla3vJg^Fx6R83EBB}Mx|D+WjmWPBz?S90sKG%MkmEvDQ0lJN z{xY_43ySCfumdPjHD~cYmY>y#Q$vI~G#8XcjTbT^hl&h{>aMO7@4mVn>7N7m9H>)9 zs_8nrDs5e~5K#?aHISnS14WB}4EKqBjffHeOO^?0K2Z*GF3FIo9)4PVj;JMy=mfA6 z=u=j&?~4wpU#zo3L@R);U@JxJi*r=9&}_3u!~lQ;VCnDY%SYW9$`MH;B5BeTQR6+W zer>OkBZ_c?ZeLL_wGv2AE&|C=tw03103=bNo{v4Xz3hRELSd-j0&UK?I)ynr2|#cU zfIYy3%J8vBlX&H*7=j1~=pdM#IU`+K)IBa2!FJG20PFlD!VjvL3rBDlfL+U-ey7jg z`$K2o1w=Fg*a)^!{?tOELdi8GnJck-?i7YKM572kfPAoyium3zv1G7fXB;9P0QdmN zP{f3?>^9wl-y|Z!9@-0P8m@JNeVL+H5bOv21ShuZf2P+93o;Pw5B&x3!yiL66f&%{ z5c~qb7r>NqFD&(2?cxxYiwHJk3-m$Uk%5YbiB}Ok2;ksyE2(D$9gKWDNGF@}6M4+Z zfNLnC8^CU$MrD`?(@MI1w*Cep@&L?Rp1dtiYL$Kw{NE5^0WAcntchiycVs4&4PaM7>o=Prgv3KGQE{QdysPf%KlxQ=kuc_^HG> z(r*yK``|u7+PGD3z?9UO`FPmA+G?_+36M#+2gvn_Brd#8KbBG9pfdV7+zWO*XorDu` YlJjLo1cQR%jO$t#8Q#Z|8`1Rq2M}u!OaK4? literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dma.h.9D5A0793FF04031F.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/dma.h.9D5A0793FF04031F.idx new file mode 100644 index 0000000000000000000000000000000000000000..ee6802aa5f92a9c0dbd1ec7156fcc8b023019e64 GIT binary patch literal 18698 zcmY*g30O@{7@l+Q+@-oYsidNiNDE0ww(Ml=sGmZFG4l>RgK%;cW?JkHnuzVCc8y56)#pBqa zt)T}(P2Na5K3n{%SRHXs-yu!-*=6XG$`!}FZ6{gpDvqvQUT?<~Z()HO$k!HZIgsW4#6!_TAp5N2^!kH1Hm3R3V z`B8^V!=>6|CNH!YSASf?b$7B$p8*kL%2NYIwr&12?8euSq1znJ3Hq8m_U~QY@%2oK zYn^3p`vdcLuT#D5oZaMBU#UNAR=U%esk?ivnOBzcVcEPhbG{6>*r}d)Hh9(?H7AAt zR6Xs^UySiRYFD>-Qg!K7*Tc>E&)aIY#a;gzvhUvV(4vh);sW1;w)6?D-%^4P9@{ZK z@5|ULr-n=^*7DoCWlxd+kKQLo^L2_oj&?pB`dQ^;VD~59_WIOIpkP;U&_?q|=rS99 zn+HZe_yviE(+7VDon+~2{kTm}xUP2B>X@-XQWqLWQ57pmwEMdmigVYuSv5|J~ zcP6gF@YQ=e?k4SY@8>t_f?#vz-p8{A-^-u%vzqmN@=ePDdfTV*Tzcl(Oc**cDDJ1G zt!hnGuUnq3Y7j+KM{x z-N$`HmKhCRXVYb&W}hz+Z?7o4=(atDeb)lS6)g@#$~$;`|$*Hs90tm+orS8@RF5U)-vAmv5^dZ*nZysxVROuaV}B z>cP%uU4r|o{J0(I*50IPJ$T$i{Y4WZ_f@-Xa`XIB^(s(g5wqSZNH_e}-ld-7%)sPO zTb<(ZPMfAZo2XRGJ3vkN9ktT%dHA)U^6pV`Yp`=?)X#o^iFRQ(? zgSMZ#l-J@IB<%QXv*1J3os8j5f8WM+F;(8*Z`_vf*!SYTZz}gEjyDM3;%)cQMQ6W? z4kg`uMBV1)3*+rmi|B`o&POc2Z~VT8zhux=_3$`{*?aTGEsa{)$GorN^VMTDViO%c zoPYK=_>=az4(p>&`(5ZdtzTUI9f_}VQuI)(dXdtrgs)?+?JE6NH(5t({Iimz^3n>s zrXH>E*Nqev#d@n=L2*SMfd^fG&3N_j+X;=>Yon6yZ3x;o`M?2CCu}Fk%7T52+@H6H6y7^JlwD31Cq)&sdO^LW;KlI>A`bVips7har9sAAR znXW#sdd%Saso%^98!eGj@$U)Xc|g0#VhMM2qpsGOZAZ?^ALS4%p5`%T%^%iZwW?N^kz4$ufc38!cNuQ2a9dS7`-GAT3BR0>%rK;ty;;NPR z-@(xybK}1ry*9g7-Ygh$BEHw0H7dvV6(21Yn!XS2zEb)9#&a{x_69dSkAxsk(zpE#*spJ-(rK^qaws&#qp#8M)QB zs+-rMvGrp6i_JfWn%w`}wpx8^D}QA#&xk$0JRhzdeYe*Cc<3f^tIz4c#iq7)<(B2m zAzwayUG=T8J<2(yu5s{o`-G77wRJORuiv<7@X!qzt!sN-zsPGn()iK(+HRfolSW!w z8fR*J?{a2)nfc7z2dl;{dv_?H{}{8IKbEX$9-HGoyKK+Tpu&m6e(n!iGs!>UNBK_m zrG}vcGP;&o{Jv%qI-w|3Y2>XC!|;botyjJro1{M8y8XA|nDrJ388_@_`V7j`%~Agq zqpvbEXqD=-pI!2IxXv$e)G(Rf;-C`z?!?8wJWW5rq~~WQ3^=e^FG>VPm+K22 zl-75v9ec%KPHI(1^>OE@q+w44#_^}>zG(&J{wcilY?We>naQgAsXiOSscviFB=zA# z?<||_CB72Z`-uM@jo0GaH_YAy@4UbA0tm^@YW(nK)#$paUAMF*R`0rU`fOJ0p+AS+ zTnhU38g(~d+3wO0c^a`5g(+UQi}lS^>^|QOd-UeX+QGh0==OMr=#(Qbvj2;5^6*X_ zv1oU%vc%>_`yO{!&-JZ(X>nF(=pn;Q;|+g$&L1hZd6KWOOA?_zR(x&nCeuAvl#&4yY`V zCS1PI^2I*Wd+UK6!!wO*226~q7;@D@cgwmdVeMy{T{?Q_|Iz&V%TWL0{JnLW_7-}U zvEcG1kNDkdPP{tovg7kYPm2#@svo!07b+bT-fgdsTBC9*C+=C?hsgyI!S0q0>rOt* zetynEs#){j0N1gmK7B7JS;f{2+wA3izB%4IKK|^O*0bJWlZ|^V*_+aT&(r*e(I31U}=&sxRoQ!!^ zZTlverfq}P+m8JWM3PrvNCRe#v;xnJ1bT`}vA znAq(~8ardF&7Qu?6|TlcZf$ToTyXO!f1bYMhcm;SEY_}_S(hUXDt;KcD(mbwUf?w4 zF3+|{{Jao3;l#GDiwo-~*10t4PHDgJK=e3c=PQ+UPt3gra2ze3>nm_vNiJfxtfzA^KSP}d7mD*$lKCyv*kV=&F-&C=Ikh> zY}TebpM3VGXr^x3g_iF33?53RU-izqQZ8Pd) zNi`O!rS-cy^U$vby=4hY_Y58N#N5bk;y`_q%fY@)wN>V!-AA-LXKw$n(dOzxRIsTb+lC5J)z1ohb6;1IP$**tt z7aDbUtaID?+(GJJzf8Az#l7rrT57`zR+L|kK0SKU@Z=4l&%Q72Z|oLXwjuLV&Y#A| z>UtjUvh9wyI_I{$Dqm~d>yCFx`Hxz?OX*uKCcj9E+ADMp%M^~dn{ZXq%_aJ2u~FTs zQr`u4Z}Qw<7{5Bu(k1nP@iw=)YUu}BmJLzXqDAxPx4((=eEKQPWLkw!q{C4=rQ(jw z3;i|^e7PuK%k#5U*H&%SN!zZ`5Is5D^=YGH+IHoa-8CAN0)FhD{3qw^PTPd4?8fwQ zBQ`r!P@^{7p8e^{->NX1OEpj3FV_gSx_cBJuG;8wz3PR#MS73&L!bJ8KDYgC?wAd4 zqepJAiOO)DU1@I6n5p)&^3b0UwVwtCjgMzn#zbXEM{L-g;$hX26`Ng@ux!yE{kDs0 zuXaM|nwp?NgRHI%x|~1IAgy6v^oTPF8fgu269vx#a@-^CX0v4SP>53}i>gA*)292#NqtS7u;1cxlUtC!NXEN;>Iw1v4d{_?D} zOH2HWdAS}69mb1itj$oh6{LCc!K(*5rK&35acVsvUA$M#(7t8?ZO*eG02`)u2FTQqoej86IjzkI*vHC=;`1RT{( z89mAKrS4`20o8Q=?eyG)hrcd=``!PqiMzV4QGd6}#m}XE7Y>XX(eJxb|KH;+m$a#D zsF6Bb{9XV&x4ApNQ3uRw9`o*sY7a^oWK%SdQU`fj2YLO71!CqnfcXW+^c@!Fl13?k z$$$|(pm+}`HDZAR0HXk)q?BOGrF*X`a`S~Wa7MZ?3WibI#3CIyMx|0nX;xLe+g8s+ zkp?r7axGljjlFVIBfOHX9dBOSg$CP^DxQMzloqiZWwC}+#xAY1T_hlkLee4;C=xL) zSql`piTXaFuF0xS&pCWTrDM1<4FY7+ND4+$jFhz;uewtWu16Y)X(eEVoci;4{ybG; zk#Ypv?!2-3c@`Dj8Qn3N%WR65O?8n{tVKdgR=6svV#Ln$-!u&ZWy0-nJ5w{da_ZIC zINOi z5M9=nDSPf$jZvq;Hq?~U6g*A!AeK|Pf5xmyU%&m=jRs4QGL(X$Xb@S;Q8rY)ywZ{p z!6@e-`nt8S!0&N<(g6oT{$wdmY)Nw+NNnrz!{k=kPia+ zU8NLjQJW1(TW$=UB%XE5Lz4#op?W=_2U9P)avbv8Lmr48cxchU6{+@7a36YjSj$mP z3c0Yr^JB9%4W=OFO1P5ohprq|4csX>XtS#a4fe`zFo}Xm$RTSvQc38zQeHv#ifDRPtFH_SWfQQ8(rTjgr4(z)1Y9~W*THix-H!(A(H#a-FcA4; zEyv&FCfDXE8^<%sc}Te#Zf4qot{hd8`u&xDC$sz0U>#BgP%r@bV=YH{aL7#mG;d!6 z2{TI8??arm;L-@(`+TTCS21S7@IcB2S1in;;?b>VQLOK4ToY~3GiLWA+B z;!+BhQX0gf%CArp*k$JxZ?mp*f#X0L9FkQYLBR+#_gTxi&){JvkB9tTY^DsZ%Lb-} z(rTglNGaBmfk_W3uYB=(khwCrCsVzpwBAzvr4(z4Dzf=T;@+r*LnRk>vA{kDD&8RKG6bwcq!&=S_o*F!8;eWf1TF_uIQif141kF>{ za+LRe8WwLcKWr%hmt@rk3qY`d8AH~h>MclD`nps)eLj#sS^`2DDem$P5$F)90R;`Q zF3}w_Yi>|>bQwbf4^;VK3LZwc$y!e3)%BU7p#^SZX>deV`A)c#>2P%A$Px$I)LAF0 zSkYiBau`j)XtX}DmZP+|k$d#ceKSV6Pv-D41uvuFW-UiLr0>yO@$ZWhl)-)3==`9x zeo(!o6l=-o`McrdUMkoIBuZq6IsA&>#K_>mo1E0~u z%UYnIOqr7&a=v@(rS*ve(`c{^HRuEdPoUvpE$1%VK5sPM>#bu=gQZA$oPx)ZlC>OV zMS|hXQ)xxhX<&nt>*4zD?3JUcT3Gx3-2|^0G;lUGRCl>pU9RBh?nTg;Aj^N2NF`FK(uVqCE``$Zjr$f+=W>S<8{GACO|W zCE&FK4b~us2Pt?EJ&CO4D6Jp#2{tfV?kEBAGN(5oxCxoTV=Zd&AkyN1$c*v<_l*`P zgR8O@f2OoPQ+mue%PeW}wgsBa2ZIfk&|o#H`TzwFpsHERsanHyO^k<~)>37VF7x-E z(t1zzl~SxF{*1+`NH4rNr{NEJuHI8-ZZIm*}X z_2+d{O?0NgL0N-SDVU0Sk+mG@La!4G0tOo_r@>*FbO+qQ)Qzqj+1n84-gb4On*>~x z$*P5*TF7)EYk`6)97djh6SEb{D`wcaDS-*-HlI_x=jff0waDp6_La!{AuqI~eC9f3 zkSXgLAD)&E&yaZzWtMb}XE)!Np!UXfG?;|E-KXGvig^=bE%G*YGP}aNdi^T7W$UwE z85GFebx>Lz)Bq{PTH>~Iu97t4VkKz(yB!&))H0W=*0td+zxusz#3J$8m?yg z1YJ3OvbZJ7vB`JJZW^pYs{It)kH&+w9OZH~Ahl}Ru!jaKkkW^OK1j)0j&jJdMXkpd zXY5r5`Lg?~r?l$P^TJwkf4<-2ZV!I2(}xC&kiSd{W>U;lXD!Fy)NcXvT!%~d)4&ZW z{V3>%YGy4*skL?ExS}P&MlD0>n#5X;^7ww; zq@O;n$7$e>l>QX-M?P80QNBxTZ7W|_ae@YRNa+bZnPEg%j%x0-?U&vA4GE*c0;Ec( zU^=RqwH)QW)&}9^q}`_^AX?T%iF}aAXC6k@qAu!BCP6|?%T=3Ct*2)9-G_Xa=4R8ZdlEk|irI@kKnk~#4bkR)>$AOZm*W}31VD5&s;lD2@naT5cscRx=9 zKbbU*f@x?qVJ*k2vYq`)rAy}$X)q4e|BQmq(2mAhq#TXk$1((zXXYxki!|7TgvTg& z4BaSeIWEO(_0OGm-h4>{&a<`iKpOfMOOsik(51@|a-%&4EJ`Y#u60`Ne9 zK38QHjn4ogO+QnTqV#PvBTbM=e?ssRGG8aGMbg3KX^$}35!imxHj@Tk=vL2A@CWF$~(O@o8Zi1Vb=LlUnszW^Z;o1AT92!hRs#S0mGm_}aQ3+=(&Wc^- zoJRv+*$rNy;1$&AtmR05c+7K2wmr*8rz3}M(2c1UT{)`YsrhRZdnGZdiAZ&ig7+w< z!K_8fF?b;z)Vw5q!x_zcG+2&=dnvdV4Gn8KF8yn^8SY*>|Gor7%I>jN0BQxyrodX% ziTy}_=go>)dhKgP0S#s&r|aN4rqSriaj0f~+3K(ApF#;Z$vBk#q|_b-utz}|D5wc~ z5pO$VuT3uay{?D`vyeA;=+1aUSB|%Uz9L7FY29ITH=^IMx4O;72OV-kXKPu1M z@yvWogSE)lAqpNs&1EgeUx{U;+Qk1hlq-V=GJma!cZ(D2kivE72U3JEy=uTvt$l1On6 zprEPPn{>+6I^Es-bSo;A!6TWskCfI&dYs84GmmSb5Bz6B$}bD<=oxQ z-`5(>A7A&520M{5fr1IBV_3^ku9>@CTQj+aQEo)aAPNQ{C2Kj#!UKz(biRFJl)I2J zk%Eax$y$!G)Zu!K>g@?1Bp_VYjmaXAEMlH()&hm@3i_nsyI%te|Fq!5B>P4hFljYXDuaR24x~Is!E>m0Sj$oBJXNc(9~1MP2A)WHl!8Z*lC>PAot@Kbty1w1 z2?&ujr-lz|_{FLj1df%qLwbLL-Cfx;hF|z?(IrrI8b-K#Uwu6!Fm&vYD z@G4sGSj&<6Me5yMVmGjZ1~X9O*T6N5Lv-b+z{V9TJ&*PU;F?uIx97=xN+4m*<#QBlxG{2Zs(02kK)#oU7)FybV z?jy15=nfffBev;9aB?z>^z5-LVaQ1=V$d-x!O7Vx!r6mY!jQ98#NhK)Og-^_`=x7m zX%}?Ar9Ayo9&_x;{>Y&#DuWMNF+Ayk z8w$RmXtLNdz#awNJqm_oFCizd=muoxt+*sPYDG9cUd7BN`?$P%VTme_@fF7J6UH}_ zyRkIBUK)Q00mvaNrOTg4PPRz-~LG!^6IAQj=V<5P^2 zlT(D_(^AZkgHpuE&POr6bbdH|^75+YV5VvBDfpg}kPlP__(;Kzl!R;}3{X$OdP+h* zNf_WW1wT^~@{P;@jTCI8BxC_*fF=qyQ4(^t$pFn1Y^Ee+r(=K?3bs%Za>&L2KPdQv zsRf_dFu-Y^%4wcv=l2LYA?)^ur_*_Uh#IRJ$k!&#XNn~9)e`wVI^WOHDP`Ate67wi zOtjv0tKsW(u7>EiL)!=HbsmPGQ=jfJuvh1q5IP>{b`$D!9v+}mJM{|Kv-3<3y)A0} zgnc^SCDFlJ*I zOygpOJ!6IXol7p-iqxdS9-SK%T0FW{3w6li!4ydrX(o$$lRXqlsVou95-AXXQDlis zvqTmIU=-ORn9WgSi%hfsDVQQfB8?)EE?ESaA}>YorAUDQjN+xp^rgsx0F0tS1S>d- z3Xy5WKLt~yQKZ@^(k2s~0XjtL9ipC{$C1pcA?_I|*6(}^LK98xmbeF*dQ6d9V!c~p zBRSx;n0_tp-nrvTsn=rN*W&(iz#B3BhNIY{K<`oLP8JQu=^h31Jqn`;Kw=7LLg7FH zo>C-+fEZcm0OKTTfN&fsz|5){OLk7J_^68(%WR%THm^4(00|$UGB{*_shx9|<&2(Y zu7}F(6&UXoj3Z^pTtj7W>;O|Fc7PZhFu)9n6(B|yBEUF_4j>$d1Ta%nB7FMl^cDle z*otj+F$~BILpY8MU}{q2?Vk}>M22GKj>Gt>Vf>z?3~(Nz~xj=nNwpM!qcJPYE4td6J*4m)6q zyfGjKhZ->R*w1faM4Z`BRc6|y^I$qpk$gEbz+)bK%u^&SWq?K=Y~(4Ddt`tUe0YMd zNS0IvNae#+z9Lyt8Q=*YKH)2p0cU^)K5XDCk|mV^A_Xu~ph#9f2FMV=41pq9{TQG` z080dlWc6c!MgeRTD3aBW0gegbF`*(^{TSeq5MB~0lGTp^9thzBp(0uR7~s7Sz85Nz z)sF!Vi{N3AB01q;fNLUnO{6Hd*p-Q3nMjc=RAfa*or)tfxKl|`1~E7igBcQpK@5(( zV1~3`Rz?}{>^0m9{|+sEK%1ikrDA0>|Qoy+lPJQ5fjTB6w70dpxGaJ z?Lgjea0oNxMF254AcPq*YY>CuKbRq*AH%fIKG1^652rwitCUPB$$J6 zSqujg&+o6Rw46L@mMYU0cAk?G48YEFIe?w#asWHemjl>&E(fslTn=F8 zxg5aGb2)&W=W+l$&*cDip34F3JeLF5c`gUA^IQ&K=eZof&T|5gmp#;_INF6N66it< z4sK!Q@|*paHlElwN0aH@Y#z+!DH3lCP|Aa)9H50KZs94*DO!2rRt^xxhhcnqA8CA; z#sQx4;ZqLK$cK#_AP`CdIddlwN)kChK9uBhfOk;xjsxr!NcIZk=Wvt&MhWC^EK>k8 zIY6lZmU4hE0{Ddk1PfuXP~Jzf5GHeg0wFBm01ZNMgHXQ5nuOve4iG95hl=DC;UaPP zKY&CZ(a_0)j=1+pybPKS>`;@h6b4|2n(S!| zzz#L}N?`zYsL4LX0PIl9?bGZ~%k9(bP|NMp>`=??)9g^o?bGZ~%k9(bP|NMp>`==A z>`=>X-0V;jfSGZTV&h1$Ir$hMAz(C?IPQzblJo~+aF`b}o64gb_0a-{F z6M%dqBL+uqF-0P`h>-X`U)rg${X21${~dgK=-8H=Zv7y)S~!Qy=nxqH)3T zZmcDtZuA*|-3 z@W>aAykl=9=#Cg1X~zsX(LxLktYd}*))9lF>6jsbbj0B3IcCT~l{&-VU^!-(n?1%? zI>tGvO6Dsi^R>wyz$gm&N`-uFvIj80N50ZWzBbtd7{CuI`9W>62QWY!REmSzWDj6~ z9H^87waJ>t0I#9aYp6~300wA-N^MY^>;ViACQu3!Xp=pF0a67@sRC`X2QWa9K&eQe zP4)l=s1qpF3AD)`zyN_lr9h!J*#j8hyin=9P@C)l43H~S$`xvpJ%9mfg-W$TZ8D=6 zAXTK4D$*vOW(-gwQYsN?lTR~}YJj>O=NI74^?Lf;dHWH|Ajp(qPq#3ECNO)LB?qua zRdN7(GDQHl$tC$mKJ^P$V#=2CR7-iC=jROYl&|`fFAp^GRU0`#Ak+?o2E-XtBoS&S za)5lOozDT@LG5=OV6Q-XuRz{Mlt48~AYW~!KsA#C6bMxdgq;eKYk|7zf-KR3+)(HV zkFQSUnxSa+jIU*sTPFkB17Vh0U|_QBL02dkqiptM3y*#m91ty z)e48I#3I~YY~P1C=&G1J@3|;D7M+x^`>EV}9=o5)z2~v}DOtvuBJ6%D_gcs9r=*dL zg56Kalx6^SKP6L|0oeVN%svKS_fs%p03Bf*I1c zh`|{mm?6s~VsJtTW=t~_mkhGwr=XeC$k%WDw-3#K+>}@(Nk~J_Yp6&&R5TD5LCaCN zNIU!=kbkJUWU;>Sb>!rwsO!srPclh0K^5ct66}SfmLNu!QG)SN9sv#Qw#M10+8aE0 zgC~-!wu}eM{sH~_9XxC>f5Ht3BW=OKf>dJWlT9 zUMg0TinZl{*W#hC#iKYU_x<092NIwlT`9Rz_x?@PFUDfyE~ND&$p+!F+!{>mQVCjV z>SdaX`m2R!+QJ)8N-#hxZ%`|5905oM4swCBZZJg>ZV)5Ov%xq?u|fDfS$+-iMRIBo zgA-{mMJ6<2aNZ1NNXiUiWSKG;kGym{P)S9h5IsKcpz*tZt2qf)p!3B&Y}O1eLlS0? zFIk=p#!1u^;W#Y@GbAkrF*p|nGhq)`))`)%|5S~s{}>-0;~Y&S^Iqb^p+OvkaU38A!W<6p8p78cpbf${4iF}QVVt9hQ~^xo07U{=!~yCAu#N)+ z3Sl7Utm3>7p639$LYT_|YK5?t1Eh*zsz|m$B24@Ok1`Jm0@YlC{g{Dfd zuurhC^Mi;1l7)K7!p<=G@-v}`{ z$p|wfzX&lnsR%P9p9nEHi3l@f3quUf8Nv*SRwD+d2w{dSDyWxmW)Nn`9*W9HWeGu; z0Q~$}ss~PmG@ucT;|+@Y_gzO;MpOo81mQv?BM31#4G1$N0|+rV?FTa?;|DP~%?C5& zwE{6Xs|PdWbpkOsi3c;}B>^!wX9qLkZbMXf8r$0u<0N+K%r7BnJP4O1?_fR2+d(+a z)xiu&(?N_ZI|t(%SFBxz{`B1F;>qMW0g%Ha{E**mxxe$|{?3*A`|iKLc~VMv>*K(C jhoaYrbE!P)Hg$)}q3%*Qsaq7d`A-L!|LpwT`SN7(Y-am3})~GT1Ep_v(~! zC9&G0e*DDV>@%ZrlKXoWpP6d+?Hc<0Ia-Q2>a_U<;}P7BW-=6;|G`4W<{jm~wJ*8S z8FVl3ir9Lz^(#5^QQXz-SKN?8AvElN!@rg7!;;Z%i#KvH6hBSz4?WDG7TPWrG7os6 z6u(sCG0}4Piy-7ANZLVhXSSp|Upc(R5fDMxIR&Byx}8b>-^YVBlCx|kp&Z7XH6{Gvy$0)$R6N9j%v;6`udE`EgxA5QgX1o zIjb_WTdYM^f|5fmvV4OdHauCcLp}%x$rtqW-<-m&0q3gCK~s^Gf-)Xq}#Q5;+-?$P-k9@`wl$YoGQ`1ZPX zv2kefJLDoLBGd6}es*>Ky!sw;Fa(nVRe9Ge!btxyWDRIYfvT?dr<*%_pePN$3P63r6(_|Rp#t@fGh+dsYF&8I2&vze2AO^DPdGQ z69$FDy(n`Uxdckc(3qvu#@5T}GstO>M$-CQ7d!89Pd-A sq3yoQR`2?LZ2>tC@<^BX9;>PK)(xH4tch-?pKn zvp)Zrsf7IOg}MeCTQ@R`-`Kl1>5JZh$pRS)HNkx8e$TEH@|-_5Lww?izO;F6rpD6O zuaxG-=|3+&b?lTt7gj%B{Dn6kfUZkeg>xKyh^JqZsY|0c%c8eqXYEe@XPR zoy&TR(#syMPt*L)+9fAhUtF1+1Poe+qSUlvaUgwLD3DQJ?B6j)E)^{fEl{XKKv8N= zB8XL7lw7Vx zN+XzZ2qrM~!GHve!N4GoU?M_>K?)(NgkW+am~059D1r%0#4sQOV=ypCBABuWCNF{s V40{;hfH4>tlo3n;1d|ED1ON+IvhDx? literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/ecap.h.961EB755953DA208.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/ecap.h.961EB755953DA208.idx new file mode 100644 index 0000000000000000000000000000000000000000..b29a5ff68337731e3f47a69fec9ad7d625e1e792 GIT binary patch literal 12910 zcmY*g30zEH8@~6>y>})vm1dHriHfMSN-0a0Wc!mPlwF~PA}VB$N~;!;B54tllqgw3 zN@*byDTzq*wMYq3eD}C>X70={^Y(k*=e*~fd(XR^b7D7l)+`rO1evjMuJ0CSA153^ z5CQei+sA8@Ee}DKtwa#tgbwvJo*yiYs{Rbw^C~EQ#_4k%m5ok~Iq8!GNn1j-I~s-! z!XpfIN+#x2<-{1O{CFE#6J&T$+jf;}OSSD-4RhOQ<(YQpv@?2}PEM`5dv0yi>V$;? z(`%{&UrO!ey8`;VKlKg0_V)Ja@11wwHU!=svbRhS(rjFn_rFz(kCl8I?W4Qm!PNdY zfxfO++@egZzut3|i?67;!8hi4*;S3-t+apGO@ro&-&O|(wL6_^*EV?YvE*^7E@(`pgbw_kUaQOWh@?;!)_Psq=5>Yx~bM`)=*JYhPYhgZ2#Lq}a0yAGu`I z`>o0wCHHdn))^I-zIs?U9Ev@X;=i+FW}WFJw;_999k#oEcu#TpE6?fAXYJ$KPkExT z>Y#gfsmYwT7wjt^H7L5qMvh6^o-j*p`*cCqFQq+BhBv1bZ_r+`=h-M&;|WZ@jTj+a3wypZk^ATbmQ@)0!ryZu|4!prOLRFbBJz#~1&+J}Izi zprcsbHb}AM^Z)kz9JVNbWOZDCzS`}icSE1w8aLa&X_S_l;jgpG4c0dP3BwoFwYpm5 z4KzJo&+x(Wr-9MG)?aiQ{afOzKaE*_3)Xv135tIFNK5hOKn=H8 zz5Ytx<908f6|d@|+gVl$%mK9oR#cV%lI#Ekou5VtDsqy&*3!V?Y{FBoXzPx;dnn}O;^$s(a@`gK_ z|HaszcWG=`_hYnwQ-{xFVPorJyx4iJ>dgCftBle=Oy_+)TW@YS`^SyvW!rvvdYjeM zmu^DN^z3`Y<@1+Rtexh1dq+pstn(o@p_Tq7TCr_*laikl3gf%^9~}?4O|W#%D%dzZ zg*c_W@b9)i3)XGf?VRC-JH%d%IeJ_4*Q{igq3WeWI8%CEVN2pZnIU3qDJ(lh8{pF+k=^K*|O~qTi$ne2YzVqg~M?5D# z6*zm0d-BRCQe~_9VISq$Rxyn#xrti4XKl~#PS~gIu*hk<{*Wbe%vT4ysMz@?%*{Fx zKeG7zh|kZPBKEAYyIXZmHCJnpa!rxCGo#?}__#@H+Z;?xt|n@>2#!j1N01q>{hc zX(pvJAAd+``CYd1_^vO;o084d8>c_<8nXV;&!)v!FRgRnc!dX)&hZTo$QnSMvXT`B zC;ERHrkQ&~U3GS@>(}vFFL$AZg_Cq{1H7{CQUJatnF&_y?*6l&1-n$#OKAo z)|@YjJrn$OX4jskI_`0|VSDFVvvPF?KfhV(sJ^?>WKMbUsR`f44Pv!8nTF@oJ0af_ z9nGHY;y0*z1e4zdsQU2lg}T=MA3h(}SUslF_T1#iXZgt?c4YUR7Uf)*E$QjxocSrF z@p?VQX07<8cxCBxO$$f4fWq)F+lK+kC-0jdP3GkozGdSxij|%XI-#}Uh<(*zv!{xe zR!(DIHyYmH7x_7Th;gp%^?mK9RKNOi`-)pX*&wB#`~_;IGpC0h z^6JcVyL;8Je0S&eG_OB_FYc`PU%|KaNv}pF&Ktg|QN#FMNNpj{U~`B28>g(6$y%<( zR!-wA(mUo~R~_lVx%EJqT-TO3`1qZuF4vTOYQsGyyxuCd(U_ZEDv_5)x zSG-M&(hi%plI+k^2A2cw7wag9rr9rEb@$P)na2cE_B8}g+-hTfS7}Iq98v!xj`P}n zT04<@urzyvR#5!V;2EaxeDYVSpFdTi8uvBSWoJT9(4Ebeb~mq?vocT0*SVRUYd4?v zv8{W|77w3mqZ^}_**eyRH(s2gR@)gjdgX-B5+bqnR?5`f1K*B(`)}&jD{7zi?KGO( zW|NUQH+fpP?pY0`)UGtl(xfl7b-(e@?Kl+&9Qx=x&7;*-ych}$QU*#=t-(au&&`J42 z-$cC`57#K9JktGD)cDeQ?JZ63)gg6Fu5U{;i|(I(JbmU!XYNWL>shNVCn=Y19Is#e zT+#K@>ylZGbJXLP^~vYOfBzLz=s#g#{Lf$V?;K3_t=#5bJ2EWIO@1i$>QLn6)t&uQ z69@9thR-udX2dxJp1ULu+rM`&DV?+{dcO>dywkIWJ&wzCrmFpUR-ch=Wl606 zyVSV3Dfft7vf;chw>QpPk+CKI+7ZtoDj#=uoy_=j#ZUOic~*=$ak=}} z>kpJ~!}PP}hsqVoFL@MWAN%Q(>+j{F7@hvuIa{1RuOD=%yhmq8%Vf{NOVr*Th+?Ij zU&Os}POvRcG=Y z3fkOfe%RL0uvK$T&Hi}~=YIF=E!BTky3$Cm>4FFEdBhHnnI1pf0xE(~ZBsoX;d)H? zbV(lPMbO!qv)|bjy{_5yvuuvy4bz5s*K4xvtcVpnwf`A- zUdcRJ9C6s1cOoIQfGil-zO5jnHo1T4qD%HHWe>^?zn=e5)%xa< z`j5S}EpES_-o88azV4ajW0%|aew(wQHNi2;@Uw<*)BOu!`!{o2?+Ki(f>VY2W~=^a zydN?mZ0t7Qu7~nmt=P{4BVTl9w66{L@oYoK`LxSLa$hcA3#>@~gS~lSobk&& z&O5zAC)eeGo#i3jUB71k99C=c4qrN>FKwgM5pC0x^T+Zc$69Y*ZS1*c!-4Fyq;+eQKxwhy_<`yDm zU;ODc?nV1YIOp$NIJa-e+5^?q6$%4Qs}JTs)tHhVWT%vMDEA{O_hMuk-g+hN&~kV0 z#ky->y!pOlPikkU-l4u1*8Ese9MbihU5ws4G;vgFfnMSG+g?rk_v?2=d7+7Ycho<{ zs@OkW?&aisQSWq73Fq8Bqq3zFEHeGuM!k1^FmL0S?fR^fK7)*7jyrpLTSj^a)m!^X zq04mLNUh*6D+c+kQ<-$Wz_+ftC+qI3KE3;$KaISVmS)??srPKTK5@`{+mHp$lglSq zD`cu2B$vJLB#ri8I8&%Uy0Rkr@I;f3_I~>NcPx1PDl~%1kYja>WKe)N?T!unRPpntZ)x1^%-azbtGjh|ec0N2CAt+Mk|8BheA@T2r_g@ZLsuf36e^1$dN#RUdkJZz(q%fJ8b9@-*Gu*$CU~LeKb?K;>e{jO z_a4*Et^!uj&gJiuEZQS)4b`5u`rgj0@8x$ea$V{J*KI1h2Q;rZ05nbq0n$g zpU1p6?AI#;2bce4yXB}_BHp{VtS{#v$g_)Hwi^PvNJV4@f`p=ZD4vH3p+w{mWUBQ+ zG!!KcTp|Qtd;2&%#1-&rSVL=AMo=Ph@~HkX^dHgg=|#UHzZ5wx;sA)3QR+ttN?>pb zf&haG8&$vR?ARf%h|C7O1NZ?E{S7#K7yYx9q4D+f_!E8bTwv)!iO4B)G@wb9 z4Ba+eLyHlL$Q;1jhwr220=|K{{q&4)@zestrVoxnr90r40nIEGOZrX?cBC(Yo5hpaOn zKlDcV6dpotT|?1KLXb(ALW#&J5yK&~Xn)SkS~fO!hVPk}W-OYkTI#B0KOZ>Qy4 zlUb{H$a+8wCI!Ky9+aSOEof5H_G)1hJJ*?qtOm>^QjkQBff6u>L1yRk3bi*4S#CUJ zD`1{s3(l~qnbQ)HQ^1TNQ!Zh$b5)au4;NVsn8hgdBY+YNb29zLk8R9dz}vgZhllI{ zylz6!O;CN)5|LBojfEC_$}bOpQJ}nohxh_!2Px!sh+_%=ywv`uko1}OV9uD{dkBw;51-@28>#|v;@|4p|y3(-UeLwW=1iW1Lk>L za2_{+5-^33`MLRq!hiX<{J6+0z&wglKUCDACFpx1-S@z{2U;KZTOZ;fj(`_K2x5q_ zP=bXv0$Thz;@UXx!Ky(#WFugf;DQo-G?ZYaje<-Y`(-twNASaV$WFklAq6!g#iS)7 zCt!;p(|zD*=zp^|g!7QKfcXm-`~o&<3Fc!8nIT>|_HDL4kvwD_U^e4|W}I39o83(D76RS_6n_9x8!Z8E&*Fcf z^hS|^YVGoKxje)J@T%E@YBn`#S|V~PgA8HMgokFyP3y@Ic*q98EG7iS1ofJ>Is z?j@}}WCh@b;DQjazG(@3Mh#jd?{B@cYWIV7MZ^{`Powy0@O)?qEC!07Pk6w)#KU#! ze|gAeK)gi?Zh_E4OYq2bph+)h7w-$|2!c(Tjm=uR3kL6kH-msNrVBNdL=#X)=pDnxGNyMM)47cqGp5&o4R63kOR@;a{<;I0 ziKH|D{p(#|jfEou-Li~pSQhXtQ$Q5?8?UH>oEq z;Txew+D+(p6XPVg8UPc!32O*Y&fQ1geS{nYs3yVWm|)UWQiOnVLO+QdC#f}n`)J=H z4J5t=l9f&kX$)5~Wut@C?jQ{$i66x4QT}X0NiYYMhwd4+iKHw671QWEwvnWq0)TlQ z+X@2INDJ6_0b33NR4>(RoocqRBme_od^LLt1gIu;Y`l&w2LY-{8{43bZ6*nup=dkX zpj`@3O?udP4_l7G2<8|DbIc{-j(XV~!w@MzHHqTjQ5-o2Bax$!$Wf8xR*+AP6FC+T zpqiv{xM`fh5TFK@%TdVXs6co42N>mY#xsB$9Q+1{2LZ}P5l6X5>OmAx&QUIx0jfF5 z)iOXmN4Z`KP`&hVM)YyUz|;x%7{CkvZ7sx32=^8Lyp!Hch&6B{0W|b30{Si7IRNLU zw+&E3b(_f6O=M4iZ~yqE7K5|lS_T-UDPSuVu&Fpqe<+}cqgBK)fWTkD?zSsNJVQY3 zB}es=RAnZihOxE7*wluE{y_HxL!ib zKr2h3l_de78v-Nr-b6wzO!_jx-hUcMAp_{B0hFp-=?{E)pbfoCfttH2Dr2WOJe)~T z8V`=gXoyoLjaObIWiMBQ3Px+!kEKNDKWqw;vZV(n2i3 zjU_~kw2)13vk4Jgk5soM1h<3`G15W@SjG!Mza>GawBj~4++*DG; z2>N$O?j2IZ2>P`ox0Vz!g8mnh`-K!Sf_@;I8^{(hf_@U4o5U7Dx2Hy$&*tW{MU0SM z!{*koMT~&m$>w&lMT~G9#^Hu>M2ujY#Nj4!M2t{+lf%8q5kX(eY6{HsiVd*Spt}2w z;=j>BjD^yV3i?qY14zd3WQ@s3!PHVPO$Os3hCh^Hlwe9F*iZ(e62mKH7>_Zf$1;p& z3~!cUM6mD(7PH%Y7M?Eyyk>DRUbg_6{(r83YE)K`zaHfq+9M6;iUgG#m8K51< z+hu^m1b&!c+DIVq1Q{TY!1H8)N&>Hx0p1h%dl?{_#G^^3(R30|mjND-_yZZ>4N1Hq zxs2I1lKe(el>zjUc&|*8Fg6~>X7-Z8##3Z~RJKwoTk@iO@0a`xz8h^1qEI6_u95r? zT8GOKL@xR~2WqZ<2@`C_nBNY>+Vk03yHKErdjARr*uSW<_O-eDPQcMT|ia{?>20$-R z2vAL)V1g&o@JKbGS1cnu{=szrNULUwK`&uOyu8TLyC^NADF(f!83DA0rBK6CfdQ0a z(2JY_(2JZAQA2T^P-&q}HKA8M46zhIuX;v^EyZ<8rIk0upxpq*TneDw0LEMjpxpq* zTneDwfDv;O2-5^M`q&e;p{U0(z2n#<=y&aVd5iAHn)?7FuTkaK(y|BUR4^p*S*X|weBwYOKKm4F z6f}J2Rh%i`2@13goDIwZ&7URom#N3Du!L7+fJj^zDXqt-@l@i%N-3b8#d|IoaPs9) zn%^k@H>$yyR6nZKj~X$6WQ?DTF&QbCZVG13U?dRy1cJ%PBlvkTKqbMilmXro{P$7- zp7DaG{O@R2Y@8ZjA7^YIX9nDiAi{LC8KwS=251PSK0j=7+JF zy`-@DDKbDRTO*Y%nJtXF;E~bC;?O#bQ9vU;{uZlXBnBGsakp6G`>b~T-iQg2gQ&66 zCmGNh1<(fu41hikU;y-Hp8?QYc?Ljl)ENN1>t+D-uA2eSyKV+R@46uX^9-1b_(Wc; z$~-UPz0xX+1nWAAqZGwq?t|+&TJ_TH4=i_q5%FQY*of1&F)kjX>ra8zYsazEgxyj$ zdr|dX)C>afL?4*=caSeuz_kr<@zK3l14|j85g*lyHSg}%`z07YNdpmV6K9hy?1Snw zkR=RcNjBvakj)Zi%K*{1FdAnvp5VeKQUE3<&?|lX53RH3HHG$cd!~b4*KpP_;GNK|mwEO%Q9|++#0r zXYIWW=IzLFWX}6AOL$mjnwczNrVJ2)3nQe{q()kS3oE3+zObg0YU=2o-+R-F) z@1IVNN+%_63YIcpfZ|IG@c`ld1z3aPOAE1vvRcBCFOjDGo~kle9h>Rp;F;B-%5~CA zs#~-6O3}m7RbV8QgmxvtJmGjxjCxNHv!^?X<40wHi#UE!1}MYv zG8v#8$IE4a794Mp0s3*gUj~RJ@K~8$Up9ef%K#+=ULpfD5O{+O@QuK~$pB#_9wxKN zOC|AC8Q>0y-;n`oNxW7D_(I}eWPm_69w@UfOk(3nGC)2X&zAve*m#W$(8da z9>!trK9e|jk_>Q@gWr?_@H!5xSo$swu1k0U2Q>8U8`Quv5199UL!w5p{U zdrAHcfxY(B0bryV({7el)mvljHXI^j{%JDt5t+CNd`EDj2Of_2&JwD;oIR+&VWIwi zht~#g>Q6clBm@QD^e2+>dj#Y6qtf3oDy?Pd>m9slGl(65Mp9RcN6|1e7^TbvOIb)5 K9fXbm literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/emif.h.BA5BDF1658E44C3E.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/emif.h.BA5BDF1658E44C3E.idx new file mode 100644 index 0000000000000000000000000000000000000000..40bbeb4e6ea8d83ed1c5884e5430b360bdfc392e GIT binary patch literal 16942 zcmY*g30O_d8$b8lIp>~p@2#svs}|8tDk&uUPJ|F&eA%-`wk&_zR0`Q6R7zCZP>EzI z$xz#*Q@`iD9D_Pw-p4WWxf0 zVVDNQQ6I0*-}rfgeN1eV_(wAm?-!9 z=kuluH(Ui12h0gJziQU+^$=^fm+_9eyIhjDKYcxH%m`PJ{to{F!pyVq`i=Pl*VAeR z!N;}?wfCIpgqzc`*b3H~luACIB^59Frc(=ZDkFE%PBFG88b0EwFOzQP> zr1RnF>RY|T4@~f0;$bH7cKRo8srNP;;i>`DaQ}*BC-;v?E-2SJ?xsJuf6X%c{SRlD zU7oTt{>Pmg9~z&GuCAN5=;68Wtg*9`0{pQ#r$VQBj{9sm`80lepqEhhmG6o?QrBq7 ziO9n2&+*sas_VA6t8B_}f91P8bh7cjWjpGv^1mOdx9vOL-Q`h`dujD@_p#c+*Popk zVO=Y+3%Z{rDBbQukCuI|aNbZ^sk-l_(x(gG?0U`2`dAWgesr$>-wL1U|D*=~oty>I6K%Ga!q>L*;Ww%bpcZuu5z_><#<-Mn8#u- zAH2MzeeiSLUDrhpb)V~l>Mma2(QW9Bd_rx7)$-I`f!jKxlX^edm^a{p-?PDe=V+`? z6KfSM^3?EIXYp`Si{JOMh~Jh|8rC}Qd#5eCUVT0CrQ6t+DY}=;9k=!L&dQrVWkD7G zYOl}Oxsh+N;b~5i7oNsOf3J{H8sVclDk!^BZT~MHJq&l;u9CXi4ai(-|J!2DMBRA@ z&UkIzlQZf>;Z|wjpD70?ZcZuht!6)dNBCQxTBpz-Q)hlzx2dvn%I!hfd(XVOHvVeN zuU!}X8eha68$R&i`NZ`b`|CR&wK(O{`^U*N?-Ad1kM&7=)?*)eNN?a+eLss|AcgkH}G1^t{xzV1jbE8Je{ueT%y?Lv?VeEl!rhd&D&f%Hgk2Mw@v{4;W zbV6Sz@}XYNd8%s$+I*VhJ7mbx%fW8_^I37M*SUOFtMc9yz4`%w`h6hp0WGso33rP=7itXu^zv?iGY9ZjnID= z*sx0V_s6od9cg?2S@tf?AwWlzFKUaZ2sj7M*rOTa?Q#!hXn6C|5*@gCb{O) z7fb%V`u^sUMK0Gg7hmg^D778r8|9Y2wMF1GieuEpAvE z(5Y>cU0ZZQSETPGIJ9u0?u#?)D)%~8deIQ6MaALTcd3`>v2rm;(pbWa-5!R zcRXcqrf|!mrKy*mS-&!RImMyzzwqfZe?4E96Y*){+3XYU7A5U&`m%zhiw8O0JX@ub z;!^c#*pry&AGcl9sT!K1tsQDz+E!{Y#eL7yPbE%c1%KSPHB7W`8ai&ivD1aQYZ`VY z?%iW?Z({nZr59%m_ls(eZ5H))NsB6T%#In}cD(-Sh|xc`xn-W6;TUzdzp=xZkww8~ zuUgMHI8CIYT6_(HN1vINGH1f=`{s)q_nSulz#j!vuXy3#Su``M{^9*Ask3*NM5F|r zx$gD2B_@8yXU&c2+5csT+f75CuU=X6%cr^fp-!EKU-2)nZQ{3EhCN$5bf<35&DQZ= zLw(lm4FGME?=+c=+VH@1WNU#zl=nGzpUY;Y&R;A%eRcCGb9#G$VyS6^wad1Y`i^YhD(s&*|uh8Jy}w8AaZ zQ9Djhyfd}I>Fmw=g0QK<8GDS4=N~I}Ke%`BJ=Gh-dPa12x$sN(t@_b%c6GMb)3@iV zdcU!C@jkkA@EyBDdz<`H+eQR88oWUZsm#}#g(MtW@0oU_%bZPBzkwQpzC{_K+eyW-Z@ zwi?wi{WQvN`QSo-Q``L9o~7%a-kEdMcFK^%sr5Fl4f(6Iath~ZZz;3d6m+|(YRbk& zqsLiUQ+78~Q8n*qidmWhDhA zXOD+{9+KDm?)lmqtGOXz9LoCR z8Q2t`KCyYlqMxZbdCz~U_AqOW`Vd>L*^uge$^PHdr?0!!+Y8MluJ^^sHL4Sa?_F5F z1;j4{EyIUQZ&fY*-=e`qN2LSjg??M>?>46IDx=zQ-9x+gHlJ-hz4DmN>hY5vnkFV2 zl;Xoj^~F5HUl$yhe!*j4=v+&cc@d|({qc?adEfA~#f}C0-JVSHI5Hr8em=+8kaJ+KI(T^S|}lG>n`k$>m5mcJE;5D z6yeSpKeweG8{4g~L;tYB87WmMIdcc)OelOAr}up3jI^p1Rc61o`}@tDJ?wq9UdO-L z+dI@c_PL~$J$`WKMogd6w>{GyYB?9LsDHopy6BqU@`vC3pKL1qurT4Xwlf&_W|h(8 z39bG1R{hsndFkbnccsJA<~_cqvRP4PN2%k7!y-MICJJI;W2AByJW@0jJ>Jmn6^ zzLc|e0M$4CTSwuVyq?CFlRGzQ9J&_X=fcjngJuzbPOi-l>^JzMb^TqcuCVt`t?eau zE5-k9|JhzQd;D0>uk+5U=YPmh&!;lKyt@^6{q%Sz>HCmgox{RS_qkx}x2#@xTLr^@ z&2v2KIok`9VgUjSOA^G;SPZR?Bu1+VdfyP75eSk5M2~--CO+6b6G*VdkoiM^{}AXP ziP0D~0>dEh&gylY*Z)%y$*?t$mxSXYxW2O8Rh|PJ`#XO0*1*-XmgquYjf1WlY>$Qw;Ic^*^pQv02PqP zN=S6$h{u;ZE+4km)m#lQb1CL8Z(@iT3lWW!QRHb0iKTaU&#Q&8Gx@Y#TFt)5yRTW9+2ZLAlXy0Q&~i zk_4>8XiZ>)jK0#ZS&`TH-Cl;RfJUQn5Dgp2N@#S`6UoZX!r~jSU>eK2h!{)%MUkSh~K@TKhe%-?BJ?3lbC?INsQ#HP7FUGGc}d`xlyQ7l3wwF_O^a3Bh8vi5oR`^)pH6!7$fB<|Q0l!kNCX5;7-j zVTq+Pr_E29_1;~AEr7&20bVCyTFFXCbYWZR9UF4|cz*G0RqTSi&sDfq6>gX$U?u8v z!jFO0_TlXw5^OWH_5{bDz=2^Uv^I*h)`mIC;%CJFBgM8sUZn`D6fwqFiP5^WG3xS_ zYk3+s@w=Wg zz3#WJDfVcl+j3Rxn!Go~xJohnIIKjy`8~3`(@vG>A@5S_Za1 zt@Sfbi= zhIzxP191?DGv9@kuxj_^>yUy`FTY%V0$3P3G%Cai=+SI(IvPPjZ^-1?Ge z88#0R-wVKdxMQ&r5>E=aEo-CZkBaCrgOd_$5oF%Q@w+(lNmvP)!`WG;TlT**hs;Ay z$*}p5_gw(K3z%iVO2~^wUSfK1(D|r)_AxSSEoA24AO|-<5;Dhg^YPyQQtJOB6B*)4 zNIZdq6L2N45)#L8D!p>ZHC7C*1cN^^LNaRRmBqJ z@_E75pQj%}+o8Wx_QiWSINMYu{4teKUF6_9DRpmxrJL@Bmc{+Z7M>^xv* z1S{bh=!>d#6;{-LNi|E6VnK3h2Z?pSeV>)k_1Ge6)`=Gp9mth-VU-sc(AM|*v zgq@B-o9g@f{Y>qPtW#y!KalxS0A321CCEz1oWgzVjXQKU4)0%@Da8)UYp*4+T7s#a zl^Cr>4o0;%EU#*sot|+?itU6pAJNz&8lF1j60TJf#FXaD*mHNyi)<-&KyI{?z&Z)0 zp{&H{9?}7by4l+KXyxsbIZ|wwoZ3QTEi^MXSP89KAnM2rvG|SMqARM{Mfu1V;wpu3 z!LkyKd_`uKH0DI>6)6@bHy9_z;>1idSqTmHK|a^Tx&BJ~v87if*cRBK%Q$`+t}j-? zLE`p9@2NAU{r9&rPl`p!O(sxS0>vC=Sc%d45+~HgGbify&uN-|U5f31CZk1Iw1`@9%XPwgfT*a1a33Eh}N=)46qicuB%NDHb6&ctnUDf&Q75O8(hl z&Pko-HwO1**fQA2ARGk2?SYlBku$hPTI?>?IM%wXM25|R#Bu>BhX+koLgG~Jp!sG_ zcGHfkmnBkczr6Aa603l-os}4^A?%NOGpyfWox<^(AF5&*^4?V9>Xq<_%}Ugp%gc0! z|Jz(%A;A{Hnwtf9vw%5Bu@cril=VTOKl(lE-b?R^DwZd=)`+V#!V?!Oku{GRvr?b= zH>y>!Tsf-_SE++r2P+XPuM-Gnm`!>r!M4IW-{SaN*f3VYI!Cj0s+W)pPIN!S@cbZe zKaTH*+X5>gkDFk+w`|P%K5wg$Vn^kJQb=Ki6l0K;7_BFEM1#_Eif7D&B_1y&*hXmb z6po+5Wk~W&YMZsFfA(;%m16tkCJTgEfsm=2l^AWPYL85g?5;B~Zz*;}ZnJ^H8YpHavJ#`UMFWw|NpIBJUu!!5m0>>6W;PD8 zp&w@@v^kdZ@VdX<#^``A(aD zr=3_F!x&({*lxd=Il{3&bRiUoyDov8Cgp}3^c7$XHj>jL3$G-os-1Drg!ZxO+M?xGBLQT-8h|EFyGib-`8)IVC>>KgFE=+27l#x9)s0SR{ij38D;x6yM_KqqJ8|JK|)3(Yz{2Ac`odh3^u-uQZJ+U#>%JxWmK0jU*V%;Spi<%VT;NI zJ<0|BkP)xh$3gk?i#m%L%`F_TpnpOObbDfO;I%<5F}DWq<}8G%z-} zizEXy;-C?iBDcu^O*m-6rRZ?Y0IzZI8keG5Gy}ZB!5dtPF5e8$iK}(ux?T5TxX1K3 zBJAC@1Hnr{j}&3=t}6qaidqFiLo^iuT%Dj)NF#tTS}Gh?DjdfH8il%z!k%3h1b8>s z*$a%jF7EKyrF9+{b{)##WliTUFz&j_!Dxf}H=u`N5lpo~1PCH%1TfVG5$ZvNGQ%v0 zuvTI?1QA1cKrmq)O!Vggy9mo&gdGovCJdqpQ*s zEJ_Gl9#Bi@)e<4OxW>&PQs{@Fz-4) z!swS?9BI-O8)FV#BuF5o2w$TmsHOs^$;LunB|hz2#_-za>*eGU>H|O ziz}oH0vJXGsaHXobRAZh1w?Apk@`x2V;wn^2Q-kD4Wu0p=pgkvNRzJPJv;^KM~ixO z9TDL**C1PD+I0zr;Rd5hk$G1v0)||4+eJOQ0y50*A_6}|QUowfkEB2(MJoZOk(3n= zU>zp{n9e0o#tD=~*QpksGjs|mJ+t;H&_qdjz(-2uBh_6A=<|_s z-~pc~l}}2HPgI{z3I@~kRtmIIG%6woOj{`{9?(XawNWkzV4A***55_ZBhLJ>DB+<4!AeYw7rF)`tHdCa41_d;Y0H(+zTJI5U zf-XP|qlN}GG>rg;QA1nQ(6&6Fg*IuSt=#??7u)iHSg~rXSgY%b18+5Yabgn$Fg8-ek`!?_1TZ$PidCTWQ=~{NDH3->09piaBj-ZT+&;F=11l+*Y-0d5o|I?T-i)Hr5a&YBTnQ9@h8iyB z%xTbm2X}fl){HhwrpXsc&5NWyY6$8+G{Oa%Iqo{wxy5F6MOM(r7HW$D&jh=m5pZfi zg2v)*&bH8mHD#@ea1^A5I2)lx8sws(h6_YOsy{pcJQDPH zq&NVe9T7H^3qf;b7^*+j-JjA$%M`mu zP&Z0w$+ZI>yIX|aTZE?F?SfF)ug0a$#MIOB>p0Oo?DI;Nn%C% zJhyyRB)KZm=egylBFR&cKF=+8h$I~%ee@xiT9PP95~a^`sdp*KT}q$lQr}UMca%QQ zm4(xia9W?|xe{ne0~n)C?Nq>`E{VU>6OqMeL&C0qmmT0qmmT0qmkd zz*#bWl)&k_D;&;X!XcO#k2I*MaE!Qj6i$^xQ`TV9be3X~}^$|&-A_V09`IQx`z$o)0bhl> zUzHf>Bi+40dMlim)?-2e2~(`C_J8c4qJ#JUcUxgJ)V=1!Pq~n+J3fHl2hca;J<9 zcJ3$vaPA;LJ}~CH$$ki6im;Oj4XPY~lL-M#k$Td)p6t&9I!Mb7(hj*~rU)Ac;Q{RY zLjYqVT4WV1vPVvvDZ)ldcmO*?5x^A55~*g1w2)h8im+2w34p;B1TaM^MK+ZpN96dK zB5bsU2e7jo0Zfqus$T--gmwa^2s`bS066Utz!b@#`eslAct9a#UP$#rn+IcqT^LFL zTo?#oY&@ha9#XalKyRaP)^qQnidp}Oa`{A!K|4{b_W5zW3^hHV%i2pB?p1_m(9OWk6+>i z@5mEJTE>yis9vVu6{KYa>5NuSYs=`?*QcUZ!LhnP8eAZ|qN9f&smz#nm|P8;7%QM+ z1-e{2F!bmPHQY-tr@8ncbA( zZp8#r9k%Yuw>5heW8P@Ah8Tcz=gJ@~PUT|;BT)n6|sNtTJIZb+NV_u!j z-YsxjxD5JT1`|02JP20-ohs0^PoUTsoIu=Tv!YwUlyR`)$TIk~-`=W-sau5%buqQr zm}isSE_eXDT_8Yj@7z-}G9tFZ-UU+Tfr{1P=$?4|+O>1Ak8bZjKsVqqcPRrOQ*pp!pDydWfhu($v*nay)m> zX%Ez7kp@|cNuO@yHDL3l!E((-(&(aM0{c}|FWk0oP^7lJu`r~FtT6x^>{9|@Y>x-9 zaXBRbhT(Vs8)Q=gU`&k%umLh900zi-02|9v0$}Kh2e9EDCBT#k_wWEVs-gtIs0t5Y zV;1?E(?OwFh+7n%^XG8&*5FdGUQ(40IkVfb)&2#||2X z9)TvJ1XPs5DWmiZsNr%lxN3b>V-nVlYC8%wCj`_9MH!T-0X1BD23H1UX26l+(lIy< zGXSSadN6@jxoi!E)ofBTTM;)<6Q|Ft7UdHH| zu;&c4KQRD%&OrMUQoxRL2_alVvQE3m7Ajlzk-CHF0FdzIjiNTBeeWCP1he zAT;DrJAkYMbRA9@MjRoFBltieAuCh@l1Nz+$!9zzWlt3V%6@@u=2Bj``gY~H2Y`<& zGhv%=h;(m=n5Sp<#{jQH>aRq`2tZLLXoSm#;Z*xVU02jTZ;%`55bAUY`FH6*LW4iT zt`h-@)j%U$q6}vQ-I$<;%ZuSOD4YW|TpA3g(b{3XqIkOAW%!jU1U)Jg5k~Y}2d>CkiOM+1tslq`O-W^>m&}9W0NuXdl49CQ%SlX#k+6Thn1JU)Gi=JI!2f3UWt_(xHL~34A>>pYEhHqcr?o|wpWRk|2 zq$9_~(BmaM;BzT63M0irNwLrjISbeTq2zH1DxfA&q@Jia1xA%DeQ$Yjc7-LQ zDHeiarNG$-A^4yKd=gThgsNQqaBKT2q`oQv2LU*!6gbNSAX5n_1)x+3_zl2sC7=^f zoq%6UECFH(F|XQqf{G{ji~<4_C^3o%sz`~^M1UqGMj#0SmEv_lBnVOh&XM4p5|Bbt zDI~wzY7$f{F`kpub0vnq2>2@n@B&02KnaKyfmkIVP6XnVfU6>KRS9@10#B8IXCm-S z3Fr`k4kaLo0!d0y!DI>~D*<;Ya90VqM}d1vz&i@OQv$+i5Ki;IO9BlNlz@C1Y>>)juPLbQBAa&6C=|FxxonWiC9o-|k8tn^ z*G9KK6orERfJR9dxbEvohkDW#QIU6r z=DBn>PF2_IcK=~x)tR&v<^oKZCKH2D83rgJ>`D}=Kj~BMKgo|8+z8Dd2Rg?=*EI~K z!$I?04jgA?%sI_{=beq-!Pch>sC1?DB=)Hq)rb5VG{U9FaVjsDJF+*grIB++U~N7`ooEPr9F~tkS)(TVn5J;WMZ+<0J3*{_XdHWC3Oq}mIlf4iTmGgW!C%IjR1|2 zP0UzOm6?@QmG#QX%6wIds`XmbZP%jVbaI{EEa!toI-NxGWIR|Tqo{h(%u1!dZSqqp zMUBbeYMh9ollx?{I3nr)o(<-MyXb0=B~hA1i`#^LAB;xxB+H`dHKsK#zI=-ArlaLJ zITA>N(U8#UJD~@T(}&h{ zFd|$fd;6r(MRuBU4-0^08l7gl9-=Wz=IL~l&qqEfMx*ct zxQ|HRgg7|uG#XzUkbF8%lJ6ez@p9k&5h8RC|6VP1@7RzjJ|DYsx7djYHC;6Uib1QM6Z#=@l zC1v9=Bp}bQ^&orE#^@%APSY_=C7Y!$g}I*Iq>I5=^u1E%Q#a|M&9}3-Yb*|g;3k2fh!E~4yVFcU|j zb5CA-7q+u&{n2T0_&#DV#_ z3`!)l#9UU7`|Zo##buA2zkpu{fAeK>0JO;dRaCIb>D~ZeDfypqb3LElNwAnF&jyRz zBkjak5=X{#qB5u)9BC2yMpxw*60sP@OVtM&Tc9x(pjTF4Lyh@Y+1$`@1ag+ht@kzA zmM0bt3)&oNyYi~3)wavCQ?W4Y|j(^(TbUGDj4PuO7O>s2~IrKo|y zc8Nt$l+}1N1YKciyNj{W_|K)G;*&|RIsXJZHhXPfmNGRH-9Kx)c2a_A14D(?bN-n=6bMtV#9KnKHK6X;8wLitp^D5}L zNERJCWI`N|>Bb96ptDLAJ={(+R<8nj1=99(h>fDFN7`^?pEi8}UU(DckXdn@V&n1Q zW>oc$iw5~y{RoL>cUPm2>CLSVrR7FxO&>fMv9pjkR7mVBB*sFvy+LZgDGNFpZ$O?! zd4kJg3j68#a`xmYBlmtsFJZgOpFE-brFSijyX6>%gmzU@!c(D|wbj)~wncY&^=#X2 zd0<1yK~3hGixJWg>yS>G--mdYnes_=l`e!v6~TFF1}%1Y-LizjRQ{FFeoj4UrW8w; zk+nAn-@9~^%Me}k{quqeO*YuGWC&L{bd}=7$+#JmqKvNTe5p2D(7B`w3i{n}?`yx? zJUg$p`n9-Lj`()I_q80=9*3ki;z#<$hf`5-Dg|+l6`bROIByl4w*_(DDLC&6;+!Zr zCq;0`Qr!65t56*NqYz%K;>AVr+TD-6GUu^9Ne;8y=>j^;3te$QSG>^24(MYq^jin? zTQBrG2lP8H^oaxdB+v(C1Dd4;XIy6KG*t4qx+Vw)|v_h0{0 z{;(uFwc|>Efvo?(eOKZ^^k4r|`9Loo>$UD;FkiH z?J6CTU*8GKj8%(jqlS$Yn9LsTXu_t*_&KKlOvCrw#R1&g031CuqIhnfweFWKwuKlC z1H@XDI6F6U?GOExOQbfQ4*#sD_vwh749GCdU>MHTCivLZU~bc!+wLq$Mi&A&w+!tv zn^j-lTd$3;Fsp;EKIDoOC3*^Sip^QI<$O*=w3SZ&#GZ#QD&z1QN+l~B5$7@cl}{En zjqxM?fkOeD32NhHfOoOc5WY1E4Gp-ofjb-QYlh6e700DFpsTk!Cr~Hnz(+(K@o#Dy zaj=W&crZ^FkI{^M*+2nT)9ILPKLk)=vi6Ln5#)C)`Sdi^V$3cmFP3o8a;5%Sk&=Ez zFK*>mq(Uj6hLhc);`bG)urW0n799LxY*jk+D&w*+8dB+377+&+n=%=2!9CP=`RYDS zhS*mb`?4ZG;+9EK;rp4w-5FI^=a!@C^>kHUF77GW))Ns1al}Ek`b=>)o?Z=bhT&@B zvHYHkeSyY|DsaW(^m?+zfDI={i7s$` zS}0mDub;niqEf|bM9k*{~?EwLa=Gx21S8nH+1>Szrca1yOZ3c*&-~hQq6(u zNb%;G-STO;7&tqTVS^S&o3GMi8EAGWxN#QB7SsH*kbqwB4a(ZP5=ruVEv}u82RFsW z<>LEFu%KYdot+hgCKsrJ@a=AI6@KWXR0x>bH@1?=&EmFr2T?3K8wsqzWIB1gn=Uib z+wavX{tuoDa0`&ZiJks{Pa-_sXU9}7@Eo_A-RF9 zy=*bs9&OlK$RS{MKHoO|5Qw6z+yWbhc5=-U40U8NYR;XU2i2{5WSO~IM<3C!0`F;9 zPNY8DX28`pa)cic^DoAVGf$(U|~R58o{Sfbg2My=okav zq4V<*D5~izgzwSs6~gss^$Ot{TCbcfs+g%CH2^0h>03j4UK`^1_2|{t@P7sI=(g291$jOCO z)HnODHfkHf?&iQEH-Rq>(tZ%i6~7D8RO@ zJJ8O8-DAKyP1PxJ+fu!G-fMI^mlr*1woCV+3Pmxm(mHCmr>*K4*mrZ|ZjO{0HrGB> zGH7koHYv0VhQl5tZkOzOs71FbRF^MQC*;c}i)Ph-v(Wn|Ad7~Uq-QvxX=y<6VN zM`&-pos!Rv%CWw@(beQiT~^kAW5&0$92FKcpv>NPW9KEKV6U==WkZueePKQ-Vc*K9 z(Xa;G+es>A#rp8mwr1-OJbq^5sIVQx4eV1! zp5SedklBCY$m1MQ2cKLlNUGSc%2$GnS;T}4FG|ISQt_f3`%sR(C~tizZ@nn*d?@d{ zC?`IY6E}){L};KGqlphlPb;xyFXserj$FI=Wq9D60qDsE zWk&@YPhISg`j9SeqfwHjP+d@ia4P3`vikQF z|B^Xw6f@nAVpH)}DBbQUP7kXs?oja{;*JyvN9BXc!O_uCxpGi`dr*F7xfXniZ^0)x z7kr9$!FAjV?vi|O*L}4niGP{@>WxxUn@@O)W)9RHv;Q{Q(JGdoL|OSIgMpnC&Fx21 z&>PhsPGM)o)2PxH9BgC-fM-3Mb$%6WN?*Azph@w>$4=capW)LfXfgSCYTb~jRU(za2NX5_nbbqn}x){spr*{3a)u2aPx4(1l5Z=Ox130^8==8IQ6j*=U zVmO0n23DGDic|JWo*W-Vo|v84)^{R$IgW^hK#p%rpx5Aa0}6zRLCBAwYwywt>eol` zaBevmk9Su;c`;88h1!p~I);Y%>s6HoS7gtK1NJI`t^pRohi^iLAUUE9CJOi-grU=u zhJ$5>0VqkQ4d=-nq%rO_ht2z2Q+$F=AFVR^k4_@UCM|$I0C}B!n~}{jsTZJetG|8ZAbwBSA6G0TqbP^k1WCFzo}&@gbig@~H#)6p>Fu$hBU}$t~u%k*dFwtSb9cQITlU>uM!{ z7_&b%V*EPxBX&{9>AdRWIPW zYKwtIL|gt9kwrF2&2BFd@r8P1*jAIdirK+d`w`-RdGtO!rtz;hV87ykx$u6)0rU02 zuQ*`rv%Ogps&)!HAm&5t`L{rJ!J$1+G2^^l?hP5-R9N`3T@6zsjyG=RBOiFX%H28P zW&!PX)IwE_Ci=@j^_PLF_EDt!`7GE}i7ZkqMSn=gWU<5y8ajE$En7Y9u0AdMf$Wh& zea3G_U9A7IZZkiBg&?6KQZWnL4H@EGmnhr6q~~wjlb$V`vhl88*^&*qoIUeYwHjP+ zoMYg2^;n{Pmn93!Iq}}U;BQyAq-}oFa1&_PP50pdFF0^}A1qc}43~7qoIwRA*w3sp7+JI=lsHuAU*(S(h|~m)+(hr4D|Taiv@C zxNIGNnJYg1qs!GcZ;&l{u`iHmPwUskwBJkA$-}_9JzlMgB-tJAs2|C!RPEFs*{bxH zS?Nz`R=T|*_+#0Xs)MkASt;e1Tat3qQrAfRWeNJr67-iP=n5ZYhIk%BP<7}RwgZI& zaY=$-CxZogsG^q=?B)fKzDp#!|AL%RI!|cflzxeC-*$B}hbydfvV>5R&v^u9Whtfq zIsykjvd6Y&e#!gh1z2CQrrMJ6C2uIV?WOe4O=NXGoy}9OiY+lY-EH~Xt~DHQ+ZSRC zM}x=yW#0d;p?G}ssw=5}1#jV9<9sKwmM%dCG~&qE3)W`H-&;1MGn9)g$5teqwmY>( zzwxgIoxe z!fw4CrIi^(+4Oqx0QD$zL9*VhsCO6$CJJ7dloUR8Z;?>yJDVqt3x)09bNISKyXDaJ z)yi8ZejXyZaAsn=alR41m?y4q?eh9#Z(r)P?*@MovE%Nskp$fs`0h>i_PL5p^|n2P zO$5I-0n3*un!7C2I=&2Pk-GiO$xNOw_^vQk5ecCoT~Q9)sBp|vFVDb7IQ{%I!hmNs zYVEO^Ugv&OB6t@?_6VY+lngsK+KiMkkD^a%kCn6|&>eI1o+aaC2zX2S)QU;Na>gP6 z&z2a{mvkiSD}*b(h@R31&Zbw)iHrUYZOPA)h2@Z!?s?Z;_iX3MrnhDqZot>VH_5{7 zbD5&Sj@-;qjc}~(yTXsLc`xojd1dd(E4xm9s^8?EqoMS>>y1jzR^$*m+t`CW_vxLs zrr*e9+o$-R-2}kQU=iI8$d((`STvBvMmu0@-O1mis_wovH3h4E#WZ9_fIc==2(us_ z)}$0IXFMj$JYhju@U6jOI>SKSG8m6sJ5|FxN9=R5c!JMestuPxp@k=Raed*W(csa+ zGmnX1$F40_6syd~%0|0!+d_fr#qEj2?O;B7VC#h}PR=U+cGV#_+6r51Q{!Z?jRrMN zAm%Ks%wSHSou0>-WZ=}mLW8k*Q|qiwNRA<8^zp%5&OzbcU|fiaOU35*1qcG+eP+po zUYksKZD@p2S`0*p8aNmreU*u>qH&^ZRxpHAdJT3vQMxFJ3=Ea!9B6ZhF?DUc?Xt_0 z20R^=WB?Ud*d@uL9SMRlOXlfxwArC6_Rows!$JQ;u0gBvusfSZ(-hDVsFsg|&CiI% zqR*BX17?FeNy?`p{1m2{0CByzCnT*JwJ?mQN2o21rw6Ppj;F`3Esm#$vn`INN4G7G zX9T-d5M5y}i^rm6A2s}Kkc)WxTtHyl4UWg>7~NVN+-DfqqC9;>uQH&?HsK*9yht-v zImE9;uxVQs?AW(70;?$tECOy0g-V!$M;`6SxLyj!`4rxUDZI_6@GeZ@T|R}AFolyG z3c@9an*tk`E00H4Fy1g5@iVXi!F)G3qMu`aSU+lSXj*WVv*N1Go_i{@0(K}7UG_Qm{h>ZpK3jF$KcS7)L3RhVixxImFC@_2%o47%20gIf3%MR7Vs zo>LU36Mj)qj86WeisE#_?<%yhu)&eH@o`L#cmD8S(KwmhEN-`>*jS;|9lF)YZPMxW zb(U;NSF}Q@yVs=2H&QWlWd}E~+^wD54sKfKmQ$QZw?h6Kcz6{CXY}LJt;~`4$y6B4 zZL}@7)icmsMD)0$D0Pw8M$ae#i(W_m~%64ycovLqst*8_Pc-n?NG%4f}0d2TKsI<|p-KL;;LS~DXrq|2y zx=Ze+Y*bX48XA}Zw%Nh)N3c=J5mKWLSoiTbS1fHbkVcAH+NkJkQxN4TdW#!8{ZduT zNB_PeD>-*HA$?U&lWg+87mR{aDG};Yqp-qL4cUMAGzz7Sw*NMJlX|9v4q^_Sq#3<- zO}&Lqwu){UMJspXCAq7E9SDKY;BaOUk1j)RE=#*>xXF7>x8@-&DBc2ZV5WaOMMyd~SQH{VXlCvTZlFzKYO zBbPSX&Rgm=k7q;~jh%k4ZObTWIGtRlH(=Bk3ek=>BFu3BLI2M(1q9V^BX?EMT%cze z*57<<27!j&9KQD**K8(yJnV>7S#IC5Dsh8KrEXgstdu@8TawnCuok+QEHN&h+^MWI zt&-W!be%PuZcUj&t!Nk0tgP_j>0$CmZ{sf6fPu1s?X^^m%+}Q!!gf$R!QybP7h#_~K2rAYT_F>^1h_zk_QTg4@?ORbUxSJbuN|Fb)D%)k!w?ozS-@lVG z>ox8DyT5RH)X`;$QK*VnoL&;&CI11TGEw*HwSCzzRzu($#!|Ex{F%sBp*}sxtUV~u zpoW)^6@mjOZKwOq?|to8>!1788iWTBFVMfiwQIlb@}j4 zvYZv=q#SIO^0T%|IoK-e^Mb8%s1KVEZy%dyANyZv_HBA|8>M%%WHi8sC;0d>51D5p z^8IwY7%)5ZB!t;&e~EbZc=}KrvDZF3Yc*(gZ+Zi7Q1kh$H@npsu?|H{73vvGye%%^ zOU&W1gW@`-53V|a_pfB#o5DUkOGmJwPno5=dZy>J@=BEAoN%>OqTm|Q`x?`k5aOR=1keK>nv;Kd(gd{PLiqlDEgnF&tzU*CG_WD)+tj@!4na5IdV^_l1l^}MUTXr16&MiA;P2k=l z@RJFj6J?lzL-u@x-v)rqE1fGxUMm0ksLbRHhU3$|#4Qjx2z`WUK14^ZB{_6%tvIJD zp;l3bT49D-MHy=4GK5R4Y^y?qihV@85-hq(e1jPsl3ydmc`_q27p@WzpY}BdoP}Xp zi{VGy+Qs?(FL08Ivu#1YsN6RnOn591BzWZ;+~B4_H9Qzlc=kF2A8tHycG%iZ?Y#;( z*x$*OTJe9eb_ho`p3Nub`w)P9Wq1yDGO{CIU?hPf@Rp*|hu&FCS?^plI?Z;y-~Cvv zx4)2~UacRH9)6goq^Aifd`G~ZS7MZ!Xb&h~D6Th3!fbY*2ozbWGad(9H>xefN4?o; z)Otnu5VpE%nUWW_haB&oJ9rSW&8rz!(=j|%!B9Z2U>06_lFHemNznC}!X*X&x@SK= zr43NoFG8y?>VH`S#s!D&i&WY4;I9z0U*E$y$D%5 zxzk&4SM2alyy*kJas1iI8C7%Pw}}-SDXB}gvjopPX~C+tSUcUco3SZFT5WuMjnQs} z&pGZ`dX!w_qefaNd#0UdI_7cXxNGe_yq(TwVE8tk4*!g?@ z={#FpzzN_>I$GRv{0IEOeSH9oJgaz`TY-}3oOyQee;C}uRCdQgt_fQ@lM8ZkT8>BP zIUXvoxE)NQH{Z%{lt-@`b0w|Z6u1I~8V13=A!nWmb1aSs!fgm?NmN39pmU#Hfqz8h z=ykNWw`cPA-(-1>{uXur=+;{QY+v^FU;noMOSUZ8BJ}F%J;%espxw>VM(I5$gafig z`4O8$A0_QgG>8>rz$H$8f|IPW@ zX^|N%7mv{p{N}7Z`x8p&fJd_yHabQYC*5;+gvE=g&mJYSV3(Al? zRP2m6%@v&<+3-O4Cl!m+6HSM@q@ADtXZB$|gt zH)*Ct6+CimY2XdEAYTHE9eu57UEZs=#L&iT27Kp8w49c4E$ucP2+U{9*2}_U7s%qa zR$gF3NJzNG1rsYgcnxTss70B*12q`cXFKIuo1SX;7VvAM(K=pao{tJJglDYhVhC@22E|DsbJFXhuP*YKi4$kAF4M{Qu{ZR97r2L~^jJ%S}e z3>^R=Pv=u%kFzyfl2ryRHz5Z8A;rhKeisRZZzi!ikSHWF%YQ2j)s$)9ST; zqkh&nZMJ&&g-B%o4aq#8itt>1he2U7V6joQsUSmG9Y&0rZ3GB`qxTB)dPDV1PbPIt zGLJVy>MhB9yBSjNNanlEkUAlmCz~Plo@Bl+Olr5>nHQNBK5bz2gx2G$XULOO&LKWH z9jMxTI_OJc)T_H#S6|~!tJCZ@&(EmY7agw(WgNRyt3$nr`RSZiTP+~urE|^HcX@>3 zcJCuyi#&v=$r1HO^&;fXj2N(%<+ea#)X=g3u;~{(;npECjSX#r2~pZNj;&gctCM- zB?W!!2NY4h^Mvw34=88abDH&^@2CSrdCs=rFLJaOhBsE>ftA2UKMOns@*Uw-zKkQh zGVz|Zs3crmwz>_+A>J$AgmaY2)t!nE_Kn%!!Gw1H-wqSjTIOksd|kxaZ6VhqFFTsH z&Tba2OBUgGyhQr#j@i#H8o<(O8chB%TP3%{HLhf1Z=b6IP43qqJqur}eFzi5hCXYx z<7%sa+V0e}Nnh58%~NC!878|r(fjVnf2f_2ywx`ub#8_>p{(s}Y%gR{T4OKdl_K=RpO4yT<6=MeOQc(Nbyml6Yp7-r?N;w5_d9usdS>X~-VR9Bzmsfol(Vyn|Xq&DzHi^n02_Sh5Nj0@QQ0V=NE zm!yjmKzP5)eya?tM0{Zbm4tMBbe+u-xQR4CsG%5`bkV0=8^%kfXMEJB8-) zt#<97{d)6rv)<_R|8-D;$&qCK3(e&YDhF>5emf|i97M;JgOj%~-IXi9F#}=t%886h zG6NF2#)$$06bqFLBGQCiP5!&R^s*INIK{()SRZ?E?p zwfdVNcfzO_6TXOWS+4wTJ&w+QB;MnJFvPd@VA5UwX#Mq(48E#cI2w{ zO$He$b%*XQCu}R|!*M-6kp(&)K@lNl&!A+V9Y&Wk{_2C%bs}NlGJ#Zw7f(gdE-xe| zD{E8~7Y(40eFG@%+L&mg+7 z=GbPSxwRQ38QMm$RNM&Ssgn8j8)?pNgCfhS_q(Vbo3%t}5V+e1CmRPP%gu&jpe*Wf zKj3awEWkYh@B>U8?q`cy2cm6k+3*As} ziPS464G|{H?RjY!R3{?LvTCxaTRvW8Z_h%$eAu%rS>=)#YdA2fzYDj8>fnV&{8rWd zxY#JMg%WcVTI@jeJVSne!M-nc8*G(!-tN~vR?p8GD_l|+|G=V6Hk89#+;0+*W}-!; zI}0$?YJV}$gBxZF)<%UF5E8A4oVmB`Xb>94AF!PmRCU@mS~4o6X3mPJiC%vS1S3QqxX)){*yzKTh- z%G#C~Td1zopDfd`L0>_t(J=zzyK05I{ioGygOa_1Xv^v_n2pwHE#cN#dp6FBiMPt! z)>vChz~eP0?RX1gHvUT{?O4KWr9Mxdv||DDEPSmpX~)}SY%?u)y^i% z*Oe|o4wNJBMmJCFNKl9ez3q3k2K&=T=VE#W!Ktlbh}F3QZAqH_C4 zxG3{WrHODTS%`{q9qFQ?*2PJu;^d~XA~zK$Hx?D-=7nq^7VNGfWxd3M(5@VE}-7X+K=mqoXm!Qxn~`lwup zP9>L4r2w5cm!G&0KXEQUaRGjMUj;kSp%OJEp96wfabXrJ^Vo%XoQp|a`22BRYo4>c z&(1n?U2WV}c5B>LevR8-4^p)#^HJ__G_^mvThO)yf( z=E5UVPr2OamGcgUMLB<>P%$nz#AbMTnpml|@{t{sq>O|eo;v?`mKttxq%g5rFy zFj>79=B$cef3y(5)EUVS1z>&#u1=ip|Q z`Kz*Fc08i?W8IZ%cOUTC_4`o~3S0zIM8_PXUAZ_79kBB1W>PD;?nMh7xRmo&$#pHd zbH|;Z`hL@iZBo*ttzLuodzUSUaphp1HDlF>6bF!ER;(l3Ik;d&tsp&FgxWhQdr&L+s1=n1 z+D{&0-S%at*65>8*lzReyxIboEWH7hS0;Lx`b|yrR}4I0bz;ENjv!dm8CT2IYu_55 zdyfa~akAUePE6Y00EN!!Y}X>>n!l?Su#Xso&-xhH4H}2yVwzciNyr4)o4);_M&xS*3%HcFzr}XAWVWe$l#V z{piX-t2tqt9kVE{aYNy6DI7JpVqJljW9SU%DiNcM1(GcJr*G?SNoCRRIFI)CzBg8^{glJlvWE#35PF+ z8*5h5YKyz+f?Fd+21ki`ilFhOaLwmr7lS|1z_NUDm1xk%vz69M0Zgq|gvgt;r(Fq>=4iGNeMbC^X_* z;SUb;V8Q3@Uc?J`7EDeXYZbn;^8=2WsfY?e^_!cEtuDxW2d0Y)pL-uiaC7R|nRGFA z@&{2v+o!!R)lMVgVkup@@yJKG3Fb<{!hMal9#|-<5xaymx~$vVFHAyIoG=59+;zteWy&cet%)F>yuG zbXE(8x|6;)IZy1(ml}7D?%46>kx(pgg_c?)zE%IEhU#Uph9F#&Ap9*d3Y;+)0UM7R z-2v8&5Pm_jxvn@a^r$DF^;S~~@dzfzS7Sp@(nUIeSmBHscTAoUSxqK1D8ZG(32sjx zZmcsg;xLy8E|fDS9w-h*%Pgrgewe)oo0JDey1`>SW_$a)CwcRrAs{;}@*|9` zv5{MWbfOqPXopq0s*$o-$Akrau7v(j*pr6`OLSAGnm=X-=>}S(LweIVL8G1e9wjH% zYZiwsS4faQXhJ1a$-b}r*js+Q_43J=4pkzUq+=DS&;PqYzmt=iC;S71PnKHHoj$tjsrJVe>c(6fF8K^Ch zv=muS6Z4|os&<;aKl;^Lulc#b4SNo?-T>8HI=N5gi)3_^PlFj2=`InQ#$aN{7PU+hRAYKXx+RNu zo#?<~Nm_!k!hFH8tf6I(tl|T!;J7+8t0T}M7!mt=s>EtmCX__k4P;8?7#4;ZqF=4O zO-5!hYFfLSLrD*X_JTKVt8d++C+?jByQkInZ<}Uf7iCn)7ODB4+1jDfW)F8QLP#^W zPAA!7FaZ;xDVBm~UM1`xNrJmR4F~kKqzxwvj${ikGK?4!c$8e@?kAlnWa;Jw!|%Wo zQ$oHZdBXEIOpLs`M^TkqCGQQQ2eJ`J_IbHNC+9AJlaMSOxcqOK zHE>WPEqV%ut$hK5V20ety@2a(H`W7vK{WR&!dd>>4b=`t(j5jb|u zP_jb$>C&nQ$v~;pS_;Jine(Goa!@ON)Z-k~V?XNK9Mrdd)OR_k@BFAIIjARo)b}~4 z@BOI1<)HrNNBw&a>fZw*@g`3u-UN_y1u7s>gs5Eh21 z`0vM#7)hClh2yy@(Wp=0FnFwk$2s6N9lVwUUf03ve(r(?1E%Wpf3;@ z!ug@$(cZq?B9Oz&d^(%MeNIUUOboY;?EXfCHWuxo_LkNfw*#`mmq-o8T^|%sK5?|L;jeb$?szsbiYyuWT zZ#R$pn(%MtC0tRl&!$8DA)C&EN7Rv7PLM;}!YPRht&=I10ipDXXR|y|`vZC5C*s4Lr0>gg|Pgt5=JR7ELIJjOww~$xpxC(c>ir_*o$& ze6ZY0a7Fq}slXR}zlIOgst55w4WEJ)Eh@k?_GguYTjUKd-!HDClmhzNa;uhDOgU9PiQuW_!V(QiO1;>bC*uKJSd_RX zN+MAU-Ym+Nv)TBO%K@19-_EC#^g9g|uU(Z!wZV8?5|!)Id-Dq@wF~@%UTJS%c^Nuo zSL>)cLR*__YRjuMgIa&4JfjyY_}W1AhPIo_xyym}a0;VjIbCMbp_0(9tt(>cqcQxB zN8H;1yyOMvN_c~%7Z>oX`+M!Q(^YPzq!N%uiRTq58Lpu~^h6QVxrLrjorF=R9-3*F zB4C6Q+IGUfRE-qa{c;KvXpSOpdGFl#OkMrG-~H0>e(bl})jB@fIX89?hrGQI9qWNY z$p+dg*2C~If*c3g&|~OsgAHp%_qT`KPHd|^U_J6M)co|RQEygz4dlxpaTuj{cgYB} z)e2K!(z&aX1PDF1^cOBmXse5Xw657dA*(+!7dHEzN9ItnYMr*qG(xBTj5|mal{CvV zE4hMgn5>X)@@2llt0JskZ1pIN6FYF?9Gsd1rRuXRq+;;Q5qV@uiDV@aqHhaIw-Vw5g z19-JPr35}#Tdl?)MpzKx0)c5Ghs+Kb{IVe_x%u3&{$$OBmUxci2=nhMANKyho@y6` zs#45VZ7lEJG`)zdgKvN0yx#t?e9n?xwWVwAs?CJX#>KmS7rx z?ojeNN*12IO=ZBg$5vpl6!+@PoON$tq$vE_$MQlWVwKUbV}kUVwiAm}Ji!Mu87SYV z+XueRF(*>&l&E-*-P=DX1)-R0DFUY`@N__cVa8#l$O~1i*O=6ET5Q_LBjyBCsc}d1 z|4yV!H0fe~2YZnD&xhylLa8O2e=%R*M^nM8{ zOtsDzP~GfB)tU|{Z3yY3!ya8AG$PS4*kvXTw+m)x#?fz7h|}@lhV14S%S@6Oj+4P$ z2hk@9qX5)YH7DsJz`F&AV7SEOQ?u(NfUtp`HIs0XkWrpC!6?>eLcVriyso8oTudz8 zFI-)&Hn11Q2f_ioG+g?5+1|?H|B}Y@4L^FK=)rS2KD^YrljN5*c~g_}+9R1e;z#@g zu{OVwjaCh26K-KXV3zTu4RDr0ee%m|2Yp8aErIVcVXR0YAe-+QQ%t(^E)gf<`Gm5}f` z_d*+nsz-VS>c{ z0#1kKURrI7m%5ie8&9tWW2m!v&n-?-y_cymk+)84;QtJ#N9vjNm)OI6-v-?=*$rA} z1+?aWX*Gri;W2+ao6POSZYVQeT-}*@fpLL=)n0tBzQ~(4Pn~I%S*X&NTIJEbr>95v zFLFbxRNSzS#b&6Q*Cjddu^}x0R(tUx<7v5rRhsP}Ac`fsO<(rR<2Yv3ATFTY953{o z`ILsxZAxE8J5U=(+;B1zT$f_@#my~_SB1KX(+jEBVOv%|0k(1_dvc& z6=ufxhO@R!J=N8G+B%BZ=9??)ZCce%ieFX7V|bP~%c4E_11^B!Z&ZG_j~-{J#cDEo zg{I0;E#}^U{g3nufx=t*!hrJ8{VS@+C+GJ`GypRI#rqMBMe2u|g*=Kq&@14S;Dt5NC-#31tEgQw8&=M$>7m83=MusK&hMz{a%k2qx?N1N@F@%BB40HVJ=ma&}Zg}<%xa!M@tqeM?RbR(ZnXJF* zn2iW@a6nesRp6Ji0CZ(V>K43%I$Jl(j{1r$yT&Z5;>W5eSVNsNrAy45iYF)b;>3tU zH=y+W1NnKMj+j9gOf_XY<&B+GaU}g_r@gh4POK!G*0G&rQ?d!2*g%9Q*ts!BUUUFZ zCk3@$vwhzG{j%C>o;Dkue$|s6v-Elm{p_@_Yg5<(Wu)!sk<*_Ks)kqGC4%A!OHb4N ze7W<$!<0YAhiZDe3II3@aC*3MLxJxpk;9!umfeq)!(|lE0PIOp7y-X|pD?EZ!i?-9nJ# zX&{;9t8vcT{o2Rs`B}r8;cqA##A4I{u^Bc2EXE~(y8&gsrx{Iv0FTZl z)w2Wqxtg~Pb*8=%v4Wxe%L`X-B?r3_#BP3S#MN$~4_!c33#mZvUQi)C{a}Lx%W<`4 zuYGpbvLuzJ`m1Q(ppb(kEN#Rj%d{! z*8-#Y$Wl|?o_<3RCUXH7y#h>kUkAVX^;)%G&I71~0pdIgahL*T!5ZE?4}tZ*hRY%O z!D2}MG0V4KXX4vTXD*&TXqq#h8`U^7=@G=4MUA-wSy*r&KR~vV zYpr(epJXI_Zq`ZbmYs=Y8}3RzaivyViO0^=x30t!XDVmF@c(M2x<;GZYi%gckM7?6 z23)x20^|^qdtl4Uu{$|-C)eD`bv^l0yWUWiR4utwT?bfHIoHn2TwsP77>a;Ol`6eA z*WP>YbzRF^*RH!(6j4DDv4a$`VFdvZP!tsfQ7NK;SWpo}5ETS0Ao%Ab_vYu@$A@>H z=Brw(_A#p&wuFDpIrWffJ}oPyK<)leLFkcG--WQ zw~LEB^c|^0BsVAbTD0+TGU_>TTCD0V+gbDOuN&s~U-+<% zx!r9i#2M*M=;f8OeX`~BE7OWbCVf|n8r#eJU}bKot-kO65^c}(O@>WLSqqbjGM%@F zwHa=iSQHF`)K@JZa=Kl*IyJY!ebhg(rA2NlWcG#` z_E}%v`@S0deR;>T!I$R#k#z0T!;!&tT;;lBe^(V9HaxDe`>d$SjZ%Wsc^4wtm)CAp>NuNHvz0z0f!K2FD zlAJo5lfP!44IOU!q-I=3)A7-xCaxRPJ-FBKx##lK7A;s+D_)-dLfzlCd#V1wGR2x@ zRhy*c4<;J)dND0Fq|@7i2Vu73_XUqS;us-W?)h<@Q-1F1m!1XpUQYLn>|GVSWvh?N zF8tJ3qC3PZ$8C{wwE5%Y%~Qk1Dk7(JORO*Ne%>ckflNKV8}~cvRuMbv1_T64kDi z4__N=^2fN>-NwE49XBfC+?U968NTC6|0@0K{p7jR@?rqk8-Nj`rg;)&D-c_hQDU$N!Bv-`9KpucKYEuNm}ro4vK` zGp)B%HwRZv(hr(y-Sx5Ng}kTF!lte|Q=B_KdB~o@`4bl&$t!eW9IJctT{rY$L-Z@Vf_st!<)@q_rV1nH3@V@l?wx%)5Os!@tRSA9h)i34Q zj5X--p(Vrrd%mjwyvvK@i}!dmlm@TN8}p~?pU%~{v%9N>kDSz_G{DSg`$0>6{atnz z)o(kD_stu=azVn^n&62|%Bv4H$7F2$8QrI-|CV*Vyhd$k{aVxYP|=vOxb5ZQqGf+w z+*-MFzrVfWz^IYayv16F%=$+Rv&f5yi9ZrFZTWf4(FZgFw!e#%NEv@+k^bz#=A%5R(8GE7F9I=CD&S1M;e z^|NhQIAE^4^JB{eC-e^AI&d+&W5L$Go4b47fBtE;mwS-(=d~xu-|6k@!J`@vBCSc& zHVv`az6gz8_7WW*|EG$dV#V@1y)zEPPpal7{1J3GM>cYCLH~x7yNklbCVf2qJ$I_k z(tU-}Z0+PF6~iAIWM)Tp*7BZc?h$!7PVISd;@8$b3*HnbP5e9Vx@z|$dtGnjExER8 zmuBwIA1b9MedkZtUU&XNWY;}j#dlnTe!0ZWe!Fc|u)0BnZ`W>P1|~uZ#8$8s9YB#(QL+(^E8kC%AjKdX{JV=+0=; z7%+Q`S%iJu{$*ZWqfFZ53Nhh966@9Lf%m1m~W zcdlip7uVKz8`Yuus^|y4KQhoj5j7+^$*na1Y+|KXp;2&6$1e+2D`&s#8$R0dQLuWa zbnjIIhrXTicGskyT|Ya&2#t?2-?;flW?J{N0m=tKzec0cI|kK>J~qsave{&M@a>W^ z`NVoZJ$a$co6^mvZcZO<>*_x8$$tY6otRblxV-p5l+EwZh2a*f!OR$m%iMkH&2cH6rt{4Dl8U}x}g%| z^lu-nYgsa_>`!Uc{l-*VM@p*F>>@sDcbOBKc*c2g_LI&IJ5u&8Svu&jioVafs2&Lq z=1ut0uVhUZ%iSX`3?7?5yX?$r!GQ+}8FE@PcFz3W;vrb72Ep|Jf-)MLL<%9sY>DfMF($XZvOQ(a_2J1GTXZ2 z4N>b4ZdCb_ezNhO!+UyL->Tbr%$5&GdlP^dxq~oJsupkvwL6%(VBzhYU8^Hnhl*<`c@o0 zJ}7=#dhe*O!?i9IsP&7>i+x3vxXuC71Fe-|!!r z_qf#^16G&EM(kbHoUG+=^}pGJPgh@$t2Z67GqbXL=D<_^RkbH;U2b&IxihEnztz1g zBLXe`-!9!hU|DhIz@29P`?G?pivyaS&D_7tyfN_1441uSDKUq2^)#KsW=@hCH5}Ty zs?*Jus&Q-9xke7yseR0+)88J4y48hQzSh^im@?+#*Qk*@8Y=dV=y!5^>+xMvl^Ufv zlBu)RwB42Gg( zw+gymmJZ)q<}~>3i=U&i2Tkd^>$7g~^u|=_BkOS6nMq;kKki|?6xP^d-pICb;n~)s z(-*40y>{&0z!}Lymao!!G~=W%*Zd$@`;NjZp!de1{kqyn4EH{I?%NP5sz116RcP0; ze^nA*X?*DG^m13X#Krn5^jmR{=NsRyQ>bT^D2EI3sLacdfrVYgSxHI$*ngt-9{O zM$JcU>9e=|{G#5{a=3NVpx=oVbDDR~OH9{ouIka+VA$HQuDPmZ_5QlVx(x$um5w_-J~TZYoApuk^b@8a4G)3QI|}ob@ljV_RjD1oy@_3EPfQ#^*iuu%Ye3wEuK@I-t;{AAmeVl zPQmzXc^xx0U07L~JuBgd=Z4e^!EZg^U0A#_??+v8)5n@6UL$w@JLu?*nWy4+9`asR zmL7LIW7gozZ}v8=-pf90i67L^*fT8T$%T@VL$CL~-ePELn_2qx!`gS_2jvufoiAS< z)8%UK!^79dFEed^aeDKSm#;MDzc`ukZ-iB;{{6p0N|(E8YMabI!hh1<<8hw@n}};Va&Zx zxG7RDMQTtir3l<}(pwVBb#e~u9O#%PQlNXPphK873bQsB5Xolg6p6k`bBPXq>uQ?L zZfM2aR>Dm&Mk&TvUy4X}P&8?<9+MR*k9s6LXUZ_b12w2R;YArn;<=&Typ;ZzshQ(gWL5Xp9l{%B+5EjD4T@phf1a@0zcc&{RU zuVPUwr3gxV;Hx72vT2^}d>hPcBg}6q;%_Qli=`BSS;aHMiyscpooXgiq9RghUu4`D z88#S2U_Mv-#aBe&vyS0adw~0#RN7Yw_f=w2ETstC8s;{W4_^2Z^VA7*uM!QubKG|h zb14EhOHD9XecwrQ#+@1{Q=m3tuph?ghcV_-M6#ozVLMo($RFsZ|JZpRCKnQNfi)_y z?ouqJ2-bbe4EDaHblkRNf2_nkqVOXz_ehKjM-i0BW?mN9x8Hm3mhS2b6hLa?yb(HY zWK=Arh-9m*&odqD=5_D6NFzX9iS`g3O4PX$b*o}2MUZ<(8p^k|f(mQpjh_jaTSp90 zp~6)_4@D8U=U5M=a7c{*>`{-oXGmq76muuV*2PkaRNt$7Wvpy7t>~NSB3GgyqQet) z?g{8X5xBRQ4mG=aH!siFC0C$k!u`?#ed&PZQbe*PrctbH#;u)Q;)=?!+!w@V+c<6; zR2)T++sG<8yVIgK>uZ)M6exqpt#C&b?vA)@1d;57XhI&VjCU zR^_5qara9RHorfZDw@O-h121FjG{ncib!@&H2oA)xZA(l zwOK!IVRAGf-#0?{p?{!=WXDD0_Aqk5{oyO-=XdX*Ko5w<>pfvLRTaD3HW1V6tMX(qreEr{h0$heZc%-L9C8UP;OSt_K{bDIa5c)*z z5bu(CiFZ5weMUtekC=p8D&a~&Rf@pf#oX5<`--9F#45}^PLy5At;D?^`~_Z`B$=0a z|Gc>GA;WM3C8{92&rIujL3ugVRt$}yKB zlH%aB_`kUBl^rj~J?^AHam1)e)+osuvnYa5?=d&b8b43W8F%ljL|X~BQk|<*$MYMC z@a;L$5PpP+`_Ix#QggDi0%a0zu`eq2#T^YrB#RJ@Dq(`XkK`}@6#5(sPA4WfE9K5g zHH)PbL2!ZEZGK|9P_z8vU*k?0D$zb-f+{grCB_O<1nv!K7;l28b3QBAOmH_+pm?Ih z4m^)k;t4NBC|nlPVN%1x=}R{_m?%**af5FX?i;uPMUeZE4H1V9^jXkr+YA#;)JRNw zLvDCOj)y6Vf@vF9=N33+x0xu=A=0>N3{j1tJsukfBAK7a{h(Oz*czRk&u2gIG?k;R z#00OU;@48#9Z-a?m(vO9%i0Qybvp5w_>Gi5krO9!dc{(TKrG_h%YppiL*jmRGE<^& zq(qHkt`RIn5t#d=hj~j$MqjZRJYl1m0#y)8?bJd$wQ$>_2$rf7J&-;k)BW!U+(s?? z`xoXOB;22F=%<@4o;DH$ZX&a4`lyQ3b&JfqC{a1lwpPm3LPMYkIwZ4(pj?)GXLZ@b zE^>5$nBb_o_^3MOQUvZRzGOQxQd`%D_B7W-Uy1$G<%a3t+7t!*TTZwuRsYA=LWwen zyxUUlHkgzm$UDxKJNJ+E`#ErKU(78c+-<7dHdQk`K_Cd+9g^RCBb=1l!Sd^~lNNX$ zO3G9$6Bo;HgQW=EbY9O8!?k}@+&pK2J%CuM)e5y*VLd5=rQ(>Syi>m3+mUBtsYK_9 z1|LK!A7Cay5u|=(Gl}eOXC>X62Usak9+8`8hw|)jA5Re$1aFw!oMZp~?ljHP8jtwI z3vwh}4)`@ikn7L7x1~|}e+6ymWvxJ4iN_vSpyLXx14SeY5cvc$kF}X(lHj~`JQiF{ z6i!m*l2kF7A_#t{*20^tTbwLqQ>(Q9`lQ1vH#TVpwnL!blB|LL_n__j%^f(&@swCBr zu7%RIu+vb4>iy0pbV#Eiz2x8rtZM*~dR)RCmtbe4NWNd~D6i|-qb7FWEFW~m>wi+N z9TIMb1iKAI;MS`N4Y$5<_=cXB18fy2f#`7G5ZyP#D`bkG!+quo>(|aoSv#}NR*Bva zxy=%;S%OD*CrbgedhkZnwkx3Pj%nV(x$#*DgiE6{qm}&ao9g?EO)0kEcC^ z`(DhwhmM9KaMM|rJbB3itF@ZmnER16od?mOL@X{5V-KSUav$=w78x{idf%$E4tN8C zNIm9*j``qGj3Sani^hgAu_r>M;vwZ`j!N`{nCzj1dk9rQ5yS?t*0bix{{Mz`}Gr3&AmW7+n9CA{iH>8Ry ztWX8?A{3#Dn^@m$)zi)K#@OpvZXhvlunHHfg3U`2tZaYiZ5&UoTM5Ony$T;1_#rJ^=%GM4MBjogsGtjOK@^efjA%+RQ#dfA_udK5d_3_alnCCg z%58@+g(3*v#m1D_kl_6x8*+UYa6sYgv=`)RlKC8S%hdiS81)H>BJR z7}qEQH-?RCDx-pi+@Iy?qd=)d;b1!yY=?b^B8(JInZBzY_jdW)eSnV=T_uS zXAAHbWTvyp_!qSuLlQ+%n75tCY*y!*)xB`HM-aFnY!flT^S`uNlOAI3BO)_a&c(v| zm?Cf^*!tM@Q}VBE79IY;a~o2wELAQ`73)e7xUrIE-d+=i=uLYv+UE~Vluu?XDRRRU zn6Xe4W-KWl(WNFaBe29vL}IN-r50R~B1rtgT+ulGO7Yb{|NKLN!bqv&El|7#UgA(h zvQwf-7g^Qb{3A{_XKSDCc#T1dbxp)w6JcXf1i?3@KX_IDyL)54tMjz(3KUHG#};SQ z;*4F9B9d)%J|Py`@4XnUz1?5T$J}2;iIWECqyg?0C?eTnljDr*JlOQX!myQCheG1w zw@jUsTrh!65^J9Y1$BkGT8^u}E@ zvDq6L_eQ2$ETstC7?LFNh8flc1N|H-^((U^Om==xO5Jr(1{21VfBWrOP3%?G@DqN%rt}=?i4U#nQZj;rJ-FP%~ z>|h0|CC%rsH#+Q%D~%$!LKW-n7I%(NFCQl!qD0|D-vAL808N4-$h{_s;43(1bf0s5 zeeH)R&}rI)O;L*}?i*SNBH3gbTE1akGMZ9yl~e*5y|%8 zAWLleR^&P@a^{$cnEa5CGd)nI2PRVlhtL)pQDf7V_;a(njmF0SMB8+ZOXrlhDiZ0(U2yiJY_iBjWEy`B>a55xHx)HP{C57kH^` zRGkyP{=V!@@K^=9LR5Wif?k{8Dx*kt10RY6W%cwv+||0-bsXMjB;;^o6mE?BQi@Qn zyNuhExNx8gnlw&{J`e?7NVykM+$bo55}}fD=mU{^P#Yc8#*R)A zf3d{Pe)*6IO7w&@_{S3NF^p9d zfg8yh{LY8h{2gvNOjIC0;*a@wZ(D(NponBk&BB>G_E@tk{L1j*nERgSTZjikC7udV z1bu%nUzjfKI6EgSa-tFy5FNI2+;*5^Q3M?t*lKOZiufHHMGX@*Q5l(Dq{iB;pgWj-UwK`+UjrET;G=4&I-R7j%S~z;Ow%zd#X~t?caA_4CN4 zZsRx1P@>C3gLn}a54*S&ft$y6aqmuB|McUBk{NPzkjT9u7T*x#RRl%g3Vp}f1qbAF z)Mw&0PK4f*a`(Ul6oGh>4V1@>m47OKsn3$5X2Q);73Zj8*P;mAN?z)+8)XwV`plYz z=fi|KK{5e50sIA489UcW?QS|gDEFUP3Uq`xcBn53g)Ll);H+C&#U^V`U21puH0ItV zPH@W--Lk}{q6l0Kp)Ytn!Dz2-el@1vCe#FPlmLSsMW7b4zF>L8tFrtTOaD}&-Gp1D z&K1FVAVpC3HXCm;rx{2B-kzC_2R*{AbVQYoxL_1P?sX=2(A{&-RxM4z+@pm137?%Q z@zk9naN`+wW|EKf&AFTAC{Q)wMwp`rbKGxG1nwu+$NW$W?mqHc)Ep%$BW*Tc!sUZ+ zQ3QRXSij-k-+a=K+tpa^O(Hkh6(zgk2?#|b+u-z=>9FM3*O>E-)mZK$BKLrVJ0QVZ z3lu?aAv@0)H}0=f2DLviH=0y$n@FV%S}sN4zGXAP^)*`iFOAQfr$9SM6{mJWshzNc zQADz}wwG8H4}7s{@6ffI=F8C!BKM|9d=u6X6p38k!7`@5&7Obe^n3++MoM;G7oFF| zZGj?^{nMp_S?v1EDG8$7xcT^yk#OtPxq5XAJaZ-pQunaM*@5w+dURg*0n5EcxYaJG z+68kdg2f7$#k3EYzB_pL$lnU&PfFILgPL@(4iu4WxkV5w*`|f2%UeBfVeSzkH%1G^ zXyMU`BGm9DCik0*SZ{3~`vpo=L)z{uDfbFSCyJo&0X90N1tzQNe|WqApREub9%`e9 z+E^|{BwJw_&vZz5UidSn=)giv)IfUh>vF^Ea_qeng&zE1uDQYCfV749vI41tt*YEs zRort>gl}(C6Sk@UeyzDQ{_e3w3bc)Udz&_D)5a1hBH1$Y6!z@}yCu~X2Tv~2MD^s` z)8vL}aG*g^`1Y$hk1y~1eFjT>O6_EcVl1&2#t=lZ)1t{`%uugqh+h?TQWQi^aYrVRcX}*VB7ah#Ns>u;IthQFFt1r(bpPt9LvPZ>OYm%+n7vNQ)xiRb zB5>2#U|=z`N;SHB&=Lh|B5LOAqkMf_7>ckcjbH`$dVj-b%L~7M6ex;tvpS%x4tRM% z5y|Ftyvj=CV#OsU?)~_W9Hr8R#fjVC5W;ZNEslFQ6?& zV5Tx{`_ItWrEQXmxk-dOS27oO0`M1jjp9OnN-}-Hv&&6}_c5=LbOAra+z+@$K@qrz z*=dey{l%wIL6ep%&^uD9cjoAwIbOn31c$C=4bau@aM!l!sw))e0O6Kcpb`tL0YxM` zDVlhhnPBce-PgDLF>M7t>LUEz~M1T>fgV_DZ~+L<)Cb%-x4WV2Z%aVynEWtIEkOE2dy>FsX)MbuJjzAQXZ7 zfE}_g>|I@))aU0)1-d{B=YvXoupvqaf+0#-*5|xalG;U4-?e2;2;|pK|MDrk;_rD&{^R+*TRaD#He*2;A-L z?4!|V^1HwpH!$}$DO;wL%LMyU1nwy|;CEl}c!}B(ZjA!HC1p$ZLFqnNUy4w+Z>*B- zKEz*mt>?BziS`q@q3T?yI-Va=B>FO&eKFm%IBj$f%=IVwp60mI94;G0;O4S*oBOa1 zCEHf4TO&siL~f8s90X$xMZ)Eq#Q8fjdWXy%wid6=iMAO!C_@KpKoQ1-6jl=_5gKCa zHDfIv^@#@W#N0c$;Y1On#z}-D-bck&!GktW|5u5w5Di*6u9d@0jUsT<*yiH!@qcV> zT7K+bIeJ34Cq&{CBHVvb1nwJNTNBTdTME)O|HBI=;*SXuE&)zTC<1do8^>*LKIt}4 zb?OEM3MBokza#Q@#2p<)B>UI?0PAjw2Q-P!%saCIpMKCrEa84gurK@|2y(x(IsL}B zjXzq`<2J}q5Ycv@ig=$2o>x-@?n_=<$N0!zN7XlNl%ob>uP7C96wH1p0<(~3dUjYi z<=p0=jY@QkFqd=7F%SL%D}gQUx|Y;m>Jj#HqXM;%+B&3%4(Z{}h9capie_c{8NPY2 zl}pHGY%3!3lZ^WWm+dHm+!yS!-K`5l)xB7WQwli5y3)lu)5*LPoI z?mKE(DfbD6kxvAHdzJOJ@$UKV>-IkOSD-sYhejXN=!1J(ilD<2*1i^cg>O=OkhC4& zVj(*G7ODJ(R!b4&ma`e6$JLTib&D&uD^NX=``HeCw!?!dMI`%6?-!FRy?=IV(WW6g z@Z5-a_Xi300lb?c$o<5;`-gs((`ZHb4h703ax?8wrafLTP=tetS4{5O$M+{L{=9l8 zo}?3fpQ>?B)$qO^MUdOT&J0H#d9uFasvkQQXgg_*wVhFIXRI$pBwKB>kJW|l*%3Et zJDk~tM-pP+4`S|v7|W#yatqkGWwx67@UJOL1F;UIY}+K* zv_J(qLCO~5ib7m*i=YVe)Elg9dp8++&%bszNP$ifZnzr?cf>3?!i>+w2x!dWV`W>G_hHtDwn8={fr{$d!3!m56qv~To%*= zb3c%>-H>oMBv@aHz&*lxJAqsFiyVSOnA_buak*S+kgJvjz*9}*o7aNGe{Yf}VnAv??W?WwX-FE}1^pOJbi zl5s^c%%uq2lae-mALG8toub+9-oXlVp7=wO7fSNNt2c^B7A)$$ojJtsg6ZZRc4+NY zqH9Fq91)iz!rcQ!5d4gtfF0jdx%%12pv@qHOKFh$_L;Jcl!tD?IN%+(1| zpl?Kj9|q`$0d^gVNVdrM8Y|h7MD-p%p|e78XG%2qB~tkXO`al1ea)Kuq~kgk0dKOf z2B}1YdXczZgzo}T1nx&(gDI!)o*&>mbRQn5iPYWd+-`Mj1B$@B&!!ckYteU=tJ*NP zfJogf=XT3+xhMiRTGGr{n$fSKA7j^Hj(ExR+CXt^N3>8PVbf$K8NkQ;MKPGut&y?P+uS z`@hPAN|Z)Q_ejJ&0&k!Q+*0NZ(*vXWPl=d_xo?Qv8Yx!;T{T7ECb6!%IOz23QD6HX zQlJ7-ZzpWf2^&1HQv}a>$C~`o7cp1+-5h!dPq>K=`&7Aos(2Wr2y(Bf37eLqI~X;^ zZdr@v?k0w~R^z zBsezoDdz4aN*qz=j=&n7B5>1LHEV6DSmLttpQB22m~eNAxLvRhMv)kTx%%U!*E^e@ z+l0Ay2=}2B*FP>CMc|%cv)zjUdUabKUB}!U(mxc7xnfu$Pz3I6wnA7OS%1sJr0}Q$ zB@+Xed7v^6ESDk}IENYduSW?f(}!q>;l70E5TMEhz}7fLkQ>Oh#^Wb!37A`QJq-8j z#K3sK-=@IxM~X~ckHwK#J1fnK-*T_-w(IG_**yh@=6I>-cS@ymXLPxhV> zAxB9>g?y1XA52CORJhBxw~jS=wJYz>iol0qq|&10Tr`|cQv~Kwb~=4&Qd#%G0sdHO z6XD+E#5ZALOcA(Gd8yM*A5XYHHZMYf_7hb<+MjRp_AEvV=XgwwQZ}lxwGm+X>~O2;4;G3YSdkukAV8EmDCl5*@a7 zLtDGyHbIeG7rn!j=p4Go{r0YaNI42254N-FBM^yMB z75|W8gHZ%#CeOTeDzC(UK}oa%#gMuU*FfPKSSCdz+adCeWsT>{`NI2+UmapJ(G#+_ zaZPS`4Yo@t3VRzG@AOv$-q;s|ubGoC&z5r8;NBGB%VU{)zd5+5Z>m`p=C%^MW=gnB zxc@;BxZ!LF&fcHg=jE>&%&jGI3)Hv*HQXF20{1JM4ms=2yS~WF`viWdLF8_iaN9vH zMc{s8)0PdIYkjK*|8Wv;xD&biRk{7DxYwl!+=r~M@qD5(=ks5KG502sdtJ<3hht%i z!2Qe)(l4sIy_@Cz;3VFeCY~577l*=55Jli(i;M6P^5#yPk7}ep!9q_FVvLxJ5o2X3 z0`VT}lNL>JHXo|;=V^SpNR-{J!tGYU?Uo|t3KyN`=X&`~NZNzB?}@U09Onn;9u$H5 zmCZ|6UGhu*W_|p$9EA}bs>R}JxXVTnxQ}>`nR+f*r<-r)83j5+yzqr9df|$h6k(Qk zlX>jNeP8p&Xnw)mAmUwVZYa$S_XZS^Y@ev#5wXx81Qwj`<>Mia#Zwj{IM*BHdgFSa z2wg`86Wr8OJM+;?X)GRhh#Bsva(Cbk3Pn)&G`oZ1Df1aw8`KeVKM-z$Dwm*&yHJY2 zy~d`5*Z;E{dc6Oim>WdQP%h@mVF^wVxR=-xe9mrQs)tQ_qpa$icsFTo!v0ympCujYt(%R{D3KdVG%iMCZDl`5DsQ3PfUy8`0# zCH!~n3BPlA6PZYjmT=LqJx&q0FWKeFqYoxn-Fv-CXODTeN)0uTg zd;7nSaSpwJuZs}5l^jB1*+g~i6WINIPb&sX@iO-b#ZuNOmsLc=T1YPPZ7AsSf77;iudM) z8=K-4=sPJ}fdMKoz*k`?BH3JntIW$@eesPh`bTQ3UQ@b^>wB)zD;O z?-I=YPAaZWg{xD+4nYyPiL8?KCk$#^TDvn*fzA=5g_xocQ(PGokt|5m!;cwlMaYz8 zTA>dT@c|DJ94+Fa;Sv)?5d4lUl@hK71e;xoN>ZRAqHvf!3bV&XqX^@5C0lu{3(3)Q zzH|z6FB5KvCJNESt%xEREt?r_jN3=+vS70-c-Bq0?`_a~8(hm2L2feRHkSm$xz0M6n?txUaxMnA6oDJYxZ4#U>^Jn;jJcNx zcfXk154WT#0`~{ICB3#dE%5353z&P8m@HY!B}?(Dl_GEx)P&d9#k*JUtciPuxoxCm zPbAzE=q4!wH=6mc!Tu9j^-)$S3iOFo+iSV*YZzWBLKP$7<;In>SC_2xnuV#q3AMx+ zmB2L&ibxhF8orZRcgczqYj0i*OTlj@iN2w#T&ODUR4IZE*V%O7jnf6KwdD<%n@_k$ zMBEWrDp3UPd*;5o`+H^2^0=9*Ku?GgUlizz0xLlg^ety@_Bb|k?VF9+sdx||_Kg*D zu`mo#1i6`PMo`g5DLNkJm4?s82)A0wRl^dDB5*IUCD^E8;b%8oOT^so#J&e5+(EdF zPZ78mrNaBL%zauK-#@>{+(IJvt&DpM_W&sZH-_Bq{dU9q5_PCX{q5OrI z#it0?{miU;M-jT=?!w$m1-ehTmrc=SQ|ylvf%}ZLwYjg=RePj;!Q9Klb6P!6s|RlH z6oH$@tngsveEaMkzccY`79zJ*ooj_LlOkxlkBymrN2>bvKdXKhzpo@E3z2gn(4SHS z?jg4ElRM|^{KetUn0t|ML&aPu^rsYo`6Y* z&z&2@W&dPk$x$-l{ww|$yE*&?ULJ2*r$pEA@1KTc!ii+ z&czRi3HO_r`zFRMhazxyGr2479u2u=otumAc@QgHlZmgvc_l^Q7W3NvN?I{;ec;AC z{8Eb8;GnAbpenW(MPQcm%>3zDYko~m$-~ig;Lg-R4kG&rEn9Z<(|DFXKQH^Hvyu}0la^?0g4W#sE0I-!TKJ4X?|{wHg;r(=sX21$25 z#jZ`bkJY)y5cY&3NX=%)RGM2}YzQ*S#@u{ju3$MAEXQs@5x7yTc@K_^2IxcAt4X5zsGi;_Q>7vY-`!~~(8QD|q}yeJYA#4!`Zu3kH<-_l=2_!O21 zo+p`yM>6;eLYvqnhO-CSZY?@^uo!P$5I?*m;V!|vh9Yo7*_fv>bap47pH?MG6i;Mc z7jf622d4+^KIqe=!zLum?Dw|in{-1ZoVMAGJ2-B;-wt@CR*%J z74J~RzDp6bc*lEhTA6wB#|PFg@oN(z_MR2GXNAi~5y=jVh9of^7MCUc_hb0%SNJI_ zsksYc?t&OEu_=PsyKL50x-x50XWhYNc+ZEZ@L8nt8H`2|xbN9Q;;-`+c~QyPWq1}u zD-R_*W=#cog`x3 ze045g9XCvhz`e&B+mL^%zQ1&my~QWJ#0(LhD8dtKOA*QTiu#;mW(co#zFYcHACpUn z;5WMHjV|s;DZ-V9Mm8A~5ADCiplaz`ISL?Vm@1x%>jD0P0-AJxOe3eXK=0mqEUM9Zz(}6E}5=NERa+f0mJT6B7o$`l2XT zpsPf1t0!vp#7;vI`lbiWXO67!4d@kZS&m;_5lve}DlHrfv!5ej{=lRJaC+aX}HdDQsyyWs%>}rK_Vc_au>f zTFjjmW4RQ8o5mb0Udz2#)}ahswpeO34;1c!`_gcNB%DhsD_qKb*O}=2pm+GOG*Kc( z#KpieoFXY4TgSZi@G&k7n~J$nM2QvL3S1ZPmnh5bCp?XN>p60LEaqJ!ykjcdG1wTQ z2;AN5LCA8;`H_(au3+wY^8M8!m1^h~C<3>ZwFcAtbsJERoOcS;ND5Yx26<Wz!>Vpq$a7I;p25x#%1ZD-#^dBMTp1w`n5Rqj6Q7E=VFXV`ABd8}c^UKcCOEh294OTztvs6G^d`-8cGdqtvpN}jX^ zkCLQV$K>2GnBr3e?qRlN;y3AD{lT;1kN8A_aFbSAJb#xNrR6H zltha5y$kx@1?xbOJh#2g3b(B6LDKhirdV(=A(yIirEpiAA_&f8{rGmLdet%iJ;mH6 zS~xNH3r;_O5d`irHXlwn@kVXXJt<1 zD)|o=tQ$)1hP&}lQU5DU*};=?C#7!E|D-@wL@3_jNLAwMr3gY>*lh5et$KasqjG#V z{RXMEb5iacL`R_r%06b%QL1eR4N_}J{H#PVgzG0(@e||5KoPj_Snqsj(b07}%fDf6 z1u;UAge#I@BTxkHPBsr36D(HWF<|Z&JZB=c_EO5dgryNh;O=Kjqbu)%8ZH<7!uvTl zNZB4Zq6csxjv|yzRWMkbaB5-fTllF<$G^0?IkW*k{wCT! zm2pqujtWKKo?v%WR(YSwus-J1h?@_QTPWrVVI@luxOdpuc9j0Mz|cvK-|#I}TEVKE zAM^`;1cBSaZh(v240eP&PRHB`qQg3F9Ue>IFYvCg5$c&;?8*Aw|6*P~`Tj-;*9fnj zC<3>dHTAzg+N}8?)BTQLQ4wyfgsX*afg*4}Gwy`yYYzSLdtz=j`Tj^b7YW@0Mc^J` z-9lgQLrVwEobz3Q!pVH4)*97XV;fK;6U@DAIBU8)Zr__>yD<4HskAU#6lRMRrif&7 z^b;8O=(H(MkM#SDl{iKWwnN12fFYG4D3Q))+F6nBEQC<3>R z70!G>ZTFrJYJcFlGbvn~Oxz~JhM)-C=e#?9tC{rBajNl8yyzj!yE5)B#95#SOg|Q9 zp~7&Z%DRZrn7e~$8=}I6z*SC)z)fTE8}@4!+;={{^rsv>Cfu8H@l842)}RR7o4f`Q zU+0Z|yg$Af8<*P49fi5$IZzluBnuJsO=4bda!ax6bM$*mK1s;u9ng6Pyaz!MT0|P- zu39{Hg`QS*Gu|U6Mf)n{zC!z@2r9&}F@4F#bra>C6fJlnMr+s%)tX_swFF62$W|u! z%Hg%{R!X73AzTYZY6sz|nsve7mwv`R$J`jgUCXV-D!^ahU1x6Yovy6E zNO~hQAN2l!` zHVSihk?%jraVI&v2|*FK#cW&BQNOm{uV6(hJ`^Ix4KzZ5MtJj%A{h4(v%#C$cOTwc zdc6&Y+ahw4BwP|aCZY&(53+8Iv)Ei))A8hQeBF^RpO1f2cRzFT zH@@$ID}o=TPIp76yXhg>7Pny5bXLxrzsfWZp=HIp=PyiCM=9_RFM{{7zxru3A0s)f9WrhD)8NM zH=Q82EWvYAa|UTV^x7;p8+`$T=^=|Ez_a zPQ(9O>=3T8wi>m%d{k#E7oe6(9W3sd)*cG+jzS2#l!Lf-cy9(bYM8yRi`AE2YmJkCMa`?Ene2x(D7IOF~w|tHe z-xhNCn6`Y55X=^G_yD$iju5&Qa`bmKJhKNJv^f16?lPs5R^1 z0d*+pYfY!ungfI!Av`U7h7U>0X9>Y*A%_n@%jcZ+@fzX0>>H7mYG{*c*h`Qm1f_+~ z@PTOgEcY9=>uR?4kV8(2I{s%Od`1XP3psp1T0X0)cVV68#2`6novz`Qt}#UTj1Z(2 zKEns5<+F6&UGaID(L_FT)z;;z?I7VZLaNs3QC6OUcp+ph2;sxj@>xQFTFBvp((*a(*)|I#OL8@!V+wM!4sv4- zj}uP2*_?Ls6~upSJJV=><&y^3;+=)gI}6r2g_yP=o{wY8e@KX63psq$T0W;+XwBmh zm0dOAi?dw4vRsD=--8osU43d@M+gZ*Xj>3M0@@0~`B1iy&WEq%bNXD`Yd6X7jV7pC zrf@A&uqs%6=>4e#<~+@Q3xN)Ag)mUGE+4dJ;Y zPPi)PuF5rp@SQjzMb4$jHG~jCI3Z2WrO7pfN1IKv4YvQ)`dkUB)j8SMIrS5YDMZi( z1^B4Bd{#qvbH2^iK3edZOkECJ4Gw+%z9Z>0_!seo)y?-Vtx+W=@e+sd5K}Zyd zqbsN+1kQyVK3FcFB}B=E96mBGpA*?{$dCiGrgZ?D-|lF4yJJs5nh-4)S|lGKm(Rk~ zCweAN^m+)peL}cgpzS7cprA#LmPL+#2;YYj>Kv`= z9J>n%LTFu3nh&STX9tq0?I*a=xhIe;tMIS+yef zd4Ba|eK0|wrB0wFYw*wZ-1fIeX(VT#i~Bwo)-4J#cR?D7w954^;(u9Sjf=wvnRHYT$qQXLz)`dzZ7Q6%tRoZ+~IdoBI;{Qo_ zqi6j_{btzOr+dM@n}^7XCr^_^G@0qh_8+!K98yM$Nz*027Daniu$q=65Mg@>=F z8E~-%igpPJ23->jT-qfR7&sOfc(VJt@Mz2Shk+}5(gopj%r127%7W{_48pv)qn$9P zz@-i7WE#-PhQ(dO?Y2|r)K2CsrU!)ZGO6ig%>sPE;k{L8XGeClkEa%$ty4NXvFi?a zp48d8wzCs^MF~ePc7cX&>_7%j&kgO*8@jVtYk2%KbiQxs%>vQluQhb2G4x>JuVHt? zCD6!+?R~%$-}t^)3(d412wXkT!j22Ua7E@CegALB!J6|y~XD9Qp z?_I3ffe3`3F^n*`V8Ll1M5fIx zb7vMn6Zfa)=I_kySS$#*&t?~3;l^&eL99rFcneb&NfKMk!lJ~&o`r;f-3XIb3u|G2 z0xK3{*)hh_j70*02tRtaER9+GAKZOf>X%xYus6|g38SOGl^MID0hb1h?pax~D+Rc+ ztt>0799W!N{Iyn=tyT^!d^YT)ScF;I3wtYAk0fi$Bx?s2y&hJY<^|Sv!rBuvYOSqm ztsU9EGF(42+GS(OE+@i+JF^ouUDZM(2XRuFsDGT6?6MP|ibXlE5?=O}D%VAb>N zEbtRz7UdgWTU&p&b7F6?@z>fLhuK@Po8a(nS})Vyn7yjTL$tlcCwqH#YZH62L)Q=o z7xpd)^p&OyH_?wDfm$U=a^+hvL{d)X}_M z!dXZ2vyOHwaxp?2_W_!{QiYhjDf( zaQ4v@Zd2lR>ulcQY{$Z%;xiQ&&d){BE@7vO^-dS3b_ppimMJa{>?sAF<+yO^E{b*u znJ(6uE>7(ds$DFrT^v{_BkZRxT&;_uT|$G4b%TpjyMz!|s}NU5_Np9D#9g`lu8MXE zVXoF;u1@U|l3gv5UF}(jDLgi~a;dJ0b_p4-))}r&?Gj$NTE1{~V6U3+GS`(Wb5*oU zsC2cibaiT%@Y}WPZ&w#~K#H4(n{Bw8D|^$9SE_DZ)7)Ix^C#?5ZkBJ|9N0^C_|*Wr zpKfmKHwCb3yE})ud$S`8cu{R}+ufeMw}y=lrwVs3Ve13e?FV=6gS(<#LW8?~gS&gX zgm4e%a1U>G7X%)^{LF2%i+N5@tV zGj?wl_C<{%JS~NNQLNY%@s3e9 z{nOn{*qH^Kr|TtmGZv28g zRTDnP_F~6=#{Z4$46DI&K5plH2J#t5P#!+R|GEjECH$<38qVQ=%7o9sLLS-ZJ+d)v zH`dhI=+*ttSd-9IFQKbxyRjzLRxj4pwB1UfRB+uXIOU z(lC`_X?Y$xc^+nb2Eqx|9y-alO>^Y`jwHap;2}(+hD{c(S`F z#)g`mL(LDv$3LWcA?M7K-o>L@JiGby8?RWc#K?FJ{`1b>S@^R|arVAa_MM;izkae3 zBbR;gpE)vNTu&sPj4&Sa&~FooC;y8_0-0Zk#FOpCBYEfI+0Bi&UydQp&&C`>qj1KX za^jnEGCi8)x*p4oK9-xxfit<$XB6y7;LIOeyTnj%0hk_ zawOO@3%(sM9CtFODEi9^nL9NA9s{lw& zLk`@Nkj7KZvzwbDmaU44BTqwDxVC++5w3V_r# zq&`o&8c$hBR73h7PjVW?>YcRMJ82Ja-!j$d@zv>lxi6Ko>G5aN`*PnQ<1=jIGx~8~ z8I>7vl^G9m-w;R^x2-$~2vx>MhHs#ig>8zS)}xbcX7Ff}_Xj@#qC@j04l zh?r^MqqGMN5eEfuIYho3!Y&1TFcYhuR5%{1kOYTFJc(~S67bj&i6_mCM*{h6h{TiA z#v{3U^U2G`c|Rq%-vxp3ivpPk8S>naGM?Nvo-)Ito-b@a-IhQk3;gk)1qdPE4Uu?q z+<3}VeALf7dF5k?MAGSp|Ir?S3Nqi2e#VpS#v{U~ZAiFjNVtu2B~*o*s={rYE8$qU z=~%c8TnUgGhddXabU2E!ZgW((ISX6}7oQDyIq;Fl+k7V{gK3ZD++5kI|O!vco3l#Zb<+;z+ef_naJnz@#;OjDf ze-uSHiz3*I8PezwBc9Yb9xLFhAQDfa9FGK2>9AdpG2%(2 z<1uomxTNH#C-iP3d$MhNvRNDk8#$Ama3-7GkMBMH*0{?}sSaYK-539vza8@M5Q!)E zj>kNV-H61KX~!d3_116q5B-#pLazR5Tk2|Ce~&-~*>}h-5noY$kw9i0BJpI?@kk(#4v~0r=XfOGO&}6arW}t1a^w(+Cohgi z0vU0L#FGWbBY|-vkyO!~Hy+7L{jV>WdeA4GoRo=ij)`&oJp$FgXMgdiuPkNwVo5=| zsUSTTBp7T-H*FEXm2}e;0Zh#>P0iqoY|Joi6u^lL(+LG^|2)K&Fx`+rnz%%Z|Lje_ z{oS4K+gJUaLGHSnR>Mszy9+S5WevS$Ww$O|C1S*rugBA9a0?Jgy*o`098IA4lVkt> zW@08e11+|c7TY5rfs{R@j3-TxM>PC7>tDm)Y{?{&Ia>T@-Qk3zzrXnP(E2Q5ZA^I9 zm~i$yHx?AUF>P)}b|36du8u<0QCe`^VQ?l2or%(d;|_z8XjBrd1;-r*>!Q)RXe~JI zFldcNtDN?hj&yz@6j)1 zlQ+yn4gRy<4fhk{ZSr_qI`le_(2E%HB=Pcy;ISkUPs%Qj1afr|$q;v*F0l6X<4Yd@ zcTQj~>5n?XtQ}!&JYh;3^wXaYy_8GJ4ED!=){8*x%8XUP?}wTVva zL}xD416jSu5Wthk%Ok=S*V@gs$`?Nd$L;3h3IJa+sn3(y%TpF|dJ%~ykC#VMHA&tu zKws)2$8}0Fo|4%2%%0xz$9B~2a!ZCdGKVPmq!9w zx`@P+nad-A2{lCG$;0K5Kprk4@#Nm}NT8P{5>KWrsHZr8)VY6dd%zDLO-;0+CYpW8 zVX!~iuwMY1tcFciUZc($R%d0?OL39EtcJe?jk{LET>(_Y7%F0zjU`9^ygN51`$6)O zAFVTt*0Jk}!RA2o=0J9PLN+jR5S|QRo`Zm1m`FVNzC03$T@r~WyO&1-dA*3F&YjcC zBTzvWFCy_|?(&G)`D;+7$Juf9y(gk7!z(CqiC!P z=*@e7z=D1OShZS0)sluQdsNaNl?)tc4%9aX@?cnyepnC>j)v%uhVWpRIeM5mj`Kz_O5(xV%)GUk`~;l8GxdLG@*2~!(xzqc-iv*?`hB@fqxhG{ zZ-4#Ny?*5S?n$)oNo39g3@#@oT~6!+Erg6{l$4pCZ=0^n zy7kJen^sx*m0PkTAbv>zJCBeSjac)fLi1SrK|AW|o1GioWyYD)#+lg+yZ#@`kECrq z@+kSnUz!xUG>N~FmnF%|lKAmyMN(*mpi!9=S((IpAQw8~7dkTGBw?e=9P!H(@ao(D zI`?GT;{!+&=lJ2j6;$uoHr}fUerW)?JqoOb0xN%e4!4?zE8qB#(#;ne@uYF{SixoQ z2ixuk_v0p=Y%(NmGCU$oDREpg3=k%aI2MNt;AVdu3yC`x@*qt1xZ_tp{^5=L-7Q<| zw5@frS!cMqR;Q!Y$;J!d&LoHD$s6Zs*`&X}tN7{ddjp7Ds4dXZ7RVcE57e~>^4|m3 z17oiTvPTKh&5>Jshdb3AoHT4~lij>Yd68mp%5FZT07ySaTI5MN=P3*mAc(}1V9q0% z7XQz=4`#X^C->fj#MB9i>~5*)5byz7ISn*$$ylH3dnvXU2MJ>(G(hwAdIy7k=%QI^0I-K>z*V{I%WwRBU=v8ku3-4$d&_iWXl0MvgH6B*>Zr6Y&k$jwj7`%TMp2XEeGhxmIHKT z%KbY#l`IZr6 zY&k$jwj7`%TMp2XEeGhxmIHKT%KRi1o-Hq2 z&VFc|yG&tfc3~=uk;eRaN9T8|)Gb*SZ&()3dQ-@xNvwIYXL_t{P<_(W*Y@w{NDB_9 znGdI>K-MR z$v2-TQKmN`JCU!>+5OYaXKwt9oUSHYY?F9I9Wmy~&a z=kNa^--2ZchOz`U;KHCb!B8uJ!wH7N0+^C)n3BvFS(|KFD}Y1EhC>Qiact93q_9T3`cZqsy;4qQ-^K}8jAun zivoBXivtXc1Nb5p0h$Uyqaq-oB7og#*l0}v{_{502L!JVVDk^KMn?et^BN}tG$#Zw zP>%-c`J6<(XL1Bf<}kl(4ps#<+>hS7c|BPqVa)zwTlAL zA^~g;lr{$jbG5Vu2DAl+aNv3%x-Jwc3<@X=;x(28p(R0lE%iZCeGqSSXfPTY%xlaH zmSzU?8gmV3u7TH>Ylxm};BT&W18NsE+6__d27dH1CPXtPgue_$A(|oq>Qe!fA`1_4$zo2o;h;9kswo$rmx3C%X~MoUe)QWF~&<7&^D z@SksKw@K^jU(4ul?9AXb#)KQj2pVg{HERWpb>X4w!r4p=e6$pMhXv{Dt&JZ+qnEiK{1G#Iv!))JSc5n)mk3x6yP7EOZy zS}d9t0qnJC_gaFumR`4@>q0FzEV>&O{vMksqlq%#jw0DmB=gs{LPiyWMx`8FDf1m$ zi;P+XjlHsQugpI{*JN}}(CC%*y)u8a6C=>X2%#MjfkhD}?pP`!P=%mT8DXf5;9I&k z0__zvE<~UU0vHvEMn&?q%#B2I1+Y01Z5F_m$lxuJ{LywsqE11hD>AezlE0G&N1?${ zd@Vzwf`&wea>ueZ3au41&PJiL0+=3+rbqKOW<&?fi01p#nrKubXzY(h`vp*7MFm#g z#&D}N+{*VKo2+P)piyV_ue0(u|6f-0m!NUeif#(vmKDcZ`TO*)72OpyR>h!IF?>79 zWBkfv0=V;05rZlOjkXxnCV;`QXmBiVV}7hOKbAk1ow3qR0rbR5Jpw3Z2{+P{2f$~fC>`$TFMeonE+}N zP^|zCC!oUuxSoKn3*bhAbR&VUc0yvnghamDrHN>1B46#EME^aB{7u)A=-(oM%ZdJ% z1<;%5-z$JhyQb34pTa7;p~}wp4qNTIt#-caYqaYc1<-ESvwpEfnds z>v{z+KMBoG;ty_V5_X{S4O^BJuq=r`9~DWO3PGbXDX=n$@A?iT=?^6FSHCw2^$N92 zNk&tW`D)iDqqPD!l#C7u;BKLI>aV zEpvn}6F`FlH8}W&-EyE?0=Vt)yY1jRgJ~&fS_)sJA_Y|lpg9FK3!pm%bqiozDjJu{ z+Zdm!AD_w}+?rIhM$o88HCCkZFRj*8)GBCPOhp$3Q0PR3PQI22PX7r`{!XrTqG~~- z+8JN%Oy;_rR;RAj$={Y2ow|zx7?Xy^r17;ZOhXF=P?sjvrSZ?);WX*60LGFQ0 z>HM+WN)Nx4&IYIW!)R6pnw7z8%+3g#oxyt_w`QQNf<}EtXnh8M7oN*N=LC)JjIeIO z#>h-GGLx@mUM89+fci{LeI|d#8Z!MFGWq-TT&C`v5a}9{g@$DDMi*pZH#Ki#d6wVu zEZ)YhENNF3f8}mwp__t@TUimeviRvz_p{J_L1SRH-@t6%=!$H#BAai=%It`h*}RQC z*=UcTaV8s`5y0>qG(3m5u^A}oY1Bm{<`$!pdLYEcrF^A z%hytti^>GBAs1~Bz{Xr@V=jNjj^zd)%jG}N&g2H45kNtnRFKCPnVl!i7Qp&Ev_6k- z$H6>wPyj<+XsCOFM#R! zXnHh{>J-4(K4@$oRs?2_5vR`4DAmy@Hsd>P&Di%Ga}WQANN)JyKO3IF z+EXH#7O9#R$)53ROpEw_aZO@sI!f`gwQIA>S}P-^%rI)%k{M z1(d$=!e_cQGoB|NsAWmcWl4{LDlBIw=8J+=MZxTw`Bqa+Q=g$FFA(!BiS`yDO5B^6 z)T=~^KfV*aH+)~m3&hAoUo_E|_34Av-kFXspL&rKby*6`%L=ED~27q)Qy6OM^Wf@Z2QoRO0}3s=<_TtU;Y>9H34$I54b1 zooWDZE$zCHcAdLcsACQ`tiXUe=3v7L45(uc z0IqhOK5(5r3;@=ko;ujl0t4!)1AvPh)rTC_%K)$jb=|?H7Z_029V~mofV%Eregd{p z6{xQY424ZEum<(zae(^r;MOFyxP5uB3kC+%mj|n5FrdCXZWoN2Abm|xC`^gR8q~Q5 z0Jq~%Q0$?gWMNB-gxf(**wO+Qq3%BbxX8p{{lwr<=oGL9^#=mL8iNdIkg&JJU;`Q~ zfFTAnL;=_abs@q;05>2mL;%?6LPO+20W2~^EHcD%8k-Ghv$8)0wn4p)Fqyy&h}RJS zHri{5=v6kXz#7yI3DXTQpl(P2xX7Xq{i2XiZvMft5VTC#uwrwFX>&*%02^Iq zOkZYnabUSIb-6Kz11pV*D~)L!SY_<9N|{ZMZIm0G<;Gl2V}}v#FzUFSG@6W&O-364 z+%W2ekLihz`U^Nd0~k#Zw?os z9%TTyNM%?;WtbBH)}StC*cAi=>S6|fi*$qqc7%liz#7!&42yj*pgv~+xXAGEkm2Dn z0IWfs&>WynXaKm#*zl0CLJ{hfh80BE2K7n3Qv<+7>cYe7 zgd)^$4a<_S4eGZBK#s+XhMRRTO$dW=X5BcmQ2>$S%r*en26c4{fVjFjKwaGeAg*oz zGmjcU%C(I}QL>d)|!Bn{_a?1%qqm zz-#6(0Js+FKj#4Tp98=}?wBoi%&{COv}6}r9)vAmunp>A=K%Gv1Hd+_EICz{zOYFQ zE<#=I9H1_D4p5gn2dK-P1JvaX8_i&&)a4EUS9{ZvbkmXn0BcYmJZwdS0rkOifcoHJ zY8KX@K6n7+SY$($Y~et)Y^YWME<(NZutW?4>ZRuZ_0q#SWvoHH^Z;-zH)O*N*#ZD- zP`5qofP+Di+ilMQ>b8e1aj*t;+XEm?j|i!XkU6kDB4v9-Hf)-Mi%`ct09@pFMC$Q~ z9Ejp$4eIIV0QL04wmMjYdir5#L#mCmS4F17wmMjYy8bypUH<@Zkpq!&2O=G?@eVFR zV*wnXu>b(1rIF#sBdr{`5$U`UnG1XMU>h`AzyTU90Dx@_jS3zbW#+*0sO05QncONN z8czU#iyVz|9F59?!5^-L1{gR%0}R|cA{t--fNji(cFlU{ znqpF#VzOb~2-cth7XVn}dQ9r|m>h0>7mdIGz#1j7`jXgC*r^HIpdlFmSYuv&dN(eITbf1#KLD^sX?$X7d>Xe_jYfhvKqEo0 zg%oZFjRXl>NF@%orEyzG4Yi@6HXQ(5gvN?EKx0K5ps^wj&{z=w+|sQ!$5vYw>`R4> z(%=yXXz+*wGG$03~2BOwz9&229ID<5)5eYNZ86MyF1}Q*vblP z&}b3|Xfz1`K9-va(#?br4iqHn3lc+N_bY6J#+x`m<4v#~7S^EgCfK3`0~&AQ0F5`n z{#aOp#+v}(cFeS+nRXqwdBI}4VX@u9f#r6?as^-;G(-g&7|;+E2WW_j12ja%0UDy> z01Z)bfQG0zKtogjaMMeYtR>3UUbr1JW(E7NU_fJ59H22P4$znt2WZTS12ksE?H6`1 zDd=EQH~?G=4Pw1MZ}zI~|JgGgH>@|w(VLV70Bg{w7OVop8dH)przH0QfHi2Ci`!ys zU2@90?83TZA+)viuPYwlu zHE5`e12j|yfHd8qpW+CGEo?BD?m*KWIsn)P4W@B`2Gck|gK6AmXblcWgCh$7wn3w7 z+jfFAeGmfCTjbU>iG~`kl^D*w~FU%pK(efHh7y z^(UO6u+tmXpkY4%SYvQn=HRqGu=N|(pm9I|SYu{d=FGG{uooQGpn*XESfescUzrvP zi~O+$jT8dF8jWfC#nY&>;tC=nxi3VGSBO1b}T6rW*>=Eda0vjU{q`#u5SG zB9qgNlhY#r;371*2rI8Jput4|xJW~~z9Bsn0M?+o(+O~a4es%;v6 zCzC zTofjpV?g7g0C15zx%xY~p|HOm)}Vn>09a#Eo_gs0U9~w7U0v!DYpQh zMozf}_%w0~0M}CBG8DKh94K+6mALY_CHgeB$^jZ%1%PeTxb!uyP}s!}x0D83IY5K0 z+%kU}Y~_~u(_kyN%%28ZVVOU!Wq-bNe||2v%%4VI0bq?k`=tHZClA*B<95(+EP$rK zGpn9C9QO)YDzMT^z0!*XP;uFofP|KSd4Q3bSX}vlj z)F!Yslh);1U-);T*X!iS4|?H0TZ0$0?#I4r^Cz#n*Y5{})&#J1g4pW%favwYDu#Bw zp{@3>kZchjq!no@qv7iMS+Gz3JA0Ok{h(~>g(i=pX05bnxBa>&6qIF*q;k7Z8IisGY){z(Xxdf zPL$r$zD3Gz)u64)O@SM*!EWB5tfa-@gx!2X0na`5)%di>GT$O?oe-BfA?^t{d+YCS zm{XDRv|F+}-MKscNsxrU-L3Y1dC^Ad^9Pi2=|q|CuVo|4StElVay5WyA4) zIlaB3@yKWYCDvNCs8!33YU<~I&-?wakavh=o)-UEtKlP_NKT}xPNXskM5>7dXA|uS zWH{0b;$>q|;SI@Z1O!P(*z1hT|0~-Qz<}d1gkKF#n8vJLS6+S7YHfyP}Pv!H^ zzdJXq`=;B-Jujbo%DZ7<_eWD#|EJ`AvW|9L6j~R>?*wr!3Y`f+;yP44ql@q1(l@mpfUwj3ZNwgwFsam1@#DELMob&%G;<) zMO6aWpNjSi;8H5OB!D6(Dsu8RYMiJ>08`V^)O22>H667I;C4E?Er8MtRGPsT*_MH} z37{tf^$1{8CK{E=7nz@l<_n-P6EzB8Xciip#TQwbg;omS&usK(Hm|WN8?6#RV>W6O zz}akcRsbV%(1;w~#^M~bSO9x-&|U$Y&q3z}Fd`R?$mMO+<)S(P)aIeuJYM5a9y%m| z;Vv}X#cM2ap(O(7a-l8(49rIZ^Z6n(^3eh+Xv*W zvB68d!Ha$F;2xw#LN$_Q)!~+#rL7Y`!eF`Hv0VQ!%uIsWBgE?B5Y^%kR^NahTXua` zzT^WU8Rw7xtk(y0W4a?niMx3#r;=UP46{$o<(vLCiY9d}EHIwFTU*ydP^=a2qdman=cb!p~0W$iM|HX`-h z3s&6=W-Wm9XhgDBlGjS?DnRIgNJ`^XrSa@76n?yOP}w(oKPE?d+n9FS_!u1N?1x7! zc=3h(Zb^qdqr=W5khzUmtB~XhiCwu@vs6(tHuwF6NM81SnSH5mubeyS@Ac|W3BRa8 z7d7mzyVW*3^;Ue;r{qg^oik&d^GT>5gZ)lvzmv^QhM6YBNMop~F_azN`45Jdm4%P{ zl-$&Z5&rWZbQ>+EjTU||Q)daPv#^u)Q_E9trQ61TMoz$u1m_LqBgH%Q)Q0ZCw$F)V zxx>EP!A2rW*Nolhy7;+UaxXdKUh>n>X!uMdZLBw{>W!@8p4g91{IjRRUFMoO<(ipU zOUFxk%EzAjoO}q}L+X2oeRSc9m&i#=XwU`aJPvp>V0ds; zwOjJO_xtRmz476}mDl9$Zhk|JZm8K85Jb|5t*%&AS1jvSr0M3HqbGg(C7B}HY%?_5 ztZ;Z3wAjooHg;h#n2;z>NMwfzfihzCK%DA89BYZ;$FGa;zWUf#WVq2D7}KuIa3w~9 ztP_IRHNoI&Nc7bZc3)v|-uB>mTYs)02b208Okz(G*67U5=*(pgDh6kBQ_kkHom$@i z{K21ZKk)ijq-9q$=!){?K0EK4b^8yKzaqz58007ndVs5DLXd7k5Pv@{35s13lnEO7 z;hR3*|F1P)k&Aa+i;iopAi>7kas%6P9pG09YHj(l{r%vtNdva4(RMZa;5$_r_{#0C zUUf^xXweugJHOzRaGy?>>VS(~qy@k2op#~5fNzN8x&~d>ur_uV9Dexy&Ii6B_ieo^ zrQX#anl$jNud@MYVB~wFGTw_>S~hBfZokm2Z07=voQY zN@0*?0D~r7Sd%Uprc77AbgKR3;q$(8_gR*d8qO$B=!8M!GG3E@7`}4^Th9OxFvTHx{KIL;2$qM@aMHJOMY~F z0=(37yx8jro1Ye7pBB&;W@&dl{+@ZM@7^ED`(j#3{InGI#>Ai^#a5BR8~{-{Wq&lS z*Z)LXvdSB+@@Cg-LI3(!UMha%C(`h-zhXDCzm1F27ac_X}x3i9i0ca{<9DA{m^j z8l1{*=KYUd^P2y^`R+0|ywMGBR?n};uHLx2e)%utERFY3kN4qSE9YeUIr%Y|f0epo z#zRxIzx_&7XZomTDh?{##w8JvOCqvhR#lGiqgNOGKJr)6k}uJh?3(=j(;>&0gUf#< zC%PlR-Vxw}bA-W(fW#94>_o$aS7Kt4Nj1sD9^#wRet*)IKJIrS>G4NB{_LjPwB%`R z?uJ2s5J{~Us`X+WTTa!;#H{Xix8z&&E&Fo4X>48n@rDNnk`fiZsKS@MCihe|9$NKv z-+|-;bVt-`zLQ$PR*-y@JMA~W zovVis$$c-M`$}g8acm+vpR78s?AD_F;CI5voOuDPy2u?Sqn<~b{~1+=Ezax(f`|I`dheV+Cxq4q3j;I^G?tw z0s2a}>Uo=dUidORkQ8wsiM27T^4ooF>E5Hs(=)>h&G2H^30E^WKtDGi89Mn;{eY*U zzKb4B8a>GiP4Z%g6IxQdeb`HXx+UlRH0PDQ?eZ?RJsSK%y*)auV}9f*mMdRFJER_C(r;eOK_vBqIRV~J#k7uunC&3{~8|MX+3f4e1>ews=p z#sINVQl>6TRi~`YY%2dMCHcj3?lMEX&=4%*b!O#*ve<-Cw=kpFb&!QezjT z_J>If;0q__Z-l9Cgt0UGWAlM`e;J!Uj(mvGl(H(%4+EM~mIE}|D+g$@R}RqRrW~NT zOaXjauI=k8e0v;e$Q>`AJ4$B|bN)!-caIJlM{b<@OhS+ZCJz!}EE~KW!cKeAhVgKx{T=ZZ@;8omc1mwfM2Lr^l0) zjMAb}T6SN0t()~%;5YZEL_(t^E40LLpytCWtG$qvnd*oC>{^sfnKnTkv%8Sgb22FP zWDsjC1l~xQmH<^t09&@__0o>nUY~w2fs`4a>Kvas0O|p!2`RH&uUf8W4_@HWEs1L^ znK%g85m5I4HIQvqe!+E$?WSJ zCdrWo%t=(uNo1;@9VxARbi>n=h-ADk8t=>A*f8ydNR~NO%baXHP}^dT_SyA+#pFOw zOUBd6>+#)zZ+q{5x@a;fvq+5=DdW{YR!knVpm3jCGFgizE1smFKaPKzUhw%8Qf9ap z8m>fonm?{p}x%J>bY7LW#XWUD%|*(rE;_o}Klo(i5yBtw1CP+xW*-i}GXdbIE7Q^_fq;7ppJ z#5rO4B`GsVry8VVU&Aobib%$#sK%wR3m8%L$RplY9xWl()=6lcWWKPtW&733DW&b@ zN4mdQRaaucl45gcv6($1Zje)K<{#1-=Fk~}#td`L3_)XuIc$fpHS`X1?hf-KaHC?Q zP3F)h!A6rgr%AAJ%WSwM>?VENoOs)u#o3r)G0d>A4?JvirX^yg5*fvy-V$1G;g6-k z651eu7E5T00QOqK_bQGbY@O2|uMj0XSN z01cNdw8@1^CV>5Ik3Lz}|IO({wb4u6s5}Z-b+2CDtIvi-qv2=wbbr15?djxZnkAuG z$}{+P^iPi+EBJ0YxtTWRrfke*o!YXOJ05&;=-}yY?=ezuP=;_=wc4CiZGH$`&lsFD zN1Zcg!%CdjJ<~Z!edm%?=aSe^9 zhXd0lNSQzTsQy&a2&MTqy!A!cn=?r3hegE=i(=yxOX29Oy5U1-kdt##t3Ih^Ex@X+ zx%SrFe&DN-UE97J`S>q0iRulF`i6$Te&-!==N%8hG|2odeRFE3>t>ObRQcdP>*&4C z^xGNMFxkD-x-iaA7{?o#5EnBcj&-lN0X1=k8bt#>g^1N@0jg=ro`c(}6U^a7XJ?UX zZ~);ys}CEQVlhn-9+M3g(*_0f>#VS3M)bPdy4**zTxo01$r+y)JfbQkukKYbhE*|a zJcdDejHx_^eI7#3LYlTtlGiD2=7D`T4n4J}pp=~YZpqlKd^`tqg?=@nc6=%6h_`9b zHlZV)Z#T^sI^ym2sO?I>i;Z2dM_o|B-$frkQf)m|N*b`m8*TAsZQVAZ;^DSCXWfz} zKh&gr9;Su-ujb?2yg8)I5N|X@Df7;j9XlqS88?Rp9a|%Du?M|_Er{qJ&^xom> zz8}q;Jck_L@EqIloCiSi`0gJ^W@T@6o3HoL)cY`B!!P>p^G`kbKpClcf-joj%f20Q z_WHbc{@o|tk{UItQL_uVx$515M>WN6$s~WxBxQIKtX=-%0l%6uk`ai;dtqr01~lHw zt>mHcUTzf*jrVe^aA>@jTZKd8z1#{K8t>&6yU=(qOfA6G(s(aSEx>@rdtt>01~lFa z3q&xW@m^S%fdP&8!a58LXuKD^$r#XhFRZe_fW~_vvVj4O_rha|0gd;(17SnhyOiI8SG~NsIhB2V=Uidu1fW~{d zNv|~C%gs-v@m`3T;UYBN3&ThZXuKC@B49w{z1-YV8t>)imeP1H3@dRF8t>(%lG1oD zH*=K6dtss|E<)qIFk=$~8t>)iW72ppHy@M6d*P!A7oqW9ZayZB_rh#TtU=?w+|)@L z@8zaW(s(aSoy0|GycdRe7|?hxOjp5x#(TL5i8S5|(+#l(jrYQ2LJVlU7rgQq(0DI+ zPB5VHUYJOO0gd;V{2aq(535khwU34Rr?>Saq1wHq7}r+;zX3f1eVtey_VrDOICVHS06~@qJ@+ zM}F>HQeQ!Wp&)^OOZ6rhdXpH~_*9tju=$m_q%WK2hyPaS|7z4{N3<{g#x3dg)pYx^ zSL@sT-n^A}D`Orpe=IlSSnktM27}Jrkj`B8o%8XlX|YfH{C6HPKgtJ<@?qvbXviJ- z;_A_E$v}h#D*Ktl{$YM&`9H_H%?}DO4GLjpu=%PGQF(@`A6q}v^*XE{8sx7_Fdh&MW-I0n=FijSI;RSU@-(B`dfQ$AE`j+ah-;`6YD z%I7d_XF<$2g{hjt*qsWmd?KkzS5+yqVqp6lBDo!; zx*fzijmy6+em->7XDf;1gc_YtI=1`|^#e;reeIT<^+sov5E#6VNSS5%s%80BxS3|W z`p2w2Pj;^)(eR~4!%`#v@GdoGE;aT8Rjje!XxOi4{HHbdz4yEgtBBPV-e`q4`=nJD z|L>djmm}Sh>soYOn+rxZWyn!4^*`X2T=YQ~ec1VX=wQy2yvNS2BImC;C#yM!T{!rp zCH0JpR*j2h=kKd=uYM6!xU-x{W_h7mUQ7b3<%ndeLp4>|j1o3$a$D1@#_8EZ0?Rsy z$If4uucnkqptDcKq`2@0H|5 zKS7NqsM+X)C7xFtJ$G&__|DQv==`b#ryRc;5yQ7Po8@P$^OlL~Y)xchKZ z=INw)IvF-s!=P0swF+COUDZifbu#RfhBamdNVAkJ%P=?)ARP#h!DEfV?EvX^fDAj7 zVNj%(iu5wv^cbwxORM!VIIJ-^sFw~ZyNh9PSub7I%doo`2BQL{QGqh-E{4I}KxuBE z%F+|FRl!BTUu48aAgG14H7G|1c? zvE3kTH^^{DV2!&5>8?SBX^9w=he+iiGR%j>;ADt&GDPNf(<(DcWk#7>MzF^y?J>$Q zKMWVSW|XcOW$uf!#3YrNWccF58b?gh5n+?2gQ3#FP#NaIVU49>($X*)_EW-Of0(pC zOorDB2KU3H`(bP^Bn-;KrSfnY*27@X7B01g%iNYjW6aVRv&?MBCWT`u=x$vxNMOwTV#l#VlY;g#>z76WP`yRR-4#21{b3B{4F%W-w@tky>M9aLr(FCq}vxBZF%OgVI>3 zG**U15EyKYmA1yp+|C@QW2MuvGE5)D8l&Q*QE@VOb1+yFC#{K-!JC6YTb$GuCxbT! zgF*4qpm-U)IT*~3m*&UI;LX8cYrM2IUWR2S7<9x-9q}?upTJ8*-0|@Hf~9hT9Rb$ZG0(7x|AeyZ{vx{(!^w$dmFDwmewT8+}n6xva~N*=HABF zlBH|OGWRwvbx5TSnR^>=cSzeEGQ5rPv0QaXR~<5V*)S+dk&04e@UmgBB1Kw}B7>I= zgIy`ot`r%(Y#5wOkxr(_Fq*(%M5;6*RR%8`2Fp{W<*71w*)V8Kl^RoJ@UmfWHdQ*C zDub5|gHcXtlv9RpEDXw>Qn^zGFB=9;PN~T$b4%^dIi+(>nOj*uJWU#&CUXnv%hIH> zG?`mBzdlV`pC)t5dKJ8*MPy0Ole4_48A-JW@SpVGG*}PVXz@n+K?%O z69R*inbOHj8K#P0a4%E3mnnmDkJ!kPW@X9X+{2(gORCS3VPXRYJy}vumJHrL49c>l zvTPZ=eHd)dmbPch;O)bpD_iQymciSH!Jr&zP>u}VJ`758q|zK2ynVz*jcunP_7K#J`85&N;7k1_*%xGI#;UBmBIao!Qou#aIOpi9%3U;8k8q< zYnn^)q>?-tmM~+D$~>tuPX>=61}%9~OP&nw8w~E}N%!+)@EBq++a=9*$>1@>pw1=L zxn!6-ib0!8YIDipLd4*vOSR2Ot?nMCt~E#LqB>$YklS)fJ>6fe@OBbIm6+dABmjeeSq$}E|+J)aNg z?sKu4jGvb#8kQ#V!^;MTp~1mGuVMa$(Uo`HMrQeGW+~2#;|~XV&7PXOmQ;L3gU%?E z9*QpXes;cpfm?FgPjlLjIhOwU%(R8StSfg*io8*gHw)5l86OmI{rpL{O0{@=BW8PDEXM_N$pga546U)Wro?E(L-A(9)u_|HN? z(0LQd?j+UjBqoWuIB;Wkcf@)ksqscN-fT2(s5>`x^`oilN#Lx~S6!*NPjHhetdNlR7GG+rQb0WxkLYY|)FH}-yc%o`}A{$}9wnR5=N^N(k%qYf z*c@rtEPySM(OV*!=L#3;j5Kr#8eNg`U6E|&FV+|wWf-iaYsFwlRMe2DWH>xO6q!9@ z#EA{0sb#*X%$FVB|9QLaXMX6jkw{7rDn;xD$}V1(eV{SfEg9s61}Q$fpFV%%+KKnd zHj=A!%oKXe#Qb6ytO^TV6~+L3a}o1H<5WZA*sOvd<~)~sK4kPJBAKK`leEkaGIv1p z>6N42t|OA8e)!M)232tf-+Xk(Y`0{qpJuD#-p?%T|JnNa>dmCgaWy)wJm>*uTsxn+ z;oM9@5c83GzOp+xZftW{YIE4rFdBh(Br(#IrfN!K`v=s>eK%ZrJZ+167OTT>OSwI; zk=qW_Z3jDT7~Ib?+*jt-VK6Y;G%%ZKz$Y}RW@WT$Wi)%r;FUupce7P@vsvf2^Xm^B z+xp($;+AO9UBx>!aPp}~1}xP6MI_@SG*0m{G`zR)gHNWV{Y9S4LNzKBybQxb!iI;W zawEptkg(d2RBpuB6C(G7WWb2=*>hVb_R~$@N~&3?#ea5*yVDO(^3V0FCz1*N_|Fb> zK$Fe>QF)wOa!iemDHla2KlOaYm>24O@X4u(j<1Pk%d0WiA8p$o%`cPr%NqZemDjjy zjlU~^ikSF{7^ZPJ?TWhN^Nsbyz4D{_NA~z*+v_E?UNQ~aSbg{B!hW$BH0lx>b$PIE z!C9U$?Rw8M+sLtWXi$f;NY6a=R7%1}Ke{Dre9;=En>&#H?#Rhs8`L7>#M(}jN6pZ&_F6)=dWI; zthm7y4@tESN$n3`%6C?O_1w=Re%(V-VuQK1L@s0ZL?z~d9hqPp^KU(Y0`Zdibtw%B~{*A=^R1N+!*DN+N!6r{oCLSGm zar%D_zBi_k7`f()|Lm!oapK(Iw|OG>>_sWp?Lym)uC1aT-Bkg0+(ONaj0!}f0(l#A1JPUo)CQtj z0UQWK2Ly0A5M36)=pZy&NTfMG2+bEjT@b1hKt~Yj5Wv7-G*C#jIW-tf6+m+^Y8Jpq z0~#r0*4%DD+XZmffbI&QJOq`8@P~gg1f3K>cL?ehK$#Jh8Tlf6jA)Mlt{Kra0hE|f ziHR?A#DtCr;9w{^7|Lrb4MR)Ac(6YV?H9oPFmzu4<>9D2oG;QAj@kq;#*D_8d5ukG zv`GM0%;<^$iY=&E$j><0f+h=Ky#=ioK&=JU3gEH@T^7Jt8I2W^Ev}T&N&z&;s6hZ1 zWpq&hVu&2((fF4H2k80DB_P9s!(*KxYJSHUga$z_3U(Oh~0TD-z8T!1_qE zUI4X`s8#@Nk*G}o?UATm0CywNT>;#SME3-+Itr~8vM(NwLdOMA9F2;F+=>;^s6qfu z(WprPe_GL>LK?(%R?(fc-IOzX0yUpgRJ%8-wl&pfnbh z3YinP#-gnPI30^l3t&_n8YN^sToZ@Z2%sVkRS2Lh4z&rOJr1=CU{E|7B&0zc9FGPI zV17KBFMtK{Xn_E>#-ptQ=!i!h0vKsSBZV}GqikrD0Cw8YP66z)pIFem{H z5|SLwOh7XQP@RCP1<;y+S_N<^0bLTnf<&}H0NWDLHUXSVMCSxh zW=Caqz7Lw6gk}qw0!x!nsQ_A%P>TRAC80|Kn3#+v3aJCvB%?I~*q4m<3E)~Xx+Z|$ zWYjBwQU@v(@&ImkpzQ*<>OfZoP?Um-Quu>gk%CqTU{?y-C4iGD=%fHfq@oc*4!`B8 zXt@9yQ&FP;&ZeTX0vP2)qnvy@%AKfO08LKRB!F{HbWQ-n)6noV-bPs(Digr^G_+m- zt!b!L07KK!&~)BLT{@~0z@>C_NdS{G&}1PqUTp@d6+l-8>Jq?^Of)2uuVq#ynk9e@ znP`ImPG+K$0=Son?g?O47Mdj_v8&HQ^#bV0LOlW~%SL6{d^@&hqwNCd%0^uR7?gts z3Hjzqb5N-Ow&$Sj0@#s*b_n294mu@(LAhvRePUfWx`yumA?-p+R~4 zv6SSY5&=}^p-KU?NIp6ufVO#Mt} zN1iOmYaye63lWA3%4i0h#H37Tj;b?<%|wJ~B#~5ER8`8T@RR?%<7<*mxUC(RjK`Hh ze#g!4NA7&!nZ0BL^nv;VHW>g{J6o4LTlXLY>mjN@jPG))b}4I}HvKa&;@cme*hdDV z>+|B*=Vie`U~n+cb})~PtmiG*AMk{xU>`BktVPXQw$LQ@#y3k6e_ptcv}2?O|M`*F zY@2nqvRRn^k0ZZ~jM(NjGDbpUBsS!1TC;3RQ(?1PatfhSimwJDx1{1ii>gprC9~k$ z@85p(vpcP%;{SR7&&suZfi7@?E(K1&!io1beOy$upO{$Yjg~3XBLbd&$LzXkJ3u5g zUZ_U#bV2NnNCw+fgKf+q)BOCBCAZ(sK1d{`{`k*k?xo2a=XSih!Yyg=Mh(ic)elzK zZiR%dJV+ce8#QR7u*P7X-84^FW3bI0wM|)4fG@>)d(?RaJbQli{gUkBL*%Me$#Rv< zU$wn*)?USh@OIGoH%zmu50SQx@IoV$2|xF|?!12K_9?eyjaIWpSxO##_?xdfUw!Ye z`^de}VC9^^@*E;*(W_dN$w=VmC6YB()fy{vU_TzVd3K`NaD+6r(`D;)F;55v_g(S# zU2ILmhtp2XdMi)YMy}^DU-d9w{+7NSop3wa1rcTlq>}o!+EiO@%mJ(a^5u24PrTVi zB+Iq<&+f+ghfL`H;IG=qbJ?b|x9R%94f9FI>Yr}>|MJ$ueZ-^ zCuJ%lGAbh;gEEJ{u7BAQ@?-}obKcA6ymDsWU3`4c%!+Lt#0S;sukQ3`P6ce_Zd&Z! zv_4z}Zf$z}+Vlrm1a9o8mIobg93^L~EymCm!yKR(430Gnj%DDl5C8h?p|XJ4E$&2y<<#pC0gO*s0Hs zktV&SevQA6=Jm17>yvkWcCR*Te%XESk`WWr?5b&Y)+0lNk4QG>s5a-Y6AzI+BDtHR zx|_r9^~qo54}EA>d?%6I_VT&y#VWq_uOsIZjz8v>T+^Uy%JaXr&yfNDzWAwIa>WN- z@nLt%s~-=X^4Yhu+>&`}G*8Xyfsm%V)!C|P*{m;qafe@J*VwEsa{qMOQ@ZVJRxbv< zc1N$hKit4o+cVx$EqTB+{e}%qc7j572V>!?Lyui&%d{BupZTHLg4`$4mxW+9xC}GTmOeKpzrKsy zc@q-@CMt8cA>$l5Lro@ClZoBfUFspJZ#RuTP9!xNRHOJ`4?O#+_h;MGCy1n0i~sDX zW|al3{q+@-TXMorb3%#!^|SnZ{zAvgZplS&Jj0zi*jGo#XQY2L!!2=Wl&t1`UVpj& z|CKIu^ATD!LTiPqI>=aXs(0sMx8$4#ol~NZFrA6CY=o>DA+u+%=H8aq)27FsBu~pd zt@@sp%_POAWOZ)x>fC-1s~+jM{*9lvzIKwFtl4?y*?G)J=eeyznx$DMNv}7_TRlmc z&WlxBOi?W+7o1NFmW5lFh4+D(UjNrQAk5LR`Xp)EJYO_ViBY}u-L!+R6$PInl4WYN zOwDez=Y8TMG?Qaak(Qj3jOUaI%x^YdDShTt-6?W77yZ>2{n^REs`t`j@1^yJ{`W-r z#HYTmee5)OT(;U%whE6+qutS{JT9+JT6+CK@4C|@u-6u5XbWR4!Js`XqCJeA3JlhU zhpr80;av>Yg~zW8XOrSF*ccwVQP9{F9=}P@=n4<*5;RVQhn`Zvp!-ieTRp7pG&#)q zzUujkR~uVjV@+CPeH7lxFuRAG#m$MT&56tvfAmdbzwwWl&k)IWU$k9W(-FHs-Z(bh z=9b*?Mt8i~&HwnU%tgKfzC06%>shJ`U8-Z^5^#-h-;$p@1jJDBt|cMP4muFl-P95|bsbvBoME@d4r*H-P(oF&(;L_#IX$l$=B zUni9fIDVEq8;f1`#V!^)ANcatOGOLS=SZ0fe^jAF>|mN5kz9{aU5{bc`-_g9tFQkM z?Jjdjiw-H<9uIL|^8NQu``nT{YIH~05CJCt5Nr1{RQEGjHyAef<;Ug*pXm1T$1Uii zs_4VskuV>Zl&KC>RR^+=%c3Ohr4ze5dx&I_1})O);iUMFOig&TILGSeUb*|+$a zq$i&6yHf6!3{?9JRI^SkNAu&ek6!6KPagW|(T3^KRdnj-Z~m&T>H?LF@Yjq`PGrZ5exKd>r_Tiv;A{(&+XDZ8aIXUezVi!x=SNO- z69uFv3LvXkEg-a709nN`0m)+m@CmrUUM8+K*Od1l58vTnxr3OdgsndV$(+(2$n!ILgd&6cI_V zMd2Xtz2#$g%Lh*bmO(BLS4dv@1d_SU2t;t-*l&^6S)Ta_EHjarWg?;;YpA#`d;aO$ zPoP}2Ro7&zEA16et2OxBRcZRbmw}>v z$L2m>eP;KRA0Xr3F|)iwc<}k!e_ac<9RSO;vU9Yu!`stJu5WDYPQCd7ZUAvI{o{m} zeL#zM8K~?su!nWfzP$=Rts5o#6J-1mPL?B_@DYqB(lxB*a{|CJ{j4ngh;!{24q2x~ zr6&Ibh0+>zfxx^&2OiWcdX$ zp68~R@C)RmL+n7L0F(LCG1rJMDIct-#aO+?*cv7STSp0w1Y?Go z#_%2lY;7z^W|a=ZDjj&vD9#Ql6cu<0w&xQE%O^xJ0$bDt((^`v;f(@Z&z5Or#;RAc zeuHFQv#`8ofsdk;6*TYOd!h3;$UjeIm7mI*!`!BJA${%7<+s3k%2>+av1Go7|KovX z*FPY$jqzW7NbK7PHq$kZ rzzHmgsd0wCIc@{%m>V27Ij(bD;ke2HH0UNm9m5qQ_EjYI4FnqilntP_1|2#Zj&-=aSJLlee?t8xT-LuJX_3F{J2x73`@U-m#$Gs?m zAdj)xSl{ zAy{2{M*iZt5=m3lmOM-S+g&e)pn4m74PJRUhlVLFzG$Z*|H<3#7UkLL;j9ZkogIO-QZyA6?+YPS+)M}`cw;tl#H5J zF9TidX56jWq`C90!GAhYD-Q(Rere9RRiizcBh{gyE`fGj(+@(mSIvtzG%$|6m)tbX zD|S}+6+?DcjA8Eud`YnJy;T;}iMAi2cmMV=Y7Du3_0X(mn|_*DAImMzsLCI`f8;;0 z(js#w|6L6UNd=zA7DujnJS1n_rZ2I5#YZ2Nm`B{+9L-febHdlh9veO{vAaR!*ZLMi znZ~3;rmI_@JX+FW^QAK2#%9K*CC{?Uh7!NqDLI%K>`!(3(Vc34&8L)s*Je;|Z&Tye z{oax${rkavpZuz)MGT|nkC#qurF;wBl0S3nn$Ck|)r_Lk>x~!G`&-Y_e{jcTQ;4ha zc4HZhy@oqq=WV=3PhBhir$2LO?!gRqsdcq`o(>(m{*S)mk*>I@#TDvGwDp+iaj{5` zrBRg^X&;tO@wAexJLi_<6~A&@h}7OQGltq#eO9dUn3r>F0j)Bgu_@5yqN$eA##+z0 z?6|kPw_7)1eUfUD^G_~+L@o9_qqBOl{VK^4+4oh-dhR_Lua_~WnoheV{q>y3*Vw+T zruP2E${&maEPD6L?9Cc9;B4N-PONBTG_4*w^TNpa^a8o_S{=`9rmSeXYPi@#c|*Hh zXN}#3M`Hg@Iz6=$>j?6=>{Kp34}CxD-ip6LVhd^4KpT$D?{(Q+{L?b0l}NqpsdhZMIFsZnpyqq`4oSIM&~coaE@#?VH{H z%)k73a*J%9k!xo86!ShiuUnQmRmD?FBXTEvws)O1&r@IuV&$*<%M0*m4dG%%F-oYctiT^CiXP#s> z8E$3!l_n}x^%X0WBvwCP7lqkTrB{Ts&f_MoQ!G;IlKnNQHB@?yfz)ihD;@NUO^y~p zK0nUAqOUb&JKnxk{oJUl(#$+Vf4$z9Rg)}~tRzOf0yTap8U!0sB2LG-F1*1O=?u~S zF!e*ik{w#K^;Jo$gW`@Y@UeHFzR{&JKTdC_ZeVihsNrwr4>K%7E~Xl=KgcsOwVk;k z`Snx!%ukyZZfv{WlU!(MbdK{>@z?I{_PKczE-GlfJDI9}LbtrA`HbkDi^t|)ey%;e z-qpi@WL|Wd*+J1sv~AJcYrU)8HwVgHiC%47D>LUuy7u* z{NwjUzw=g_`}z&yz2-&6aNGpdwQ9-snvwH%X;38-5~31J?yfLG@(1=ySSLo@*K4!9 zRrSDj|HWwOc*|^$1rskkzMj{a5Y!?^E$dpe^F^?gfpO6!^jn&pThnXx_o085F#|W= zc$6QG&6;|-WN1^|4#!p&?a@D|V%cvw<5hwo`=H*Rqjv*-N_+J%-gSD~Z|i&` zDkr+JFY;5=3X!6~GyWG72QPFRM7XAKIXWBsLPBh-HRRhT&YM@&;U8v0&mT6Fh5sb0CgdXq@0-A z&3sP}>XER5$EYmr@=+JB1IFt<(BR#b)vFhRzot101n`}B1P&_N=(d(vFzN|YMAJV_f z3^%bdxUABu& zy1R6iwoWET%6Zn=RMRyc2OZa(J((OEt~BS~1N)erM`rI2p0=u9FHCOr&FF=_6Rrmb zYqrpTj(9iiwvS4gzcRTq%(JlOv{-lYUgg_HPWtz#CphQL7{y*|?Nwq$EXoW|z5n-j z{}f|`l&#mAjJ9|-m~6M1KB&2Q;h`@_3$7e|ML$|0o%KztyshWddF z_IIU2HhG=ZRJo=4PPuZoYOQNd(fs2L)Ex1% z%MNZemo1i-4_)>byYx5KTcIys{6wp4FEvlZ<%MSbzsD-#LynhYs~R)34@E5)U6~c* zHerR-63HIf;e^k{w1-L+8k$IEWxlh=ymqX&_xjey|D{X(*%;zuKdZ?6$+Wp$H&a%m zb~CwJHfvqH2dA!{v+Rn61;n-(7dky|&qx`2KjxfN%DQ+|q#^ znIB?G7ykM7egErTFWUMh);sw&&M~>_txCa%G@`qvD25-Qn^0#5oQ_#j&=RmQ}JS}6eaqv_I=8C z(e^Ggv2}@ZUC9qcw@gjxFg{l!()8+P6FUS+x`DzURbtZM}`KCSWm zsoI}@Mg5VI$#>TV9bXgv!~gM!!N`T`8(ZU&=Xr{#8m=<&C; z;wSzL?K4>3X1h2%d*S09+ESF{vrd)kX3ai&cBsJQ+lmZN?sjJ^rFpG(48v^QEFVi_ zqt|Mbk)Pi%VG+3kAwT&4$n78om^s^JoHuiafLGb>%qIL z^F{`$Ot=y0I4hRF(9gPcdVl4XN9VDNpA}t(<<>X^4c;%FQ_5{<3(_+8IYiqs zRjWnE)pfpVl(E}UxwTcIOr6J$`!`vi{A_AFufo1Luj6Rs?nMslJD=H4BEqJ>I^Pwm zkdgI-}$iuG>+?T(fx4NB8aa_ndzmV~4bZ!)E$=S4VyK{Bf+?_^V@$ zF=x$-cojv@)F<{jyJ{1P3qK89zw~B~H)EO0I=`}IPxo(i?ztE0VxbZ2syJ|X)v$a} z$mQV~1*dYw22Co<`!8|de~>S_WNN!QkZzfc|C=ekpfl0b)r++t(ipQ1anO4D0l^q|b=H*1l!XeU0h;%0%Y- z;J8Z{BYvB8Z1p#9w~sZ*d*ic4k8+X23R_CGj&1x`yKZkHa)KK^a(F|;2TKb}_sgn% z+qET&BLj<`2b`)p-ZAT4!KaZg%6}a~O&ve}_#0c}pk?Z?L1X&C-{GgDzXay|bdgj# zvi0ENjdo_k@n@bvz9}t91M6P=F>19~>fUAZ^23H~(ew9~ zY9@7FTAO?JY2(v|Zi{<=x=YFnG##9->+7D4%DR?e($U-CpHrc+lqss)(6~kK_^Cx| zwISJ)xxw+=5W3}Vq_+Hy_GIdJ*YxFI^+S${8VnzMWS%H0K6?S} z@`lpU+pDtcO4?Q=JKF1u*r+>v{(zMn-Zhwg>);b(iC9-xW%p_+wYjPloXQiI1J9h6 z&L7d}J^5)SS}Lo)G4r!_DK%kfj6+=eq@%H+S!T9xC+fS)YNsb1+il%l;ou*fp!s@` zv!}&8G|2kg=Jg73Yx4QTjJYRN3mL!)t)ZPcV+i5+ya zF0lj8p5u(IiW!O)heX$fQGJUPW7T}NPg0*H%DUk+S{CugRrGImQa-bs6|iuxlthMC@-cAL2yQ94q~$#%#+Ff>J6*f+OXvF1{hL=etvfR%WIH zP0Ul4ZFPpX((_paHNf1PIr(x$iSzdkG4|DR@ZN@8Q9 z!tZD1!`_S4w)$MC-Dw+B`WFibNSGJbD=~j= z#Ip@u-xrEM^6ta8&Ae*bmL59nNe8UXSq{tPwuB#X$O91>e%*uNUU}%e3G!5`z&wYqPmS=KfB1=`kbhc zcA8OkAR|%Hspyu%LCgK`9j|C6vTDQ9gPr&F&)bukK1ng~;Re}f*s8`k`8iG>C-1EC zUVdWR+J^hrbLH#H9sPsnr2bsubUZxQJ^s?WZBeo42J6t+lV*>~c3a&_nbK4+Z<74( zm2%XYr@rBF+Y4B4+gxM*g(s$4@6RX?XPekv3jSm#ce47`&mms|0D&ST>~Kke1s;R)KCGFLuJ@`#V7-!8Q( zcG;wsyTNpKa{Re>s{eWqW*v1&vp0WQ9lGc7B!vT}PgGS_@0mEuD_C*3xZz3eNN{PG zT9BOvWpR8ODspDlDdXGbSGY{bN4EHQF0bJ1DGk(pqI&H=cQd^|$-O5IoId=7 zlWMUz^^{sv$ks@;BRh~(pL1AW!_kG0mG?dxTygKc+|I%y^Z!LHf7A6jr~cZt_(yvy z-#dj!4mX$n+4IT1??C*mjg6U2+yRlCHs9?EE$zqq%HnH1U%ADkPUfgCnppTGPx3R} z^HQMp5fMEndhNRY#3Ooh7pBUoRhsJ#3{bB<3t>vY=rqqf!&F`YH1e{UXK+p|BX^dp{t2~{8$ocm(-yD8kd%BTPuhEcH z^T9>Ltc{a0-y~(O*P4A5?XR`!7EjS|u+VP~uAY~>(na_4vWNZG!_608vwUT@Y~iTE z)U3AFw||>6Lf`yHl~z6Xm-T2}>9qlHRqlr1)fO4V@G2anC@ z33!*h%R+K0wo-V$vej&zXw4-y2N}&b1s}8(haea>#?Su zJK(XauA^yVi)G)cwSh-JoI0brUw7_@(_vTMM(ioyWSukM(P}N1*&K5InzBX4p0Dk% zy$X^#eyVkENBFnhkAcGr_7pcheAA6OE$`fa-t+M7 z%fD07ivLUqESx_2;NBPi_8Nmq?=^3Ouh~xiDdYP0QM1vZKMt$!a9%7ASMhaRA9ecu zCh-gNe=PfP8b5VmK&E@x=+rsadrxm4b#^`5ut`x*#U#9b;&G@JA=)mEb9-cGJXuH5BzD(8U6B3r1j{Z!m}c+0dm~~0ryH9v}_LVJYyiK~+e{Ra%B_ru$@ygWX#${TKZ6AvI5o9)cVk-9s% zK|Xz-X2xnZhG%B4j#~FEKy>oJ*TxQ$DETcnLp5&pq)Na4EE?3FWWGB=YgJ!OSn(Fa zpQ2wBbpk(A9X}~pQDb4scH}%;-tc~bU!Q2gJeTS2o)YaN6%Mum@yuGcXVh~)5 zJhgF7-Rg>E=QpgWE}VQmpmpKmtUFJp4@fPu^~yPYbH^afgoI%G z_wVPT#YR^1!}i!&q)xgwWKez+u?_Iax@+fV;(2ane9c$Z&)}?urnB^Q=bX&CP*-#z z%V@$yE4;g4Mf0S?nnl5_3~^-LK-;TVZ3Aspw{llSN%$0QH7!zIXmWL#;W|Ch3*FyE z%48jWU456+Q*eSI)8809{O*Ut8C$FQ90ZwqN%rA`ocRW_hdvQngf$7D z{(|zDLdl`foi=$iFTNp$iy?af^EUIYALhYo;K?|505d>VjTEum;g{mKC;mAS2i>4C)B%uX76CTfIZ`>cF)ZKG9$aUVO z<47q^+@#Vm3kInV2Wf3^oR*R%HJ5|j8l(E+h%YXlL*ZG3r6{Hj@6v+3z3VM!IWOcO z(PPwM8Zu0qkVD~Fgf&fkEu`*TVN=)EVyGd8>;?nvr=a~5;(qch7^o@vkeuJG^z_@g zVi5JIpZO8* z|5kHUTMV%W-TP2cAL?XiLHBpyov)Qj*xdQSjbNSvOg}2>2beqym>H0{d&^DAoq2bc zaFDpM?sM5lE?Xvt!m|iVhQ1z-R5Ho>XyExH`W(c2jOxNcTsXvR=21Hwp+?7{qL$pe;bkcoxJ=pxE*R!f$cn;M@8rTQS5DFny`0FPNr03z+xe zICVYmyNnk4+KC}HfZ0Yt+bC0@1T>B0W%fGJTVfn zu6>GNm{o?qYOgCkCW8AzoDQVAx{f|wh4FGyL- znQWuiUjxOEBY@XIK|3fjpar~mc-^*k)nOg6&x6E}(}3wsMZLjw^DJOKfTQgHgRdR6 zPQK1TBE}wNAPotmfzHP)!jfaE!eQ23ICch~V0wdtoCiUDFvJHVl$mG2l$!&Y4|UI5 zsb8-N<{++PL0_WCOO%)&JPWRU0i<5o{%hnxP*aE)Vhw^uQK?bX>Cl3a?l{Ps9#8Sq zH0MzD2oB;l7V|X~c}*omoM%DznlNVRNaN1WCE+(YNYwbVyefiR6(OFbEMpzyZGCb$ z{n#NqS`4uSeGgF30ifVK3;Nzn&iAZe>u%&1?TF?e7svYUpduYqLcw_!^gSQOTyNzP zViK<($3dJy%n}At!XPAsXA#z95hcj{<#IS?PtS*V4&pZ!G!;iuaiV*k1wmIrwfS!8 z!K_LONZ=snK+r@clE@_PJkJ8=Y#3DC;!8L8?VSt`5;PVxmVv}FL~|%S3#hB1F3c5= z_?SND^kWXIZfOosFB_zu|&s=&ElZxf5JUEWpu-e&81&AwAgCGHJ0m;T!18I?OEJU>5CWy6Vd+IY{^zH3dUbFk+qKS%f9enhB|! z3@bh{STo*=AqPPBx2V)x;Np1}bZ<^h<%Q34r{0teCW!k1afpHrfpPLIAZ{ned85o! zooarnQ4Bc&h+b6G3%tfW3y5j(cJ`L{#2>jd_cM{yjScfT2YJpRZYR$oEGgO=ILvLg zYtHHARuWW~F{&#Iab*!yo(0c+E~NIKc-UNTyt+vYISTssr=tEq?06RRp91?|dt>8r zXF2OO4sv-cs4o-o1vw7Sf}jgwP$@&L4^h=eI>eAeAm~>L`W2`*&w`*yP{sDT%OAUZ z>UlQ@i5Ux;O+&J2#P#zm!jeXnVbI^&q6KBDii2Xve<0{hD)lB+30e?zCwcFa-YsC_J?4`ew!3!*NCQIX>ZtR2La z$9E1CHh;T7u2K1o3XVs=)uR+n4ka8{4#yXf4kW2UEPR`S4xLJPB54wlG)3qc0~SWo zRzN`Zt;cGQUByfgzLbKMQYJwU+=u`VZx;eRU&Ko^lpixVAbbW(DTB2TdI+F`rCh<{ zkEAAN^Q*=quSGx*C(LOwB*M+hShr&v7wDO*`qi=E&NT^eRsR@M{xKFnPt@p9&(Oy& zBzc}i{}{x{9Nw>BZt%+N9qrN}ni*!szXZ7N0XVtWAzQS}eG#&tcabdcsAKA)Fp}lA zQ1o?Ox|}Z2dlpqZi#m~?mV@O+;x$#CzZiivK(d3%<*yK6<&+7eP3EtwV7gAurYZ9$ zGw}#%lXJ!aG>1|~L(6C^0mdhq=qH*CKOY4tsCWZyA_RygUupPP+5`v?BORuR57Q>{ z_b&iY9Hyy4fM{|VMK7Z)2oOzfpb|GwdHy;8)@SLLr~-fW2FZ#{7dn}r$$+^p7erU& zzZqaU%IDCh@wc`>L#3MNllTe?5^d2xbQyjc4%Q;EScWWrr2>nicnM=7f8_*=fJ`rA zGJlBxG9u~A3e5()COQ{_765TatZDE`Kuy5*H~S zY!W}K0h%tKf=%NqKG;S}mSS8uPl-ELicKrUWi_Fyas5KUZJGOn!2d|3vnAr;4(#MczC0gx_WDe$)kU`xdP#G20EFah=8 z_OYh(wFT^iCPuKQ^7lz#4=0<;p2FYZfvt*MGh30rkpX~8GkY!sh>>=&(JnR%0>nst zaS2~sp1++2z*JvcO#rxqi{8Oy_^A!ZX1J;NbO;bZvv52Mp8x?OXbCP_g3Iu?^I!)* zsT5a&0JzCGUW-qF0MVoc7j401_+<)EnUHD4CqsZ}(v9QY_yh;HrqsRguXs-8`>Q_@h&#s18Xu=q6M!Y1KSYPY})K> zngJB0>Z-Hm?=Ngq2f?c;ST$uTq(-OjA#^8?~)^YLJ$%V5Gc*qJ4>2Y*$9J%{%<9y&bfF0nE@H-xov23mD z0)R(Qun5XT*zIjS!(k_l@G*}E1@oZDLl2Zm(1tAjkSe6%hL%CLSat_Nh!fmB|$l`{hX9_T`ip;nwq9z0^zAB<40Jw|DxQp-wfC%a?qUtU(3o>S3aM-FIdsPo5JflpB zQKlmF5I_hf5rPQcgJLl#f2%_DQiY;bs9?}R6de=-!s&Q8U0kpi zI$B51WKp&^)H&`b=?{6AnuCMI~3`!Td%h~djZ zeOZDr?y}IkLO=!!%@6`ASZIY1(9S~Jg@92OKFSijmUuQA&lc<@o~;xwBvEB-tc)%A zY%AGVr4SH`qoKH9j8I%D6rU+@lRY`OCr7Z`1P-1c1e9^mGLB%3at^DUBL-vCRAgE; z&rC6!FgB$n>ZttJV{A%G^a%llG>Jl*Afu4Bppd2ugAq;oF^PUmkm1Xc@MQ@C87zqm zA)taKQ6U7xvnAr$f=%Mt3*y;=y_B(K%GiRFt&%NMDFlS#5}~+Yj8J?*C@vI(BT>c? zWR!Dc%Q^gPHll2~^kb7tn?au2&XQ;s8sR8w;wX!#)bM`0EFYy-@1}175|c*3(kT4B zKw9&aek~=g(ny=?;`-7UysM1Sx7R(F@22W!kK*Z=mXLO;nVX8v1LR0skDBZsb*L!S?mNrF*0CQA??7)|u)O>}jbT@nnQP6+@!oq{VA(Ikc;8pDu* z=_b*HCtMI97$pqF5{4?wKM4j;$piqNlEKB4VDOX-0z{09%*hv-%0htVMW!wUh$cL( zg9Qr$;Ax#e4*Q%b`kW~Pmnnk56F&$Lz0@&9>zFbysU;XZH534NY6!O-1cRrB0$FYf zrj~-uhgmMc;K`#90OSz@M7LR(N)|R30z?y@Ucx+>0C;*SkO#-HrpK|=VIE8{cmgT_ z@B~x<;0Y*P*@3;`lW1&3Y1kq`iSIWu}Wvjxf#zc@0##tRnkyDtzS@?$S4 zPYtI|ScNT|xgF#=VYqe}ZUluZH|55F`j(UCG{O^u%EX|8lA6kxn9AU59KonzNYpU+ zf|+h7YwY2-X$R=fje@z2=VI`?GVqWelgSPTz6IJJ+CIk;j3fqCi9r{`k(^aUrsW4` z?*pD&G?iO4ex?p5B8WzQa3&kUZ_U6%eqbg&TA>?avptgj1KM3jRjQ+Ez{Ob+lae_c6=(2ng>*!Mw&3NBHR)c*yV7WFz>gdTg*` z->G4=RIAy=*nrzn&`&om*NyY`(|a1K&fph!0M&72GdKbM0Ra35pFN^T-%I+i+Apl-cT>#*f%mn~my;lI>RdWRZUeQzl;1xUt0A4v$0N@oX zAppPfgUjT7;)kB2K4*>^=#B(}2XmJtad$ienUgj#fI~)wC7MH8VRbcRjdz}0$ixeV2kWl7~P$vIl7XhR*RnnRKcNXS%U>xLG1u}|Z zWRst5wN(TN|AZ>_Wc)pY6=m=~k>?i3HUrM~&qwZaZ-Hp&VExk{RwTcw5H;Pc{Y19?xK5q69qTsRl9{tUmz{ zd5D4Zz_bT=$U_UHXVJ<|8L1WTQoubZ=ctu)^hgJ?PD@t*9VO!qXmbKP!B4|8mv61p zSgMu^$}oQ!5`P(rumu5(GSo*I{9QW%gfb;Ug$gz4Oo{Yy!0NSA<+(odd!Q3v3g$ar z)ehB?<;JMs8NlO7!92%n#v(uCf43K^jCmeWutyaB03hP`_=0pG z$}`-(RkrCr0Wdu zn9ukEVOSM*<+71}HSlc0Ht`pJcsvT=VIbMo#n3I_jdSxbIzH#6X(p#n=)?n=!UTbF>=YcEvx_Cun-Ugp%4Fa z-QcpKA5RcjP6V;#q+l7>E6fe6=Oc+%+HC}?xwvg%C+|8{4rmy(8VT0f2WS>U)byJw%=1g*iNU*qncOr zzMZ-}?VGv3?yLS}a@V?IS-rb7! zXYR1vX%$DuH{R4cbj85xp9y0pHhuQ>jkp-PH27`#(I*{qOucgAWFhCe%qm-0d1CeN zvomIARX(zqWwgqpM6X>J1J|^`@9zEGP3IdAE_FTnSCwbNqJ3eBCV|7Yg7N$Qir2N> z;yHDx^}+-F&iMLV3byU6(~BLv>ErfqJI}j3a}OZ34IVG?vgWdN7N1S|cKT}G{DWBw z{&+n}95JNpr&-P~CwY^L-h1lZ4!ZyH@-Gu(_eH%z?b%=Z(?KG|7_x%p_U53$~?Y@7TKB3Ces_8$*(a!ox zPlJdhuJ>NetBeSmayK$3>+_Ir^z2&Mr!Du4+`Ah#yfvIzv_0|EH*KAtHxBvb{?#UM zfA3*OR#i<{_90vhG*Sp^(Bp$Sj-m&%k4~s_&J_5ZCN2VRhJJ)B^-m?z>zOf#+f&V_E z6=J(&uj+uiUWIEpONDSWh3vx~;9>7DQPXa^^AZDM zPW;>RbxG!`HTK)zEN*(~+-=C1ff*&c{#yR7q<)C$w>8}+P8+Si`PG^=_U($3UPc_> z^y6-`nA>9rl_oR7DzxzM%Dsbky3sf+tMO>cd6a7IZhqw5Y`CYh{U$-lUIZ@5L# z^dWhrGW*TWDYe5Y4>!D>>!A1H`uU?4>z@?_tXo!;N452{OVQ8hSyecsad~(}pHA6J z#=ek!9_ee6Z2rS%ER#8PfB9}}!v%An_I-B#>YmBByI#Beqnl$!ru9VcG1GcDjjc^C zE7Ntf*)Y=gPFzs`DW2WsJ$0W3XO3K*ll<1x)!w+_=H}KmLv)F^UmEoE`>Y(*ZRV&o zm4)x-xqkRj`0H`WxRI9(JRdfln0LP4AF+m zXN*!G^zyv4xcwfQb__YSa;^^ZoK%i|aG7X!rH_~1@*uXK`a0I$&h5io`+x46zOLEg z>#~XTTN$eVtgv(M?Nz2qE29VR_D1^n_6(@6-_BMgAD&|M!Dxc?fl7<&4BYnOw!fk==??VAyNbrINmQ) zJH#jERB!h^mpeS$KFaV^+}WDlw;X%7zaEw6<$5xr=CAcJAAVoAae0vK820MatLd-C z-&;JP+VRigx9|1i-~IdHO=hP~t#(vzE-~H{FqI`Y=z$0v7_EzJjx^|^d}{cVT&GwGv=i6INMgJ`QU|I>Xw zscuG5yQhnt=1(9fE6b)~HBlyhOW#be9q6)RQ&Z8Jj(42uw~uISw=69_@5uM7Zn;~O zyZ9+zGEWU>+V1sDnjXjH?+zI4Kjy>uiB^+hi+pw(K8y1;lO=>s%ida%m7Udb*H9yu zPM%rsH}u%@`rDXao-cDeT}%u2QF(#AK6edp4|nk~D_VQ!Ozhcx;FGUCy_cR}*z|1E9T55RVbJnUxAXgq z{a*1cmC_v>owmO3yzC`~Y1P|&TK6*GtA}=+`)$^=hVq%+j@;<<{@9GYU(Oyn1k7^+ zDDU@f)~0uD|K9Xsw08fQe&cWCZm5YqGcWgr-AX6peB*XH?d%H7u9aGwnT{R5e$ugm zQ+8Wo^_1(hOf8E;+4p@Sg71!q&%ZK#TRQbsN3VB!;hq@_tNhkm?8v>)eptV0_KIB_ z&-ZcbaG-bk`G)%b^UABO9Lh#?E$Qns=}YM+a=qzK*E_`n*Ipd+VCVOFeez#B9uJEK zZOJa7r^hv1ywtF1>zK5>ha+FlUqYV?H@}cEA}O;rfc`YT_jecF^p6*Y9zHWI_PKwL z=J4U?a+_}M{FVK!|NEDXV?I9mR6o9-cI&wtZ=}lC6{n^3{}Xkj?)iS%@XB`=U)MHX z|7DQ>(EW(A^zWp{sYj~!TnbG8xY%vQw1?Lm8&ACY_;%jmAmH39>h<`z9i<2S?|j-; z&-8ff*6}gX)-7eqmb^QjrHZ+ozGwDS9M4LKo`3ynxAJjHpzX3Ed_cfNs~p|Lh*uNS zJ-J&`T_43gyE(1zgBinupJtxg--R}qMTGC^H>*%F8opyH(bzd~%psRlNhbfD#;;j}t)@+_PsOu=NR&&Ce@9p2};;_Tvv-7rN z!v_w$I=Rfs-D9Z#@EzB$`fsm3c5cAN2(zukxDFpneX~BDP5X4>^Vi}3D?L6W<$dAq z4cZl@XXY*?jve=Y(93v<$690KSxytjOeVK+`C~T?UwwG*%H78|$quw#_}93yC9~G= zZNK+KO8-`AQT4@7g3Lc9jF@oivR9Mrh}Zd7Z|^5wiYnUue%-SS`flyB^66UJoIYH? zuy5zb$M)4Kbvf>8F8~t3&_y-|L>uJ7XtU%sg4(oY=Ie>`jm2(X)3r(I`;CqBbF{2Vsf)cYP7JPds{5VL$|uoh(o&}^XaDtmUdrYb zTu9t`^T4u#r4Moso%Fyz znUE5Uk#aN^o!qS=e15w{op|D)O7ysrIIe6LFB4K^bwG+t=+V)Be0a~}6+Jj&6)JzD zd?TzS`bBk|Ak=a0V-qlya_Y?!+mTF>f+$kJz7$eb2jPMbHnDmAR^Nq^u1GSBCciFSg0*r%lX57MFsh zM#3+u-_*52BeJQB13Eq$KY%B;A)yonk)nXj5K@f_hT3mgy1!`k5S}>GQtTI=_`>TV zxyiWL&4t?k`#!E{I8S(}dN7G5l4$*SnUJC$?1Ou-u>EIQztV*cJaJMbng@tH0EfAd z5{w}^3R~T^|INU5vCgA-!bc^Vr6jVH@DmCtvf5+ydDZZ#OrNyfCTHvzZDKBJkt=Y8 z-H3isvtwnegmzQUO1CXP`fjo|u?$J=0=wW~M88NXMkda#)e8@pCIwQC+Qe)m`~bap@I021{W4wYVDtK)qHyAg_A>q8$n|nVtXcG&O#UL37l0l0?ifTDS ztmWJ}ZTznXPT0m1Zb&dhL4+s_aH>&szoZv`CiIx@#uL7(_9Re50tKgpkfQeVT5~}) z(#B^$u&!#`&YdUrswAIN#B&PHF(E~gy+z4aa~Z%iu&4Qq=hA z>xEA=DeuI*9;d!|YZL!Nf@fsl3^FOCNN}bom@}|u?Vbd=4^M1Fg6<6A&e-Al(llTadj=fVc$U_9Uc8umdjn;!o2p`**B5!4tcXWHCn+bFFcTBs=5b z_Q&CW-`wsS1aibmBso_;7Y+^di|RODSfFEE7r*^BU`Y^9xF8u=(}O&$ppX)bm5wzo z_vY)d1^;eK3D+j(Aju721DrVM7g=)@mlez2fnmK)zKrFGa8-l7Si%cUTOlPFGxjfR zuTR8mw(!;YD?D*rCECmq&8&I6Oh{2f24T?!qaBa8jrli$CjwNWH%a0q2`8hFqR~4P z@3SUt7Z1pqH{%*l_zOKw5*4I1>~U3!toFm*6ZB(yQ?IJ+$=bvc)S&$`upfB@LW&yY zEII^Xn@@}wJn&cwN321DAu@RgS_*^|3H~GW<@dAeVve-^`vy-OR+Sx062YjNLP{`t z@*%jIUUp6XX3sa>{E#z;fNy~{ER}1L_1+odZ)X#aj9)KPaIH*UQ!a5l93> zKNhXKmQmmsayo}6B2=O|G?7EYk13=CW5JKXUugKEN1syK^?|$aX_aV{oQRUcxhSLr zV@#=?k^kDvykSuJsemUopr(7!ga-{rl8~Z}-Ub_e<2xX%uwS1-o(NMJEoX>w29__R z1k<|JSS;EtW1>NixAUKK#A;;ppiF)cEd@e~`gEMorxrz{%-V0=_JSu)sZ3sBh%3mX zkfOa}BsSS|dv)dfwU1u%gr7?E7fJjgZQ^A@iaM$-j?E}_p@B3cc$P-?w;@{K6dm0umq)4LVw7C zvU*Odp6jgcRTv!b{BFJz1~`I{L0uty5LF2rGN2qGUcfmxMnE}YU?67Um;mJn0Rh%g z#{e)#@c(fRtYfU4iEHw-yEGuCP*n@pxIdf(utzskiHRS(<`N zQ&_3})Ogto1@{6U_Cvw_P*|y*3%C~mt{7OUy-O$oxF5hu9R@(Rn&iSrEA@gE zFUuskOwtN3w6+cpn{QW|nvWLRa+vc}Y5P=Zk8>cXQ?{*B z_QjxBw<^`L>Af-Pvt${UEHlM93uXp^C(o~%L?ZjIWJa%KZPeX}c6!4vves%p01XjS zAGx)90HIaIAWCk5yA{OC;^iP-&PYIloJo*tVE{`>lyix4eF;dCb4ePYKyF+hx5S?Y z8hs-NZ{&;wl*^fNxfTY{Xob9Mh1^~OD&=gYTu%eoRLbonpjmF*EVsnp8PDzt^noGXv?^3ROmM<%<;H`67B%F0|oohV1s7}v{4E`DPS}}`%=&u18AcRbSwisB%l$PG`37CXv2#H zUL=EO83f)W=S}Kh0B!h?yboz00ls7_U(!$mwD%>uNq`^8`H}h(5KQU?lV*~s8%csl zlGgwxks6abk{lRGI$#M{v1pQxCRTw}G*WM@XfL(>MRvvjs(30nPo)k9Q016X z>zL9=eJX(tBHABUcEbRwgetjEr49yA<)TvSqS8q1=OEXn!zE>R44_Jql1ozRU;tIJ zlqOk9D|L(wTdM@wN*)8K@>Hq+RB3_%RH;y!Rw%924n91|QGzNZj{#JvQySDMO)-Ef zyD6>Rl#x0Hh4Y0nbEj-DfGR!|??dTg09AacR=$*>1O!uB!IY6Y=7e4-WgbG=VgPMK zQhX$(ivhF|MYW2e3?(3eGD@J@;5ZMeWKeVl)d~Zs@|-e$PFdpk4oXx}bQRSK11RA^ zn|aVS*q4J6{xtBX84RF=Ki$)x9v}f>w0Rh9i_dwWN-PaxX$AwR5=-}tr3XkrBCVB3 z8>vrJ&>@OJ5^aG2w2?}4sk9CT&_){FDvdUjfE?N+hql7LEL16=K>^KR096X;?gex| z2`HqQLRwb>s%foi+DPpfAz#S&J#C2rG}=J(4YV!>&}akQyMZ1g0q#s&ccu%DFrkVs z1AG|<1E>07@L@v<`Dd>NpLBW~N6tYYd=D5XS{^Iv7Be zGo02L&PaW_h7QzBqB$!Jph_Ia#c?_qK$SF3D~&T!2aYIKG*0I%F@P%B9G}hUVgOaL zIs0sGhy)aIT1A|Z`ji2kEVL=++G7B1yy5saoGu2?MmfinYk)7D?H3K-ypaQq9FKi- zXyZ4h_nR}u0NVJ&>HgtNCEy@$dXTrq=MzvRnCF6d9SI2K=}^8E2GGVS-s%+JQ3B$4 z^EloXpFTkw$vjBr84RFGF0Y%*o2rkL5onvscaeY!UZ;XLQ6I=b|CHDJ!kgja;04pI z^Kaj6(;B(50jzBR+aG(mczhuLS3Kqyv!+d~S>CaWT^pnm#F+=RxYs>AgBPASx7`Z4 z*Z#DDKW&GtK@dwD#I^u@O(2Kn#k&Df7K%2@?V9C7u!~r*_KkP#jzKo4JU`OFkL-x8 zVz&y_@u=zo0q0 zgy<7P(5wK>3Ko035Cj7d3|QRH5F`PR1X%2gLQn!g31G2f34uEa+({OH00{hO;77A~ zD}^A21~D{?+YLcJ4f1Ig?^qD{Fu;dl@#X?S7z4r>7VjkxBr_nHVew7@!4n2NVOYEm zKv2hkI)=rIIs^w;aDZj;3Jt+o7Mx{SydXo6&VqE7#mg-Og)As!S-hA+@R0={;hHR7 zhe5E11A90YFO?7k@gRt2@hpbm8V|1VES|J@YRVY(t&jM*CwKi3y88NOdjQ9d4`ty) zb;jcWf=J3DQUhdACK*%*i9{7;Qq=Oa6)(O2N9nlxe+`>0xUS z)XTK$HGsEV%Udp$2qLwDNGXUQK?F%lY}_EVZfHo{BEhW|339XfifT*QFtifAksH2| zOS`IEZdNYuf{kHk3pHH4)_#zbj0f}F$??HC`Y{A z5_1g0-B;8dvl)Y|HOh<|W$myveCLI9R99VM#-^>a&uh7yRcRE`dWE$5wBp~ikM84i z#!pZ{Tfw|#Fy9N?f*_Q)2<74Vlkg9MWZop1SC6Kmduv_{7&U03Im{7O6^W>@sz`va zsz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`va zsz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vasz`vas$hWcL(vFQ zU4x1l_y!blbp46tw~!AmZ(1~N3L1-va)U&9C!B-bF{B}0fr?q5gD0(eYrK0ZI?lW& zqwmSoiwZPyiq|^DTVNxqG1onrAA-TIcLS%~-jp;ImFKB6_f+=7Ie7I&<%t)mV%CU~ z$q~AL3a6{qLxrJ_!UpR=BfbhVUxjo|dy$4-q*TJ2wD2a?&AL+V+1S5rznL`DjgohW zl6S{jDFk_-YaX!2a~gt1(76%x##cOo~)DKtX6wn3*w7OqoKdcCfpAxbJEhg9G;F?^zMpwx}l?L!v0Dpy4;;aIk)c{!v zkfi}C6`)cB>;Yg8klKg@AW{RQ0g$Ev-T?4M1Nf7`zh$q0Ro_R0eYDi*SsI+x07Wz? z(g6Mp@Mokdkqn5`0M{9CT?0I2z*7y-#DFFZaEt}VSgFzTEI6+L{$s&^8sHfVo@szO z7Sw5gy&TxfNsWf{Ae@(i6dt6s0Q`0UO?2_WfH*>6Pu-#nZ&5aq!LXDizd z*=+8ZZnX@Ju1p!1DQk_#Dn7wMIpX62G3%Qmu{ou&^BOen8W@8HMm^y5wzwSsHG9;0 zG!%(42;j6Ur*m~L90a=FbD%`BM^iG({P~P03o;m3~p#h+ytgK zTO_apjOr>pbHL@|Kni(0;)4b;3%_MRy(T_j5OZL8S(ITGWh?2mkCfp@$`t@D~)u-w-TaG{e%?< zZa&VIWd0~?aFkWI3p>ily!gOEG>`98Y+#P~ zoMer zZ8@%lz?-VSX?M0q- zHfNE|siz_YZ#auL8sIl)^P5w9<@livvMRpL5v}5GM>)c?95I8)yYRQ{hqJX0nh52b zUOA`s=+ZWBVc)4M`ye+l{L4w>Yp~aosQTfMz zQ+SX{G@3MxCe?d76un29-fIE)O%ST1>M4+DbW3j0qU{F;9PFzq4c$~~l!k69B|x}# zlmOw{Q38Z3LkSSB3?)Fg|C0dWx=#Xx%RC7X?(QT&xS5jx;bu+(gnKs$5boV1K)6-Y z0O(dt0)#s=2@vkgBtW>Uk^tdqN&~zp0|^i=1tdT?@|OVN z{9Xct<9Z1Y&fX#^L_GN$B>Z<1z(|%8u0+e9zcC!eDJ5rX^KBhsrPie4kPozi$7d@ z{KyY^O{%wjVg@u(Ah#=!55xzY5CoI$f=PRP?Tb&?kWKNupQyWg(%zH5?DvPFdX#~l zWndI8ZG!v94l8ZCoI*LFO7l=gZROy*Ryyx)FtrZH1T!$C?lbF%fPR1VT(CIkpvIBJAEl2_YuJ zCwCACF_GlhR)~qP*9s+sm%^vF%gb=ArN9B9P>gT#6;K&fk23fuonV> z5EEgi1KCi;M0m4|;P6#6;M~fIx_eu#W+O5EEe^0|Fr?!h;F|Atu7!=<(Put_F9f$Dr}yOBwmLc<84+ z@@~!z=pT#5!F3sTU1o;I6s|JL5nqssS=l-(kBt4@?>w>=!O#&ck@mBV3H1rY^@}LS zle6>W)MFRd6nTpo%s|J)Kz9|)Ru(OMD#3!U;&a4lo)3`qM*HAe%qQglmB76u7PdN-0pP0laD8O-pU~(7;CnoTkBP4RD4AXEeYK z8r;wTPigQ}1Ju!=P6K!`z>AR<8_IxC4UoiuBn|M00gp7mI|jVd0RAlSXQf8>vtYjl zh+#pD21sQ=ss_ksLB0m4VL^=saOZ$KCoSa!2To{!^Bg#@0d8~Pwgz~~ftMQKI|sgN zfB+r@@X}JQ^5AL<*aR%boK8&5LlZWQHcF$_j+Xz~ZCxhrugphlNHMEl%&K!BsAcVH z*}w2S#k)0{+v1aSF$-^~C`WvOF6PK`=R7_3~kKd`I zWnFxnE@nZ|yGpIQ8fPPUNsLaf2)D;&c&K1fLAKl}wI96Qgwxv}AYF4QXcBA@) z0lywYI`37l@NvO@U9PO$`f5TG%IQpZ*2WyW#fXcK@Wm|rd>X|G;+uOh2NoN^a{;_9 z-r6C!%5zs+9?n$sP2b`dyyF|HVG3iA(&BBs{2J7Gp1JKGbZ8u-FpN>y;hI2jM`3tJ z1C%Qa%Qb*IFmwlM75MId)k382>ay5%4NT>5BFkkCmv!FNQrF-c@&s9;EJ=1nc2!0s e!~cl@|GOsnJ3;bylH~6zlE0z4`d?zp-~R_q#B^Bz literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio.h.1092B3E5A67E50D1.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio.h.1092B3E5A67E50D1.idx new file mode 100644 index 0000000000000000000000000000000000000000..3ab2c4a87f26391d56da71ab6e641337ef73c717 GIT binary patch literal 12160 zcmZ8n2RxPE8-Ldwa=CW)$S9IB+aW7SMMk7Dima0Sq&+B-m6_6zL`WG8RA{K|5mHJ! zNr;p(`oE|9p4;`mpHKI>eV^}no^#IooacSc^I>agZXPllK}O$ZW__EpYz+lzV4=Z0r8JKq|V>=2pm-SX0X`^~Lye;l@Y=hxed&v0!N z@!(HVJtx1b^KIYFuG+Z7WygZk)YRKb2!9QMCrb0v81r@Q*2#2@-5vdLzhnD>r)5vf zq=&la)vr1(B|5ic@9zdr-y_TYf7JEwDHJq1dUHqR(qC6wCp0a07=&-+KQCg9TL1iM zKHn;G%uD`?!%q1sg7u&wq;`r{t$ym>6ug2^w{FqP8LD_YMOAoeV(xIhecZj0j^8yN6Cv^oqli_yRT&YgDVpb|B-b5b4~e0{ zr?nM*1g6ZqD=^EjZdbL}_v(958cH8jTs7~7+`H9(TvN0%*nZt0!{D{w(N&FKhV{N@ zm5z=t&fR#gYE9+H2h}|7w}a0DrhJ`!d~JS7*GWt%+kDYo)$Zvw!K*@rE7)gSV~hB< zm*iiqIyKaQc?CSoz|8n&?&;OB^qLp8%HxTN*Z9zzZpSUtT*u0NrU~C$_Wq#%={u`z zUz;vDZGo*-#8n*LY1N48@94;{S@uJxt>byu%f#Yqp5|e4;lJ9_M$frT)4O*=I`s9N z;2B}t1Dy4`HAPDv9rSo7>vh)qx7#BRC2xLHum1D);hFAdBUwG3Rn8t?SDqf|+kHH@ z_l8s~o~&vV`1YLLdo$^x78QwsiR`HH5%>67PdBa0qN)>KtIcP`nk|3sy3fq(SFx=& zpYH3HS~1OS`cIrKuiZ{k@zt*!Otxxk7uSr_Fv-4s%1-HWzmlD~z*Tj-GpB#{JbDoJ z{F*yGU*Njxp)5QEiBby58i$)Kc64i=tPd2@^GAS-Nmi>NHLA8WrrAV|4M2?7UMJo7b^_ z*NGU0dDE`t{Ss3nc04vIj|g$Di!Qh;oyN}}8Z$4#cpiTGo`=|BHRounLiHz!{PqUc zkuwHVw9_JV8qc4Y@y+H_VSlvIrlGiJ@(#yFZQU0)W>uucUn(-g(<&!Kb06thM&Eua zJ{B1+tYA{EyCnRurFr$-nIDIkDeS6mCTIT$EH_{6w&(YK!P{5lY7~x0)obTE8KfJu zhvW%)JJ(t-bliHqhF(}wcA~E2P{&3|#;rfWKNvn&mQ{NCn5!H=?;78+0&F!hCHi6L}7YU`fY3jV3{Y<&X zw)tH!s^8f6WY=C1y0BHkFNx9)4f~33>d#C^u7AP$N)C={y`DLBV7Rovd-g<*i^kij zYWv)p_l#G#8ZtKrhc+KL6eCpPy`^{R_m#%}Gq-Jj_?Y?dptl!g8vAdq>|OB5_-o_ax6c?o`F6rZi+A#LOS7^UO}CWC6L%}shn!z^P3u3?PY39C%nr#HEVcVB5wptTepmhOjLL!R zulkiRa#>h;yr_|G!=-O{v2S%yFB!@t}YNlw|@;k@{uVb7Q5-jt|yb-Ok(GhD9w z?Au@3eKv|-en$R=f8)gY(QmyM9Yf`}%s3^Rd-3?ZHm@reW36SLUD`UFfSprt-P>kV z-Xd~gdhe`g$GX(cjm_5KuW;GU*EcKQJTV-dYI5|2&{PF2wRDwXg|oUVUGD`Np9|l! z(0PtR*2WiswtLt^zNgVk;lHmZWsE(%I!@dF^{AChD_@MruEr;yig&p=p+g_5#ylSi z=y^Lnl5U*XAzY;RAzg27AdBxz^ugux7a%t~w$~pfB$ljnSDCrfM!v%TM?Jn&U2O= z%WYh4r?y8#!^CWh<-H$gRGVzVS7^qbThi0KSV?)A$mRL-=e`{fH9cdzIH=4wRXASXzeQr}O@;rCDV%Ymn~P0J3_N@9uCQ9@d_&t=h9WiH zo?-Kzj%Qvd4lw_e@88h;?3CVcU~T*Mm!qsJ<#oLeF^OmMdIZb-4Y~zh^bTBXU!3B; zr1!u`K=X^vwvVUc98SkIey|vNzst&eIB$IZjjg`94mpkYCw6TM3JES)xM0!ez6-NX zRcakkdcRIm3O)UPj!OTR!9UJxD-JzwUwB$0*V=X1MdN7Y+dY2K=bW@!2d`)+?tgOk zq)$kL$}ykwa_lr6!y4B|%6-fr-Oq@v^xEu!)TXaz)J1+Q!Tf!sek!UU%zKt6haM*| zzdbb$%n-%xko+4jEF5kL?l_=vN1-b2xg_5MSB0Pporxs_S=yg%F#g)+)Ni*c{Ft%_ zAG@(n``4sqn^>gEYggS(aM#Iki% z|2$Y~Xz|_!PKjlYwXPA>v%XcW9Z7qdU^n>kbZqFWCk7HP9m?i~%IPOx7yqdt5uq2d z^m113Hr>7`bTcxg0dO}leeJbg}C2|Gvn%!c5&wpew87{#wTsU@-7Hr%vH zG4h!e#OjhXl3qC{c86NyI&se;+Gv$~{>m)xlVTk@gwuzPjW#`PY8L{|MQrbi5K0+} zFL?Vr@BOCXmCm!$Zu)hK8Sd>`Jb(TY+UTzD>C@Yn(ch^rNSPDWkg)a(ty(lzTdrfL z`yxa6PIh`VD`485c7=)1)dI4&9tYXdE1y?iTex&W?^1)(lLZ^@8oAVI9ADa#tUr`! zo0%^b`uz469Xn6EPDw?tp=qbL*6}a$TmDIUGuy?SFY8QR;Q~QZotO>hG!>s?0z}JG zsi4Fdq1nbyZ_>pQ)*P@}Fg)|XxuQ%~t<07CBg-$&m;0>Tcwqj=rH*G7#-n0KrLr_X zPW(zb4zwba?NYpxlA<+u42V+i$Iw`lcvw_27X)y9Wt-OLcyh(D`SM%T3%fzB%>Pk-QPx z9<}VWp=XQ_7n6jZc39}!nGbcZO!2X9|I~TgBZ|+m`H+VC?qA(sql4Hxt}a&{nJC-i zIyzCY^yZ6>E{BVU4Xd|hzU^A@d|5|a^C7o|YrY>oKXJBM)m>fWmtK@%jcVf7MMk    )0MKMF+3+vZkeX1*7`=`24=tB<#r z+_<^WLsTWR+R*Xag`UUGR-R8gw8EkSyF`+5?8;iwXAiqJC3>|E7o_N38fDP;2+yw8 zUGHe^q?y)a^|7~Q%WBJShDLq8&X%tlmXAuk(S16jx!u_6_>%)8Zjs7ohob9(|7&5m z22?j7mjpL_&y>Mks(dY)OYO~ex4(M*%*$xDqV=$omTyjw$N|qai!~Eo4Cs2a1!;TK z@7X$Z<>hgGDJheum*&z+%BzoBC#0I{IF;92pJ{XH_F>EX@*C}%aXWQis7iIxbOu%@ z+h;%BsaY!$Iwt7#MK>e&V!ZYTPhtmO!<82T9Z6eSMjp6YDqQ_s>tdw(Y>~J0{KoM& zpD)%M?B0ut>LJv$xN(oRgI&6?@2{Ng|Kr%T1YsRK#;Bc=AUR4DQffXWyqCn&dzoBZ(&VY%X4E_+(>)Tlk7Y7RiOO( z^Wz5W2&2C*VouhH#Gj3O3KWxc53pGe`FQ6&u>;` zOh@ZV18Z0PqC9Qgu7o2e$&`gN?l>%H4v zgWu0OY5tb`_8XMNJ5+TnY$VduG|QsLy-z)OQ||qJ)__G4%^$ZBM*F8#1-a8^%9@lP@mc9s?G(~<36 z?P4gj&`JKh2pK4mfl5LN>?NYM9M6go z=L66eE-V&u6y?|>`AG~Ui6MpXNwaiw(X)RoURxl!SFJ}!h##>97Bf*S6BULMSe%a_ zU?rQ5TpJmfxmJ{oYy-Sxlt@NJpai@WG=Sq-x6QzHqkEtz3kd|wF&Z*P6NeJv6Qe0Y z-!{I}T)U&Rq*=&*?iBkONIyda;geu$L7J=Gr>40Ri)7e{7cf|k66GixO5l2hFUPZN z*`GzKjD;X=%2wBI?_THL-?flb)dn4MvwJ=jsuI>$a-M#7)l&N<)H)yV_;N2?djHx z(B8g;jraj(3QDA)(2)tS-Qox<^^JrdFsq zvym;pZv{$J0KXgw{903fvv-8uzJ5+?9SaEp#Ci;=$Hbrn;h+pX`#zR?m&c}gu#v5R znTisrs3?@cWE@0 zc^}2@qx?_;qw_fDG$Qxd&FBwfyI9C>!0SelZm=GX1S>~QqG$dFz-l;`m=gM}RbYw|vh+{XpT9ses4K3PFSXmXm-NWJ@I!+aJJ z3`|DgNCZwUnkbQs{K_C$X8QUC*@QL6WaC7!Xc888Ao#|&IHh_5%B`$(!3L;cBj4GG9UxvqiEF?&M*`wfYB^0+-!s$J{x{46T5A%!$DpK&BOTk0^-zHW&5v!gNL zHw)PTm|rpED~N861P5UnWF~FwXmz~vl4KtFdk|^}q=p~^oFjqJS&%yKyyo16*G7J` z5pQ6$5+y1@Y;Yu)=t?R!j-NS|X~SnV#zKy94i^oH1{00`D}haYXftrL=MH7@f0Z0M zgYHg;dDg^z;X^arK&he1q(P}f>XW0F{F`xhEhLc4y?0a4F_hy zDc~R#)@(q-DcGRK)iIT5d|oKIgtXR;3U#BB+&4@*nohnia0zaD0Vze`0xr%2T*L(~ zP6Bdq(Og`Hhmnsj$;Zukfcv=MeO!W@enG~Sy^pK#01t72hqyQoP=ym!IEx3U!$s?G z86Kb!XE)+gd4OJ=-HT7k|xUojM3D_Xj<@GkikDe6PTch^8lfA(NMY!4-iHd3!}^O0GV`&Ou9U`Udzic@B61p;$nu^PJXZLa}+$X&oXIhX{3^ zbCgI^Or)vv9EuW}VhK&1C&D{vik&odo^TDND~8h5VeHXcq|E%w8fVkVHN<25@t7D~ z90?>~LJ1i60g*rvrdfpP^DtU4{+3BY1~LA@NkA+v8jEuu42({&nbeJzvIZ9g9sqTN zr8N7LQbb4R{L(?m3B=+GvA71DKtp)A%c+andN@JGC5^aEn*tY30$ntsi#7!=oCJ>2 ziKFx>aN#}8u4x-pYxRLYC#Dm3l`yiw45=G3%-{iv387*_2?FpE4ct>VXG#T=5LgU#S*A4YkGFQtH(O{8ZUmg|hSo@c zv)w!ZXS*SA_05qhfyrUEoH!%mu_;hPj!nS$5-{?wU^pKVD8f{Wu$eqS3r4g|8Zw9x zgOh+*oE3|6cM9e>un6iZPgyH?7dAXkWv(NejEHy)OoV&W0)S*ZrU(I&!I>EZ{!Udc z0aN7x5;49+Oqd5K!eojtWtdM$8=S>J;P2|@7h%Q_AQ_z1aoYv}kZi#eAwV)X%jFi$ z0FWHS6nTJfTreD$fcHys2xmheK)Q{^wPJAt2*7Rz2mq>uLG4i4w{F=pYwewJQnP`% zL7L|=+@T5Gp-tlfUeknL{{!HJflW@=15(r1zn%6wWU(92I4~W!kqa9j0Oxc+;E3#A z@6;mO)0;rB-K7zCX-udgfj2bb%_Ja#PDIeTj4AGMA5spk*bJ<$Wv-QhBXxxP6mF;; z*#cI!iMffJl}L*txX=i$0*NG$LK8}%aRHc=fkmq2LUDg?Mpqar0E4RL=RxJi>ge}vS`!Gl+dAL#@uE(=4^|(^~B;W_G^kWhbN2tURb9sgo z5-Nq0fEGffWfJh6Q29OyNTR7E(YQADgypS2+VC?L%-oad$-P*?P8PT=QSGaL+tb8Q zZDQ!bqGyhmes)vH!FXW8nd!`pZrJ1k@kVvF{+UQ(%t&G^;iV&JJ!U9f*PqcQzx%$O$`UBLveVA3$vkXv4av5GKB2*9oxaKdSs z!JYkl)w?$3wa8hZ31kLxcLhchz^RrQH3W9c7^H@3k?~GUA{tZYnOHt1k&mgvd5{yU z$HeQg88Cy8z*kJ-E2hqq;UaLU2wW59FOtzhS8kyjz?ZM^lzjVkMp*_Z1~>@=9t9HM zBn&ut65u2Zcobk*gH=&oJ8JGTEs``_KcCJ5kI;kZ!5h6#aj~cPbhu&Ue0~r@KL}+A zz=;BzRDX|BomyA<CSz$q={#^*fU%enjnEzLa6oMTN`d5ut_xnDK6{* z0-K-#$YUatu98XDfv?YfzT>!{s9fu@uO7n z0V`(Loj6*>B>m*#8o4<4oRL5su2DA$7{)b*Cjqg9M(m`sT0m$NOaht-jpj+f5TP+N z2}q=AB>p?zu>A<8`nT&yO%yg90Zw%pDGlr}0u9wxq%iV-WAh*&`OduOLEiLFz{Gmy zdamhv3!Hk*{g-|L_)O+ZLCA;q7JyS7P)Zdv>rP$Hp{4!6X$v;H1tVMeoDT^MVsi#D zLkJixT(q@ruW3Jc$(PVHO8z}I66mC9bWQ?7=^CMQZal#rE0_S)Sf$Luo+{8#ja29` z>B*>RUFvNolMG_@ZxY z**XT^CpJtQ-UL@lQz@PF0AA8mUQPnS=qh3Vo(K}S*^g{alYiA7=&>Ub{J2DRSK%j{ z=XVy*?@XTG7kPeP`1czlGrGmko!Zy@xA0}5+2{qbXL^xrVV*-Tq32QL+&?Bl{+Ij7 H`1kvN6IX3} literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio_driverlib_main_cpu2.c.67C6948D8AC654E7.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio_driverlib_main_cpu2.c.67C6948D8AC654E7.idx new file mode 100644 index 0000000000000000000000000000000000000000..fee11ed2480ab1d1c171a950695aff265245b8f4 GIT binary patch literal 604 zcmWIYbaM+~VqkDi@vO*AElFfyU|y3sa-(-`W^ZgvIXGpEI+9j#! z9}sqEd%`_|du!^KE-l^SS+91m!!msBiaCKS&T&?`ou}O-Q|#ogF5E$D zO^z)x-8*@^nZY~Jo5vPE3i{n0KUMPRGnt-624-Sq2AsWD%mmN5F5p|m$MRTL+;O>y zRN!<2o8&#N-=_X#Rla_G`_3rMWlXd>9UO#uccvrm0+jDQ2Cuwh-!cbh9nQkdPRw7$=wj z%0NI-YFe=kkO@=A$b}-`;t~CMP4ctFOguueEV6z=RnXl5$tHJ#fPg4nK@l6Gf*pIsf?ctKy?5+b5R@WCqzOtQUnoH)bBQTn_T>#FU$YFGqZhmb~CY?K4nVdEDW3IINfR6y1i=%48t_& z|Mu+Nz3GYyhRxZEVNRDC^tSBzFvYj9^W0DG^ph91ZEfl`qR&t4Ov;LNJ!e!#`OeTZ ziNY7C`9`=(XE*-+-FE+b_X4nHwZ_wV_qJG;zN7yK|CJ11w(8HpUH;Z9I~#ZRhz!!H z`j^`CT(-vdvdaOB)3R%$UF+IPzK{ND?EWX}Xp>WgbjNGe3{M|2lL|}J-Z8al&ERye zi2=U$RW_X&!-`KxADoQokPa_?Kltpa-c!c@vG{&y*x)~p-FG=P#PckBN16R$a^`lbD8T3c=P;=&##+fU~l zQ(xA7@{^{8#QKaTa5=-=>|a-^R^f^L^1ojcKobj=$34 zApG!|vN&2dW!2E4C#Iv*ZW&Cuyu&j!@b6s%yP->mj&it^>T0Y6Q zQ0cqa_Vny0BQ|w>x7O+2+`8t)Fk$Jy?@xQ}E$r9zkmU6HHOn+gZ;3QMl$$OcaNNOs zS&n&1n0fB$2jS(9J)d4Yu=?7*ZmF81%(q*P{u<$XZT{XZMK^a%9ToZ7(NSxe-}|Sv ztBQ|rSz?>MuQfODMYnl@ZL{0%XD%)MwI#*ro@9MoyQJ;KRX@`?Gspa=>bO3;t4%)7 z=XOuygK2pWRBu?S96hjH6n5=9aqXFH7ySnfiK;^9makJE{`!7WeG+EjVD^67<{Xc_ z_oFmiMm4?AX+PXMbc8gldwc2McX!_0Gl&YEwEdW4+CJ;-D}}`9n~`39%Uu6DSgVcL zK2QDV*Wmc{@No@CYUk{n6=OBrtspzzYIyL^Z@c-zr;qoHDf*cv9#kCO;1;K8e|5la zuUA<3gief}3OTR^(aLcbX@)NoUmkL#@4m3Hd&U-z{2<;VPQ{27z`I^MU<^VE=~syn5NT?acx_FnqpW|A|{ zOd6^gSX@F#i?-p09 zoU=v)w$Jb>pLs}f@#5X!X~mfv&n7(0^wk`{xr_O}f}o=|J@Es(r*0_9#=Gw|^Vp8R zZ1@+_Ii+3JVzwl|>+OZBh7n^@{O04*3HF1sGfY`1JQiCJj=ByrGzj?A# z#Qr|`nD~dLPCfR_GZ`@XZd&q)pnN6Nxw6x=I>BkNFwWS{SonuNu z=6_bPIdVs0zs%Opy*oUg3r}N_2e#bas=NC9&uxRu+rwwyA3JAO?zW`zy8+ho zYuE36qo=xinOfJwC0#1ssJyh8HKEkq-coq8hts-|VO{dq^(j6Rvqjr&*KoTf`qPuW zUM3vy?l-7gS8q%GdFt*TiWerlT@YqpIBr## z-<&noVcIJ30or}jHf)%Cx%S(WkWucvd%vBpRjg{$^5<-2z%gmZ>`xIT_k~uvNOQOM7hca-6eX=a$7xhxy69!A-jlgLe31yC(lT>OOC{rPr38 z>pG@H4sDsT>4rsK^JRw%UzR^$VKYGjEmfdeYsbAPb^jq|P zb=$%TJ0ki%RI(~-7AAzuCX!KOe z=u`bSEt?e-alEV`=HZFO{`1%AcwJiAZ|LP^hb#&tXO1mO z`+Sh4XoUqUKp}uk5`-9Up1>aYPwbh&w5Dpx|P4yKljlM{pfN)>{Vyfxbl+2 zvIf8P!n_vDQFLu7_U(&JgxL~vv+kKj1G9$hskxwMbAI{dZqXZO-0gYM!7p_51`Gc3 z%J@oM2kqs%=KcB}^tG4T&;OoEQ*QVDl2~wS{~~u$Y%lFmOKdkB46kr+Ec@)GaR>o4NeRk`xtt^_VNahQ;RY zT(|kgvZdQibke6(EVWLoyLR9!sh%`!yZv#Y=g_+WrVEy8&k1S1ES+MOlC^xn#-+R| zzus$9d`iM?4@(LcP5jpLeEuYdHQN%Ux5JMnx<-61y%N81*xs8XoF)qwl}#KHm%d-@ zDVkdMvOkuYyJ^RY@EYE}duyBCzE&J_Vtb?O z7-ysPQNk;pUv8bP1}_ygSx<%VkK%^N~CB_){fr;h!^R%+=W7a(FONeFe<@THP>v zQt-xs_vY=2dDgb@iD+cPeVg>1qv|gfuKA^(E1sOP*W`-hT8a18^lqUgv37WPsHYuR zv~h7A5u9V8l60nj?t;gKOP;^(Jv&8j-M+Y&3!*GcOTrdqMn7rl@*_f5Klws_g8QGV zqkgZoDmc10?hpM1k7WyW~$ z^B=Fre`R`|p;;B5r^NP7d{MIHf?clh`M1wno<5o7p!1~lk$+v-uo^G-_>rNrt$=+_ zMAKc*k%^^=)0Xc19NhU^!(*hh(|XLf4aZ0BuYF*1%d-C2pvA**SiuR4Zo_r*zF{o1#zi55JxL+TGQe)2D*IW^H+`7-WQ5HAO z$4s1M;5@N*Op4YwvvsQv{jB=>;ltO?ug8X%M!kES9ojcF*Y~x-z8v>GkEgF#|6=Kl zXU%(ZjwX&AbgX0f?eC}DrvKYIgfBZhZ*Iw9jaNF9m zB!;Q1KWTRPbNz55QWZNX z6TOTRmvKEQ&XkxK!?*~X5)=1Pvqn~J`t)9X zt)*6*#5TfS-Nt#haa~kGqjN9}_Q@@DeCJ^C93u)lCo|b8!a7Agq&QQ;?himF-%apn zIsW&Ukt%iwn%qO|>CSvYbMg3Yrj0sSlGNtf3KLa~egKf-PjKQ1>w$?NzYMsnJu zKVPgz_voXF9fp$LIN^==L?x8GgKuCYzi9guGluW}nGLqL_ zYd(Icb2p=~U|DxwiLqB=6DiJ=m{?CV26e}h%)w{;jW<)p) zHm$JAcN#=tJ~Dd`1=vG@p%iCII6T91*vV1Zw?=E*$3{yE3y_JrQ6B|mb zP}M&po_%}1vw65Gb{tk6jT6y$FI2+nm!KJM+kXFXoSxQ3D>K4A2=})@LI??OnQzuban5>ar0?Z5chbb{}Z?zyzo=^7e>y!JEu&Xko2^5w<(Vb^X zOl%+?g*tyXl#T=h$JbJrw@frmf~865b;OjISXXF?=KbRx!-sE9J$6*Z_QCpB5v%C! z13zKitJ!hyHvXZ`f}_JWt76VFdslJdDx65Bgpy0qL~6X5;IjX@?`8_SBooaeusnj^ zx=e|QO;pFCRt^_BjUBga%vK6JD-+EYVc8-$@Ujw4(I6yR^k`wM&*rV$RWV1{$|Rgf zf>Xqlu>MrEg)UYdEBLoLe!nW_043)W^XYv7KcUnrc3;G;YTQ>)8-G+4bCK0tgcC(L zz2KM*j?4mmj zKcT&atPA{c%2;%8!J11H<{`5eC&J>OPi0CtEklsK)WhzFC6^aRP*|u;)Rn|sNqSu{ zB_=lQIu(gpExa$-c=Pvl5?c?eUcg(R%6!7A=QCsIn>SOk`-AUI3cJ9V6Jf4!LAc6F zOx#m21DOkU^7pJYHH)V(Pnl?y2&)q5&?l6vgpC}GL{Gafo@q@5CaYp+WTGWFQ3AIZ zQ^M*K(PlL7=;x~D<9~<5_QFQ4=dGs~5B!8uc1$CmU+el;VCs60#CAd%7o6vU(}x&S zLb=(D+}Gr}dcCVma#XP+Q0_cVoQFpkQ$o4B=zQ?)XSy$Ya~v(X9ZEXmgfm>+ObI2Q zAQ#}|47~PDKK_)#Vq{%8DaKBUX`@VuiTkRLN4-umYpn|NP0FRPi!#v|F%|^^(0tEqhL3=VhX963k6PTV+b< zScW36YBVD0z2PULLRIVl?A1DAT|ed%_UHy$=GN9;XP%BWEv2w)GJ~%H_8QO!GgD$> zBXR_)`?SByD~*>sU#MbRpusGh$inFvXG&-^4js*n7hnISjvahKVg53s4}{nQp{W#S zN=)3HHw_uRbUgm@K~4Q~RcsS9nu!yc@VsYAXmmAu-0!q?(gzM`-onawf^E2HS8 z&Xmymj+EJy;sR>xIrW!ghrLn7wn3XGapEMj$&}FMV>F+RewJrvCuF^$un?KiY!b^R z>7~h(n7CJ$(Ws#m-goCa-naJ@7AX_GPGHvwdUY}-CN|fcf<${5+M2G9AKsvfosfx! z;zTG;`xvH#4OoVJ(ex0lT|}8>6NP!nL<0d92Ue`J6GVnT{W1CX)e{4Cv*|l+ffrWO89N*(1qH^o_)JL6c=T zuMEy8Q$myU7c?-+>-4y4cGonvmBONACTk^Ft%P1AOo@s6YfVHZbx)Xedt#8-Mqz<6 z(HIhoA!(aTiHXfLCLqzCo$7(Q2ao?GvE8uty}Z5jaKcYm^E{^J$(5zS&YSH2s$!d= z%p;t51Y5|IP%aj&Ic)d3^?SMu!7x8V(~bH==iss8jt zm`XmV$>i_&f{;01q<{J*a;bw@rUB^4KyytvAtf!3+ z+W2w?-3bh6hPe+Q9g2B`RpDIPB(<3+mi<4KC=i^zPDt~`vOZHUMkk*@q~km4r*c>?Il zZwd4s0Awi8l`nfKeg}|ufUbPe(ua+hbQSB$JuO|Wn2ZmskdT=YU3nBn-?1cQgG5)pj_J;kqz9=hKR>1TO_IDx>dKcd-8quXCw1i> zf?n+;Sxf55FHut5ha!C_U3uUx#ZxIVmC}{RiL@7`$k&uEa$UE+M|SavPA7!)G6dR+b9p`>AQpUMYgiNj^BK*nvsLZke{3GXP{NaZrgHvMQL@#tQIg|0x+$ zi-TI+05Lm7k=^WfOGu~_zykq1`S77jF=W__FstPJ&E%BYt{M_{{j132t7tf~Mgy+E z)D>7E;I-xMj_coVszT9JLM@fhM+^;=5$a`xyd@RY5n1JjQq^F6Z8&JdEs*Gt3jtf| z;zHCR^A89AaN0vL|3b%}m_!yf$(T<#_@w9;T4GR#y_>T-MVV25_tphzLZ+Dyn)!W^ zHFRMY&FEI!o-Uhfczp2Tqn9+ zSMq|_iC)(UbL18YIO0SqAw~eLl1J#}5hffz*+6t}APmt0r6n4OJ`Kbm1kg4*2%>`! zBLKETVB{q*<9N~-fl7=(i{nXS1>Iu>h6tc-Bn!x7L01IOHXaI$9tzAjzV?ei`-{MU z<7@qe-Tj4z9AEoD*yn+85XaY63AQN;!=J?u9QO{0MFOIJb1U&;mFOIKG2D-_hH^k$w0JXX`oi3Q!6pz`21Q)-&)CF z1kgrXB}A)4i~u+dq_Hd6k8>)-kUe5ZW6r4%Lz=~q76_niB$GrkDMkQoBb)4%O`3Dg zjcQV@n$$s?nwD^<4BV+coO2_AGD@J#IOj$gWn4z}L+1vXQn>rrhc$Nlp*JU+7qK`ww=VboE_-3&{N7fgij2?`9dOJC_&DH2I_@Gy-9!AB`@01BDFp0E(EG7oR7+@$wQ$0H#V&j;~*`N>xw z*QF}+-N;dpiRFPIbd5lH%&`tUTbUuOMXgu{R z{`k9To*xa(KjwkQ3iC70<@(f2o;C({!%sBWPc#V`L65jlNA`Bh66sxjSUFCL9t$HG zFG9tOP)8axP$leBB{WCC%|vJC9-pknLlaeeP^E}4ChSl3u%DRCFgU2f<-4%GIAK-x znX(DYxOVeZ1WM?nh1S?NVz#1VrH8Jn9@{brGM+r($&*Ji=%|GZ`&i8C>_6<>5?uOi zGGv1JAeb-rPzOFvudqBJoF1w!otC5c9%R-;gUf237fgjy|1fUij1SH!KwPo(Q7>c?qViby?0NupS! zUaSDnvp8HV>{~diOjqYY8F*0EXeV7w&n?DjYK( z9`NDG8-QNZA;Z3)v*wcs72RJ0?@foyH$M2LSii3d4rgcutegSs@ge&AD0YzD+~*Tc z9wKK#okTuJPo9O1P*kR++X8m&YzF`Zub|f%~1Y?m74P*e*3@{D>=$j5W5zN;dh%pX( zo4Lhc)m+HjK{O>3YftqKuFrYcvof zAc6#3;F*AYCQ#!@{16a7lqA{(s_gOzNuod~E>Mza z6oN(}olVUAqZ`&D1T9K{uZZv!acl7tsrZSyaa2-7M2eC`v4|*E0=|lfuS$R`AY1|0 zXe1yam4FODWGDfj0r(8KEv*GqE#Ug;MgSU>B$@!#q$J@bCcMPlYU{`=m9E{XcZ{|z9ivGa*Y;~M6nXkL=sI(Kr^Y@Ome3(fFc4Yu8lxS97u7e z@;*h}SCWuYKuU3&UP%#^N)lC+xJqHeu-AH#ikhb#+y^NllN8ZN&J-4lOp8UM5O7vv zTwCJRWj#N1vB5ANb&d;v`J0KHX;B+iLMRx}H3ue;zRu z-I(d%irJ?Kpe4KngS`aS=#-`|_qW>|{;^%j{$X&^Foy zBijWNI6#M>Ylon_5@6OLus{G^3$yt-Q82Ul5kMP_5DtqFj^O~2LNZdQp#+#j3I`wn zHeKc~IFU5tFAzW*Ef5YX5RTyh&xPc3p@tIB>$%Vz0kl!Z#c-l=#>H>|#>H^LbH>FW zfUfp}NcDn98v(RY#^-PXc*f^&0(i#fZ~}P7=Wqge#^-PXc*f^&0(i#fpn#LEmhm|V zpd0oDbol}_5deEDb3z<|aY6{7RhmJUW`zn3oD}yzDIUtX6)`jH^Qc zEs;$Q$tFjlt2`~i_&x;C64j((HQASQ!(p5u2Vk5b2Vk5biri?Uj59<4Z8V4?gD4FI z&=QPyPyWuU{U-10SF6D?<~tvJ=l4PW2{i=ju;~#jb;~7T z@$Pe1>>(4&2eFEPqCV*K*|f#o*FdHL2MzcjWXHlhF#r37RG zB2x)y0Yr-ua9&KD7jtd2kVFf~1%fFenBoGN6p^U}R8vH?0zgSCaCBw4Drlg_&h@UX z|K|vC7d~)N+}9%#o`#DS3|t2p4<7JP-1ks!3uM@Q7S@{m&T~#v9lbU~CWQ}D`2A2d z=m>)ho7loq$Ii@GIUF0d1v2OP;Jo4+2IM>;!)Ca!I+uRmz3}_l`)!cv;DZjuia=>E z@Kv47bzybr6_Fy=OcD1-51%wpBi5`D_vd&ie~G5Qq(6GJq$M6pG#^X)qqX_lqV}5F zuej~7-V=Oqf^Wzg$DF+X2&dn&+zFW7$P9g-jq11oGr>RPoQspKS83lQGFWkgRwMLuouvN0z>L6rJ@xUp?8(GDlIbD04B@RR80}ehYzUe@DK#*Z` zf7p8b4Tl{w_0K#GnGzl-QM@doj39U|X0w1;9eRLYgTAl97<3#xPb+*yf6?X4T$}oP zE3T^pRYPwbojCp^G#|nTA&PESgI-hAM#cr>|Gf8hJD@EXRP7zIn@(?$cilHR!zc|3@cpJ3D2j3;(XGW%TW<+Ek7CuHvOz+ImF&0@5u zG3JrlHyQJY4<0Fo03}F49he=(n!=olU#>muHR8OOuAljO1~D|ieAmJOm@iH^0P{rw z2VlM^-~h}cKL=nQ`8fddV$T7X=XV5bJ2C(Ga4$b9C3&x%Wfv_!{1kiX#~v*Nn>DK7V9V#w$t>o#75I{AE%uebm>6uua6 zq#pG>{c{tm=_mcpq)4>BBiY=Y0J^`pc%ng9`c!|}$#PW$nfj87)v)0&V zr_>*utM^1Z5HfFg;EiJaqEt4>$THYi4a%^Wn&4<;5XA5Bz#X3anQ)U`l|$79jbM1Y zN+#8kNkcR?G*C>c7nAbYLXj^t!lu2kvU8?dS3Zipa|tqGJP@Y1Eww%xIoY;z?q$fN z^FX@d-4{i4kYO|9SZn#O4Ajl2r4f*E=L2`e3A3}N4>-5UAQCcJe2}FW;Ql5PhS*w< zkufzmsKMnsYTvkjyWXa+l`+qF;F+T9YLZ(EUyANU!WVxgvOq&l159MWxu-CZ1?P^z zL>8PY1ru3tE(}a$frgDX%0w3E%%cG&vfx}8n8<>2VPGN)&V_-AEI1biCbB@@l{U&m z7ATab0VcBGM7vC6!HH#=$N~k3vQC!)b#yf!6v zs+!{sSjlG`d{#Vi|NS>{;+O7CGA5G`G8Ie3j{XtcBS)W`P^X0tS`-YLAjq&elx*8Z zTnyM4yXe?0=#DxFwGP6N)94_9dXPZA7ifuOLHA^VJh-NTX9AsPg1$(l>A$PX%1_4L zl8p=xH1Xt*bZELE!)9i(O6OkB%F-WWodg*v4@ebm0;Ow0hE36Ab%y+Nv6y?r;WlKN zanOv*AC4+#WsF^TPcsEFzj)vm&k(ik!@u61+0Ru{A(PJo`HK0RSQo$2JZ6=QY2<@O zzT6!RKDsRGRBfY-Y2t$>MFv;+&6-PLgHNPEYiIf3tYTN9%uyH>$Pz}`2GE05FVLwP@xFAyk2|Mg*qO-2bqgJa8YpuLMf+kfw6g}3iDaQK3T$H zXaUjnB~nI-)F8CNX`qa!A;GQB2$6(gp>toKYeF$~Z_#jOY zuI#bYm=QdE?IT!E6=hyUO+~XMdMLOA3tCyH+~Q8q1P*c4h;>7e7dHS?eN zx=hE>5%w+IIQYCfJ1b>ev-o+tMiFQjfKMr|pUG52}kzT)e(4Bc(j zdmh_7gE}re;G)oBsx}OOIk)ZVCo=6ahNRAV)ytC;`m^qFD(D5fULv&-U3uB3lWl z5fU{@fQN|iPwL5vl~-0mL08z*S7RDm|#X zi3v9)AYM$wD**{&B0&kL6cd$7K$V!NQUbgsgttV3CYhewObL;x1T;v91|^_TLNqD? z9wgzR^ak%q5}r!HO_I2&1l%HtTS`DaN#rX5&q(5#5>QJLwMsx8Nz^F;J`~}j^h%#f z5vfYRYl?WS0HQnedsQ7-T>_VSDIb(7oYXzBWnql^+7dty$XAj2SH<_DG~f!9vzr}8iP?P*r0{xE<(alE@z@tzJc8|@dXB&-@=^?{r(6bCWNg%@}%(D#2m4^(Q zAkQ*`k1ZROwn6_DWM1;YOTIjb5uG}aVN>N)pP=`&L zXDRgZ2^ls=o@E@y^z)jg9r6w`aXb*G@S4-(zc+k&@%}wzPVvDh#hHzg`yj)n(X-ZK zHC{9w`KeO@nFt<;;K}>b^}v5$4WB!FfXoRVIH9#_iJ7S z>t%JXfy_ldxTuIU@_o$QJfAM8fmf0`K-B?L`54eaCK%8Jm`M_E6fc0LaTKn@C!-Vre zIA4ArMR7jVVSjDF){}d+vx(oYP-ZQG2NHPlFc19%0R~y@?+#cUdi-2P=B}b~DC9-A z256rBt>QTzsQNxZlL#CDwY88$B;6x`vCHcyjcYN?pF_7qo3Q&jrbpmS*CGW|s z$$pl=64>EMos+hn*Jy*gGLSM4q$VK-CF?;Q_IC*^b`$XrhpF$6km~twP@dYb{CfoT8JYmsdFcf(`q`2cHxPb-S0v%)9rqNXB^bfu|w>Y`VXp&#$e| ze?y&C9JJ!{*Qmt7m2Kj@zrW!?dx-~mi6@|nFCBKikVU-gggPxaXi;1k995k=e?49C z2Qt-sP^}2@uf53~=NrCL#>DVIj3O{YzXgFh><>WLin^`N)wMZi_75@-dElX9py^+Q zY+VDT_Uv}pbBr!|bP8qGxxDQ^4NApX_(R%{KEN~Zbo?HEAD80TL!3297g?OY?{ofs U!1+6a^LIMu?|YoTGZlaT4;pl)pa1{> literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_adc.h.98EA396AAD9DB0F8.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_adc.h.98EA396AAD9DB0F8.idx new file mode 100644 index 0000000000000000000000000000000000000000..3a0db12e973015aa714d15e8090b4946bc0bae1b GIT binary patch literal 11686 zcmYk?2UyN)*Z}bU<9)jwvtxvVa59cvMuhCL$~YQGl5&hfc0yZIDQQzm5-pmVXlbG} zw1?1;jHsx-=lQ;?|NWioa-HkCfA9N$p67nb%&s z-hM;q7v)1=#NrWm{dctVeReri}z6g+w~L&BkA2o+Bl_|#qX*pXn~g0z=IBG{a&V^uPsT!YhkT0hNNd3 zx3N9eG<;tS_r;S3KELnwR`%n{7z)iCG-JZ&pHOn@obrLfzwqyrW;%6yRuwlT45$f+kU$Rb!`4$Qu9C%>kHlyl&&q?p1P|ZL!PU$GOj^oF46DcI} zkce|)Yo!TrVb@=m4&OUPzFlp6pltz&81+?fHe*U zypY6oJE!PxzL-v-h=C$Tc+{oOdc~#J+bOh)p;atE(}Csbb&d;$6NnN+6wdhMH(RHF zKj%!LkcC2a+`!bTl$-V|w>yj=aF2(3*!aeh83yu8^Q8zRi6KcWESPnxz2_+Rwo`b; z!Yh1K?W`Ejh;LOR31oASjY)iL8ZpOVsMlx$kHqi@dnG-}qifosLJEBx^l`!>JDBSf z=l-sYLK_clxQykO8@@67X+DNP6$@4D*nx4tvC`*7j=w2nv5J)ky=wXCqb~4|`W$z}nNd)?M=)-9Zc`&uF z`a>Iq02Tsp#YV0v<({W6noPi41m?Ksh)=mspF8y?g%mNQ;4Wpkp}#>Z+I0$nY96X_ zlA7M_-mcItH6>ug#Zo$aQ!uibw|Iu^MXPp2bBoQI{xa*Pi>k;;1>(OSfSXC z?U4cPuNNtJv*3-T;25yBp?SJFg-#Yaaj!b;7I5p{um=?EMPQG)V&rr4MjF*qs1ZXA z&bY#%%Q} zf&~v2m_n7Y6S6zKKF=Va25Q3YY2@mAr8~rNCJC>Db;8l0sJUldUuP2yKj7d2X6bhE z)UGm>Y5x##=D`^Y=hObbxxATw%p#D)LlQQ8Ote4y?j~6Zog8%HqprO^=`Aa|PeBD# zgr@KPWfY+jTuH;FVkpJ?!M)6di?{ik%_gt}mPik*iXHo3gyx17%_ZSX7BaB}%-3re z?7#7B9)Zt1e8&3gTU!y}6YzyX8V_kWhMOx_*6*^^nor;k3wN;i7yFnOo+{f-!IKA1 z9NaWRo8F0A-4_t}!owF_l2c|+?dX$VB}c%Q1z#+h)8-Q-*Pk+!ClJR$9Hyi2PS~Wb z=6DKyV(7yf&r6#S9^Unw!h06p~6&6YkJih78H~~ zNtnIC%~eB>XU5TR7zbha`JPLM((FnuEg=xdLm;Nmu`1X z6_%HK_1X{XhKZF(IF*M~%U0UY)AU^r57kPh@e3v zTx3GUM@Qvvl~N;6!$1uqTtx$YXZlJ>jizA7fF0h{o=;agTJ~rP1!YhcGIhSbZm`CZ$m5V4(xgx>cv0T)ldg)Co8+;J^q+)clIJ8#Z6BP{?B;4@WUPShv}9 z(K8Cyc({hWn*8H%^q^xsnglk(W?>X3?+g!Gx#WTt3AZuOhVzix)-JKA*O$T*4xV6V zWxSSYxa&Qm5WqkHenax;hZ)?%=M>6CP%aYA_>g^OS!;eR+DpKO1slw4di2<_y-Xj4 z<8WLU++L};f~21Y+9cc}h8Enc$IMRem6frha2iev`#|ISA)jQ|7SpgJ1CE%b%Uu&y zO@j4x2n4ebj7LtNk&43S_(TeJl3<5#7G(ij({_c8*Cmk8LO$lzcf@OhQO>I=1c@L> zBsA{0BRtV8G5G+29uf55aS-(6O4iY66+Hr840tg@X|8IHE!R7xM`17Q6~f(i%F{)T zr)c;roE4rwy4&tb{^8hzBwWWp9lmItythMJZ}@tB0O?UFt9aI}Yry2x{^#N1ZBM zOCgAZAl!y@4|CryZO@@l!9oT0N?rZW#}z-e9U<_QgRl6g86KnZl>PQoI0T1;BG^*? zXP=*?4GlZ9;EY8R%2%Za{c@vV!GHyBr5iRkbbTtkP2sT^9{<0)%}&ktn?6rFN`Z&R zIK0@JcQVG#VHAp3D8gNKTiE@Mg(q%;0BhOjq_;ft8c506Nu&^8V6`JNXA!i80h#&?NcpDxbn*8H5g?1j=ad39`G|Y#rxkbT~15eDX(gb5wovnM% z5~$#z0uN8i71QFs&i+cFP7HPU{#9oCXLQ!V#peiIhRecsx=d|?!o%67G#t!BFs85J z)7(3*O*IsLvhWkP_{-;~cBuO+o+nVrLM1L3-!0CWdFMA$xXHjxM)=jhAz{?Ls3t24 zDLkZL8*19B#^IXXCIqs1$i^~gynFuss=p^(B;d$_BaS=wnZmm?T>}bHJVfE6ZsfcP z9;s+-O2Cr=Pe$0wgWPY}zYDOV;3EPbOnOh(r=YMEn=cXA1-pb_ud2d+hpYW(eVK&) zIq=8wzryj$Hpix4ArQ_$IJRI>Bt2n%*9bELTVbnEA1XI%D+0A*sKxCor&6s#EB-Ep?XX=)NX&G3&i~VDYZC5apbNM8VZ2(s zM(!F4r{I+E`BiDM&NWW8HYDuIf-7#QEBef}ub%0r@Qi_H_)C|~ z6F6l}`8bfCNTHjBZY<_u>oROpPWe%I$HF^I;M=tROqHF>>X7C8MlZL}Y5GE3S z$bwK#V^`m(>jVnKP=H-EYFf9kcH=)3+8JoarIlO0pkDK$iYoz29xSo!&%4ZT=}@$z z@Kpp~aThqGdmv|jS|x?sEZoLXU$38=s;0WjjX)$1kyuOS(#*=4+HDlRu=n1QYb$BEfQ14q%q`;@|Fc!|^CHl}LkHHM zY@~FqTjDZr0ybi>!Oh|H-fhNKJth>a7_h?Er4ju1e%EJHeF)eyV2_vLf+LTW67!rW zd}HAoCj6()x~n&47E-9?p%xpz2s+w^sqGZBL0cGg)H(B-lcoE7NjO{t;aF%RbOLm0 zrk|$ZAPElmW9|A3|69ZPO@0(a;2;uyY>!h{8J4;)n?gJX@i=!r9}aGiaKCtqKoAQ- zICn#bym_{*`+s2(ED|!C*6E(ntvvBI`Ft)9xmd9ta~^~o&6z>LMg%r^6Pjfx<5hEL zFNHiF@~|+6$r&hVT3zrbP$7Z}JXb=B|2cAB!jeKY2i4fwhAl&t62ikN)Qg}VSH;$+ z)0hvUA_~4d_+qbiNPnDq-+5dBfj9=@@Ky2Q(%1GbM(fYqtMDh zD<0+lDlhvo(Np&h0S6u&a2)SfFFjK2Y!FCb6|54riHxHb@W95GKl&%xFYd@a0{dW}P-=;lOJyt;N!%x4D=}E%O7+?nHZCr9 z9ED;Aig91&0yenr@u>+V@RWh42u{bd)EH~ z16OgiCc7%E3x2hL!gn!z#}|$VirL*)#2ys<#o&**-M8s+#LY_e2m+g6lQ69((v7ND z9z03Ii5w(ieUzoQdQB1gP^jaf4zIXRmxLX?@ab$Mfia z4{vY3sg;^Vp@V@AJiqie4i2l?(GW$TmxW%u3;A}A%hZ$~`iQ_0I3l!Q5!fm}x@gp6 z5`M_QLq>RU=rf*X)=;{i!cPu<;utQg6))TsW))4~B?~X{dePKkzoY5ZH467wxQE+> z!SsK}N~m6^@STJ2I7JKJhRepNS;r9QXQ3ZE`&MO?@1rq8VhJR0kbvKC8t%Prw8oA& z0yP}eV6To8yw==(T{fP80w@SK-x-}3{~VflnTA)wN@3J1ZgC?D#_vra;XnogF?|&e zhTpxZx9JIiuPl7U#j-_CN9m<_CxuT8e8RstZ3~6FCDn2H{>usrn z7o-rl!@(WQ(HCZird{D`3Mb*D@cfjEAf);#G!lzvSajnZz2{f|MhzFsf z>a1Y3BcT*pd1%G6=>6z_7P`MuOe0_jhC&PLp4;|*_J2Xck6Cz(4{EYrbMD_g)=vo- zfst^j3SXJ9XPfG=XC!PZ23uV0yKiREf*j7K>i-Ph;C@V-<4=eBt=qPtfQ0K0N`vH>gbL{k6zo~B z$3BI|ydA10HK>q)KMVf2*w5RVuD5I-PQgnIUN{q5Ihh0}R_!H$CoDX{JWXV-sBkL| zQYdDj7(t=CP5blieXj^OaNvOB{uR6O&!-#wDYS~96-)WR6urOHT}vp$iXavzb)Z#WSghKnVjSxWjIZPtQ|w&!gbPfD>Nb2K{$m>&hzSVgd;) zBw%+nJ8sNEZ5S~zUKGX+N;9PywX%rf7ALORjCvlS#ZQ@Drr{K@*6X!lzG^C`Kw{Gbs}p^AeltlPhSRa_eJ)QLg{3mN#0tBO0My?jF{ z#4`|&*PgDMjgvGNhf!!?p#i_~WAG50$5%Wn2t;rYfyJ}w{@E+i&vPmGioh3ZHWc#Y%uko;nCSHc$xm*A2x8(M~jGY@}XT1CQEJXqm{@=eT>j<6jm6f!u- zz~L>}CR1S|=Tc1|or81)Ui*WYdgjC$0(lJN;qXp;ILs)V&7e@pLnZDyFAix;Jb7kV zErI>8U)V$175bXL4p~dX^(@q5I;3T8E>vrIL7|3+8hlXkDpikdft?f{a_|uQbTImf zf6d=vbp#B+Kxkpk2a^Nh_0MUznT2L7fA92g_)?NVA(eqtTuG`mO$t8gWfaUM!5rU2 zBn^Joy8rjCoLJkW#*m&T+AYH=|78D+_@Cad5K!yZX*h?694uw^pw;EWC(ZdtpooJaOt|g5 z_xs8f<0$Na9l{CoaL{bU443CL?8ky19t)RUn#4vC3e5xpSqMZJIWqpb|MYMQ-+1_j zh572*c;AYLF%+U%h{k!)7<|jjTUWA$f*7Ll+EDLz-3!L7q40`_S2&7%<*+KY1RKk)Cq?}rBzHa; zEAxZEYYtxHnD<3*Tvr?EJUC6k6ikKj>S~qS_D^_6!;g4)ggZc2&nv6BWr5uU zY+10yj2=kN&A3-6{fj_75A|3_`))~Po5@yDu;;)Y2j&@+czs-5HwAAVys?cV(7LE8 z$fB3P4GwPLH%beoHtw?y?IZAufnWGf;0oJc|J?O#Z$AM$7VNNBi%k#Cd-6M!!XDTo ilqC6g(1r)-&%dWn9Xvgl{GVl-^Rip#T^S)OA@M)K&17-_ literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_asysctl.h.6BEC768D9E461FA5.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_asysctl.h.6BEC768D9E461FA5.idx new file mode 100644 index 0000000000000000000000000000000000000000..810ac0193aa7d662ca5c618355f5a24aef232137 GIT binary patch literal 1174 zcmYMz2}o0M90&0CD(t6{B$cr!6)BHgI_I^@%Cwd<%T$tWu1MXc*35Q@=AEH#*}**0 z%vzoxYS4w6VJ-tT6*G?xD=0GxqYz58H2Xbbe;+*F&2p91Amse0!pj42W zDAPpaEwu(uwMLb29Ir8WrdGxV_4NxLymci!5o~M}U zKj`*1O!MW_W@f8v4dErCtKyR4YqbWsG+J?7pS!u}T3M4J%+?^3h$?x=5#J&wD-FsueOVLKT+%)+739yu6-T}&a$hTjqE z$H$zJFVJv-CWW?U>fH>_n~eoAi0w`N2j_U@b^b>^kPB%jq)EQcji2{eH^>ySAdAGj zeWNwcdOF~REC2yvr({26jC7EP91rm%q~=7<-G_QhKV%;8$WG%V2RfPpCWDYgAR@Ea z{!F2rzJCZs&Y>Y^X_jt7V#LT7 zX}Gu)lY8^JasEj+Q}6{}GL61p!?m3Wmm;S_I(c~x1Gh@;U%MnAdx00rwCE~MYoAdZ zaT-|&!i^>_vRXYn&vH*jR)LDlvTyCY(~cn4C1fc`N%kp+8f99=20gM2WTcyux~pEF zUtfeQ0SS37XLDO3M{GD1$WahQcuGFG;9*x$jhq1)B)io2eCJ^0izZ|)aLFz=1S+D= zv8L`JyMpUl)7Fk4f8G0WH{+M3jd8~_0%=3|dGXz`cdE96YbB&;hvG&Ps^^CR*Z zI74PRpHW`5rSZ!IvK-{3+sNWu-%-qcLe_wWe01m1`VNdONd6!vK@tgZW$!dr8HO3& z4%^9dX??tM!kHhjfUKiIxAemZC5w52(T=}Z@BtsvkN>oR)uWIyKS6a+yGMr4Sh0|k-$rkujifKn9YXc3VCEeNRd;1pMsYaZnk zud1jM#wj=v1zHZBK~QT(U`8UIL=F%5sw~g`fX&Mb9160W(E^fYmB< z^SdeP1;e=>=g0Y?adq|Crz_SKha43Y7o9j=A&Ls$5mu0HRCwZ8bw!{-MQM@zSR0SG zJKw-gk`@<%;XJWWBxwR3Z|ReH@4Q`-)yY>RlRzfX;UxFc&d;bz5&FzRkpxK;Yq_>8 z$#ip?jo1f#=KNR7<8^KA$_c)1p^f-5fy+dDT5Qr9(;S`h^}kOV2eA`l-rM!HEI_1^@eom8$2=q^~K8O9U>lDI}-vDa_s)E=O^Jzy&5k#;0r- zO{%Xzv7f+x7Nx84(r;gg$`VBdfeNBGz4#bEODBFX!U{zbfhP71o4(r-@5TDoD0ae5 zI$qVd`3;hI&JOWm0*6_By5}3|`erpJ6fqD(&n>9qd-v9dfj)?%Ad2D-A8Q=qMudKd z%LtUQeln%U{|GL88h|1MLgr7mxv^OgGAprvJz^mUX-vk1?4u`dM-XB+aHF>yHI-D0&F=uoVt#gy_%gCkZIL z!JBrZG6+!@M|6r2O9@C>y+&NyXCA~f4#U*={d1WUNM?eI<;tL1v z$#PXjRfsLXf>wv?Jt*-U-Etc7Z34Fm6+)TenL|T=pFwewz)5x_?Rr}?Z6f{8qR1eS z!TR~;bopb`6Ys8~kbs1a)mHZNeU})`I>db7)3KCQ4rUt-66z5)VNI7wEO4C?rtG#ALb0#Mnbs2MQ~&qAT=C zVn^;M?{y-Mgh<-IdC=g4ZtZv_;&cM(EXGAU^~u}z2b`!UP|w7vCAMxgl`2k%K}>hk zSgszHuM+hl?k3R9>c7)kNxW+;`%pN66WveUl+QWxqlfwt=M%_h^;roPaR$|!AEK}Z zYuf)%XpK*eUz!TBE4b2_gb&MJ+^TXBb5zfkq}uB13OA8V_-z znm{%CZ3vKU@|n5PVg$u`0_T~SI<-?ipx5KXZ%_TBJvY1@0mN&-rvJN;Y2U!1@2;Mb{>DAvFl zx)J@d{vU$1-*NaBfm`gsaQ@wMiHVNkClq#IM{gYdgV_hm+aSAJY2cQ76$+t2(U8(ENjtMCN`;0t zmCB3?x!R#!{_p$$|2yBFr^oYrKj*yj`@ZKrC%T&I>MLc$#8gc*Z7ofY8S!FbViU-( z^)ahMd&s{AcmOKcfylGCcb$h(Z7Z z0nE%HFnuU}WbCnY3KgV1~mgDecP(}&>bu+ja!0Vy1TSQcVgp^oyL zN2|}rwNX$3mB~ZbS0!Y`=*#ZmN%%7dpE;q|l9LP%Ci=an;KhR%FH|l4H1RLro!=lg+d$)aX3;%&+Juxb6PQqKr#=>{IsDu3hOimQvCm+P{cqHBaCfD z!JP4}-^Pw6a1aiTAG%(BY_5@+?;0BJW}%xEy7y7%*n@^8GGhotF%X3X`E+>(w#WNY z2;w1#UpQ3Mq13y1SM*XTyky}eJAVi!yZ_NE7P)CGfkGAv*#$%3W4HLWY)m?Z4-9<3 ze(zqJxOZ#r8wvv)4B((kH&<7OmZXj&5W+(UR=z#?-?4jpe8ma4i@;qpWvGsrO>d5U zb||IL#6uG=WYx)sfBq5G{&FpKWkHK83&_2ZPwAJVS+DC6WA80+l>e zV)sgOCY-sTXfTaHD+8@K=to@UrEgefOreN{B34*UCCGE~092B2L;2j6=I00^Kvq=sa?nA+e0VihG(8N9|Upp&q z&hK*wbo0>73)5t#`oLH1kj!rc%2_DK%=Pzw(P(ycE(JFp+_2{%t;f1V&T_vKXknlQ z2eE(Fh4=qn?x0Y^LJjs~P&y?j`k>A{0@h$HR2`Js8NM$|Y5@s5vfzlR<6z%waNtiH zIRZ^AG+{xSVxb1ZuIMkMz(5mL{pG{3K(Db;iwT7C5Q=NV?q0ZJg~}Ou0{3~ikDEnB z%9+z;Mx_)SMc^nBS~d4=aP-94WfY#X@Emu;Q>JM%T~)0W2$VBWj+MuSy{?&3qo7FO z7Z1O1Y;E^THhHV3FC}o9fy+1>JtM}2A9VCoB5)4Q36u1=BBWtSeZVpj?qQ(^`>h`J z^1IiCJIe{gun>cL;gh4oW3&#|Q8)o7gg&%CI$CZf9y^*~S9AaB_~sMF^gt4MeQ zY!J3PHRX{#5@+uzlW-shftZ*_PUl?r7Cl)_zzVE{(l0rfhuL|LUQfdPJoMvp^2M~- znu&K8{XxK;19wczg)`F@EPJ4-O5g(vAFyMNzb_cflHW?f49q4CWvfHwR+#!yX)X zV4v?FFA$d-5(Ie16tht{=~`z5y#c*eprd{!jPJ-R%& zXP7pD<8WN)!Sb}$OAX0}G+fF;DQ4=4mI)Hc-!mv&5WxkJ)X=!vo2P9!^FT?5z%?GO z;WB~FDQ(-&)>6plAs=^4smutoE%}>t3Ebl07T!_D7mDeF4TV+?T5()2ZcLa^U2;Q@ zKp_u>Sk&(9>rXSJk|@M;5RYlLFl}1Mz?&)C2?TQxj02LSekQH_=}QVJJfz^_ec`4% z@}XBRg>|rQ>QMI#CC)rH`8;PQ39pCs!eh|&*YISEw2ECMoX$czW|Km0cyd!t6@@!I z+`-N*R5)0wY{%^(P{}|gF7;vZ5>oCSuPCg56~YR#?7y(#l*8`5B<#q8BR&jLTrDjo zHJsf?AeM(%tl?hcyXm2+eH29ePHz1{PWnmS#tuxwuNwn1BxGNDd8Ng8mq3p63sc za5N9m*wmXR`n}nf@e~{xaAal;-O*{T?BXrHltMiV^?1njixWK=WpvJjfIS2Dc*nzq z8B5pp6;sILArEt7gWA^Iwnd*Pyy4*uf>PCo-S&I?C}@F}kjUEh{n0rp>r6@bH4m@x zdiPUr4<+2NH6swkK@=ugf3=m0?CHzq1oS~)C}^|OV3CAw5e=8IP==4chT8*+*9HDB z?1tUK%fl0oDJq3_V-Aw*FL7`Q%U{&Rh1I;DOF
    Bn8%8I3SlA$!!KX|PF?7ms^u0+;5xu{ z-05sxuAY&y_gxr)atV~<)O=-VH_Y9>nnEfMsrbgIQFqaZ0+V&&1j=|Q!@J7y(ysTK zag4$v79L@`X`1Z$7(Poag1}N(DwIiOw>w84?lh(0ov>3VdUMr3@9Fl7r{SvrSMgRS zW`F-TrD*FT0&zUV;iJUUz9mQVgAP%M7C|(o^IpT{m4npcDU^$$91|y7e@^}JM5)IF z{6*l8FQkoC)KU*70|j3eeDM#uiq019P=6Ojp-2oxI5R5Wb@9q4lPKI`;1*UYgDIhP zk%QJm(jz!1!bE78tWaEM>P{h-gozKNmNT9_A#e#U3G33R!>bogOYnP2!nQov zVh%clZcmi8I1okPJrD13B#O_xm>Z{JM4?9lJvgWzv}bKBm=R6kC>#|=Vt(k}%Z|B2 zpOJ7i57jtVN5*ZBmG=2bp_GAA+_!iqE@xGOWMc^QiJ=cOa9CJZhS>o7I0CLBaK)lp z@$}KX^>Y&92`qsnLgO+W49_Rc`!|7v10)cDyV_|wx&C(^|3@K70!g@+`u1vm#P;Ym z3eQFG97lWKPp_vIsy&GW%0y6xZ(15E+Y4uE$R-h}W}zDE!SH#jy2HNMQOK7-KK7H> zvb!qA=Y}K`h!;UTw&HWo6OZ-wFDN(wIAC%b-sanu{xdR#z#SIuU>&?Zf$=XgTuq@> z46Rr>)n;E@-JJA{LN5os_;#0{Yn*HNKqi%d251O_#5_`0Ow!*=!|x^V9&gsrYLAx0 za6g6TJUqt-f5}FrR|WC@6z%}r!JGAaRyW7~+>0~rt0;6a(1q`FG=eoFTC+#L zAP^^lIP6&i#bF!os%lfH5J3fwp8w4Ck85&l(+MQac!)N>7ZaP0dwrz5mFjuQ%fB)2;{Ml zho^dA|9kRAMa@hC$KaT-^q5{;n6Wmkn}*lITA^oq-zc0eQsT2o*qsG;Tm z+NT;tZp`l8`2-?Zh`=^nX}B_TQtNvP`(U3?fF)Z}bXTqaPQ#@lD8=IVc+mmHmkFZ_ z2>7tzgRL-5$SqcvT}Gi#0)6=0J!o%Kuy@>B3MD+0V1-&BcUE0T=XxQ5ha5b_-P-mu zCa*49u6RYjmIYgUYIVFNGI?&hlR|?88gPhqNthC~*ZLF+#87}e_2f*XWAW+$3OPLF zV22n+7@tyo`;I~+3z66%3DSy%4~A;LCa@Y-3!^t}Wz(&gTvr-yVxWl;zMu6zu`S%G z$BTjw2R`@$Enw5U^V@$^QD~MxGj_-T$L9-rPjCN^K(82jv2LpW40UvKI6}b#zyo)X z%QD{fmb;&#U<5|OJ-wIO`1PW0It_O+(1{c5>Aw$;>I^ET5G;XUEU4{u^OZJm{oW8r zW+54?py9h0_rtxXwyw92p^(TzA~x^-o8V*OBWp?sTouDrEMCz^r<7k&+({us z1RmJB^D`N6+(t zwKN>cLMW!$62&Q#5|dw)60qXH3LgWv4k>)#Fz&)T0x>+q;10(??RsR@!5b9r0^G&y zI5pT;=k{0fhN>U40X7KP;U5&;e}w8W8n))a8n+B)sal=20}Cm5Nx%!UV{1-|-j976 z?+H|jp%Qy(`_@?HlEuyx&cQjMNYs9t;k&TyISq%i5RQ%e>z1v{?-^eyWb=@X&q!t~ z=RJIGcBGtu9|wM%(67Ul!gn=Jw5HG@fey?j!$Ef3mZ<3!1dPF0Xq?>g$MKDiLTLB| zoDecYr_f(PW8@r34S^>dJi!6=IeVk+Y~4}{KgIA9 zXV5>7E*t7qCQx`Jf=8HpFJw9xOWmdq1hOTNjh*qk2BnFc3Ws0B2#^n1tx)h>$h{iP2$?37FjxPkP z0IcvDUq-uHwA~H(N}!2{CR{5%UeTP#)z(n3;lKuaSIEb&xw-BUjA za0#Z+!9WKViS`erqC&YPRx;#92j@?K))seE)sCT z1ijt4;cJ^#e+pGRRN?qd8Wh~AGU;dwfd(ELu+w#_dcOqs_n~kG&ImXAJZVS3ROTHG z=Sm=>}a4vf*xdgeXBj>2m(yvB9=(Mx%^ zTKlgQtXQzZ4q@tzhn*g*`GY_V12LG;KlNQqeoV9aNx)VFwz!L`TlI5%y2fJ)VGM-f zpT0HE*RWQdnMq+itQSg=ZyIA`61TmTgq?VB!hSMY)3fHJ{jgsI-ihEH&e!|9o{t|q z(w9Od50!Yti4jZY-+um>f*}|RS2%Mi>;9E5PiWYk0e4JI(>LF=w>(?iMxcd<7VN-4 z@nTt>w|eaaoJ8P+^SjOs^lFa3q0l0M7RoEPEKLm-WZG<*Ux zQat17S~RMcKqU*6xGB+U>{%_}W<(*Lfp~ndK7A`kTvjo-k3a_p9r#rExk$@KoxMik z2pka}IHGLF`b+kg(y%29mbfe!$95LKJ=jWN5iAnA{NQ0TcIeMFze(7d18Xd%X1W0Z zc^3~;NMIlV??^gmh-XZv0fh(#B5)2Z^=Xasa&V?_T>{s!XEz>y-0rlxkwQHS_4ph~ g{tx5HL$taXoI7mLpZqIg{<2s*xbkx004b^e2fn8r_5c6? literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_i2c.h.7F6CC3FCBEA2F327.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_i2c.h.7F6CC3FCBEA2F327.idx new file mode 100644 index 0000000000000000000000000000000000000000..1010945f54b52cfa68efbe4964cd59af6d597205 GIT binary patch literal 2132 zcmYL}3ozAL9LN8sWPhdEmA1S}c4ME9_#tE-h-vuC818}cjun}f95~`na}6U_nhnuKk_Z*E4&$chV;(4@$RvZ5hjgtRffM= zgrc56Jv+7jl>(j9i6$y2?7?15F}@|d%eAlK?qb9#1X9=_t!||!UfU*BQFIaLVuQv= zOzfFM+FB@hz@sa=^lRV9SiFHY;@bpnv*R~fhl!F!wfZPB2xPD`bls0&{BJ}Xqi7(| zKr|FYmXSZ$eUTIE{A8(|~Gs{I#hTDO*%Bjy927GjxNkHB6f z&A3kSnZOu<&KEU36v8W z#G9ST_Sn2hF1iVHv#YmJ_6hyg>%le@Z3NobLioj6IscWK!9~FZ?lQ&1{Zb`SRQr@W z;wl1F?0ApVvkRiM<2+HM5lCYT7xr+!u0cb}E)@9$^4UH3>+=7x(=FYN!Uk+;k1hGO zuqNlSAL0$LffjE2SK&=YQvm|R4&XpX@2&T4+n<~(M0|$88Ft!*M|W*%{2_2J3J>t0 zg}&9dM&sCk(LTf_1WMTP6JhUNu3q3AK(QXy(`g$o?NZ;eY*<64e1egF8*1_5L}psIU11;&=k_Y=7-~wIm{QwNog{2$ZoxtH+rvS~V*dwqQ%k zmJq{F;l3YCMC=UCw7Yux@p{?=FOm_TCUBb2@f>^3HO((I(ouv$C@n(X?3mZf>CsHY z5&{zT#y@Jy7p7LkWub5bH@bdXNUv@(Y?L5QC6LNiXWD-Ep{>?dc_^&FidHA6wuMvZ z@0gD`00L;tWBUvJma>@w#5-Xp#c#ZID|mwgMTq^upW>Y>RxEbEntmBE2RJm_l z{lW`nh&u^%vR7hGWhO}Fr}#<~Q4mFIGbjFZa`I%r4aC-9O=Gsm?s9H6Exn1@2#iz} z$75yWn9ma4&@IFQ5YWE9+Mivg+iO^b*bn^Z66-C#^Lk`dR*krwKs$S@VtfB|>ztUb zMbSZ^gZ%~nap1b)t5XJbD9pi}_Nk_L$TZ=L&PK#>1mf6pz;T_sSKIQo14RLW0-~c> z=r0A+^Z9Fz%TS~fNM~EV`o%D}CM={Ig#}p988}Hlo=h*0{DxRcK*|PbWrm!XG_B}E z5dtA}eE-M>$31VR1`sC`NM>7J{%oYR`|GpAD15<}mcpgtvr7}s<8quxAdx*%#;ZQ; zw%MaTfufo~HCv;14r;?Il@ajWjH`DD})8nnGa)X0&6zl^R70oaUwxw-RV& zgSO_*jbDGO{{)36c+y`+yzd|%Moq@Tp`DaU+37c2lC@eF5^` XiA6zT75vU4!>dEPnlHvZVwiscfb!>G literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_inputxbar.h.AE44D51A98000428.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_inputxbar.h.AE44D51A98000428.idx new file mode 100644 index 0000000000000000000000000000000000000000..171fdc5f4d64b219d3c04e7b47fa7527f08b9080 GIT binary patch literal 908 zcmX}odq~q!6bJC%X4+998)^2CQP|V1Quk0dbuwvf&TVcwXG_gFX9}9RNt#I1iohPw zY$@Vw5mJ<5Q3748;?QToa!8}bJN&FnoMZ@!Z4^}S|I9`H`6_^HXsZ<-@) zAKDMzotIS4M?|deb875|JN5Q!-F?pLDnnhl&AOwbyKBIyW;(ld1$vFmUeeb!Mp2@M zZQm@X>MOAYWj0k?X6Y35XSv@Pe&Gp4i=uIXyES+fT*cX&#r=%JNaS=#C){N$7qoY} zW03j4Cmdxz5n)usZbDXqa_|2LiqhY23{1(LJCO^Zfbd(HtQ9`JCcgnt) zbsnt{SpWi(9cyB?a%SSi$f=M@c;Z1+!kpZ72w4M~q)^C@$7ecHroYIM6`&w3*-6K_ zw+Ckx$Z3#9LKtJp_{i^4HF7@Wlj7X822tx9l{be`Gb_Ko~kh3A1ut#kD-P<}_iChSUB*eA$=;?QJzDDE>$RGnI_AD)2 za?sBrOF>E|Sr~MdzZ6CXSq*9uGWWSGnW zd%uPTf~*1+X}PL;`jJPk@FV9z9^rGBOW%B*bj0GX#gVn2nZbJn6Kst5>Xv7x^bC>K`-?)JFgS literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ints.h.12E7A906946E97E9.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ints.h.12E7A906946E97E9.idx new file mode 100644 index 0000000000000000000000000000000000000000..3f2df1fa1a3ad232a8fc4685ba7563f955b2a60a GIT binary patch literal 3626 zcmYM12{e^k8^_Ns)$^$&d=fe-DPtMW&3^i3Z)G!4%yh zMKXmbB28MjX>v=t<*V;`zi-+5taX;Pe!u7a?`J>neqY$FH#3_r#^af|uixwE5#l1k zq{SXc7~}cKd85|R;_PpQF)?K-(jPtt*O}>HaYp# zQPV$$&2|k>o-BS&XqUD%-7zgS>zr_xyNmD62OT{u_#hn$n5{!A2(;P~(H`kwZd3+Yl)(uk`FRI&P1qsL@p zr{0)_;!gs95}ENUJ~Z!$7S*hjL2-w`9d^Y>!_2=2-Lqs-#1e=lGsdr&V%6<1-8`EU z_X*r*d$22cv~W0CLJoyK=+n`yPQ9m^E&OW^;%Wlbgl?`{vdOa0)18lE5iFv^%ljpG zz$=$hK)e%n(rWbz^&^(9dlV5LCUBT7JLRToT!m7pG74+3rlW9k4iVHFrY%Oi0X9&) z?u*RWln$RIh!Y7UvY1K7|JHu_=rAX|!JBsfGT%(z=JFO5#A{#;#SUlR%~HC3gTq!} zMbmpS)UF5QRI4LCMc@=08Xx@h(xtUDP}C5pVPfK-dTZ^lye0};u%){-NVRgzDY50S z5-8Ex3`F%+N(2RKA+`idx~y_YRp{L1A$o|@2&54zhKp)XrN#@Ep}0ce3ft|-yk=9r z=)abuC?inD&O`fEp^SObJOdQEpiB4beK4rQj^D-M3IY|ZzUi$^f3Cy#l_)I0g7!b- zw(`jSZ+2#g!yt?vTfesTmbd|;ozW;3H zmpyif>j~7epf0mB_2FiRwxVbu(87Y|4GmR4a&2)!ahJedB0m0Dc~@j6&X2Uj=j>ll7Cg~K5bLaQ^q8ux|t$9N!4 zCXh_%iO_wjx!ma9TTc|f!EZFCIj?@O#?jat@ov~nW7ICcUXeN4#^D99fQATj+B&3f z4|4bjfg^0tV#Q;}yOeEwPy|2#jfqi9P;?C+@?7F&NXyhz_nw zC{_&$KwL+lj!i~7NhNp6Kv5tHMNp*OXn7_TgpR!kM(hP%G(A2o{x5&mCn1Qh61d7n zP&_xz=I815P!y>IQrYPrNUoedA*d`2MJ<6^_U1`mdezx8YeNKz%LFd7s9)vnEAMMn zaUvYT>9O^4_n8=Py(tQDG=XTggKAYD>kTv9_oLtgpSD_7SrJ>6^Mk`p1e#dAQ2dA3 zfT&0e3O8`0ck5;J*grmhXvQMe01X;bB-S3|m@;q#@p%I0*;zY!d~a2N?GPuFL75J2 zLigdw6GeST5oZ&~W{0-?>k8Z5QCs3s6cH$5{rJCGJl1&O;V~4;U>RN5W4FG*JSiy= z@eKkui0t?w*P6O0e}?(oBouNWN9!fy0vj$SI3y!B1Vf5nf9{SOI_sB$cqOc)xNxJ( zN1a0f9JT{HI)uuN8q+@+Ii?}r2m9#kBZMO&Czt-@a5I5s*84P-6JLw{CDKup5-26o z<4qFtdGC5}o#2EH=+I?NB~yEGedE`eNjtlkS8R5tj%%0bacppmU``{IR7Sp&7_P|St7bZc^T zEnvC5HXpG$nA1TV_Z10e%Ws?MRAD0A$Em6OwJVeKPy9#LLh}bs!=u% zbmV6ru0U~%z%6zUyyHKutLROm%bW=hl+NfSPYA4H{CLQJbt6YW5iD2MALgsilqV)=5->L2YGs|EQxAf z>6TayYl0@lQI{nB`frFoMLZj3Q+%>S>5@w(=|;Q|7Sbgv-ftEd7^`sD1Wah>VP)#Z zlhzjZAXWecij#9Zy!u8epCP_T;39j$9GB7>{OL@dqlkbAdZ2Em={5Uo;d9sk3}`Qv zxAMZppR9X$3u_FzwM z1aE5Hev>`+gNS#)4vJe%A+=ON=`CU-Frvd!EO7PoUFI=_xRpRFyZiC4>$Rpn3i^Oz zD{Q6pwT4Z<6oqvhE+kOM4qah)eO`QCpz5t z1@U@VPn*>3S^QMxZSN@JcmnY(eV$>XSmyBjZzyCzmd4y~3Q^a7*YF*241pN-Qkf99 zz{G4r#19k#5YW4{v%){$S&+}+APAx{rUOr2Er@g)LwuURX%;j0v-ym!O?v-9u^g7u z`j=w5eJ5_Va=4s8Is41v%kA@TMf=2lqF4)S>Co^$F<%$%{Tm$Q7CaSyP9Pclvz?m) J9ol%j{{rVe8JPe8 literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ipc.h.F1C28A8A3F99F2C6.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ipc.h.F1C28A8A3F99F2C6.idx new file mode 100644 index 0000000000000000000000000000000000000000..e086e928d2cf007b89203e3969a1c4aecb3f4d64 GIT binary patch literal 4558 zcmYM$2{hN)7Xa|zdzHDGNYkQ*nzYemib(&4;y=n#jO5=)#rS1O3&}R5#a>!vEh@%t zqR5gpOC?L8G>Altq(uxhO(*%^@0ru@I>&L&{k(hcyYD?eHW(WiR8JC#^zDtkogF;H zV?`p-Wc+sbaNDsNf7;-;_c=SG`rF3&_gY(jQ&p*{HThY!_IBf0BO}fx$2;1KciWr}m=}IFCNtiAR=ibMW=y3>^O(xe5!!Lm$!ZC;H%|w93hWE9-H!SSS0E@ z_jHq6q=Ntt89XG|p}T4AD(*K1p_4%;!KDjQX-;}2QV5qhT&5n=;uRM7M)wI&z@dQP zg<*-JN$)OcgvSgXGs&)A#?+g>N^%;Hkj@~TV6<;&)}*TF2?#|Til~&qrJROdtylrP zz)Ld4nDApu#&$@{VE8tJ+f?XgQR_d(ozk)hK^%g(BqMTfTkx{|QzjzVf~{mnS65EU z3cR8zgp)ZW)B5X4iK~K=Lj)LLFhCswwS&)Wx*R2kP|Tp1KxRryolFv&j1a{kie@-) zr}h`kxDx_wgpJd`+(cUaht4O#j#Dt)$e@u5E!XZF@=mM#t~*&(-X zCPF)dc6tWN|Fc_vep2pigwG5<6Lc@L{_y^_jS|8jgFz}4xKlQBh`{)y`3RbziLd+LFM}x?kJ+!UTY%ww2Km(ZW&G-Q&L55_ zBlI%prN#^Nr85I$cB>$4gKg8k6iWAu2+!{<5W=M#O6ipJG;52SN^MmUu5h?Q&{8nE z{`obp#R!=kG70|CJ{6Smak?5pIEQe8^h%Q=*DFry2z?CtXir)?vfr-NNneU^n!{7 z^`5H`N;s5IhM`u4IP~^?0hYsZ$<1x8U+7e0^j}>J|H0u8y6H_5!_+;K!}SpSIrtMu zm%B@sy*;Im5XT{oIy|o46PaLBx*FjKgClfG*9{`QyB?fagK!WIN`9~JoX^(?l4_PzaKjv+!3gCZL4o$;iqcIz?${5bg0p1z-4XnaZOfHA@-gHg(G8`!GQ zX`y6-aDu}L+U%U~QajErUL`;&gHmcPZ)Tt#q`X6bAO=AM`Eym>k3}soMabZgLCx3H zxK4i()h$3bgKo-Lonq+NZ4qaN5Xm5tz-3$hvZ)KtS|MzKEs|$5WL%Op+3e014FAR8 zFIunCSXVlBEo?4$9?PGpcs>pgRa>RXKt2ylbJ4T1~XQllJV zbnFqr7=#h@q+2v>`MO_#8U{541{Q~_Z1y^BM|j8J9f9+kHsg8=?Hvf$7+fO=9lPv) znCq5Z2yG17=)RS*$7rNG)Cds3A%IRQt1ac8$LlU4NZv!5iuk z7wJ^J?C9togkTQARLXSuLreSm0t7G!pp3D19}Mbv z>v$ogGDsz;c2R$=Y~Q-n9;S>%jbl`I{g5<}m=mjHKgY}Fre=A1Yhh*m}e{&ea&lo(T###4Udk=2d zas=Thhof|Sf!oimOo&zwMX2OZNpLi-Ol_aq_!9^o;33)3_cd|`zc@`hg<&1gkxU%h zmS3_ka8DS9k25$%eI!CT zgK~m~U!G;j{azN0aFfAJf~FaE%I+0DF$g&va%cw6LaP};4dY@FT)|Z`gIu@xS=HtF zLiikmb5sZpl<9um{2~G23WF=O*^Y&CK0X@g6Tln1C54h(<@IBtt$)XGA%j9%Z>ifI z{Jd{bB0?*JRs!j+{KxN|6Os`u!BXDuzcGjL`ZuA-Bv162xf;1q=!Z zCaG>;SZt=1j!?m&f@Z!LGVGZV6(T?mgB;4Rn`zzS74U5a!UYBwXzBnv1+l9Br#}$# zIOI{OIQhCU1#62hBE&L?rHr#C#yR;aKV=~t<8X{J`W@FPjf|cbAeTWdHBWng)j-#3 z=n}#u4woona*j;$ulHwVBb?!IhG6PxEWzNCm*4lLpf#q zUix#*OaH|JWOK+SxPL>z+-Iw)0I?im32eUV^PL{ESpW;LkUVDp#`2;{^`8ncyaHB8 z{x4`!m>JeC?G#64zZ2rn4CpmQppu)X8YV`l_-%it}+ge$4HRhVTZ z!amq1c~9>0>gLI|!&MkAVNgQr?UoJR^yk=^5QA%eI!cN#Jx$XMDKAXI$UGf~m`5f|T{lI#s_0{WCdl8Zu zBvXf<|14D$N4N^m#h{BW>E6y)qkS&hUm(;nsHKdo_xev0ja>yOAV0*x^@|FIky*N3namP)R*q~vk&OR?`u499SYq4hT(g^%0k;`bWC49p~-XhyXa zJ@Y*8_G7r3K{f5@@BA`7pA6AkgbD@~1a>QI-Jsl0fLjc15v&uxbxHi(DnKHKM0!yk ziq5|4$9^|}kj5d6!1Y%{&-XGlLkQUnvgw>YIDWKG>24lIXkpMoP}-95pL>0Ie_*&JQ1aLq}d x5yCixQK@^HhvOY}W{)DA;&6(<&0)7#_yu)$vvdC%e{yE%(Wd>8g-sBN{tvti3Dp1q literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_mcbsp.h.4696A07EEAA97272.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_mcbsp.h.4696A07EEAA97272.idx new file mode 100644 index 0000000000000000000000000000000000000000..0cfe8bf9d65bcc796a0766a1d0b73273dc90b696 GIT binary patch literal 3470 zcmYM02{hH)8oUB{{ zcU3CMYtShoM8l<0T|-nBA(h7KegFHGz0X=_owa_yy}$3<-`@Lw{;oDwR!IULZ;iiA zbZ9`N?{_>NPZ_@vk>Q&+;I9vUqosb<4UIMz@3*x@X)dm-w|CU6Z*10RT~`0l$v{_I zyCq64t224+$ziL&VL7=;#YbIp-19tg4oixU2KxJkcxA=U&z6W!A9WEPEtI-#_>cGo zk5@JH!rD5CxJ z{eq`su>y)f2vi@(riy7%jvEI!>;Mj`)KP4Q?KJVHJG>u+tqn5}i})bo)9$Nv)>mv(AK`?QfRs!fU-7Q}>W437-k*sg z24ZNSXQCgUI6Ntyh4?yw>umg#K2g-1!@Fjq@B~jf-c69}(a;$*7jYSZGFE7&PQT&G z6K5BoXd=+WguL}s$F8*2g(zwW)G%?t;^}Kaw@4F33LjGVwA7eMvvtTCZyglx2)tv> zD=PcqQnYBV0SXWBpfw5458nMWv6aK?U>)u0kvyj|J6^I8VoR{(F3{f}uY~Hi)qAy9 zAkHO_%l53nL;7IU>!JmUG(M#9)y8MUn0-pr&)&TXMKghBwt|Og;vSa~S4$KUK1leq zBJIf1R|+LkPJAWsm7Qw!_k4?f>v%g9?%++fYx_zfcqqC}5#7 zSE+C6R*H5<;Sc__CRtU_>r-7HJP?OL7{!4amzG8K?b?Xg7>wyX9xkY_t*{F7Lfk^2 zg{7Ty(|pVNf%7a(vnaRD_JMd4 z3TJSpVO+!IH%mK1{Sbd4@P!@Ukq+<5BhSzKqtF9ATBgscn@!rf&w~+1K@?59L*b6= z){ywEh`R`Mv9yPLrNT2af(w?6Kh}%4Wuod+rK197=bv6KoZ-O?^JXT8R#Z(B8xy4%dlI#IxW+*oD(tv zGM3@o?oq2_bGJvKh=o|Xw697^k%}J|#Ufq{YiZ&=Y15QG%ar#aenj9AJE8r@t6PUN zPR66iBap``Qe3@wOV^nx2`IV=bhE^oh7-@HF5SwB1Of?6yjuT@rrE4qP8{OHA$GxQ zR0J9mgiVPk^g*9)PF$?U&c0T|6vS3wMN93ANHvZ2v*U0gfkal(ys=s9D>L?_p*TR` z0P9g}WtmKT5YkbshSfBXS5oit$SnOV#1{x$V1+JTc&)?mrGFlZ6|jPiw=9GnD0Re=gThD?wod zMzpI%qdUgD&4ecqZ-Z@g4c+Nc-^7zrP9m-)P|L!^S_b%K>Q!^%8i8vpvAl5Kkk;gT zoH#+?1bgJDPIpu8Fni32Xo#j6bmbPfb$^U2L%bZ8(|YC=ng@>_l5+SefvYUOgP5$_ zxMAWs6sdejWzXModRVZx0hVFB^QBmIBlE+sN8-gLl0}i387j)KLMf{k+V|KiL6P3QOSKrKu zzX<%r4y52!#S-(GrPooE5-4R$D^Shu4gMgJp{O8G!NgHFx$s0^gsw}8Qyq~~+cAu^1l)G-a*?1ep69P|I zGa}n>C>fNEaw3Bd8SHlImb{f+i%Y0S@r}SY7Ai1Sa9Pc5OCt(h(53CJUpabr_n!-z z5u1W3#dYet$~`^PIh@RgWEQ{k&FHA(ZxbG(s3uU&&QYfzUS04cjT3(0N0(+S2z{}` zTKEUzAp%3J6?v)eB20g&Y(tSvAe(K_ow^3Iz7N@tQM@4Vf~~+YS3y2xc}6=5Gccn& z?d0v5RJW&;!}efLaostUq@}#i&k&0Uh*U(Wi$0yo*&o+tCUWe_Xl z#9ab+nRuvTq%AqqJB%WpKs@WKf2B^C&HKwAP}qSTP2A}n_)_HLKZ^Jifm1AyD5GZh zxnAuz6y{(~PhP=i+p7CJZO0H75h!BgD;AWfX$|e+L_8nj*}jDbg!po=ToK`Z5#Qr4 QpYXDWf7fpv^5OCR2TZF2(EtDd literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_memcfg.h.68C2AA9BEEF9C297.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_memcfg.h.68C2AA9BEEF9C297.idx new file mode 100644 index 0000000000000000000000000000000000000000..b4a8a26262e7e2a2d4cd74698eb62524e37957e2 GIT binary patch literal 10302 zcmYk?2RN7A`v7py`gUu*mG+R<`)dy>y_y;{NJT?YRw|mPXuTRTvMOZD%r4myT1d;T zkc=XvNCTn&IltfKx&N-q)pgyU@AI7JoO7T1oad`8>r_-0PL+~cWwg%n&|V9DUP?+z zhWwgam>tk1|LT)pOJBpa&z`SKEPVa?ub;y7;AZ51K*!=o`q@>hl2}8a-sgPp&GBF&)aOA=M_wy?)T}v%qhasQ}s$+Y@ z)pZ8JW8!OB5`M?SJAQUAHSbB|w%S+k3@aZ~Lu} z)08Q^WZ@+{z8C(jk{n6RY^UJNgEK#|7kYy0nnSvOQ>bB}hMCk0eb#3jiBjvKaEpgq zyj(9BNS$bLIH%1M=;Wc37aN~sT=nEkAP@*;Ae0dwH#qM?Veq3Y34urkA`w!8n@YB+IQ1crAV7j3UXi0H-LEd~B?V6w zJXx{v^()3@2TQe4_`|^;PHa5N}LS!Gk^KV4TZW zwNnQThZA@tz#|+$%_Do7)%JIfAn=@p=h*m=j$^;}SPLTw?1O#cN{Sz9k(H<~KbnLc zS#ZQ&m^n7ehi&y7Ltrs19^E^xzn1F0%9qQbVRcX+*Bh=6Y_r)le(qQjuHm2trzg4G zCFt?&WD0RS#9?lXtXp%aYP7j5fpxHMWbcjMOB8+XFKMUY>pWb?9=o)qJ*XV%Hl9G2 z09}Gy?-l#D$$eR+@s>gn4@Lany%2bQ$gGP)YUK#LmB3qxn0?w`+`>NT6B*)e^B1m`b01c;Va1 zNdykTA#tG$(DUh>ZT_5wb9l(X!AK}>UwU+u(_{i0V1xMiz)z!w&3fxX!+9*^;be}K zlXF?Fmqx*n2S*&GKP&vEOxAOnLf|0_4_R?3?lf(cDU31t4}n$&S{X6%Z9dyd%esx5 zM&Pjkk1>-5=Owp<9i2qsE(>?D@vr9N_ZgKbOegSGfVYBJ7-v|5o#x01GYFi5Q{t2k z-?kv*v$F~fD}v&f-s$Q8xW1y=t(k^HSO~$TICkX5z&qyOC|u&;5;wW`3ZJ7xwbw1& zGn0SW619G^qLmjPc!%vUY%wEdbRS}3T1ikN+8o-B+G`XE1-gu@vK$Ks%= zY^CzZNP$8o2btLP#`w$WtIQSV5ikQYaUNELrA@!)XhOpo9Ax0FYbU?2h8*c2QX(mK?e!Z!xKVPgJxwD@<)@R0SW(k3K3B*gphyD4l4~#I@qTnh4SBaPg zi=uz^-)?k@LV^Sm@QT0U2R^r+^@&0{59zo|G;Cge!|hV!QUZ}IMB;)m`)pzCHoJ(z zEf#JeY%@zluO82cfu>Ja}9y_JiN!l-swHvGQ)D^R0#ZF;0LD8xSicE2dBlT z5(wfU2-DMbTXk*45Y@E=T3Bdd#e!{A{#0}5g<2cI$hTTLhW z*O!%02x1`!vqL%hLYZ{YuFVuA5QLLDO}eb$*?K(+%VD`#KiT;#ZsqZRaAQHYdH<~Fwlc7l*v?$u|D^XLLCcrSjTfujL`B5`$6F= z17C51@+-Gge*8E=n?NxK#n`?G zTd<3OAsC8>+mEl>L(K-5=#a1j3l3PgHmbR|4wdtzFau`L_qqT6?43~%=+rr5Hwkxe z(1G<#cH)2!r#rMLTomAfke!YqDh?{xz0x@baK#%jgQ~)^2OF)RuqzWNW#;Q#$V_AygyM&;WGoD zah#fG{&pR3@|_-mLLLfv@kFO9HMrI&b)G(f4=jAZNz&R=*<5-+k-`-ouHZpwqQ{a? zx}j?+T;t&yg7KO~&8h}E6nr`G#h%;P#l@NWq*I6xAOa6co!2&Q&#YB2AaDXshzs~> z>7c(3MXAtm69-MWAe|RZe0luzBSQk^Je2dZdI#O+Smm(^h7uzJu^hx=;&`flu9o)7 z*-OBW13!GG=8yab?XVIGzj^qLFP5sc<)(_+(~Jo`XW%*3vlW@UBR80=q~OPcAC^Y- zMUp_*yTU#KH+i^;Q23u|1LybOOCg_we0-|wx3XUaM4#DDzyd79bKN=ftw9m2Ee%(& zP=N*Bbmj;hSBq#04_J7BXVYI*fxC1kJ*04vhl}{Ks~DT;9a6gW00AEcd~l=MmtR)V zQL>*xJOlA~nn>0@+235#n}QmsiD!eH$|X4`c`AKXObFC*P=}M0 zx<*G%F5lXeKo|pIIDmJ~A99S{A44IVhiuGRrR<=CFX~SpB=ACj7r2OR%QnY(9Vwt- z3Z~*SZFw+A+A?j>Q4+T1!5Vw*a9VFl%pN5Q$t)z}06yQj-1hj10mlg3=HNE=V)D!Z z4Z&XyQE23#5qq)u=ccX#%PExU|@HZ|+s+!F*!1Sk>2{YCFyr~LLc#T5J)@WVv=t1D^OLcbv=3Ebh~ z4$k%o+x#ylj*O!4iGxo#r;SCJIL1PH^;aQF1aH;osEog(1Hf){QiU!LCC>hsSu3M*lySko@*G)G+b9($UE z9e8lSs+sde{mi)CTPWl*kc)j-(OoSow;_VUcMiT|^&dAlt-<2X9|~m*l;MV3AZ=)* zwnOm@fj}MtF%8Cit<1i^Cyv5R7H(qBy4#O%+;#u(SprEMB;mTy6CSL%lYElG4Hj-- z_uhD3NnYWhd5%Dy1oALvODDXGyMARig-jkY@$l_!Ja<`O=i&1N5+#s`SA47ORxQm- zq!7a-S7=TeXLC3o8v+g-IN)ot-#3|cx)u{J6YyZc1ADEz%4T|7k~)Q_ zJUqqD_0wV|T11so*bJM+*>+h3&o)>$({PFaDOk}QHYeqLO6Z}m7xs$lF8fh{)tO`~ zTN0iR^TiEec+>4gHgc=&NccVv_p#Y!x89FiV39>3hl3pK+N-Un&RCA?=Rm+;0DnA| zxHPIu&ySr&VF&CGS47PdzFImVgN74WNWeMBDLgm2u+8`if%7b!$7<$h^L~+8KPw7X zdAN#+Y^&kyxcby4M*^M_@Wfg3-D2h8n0}o?8v|`vRAl=p@A@}lqB8*>9(*ugzjQtN zIHdf)&?rD7uDTUBTlx%%9_2!=$Y3D@H^PP(xwjWvwJ0ovh2pp_4pPEsEpdlte=8drfqZ9nxNw|xHE?m4y8;|noNv#yVvG5JY)zV?$i!*u4JP4eDGh%Kp zclTCUoj>&k3IF8aC*DZ)^W*C;zRsf%!9WDojk9xeA39Etr_jMe2OjmF$wViA?3+s= zTYzlrn!iIr^1WrRya@c};5W8mG5*Gw(I?9(B=V4mH9WNaXiNKBX&(Yd;i&kq<3?(# z)en`S;d}=2@tH2>tv_z-K9Rx`4xV7XmdCr~eH!IWA(MqnoS@J(Yp(K3cwYh@9C%>O z{~&k2?bMgunqfAkIWkf6ahNLlr|wxJZDa|F>U8g@DPAQ zH>Ie&Y2npq3Kw{|fKL>E<(I$i(pU-~IQW1Es@A1CwI0Lw-6IgrLpc6H@2qUc8?Rr! z=>(o~@DwY-m_^^pR_<7KpTIFVCN7oSnrWu_L2fkc#DWuU$%Tpf^V$473RYkxo{{VG zJgZG=W@nJ_8xG#!6P>ZHQy%(fgCD6k`5B9=8AVR*WdlrQX1}ZR()$!2GzRQbQU(2`9yQaC^p?$F3`(VRJAShg&)J=xdi-{hpEVcNV^5($_d{ z{$amv4Fy*oT(M?+8CutM#ZCV?fd>LSzzXpDr~F*al@BSbg|%V}dCz`al6Zfo;Y$Ks z!rFaqoZ5G#+p}K~DB_?9r^mU-?EBNR>J(CVNWn3(93Qe~i<%9E8Ww8seT(zmY2`BC zgF+b#Wmp`n!(BgbGAyCs%77~t(cwXD@5g_YdPU$1178sOYM*ZTKK~L08v$(aahD7l zKOn6ln1Uk*j=0qrtNO1GTlba18y4PRWhuY}_ko^NR#+B?_S|gyPQi@`iTwi@6w?JQUy|u8p*mVT#HJwBHf1W5EuqW?cd^s>D~9!fOs*W4~Y9`D?w* z)~zJ)n1jdIc+JG5{{CKfDXf4M;A{Uy}0PV z;d&10u?LE(m-w8{TUTT{M*2|JMf^P7)vq2XD87 z^Ts7Qp&to^@DPG~SKATRNw0BJ9f2|q%CKp#en#u+atbKaa!`vfG)zY=B(H`-IS1tk zu`{wJt4B?(C!hy<;-5NJDR#o-&45oN ztP8s0;bri?ZTr4kOr&9F4xDlMS~YEpalEpTLN*84ILk827H)IZGio3ZDL^C+#>@6J z%gleTP-tSH2@6-+gf(ln9lK4Tl7&hvj@`2(9E0Z#Y$R}jgA2Gx4bMm)c|~?v6M;7j zyuqENrL$`HZ4W&PFBy1=uMK*tNmJ#Fx<3nwbx?$G!wAn!47u|XC<|h zc^o5?6R*<_5<551oC*u!)kM4W`JzTwP7s;(j}0N zi7e%`eaxD-|4?XWp&d)a2g9tnC*M*C l<{%h%Jo10@4(ijtOqiP)n)f6BvdpE5j?P@kTPA`PN6P^3aMPolaJifBT{hTAQbN;13#nIbbu zMKYD@8G6P(W8x{ZZ~woyI_Iu+*In!PJMFWFbI-r)WMgf;SXm^p^s!kJ;v3;9D-wxR z=q-*24_rc@p7dUm?LGTOoz2O+O-+&G$JW%^IgGEZyQOx$LXx8^%C=%JsiYkBV z;37kK8crL~jTev6F+B1?B4Af^9o&t3n9S;7JwH;Gupj#M@5bwL!uEbN%#$ZhWZiK#esVE6h18*hB}$~z_C1AqsBWz#R*TvJ_T zq#}tmxJGF0|6lVGS~Y_7Dg|tdwk*jy#~-^CWIF|HjK-`1>v|rPc*#EMO}HMg9#{(u z&ztEb`q=d$VU5--$-+g$UXHjkSBdapz{5Nn-Twx+xUaQWCb1uIKNp^oqRj7(DJmrX z1pJeWA;w`T5iaU#B#r_eg%RBq)VS%Y7P|EtM&bhC1z@E$XeG$>Ua)mIiG6_kc&I5l zQ@%JkWonUdMrT&@z}8MVQ~O@pgi8TSLA85_bCN}hReeInkXV5$SaIcD#V1bmOw%P? z1X#q^%bNUsRe!t8coN3|kMUIdHr8etJC#fzF$-s@cgO#*EIJ(*j-N=l4zLbbyXEhx z&kQ+xTaQEnU;-chfpaf@zA&0$Kq471nTr60_%9i&I|Q)@a1XCp@@esxeh*b9lc)l$ zfrsNZ$e5)qxIUhctKdAB@5Gar)=r9#6}CkOK=Ix z*{I)mY?^1>)0VI!IKzI11l-A6tke|0qB&{TToNmBCF@SJVXwj^hZ5%z zj>Je7M!R@D9-3`7pRg|KGOWI&_x23S*RF&w0$$|bT;-qN?^_g#+(?9DI9soICaxvt zU9y11C}#NC+s$oVt@_IdJE0S6SBrZ=ZT{8rc2bjmjnF&d+^~ZSykuXPd7Qb_k^2e_#$HE9Nzy&P+ z+o;}iFQre8ARLH+tnV7;`>PFa%B>@8fCj9j2M=|!E{^>n;CVQY1xaz;?)^+|cNF1Z z3}!*BW$%5hd>^r%Z~m1(B|w`0bvkO~6+Gukc)+W(Aa_O}ZLSA_5~=XTnp1hsB3ABoICVc!XcN zsg<>TCu!6qlGq5ikw2Oq|3`I$MAkWpL_T0X-=Roa{x$IAUxL^UxSb#FfgaK0v~~9H zCQ%Mp&V^yJTAknOS1BY40SkGk^LN!XvqEEg$0s&K(g!0CYL{P|#$^JI6(U9W5sAsE88 z-8k)HLRbwss# z|DN-urG)3=Ty`cJMrx_22ZbCVTn1RiXM9`n&hUawdj;WxJ}gXJNxRO|z=|@$C4eP- zy^;9&G0ExQr%7xE+{_2Lw{k|n{7|EFB#h9AJ#W#)#G!QbPXV6*Ji+rXwEWaCsOa=X z5?2AQ@=M^k*uhqI)ptQ`0^G#!S<&>eT-yN#mq?@mrtzGXzFBx@Wy?-M>;T-sbJ|?% zpOI=Z^fC!kG-boznPcBkI9R2Ma1CG$Z+1$ko!-sl#A_rn05kXwektO#XW&vzA_*{w z@6hb-J*QX9_*xPbfED~We!5lbKgP=ZIthRDXH$ExksEGoo+RM&fam#onG4RIx<)Sb zBys?A_>pl-a+H5^;NWc%X93TGX7^)9TXDB7 zd%;_Sf>$p|Tmrnr$L}nsJrt!Q+DLez7Yn5Juqo>PhzSDT1-OfEtZDgIwq3=SS0qjW zp5nvYvbS?#wkY;BiQRy^`M)lokBy2veO2oXi7kLzc&PVn79*uOrf*63qA#1;G_Z}R z|J(H);Vi%`-aeUX`~Hbpse+h^Gua$wn3%4(8Ew^0SPCfR2e@pxYgujn*bgLvFo?x} z-1G)sevx(%t_G}zVcm!8bDRGL{p4qYI1PB3C+Z|=ez9RqpMOYP2fWV5bEWW8g}%|N zP7-l|aX>#j|9yQ+RddZ$b?zeJiJolhY2!iy49+@zBU}ks$pZxyyl)J>n(+@GUCwf6%#FdjJ3c literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_nmi.h.A8AF2163556B90D0.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_nmi.h.A8AF2163556B90D0.idx new file mode 100644 index 0000000000000000000000000000000000000000..ff1c7a4a177d3ab509697654bf8a3943fe5f3e68 GIT binary patch literal 1320 zcmX}q4NOy46bJBE#pZxK4L{aN(>u=X(VR2Y-=RjGC~7$-GUOQF&lC(^)E1DUOdBaA~^Yw|8i(5^u$kR-Y?y^8e%)x zdCv?#oAUOGo6cQckE{b-G|RiZ;#>bd)`ua>K(>wLu|VaWzIf&?rOYg@Z?}0s`(|GpC3WlPLjyN7NANY|hANWHae)qIG#7E)it1Nqe zYiYk2v9KMv6iQ=Q=04cxlL}uGAUATLkwbZhX*sdC!>}7CG@zmU;1lidmVQ?n@^Ls$ z{LzQGi*^(DP2>uwpu_6x-qCu_IlmuS2*R!Gq66da4MoowGLiEjkJ2Bw*P z%VUe2$q>X(JbyulECw;vwwSK^_jg$I$jOjQ7vYV&y=^}JS`BgrWKe_sS0265`%6y~ zaw??K{n+Q;S}3%)oT2(k)Pl;)?$SOee3 ze}-HIRkZo$DBD+^|Fw=G7eXQR-E(s2=G(F-A+Cpd;!Dn{nr=tk#p}q&i^=tQ5 zuX>Rk;GiYfuYCD*w=r-7`2?Jx^vBGwv9Nh<1CE_;d9Uk8RmbT CJv7V! literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_otp.h.79F263D4926CA8B4.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_otp.h.79F263D4926CA8B4.idx new file mode 100644 index 0000000000000000000000000000000000000000..0885cb4c51f95793d353398c011c43916f518b2d GIT binary patch literal 374 zcmWIYbaTsNWMFVk@vO*AElFfyU|uK9`C6whN^(axt27m`j4B zKp=rba@N{&mok9DCLAVk;e4YRclYl&QU??^<1m8@E9~jLc-F#oK2X?*!w4?COfM#A zMaqknKw)DJW4JI!N`FG`+TWXi!WJAB5)ca+7T_NX{>(@T`2`fV22?PC=lL+Dz7bO>S18F8k{ldQOrq6s_85jUj Cm}QOt literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_outputxbar.h.36517E226CC8DA79.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_outputxbar.h.36517E226CC8DA79.idx new file mode 100644 index 0000000000000000000000000000000000000000..ac8236c94fcdf2d377873ab8f02ce93edc8df9f7 GIT binary patch literal 21104 zcmYk^1ymQ?^8j$ZJ&T2{*xik&D0Tp1CpLB$24bOvAl;pcBHbm@rAUXA0s?{(qS6xo z9slQj=l9O>ymRiy-FxTG+}U09z1@nNH=o}vA+h1KqWYCHw^aEO5)wn%Uuw5*UO2)2 z`waU_-EmvmR!Pl?!!}p$&wsqg^ZbZ;?rt5D3-t6agm&vqkFOl#c($ryx`dk26QkMD zsXQH3{$SO6NB7;?-C|zXPxjCEn|0X|v6&TqKUev#LdA#mi9f$1XWNK|Nd}=4AL&)YrHdnlfu=luRs+v1O4+nZ^ zxew3S4^a7|IEaN_F7(nIhQG>29thrwkSBsXI)9!Upe8}i0>PLA#&oMW8tL(^=RPC2 z0l3k&*JsZ?SU9K&!HNr3G{=#|Im^EK3#C~24Dgw*knbAhG*^EOLJB|%!BB_amz{>+ zM=%wEDII|-&8}UO2LvGGFp$HD+r`C~*{7$^`!JY=uK-`^R$*Jl%iXcGAHqU6KsRmT zG`X>!;j?`aqD2r*NBQD2-L|ZlJcO?T_)3XN)fhJS!qjGjP7!p{UNt4`3p^1%c_<4N z3{=pn4h9_bQXjq(AqpUhR%J4w-tgL!WQ14|#M0!4`Mf;Qg+7FENeGu5_g_oub4~tZ zccu*zm!ID)IR@@4d}M?FfHG@R#C< zeR0Tkp6k_-ELZ|q(yeO1U2|&fuu&|$5y2bEhj-eGoNnF}1YH5>(q73ljU2Y|(|3gJ zuzl2jQEW6^`J-Xr(9!I$HGnnE(6?`}Wr~HFGz&k4@RNF*T4DK*y;Vwm z{QKmsW&{%kObE80aIo=9pE-sFF90vvsqx28GI!TLMkwb%IW@6+g{M5PN_il-iolh^ zQ|Q@d`_3x};foNy2*nLU;k1WYQsqa4bS|WG#bCbrp~^@dxv?zd3n8Db$T)7%leJ3$ zA&P-0TJDzZU5Tep{)4|<_)Ev;gT>Vg;rq<-ijN}rNNL(VL(8UqZzX~eAB-rmmx_9- z2AwJ$$3i;;?KDTsSoufq`0K{A@JRrl1mcc(xb|i7A&+Q;H+*%hNrZ z)lZYdZX@ycXh5`L3ql6 zr!>cqYgMN|mZc-ab0MD2#@xn)yY`u72sM1Dp{J~+y=C#-jNb@0BCw&FGJPq$U%o_Y z1`C0F2&BmSR{7|DiGGft%L84isptbot@9 z(?e|${CMC;Pjdf1M-O?a+YYsv?AKEE{ zTXcs6%@uB$&4P~rd}tE~W~I%XA$bYmFTh`_!zO9j+=KO;IV^l+;3Fk!QR{>gXJG__ zo+Ri=il2aetrv1sTc;y*@}ZL^A05C{_YeuT!a4tYDWutNY z`kRA#?<2gHgx8Ye|9hVGm0xO5G1W!54Y$QHFr6;11{M3^u#Nz9=&|T%J=>)DVi!Uo z9||c3i;o*?CSII8pM^VcM|`79t@Td?L)YN2n*iKsmy(v2mK2Zwi{J#{M8zp>9IoJZ zb?E{YyaeDyDJlvUsw|L~L-@df5A^hVbt_!`uetI<1O`6PE{!kS;Ppmv8^RY3e4#5I z4jvT4y>TDms|dc*+l%T+Z@0=QCm3)D51dbCYOh~Pj3b456+tdlhw_qr-hOLKz69Rjn-T@3(Z$dxSP2w9!k7 z;BEA1hsy_+vfwQOZ)#wV54tMq#a>5{1G!26mCXjP7ZaY3{e;8u0Pz%_bmQEpB*$We zRuQz)Vn1nS@=i+DBRu88Q+fbBR@}6&;%*nhD=xeu7*Xo_^ZwqMvMlH^phr>ME0|ck z`M`OER1u`o9EQr_CFb5f2&H@|rQ)2RJaGCflQGL!uw=lJZnZ9U-h(MF%MiB0R`I*) z*W1f3@EOPD?64aHZd6eh`&xER(ePNof**h%9kApVvzv7-zWoCc_|XQMyWZHO>@z`* zz2b)ue$bX{-6+^E-K~LO%?E306F0v;99}79f)LL@JWalKOY*v+ef|hm0$ANr^OhiVGSEpIve;_VHn#{RgjgQL z^27&ue6z~N5$(GXw!yZE{}n>X6otUY;r2MZ3Ra2hquxyV+jz?m9QI+rhwdLM%CT%6 z@n97Ti5y6zDmQ8SmFlVa96?tIy0lNH=41;Ex{?syGw`0aV?gbWj^SyI2){V+i&}Pl zlyA)XfMN11lyRYqzAj(nO;Db&axB6p9(+5c0T?M;Uy~*p+G;&ELR+nF!1%zG97H{Q2Nd#Z#j8 z@?B)%Z-f8_0%%Q6t1rt)-MPM*g(nO=AyC?Q=f3wSHv~Th{0JtTZu}ElI(Q2UK^zF8 zjQ3Y48y5d<141qjaw+2n)h|47-F*<@nIt@;H#Y4pj|F;WNeD&&M)VXoRF<$mS@=PL z1zC_4cZF5{0egpLEmdTPwHVN%HO2al_gGk@gAfc5{69B(Q)$uoOkRlvb1scvcWIZYvA6024hM4~m|h<)xkXM4y{C%c!2=IE zOC=Zj>chsILHI0!&$QUcS=a1tuhK(E=0P$&HCD%@9=n}-cRLGz1@M>BWdC!@A-9hY z5e~vZ@tV@59lgJPe1*exT&SabUpuiWCEjeq4i;hoVyQy*xmR{DE@u&ba^WXkQP#d{ z?y^(r2njq$pf%;p8LRSsNh-oyfVXt3gZH+`GzQfoWC|gZ&bLCCZ>HMEzX)-Bh@?4-*}GV% z5}2wEN2<^J{AJF5I{9}xo>Ayq|NF5 zEIbjy6M7wZRuRzUQzUSMF$;X!2-a7D#W2lSRTYgAXJN>nv!(XRBx2e?RJDT0i;o@ z2$DXbc-f>2;TZ$ZDDp|SUaFPG-aO1gDg&w1D#DtwUAFJOeT0QInYQ4Um|j-RA`wTLM0z6=~jo8j}=^(IfUTM1!vl;j^iu# zt{Zt5Axi{VR3Vc`oq4?AqBnvI2V7_q|1OdqTe#{2!dh4>ZuN!R-^1|c+1#*0rq`p$W<2O)|FQFM@_qlevyJvi?; z3!i!LnNEi5+Py||9$ZBT;Xnv2)=e?`WJuCmgf4(CdLlQEw(%S;=XHXG_k4IyJC*Zl zq<6hc2f|Mt{G>VT%jD7{;F>B6g&ZiP7g@hiGOnNQcp!Y@!Y6v1=uSNpQ?8hfU?T}O z^rv{fa}PviciEq0!JiBMREIa(@-j8oW+Axnz=ay|?Ay0o-K&MCSZHLRkzTddNUfC7 z)gFM*EP`gr-{HM7(s#bCM@ZyBB5k6mYjKi7&{>2M9+XgkH`i55JQ5WkJOg+}d$n%m z=C~W`6$noS@RZuiA6>H{+MJ1}SqKn90JV!1maoqDj>$d4f|dZZ=!&`X_dGnczYM{h z5AM_rUH1E(ociVmLV*wpsDFAG)en$aE`5##GY*(hY9CwnA2;CGIfS<&cuPk!Z+HCf zgR^Q7Jo(^B?^J7tq>q}rvlSs*0NHeAxx)IoLE~1RXQ5XBy;QpkevjfZmo^~SbHJV^ zca7J5n!fTSf;NCQ?UkNPx96$5VF*P+D55x07Ti8Lye9JB6_TJ$?^LmeVw((BrXXZ9 zkWJ^qq9?}W^Vj|tSTN;)DNXK}F|Y0Z$}tF`TnMG|arrdsM$Gr=2pL?+ph~pJ9=3p! ze-^t%Z!I=lnRG|Jl z>;BG8HAi^KgO>z@S^}S_&s}kmgAlYr&5r;(i~;~aqwjpYB^9#t<}eXJ9og?RS1cENTfOT&6U~cXk&x04%UeujrONv zp2R#Zz+p`;XwuZ@rhYU&7Sn<7TL`}?iVY?eQ9mMV+^;!j$0J;UE8=H(#n_Gv=Sht?>@EU#dXKz5chW%#{oe>CJTRdR&p5N&SbM;x zt1NVgpo4nIh0c=SWAzLWj6`5Wx0<%BZN}4uu?R6-h@lFUnjf+>Ev*fqUIg`Yt4hsl zxjU7ruCbuQ0Ug>`(=}4=52rKNSx^RL@egE@LuKuA*NnyCTn^+?x81tF@nKfc(i<%F zaiEV%S#^L~c&)ZILM1>YJ;OKZK5#6Xxa=kijv{cRC{C@qc5|iG7lb+v)X|!rPV67H zxQV02LJA*JDA!=L`F_uZ(FlP&2&5{v{KLe`?>>rP1z<&!+o{Y^YI99P@B#3lMzLgB zNl9sPB|@tZTB!^|kE;2klyh#eP{4-*n%w2}^0=Nm6AK9C5@^{_?fkEckK2 zkGABrT&Ph*+yjIce0V|KHhqSm+hIv1LJt>us5pO~>e?+eWW^m8Qh1O;PmPx{9&%v8SYjvx>6;sf(#tMj*g zTZ?h{hX{U9czg6*Uur#CdzXc72D<40_>JBja?8#J;TRkf9{|N^33)$ShN`o}nOw-E z{=t(RE;7)NM`#p5Bh4`XTvR;a$Mo`rU+bG2^&yOjXmQdb-C=k&UX%0>uQl3+z| zBCe@3)%Tw_MTp=+1RZ48yJuFr*jgj};J^<$8>^z8|BCzUf#AdkC#tFHt$zIGh*tmD&2opX3adl140lNf@oFEBUi~- z%$xaug&G0W(5=Q>Ci+TSE=5S?Kq_TWgL`i6uqp)veM!)#4DLCh9IXz_InFyXy z=eaYs(z$(CJ3^-rI;l#ITHYJlRC@Ih0zfAnGuP3VK7Z|egb*%-a4H|oE$$XCy-W~F z87QSn)O5dfzqftBV;0WBS@G$p*Ll2g;*l{p9La-7I^l<qJ@eWR!AS&86!(|mJI_3<3Pbn=@QK13 zoxNkiu%1MO6b4f0Q^z52bX4}_2%8N_Vl}#$rnClVL2=pf4I!6)w(vfd^8Tf<-%KvTXj17UcdK5~kmc&I@JtBLs64lp+5Nc@AcOFO4?pO{PPuE}Z;+!b zLK8p}t!nvzr-urfnh?zRU`D6u`WD#?%hcZp-+AzzmRnU3{~=`EP+b;YaNq^?!_~V? zesm5nMsVYS8|7oxRm(+%UF`_5LWrfa(Ij(e3g^R|XDm4Kz>%(qdOm62^sDm_@f(34s_D0q~#uLwYt%U(8Yx=dX)YhRMU_-R!)zF zNCqNlcXw(P$?ocOK}cdCiE7=XN4{0XZh$@u@gj()RTX(IoVH#t9O1hNz7yPF3N%{} z?nSWRg9Ytw_`TNV2^snb?|ATz%BOJL^2cf?CK|Ai#D^rx;O)EZk+pyKAtVSPfi^K$ zlOxEua}*&)05SAX`C1%&-hGTGf+-J7DT5m|)FhOh0uV|$P)g0X;OiQ`O=JUtJ_Gu+ zC39+i>AdNlX~;q`ABt&JKJF%KZ`dm%_=~`wI?4L(7phuBA*PNX3eODR6 zPXYX-N5mJ9E#OtxBV=UjDfhCV>-}YfEC#Y@ zOC;v3@-FW1LvR*?Gp*{?6G8m$*Aq=y2mlD6#wRcHHcO^A6~SBp=G3Q)?%LI8tu99h z6+kFu(8t%+0j8;%v0%di8!GBe*QNdG!N&`5HpISW-hsG^+Pjr_3p z$^}h?9k65ce}5vmy4?UqNUPK?9|UGdRS z*|58QZCN#fBY-1?H!RY>RQL8eI~L5iU`E*}&ewdHX>h$Z52qj!7p--f4g_gdTu>waHqJ{VTGqI*(8@q7rF7K&&WmsQJwb>TKr|IWvEpjg#m4ttS!m}%JC&waPi08o zpqB`JeCVT2=vOsj+K3fj5&rPt59QmlIdk5K_mXZb7zx3MiW#CE&+fmZiBKVe3M$P3 z@kLF4VURluu6%H%Id-1Q`Fvv77=$gbMSLWcbe?o`+HT@-rU)|W(9hNM8jxWcj*!Pd z9>slgmrRh7?Kgx_NeGo3`(IkuI`#bQd_Ca>3&jA%R8jAH*9cs@zav<4z?!mGpehrz zblt0$EQA4s(G~Y4(|!e+c_a74xH%aa< z?CQTBA&(Dvbovylf8OqAdKDp=fn@6Eb>_89U&BL$8V=OZhy9=l8oehfA0b2nMAGgi zw6>hJPjp5w1TduYcj(%E?cR?r|9}BQihSn%Yiq18=OLVc6XHYDsHU~>^w0_%4q+gK ze*bOXmcodQ{~$pG36!SjaT|TiCri9xuc!j3qBTXT{92$nc^QJX5VWb%tS&O3*a}s zt$L1ss5tQ6UWDgDcuoOcT)ez``w?@5W)3t{{*uP1-_IWR2H_hIzR?`}=NaCs)=fsJ z;X(~9cj}sH>1(Q%_^|Muf$#J@E<2WYX!LjsgmeLu_CM3LjpoNuP7^_G5>;dC*OZRrYr^JF4^n;WrO{ z6X^EV={-mt@6Un`7j!6!XsIjCVOjGLUi08J9p#LEV^sNz%sJ$Da6mk7G3 zI6sVi?;XFn2;m6_o=_QRpK@8VaN^V;7IYcVrKnTJt()}s_$-7TKJ-xTE)O5zdnIfOKTH0lXn zmHjW+_ESbs12u7)92Aq5OUiA>;nQ$hJghi$u5L-WHV*p>z@M@=W8;(ZN$qY3rVN-; z)I+xj`%i1R7Rtg`K76HKJ9E<(b7s-VFcwzAO7Ux1S%~Q(gSbOD{7nGg=xk5ko^2Em z8H!-S1rrJ_e9B4JoC(zk6#}TBE3|!v$ZXKr9?rrO5j>&o+gIsfwbeKQAxHp06vYaQ z8BzT<)g$C^A%~tZ+5=8(c~Lnnf`twSIw(Bp7M&ke{6RgCkWu>AdrNEV6! zim3mG2b>-^;86>LrzCjN``56DtOdSj<)T<<6+kP+5$IZfbmsY$2roqNg5nrAT+LT1 zIRzmPAdlvVFDZO9>Hcqo)v#LpCY&3VFgkPCUmQ;1Knhjh!%3&ccgReC%R&f12vx_0 z^M5uUZ(EPxB?(@%*e7n6^LEZYfbd!fuc-pnr%&QJj8{kaErQ>4_U?8K$ZeYV0O1D@ zeo&8+k{EQf>bwa;J_Gr*x2w*E@7z()6wQJK4=m`4mZN6}m>q<7EO_w2gMNhiy-#h! z#a{;yDgY`dj`_nZPRumQKzJ{L_q3|NtKT#aZc&P1p;QQ^^kcs1J2&}g4?BeLhJiP< zs)a=Ih!f#tk3)%Rz|YLkuN#w&~z0yEhFH>C0sD_&LQv2^&&ar~{~@1Mqgzf{5K#V^diO=Rr6{?iO(8 zP_5G+MtN!#w|qIxoVZ3Ti62aMh5#h7lqyqk3A%Hx(RmRh} zHEIjf5yBV5DFP6q^VDRt>1dNnUl#vtq5wVJReByPDq<4M9>4! zqyDTcyGExbFbF{hK!;%G)kB~E9t=j%2hb zgW0utw(gkBT!i~@U;G!DR@S|JG2BHmj~#v^fHzbKwTYWK%7zmVY5;0z>dkL@OtkvX zL@4G$F}*mg{`F;H)2+P-xqQf_Zg}CeoRnRvIf5$(Tq(T%CJSe4h4@b|;TK>lb!ATOF=rgL}>4C(*1I-bh^WizYyia73!mnNWh2SFs zA4;sS{hD8LkZu7Bkz9zRIy8T1d|YKn5rPK?JZQNs4)da<*BvWlAxa2Q)Y~d_f4tvp z(2P(EP)mCiC!MpCE7y(SEeYQAPNiV>I$b(#*e4d=0lcFta(%08a}{b3B83o1a|km< z6Iwr63~BT>w(5*Ew^U`DH&clu1gvQ#yME)I0jw)@<=yJ)+7HG&HtTqw0=QV*UV zUpKpy1s@Lh&=pGEagEmkRS=38D56fXF=S)wY`>QX-6H6w6Zli3MYw3unlcs|02(O3 z^mM((uEQq~^tqr<2kk_s5RAHdNU-*3 z55i{#K2zKpS^+|**A!Jc^>%Xz9FK^a0gnB;IQ@M>eC$t;2 zBLE?g1A(-On;$PDy z$A<2D*;0d$%Rnx{o#O{v7CQGK1Tzp!u*J(R!c9%3iUms!SkkKISS>IfvQG_R87vcj zDK`zaj#al(uV#m}xS&NlHRifq@{Lnk2ps?&boe*=9@r(5WsUHK2VbbFY&8C4N*nki zR0yGhws4EeK*eZ_RD>2Tw9p*Y>pyh8newoP1$_bNQ;j^;di2R#*A*dM2%|(8Y%?IvrD&^lRu2B4Zeb9BOID`Nm1kjuG_kI_*Ex4G1un{(je-6fP{Bt&=R{A?T{E-hIsR|V} z-7~x8$00o7!4t|x)0|dW!V( z1GU=_Dn(F9uh%M(XXQAzk2bMT&OkXG%FQbb?%Vx&h!7)!7`j4uaGi3#naqImU_BSHGH$@Rb8!=|`yN{dQdOG4DWV<3Sr` zQUwwpMBKSp#>TSOI*haz{;S0bQx+1r0y2gFgnO!XW z<-uQC)z6xHzRj}@5d0bNr^pL7Ea1k}bs<>t!ID-rbFpkm#fcGrS@0EtFIBGGERAK$ z)*eClBZ5D)s%>2*&3(I^{(%tw(7Sr1&!hvk!Vm-p00&y`r;w=QvoGE2X5pI%zR`J# z_-vq2meH?zqhi4Q;Z*S)2${}V5 zWdLO~wUu%87~e~;5t2oaOi{EP@OFASe?kunPF!%J{QYT`dZ@)XBfRFqYl80{w|7_+ zxg-2#;4kg%E6E8)LwEZjEP*BBN3~3WrD)KXtG(>7Er2bpX^XD;tkD&`MQ1e@!Nnbo4WVtq^P}cQ?;mR>hyxsogxK V){p%+mlJo#l#%_kll>n{{vQoj+F<|y literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_reg_inclusive_terminology.h.4A63738FFC69C437.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_reg_inclusive_terminology.h.4A63738FFC69C437.idx new file mode 100644 index 0000000000000000000000000000000000000000..bd5c623626d4f014c630376dd49b65cd8bc39564 GIT binary patch literal 412 zcmWIYbaR`+$iU#7;#rZKT9U}Zz`!63#Kk2=nVCSk0EjE*_@40PYIfjpNc6wbq8U;c zZsRiD@%V~H3+2K;yZ3sTA9}32Z;kL%A%=aImppo{Vt8f(%N}Q!74QCMB^Sv%{b65w z^3<|R4$r&F_ig8wG&6eV*>pX1-vpuC8j4wO`maxz`$Jq!lcBgWHwkDNLs4p4@iQR3 zzhbuRQPwzqMlMDH4gpb+6bL9hTD>f|p+XTTEXE-w0uf|jnEm$jWJl$h+CX7G4n9Gc z@P)S18F8k?pSWNDNC=pFfafBl2UGm literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sci.h.8A0443B5BC315791.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sci.h.8A0443B5BC315791.idx new file mode 100644 index 0000000000000000000000000000000000000000..ca57017c5d9c24de772f53c5e1cb3cef982a4bca GIT binary patch literal 2008 zcmYL~2~bm46o%gg8;+nz6$ONpQ5& zacg3PnMtu}QBydMn}w$|O|m^4e_%Wm`r1lsoY-?X`B*Lx?( z(VovA%;3p~53W^>_{NR!ct%P^$dS#*!jF7krc}hmMD2`_@3Sl^E3H!m&xgC2L&Uz|OIKSx2HpH^rZW)xfgi>Gozm>n*>$Ff z-NAjPw#b_qfr~{goEhS+u+>zH4_Iv2TCbR;!OaAkS(X=h^#fgsxCJQUA)c;(shVwQ zn`*TXaT9?ic2h6km*u5wR%?U=Bs9By%r>JA+2JLK?ZN(YZQHXGdLJi)hn6DFf-KGc z{CDU%R~C5wz1s%yRRULuu~sa6VBgMH9kNAHMxcz)Ja;`K`>qPCmZPX3P{H!+m9Oyd z@_foi;RH@}4Cz(RN}H$qtVApT!57;4_9y?aji0Jmh1dpcjI?c zvDoE2{I=mo6nzBxSXkYxxhVx-Sp9^epFlqoYX|d1UG3eCC}bd`J1~7pxr3~_ZxP)R4?4kIR$K}yA zlVd%I-N22$G2`wvK1L7R1`xY|3r(}3X@^bWV#yHVPza?@TdY@JOVrfR$B45bo30*q z)h!V_TmOc5FYKkO4T={1Il#-%U=;xsix^}uVEoU0^XDkSAdF6bj&pibW=DqxR}rXU z-`QiWUDvBl)x1EF139$*WbDP|`j$qo5LXhYWFxz&vwF!2OY#~;4S^c=?i%e|Jf3^> z)*BQFkU$%&1NaWM_g;@8b^r%D8;P29?^aEWBQ7RT%<>;pRhyiu-v1Fr5rHBm66Xu# z%U%AOMA1N?fhAg^Z`hTjp7?~Kkw7C8_|LgBO7r?iCDBp?{M8|+^nG5K+SQ)qxPJk+ CVYFEQ literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sdfm.h.2985C998AC8213E9.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_sdfm.h.2985C998AC8213E9.idx new file mode 100644 index 0000000000000000000000000000000000000000..e45eb46c39b4f6b348ccef24d980bd4260081497 GIT binary patch literal 4462 zcmYM22{e^k6oBtJw_&HG!K+Y;)GL&pp-A;AlBpDxM_iF19u-pb8Vn6+&`m@Xi3Vu?myJ3)+wp9nW{Tw%0CWeI?Rxjs1xSWhskQU6S|5XC2HJiIV23 z=86JC{M<0SD8R!ruyBw_q@*=7viaLY5s@Q%DeR@A1u6U_87qznFY6LS4uKq^{67|n zdMSw)erkQ3ODMN)PT!3^KN=Ckyx(fn$WNVBvE*+n}LO zUleT=+9(S&T4iYA5E%$!D{N&8_vDhX8b6)r4& zoO4r8(jSG4f{d?l(AP{7nieUK;tqj3M5!lPQR5cxyf;<@QG^l*O1^Zbcc-`c#&l0k?Kz+iX}9;10WZbf&8fUgm_#>41IHp%*XIuAy1LJTLwtY%Y} z1$DdCLx-Z62Gdx4#Vw}G;!eC=c;{8*uM-eQiXoD(;Ly=YK1F`fM&Svbthjv|whsr_tLq?+p%BAI*hz1D z#X!Gpf^Y&S7GGs_mYnt^9e!tN#>BP^X>v51iufggm;Btg2E-gL@!2kj zw*=nu&Gc@qduFhn7^3h3FBWJ{$JU(({7MBJO(B|ZW_!Dm+;Pt*f_P8iJs)@XL3vwN zriL4%a0EwIn#Y34f6IJ#3D_IFS$s{o8J%4=n`a>YOyM)Hc*gLVVRt|FpM@ey3{iYz z{D%%bUu?Kc5G52!_$Q>wk9?oJ|Lu1aZ3No*6s6DpxOM4Q8$ry2c`Tz`1EcHq2i^*J zF)U^i6qIr=%!A0!MqEyyoVRY-nzq9l%3X6%WQrkE%h`ZG;sh}y zh}m&kwDz0KFn*6Yio;?!%=5`F*k9~BzrYejCV@=CD$dB!`Q=={RBIF_V8T`iQmA!4 zXd|&jyZ{!kt+CdYH@X~RzZCIL3O^|e<8PQ{a;bUoG8C&|6?=Z!(H*4s@H_#}fjKPt z*xQHiEbN$Qk2s4!7T=cdOWJBL<|GLsl|U-L7i(%-?3zyg6hs+;GTyjH^&3@v{Oy;c z*a#chVX}7d9<3eL;*7Y1LIbf&u_UI+_WkJJ>8rx?Ap@<6p4;#J)yA|~FMBxtZtkpMG9ysbCUn}6l z1P=2KrBSK;j}Utw6l-BETlRj+x5noU%>tHygl(kOB+W?~%3gmWHV1Q-O}*BqANEJ1 z1RM;(tj+DQH^ZE|%zY6*A@GDRDqb{tl5L7)fB3^aC@WianZiVf;dXxD8HT-57f77H;;Gef_&K*XD2GpqWH`Pi{T z>}}Q|o(fah;Vzc_xHwg}Iv8=N7()5=H2Fv)c_ZFE^oZ1y`2Oz2sXrJ|B^VB0fvuEU(z}QJU}E&OgIZ9HVfISM1TX;K6mr z=xrztiQ$l#B}<1mkF4A++K!@&Ko@U?gEYN8_40^F6crRI_}lVjto4N^^8i64i6M!H z`l&MZyh(m}G>S?JmHZRa?4sM^WCL~ypP-P$w^Yxt!h2#r$zBv2U;`V;8Ex0JQb>+~ z;|Rp@X?mdebdC4aZYhfSFrN)&!q4>VHT^aABYr{Q1&<%|s&Uz56Sp`NmSD-A&lZo1 zTC+zr97U+#ruB%*KzXLdxk#8w){U%4gV%M>p2 zOYlb0bhY(0qYt6@3;tr`QW}#xd{vW|fU_xN^E5R-=AGN`D1QV+m>9zN_HR7pWn5*g zBM2?f!f)#T|16O0^4zI;?kM6du!Y6fYkv6B_4Ydf7ZE7pUq6iow2oK3O43lY5NP3- zzCl`@VWnE5ApF6f^wTneseh^X0^%7kgKhm)t>V?a^a67bU!`!B zXJo0?cdp0Ni1U=@1n4aAHh$7u}*Ql z6t1G!Ltzg;1@9ddm8T3;`%g6T+r&CDh%?>VX9PgnoDMfLb!fC#==`8B%n@1m_SP$#jB)tu-QPepo z{ReRtg)AOOI-_z{Md0Z&6paKLc{6OkY|m7jb59Vup!-YD$XnSc_tKYNTZ1@}LLv{; zH1m+>u;9SqBuw49N)LX)H{}5w>#=k ze5LS}pH746&u?Vk9#fAZ5CU0g&QGQm=R2KjKx_m?Y%ZG9Rt0;gei!gl3Qu{W$9G(6 zP@kpr6onhOv0c`7+H6#m`$52)U=usb1>YApZPuCi3~@1mVtx+%K1VBGTHf#qMIM1X z-niA(uT~uLn*RpHI|A?cC;qMu50lj>yhGsvF04a4)Lc~6YTX2!Mj(w3{0Eo$ni-*= z1o4W%D}MX#&>di8b)rKMiDF3P-!^|l)a{LaV*ClkY?#ej;o##RuF&gHGvX8iDLmC# z-^9PBFVSg1QAMGOw>nSZj!T`woK_S^2pr){duLh<=^ALh8GmbJAzT z1q2Fs4clL|fApU4RuFSxE_?pNuu!kX)z8`yU!ib?k8hC9xOs|O%)3!EP-x)0wtv~o z6*=Pff-nR_7HG+-rl4W){U_p?Fq2(6_}>g)S7BrW16Bt1$G?;mn;yE=uQL~$@*iB@ B<^uo# literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_spi.h.AC453C0F657BE042.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_spi.h.AC453C0F657BE042.idx new file mode 100644 index 0000000000000000000000000000000000000000..5333f036669f882716d2036b857e7566c836eda4 GIT binary patch literal 1458 zcmYM!3rtgI6bJD8(SipV2`DlqgRq6oxf+4W8=7q))Rqw%Dhy!-WYCI}g0!VP3J4WN z0)jj%0jUHw2f_q5kts|?-C&}Og-AAeY%pdbWQ%NoL^gK1<$k@%%}sv)FXwxmRw@<> zJ1rR|Bt@K~lxvc>48v^4SFKSUiNkLKzB$dwqWh!bt3OOmX771xcqBYx&&cQ)?~%vI zgv6Kc>G^%ORrN1rp&ieJif2|KU2S8#QIV3AmQbyCuW2-N86#a2WoJ7K zw;3ki-8Dv?tNaLyGb*`4ZG$U_9($1X-ar$FY$ah3w$l`up0d0kpTz*Z4YC3huKy#$ z{PVdLU+T5;5;7n7_AH0HTXQsDH!m>f|nzQnH=x*d_ zh<0K5^uwXLI%Ce;$TE<<%5r~f$>VPpTD*|cA)OW(<{K_+xjjC}$KV*9vg4~QIw#)+ z6E_fOAdYOAoEB~u-)};I!5IQ)h!Y!l_{%Rk8mHgIKnhX^miu*oadNAg-$xFH;B741 z-?%w={vszF*+9TR=y=Jnr}faFy##|S$fC<^dt#TD@7x)MtOf1MY#HvQ?;gp;4$;W_ zU>`ll*n*-O$L^&Mk@W=hgqB&ej(FU(?s5nNZ}6t$vpbVy>x(l-kVPP()f<_E6&b6~ zO&kiLv`9vlT+{dW_M^yhkkdQ8blv~cpS*k1kfR`qj!r4t?CpD}UxS2==prSnPqiBcr7dm8L@HMsae^1|?=XWm0PL&}ahvRhgbVRM^|4SQfawvd-?)$JjBzE$qTX1E)Z#3 zk$u32UPjZbdrwru(Kh5t0+r?t8}H{Qev-T83k;N?q-&ALJ{~>PTY44w034wGUb_4y zZ~b2FAaV(T5<-L4HIc64Gq-OsD1ZW5##nlH+rw+zapXV>%h~AoYpKaUBL_eLEt7R2Fvt7F>Kt+c zB+w<6{22UHx3qU2c|Yu@zrC>Fr?qzvdObn*2Y-6J7OQ{maFWigAQuxTHXoSpUf!>& zjjmM;gdn6l?Xj7!y2szWhO7oPMk9u0K3=kH#N(W&+J!og^OsK?J9>1Uk<6vk zW`1a$?(RC7tV^KpD%TB{^<6J{1p4mYx&7c47qh_^J+6fNu2kE)X@mEsivd^eD=EF6 zrXHbm{M4Zx>;y{3cI`f1I!8&V6nc%{syRW4Q*hNhRP$Z~M&(-BSCL!G6;0`zN z|HDd3+2&rhud2!s{H5S86^`gQa)a0P@1GGa$l!uZ^Uo0tD;IUPb<^b-yp+I8N&i3a zcjqSq3-dz}-iYCiSokS*=fbCrMo$syWl&E)Wo&=_y-s)yLL?87{D40{l^0{+UuMCJ z@Ekn67x|-qmQs%I>OS23`PO(C-hZ8)P@Wi{66ZC<8~? zus<*|=k)MpKP?d|0V+ZL513EcUsAoXmxMvN7|Q8BjBj?ESRR^!5F~~mvFe{ARvxfC zHL39tLMsogeBVD%?bH2Z`vAF=L4p(#sC7qeo0X--?ML{ofbR<7KHTme(byaG9pSSK zK2uwL**xgQCWduKLz+HhW>$*r7H7AEjCBk2pfC-2|qtr z=W|GFp`3*;^KhA(JSo`d)tAwY2wPx_@b|}JZ%k;UQP{H^41N*-Yi_^K?iV)00Fx|s>qvQSZ7q%mK%D|Hv?`wMD%{3Ey@(lbH z;7_geamk%2ZsXq}q{|>(CM3bG*9V&_`W;r_5pwXC3j-$X)91pNg}w;EVhE-rXjpFF zY57|VWd^1Irj&ua)6!n`hP^s4h!H`||J?bRxp0n)LAb}mJ-UyYmdI!GlD;B@h#`c| z@vd*>iHelX9U1%!|Em0H5dX@Xt-rP&!0;~x{8DKBfgpph3o1db2%lu|i5g_p8so#g zuT&sB2Y3#`SRGVh@QE|2M`#d1gGgxf3#GH`0;kRB#2`Qp0n{MpPtG>IwK5qYgohBi zi$OZCBVQbz*qMPP2bPpNxiJq?!&mM{a1?{1SV*2D&rKKZ9r*wu4ImAK((>R*Rj(;$ z-Xc5|!BdfNgnQ`T>v6jSyD)elh6glO=bx~hbll-Ff|D{hDGN=aJoJ=G82pgK z54lh%EDr4WIlW&ALJS8nR3d|O!nRg#QR%@TP6}}}h+l1;Q`t#x3xcUKm{Kuvtlbpc zYG8!mECXkmP}lsQoI1AS$OnXHa(E`!_|sAKO?O_WeHh=9!918JjPBFtM*3_@+l1j7 z3Dii0i#2tu>V2@*PK7}h2U*;pKR>k2ujhlC@;3-=JhV|Mx*nM1b*}I~C{;kILa66M zPDJm$v=&s^5kDmGLn8F}h#~W*T%9rvp;ipF)V7+5+sd}Tn~#ttg*2(qO`;;>@l%FR z>cyZDppi=I_DiStT==Gs;2{MMsc;`xFUzA_?Pv97@Q8y)obXdzL~-XarV$9P5^$9W z2|Der$=q_2QiQ26wa1_PR!v_utaqw$UluOlp@0|8pzf|y*6VmQf+-KCywK#CYn)U+ zwq+w!iJ*#dYF2%|)ua>9kHKv@+@?<2o;keloc4|gN8zZ@PPaSl++`phg5f*~S{vD1t^BOE#-5#&{NV?ayE`Ocw6JSsta{(|#|8cfbxI$6=t0YQ#K843{aO zOd-r*lY1t7$=Y3taEpgqH1hTaebbuqYiJ4`sCH+2Am-%|K39rC9qx-{MVIQ{ip zgm!>-5E@+OvgAmyioqZTDI!RrI_TzDTe-^NJi>BVF0||3@8g%uzU_|T5*d`pgcOL` z_RsH0rPBs8h>$~sT)4f0Gv^=#OCVSxjJwXm_c_>F79xC$;7SnH+eF z5F~>jnJ|6w)^Wu%8u|}mP%MICkuasJZFsHa7_|@KmIQ7|gc(EYNTFk3-p5-6ZF z(2kkpr9b*TLOBoRG$b{8+bJ(EP#MbLiyXelh2+1f4JVhYXCPbxxI|M)(#J6qUwaiH zc!|J^ny|{~ULV5&do>wc+^d42r)dw5X9~;`8`xK45360CDbJGx5r=A zPD@3&D~7vbq5rDw&b9;;e@8Ik!GuOq_iJ4$+`jw=55@3MEc9Ub#c5Y`rQ?RNBig0V zPB|h{E7dADIfGCphB7KG>OmKEJLgUr&cH(q9yB#LIuH5uV3bUofir+JHOcDxSGn1) zD-d4r@PZfC6@LHZ>8(o)8o?l33gJ|xe)~CBmkg7QWYD6378(Sw_Nt#pOag+h9DL!(A7sGpMkeCZ&T&GldBE(1`h9(~a#r3hC_mdF9#SktQPTuyh zm-MtskI@WtL06bcIt+1-JbV2FhG)SnAsn)J>bXr@{>8AT2s|mHK26qd)6%R)m;{rA z8kH-bIxt$T3BwCvq3|<0We=LnlQ)cE;l~_2ruw0@CrI|!@k==ccx=&G+D#u?#MY;WDLwYHZ>cbI(@@f5BhE6)ko8lIAhD0>dp*XrUx4 z?>w$W`KIMK21Z~c46gY@yZf~~e2(E91>`7%BJo$OQKYYN_X!NrC6G=d+uO2b_?`_% z5t0>Fm;SjZgmwy#nWI#nVRa8SSr^~T=*x%0oBR*%4j{ z@e+uq)&GK-_vF{t@0-EE8o(NaqO$2!_my35oJVNmpp9Be`&)$4m49c>WN;4735jMq z(_!knR?S%~{96IPX>q*d+kRJvY4;GGN#Ge3>;Y46-q%eYKAS-$2bI+18^cYWw7$AB zhe478k|+@zMubiowESX!Gj~^;K#1UHCKlDBJ72|Lf^F<=;mDZyDws4e;)kl_h$@9=rFEk2Es!*Jd_J%BB$i{Ag>8}2%i-2 zNg=F0G;BAXeZ5?7F@u$`Qn+WkMWM1!T~}lHffOFlJd~gN>hQV~AqW?ExIpvifL-f9 z1?BrlaJ*TA|+(i{k5Im*eNq60B*stqXlO}|(0AFbo zI-Rf`LKm2c<6%2wn2;zk0n^nZ(H7_2|MabkK zlNUB#(hW<0JZOtT$WTBAO$*N_%ssTW^E-sAa=0oNmfzdl$9GDN(^|#grW|h4WPZT& z*Q%~#4H3LK@aBX&-?X{y+uWC72=ArvUMg&B4P9mEs_x{vhQTJ-BqX!NNa(xIKM=#; z0lrf$@Cns>U7i<=;4A`Xnzh$7KD50(y=5(fQW2C=0e%;!Bh!1|hF~WKI~v=se2rz3 z*0&?X^AJyM+qC1dWrLFBZwB=usHdlwB8~iLovfV*24En}dD)x&`mFqDgyBFL1kzGE zuwP^NeCb()3<+dVCsn)NzSrZqXdMF|Irz|eYs%P!DIJ6L*E49BLp$ZUzv;-*3|lh< zTM5|GLhSLF`fC#N2M9Ji*w9_nKDDnlm{Eh!AcY30kO+C=-GBAVAHIQs2M-=}L|AA{ zOyltm`V8(%;XaMmp*kB4f+}?p0(l6eBib4&dKp-+N4O(`JJcJu>N=;LJb4kJMhrDH z$aZ@U{(d`FXCs3OfC?(8I}C65WJaDwuu*`GLRhsdnb#I}qw5=lxiD8)cMa}3|B*}h z7Yvulp^RE;?zrS{&tivfV(<_ABiwcB(tw<<7Q3Y z%-}f>&v{{@%J13l=;g_U2yr5aqvmt1ot5oc8L)-HLx6{r{$(mQ_V=b0Av8;&nMzTs z(~`itwy>=X!T`ePh@0`FoHubP2u*TmqIU8~QSKF1HhCL^8)CRYTW!77whq=_&dWaHSk7>4#)1=BQXBL78Qhe>O-ldnF`JI= zROBIqiXoIvy+6ifWbyLQ9SlB+;1dnvBlV>|=ac_~L4Ndp$rd%LJ1U7avtfPX0_}32ZWh0 zQ<&>DLX5)Wf`{#9;a_6-MZ@vX`M_9@ORE;0ev8n|K{G8IKKp6}1Wo#maGQhM^iX=L zWx{p$L)Hv-V;21)OoD3@(qMyDHKzU>L_a(?C~=Up@D-2y4)0-(LcuN>^j2WsRW)V54HQpBMITH0^Snr`=%P%Axr-#gGMS&X3b9r+!D6d3ll|m~u`@74VjyP)XLMWC%F+F*Y?K|)`|1cBbtr*@? zRj9K|__k_l6M}^ZET{}S8Q!`3Psm|I2FVggres(=_*L?rDqn<51!Pi+&T(=d=IYkT zh=G*?tQ0~izBD_%e)EpA2#pG8q_y+c7HjwYQxVFb?OOx!7>8d{XA* ze;K&Tz+EO3fUZG~HdQ;a3Xi5CM2R7adavqXxw>BYD};+uxJZw7XACm@@F>!IK8& zzNxvBng&E7JmlaZ?dPb@s_i4=pCBB9L&CZ<(s=%zXj@$~7Os^+Exi_=Q0BNX-X|8} zw-|m?hAeJyJKb?(IYI;v5p-&w0bhF8FW+j;;F}n}(Glhi`Wt8OGDmnJh8F}fqvFM* zuHHs)k%0?MLSbd!J$F8eNAMJbCp{F+y*a}(YFAGS1{NGxP>ud+SyH<5m=;321lp-a zKWow7*4uSCf;|WJl!Z?R8mK=0CjsFO4|nK3MClJqK<6Dop%eJ^*~6yiI--H~ZJXoi+^Yd9bI8o&9_7 zET}a_2v#p{(xhubm81IVM*%lYT;tk&4BL5Pq+ zgiKftc;@7H+}Cd_LZ%2Zsjm43+ZFXb{RQEb7+z7B55IX{6~$e zfx7{Mw+y^#Mt){kwe{rsYzGFPr0|KB)`l&?sd|IgIWm|J^M%SecFc6oaPc_||5U(F z>bq&0YieIDP;6QH=0R2G3|1 zuljI$^N4Lf5OM)>sW*OPbiQ8Yx6OsY1rc1JM*qItskiyVoe1V4FsE|_^eLRB*8M1g zn;6`vBKUlbT5wN08NpNrrZVAm=fn4&jYi=b7a7EI5KCk4<@O|p7ikj_+&OTk32Wxi z(68cA4-gi^Vqp>;R;0F1KgRhI3kQlIkXq`;izzQwa#08-049{>M>ekA=ozTu%D_|# zrZmLz3Rb>RTQ~wCUjq45rR0&OXSG-4AS8+*k!Ji}+h1Buo$>?Wxg4I;%y&F@@zSm@ zecTu%NFagMI;X50=dI25M|jM`W77+HuB3DZj(S8CC)m}lS|r-Vi5`yP(Ul& zq>=NUr7TE6xTAnOw4ezLpI&0JveApdH91_PqB>f0T1dsQeclW_WZ*%I%lFoUv{WYt zBe;vfojP^i&KXbUWDW6Q5HE&!%G!Nq>qn-I) z^nN9Ng>_PgwMGb~5-6o3riuqWIuqlHa1u@mn>TynhM0Hc`vc)-4YK%2O`X^y@=!_h-n+&q0kWD*ekq5S)Est6Nuf412?%#3aF^!p8%y8z4WFEa;2{DJnyeyBzh1S^`a7Dz8-O>o z|F!qUNu!BwClEe!@R{DHb$Rx7+KxSYV;B_6pqO4LXo{?7=4+isu;IXlYO~|m>Lp_h zEfKPL$fn)Jse3J3bE@rP861YgLIdh`OUxd*E)K&^JUCI-4#*gFNx$F&f{6%B=q}Dp zy~z5Z03OQT@K%=(GwGOK91Xe5g~zt1S%E*`^*>Y>*$UU%0npKM}Fy` zZe=?%5q^r`C+*MpeEjZx2!{Dj%>O_E36z|BDy5UZmii*3$RLG! zBXPW?R&FYv$e>ONb@X<^!|9Nvq0MZB&9GTmFxgG%pfNppBZmKmzlFXyxaiF3o!@5N zW#JbJctJV)cz|zYw&Q7ps~lXVyVg~S7>> zvdSu45vq8oqVH4|RJ6$FHnk=(cp`@KI-}i^$;x#W>>BIr7{SYLpVJKn(sGWCQ>=|9{_~YSnXQ&scrR~G=yq7RMTgLHF2M;zWR5) z&!9*IMRc+In$A6)uH6kGOblVP`E=PHe zq$Z#B@8MN1`=zn)6M!c)z0FAPG+1lYNQ6*1gwl$0oR)iXe3=P?i406A2gQ-iqqMfw zB6!KbiwebuFFKD8)(v>bpiTjGG#fj6Yp)F2?uqb21V3o3j_%=nU+4FgM+{m3TIjwj z;^c!Pvw{$g!*L;ToZo01uy-aXLCU{EfHayp_z;o)9ymrp`S0!X3^8R&DX)77C-2=8U^o}Si=9_^5t z`;E$EP$q#g>Q;kSt3Y|8Gs0aC?$Y?~*)n`;@w`h2K?(?>QZ%qJfBlE4c8?i+mcwVd zs$cDz9~XBB$YM|@hB_KzYRY@3%AWh?FtFsol7_&(BdbnicYTgf%tJA~p3{mLym*c6 zpj-ycJT%k)Ld4hB&UC%!5`;$pkLb>KEq^)TQ?3U>A`gjljx9aiKIB~cgy19sCn`rN zC)J}z+L}ILkSc;y0;`C?HQ*bM@B-ik<>B`wYY&ltNH@KxiH`QeGOoS2uFK&%m6%)Q z243#Hd=LtGD5P(^c~#YL?bHN>ZLm!!Vh2PO=eLQ67qD=Y9HOYIUpe!zB1pRmAxHv2 z^a=ZwvSUFi=Ol#;d}QE5IpTKOr)ha{7lc}XTB0P zBUCD&lHLw>$$q4B*&qj@LID*7$=UleY7_H|7_5i&LJ_<6_x zZcsZ7OF8uQeRUARYcag00idRBJIpuw4MM8|TB&s3N$<*;of-X-!7mZ~qS8IW{#CI- z*?5FYJY1sQzIJ_&+o5g$zGCo50gq_46Y~CFWqnOMgh&ZQ(kC5j)XyE1^shtklY$>j za=J4vg^a%1`!$0cDdfN*-bP=S@1J&Hmcvf?y2B!WRQ)FSNR7bToO(!Z~utkqZwL z9x(KEAJv$545B0uMYnhEMrmWj^uF&IR7jwLMr+~~@1By-w+MC|*wNdM%zbxLTyOKG z3>@U(AQw`{+i*t8!LS{vTPm6`+;I>dLz{VU_p(LC^y|;qN_%rHbR$J;87a4=I$I+@1DACMvZE$vh+z z?AX)ta%=YZN(SK~2&Z>MF~unzrF$ix7`TYQg$imXlMkB<^A;h5NFaoIJHV}A#+nH` z5o|fIrA~dTtV{6YdRC~ef1 z-x}U-J@N|!a}Lbu8S(6(^dYlyHLDohbr_BiL&X2AY|G8=Oq%fkp@oMQS~{f1&Dk64)vuaCoEYM0vvH<$ zh~e+kM-g5DyrMP5ORb8qbM@&6o&cV-_Z4d%6IM_(s)j+R6hi4@<82R2JCHZy8-p(* z_(G2#+mhEDy=7>RU@r!H%BL~LoM|={x}yl;mK<);WLO1TwfZK$L1>Ue1I@&XjeDy*MRl)d@Dbo6ZFwJD_v^Do`#^*{ zQn*8P)8A?H;QPl8BiKp6jt1nr6ty33B76}d#SlpyE4$Hby~?Mhfx%N5Jf->(_P(vF zQ;k+5gWEjZruzt+)Ok*s%Xowj3iv=Jm{UsIp&pcqumLs*bN5?GSLIcyVc%JJ87vd3 zCN#P1eB3;m}T{|#v+ zr8-M5mF34Q5t2AaqFHZZUanPpYZgM79KvXYF!<<8tF+y(5v)0|rj!5tarC|2z_$p_ z95@rKTM@T*$>Y8)3}U4aOIf(BLOt`fp9z8;4|bF~L5nZ+4?R$gupPDw8Djmf-d}sii(ajcKrrLLj4oAw z#-xCi+iDRkc(9;d#jaULZ3?ILZ(~r+K{dTHYf|`5eS3Zu!UqX_phP(KY|i1$9y<`G z!*pS4JM!+wuM5g|Fr3aoI+clSSz6ljHs&H+=HN2D*VNFQ7&*GR?!O}d(y2hM&daTF zi&Ac9M`Vj3o4%2oInpjQIzR;>PXu}YQwM9p6@6=i5o)DSOWRfK|LNl3cFc+6#|(}u Tv;T^?)-%_OQe+=iDJlIQ`kibb literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_types.h.4E48A9852A3C6224.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_types.h.4E48A9852A3C6224.idx new file mode 100644 index 0000000000000000000000000000000000000000..2d94fe214a12b88296667ee5fcb022c73a8e20ab GIT binary patch literal 920 zcmWIYbaR`)%)sEB;#rZKT9U}Zz`!63#Kk2=nYV%TIz|SDiaBcoPG=o95cm=qzwx<@ z&ci8JrUYe7w%1T}UwoWPf5oJU+Y0}FpEy_M7h`1E%*4c*Gjq$%>nJ{GnWtp9l;fl` zf15(W|8cSptM{K0evQ(PdyR`b$S*oZnjKizqPYx zX@>BId*QpXWUQBlT-`hA=q0X?S6t3kCx-KGd+h#L^TF&XpNeNOMea@0ndEuvYQvqJ zn37`)t$DoeM(@(iQBbbE{yzTyo&CJ7+Q%zz?7Q68%kTMlpY)G&eEL&EpYA*Ko;m-v zYiTG$ab<2&3($|ox^=8Om{)RhGq5o*Fb4?)iGc|QPM{nE10xfwkK*NE_nj;Fxfy`L z!<-?OArB^C3Yb|Vk9_}IG4Z(*Hv=nBL8e%yJeWWzD7iYhM&!D61UCaaP(h$zpahrz zDF6mA(2AnewBpx5=0f2MxtaODI2gH@Jvlrjz%Bq1K9gp2Z?uiz1PVKFIPk%QVJ-&> zgPaW$hPf9g400??80Jc#Fvy88;q?z&*A`7{2?7dR@mLALgb%)-vbnOqD;Ox;%E-~m z2$$ISxaF&big`FA4|5<#pa9HkFdC>H7PCTGnXfx=N7Q9LkXDlT46s_wJw2MSy8 zSilWYQ|;(g4|m!FbYc)k5I-!KR!lmQ_+Mbn5uj>q4sE#E4Tmj4`fo~}1PXg_c)(r0 zZ~Z#qBQ7Ejfx?RzITkVU!YrM7detxIUFOe$5_TMR0x;q3%;Jm%o0k3s3eRWcn9m4z uWcvq?9}h!Lf+UhTlBHql8H!SK5<#5eqU2(3AkD=b zw6(N4BcwC>lSQTD7XIVX(sPT&4%x0bZrNFR#bWGIqC4cPf&zF2rZqwc&qwllLj6efC0rjoy@uxK5qIK z;?o?Q=4fJ(*y|0qwqOa0rv#poMUoY*-W%V#OtX9`KZC$&LiZeT^?>)atoh4OY=JFw zYrR2U%WkUA6(a5;&_$L=0vXOc8PQRE$BRA!eQaw#DuSrlxiX$I)YokcxAdStqSJD#Iq@AdXVmoZ7fzGSuUmBG=$zwgxqf1pW z?f&NVlU5#^fC;UUT#8!adAncr5gUUs#beWr%f@uV4G_O2@b(`YJ2I8}`*g1%ifD+Y z9jCT$(sM?BipL2A64;3aH?>!5gnVj*;x2)^Oq>e7?3rCBZ-ye3Kq{+HUhUzWCt_z_ z6mw9_POU^}J97P(2OCkifD1jE>y2gR9@`Zx5RVfWXBkST_MAyxcZL_22wY+r>VmTe zluK1CQG`M$-9uz#a7CCv)(UYgfm$|xUJUtbLhY_Sia`Q{gjUH;EbJzh!%irIA(*b{ zzh5Vw7;Uh2LHv%uJ61gTH8INWX*O;s!XS(${z*z<;F;TmH{w(dQrQWYPNzIfU*zbI zVwk`%>(lzazQFx~F##yb2$Zpo$AluTCs5DE>xsOC zGBf>AD87I%=!%k;n7Vh10;3UMsXbNHO% zD*+x2k)j+PHxp=PX{)Ah+*|Zp{x>MBz-po7)+~nx2-xi=qB#_8Ll||jQSK4*)EQ&M&X>5jJ`l?E051nEZy##uhh&^EItsABA zEs7nmgD&>Y`(tCqwwHMPh`=K@-tvA`jEPZY35s?C?JTwW*Xs@)Zar6pLL0Q_NzP&N zLt}rclb{-L1qT)E3QEg~I!baAc;N}2wBdILY&Ab+P{89R0!=LOsMU;NiTx+nQ0Rj` zeFOf_RVwY#FL^xn0xudSS@ro!#eA#li0>1)&+d(RXL$VjGWA*%69gvM`kjAJR1Y@N zszXslpo%4a7`LOf>y{ZWDhX6Fp|N_8y>HR_4L$S|5~1z zu_K1Zfe=Wa748{fBUeV(-b36*pp7k3PPEC>CNRGXg(hgul{D9a%r&Le&y~9o?}fee zogD3M<~nF(_A}xf4s!l+p=5vTE3+@D<5y1+Z-&jZo=Yc(4VC1_hY^cFM5`aMTtO;*VD1QF3$UPg z-qFh=J$qt#Yy?I$NXSPArlSIypCOLpAdb~%Tx(mFsnWgQQHTkMSsC+UhG4OD8)gBVHj6f*|_$P)^+TBqPdZ0q)gsa28{YDn?%n-KIH40;pPM=Q&#J&eal*#|kAuvw^=lT)s!Z;@B0=Ij;CUGP zOAOJBY_`lBF@(ekz!Q8&*6??R3sPdFNmK(?^Hj5AnsnVJ$qpy63Rg||b*?pxKv{tChlz{9+>Tj}Bb6V>G= zkeG^7X)OQ$gzkyXiz$y%BAgAF%~PEo-yeHssQk!r%92fj_zC!v3lnd( z8dod3NhIz8-s3q1u38(sEWAh%X8_Oe9ZKRuswYTqm`uV5jaUtTFFI5!DT_^FKgbLxkxR>GE;?450zyB`aow$b7DF@E)C%pO7X z0QT@~c3zKlP1bLkM&c&mO`iYfId&e9YpqIRHLhl9_DbuPBy=xQBm4sJ1#fk?cK(ps zxV^JUtid&GJ$~7L-@;4!B5al1Kwg z<43u;ue@HU^i7Mz1;7hjB!>>vk3I39I0bl$3pLrhz2n!uTS7bb<9;?EiEm}b5(`6@ z5%v{BUw(;e3cP;kFT5&Xbk56|brzJ3{LuVMv}0GPnT zzH_TGt#&+UNJ0}e*+KPp7xl=?JTM}BAMieJ_KFkws3WIrOhOO!*!qIXD~<-H@g{^{ z0lwn(y1HC$a!VS&nnVO(1P`30XxVRItC1km0n@pdHNr+>biBDBoY9%Jx^}u<)v)I^ zri8u4(3_Vw*D+3fu+kSnyaRm4Lzgvp+S__5nvu8$c#YT4p&eqb99nBh;yd7Xe)k%d zI>iL3_*jv64EUHo&ni1yZ3FHm3E~If558mc!{RJRXtyS@441KXxE^;|TUS4E1K~M1 zhrM~1MwuL(pJpjwPcii5HG~h&&%WFkA_yC_VN+hDn^Rb%UMt`(z%Cv(Y37Gd6-6-{ zNqC8&7e8o>Yl~N0tLA1BuIMWF>nV(`y1BPaEz*YYH^6WFAaPgck&lMn+(zOp;9K6j zAWIL=qStP=BpLu4_zruwv!l%ihioU20+_<*W^AM`l30`?i0!zY)nG9t&ENL&l|6)K z;!M_xE{( z@gDF!kMTx4ElF#8w;_d@Z?q#SXXXZ|F1<8JmtwI?jHbXV9*0Ve|{^BRWcJ)N5o8giV(K|ILT zhe}F5vOak-fN%$32M;_=dEQC05S@%h?p z_=|wvnPDUf01LSIkz1qC-ug0}gdrNTj9T4~hre2SID&8zU=nYH=M2r%MU^GzNbJLX ztPycx7mZ$;=btC+1?a^y5@p34YQFwV5T$^nyoQ6pl}0IABO*y80w(eZME|9Q9OV;cK$9{KN5i#;I;U|Dkc<8&T zrDjTFPYGfhZe#6^zn@llWL#n_VNXC$9@tCn(D?QGcLZ?`@Ei}kskC`@XKk4v3IPjw zSM8c~D&omzp}MJcUq25>B)kGwuo-Cg-U(2X>{NNh`E(0v%WqH1NpZ3h9 zUJxGW!Ty@syf5XCZgH54*hEP&p@Fw~)l&V)!=?`_Go*K_)@tib>Q1 z)&u)});>N;M)pc<35nS_n?0CnQv0fvv)4Q#tdIIEpXt^0B^lp+1+0M@Y;}?EpVB3M zZ31>fH+CQ1`}zj@IbVECI0`U|r+I$w>~J?r#ZnS40blazwl!xub)-)hL=a#Qzd?Em z_FqP}%oD^RJj5cz>CF|nzTNela4ujjA7kp&`Nfm6eO{0_DuzdSBYq~|%V>~%T28_O zEm%kA>rK^c@h+$!{08t1&*;KGznvAK*DDekfEm1odevg3;v3dgBzypUc&ekSl+MXL zuoFZhU?UfOO3xPI(jL>OQg z&nL~xD$?=m{00(haV_i7>Oa;OTv2d)Pk0F~VRzz^O5BsiF58cU-O-(;nQF17XZp2M z0uBcZ=cm8@?d!NtGyU2~1Of)~e1bo@y1kkGMG*Ob`Fxl@4p~*E_rgAtXaQ{DJLYD{ zmwj?Uyo@CFwv&n4VY2rla*5ds*(Got@7*|kylYt+Ghvx5YE7lWRX MzitMo*VDiM2U2Ah=l}o! literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_xint.h.9C59935F074A8FD1.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_xint.h.9C59935F074A8FD1.idx new file mode 100644 index 0000000000000000000000000000000000000000..0d4e864fc4e02a5e0bd46e0aef00266e43d2c691 GIT binary patch literal 720 zcmWIYbaOkw#K7R3;#rZKT9U}Zz`!63#Kk2=nbANx9*8UEBzv4bdx;W<~}E7s}ZtKJ0W|`Oz)yBO9B*lKDYXBBw=7nLKmJ{IrzBoVbZi zDwAeTUo$^YE`H+7@I})PGBC_OE_aThxH2~hXgotvYFe=d&Vd*0942t#>x#!$+iiT=0~FTg z&=!QbWW(Bj+fOkk&ISqxa|DaSgxx-uTg2~OKOZP;%wY^SWYv3#!T+_=iO#X(o{cp2`KEv;RQFlM0EXvLvQ&m1BFvL zQsKg9xA!TR6zshT6n5rth8t3};rofnb#nKC!af{6aN!c&y=PZ7I=u%9J90R}4Jk^^ bNd$#YaZz$HH;`sxytc4({{*jFmDlx{SNzn zx>{v_$-ie`(srEv$o{wLqO)_WTr_P>#j~C*qNlPv@?^XJ=~j(z5b027u3pvbnmSKW ziyh{2xWBKkt+B0lN#1vnai=N$)!TkEmavD~cPza`DjO1B2KhO!*NPDu$lAVswSU5Y zc7;zpK3qLd-QQ>5u(0x3W!c>$vz)7Q&y@V$a@NSX|KHUEX8W=#COQkXZw;p2pM`EbIlg|6W&IOnyDhgiKJAHO z9k-}oH&8|0modNm9Vt`%(S8enk*wa_M%4S`O=lD zaM(0_u3f?HkZywoLQeNBvwmFE5p+FZrRw?G)>vXboN-HOVrHP2_?&^D1fk#QK?$xQ zu;K2?3_tf7r?cjzM?U-$OIM+PZ!T!xKig2R*xUW9n}2ffd%Z1U`E2%gsml6O)Wxu{ zLpvOKD(&kUx|?Y7?liB&k+l(zH72Xo8iXI}=zEnT*B8%w=3!E(^I%ZR^+yj$Ft7qP4o_4e{=7T?yWA!-y^Q5bPla&RaM8F)7xkM z%z6F&;=Kne&&sY-zr6K$)>)nY&7J0jkDa5|>uZep8;8$HwJ(>>-{K0NQDnvIX}y!o z-?~dES$fBY7j+^-tt~Xs5@^$RxlW-}ZQH*e=n1=B)WVBI@)wO)=W1t{UR73Ipms{9 z##vnAoAF}_=AmU9g4&V;+ROxA1UK}SJ%2ZGc66!VF%kQH!tQBRuM~cj#NOFzi^{&h1PtR;fjMbGya9N){VH0oOg3y;dr8P+4Jwer@rK5 zHvjk4=20KpsQ-KM`1$V+-vgcgw!T~B=klraQt}L@%(k6)m?W6}CNNti zF?!>NFUwsMbe5Zh%~Lax`|L<}Tbd`ZYMbYzb(((nPD!zY;WJgDZO!iXAgje{)>v6R z$$fF=qeuIyw`Bu#9Yv@^MahvXQAqS6l>&1S((C{03EiH{K0hPO0jF~ z!H-A&Q{TGHew*B&o#fHR(OQ|ji@(AjpT8wC>w)~o$B|9v9GA~#d2Ko8y28z=uL6!S z%#MI=yeaV9!5oYkTCUY)#}` zm9>{gmfG8x966AAZ*@WZ#Lj!GcZJ-sS<<8(#@JU;5l_wRQ2lCNHu-E`d4^~9QlpWU zm_8L(s>QOceFv4EQ9_)ud}Y%o--kXl5o-1s9HgB(6@9?*{F@|qm$uBfH02F7wJ$GN z$DClDiPt;1=-nAw?4H0~>aB{T(*-n-OApSd9mc65Y$^F?-$A)|2slp3?mbq^t_aD{!Pw(iD(0z=Xiq6}=rAmb?AHA15X7|_W zsrSg?RNMK>L^`8=igdJR+7(56uF~!K$-H}BBqrYL(R-@oNLjsM((di#rXocXaryAh zW&3Z6EII9(aUi}mrg>wk*yeRxFKyYVeB^n>&I9enHm5=#9+N34KBRc;T=auAsu5$l zc29=<<&#piRl@Q^Kc4yW+HvD^1r`+7nQHl1C&_$vliJpoLfu2>_pwsnm%RQkQ)u4J z_J4OMLEaNtMl~i8@QezS) zZ2Pk2E~Kj6w2V&t;WECnxKZ3fu9@PLyPMu;5GuUqSj>H;>{DAUTTOS>)LSH&=2SlV zG&kdYM}6PNG?$a=Q@7tS41Vts@ z>#(js#D5B>f}^2@>2oX|pXzREHMY2Bz3hm7`z5_h$Zb)}tnTKBj-ei-K(+UG`m;;m zoTW3<8+%`#6H30C7BaH8`}VaESBs{HmM4E$&Dnc@#+1{7SIMs){}`m+E>PQ-bvE*o zmRfAh+g{e^SI$GZsdlnkmzYRessA2(3LU@o>uHLbS0imp;Jl=(u9Lx2Uw5Qj{;skv zt1JBidz2Ev9`N#&_SR}iHw{&~wy+5*HosyZIi?KH3JKNgd}XgaA0Nmhln#61~OK0I{blw;E7!+IpR~4w)>_Q>zW_^D7GsAG3X zLTf$p8I9EVs`M>O=4M;$6aMTC`&_zyq3w9_&H&cYto2CJeiz81f4T4ZM&BF0x37?7 zUi`Lr*Dt&I=l7P)--OQ>eU0A$|E-Q&J4}^QTYBzQ$g15Y)f&r{!_Et{6WO6}B z(P7biT~SX>@gMVO^JB(@g(%tvhqHWNi)^+QRut_gPvuV<7|+^k-hKeS9%U3{@~Uok zabJ9%dsF${&L8Xd%j*qxdAK+I{Ng-zE^2CDLd(C8ueX*;sCB0LJ4-Ol87IXC4BRf< z(z+dBCT63bE3S}`v$9&fq~eUcuj```_jiKvzI(}6-Y~6>Ox{q{&AD|a&RDd*z0=*e zZQj^mgRsf=B#JP-)TQjfkrN;3haWApBhS3de42Z6_>brDCjYbJ!+P=0N1CwJ`jY+=$1@~EeTz*p0^j_W0p$EHWJKbEjHlf+<$I`^= z%tULu9Ty5MmPHi{49GAnG;eH7v{O5{%j<@U%pmu z+ab+VqtS1^;XignsUQzG+t0KL-g7hNY}nGb>e4MaR}%u`4sKf{p|`zV@{!q^AHKhe zH%zd|~I6uAfOOVFl$(Q|$GM^WR zrll<@3%c6s|}hf-?PEiUm2xh8o$M#1Fgvwm0gWTy)xPV?jn&!B8pl z2VMNP?`+Mvihk-}awH93RumiPO>7n3qT;}O-}%gMx7zBw7}fMUQKtLUqWbrLe^P8S zG^9AG>G1m8-FGVvT<o?ebmQss&cdCh$^d;gL7v)Brodm|E`P%Eco zKi;nY&>UR1XeAq{G_`EMVu0m9rWw(Bt+dq%t$EwQ<4BW)dSbbWr5)-?6 z+tS#*`b`I)oHo1Mvi9MnmZu4q*P56=Uqx~fT;!#^s>x&D+*T9uy_-#f7w#pk>D$v} zB6m>ob)lY+n6HbBz~NVnEBg6TGZVc8GadcwK3TWFn$tEIIH#`tgz1uXx=Cl9hSFEx z7@BS_t zZ9VhGbgDwDE&Z8IL=(+#rS601AG5x66)sASt{Pk0eGYlC4%zH-ma^jf#h>OaM>c*7 z?o_9&`KsXK*CqM+by|$k!F^3jKUs*{md-0V^CNa8WBmZ!5+miuo$ z<@iJ1$6Mp1sO_fHqy2}M?^ygpByH2pCq9+6ufOQ8we35!X2Am}Cil{KUy00W`6FLj zU5|O3v+FNbRTvHI%;}dcShrncV2)tRzU#3qJ4KAVdJ20&>do3;C8gQUOLSVE@wBm} zVboo^{ngaEy>lAoXIQ?QrK2BhxL;}ekZ(jv-tO~l35n14W*b+1HykmYtJb!v<-g8r z6^WWr&tKM`T|wF?Dr&oN%}aJhjf~{ILyJ$BDre~V6}zuH+Cm>m8wtPFzxdYeZ%fzz z-dfvc9@?b8SJfeHlU7*t5kn2{hwHr)bKQG4*&ONf78h%o6tpRL7nb+D;6tkG-b-SZ zJM-KMKP0%GbQc@fzUXP}`RI!@`FmsPpH1~qH6PMn(QI@2n(yt{ec!mlhIyl_P?V}X z@Yw7|+~hxU!0+Uk57c-{abJDxh~JYFg~GiNC8ix84m~-$)$V4E{mq1|3W=*Poc>Lcyi}h|odpDh@nEm(T$NCeKKUEtx$sK#U#A3POimb;LrH&e6&W)!V z7HSHuKRWP1{a!?I$I*cX_16mmZH^Aa&#QPAYi4rk$<9dG0D&X2XL_D~x5(@hk=XLG zqOVhPZSE=S8C5FJdOysIl8o;#`q?lqw{{a%nCt@=cpQLq>X}+Y1t#Y&e^%_8IZ}~2 zKSx(|uMFeqWu!^}$_e>5ORjyDHa;b&oJ|#N{lb!`vdCWW8|c(SiTz#P(SHmC87IBH zj<&Ww3Wty63WXt6i>SATq!&*(Wb8{KeAncl;?UWPDh-nRJBnvU(*MVmBv)+ zNQ)O;j$hmmXS$xYUaND-+2pa*_}9t*PH&pruxavl_?X!RcjkzAr$)ZzfxJ}n=#P)B znjc?EH?RNh@@(TT>q*jyj?j>TvlgpFYENJF+q*8&V)CHn+HSw^Sw3M|J{|Ug2^xa- zW*Kj5m#&#LA)zs3qcNmq*>%Y_QNn9!chJeRrY6^wyGBwjj2h<#t0zy?5!9nf_Jx z*0L~?Rey1T9_EP!GDDlzt~ket?E6Ov>Oa@&r5 zhHk(RGy>VrD~$-R&P=-g$1RcT+ZJJd_w@bAs`MhL}Beo zoL74Pt`FN{qW~KU<=D)Ekt|qv1jZz=`IBoidtqGtf-|u!Hsr5@{yvbus5!ffa&$7VW=qyw9n1UB2aHUqC;B?}z9D8hmsak$+isGB4-0%H<%ffiv_ ze)LrB_?vlRZ0IJ3dLKsa!_p%#CV|=AQFw33M`-T6;^{S$4V?uapan)+KnGwFFstEv zI5n8IFXCLXl{5=V=U9!SKyeho5g3!efh7|-H7U#L!cY5cvsh3vhgwU9YROU~FeV{} zIAt;6D=hN6O-{2+js-pCP9>8&3z9XI1r8|B&1bq@78j64Uu zg-PIS7q_<_^k)kz{n1fiLRO$%V=!q9ver3eZG0+tIlCUCjjvViFAX+ zCL|!DaduGic--nmgH|gwSWp&PGd`Y+7*G*I0b(c!FDE+a=BYiZ{#wNg*w8JGhj(D) z4wxgD1O`iC;%h!G*ZA(asd^C$dcom_(V#FIa|FgD#F!7lD3C)< zg^^UynV1A-zjHg&LVjFQ{%fZ;3(DtkD`-#!4dr4IVn{Re39|<;7!2CX__vG=*?`vf z!AKu0N=RVU{210veV1gduY^9-VL|sfHp?kcIR)(}OhSy=Ol87mp!@2T-M$M}upxV3 z)0>2NlVk}AY!<_K-`}38w)o1)NR)YnWArJEJOz!yB%pS48};P{EwTEDz#29b&f(sL zk-Mb0%~Qc<>7*{esa|3X_1k z5gY#Ud497)zsl}mLAe~89W)EmOCQwzxvcu^Fbm4&*z}-49$+!UBxwDz zKKM6h*;(jp6R*9?(}oS516EsMq!rYTNnrH@*J_`W($n1X*~i$BAIIt|7x z>_Dj=90w|4q!OMn0%H-nZ z@k{N`v!Lf3Y7z-b0&6fP0Tm)Xu1{)LkfE&pMKpTA;wH(4bd*oLEJDg!lP=%( zWd=ZW$$eJW6CV8vWUjEpRoAgoKgMMqv_AEl*&s-t}@y zWawK5v7yTxqn}{p6WE6^37FIKz(COM;E;`3FdI4qjQ)g?pJ2hnB%p4`7fi3+X^kTF z=Amrp03de2NCzNd5)ilIM9~+S`9DMZQR03;9D$J$uvlXf5O?7{dLSgWKaqaxIveuk zxS0bZIbcX(5-`7Vht%ceQN6vh22gGUhZ_kakzn)3B;b~C`^oHEPRFR}^KdqF6gbce zBfY>=Oakgo+|v|+N-?T_>1`HNz%iOgh7!Tq2a^y(f@(l~r=|==A=#k6cbHH#hnf$Q z@`10I1V*=D3!Aq~-R!w07ou6vGY&C@2Bpx@(+4KOw_iXEXir9f@CH(TEDOruQ2WVH zKN9~Ejmu|EGUO#_7N3&L`6?@m;@fIAUZ(NP4`g$GTj6g6pvEz zGtejl8fDCY7_x%%2;QnW1$J*6wq&rOV2;UWF!Bskk4aE{JNKh*d*A%%;t^678#)L) z?Szp|@S!jXsN3)lRp1i;@ON4Jb2j7*h|Mt43_2f^fcTc%B$0->QrhK(uUOCnPW|3w z$eWB#Q%r&;sS&P<%yU}ofrLN;_9P_L7a>tHTp z5>PGhxm;?zVXf6x-BK3xnA4s-5|l?m`xBF(J(`4{1M1Fe<#&kGupxI~vmQq3LC<3n z*lgfd|4!;tx&EHxH7w`}$Lc5*8l|GAPfP-v+9Uuq383d>MG+Ok(TB;sVWF90AK1_-VDc@DyakS85|}LG znykoNUtKAj(87iSIF7!Ck=LMlOakuowX^eyN3Fw7)m9c%$l73?Qdg1Z45CmN7M=4`05P_p4Z9UEa(--WC;~2p`wc!CPDA(5!Cbp zI(CYkn!PM2X4+(m0F)vi2}~*xyz&;x%nPgR2iVXN(4Za|=>cODlb}I6@G-h*OGl7< zm(gD~6v?SO8b+eQN`gti?B%W`)%{{;;|dp#v7m<>ZXO-VqoWHHCV`)-ME&Q@FWy0!Chd-p3^1e&#L_^;RbT7MrP{ zTu%-+1x8Z9SivOVwsN_tI~ugfKGu_LD2&5RhLL1&^1&qFPG2dYxAoCGBZU94q0^wh z-oway-~uKAwVXQuiZ6B6zwtlyj|rUwR6i2QkA!vtCINL5w(>7t5htH-kb{~G;#8jo zBWb`@OakH$uB(nmjygS1oQ|r%0^CRnzPL74d8Xfdm;%G-x#1onbPtik0jPTFRkLP~ z69pjQRK0L2dP~Lrh`0;P;D%dp&>t|rjnp=$OD;tHN+Jm-ktDfCaxpy4kFuR*1K{Nri;Y}9yCQEX6VQ`p|P9!UGk6IwIBwb5Zh%uiV4I6=r7z>LS%lQFQ zkV+9y;BKC1CkxC=5m>;ZC=`$>6qv(30*=6i0_ueV+B}LT0mUYP`P?%NdgKvU*d(x= zPhr?3u$fR0Lkr9>JkW|yviQ8(&;MPXHw(=DNwUx+nY)$~vjCLABd&NE;!6Pp53u40 z5nBZa9#6#)B9cl%5j=c~BWT4PG{p|uLShgR!BjFz#RI6*)NZ;^H(i1704+OAXAMse z9wNR99KeIBcv&K#3anz$R2+a%Blj8X`;6HO1dR?Ltm#>U;=%CI#`x79!=)gz+y z2zQC9cz+r?knXAuHm@O)_7KUC$7%?9X$aYfP!Ptzij4Q={vdK=8)U0@`YE^w1m+TB_z=j64xPA(Ml3+PQCbgF1NAETBkTFa;CqKbC$DPGW|U(l3zY8jx3 z4$ydO8K7wn(0FSJql<>oc^P4J%`iGIBZV%S!pA75i}{G(hn1GY(zIQKQN)II|KAn!j{~zx2gKnU{jY%d8C(R*_L8ktCEz z5+x8+@edLDhwv(%(uAJUxC$bi4eG-~*mz+gdJPafWQ`-2{{4H|NR2T7h!0HnneGcB zkPQ$#dX1MM;?@AcgVi`<`giE&PJ=b;z>FFuDGZYq;sBVZ*T{<3$lT)~vFQRMcoZAw z>QVO{+qCD~dSK)^S?M`ho5#p!vcl(SBUWz9jXwp2ZUFt*gNXGY@&uKLf&=q-=o^QK z%?u!Tpc_Ys7&k!hxHgWY{O6tQ817}Ng4R<)LP|&iL_MgYm4vkNDTYYM5T9b0gbed3 zLdZx6nb*cOGIEVikwHc>{!gKhL7vM~Z5A2H;$viy6|(pkEo6ljKE)@p!Y4k(1X*Z; zjQ-~i>v|u8^zkWtDJ)+KcTl26lPSz(3ZD%M zQcvNvF-k#3|4$)5O5vWqQ5)e@B%I1yB%CTAPUU5!Q;~E&MlBVo^GhD6bLYk5Iqy_lY0s2>e9q=AnyKtl%pPa!`*<8>^Ij)c*9jfT6grZ^ z$0(;G<$Q`^y23D>`}LJd8ryT3LOZ}fHKm)%6Q5^iP&mb9md7qIb5iK?DRkc3SUFvx zoUTq#)4qER=_oHVUy24%u@Oz2#!&?}qKVTus=!7xaT-Sz*ofv)U?ZA1o}&zGMDr-H z5lx)eQAP$CjA%lEx|~VY%_JKT3Y38jaXtkY;)DV%@|>*uoUaHr=85AEY6BbdgaR!x zNJa+9EaFyxGO$TNC{RWif`lO~;+lXmuvtMUP(}(Ol!Ay8OBl+)rU{`y8I_1~C8ADT zBv1x6ZwLj-Xh#&<5mn-5fikd(#G}9_63cTvE^0l9Di=gmBYK-~3@irt%PCGJ z9!;qzfMGf_T~g+Gzycof$Vp=*c?&oqcZSTV>fLIE|; zlKmKKXbBv#rQ33MkpuG9U904uSb|M@n65QU=f+*09PBCBH1iv$#4-9Y?lCN1rrOB0 z;qzW#=?YB00!tFhmX7sG`rKQOtbnZsnrOrHiF9f`d}f<{{6SF03#NO)+}H*2Bn%Mz z9T+!9Of7)muf904S>;r|TF=3wAiOk85*_9XFI^*xUgL`PACz$@c!k}{Vi|LLfOx`mPgtBNW7v?UDj$$y z53JQ8QgzdN-s8T`>1FGM^y0|b9##u4Im86fzJGEpYpTw<+>vjeE7iz?qm)gn9~ z7E?|c>}45;#`FfBX>U|<1c({kjC+sScG@HGpPTbpU@M&}pFSO~B%Yx`3H<39w?zzZ zfZz|!I6?%pWKaZuSH=<4d=ZIRM3N>pRaDVTVm9-IxcW)Vev&k?hoX!CGBbcIO>CK{ zB8ALMAxrbj(f4HLdvx9ssa5FZfz13%mgd>JA`oT-B2D;=+Q>whnTRyc&QyyqYY}Op z?@&fJ!tCY?ad}gi-V|wKa-fVy6y_s}G|x6uO<`73q0kwW-wivSej8q5}lbumnN2GR8d4{7SW}N zr5RNW(3t~tX<}*KUi$b}bmZsrU<|!Pq+TN23qO%a07eR)J%En~qB?-!xdJ%yIb`g& zd*9bf0P%(CzSGMVkw5^DQBL*%UIZd~6(D$)01ov!$H;oA9`^yr5&9ACg8CF0KCH6w zF-L!zep-UCM07Ub<4FWKMC12eU*^CApjsp=|{P>E6=&C zJgadq0QA@ZO>cl^MASbeu-do6P$>wMxC+y+!cqi6q#6JOPcOhBBC!Au}H`-<)e{m zG;kycrUy-L!^DgO2%dm|J3^EN2%c|%BSfkJK=AYe95J#!`*B;OZyZ4UVY>fx41!2G z00^FEfR`Z_5`f@Y1vs)#Ab0KI%fB81)q_5j}|6G__3+A>jWv(xU zH@4+VS?WvC$C=Qrs-r(u)6MH-QECwhDdLO$G?S2KK1DwX>E}}fkdXks$W96wN#Rqx zCnN9q6o1LcUp_?yf<*8|Wik;YlTT5LAhmpoIs~cXQ*@KE)pj@`q0mN<~8XqB6-;B$-c9NkuC86m3+bjZZN}MW*-^5i}%%FDjEk zLo)ajH8iA#Ptij|diWHMg8vfV9IgXnDFCJi zOs}8B(+-%kcpeKrb{ak}Teo+#rxA?*ams@6=`%W!+yboO87+7jB9{dqc>W5G5Wxh1 z;MpoTLL{mH1kX;vk0D3^Gs16_irw%|sHBO)-5XR_ePL_Z_ZDoe5( zAcyIPxmT0y3(<#=l|snew+JGa1sK5- zSa2gm>Iw)?;Q1;zf?D;bEBn)z5Jz4jdj%N5Ggfe_;}N@q;HQ)0VW$J&$0(ZKLj3*Z q`903_duaMM3B5yhmHS5YO01=hqVJO9@DMx~;#rZKT9U{DWD5gvaY<2TB#@2;;)*%R9;eTEZoPER dO3g_Gv5Je5i@AX`6Qjkpg}c(e6iG5L000uSKGFaH literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/ipc.h.03A3F16C4A72C88B.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/ipc.h.03A3F16C4A72C88B.idx new file mode 100644 index 0000000000000000000000000000000000000000..452eed811b39ecb56693b253599b635987f3ecf7 GIT binary patch literal 13496 zcmY*f2|QHa7k~H7dt+o~Y*{0Fgvb(FWGSUmw9}%+Qi(_sX_2jkN>a$$@{44PP?1W7 zgch>3pk04$)>8PtYu+8xeCGE%^ZB0dJ$F0j-g}OgEtoei<nzxGo6ra`W3nU>GJz z{kO}{ciU|ahRs-xVF5{B*Lm%FX(G|MWq90y&ovryYl}XZ)c#s7)w0C=%-0qEttB_# zY}Jy8HM`6@gJpl7G0^6{=cje_1<%Q+B(F*?UM{Sh=h!u2k5crG+rPf$UOXK+aJ%E{ z=8A~t_UWrXWyKB(qyWJ3d3pE4#k049M>2_rTOa&RYDB@6mBF> z?3*U#GB}iRIqA{flt!t=a{tXLeW|TEOni%h)~Jb-8T>TUHeezu_(JB=K0;d7yJLNeDkw;U+>Y%3N3p_1CJ?J z*Q(^XU2S4KYPaydry;W8oBZ8zRuu&gV`Xsv1ex>u0)3zFEv!BH>G%4@B~=Ofnjj_fI36+X30LZQb-(kbet_;LTRUHig}%}Y<6{bxy92*H>6vR-usPP3T;kKd^5E}D@k*h=v3`$S796{1t?N^utkQgTq*Avk^ooJ* zc*P~IP6nh<-L6UQvm#?Wqi~}TdqbZH-4*iJ)EgwuS*9MgI<|}HS*=kp>sP(yE8$YH zC5{2}UCwOzJ!_uMg5|SUs|Q;i`-9meyk2P{V{j^}z%pcM!>S&SwJ8Rz))Ty{M?yPw z9!y&namMiAgS%0dQ?I?&IMMz0kMfjwv!5ffr>-Uslzit7?Jo}8H`ljDF5aK1&>nXe zZ2YF|VDt3+*B`gDM{e1J4!?6`=WT(XAp3ThP za}5*^4eUH4duhC8@cP8~fCEFJ@3eykUiN)pZr6*u8hx!}?^mJPoTcW&vrb7`*mdXG zhAJe@Iw9w3AMc{!^kBApOZh(At9JdX^36qJl2qdkhZI{s{OuOxFwbaHxm1T|_#>An2syrbk`V#}(#>iFcIg+*Y6O zF6(&zy4bSUT!loYl}Xm+W#4Rd>Se9NOibRU?RII}Gnw;fw~2<(SHdHETo)}Hf81?y z>*FS4na$ZMR_iJq7QV~)_%g-W>aKa+)V~YPzI~w+b?5ef!QSTfGeO1dNAspSW)+Fa zN87YTy+0*7b>>E(dWzY+s;*EW;?9ZVH)_lZLo`;{By(&oxIe$()@*%G&*%6;PL<1d zCq1u2ADZzRf9avad1QP%x#XyudirXMZ(S!PY}2Q^J)7;?*t0+))3|}Hv8Y^_c&@5h z7co)I^@igD;-qq8M@5uT&uYxV?`Dgo!q4kNIdX5$JCK*Q+*&aupO7f{@^K(-LyvoZ zXp^UAcVop}%ZHYEmg!LvS*^11r^$RB`STxET(?|vq7T=|vTUy0IAhMtM;n7e#ufC` zCB8EqA#`rquh3|iThJ8Pv-H!p8zpc4+woq*KA#hqc|m)ntIEocx)qzn3Q}t%8cUa# z-YO0JBzh|@$UVZPR$jy*$n>LKigfk3i}iCYW0aO?MejJ0oz3!aHqVr+UOcN+!_}wK z*y`LXb8|&@P*dnVr|n2ioTlT{n)OMt<~CpZ=U%Ea^};%NcDcB z3RUUby`i!ng5OwM<@xO?>6+7RM1EJipFd#+XP)Z#9hr8beotb87Uo&bd%Lr$UUGOgIKZ|_QukM>YQY4hP_O`wv<7)cdRknHf>+p#cgHLm{w4-F5;@2mfh)yp28b~xb zU945#X~@wtOt|!4cbp9K5OcsPM!VDfaoW3OXBW=bwEp9?M0@h_t4FOTsLZ@K@OSRs z>ncm-=5WKe6qd`LJ(Yed@brm}GLg+T&*sQ@2OT_p!_)tKY@uJ<8j-pCU*7pPwO?!FPF=eaZn5-%UTTTjro@nz zKR4D!?Gry;q?@I6)Y$FG$3+DS)of>$?VVSXKb%jzsFxmaHKRuN)*SKqlf=w4Vx99U zL#iEGpT#Yes0%m(rhIE^JDu^rref__O|fg;YnGY|CuLL;!i!oOtq%4DH#wvoUeJ3= zFXwVzcy+?1kl%Luc50n@VkGauyo62C+rc!cUsGM`TjG`E=6_YfCO??9yxg;Md{a-L ztn|&aPe0a$M8!<9*^$&O9&oYXaMs?i#h)W;rmtD!B(wdd=Q7`!hwm)8$Ej6%`5}Cn zdF+uE%>b?<_ln_%XbtnA(A%4wNY8Z@Tkde{GCYN@eO9!T)-h|HQ+59I-IKkGwUt-c zURbauZ^twb+x4PPoD*VPpXH|{c34MB?@bk!iP3M(0EKA|QAgajUOaTgJNTXH-JOqv zT@*dWOYY<5JoP9jrrrWI@9$oUT^xA1SR!bHOmmV@yUsX~^ABnkZj{1Gk57vQPEUEW&S zBU3ppszx7$D+aenq%CfLS5;>FySrttn#Z=o7AMx$jdKd0vO47S!t=IH$w?W36C*T# zG|v)Nzk2!87pL!c7PKGqKQbxgj1E{FHKdnubCGzSuVlUZYKyCHW*GNcK7Vzj(afn= zZE{a$wz126=MUG8C+mQn*4m|~VU~V+e$>;4bI=_d|EP4SeotY1q46ar&*Nd3)=3CmV}DO*RMS|EOqhT=l0q|8=oZnFCvYNK(2| zWsq!JIq>E8xh_+;q8F8gra#AdUraCDQ%!hi*4{dBB=zl~;ls{a`cul6cCVS|kp5AY z@M3OYuAgDjEbH^;@7JH{d11w2P1iGIoA)?xYhJ$XeOXYz)9338m(DL-`aQm3MVpF` z!d#hOlXOfDR9054h};v!D|=Qp$W*axo8l>L3yiQE6%l>6xF z=7rQ0Z|^wh(_c1{+h{no(?8*?tY}DQp8oHl>xa$!jJFnchj}*2ShVbxXf5R@2c;&u+Rgy<|q=_Ko+m z4&C`GZ@Q)U%UT`9XOeL_^^Jbsx!xs19WR7z?1rvQ92D-5FLbl97MAIEJb&D3^+xMB zhrp7r6Egek?Cs4xH=X;~725hsHFv1vi{0*V>%MxaNc%s`f1DpKq-9Q~HWy9W&F!;X zQ1?DYW|Gha=P0XhexCp9EG|uodM(vxw(n1upOTg~=)GvS{c6_6=2@QtO-pwr z+Fo3FPU)|qxtnotge1qfuBH6WgNAYT&ie=I7Z0SL`xB-q^TV4M`L@T)Ag89!f4t4Y!}aui8?-ApN5Ly{6Q8CasyN zA^rDpQJYUc4$t{JJ9^{LTg)?v8M^DnEu|A5W@pdr`ulYD3=gHEKgFh6QP+<&ABq;A zQB%KE=o+@O$F$~i<^R5S2n{C`H;w=eh1K%du0XHNTiF<93gTNTl7ulXwq6d425$i8 z4Uk0=V^R4Y_32!-^slW<6qAcBhNMow=>!vyM5H&ry;P@cOJ%aLJs3r*!Lb@#6iG~2 zjG=Z0gaZ%_NW;njcGJ;85iYh7nyUw#dN3YIWbWlz<)McoG?#8MohWY7;Idg3X7(QV!|AtbsB_@&SAIF1g+?aLb4**3djt`sjnE40>k?oYw_ap zrf>3W%y)Fikeo(fX@n>yEJ5lV0%4=(=IwmH{FC=&Wj3~pPb+0&rA%o|SVlw_(YWoz zPj~#83LD!24W%%!6b7{@JPFrW0WnRcwXfb~IG`qq&4J7cKvV!JB;oi>TzM1eAh*Yz zpSxIH1ha?4-+=mZkrbFnrR&2L59}+nxmW~%3*84eeQ=?95-qffl41bU*I18>ZGxoJ zxaw)#07*nzHNndFXsxUf7YiOW)ekuR&=gN1mf}gLBg}xZX(HI7(YfLv1^QFUsDuMk z;_aDtZq%vkD~6_VF-O>C2jFx71tgKN^M0;c8iU&{xY#sE3d1GBaLUbj5|M-|FWOJl z-Q>W<>>%kZu6h>NMG}#o_ZAs>KHR^Wi&;TZ3*fW>IV2IuWl8FflM5=>aIsmC^c`@% zLlRFS(qc7Xbw>L1bzIB=lHzdHIJj0kiAZHdn7ORzO=mW?8?M4Ifek~C~p? z)$8@Aw~Wgk+`z{CAhVgknhDAyc@h)m;!_aQE+bTjz z&hoZY7DZYKNuL1c6PyB1B9dQ!#_CSd?VH({8|IBN z%odtU!c~)SeI${&-Hgizu52TGMKKp>t_l!UKpe?YU!E^*3dbeFaiwU$lgQTE zch9rMD^~7dW82`!YDuh?q@si;;lVIDmOdClKI$Gi^XA8SF(kG3JPGYhLiV(coTtlXT12riZ~jJ95?CcX z1H}n-bY!jVQJtO8yegWG(IFr)1g|2VM7`d$Aq((JtI4))l*RC0GnxUWbBhrDFIha zfbPMQh~)on>(__1202`8HYADEp!=s)LDBsBm|1N01@M5Ki)q}}Ix_Y|?Qy>PLr7+4j9a&Df)ghiP~Xt5-u3@!ic z9xCEu2cfxPATbQ6Sm8-z?vK&@POU4$#awJDB*o*Z@oVBY}e8+0(9M5Me;e%)YrSq&Fk4N0E?=QG?zo~EN!%0EuK-!!_*4uL@*0D$sd6FQmfCC0(Wa$R!XA!laVJP*aFBq zj8k9g=;lcQUe1-dhpnvtJZED;keAQE@)=af@g&?RW7Ko^gwCej6ZW^Tu>iF4x}J65qX@PZTKfX1FXc!)DX?}ni9ZXU_UU$VF(){* zCctTeo6nQTSl>FeRmPpuzi_ctkn|C7K0*>tBGR|~bx&64HFtBdd5{!?tH$7lNFtKD zTHpl-d`ce&Tgdm2G+ZGK*BTwuVGuIK!C!359j-(>jtb#vd=HUJ4>WO=B3RF=q0g+tk`H zjIJ|gpa4Y43G9ZKnFzE!jdM=p6VXc;bLR0!{Ez7o?#~#NeD5TnYK4kJM7R6YIjnpouepb!Kc4QECGD{tl;psUc^QsC$B8(Rh)bfIapUR);%RHXtSL35=YV()*l6MuP!EWD zz(xyB0S$m?0Bm$QQNRm8yZ~(Uj-h}?Kr{k2dZ|)C6Cj!Z8$~e%Gy|d;u+jBR0WE-N z0c`X>r+_zrcmvod!=->WK(qlix~D0i9T4q+joh39IsnlD*eIo-fRBLq2-xUcpny++ z_ypMKbxZ-D0r45I(X~MVoq*^BY?L!oz&AjA18j8rP{4OUd6srC1cu z4~TxiMu`#y3;<#Pu+htm0)7GF7ht2{qkywGaTaHz9EJkoa3T(8qb!30;&CD#XQS(x z0upc{0cWEp2?gZfL=MhIrws+v;OaHFE{ZA&XvZhD<9hs~2EO&xdvRUl!W82uL-Qy@ zpMSr@>{K&_p)U|i`3&`ZhAxUFs!0_?t%{+;e}=$&O0kWhfg+V+q!H?Agf2gsjt1um zvGauNKY;3aLi-=U;5;#10H`F?D+yixW0dNa5UV0&{{hsh2%Ucbqbg#i0MJZmG!s+M zX+sUHli+p|(kQqnV3<%JCUp5}TQoRDa!--c{MRykgigvJ_4qH;Xi!3OOGs({`<#jw zlBg%y{G5Y|7m{fB2k0WTyGTR+Glc4v)Ey>``6&;z>P)E=rXv4-fq+&Db1DMRx&UE* zJ%Wzysv_q{>wn2kgvUWRV1)w-6!fS_0o%~U30j3V7q+2`5wynUe9^<}F)ga_lyzh| z${<_RN)3UjLx6f1@jes~hEEN{`2eb5z{7`Ez7U`WlhVPYCR$}w!w{mVyaI**bqEkc zKpZ6(qumf;xHzf^P(U_LWaHxK?Lq<9aN-&+jvm+)P{!0PV@^l&r-0W?z1Pf{C>c3* zdu6}86sZZP@6Gb&AKWOQAx_sx=z*cz0ZxurBoP>K7opNcOhrD04gqL{u8`1NR3U*z z=&}f{p+=a7bJFk$=o#{P?ZzL^0yS7bkGE^a`MkO47&&`G!DacwP7U-~@* zYW!LL`~ltK^qacQO`pxCrf`J8J;LB?C?J`^P5uW+C4^E55!4%;HDR1amcU~XrqiNQ^uSiV55v_S;nN^s=N=?ODj{T^`9oMnR2h0iUN$+OzYRo zc?dwh1}96GoM_dn1s`Sv?%r<+HKzgV^w`}Sa?|BtlFm$PsEGrtxG{~G-IqE0cb}XG zH3wJ+_zRRJ8+~W*+7q@AKMYuh#}?bc$TfE|bIu~D*}~ca{}s>Z2VE8r=T*Cq=Gwck zJ~MUG)hueZ!+;nDY?S&@zz85l02{r|DIgpt!f`e#q)j-Cc2(S)~tpmDo;bBDA;%Fa}_WoA+-#ClyP@}`rq5h>8?{mku-r$qNZ!d`ZvV8e& zN2=!E3BP!22gH3?KK#QE74zU=c$GY4iCWtGk4S+@>04rk5HBm(n zYIx;9)N$90ID;DX1EEk83s|vZ2LXz&QEQ`xLDU94q~Vb0D&W|V-r~A%aU=AEL(dLq zgsuhB)RZ3+zPnF4egtZ=0V{j#SVzxLsG*C3bQ=^cP(xP&X$^Wr!QG&Xf3)Vx$T3m> z15b{_Hl8d`z5}5v8{%{kkZytQU1*Cg{?Qurs)B9kVjr!^kW}xElxCcPnjNei{9aH3 z0hfv{`q3?@-K!^O)sG!4DA$1|=+Yle^_)~z_2K^KOHdQQ3gE{^g#4212i}S4B!w?$ zEtjR~7-hN}5Zz$B0B{Z`&f$W<1)R9>4-m{Gf~mp){XuCA?31oB(wZf68t zR@PSjRMA5p;&j20Zjs=cI!@tpUN+QhV{PNNK!r#+eqI$4^-j$ogp>~Uu(%4;RwwzGd! zTpzWzi?xg23%ZnH3%YQ-VdaC(RS@6L+Rw*P$_sBf zy2?sh8g-5-S)|!N&S6|eS|H~@2{p7y7hmbN&tB#nx9Pf212wx@yZODLYzUqTbTO80 zf$FeuyXfNU*f`GMoHMvG@^n;+g;cu!Iz~;xi6mSSU7cD7Vov7z$UKGP2m!2+vE7KP zaqpa*zxo+YO*5Dzg2{2T4H)>DB#}7=pez{nN7r%3`g_YD-i}?_?a52XJ+r#&VSjoZ3^ef_T#hhz|_&(M?K8`#P;&kDcHvKztil|*-Z7bCHvHbWgP%T)N!g+;YfpOR1 zVl}utiVSKZ?YKlcu7K_l3h2efdU1L52%&(Z49TMmMdX_lkiw8mVJM<(kpl7=V)+bt zvharjXOA1IM#L@_Pl+aQ@B_UQx$fFB~0-6c& zW?}-mgel+)A@+rkN0|);3=?9*guK967DI}~kn#d&Sq3SQK`IEiYbhyFN-7|CrEJua zqP3(PdM8jo7b)FEDkHaqy^ylQq$+xsP(U(MDw(N-a&ihNWy+K?RRj{vmrS{rOf_`j zq1Q0nIJ)vq?-0sfp@uHE(;8H6haN`P*l7*bUnVJ?Not~5p(i~wLRZ;oDyp(WBXntf z%t$QGiNzr%B zqLmO6h|4ZQq>GRdh|3U?2qDD;;xd*Li6vzO;xdaQvPd!H!PH#JNRcv9Mj$Th$?^51 z@;?hRzF`bN(Fd;$`cE(P!sHyy3r?9?bJ5G#m(#}Pf{1FM@|9PJ%f!`+ue#Z#>J~j3mj|N}mW}AH!E`Q28 c1!BN4a2%WfQ6LgfjZcj6uww$hkB|NSKlD^ho&W#< literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/linkage.h.13BB6EDDE8E2FF5F.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/linkage.h.13BB6EDDE8E2FF5F.idx new file mode 100644 index 0000000000000000000000000000000000000000..cc11af7881d1fc71df9e507d2b0f12c226737159 GIT binary patch literal 334 zcmWIYbaQiKWMFVk@vO*AElFfyU|dY%$y`NaU1OCE`)0R$?YQ&s?9G~Y;_|x1mAOekD;SDW(~1`Y>4o#xEPoN`md(h; zXvtwI4Uz(Zy6wSkt3Rfc0EJyRT=*b@3=AyF^R*;-!h{{Ssn0Q*y=V(i*qOr_ZiwygIXY>xIvxUrjW~=%V5%P<%YC~{m+v)DSeHW= fE(~;OP9jK6aZz$HH;`sx6lj!Z|2IecJp%&(3W;4z literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/mcbsp.h.61C109C74F5CFF8C.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/mcbsp.h.61C109C74F5CFF8C.idx new file mode 100644 index 0000000000000000000000000000000000000000..6bd2d4bd55b8bced2c51ef9881422f25cde1604a GIT binary patch literal 42164 zcmY&g2Rzl^`~Tc~KgQ*9?Y*}$QYcAUD$x*9NRmpSGLjOKm09+zlvT1Nk-bBiNmj^6 z$ll@q8TWI4-+!-fuXnG{dEe(e&vVvu&Uw!FtoG5P=}7=^*izfs_NwD$5C8yn=&ysL z{f*<20FbYN1DxZhG%h;y>LEd)Ys^VFY<;A5 zqPFbP+FQ-W__D9_25V*vH9Jm^UjHm{=i2bg+Gno?>Gz)7A15}>7J1jR-hCg#d{fL! zStPEkSp2?p(ifZ)u<5Nu*3rT(UVY|vs?E#jND zg*sp8{woBT(~GR0F7yd#Yku`qzS!h&^!OXM-N%wXD@y;ddC0A()4roP$c22L<@!T& zg~UOhsEu8k;u*kkKQ>8MqGeV67FW2P-*D}lUVTHKyoDv_`$|$)#VQH2=L9?Y_tNGU z{7G0kC*08=3;omQ;8ezyGcJy2>f9{FtP1y=g*})#r%$%%T({;6^qesPN_y!58%Bae?(br}Ryy+@X8F`o9ee+C!yb0Md*Ss-Vu682x$_JBo?=rH_ zy~9}tHby*3PRTy>?YC}ac z@vhw+9^b#x-=%N5W}#vr{wteH>$&!M&xCH4behbaTWKB{M=!~D>C=UND}P6D89I=* zYn1P>qS~`@&!z3xr|+AwPTaX}G&K`BAZsw?K3`Q| z=7-mz<8R!n?caB78^2KH9p&ZiZ-ZUD4qA4%}aQmxVXjhr}4z$zVo6J=f?K=c`{ifu?$aFYAM_{ zDX)-t;ZqP`z~gy}>j=(v2T%J~W$l-l!Fv?d!Y%LEn>*x7EjgUnK1k2fBB1qIU6-8fDS{G`G8&}utAd>q^VC`C=3*80sZp1|IT*4eD*^Yi`Yd;UDX7ff5CAj?*r z(EQ|PfLO3dkG=T2z@eUpz81e14clVnvZ-ScTO{@(gnYT|sr{EJ=0UE4x;DsBUg zdJeY!PMT)cV3!G2R~Qz)tP@S-_OMU69IHgQ5GtW_(J1lY*e+J{X4aL={v(^N?0eO( zcAX+RU6G7#7Sk-HXFPGqaz)GMD(}~5FqHG}Ozw2ko!fjh)`q;DyFb|#{%vCKRj!`m z7?nPvFYo7|8ThK1_$->1RsTT4^(EUyjf)GrvJY|1v)%Af{d>Xt5Nv0fA_$Dp(8fSv$2YwK2bz}fYf>+L;7 zlZA=R+_&y63{37NfBpIV=_k6WKF{S(QyYCtpZcm)kA;0Xd}_zm;^iLOQ(kgUVzm8i z#fPdc65J+-H>bUgbMuEzUM?~-BkjHQbA6}%`eB}~lD{{yh>Vsk>=q{+&PPoBmF@Xg zvvBK(TGR?Z^8E0?( zY3BGX@AtOfT$x$hx?2pw3c2ofcpc8Xz<4WrXF~DUCnA0tkrD69byYt$eq_256+3$3 z;MmKxQPS&V{@u9|&`{o@4T%UeFS$uDy&rgI-M}*w%=B{ndw8e$j`PHOS!?=YUykg$ zG2gxKq^qcTXO-ZY_9nVz2n)!=!zOCO@~_ z9lc!KNGja-md%7?cTs4C6%X;CACPk@?ShP~x#N@=_&nIlI&193y*JW9UvF|7{k02{ ztbVjUcFjE5cp1l2`)Bl9sDz-EGLM-M+0EJ@hxjiLU~f-%&+K4+tMF9Dg)l!BuluSp zQ$ntmE&g-l&l66G#Pg~GckQzn?bmbsx~&sB?{l6KtfVs?6T7$lqHw!%3}<;3|NBMR zcdqQ|xxMZeJ}PeH$=vD9mo&B+9ouel{6xz&eH8^(^Y6p<;dhg_MV+K0?n<+<;A{3& zCVP?$A2ufadYRkvhV}Y|BK3%XdpYml@H}V}+pl`SB7fEOu`fr{w@}mT%s+Gt=}Ldf zv;aA(x_irc&Xp#(|7!BT?`5EK{%*@=!lCz3K6_T=rg`_-mOVOGLVF~3_tA6bV^3c# z2(41N6+L3kSa4#o+Gx;#RqmzC*p+ZvCv`L5Onr|Vi5pV#9p=ojdT$PL_UvDve^k6E zeyw(MJgfh=u+iZx_d`;Fo8~*#reC~fuzw~*pYupk#`uE*` z+c#e6a#*jX$Mf18$;J1oPX{ZUI(p2!L5}P?Rp$d&^jruFv8x z>|qqw9KkIIhyJIUc?!cj*dOTILV7Zy}B^&W}VstG8qcVWA6g z+$nJ&Czsdsq1j_vcArb1C-a%oc2wWp*0YkbU0(UX#*g^=aa$I;w=c6;2EV-OAUFb- z(%89Od>(LSL}}mhWdOnR6=(ZDZKMf=Z+DU2wxkBcZx$Mn#Z`Cz4xS}wc-20UZj{K$ zmHt@mLwi@K_rO1ypDWQxNo5xF74MbpwtI#AuuV70i>OiPAW!Lm)u9%K278#&>bEt9 znXxa@T6s)dYiD0H)FZMobd^YZC5eV`bm=SlmYYnrut`}RXZdxlfvNA{+j5B?Nqi@N zTRyv%VY$yN$*2BdqFVdT(_G@oU|mh=|~U?2HO-6W;p`D-leU za;c!{2|>27l+;ae^Usx<_y~(GmW(7&u0u;;^QV}MuuI7OQ{3-wf3&kuJKlar<)+4$ z?Cr+#Jfd#BxqCnHIlBf|tUpvLn*3-c?D>yB<2vVx&|eyQ(!;En_j#w+4u}!@=ClPg zxUTa)DzHooWV^FGSf3Dg9j6<`Ap6EYndV$$64f^Y^-qDJc zfj?p`awX53>s7#OrSZwYOg~HV z4qaKxi+6e_?z&tQT~DH)Fx-g`@KhlG5{b4<;B9j5_U;JUyGJKy<#x)i+Ru|xfj2nH z-#dLSck?cG`eUtO?4EIK)OdYtYm&5fkw*!w^=gXA_JjeGaePpXpzt}0PcCF&J zQr^krDN)O!leYctQd(^@OA7Zk?}dyEDoeCE`J_sT?Wy%~IqMGIc-@l~DLB3}_whBB z;T^YB4+x4J;~BL4lU^X0SI^<>vB$HBfd z^_ZJg9&{gKvWHGFRDi4D-J$QhUn{KqdDF#XUVO)=Bk9g(<1)Jg(GCr}X{uH68dAw= zswOM-{H|g6kbxz_hq%7YoYu!X#6^Gp$a>-3R=50DK{}6bN?Vvc-iTcPk-zm)XnI-2ieqkUqny>f zf0?|pesE}`lIK_DgO8FjFOSQ;CKf5DM++LHW#!O|$auIF@Km)C>p7bbsH)MdvVHHO zUrP0}PN!#I;4qR}wRd^`H%dz4!S)(@n&+B`aEZDYNu*vi9j8O9HJQ?jDeZfzVVS2^#%Dd1#E{?y9hxmh7wRfyX00soLqg#f^@ba@jaPXd0YLi2j|a29Jk%~UYn1wt$n^2eewrCMx!&IIw0pLC%>_dJ zDp?h~GG1Ot-e!JqxTsH&zfqZ0Y$eci`*)npr+)Jf6%T@&uU!s|WcNA6z3rv%m(1d4 z96Y>MA>{+rp@uH+d)(Mik!@)15bqw9+0&d|=hYq=@`Yt<_(zGUqNcBsZ{%He}UCr5w<_ipU zCFdubqYT0_Rva&9l-CaDOUC6Z&UOD=emLjPx;K0EN6F~rUlY#*tZ0;F1h>8FDe=<# z$7krIv_9H>Foun7^mxcc>#^jL7eT{uLh+ZJC%=z`=1pY$s<@r{QQCgzzKEMgg#l^C zl1-2%tUv74r@~^clxi_%p;2c-uDr;=g-DH{w5zu(KXe#v-yQmM&gLVlT){qk39D(U zUb-RUgL_kq4@$E>txl{y_^Z*F68g0~s9)b=pXI%pthLe1AVb;({>G%c#at#|QsrB$ znhR=bFXU^e+XP;1{#a3a|AW@Lb;(&P8P^JX8qZI4A1$j3J&ISuko9B`r_wGag#$U?w;vi+a;Vg@$nsbm-*UoL1*0t_e5Un!|glX4sNBskAvV+YzUWb!pbWfW3>DK>=V7GfcKz7Gh zR|PPhw-(JZR?B#vzF-`)W_nQ~z5lx4#!dNmOs+=4Yj>-fzxlcAk;yXq*pFW*X|9ZB>!V$Vdth=~T2?RPmiHkXZA%{oza!7^Nig@o16JigLdP$l<%0>vubo{^ln^@GGBc(NBs1SMV8V0x3QNB!?D{| ziGj=X>Nv%l9kn4J&#{`h$l0!xb50GP^y4P62YuFV>a?df&xcAQF&k?5!*#$fg+_HUM+#L84#%0oUrb2wdKg533`g#|C zh3CnSZw4d%;)yAYU*x8gPF5*5&enc^bbRv2wc9!>dY0C)rDx@oo|`c!%75taP2V3X zI?t@oHgK2_NV$E`FBtQH5XJnXNl?nslk zK{rMIy8UC&dXU46@i^P@>LJaL+VhPW?20FTsmn4s>Fsvx#|H~%>*$4F(M{IZRZJVw zGRzh>;OuhD8MBO`?nkb{vtMxg-K=^=lw98}aW~oR+qNhmy3EAI^pK|R z{)~p%zVGw*Ry3WzFK5i(lxttTloS`>`KWE4<%BFx<8PI2_dRMqdN-q-Ovf9omj}I~ z+x+FyOLM?zO~R1zg##z7o{AZGcdE7qteLRlYNSt(3|Ky~m`T&+ax8h`7ugb~CDqWh zVkdBU&tYDU;J(zn9n1|aSt7Xa;zfm+QKzC`%9bxR&375d_OFEP(`Ym<=_XN=Ng^9vrYXGQl}yw zD@MrQc%1ejhbdm`$knVw`P|f?#a+xT39Wgo9cD9w5{t@#_rniOWu3eA$K5nn)#zzc zPQFZ|*6#jfZGmf!UJPH#Le~!TevyA>F?ykZDE2vRCvGrjsH{E4n@9BOgF?x(Ut6#9 zH|W{4j5g3{s)~JmpMC6$k;;*piEpElQpFz|w&#{G_(`;?v!^(pX|UW|u~0r_BrQMV z5fHojl}XDZf1CBeDxK~R#e||W@An0sJR;&9VSb2kZ7`>I<09SV?z7^mKW8QDE^{!g z&s&aY8FbFLNa-p0PBi^!FSS~BXN zVtjG%os^8X6>x`4t2TCMcZ_bsQag{Y_r$;(-6m*v-;?p&wol?BBo90>imW z3&L5e8aHFepI&9xY~K###)jm5__zUI{_w;p+JDGjG%FE`pL_mmYQ&>UpkSi%9;o0e6RNpOGKm*d*_Z+@dEOwy64kpiJHT9ZAbVv0dx%i>AAVPlTE}JM#;U9pT;3 zy!uVJ{({N(JGop5zY029e~G!Sul2|;Jj{{m*v)V!VY_;|NfWKB=G40fpyRr+g4trL zad3%HT8v58!}~sE!*yI8^0?mJIg#xCmFF$^4QsKRD?UbJ<$X6k$%)wH-h25(L1Wu( zzE@s6jU4>Ve>z(u@6@iVrJih_bkU2V=^1ltJujl`-oM)L=nfMN!}yup56{%H&;FTn z#s@f@Xoxzm@1UW+ZbDk};`hNBj&T`_m2^Xe#X=Ux|){ODT_gC9a8{TyVe>+hOL@lRCoiXf;&6V`w3f}0rnb}HzKiuc{GbDs>m#2% z)!1|@*SCBl$=J$O56vJ}<17u|Ea`XRd#n$zyfQgBGP)SBnByyKXTD2}Sjak%#rti9 z`Tlr2e+w&SQ{4dcS#!KSZQ#chTAJ+50twtsO zlHK>aZZ(gs8oy?Rlhrps23JLI*5MM}CF6u-%kF}pVUGngmMD@|L#?FR=&xKEp+ls|+MGm>B>#EIJXXl+;eH|p2 zlf`(tNdLBC&eF(&MC9Oa@$Dx*q=)JJNZ4!Xy!68FT&10G!j(Ih&os;n%}iC=(@q_u znKF0QKDuMzal3MT2-md5;TOL*J^uNh9wi0)WXR^6T&W3#jvjIg4%2PteYrz1o6*xZ zvH$*bi<`Z}mB- z(Y?$3qROe4IdF}pdigiK_0NJN;qz@hkqd`)*3@;@6eAawBNxc~E|&P6*5)*t$uZ!* zkaWkPOH-p@jLq!QjH%~CtF+`f`Ow#aU*aJ6`^zrTmPc78pd zaNtUl&{FUIx1^3JwM+Xl4K4XIWDkF^Ov*9csq*{E)g#iu{&*{uV1@Ouv%Fc%er7;a z^UhGkBZ(|I>OOytU%sdm?dT)L9--*WarLHUr5pbNy>h2}26u_iSsIg1p7l79GnZD= z@Q#aLCGKHi$*E-?M4-YN2f{&PTWQ>KHKNvX!sg+1{w1 zD0Ja9+nGyApBXh(B988RqMW3A%}>;zBtB78t-_U)Gl0uov@M^jLF7dFyAGj|9SL~x zmtp$5diC{Pv~#Z?Un1!)1nMduj*7OTuh=$bb-Y3MJ?-q9RY|F+*KZiZR~WK8LNv~A z*57|2d0M^c;wc5@`G|S2!9G&=?TdE{pG5T?OJ0n{_$_REvM_n%fs~lEV@R*-N75C6 zsheve+M~NmMLd%IE7GLj?VF}mbKN?jC{<+gMdU0~w&h}a%HbqvbH7{>|95=++MHuZ z_Or2w`a~CDNv>8)4+kL2dHV&vc`GqZ$waA}9P=GFAK#bVRU&yS*Rq(Yd2xOq{HJ&7 zu#R2C&7ywd&D>N;etv`RgyQi2gt@nsVpXmQirNifM5!xGRlUvJ7eXdubXF)J8fs%0k+htD;N$8+b5KRN5h zOXEZSy+&eZ^mYW<|Zp$qA2YuqTNw;{Q1)XrH;_o z!)~{I)4#WP9Jn3u{Lb`g#uCkB(;untf4vrdT>FLgVk^NpB zk2h@TREu9#_cNz!%e%4Fr_D*X>^`UMdgbp2R)siGci#@y&F7-7Pamrt@_Cwf;aTcn z7pvB?)4oniN9Fp=9g@c`dr52J@(Uac?N$3EwBPUA?2z8-d$v_NwZr1+AeX7dh5DD( zuggc&ZZ$t)l@HDQCSmZ<#;euA;E02gcTHKVfd9W9!SRHMbrJX3y*2UPmtF*#7#gx` zX@&%o_LsP>e<1WJ*UBom#QEN?o7&jeD5#s6zOKo1bZR+q!*#8!AdKT$w@mSUbzAp+ z|7LcCoRzBhGUPOUYs$IG`QOrCw<8j}T=q}q&7M?sKe|w1GpZ@R`Oi*hANgLF?i}f( zTBDYrOd_j^PdS}`*~2Y*iBP2k=@1VQ+T86MOydc=nD1nwcgttZCyt-8it>LyB4#76 zrNS1f(yag2UdW604ME=9;DsJPZBN9P!)sfX=eN_INXb;3iIem6s!aI#yL@|W4EP}u7YPE31esX^ikQS@*;paR z3+=RIAQRDX5DyOG#b*g9!a9BB+z|M5r$g^u>wH5>SMN&f~sOgz6GI-D-9YLfj7sw-N_d;v{AXD8k%7 zR448Jd!h914ju+(V2%JgDIOGv2W2tDOv-wBJ9+!tOa>B=h&ZW@0cd03oh6_M5O>g+ zVm|T+9P17KbcjR-a*)as2w(z1a+ZK1TzLbbpQ7lu>+f~f-+M8UfJ{W}It#GQ!Zk}k z5g=;unP6fWuBvTV*?lCFfQbJ&s*)3^xlzB zaiX&X6k#2j30T8MyVlCg&Yj~T16~Ms76;Dagk}jS!rUK(YKm`fln^{*Xy7>>U(g=2xnB6lu7w9um7GL;{8p?jS8NNXrk6 zI|N~`U%-0P2~gjN@!3Za5)gwl<_9|910DM;0Y#V^LTw<0x|>hj@0}JU0bU4qiwJBH zxn~I|!d!Pu?8>msNL-z%C>hv-^oNEA0c;~ccA*Gs+l#BAw9ol_f9JLzlon$Kd=XF0 z5{R<|NLv)Cp7K?6dZ~CuiVUP8HYMZ0WO%+q5tcZCYo|!`pS#L@w*I0t3HS|hDRW66 z4-m-12M{&bEHN$36#ouiITQi$;t_-9Xn;8yXoR2$5EVgljLQ6JDOb=%QkDcfN2oJ& zzziKkMG+wGqQ8t$ox4WLj6X5Uk$`1H(@I95k`Zzfim;pPFlyEF;p_i)w8@izbVO<# z8Hghb%o0!ph^mY)sNUcEJA^xV!(M>|Y&`p1GO_2n| zBGeLkpoAV89Vo&Ygj2;zJ6mVYpFO^V1Vlkxim!$_fnj($F^~RK&CVhQUFD)NxM1K=DhsBLsgIc zubF=F0Ka(n0pecr70ev5Hve^_yNODSzz?M6SUfHk4>=S?xaJJXAo-d8&LE|89AbV( zm<2do0S+3(D8kGl3UjvK>N0DJuredijxbYkxKtc8h*5-@r4;4`u2rddeNSZ)@acaJ zdddkrrbmn4StVFpoH= z8zgpvP(z}KIp-PATbc)k{gAX2qz#MMfFd@iYoG`a)mhr8HCIeozkF{Asxkwsh{R}+ zFB;r7OF$8m*k?LhV4%aNN(PpYG1-p;`{B6;McCwTxLQgB%CXm5Y`!moxXFln5^-Q6 zJlar%xl`29#vN5M(&pO*abF?abOM+TuX8BE+y+7mMXp)#(;H@cSNAXiKN0Q>9yf!B z+>Rp5t)sY|%OiHCdOw{S3D`iGc{D&C4b+q5Wx#b)of#NIfG#Vrz4r$F%A}~sXrVkWh zYeK2kobNnzI)4AD{fs~#BKJ9ndk#WVGK#R=9EzSavn_Uye!1)?0jmfz2Aai5QnLgU zVW}=yr_;~&+sT!GK$8T#LlkJG0a|Gw$D;@k4{%yx)W1je`wt)0IDiF0IiNre90;L^ zS)W~@KYyy_4aE9|_^6-2)K7r=CyE%W?4X|C5<&1FBhZ0pSOMZHKxooH5w<0lVvDN6 z$wBk%H-|_-`2U7k2Pe?MDFlZ#PpR&S*SLB9Krr`V5>SL#lEwn0u|O502+x@>saz3* z5-SPAV~5GWCREKVAsh#W!;2=0aP_}&Rg@;O*xFfqhST^kG+QI8juCKU1h!cMiZC~e zqALI4n%He&yN@seT?jK6j|+z9BNSogTMDzCT>6{C=*kf?5QZ?z@L(A{XQBu*E2(p) z`8`o>{%5uj_dUY>iwFP0!9R*Hx0UddqU&YmZBd&veOk=G0^xzn7Hpch7F`%kf#?ONGM`@8s+J|_gV}& zMh0FZdS(#73<4A?p$O~QNS#1(^+#I=7t4-glV>PM423686fudtPv--lx{B&B1CNl9 zVhZG&0-<(C5n~mlvvY0u9@8ZQX-K{Pc+ejY)r%rr?<}s1;&J@~a3ZryTbBgPBHUOS zAeIK2JWzy(nlmu&}7YXJ z0z(n@)kjKS8e=)@@!~6kJ_(pdn9~fvGy^m#p$Oab05hN7Jxcy;K$JciScQHJ&DS_^ z5S~F%goXZ~u1Ka=mVbPB;(P+z%85l-}M<0RM zM}RsBikL|730{bK*Mqmh0unvc-gChzQVFf=^Jd|d2$)Yfq;=xifOvRmM-d=u z3%#M%eRrjxxZZDA}s=UBEW@ULcbf2yO6D#8^uc$@k0h zS1&LEji`orXnlhEa2@D^tpL74fT!VD97<>t3O z1Tm`+W)uz=1xH*c!puSnvmY?v@x4D|LIS2BCdJ(!d4P{_w0B(42I~}0SPmD-rtC0f z27V)rH$>ovR`po|ikK~AlRndh{T8MqU=yjgnGR^CgX%>Q?qzP6z;V;0zSPnPQ%0Z# zp=J_rnebi&MOejRii$gJI>KF_&YF?|e}tKb1M_f@8&O0Yg#S#L5cFV&p6+Z=bi$P6qaCN+a1%^+kFikL}rW@j@?ilZ))fJsOq z#X*_eKqeYLT4VOi#*au^g~eQA1~w6CO(1g>&nmBM@!{9;|?u zG!$WOHFZf_aD6{m;`QY^37Gz$MPa-^7_T5eJSBc707TESZuhn`=U(ZtVg!C6GFw1g z3*5<3gk=^`TIe9Jp^M59o*QJq7h!JUz%6*jKoMqsr^Z|?>22RyUa8z50k4r^w#f=? zvO-f9iU3iK`3B}v+wNi!tK$1NuytwznT0eSy3D~Ain zK@aI(QB~E!xkU3XW!sa1L`3L6Jopa|W>AEMwi2+DOmXfZ;ZEmHM>4PusRYf^IIs`y zsVKtS9_lKvsDI5OHAwv~2}na-03GTuLtIY;0pekvt5_3E&vBol)6I7x1M!FoZ8)$E z7KXvFp(-d7rR%HuuOt7Q+3B2Y=$BH486xQ{*bJ;6kb$=dx0V3b5};@W zMVR}A@P(qO@y&06Vj_NS%)lrz_y2=87=RoGh>If3 zeTX^#+-*ryWs4Aq8iY_gS%6OXJQGEj8bcKuC;0EJ%OJN03GhI;ksLrI2NW-%2y-7% z`;}Jc`kh$2oe*~dGK?}uuJ8gYywDIr=all_3_!kGAQKASt z;1_lF)7{*9B-bzNMFM<~`g<6G9!5x46yf?^F|nZng8RzzySJi6U&y758Sp_QE)bX&;OhevF^RU9iU0I)9l<2v z@Bf-+nj4trh7R3yL~Jo1_DyAdM@aUMup)nrlgIIWS$$_(-1PSfVig>54Pf=A&DaFo_<^tWk||gnLn&m z9~r_3R3m+D9*3XDLH!3sm|IO5Y*I>NN4pEZhLV6nMA3K5z&m*MLJ=Sy;k|_^5UU`^ zTs{&IK>`vG>K`)jhYSft5g_g+8Dmt5eafGC+2W!}z{>w@THpc}P@9}E-eh@Gqg~C* z7-nDzab`IvQVvHUC}Pg6wv!wmEfa`k1o{zcUK4Py;b;j(*qU03HMc~J9-fqtjwJ!9 zh>B&bKpDKrKoKDBV~wRYqyuwtt~bpki0g@PJL!Q=dMIW=5pE(cDmQTKTe}R$%~-6v zd4o*ea4?G^rsrYzr^J|h{mI&jHlK zGa-twmprI))3-OS9@JY;!iGi$$d>^R4HPk}7zBqNBse`tCIOLpdaykG00R5dmcqh$L&`yH-heI5NiNojS%=o2y)Op6@nORkS9@K z$2;M-WFQu)wH6Q7!hS>%uJtq3k7gO65k9YXzGVhB5Q!xqa|s+Fqligtp{tR=?Fo5H z0-hiy=Rr{o30g`~giZFQx~DEAMtLBH=^YseL~0KwfZ=eok0M+lxbBNp_& z19{%TK`)9JOEcl4Bf#WZ#0>mFWMzRoSuhJlj0Md6dz!O&x|kVwf-Dg}pnwku-3OzH zv6xI8eo6b+7L$Q!#D;1-SPi!!im(lJ)HY;28J>#I4J{!70Z8jKkbwqx0z?sRooH$V zAsR73`>{`U=!y0 zxK({fMQ8;XSc4h?+JWN0A$W~M5f2W092p?x8WSgUTv9(B-jKVC-yJ|b27vH-p;P`HC49PT`)n*Lha z=7W0|sUEwjNC)}S;aLksOyV13A^c!51Z6*Wxhyp2iFa=fsMObJHltY2; zo$dE!hSZlSwJ-zY$oPx}d1FCnqk$sk(PP8OXX+kXwUK~mq>TdTfdG2QQz*jLhf!;1 z)tBOl536Wn1Zt7mf8lVy;CKc_xb}CH{&Ab>@vE`^3ms(O5yG6qfpc(JiXzPHrAFCD zZp+!6jZ9Emp$KbxA8RY2 zzqm*0s~38(h&%#hihv_>6fyJ1t5_EUxVU@Cz&k`>ARY{aD@PHoyabP(^gf^WPy5Ys zwwDBqAlw`xkVAwfDHP$#&tsLVeEAUUCt=&m42&SYA0Y4yz?(4?vC8>XZT|kqZ--c3 z$lSP05LzZc`3ERstc}>(4drX1ePkd2sdfMl4&b3x5JgzUQasj?B%aZ`^RDfNxc`t& z7ls4F;E4%Em^(z>4jANlKPs)g+fN2U5xIGIFc0oaD8k$>0v6Y>yq?3AI+j4(aD-cq z2g~948AX^|MV+7fa9=ApUJOIrB!v4K2fl_=Yfyx_f2cQv87wwCZqmvRVaM_PAYVUx z9FHRA0qecYoH?GihDpFUB#|;a%6Wlu__Roq<2rV00jXVP;?p@p?8Wlnvic zp@>P_GI{5ppZ{Ql1eE-5u;p?Bx$w2E;kG7fcW=2ow|7Y)V2l~?Mw(}dAhASHnkAr! zi7R&K-H-@#{Y?hE5py?i;0Ek+6k&5KpmS7oNbV9TFXCd^g1DXtx0L|4!XY$@F!u)m zOMWo;Ejs#lg%%3yQxNVe9QX>}sGN$*47^0RZFsN^4pC8rxore& zQzE!F-1fqGeu5DgM7VG8xHoucQbrNx)>8(tI75KhQrW@;Gq8xb^DD^n6`qn&#O!}Q zaP0cbb-qb5@CK1rO#rLmB^E_kUK903*7ge0_lglp#7a zumcV7CIUrxL1>}&(Q^g6B3~t%Es}shgu6uxY{935D8l+iQT4UG>(&k6-!3u&-H5(J zcqnrVl8Yj&LnXxv(Q>4Cu7%VkZ0X1Zc{Aaq14XO_w2cqE;X8m|CIc~uyc#@M15XMl z!t&~=lfwAjQ^#Kk7%!86Ttv?n63{||q97FEC@7U`Q%9wQs^)`h%gg|DR}V#3zX*K4 z;IJP>taf|9yJ-UZFRqe-0;KjT99RVh(4J}YZ3pFT; z0C7M2HEc1k2&$4*DJkD10R;$ki5^&jQ{7Mmh$qEvV^rH2-}+;_?{1NRY=rug75E9C zOrr=8j|tqws3(#-9fF=!K-4gVn#B%eu|u&Uig3#Z;Q}eg=v<$|-VbF>Y++|fsUR^G z9#JS_9tG^LUURr+002>co^dL?sK(()P@W;(-gUYY6jxC5P;m^@+*3*smURl3)F2tB z*l&2011|8|77}1-y);t2G-_DM=hgZi?i~dn{2M2FC+Pnhi2lK{QsM7tMk-c={V2t1CiBq9}E)n6D7+~2pz_Jf3 z!BSjdtI+gTtOQGIg-a-@tdt`6`HfpYrX(2Q5`B7o4(u0Lb}RgylF>>j!g5*R5=#Cm zr36b|gu}Ue~Q{cRtKb)Bb)_H?QYJ+AkRu7iN3QMD8u2PDyoK?7_0?Aj!e$%tp zwo&MB6%6;|9z+l^MHuyK|bkgf|yD@3xK;|~_^A2qA zZ|>3G6UDw`xvlVbNYf-9Crh?;r9j!l$Joo%Ax)vs8F(;a{Q`r>;EkwGDR^QJ8wE1MgY{a)=Vt zJq>)I$I?XPp&s|aDQMiIL}6-z8l29{vqco4Ci}vPD?HH*BGj}N_`-)fhe4Qn9RyDq zd~FP3*dzj}KFuIK&7eq41%WeKr2H8bsQE7N!3b|EqbT**1Wu3TsbmzPCeOn6FWfzh z!qnRtIMbEyAEOvG4;IdIla3)NQnTRTqdTcQk^=Q$4-PzdTS%hRumrwk5Sk`QQSTt& zSwJF~Ne-JAAk{OO1T&c=saa0&u9K&cNrbv5g{L9z5hh`5VuF6+$;{`;EJnSXgb(!j z-Z6_&kNe?OOuU>IYg*8knk}eZx)9r^^g!gd*`X=5TTyT z!?*psgB+sNTmWdj;t=29*iJp%nI$~s6nV-iL(Ln8)<;h91kUZ$d?Wb7&IHcA|M`&1 zDU!=6L*27NXMvoGxtzQI^P!SctdesZwt_+}*TE^=!6{8mn}m$x6dUH;M$PAjKPU}z zs{QA~5~uJIr!@6W0GdBI6_z+v|MMY?izAFn0E?KQT5`BJa<~Mj_x_MSxVY=NgsJyv z&?cUXtDj4V8c{>nf?V7ST*A~_DQN6-bNO=%QBxwIw&mu|M`ql_E5a^Y91qh*J~$p$#C9z(*blYElujZ{QL5#Unw@DTjhFUZF5vDQXT1 zbd13(RL(0!J!XJZ=N0Vdm870FLZgybV1-u#yJW^5j=;+p<*^859m5`r;Gq)A0})CI z7VkVi9x6$qkxZgd##Tw_LkW#U z3C%9-1NP(u2`JEKCX^!VnF(A%d0Ij#!Jd{7pc2Y+5=sdqJ{ttHK|$;!1^UoRqtHro z3|mOC$0o2;Z{(o~rb(ZNaQDgXBtcl|M3Q(SX(v_!D@~FpAyJja7Eo9S<>d*5i>;Gz z3FV;)r371b;1bHS5=sg7q699Xydt5LVDCrZ63UwqN=Yi^%?MmVc_%_C!8#HgiBcYh zP)e}S0sal;9SEfaTf5;B%Ciqj3ASj#C6&l)4@v>xd!Tom>6eEb-1;MI5+iI>?_e`M z{2R)156X|Q1r9EuJno>BV4(n9LV3$UDZvIgY!Bt}2BidhwgLZ!@>GLTf<4lJODGRB zC?(h+f~8U3V^B)&vxq3+4qsA&?FnO%3}aED6aeduX4AO~=1Q^t^&1MY_Z zSJl;rS5aPhw)fn*A2WC6-nruq!9hWiv=+3ARD#x0KdRf^r*3s+ecEoje)UUhcOU8Q zwysqqmq1iLlq3{_$cI28NJyX|Aw(kzD2e66fJz`lC22{}pb%)ohkH)uoVoMzSDxSR zob$eS?%bL4p7%XJxM71S4DoRYJ`RnN6MqP-H^;0uua_66v~$qUj9WNzz9%CSPDZB6 zmm>WfGz|A}flm2*N(&N)W+`AiY4WfCpCRsZtP%Rc_IU_3T1=-!v8Ybj)u~{Nnv_$M z3dY!-vUe*MZ7HWsu{fTxk1G~^DW^}dm}A>>?BFP6wo_&YM_FszYZZ%X+o@J8cG&g~ z#bT%J>{Kj{+4eETqQ`c66pLADdsaF)kJ7YLn)c@*y)ASLaz6`yA$TnZLogV+RLU0! zEK7}DmMWISOO`bBWpalL`$}&MG2G9>jP$e6c-+I18*gFe%7vMm0x$CV%&7Xz)$$^j z4i}2bT`lY@T`k0LCkr#OL?DLyR+y2F75bfWmr8CXO(U;p8aYW`)RL@I5N=ap)2)d! zlOMWm?YAwwI7dR*XUuKMBSs+bc?dpNfGqpbwx=0kUB;8@BmF(r2lPm{pM=&=xb>Vm=`6V7fxwox{%Z z03(K*ahQ>29AdZuhncn?Eq(9oPyh5CdKOgM1=Y6yzLwS;`qH=^hkelWjr?(MkavGyA3;|??)l{C^SlbFbHJLF zt4&U^0MfTZljmL?rld=U81Bqr=9=GD|24jP>1}kS4_NvE%YRZxx6W|1;Z7YHM>=$3 z7>&Dfn8F~f0IhJjoZ3QQ55OL{Tn>{X@OS)QH_TfCi^w_2ug*!{5?B$wlNtR^rZ|wT zAI-Q&Gm`_^`e0`CV5T^btv{RRKASgLvUORr(cHNkh-WA(WMa7YN9N95Kg4jS4>LFa zBsqQluS)J9=C0^nelbxxfC%TVANG)bA7Z%2hna_We`nS$lO}$TnERvm`&V0fe+cJ( zANG)bA7Z%2hZ!j`5yKrl%t+OP7;fNUMrs+u(T4kWm>BWpb?+Vj+DQFQx)aL6PFe2# zd-KNw*T3{+&zaIX$CrydG7ztMZ^-Nf7% zy)R!zkscoU#dF^dQ#jGAb9vUePL7z@el+XV$11aTKa9-FVR$(lmmmnVgrP+NI>XSZ z0Effc;jj^KIUk1eip7Pnc0sYI)Syxejab-O-PfT0KsDZsgib}kYewjv4@(O`@XQP`jWyP~j50lK5m ztpHEQ;OST}#>|*DGZq|WMND523x1a77&I#`2V=&;+CrNV>?#iG*GDiw0l z$!JqDII*qC_|{}_V%w9^?TW>l$@rU!MR(HZP6j77D+RMs!C^~NT4^dcY;_8%6^ojb zR-;(#PQh-)qAjJhDHg|5a9pwIOKE+I#T*;v*ui;}*;*NDw&Z@dYi(GoSXA3uwPLZu zh8>Ez zhFe#e+4}9j9scE%>C=W+;zr>d!{64Fc2@G?7FPC==2c?2VU?LXoz)qRp3EH0RQ?`t%tt`KyE3|T!Oa4H0+LWbuq83ABxVMH%9vRh%gDwjx_IeQ0PxZ!*$G7pFI|$IPz1bmNy;1u zck9%`0JQKj zEGgk2;AL2{-->{jVaa|g0$zqC00up5Xon3m01Oyc4H(~)9a(hoa?){3oFfNCpN zoda+bFG-ac2zW`V02s8^iq~4U0%U5f%LG6dFO3ZVUK%R^#%Q$SjY^D0E7O>Zffnyr z<~vqKcKtD^m-z+&FY}dS0BGT5z5-y3L2JsOb+Z6y;ibY-7DB*Fg#|#Dg~=NhDutuE zWUMZklJXu})F)&03a}{|+oS-Sld;V?07voiYl(q?mtPBjL7S6$b26;}ndanW0-%eR zfd>FD0~Y{eyp`17QewQ7%)FJ0fffgn=7D5JPC;N$FKG_|UeYedBGAH1+6BNEvs2pa zlqmpOcv-xZXAtnRcmdF*CN;SxHB|t#@X~rYT7iI<)(e0xZK=s^si^{>g_q~c;R^)3 zJYN8G=}S%NOWiC0T6l@S9M3?&OZ){umomG!%>Ir5XyL5{nP?;W4nU2aq5_IvF7XiRqUdTZbwD6V}0$|YH>4M$q338AGExh$c0Pxlu za*zZqy!D0v7-Obm&U7+TPeY)@$uDun27pq>DRo={Xr{wU6giB7fVV`E!zc)NOB6Yb zf`GR~Q4XU_yx`oR97g%Z{7WXw7AMYQ`z6)R1b0-3a0S-f+NO2+156};JqIrVA7vTwCgr~}q zMYif_?a2B(Je+LQ)0JR39%f|CKnzRpFeB40OO7yu{R);BBG?EXi=rHqo$H*x~Hx%7R z%%jmq{bRFtKNkDd(vKc}kQUK{R^g!KpWPAN9r9qU9gcOX`#&0&b!~cxd_GItpQZgH z+@iljKCHRJKBBfm3@hv~BR?GaG%TsZjHv0*oy7_|%;3P~`Qys-ZxUyb)1mMzp~I%~ zb|8iYbC{9)h8WhzVMZQ9#IPm~GqRgRlVuegW@HsiKCF4ej64{LVTBuJ5}n&;y=RR3 z4b?#^qJqM1X{ zSSN>>YnEPd;>yy?rc<<;v7(tVKN>g_=U+cDJDn~?Yow?(65P}LFjDYg#J?0GvqRxo zT8G2SN@Dm*dqO(Qh=vX^teeA(DCQ8uDml!EJ`ORgi6hZi6Nebq!C^)eaEM{m8)iiB zW_X-ots5prh{g>)SXkGFDZCclA?Oa}Nq;5+7gG~1rl!hW{p52a&7tk-8FWF<8Aay| zf9F>U1~eXP;BZt~qIlSrFuRoHdTWV!&{K}YLR79XTR@j`o`~EuZ-U&C2t{5J+FICW&@=v!( zZI6PpI1Udh3prv~5Qmu^PGWrMvUg|Ez#VD3Blmnn;8fZ^l>L!4kemdi zubTC6IEa)qC_KyGFeAb@#IV>6GtwS$8!{|#!wk;krLg`|*p-qe0*zt4G3-jo6M=(a z{UBP18Z72VVf}2_m3Kc{Jg@1`Yp#?l5m=|`>oiv$)Cja`dYk4-F%p4ZP4Cs*Kru2K z(X$a(YL95KBBHN|xKevWpgE#9D-9DJ5xpbgN*;k0gAsi&;!0%^fdx^0LDZGXA_6s0 zy(a2PWf6hxQGI*VmC7Olol(6r>Plr1f%8%QeAJa}5P_vJeQC^tgSab2 zKm-Qk`e59ZA|L|ub$!0>N)Zr&^}4=ZcLVRDUAn$YccsLK7Tvnut-JDzM_{I*&oo>q z;32Tg(3csm6z~veH1tNpl>#0D2Mqmy;mQjRfzyV5+HmDgMPOkeN)1f zIvHB*P3U_QuGGm8=u7B*30LZ52$Y$6nd!=V2Z1_MuQT01DXH7kyG>W>LTGW()GwN@ zJUtLtZt2S{H;`ZNvGhHbE0q$o7_jsK%au9^0&|o4+@u>Qd(w%<7xeP+6}Bxs~o+`apfgNF&urfB+$&dbF{M z7C($cK#Lw=ESklP$YoJV#u8b%2iOvTB`{JnEpWUI02^SWbSfk8UVO}Z@kxPS&INtU z1$~m-2xoOInQ75$-IM?FP-Ps49Wv}8 z!$0bYz&XP?XZSBo1P&zZ1Bsx;K*AnSfO)1pPdPq2-*o1i!59su-Jn=(F`X@nMUQFs zC>Fh@)0?x9b6oU=uml)?7&%8qACncom=VPXG3r{G+HDq5O~oZ_oDqR zxp(EZr>Ly^#lG^;C5BbLn31hQVp!9QnHyT$e>m;GudJe%>VZVzfkZHy9Y_=mB>YTY zu8L zjFWASk86(m3B4$QQ4m)B;vnhRKmBX{_{{1k`mBuGE93r3b2y0ItN=&i_7Mf>iaTBL zF&vAo=TO`pQY^}KyIcdCyN6DQWK7*rpiNCHjXJOi;c0b+!VyHz!);$$4et?#`J=67!-<~Pyb_~#VAzvv(C_{qPA>u9Pw?Sh@T)5PJce)Q}6@7L;R z*!@o7e&uj&zw_1p+~L~Mr-$C(efL#$ba%GvcDr)l^yqev0?an-*+%eIn`1b0j4?b> zx;s}H_A14q#jslx;E-V-Qh-jw>CDBr>py=rWycST>*&+|KKgq-KUf4Gf~+`k;QU(Ov=MW7{Yw%^&$sQYd#j%l-q+LtY z;>eU0;&P@(^T!^|zd?E(WhF-Au|yo3zI2cF*sS~GZ_%~bU|qQ(*RQzksvrE|sjqx% zn0YgK<(oNG1yPivM>VU+L-&zjI@O_j7u`u}MrtSiU9e>vXul?NJ^ z?4+5jh>c$nyNQVrlEIS?tIRR=k7Miae&EgaUGx~5Zx+oreH8};wwOg*a=>pp-!QLV zcXrqCPu4Cd%eCf-NF9Y|VLA>kmyh0KtVhR;NYRlG%g-@0arGD5Uwb0^4vo`ceZ3=h zL1m3iJ}g7WKGtJT|6y{?Q*FfD8@<=hRYjSOa8{#Zk448ecICBR(@xCz=y;3a5kG%C z(UiI8;dUCmDP7o#$w{cImK70lIbQR)CoX z%v8>2FEe170yG-Xr~n5HIG_Nh4LGd;g9Z#Lz`_J9RE}epC!kybHYH$_0&GseW(C-r zfV~RPmw-M6C^Ml zW~5<;a;Uc|4OI%TISrc?U{4zMD8TVF99MuU2dZ+XeDRU9*@4Xp@U8>zDnPFTy*WTC zlJp>BJxzX)iIOI@cd>dVGdRp20saX2(i4opVt~bvFO^>e)&s1Ee0duo@G8KokT2^# z1dae4fqdx%Lf{0z3CI^w00hc2qslYi2=sw&%8c5S`G)L5iGnB1omD$|hLz8ro_^!K zjqlT&bWLRZn#hezP|CeFVy=z&Nx4XSQV^E&WZT_ux82lt=7kUG>0gy7tV;N=W2p|3 z56gP8j~pB(hE+V7xw9f3`}KA6P&5d~N!W{(;>wbQvm_Br6PprtlVY(o;cU%Wh$JWt z!!n>ejMRRKVbM=!WIu@**7#&b3M9m^t|v31>pAQ*tm(~a=@pry}jeA!;f~;SGy!pv?Sqgp^4fjg=d9N4nOLy;=JF!`@2sl z{7`({P~2}uMW9?SDA)b$K#qY>4#FCs97IGbC_GDkGV_aHHWpVs@%v-Lv)2kMH9w8V z@Ef&)jhcTQMOcNxvnVJB`SP=aiL;M1_0s41D5-yx^cxFBD3k_faZvWT$DQ)T(LWXc zm3(Sa1vM%EbBSyy`LI+d`-n&=F)R!!(O43c7?uHLMg%~KVbM=!MDCL^aF+OF2B&l; z1ZP6yWcmnnnnj)Fccr*40-zL?ML*eBL_djPp-*OH)0`NV^<+k5J&9o{PiC%7Kl0Q^ z(>D*$RccEWwB@c+cj1Hem;U1Alk~%0?%2znG3-LmnkL6?Qh@!AynZaQ`3Bf0!{0WZ#dO@5lUytVoMe5SA0=AZKb; z-uhD9xTlKbgVF zmI9Q*rBWtApfxqNHB~GXY-x!eUfOv|pzJFfox`&q*8gN;#MAS3eBL!_=LOP&EV1ko z%m20z$XZU;8Y89%ylQ1$wSroZ8?2EVte_TTgOzDeEVfu9w~V*(%e~ylxHNRQes$ll$nOY)tReKKKUj6PP0~F*7~M=2st82J}f}Wlt_;f z!*Zj{Jod9+-%o!|f9%2O_t76GP{&mMoecav5cvDk+}~gMJoH}`WnCkq(~7kdp@Gn+ Tq0d77A$07|*^Kxs_xJw;s!fN( literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/memcfg.h.39A2E88995CA1A21.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/memcfg.h.39A2E88995CA1A21.idx new file mode 100644 index 0000000000000000000000000000000000000000..05789f4802f75ae86433a056688f3ff07a06021d GIT binary patch literal 13270 zcmY*g2{;w)7oWK^_ujeJMb?CCEfFcvqCM?tLq(rbL?xA?e~2WKC2f{0$&y5&1)*#q zQdy%C5=lk0C`-2f^ENa04$t#F?|pvfcg{QSJ7>;$&w2Yy*REPsr4K>NZP&UUvO8vt zLJ%Z{|L1(n$v$5c|Lp`puF*aGosRAE?o^M-cv`gH^vhhE+wiWW*-W?ccc5|9^$khc zkD=3hv;*`m@GaKm=9i8QBrKk88GP+(bsQ$S7DF2E^YPQVq%if(=JG&g4jNIS93}t52 zhi>pl7kAlR%1twtj4GSmQ@GgbU{K<%6)}xT?FogBzh3+rvGVp-9A28Pd`7jn;Z#t@ z^y-hqKVJ#;&)IAJKk>?<*_q~VcPSnGp>$)( zYTIi`$9%C&>lFDM?UP~|3)v;o>!qF?Q|NHJqQISg=={!jJx;m&f_m3HFFl@!+T*Ov z`yXt$yv$eR+rUtEwyC@2tK+*DJF@>vS$-zd-KOj9e7ob}A!iJWw57{3h7dZ4@7B(T?Ozesb_PWIuG zccVPMn|2JR>nf<9(a6qAk8<8$_=dk6>DjEU?|Wx%#{Ss;QMIyT{MO6o&$h~|ALm9z zFV*^9n(F;pYL50m(xmN!a=u@q5g!BZte~1*{Z~~tEvraVJg_(5b@;#zwF!s16n}(V zySkt(R?*G#^BJ**UHwn&rI(b|$}c>SqVFg-Y_2RN5j)gcuN*xz>fH4rOFj6%Cmo9z zlQfQG)@uhR89Y-qaXiB}HeH^4(TJ~dI84ng)jM)yYqB@1Mpdr0_BZ?5QkN5Bx3(C! zS)v!qH|Z-^?wzTar#$DX{MX-?UiPwXZ_QI){mc$>82xz2^6|A3&u15J&nQ26smi6h zaG=gdA*o>6NJIQYm#kQ;=#N!R3yu~u6g_f$#IyG;-f_OIq25P3^GkK?lten|19oj(7dUuU@m_^Zb&t}xknekqj7*^?EvNiWCzbVYR3!!6T7 zq$kC{DO9)N+o@%B&OBeNq%G4Txd$*1D3SH>yL z5tjWvA^#O_i{V^Jc{lC5OIC=QvuO9lx`-#sB>!&OuPQt6t+C8L`=`?{gI%jW72Anl zX77sok+R|MXa6-F6QzEYB*d+0Dc1~|Hnr!E*`48Cn*%h%>^|2$Y^zYZ>3yJPVI8L= zH1FW2wN2;&o>HV|bW5Lm`?Gs>v!bekZl2pHQe~6Sm+B<()bj6wPBGS%TPzp;f6159 zK8r~GzAE~vwaWMF%ky7fUikVlz`@mpb7Hnq(cF-UlB|sqr3cy=J&etBtakey+P-H? z50+sT$#__6J9&-dsW59rGqWv{+xJF&htF#&#M@{v+e-9GQ41#UPgn4bbGNr0Lsa!ff^Tuw2dNedcrHD6mLhf9R1P|rk=PUopSo>+qMafi%?i8^r zOZLBE<(aa|?$!S?G=7ZPi3JpAxO~s}VX)zS#-r+0nG<$b{zXLPcMe3hr5$Wjm0OIK zyk8y`e5b22P&GQ#XhGKPgxnfe^Ji-!(#$?M1=aOAaStMWbJ*!pGesgVD)mUPUDsPz zACdN5YL_(UjjQS0d$WRK9lY=61+JKqJp0gftK}WVx8}qCZkH}Gox5jEQZ+C8!D-04 z_vod4^plT~O8M4HM|EY@&m9RfU41_5O8wDiUbYthyFVQ(e`72=ysEz8*FtpAcKF+^^PeF)?7rud<*@>@^rwBdf{ubkBy18JTrD%uF8*fV`fBObtydSBU7Krh#_@K>=bFz;lB#01 z#`?}L`910DVQaVbC$;^nrS%v7)p9+oCn00|rSVkFAD^l>p74E_m+p*BE2ep`FSruh zU8DQP%Kb%B=ffvv3u{w)a~m!)u4hUe7Y%jSJt&eHF^7@++UAQ#NBX5Q`Iw3V`_NE> zmChI0?>HXOJB~elw@oH|O?Bv%wI^4v3&~QFZHdryJiI#GYrS<^1Xp{Tg5{jN3LOXc zwa<3lh$-dEH(mZ#DN{X_nX*;VS$#uT#FU4RH`naHn;ho9??9bR^w{~()GU>kPF1aO zHYc>NxH!(fuj)5A^tABwEnn6?i*=^IDSR-?sJr0){DmJ=k2eJ+UirX{|Eox(xVBgHdk7A4y8AidS3XXcedlh^_&+WonD<8 z(+|E0=2~a%C|kjP@@Pr-{gDrG8Vd zZ$<7;-{g7Ue;>HXsFh@1um~-Df8f}n0=_8g+#>F9-=-fjnKvs&S#|q< z=5oys>uL@}4(Hk3{}a=D{;l`^ey)0ON zV$i^?e4o8NVbjdN4e>R*nbZ)?PhvI%=hn+NnLS_WI3oej0P&Zbx&!ywisFh5cgvR_-Zq z@QEJP_wzT{i>zs$XVIhd{#2qzY7<9Wq5j9R`cjcRL@G(i9a)@q4{BLaw zNq*vW)2^6#>PAIK{g(%SjNWo>LKU;0KhW0eZ?UU+|C=$lXVEr=!r^s6p%**0zdznF z`-W=v_QntMMXVn6FM8iP6ddXJu=IUv{$5$thR`MMTCCsi9#7LUwHnZUxv+QZlP(kS z*^34q9mp_T`T5g=e7)J-y8>O5&2L;d_g@XI=k6T*`E{d{#_P{wX%A(7SwG1xPwnp4D>_+cJQNq-XKnuZ7g)b)p8xJphjyWyS?RD^l+~Vm+i#mMA5UJ>G$`UfTJh`A`t&Ep+gFJ3WG%Oh z{8)l5dy&~XPhz5DV%PM$zrFp^O#h_4J~*Z)^5FPgjnP4?D~@S*N5AUq8q*68&U?|i zH~gh;MqX;Dzujr;w!90%rAiMTj zAbKl9bJwVwtyXPnR)D$W=MCI-2sc!EwoO0|;nKM6qoG=iYp(F0FSI6f?(4Lu7 zzfY=PG~>(>?xFC)$B$WEwK}A(D$1i5Iwe7GPi%)fU0qUR|uDF>&qUpMO7{x+H@ExEoh zAgSl=pCz6n9ocIfIObpLN?+e!wf|AfcgQjNY)@$&dR!~INA~Y5iypBhC)Xk0p_BT% zj67QY+**Dri{meQxTG!JyUK9sreZ@wYqL#Nr{*tOu%IVetjs0!lPy1fj)p{7**oit zW{mQV_tzGjsQB>Z%iqfOfm4vP+aa5qYzSI?d{2oR)`;++19)u*{(RvU4%EU?gg6sL zH2vX|urJIMk1@K^vQwJHgLVNz7YpiQO`=AKBPyyM0G|Rxclk7>mFxa+c+hS@>}Npz z3}tGBIO6bRl6dE;)`G121u{HnJ0Oms&={&hjew|15^WVHeZVU(WgcV=h$&1cg{ef1 zfT&Lrjh}zCh&uF2od<0N#2gls!&0C|h$F{UAcxl93~BM zB$x&yE2BvKPb5Q8UmV&52-g_sHHIQJLL3NkH~Y6WJMK-h#Z`?nqF1@K8Sx-nK>UtC-w}Kdi4j|&P1q`TwAx(`CM~1COPCRtP;IpX3`n^18FCdnqP&q0`jbJI$ z$fdMtXbjDa7(T#*900M03H31XnTZh)bxGm{lL)Jv@&4F%na9@ySP4(~ut9T_gNrpS)v@;Jf2Xls@P#8Ly8o~C-ldFi( zObrNb>BEW60&95~l!xITlN4tT$+}a&SmfQ2pRPP;3ouv4gvyw>IbsCn6iMP}=uZ>p zBMK+Pp>=@x7e@cW>eL8!d70@y7aZ7N9KQNxt(Q2o0q`OjXe2|P8UgPF@z#=U!!Ov+ zM}2wF9>9xXK`|^oHG(h1ket|8`{xm>JxVz7KR~?4hVHR(Hy}o^$x0+KX2i!dvEX6= z584KZbu6e3SR_VZkxvp2iY^@1`j8gLgDeC)<`{jDY7#EOpoB`^s8_<@ZG(Gr)^sFk%=I)ChP> ziBB@>nQx!;wZ&yTXeZ#cp->x&M`&UM-ZzC@$&b$WKkjOWz7T;n1LAL(@f(((-Y%QZEO>V)&pKR0}TgWN{oQFlJHWK z+$-uk7$Y6x&|1Jd$3V}46he%Ex5DJ#yKO$D80Dcht&;~G7rc)yHq^!b=TZyFRfuTc zK6LkJ;8z}G1*}D~p-46!Scnn44>gi_+kW$dn!8@z;?NpE3}m2zU|M1X(=I2b9X(xU z;51hrAtZD^qbz_ zFFwZsIv-)|BdkbCsMHT6MBW!j9;7C3muV6Kk|Wp=SqkTP*jw`t}=k20|TT2Qg4s4SK1aYiL7Qi)EW0G!c=sg$)R)Pj0GtuR6boU>R*}aooDs7#%9zusOpP-tnP??G3zfQk;YOxdBU6?-g5iu-rbsJu z0tMhUx|w3#Oj+u{f-`!VBE8HB6o4~)Sc*QZ$yBVs8G$S`kj0?@oDsuPieYI`i5q7m zvd}~phXQa$4ofkIHJLj6;*3HTTFBy10M4jmDb=wws8o$J8d+!~i$eo`ve2I_4izYH zm0p%eFH4F7aFqZy8o=gI`56b|*k~M^Lq%5{$Y!J2Y>wdMfIk>pB!?|U1M1k4b!>S- z8pWd#Te^#_D2U_ueqho*n4;jU0FLD{aTs54UY85QPzCWLZsVS^Um}DnN1qJ0S>p@uwxH z`$)E{0OP$Z>0Xu~VC1$mk*I>|{kW}MAi?yRo|wknXt4`d0RYY!H29e%xX z77L$aH?~`zdMccF8ku$)Sx5s?5uH>7ufB*soKcI2)gmf1U>KP;JWeGJofd}*Y+Mh> zK-N!qHVZ5$7shg7B}$j7h=GJChbc+5pWlwC8+rzkcpP}nK%Xh~|Tm9KX?nhCs3f+ahpX>Wu-MXi88Tk3{?D+O9}i3|#jXhkc79LP@A}2z1E4 z1Sz6kH;|Bx2vR~dA%KMJJdl#5``f^Nx(XQ2g6vfFqpn6 zKiq7%a=`{k{K*K#{&d}O7+Y-1^ z4Wd(nETD9Kzf~KBn0f91&vOCBE(o88>P9he3E6@om2e|(G5%X@4s{-=Z&%Sd4Sm=N zj5uLVf>1gXywSX{UEc;wn~U;uQ9%Y%s$KhL>Bw3epz#UDJ_&Qq1Em``PA4C=1(He_ zs}xF-yX_-0Ot0DkuWMqUO$>}$1P=Hhs1HI1?jY!$alj~oj*bJaqv&;%u9A!>OLNQnL*C818#KteVGNs(Wp$^A&j+JoS= z_A)2;GG|jd>q})h$qF8hK*tO-6P&(24n2Ej(Q0@E;3+VcBCLt2vmMCXWFwI@Mx7ji zglry?lDRE&5|kDPJAwHtnfywo;4DWaH!u&;P^6xWI?DoUWb=>|P1(Ks=61C#SMc3g zVO9d?#f^_Kq{bM6j|c~DAu_kdeRqS1)Zn=9?iwm}P59kWc@aDh*@+})rMi$nLbM>M zC$)Lh+No>v%>zh$V9ZB&D!RN@E=lLr+>=1k0b?D)E&$D(SnsNk48)~(s@a$6$+==i~y zpYWNftPUh(1Cz9Nv1QE;DV2$iwk`mY2H#Y7U z3@`F=YebWQ6hJsYG#O|B(NmxSL{EVR5G@26K(r8O0MQ_z0Yrm<1`z!K8bI^|XaG_E z(*UCUrvXH@PXmbJo(2%LJPja9cN#!c>NJ2T%xM5ohtmL}?4|)kl}!VPqM8N}H8c$% zN@f~BRLC@dsE}y@Q4rGrq9CRLL_tgeRL2_l1JSOgB$H-*Ygn{(`DGw^0b?(OX@q-I zY~Im(Ex|x?6gw(7?%1VyRFzHD4FULeY`Xw=4HT>Nc)s`wI2Zn8Dg9*8&xHYOr2w`7 zcz0)8{lq=hB$fM zA+W^%b%E2&_&D&X4j^g+$Si7`&nEfq^<+lIgF}KTW-3@7PAp*8$Ow zxv4zGwG6RZ2L06Dzz}N?0yQC->CC|3 z$6#6)%tbJ*hu5cN(tnMLz_ih*S~M#7wk}-T@H0_fs#Fx0? z#Bo3&i(5DjXk>94g#h&#f_)*c%gC4N6fCho^r?I~aE#5^W06MU@W2BeZ~ao{hp$tm0;ok7z+>v@$ibhom%PUwP4~B23o@4Qbu;>RYW~| z)=>v^95F{hno0V6rA2?z`38U&!dRiOb60mo>CQ(DW+RYn!?p=Fo4O(d4@%w(l9S+* z=41SPYz}qmb?l8sT?%4afr&dXc1O5F)cqllke7y}ky5dT+~#PV4j{P;V|Rr*)LkNw zkQa!g&i(%qy7dz}KM^^F8^;zrEdEH@Y;Lv?pc>R5F_9OHq!B9I0rTXIA}OJ66M=-h zLL?LMnpzg ze24#a{KKPQEJ|2Sq#Hj(ix)7sk|}39jD~^5h1A z4DxExkcn|AZ z>BL^`lLOfJ;`zGz*>46baqYMY9xC{ri1?3ff?u$OTRK9p0Kr1v{})zLDh=zZq@&fI zV{n^;+gz{z;6>=x%gvgp2-kVIPF=N*{5Igv*ldLNGQ5`+Eox@@YZ?jSI@Bf=d~(bXE?16e<} z9zqC_AVgCBuf@3nkKd2Bm>|T65JN4R(>Dr*!+4Q_tq8UR&ld`V`-OH#cqGCjg2Kac z=J@aK2!%Wp@`~v;N$P!P*@s9Bs(GlUl#IJy)~WBUa2Y{_YU--EGCtq*>!dae4#Gjj zDsn5-bPl*)#IQFH-aMAd|Ni-~XsS}esRRT+0sI8T(6O65{ZDq!1O~1=xbi*zYjLK{ zDJSdRquVktmcdw7fVuj%H5b3lLRbT96q&6VbE}U=#as+Ok>LsLUhOBRm;JJ}+c5}| zAc!_;-Kd&&o$mH;&%m7nciPsF#E%G$GXWmSal9DL^#t0){f%|2zpk&Xw3X9=_33&CcodT=MR07Y09N_(=(j>vLgf#0H@&13Mn< zs6GOGm&3Ube}qQ@Jfc}Ce=}b;Dq>YP2ALdW(!syeIyE&}^#DSy2)UGw+m=-eW|-!6 zXOJX75_L7o%rx@*l~M#732dlzx>t;jtKHP02ZLKO+@fOpbSLFnivI+JBo2~jaJRYz z7i(ueMtCH_BdV#EIbHHs9nVIH79d(sl+NN5o031XcK^j7fP(<)N_R~Ai(#cj2#aB{ zVw*l6{(ey7x^7Pv&gLPTa@)6)0Yr5QMsSe8frjom>ck=yqs_e-Y=JF`j_iyM!UFyn zhU*2Wr*zEe@zo_@duL?^K_Uc+iWaR!D%C&a?Fj2&U7!Dsa7}cVs&{iLFq|Yp5+!^{ zV%^$FM%{WdxG%wdn$gbAF%eDArz5xs;6g*6IH;3iyTcwKMT8U@`tx5JGfc-r9|lc4 zG|{T(H5ZNftTP6oR)AXSYTnbKzM6esA{1~?K*gzZ>$R^+XcEF@xUATRL8D7y_`%N@ z_7}jPIx2{4>wDfkAEAziI$qHtWkjyd->zI=200w$aEfPA!mDzA$a5_OGYQP3-v4Fl zxYSNv|8_D$0S^VdBC{s~MWtBxbc8=5{Gk*!Ebgg%v%V4Gp#%@9G~n*WEh(%^;D7M0zY7eEI!xiGMGI`!d|8Ls?~f)_;gf zRDT9n;i}?3c+|VF*tE{}ijwYem=#dlh$oiqX<7B|0#Gg_prH#WnOI zDz`r9RR;`5iV#UxV_aazt%GYXAvo~hKzG5>8LC}f_hcY^65$hNsYGQ+qsM~r0~uIw zU_pCbGuQTc#Q1p#IXvW0!ZUmg{I9J#f$&O%SE6FF`+k}>Jl$`B&?G^Vq^R=2ruG+g zJFgwYKvxD`x(kjdeYb1=qcoVo3Rt1|`=ig6-1S}18N=@dcu)0o=-si>4=d6T3S}sy z^exjKS-GuPc?g5&5kmx85}9QzgC9M*}u;U!A}N1 zf_+Ll|DGM@ir~e87pFMi$NV4eTvxbe1cQe>JfvA&xi@)5rm-HvT>cgpG=;<i8Od_kv1;6^df25rR%7fg{|GRfI*G08aSvHozPS~k9 z$gz*^?mq97iQ#k!(kV~(9DDscVr08<4D@->=N0$Ar0aa%LuJ5t29G#+L39NYadTIy!XN|}=fD8e&6T6Ql zMxC2B5Fwq1bo!iaH7wTK>&!S+3Tsjyx*i1uyvKn6|s zz>S>wWz`!IKJxI9p5Mw-t*lZbPa!mk&_rGBTDi79Bl8zRJP+|SI3F{|p>0df0tTiW zn9?hnQp4V(8+QFhSPN?vCu70Q`(1lg?_9{jz8v^cLar=Vc^RU$8{rKPZ)i^6P8t23 z^s@>fSAtyn*f%IpyL#8yk!lR$1&F8Tg?F2E3(pp;MDXFkhpI|Q?{apJ_!!}{2%o8V zTDuh#Y8(qeSOkj{yVvNt;;U<6+ENy_62OWQIJVcXg<6$f%NYFO;SZ&wc39B9Ly2h! zOJIrO1zt<9>AJ0NHijc5h@=Cs>Zeg@rOS-v3_N-8q^Y(G{-jwQF%LnX1AWTV{h%G+ zZoJw1zZNohQk~~b`M1n;pCiI=34YTUd;VH=da%xYgljxpqcQ%f-@NL}jQ0qQJT%fO z_D%b9yjm+Cp`L?!8hpcA=h8i0`mJDKB!Lkf%Tp0X?V5%TK=75pmuBVm&B*kM*-`{| z8QcllUv*vL+O%&ag8~5xD7O=jj*aThhamjq;U~Qq6#0cVtbf#f6@&L2yr(O&qURXD zA0M0$OnES+Cq~Q+-45$DA0PzD5JZE2wsAgD7?_EWBSH?XCS^d-s5qw4Pr8gzV zb0P43$Bxwu9*Xdgz_U(R-l|)N@Ku7ZbXgRxE$H9hYu*|Le`NSWgMZs+rybOB1A-n8 zdbGfh57oD3rCA|Z@nA*!@qK-(YwR^w1WO()X@MuIFPN|Xcxf$zk0N}eb%YpOZq)5u zjqp~4w^Zpi7u0)o-B5#IBY+JZnuewU8oPe=TgTw106%Fzs=H4yh2I(TCQ;Sp6TYHAN`lp@i1asI|7$yXT(u42lIP zrdh33Q|;z8?ixZa54lvkQ+Fx(cOGen5GX<*jgi{iFkpljf?&ae1tl>edcsD@*<}NR zECI6UIk3oN`xtxK8{v-xf9Qf)&`0x$>FeGb89d_Q5ly$=YwNDPdjBGnh)_a7MAF5+7EV4POxMb8w&Dk1bAFd753By@i3f1m?6K?MDZ9xVR-3;T;d}=#k>P;mw@# z(L*#C1o99_xyl@-zHQa@MF`;>gws)5<9_za{qar+CK8y?1>l{gefp%Y(pCnhBA8Oa z6@1c8+4yhNb_OXNq)=C-M^pQq?i!DfBta5QcV>-sENVS_wB0Md+`ni zaT3H)i~E_Uhj)w^v6I0|5nj@MoS$&@u;sHk2x&5;(NosPbn(#iWv&Re0@zY^LkBGj zDn06kV9$X)?Z?l(L+z(Q5W*`SUQw>TEbnilq`c{02Hqlg)7DxJe()HZ#}T!3;x@o=oWr_{}~ItAf}1V8953EAPSyY~B)-3$svD5UJ(fGO`CKNKSb z@eoAkga6fALupH2O$K=quowkam-(69X&d*xCL-x1&rb>uVV?o0C$3oQo8G9**dZ?zqHWYM++gh&}8 zX=5|yKJK*G_ya<*48;Upp6qfuWzlOdgAK4jF|_ld+ew4wT*a`r0Nyn8??2w#%k^&} zRLf9J9qBeiuDCqCU>^fJ5$q^|_XZ_bRYbPm&%j&&bLz^!oo(^?jaLxtWU!;ICh2>f zu{j%tkjgji3f8Edvt~d^qr-EXB0$e>YE;JIWwdgjnjzvohOm;D=ub zVG@MV>2`MPVSmBj=oo{i96Y5PWW??I_BR_t5wdv5qT){-5dY+$*Z$)Sq9ll-yu#9Z zjZa!r5uOO}gfb=UQ4Y-Ql!@??hnLh<&!q_~G{+Vp7>Qs+(^Wdt=T7=T;RJ&da6<8Z z5}s*0N8|iv4A*f`N9$fU(%ah4C=bC)0xw$L@RQu?n4R}eGH~O-jauCHAF*ui73ma% zf8k%nhtfm6yWi=hx*Nk6;iBU0_~dzuDSb08VOU=VeL8hZ>Wz;ld%j1AlOc|ZK(*HN zg4y$7rx`?u5J4B$$|#s#-8u=Ogo6^Ak%@QYn98UAXBZrY!-^SQ{BDyr>}@fI4Fxcy ztoB;e>U3;e!C3}>1o%TxAAa1k(DOTj84qT3nfBDrycaoq^*ILj1-MTwtX?b*?_6^T zp;&}s+J|4i?=^KkKh`AEZFeeJA~H)yrx;T8@_7d_3HmYr395!Xwm)l`z>FPhAqCx@P(4@ zHbU1_t*+-q1}y@#P*)9eLe&l(9Efn8gX=Wi0FAi=H@9v@xGTb4+NQY5_1y+$w;)){ zU`;#TzqWheg}kws82skoHys%LiwS8HMtULWa-d6Nte?~7$+sv!gggQA=(Ew~L*ARL zm%K&z%)w`Bao1^eyExA>gzExar*-tn-QaiDx)NbDj8@c0^U3-7aqC+#>?DB`y&-Qn zbGqcnv$V?$Tm^8Y%W?0Z=kKpy{ESd4Kq-xI=Uq;{SCrco22}!75x9pd8QL_)BLoT% zNHEJhcYw6vD}s**K2#$UcGPECt|&lg=AfCD_aJP*Wn-mDR~hIDphsP`Zg;-*M|lQ9 zz6kl$)l;XYp05&@BE*XjPY|8Ch1=h{8o`zaTPin)NyUY=dYTA+BKT2@6(zFTLx*b! zdti^^n!lPcwYF`l6Ncx(JjJE0IeC|Kd`=UFKk@L1UYy5%wdfP3+Fh4Hr~sj~2D`Cu zA@t=)gdhQesLu69Ea=n*0ui3c@QkXqQMkRNs((I0vk1-f`0V#|X}iGJ3-uV-3t&%U z*uTisin@ACpFz3+=`@Cx!6mz@vnmD*LO2Malpj|v9+uW_D8g4BzS3*a;o;{$&I{d( z@Lq!VbaRdlDC#oh&kaKcGhwEp)apxBwAH@28L{wo*schF-f}NMGb9VcRT5OuPY|kY zo+j*j*!emGGa1b29GO>yUwpo^8$yi;HMDAt==qmtrMy5m4#yRDzs2l*yFyoAGGXBu z8DglTbqz~zUvoNP%HX#MziFojJ+Ux2vGq1Wm&?}c~fboUd1`7~wh;V~uH8oy)iDBtV1S1)Ys5FgpY>YN| zmmz$T;S+(H#=hLM!Ch`*R~+1+S+z@ZY#;A486if17)s&AF18VuPR~X#7QmQp!LG)4 z3x0=cAcXS}PA^bCX~NH49V`&a1Sq2_Z|jpAKD$c;!aEM$QI+@J_$*JkWA9rGk~v7G zS(SIuc`*3daD;FP!l}xO1Mhd9kuwn?QG!Iu)ehT{+iGVmMQ{|rk=D_r&xBi3hOS5W z!NU(Kp17HQe`dSIA(YBcO1YZQBi!9`SZ50ccO|$>gSVN{eDToiUI;N9#Lzlc-S2zl z(yJ{9fgA)993Q;J^SIp|gj5MqsVn8E=*&yw?;(_NP)6^qs?Ezx@9FinWbl-Sr&J|h z_WW*K<2f7Q031-F-6aSFSK)&=e0@?5cFiwqZVC~16x+yeT=XYRw}N%yT`}s%~Si0;Ymq)9})vXArVD$fAO_u~l6( zuyf&U2ERo3MJP=Qd(LoF@Ou-II=T&?pR2GtT&Q|Z(OZ0@HLHVz?QfP7lV z)=Oiyr=A|BiFi zd6wn~jvP4B;CpWlTN7;Hgz$`mX9R}>OP?5T%0;*YmlRjG>IpN`0ae^x7B&&Ugwk<+ zfYa4B4Q&zL^6-}C)P8D#&+mbo5OhFCQ6DXT7kY0fO2u%L08zBt$7Pc8oDqTA&7$@TF0YG+4^Hi3_^nd4fNfN@qizu|NLx5u#muluHn(m z=GB+hUvXjZn1jc302WnAQqPka2oEH9K(ktR-lWti*3Ol|YZ+eCIzsN-ZJB1^gJ2_r zjjVXN)B5|ha_Q&q2t^VUQF(?wZ@Jv>cYkMgl8 zSK<(=IH;nP2k%R2(3sfYjX|CWdGu-LTf^|h53BmPGnfUl6u)Uq(j1b~CHa&G3%}*y zEp?Q4z`bu+(07C|4#Eh2l}{Z%>{JcH10EhwdG_;<({)-4o(%TEK1H4TcUb>tNbxZ* z7QQXRZOT*aK%dE*^P&-)cyOYQzG#)tvaRdk&A>tc3p#sMotsSe4quK?E z-$pLEhG4*h0d=*^ym!)~CO3o}33BKNtf*H#U-Zfw!I%eQYO!Ce(C)my%Y6p7MYv64 z$oVmO`p1VO=t`hVh42tg^cz;O3ZYnnVj3eme?Zvd%6UEvqIig+4;+`hr$y*!enWUF z!c%$~JT~Rwqz{Xfd>Q1+kWaa~(eGJ)c(1MqUuF18aIC}OJ}dHXAr$dYMC;Jq(EN1j z=Xiv3a89usQ0Mw3A^H=BD@3TE@xh) za9&OFXW=*=;^=vQ;f;Q;>ZoA|>Y%Rpdjo^Z)5q$K!?2S8PIQPvi@UZSy}A^^MFtnD z@uUmEdChUQ2&Ej9QU$gy8sZjf`&R%1R~cL>8Cv?)i$n9&5pGFviyqPrc|nQQ;}0Vo zfC6E1{K4g$BKsK$y1O6)O z@b_Pj7+e$K8l`V>+MDycKd(Z_=OLede#rf5)<4-{J;DtEZqO^U_-VrvGKpy;hIw7kCEYD+gccCz0a0!H-SM(h!n)NTy5; z_A6hY{GoFQgI^N-qP_UC>E`2v?UNC_WbmT>c3*0`=IE|`g!wREaYJ=`zx&y=>+7Dd zaH9Z?beHE`Ogv#+xCOyW1TRXtbIy$L)amyT;zWp}RkYDv=-W&G6M_{7R+NzXS0UTG zFFyB_!8Dkrs99UjgKuW_HpH;045l>Ifk)Tsj|g@}*af>3f4_h2zOv0SEGgkXXb0dGgOPBKC;Q+ONJ~ukXI(T78_p9eZjzn0~;E8Z}+YN@OF z*2AQ>Bl|}%$d)0S);+HEib}A_cLW;|Z0NukbqF~-P^Il#2Cfpg(xc6?Q(0jXG!Y9>+2GF2HxHkmC8V>StcPK{x_O z6!*W9imYhbd7F|x3^o~1dRBJ@PvmabT_9*EZ#PM zQ`dL~RuWiIi+wKki(>!wLa>*?o+i6Fc;?(*xepQE3Gj}7A>J^0v*4#xV#c zBA8HlmRmT@wl&j5xFx_X8hj|1r|K4V;sb+R0dfg8>!&ZaH8w$bBfuLPW5+*Ymqt4~ zgjfM$31)<)JoUQXIf;Rf1U^)rAG;PP?H_#tA&G}1Do=+C(FfCi#F82+8#Kdo4YO{N;Zd;WrPzX|gd(hxU@>#|SwBuZ44TKUIO6WF}|Bcb9eeyel!Dk6R(-_M%MAdJ4 ztq3&|)X>Xgy=|A3e_iYRiGe*2_H?)X6W_dQQ`KOE01*P{9&t80T{m^wWrT1U!YL(F zv(ChJ%e6(Ql%bNK=}w1VV+j)ORA zVdbFy#-(gy7K3X7T%)vKT7Rhf#FAGCx&r7D)Ha#41;6S;`K5;rayzj7F1~mfIP}n>Zl~OY2cthV$)x8k1B*>y! zE$iv5o*!k7@QjCNwDO%F>q6!o{Dbg;gAX+Le0l$}-bU*A44w<{oTj^My32v1UF;AF zIVhxA9Sc@VJa(c4;T{k7=wpQTw}*E#RRJF4zAJQ=Py5N z2s)U8P{u0vTu!ch!2a?nT*p<_2KFI0D|LCBXNpGJ7GX^y+*kCWvLVmXMV7WEzHFE)-*u3+#{ zfR9w1{<`V|ue2^hFp$AOR{S5*GQ6#QH}zRu$>1Ib_b4GHLC2Dx-Pc6Ol_8h*dv^O5 zUuSDyMF^82j6iGR!0yAselheFU_i(Ip2ZjMZ7ydKEM%~t z7Q6FbS6ub&UeBOHh6+kKw6vRJ=zSI;LWT%xabeFd*AC?`5!@wkrw?173j?cmM0RLk zkSReXoz`ZH{J+b#s3SOY;7l*8%RKzsTsyb{VF&C`RPB+h{{0K;wqf`t4>#$+K`!_N05W#~k`l9G%k+!RrBE<3#OV?M0RfSOEvjQQVgLLYuK4)E(`HjDu89e9U zIaTfc$eSluZP7&VsmWv$hQ76$GjxYK81rLqwN z?rLm8xGuwWT44S9Bb%Rw{6uh;z?n*+XHiP>m*&z|1`QlE(5z1EJ+vF&1W%sOJlUT8 SFVC61i5=fYZRsW@rT+sZpZ{_I literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/pin_map_legacy.h.A4E8FABDF32673B0.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/pin_map_legacy.h.A4E8FABDF32673B0.idx new file mode 100644 index 0000000000000000000000000000000000000000..e5ec467570d1cc4c2251c34124a9bdbe8ea8f8a7 GIT binary patch literal 694 zcmWIYbaPwB#K7R3;#rZKT9U}Zz`!63#Kk2=naMzU4-i+(N%lB>#&heX>(|S5G)|oK z@zXhZ=DhYb{gYSx&5R5TE|jxPeAwx_@}pbYM>aNrCG&%(L{5vEGI{2b`DrPMIdK!4 zRDveV6rVpkV!`x-4$6}s7YAJyo~+#{#=v0l#WtCtxH2~hXbnSAYFhCxMh1pgJGU&J zAGce8k&DTN!$lM%1p*6NVtV%cG!q93yK%U|g|j-Ziu8SCl>`b~a9F^Fxf0p+e6DiK z0EHbm9N@xcM?S9N=Kih-6b|ADf(t8M+9;s>aGE+$*oVUhA-ush@NipzE>JjxBSZq? z4hDwni__K_UOHs~6prDD5r+w{o1ApV;qWtWps)>x4cw5r4gJq1CNRVSg|#`fWnilJ ztX6hcGux666t?5AgR54(z2{C!*pvpKa2Q9JBuus3sq5C6QOjC^!d@I+2-VREC$7vZ z=mrX#aG1b_Zw3695xFY04Jhov;Q<$xc(|V7P>{f0pl|?309;s5bIeOaDq*?x6P!ZV<76h{D$D$&5g#+ I2N@X|0N6vMLjV8( literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sci.h.E64424C04B59AFEC.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sci.h.E64424C04B59AFEC.idx new file mode 100644 index 0000000000000000000000000000000000000000..35fbc2eff11e9448b527c9c4b53e04557d417987 GIT binary patch literal 19952 zcmZ8o2|N|w7oT}=-v09Rl6dx|A}MLp9xA1Uw5LrJX{FL$ilQuqvI~`xH6qDU5-Fuc zi1N!$p+aSe{O7)z`@H%4^mBZ^=X=jx=FYk2+&Mq1C5sldEJqMiyCp~W?l@$FAqX-8 z|L@=-=UtcaKW>~xkfY)4b2c1om{xMSJh{d+u5QWiw97Ll|4q#u(|XA^tIB-#-OzE# z8@C^cU!?zgtodA**1tb^t{#h*=x4OM?3|Jnuxxt=Vl0czM{Z4@cBZGh#KUlf*Sf5A z3?^ekY=Up9z^0w^rp^*(ot~BRG&>X)BudndhFzVi6w~OaAA0}&D z%Nv|GCU14Z2czL$2ECn^&us8q*=tcBmdP2fb4?d@5Zs;_d+}mTa^*;@+Kb!4nCi@`ltD&n2q9Vs0^o>zmntJHv!OIMj15dm&TVFPfZd<2p zxLBy5zGAoM>vL1gkNSF^sy%r&{rZ|YFD9$=E|=;$FPyf#{tS9`n+SH-7+0(2zHFXxY$UJgzBfvg01(O|_>^>@hCN__?rk_C0%D*-f9e zY`u0&JLkL7yZbZlmMo4x+cIL+*Wd42{Y(FB%n9%dS`HOK>$s(!q(Uk8T+c)t4=0fY0Aog z=ZBSqB463{49;>>k?AMbm4%#p&#kURnmj>Aj!&NTeZz62dE|%XjkNwyn(#>bkTE63Xy9<4|p3r^fqF9DW1by{q)67lU zgMs>QJ4cnhFjbYe`gr_a_yGmx7Sj!ub{}jOsPx&#?)KlLeN<=Th`kI{%bzwprLt#* zxq0H4i7R}4OTH@TDk=Ajowaks??6w7jhmjYRMdWRl6Gf{-u1l1fD2jXFJ(8nh*hU6pZwe&yLq{G|6G-b?;585 z*Ln8Gqo+D%KTbP5UM+3cp2*tzX@~N)6ceWfKd48nE`Qx+tydy8M2s(mhd)XfsY6fyMYe6JGgci| zR=;YHJEhX$S<9QHW9E4`RyoX^+27@O=2vU9#opT8OHb>!*4io!+jM&T{=N>a_)v2* z5AULh&!2xY+<3S6xmMw_pv#NrxLj@Cuw}Q)&guCFoVMIf9QLODf?p1=dq&EBUP$wU-@WFxzbijX|F9_|W^hW<=)cbDIpr7J7W%k-THBDd z-Zj~*bDHrxYp;K!wir28HNRdR>S!`o$KvkjjoTj8e4WP2H@w4F@?A+&+3Hl!+%~#0 z;=LNLG&$1imvXVmuf@E;z^+M){KmG8DZaUAg1c{4*{GJY>Tzwlug=m+12R7PRJG;F zY&*VJ;K-Qu`&{+$y!e^k74&J!GOTfFcKOFYjap%_ePDOWIkzWT$D*fQ^e}YWYR`OJ z!ap6M*gtb}PjPVG57uP1scm|Sv&zSX8y?B?-q?kG)T^2s%Ad2lmuI$mwtvw~MYF-j zhPg6AEK25XDx*?=(Vnf(&(3t~Y&D|iUWik-O4(-X{BFtpmlfNm&+IALZ~4J*weooG^qGGK_XI``pscT7EUarzDz^`~oa|eAzxZE^ z!;gxcldh`%oAI+~PeMhWg8j|8I?HW#tXF6@HyL}lhQBK>g!|&gs_UJ~n++{GN8BBM zCS+rFkptiE*h;%&1`GWHGZsI2*r}@B>F-)OV)r#q^&eHwHlIJ8tJ&vkc*gLL-nef0 zHZ%8AoA)hOVaDp8XkC(C$4EY}czkDh7R~y4MDl+D?uB3lt2iZV4l1S9dqm_1831M4w--SY3Sj1KTXI@5QeFJ_XQhe@+rCE6+j~ zDcejnh*<67zr@n5t5EJCQ;zN!XdS#uVN}#o`C~3BW(KW{H}#B`E9xtMeZ-~;UmhrY z*IuV?%w0aFqn&qmMvmk2)gN_eXRC~Z9_S7#X;pMZy!u;b-es)kSob1#hR&u5+>mF( z9NQuXUu}D6AmgugCM|Ys*@HPd+|2l^{=U*rb-vfwa6MKyGOi6POLCUAKhXJfFSqZH z>o>c#G~bG-6$$zCr#tW-ytS}@UcK#fWpFWn;k~iut*==2eO|MiEVb9&8?ZQtikDB%>l(#?u(Xnt_@Bdgajl9oDLW z&P&f4MxLEiqnq!3?%sxBAq&qhA55JrGA!V(Uv2-#!#Zs9SdTtgdKgMS<-}SsY{`P` zMW0v8 zq1C3PctlexGxbeSURz7#;oLPwpcJci! zf@P5ofsrbzr@QzEXxmNh<)ju_S|#teXdHFJ_4zVKd7UTTcF8gI$HxYhyiRcRwGLC) zdA4RB)4VBM>-@t>12qdW{v7PuJ~BI2&-QuLP8~!~JIkJT)#;&6!`IAjleX2T&L4TL zGgu~e?c>mE9?u=U+w1Ns>Z>Q6O7?WSdNs$o&2Q7h+VFv|aati-i%u#ucK%$W{o)fh z*M()iKeQ_LW$M(EQC&YOgCB^Tw_mV1bx6fi{^3j2`>9#8`_&cYy-a1}PxLL~k5^RP zH*IUwF1O$6&l+Pod38Hu4Y8Ooxg}UD>t8t%sCHTV-X=_{E=8G}U&? zC}ZmjJG-_p(U#*jzIMy^-tkNIuQ9WjR^i60eD^4$+H}PPyO~cAkcZM^zgydOmbozazdghdrlV*#~7k$)9OF1?n?}A-=lEviRbEjh_nx@~nw4&O1nmb+K~RH;ne z;obG?5@WK)6=%davhJ_?x{~FO%)VZ-cv>{qaKU^xkLx`@KaTl{^tBq(wTpD829Nqz z*;`im)i0vkW?gTPy?N8((X3a;O>4`}k2QNYEA7&^rT3oE59mIv~U-!vtZI41KDv2qw0A(JEP{L*zuhT=l$tEJ@3|v zxEgovD=+=`gO}v!nl<`s=X3Wz@SnMsvrTyYytmRoP}B8G5rW3oqK&%*lY|{p7#fOo z&X%v@oy+t0?7T;J%Gl-lEh*{6Y%f>Ug-sf}jVEjJ6t?$>JZ_cAt)8d8u)m6%lo5Aw z%b10ms?FUZFO7fYIZ1!j`3Ju@)=hk>*waW~^zXkS>&o+I^qu0J4(~eiqIFS0q@C-x z*bKu58*hG}KSwq*zfmDp{&mr8u7P4e^1=p>!Y5X;27d6@i_3GAY`eD z$E=v!qk2~FzNNP5>>SrSdjr;(d_VVk)J!$=UO{%~^0r{s`|2tghJJ2&@P9`vGV5xu zTALU>?snJ8_wxTVvbN#y){~m^OV(JF>6-CO#~N2oyFWVM>7Kb0R~8=I^~J^S6UNBB`0>*^l_x#JoGuwmHQW=_ENgdqsTk-2u*z+h>T91n6G+$O%^BJ^x$pP)~cIV$&a^Ck(yf|1p^;pHr8~>Re{iQ1Zdu{EzAD#;z zAJ%(XYiqkWVb7w6)se;i>mOBav{@fwapc-RRig{Yup1YDWtzkvPrCi))3rM9ZqbDA zKgKx(Pq;9CSh3aqBP-jFWWGg}XSUBTIdRy!&MEX;@>QDI8ux?st6B4=mn^$_&~~-O zPn%iRv-aEA_}@z0mldCSzj@!f#`vU{6`QZ^pE)k;LYpXM_miZK|6D%gw8ozJvaJ|`CEQQbIYfLzanPzl_;OG_syMb_9f)zk5})GG_{;@b~Q3kmX*O+ zPiFnC&l%8YUO&)e-j{azqV}o3>HGWi8HJ@2Hao64fBIYTxOMy8HRb+(a=pjv(Aah| zwPM0wAH$e7|95-udvAHPaDV#dmQTZCwoG#Pkc1x~GQ!kYbms^6w(aW0%Gm9`_mBQL z7LGr(TqpNTe4=f|An%Qt*7!UR23{A+r;*5GK(8F5bd({%@U)f|A}tDpZa|Gy-F+3 z^r;v8i)(n#yAOU1o3Q`k6vKtXG^aZ585d$6wycS19X9Ok+RW+=pQ?{!-2b!2zP+`i zYWn8%hQ=!TYnueL1`)_eWfRX1rA>ra$t7P56!%i+XB39;>wv&9wpWVl8g=72k%gf8RjJ!SEdSUj+@B8-e->*`0W}?mWt?juvRsRJJ?prux z%gq&a9p!f21Mx>P{MHCNoMxz$l*>$Ck)K%kx-9%nb6#C*$Xzk@ z6BGHw9A1hN5>TgoL`%ffiEgibEOwS+0>lLj;4+F`MsX$~!2ljf25_WMOKHFUS_U5p z6kDyKBQ^A4r6?g0jvU7TTD`+!jcfn?8>a^2RPj$K8jX*fFAsX3R6)*3En&)-peiL6 zABhv2yu(E9Fa@P3ApvzdG|3I)nVwMa!l~Y3sy74iW{fCB2??m`kUD52=+(*d;|h>d zU``$=<^dL!kYG+vBy)<~doJh3y4zen;w82ki6M~~K7T?2tD4ZNj;7=9=Eh(?AGs=~ z#xRf=FaSaV>S##y<(w%qQ4AIckgZ?h~J>|rEcWp)u)Fwge}xp;3E-YgQ+Ye zm4zE5BrvFd9xWC>rKQzYkKZj^p~Oe-iK%%sB#)+2iV_k~=fS=wrDV+7@u5MDkK7Sc zD>z662j3=y1k{D)FIDp9~p;!{wQG^5wu*#k6fA_?&)t6q4o+dz? z0n-h|+`w}pBw!Xwo>T3FBOY^Xt*7&mcwzyVNFLZId148MY6SbYPIRfN3Y|2Ehq#HU zM`=fKqu@6%X^J4=Wg1r#KliESu=#u>R!r*SAblMCArTVTn+jJc$NFQi{Nx$N0^}qZ z@tlFnB^I3w5!khi6Y|FFsq-O5Lz#3p^1 zh!5~1gajrPq02dXKJ@t14})6;$PO^2cod5VPo0opN|ta+;bt{H*K|F%3y{5lc?-pE zfyomRFxNq5>6O3(vD)&EJmkE%`>QDJDlke&Ks6zrrp4F1%L+1#y#mArn2bcRNMMqX zfVT;nbY1uuJLYM8kdNFHo2;TCRWzJRNHC+xaPnoT(E@t2@gY7EAf|R=NGB#NMF|P0 zV067GP>VslFU`m7pLwzXO zO_PqjSlY^c;VD4u05uN9;sBM9fNB9}71(kj<77gBmjJN^%)2Od7cdD4m@6Q&piA4H znIh{gK#lWFb)SO*=)~3W{ z`|y!#;`!%dNG@0^LW22^gY#eDeq@u`6CZy*auKJJugF#0r}E{%)>DJLW`mh@*)yU3 zJj7jW@*YaN2S!Rr(7iG7?29&svO3w-fqW!POnk#a-T*I3NYM9qcl4#$i;nfJ^q76E zGf03O1vBzPF+X6EkicZNWJWU{?t7nA`ZQR8901fiD0T--o{)gL5w7T{6W2_(haV2- zBa!0%dzeTMQ&fr)67(;E@5o?q=&r|OhDY!bKQT3hi==SzWg;Y?YQyQjN(uOxSvREO*_0z40a= z2^Uj+IfyR@rxFrSCqS3?xV>&fc1`h30b&nkpNL|KV4(;JW^V;&uV=D&+(^;R7~FS= zjTW(yBDQiVN=R@nEQUi}yzx|e{)0<*1jsot)f>gU!I}~hSS^q&zjxm_pl`0&7%c_*<7XiFvK5|1$ z{l!9lu|}4ngalM&xK`^5;`-Oy#NOv4_i-w@{3Sf3geOEevWz9rWc7~xf5VrH9tx1d zV4S`v<_i{zkYJpdk|{AV&L>pR+_D7789=>=Vi&=b2nnc9CDg}Lf;58Wdg9cBfa;E7 z?tn^2K+TX)k4{*YQl;@HM}X`D)EE?t0aQW)>Uy|PXP0t!e%U3=-_EyhY8cP>$SpB7kc$Lz z6-rS;f;F82sqY^j>PxE#c)>?vhSs!!hcxhpBb?#PMUXeTzk~j?CGVvG*#f5Ig1O-5 z9rz8VV-AC-y>bN?SI?_5m1z5=_mJA*^ApvtU zv`2eTOuv1%x`mG<4vp|7A9=~=A)JxinQ(+l7IdfxkF9MLAUlD@1QbgE76}O~u7no% zOfLwftbR-RIVL~Dt8Tv#>Ju7%T zu}&qsi;r9qQ;WGsF&95T2nn8$3Z$CuQ!-WlY4uxxxQeNlQ0x+z79qi4^Cg45J%4yb zf_&s}KH@Ltx?_kthI0uC%<4k3%CyKd7saSQeB`#6n#e&CIrzK?38)L8XMTR}(%V6u z_1ywwJ6NqK6pI1_AS4*Ta=5NF)#lboqxbX*kYj-9k7E8{T?q-8Ig+6sdtGQ_p*g&t zk0glukEJ28AiE$W=zlI8D&o9j=fPomLzyeem1L`=ql9@X4cCylDXHO?qVL(f_v|t7 z)PQ*^Fhb_0Bo(HmKttxDqy}c8KtpDpqy{FPC`XcOk{ZJsSLOIGM=?R0UF=;-B#glH z6X0aZNvdGB2{dGeNow@e2X(Y)`fL=RjVDjTlQ#ugdoVnI_0q^c95C@*l%0!;pa!RA zbF{NL(;xsdRA8P=OGy<>NP&h-LP-s?!^b{c(||_<)>t#MSxccc9B^anyRqj&K;$@Y z?yr%?d<@t4Vv~I_W2nJ_By36&h6m2X4-WKWn*Er86cEVJ3}i?EnD>Gak-09(g=sF( zfE*W^kUOq zLmy263~J~`Qa~+Trk2vAjV|9tSCwLP(gmILQBr_AHryRkl=wHWPlb_~2<}|G+gxl! zE~X^O3c!tm+(%4Va^C=ws1co*k|f0fFPWS-Lm9qyxQ!TwTns}QZa!d?F*28-B8m4v zVk@X%jFP0iAl;JfWGG0IF_5PUeV8Ii77Jc-**i=H_}b$}^O&-EOa;m90&qjZPfQVX zOgN*5sno;Nl0^Byrzu}!X+tlEGg4V{sVrr4e zO|~Z7?0AzRwn`CuH1vx&@SUyrovk4`@j#d^>&sD)1o7Z>P)y`#NX`y$!=qfm(U#o* zfXfVpK90KNsslu2ih*1WNz4W^j}a+cB}rZa4n4VIuCnAv1o4!7BUe=tZGoEyg@0Ui z$-P7=n$D9+=gCX1J^-MS&Kpeu4AOZ3jnz;3c2`k}oF-m`c%?e5IFsEebHh%0RP&y+aYUfX^D>97qBM6vi$EXm;n-%4PFy!j)!hIZR!vrk+Z!^Ye6pu!$ha&U@) zi9M*1l+_@bau98_6p%_2rqZOF6w`#o6rhtnrjtHVs!0}Cn8lTDQpOdQ4FN2p8y<7} zT=c-KT4@@sG<~VIy)?~Unq)D{=58&1x>$DtpoY`6!s(J@8VB;|8hLa>*cQHqU;)Vc zOj5-PpEPIQ+!h01*kM3sGQ%yagq>!%BaD?RGbu28=Y&gbg$mDI;xk{WiMfQ5>(>6K*?t z)ihwlj%_E|EYQgToV+$AZEXE*uC&^JuMsfr&DQs3&yh0j!XE z(9M+TrT|x2GFMsBj4qZ;7X@hG$~15#j4x%Us=bSu^T718QFiuFbOs$H(2)1P%!SUzX!rn@-CQE!E0b(p1k`dH7Bkp z-J0%#E&`f|DElEQd5X~S0u6ZyOtvYT)lq99*S(m552=+VY^6y;6&z@z3EL<@2Tieq zCfU6>qlYH!p)h)B!rmcZ+~tEE?LLu9z=VHrb$)Oq`%MhY`N3TdCp>=o(M2f_Q_R5- z9odeO*BPGF04Fb{$tKyIa(DNR_geupwrpF;WRq*pCprhZTg?XJL$Mx|3;PfQ8a?P( zDIka@6GW4f0#a#MDowgcF%2uG01Y&(fdVwruto~dO2b+yKpPEfqW~Q=UI%TsRJT1e ztcSwrrD44kAdHTM(WM6#M%M_VOV1^Ojzv%y5p<0R3gZb~;|T?LO4oQw0ov$lZFFgm z)lL_*(~BE&!V^i!Bv z3R8LB9yZoP0fITaV2|RqLFWL^9x(u%0|aoJz3A*-bb%D$L&JP%e0VzH zO$hfP1rY87rf4{Wa33&C!vVs5z!VJ!2=^fc5bi??Al!!(K)4SnfN&pD0O3BQ0K$F1 zL=f+ma32uBXB$qR8BRBW0L~!%2?YTD1Oj-I>-3q|DNP6m1G7uq2H{|&0K&n*%n)Y~ z4n_(f9E=n|I2f2a;!Ow#19L|lARLSoKsXqfOyUf}!N9N;2M7lPlSv#P91Kh*ae#0z zFqy;w!ok2~5(fwe1CJ;iARLSoKsXpFfN(G{-Nc&^4hE*1I6ycUm~P?#;b5cy!ok4M z3}+AyMhYMt3`|II2H{|&0K&n*3>9Y(4hCkZI6ycUn4#hT;b35fiUWj$ff*_e5Do?c z`2M)b*1gG|1Y>2KL3kVp;EW>n_#*Zcn8Siz#4ZQ|IO988=R4Z~Cbc+&@JSHB89p2t zAC5fCa&ZRXq#%GZ5;!sm9C@j>DQI5p@ucj~Mb~g#rO2Q_= zRlwU8VVXr0MjfVEHw3`q3b3GLMa9tAGdN>2IFsSKCOqmKIIv-%6G%aVnHs@N>FCpq zrRv7glHGDTQ0oy*%|DJ4h8gC4h#kY^9W@>LM2-Vx_EILqNIat1FJcJhAiPA zHObvKm`QcdJb-33d$lADwXU)fK6}UX1e3_(s%LSfpF|l~ql{}vT0mg^2QWbveUK_x z?*TMqkq4=P^&LP%7IlysSk3`7WDN(Yfk!LQkQE!G=9%!$uQl2ie1XP_Z6%q6qkU0M z_|L-20AImgA$er*t_{5OWK9QY36^t!7l16`AT{_p_|ZjvbX}@ z4^s0%?$h~Dr-D$h&+lSdcQNV9r8hk z(M3|vw~5YcqKjahh&Q>2@h)N_7$@SuEsS@I@{J)M2RQi$*ZA!V;Era2ACrF+;K)Iix`xa_L|Lm%@#?8V_j@s7h5D1 zeFboM0UVK3u$9W;rE)~@Rl$vZ=I}mqL~#4zz#xY=$PvLX2nWKryfCf^Mm;$2fXjQp z6~Uc~18=#!w_Fj7dT`(ym-me;f>93+xbb*yJQ0j~;CR6MKo%g?uGzX64X#RamhE+K^RBWE7IrpJOd zIV_c&p-X&NxdhsfS&T$#V4MfuVzT^*)WFIk(1t8GA~n+w zHl$vAIQS5Z?ISAp5tTTWm8fH7;l^cI;OuFmX|&NKM=K8W&@_6609dUA%#$Tbq)H zLMal5Zxp~A#r0970_mB3XMt?htk)p+E#PPuaHK!Nv~aXrD1bXx+np<6^qbGz_2}=o zH^6EZ%FY^!lY(CD{HmL}?%i12Y8Q%iQLbzKX_!Cd5;T#9B~pMw8dgXFzR<8Q6d;g} z1yXKBv*=hB1!$sUO%&iFhFzpwKHkExTNEH4!}2LWHHKAFfNl)yrT~5n%#U)l7{|ck zC_p{~%clUJ8Q5nE(9OWQDS$r{^QT-KCNQxC3Q)+z3MoJh6RV*B159jy0)(=#P?qE> z4Sy~fEG&Zpd|+W8C_pa@>!kp(Y%G>?arl~zy`}(NY^;j{1aPnbj&!%F94wUreCA-E zDZn5H8>9eXTr7-oPxyd~J)i(@x!79@@QsUoqX2F^%x&l<(enOoJ)hCe?|}bHW@scc zBzqbMiWr(jLq#vJW)N(0vQUtGci;sf(2#Y3q-K@vJ3Xbh`zwHEC3~eL`AfPM?KA^D zP$B-}i^^3EIb>Kw2wISpgQP9^wHUnYWT_yj8KZ_Cemv~&N6=;)dz&QnG~ovC_~N5h z33{nOhNf@~^LcU?S+te=rU&US}iThziA;8HpLb6Hi zOuGMCqj7a$Y0t5A&r!ZNyRrCgL*JWuzFJMMnMdk?@2O>I)DA5=4m2_~8=2B6Q4>?6 zi77d!9waI*jobQP1Ni*7o4s3-c;GF2QLSE7`syNxHZF)J{Ux)LKBbdx2IsgUIOprc z)?W=^E;%SWXXtw%{B#f2o-BeS8*Pf4s^vE<{VRw>wz9WMA0of#Q+^HIEyNs2x_UD& z?<jX2UKUBN1M!T`b!ExY2k7A9Eq5$q}Rd=@Z$2lLiw$IQ>V8MGW_pegv8?b&E z)4YsHXB$P>?tsG zeM6f+W|B7g9c-97#?(5-5~$CiJBQD@m9zi2@X1!XgS#hY9N_KtCqzrvQNrVIU=(NoEL>DL@fJSVRG$ zxWXvPho5M!FnS0G{CvZ`+kR{}n2ZJ6Lh_9fma77stWhN=>0E(6bGh5wLqs5x3pmmh zi7lMTEfm0=JK3EpVZhQ>V3n+AC9T4=6llomRZ`=qw%BjNjIIITpsv%ku2bqk^647+ zL-in|KKrN}Dn0uLjAWwh%%QTE3k*MxJw_u2fySO~FL^cas@Od?preD%wgTf*Zmi)XQ`kRIaZgHV2)fBJZXMRA-(6{J2^ga3pMeu);pSMGQ{|~tDAW;AS literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sdfm.h.F6782F71CD95D796.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/sdfm.h.F6782F71CD95D796.idx new file mode 100644 index 0000000000000000000000000000000000000000..5b720b9fa80d8cccefda3e677f3d332f5df8d214 GIT binary patch literal 14168 zcmZ9S30O_dAIHx!XQ_KB?fa%Zg)9}3eJ4T**|!i%)@&s$gruY>ZK6_H63Lb}%S*x= zsU#JJm!za@|1-{=+qwVyJg@2f{Jt~ioS8Y_*^bM^apR`jVc6(p6SsOT_gxGy3{&R* z+vw}#c~p#HX|phF>&gFg)~v6xe{!nb>U-kVH9gaG?@io%#QB5i=B4M9JJy~VmS8P* zPx4y4{NCfq;lm99Z=V$Q9;cL$D<0T+u|y~Er@O-Y6EDg} z+Z{Oipx?LOd(6Tdzqkz>ApW{GZl&A0x8L3@Yg}=+@9!OLU|GV>o@8{v5(jrvdykUD zh5B>9*NAGy&ebpJw`(ggq~7mjSk1pf#7V_>9|l|<{;b*d_{z`K{c6*DQdiZ-e_gcr z!<;#nz8*9;Z;CfxRizU+4pTMw)v4k2uITw4t6#AfcJ3hDe?lE()?W^H0(xZO0iv|>}3#hPf9od<7C*`oJ?rX)RtDKZaj9s7?6XSn+%}44h z_JcA^D6pT{I_PO#>b~14gno^3A@RwypYGS#xZnTf>>k>DXxx_dW=~%we0_Voa`kTP z;7q^mRXd$-yq_}U++l_K8;2^aIxb&1t5+JN3r2-H&hBmZf)Od|ju%^V+7I zVK+YA%8Q?tHNNIc`-VkDi=3Iljv*nFUavELWMll_u<)EMh7L94y);~IzjDL4g}29M ztr*$hva{au!=u|Z^CD6=p4p&1-s$EAm&2#bs?VRjwD{0FZ_@`$50sbd9ViV;aah;z zbVI0%Uf&s`uFktQ;rAE&(~<2{y^MmV6kSMF82Q%vaOGU3>$Hn^WdG13_l}FqMn-A> z$x5?aH?ActbLtz-%dHb)yt~`5d zLk){bw{~v+^1*E2EMvzdO0JIm3@5tldmKr!7-8-K&fACd8BLEJ*W@{nUVHoj{>&c) z^|@MF7j0VF@6)u@!Y@sYyAM6S-yWf{ZC&6Bjm9yN?qMz`XS|&`WS{Y}Y4gJVZPFOl zhg>h`Tu!L96%60}=#dkiw&3`gekK^`^;P4;CZ+77w;vu~Wngs%%)PiMmQ`94=ycS5 z!$kjm3oI8X|2q9W%lpqapOX z6PGoK}a=86BvTm*+QmUYbgbuHvD2>9zHNgJQmC z|G06l&12<;=QYkZtP^XmIUbt*?{J58RS_#rs8qQOoOev8W1`aLB*%`(OmCH47IR7> z66=~$2gKYt)VOK)sOF2lE6OZJw?D4>S-$l1?C^*k@x^6E!*=>!yzY0Z_lV+M?t7vv ze6-$$24^Ietuz+R+`XrE$0hNuz_si4zY(|qn2 z>W@t+R7u=_mbJecFe~+*;=tOQw+!$7h~4`3c-Ncc^wP6Y8=XyqhbXm`wk!;oJ>_W5 z?jrfsqAALE{OxZ#j98I9pB=w;Vr^55UF(eTJ4gH&w{Pe^=j;|$uThza1_8v!?hQ7);=MZdgF2vvq$YXJbH-OH`1xO=<_-C@R)+K z^Hz@j7U$&OUc9y_uBgM`IlExwfv04;@$|QYT$RjIetKBRwT%kMy;Pq&J8vzu{hNjE z`KhPLLkos1IV^GdPq(@*a56DzP`~idw#Rf3qqlapiZ zlUmzW`S;edyXW&lF2VWzO=FF$>1rcV9KI<$S)Vp{*@RxFoI@Kr=G@2D7_W+!_nNZl zLwN!f6RuZ0$MWCZ&blsx)0~z)tJ-^~hvnt-e&eG@DXXpwd*SXh zFX!ojp{JbF?r*77@p`hVGGVw+!CA$@lT(g-EsHdrX}F-yync4l^*)jE(Q$(^tIG;3 z7f!UF74UNK@?x=ZOr6L#+UJOR&f}?%-Z~UJsHZI%HsNz`uZUC57WdUX293CuopPpl zV$YJ8wKES*9liBGtj4xLZ~C-&>uoC%r@sktaT+<{%IrkFc#-*}%`dD98ag#i7F-YN z^Lp@+OCw*HZkRp1SX@!^Vu@mX-M#Yb2Y$Z#wkCDe!kJksjt)Kda*pBe9(xZD!-ukhUcUxez81~P9a~{-@!C1}(~ittalzL< z*(Urpez19Qp^46zxii*&SywQ!Z|>Fn)a>)q9r|u?J-Iu~GqmVI@-?^3s(k{)-}0)H zUvA%H1mf4r~M`8<8mLcH+rR7H)7iU(>n0?d7h?)X{GBG7YCfZx~hEe8b=k) z;1H#~Jw~s~saB>ty@%I#to`UQ-L7!l?bF(iX7^K`^}29Jo26L1*v!}QlwD;;R?CL^ zaj%rld^D{r-F0bX@9mdM_FKigvYwPQ*jIhuVxL=egC4H-tFovnZclD)Fn9K9Y|fdH zmzt9?b=u`L53l!|N&>|9qV8H7uO6K9T+W8M<(wU~C7bccO`oyy$)Ez?KRcgmu4VE* ziMLl72HjY&v{2oCQ0}Z}7CYy*pLlXc9UC0>+3Z1P?93$|ZB?#aZ(5?RhZR&cU-pbi zx|^votkHH&5;6FT<6`1vSpSd8U7xLQ3zg zqdTTMxy)YFb~2|aB}aX{*VwN%C+R6G1`RTvaL`>RxX0%=#p`Pxt)J&xncq}cCf@Z) zTXAvA*o=SQpYzvnoqQzsVnU;XnVDJUeV^P6F#Blu(MvDG&x>cmR%v;MAGi zXPS8>qvXWca;PjOuwp_JrBJDlls-*`ZIyFI=!&s5P+3c0wL~wJLZt~(4tDRldf4E* zi2}wgkwWleI5>u@p%jzDu#s+i{$6}gLrkJ2#h8h)wNMyJVWE@?N-;SVrZ+0`=eU$`?63d&{gOYkPY!wiOE7DXg8+K`ADuNDf3r#;?5o z^2ErU_9Dy`D)-^UK3o~4ut*0CgEjP7e=9ks;f#YA+YEIL0BZnxD8=Md*}ka6C@aSk z|7_nkM2xM1$|M#`V!7w$Q%tTWZitkg{l9;t=3tHr*i@*@#mQV;3#IVdV;1p`vp?5F ziM|u&D8@XYu$94D8LoNw6c%ZOiu4~CP;<>N&`E^3L1i>fM8g{5Q&{9+{&7aICW+^K ztw)QnMNoGIC$8Y?D1|z1$qOI5CrwiJ*K#L{u}x4{0I&j}k5WudnYKY!4p#P))2>LJ zCB`;F<#QT)PID#lDeM>)i+95kr?jlB4mHtp6=Qx-7fE7~B-bhV6gG`5D)C&!VY#!j zW^+p4ze)m&BosO2-xNMIw#)x-2TB>Z#qw%NgS!GY2MW*P z1;g8m6fkEf48TDEtQ|guLPtse`BP@|eS3)JQZcrSTkFGL2p%Gbg~+L5avCCCbca40 z^NjbM9JEXUn++A=I0(nNcHvW4-Y7{IpZliM+hk_b4l(8hh5K1-KdXvT_$a2R$V)Dp zm#05W3Q)kNL8U(q{NXL~DJ*iR$o&5hlhqKw%<-B{JO8@F{$5bBWM%6+8Fg zi)9DJ*iyc}IdvtARkB=#Yl{1zJJi|S{Br(awL@ZT9W3u9gS})lPzuX4L&`&Dd;G3? zYeb2##ZbA0*uuU4@L%{GL-@}9T4#b9J$H4y0yYBj+Z zw)qs3Q=P|Jgl7SV#n`6u}yz2nW(xrSxuK zV3`@U=vRj#yvJ5x+1h=NV-`-W4l~-L%yN-SgwiE~dm{eFfro_BLmBXnPRu2_sZ#f1knZA<h!W zd6TpifET3Z3(`<(XCZhM393l30MwFJwd4Q+=pr?{NJHs66oUUE!7oxQ0RF(jAM_W1 zIG`Q}^ram?1Wy1U0f+_QG_W`g`U^k-Fem`#(z#0rUIai95DUOPV15tu6MzPw-vG>{ zvplZW0eA<*0`L)-e+2ymAe2%KrF5mUSLn-X1(crDwBdYHx1BPPPDVrU?-ck>i3Q*% zW$}~hF96ZBaWvgWY6v0t2^yTB#R8B(TO`o^1>h>(^D3<-wO44V%6YUl0w4sxO^a^R ziU@F>?lx_8n;swl&uNY4v;msKaamr`7O!X<1h_0Mv_=bUfJS~!(Lwj;XlURM}L>*2w)GAp$=_CXK zyGqtc07B%{Lge(&yzu^k0^?Q7qqQi`^h$BI6t@!iMGU19LvizG{s$kM(oLjB2tYZd zQZA#Yq_irjVMu{qb!e&l0t-dT*^d8C8Yk&NpUePO89opWXy&OjP1saO1+4tUW+J~3c zFj9%LmAE;Ipw$|TNS0`lP+4&B{MeNK1C_bBp_j|_kV5fq4^LdoBrs6;(X%tBgKuyJgT(WO2IRZ5m2VRioFGvT}R2=9c z&AUhk)KnaZ1Ez7n4mA}A3P9fiFak9d2O5A)18_o3#eq=DIFuTMnhIv2ObV#MsHr&6 zPW5T0hM}6_z;W96I6Vk86$kQYqrCq!O|$2;y^Keiwb1r5mS`2qI3fpZ-)U><(c0Yy*;fDy^&f+U3Y6<~zlR6u!9 zw}KJL?tvuan)@ldG;Qo~7+J%v(Ly<{_4sDDY|NSAfV;D!M9-sy5{hu(Gu`tuEd(J< z&k#lk5}2L|-2m-QklaNiTN0AexWb}Hgoo+vVJeI z*_JjMUhgAN{RpIQ59(*Is`w2NbiIP2h`VdY7fphBf`L^q7>Xj#@2;zM7&~;TG8f?; z4@Ee@JDvdWjwb-T;|T!ocmlvXo&fNUCjh+T2>|bS0>C?-0Pv0{0KDS~0PlDLz&oA* z@Qx<{yyFP~?|1^hJDvdWj)y>Y-M&npV}UMuT-9A7z$HQ+ML6(~01surI|96u0sbWL zCxuxONs#z|Ks}Mv6%<-Tf+8735vg7zqi7^Sql}`FRBx0~1OpHZgqIBl>cK#Gl?(tf zWE2@dJwrxO20)pNq70~)$tYR@Xq8d40`*oIMLfmEQ#}O_mqxK^GN6KDD`Y?&#n#Dy z02&0)!eRYs9YtEb8+-Z0<|BP^qf0bMd6f&~$*P?64p^lpHB7rus) zT}H`MArFBO$-bf_f|hDpFv9O6N+Mj>$s|OXgtlOKDU6eL5Q!Yy!EsCSH1;blDEz0j+HE@bb zT2x7EqiW_rD=liJwFSf50Y-Fy(MH1?r$}Z*$&9vOK3~j;iWzOeY`vNhRWsUXzQbi{ zV?=F?HX4{X5XOqaSZy@l;Xn#2N@2CpaM!yqu4Gz=g&XwPbHL;rkj}I()CacP8{4@J z;O0oYFQB&M0PhQ^EjhsZ0%}VR@V`Q0IrY*SGpI` zTo&FrQ1kx<&^ZKvcMjAaI0f$<2yj<OL(lo|qD8N7oD0PkQ3z+0!(?#L{}izrY;i3P92 zU8?6@N(}+7P~P+efHyq>;7t#`L0lHz^bp`KyO-A3OB)D43~e0Ky_n~+@V1Cvy1xM0 zA_80)wRGQF+D`D&b&^h@4%BoD%{+XML^8%{k!)CsJwDz%**CU__~-2GvpH z5OB__UKTMe)*ZTW15L@gr%|6d_|)SiFfxsuCY`^b z8^h(KCpD5B=#U2Hketj&B4M4ij$;46rE;9&j!pR=2NEdV1j&2B!b3Y7?GU& zNh0XT4@M;Ce3A%q92k)t>`5YMc!v?mNuDHv`~$v(lG8g$1i2H;!=Kto0@&8_=S%z! zIUJ_Bn&tN?QG^5hE~EhPn~nm&?=cDhzojSu{DvU{Q|d3S%d+o00&nCC&VK3MCqpNO zaB=$gpiq*9yNwFEX9aC8Fy&XY_!Vu6zy;DIbp1iSV{nZePpQRI(!DpBmr|>c0Y53# zpOi7WA5M`#t0vG=Fn@`I$D|vdkHH&sVO^vLFB>rX=jvT6k3&9}ovVQgK!=!+^Cy@n z(n~&T_H!mb8Sb+2_9mDQ@%AQ|5ApUUm=E#xCYTTL_J(FVT%o+Z3Fb1qy$NP2yuG1$ z2$zMoH#E!O0B>(-4#5H5-p~wz1H8SV(VYXly$MEU-rmr-%PDw!L!&Cp^4H!_C*%Nc zZ-OC`w>R|KaSGnv&=5KBZA`_MZHrT2Ew5%*Yoj`LygYW&=cfzLLjDwIpW+56g3gR# zFDNCF^9X3d=pK(Y)d0iZ+%lmbvH1DXM7mI3bpcrODEQQ#0ITn(2{phO0AQJ_l( z#L*y5W)U7wgLoN`PlJ3JP)UPI8PH0DRvB=B0S9E3>B$U8mI1{KD3$>w3@DKS)eNYX z0c{LulL28Y2*Ev(F$jT z;4GtgmXW?)M0nPW^%i$4VfU-X+3M~I>L2|-ijH;XYhYvryTTlmY4gA?mKhgZ3wayP zwsj989yNpS7R*0e3%mb4pn9)+*D%$i?AGz0H($d%maL_82d3!fjE_6}TGYWD0kl;B zJqld~eOUo>NIs{KgwVkqj7YwpkVIyE`MlR_`^qL5`GB(@1aH0JLOsK(CGX*N5=pB> zQaXcCUPihOKjrft=J|xPpSqt0Eizz){|W=$o6@_zxHIed2@aO`arQoLgCbne3&BAs;GN27!7eShvX9vNhZ@O+n~HZ)@?9PDs7cYODiCD^UJoKYiinH9yiua z1ziPw4+8n$&p;#rG@d~&`R+p!L1Q6|NWSxsMCRKpkKEWS`US6koKQL5y~B@&DVT@< z@&jET4U;e;`NBgIif|paD2M#;3s#{&Q1u7W=>rE&1J%>rplkS~U>ob?Kd_Jm>;g4Z zIQMhw41!-V4d@nAfNI~v-{9qD1A U-70Lq;O}6;-$8=E_jUjMKdWsD8UO$Q literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/spi.h.B44947D573F24C04.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/spi.h.B44947D573F24C04.idx new file mode 100644 index 0000000000000000000000000000000000000000..67d5fafcb2fe24563a1713ae6c49c0c8b41667d2 GIT binary patch literal 19926 zcmZ8o2|QHa7k@MJW}h({``DFGLJLV+Mf;*GX_rvHRlVam)J}JxY zQvCY&aowB$SnJzgjI`(F<(jJQcXd{gwZ3|6kwuxyPp?D$SwC|WcBpK#c6;`%=f%e3 zf7>oqUg}kQ+&KB@rVW+6#D-g~`3}*=tw+6cRU7@0!+fiG1-(({Hve8T|G7al8JH+FrK$g}Kz8c#HQ3r*R*utsGz2mtU&7>)M-tZHJmYUr$wtZt2Z;=v`7h zuDSi#U%k@#lQVtyUh`S1Ij(GihTYyQmYt3KgrfFON9}BAUMm~7TugpvTGkT#`_<4K z?#d(Og;WzS~qlW{on!SIlY&F(zz2>_eo&l34W?GLgbXD3EG~wR6m%8s-cghW1 zW~W!2(Ejh6zN1fOU-sQchhHwC+835rWUs%fdoz6N+qi8pkN6H0@6Z#j;c>PTxozYR zCkBp1kC+Fm7Mj0wk3#sTTpeZ@uDups>({dT_K1_(wx@wc+Xkb8W89v5*e#oJ;N*|+ z$qMQ76kRl`Iue7mi~`){KXYpIUp`LRzpVbUm6K)3nW!LXO|{0FVc8?+Uu`=jKhMVR zrks}JtcIToSEamd{AT}AW0u+=`LxJx;8w=L3ma&pCnO20)#q;XqF z9?LJ8ljFSYeB6y{O>N?oZ@EPo?8~~VVQ_f3%E_=s-Qr?F1=-c+r{oN z!AahVJ#^(IGN}2f!

    ;mt{LTmh^trNm;1kz1D}k-0$ZT>*TFFathjvXmk4l#>Ip$ zxnGyE_i#|(_Q}$m%y80b-R(aZwQ3J7ZI;RT4ZCjd4_InZ!OQX8)#!Be>e8ZsDNAb{ zuI}^Pba%|!$BP$Va+{_%b%)Md%P9||r*6@8aDI`rAm-){%TUi7C*G`iTboE9Bz@b= z&T3rDIwiPl_vs5Cb;W7BsNspfN2 zqI{*TRnjMv+$zsPl&*PK_1p{kGwDk~h^G2NrepI>3)T6XqZDdlbp7U?uPj$Mm-MQQ z>(pUfGv7$4aLDUhLwb68L+%nL_i}u%8jJEdOuK$J7=UY^c$gmGM3& z*R=ItMvza>@Jg=jBL}(?DcCBcsHxePInX(vxV zs(f8vq*}CsJ?Y!rnQsIB#ZsfGQ(l`K zJ+dN#dxjhuGx?s~$q$wzAJsQR{W@sapx)W)`BuL(?PGJJGGr=U*+Z+EkEUU z0O1Dv2Ce)2({Ea@UP)>rYHhf1;z;u0qLCL)?;pOTrpt^N8TWtgN;+2bc&W@(<^BH& z_M1Cc({ILV>=$V4M^AZmNMDs(xtQNNsCSyexbeKOYJQldQsQ}Yxq2gX;nL{wmb6m~ ztlx0v{fqZGz47HZUwsbg>X-#S4QH*@IHY~+ij@oySXF z&yG?*L|@qAdSWEEx@{o+hIOH3rq_|~{JJ^q=>juOS@3cGtgb`O2JzVpAhVlBPd>#SxitnZV}KN+~m zW<|MXX@^Rh_du*7ziQ&JtcDWl;z2ZIQM|K?)|n-`wYIV$b6@%J;@YGab7#C%lb%U> zWlDBg@m#?F@3ynrbOVN&)zioe?n;Z7~U9gWMiD#*ZS4iQ4aze0i&8 zI-8GqzO|G+ZEnmOM~W?NyzZeb%gv?ZCg$n;8ZFypT_V5A_rg=f-R~4%8{E9}JoEJN z?H#2r)Ae4RwK`@(zjda-&v(sREms-(7N=#q-o{lf2c`(i!T_{j2@J!R@AZZU78 z-|b`@_scxvI{sPlJ?p}O>%(77?`T;>zuR`+JxEZ1Z2EC0_{v+Ea*a3TVU<1Qy3wUh zH~#!Gyi+mfk3)!#(Tf8wZ#*b#Qy(}ncCVJr=6k(6UIke2-+$2JhcxVx>h98-uSe=# z*EoMpq}8P#0ozSl976)6i9UpYaKe%+e*jTUvEVNkO{=vvP_*j2-%KMwWk@-uFFHZP&H>!iH@>9*IDrb&R_Q zbzTR>KHuOd=X(9+OTPoC*6+d}<=OixL*7>yEo@nMD{kW2fX4?qOq;e^PF{RT!O!}N z)3pTJ)WAr^W%Il{Nz-g)o~~X(d9Uk7iRRro{rJMw!F_tC8V{+qFORSM<3Y02){(nm zRq|VL=VHez=awH?zj@L8o6Vswdfk*>xr9vJU^!OW^;%`3bx38R{-0hn*kVis+P(io#-*aA1hJSg)>SJ>h_rDGW2qzeRfjI6XccDmu}WR6xHIuQgz>u zX}{0wj=O4dL3p^?rO@tf#Yau!!`?e|EjM;CZm5noUe$2hlys^zE*O_0{`DZN@KS6JLtbF^3+m3q;0%8W0k$ltgW-o6jwQ0uWF3k5_o4; zvwhHr+Uxm$jemsklZKq_x7L0RAOGjngNBXaKQ7CC*fZ^rnpsQZ#Gv$Iz3Sv#qc;oK zO}n3Fvx(v*!ku9prx#l&i<$m|$i~VIPov)65YR>EGX*hJaYkE(^ zCr*RYswDyH=HI4{o22^9MnB!q>RxgAg$1`iFIA1czEFK>&8ACoWt^#>r5x4n+30NIn*GV#Qth)gJBs-s zz$2woZhqHLX-{|WW;*+;Wwy#Vr0368ACKuB%GIy7s~nIH z3l2~ip%328+BeZ;$M)l|%{|WA*w45;sj1gg@y_3k^|z&e$_;nsnQ6xiOxkQg)h+mG ztFK|u@NE%4%w?wO!gKDg8V%%UxCbAQnyayGTTEHNY3tdnDdwv`svNXgzr<4`#o%j- zmXyvDM$OaJevS(iqU$H*hD=h)H7N@p=*|t86q``_#5ac-Tz&D|+w!Z&9CTWX>e9IR z`Pb@JpUAg*bR}hdmgD-{^$t@aC+xb(<>g9^=)9>Yl`TFtLwCdU$&)?@M_e`YyVLNg z;CbW%o3GNVRZ`S?8eFG^?b&FNd-KB*Lz&f=()msuae1L_^NX%N+&6m{`%wD7PLo%$ zi+%2v^?azF?!21i*Q#A~TRG;-hK1C*Qf@j8yWN-xYva6Z&$e~upV?$*d&_oUPR@sr4Dwk`J?UDSenJlB7$cIf;&+*kd} zW$y>Hy8cI@il#!BqIU$nz@XNYv4;AG63d-j-MgXInvpZ7;+J-?z+{#k=INt1Q@ zr>5$>hhg^igV8$!GB@;Gvj1=@>cE_1?W%unwYd5&9r?TU=a;_Um73!h=etqRYRb16 zk(OV`pLR_yt>BLf2?=I>eDyjYkUsS!E9CYni*;`I4*Xc4VlF=>D?+M7$w^be@cGl* z562WglX+aH{`=pv)K|P)v!~5eU4H|0es@s*^h1t&ss61SUAKQJM_zVYLHEr%@ZR#X z|K%QyorRe_Q5E%5nTAC(k4!pc`)Tj(y~WeEcvW;Aq-%Ml*9Q74XovJR8f!2To%CE! z3YM?fJ@tKi*Se$YH*Kwa#osFTYSH(fMh*7&{@iVznCbCsN?pZ&A7&Y?bK@nd#r}~? z|Er!GV|Q+RzLM02i8Zki4ZO1tZMAoj#-aZt5lmxX|Do;Y`L82N2t zt(z1abo$;*yQJ5f`WnX{HOi}V=>0IhUy!)H=yYoT*Y(n&!54KF8=YVJYD3CEB!hBk z+S2zv(T{kB)m1;!Cf1j}um5Q6Xv!+3NjEhv-j%jIU*5GT=)ZpVjUErFXTl@5bv@E) z`Dd_EJN#Vo3ClXCu*QFRI(nPJjEokirrG(w*m33Gtoi!wKb^w2{=Tm$r)_<5A#J0V z)x*`6i{+ZlpDE1pPEKlG9rQTEM1R`VQvb$tRC>X^@E<+j?@7<4%+W(b>+~8b2T4a< zZx5-Fj%|!zwA=H+*oNhfrAt>7bDDX*x5wJl$ZA8{p(Cw_ z&OS4(x-e+gzNRHb^y z(ClHALl^vLi)?1xEqgjsgPwozt?tL8dhA)L`@L3%?)m%fezkeae@!16CVo6dtA67? z*qj@@HKB@rF1)67*2CHuZFAeBE7F2omOJdZuavr{wo8qwdx@sob8r#l+fu5G_bM`?NeO41p5&k2jKMOD?k zd|5?)bN_Rx=8@$Kp3O=!-srGadV=%n1(OfHe%{u}xp$9yNO|TPDLduK2Ohr}_ldcT z9{aVyM@Op7CfVtLq4k`N^M`ac&-duF)DN|LcqpL6+&l53I{Vl9wM(ZPl@3YwCu(gv z(0LC1v3Sk3Y4HQsP%x*+vNN! zCHoJ~Jy_(dGP5v;+q}Hvm!RaAa>-_s(8q~}dy!8_9?6r^?)#^)y1#I5Yk*gh;rOYJ z3f5!SolM?SVj8^b!Lz89iq`Don~M(b`tF_S@iwP2Ouf6|)&15ZZ`>)l)@j&gT zR?O5bpF6?QcKrTA{Z0ATKg(8ccyxQGX6Jc7fk#l!mBT*u$G)%S9Sqx;={l=p{Yu08 zx9qDbPY!M)J=n5VL!TkXdxz`teH!`HK}k z#RTjvFUY5#ii8*3RXe`g1$>oPgPu zSGH@BZ?f3kS%If?Gu@<}*xi=oWYuJIJSpu$t`v>Z+u2}QRJ6>>!VjEvfp5xrhadFJ+8L#_1Y{=F4vTkAF!oy*! zUD_4>0w#tYK2nVm!&-3=j?lCaqC#-otOtNHmxZQd#O_^OYQ?b3%f28x2lI{Wdh0mh9 z8zTQzSKqYe_c+ejv9em~&?AIBS;=PeB^5uzzIZpY?8Dw)wy3DM7rCZx8Q%A^_i*37 zCjpT&-l!vgRTl;KGh9+#l| z7E$-kSMJPwmtoD}At#00CNkOtxVQw|t#^o#a(_=W`==Mfa0x~* z5stuj-6K*8sff=(N-!$%P$66-ggXXd%F(R;5hnd)XbxWMqGZ`fj?m;)3i&F9H%P)I z=zSrAfLYqEq3uUj$JJfPwdSjDpZpm)76%bhV^swzChUr2mPMxTQ2 zaS4d+q6u~Lm#ME|xnSIQA@>#;y+xKAB;gWp*CrBAubve6q45w^i-SBDQZLYv3v|Un z5-!1nuJ}t(OFtj~+&|B291rmpQX9!=BNzcLfmKI10k$Q9Rgrajbva16km^rG{HaQV zBwQj)S?X*!0iky^nVO9or*M!|AvKDDL^1f-8x=}00BuNhY-zn^`x~9gMiPb8+hp=> zviu+kmtX*k@wvL2@9;)&QEDm&d5IB;SKr7%8acvOzW_cFdvRIJvcTG@Jmffdqn%{5 zlZ?$hE`hzx@PS@M`|vkz{(~`tgk8TTqptxKmw@_7H2axZi%yN*Jl}+exC5&rWORfq zfD%yG9Ke^|Ia?CH&W<^Qhr|hu#*@)_@S1Q5nD+2B#oHYT|Cr95#X%kjsSOmQ0emL7 z1hb?EXQ_Q{VUj>^@oXM)TSyJ0pn()@mT(EI?oA-xs8hGe!i|kVMd7=jpriqTvddr$ea&n^o`~?>KuS+bcG0;vpA=+_z-(E%=^r3Ajxn?$w>!&PJ}!0IkI1J0H!Q|I60@8lo_7?t=+9&wRJTmiyVU|2wt zR{A%N=dUW*%|UX7CX=X05^xW=M3^$DF{C=l3j(-nm+#>q4~5h$7LvunyfZGrK*vF< zF|YRL+FSK|*vMTWwUSJ(1doqPFwkZAr_$r$c6>(a*~1*9R!B^wA&E51=iw4zDzTt+TD@-N`|iAp*9i_%EwtK7Lt1Ir{NoZ#z$!S_M)_=0 zonEpR54j>fC?D264X37Xsi}!0qsh?o`aF92nCL`EL1e=R6Ri(5bZ!%3C z;?F})3yCdcv;`Q&B_O)M31yqSxi*!57o%PlQeTkK7l4XOK>aT2e;fH?SMB|UfgB`X z$Zew{ZB)#o;SxOllslv@VZ3#XnzDZCGTRFrqzt1HGn&apGO@6Vsm9ZUkMH(rV0e&I zagm3d6`JfOqupR*#3ktd0|^c_YI%xY)U5rNILK2W*Pn*?)3C?KCFp)^C#gr+{dju? z&0~c*p&aCekb07ZoMd622`&M3CUmJ@hFbe{=J3OLNTiVZgp58R%MOxo2}Up)os0?H z`|)nbnFtP2D&&@-NEwPPXp9&!{g+sSAQ0ma`)C!F0C+xg|j5dImk4r!mdC4P@%*`#0|5AC#5n!~9 zjJ5%zxCG1%&}iU+hljRQm!@-&8lll_I+9IS86@En_$X^QQhmFvDLs=|nH;1-NbP1I z-3-k2;u2xJJq80oDmFfz=t%YF~%z@RRGa%Q;A;klMmTT9}xZ z#wEfOur(m{ii%yKsq}(!9ug&_R*=yOGUk482?j8_q?W9fpMR}5tAc~v7jjckBo&MR zmtX`FpxN;28d?qA?ln9lL`Z!@M&E!pi%Vd(QM6L~YMkC)d!K@FFA2HN$mlaL2e<^> zuOjZ4AeUEis(p1FBt^(AXCUPaY`C}tL(qXkVC`3?wbOQe>5}qSD z%YHRDwEz6XLjr{+Uy;#QUndIH$O;om6J`hlj)nt==S~H^DsN5>Rd7JdMm~U24?Y z@Rx_U0izKVG=hRX5-tJL20CifkvmyGOS!`wQ%$`~`YGHjWgR=N z&41A~!b2j2)R$!RCHVSq39SAQJ(at&i^oOn(Hsp4+kf%=3^8wr?VHkF^Kv68C>PyuVT=*V^byKp2*C6X2@CLvtPY`q2^}y1B8fw2 zVEzVZh@1_ff!P|MX%c2?U_Zl2v?;46_j8!SLG#Nf%1|R5G{0E_7^X}Zrc4!M_@I0r zRJ@4~YT$!T7h^nS@Sifo8FdVPodgiZ=EfBLIpENDAtC^77-fkc^f&JjT{3}CSs5@$k80+7>K+HFs2#8 zHGt-~*k3{4et4)j18bW?kxro~ilP({8jpEFQ4$5t;M~t|pa?`+0gzha|Dp&)i6`L6 zcvnybk)H!jTRIh06uEQ|Z%LP-ilS%?Y%J10P({(U1JX4Df2x)!nF9`Jf+VVz==cT} zf@~R8MYK#n6f4_CRT0IwAg*Nl(_}mr>AC$Tonxg0eED^;3rUqOz*o%s1D#bH3MMpp2LFI~>sv`dic3|Ze z=2+4G41#CDNtTuo<~ivd^Is#hd{Oty3;TTyhNz#gBip2^mc0H$QJ&BTBTwrmAkMRcmeLIn2M3id=X zpp`Ax%2pKxl-QeNk85S?ivj=G^nYxgXlEEC4YL)7+3I3IG)F0#qbbT84U(ccy3rgX zF(8d2lg3eoP7Ir%G>%ppXMz||!jUQAD2rlc%$ahuN;nh5fJP3#ks}aWjlVhc-yELU zY8>S72RQ;UAec)J=JMe3#JUaP@oZ(a>9fPrh~zOlt=-Ox|D8)ZZ~5({2pOK7#JavzyuYhe}U$fF!c*NUU&Y2 z7Hj1}4KnsP5!A5}RPkLTm#Uvjodv0IwE-hUGMG@oJTTA@xnDv9Jq6GZsa`_kS5^=j zdfjsZ3G4V7ef%@J8SE#^;Z$8w^R>xfNa576;Sxi7MAd&ZIwZJwfq5c5Ojt2E?&Rq) zb;}f>$s;lHNV?EG%o&3TCGy0C3QPgpD1yBJE*toD07p+GiwP>s69e-^a+uJ-yfDxZ zxnM#Av%o-ur+^6s@;3IHbM%4vrr?Q#D1so0Xs{SC#4sOXh_-T=AqGa`h1p?f1iF6k zTtpI>P+>++qUcFf4t`}YAqKs$rD%_2`qgvBLytY0@fr5!1WJ| z5cy+5r8&ad=R4le5`0Rj6xmdYDs0nEB$dJA;2CA8nbCgkRDvLIG0;?y7!@Q1sG-=s zLzXQ_TLLr_856k>hiPXpzj)3WYOrpLnd6F?#?Z@W9qpqW4vtz12Gqmk_b^o;bxh9V zyy#n$WkBKp*)eo+ z#xpwmnFLTmM@#79MqBCZRtZKoo!u<~1ToMchIo?%2AUuNJY}FyC4f2xS|s^ z12l#h;-5np6AfdE_ma#+lO=#kCR+J_fJP-#+(r)*?U7&vu-E}C@%cz#p$RPUUJ6)f zfdo*;LhB@ek1X`#C=lBsedL&Oq77JCbu6tq)?~5w@sXwZk!1t{^lnL&^I}o9v*ct2EO{m0DSdJoPBf? zX-4qugEhh30R%9kFKJRQY4Y$egfVdc00E5AO4DnlO@^lN{V9tLn2 z1NR^hz!=$d{cQR)cz(hdxJwZOaF+rBtjQ<3)F-+;+?}u{xQ`J7a33QE;64VP!LTN{ zkAYzv2H-vhp208x_c8Dch5@*bfibTT06qo+*uefWH2yMlA%HP(rvp!E7=Sw+cuK%yw&64tF$-{#k#=!lQ7=ZgJ zc+$fdxSxV2Jq*D86g=r+0Pd$Cfc0{PZFq$}9fqtJkj9yu#+e~;7@AzdnIU%e`NE-p z;qYK|i#2KF%xvUXhyhI;ev`!MXpl2=kYgcs82ZEE|B*Nyg>Ywva4p0RLl?OG3lgWJ zI4(Vo%Y(rn)@?j@QasmK3`pRrCH&v{X~HA!6nK8Zn&fbmb4CwTLcl18YbwUb|Rc#jX-5O?>43f|fS4RKRX zXnrwQ)I|=eZUNiEGrH0sN>^$f1>ki)Fhbnn6Gq_mJiJVm#T!8{Ilfy6C6 zp@G2&IQtNn@`MI^KtGh>hbqF*0y-jKgt(U{sPIZ2bo^X+9Zx6_cmWU06PNCz=C81& zu8gL(;1xVDLR`BORCwbKG{h}Cp@I7^Fi+g6kD8C9vm)uLa3}n@i+OUh8aD*IxOdFS z@0gsgfpIWf%}cSBjyF1Ko6`?oj}y z($z7m#3esr6>IyN!hVhA(qUB!cB?^QH%TPduc7Q~r~n4bSd%Q2orMZuYzzj3vMW&m zd;=KJiLyIU0gQYxAcV>ep$f#DSQ?d`Miq$ptV$}ok}7~M3TyI{%Kk|e!0#CYf@$nv zngD)H7?4b3C({JbXJJ4Yja^0)z)8e_E*iUwCV>6{1H$R-aJm4l01U{dv-9Z!u}H6( z&Ths4SWky7c?R20BA0%X!M@25z&H-Gk;`D`G6XP=!+^3#gVi12Ya=Q;i0=Xxa{vud!9i#OEY4F0xqdf*(`coS zZ>5_M3IvvQfHp)e2cd$|7;qXy^#-AVg&Uv^QLI5|suTL$j#M)50! zutpSa5Gq)+0oo9S8iWScXaKKB)MXGF>@gzgI+670@SA`&8o&rqm_bnCM*=iN9R{I+ zFBWKsvI{~3!+)S5sw@bNafN14{+e0YKx4zO5rs6c@B-jOu?5lMY|r?KgN2v!z^!N; zsu_nG6AAjPRP-(|pcmEZl>qus&A!nl@M{I#5QQ3qHN}%tIt0^i76Hv+#$nM- zAgtX0I8m=bw1DdzXo&I*LUaA>bADMSTF%A>6pQj>CA?)G%FmMkYEXWS1W=3eYbAg% zDnCrZ!G=){!z3JRHq|U!!ok*1r`L=+SZo}jG(o6@_pD>_>saDm`y-40aTHMN?~@*9 zJhL2p@o5yDqoHLIKo@aD&;bb`go%bok-QzBZx+iTI|zd!94l?9zJ&G^-h_ zMfvVoxr;lWJW;KtVZ8-0_(2l20tpO$f&?(c;1B&DU@*iGFF>ed@+(KH2{5CTOoK|M zh>=!MYDj9kUkw&YKh?6IY6q7CERO;MBub(P6)c7V8lnJ-(7@djXozwrLX$&rdFR@s z{So-VSkyQc6_2O#(CK-o73>&e)Sy~5sCY)R7S*gpMTb9FHU+vNN~MU#M=fN}9(BH2 z4>YS7t3-Yf20{QQ3Z{q_Yqh@J4GtXp320myu8MFJFp~gwETVLZP{FDx(1NIxA~di@ z3TTMBC_)2EqJV}dgCaDiYRy}Zwi`5oGw)M|##4sq!UY5B7@Bnq(IFTXOMw$7Q6L3} zgq`B3f&i+XSg@8%6(m#j#DcXPs&tOTiL;d|)k;+r3)cFnoPMe@1Yj5g#!Qr15#22@ zZ@u(Z7sxXsU1<3G~Umc)=d~ zzc!dAh@lZQ`l>M?fuWhe5PkBnRtxk;)MpV^-JN$if}bAlP9A%}k6&0Z7yRoN`#mJ~ s`_JfaGL|}=;MzXUKGKr@hcrYQApIu&BK485roTs7NT1m6fzjXp1BBbucK`qY literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdbool.h.3E82B883304EF4F5.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdbool.h.3E82B883304EF4F5.idx new file mode 100644 index 0000000000000000000000000000000000000000..b6d3bb0e2465415008f9ce522c262d6f3f773522 GIT binary patch literal 358 zcmWIYbaRViWMFVk@vO*AElFfyU|#I`6+Pku#m6S zuaXPV4>z3j>^tAp|Npp+(p52QYipI09~l!?nsV>=*56zm#!o#G- zpe6=U%fP_Hq|Ts@#M5BVK;oG(n8A7FO7~OUtr#u?%~j%1QiU0?w0zx^#Rm_*1PbeL m=_fjQkA2xJJ%r91+2I;U(# z7RDyqcnn#9iDPDpG7u3K5M+-mi(s51agiC6p^mr!6-DOGz3g!LlAe3dzrTC#_xPW7 zyEQsGM?{Dv%UW8HU6kQO2=RbVVUaC&2(AW4LP{I@uDvL};w=#->(rJrA;U_K$J0eg z^?sez-jceVv-Yk^(_K>R_^f|YXqp^yD@*$$`}&CvU(!AN7tL!O_s|P6wZ*4?P=z|x zkU@X(vD<^w@-KU@ZqF@U(BQY{T4? zm&4){R%^~vpFN%GIWd)fM2SS>IQ^yYmg*!9EjS!K)%3s3;;sWa=L?95>y*K`R zYxTEo43Pn#SLuDZzysy^3yrgN$9)+>0Wd0!YA*1AZbNg*=9$R^hPVQtRcSR`;DIr3 z^ZL&}uHV6s)d2V@{nT9G0q1wtc6*N*(-JA0>Gp+sky)d;qsBHfpcOTL*xJise*jDzymj3rf1)*z5fM6+yMwz zg=@IL1EI0nx2yAN+8H7Nz^pQBxWEJ7MQ@?vKOX=9n=1-YhN!u~1640Ap4)G3>R^Zh zfIwBCh6_9(JXlvNI$dy$Aq)Tpg~5jlJm4YwyRErFYG;TPfG|~b{=1Oiu4I1N|e>d`KORZBMETtWz%1Z37B|EnbK z(uAa3pCpAMVKhvEv%5VPc<<0I_w^v_sa}Z>qmiHp>mn@D|MW)YS8YilKnKwvB_7nL z$EE!bt30hBo2glWyN_mrBCOM}NLO(A4Uwf{8_@pLUxCZ0yWrC;&Dfpj;3|rAjf7oa z8ju+yH)DqOgp#Z`QASgO%sLX~TOXVlS=X*lhc^Y#00mO%1MBX*(zbRt$R=u%qaVdv z-0KJC?HN!cp2owWEe-TD$gG)B#-~7LEsQd53COH*QMS35ehPb(RLm|;9T|u+WR}Qn zm|eVc=H02qiZYm&AN7;tTJgN0Bx`k~pMMmwqw}-Z8h}o8N`yvO8W*}e8}?kOZ*+DQ zZ6ceXftH4=D1t<+$f8KpiY$i2tjJe)9A?P& z8om?12ASYFRs z_&pTyqF&1r^vX#7y6MQ1AAvSfqa1CF#eilz6<>LBKFj5R;pTOaE!48Sh4aI~+OagB zF(?v90~I*mZ`5b)Ys_gAAZw{sf$pA3J3lwS5IYA&QfSJuZH~n!wp;!=ItO$p4V7cF zW8VSI{v_Z`lJ`wqzC=#jL5`zw%SG@hklEh{q=_v%KZ8vQZF>u2;OZc{71dnoxl7X` abZ{0rIuWO3lsNOZ@L!2Th&S*sfBPTrcg+I; literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdint.h.F1B42414AC7C7BEF.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/stdint.h.F1B42414AC7C7BEF.idx new file mode 100644 index 0000000000000000000000000000000000000000..ad12c646886fcca522278426a4852b457f70d97e GIT binary patch literal 326 zcmWIYbaS&~WMFVk@vO*AElFfyU|@ z?;o@CtMBc3?%|^8mngy1dipJw=A8SVn^Nq&KTbTfIQvk!=bF^1YbQSVzF+iDa{WQ^ zdspf+8Hy`&lYmZOC`wH$jsnt~w#m$iKQwC|3lFmeC@CT`Gm@1(q9NJYgzS-!y-7Bay@|4CX7&o{ zea<=cyx0GKyWLFm*xcA~OBFCrpLHB;@v+gnza$A^CeYgr{{6CO%Fj@t7K5AQlE zvpzbXD64g8>eU|`i-wLt23_)$U#Huq=W>!}<)Q;q3>1=7=(_&ci0$wFG5;Rpxlz=Z zbMca)3UzzGgZ)e6c$&@z6~olKLD3a|N(MXnH*DsODQC@Ng4l(hXwhx3wP~{)e3K9o zpdb!sH55Le2}zNT_72EsnYJrXlS+uM?mxCGcG&D+GOX9lZFV5fQ)caS6kxuVC`~sv zV@pvUxfvC%96~rNwRSX6p1~@e;QZ9po zn#v>x)3+mUI#ark%p0q@kKeJi?emK%nDFqj73jJb{_uivphH@c%YJpNYNnQ3duqnD zei!kQA3nFVniSBHb8_dn9X@aztx*=HIf%0renjOzU5|23?G6{PBD~VKxDjg=^N3?0 zfIX;0iOO8?qE~2_8vCmiGL~MWN9(svCFotWb&Pyl)D+dpZsI5u;-&H^o08YbFiE%f zD%qQd_!>?<>^D#MzB$9$7_M-Og8Byu`D=zd&kX6xfXrxEED%TE%!(w z&TGUdY9jl(BQ-Vyi<#QQt^8gh(J2?*t_HR?&xdsAt!?Xb`trSvldP-Smpb3Sick@7 zB@&9UD|1Rd$`^d%xaJv6xj4EQ0rYe~rJzlVscQ}w_$JQk#8K4F5Rn+!`pLJSBU)B2 zf@hi|t6pf+5=8=ugyGTHo>U7n(M!8EM1Dx{6Kl4iSGwf zSu$t7;PHuKF1;xV;bW270jei=Vp2adHt74j!dH1%x{BVPdKO);+%Wb|iu|(y<@~ew zQGc}s@!e;-vf)1o_O$w@DYRLMR-${PD#3~?cf4e)z*L%nI0E5o-gdFZUU#|jB9>vlgkiT?_o4#;KDnu^9qZ%WYh>?X z*)EK3m_f$7hPuH#PecmELK7ZB3 zCZ{dr0gdtCyZ7{# z0O?5iBgt5o2_h%kmbAE(rH?O(}wBd8_GcZ!1LsA}!Q{P;YpCT&MNf~-WirPKmsP^Vr zq9pHFlGJtP^D*UQbVCz0J^|@Z`8eW-c{SQd(CurmhiQTZ6mR(F2Dpho2!@-T*fJ(L z`;`A$u)fb#-Xgo}_q;h7FI~-f19Tb0WWF&m+%!z)Yr2OIP(4UlA9+{UHA7rZ+%J9bBhV|G4s@~@;BGikE`2iHGb`#eZ|NA z$NoI9cHN*(;dy|gFV&+Azn-Csm5m+WEHWQHqogxt8SP{PP|2i(y&PSOWv}X%wAYgc zZAHo%3HnUWc5Q_-8oSoTRo=X#R4DmwfF-K#NCB^suDpkcF#(V8_}5k9$|%B;Qtv-L z&thkr9%ptG4XCFA^URk+KX%#YAC(!X{6OP>HVDS&i5K?RB8~R?cw(s}->144P<8T< zetyzetTEbcFlue)%ZYc@FA7a(mZI#Y+XJRa>xRO*AHN|{Av`bg&N<`^4w{<24a$St$ja^{RfYO zE)##@F*AAfc-`$9$pc=Mo(b`5OtVTX#07VXo9Ztsw*P80h&>(uo`@g^)A*2qMMW;@ z^b{|zN#CYD6Kx3>C7*TC`Jh0e2FIxajynqOOtD^_)e43>uk2ha^1}PW5*E*CK9^R^ z(FU3?+Ec%H_k1d~pZ}o@qa_LRt{f35$8r9(Lj|%NuVqw3%$IjR0_XPS`0cn94=008 z%wNCyaYOM%eBVEzpWBvd=%Z6R( z?HMvm4EYSlZOZd|W?5v!p3xUA(+riAs0U6d1n@d|hu5%({2gT;;|SK6wTM zrgz@gMUwmNyjw2|II(kI6j9J9Rv&rDq%B(}7}NHQ(vzkUb!bjUbzQSuFq$*vQmDgM zN`|lHs6k#T%6=*mncsd&eI<9(Jx5)b)HGCMm>&AP2dX;z>=m+jZ<`wssICea>dJl5 z%mHV#VsDrw`*{ECyHcx2Eh*@^Rd`cqd&yihDcxCwCcrj6?W(2jlrmqUi@e~{?kkon zWy}5A7yBsgr&eqHBxvOu@zR|x(e%wC2_DxvTu3Ekv~JLEI1zrut`UesEvl*2_excZ zmXB6VP|emh`}d4?8Z}qQP=B#5-cizc#9T`hncbI^p_;qy@{K{yah+9qV3?bgZ{%Fa zBlrBSR^{KtRwE|)oW!|h1y9I$723)Q*aHOp3a1Q1qh{$%7TL z`8T9Dj3aqd$f6@?nXbG)jVXSwD}*n3oAmhb^}8MYr4IFrl=xz6MDx=k&Cv}l*|+a$ zX69|S;n52At(@S|y`*gYncrHb{p_6wp(H(WqxH9Vz{Yiy!CQOu;AjDn!d>q52qIDH zCI|YxxDsys?-addPfqsu=S5onHYNG-c+Ne#V1ZDu>srRtec6O#tGLU7WtTGQt;HTb z(n+w2eOQ=0%SNI-V5=VP)%BQv=b+WulFH9PhPO`Yw5@b#a@~odz}*9GtvIu@Zj8yK zekZIhso%^wwd$G~s&^(?N?&}rDDS4wEdPB~_ORc}`$i8$nkwX9j5sYb411+@qAac0 zc^>Q^FHB~(d-5*jq2JPIV`x0aS!ih;LrC6>T}Oi-g!4EctkEzCOg8+@Sq@gdG%L!bwGe?*^R+U5#?iT1N5dY zi}H+CQ>+93Cts(h6tB@8o@W^>7UjtSARE?;6MICTye+f=EsOCUEcnj$wfTbpoV8hVy!nssX`AV zjt8^V`j0KIFm~5)D`3d`-_2JT$v*lc6fba_HNeN}`~iMGiCm-4dKOWaUHs~_`0)Mv zcMRX^meC4^HSrjkw706&R^;iPe90wjS7XCKnwXQSa*uTN>z5@3mi$WT+7mhLrEVXE zf;o-lBT>^d%&a4xW=tT!`gV$dPF-B^S3URq+}l#Y+f;NJ}^r8DY zH&Nka!j>~`Z>dg+l4OZ#G|J*gP>Xz3h;xI(Gkd(YcS>u|t~=GKrVuH6rS1J8uLF@MKK8-Ld90Y>Fls(J~#7VtVOS zYn8k-X`@9hRN&su@a9US#yK_8=pL7NRPMd3Pmd+Tx+k8h42-#||0rEKcPFBInf5&2 zw_=|qH8XXJdlcq3+L)KpdPb~PFF0wn$zOOAR{O_V=EP#OfLF##H@6}}3%P*jZk4S< z`#uWqZ-}}Nor@(BsjYZaYUbWXq0(}T`giQ3jdWkpz9S13gNJ`^r%vt1pU;d=c`#~4 z$kc2e0!;9?|FMgpHH)IXYMW%}^gODBsF0=Zv!vp>E@3L8m1@%`^_x9g_$mr7J?QX4 zwZ#@p+J^AlZk(9oMm>0QB{u*1BmOO}fa|$#g_|$)yb4LFl`k?F-HMd|IT{h(YIxm% zTjH(dnck-^*OT2%eTqk3_dOcF!eaJ}gC*9P!L~b;lUPx>hq6V1_8V&g7a2=|VrWI` z8IcE1#X@2$r(RpOy|9v=8Zn~6(7AW$j!WmrUY(A}>+DK;Tz#gWoF?{3kN+i7DY-|g zzF}0mC(k%(>+mtT&xgfV`I$yb$`U@lJEFrDDH}{pGriU;b;oU{%T4SI;X7XE_NdC8 z+e$6@D@SrGmilia7HH;OzdE1__b-X{H>43y*7`lw;3^51?@3h-D;beid|6_U<|hA> zCA^y^s+)Yo5MP~0(O5*k>vLQNU}y6j&(`=?#jBAj7 zH838QEBdgG64)i~F}!A~DEP#AZ<&@h(SdrH_I=;kkCSFA_z4S~iOpYR3b>=pgB1_F z%N=gFdU6ibw8d$Es=RO;%98L+i^^bo*VApS*zMTFZ2+)g#hN)61*o zah6R9;U9-xWz9NLbWF@uAJs{_>^}D8*y826N*l8HI4bAVn|gyY)_E$7zZvT@{DRandrIlB0**TXk~NyXg1ZE z-{YfHETQP`+x6@s*9m#z+!N)Sebbkze=270*?Ca*{AgMdtN0$~9-V7U_pqo#;^P}4 zZ$DzEDB_QNg?23x+H~GC3+>0KBhN%Hg+l@(fLI| zvs~0-cKw`FZU~p7LLd71v-Fh_UKOuqu$Sn zMsSnIk*MiZ{VyMrywuRHXI_}|GgLC+!)Ynk&yLxkb0=S2j=KHvQF;C4U*?)!q}4fv zG9rE&PG^)J+|XBl<#z*pi{0Nr;qntyGCA`B@nGf+CEJ6~uBrUtd+!xx_E=P}Ag`nPq}v_wD)9FA_i%;n>%h@=G_AXI{{YB};r>uq_~7wq-G? zQ4@YrL(FDa>7+|E&gPAwBdyv|r4{+$g8C?3nnLtL#h!GT--w;=^xmH@oy;fCh^w5g zM1S=xI*%Fm=X@wvv1D+SaP>gxgEXqQ(2n3B%S3*X>}$*dYX;{vhgTs*5vJ5%r8z%R z31(UPtGaicYL`7|$8RHSaLd1>|E^F`&tfuV!+LGrHC=dVS82F5Fwf^{BJ;U0Ba=Rj zFbxIK$I@sDwH2<5Zj!e#Tm`^Yw1|D9Ij+B_T-R0 zLRspKv9Pk(7*Eaj;;ylKDRMK!#b@ig{81k{_Io7Db5x|Q)gOV?VXa^9GB5W|UAI2{ zMq}q{1n|mCm|HZ+vsF-GjjGy~|4(lp7}Mh|(K&Fnp@PINb2<7$Y`V75HP!RZEAsDz zJuUx4U99caQqYwR)%y6IFR3M@%nx52CHH_QEt~l1RKU=^ngQRX8ID&DQSPI9I(Cu8 zb}ycezex}3`1N%A`m)A*Oz7}faF=OduzzCXu-F6Ipp;*-U#3G%jfx09rqb`_JbwF3 zPwT>+5`xGo`$wl41Q-gHNrlT^1~)Xy!%YS$!071_`R1m_i@kr7mde1 zZdy|ob8OImah{3k1vA@11==6qlx`@~O0QkINj|C60&2 zXj^MuvlTQm4IIi81&x!`ezqz4h<=@}4G} zYT7F^QW{gU4^Wmd#l+crmJj4uYtBySvum8H>dycRE*nZ`4($dsj;%iK#@>_rW& zD+Nn$=ieQ>^4ye+=O~d8!y#5T6!k? zk^R7?F}D4qdPI%0qQ1t4lfytb%Ux&9CXOqDV_;-buJVv z$QdpezcRAY)(eZ&G?Kx8wzJ$sf{uF>ou*_^M_nrJg|1Mf8_xP1`8qD+Q-Hy2Ch^0o zR%#7b!o;W_Outdgdn5PSo}E05GCQ_4TxFszP2>U_iJJsPAZx3^x5-(56ZAb9&(r$D zcxdOsUs00}Z5fV6MkZhV5f%|+Ju+Ulxp{3ni6(*ej`oN0WsbJ!!HCL>SyEYFXX#8< zZwvJ=I+}_HMCo)_D^OYGb{ruMEzZSLQrS!ASU*22EKk#rqzbF7 z5Ai&HW=�Lw57=a9^+d3(?T14E5gD$q3A60=v(Qd~bB`UHX<<>{3@;%0w3WZPpX7 z{Y+ww9bLr_-UOKfc}fKXW@7jBE32K$yUG%Gqd$h8Tg&)SYTUL@koJ`FC7tQ8ci>tl z=64DY)nE=He6@NA7cImGjTb+zgE|G8?#~ z-C@}U1bZwk-sWsBh~*0KuLe(|>>YteL-aNL50kRMtIrAi zNKb`RNqqf9WU9d5xtPPHv|x5ulZcm`Qz(R|Am$rGMdLVF8b7V(XSw3WpZpz<;myz` zqB{kCZk|8xUwhrrq!yNFtSY?yz?PQOKuMCCM?FQSnY$*TRZ&@XlP$o;hMiL6bLKU* zfU-q#4IkC}>!(bTQ!etKTnyAwlC`*;`(s*E>HJyMM3Fd0*R#*n1`Nxe`1cZb5AMG$ z>Gravn?HN$W28@Gnx)Z zOEG+GuY+1MDZlppIwi`@AU%@WOT}UDX{9|&<+JCoktlW5v-k>|Qqz|Gd(Y?E>iOAj zo?XGqMiu?7^q8jX)E93Z^TSp{6e>!?sH8}S)Lh4S=s$m?7gSgnNf&9B+^M9M8wuQx z3pk4D%Fj{pNg2328d&)>_5SX8{gd_q5^d_WVilsxe|~43n?~opfAW%nHR!Q}ltq+Y z?6rdXG)*#|70uJ2QaXKood{Q1(DP^~|R`ur4jbDY^M&n#o=LDwq5BIWn z{b)2E3LKxhzx4D%8tLna?Z{Kx8`^@rE?L|wKdw1NDopY8NO@Mzp73A9cgzpC)=a4u zVOYTWYHB8YcinSLRqw;*{vOx2qeZj!iI&|jXFKi{e*+ZA3ykicNbT7e8kYQ-bo6kD zk$3u+jFqwJ{MWXw7S=JHRMZ%wDoXtgh2uq2%Ka6#+h1&U3xExweUp3cC<{7{CCWZ6mnQ+KlrXRlw;H_=6r%-&vGD{X8EhnLw97iuZK~;mPut zKW=tO2Jw7-MQ*=oMJeie#iOzlYV>nf1Ny#7b){YBdu}J}5pyk(-#&cO>8E_|XYahw zfUDY|{j(5;rIa8}xi;$6*Pm;ZZ0HZ~P5nsL)qO}&pB7+X`NEiTlFOkecOM^B_JML` zY)v`6KklYxp!Aa5Uhk*bxT9`SRX*X>QL#hb2R0;XjyIm3*B=d+x9g%SX=h7FKOLM)l4x&PTNS%< zx~n_;PnlBs?-X+#oXS67Ep%@$FXtNj)03}oxGR{&|NCP?)XCY6msg&%CCtTc2-%)XQ~&hL4XOP?)YRgmXt6Cv?NJr8ybk+mw%a2Y-c|ix^%1=_-IPr1xHQ}Gh12wQ z`=so*{hVg8+0G07?n_M13*^R_<&@XBhqWRZ2qx~%L{Cw^caa2xyj-Ga6x`Fjzp3|v zbT1c*&FA)l#?`4`8p0f3pUh=znG*mNJZ>1t;WPDANn{SVCgypvB zd=!419z$h7g)E*F>@F6XL@zv&b@s?28RUm} zGi+mI_Y}uvTS-HhmGzqrGi$+#^>L4LW!twfvNL|~#xHKxEWhn)H<0uadD4-f&%IbG zIa>QLZa!vdP)Ig-^@X;?16iM29cAC;Vw7EsB_@Q{ihWz$+QW!qvMaePQa2?x(wNsO zpX}bd>S6s>fV?$qL|mnFjMDnFu8Y5~+IQx$dGA1tsk+?B{%I{1hbg*`3ell$V%Z)K zOTRQOnLY^Mw(J(Y-Yq$PZfWtnz1`F$p(PS`C%-GJN=Lmd4t=kF8>7l!UN!`Gh~6vz z3B7UGx2T=FhFo%$xs)&KvWAqXiC)}~0KAK#ITx)inJmpyy(Y2qHPmJ7*2>ENTy%ec z;gR_pI!yb`Zina#-PW8>O)P^ZMLjbErBBY887}|IG4v8UyTj%lrY6E{AGoO6nSk+@ ztSjvSr_wJahL4`;;+~J97ZcY`{oasg1YFObA9WFy;bJ^5k<9fai{jvBVI$L0a#Jj4 z4wLBvS+S&-?Nv9UHnYmx@|9QyLx3sST7}AsXFhbbu5pK*bO~xm?OjYt^H|zj*%00B zNy{Wkxq77}XyNO~JoZ1z3qQAVw$|oMwruH?`YNNM2O2PAL(hJT=IhVz_}50o4eg%w zKG3q7%jM7eE?IwYpFS}vwyE^VrR)b8(Q!{6Gbbqdegf{hyxZyjwqVc{sIswrg7%83 z+LBiJ)US=X$@jul!n;6QA5*N}ZF#rA$%uw2#t{NLu2iMSZ#Pew`h4NB?+)=k=W0D! zFP3O{djsG7s@&-*m%Y9v4H?!~{7xlP>%86{YFt_c9&oqGj((2Fr*ZLbkndr2+y~K& z3Ec~~J1?>4j#+D6@^!H5uMunJ*WAkbS#$tqFH}&+-WZ`1~M7GPkpW@9bwliYI8??_f|-(28(#l^&j6ZnJ>uO%exHTDOJ6q zD@EP(v?P;C*@b@+jn00nov?n?Uj5&I`FsIXZ zk?mMZ@*kdEYd?;C-S;ur$Tcy3erD%I*7V}-^#z^pf1ZB`Ky zb=%&?M7uce)|^B#A-g}r_T$K|uMCWdyOR@q8Sjo6xtxd(w@8P?KP}wtOLHEUij;gl-RUedO`l(9ap1YxX-b%L ze$sO&?ubLvLBr+VqdS7)SM~?o=Lo*U7)D%_@jBm2{pewLw)O?~D?JWAMNi&F6~;R~ z?tUhpp>xK=k?uZvMaM>JH*@Yy#}(*nu;0SWbPm;95mLYP^Vc*g%b$-NUsm|>+%K2) zMd_eVwKiX;UhcU<4T~!;O7*@kn`>N;Ze8U>DV<0e66ct>z#{uDNraF#?oqQ!+mrpY z$=E(Vo3FpASeSIp?C&QG45!63y->d4rBAVV$8?TcZ*=kI!823@H&^LTn-a=zPjq7Z zJ{`W;YhE|i?TWs@!=vxDJ$q76tZ*eb5~Fj?`B;vN@B{uGS~;UD8U=PeQiAQb0x0Ep zqjUI*RXWto`g#ylWq3V23L)a^QahJKMw8vx|2*JS;Cv(>dwaB5@DNp#Ewg9{ z(XD9al<=u*D*g`(o0&h!YN|-aiMa#`jJpo*NKu#3|D4#V3d~zB7IxFM^om?iI!qN7 z4VC zslI(3dR+o+PXb(GDb%YTi>kMz=^qaVy(*`X7vk8Z)}Wy@Xr)5St91AH6Ov_LnX+9^ zv)GiCTN6}2r!LbkEPN{#BM@dDhZ?3#q7N?ls=j!+%4}p#Vo>N$Zo6g{`$fknJOaLu z?Uz?7e5I8snjRO{ceRoZ5UZb5Zd@j9tX-;?ZaKWnxpb1i-D!!3^3J5`oaf1z3yw}T zsb(Fyr|aCQo9h3#(D801MK0KmHEjy27-@D#n;4Prl39O_m$}LGt?&VPMF7`WS@!Lf zIm5<{lk%G{ z-pGDRb+6c!Xr39XoFH{28W)_?psv;4%=XqNtp89o%iH-`N1#E{L?l9=aDOMU#%WR6 zSd7B;X}{&E8j^u?#|*a*H_%5`acHkMn)%Zo?MV7FD>`X1 z`nsOSgWpl}?a#CdM9nE1zN*#gU8i|mnQ3yvc{C6Ln575-e)~~iF!oeqW7wyWPhKh^~T{H%6qRYdp_uM1iZfZ;P>W8Z#u`B7RH&- zscW zMYOtgiihU~GBu^=DT`Vo2l)%njza^lO8V8#)KSR9c=Lt0O8owq6!)@ZsHs2mSw(0f z)4quv=QLiST*8T<6f(Y+*0zl?ZO?B<86R9`B^kS^NP42>wk3bk|J+w-JrjBDxD~_q_wIV1j*-2)cGS(9xl`WcE3=e?u}~E$aJ(=+qBhiiAxgTV zxhrvQ>89aV%ZGP^PD~kfRGuOCJXkT9EoYvq`&qE9|d$#6wJ{bH7fOEx4xy78MsV{VEuD{^f8f=c3;xQ3`7t zOIB#=#XRk?mwHoI*lzdCC5V2Z^`+iP%@BDesDG6=hn6;BS7?i8TlL$UM3-$Q{Y4=q zWxVt%0g3t>@#z>%?MmuCX|s4Wb4fo3%H(!4rt(M%B~QEfp!QGSnsk$gJvi_PE51Y- zgX6Ijg?wzsui0CgT1_2)s=kxgV88eIOOL9k$T?$0S;sOL{f)%kW4vlsi?@vrs0PW* zt1f=19G%bD+8D`y(X-FZV`ExBRWthd%kmE%*6lEXaQ~D+EsWnc7`6q-s-8&XPMfMu|h3M#;uoOi{ zNZF6(MOWA3L?U9#@yWx2!FFKiuEdYb*ENFuj(ou#(N{8v6WA6aM0k zuW3{oOEvX)>f#^X-o z&4aXm~@TmEy+#$nz5@4WII%&h45f`tbXwDirD@gsbm zE)_>;7DV9vL zUNG9LxjSA6%|jQKFrWsqJa)6+d0tqsqIJ|nS7&>SkDS(IxZyLH_Ad9rfG)e>YzBUz zxuL%vxw-o3L)sQ;^yWwW!b8hjkI3zo1US<1zGr)gmuF>Uh5ja)eTV-{$DR59>9q@? zd$cXiLXDy7jD1U+RTITdq1fEZBWXIRBM(1*&Y8&3ihlK#R<7dh__n8x>v|2V%Oqj#jwj~# zq_gY#3t}hFnXh#^v?8ykw%qa5@QT0Xy2+_Ypb2xUoQrOpJhIX(zWRAAk{m@Tf5^r3 z{L<&2;p9xcA6h+1L1%3MDNj`N+gLcBvJv@v{U76%$GG@Pv&}9wZ?w$r-xs_MF z(;?aEvTneB@y2o_A@-}0MHJzWFtQh@1O2JGk9w< z^L);|yg}X~l5jVHwBboRD!YVXh?kJya{DQLpnOL0a(m~EYr^L`Oodt9#LIPE@j}HW z3_3HejY_%~WDE#r3<~$`eCKNsyX*RC9DRKdLy_}JsLFCiXw-d1XO}kTsIHoHWkzXv zr4JAL8RaFL^nH$^4=0BOl6h>#?_bHMoJw0nWyM=_hnQG>*0Z`LQRG<>G0awamSUM| z0A$?eJ@CY^-xfTHW^$P&bUvEQBedkD68iRm{!<*%Kf7!@3B%?ytJE?#MfF5MD4w4*0y2(6e1#c(PDCZH+ngObRt_Z zgGWU}?$oFviNkOENj=r*uF24 z?UnUD`rR~M`qWzGHqwHT%Xm&Ye099ulqFlR1>>q07v!5toT*{orPSrz18dwqmx=p1X^c zFWt`xv(=31%Tg4{P<*<^ac!nWgflnc_)+t>MMcLrHY!TZ*R;7Y0&^8&q7rMjE zm5jO-#69kb#5rM|_$&wScvx*GNF~ExGVhOtmfXMYfXDya#!SPy3XDkm`f(9TMe$Md)Sa)`SjI; zSL%#Ag||vJ#7T;GU4qvtrh{Kx*?TN(7{g1%@>mN%D;#^ai2Of$1}Xz zS4r#vqeZ1+xEYJ&0*1LM*o4B4wcJ_XO;u8SO~m->&Li9Br;h2~woAv0D5Ph!4(VDs zQ9UAjT=#ocMuhJ%RdQ|X><@Px!&$BG4mJJ{`mZQ$?*!fp4CV*qH=Cb5_k3g9Nb2tN zymW%hxzbAJr{0LUVBawZpTxo~{P&liMZ0g1KUbqsIh!UGqv4KUNu16#%lmplm4klw z?!f82N+rh(jyaV%PTieKf*fJ*U)R^HW3Ns5+b4#Ixm*oNG`V808TFX_(?Xy`IDMDR zm%$Iu4eWJgnU4IJSH^CpM9CNDNW?^+&H6lbzxi#(;w;J3iFtb`=B=&Z2hZ^YVi(B5 zXktf*OhW5#OUDpd;$PUn{yrlkcU)b~O88@sSmB@i1h2vw3XJaq0+*$g^==7;-}M@~ zTjB6I-pD;Lb4B)4LEWnCPIJ9>!ctyq%{vvR;qodSb(BeUof5Nr-HO7SGzTN&X^z2p z4zEPTtlew@i_TCbf{sq3EJA`$R1_@=7GKk@?i~kltfh8pbZ{~chEpFE#By@P%)Qb& zzc4D|q}uT!Pd2mR+SxuX@pYlq&IO3oUnpOi+= zBk$gn*=Da=aDRMpY`&^ThVRpy_v&Fiq259=>yhh>wwxUq^(m42HGOZI%T7-$3!H88 ztd8HZxqp?SA*uK#)v!dx>Gq_X1lWI#kafR)P1w56v4;P+2J@%Z{m-l6=%%fOLt&fo zlBo9b$*Q9}l(h_HySuyNj_b8UhIB#NuT!cejwj+22t4@XnuTpX>Nr9s{#Zwdg&fCw}Itf2$Q zfB-U@e*}n6pElY?|3Krdq0z*hnbDJXL;wunhJw^C5bOf!{t+O?{*L-0I18(9vJ%>! z37cZoLs)%}0^g$;*3bwcbqs&&ulqSR|J;ty53E~-{Z;oh^b{JLLeu{v^*&{mW3p zF5mRgM*)Qay5I~Q1YidN^BNi<h{9b;dXHeFrs224uo+{|TV~#HlqjLa4h>X3%qR%Z}>{s---fKn$=A$IU~5c_?fI zgiwS;T+7xvycwyDvaxO~>=uAv0n`SBkc-=iSf_}eRmoG>1c&g-#;JgDDy)hSN^s*} zSd7!#tLn{~XfmJ$4qHkOl+shLp%DVaf;7Rng*|^uCrfP?h;+nn#3?JA|7@UdGp} zI=3oG$pCLSLkA7eK|_h1U6@dY`~TXo6xy{#e_eqL0|dZj_fg*f&PI4P+EkLTZc;!SJL4aSUW{Q z2Kd8Gh@b@`Xj#|L2%#qE{A#lpG550aV zNP_{|;0(S5pf3T(8X6(wdgJf?b}dE?PD2KG!A-~^2Xe@dx zS$}s|`Vd<;2(Ej80uP|IA%yB?;no(D#r~~I0V5%5SsxZX6Mn z#f&}i;C&ka!2xJ=5kfBR7BNh>TSBdUi!jsares`((84<$hOpQ?ogOagvc3Rram4*L!S-+|cHB81ddT-f8x^k7k! zI!+AG3YRTKfu&Ht5JGMq?qrf9Ot0~H&3z67%)xFD3JiiK0U_ib;oNlwfPYCX7VB2Q zZYCPcgdXt_Las0V#^1r^Xb@HmZp*;BU9ek*0?VKa7$M|V;p&zZ9AGFz>acDByua%x za2;|HLT)E+e+}5icFoL6xG+FJ><$xv!vxqn1VYH|L;w7np}O8*w#K-QiwtOocVdVZ z7^21Y0UL-;U25!|w90x+5Y zI}HdScM5mz22-7-P0D@GM+SU?m$pd4@R;y586|`vx zA+;V?_PJvU>xceytlI*+B`B~28c2kYn~QUAKUTSLiJbW|2KWefYz_s^LGK(0A-5m5 z6VeBuZt&45A?&*W>}C*v8Bli-LhdB4y9XrGHDe}Mu&5gkl&V70%lM zf*sJdA%tAqwpo(>u%C7@$Ev+>*%1P8gy8fV8X=@c;QzaRD$hBWpK84?j(uo=%O;_~ zBq%OI$PK{VC1gUn#=CC4z`7N1-3=7D0kr`k(0P+BT--^v^0c} zyN_F1N6p33E5B4F$bfg)L5Kgr_LdRYW;_WHi!xr@LL;xL(s-KN_muur6L%|;Mx zgj#?Qs)=iXg#*c@vmyeL*cTaCZ2`d+NJaP`b*!F;op4w{8UvKUt6D;VOVFwiLh1l+ zRgM?>eT;U~u45lV;IaWIFaYWnLde~~t;*fVc_;0srwj%dgxy*cSPRuf2)Uy;xBOu- zFEELbB?G>|mwE{?P(qA#5dy>)Nc?b*O`k|>^Gl7~ux<|Q#?k<>G}wy=A$0GN`}d;i z;667TtodCI1C+x{TS0*HE|!Gzp=oNGT? z6_Y9{b^`1>%;_aj_3k^qb( zz;*#4gEyTMt6$LFm@MGxy$z*w)uOC$MS~ybtvx zKt0KsH8esP8N@kz=Eis5yb11%%Mj9RDpXy@sMx-YQQK0}R2< ztwVuzP+WvigfZMGP#K+Dd{Q@!bwgmc0t73dM+&-kAwk@1)PsO@wiTc0mmT48ZOf0XRm0{nCXHa)_~HcBfI`G<4u0gxnTf7m6ngi}+RIv2G9SjuU|61Z>#nXPA&%hO5gQ#c+)& zs2=O)!%J%e!8T}V2q70Y3eGLxy_a7fU{x=;Yyk=^fHndlq<%&J`#3m>Z_g>Fbyl4W z$c1Min*qpXz?MY_4X(_;v+?Q`fybv``f88?9_8dLG0hx_0?|k!@>U3nxw!_*qkK5n}m)Ugpir|*TmSN z*TMk%a0Aj%U>dY4gpfImyYH?rcG@hUi?qmq5;*EQ4X{pw{ak<$it73=>Sd=@i^`Yn z*s=%kgvWzmJamL2gvxf~ULj&JKi$)e_OWg>9Ci!^jzN2i5OPa#d+V@4?4iU;t&N=- zIBqoxtcK@9>%@eb|i# z!Dwg>5JGMj&V8r7+OX3Vj&(EOyn`rk5Xy@Xa=+m6)*ZJ^DBfJs#lCsMt~UzwhVmkW zU0hzXvTbu>HLnL`KsMZ7FDk%`3j0Y6A#_8P{Wmme<3cLg7d-SZz%m@S3k`OmvAc#4 zD*Fz1fTZjY_U?U7#JU}D%REq^2eiWoA-4h-p`%w0kJ>&{j|@15dlFQ@mx|Yz+AzWZaY$GcI0;3Vgb79Xgj-mCj)wS_VZbBoXC^rA1PD$*BZd%i zaYqfh}KnSVFxF$5b`W4q( zeAXBP_`qqmP~a9c2?!xK1()`EO8Xmo$_pmgFFf#sb)&&W65 z*+>wKgmxDpr1s$skhdyP!}-qfSa%I}13@ql+Fpc^+ktbp-&iErpDMt*jc|lmG#Crr zrx8MKJpSh2xU%0*hc`3GT9N@N@IEw90u7Yd0|X&7xG(=5AQ)wPLAG1vShW_b!vA2O zZ<&BHCMtkfj7jm|RsI<>D_V4C*9!Y)2>6qsplGun~?1#qKgPXe*iUNC}tF{Lw6t)((un!jsMkh(p4j3R5c7LP5-_T`% z5OQ;Iu8_c{Zvg3xBlhJ9-mYp8tcE5FA>`uD7>f10+bXue6EYy?|9f!2030x2CqR@@ z`ri?kY#dXs;m-C11MI?mjR3(2Xj>6NC3|qgI(9L1Mnf+L>sG@*J_`+IK_Bf9Lara~ zqg`B_MhK4wpA!b~hTZQV_#K)og#U?J(4|AuDrb&Wr{D->1Yj9-$s&Z*eB32_cw->- z&$y{G_VR|yMxnqcs9Ojj_ZRLwRLYWxc@rFlb)#W74+Qg|ZXx_n1m}`c+k~#gXV~xa zaD)m1umXyJ5K=$lA~1T2u=JhTd5!_5;j(X0;9DpHLdf00MF{kG{_1LV%nLFg6`q+~ zY9N;y>mr24%j(}7j-q7>@%tpS3-)4w%hrHk4U`t)f6}%+oRLD?iDK0(SZxNuW@yh4 z{zqlAAt2l>b;GKG@O1q`fxn=z2q85SH(hwzR$UGPBrma_pWw11AUFbT8N&aReN3Tp zahc-0D;W^`|LIy}02UdrSGXwS^?%b9_cSq0WY)kH``2Y~$qy*-19XKWgi4O!9zTyH zBEZ5VKdjpbN8Lh$ThQNSAcR~m{N2AtVUodz{`ax_Ze)Nb+}A)lAdn9G6oC->8#}Fk z*CGM!Wp+^pS$8tv1FXg{05J^MLmnZt1vdZE3M%d~aP+?NzyKw1f<+X#2&F{`CFsR9 z>&m;mpj~!fth)=ZECmIoKrTYa{f1lFr$<{Gk~za3WI!n#A(jw`CB*I*LV%cu{MEm- zoqYGh7=6xrV}NEjf*%3sM}Ykpix4Wihqw2)3EcVx-xAlnux>3JAs!9Jqp?ju2)R+X zdqcHaKvxJ@3*t0iLGz6eDvLYj*uN{tDohq&tLDR1u?zIUV81~kgm%~A-`z&@ zga*^-i+*g?uW$=$P+$$z0)$Z25!`i4Wjs|L_7dv&y zDpA3@NpRY4DDWG!GK7#@gi-e z=biV=Irp6D^FHN$K7NIyP}?kKdp?$&hw}0iY!4f@i@i0&X8$#LqQjEU9`50YFCS=_|)ot0r++K_$7oi^IDVW|i)`YWeEco}D6}_g>RYPW5 z8A~eRr{F2rt~VZ;_58@3A=$aqHlGz?RveiH)eTR~FRA4xX-At~1+{an_S@bjJ)&!FH~AAs?;y&x*OXN~gOmTxNcM zi?jX~N1I-rg6(Wkf)6hxHe{6lzce~Y#JrXgQVKr+=*$|BJnZhbu0pR1a>NMOP76 z0aD^gN<6(SoJZIe5vQ`>yz z_eLDK0dF@?!M4tLv(#q4Z_TE~)OH24y%_xdpqva2gf}(k1pk~@{W!pqv2QJDcDvRleV8E56>#g%;8U4`zEjmK+CLo`UTf!}jFMziNYgs}|8YW@g(EOB&$bcnY?= z4coj{Jv!d54lQccOEt@RW_mErdN7XeisLD`O&0I?=~s4Mezv!wX3yXn z-G%C=rR6F7whN7htYL7jnv<5j)?sO3r5$Rw47JlriKiC(W9^>C=XEppPwHO_-d#`M z1J+L%Psn(9UOa^&>^6p*-*osi>)OLFZlE)p%hj4hAX-#^he=fjVv z?I?C@<%E<&b;DDzHGYSY?pMCbjNh_>?hR#kR^+!7!CT8yi@kqjlyPVEuX|1nJeHnC zmy%c!nqx^b)F3HScKh#g99;kJ`P6n1v)x9> zHfZ#CYI3_dx23Z2#*;a8;hg;t+3_SBI&3@z(^W=??Yqq9R)6u_v($DsbGs~-EQ2?f zr(nC$cyk>`kGbE!^;(X@lEa>EZpe}wqP9G>*dGkNjPJtce(&_tyFQWYu*_wqH~f|x ze){|J6kf3(v4u=Yz4FNI2Uq6Oxk6Tg^Mss-8{;XI;Gof(AKV-H?ty`~scjmwT}8+$ zc*S^XdI*KLdOX|z*Z6$88;qIGh$k~(VUwp|T5WthLypb6dsRjewJl|~!(+*CXry=w zww1<1ShC^iF_|Q@fG+AW+iCG+8cbL66l_l#enS@_fy=f!15;UJ~YZEg@^+iSZQN8XwQT={-vdf4R6#vz%iuc_y)D!b{FmFr6eS zris`0)bCsKMiHGRVJ}!#JjsF=jHh6^(s;oJkXJ8d_slJFST@nJvVU~6mtZML2*LF7 zaN~RQ?wPT<6MsEq6Ql{AmP*O!$0n%yAqh~`Z%&4YqAyBwAx_OPbgEz|Av3Gmcn@2-tD%CL7qdd!}bl-+c%AM^WbEcrE- z4mo)WekU4DSxK*t2Q)8za1R|qv4?Pwkc05v@)T^1CtLD*_Ug5rU*4lxuCXUOlvsxn z`p)naOlOHF+jrd0U&MJo+vBjTW`#WzvK$K0Hjk(9%l?4B?6zt(KYXs#vlL%F9!*J!C9;^`6l?n6`Vv0f%KIe`V+x%1wV-Iy#{# z{0eX4ukd*OKh{8u3JKSZVL4;_n z$Wkcot61C)50oaY8}P?Nn&l!Z?uIz)2I$uD6x>b|FZhP@CwJCo|9psU^JkXj@uVC! zmhluUQ;dyena{LeR%$J$wnfagDULM7(d{uj1>5n)tl|2x2Oj)z`{Re{!VJ5yj98KZ zuL4iOcC7K`?x?=8IR3})sqGHtHz}SZ!ESV(f^CyA5ts79#($)BD?IG5EN2g47wzJ? z>7DTu9>Sk+63Y3^UG@Qo_fof|%xyCv%}{^x6x<#)ezT6Nw!QUvIB>*a8O7YLb6M88 z=xf7MaQhlQ+gp#n`Rq?0>@Ia!mN3)mfTcP>pBPWU^q*LQ{_{V%>&+KE$K009>>*5x zBh#P_;VG10s_`a#`rpw*V$WoiIV{D@?KsUcPNQ9Bo4S%^!Cli#v7d6?P z?TsaS;o;lEuyB`)KoMhrxPrv6Iw%AhZ$vUx$w3!Jnt4YoXC9A z-t#IqtwDJTKHtM9`|X^jL;F|6l+$x-tY$nw2o1hP_wuk5ifYv0=ejm@-~2#VYPz32 z*{oQS1)W8nf@!W%gMIeNuZ=0!`c=|7CH4ev#gSX^+VT`^#~H6}?LYgpym{r}Du-n! zEA2t2<)D+kiafR0@AHo_?kxYax(>JYyilcCt}wr|*BCwahTQ!Jhj;GCNJSLDDJuQ^)AiRtLYLIyRmFSvY~b0sp%PXi0!f^@1eaX z=zei_{gLrxBz!hJ1=AtMA&$Xh?u|2#FF!@!L}ptNM=GGKJO$etW1M$t?Ji~V(tn+% z$Dddc*2j|d@N9Vsw%NwB{bg``y|qrMp_`wX-`ZGG3$-{;!FIp#cCDOza$wiIo;423 zX7&^+=r|o}ah}4PFv57Y4VUJ9|I-)EXXq&%=Jz%sx1qk}DflfjzTKvt#|PawGqaX1 zSF-X>iY1faYv3u^4l}BnkKU?2{pyz`)OHE;dm@&c09&4d?RKNQ!+!2{|HIE{b@WUE zvppJ1j)E;u!M4b-oz>^|3xiMeI!pKCvsX7Kp5#CejHh6`#^`|!{PClA|CG`~ZBzL3 zC1gF^+j^FQt?`;KZ1;T1xW^tk@30JEk8D`bG7L^j@f04}V0>}5&3`Rz!j{;2%~H!s zn;##O4}Dvng4Y!BHV$}Z!txgq3hNz~Rm^Ed$dUoW2A+b`@6qWWiWmHJC}F@whb5Pq zvVYWLf+at}3wF<;-3N=F{>8O(+(lZ+uv^L@BnRGFo|Fe8YFsVOh^!n9&}~Xb;`R!&7(>78xJz&C2%^ z#>~9kMCbO{Z?-p%?1jxPJO#INjJ*TRn|iIhr#R9~D{)rbz42r(^woF@w#SUVT9>e+ z@7c$`ZgyDGSs8AHEw{q73_OK0e2E?GM=wpiC%f)H)NL}mvt@)VgFEA?>CP&ic_p~A zsYeT4$zrBugp|Rj$WxQ)>VdB;yj*qecly<`!VV#12%$H|Q!rg^JX_1xAAa=BFW*Mb zcgLv4nQrkJ;c;$Y_OYYfg0SG}ZD8iIliSE_5ofi5;peoG!IRlm$iq%$Bjcd&b=bBd zoPcc*9?S+OquHTsG;KHW$o^~J?~k$4Jjd;h=gDOaA1L50$FAnsyCH)|uOZKMcI+CNPWtViroYk5 z@{Do!9OE8{3?9LTJmT23pzy>sFpJq~Ys`b^t6ACD*=l5Njn8ktT^XnX(_mE^tal-U z=d6JdXR8Hu^O<2Cnh%{|c`~g^rnL>`!SmLT=O8<4jSQZy21cBy7F63n;G>5B8?ON~ z+^P(>w!%Dk${HAPvRY7hs2Z4?>_9c<8Ejja@*b&hz_ZTRz4^M1OjWDef1lp`wiB2_ zwSA#Vb^Z9i+5r>xje7cXCwMz$RZc~p0UpQ(W;#2Jjd}3+HGF&G$hDxT`|%O?_(%s_ zw#M_<;N&nndyP);v^6lD;DA!_) zTmR#~NB8??+)fYN`ofU1Fl4-due=p=;O1R*o>-b^c8oGR#(4PDv_k1yq5KhxM1e}h zTdCZQ0G`x_>&;-Nw2{Gc+3;}0S!_X3Cr5*=jt2YUalg6WSWgXK{eU-?GCRF(cY2MQ zg92x~ZO(W*qgM*d@U@-cGc52>H!A=;(2b^egc}%fY+F!xVjGGkPH9JrR_+RyyY9ww z2zX>0oRqQS+UOn+Xage-Wg{hyV*``Mj$$J*ef>9^I!|x~;wkf@@?u-W>0K>R$r3d| z0%}!9t!jLT)FNGTq-!!T&qe0B^<#9q~qQc&HngiR?f(GI)d=m?n078<}@sn@)<$R!80;wA41T)Mm%cK@?bK zBg;&{NgFw7v*X4?YLTdrM8$4wrJ;)!imONo8C#m^TdI(qiUR?fWuM~Pr-Tupk8!^e z*sruU0loJt{UxAS2^5GCZI$Kltck~l~P41Rh*KKQl)FD(nkW0DatX$g8~;y5Z6~wscAU2{;)-ofc`NNVDTW8`bV|S!r!pl9P^U|st(H1F;ulGQb1W9(#VXVc{aY)cx5Y$b;Lj}Rd5ujHo43fg2T>`cS?OTH`1n5<^1=Vdqp9yHU zE!YJC>Z2k^DuQ-w04Puyv{wdQ2v8qYK}S_EAOY1uwL0jNfUChaSA(6fEu=nf1<9?T z9RccNY^d$nP-oo6NG&FZ$mEb+0v3eGf{-1@#nhr8L<&N7TwkL=S%{Q{?6?|0fe~Rc zB5cR=+!RO*D~Vwz0`#&;VS7^8D*;QxWNFxe{cxIPV_4Z3b|OHtYz+6=7=8!=YLOcz zxnVm3)FLeu4svzZCOw1`h%`&SuI1|<1ZdHZ=*}a0 z(Ad*LkKO6EI^At-Z>4)bbu4?3J6u=N6&=!fXAi}ozX05BH;oDZsi9fX0-$8OxktkG99~YdHt(EerxElWW^|1F+OCd=};RPYI7lg0Z5=Ehgk3t zWOlsKJvjdjZ<{tW&uqIo+a5%Q0vUF9hF$JVY_e;c?8fkgT4dWj*><^WSY~&ZnX**d z-PI;wi0U3<>eM8u?j#eiNYxgp@>N!-+6og;sQL<3V{k#sQKR~6RJrTap!yq3z)a0Q zQl1qwnm9mTj`giL}m%7~Nm`JdQ`S<0gypNbB;b1xA^H_aU7{ zn89EDp^`n_)2jEjiK9%ORmqF?#;DiHK7F!J?iUvM^db{5#jj8C%NC0Q`l5gVV8j}@ z?qn9N2Cs|lH83J3ji4|b4KN}EjbJeN3@{?#j9@U<3@~R{oEf|hMwS6aM3WH|29g0L zoduD>JQy|xm`WBh1{sVJ1B{3aBPa|C1I!8*5C-!UEMBwug{l2I0yEmGjE)X#F**z| z87wjk=6TK6Gk(Ztm3KoWuvoP(R*m2KPlJcwJ>>nbJHa^Z6Xg^6V?FKea@ze6x}Z6m z++CWYK=-x%(%$S{-3jWTvo6nBS4YXT-qoYtH4p&|MFRy}$HLGcgMnv&8OMUoAcJ9M zfDxf(1cgCmfZ4zT%3vN0Ap^`M7Cr`Kk1k z&)FE|Y)lyQV2~ML%29gKs*EiXXDH;l7+uLT_??Y1xl-b*q+51XBwY^QX2^gZb8KTM- zNot#5s9{Mi$ysX{cCXBNaAP8W|2z$Ph)vks-}8T_MvI6{pE4 zkZvdGb`{4t6xe7d8|^B_1fjrDJ2`4sao&*vEq2mkSMe|e1u|8Vsj4_@N`VTMRH!PB zl_-#`kz`Gk#!3YmDbQ4`S*b;>Mrt)x8t066kns*x8pZ5#kX;TH$0#(*7$+IyRHYHf z1}E9zRHflWnUj<`Ra_~hSuQ)tWv7a}DJYQWB8e^)_bX5!-9^$}Djoo&zy=rD;8Jnb zodT6EQt480!i559Zj$C!apwmG*0{+Uw~EWj6sU5ODz}QOiWF#clSa3SyD2F!){0OqGX?5Aq|T#ah!6@4^^&1p6^|BBAl*ySy(*sOrod`1S?yKv#0Uj; z`^aveio0VeaK=Z@_*9&Sra-Enr218CJ1DTjPj>iK+#N}Q+yKc9sJM@e0{a4FUqHoq zPYPTKkShTd;|5S*M39UKs<=W(fvG_x z6bhUPlQUrz2OJcb5+PF}Do&G9U{i!_il{hYPl2)sDT}Chl!OA!5z-t{F$7At+27B7 z=H;RXVDd1-{f7+qvr=ua(S6UxXfsGHiru}6qtoaZjtXia5rRr&#^6)HjAwzT&}-*z z@4Xa!b-;tbOtvbMqczuGE|)xXxoPNw(4We;D*4vdn1^0?icg>7>mdQ#efoA2knGo! z{j$a4fWA0j02ty5t~-{6w?bza&0K!|>yOseCDqljhmF%(D$ZL;7gSY+cGsK#Q$QiwS5Bb!iS6S#W?FV}~Iti=-vI zVGu1Sj|iM4nB{LxZfy8G^e8abW0dRB4g*Hh0!Bp85_vW`8~c6m*Gvcp*fEmML zjbT}5O}{5;;x9FW2)(~zU#Qq8f2Rk0p#vu1tS@xd1f27Q&P9QLJgbyYMcXIf#tW=U zLG+EM-jjWLvadH@mjXL{`VJG2;@4CBvc-~sz9e7(7zhn+B98?@LuXU3&&hvd=9(v< z*L*9e-wGPD7ZjKr(kF)uVCEye?z(Hxc4m6g7CC7%ra-7^q7q3|3;;V$a6J(~OfB54|&E)z&|PlRZ{tPxLLp zaBIL^V4>D9&tsi?Sid~d^-sW@v??c~l?{enW8QeEHIWH}tO2u;1z1CG7*Y+GEEY}; z8H}I?jEI^hC=8ee%ncSS4fA|0!lMBrLZS%@dpf{~0BC~2*k{0qcxQsaz929nyqRDY zxqq7Ym)^6V0p^@lITsz>V8}CIerMs%L>3DMI0HrmH51gHW4Ak|J@Cw*VaQhRkkn59-_snwWQ!+>YNh#+So55_kGCO;Npn_<~7ni(*g zSR^xKFnAd-B4C-Iu*(XJh)*V%Yo0%R&~@IA&%*s&3*37x`o10A@kRMVfBeI9{VBtT z8+aWG@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98 z@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98 z@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98 z@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98@Zp98 z@Zp98@Zp98@Zp98@Zkmm7yM{j zfILU7_M_1rK+D`8+ARHlyy2oD6loycB`q;t_bQCCX32o+sdfL$Yp1aIUW5W9>Rl6cqx+9>5nKYzh0iW|K*pUtkS@yNA(_3Z}O4kB}rcSDr3B4 zj0wo_k_;2D)=So!fSq2)PScRL5pWz{1K z2a8PknIvyf*@v$HQ)^Xfqazm#4GYXk78VxsU?5mvMDSNZVc1t-M5tH6V3b#2Rl_D7CdOwcR5D$87D7nSe5zx6GzX7T0a$y3K*h4fHCFHqvMUnrxmX zTST&GvbArr-6H|bw)V{?pvC5GvFT_*=Tmv>C#_-d)=vU>>xV;enuWK12+)G%*n8#J z`yl|cwyZgnRylZcC;_}Vl$Jesb0`74Ih58xcyovVz3d9L?+SH*1mvr(d^Ln4T3Qa? zU`haQFr~E=-e5`qZ!o3B72aSX06(^~(?MqsX&r>Opc24aPy}d}N~gcl*$M$#Fy5p} zODDWZm6lF;lPWEp@FrDSI^j(!cBQCO-lR$ZZ&D?IH>nuVi)P_Xs zss!*R70+W*AG}GG)?;{+DgnGnl@@4tlZp#8^a0KHkog`5F3?b5p~tn*6EXpJFZA4t z0KF`4g-rmo!U#|wxgJ-pCxjCMGz)K*C4e`}cn*PD@MaljOQ?_EJ#ByYbe7hIcsnft zyq%T+-cCy^N4%YuR*rZ(ZNwU-y+yC9+8e?cMYJ5e;YNU#V}vg-!q*z(8&eD3k|RJZ zvV5T|Ut4K8iZ|^Nz?*giXqIXpsiqwQAy!A7^0re*OIp0~M}S%^ z^}Ck(Ll~8jI_13q1gJ%kzjcxSZfO;acMlMt7RUUqWBw4vzM(#Ne?bCxe?i*HI3tiS zBXAc^3(_pS10eyt10k)o@eYKv*2X&!c+i*n;2j8Q@r`#Nq{TPhfxyK#TJ+pdtK3jW zTqk3|gSnwcCE$99Tn{;Los3#EhDf6cXbOdzLTx3B=8(5Jq)Wh(aN8x}&bYKjeJl%; zWzkKB6u237-3*8D_!PYt-m{Sa-m{Sw-+0dk0qSE~M4uKt#Xx~|k-)l0YiW6o_kARQ z_kARQ_kE-VJl^*~fI6*+JX{fZ5&>FL-WkHlKML^9kOc6~5CYW42t71HZz}CK5r@+cU+m+F+Ot?J*hO;7~yy%)x)AcrG zeYC%U(dEHZM3j%3W_ns@dU|5@^hpfb% zM|N5eQVT-z-L^!u7Sn#bJCW9RqWkgay$sj2;kxW2P4}kh#%eLD3BZdX6a>W2kJS(` zLN7otC=~$AOePZ`2nz}W08_z40g$P!nq5>^WO)|@AQ-*v-|lYz)GP18cBs67o)<8-o>8DUpck8fnm~t|KrfNiLM^TZ^lK)Iq@bP@ zlzpTI_0%YUf&@^IQA~^gouT{yFo&4*05V^EvZ8p<68ed!g^~ZO& z8uE8oip;SpIo9@=hni0C=@Wc?B%siz7n*>Hetn`}wwNE#=LZY`MGjas$pj80XIDa< zuY?}Q_7YVNpzyPp!U39o^!NWhGVb^K_n`30^!CeiW2F=8X~-iK4n(FN=ieVx|MIT) zfvJj7s-la|c<=@op>!bfpvVC*)v+LOfF=0a^Un2wv-^JlB}miTrRm20HWWKx*I_~j zm}k+2Pp7YWIqd^jM%rj28*K_Q6gXugr%XVSLXs5OVxdA7nt-`>GS@C!Y_^llCg8N4 zoHhZYRWe$Yv#e6dDid&9CAUq$N{y_HZkeYg-KCLTCg74rE}4L-4l>mtU!}xBN=(31 zCz3_00;C`yTa*Myi3w;7kVX?QDo92JEGsn1I&_Ov3~jR4oDKDpM>$X5q$rbK)yGI!p7;dn%Gz+GHf%KRs7M0tg$jvqg8C!C2+a|}yg2F++viIXJ_Bzf^ll^c=deg9 zL;`t)_=uoTb_5t9H6j=k839HJiwLHw;n#{6j#PdI%<%QRB@F?Pqowcp+a$0L;;inlqjbH%rPdVA_xnrrvM`qQv{WB_mN0Vr`6xV<6rB&d#%^#Kn|LadQWnS>wCT! z-8IQ;Eca8>G2T97yicHe6kGxK)0o%_GAOSCjF40j6soBJBNS8wQ?;{VPh2nwZAfVstFQZNq+qW~ksPy`i!I__gzzqUUq^nTKnV7el2kDR9j=b3;EcQC^( zTV%O|S^op{&vMH#EsEW3i{0|6yXBtXa*ym|xu^efkCEl|SuX#`Ytw#$Uv@!AUl5X4 ze#=67Srqv9Tibfk<$|B#x0quO%&{A$c-j@dbs_2^?icl3;7JG#7r~%<3ot^lMKE`Q zNj;8_-}EyuHCCl2`unx>zw_6a4{!eh&Fh>PWll^dkp;$w&GDo;-q<;J-_%I+`1;$w zfRl+S%c{(>8t(DXFfc*~M&uzqK3sNWd+JbN z(yU5abnjmJvMb$YmZc4a$Fc#|VZ#;+yu?H>vQAP|-ml8E_)RV}vQn#sDLvVg!RCF~A667{Q<<3^1ik4n`0b z6o3KdJQIIG=HdE(maVtcj)(7IvsKv~tv+aBC;9YAzMg1Gfo(p0n+cfg*C+dBi-iGw zVZZ=>IB@j6|BioX!aX!E59%U0<3U{{fCqJv03Osu0(i(43E47ctjEj;1NkAfQJ{603KdM0(kHc z3E;s)B!CD0kN_U|LjrhM4+-F5JtTm~=#T&&l0yP`NDc|$Avq*~hvbj|9+E=>ct{Qj z-~l%zfXCO603Iwu0(h_t3E-hHB!Gv)kN_U}0)dpGVclCbeKi4Uw%kZKH}ViNxY7lm zkkCRB6sjNrBb1K>gUidn2%RIrl>I$t+`+;JC&$t2)VlOqmr;XKpw4wyolBk(u6OD6 zCW|rdHe=k~uxK<(hBuhuH99|!bza;M+jGlgxQnK6`=+o_$)mColt`#42`{;yyDuJp zvuFxb1X)%k%M@8)j87k93M7!{)ALNgSie5jFPCUeK%Wy`j{DS_-gc$-PBL8gN99Lj z5C4eLtDhhLEXXN-NU)?=71@7VZNci`N(Gb6X&OX&%xQykwY*j8t zyG^JC1>S`IlejySega0wJqhLq=dR@?mxfM-262kB^^|D)M}a(N>%1uN&EWl81DzVD zf|DCobY5UPFrH4BP9-j_P+UOW%v?<)&s&I!@VPgP`qE%ojgsMd0X+g4r30c8zc*Ye~ ztKe>$m|~T%w0xKM_{m@P24=vIUl!_97BV_rs9ptmgkqJ*)G6HVr$HC5&43FpiBXos z+=JezlO!8SvKc`MP}T}eg_KpajBD+!*4lgHwkXuKg6owsO)K<@F?xUz(p7@O4ItoN zC{;z>*ZJIazRtKe168ZQiBPH%rrT~k+dY55BkAy7HahQZbUua`rod=dkI}Ay2%wx5 zI1v(7f9bY1nw%YL}B57wGUm}wB&G987Y2O@Q zBEo%h^s;=32p20Uz?X<{0~-bS5)t+vD8QG9aLt(le2EChClugIM7U3k0(^-GYZ?mh zB_iDPMFGAz?X=m%~pJgNZM@0mxypv1I@yhh@`z$e2ED6R#6MSM1=JW1^5z? z6xe_-5lMj!_!1FLV9+dliAV};z?X<{e-^diOGHv&1HMFr17T{xmxyp6OaZ<`g!A7N z;7dd}f`lw=iAdTP#g~Y%FGwx;5)rO-oOQK7@_3?W9<*Ck!C+O;=y;)m9engcwN8BX zs8G)t1>-0ql2<|kVi=2i6Ws09xx3|01xY~ znqQxrcrs?!BAD@*hxRzSr$Dl!XR^ZxB+;|aN-Z^Y;Ziu#wnJ;ZLz7?Z2Ca32 z2}pKCk{xoNqu3ECjsmD&2z?x(SST(`z0Xlw&r!Q$>xFd?yBj85h($!TLSTeKp`g00 z`fl-~r{7!-Oi_$d6ur-x^*OnJOMH(p|5E;C`~vUJer4wKw{w?6zhaYB*%VziqXio0 z)5n>D78LmO0uwOaua7rHF~|()nb9Z)SJ(aY)aa#uSOMi3W>tno2NWoy2#k^E3%1+92>nArJ>B=c=3}dt=KwRss!WMa2;i=9V1y8&$kYFn z_w_fkXXe6_of>I1HS#cC2h|ZFk5EJu6lx&?BlHgilmE#(LH&HMJa~0x+at5>^3J;q zdz*}?umY+if)k;PD4fLa|8~^uiuU<7%6y@GVbl%OXQr)drp+iJ1yw)&U2;_ zWEw%v(VTOlBS_SVgfa_lNKrBjmONMM8>Br-w@5{e|`AEQN@VGGZ&^~Mo1js(ET zA*KTs*D%_d-s zpNuh`A|Fj>@Vo$5^%lO2)C4%x>PM~5j6c>!RbBeKtAvER{QzsaK9sh2zDma4+p zxgxr)h?ca`sW+M|M!WRUE+Y$SX2P=*I+@}Tp+Y7wLKRamsD}xkqtL*_JhZ=J_ua8~ z!I>nSg#jl*0#lfx`Xx9KikDF*CHB@O_P$unp!_8`DQD7`!qS3bm%s>tOF^NuB``wH zQZOiF35*c06bv4d1V%_z3I;6w;gI$p)QHugsvpy5n7UhK^aM4 zgmk1}P&E=5p%f{Y#$LULJ^b#Z3h1IGNA%=~{H>%!dZt8-{kAA42~LEBq;P^Whrk?U z!jXcopj0HhkwP9)Q1p7!?UCvBp4hBCKKG!Op0J_{oQ#N3Mnr!>oM!??C`Sq>C>jZj z5Q-Gcj!&~UC$F}jfcr`c_Dl-OL+I4ty{SQ?i-&TO;6zAB3Mb)-2b!}>x15C2E-ewg zB_fZK?nJuXi5TN>YB5~bhetfTxV#O5==?6fL7qq|36`D&$S(ebm4Ib&7ML_Y`= zpM*TOneZffL#at%guJAnP*@TeAtospl#v8RNJk0=MI(U`LXm<&iAZ3CETmw%_Uu0>0Y6Q;ljeMpgK%Bf-N`#rklJX9nrJY82rBMzZxB)peGC{pC1riUYe z!;$VdGl?^$;9e+23e#75^((C(*XtrM%dN`t=&T>gN5a=DR3k+m6pVyCLL^c!KR*1% z#{)jN$h;NDD8(ycr?d5I#E;9dwz3ip5cL2ox< zrT+>%i>;xKTcd}`9v#xj-_m2$707ees+^6k#i9-+FhYA$c#E+VzSnMk{x#?Xj0i_Y zgyj{&#Bl4x=+<;9H!ssL0s$@rJ zf~foPK6>z2{_?l@^erY}f?uEDmo4T6^mzdTXcqdIa9yE^DN3|u{?(1W`<-nJz+EU> zx*`WEnx|;xr}8p>Z9J}t~XhXar?)(<$#W<>BpVw|3f;rN*t*n1Cj?)?@-Ed9+EU@IT8v+VcMadM@|Kmo4=8 z3Qb#~le}7zDY(xVuQtX6WO%iVD1cIgp=c;DLMT))2?bw_ zIlr}I3!J^IQ9IPA#>NB+G^iaKOu$U7!%R)Kn6Gu1Zvrx1dZx?xD5#Gdm!1;^P?8i1 zB4kKKK}K}Vd2!eG>K$OdQ@%6C+wbn`*8R!1_TGU?XrIz~pCXSHlI)QryRjLUT9kS^ zlzQaZ@p_M5?=i*-Ph9TSkUD6^?-2cWsZCvKI!eCGrY(xNQY|IWL2p7;JfpWo;7`=0NdnYnM~%$YOC#(e2go&ONT%*Fi3uB`_*V+exC z;Qt*sxPQl1{13?h1UVA*RnhH0i&1s-p!UFKjfQWr<}F`89sW~w@y+WD^Qdym-2Co< zW!c@~8R;MERL%Evj{ZSU_{C0b+VM5MI{rXI@-JkeB!WuDuD3e%yXR@onbKd=rY(D9 zDsIqMn4r6?y4fCi^r%F$ql<8_WQExKwi>LnH_};a* z!Or`Gk>3=>Pz#%!%CI#mbI*ldPAxIv7Do-Q{t;xWnB%X)J`nN5eaEJYmJRmTo$_@0 z#Qln=d5-&=f9K?B^OyUBT^>~{P>;#_N|kAemq~5DzC6cmF!jQYQ_I3COYW1`WO0voA8!(a0%#s{@>pzs>Bz@{KfhEG~9SzjDdB z$zOG9m=lw&0(=veuij}8p>yq57^YL)!<&#Bw% z56`|o^+UuqS;MT|b8}nc4t%HI)nfDvZ8W?48p$}6lzVNpcTQyUvAQ?U<8!&6&_mJ7+Z&RM%!=$@6Xi`=`! zR=4TFpzqouTl~K)A91z&o>esag#GIo!!IKLemFWhy=H!u=hT4AB?`Zu{+gp_CMBgN zYhLGk&6QCz&_82k2~9P@%D^;&YEoOZJK1r2a6K zF-+|=Sj^1q)7TtPQ!?zoc+-`|tM;3H&>k}mU@H_({=0?!pQBWw#m3{K24nrBxiILHQY$V_RhXcAGq9ojRLkx%=-oL%;rGN*ehYDc{5W zko}9c*ihfcTvL#Dll%b0UB7*`D+Bzq&I7?=O!q8V9V)-$OSJlQ)bdSY-tHB@SM5!S zapAta|7?;0dzRX;p|pd+ROY5T=KYVWLu{=XGZ{RsQ)js|ru6qloLSVrr$en{rq#pU zB^Le`in5nX^R~9U^RdVyJNWV>*T2MXQUF1UCo;&Uh5dN9%N(j zi3b+`L@71sU{Z9#z_sv`Q!2*=-yL`OPr#T%s<&?=C1=itU~1u2gR1Mkr`O76r^NW4 z4mfr_>|0{pr0k}`6VVkjq%}&i3teT`}X9!E&C|mI@^5sDdN7YBRvvh*$=1N;n8o9k}tgF^EeY9)2lDg99b`R&7A!Txpq&j-nWG6a* zKT~S?a-HSd`{7g0 zUt@9?|J{A!^b~oiE!sxCJzm!~hUU%Pe9|v`$;hI4%}znt4Y$7@@->a1KipX7f3NtA z?;MX;XM-1y>K&F(n(QvW-u3-Gp*~_Aao1qEO7@T0;Q>KQ-`@_gcT?NF#^?Jg)$#)$k2f%F7te~3y0dArVe##y z!+&<1^*p=!THOrg0iJ#I^{(odE{{KIKOD4TeE)m%}^4->w0d z$BRq#&2eU@scqcbGu|z8g_HS$8ILq}z43~lUZuHxsPaYVx>GXo4;`Ifvaw7qP0 z&H>8$gx2Y=ZcOqnJp0+)apER<>aeYsg+`el`sK?*oxT>HV9Su{`lDFXc4L zVhnA^MpAB$Q`mDmG{^9f#KOZVe(JyGZDA>nHQP46N}u_AUXdQdI?mfOd}_>nIj5?Y z!pU>mG^v@zP9`#^r7Sxh^4<=5J~mpny|~Pb+jt0hSFkT++Z@+mYa`Az8%Nu(7rd1m z-F!UOL^E$~-n3$~vzynCl-{Qn=daop4_HkZ+;e=-pV9ERa;s1kJ*&3F5|>9FPwgvQ zJtD(gmsEtumyEZVUQr(B?fzBm3}zb8zA;TFd+YD94OM<9eX;R%WXccsRg33rSo%>e zDLX$?jOCr+Vn4&icX^fVq}@&ps)6t9J)U(An^`sQcigw7cbrkLvSUN*_JGuRXkLP| z>s|GDnE>NAbrq&dueaSC>4~is~=O29Qn^IYmZ;ST59rUR5RJCzl@A33eLGJVwd6%nG zD|T+H_<8N6*PlD5b3>6C%kHZ!oH(*E@9$-FdzXX- z56S!6S*wNA#5#t)aoIbX=y@dPZhf%hnFqJgPn&$^qf4r&>75!H-d5fp!rqQ(6nU0) zUY#cXWY5GWWfe;wN^R-G9>vS_U1|wpz8t)C@s}DqTDKxg?#F>&hnd^l!avs-eBJGL zD2exGnB%hghx3J^$`41|9+^zCX;)U-=U4wNJ>F4Jv_ijpS%rSks_kB^-5~~OD zrgtAm8p?6bEq%3esfFz!t7%rvB~D{sGT(LwwmtB!-qdL7`}>yPsw)~Rf?Z99%dpGm zo9Yd%&s1bQSa`Mj&E~C6OWdou(FOaYAJT_!jva11>uj`TU%5+K0F$j!-0)(nR{NJX zvI^=`o=Iy^IxcrRHokE8Q%l!P{LrUfc|j~Dc;*S?ipvLn>g0a5+~EBsImS2Vh5Gq- zO-?tg>zdtvUfSqtep!0c3!?_9uvP=>>WADZhtP4`RvmA?p=mSlyo$PZyKcp@hr6~u zTx{g7V^DKsN$ksnfB^fGnYs5*PoCZs_)6vNv1EB^UFSZrfRqVNjnx@u<7b4fDyyek zxf!L&Jd+K$_akjaukC+(^XtRd6HeDt%st+3wJW>sy8X%*2V<#fv*r6*v$}iwCzQwU z9I#JLO76)po@!%}Kf}>}#Hj2EMFfVO zcq?O^GxJQ%zC-hxo~8eMN>!DsnP{Z3?DWjaFX-X0eLFL3DiV55Z(4HU8um(cpMi&h zk;L^|rSE*2;xr`!muTkA_ZmU;b3pXS?O+8t<(anx5;@j%Ke3+hmK3le+Li&|Gi7E?Qzs%$d#&q< zDPo^@GM`lJSbODq|J-zTlv6{;)xH~NGB2rari?DT7P@g~_=VfO`iXivJ)v2PADcxc z{-7BfI_&%XyJm{RDKo3p<4ZmC8q21dBq-beF=UTy8P~Qn;n1|jGv+HNcDb~Cl5oCL z;!tuyQl_on<>b42({#CIwVw-)_U_D^OW{rYvTjYX&eu)14GJ`V+s+RdzL^}@o}4Y_ zU1v1-*<;5-x1f)Hhdt9~iA`{FFMcrpzYk#+v$dbG)X)9tp2AJq)6pH@?r|b#M}E-ktk-T?uRRji zyPe#9M?Kr%8t?X-S)o7XE|a;Ytn6^`UN6UChP8!x>qjcHQFQ+O>t5+hiLHgYLa8{PFhr#Z9JS-jBAH z`8m8=td#$sYHCk&SjPL3Uch~&c(R=o~*Jim3C)gRmt|v0Jl--=1PsgOMzf&+? z^KPr1lG{$h{R)%&I@FhT*^jf;v0hs}zvXw}JeTCQTd#*N+0NCTIDO|@#^6s5=Oa6Q$uhnqk{j{ZF=U(|V+lz-;YR{&arnfFJnJQj9!A`8I zW{R_4+xyu?pH@xz)xw@{dtpi5@=JFYwmq9&ykyBu}`t?f*IXKf?@wdJ*ud5qk*qh;ZywGnyW9*>pvj`heH zadx>=#!jxDHPz-s_vNwh+VgqyO-$UUU6s0?>gVb^XI@m^iP68m+NY0>Okeq|>r-vl zuLGlnX4`yYr4%PuJB|LXDBPW}{+Y|ViIua(4=pc!`bzHI%Om@Z3die~J4@+3V3>}j zt2O;BlCRkHuKL!}3#)rKp6pP~ta)s7<=4jHM9<1$XG1N6%BhD6Pup!g^!Uz`5wWko zbbhqe1eDHgKK%4+$j>63C}MrcfSJB%4t} z0_rAWR*SbJO`f^_j4B6-<`Xk0lne?!eL@1F3qgFi|5MVFGumogB#%$@Wgxx`{O2Sj z!kR!?1Lw3fNPnp^rlu)@`0}Y)D3*mPHlu_DHak&2a-bpIW;q$!FTEkz*g|$b9l%~1P<04P_)KWT9O2?NxArY23cNMf6{dU-L?dwsT z8qcRzvyf^QP9-E5fH93f$up&A}meGnUIRe1t$5T?n}7H zLq64)iui)D5)xtQ$qL45HvdJz9D{+S63BHvwGqV{QRQZokl>T)jr6MF$5ilEm-Y2Sa=?d_sf-UC)7C2WWa(U>4L^T0WZw6}iHoH1x%Et>o{8^ILISgkx=3oTSJdUy4c~F< z9X>T0L!vR9aN9y+#}gWTd%n^8(L3U&xzf)Q*XR;kT0M_J8g8E0{% zlE0NIC}I^9d{%^nTWO!`A(vMRmOD!zr@&VFh+-dsH9`VwdrlHgd0o~l#<*DBZCoUu z-|rX=8KX^XMhS_qG{jfJAud?^>rKe$B6o45p5Jo|MXUvEVnV{6`*Zc$q{CeIiX$)i ztR{+B6F3kE30d|Dan=tR_xEy<+x%`LSV#m5UzdbLSi0k8z;09Z6U>tu*6fo&LiyBD z6dMI@fskM>?$963=r=zfx{SA$UVpSMLno87`8;=RT(* z&#Cy_2?>7h#c)>ZN3|3~uUenwB851WTXElbTUN0^)mthfh0Q#r<;XcNiDR;B)&Z zNFPO_86_l`y1;vE|45s&_f=K|7fIn$zfzH}RNNsG5>V&Eq1tG^l^L3v7sWx2fo1GZ zq4xhvSZ~sy@a^htS7fI%u3}hmKOq@tau$)Yw$rUe#24Cc#y)BNk@YiQ0 zMXZv7Z(l;f^%?H^BujHtBTgKt=Ci6OVpV`eNXXiX8evdt~Z_r3%Y#qazo1-nYY ze@H?C>Mpp5Mr?V*yqM>yTqK=O9bzIwOnki&5{z>p^ln?iy>_fjNzar(!uZr)6zfHC z*Fi{N^}rQ!Y3gNMl(k5`p3OnL_|#Skr4@WmLIUbmVovC;ORQOHtMa(W6F%`ThWy3w zNf8oZsd4P!XNr6C-0tGOjzTVSmru=PA(k=~0yzr4lph82 z1A!+YLGN$imrBv(QJv-8OC*qMe50upEEPnPgalL%7^BYcs@cf>>`}@=&hV)(D3ljq zaS{?x9f>)O_m97~q8kYE4{-~dXT%iW`wPpRV~1$=5N4QZv} z^Cu+2nn+y^2hj6Ty>hB}X(I=@!l(A3ls<605)zDHJ@Kg;68>0N>bbRXks_Q(dc`3& zGQ`G1fXVdL0)x|N2|k-9e2_rS@(spOus9G;6A~DFCy1w4&8oZ8*EjTmgWTkE!zq+- zuuljHxb{TnC0cSTzjJFlC6LqLGkrp_PbfZhLIU1i^2{80vO-yQPEeNwa+Pl}je@0t z^+ZU(JOmfX>Fyng-N#PR-Pc4bc&7kSL*M$(W-8vf%G z5@9Jb*TVU;o-7(%JGiAs0=dMe{y?!G=!9mJkihIgxb>d)#+WQ=UiX!YBoc#VB56!~ z`e}R#T;ptLHLp2u_O&FHJ}#1qQ^~L2!$Eq80L&b2{2!s8R{uTM-!Fmq^G)Vcuzaxc z2?=`N4o}b2X@9L7{dNv;kzziz6+>FVekLTsQej!c-UFSpPwWlw9_ApI`P4C#GKS*E z0wIA_XX1AXI5qHLz&&}Gino~*7}>1>0DgnPnY(m3se2+`u_B}kcu->=+Y@7j1;cNfo@;0}XkXCp8|Sh3Hr3Lt+&C1JqMh>#2s&8VpNUHYcTQt>udQ05g>3Tl9PrdAu% zKnU<+X?w9|LICCtzz0eCtFQzCswt=^jjHD?*Uxwj6nTEyDSR#OO9Bm2&a2xS7)p(k=5RgDqPM~QD0eQ3u zc{EkHdhjN#v~jJpiGm{t+*cIGXzGI73^)fT#L`s-rzE&YPbj6U3a;58Pb1e!pCriQ zfFy^kFGEp~0s*(=@ktD2!5td77@2a$1c3trKe9|WV*>oy@!9q>uzm(h1W@j0Oo0GC z^Z|zI07F{{7-XmnGPHz%K<2nW=0rhE3w*U~8dFi=$-!MyzMeT*a1#aL8E=TGA_(5V zMQVHmOIdKu0$~v^lcgdEnn1Q-LN!ZOkV^n({P=E`vLFHg0m@`=wuT^l0he~!D7K>D zN)J*Va#`$2f`kZ&e5GHrd4jkY9~fIgi*9S)-j-w=SzxXAL zqfo$65@Z9K(N`S#SDeX$YkxD^!%^trC<%@$kfo6t<%}03aGKFju5>7u2X931HwN31 z%+A3b9KBLK-6U@!@EBgK@m?$qxa(oc4zwZDbfjv-TGN-ZZ3T*;%>YYofTaoBz|Ldm8*`9+~?#XNAcq15a4Mk}hCPg646cktN;u4;W3D zNR=@%Q~~|1VXjeyM40Xa-i}Q1{p+opq0-GT5L#}-Y=vRACj5!u@&`7_tRLAHCj5Yg zO!AQ$nBD^#GNngqU`h{Y$UGjYff+oYA+vU*reUJ`Jn<#=(}89?bGu;rFp|(g-I&$tS_;-E6R|a+%V( zOeIo*Krav4keNeL#awYa&_XhQF3@abZWJtlbcVl5_MBl8u-v>+rZ+kf+QN;$q^rK9 z&xQbWh`4w10I5{*R1u(yCEmpnZj#Soq%;I zc3pa}ki;_w{e&`fLmBg-G3Ylz8#4V#s%#amZaO_QwgR;AqssYF1s(;iPO#?4R4Ccz ze*3xP{a4P~XyI*gsoY$V&sI;x>ZxqlG0teCVr?S85EUB|0fI3s7!z)igkeb{Krx0D zivS%M*71LUY6m75JKn7i4fCN18}*^7_|T>b4Xl)gm5MM*X)2{6j1C&sA;RdOsdR`i z{OOoKUAPy2x{5ztxR(?sMaxrziBuV3ug-VlFP($MSwOYr;RBb z;Cit*UMyiCmW9Q#gl!bCumTaFk%cvi0R1d(zsOF!$i^A&+MY$qCAsZ_c0p78( zcmD^dzGDj}2R$!X>|{QlTq$WE&JG%>&9-yG*Hk41tE6yY8V?7mC|DJR3o~{&P))(A zDO`9>z=388){Fz>BNPs_P_PyX7bdjvu#MP3FnY!TVh6$K83%|R1OePe8&$oHstW;} zL2M})U*iC=rG(<^U`#z2(}e)eAodsxxN(5kV?qIUF{WOO=|TW!5StE0;CujVIw7DF zQ|rVGAb^jw6Eo_>7C-=RLTpPIwDSS5Eg^t6@ujKx(sYD?^E8$7G%X0=O^A&PLvlU< zHZBBk8)Y=LGMbJMP)<`Rr)fa|Z$fNs7{&7eu(crohE7xKr0EC&T{M+0nid4`CdB54 zfj=Jrn_mbZ?&1)@jb5ayU8L&>0fBV2KoKB_t{Ozwh78;&;XvSRf)4-(0s-9UeY)Cx zx{eT#N>@##YeN8ULbw=s-tqz9VuS$VWQG84w2rP;N7oSo>gj6rB0wiyy_2pB16WpC5)j30lW#}+2B#i z2Y_dT0B$3bp_a+e5dyLpDp?FIA)uV0QqItVw=3KR;S5Cp;0z&v8?9%k*E4j5fIy~d zAX6LOop2k3yMzGVB#o(-#?*nADV#z0PYB?QI;MCXQx4v)a0cN}MF5a7fB@d)CsX_< zQx4w0@Fs-I6#+m_0RniF2-egHmOi|p;Y|pqECdiv8D80N2H})pT!!0dWT`i@bRmE< z2rn&khZ|st4X|V(fHMfU4KH;#K)7ufoZv>|+3N9ZT?pU|!jHqq6$c1E4lgWx0QhkT z;5ORX>g{Y@A>ch*^*vi#2>8rleC9~N*cxv#%265RXu%+x56m3pmL>Xd<=|` zPsSwGGOT4|y-~~&VB`$SJR@@Px=+`=PhUtfkp)L-N#l z5SX=OlNxKR{V2FyRx{+P8G;-I_=y;L^$b%;^_w)$p?-&3GL8XPEOs}`~a zSxxw^4dy_;Ws_E5NCPzF%QdNiw`mZdk#E(cCamO{K41q8P{s{V1Q*WxzaG@e ze~35_G#A;@7ukZl;>X)fyfYpHexRQul$nGo!)Y9;ZE!vwI420h+YsqPsNn-3eJBL< z^HXjj07$t(0KTAuZpc@2QWfdGoU(GecL?|ejxvwR!xnfaL<|K1=up7C$p>{(1>e$v z3G)4%)Zj+`VrqXeLl`r`*K{xr@&%ow!aT1Mt|8yc{~5`qavNcFsj6Xc8t@G@nDFE170+a7mWwU zjsrJooSQVBP)_zSjq{ksgI)>PpmEx1JQ$kcfDfJHL+3%?g9Ax)P7<95Ln0igq;o3i zJfZmJ3!U?Y&V#WD&In*|0vJ3PXy8B!gOkGG2}KQ63{Dk;ClmsFV{pDPctQ!TFeWFA z$rB0zvYDK0CQs5=#ffI|pkKimk64^XEFL_ZaiEUH zsblfrS&ReUSe$Px9z1$+;5?gip3Q?tFAm&db8fMD@TA3o95yG1&4VW`4z#d2E&uYV z3+;{u)z8$r43?`>L)Jc!n*P!J_Q19HyC-g~ovqi- z7Px7+20$CK2!d<_>mPuIta%_cUzU%}iMO7Z1>A5yL#m%4@P>Rqub(l8WFoKDQG;3= zuVsObeQCPB|DLR1%>I8Ylo70mnLMp&XnL z@oedMws6Q%$d)b?0p78t-~Asj{T*8nVZa>;Mno26ko|sTCJ%M5uz1GAyYZn(`_L5O zEck%F4^8;NG>#?}M-%?3<7j$uG{H}eHz}n_mx|aZrRkT7*yx~1cZe`LX!;%h81Nhb zLnVts$Pq!W%KzYWPzwTw3d=u$hOGG@RaYywb!(>E)hgpd%cf%4A_>74RP2Qa&_~7k zL;!yb^B2kg#bQ{j2#}9q`656&hP8_TUNp>0B)fN$hTRka9@DVLB0xJ0YZn20=$Ma4 zW-f`2C5Zr)bgWVY_(I3NhyY*d*jEuCfPn>wB;rySSc(Wx#lWgWfNBO-EdqRFVBbW5 zFeVlzlB&yQV%Z`<6BBC^0sbb?7T=K z?iL%nB?9EIu^bVgg^jiR19k>ZIA1 z&ErPKXgXuG`9h(HCtcB#K1~SlqAPm+13q-AYBkiQwSaCmF*gYwRuW&<`E=RU#+GR-_$^@k25_>PiENP~H`n9c`_yk>Ht{r__;Z@9+@67rJi$zaKcMVt<|ArNkl7A`xXK{yQ*-StspktTKkcnj503 z4pD{ITrj2={BO;{8Y-{{$hs+VKzQ3&x>hXR2%Zx-P)gS-r5g!F-(~a(Wpqslz>pe@ zh^(z5jlr@ipdm}CNR7%vgZY_5(tp7G%4oV}G{MG&u?qO|WLXv22Ct}c-wggfuz$+| v8(iX*?^q&NeC348wzLNPd94Y3g}z3SMie$ckS3wOUkUw<(**w-{{8(wX8goI literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/version.h.53889B59D65786E6.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/version.h.53889B59D65786E6.idx new file mode 100644 index 0000000000000000000000000000000000000000..81992a3de4f3c3fe88700070ae64a5bf16c53eaa GIT binary patch literal 592 zcmWIYbaV4yVqkDi@vO*AElFfyU|i>N`!{v1&}a&nRI;mgwwkKv-yh%oc4rp`=C^HePBZfVv`^*cP2X?-ikE2K zNs`&aD-hjs>vi}SH}3@kTQ(=O`z>0Y`+Y6n1)i{@hHG0`I}KRYC|U*RuDa@S;~n$$ zoMOpZ&803Zhcc~&BsSKY?8{76=o0n&+xuB|Yfa6Db;-5omz+`9VK_I)sNU(J@rzx5 zy!Kf5cky%?C>y`{{m0Ga>ba@y>$|2{&f&dvrNDOX>7WDU7r(L@UwFOy{H(vnRul#L zDE~fe)Okx!J^NB%%FYDWjWeG-{w!sD+s`day3li0e5>Syu&rTAeLe9%S$-Y2U^#i2 zz1Qy>#dF=-e^P78(L_Txxw*!T+Sk8sxfyI4etL#~diYbt+xOF1ckkK%_?DLOl@rcu zPI@-+i}0P&Qk#F|!B1y~;>z44MPN+G9z6B!!b_(!JPg3700Y(_h9FS}PDVy1b{0lf zR)(U~wBi_`OhWifmJ7EwNig!T2C@h8!!#ZdS@?A0Gt-HTT&&t0+JaC+;N~)NLd=7T z-*4Qt-^APh2~f2Yhm#mgbx~?gB8XjFlw2$hVz7Y-FkoVRSijI%x9(g$BO3z%!%gv_ literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/xbar.h.219917B2A4786F17.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/xbar.h.219917B2A4786F17.idx new file mode 100644 index 0000000000000000000000000000000000000000..c9eedc95e1f3948c3bce86c6411777cfcbbf26e7 GIT binary patch literal 37832 zcmY*i1z1!|8$P=`8z8!h#Z?Kru66C!-|p_f#O}gI5k(LTP^9caP(sB(umez#5Cl|2 zP)bxpK@jwxZ)U!A_de(M<(c=LZ{|##Gw1A?_a8fC;J~|XlGJbB5Zh(**Ul!ABvq&X zTeEicqUfrURBx*!+4>aB__ZQ!plNYzc}vGrecbHlI%^|`j;S{*dPt0&n^|ze$IoNU zuJ%vq-+1hSX1!nJ|Jn8{D<&pp?D{#4gU2=0u8w%)>AThBj(MvOE>`71*MEKfkm0}Z z^v!+G=Z93gy>?W6^mVQgN`I&hs}K3M zcgc%-baSNadf&(66X%|@8L;T^wy=N+g+r%bvp*5oDD+}jk2?LWKg?g>DRRXOpPZ?q z3Xg2-=~=t|%m|x5{Z`DZS5ds_aGU-!tRFa@T7LSKWjaYQnf7t+lAbS4C9Ph+X6=|c zsZ&O`zqHVAynnW5Yx_ZwO(%`q-1NvDi=!i38mIKktaU0(S>^oVvkUIO=%`6pFI!q{ zSyEb^WXw9WplHBk>#Wr$?hl!$ZF7HB$J!x}{jcr!{@2>lI-FtE2ThfhYo^?#y zwegrUzJG0N8@K;e{@!3-PydO&w$tD4npC@M^*1XWGBsc#k#KRkPvqR#Gmkq0>jF~Z`#?o5D zCXA{z%6{dlF|C>|4Jvw^?7Z<>k2_Mt$}hum!jJY}I^1MPZ^qWWTyMDq}jDo=C_tYznvd$-LXoYJCiGovcB_Y^pW$)$x&TremkF^e|&A4 z`?Y|24)cxb)LWQ-e65$os8i?TzXweH*SI(rYvTo+ryv`YE z8+sS|-E+@c+`?NaJ9lR3y$-Qa4mscLD)N`bpIe%+u9NSGZzF839a+=L`*@r48>e)C zla}ifVfM*lKo6_Di5}PeJbWx}kE!cw+kRgD+^&8%wGKYkQOlB=-*+6{>Y_4gQlj?J z(O{L0`~KbYI-S0>^6tu+6Q5NrSh012$)jCH^V$UGw)k~tm$pVb#eDy@Zl9(E>~i+m zJ7`BvM9`dl9~RF{ba_4};)3O-9-$VKHfSQ}f4w;>y`y^Wr=v|R)J?3?J6Y@rbglBX z(~imAZZt5izNLYE(HK>uUZwf|K9_<92RQcf-u)nQ^_b}&Tb^oXofN-2DBC4Q_Rp~| zwR{!ZZFm0;?Vo+3V-NqBl}}2B4V-j#ad_W}KjMAu11{J0w5t22{?mcm)l!{jk>8R1(z%3b-LLv=4CfBTQ(?&46{EyVdadg3l zl{pKXkNSB(D9mt3v7Pxbwzbom$D>kiPbhKAi*k7qPexuos`9rRy>Eomfk}O4yN`Ik zDPrEi;#o_hn$3E4Y}nH0b~$s@SFE1Z3b^3ybz_N51FQdCbMttiHF|q+xPMy7{>39r zQyvB$_*_0TA!YU3_WLh&t+geohbp1ViLrs#U%&b%-Fw0E{Ls(Uo=?21^1WGRbmm8; zQJr6Gy4yZtURDj8Fa1~e9Wbh^eOfTLlFzS4JKgH%%~cKvez@n~B-gyRy$3z5z1ls- z$!paqpMs@{R)dF!&T2Gm=$5KocJ{h@^>qj1tcuFo-}3!4HZO5+6I5-K`e{sp`H6iY zA$?!XuDAB_drjtx)q_$~Y7A}guSefCV}c(qb@){}Ibh509Ixm8(Q_V7Iyfg_OEkGM zdX9girsW4*!ow0S_^+wi=VG7EhYDwg?)3Z;FH2I)sx+?doEfzf_SBBJ)G_nSwwGDe z_ix)i_LGHa#FD8U-|l{Jq-*}i1dE~_-Vx!;ii=OSwzxg-tCP|4YxC}VtZW$bWXR{{ z_at>j^;i2w*7>b{JIMFzBHPCCgKsJ0SGMqR>89O0<-!4nZUwv@gv_<(3TFu|_sM^gvelI^y>UbnIf9X`qgZKIkvn=?xVej{i zyr$+=ACa`6z>ktoy#mQ+`P+#zTDorVjp(suUD=L`3n|5lJHL0- zZBbfvYTaqC;!@Rzhs9a8d2pn%e^+nMD;MkStrqCzv#&6_LFSrct*k=Zcj+Cw@y5GI z?~sd~ADrr%+1Mm6_N3+4od3<)=rQ@?z#m07zBug|SIf7Z!Y^pwp1V)lk9^Y2?`gXI zyTDG)gSt7-iwO&;k@Cpx&7W79UK5nHwnyJGOaFSRIOb^0#XV2|tIcpa@-6$x&Nfe* zr1a@9x%ZZNnNORVZ!(#eF}O!7ucs~VKN#`O;(tfFP59NZ^6IDCE}LKPG+3FxW@7u} zMd2Y!HJkpo($a1GIj7kpDzavoRjOm@-FoxrgMa$3{W)*!j8&6rY#&oGGoj(*?vwXD zX%IM|sb$R%Zs+$u9`~#9ij8@bZfw5%`h(JSfZ5h><9mEnws<>!`PV0Lmd84u+G+Fi zQee}cBex8+u2 z=xf_C*5=BVh*$1w_x{=b^<$${+ro^jpXn=9>J<&@?yYRP!s%1W_R>AA!qW@pMDBh~ z`g@JL-+%x8_qG0AbT7VEK-$h9Q-geK1&o^WI{(7y`fdZ=`(!ERXb)`4nz4V&lZIb5 zXT=(I{n_@WVnqYn>JPlh+cRI!Ra&v>tIdK3zg;g>&UQXuXYZy#`<_R?seR{I|H-{< zx31k%&$r5r-hUP=N2Nz}@AFIEfkzGIpkc)7Uc zz18b$R?mESZK?U3pu$SI`HSw1{kL}B*!VWYblZB%^jSV_VT$EiDfTYnZq2&Kw$T zle@Lq+6t$6uXDO?8*s3=%@Ws+v*?q+A{9>C{1Z$+P&7buJ|XK zUuqWoZ~caT%QriHI5qb8((dxTp;um64RLJWY(~L^p-(+0ZJrzup4UxUsQ53vd(XG~ zXIdN!l5PD}=eos?+dsjEEKRGdIdvXhhyT{~y@b@2AD%z?%RDs!tcQZayW@&%*ccYM@ z&0nNu)u|SlD)o8M$P`!c z*<mKJEyr(Gm1@Ea|#2Q6^V-eZ-`&Z)B;^JsyaDmz75NSe^>e$8u7 zk4Wxw^lOUU>@9sCvXQNJc_)&DyqI!qY zC8G~jl#V`bbm&jVW<#W{7h=f}SzY%myIzS4cFx;Td1!ne%e?k|P5ZjU4}Y;|)9@G5 zN0SiE%nk2c93FmcvZHhJ8#~Ueu@~`%5aifSjdjkjN`5%n$ z_}aW`WsA@q!`CdCzdPYaW~b;?-XClo;5hSqb-Yd2DYM~NcEu-j%E(ER>G3&q3LKY% zUeB0)GuZ}?>-Sf$aQNWcDZ2ZzBO4}8emiCM&2$?$?%ZFUzT%(8jh0#!%l2vqZ|#$; z{ytb*HP60_c1go^4Q>^ccO2XFUDw!o4GU&BzjtiWi`->9Yb2aFZxcVU{UU$Q(3fj- z56I1JhT0$Vn%UdD!QQ@s$E);ycp`a}M{(}Bs%m9Y+|z0^WKya7xro)N16Rh!Jd?0+bC-RW(uI-F zN4{{3`)DjRs+-s)re~e5&wrG6$=Kz+Em0HGYwGGNr#sHMI)F$+x^^7d#ImQ=(9E2% z^YX^n&-)ms*!10P;~-`HqCwih`RCnS>oi*9YVqRq@n>BY9~j9*|*m(`8b##P?>oGEh;xsl&#LwWLojJSK1O zTbF$8^QMm@>mB($>U;Mtoy{v;GtBM>E1FgvY0{&0lhW9ZTFHi*h@7UmA61%gKe|y&MC>Cm%2C*m2w8 z)Qkq7*LE-eQ{Xk=%%kEUub9ahUHcuc9Gk!3{?|pX-#DGR6qA$@Ss42B(4H|7;THz= zaJ)2X^O&UJrSm83>-1ZD_CHyiv}WV7Iei95QWvw0T?ZE>NLuNuOp=_*ZUsH+AxcK{ z^~Y6Nu|nodl#{xfT2HIKQ>K-UD?sWZr$=2xkdk->mwNZ=@IUV{x2QCgNiWLCMOhVR z`VSyT$GjHOg?Cop?UrUD*Ggq_i0Un)M^!|S4owi!vG1-LM=Z9b(nKb`N60-w>&g+N z@0FrffW0h7aV5R2}l0#@rj-XUv>GQVynK*FWW3^U##?OfmZ;*O31gQ+A8+RwCtTv0J z(f}sCNytq&CypT1ozuv1)$BIrr)jj(DmbUR3VP7y=cr%PGc$v01_pem!XxaQG87~O z&WWSG^8F>ZzyZH18)+q52>DP!4_Y`!ec`%Ox!qbPgc@t5wIGa8(8C;2Us#?sxv)c{ zQYw7Pdj5)>T#?gL=LkyOAQ^OG&*F1;XPRgwPbS?dCp+a0o#{V-22$4v`FGwozh+`0 zg{FjzzsKC%2)l91SYauX6V*^*u*bGm*YgDf`cv_!vn(MztlQx+aaW^!m$EPXs@f zn^uwvS?T#io=@m#<_ICX($1%oX?255^)ovRFx5(zSRa)tNGXg^jv&MlTBh7EtdV&( zRR%ESPX#^G=FapVKz(H+v&|mZ!qycggAg4h&8k~As>l2&ZI^LvGA12)`C%d7WI2uTw_nrLm-mX+CjbT-NCnxXZ z^_}TIfUK%`F*&d#wQq52sis!SVh#0%kT)sg>il9tbZh=t0LbM}1+*6 z8y~8zl^(Hr9wFoi)RQA9byInCgR@g>w?AP5s3=GM@=tI4C$w&eMIEga#)6)clXK8f91ViT`YIai?YDqR@35e8auO$R;!OVm zWI?g@x6ZdbZWpzfN?$Q)zMSOC>G^XskPh~E*Uic5HnS-oC9mU5{{b|p>uuY#_GNuOQE48Fnn_3|MCE7@_2Q%szOyP8)YD22 zS=2x|34|8lXb@G}`{Lyj?M^C9Wl^6H@`TXS;s{dR+%N8>_}C(+x4Bk|XD#qiPCh~l za0IFDzPCy7uPSxqaw^SX(%*9OTTZW%91Wxi@gM$tx3jm@O4+Oe?+JMir^OMZy2e^^ zv}5D=6P{F>!cNOiM*QFw$q}TZ@fNwceCsHWgM+P1q+BNTP)i=_n$CoyWMoyXInHbK z;!uQm48@94#NtKBPjdh3N3QRtaY`#6wS3#36ma`k)t5x2+~0)EegMw zP}SO`(u=&9J=*X4TTWF=ZpuD7@2W={j`ZZm&vvn1_m^do@ z%+AS9LF^Q?{W&rvj?~Ge=EmPkzEJ5?R#Q(xJYlAC1gWl3cP?9)IBMm8E$R8QsCyJ- zkAe;=js{T^M=y@;_G%85o@P-K2}y*Z$`Pcx`QK+?eWy+7o2it(VxVW`D5nRNas;XF z{0E%O`d_2iP%8bvqP`>K9n_VhLDXM!9REA{r`Nw)DT+nCCMVb6V#(1U>R~%Y-_Ual zsPsCEdW?``FswL&RM!HF=3Nh1RO(BmpP4k9kZh;`M}rFZXD_|&IlOKwt@M~R)+;%A z1v8K%NOjlMB|f{HY91R+r6-v5lY)GL8OV`I#R%N8cI=hkZ7xuyBRi|_GV)zUhc!n~ z>e^~!Y1b}0ovu*nc^0%tL5g6oaMTZaX+ZJjR?ow!vWO||6~rF8m7_sTyN(abXuI?w zm2QBpy04%IT~Bk=k7;r6Ys1Bt>$NtK(pg2LHBz+3)R}OUjB2S{;FbF5_}QHn%}Q;p zm0VbxCdfzvOcjn0v|RB`Jk31mI-r)6RZg{;tg7GTZjVdQaa0e)2 zXi$Fmkg>Tl!p61JN`F}S1u{|q)0!hlbzOD7ecX^583k1Oo<%K|lVXU<(ID!<9*1vF zIZ#NY&skJ2LcHLtID%9+R{N=akDDYl{*NvfSk#wt@=|W$O#cBih+4-lYWWiPPE?x3 zq(9{32S_;@NIP$D_t@$2B`Q72I(CQjP}FJF_=y&F?&< z(qF8uIWm$1Gm4{uw0gCht?J)Pq0$RXnnFklbSg)X>N>SsUPadienY#PNN;Eb*njk; zhmn+OR9!Nvt!aSgG-7<>_~H(k-RZjoR?!`DvI7P_M}yMk)684F9%A2vPJPx>hZN)x zTu?cJRCnpWv*p95$B!&}YNc&3q#_mcpv}*bDaFWtxZCCBILC!lSj^7ILqy zKwMC?z3ORGp4_sRR{G6~Kd2xF6)l|UKY#|s`~6qv#y^9{QfVNIdYh2jFi<&yR5wsZ zlq|Flitwk>lPqe1f)qeiIqFw+b?>C-w)1QB)=K3p=tmj(D5LjNj-b@_{>64)lcT(D zQ0Ye|O(!HBh95_e>iWsrrs`)?^IKFJ$)raKISNvaAk~f3n|&M4I-OLxk5)Rzy6T{u z9E7goXix#!#Mvz;_AsT=2qyKD6F*oca5Rvby_n}}v@e88_cLjQj8wqz<7gm__1n6w zb6h!v^DMIZYNZG4w9XK61{NP2L8?0~^QwJcmL)gprbxG2DUrXIXZnlmEK?#I4viqp#?Y^RG?DN^#R7MJ^RxaAS|joA@0zw z91SY4x5lKv?eFRg&`Nii^e`cZLCVoU>SKP}bbi}KR2s!b%Ud~l3%4|m26g=qJLbyLf>=i(+=HBV4!Fgr0%Iq`(|Ivhc& zJF&H2tgNq8Iz^>Vm^4IALSVddG>{(3i?MC^zj!KjX6N-%L0-ayHn}Ql0 z7Y(8BAegd3PAZ@UI5H(ZEwmc8@TSe;qM=$Tjh$66A;EBK;RsUQS&hiwzxP+f!C~~u z&Y~77NFkKZQNR2f=T_wX@me&TJ^{0!9tz?C7c7nj<)3Z)A^uz_NL|?Zm&izojNUFd zf>hU3uDND5^OhYML8l8VKS4nfU|@07FaOE5j}_Cazop7xR(=E_5zti}L8&{bse5f} z|B8D)l0Mh7pdaMq1FV!d8dSB<=kZVH8#|BEN_$yU9|iG&>B`YSI_+J+t$Xe5M$-oX zc2@i3WFJgdjv&>YRReeTv`L-+8ABII++R znmH=<@S5@Tr8aLV1^J+$@4!AV)K|W_7VY*~p~K z$VxJ*p=^Y!id`4aO)UJcm5HMXUd9i_KFDLde^ErZ2H}HD3ZZfBM zKmnCLXVM#Tas#eB91Wxon^%q9_vY~ot#p`4|H#N6n4}yHq=|i>-`ukA`b_$e!p_Qr z5D&Pea0IFD_E(%>KdZ3&u@g!nBnbvHM^NfkG?TJrS&MTv%%RQ1q%krQ19uaS zAnl9ysJVB-OjO-3&oz-guru;dNggVA@ySp!s#B>gp3!z$p;P0jsq?jxFKeb;1<8d+ zB#x}AVk$T7v(0iX8D>M@P_XjP6LKDw9vnfbYx^GAkxkp2^rO=IENGIPB*8f0$b#Y& zxjO#(*pYYAsdPTH)D;Ci==pQhFMdh4_cuIdy|Hn7!pn;DC>(oUv~RghSCNaCokte$Zrq;~KXs&r(^L!R?wrg9 zx7r#q>o%2!vDQC9$O&kDjv&>wzJ0k>VO?wEW%LaptH5&wc@FcLqkdKA_v>kF6kVAr zBbhQ?PSWA-z|o+pW51bvbBSzCrE#o$A3}U!=5aJA|MHZg?AgBYRQj4lEs&D}xan~; zh`P7^+QcE6k;~~lhc$qcoH)T!h9gLI4G@tQuSoR0Mx|~{Y9}Xlut?@;Abq^E&e-)4 zpQ!XQt3a88ltBYjSz#g-vY=0u(odupI zoV!vhylaF^Ij*Eq2Nv~QqZd}iBx!n#q^aEUuY?g1~D^RTwAoJAdN}`nDmI8904gu1F6YX z+q&-8K2qsIDE_K~9<+Fl`o%9E_UhP?&3RO4$C~t+f;yiSr@y;0sXrn9AmwNvZCbqM zrlL<8m0o1h>x5h=&~ zS>wp+iv9X_(cOa)lZvUdfJy(z$sc&_%F#eNbxq(oyI!ZZ(9yzb@Q{#)(61aps_WN~ zv?kkMkL$Z#EB$0qofX6xmi-(JqB>oD;CB7NY$`p?n&5z(9Dr*DN091zpkuoZ<6NpO zp;A9qfmA|L;RehRq`Dh$baHBCO_S$TYR{xc6yylB07rug?6Zp-dEjnWyGryC8#?y5 zLVjFP0}-U%_(I|H=jo%Lw_q)m`Z8%WA<=MB96_pU)ibK09W_=tR2s@E@KjEoLSJz-sDPsCn`w2X zM%mNR!lZ8$*^n8waY|$%i7;gCE3CHgCndz8scR&eBcD{WAFMo z&MyED%`F)G9^yI38x?4pF86}7y3?%m7h#VGE|i#NOf&BX`lP~!w!q6 z^e~J1PC?#5`5g7jKQ#5zl&^Evx|m2GXDm}=gWinC*QjP}FZ0o11 zKO{xDnn+np>Zp_)m2^ULl#DF29dJaK7!T}wGg)zfzDQwBe@sD+!DWJ@L0#()*>`jJ zGvz`0yEl_wBjg&aDL8^uH=v@=HR?3jB>j+yl))REo2q7c{D!|d80vBdBetULw6Dmz&6}T)T zmtjP61nCI8t(aAx=D)p zN-Kx^Q=%rjYo+BdSZ*rlL5C?v7F0}=$0w}o{n_Y5h5jt&4MJ|ft(v1j%-<%T?#`bd zOr@Dj`j(KlF!?!xR5wjz(R15n?f*@sr`bt;QIIe2pu|zX{3koJZK^+<;XxlNSWD&0 zNWP4=KSxmNM&J!)+eSvGmQd*vR{l9c&cSV+BS>{?l_%R@O=#I?^wCPvYZf(7CJ%($ zI!BQ93QV|PAJXe`Mw3R*sPsIGdRR^l z!~KM#K~$q5iKon#jX9x}_OPg43gQLJ6pkR(y>@RD{Kb9X#b+n!nx0AT5^@(7KO8}- zoBrkx#~wVI_unZKDUVekL?wl&=z|JJ$;iA)Gi+Dcy{0ZZTh%&UNtzDx#E!`A2>qCm zBLwZm$B9Gsr6V>+8l9#ub6Dw533&=rkE229vyD@e!d{P|(sI`M`xRtAT+%oioKu|7 z?A=XbPf=+$la|U!DJ=gv8c18$S$XWMSK=A^%8ykbUPj{Kioy}3zjUk5yk}i!w~|F% zpl=-6`R|pJy)dXbf>t-DLi^eKM{Td;M;{fK^thZHhrZ%yAZ@$O{^&~U-&DE=nkrmD z4?0#jvbu^fop?WcK(6y{f31|y&gz$({DM^yN2bI%^?vc|E$h^=tZUYJlyp zZI`Lgi`Dd_f_wxeM}4JPicJl-Wn%;Bf}WM0EhE|Rl*-YdqUBA``P_R^Em$jkVL^8) z$W8@)qUUH((Z0twHCRF>QR#hl`j_P763jo222sBsxHWZQe_JZO!76Z&kb`jXRMaPx=P=vu&B@EN!MXM;uGfvH(pVPtmYm#zx^gs#`mBxo zkBNKs4f+Qev9a^5@Z%n_6iW4AuYzJ!n-qf)bx2^5(C>NQl9G8kKKOM2$ zdg8+!`m%!6^${VDpspMZ>gqGHHF@pd{4V|Bl|>DclQ8&2fg?zD^D56Q?&-BkN2qi) zbif@2J!nvltg4~|##NJ)-)lX)M?aEb#rrCVFLWwLro^G*xGHq4`t&<0eZbB?QBD%! z{5cv(y=D(6X%d!0r4yj|Fd04QTNRE>Dc=6qD7dkI{gvVO>0ON#|BR4la0})LN?lJC zb#6?zAp}wBOo-{HpobMAiz!a&b8Wi;;VVNP(9zFgz9!@~%zlob)GcY%!DEh;hu){s zJ?xa?6|@EEK;@_(^h4me@?jZfkLcTP7Svloyx~s8ktwmA&b{y-*2eM~l}?6=M#$(v zPo5)FijyCvcH4IP=0A_=wTH#LNXSJP(HudkyG&I-xzg5j&~_?)%(^~UPJ-du!x5yq zt{>EGW&HoF?Wpt?JEs^qiGhb7js`W2$vB={k`hLx*I3jOa&iKs91WuS`8R35>CLSt zRLY`8$w?GkQaBn!9T;tD@n}RQm2QOdf2yDd?NW|RDLN`LzTQ^5)TvKt>$Bp2$jA>^ z|8g`ae)xh#0}rg397&&&nABNLoS~*14W#Bq0b^&>+d!p(OzI^kUa*&dqk%NDU&Ln9 zoWW6aNzXbUoRDysdmKTk8-1_dg`P=^xJac_;iT@$=s`P`BPb=&sT&`R>8CopFq*E^ zSq*$jA$*D@Rb4 z>Vk$23K+NW*wq)6q5psEiycQkS3_;tSud0il9q4IV|3VyHDzTt>gyg~W;|N0C z^sAoUEyrVf5S51W=_e=gFsR}gvYO)gcYHGWPq=zwqE=cD=X6g&4;qvsQ;I=le&E8n zM=d(Pq<3i+^R=A3hN~1ugP6|C8-46;Y)z%-nDm>1e1ivCj`~46`*&$FaONDUoCu}g zmeGT@C`Tp~y?@|Kol9<>WJrevSrFE7gBr>s(|ol^$VHV`U^3x|AbG|A(*LZvI}F zD(@wwXr-laQlScZ(4ZVyP|>7;qb_Z>wK_nB`&rDFGV&5mpCc%L>xRkH`K4!C&;L!e zds$UqDab3B{T%h94u8<`wat$qsq}RUi~4|&2Qc|Kf>Jm6WIZlk==9HaDve;$(}bLc z3nfR8>YD0Q;rEp<-=q&Kl|G;aKIsNU!yeog9fW=v4RxCnBu5k z)lb*YMORtZ@iqN9jg5UDIq`v|7e`R)uD)&C_9|;LOL{{WNlcn2BYE&fjiZ6I!{t`K z6%DMZbP=@w4Fx@DP>%Y=zfJOtNSd@Xoo;kx6?IV%7r6IuWJ;VSQv%h~x<5HdrFU5I z7v*Cne-ANm!SPQ zf>hW3zP&Og&8+2_p_RU|x;iL`1B@z;26cUL?{cNM>F3|mA5@t%TTZfJ_H#6lPRcz# ztM8daD)nWjwMS0&z(=nfL8|M3{=w626uy-*=_-v${bj@--V$*H=~!HP4RF5Ito*@B zDotP&$dZ#Rn5-NPDlqND>`Q&ZS7*~@5{p_SBSrB3g`+_Q_AU8+bWVpy*_EVktg&9n z1O(KnXlL-$HasVy>96_jS)#&Hz1&Y|l`CcRI{eV8j8 zL8_Z8HNQCCcwSwTtCbeRsJgD82UT(eB|dsIOZ%D7#BoU;-NnJqK2lC1;XMUMro>TI zH@NojiSr$()SEYyf@Hx=$zrG0bCqJP_ zIWi@lQ}0$IjySkHr_yVzNnHtXh1TZ?QeErUuQ-<Fq7S#4)J4@RsYld$D*eGK;HV&uu=?U?P=SP)vR#V&8&n#^qI%1TH(aVX z8bq~J);T(OM6Dn6l_rb&M?wBT18`(fMN@^SLlW{chESzDQ@&S__izK?sIMG2!fWQ7 zX)~$Pj&-V=g1A9baWtsur5Sr~T=w5VrT19SWI0KOnsPLdnvK|0{c0vD)=H&Jx=%s& zK~#d1Qr()aBJ6H5Ap^&946WWv`Q{te0y17bG z6E~}0^oM^|(epBL9&S_|K{^s|RLg5Soxf?*l}c~3@}JAeb9hO?(IBc@m1xJyr30vR z6P(i%1wCl@bJVZt`T<|&y1%PkPG9JMlP!rw@M_eS3DfiIl^nIT|TPLw_aYC>hmMHO1Bs_%_w^yQ@V7y;U%&yPUYg zNabh{b#mik$Ch<#{5FxYnKV}^z|b?)kzIU{-$3uFzF#VIRx{c zqe0Zrcb5`cy}tHGD_KKRT~yG6KKpY7CEh6q-MujX(w1y0yvSm@$%z{*zd0JjTz+_1 zoxWk8skD@}s+Wv-!ILUp?Pu%}Y9H(MLsQtn*HxMZ)d(;&{+f+;U*#&G!g+un1=`keM5k` z%{)V}9JC3M8PRJRcLxy^8iOck9$^L|7!&yRz%1IRiSDxm*oajl)u;jP(L%2fD6f?H zgkX8-4Fb$h?gt_$^a24!_s#&TlAB{dB-IbYqU=H;40OkQR z^*{!VJb<~(Ts)9L=MG?wFxL)b(5M5LAZF5m%&bYC>->l^yVd2||B& zP}0K)6R5&p*~(wp5x;1liV!6|j4**J(o{{-RITx5MiuW>^f1B%s(7zz_+HggFQH7; zv`p0oyN_nsp{9osCeSQ9)D3s2TVeuLWT@$3gr9%Ygr91980mgNqN7G_T&gzJODIzt zm8q*?0?l$zLk}aI4YZU)8skG6Q@sQ?jggzCnqGpx=3jqJ2fX{!7$F*Z7-0g95u#}j zqG_R*5Uptyt?7unq-mCT4Lyu7fo6%F%IL&i!Jg{yxps~I$+>27 znkP(EKTOpQ8JcicRsZha1hi0rAi_39XwfkRm^ki|A{aDC0VbcBqhNUSLjfj(d7&VK z_9wuc;+7|Zn)@qd^|z66b%9x_S*aWF=z;?2nalwNW1;B@FoDeQ1R3-=0pAPurXI+kj|VU(nTH25Xxjly9<%H~234$e=3+Fo&5V2Qq`y@6IYs_BI2?PNuQ@dx1xL4q${OhscC(9KZ+%4#A-L1~8YH z^9GjF%&*n=MqO{U0A`71iEdP*3kReN=M9ksO*eoMMjL`bj}2hbL-I#U31pV?9%gO^ZXg#Cn| z(0KwF;Wi-{^qBzWJM);pXlN?|jIfdrRLq*_%0Gvvv;k&?W`%APpt}U5|7Ok-7z^Db zfGOe*5`x;XZ;NyPeJO2$vDMh>Vxg%7q!%zl30*AVApuM=^N&CVEhB*OVs;V8phE;O zFS#p(pwJKkm>Rc{^Yp^m72_7xQvJ2K^g= zxyH;Jkcr*1XS&y!b{(qFyQYhh9>%y5p$S1sdKlxvgC;~N>0yl9LTJKu6+Mjc^DCP0 zPDKx6TzJrgKPq|{>n$sM)Wk<^j8}WAc&es{F&ZL33^hHB^%fq*YErB=)>~HW*O2`h zV_Y=QEI}H27~_(FCcMzl!x%>^O(@XN!x$ey(We3$i_At&Mwm_r2K^?0+0VQt1R7bAE%^thx|X9kff}i^fv*WB_R9`<|=_wG?D=35HpcLX5;X6g~tb6?g7kH%~W0g zp`Qe#M=~=B%rU6m@q`CC!+Nq(WSSj+Z-!_s0gMN;mB2jcBmvAp?j9j1G>!n~HZzUD zJh?L+9{*Uot`{(iHH&qZu3MFhJJ0KXzL$!g|5Ig~r^@!2gC^uCtK=wkQkoE=Y7?T; zS9qwKd#GFKXVJ9D(da9pjMPy^l~93p6;O==W>tX<+EV}{EGYzqZWO?zGbakngXR;! z9A(B6$e`B*FbA2>1TttX0gNBBl|TlaB!Cg_5rRVF2w)tTX$0o6dh~4M1CK#{fmy9t zt!pdvkAUe6q!Cge0$zEmcvn|as1oiXe0r7j&kz|kqLbxfH^G(&j^f$HW9$M zGm8jh&=mq0;RGQlG=Ts{7(WOGJs*JaXNC_L4NV?^xy}q8kU>ueV1$o@pwPhqm`vv0 zfO*ic0T^M@ASkqF07h6c2nO94fbnEb3>Xc~7k~+2#tX=x*8(svna=_;=&b-u1@l!v z2CWo;5%vj!Lgxfv3YlvH=GmI+8XD9gYZx$lWSTvH`xHGCfbn4d377{h6Mzvm34&TQ zVbsPr*ZafaRm^zJcyr7_=ihsk@q3k}UcwHw@eZ{vA^GX@*Ifs6A5n!$`8`-q%J0E? z3H%rZ|d0gQu8 zM**`=vraeJ(NY4^eVCmDmX8h+!0co05y+rn1TgQJSp+iZ4*`tugb)(A-tROH? zV1~n`)kk)XHK83Jr_{tLs~|%Yl9ZYxgM`mYlg|d1bq5t)Dj4f!@lg>UgM=`ZCQPLt z^sY*C*C649T603JuQ;pLoHa;@Qj;jPekp|-O`%3VOR+{%{5JtTE#P!-F+&TiA(~hK zBaABqg{Bq2L@~n(%!3{kzzAOoL7^iBFwqLIqrg1DnY(^;Y1Da=Ic>%L%EtSZt#D0C z6GD`YLzJ!b*0j9gaZO7V@yc59N()S&OGn-lm_QZDO0#686(&#x?;71N5p*|+vi29H zB_>b>?oSOc>OIYb8M5voY zs9WO#l4jv!1`}wOD78hDx`|%Gdv%TX>Uw%>d_JmheNMA{)71K=vA_fxln*mZpo$WW zS&7C96VP}B#zP7-9l`P76!hP#4)Ka9z--rS*IfY6e+1HlnfVCjK*JGOi3*<)L7~M6 zZitnhh@CPZthM{DZi^A=6W z(bUY*G{nxK31vq0%Z%D!%c2DclzWT&eu(Jk`2mdZ`49|Rd;k-}>^%e_;hX?QxOfQa z!ly-^SH^nJgL~^iB|S8lhbCNA(nCKXRY_6}5+16^LzTWFQ$;cj671E)Uahb2QxiXf zglB5<%pf6CO)?D<%GIRYAi-Tj+%@_^uWHCugM>s4Ni;|((~z>i3Fun_4U)?|OYpSO zrvw<`O(H0?B>^UhS(0ELbRhxe3bPxFE-Xj{h3+H3 zq%-Fc%!6(tz{E1A5oFL^1eiqTEP@QWi2x%ULK3AOO6*q}?^o8x z5Huk~X&mx5;l9H-zey7|uYj0qG;4G%w9i}_KeGNgmcBu=L6?4@chyr{n;5Nx*BU-5 zbDzJjHPA2wA_1cP=Uz}#kDAXriK{{TjKeh3QfK7cvGtUfRgx_ba~ zm05crgLWRkJY!ZK$e?`(FuBaS1DVJE=gl7;U9lFJWtwHW7C;vdNEgl>A`6;!03(b# z1cM$OzzAOs!Js7vFv5ldqX`ENV1(<2V9;;_7-6y@n9`Wa#W6$dH$d+k)YLhsX)Xu} zoi`wlu-g#Sz8WpZJHDB`5tv;v&91*Ia5UinMi_61Jm|RrjPThI3|edeBWyJUgN7Qw z9AIV|f{@+{{|sRMFz*ax&@KZQVUZyybjJY3nK@%%9yG&XB7fCDw zm~!S;f#st?1u!3&IR!H4M*&PE^P)h;Mz%UU%6-gUU^Z(u>uQF!6p${gC`6WZNg1*s z2Vb!q+cevBInbQ~atKEXkptZ*fJtRe6j(Z%PXHqfCj^CF6Tk?63Blk;9Izl2mJ)(N zHwnlS#;hc;9JG%BMtDXD3jHF05grkOL3;>bge8Pv&$GyinqcFIDP9^X zjZA(QfiY75Yqx z|5X2jG0^OSH9I%B5L9II7G~L#%DsSDt68h-_NN2)6}{WI)*A+KsoK0${U65KEU)Uj zrt=6NU_L7we^z!z27NLh)=lP-fehMW03)n01cglo7c}91As95ifIPzNLNMra0gUjr z5DeN{0OQXrEd(K}Q4)7#=++fDyhEf~sbGc|x)}>@@rs%paEV+D;Sr!!lmVXaav& z#-|LLz#o?JjA;UYSjGuO6Zpe2PAHndAC_@K(FFdmj4z5H276e>*Az5?KP>D07|b7* z^?nTI56k#+f@a|l%lLAFCh&)4d^v$m8_*!aT|+bo`f32Pmw9SnBchE4Fv2=RP`&>< zRPRabQ$JwrWg7dx3uN@u04AK7X<#%o&;aHaGtWR~`gpnGQ;!sX7z>j$lWJo+9SKqD zN>OUvuVvZNcpveU=!q`GkXR3RQPabtQ7??4dF;Ck| zE^OBA77Q?JjkWI9K?m3awdn(OLlmOL1cVT_5`scU31CW?n*`=T0|{V+X@sEAF9H~M z<`sc?&>jMqDCP};4EjL;vx9j-AcOV~z?@>%56Ga~12DqjK~QM!0E{qn5Da=b03-Yx z1cTNMzzDkr!JtzEFv6WdFlfvGOc*m|5CpXv3OYWtM*F)8+SVu3+7oKs@S_Q5)!MTL z2?sUC2Q|9+j~)&XRTwvjuxQ!-fyC5jE zTmXjqEnpt>SO7-&DhLWK6@ZCnb_$pWEfjzewh4kl#{^)6O@d(1A^{j-iy#s1elGQjk>iG+8#i96tg_QSm<&9jIcHk z6xtd9BdiPrgDwWZI5P(WjE1HKzzCxPL7_(hFv6EWFlb2tjPM~440;d%6V3bwupD$8 z0LGQM4IqOC1HdFPa{*+~P5>C;As{I94**7Z1_%b-0^pJ(90D*8eM@N6#>c21?s)Kc zW|P}IWKtX~k{+n(q5B~codh7fa1Rhc&^Q2?cy1OT81xAM<{mQ%5QK!r0KmLvrU1yG z4*)P?@4ujM-#;*7v%g?)qdzcWbH8AU&s0k~>6+=ft37Uuhjg(OUgW@C@W6ETIdCI8Jc5hO>w=*JHbPx3LT!PIc$$!= z)~5aawHNocLsYS!UF5~B?7)ca>w;N(VO_kP%di}{5V&bf-878^Ayw5r&9H7VA_wy9 zmT7kXU2o%VcVNU8caaIVw*w=#vnxX&H(h`sHC!hP+) zh`sEB!F}w&h`sBA!ENinq_8dPSPpJe2S#j77ZmPF2S)5f7YuGf2PT7UK*wmf=NuTZ z&sJF$UrW4o{gA>qbrV8mu?LE%1YV8q^P!Qi%PV8m8x!K_KBm*ep&sTjuS zA&vPVjqbBz++PiO#GY!A2cL$45j&^_gPW&~C?hsZ3x*Ok%;ioS&!A@1nPSps1C!h%)s#+d@zhj{ZAu6*FRTF%1 zKofk7%zTWR;35EDAVA&4PHj;`+@uYR*qJRD+?5TC*oiF|+=UH{*m*6Op;r&A?e($p zFJKmF7U|Y`xEUML#RhDV1NUA7BlcSh2De%RBlcGd2KQD2Blc4Z2DefJBeqWq2H#Ww zlf!mR3qrz;(!hw#(SpJr07mSE77T8K21aas7EHqAH~l8HoAVo(Rhm`07Qo%mkS?}B ziyXN985ptUSunWU85ps{SuoP-`AcWR-)mOSU2_ip*iGPH{@+f$zwQ72EvHXuo23^s z|M^p+(mvusb`b}%n>Z3DvWM&?I|-G#{8dZ)^!|3#``bzH@4b3|@6!9*LGSN9fB*hJ D(&u<$=6vt=RPU@yfn*;PKDmWDZ5=h*D8y60hIB?;B)C>0t@dxz4fg7|)T#zW=w?CZm)IkY|1L8^JneUs= zy!rKZ*EiR%Zb*{EQj^$+>`*cG_35~0jwxtNu?wir?>yJO^Ud_s9-C+{!%O97lq?E< zB~{g`cH61g+D2hLota?>@D>VJ^vTrsjd#V}KBUalEY(LOyb<^)??tVqv_x!hm zJ+B#PyEL>|)m+n>u{&nH>DqyopQ$w+FPN#eOm_x78cCz-J8j!{9m}XRTLo=(bGu-? zwsMV?OG^3L)@(svE$F(gtOS8ww_Mv-wi`}IX&2_zd|uU+Rj+yAJGH$~nW{`H`C{?X zOhL~tDrHO?D5XXa`mMU%2&rB1{HEudpJ3!@Ad0z##(7>PGI6&%GA*Agsg(^dqCfJrdDmMRWqE% zu9vo5rvWbZo0jF^%H3dd1D8P&H@_;{P(Xn&M5^o}L#$GrtkM;~#x!pQn@ zA8{Oxvdevo7C-MDZeDzfj^yrg9Q}hJqj~S5@bT_}BR{PVpQgzAaX)d~Iga}gZLGI@ nAHRU3XH~S{;GlC-l8zBf@>$YOE4t@DP?R9Pq@ z?E(rYiZ&|HYCGsqDvAs4v>P)xfDX3%(YCu?Ms2mHb=1+GmYU!Fa$oWiUY?vep7~?u z9g^R>_jm98_BF+&^BU$WiX!w!5!Z;UBt*mPG&4nb@iJbF6=Q_`sBi0t>(=(wZuK1& zBM$WWw~p%8HjjFxcUNsm?*{)QMVx4 zSa-C~Ask2Nt*#xeOtAfIo>tj6tZ#&<8$POgwp!=x-B9aT(zpMa!_N-uUI+i0ZXrJ- zfQl-HJA~Lqy58|ZWwbHc88ycKgeqIBN?NP3m&#r$d#UWDI@r$1=wd8lEM{~Q+Bmw6 zquV&TjicK*x=lv6v$dVA?b6!8T8Gp+S#q+ClOsB1L>IFzW?hmkVr`Ms7PC|=B{xfM zDV4BP!u};3y+lU$FzaE~!>or(4d6e z-qg&SE%Rp2ylMPKUa}XB@9Wz&zVFiBeVbOh)ZTrES9|f@?-H?D9NoFE;gVt9WHop5 z$$#6quit9)4$rRf;%~kC8u0#+f7kfG49|LsV?5QP+Gf`gWx{?(?-1b>*Pq$v+o~g9^-ShB9shx9e|3Nx~~ zzH#2-N_0_8y|N&W*mg}_SCFqp+M2rFj9;)ga89ETrJ8z`8Qolq>^Gge$S*{HO}*O8 zdmIL?)L?%sN3CQ>J7G9*ih@+3el5=4Yj_#5IsfM5PU}= zdaAIY)_+xqo`#%h>aC_3KYJcB4(HoUoxxTMJ2HNIA$qc~Bjdj|i``ULCD5FAn7KC9 zRSO5={)4HbzuqU%(mPE({q?oN3D-Lduzul0j_xYJ)(IzS@*ho;4Io+cpk1b}0VL}} zvb_aZzi=VhyUhaESNnYeUGE+39ZZlVqwW1iV_nEmi`fHm4 zK7lTKznQb7YlR!`d(8MHO|@{wRQG^c@Ff9+?x(2_nvuRbl($4vA2N#zvR0HJ)rSkP zeo=yo+*^RH6D4TBN6eD-HwK!Ts)R>VA2oB9bhYpx>BkE4lZ6L~KVFcZB0Na`iGuu8 z;lW^fvLHVV+0)dg3i8v12Sa9GL4JntU|{^ljIZ;d)=SY~PZwZoMQNF)K2w18i&89F z&ti41!vf8V_l}bX&41$Z*&Dr3WfpIH)2gID6$=I;iD+kgBoT@Q{0(RM7y1`t5_?Y3 z7kq51GjVR675{o?czJV99Q8UFD2i=g@tJ}8vx0%M7B>g6xNElG7!xsI{9 zepEx!Ymhcyk1QsNObs2G@F(Sqk9YJ>ne(Jt#j&$-JHh0de4=$fdhZu z)tT$IA{Gy!SKEy_zk20!-BnvQOwF|n$Gci$5n;C*hvS^h@9qDmcRu^iTvM6zti7QQ zpJ}c;eAnK0{*+sX`k;1F7-LRGZtVWbw$%MfPI#MFk0L&XIajw*US1K7bVpkw4CSp9 zOsEx0l95ERqHSd;(Nht-u(jgCc;W(#x6Wk6is~7Yr_T&m#6m5TB0Zs%ov}!=qH0oG zXEdIi6z&SeCV{CSF&IunyCaEMv?bWu*;QTP4=kw;F7`Ew=6Y{)W7Fj7N`G}_Wu^Db z$zFejf8s>1KOT;>MLN7oI-)(^?&_)KRaNDcBO#0(pn7fLVGxA-sB)q6X^;q*m(HI=&<~vBeXgDEL{c3@(Mp@p1 zR{B5F$U&67-mC1mqX$_2qB9ji=POFF}8T>Ar!F1$o4ulU;_1qsr z&a)!xt;j|z@@y+|i50ojid<$zF1I4XR%E*s8M7igt;m!W*<(enwj$SBkylue>#fL* zR^(_pQi}tjJHT$Uj?=Us{phSdo9VB9B^;Di(%<)40Qm zEVd#&R%CxG@BXgV)51s z0yuU0;~guaZQ^9gg*i2{Fg30)HL);NS(utiRL;7*q@yL?5sri@Z-K5@tgACAro*ae zCccFI-?FumUUyCG=f@LO)29WZ9fInr5g&(bxL#k!;bl^j<4}`D4KfGq#hG@oj8$1l zIiS?fmpM57xN?y8GRZ+5>-e?NqP0v@_a~-YDyr z20z$bRQ>5djd#CQt6`xoe^Z7HpzVL zRrNDMu7yb+A5+ng8)f8;W|8G#f}&n8BR_F$WNBd%c^^f-jw0Li+=SyOH3gzmhr{-C zCYU5lVmyZ!+B3L~FrOPnAvkUE74>!1+@iwQ*%^zrhEmaZN3tRnt!SlVZ-qSko)bz$ zg4NT4m6hp#6`3=0`k>ttHfZQjUEVIHlg3QprJ3$iB~iYMH1S>9wGQdk{;QH4L=zS#z#?JwiUAZ(Tbj2m26GLQ1}mR z)Sm;LnOk9@-yX}MX{uh6h_uyX2JI30h=uJXEzwl2vgkxAl6Dpjtp!eDR9tFrMcL*o zVDjUa_)aJK@JPyIBB(~`at0_xnPppTNid!}1569bdJO`b5lU8T6cWw(ml zxIcc0kj{@5l*a@@7Al^G!l79e+sn=pO-t-J>{E+9nli_sswg`C0)Sc-^tKZ~dwk!m zG;-A1_~}uxy{>`1U3HeuQJp#7H1_Q_SiFEAqqH*H0dYa6rW|x&BPFBP==@HF;%`5A z@ZgI_=$oHI@*UrYw$m%W9NPYJT98(U4jwdyq{F*Ra;-{9en-#uni9*TNsGKRxRne% zb5w_C`*wstnK@Uq2uq76(iR6{a;z0C)6(iNtOnQMH>IKzwW5_;@eX`Da1$*{NNbU_ zx|izcHkk}|V^p=YL`iBdQK+|Uz0iD~&cQJh&CZf~8kF0U&h%AOkK$5%n{@3TtvhAr z8KhIFL!o3s{tD2C$Bs-X%CLR|h0Eb`x?HXzSFy|OI@vYLHP_{LojC-y`a>OUz?yBs zH{hZr1J?NDKqij#SluPJ5UBf5=NrU&-+-PbqYrgEZ2Y88J&+~^dTQ`_3m-~H#fz?| zJ~NW_A)v0Ot}=l2O$I%65Snf%&d-5*o~TREJee-X>SoH5&QV8jX1I&y8S_g$L1T_? zgY@*N8<^>-58z)q9iUPsY_8J51KcOM#=17vP<1I~N}fu^-;E5hxn{agch7Rq9a``0 zz*QLi7DL*4FK!vrE@eu8#SqC>j@YD=j@sOz9ja&MS&!5K$|(6U1aU zMX;X;|FjW_T1J$tV+>fg`wVzE$BBCM0M~eEPS*6WMN-V9Qfv_6K#?@n0i_Z@RClSHtU~3(s!DC15f8lU6s8@Uu@8(FU#S1A(ZJ@baVa{G=?LsFkCFB zH)DBMz=nI@%<oOdz4I{Wsc|AC+K9BJ)qDbMz4$9V}a?BLRO6NNFev< z|AI4u`A(a5>AWvHX1i+G%I06Lqn?G2CcEZ(q0r=}`I5=VN?fuhglkxFzkUjhyVmL% zJ)xGUP>=}zTFIdlEB(@q1v&Ge1v8Ib{h|*?NZ3uJvNAvp$FpHfJ^46;52k$f*? zeTpIZamdum^!SG$>r)l+l$U|{;g9;!z?0CA3E?2uSfJb+02^6PKba6u{fclY<1)tO zjA6!h#uy|06hVF|#vVqRhDpDc@e0QEj2jv0il6LmV7!Tu?&wKR*YSjRFw!ME$-Ru! zA4sNKa>9ohsUML16eHbelT4S_gw!tx=}MZAZl4M1qM4BHlnLKte20-Pg-K8Mzl0w# ze#%G}xTL4MTEcG_=?0c$x@;vxQ%R&NRFaDs>0*@R{)}|pNiwY(1JURs8L8iqOqYs; zbc0Ap*M)?1AvkcP5Ol#b@KhmaF&a2Vh}lTr<;54CGw`u{=}m~M!Rz`Bc-QsU8uXhD zdc5Mn1c`_0gw}m38{sgJgtHl!G2YL3gz-zpAt)c&pTT%8V~TMzql4o27h(iqNqTXm z&8pO611a^`cKkc>MUW{za0#QlIMeO1k(TyYSVwcdQB5)*8t1Es@u!RzFm^I-W!%R2 z8DkOWcO0XiaXI59jN2F=Wqg(K3q}vdG1bdN#s!QK#>*IQV|Fn-QhjJ!~OPGziPtY>UxY-8Nb_yXhmj7J%VqOVcB zDU9ba1{rT)yovFTjDxT#AitrEt&G<)Zei??-4faP80Ryd$N2Y*zh(TA@f*g|uu&ra z2F3v6I>uWVf5rF#8cct6G*>5nkJ%J@@^Ez$>onQ=NeeRi~!Vosy+ zhW*v^)E>~kMhN{|gwVU;OZrm?p&v;I{SMaO$NC3Z{|f6rWc??s|10bJQGFv$DIwyF zCPe(Hte?sHCe}w-A7%ZOte5SFINMqO0PCM8g#G~Q-)8;itp9@b9%@gd>m`K!7((P{ zKI@mVei`dmvtITG*vtL^`<<+RgzcYT``1|i5$iu?{ZZDJQhz|4frN-tNr?Q^vR?Kp z=-XL;5$o3wLVqjk_ptt9*1yR5-?RRG)_=?TV(Ldo*F%Un;|P)N4A#$P{m)q+XMK|O z>sc@RDdNa}iZ~Clem~p4!1nL4{wvmh%lb0vw@7z1A>y1$h&ZQFe=I|N@H()7sKMp=HO6JU8M<8sD!#!g0=9@<(@7uhKE zgykPZ;m->T9nV;we>5{c=Z*1?X{ZwPT`j*Si}F;YCnd_m_+10vk(RDD{PER_xc)AG z#A5x51pN-iLa3!B5$V>Y)T+)%QWx+yh5BnK5$b5mGM!y5^jlg|Kb@PN#tkQTDn#bk zE6=pYoPnj*;F2-tO9ZA0p5YB=>|9kaXf+2_XB2)l2gO~ zgBCiDMhOO+>w_&_(O5VbN~IFfmaY^vU2@gRRH#LiCn7QKEO-m?YjZvEE%8`+C>9OD znyk{@DBX3kayrvlnM;&aaR16GGQB6O%JiUeN;%R>KMj_zh=tlHqp5_0}XPa-QVGl3&6nS>zARE(NGAez?oo6QhpxbEI4ZG?2Mv(L4 z?S|b>y)q2;`F3ZI#T|ix*I%pgVodiBu%okt{$QIepSk!ps72sZxqV_b3;A}fu%kIW z|H-%82)lpHH-emRcOHV>X=2w1oiTrXush$xj@ApKU35bFJ|N$;Ezj-~*fr!ELC&|E z`jhmzHsAC@D9|-&S(4A5iRSHl4OnAyehj;{P>hBiS10nJ0r5+GuyxBk?d3vvVTU7R zrhG2E--eIghGcwIr4S2%Mmri;cjJRGc_~0XM_^}+PfCjSBtAy{JFshqj^gQhvO8pu z@hb2?Amwi`WT)rH%x)R%5K_j&5lud3cAH?=g9@d1$alu>ZM^CEAf4c8#Fg3`B>}X$PwEF;dq$fLE56H*N?lXfO urjU%?7{o*QGwtye>}bx(f2P5X%H?IkgG;urp))=to{?u~n}vR0V)x(aV~(T% literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/device/subdir_rules.mk b/gpio_driverlib_cpu2/CPU2_RAM/device/subdir_rules.mk new file mode 100644 index 0000000..e90c90f --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/device/subdir_rules.mk @@ -0,0 +1,18 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Each subdirectory must supply rules for building sources it contributes +device/%.obj: ../device/%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'C2000 Compiler - building file: "$<"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2" --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/device" --include_path="/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/" --include_path="/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --define=DEBUG --define=CPU2 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="device/$(basename $(> Linked Thu Jul 16 11:43:11 2026 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "code_start" address: 00000000 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- +PAGE 0: + BEGIN 00000000 00000002 00000002 00000000 RWIX + RAMM0 000000a2 0000035e 00000012 0000034c RWIX + RAMLS0 00008000 00000800 00000000 00000800 RWIX + RAMLS1 00008800 00000800 00000000 00000800 RWIX + RAMLS2 00009000 00000800 00000000 00000800 RWIX + RAMLS3 00009800 00000800 00000000 00000800 RWIX + RAMLS4 0000a000 00000800 00000000 00000800 RWIX + RAMD0 0000b000 00000800 000002c2 0000053e RWIX + FLASHA 00080002 00001ffe 00000000 00001ffe RWIX + FLASHB 00082000 00002000 00000000 00002000 RWIX + FLASHC 00084000 00002000 00000000 00002000 RWIX + FLASHD 00086000 00002000 00000000 00002000 RWIX + FLASHE 00088000 00008000 00000000 00008000 RWIX + FLASHF 00090000 00008000 00000000 00008000 RWIX + FLASHG 00098000 00008000 00000000 00008000 RWIX + FLASHH 000a0000 00008000 00000000 00008000 RWIX + FLASHI 000a8000 00008000 00000000 00008000 RWIX + FLASHJ 000b0000 00008000 00000000 00008000 RWIX + FLASHK 000b8000 00002000 00000000 00002000 RWIX + FLASHL 000ba000 00002000 00000000 00002000 RWIX + FLASHM 000bc000 00002000 00000000 00002000 RWIX + FLASHN 000be000 00001ff0 00000000 00001ff0 RWIX + RESET 003fffc0 00000002 00000000 00000002 RWIX + +PAGE 1: + BOOT_RSVD 00000002 000000a0 00000000 000000a0 RWIX + RAMM1 00000400 000003f8 00000100 000002f8 RWIX + RAMLS5 0000a800 00000800 00000060 000007a0 RWIX + RAMD1 0000b800 00000800 00000000 00000800 RWIX + CPU2TOCPU1RAM 0003f800 00000400 00000000 00000400 RWIX + CPU1TOCPU2RAM 0003fc00 00000400 00000000 00000400 RWIX + CANA_MSG_RAM 00049000 00000800 00000000 00000800 RWIX + CANB_MSG_RAM 0004b000 00000800 00000000 00000800 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +codestart +* 0 00000000 00000002 + 00000000 00000002 F2837xD_CodeStartBranch.obj (codestart) + +.cinit 0 000000a2 00000012 + 000000a2 00000009 (.cinit..data.load) [load image, compression = lzss] + 000000ab 00000001 --HOLE-- [fill = 0] + 000000ac 00000004 (__TI_handler_table) + 000000b0 00000004 (__TI_cinit_table) + +.reset 0 003fffc0 00000000 DSECT + +.stack 1 00000400 00000100 UNINITIALIZED + 00000400 00000100 --HOLE-- + +.init_array +* 0 000000a2 00000000 UNINITIALIZED + +.const 1 0000a800 00000050 + 0000a800 00000050 gpio_driverlib_main_cpu2.obj (.const:.string) + +.data 1 0000a850 00000010 UNINITIALIZED + 0000a850 00000006 device.obj (.data) + 0000a856 00000006 rts2800_fpu32_eabi.lib : exit.c.obj (.data) + 0000a85c 00000002 : _lock.c.obj (.data:_lock) + 0000a85e 00000002 : _lock.c.obj (.data:_unlock) + +GETBUFFER +* 0 0003fc00 00000000 DSECT + +GETWRITEIDX +* 0 0003fc00 00000000 DSECT + +PUTREADIDX +* 0 0003fc00 00000000 DSECT + +.text 0 0000b000 000002c2 + 0000b000 00000192 device.obj (.text) + 0000b192 00000049 gpio_driverlib_main_cpu2.obj (.text) + 0000b1db 0000002e rts2800_fpu32_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss) + 0000b209 0000002b : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit) + 0000b234 00000029 : exit.c.obj (.text) + 0000b25d 00000020 : memcpy.c.obj (.text) + 0000b27d 00000017 : boot28.asm.obj (.text) + 0000b294 00000012 : args_main.c.obj (.text) + 0000b2a6 00000009 : _lock.c.obj (.text) + 0000b2af 00000008 F2837xD_CodeStartBranch.obj (.text) + 0000b2b7 00000008 rts2800_fpu32_eabi.lib : copy_decompress_none.c.obj (.text:decompress:none) + 0000b2bf 00000002 : pre_init.c.obj (.text) + 0000b2c1 00000001 : startup.c.obj (.text) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + ./ + gpio_driverlib_main_cpu2.obj 73 80 0 + +--+------------------------------+------+---------+---------+ + Total: 73 80 0 + + ./device/ + device.obj 402 0 6 + F2837xD_CodeStartBranch.obj 10 0 0 + +--+------------------------------+------+---------+---------+ + Total: 412 0 6 + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/rts2800_fpu32_eabi.lib + exit.c.obj 41 0 6 + copy_decompress_lzss.c.obj 46 0 0 + autoinit.c.obj 43 0 0 + memcpy.c.obj 32 0 0 + boot28.asm.obj 23 0 0 + args_main.c.obj 18 0 0 + _lock.c.obj 9 0 4 + copy_decompress_none.c.obj 8 0 0 + pre_init.c.obj 2 0 0 + startup.c.obj 1 0 0 + +--+------------------------------+------+---------+---------+ + Total: 223 0 10 + + Stack: 0 0 256 + Linker Generated: 0 17 0 + +--+------------------------------+------+---------+---------+ + Grand Total: 708 97 272 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000000b0 records: 1, size/record: 4, table size: 4 + .data: load addr=000000a2, load size=00000009 bytes, run addr=0000a850, run size=00000010 bytes, compression=lzss + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 000000ac records: 2, size/record: 2, table size: 4 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + + +GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE + +address data page name +-------- ---------------- ---- +00000400 10 (00000400) __stack + +0000a850 2a1 (0000a840) Example_Result +0000a852 2a1 (0000a840) Example_PassCount +0000a854 2a1 (0000a840) Example_Fail +0000a856 2a1 (0000a840) __TI_enable_exit_profile_output +0000a858 2a1 (0000a840) __TI_cleanup_ptr +0000a85a 2a1 (0000a840) __TI_dtors_ptr +0000a85c 2a1 (0000a840) _lock +0000a85e 2a1 (0000a840) _unlock + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +page address name +---- ------- ---- +0 0000b234 C$$EXIT +0 0000b040 Device_enableAllPeripherals +0 0000b16a Device_enableUnbondedGPIOPullups +0 0000b14d Device_enableUnbondedGPIOPullupsFor100Pin +0 0000b13a Device_enableUnbondedGPIOPullupsFor176Pin +0 0000b037 Device_init +0 0000b119 Device_initGPIO +1 0000a854 Example_Fail +1 0000a852 Example_PassCount +1 0000a850 Example_Result +0 0000b191 Example_done +0 0000b18c Example_setResultFail +0 0000b187 Example_setResultPass +0 000000b0 __TI_CINIT_Base +0 000000b4 __TI_CINIT_Limit +0 000000b4 __TI_CINIT_Warm +0 000000ac __TI_Handler_Table_Base +0 000000b0 __TI_Handler_Table_Limit +1 00000500 __TI_STACK_END +abs 00000100 __TI_STACK_SIZE +0 0000b209 __TI_auto_init_nobinit_nopinit +1 0000a858 __TI_cleanup_ptr +0 0000b1db __TI_decompress_lzss +0 0000b2b7 __TI_decompress_none +1 0000a85a __TI_dtors_ptr +1 0000a856 __TI_enable_exit_profile_output +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +abs ffffffff __c_args__ +0 0000b180 __error__ +1 00000400 __stack +0 0000b294 _args_main +0 0000b27d _c_int00 +1 0000a85c _lock +0 0000b2ae _nop +0 0000b2aa _register_lock +0 0000b2a6 _register_unlock +0 0000b2c1 _system_post_cinit +0 0000b2bf _system_pre_init +1 0000a85e _unlock +0 0000b234 abort +0 00000000 code_start +0 0000b236 exit +0 0000b1c5 main +0 0000b25d memcpy + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +page address name +---- ------- ---- +0 00000000 code_start +0 000000ac __TI_Handler_Table_Base +0 000000b0 __TI_CINIT_Base +0 000000b0 __TI_Handler_Table_Limit +0 000000b4 __TI_CINIT_Limit +0 000000b4 __TI_CINIT_Warm +0 0000b037 Device_init +0 0000b040 Device_enableAllPeripherals +0 0000b119 Device_initGPIO +0 0000b13a Device_enableUnbondedGPIOPullupsFor176Pin +0 0000b14d Device_enableUnbondedGPIOPullupsFor100Pin +0 0000b16a Device_enableUnbondedGPIOPullups +0 0000b180 __error__ +0 0000b187 Example_setResultPass +0 0000b18c Example_setResultFail +0 0000b191 Example_done +0 0000b1c5 main +0 0000b1db __TI_decompress_lzss +0 0000b209 __TI_auto_init_nobinit_nopinit +0 0000b234 C$$EXIT +0 0000b234 abort +0 0000b236 exit +0 0000b25d memcpy +0 0000b27d _c_int00 +0 0000b294 _args_main +0 0000b2a6 _register_unlock +0 0000b2aa _register_lock +0 0000b2ae _nop +0 0000b2b7 __TI_decompress_none +0 0000b2bf _system_pre_init +0 0000b2c1 _system_post_cinit +1 00000400 __stack +1 00000500 __TI_STACK_END +1 0000a850 Example_Result +1 0000a852 Example_PassCount +1 0000a854 Example_Fail +1 0000a856 __TI_enable_exit_profile_output +1 0000a858 __TI_cleanup_ptr +1 0000a85a __TI_dtors_ptr +1 0000a85c _lock +1 0000a85e _unlock +abs 00000100 __TI_STACK_SIZE +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +abs ffffffff __c_args__ + +[46 symbols] diff --git a/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2.out b/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2.out new file mode 100644 index 0000000000000000000000000000000000000000..a2d62e7eb1c9c89a9077e4f91c5ae2a94c0daae7 GIT binary patch literal 26304 zcmd^nd3+RAw*RfFu1-S8M%cm7>?AQOdl1cvWCV#xKyaC+lWs_lNji2X%_5tEprE4Y zb4Jt=5HZ0G7)??P3b zbI)?mJ$GL^8*3KKQxrvTP{qxHu|vy+=v4nZqm)%q?^7v%n%82sl zxI;o!EJ(E=&4OGOq?=HA^jn8zEt=BX+dZXsW6#l>)+MVwM^CQv;5~4?*eOo$Ke}N3 z$S84LuygcR`;QJ>huV?eJw<%gb94dVkE^<;{4OUZDf&pNr}dr5uPeDH+&#lZlDO@{ z-ikZ*de`#u=)%M9kXu4!hn3KEsFAMI)j5^j6H$+;ehZaqCe=&Df<#C?U76FZif6@> zl^JS_^5lcJt3Kt~1G`Ax4O)40*I`kgwA|BsQb7*7%cGkPSGtwl>fVyx;@;uC8_^yr z-D7U;k*#T7&Ntlp^6KsL+`r6mh3NZM4z&%}X+^EfnTAr@bGRxW|3+m_)>l>ypzqf$ z!lIF#TZ$gaA0F!2vqw=zJeYIssclPzdhID?#PzEWWc+=(7TU7w`a2KqI^Nq;^w2Kl zo}S5>^&dAMEdR1?%dVauWeD}&7kayI=vkW8;97pby(R5H&Yn%4-rkG{Gk&t%Esh=$ zI}eGY2Yb4Y?mK?-!{Yvo(LS;BaZ!HrA<@&lH)DuzucpkY=v7AaY`u27GH1&!ZAp)E ze^Srp7hk+~^UCwD{Tb@ThE1mz^pqXQ$n=C9EIyJEeV*lnJxesjD-Ybt@ zc?7j=H*pn-3ekaots*Fzg->+i8xrjz0t&%Jh%FVx@?VjtvfxX>8x{fKMa&GmiNpRb z5`NHwA_|_c)ZPSLE5JQVOcgW5YS0t&tb{dWL!oHFI58fN3lH8OjobYFN2a{?u?NVM zy~#qX2QWDr3i^eZNDO%J&RV+vowu)>wb}#3VjJ2N3bmqPiF1hs58mJJ`svOm7GH7D z10=>639f7p_&v=nzOYc-u)^a1diBuvHXj~V;NXcYT zy1ku3b&E+c-iL?ut}S__?g=Mvq$L#Y6p9XCSy~&P`O)m3U%a>3$!XbPiX@2%F_F8z z+@a-PcIZ;4NU&Y1E{O5@2R$)j%<>PucJf)Or9hJ1+0prrJ@i^b)LOq3U+$ zJ>W|}HS5!=x15ZYWF#ift!NGTP|sX;%WrIZK3cMC`*bI#Kh)LK8W1j*y@AZ#`N4@7-~IJpoUGFF z7{ASj#~Z6p9(dy2&zwHwW;Tq}*ew~mBl;(8Y3iE}^(h|KBA!aJyz*wt_TK0x|;ghy7}I!1sCC|C=o(eH!H*Y5~~+hptsf4Es2PY zwF_(Ni-pj1_4bmWV#TzV6b6LS*Xd4T;E&l`y|y*~L{t4ARvb z6R})qgp~1k*5k3 z(mVSjPZKJ>8P^0dRu?w8L&)OclAe}iH=oQZ|{#hOQ=b@dPjfc*+Na$)qm@c zTv9C56kWZuUpm}2Kv%!rFCC6c)z$AL^mR=4Gf3yeF=p@Efp>pzNbI(RN;c*dlTtys4fvG z&V7kQ8>&l%8+z|gC|FfnAyCr$6G~RqR*EEuKF|-fN+iLe1N~5|MG`#uV8UeUkSuCY zcS6xRB%6$6d-|bPiDV>uFp=Wg(y9u9s`pSLQ4lLd3KTz_NVKZr;tGLU`A8yB5G%z1 zh(4M~bYWFxLtTYHm3=Icuq0QCREQr+L|@!c31M_~hZ8AZTnE(yb@fOhVnsFbo2IMZ zOQaXXN|An(x-`ZB>!~3^ywlUjp^U}rO$wQy82AN^qC?ZP3CC7^jRVu4ddBF^y&(DJrf0X ztRHHn$js8!Smvs2#IKRAC6wj@u%t(YtBS*&=GtpJ~tABIaR0*Ip3zx!SHTR^Rix?k6`m z49Yg_plQ3NonV{o6Wg2SpL*kP%k^HTm@%;}nIR{(6+FkcPi*fRwR8N*Cx-mkDMu4q zDK$i|V9g>2PBFbd;RlzMVj(t7N?n{{teP_I^RT(K8!lfx^@p!II8r<;XgB@ol&e0u z@T)HdI9Rhgg6+Xh?}~Pqo~abDI{WN;+c{#}`WwZ4a%RXz=s|UzcmmxGCx?E%?j5#%-1|SwD{$v@Aw@F$;`7NWZpLG{`i?=1OI)`H8(reb7kqXa$!F>)TelOmTuR4 zG7{ak?B0*IIyJL`KJ)qark%I)!F!&5GEOsVv9Bx&-uvaDR~BD(*ug6E$lS=|YGFBl z%mbq?z2-m4wmJCIuK`1IsAG*c9B2-O{lYz1ot}&(kKgO_`>}e@Qpau9CTIRr=)k6Dl3-CbJs;z(_-Ln3_*7-Tj(eY8eP&QupBBgbCD z@-%f3mvvHmR~z{vLithB)H;j6k!rSj37aMC4g1!nl&^o)y6G-Q%0?y|D=HV%pi{1A z>+Drz?Wx_~gFnfA-C0FgTc5f;cK_zQ$heVTI+Bs)&Wcd(wqO;NVa3 zuztHGyPh04^T4n3?~s;+QjC5sm-lS?RMw0BkoQJ*=xL)9X7&^hYZ2$c>1L^{`_7>7 z``4ELhctp&vpYiQc+v7ZL*C|4d!!ScUyc%BwRX!wbN62T?hVPmb6Un)`&c&fiKT!3 z#bv)V_OCd(6c6XbJ^;NoBHVOd;Qo$&EQ3LQ)@C>8)q=~%f4271mz@T&GQ%J&fI0su zrJE0~>s@?}GZm_R$nyxb+}ebh5tGTPziY<>TcSRvjL}X_$sDDLHH+CX$v6LW!S^;M zpI0v>Z#B!&-1hOV@I{QlZm_z}8ti7qghw8{x}f0WN3U`U(-0XG9jTRZ8iE?5S<1(+ z&ujQ33{`dN!JNh^y|bfh+i)394RXm57&8t={3 zPSMst`^wH1X>A=Vw>##Pb;$avOT%1)u_F;;qmn4 z=d9ZEhg*Y^{l84}bJ=Et{bJZW7{^q@|UkHy!_Q$mpL?MSJYqFAPSU9PR}mEY8(=B z;81z+rGdlNPlgT`p8B@?wRH}O6c2OTSzq5jV?a&ATw{ZA`~ah$O!4sMy4}-@|Lv{4 zr)E6%E9p9B&1D6BJUv%=?akxYO=xzqvtonYX7liG|KqKV9X+2)n^}8`hqc%Zsr>z< z7ry?@fv23Bx%V(MpN~a{S%#?qWx&yxJaksa0HxCcWo#SXKgIK+Nph>h2qlRr%G!zQ zmi6xeloJZ!q~zy{vN}!+wk@NVoIxv6S+^8)-l7J+)^Fp_BLnv# zoxE1W9t4no0xy9B9Ls|Pqagi-A`w(PmIDj!0fhp^_LW%xDjojQF@H?v60A((_j!;nQK^Y|}=QD*+P#QrgkdzCULa11zTZyGoV(;S- zhm3-YB|7#>#Fl}7CP?LY+}eCXNn*FMA#a{Z%DWQ4Y|!&Bz)OtX43wfsWCWb(*7g%h zVt<3!8o(7GNuY*-S_T#}a0vs88Cc4|6$~tAz|TMn1FZ~nFwn`sY6jLZu!(^!3~Xay z2Lm{RHEh0}fp0T#Hv`{gU>^eq80cZ(5e5!1@HhiMVBi@Bjxq2811~Y~3Ine(@CE}v zX5gm`yvx8Z82FHZj~V!!f!{Fj2L}Gkz~31-&45achRW2iI8~EO1@&YvkkKGWU@QZZ7|3U!n1Sg8d>>LX0p!odOPrIbp=U!B zrLYi>Tgy=hr&J~(mHY*gZ6?@MJjC)X$yTNiPHff07L;t85Jd?P%O=UTKp~viS`=j+ zdX#ym>%8UXnl@e=2Jgm~&`NXa%lZtY=}a8mR=RavVmS4;;BuhY@l zoez}TFp}9|CsXHUr{`~#i3~)~Uj;Er;3k>K6Dr}9$PZLxYKLT-3btj4CYIYI+tVuH z#CDX}ZY8!+Aw&_GI(N5rOeLIHo(D_Li_k&kg)1nsw@}o#Rl=#a{!pdf`igbn=e;51 z$KLr;e&X=>&iWd=c>W9|BXaW5i&4cBz=q*bls7cOuSH59Y2?JZHv#fa8x>9*zTp(; zTv(v5|Ja7-50$CZBNgiDCO*9G7f0!YKH1ndN`3xL3_F)NYOI}rOO9^8x&&*4$6 zRK{EiHqyr=U75u*Gm0k3ISM7aA^*74yUnKeKEw|~o>M@X=Fsce4z`0JGs&$yOeje_ zCiShJs4RII7;kz^RIVTsxf)MY>fQs&yDH~Sf%?2p5mN{te=1(6Vm4F00%dP) z63e3J4zOk0NN(jSLP_EpBWtK~QxL-|N?rM8Ay8h=O;o-~R9=O`P@?i0FmF1LXUM2$ zrBNT)j5-gb_wdlYJ#vK2sE@$bU?aJet%Q=qPtMLLhsm(fX>vmgH1U#bqEi1J(&K`i zs5G{N%4@HQ%JMFtytskq*8%0(*hHo2TA=KV{A8I+`xNAQkXO0wxx;i~DW(%QfiPOJ zmI{P|av3Q1N=hCtS_lPY2`CQ()Rh7@l~8fe=2A**9}=VLcBRv$w}6f6KkoZTl3OVy zlq4>ZE~V+@NnorTHIPtV59PfHWFCaiy@+1*^jeBn-p7bv1|a_myu@fiDS1lAtt=sw z(pYX3n|)g~?F+;wC&jtu3S{$35QfFJdI{|#I4xfAn-Kg5IEN@jy!;|m{0t8=O7B!k zaXADJz&M&m+N#_lFlcbyqb4a^nM^22zTPY!w7^hiva~NXS z3N#5qd8L^Dh*U#WZZx9F6jGI~%pjE1%(m1NIMonpsp%m#f;K5Rchf*VhTKt4Nor%c z8?ymy)D1F8SFYxArf8DfZlsC|UJi_@Fun#TuK@FCHFH07=RY8mKWa<<8{o@GHfk4j z*tX=4gN=Fus*^-YQYP~{kD^I(o|WkaU`$14vjiwF=1@g12g*w`v|M85g(O-oQF%Fs zws|E`UZtWF@Y&G(but4BY#CSy@(N^t27%}C#4_Na+Clv*libP$gpx#sVR$}~Q2S!~ z23!rQwMzM;B;0^E-FF_EMjs6N6ckZZ(b3TwZ1!~qvDa7B87yipEiNuDs-pL$zHq=> zI>TFBZ2T|shl9~TxHZ^Rw4!v@)S0XOwwRS2!BAlfDJ?84BE)NPd)s`$c5ib>S7~80 zG0^oDnu6$x_NkJl>t(v~nOjw17YMXi1mT1RLiy*%Z`V`i1a;*Si%ttk9I9t(L&1=z zXK&C`Cg^G7^&yMstvBk*I)nETq~j8E@m8UDjWgS@(I1Egn*&AjWKOERRUv<%q0<-c ztPK0wn_CKf5n53r=$I&={>S!4|xrXjoVUrNP?92 z_NUx1oL#9XdtjhT{FfRD&Q+5f(ld!e1IG_>B(G;_ zFNv!aks#Vt&BZPXjkgb@|y zVI>V!%cZ>|F4WV>vt!kP8JqQ#Z|Lb*!6YfT7o=;iZ9wgF<36mSG{`h*`xK4)kLNkl zl&4^R9QL)r_(;Ut9%>K7%%{0CQv6(u)Lkf`T7Br1y6Xxz7N&|qa{`y#W2HW0$(hx* zu8l-uYH9WhwOdiMhh^&NEA;GU{hSB%L8_jikJ2_a1JcqBC_}4OaYJjMsx8#BwWl^3 zh$}-M_o1HQ2OHS^K|>(pn33Vh(y|;Q!|}aYU^P3K{L$oK9pub}omE$9f(N7DMssyd zwi*OY`4C%*$Ypxcr@HI%EA$a1x~okeh4)l9Zi*_(6qyPQiwU|{Z)>ReD)!C)jQ4Vf z-nhE$(2I*#($FehH!Cvg6HUQ%<$QY-P40AMnvp$Yo-p1tJICo9Y|=;M@XDs+2B6`K z-;;;V(MM=ke|@f=wCWqWtH`J^Mn&`(`o0?M)YlehYwlPRQ%2J!ICgTDp53aCL*dWX z-DSG=H+{q`U7w>5o36Vnj3#NEp*zF7r}*+P}GqF z2V*IcoRplLoRT~sIW>87@|@%glB<$091cDiFmet9kiBuYsK{QwID2D-EMlV3n4N0U zXk=g+8n0;@Ysjo?u*=X$onq2z@uliQfkx`pt%py8`a9}bvv}C?DelA`!82yZ+xkO^-yO_vt#0~#CJ3v3e+7__iyP5kW|bE z)T?+*`f_|(A9Y=W%=mg+JoTDb^GJQwws`6~6U9^iY4;`Tr-3xt)HC0vM{Z1+@stnd zr(Vjg2jhm4otj$fk!uPin*hxv<7TIprOrXQx@;(_xULIzxRy?gZe7qPDNSg}rKz)q zO9`nf*@%ioq-2Pxk}@DmXz8QUC#LTxhqBZxMN7{dmZc1W6;|xPSgaM7X2jXJ(z9Wv zmYkYuq=NM_Ma0ldYIj*f5Qicd3KNYCk;T~-Ds37(7Mw%IiXvDvbOJb2Q_lxDY?7#j z?C>dw8Lb=AI2n+rktn<~(uP82R3WlQ*)iBJ7}1`-wLE=Wxqd@=>K)~2s89}uREr@M z3_HuyCC@p9l(RFc$%$u)PiIUV15&E>m`wJxJbn2RaE(19mo$1@Jc}ba$ud61LixU_ ze1yy~+%^F}GeD&>O46_t{eTfk1vY8AEQ-l8a*0FcMF zmybY$CoD_3k>GO;81Xj~T5zMuI7qpJD&Rj`+ZQd41j3P`m2JN8>Y~%J<-zXg(W40#hxnMnhOV4wsd-?H0OFsX3w5cP+D9v z%hQN7Bc57ZX9{<<1=>3aZVrVzLSbKLz%OWn0>`)VhU=-*cRAZE)w>}W*YV8z^*7+ils!$hxfyXiPe8E;xEq7bw zx=ffir2WAN-TS-L*V)|S53OXDKs&`&w6?}>P)AtApv4F*L+dpvE~Cu4+G#Rhhnvb( zq4pKQIL(XOn?mjWfS>s5x>{SiIwGvbP@jNdUMO5La|TrkGaqND9u?PKF4hq!O&VOAUv?jY9);)C*4y>$&XI6`*V5bSh zR_12gZjMHZz7=S{Du~@e*}6M?*hH)B3by(y+WoSjphXomQACli{i>plaLC`)+*#D- zYc9ghVS&6{*zRjBiiDemw;45}v$&Yr_JUwj*cVQOI8uipmj)Fr&R2982tD~z^U`^K96*1Iw5RC}l7F_!lz9y<` zymXac;Wb*7fGax$F5|8YqLji0jhdS+&g3*dR&h}Q(JeE)qNY<2)fo~i!l5?IL&E^W z5{@kwWuCao$ayNwH;q}JagI%E0iFl*oL92oMe|WrRALH8vqU2p@&;_s=}M46r#)GW zm{y>9pehbpbSA8m@x!3X)QdI9E^zU>hSxE?X5lpouSs|f!fOs*WAJ){*ABc^;I#p# zZ`l1UEIo|$X}gTpS{w}ee_C{&-#Y1&kyS&U=lxFl5sS|AW+(kZEXNFaUQaOH@LK`y z;F3UBeigXO!=wXT+{^^>DtR#JAH*|5woKhLxy={I( z_iOr@ZjtLp;ZX&3BtAe?pR5rXu>2bps-S+P5g3(BpTU{fO7N(Hx|3~yB-@!sUlN)u zg{Y6Y%`RjcAZZhvI89dSZa(OTRSufOdKn&7P|w5lvd=I{H8XCgq-rUn&M;hpMU2H` z^j`-7QAXtqe=XcUaGLhUqoO*jt7kmUDr`S#9&TO0LcoV3hLJum_)0* zWAh+lM9&5-)WOlV0fh?6T4SxC{R5#JYcr8Na=^fW3MJWGI%~DBDJT@^#!sf*$^eCK zzQzS~1XjS|hTJ3EXU1qqaF9jCz6<_Qn#X&|ZG^jI`EZx3VV7-+q!=$vxJ7{jPm;gR z;3y3ve+?nsMvR6LguFm^b}49LfS`K9L4$RdF@moq2I8;4#DXT$@b_L~L4(t1-oQZ< z8M3*Euh2UnXd+X#gczPB?j?dnAH=3nEcmnOWYh{8cCDyLIcO-Fml?rV!*1Y@9r!TW zoLGs5iu;L;?oxl>tD!(>|B-^K4#!Oq+#0swBY@v)!^Z%pxft^o0DstqPX&J5hR+86 zf(^d_`0F;j2KZYx{377&1Vv4e_OpE&>}#;mHP9XYP~-fe4we4-i(xK)2Nvfabr`!w za%k#c(M0;qK>pbPoaT%a$UoFQF;4c_*r8vM_7ob$4Sa~io6vhxAe_o;xG6;T5Z-3P zZ?q|-^l8q?MpF7T9@89@0^!dAr@1KORDNr0{-pBTV8f}rXs*fplpoel`Ej%db%3=0 z+ZbUeaDIkjv|yaR-OJ;ncrqHviJybxx1-S3!#f z1orP2w){~3wpsPv@b8JZ{QZgsLu^)=(74 zUTU9oS(Achw$HgV1ChAV-@Hl(;3iJ?ciZeI{LMIgb~163J|llFt34X^XO%evp!_`= zm%k4nM{6+(WZ#pZ(=AH_A0VCwPM0Scr}pI^%eZ0h<>Q?AlJPN|?7hrpAK_c$aGGIK z;Ql5nC5BUd^vC6AhSfg|7O%rT4%8l~KHg{ZKb03Q}^uQ~SBbhJOJ2Xe~^E z^LJnp<3|3D*z!a9OTk>60@t6xR)1{NpLte)I#~QQ&VEYIxZD^^uVji;2Yp6*c{cr& zUciQvKO5uHGo(r1VEJ0{n4PfbhyVydL<&Hu|^X zEc73=2<1H}qSpfFJuSi)1DAjA*5s#OCh%Ss(XR*2 zds>9kwQt_rBAmv4-U}oAKY{aJ7vb*$r(ee5BklPO0Nyhr`f&J;$9uxZk}ruFAq)P@ z19dx<=3TJ^-99 z+%x_paO$5)p8WeZaNe6D`JV%){*n3r8#wikjDHH8&%BBMufX|iobVKkO}v*y_+a3? zcSZOp;JjBwIGT5#K(--X#eTIvAU9$~p|Js87+Dp>QH?0X6}3R8CCyY7;aW5NR=hnHdT@It=apKvUOBZ|9nh0PHc4VEYRExlIF>hc70) z0?7wNVP{}XD~%N z9-LH>xI!?Rgpaf?ylYm~0WaN#ADR^Uc4j(@2M$HbG~+O+iCrMb$;#hT6+& z3%_)+S=@XqubEj+7GY(IQ`b2F?jty5+IyKT{Apw`F;`m&!&%7`+eb`%jAuJ}c*f2`9*TQ?o#_6X zx;m*#iL7bENwgdhBY|f64NjqP^h;xeq(oXwh{oz^w$YmA1oU7EAjff{)7JJr^O=Az zJ;Y;<>Ea5&azcwa;1&qdW0#kE2P8lb1qfowV9855<|DKRw+A13?D{u>ndXDMXX*i+ zqkvs<2~*xE&y@EGcsNizg+X|dC6xHZ`e+-2`FKy+F2Q_b zO+GobhGEhtoET^fPO!UqsN|&eV{qfB{OTHTLk#1>6w_)EN;2hXK+AH96 zsk|s%4>RG*eDx-ujpP71AG8-v`uYpZw*m}j!`E?^e6(M9Hu|>N`OH0aL|K9DyA3gx zzBBOMdzO6Nc0Mb$7{KY$I+J0dQhDT>dwYa4jrK?wruZK0?^Muvj2W0lYhi|o^x3&M zw=~zrgforS$P80_@l3Qgu8hFB?R{YK$!ZK^sV|}ag9GdM1Q84qZCV*{n?C0Ma~$9F zxk7A|%9+FXDo|$E_jr{M$GLLaSTp1JI_F_6$Hv?EJm7;lRJ~+abdj@P<@g!kvnR6! ze4DUW>H)(+lPMElI?0C{HkwhwwJdfIn&aqOXQV6T3HN}nFfPAf5%d>s$Xy;h6fX7( L$GHQ=5#Rp<9X~rb literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2_linkInfo.xml b/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2_linkInfo.xml new file mode 100644 index 0000000..5a3d16c --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2_linkInfo.xml @@ -0,0 +1,2585 @@ + + + TMS320C2000 Linker Unix v25.11.0.LTS + Copyright (c) 1996-2018 Texas Instruments Incorporated + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/lnk2000 --tm_feedback=/var/tmp/TI0RaeVor7F --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --buffer_diagnostics --ecc=off --map_file=gpio_driverlib_cpu2.map --stack_size=0x100 --warn_sections --search_path=/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib --search_path=/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include --reread_libs --diag_wrap=off --display_error_number --xml_link_info=gpio_driverlib_cpu2_linkInfo.xml --entry_point=code_start --rom_model --output_file=gpio_driverlib_cpu2.out ./gpio_driverlib_main_cpu2.obj ./device/F2837xD_CodeStartBranch.obj ./device/device.obj ../2837xD_RAM_lnk_cpu2.cmd /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib --library=libc.a + 0x6a59182f + 0x0 + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_cpu2.out + + code_start +

    0x0
    + + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/CPU2_RAM/./ + object + gpio_driverlib_main_cpu2.obj + gpio_driverlib_main_cpu2.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/CPU2_RAM/./device/ + object + F2837xD_CodeStartBranch.obj + F2837xD_CodeStartBranch.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/CPU2_RAM/./device/ + object + device.obj + device.obj + + + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/CPU2_RAM/ + object + <internal> + <internal> + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + boot28.asm.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + pre_init.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + autoinit.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + copy_zero_init.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + copy_decompress_none.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + copy_decompress_lzss.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + exit.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + _lock.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + args_main.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + memset.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + cpy_tbl.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + memcpy.c.obj + + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/ + archive + rts2800_fpu32_eabi.lib + startup.c.obj + + + + + codestart + 0x0 + true + true + 0x0 + 0x2 + 0x1 + + + + .text + 0xb000 + true + true + 0xb000 + 0x192 + 0x1 + + + + .text + 0xb192 + true + true + 0xb192 + 0x49 + 0x1 + + + + .text:decompress:lzss + 0xb1db + true + true + 0xb1db + 0x2e + 0x1 + + + + .text:__TI_auto_init_nobinit_nopinit + 0xb209 + true + true + 0xb209 + 0x2b + 0x1 + + + + .text + 0xb234 + true + true + 0xb234 + 0x29 + 0x1 + + + + .text + 0xb25d + true + true + 0xb25d + 0x20 + 0x1 + + + + .text + 0xb27d + true + true + 0xb27d + 0x17 + 0x1 + + + + .text + 0xb294 + true + true + 0xb294 + 0x12 + 0x1 + + + + .text + 0xb2a6 + true + true + 0xb2a6 + 0x9 + 0x1 + + + + .text + 0xb2af + true + true + 0xb2af + 0x8 + 0x1 + + + + .text:decompress:none + 0xb2b7 + true + true + 0xb2b7 + 0x8 + 0x1 + + + + .text + 0xb2bf + true + true + 0xb2bf + 0x2 + 0x1 + + + + .text + 0xb2c1 + true + true + 0xb2c1 + 0x1 + 0x1 + + + + .cinit..data.load + 0xa2 + true + 0xa2 + 0x9 + 0x1 + + + __TI_handler_table + 0xac + true + 0xac + 0x4 + 0x2 + + + __TI_cinit_table + 0xb0 + true + 0xb0 + 0x4 + 0x2 + + + .stack + true + true + 0x400 + 0x0 + 0x1 + + + + .stack + true + true + 0x400 + 0x0 + 0x2 + + + .const:.string + 0xa800 + true + 0xa800 + 0x50 + 0x2 + + + + .data + 0xa850 + true + 0xa850 + 0x6 + 0x2 + + + + .data + 0xa856 + true + 0xa856 + 0x6 + 0x2 + + + + .data:_lock + 0xa85c + true + 0xa85c + 0x2 + 0x2 + + + + .data:_unlock + 0xa85e + true + 0xa85e + 0x2 + 0x2 + + + + .debug_types + 0x0 + 0x0 + 0x3fb + 0x0 + + + + .debug_types + 0x3fb + 0x3fb + 0x93b + 0x0 + + + + .debug_types + 0x0 + 0x0 + 0x0 + 0x0 + + + + .debug_types + 0xd36 + 0xd36 + 0x4e8 + 0x0 + + + + .debug_types + 0x121e + 0x121e + 0x1c8 + 0x0 + + + + .debug_types + 0x13e6 + 0x13e6 + 0x191 + 0x0 + + + + .debug_types + 0x1577 + 0x1577 + 0xbf + 0x0 + + + + .debug_types + 0x1636 + 0x1636 + 0x2f + 0x0 + + + + .debug_types + 0x1665 + 0x1665 + 0xe1 + 0x0 + + + + .debug_types + 0x1746 + 0x1746 + 0xe3 + 0x0 + + + + .debug_types + 0x0 + 0x0 + 0x0 + 0x0 + + + + .debug_info + 0x0 + 0x0 + 0x32e + 0x0 + + + + .debug_info + 0x32e + 0x32e + 0x134 + 0x0 + + + + .debug_info + 0x462 + 0x462 + 0x135 + 0x0 + + + + .debug_info + 0x597 + 0x597 + 0x17f + 0x0 + + + + .debug_info + 0x716 + 0x716 + 0xf50 + 0x0 + + + + .debug_info + 0x1666 + 0x1666 + 0x148 + 0x0 + + + + .debug_info + 0x17ae + 0x17ae + 0x13d + 0x0 + + + + .debug_info + 0x18eb + 0x18eb + 0x1af + 0x0 + + + + .debug_info + 0x1a9a + 0x1a9a + 0x1a7 + 0x0 + + + + .debug_info + 0x1c41 + 0x1c41 + 0x1fc + 0x0 + + + + .debug_info + 0x1e3d + 0x1e3d + 0x18e + 0x0 + + + + .debug_info + 0x1fcb + 0x1fcb + 0x199 + 0x0 + + + + .debug_info + 0x2164 + 0x2164 + 0xf7 + 0x0 + + + + .debug_info + 0x225b + 0x225b + 0xfb + 0x0 + + + + .debug_info + 0x2356 + 0x2356 + 0x1f3 + 0x0 + + + + .debug_info + 0x2549 + 0x2549 + 0x15d + 0x0 + + + + .debug_info + 0x26a6 + 0x26a6 + 0x18b + 0x0 + + + + .debug_info + 0x2831 + 0x2831 + 0x137 + 0x0 + + + + .debug_info + 0x2968 + 0x2968 + 0xd4 + 0x0 + + + .debug_line + 0x0 + 0x0 + 0xf7 + 0x0 + + + + .debug_line + 0xf7 + 0xf7 + 0x21 + 0x0 + + + + .debug_line + 0x118 + 0x118 + 0x55 + 0x0 + + + + .debug_line + 0x16d + 0x16d + 0x5d + 0x0 + + + + .debug_line + 0x1ca + 0x1ca + 0x37 + 0x0 + + + + .debug_line + 0x201 + 0x201 + 0x2a4 + 0x0 + + + + .debug_line + 0x4a5 + 0x4a5 + 0x8c + 0x0 + + + + .debug_line + 0x531 + 0x531 + 0x4f + 0x0 + + + + .debug_line + 0x580 + 0x580 + 0x3f + 0x0 + + + + .debug_line + 0x5bf + 0x5bf + 0x21 + 0x0 + + + + .debug_line + 0x5e0 + 0x5e0 + 0x74 + 0x0 + + + + .debug_line + 0x654 + 0x654 + 0x21 + 0x0 + + + + .debug_line + 0x675 + 0x675 + 0x57 + 0x0 + + + + .debug_line + 0x6cc + 0x6cc + 0x21 + 0x0 + + + + .debug_line + 0x6ed + 0x6ed + 0x9a + 0x0 + + + + .debug_line + 0x787 + 0x787 + 0x21 + 0x0 + + + + .debug_line + 0x7a8 + 0x7a8 + 0x2b + 0x0 + + + + .debug_line + 0x7d3 + 0x7d3 + 0x66 + 0x0 + + + + .debug_line + 0x839 + 0x839 + 0x21 + 0x0 + + + + .debug_line + 0x85a + 0x85a + 0x2c + 0x0 + + + + .debug_line + 0x886 + 0x886 + 0x2c + 0x0 + + + + .debug_line + 0x8b2 + 0x8b2 + 0x5f + 0x0 + + + + .debug_line + 0x911 + 0x911 + 0x21 + 0x0 + + + + .debug_line + 0x932 + 0x932 + 0x50 + 0x0 + + + + .debug_line + 0x982 + 0x982 + 0x30 + 0x0 + + + + .debug_line + 0x9b2 + 0x9b2 + 0x57 + 0x0 + + + + .debug_line + 0xa09 + 0xa09 + 0x21 + 0x0 + + + + .debug_line + 0xa2a + 0xa2a + 0x3b + 0x0 + + + + .debug_line + 0xa65 + 0xa65 + 0x21 + 0x0 + + + + .debug_frame + 0x0 + 0x0 + 0x7c + 0x4 + + + + .debug_frame + 0x7c + 0x7c + 0x170 + 0x4 + + + + .debug_frame + 0x1ec + 0x1ec + 0x40 + 0x4 + + + + .debug_frame + 0x22c + 0x22c + 0x58 + 0x4 + + + + .debug_frame + 0x284 + 0x284 + 0x40 + 0x4 + + + + .debug_frame + 0x2c4 + 0x2c4 + 0x40 + 0x4 + + + + .debug_frame + 0x304 + 0x304 + 0x60 + 0x4 + + + + .debug_frame + 0x364 + 0x364 + 0x70 + 0x4 + + + + .debug_frame + 0x3d4 + 0x3d4 + 0x40 + 0x4 + + + + .debug_frame + 0x414 + 0x414 + 0x40 + 0x4 + + + + .debug_frame + 0x454 + 0x454 + 0x40 + 0x4 + + + + .debug_abbrev + 0x0 + 0x0 + 0xae + 0x0 + + + + .debug_abbrev + 0xae + 0xae + 0x4b + 0x0 + + + + .debug_abbrev + 0xf9 + 0xf9 + 0x25 + 0x0 + + + + .debug_abbrev + 0x11e + 0x11e + 0x25 + 0x0 + + + + .debug_abbrev + 0x143 + 0x143 + 0x28 + 0x0 + + + + .debug_abbrev + 0x16b + 0x16b + 0xcf + 0x0 + + + + .debug_abbrev + 0x23a + 0x23a + 0xa5 + 0x0 + + + + .debug_abbrev + 0x2df + 0x2df + 0x3d + 0x0 + + + + .debug_abbrev + 0x31c + 0x31c + 0x4b + 0x0 + + + + .debug_abbrev + 0x367 + 0x367 + 0x1c + 0x0 + + + + .debug_abbrev + 0x383 + 0x383 + 0x71 + 0x0 + + + + .debug_abbrev + 0x3f4 + 0x3f4 + 0xb3 + 0x0 + + + + .debug_abbrev + 0x4a7 + 0x4a7 + 0x6d + 0x0 + + + + .debug_abbrev + 0x514 + 0x514 + 0x44 + 0x0 + + + + .debug_abbrev + 0x558 + 0x558 + 0x5f + 0x0 + + + + .debug_abbrev + 0x5b7 + 0x5b7 + 0x44 + 0x0 + + + + .debug_abbrev + 0x5fb + 0x5fb + 0x28 + 0x0 + + + + .debug_abbrev + 0x623 + 0x623 + 0xa0 + 0x0 + + + + .debug_abbrev + 0x6c3 + 0x6c3 + 0x57 + 0x0 + + + + .debug_abbrev + 0x71a + 0x71a + 0x28 + 0x0 + + + + .debug_abbrev + 0x742 + 0x742 + 0x28 + 0x0 + + + + .debug_abbrev + 0x76a + 0x76a + 0x5f + 0x0 + + + + .debug_abbrev + 0x7c9 + 0x7c9 + 0x3a + 0x0 + + + + .debug_abbrev + 0x803 + 0x803 + 0x64 + 0x0 + + + + .debug_abbrev + 0x867 + 0x867 + 0x79 + 0x0 + + + + .debug_abbrev + 0x8e0 + 0x8e0 + 0x61 + 0x0 + + + + .debug_abbrev + 0x941 + 0x941 + 0x44 + 0x0 + + + + .debug_abbrev + 0x985 + 0x985 + 0x49 + 0x0 + + + + .debug_abbrev + 0x9ce + 0x9ce + 0x1c + 0x0 + + + + .debug_abbrev + 0x9ea + 0x9ea + 0xf + 0x0 + + + .debug_str + 0x0 + 0x0 + 0x6a + 0x0 + + + + .debug_str + 0x6a + 0x6a + 0x6a + 0x0 + + + + .debug_str + 0xd4 + 0xd4 + 0x6a + 0x0 + + + + .debug_str + 0x13e + 0x13e + 0x6a + 0x0 + + + + .debug_str + 0x1a8 + 0x1a8 + 0x6a + 0x0 + + + + .debug_str + 0x212 + 0x212 + 0x6a + 0x0 + + + + .debug_str + 0x27c + 0x27c + 0x6a + 0x0 + + + + .debug_str + 0x2e6 + 0x2e6 + 0x6a + 0x0 + + + + .debug_str + 0x350 + 0x350 + 0x6a + 0x0 + + + + .debug_str + 0x3ba + 0x3ba + 0x6a + 0x0 + + + + .debug_str + 0x424 + 0x424 + 0x6a + 0x0 + + + + .debug_aranges + 0x0 + 0x0 + 0x30 + 0x0 + + + + .debug_aranges + 0x30 + 0x30 + 0x20 + 0x0 + + + + .debug_aranges + 0x50 + 0x50 + 0x20 + 0x0 + + + + .debug_aranges + 0x70 + 0x70 + 0x80 + 0x0 + + + + .debug_aranges + 0xf0 + 0xf0 + 0x20 + 0x0 + + + + .debug_aranges + 0x110 + 0x110 + 0x20 + 0x0 + + + + .debug_aranges + 0x130 + 0x130 + 0x20 + 0x0 + + + + .debug_aranges + 0x150 + 0x150 + 0x20 + 0x0 + + + + .debug_aranges + 0x170 + 0x170 + 0x20 + 0x0 + + + + .debug_aranges + 0x190 + 0x190 + 0x28 + 0x0 + + + + .debug_aranges + 0x1b8 + 0x1b8 + 0x30 + 0x0 + + + + .debug_aranges + 0x1e8 + 0x1e8 + 0x20 + 0x0 + + + + .debug_aranges + 0x208 + 0x208 + 0x20 + 0x0 + + + + .debug_aranges + 0x228 + 0x228 + 0x20 + 0x0 + + + + .debug_pubnames + 0x0 + 0x0 + 0x41 + 0x0 + + + + .debug_pubnames + 0x41 + 0x41 + 0x44 + 0x0 + + + + .debug_pubnames + 0x85 + 0x85 + 0x45 + 0x0 + + + + .debug_pubnames + 0xca + 0xca + 0x4c + 0x0 + + + + .debug_pubnames + 0x116 + 0x116 + 0x17b + 0x0 + + + + .debug_pubnames + 0x291 + 0x291 + 0x1f + 0x0 + + + + .debug_pubnames + 0x2b0 + 0x2b0 + 0x27 + 0x0 + + + + .debug_pubnames + 0x2d7 + 0x2d7 + 0x35 + 0x0 + + + + .debug_pubnames + 0x30c + 0x30c + 0x2b + 0x0 + + + + .debug_pubnames + 0x337 + 0x337 + 0x2b + 0x0 + + + + .debug_pubnames + 0x362 + 0x362 + 0x5e + 0x0 + + + + .debug_pubnames + 0x3c0 + 0x3c0 + 0x25 + 0x0 + + + + .debug_pubnames + 0x3e5 + 0x3e5 + 0x1c + 0x0 + + + + .debug_pubnames + 0x401 + 0x401 + 0x1e + 0x0 + + + + .debug_pubnames + 0x41f + 0x41f + 0x43 + 0x0 + + + + .debug_pubnames + 0x462 + 0x462 + 0x21 + 0x0 + + + + .debug_pubnames + 0x483 + 0x483 + 0x1d + 0x0 + + + + .debug_pubnames + 0x4a0 + 0x4a0 + 0x29 + 0x0 + + + + + + codestart + 0x0 + 0x0 + 0x2 + + + + + + .text + 0xb000 + 0xb000 + 0x2c2 + + + + + + + + + + + + + + + + + + .text + + + + + + .cinit + 0xa2 + 0xa2 + 0x12 + + + + + + + + .switch + 0x0 + 0x0 + + + + + .reset + 0x3fffc0 + 0x0 + + + + + .stack + 0x400 + 0x100 + + + + + + + .bss + 0x0 + 0x0 + + + + + .bss:output + 0x0 + 0x0 + + + + + .init_array + 0x0 + 0x0 + + + + + .const + 0xa800 + 0xa800 + 0x50 + + + + + + .data + 0xa850 + 0x10 + + + + + + + + + .sysmem + 0x0 + 0x0 + + + + + .TI.ramfunc + 0x0 + 0x0 + + + + + PUTBUFFER + 0x0 + 0x0 + + + + + PUTWRITEIDX + 0x0 + 0x0 + + + + + GETREADIDX + 0x0 + 0x0 + + + + + GROUP_1 + 0x0 + 0x0 + + + + + + true + + + GETBUFFER + 0x3fc00 + 0x0 + + + + + GETWRITEIDX + 0x3fc00 + 0x0 + + + + + PUTREADIDX + 0x3fc00 + 0x0 + + + + + GROUP_2 + 0x3fc00 + 0x0 + + + + + + true + + + .ppdata + 0x0 + 0x0 + + + + + .debug_types + 0x0 + 0x0 + 0x1829 + + + + + + + + + + + + + + + + .debug_info + 0x0 + 0x0 + 0x2a3c + + + + + + + + + + + + + + + + + + + + + + + + .debug_line + 0x0 + 0x0 + 0xa86 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .debug_frame + 0x0 + 0x0 + 0x494 + + + + + + + + + + + + + + + + .debug_abbrev + 0x0 + 0x0 + 0x9f9 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .debug_str + 0x0 + 0x0 + 0x48e + + + + + + + + + + + + + + + + .debug_aranges + 0x0 + 0x0 + 0x248 + + + + + + + + + + + + + + + + + + + .debug_pubnames + 0x0 + 0x0 + 0x4c9 + + + + + + + + + + + + + + + + + + + + + + + SEGMENT_0 + 0x0 + 0x0 + 0x2 + 0x5 + + + + + + SEGMENT_1 + 0xa2 + 0xa2 + 0x12 + 0x4 + + + + + + SEGMENT_2 + 0xb000 + 0xb000 + 0x2c2 + 0x5 + + + + + + SEGMENT_3 + 0x400 + 0x100 + 0x6 + + + + + + SEGMENT_4 + 0xa800 + 0xa800 + 0x50 + 0x4 + + + + + + SEGMENT_5 + 0xa850 + 0x10 + 0x6 + + + + + + + + BEGIN + 0x0 + 0x0 + 0x2 + 0x2 + 0x0 + RWIX + + + 0x0 + 0x2 + + + + + + RAMM0 + 0x0 + 0xa2 + 0x35e + 0x12 + 0x34c + RWIX + + + 0xa2 + 0x12 + + + + 0xb4 + 0x34c + + + + + RAMLS0 + 0x0 + 0x8000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS1 + 0x0 + 0x8800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS2 + 0x0 + 0x9000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS3 + 0x0 + 0x9800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS4 + 0x0 + 0xa000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMD0 + 0x0 + 0xb000 + 0x800 + 0x2c2 + 0x53e + RWIX + + + 0xb000 + 0x2c2 + + + + 0xb2c2 + 0x53e + + + + + FLASHA + 0x0 + 0x80002 + 0x1ffe + 0x0 + 0x1ffe + RWIX + + + + + FLASHB + 0x0 + 0x82000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHC + 0x0 + 0x84000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHD + 0x0 + 0x86000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHE + 0x0 + 0x88000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHF + 0x0 + 0x90000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHG + 0x0 + 0x98000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHH + 0x0 + 0xa0000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHI + 0x0 + 0xa8000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHJ + 0x0 + 0xb0000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHK + 0x0 + 0xb8000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHL + 0x0 + 0xba000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHM + 0x0 + 0xbc000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHN + 0x0 + 0xbe000 + 0x1ff0 + 0x0 + 0x1ff0 + RWIX + + + + + RESET + 0x0 + 0x3fffc0 + 0x2 + 0x0 + 0x2 + RWIX + + + + + BOOT_RSVD + 0x1 + 0x2 + 0xa0 + 0x0 + 0xa0 + RWIX + + + + + RAMM1 + 0x1 + 0x400 + 0x3f8 + 0x100 + 0x2f8 + RWIX + + + 0x400 + 0x100 + + + + 0x500 + 0x2f8 + + + + + RAMLS5 + 0x1 + 0xa800 + 0x800 + 0x60 + 0x7a0 + RWIX + + + 0xa800 + 0x50 + + + + 0xa850 + 0x10 + + + + 0xa860 + 0x7a0 + + + + + RAMD1 + 0x1 + 0xb800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + CPU2TOCPU1RAM + 0x1 + 0x3f800 + 0x400 + 0x0 + 0x400 + RWIX + + + + + CPU1TOCPU2RAM + 0x1 + 0x3fc00 + 0x400 + 0x0 + 0x400 + RWIX + + + + + CANA_MSG_RAM + 0x1 + 0x49000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + CANB_MSG_RAM + 0x1 + 0x4b000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + + + __TI_cinit_table + + .data + 0xa2 + 0x9 + 0xa850 + 0x10 + lzss + + + + + __TI_handler_table + + 0x0 + __TI_decompress_lzss + + + 0x1 + __TI_decompress_none + + + + + __TI_CINIT_Base + 0xb0 + + + __TI_CINIT_Limit + 0xb4 + + + __TI_CINIT_Warm + 0xb4 + + + __TI_Handler_Table_Base + 0xac + + + __TI_Handler_Table_Limit + 0xb0 + + + __TI_STACK_SIZE + 0x100 + + + __TI_STACK_END + 0x500 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + main + 0xb1c5 + + + + code_start + 0x0 + + + + Device_enableAllPeripherals + 0xb040 + + + + Device_initGPIO + 0xb119 + + + + Example_Fail + 0xa854 + + + + Example_setResultFail + 0xb18c + + + + Device_init + 0xb037 + + + + Example_Result + 0xa850 + + + + Device_enableUnbondedGPIOPullups + 0xb16a + + + + __error__ + 0xb180 + + + + Example_setResultPass + 0xb187 + + + + Device_enableUnbondedGPIOPullupsFor176Pin + 0xb13a + + + + Example_done + 0xb191 + + + + Example_PassCount + 0xa852 + + + + Device_enableUnbondedGPIOPullupsFor100Pin + 0xb14d + + + + _c_int00 + 0xb27d + + + + __stack + 0x400 + + + + _system_pre_init + 0xb2bf + + + + __TI_auto_init_nobinit_nopinit + 0xb209 + + + + __TI_decompress_none + 0xb2b7 + + + + __TI_decompress_lzss + 0xb1db + + + + C$$EXIT + 0xb234 + + + + abort + 0xb234 + + + + exit + 0xb236 + + + + __TI_dtors_ptr + 0xa85a + + + + __TI_cleanup_ptr + 0xa858 + + + + __TI_enable_exit_profile_output + 0xa856 + + + + _nop + 0xb2ae + + + + _lock + 0xa85c + + + + _unlock + 0xa85e + + + + _register_lock + 0xb2aa + + + + _register_unlock + 0xb2a6 + + + + _args_main + 0xb294 + + + + memcpy + 0xb25d + + + + _system_post_cinit + 0xb2c1 + + + + Link successful + diff --git a/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.d b/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.d new file mode 100644 index 0000000..0b29d5d --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.d @@ -0,0 +1,267 @@ +# FIXED + +gpio_driverlib_main_cpu2.obj: ../gpio_driverlib_main_cpu2.c +gpio_driverlib_main_cpu2.obj: /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/device/driverlib.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memmap.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cla.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cla.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/clb.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clb.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cmpss.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cmpss.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cputimer.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cputimer.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dac.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dac.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dcsm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dcsm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dma.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dma.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ecap.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ecap.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/emif.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_emif.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memcfg.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/epwm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/eqep.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_eqep.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/flash.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_flash.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/gpio.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_gpio.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xint.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/xbar.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clbxbar.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwmxbar.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_inputxbar.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_outputxbar.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xbar.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_hrpwm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/i2c.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_i2c.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hw_reg_inclusive_terminology.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ipc.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ipc.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/mcbsp.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_mcbsp.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/memcfg.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map_legacy.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sci.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sci.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sdfm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sdfm.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/spi.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_spi.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/upp.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_upp.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/version.h +gpio_driverlib_main_cpu2.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/driver_inclusive_terminology_mapping.h +gpio_driverlib_main_cpu2.obj: /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/device/device.h + +../gpio_driverlib_main_cpu2.c: + +/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/device/driverlib.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memmap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h: + +/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cla.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cla.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/clb.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clb.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cmpss.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cmpss.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cputimer.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_cputimer.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dac.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dac.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dcsm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dcsm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/dma.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_dma.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ecap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ecap.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/emif.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_emif.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_memcfg.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/epwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/eqep.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_eqep.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/flash.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_flash.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/gpio.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_gpio.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xint.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/xbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_clbxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_epwmxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_inputxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_outputxbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_xbar.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hrpwm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/i2c.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_i2c.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/hw_reg_inclusive_terminology.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ipc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ipc.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/mcbsp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_mcbsp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/memcfg.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/pin_map_legacy.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sci.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sci.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sdfm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sdfm.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/spi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_spi.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/upp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_upp.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/version.h: + +/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/driver_inclusive_terminology_mapping.h: + +/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/device/device.h: + diff --git a/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.obj b/gpio_driverlib_cpu2/CPU2_RAM/gpio_driverlib_main_cpu2.obj new file mode 100644 index 0000000000000000000000000000000000000000..e5eb41583746fb4bbcff7b0c6fd8061bf13cff37 GIT binary patch literal 6784 zcmds6eQX@X6@RmLdtT?_#E$bpAUFqcf;T%s5aP!WGQ%2J9LeQpX6- zcWAPZO%p9eQPG;Ny8o4zZ|t3l0CH%7WTB8Fq0t33;uDqM-*I%y7r*Nzma=2{OgfSp zH!Tt&c;Og6IW_+eH+_FWyO&?dds-M+Yp2D&eTQCkRKyWcTe88%~`Maz8!zbOLQz( zThvic&6f=?E^E2`rQ2Wgw9pcX3cTpV@Se#CvbuH@zH?6E%iyOJ`$r9VeNIq%r<73*U4UbbhRRI@sF^gQ&H!Hqxr^O2&r+4fw)M4ScP zo*$fecCz!(Ei1jubfJ>WWhfYQzaSUi@y79=zV_~iUaIuG#&^x(Go$OCd*JA6C%kiL zzh*%;X)8OKv2xjDV#3Vk z6RBdQE1F_YNQ-SLWvo(cY{ImrV!0iu*p7mA9bTVeDYm_~#x@pr(sWATk!x)PfPuAtH3$mkWDySqB#T^$`Ak@ek?cr3nRMI>HG zXT~!5$d-I|Dl*x%GTPZ0?TC(yZbnUUrgeo^jKYIbWH?_c zTa}4SzRcxR!73Ikvz$qj2rR?66N!vv6|6*p8pO()BJ5cfb}SQ}ANY5siKlA#|7p5{ zWlR?bgM9CJXd!KZ)IT|9+QhDqcJr6BWbcx7>o*Qxnb=`v%bAU^wi=dv(4~Nk%kUt* zRU?x8YzgG8W{!_7q*=&9ylqFgpAs7=7IWE@S( z3NhvLQfN0%7Aj@T+i4xgKz8#e*O_H=Q)Z0pJsS8f4DbrGbe+?-x=ya8XvDzkYOl>1 zPz^p*h`xjzly?!n?@c#g{Pw+1&}TOCbS7CD!}`c1#9w8n2k_+1=Kq&ERWX5HJ~{HG zQ#t||aV!FFiw0f4P!}gcng;hs*EljzaXf&E{&$`^tk?Htb@6$pUY>87-WZqlo*YW3_H7<*s9w=R0+~M!62xu;B>KjV2K= z8W%K&&oY)8xAuqevP6Yw4j5~~7l!-77cE@7FmIqK=-L?p!_}lo%n=`N#;9zn=Z*dS z##j6G1O4H<`tceDt9Bhim@P|6*rw=y%5cO_3H3OB)E&4%P{3#sxAZSWfV0*l4sw~q zZ0Zh6U+05S9SW;~R;c0dB^YLK84WjMrB_N3>O%!yngP+cU@4~3*avIeg8p|$AK&I> zSgK>6JLe7EURiq;8Rv8{a+S|#;50P3@AHA+-*}z<+S%XPzyL?+=r9S64Sk?g%1q$i zWRY>^jF~e9&ts~qcgjp=N$@rr6d^G~%&c|^y_V3UlY-iN(~BGp9%@2f!!WxtvCexD zmcY?_QQ}c@;`$-TGo@D5M^KKs^i3#ty7a41zQm$sKz`10}Ubw1sodunv_S5FUk^cnO6j~?*Vhv~LBA1}@TZj}@BxKyR=AuO;8}%VukgJrf#0j}hZX*q z!hfRh-zxkSg@2&%I-WQ58)gYR?JRj76dqT2O5qiS?^O69h2O7m{5B-*98>tO75<{a z-%^^=G~36MV=Er zqM!E^9F_aGkH^0!y6v5)C#v{3tonJ08AKm`3f@+niRYYx*9Xkq?-Y2uT|9f}yl1$1 z?}Nv__>-Tv1p5b{um0rc{RX_t{UqpoX1V)aglpWjr{I}B-hS|Szw@Ue0Jpuz!5i?C zpzlM*w#sywJ_K*It+?dZP_|=-;f`7OzXo)`XYpAKAT=U?0~t$NO90!T;TqxiW1xHl z86mP4LZ&wGJneuo?@44g-UA-*(`--v01C;xUm&}ABQBo3wx{By!MhV}*&ae$Cg#0@ z?6&tlcx{*f=3%~MV%`a4H*b+Tf0$?E%=@QHN0COri$F3DQz;Yk_-5N&tT#40x0j-8fPyhe` literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/makefile b/gpio_driverlib_cpu2/CPU2_RAM/makefile new file mode 100644 index 0000000..b1c9797 --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/makefile @@ -0,0 +1,149 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +CG_TOOL_ROOT := /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./gpio_driverlib_main_cpu2.obj" \ +"./device/F2837xD_CodeStartBranch.obj" \ +"./device/device.obj" \ +"../2837xD_RAM_lnk_cpu2.cmd" \ +"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := rm -rf +RMDIR := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include device/subdir_vars.mk +-include subdir_rules.mk +-include device/subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +gpio_driverlib_cpu2.out + +EXE_OUTPUTS__QUOTED += \ +"gpio_driverlib_cpu2.out" + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(LIB_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "gpio_driverlib_cpu2.out" + +# Tool invocations +gpio_driverlib_cpu2.out: $(OBJS) $(CMD_SRCS) $(LIB_SRCS) $(GEN_CMDS) + @echo 'C2000 Linker - building target: "$@"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --define=DEBUG --define=CPU2 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi -z -m"gpio_driverlib_cpu2.map" --stack_size=0x100 --warn_sections -i"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib" -i"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="gpio_driverlib_cpu2_linkInfo.xml" --entry_point=code_start --rom_model -o "gpio_driverlib_cpu2.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(EXE_OUTPUTS__QUOTED) + -$(RM) "gpio_driverlib_main_cpu2.obj" "device/F2837xD_CodeStartBranch.obj" "device/device.obj" + -$(RM) "gpio_driverlib_main_cpu2.d" "device/device.d" + -$(RM) "device/F2837xD_CodeStartBranch.d" + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/gpio_driverlib_cpu2/CPU2_RAM/objects.mk b/gpio_driverlib_cpu2/CPU2_RAM/objects.mk new file mode 100644 index 0000000..ad64ce9 --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/gpio_driverlib_cpu2/CPU2_RAM/sources.mk b/gpio_driverlib_cpu2/CPU2_RAM/sources.mk new file mode 100644 index 0000000..beb2fed --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/sources.mk @@ -0,0 +1,110 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +SA_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ +device \ + diff --git a/gpio_driverlib_cpu2/CPU2_RAM/subdir_rules.mk b/gpio_driverlib_cpu2/CPU2_RAM/subdir_rules.mk new file mode 100644 index 0000000..dc43bd7 --- /dev/null +++ b/gpio_driverlib_cpu2/CPU2_RAM/subdir_rules.mk @@ -0,0 +1,12 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'C2000 Compiler - building file: "$<"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2" --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_driverlib_cpu2/device" --include_path="/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/" --include_path="/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --define=DEBUG --define=CPU2 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="$(basename $(>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/gpio_driverlib_cpu2/device/device.c b/gpio_driverlib_cpu2/device/device.c new file mode 100644 index 0000000..b64b33d --- /dev/null +++ b/gpio_driverlib_cpu2/device/device.c @@ -0,0 +1,706 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#include "inc/hw_ipc.h" + +#ifdef CMDTOOL +#include "device_cmd.h" +#endif + +#ifdef __cplusplus +using std::memcpy; +#endif + +#define PASS 0 +#define FAIL 1 + +uint32_t Example_Result = FAIL; +uint32_t Example_PassCount = 0; +uint32_t Example_Fail = 0; + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef CMDTOOL + CMD_init(); +#endif + +#ifdef _FLASH +#ifndef CMDTOOL + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); +#endif + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + + // + // Configure Analog Trim in case of untrimmed or TMX sample + // + if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) && + (HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U)) + { + Device_configureTMXAnalogTrim(); + } + + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the Device_init function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // Sysctl_deviceCal is a wrapper function for Device_Cal + // + SysCtl_deviceCal(); +#endif + +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); + + // + // Initialize result parameter as FAIL + // + Example_Result = FAIL; +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +#ifdef CPU1 +//***************************************************************************** +// +// Function to implement Analog trim of TMX devices +// +//***************************************************************************** +void Device_configureTMXAnalogTrim(void) +{ + // + // Enable ADC clock + // + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + // + // Configure ADC reference trim for TMX devices + // + EALLOW; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU; + + // + // Configure ADC offset trim. The user should generate the trim values + // by following the instructions in the "ADC Zero Offset Calibration" + // section in device TRM. The below lines needs to be uncommented and + // updated with the correct trim values. + // +// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U; + + // + // Configure internal oscillator trim. If the internal oscillator trim + // contains all zeros, the user can adjust the lowest 10 bits of the + // oscillator trim register between 1 (minimum) and 1023 (maximum) + // while observing the system clock on the XCLOCKOUT pin. The below + // lines needs to be uncommented and updated with the correct trim values. + // +// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U; +// } +// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U; +// } + + EDIS; + + // + // Disable ADC clock + // + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD); +} + +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +Device_bootCPU2(uint32_t bootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) & + 0x80000000U)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & + C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) || + ((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U)) + { + + } + + if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (bootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + // + //SCIA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_29_SCITXDA); + GPIO_setMasterCore(29, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_28_SCIRXDA); + GPIO_setMasterCore(28, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + + // + //SPI-A connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + EDIS; + + GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_16_SPISIMOA); + GPIO_setMasterCore(16, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_17_SPISOMIA); + GPIO_setMasterCore(17, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_18_SPICLKA); + GPIO_setMasterCore(18, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_19_GPIO19); + GPIO_setMasterCore(19, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + + // + //I2CA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_32_SDAA); + GPIO_setMasterCore(32, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_33_SCLA); + GPIO_setMasterCore(33, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC); + GPIO_setMasterCore(pin, GPIO_CORE_CPU2); + } + + GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_69_GPIO69); + GPIO_setMasterCore(69, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_70_GPIO70); + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + GPIO_setMasterCore(71, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_71_CANTXA); + GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC); + + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_70_CANRXA); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + + + GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + // + // Set CANA Bit-Clock Source Select = SYSCLK and enable CAN + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + SYSCTL_CLKSRCCTL2_CANABCLKSEL_M; + EDIS; + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U; + + } + return returnStatus; +} +#endif // #ifdef CPU1 +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(const char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} + +void Example_setResultPass(void) +{ + Example_Result = PASS; +} + +void Example_setResultFail(void) +{ + Example_Result = FAIL; +} + +void Example_done(void) +{ + while(1); +} diff --git a/gpio_driverlib_cpu2/device/device.h b/gpio_driverlib_cpu2/device/device.h new file mode 100644 index 0000000..ec143e5 --- /dev/null +++ b/gpio_driverlib_cpu2/device/device.h @@ -0,0 +1,394 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9 +#else +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 +#endif + + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX +#else +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX +#endif + +// +// GPIO assignment for CAN-A and CAN-B +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX +#else +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//I2CA GPIO pins +#define DEVICE_GPIO_PIN_SDAA 104 +#define DEVICE_GPIO_PIN_SCLA 105 + +#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA +#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA + + +//I2CB GPIO pins +#define DEVICE_GPIO_PIN_SDAB 40 +#define DEVICE_GPIO_PIN_SCLB 41 + +#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB +#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB + +#endif + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +// +// The macros that can be used as parameter to the function Device_bootCPU2 +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU + +// +// Other macros that are needed for the Device_bootCPU2 function +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U + +// +// Macros used as return value by the Device_bootCPU2 function +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +extern uint32_t Example_PassCount; +extern uint32_t Example_Fail; + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup device_api +//! @{ +// +//***************************************************************************** +//***************************************************************************** +// +//! @brief Function to initialize the device. Primarily initializes system control to a +//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +//! and enabling the clocks to the peripherals. +//! +//! \param None. +//! \return None. +// +//***************************************************************************** +extern void Device_init(void); +//***************************************************************************** +//! +//! +//! @brief Function to turn on all peripherals, enabling reads and writes to the +//! peripherals' registers. +//! +//! Note that to reduce power, unused peripherals should be disabled. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableAllPeripherals(void); +//***************************************************************************** +//! +//! +//! @brief Function to disable pin locks on GPIOs. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_initGPIO(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package: +//! GPIOs Grp Bits +//! 95-132 C 31 +//! D 31:0 +//! E 4:0 +//! 134-168 E 31:6 +//! F 8:0 +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package: +//! GPIOs Grp Bits +//! 0-1 A 1:0 +//! 5-9 A 9:5 +//! 22-40 A 31:22 +//! B 8:0 +//! 44-57 B 25:12 +//! 67-68 C 4:3 +//! 74-77 C 13:10 +//! 79-83 C 19:15 +//! 93-168 C 31:29 +//! D 31:0 +//! E 31:0 +//! F 8:0 +//! @param None +//! @return None +// +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the +//! 176PTP package. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullups(void); +#ifdef CPU1 +//***************************************************************************** +//! +//! @brief Function to implement Analog trim of TMX devices +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_configureTMXAnalogTrim(void); +//***************************************************************************** +//! @brief Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +extern uint16_t Device_bootCPU2(uint32_t ulBootMode); +#endif +//***************************************************************************** +//! +//! @brief Error handling function to be called when an ASSERT is violated +//! +//! @param *filename File name in which the error has occurred +//! @param line Line number within the file +//! @return None +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); +extern void Example_setResultPass(void); +extern void Example_setResultFail(void); +extern void Example_done(void); + +// +// End of file +// diff --git a/gpio_driverlib_cpu2/device/driverlib.h b/gpio_driverlib_cpu2/device/driverlib.h new file mode 100644 index 0000000..932ace6 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib.h @@ -0,0 +1,87 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "clb.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "ipc.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "pin_map_legacy.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#include "driver_inclusive_terminology_mapping.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/gpio_driverlib_cpu2/device/driverlib/adc.c b/gpio_driverlib_cpu2/device/driverlib/adc.c new file mode 100644 index 0000000..9e74809 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/adc.c @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: adc.c +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "adc.h" + +//***************************************************************************** +// +// Defines for locations of ADC calibration functions in OTP for use in +// ADC_setMode() ONLY. Not intended for use by application code. +// +//***************************************************************************** +// +// The following functions calibrate the ADC linearity. Use them in the +// ADC_setMode() function only. +// +#define ADC_calADCAINL 0x0703B4U +#define ADC_calADCBINL 0x0703B2U +#define ADC_calADCCINL 0x0703B0U +#define ADC_calADCDINL 0x0703AEU + +// +// This function looks up the ADC offset trim for a given condition. Use this +// in the ADC_setMode() function only. +// +#define ADC_getOffsetTrim 0x0703ACU + +//***************************************************************************** +// +// ADC_setMode +// +//***************************************************************************** +void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Check for correct signal mode & resolution. In this device: + // Single ended signal conversions are supported in 12-bit mode only + // Differential signal conversions are supported in 16-bit mode only + // + if(signalMode == ADC_MODE_SINGLE_ENDED) + { + ASSERT(resolution == ADC_RESOLUTION_12BIT); + } + else + { + ASSERT(resolution == ADC_RESOLUTION_16BIT); + } + + + // + // Apply the resolution and signalMode to the specified ADC. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE)) | + ((uint16_t)resolution | (uint16_t)signalMode); + EDIS; + + // + // Apply INL and offset trims + // + ADC_setINLTrim(base); + ADC_setOffsetTrim(base); +} + +//***************************************************************************** +// +// ADC_setINLTrim +// +//***************************************************************************** +void +ADC_setINLTrim(uint32_t base) +{ + ADC_Resolution resolution; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + + EALLOW; + switch(base) + { + case ADCA_BASE: + if(HWREGH(ADC_calADCAINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCAINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCB_BASE: + if(HWREGH(ADC_calADCBINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCBINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCC_BASE: + if(HWREGH(ADC_calADCCINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCCINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCD_BASE: + if(HWREGH(ADC_calADCDINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCDINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + default: + // + // Invalid base address! Do nothing! + // + break; + } + + // + // Apply linearity trim workaround for 12-bit resolution + // + if(resolution == ADC_RESOLUTION_12BIT) + { + // + // 12-bit linearity trim workaround + // + HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U; + } + EDIS; +} + +//***************************************************************************** +// +// ADC_setOffsetTrim +// +//***************************************************************************** +void +ADC_setOffsetTrim(uint32_t base) +{ + uint16_t offsetIndex = 0U; + uint16_t offsetTrim = 0U; + ADC_Resolution resolution; + ADC_SignalMode signalMode; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + signalMode = (ADC_SignalMode) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE); + + switch(base) + { + case ADCA_BASE: + offsetIndex = (uint16_t)(0U * 4U); + break; + case ADCB_BASE: + offsetIndex = (uint16_t)(1U * 4U); + break; + case ADCC_BASE: + offsetIndex = (uint16_t)(2U * 4U); + break; + case ADCD_BASE: + offsetIndex = (uint16_t)(3U * 4U); + break; + default: + // + // Invalid base address! + // + offsetIndex = 0U; + break; + } + + // + // Offset trim function is programmed into OTP, so call it + // + if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU) + { + // + // Calculate the index into OTP table of offset trims and call + // function to return the correct offset trim + // + offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) + + (2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U)); + + offsetTrim = + (*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex); + } + else + { + // + // Offset trim function is not populated, so set offset trim to 0 + // + offsetTrim = 0U; + } + + // + // Apply the offset trim. Offset Trim is not updated here in case of TMX or + // untrimmed devices. The default trims for TMX devices should be handled in + // Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim() + // APIs for more details. + // + if(offsetTrim > 0x0U) + { + EALLOW; + HWREGH(base + ADC_O_OFFTRIM) = offsetTrim; + EDIS; + } +} + + +//***************************************************************************** +// +// ADC_setPPBTripLimits +// +//***************************************************************************** +void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit) +{ + uint32_t ppbHiOffset; + uint32_t ppbLoOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((tripHiLimit <= 65535) && (tripHiLimit >= -65536)); + ASSERT((tripLoLimit <= 65535) && (tripLoLimit >= -65536)); + + // + // Get the offset to the appropriate trip limit registers. + // + ppbHiOffset = (ADC_PPBxTRIPHI_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPHI; + ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPLO; + + EALLOW; + + // + // Set the trip high limit. + // + HWREG(base + ppbHiOffset) = + (HWREG(base + ppbHiOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripHiLimit & ADC_PPBTRIP_MASK); + + // + // Set the trip low limit. + // + HWREG(base + ppbLoOffset) = + (HWREG(base + ppbLoOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripLoLimit & ADC_PPBTRIP_MASK); + + EDIS; +} diff --git a/gpio_driverlib_cpu2/device/driverlib/adc.h b/gpio_driverlib_cpu2/device/driverlib/adc.h new file mode 100644 index 0000000..136638d --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/adc.h @@ -0,0 +1,2098 @@ +//########################################################################### +// +// FILE: adc.h +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ADC_H +#define ADC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup adc_api ADC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_adc.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define ADC_NUM_INTERRUPTS 4U + +#define ADC_SOCxCTL_OFFSET_BASE ADC_O_SOC0CTL +#define ADC_RESULTx_OFFSET_BASE ADC_O_RESULT0 +#define ADC_INTSELxNy_OFFSET_BASE ADC_O_INTSEL1N2 +#define ADC_PPBxRESULT_OFFSET_BASE ADC_O_PPB1RESULT + + +#define ADC_PPBxCONFIG_STEP (ADC_O_PPB2CONFIG - ADC_O_PPB1CONFIG) +#define ADC_PPBxTRIPHI_STEP (ADC_O_PPB2TRIPHI - ADC_O_PPB1TRIPHI) +#define ADC_PPBxTRIPLO_STEP (ADC_O_PPB2TRIPLO - ADC_O_PPB1TRIPLO) +#define ADC_PPBxOFFCAL_STEP (ADC_O_PPB2OFFCAL - ADC_O_PPB1OFFCAL) +#define ADC_PPBxOFFREF_STEP (ADC_O_PPB2OFFREF - ADC_O_PPB1OFFREF) +#define ADC_PPBxSTAMP_STEP (ADC_O_PPB2STAMP - ADC_O_PPB1STAMP) + +#define ADC_PPBTRIP_MASK ((uint32_t)ADC_PPB1TRIPHI_LIMITHI_M |\ + (uint32_t)ADC_PPB1TRIPHI_HSIGN) +// +// Slope of the temperature sensor based in degrees C in fixed point Q15 format +// +#define ADC_getTempSlope() (*(int16_t (*)(void))0x7036E)() + +// +// Offset of the temp sensor output at 0 degrees C +// +#define ADC_getTempOffset() (*(int16_t (*)(void))0x70372)() + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(), +// ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and +// ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also +// make up the enumerated bit field returned by ADC_getPPBEventStatus(). +// +//***************************************************************************** +#define ADC_EVT_TRIPHI 0x0001U //!< Trip High Event +#define ADC_EVT_TRIPLO 0x0002U //!< Trip Low Event +#define ADC_EVT_ZERO 0x0004U //!< Zero Crossing Event +#endif + +//***************************************************************************** +// +// Values that can be passed to ADC_forceMultipleSOC() as socMask parameter. +// These values can be OR'd together to trigger multiple SOCs at a time. +// +//***************************************************************************** +#define ADC_FORCE_SOC0 0x0001U //!< SW trigger ADC SOC 0 +#define ADC_FORCE_SOC1 0x0002U //!< SW trigger ADC SOC 1 +#define ADC_FORCE_SOC2 0x0004U //!< SW trigger ADC SOC 2 +#define ADC_FORCE_SOC3 0x0008U //!< SW trigger ADC SOC 3 +#define ADC_FORCE_SOC4 0x0010U //!< SW trigger ADC SOC 4 +#define ADC_FORCE_SOC5 0x0020U //!< SW trigger ADC SOC 5 +#define ADC_FORCE_SOC6 0x0040U //!< SW trigger ADC SOC 6 +#define ADC_FORCE_SOC7 0x0080U //!< SW trigger ADC SOC 7 +#define ADC_FORCE_SOC8 0x0100U //!< SW trigger ADC SOC 8 +#define ADC_FORCE_SOC9 0x0200U //!< SW trigger ADC SOC 9 +#define ADC_FORCE_SOC10 0x0400U //!< SW trigger ADC SOC 10 +#define ADC_FORCE_SOC11 0x0800U //!< SW trigger ADC SOC 11 +#define ADC_FORCE_SOC12 0x1000U //!< SW trigger ADC SOC 12 +#define ADC_FORCE_SOC13 0x2000U //!< SW trigger ADC SOC 13 +#define ADC_FORCE_SOC14 0x4000U //!< SW trigger ADC SOC 14 +#define ADC_FORCE_SOC15 0x8000U //!< SW trigger ADC SOC 15 + + + +//***************************************************************************** +// +//! Values that can be passed to ADC_setPrescaler() as the \e clkPrescale +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_CLK_DIV_1_0 = 0U, //!< ADCCLK = (input clock) / 1.0 + ADC_CLK_DIV_2_0 = 2U, //!< ADCCLK = (input clock) / 2.0 + ADC_CLK_DIV_2_5 = 3U, //!< ADCCLK = (input clock) / 2.5 + ADC_CLK_DIV_3_0 = 4U, //!< ADCCLK = (input clock) / 3.0 + ADC_CLK_DIV_3_5 = 5U, //!< ADCCLK = (input clock) / 3.5 + ADC_CLK_DIV_4_0 = 6U, //!< ADCCLK = (input clock) / 4.0 + ADC_CLK_DIV_4_5 = 7U, //!< ADCCLK = (input clock) / 4.5 + ADC_CLK_DIV_5_0 = 8U, //!< ADCCLK = (input clock) / 5.0 + ADC_CLK_DIV_5_5 = 9U, //!< ADCCLK = (input clock) / 5.5 + ADC_CLK_DIV_6_0 = 10U, //!< ADCCLK = (input clock) / 6.0 + ADC_CLK_DIV_6_5 = 11U, //!< ADCCLK = (input clock) / 6.5 + ADC_CLK_DIV_7_0 = 12U, //!< ADCCLK = (input clock) / 7.0 + ADC_CLK_DIV_7_5 = 13U, //!< ADCCLK = (input clock) / 7.5 + ADC_CLK_DIV_8_0 = 14U, //!< ADCCLK = (input clock) / 8.0 + ADC_CLK_DIV_8_5 = 15U //!< ADCCLK = (input clock) / 8.5 +} ADC_ClkPrescale; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e resolution +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_RESOLUTION_12BIT = 0x00U, //!< 12-bit conversion resolution + ADC_RESOLUTION_16BIT = 0x40U //!< 16-bit conversion resolution +} ADC_Resolution; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e signalMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_MODE_SINGLE_ENDED = 0x00U, //!< Sample on single pin with VREFLO + ADC_MODE_DIFFERENTIAL = 0x80U //!< Sample on pair of pins +} ADC_SignalMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e trigger +//! parameter to specify the event that will trigger a conversion to start. +//! It is also used with ADC_setBurstModeConfig() and +//! ADC_triggerRepeaterSelect(). +// +//***************************************************************************** +typedef enum +{ + ADC_TRIGGER_SW_ONLY = 0U, //!< Software only + ADC_TRIGGER_CPU1_TINT0 = 1U, //!< CPU1 Timer 0, TINT0 + ADC_TRIGGER_CPU1_TINT1 = 2U, //!< CPU1 Timer 1, TINT1 + ADC_TRIGGER_CPU1_TINT2 = 3U, //!< CPU1 Timer 2, TINT2 + ADC_TRIGGER_GPIO = 4U, //!< GPIO, ADCEXTSOC + ADC_TRIGGER_EPWM1_SOCA = 5U, //!< ePWM1, ADCSOCA + ADC_TRIGGER_EPWM1_SOCB = 6U, //!< ePWM1, ADCSOCB + ADC_TRIGGER_EPWM2_SOCA = 7U, //!< ePWM2, ADCSOCA + ADC_TRIGGER_EPWM2_SOCB = 8U, //!< ePWM2, ADCSOCB + ADC_TRIGGER_EPWM3_SOCA = 9U, //!< ePWM3, ADCSOCA + ADC_TRIGGER_EPWM3_SOCB = 10U, //!< ePWM3, ADCSOCB + ADC_TRIGGER_EPWM4_SOCA = 11U, //!< ePWM4, ADCSOCA + ADC_TRIGGER_EPWM4_SOCB = 12U, //!< ePWM4, ADCSOCB + ADC_TRIGGER_EPWM5_SOCA = 13U, //!< ePWM5, ADCSOCA + ADC_TRIGGER_EPWM5_SOCB = 14U, //!< ePWM5, ADCSOCB + ADC_TRIGGER_EPWM6_SOCA = 15U, //!< ePWM6, ADCSOCA + ADC_TRIGGER_EPWM6_SOCB = 16U, //!< ePWM6, ADCSOCB + ADC_TRIGGER_EPWM7_SOCA = 17U, //!< ePWM7, ADCSOCA + ADC_TRIGGER_EPWM7_SOCB = 18U, //!< ePWM7, ADCSOCB + ADC_TRIGGER_EPWM8_SOCA = 19U, //!< ePWM8, ADCSOCA + ADC_TRIGGER_EPWM8_SOCB = 20U, //!< ePWM8, ADCSOCB + ADC_TRIGGER_EPWM9_SOCA = 21U, //!< ePWM9, ADCSOCA + ADC_TRIGGER_EPWM9_SOCB = 22U, //!< ePWM9, ADCSOCB + ADC_TRIGGER_EPWM10_SOCA = 23U, //!< ePWM10, ADCSOCA + ADC_TRIGGER_EPWM10_SOCB = 24U, //!< ePWM10, ADCSOCB + ADC_TRIGGER_EPWM11_SOCA = 25U, //!< ePWM11, ADCSOCA + ADC_TRIGGER_EPWM11_SOCB = 26U, //!< ePWM11, ADCSOCB + ADC_TRIGGER_EPWM12_SOCA = 27U, //!< ePWM12, ADCSOCA + ADC_TRIGGER_EPWM12_SOCB = 28U, //!< ePWM12, ADCSOCB + ADC_TRIGGER_CPU2_TINT0 = 29U, //!< CPU2 Timer 0, TINT0 + ADC_TRIGGER_CPU2_TINT1 = 30U, //!< CPU2 Timer 1, TINT1 + ADC_TRIGGER_CPU2_TINT2 = 31U //!< CPU2 Timer 2, TINT2 +} ADC_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e channel +//! parameter. This is the input pin on which the signal to be converted is +//! located. +// +//***************************************************************************** +typedef enum +{ + ADC_CH_ADCIN0 = 0U, //!< single-ended, ADCIN0 + ADC_CH_ADCIN1 = 1U, //!< single-ended, ADCIN1 + ADC_CH_ADCIN2 = 2U, //!< single-ended, ADCIN2 + ADC_CH_ADCIN3 = 3U, //!< single-ended, ADCIN3 + ADC_CH_ADCIN4 = 4U, //!< single-ended, ADCIN4 + ADC_CH_ADCIN5 = 5U, //!< single-ended, ADCIN5 + ADC_CH_ADCIN6 = 6U, //!< single-ended, ADCIN6 + ADC_CH_ADCIN7 = 7U, //!< single-ended, ADCIN7 + ADC_CH_ADCIN8 = 8U, //!< single-ended, ADCIN8 + ADC_CH_ADCIN9 = 9U, //!< single-ended, ADCIN9 + ADC_CH_ADCIN10 = 10U, //!< single-ended, ADCIN10 + ADC_CH_ADCIN11 = 11U, //!< single-ended, ADCIN11 + ADC_CH_ADCIN12 = 12U, //!< single-ended, ADCIN12 + ADC_CH_ADCIN13 = 13U, //!< single-ended, ADCIN13 + ADC_CH_ADCIN14 = 14U, //!< single-ended, ADCIN14 + ADC_CH_ADCIN15 = 15U, //!< single-ended, ADCIN15 + ADC_CH_ADCIN0_ADCIN1 = 0U, //!< differential, ADCIN0 and ADCIN1 + ADC_CH_ADCIN2_ADCIN3 = 2U, //!< differential, ADCIN2 and ADCIN3 + ADC_CH_ADCIN4_ADCIN5 = 4U, //!< differential, ADCIN4 and ADCIN5 + ADC_CH_ADCIN6_ADCIN7 = 6U, //!< differential, ADCIN6 and ADCIN7 + ADC_CH_ADCIN8_ADCIN9 = 8U, //!< differential, ADCIN8 and ADCIN9 + ADC_CH_ADCIN10_ADCIN11 = 10U, //!< differential, ADCIN10 and ADCIN11 + ADC_CH_ADCIN12_ADCIN13 = 12U, //!< differential, ADCIN12 and ADCIN13 + ADC_CH_ADCIN14_ADCIN15 = 14U //!< differential, ADCIN14 and ADCIN15 +} ADC_Channel; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setInterruptPulseMode() as the +//! \e pulseMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Occurs at the end of the acquisition window + ADC_PULSE_END_OF_ACQ_WIN = 0x00U, + //! Occurs at the end of the conversion + ADC_PULSE_END_OF_CONV = 0x04U +} ADC_PulseMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_enableInterrupt(), ADC_disableInterrupt(), +//! and ADC_getInterruptStatus() as the \e adcIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_NUMBER1 = 0U, //!< ADCINT1 Interrupt + ADC_INT_NUMBER2 = 1U, //!< ADCINT2 Interrupt + ADC_INT_NUMBER3 = 2U, //!< ADCINT3 Interrupt + ADC_INT_NUMBER4 = 3U //!< ADCINT4 Interrupt +} ADC_IntNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e ppbNumber parameter for several +//! functions. +// +//***************************************************************************** +typedef enum +{ + ADC_PPB_NUMBER1 = 0U, //!< Post-processing block 1 + ADC_PPB_NUMBER2 = 1U, //!< Post-processing block 2 + ADC_PPB_NUMBER3 = 2U, //!< Post-processing block 3 + ADC_PPB_NUMBER4 = 3U //!< Post-processing block 4 +} ADC_PPBNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e socNumber parameter for several +//! functions. This value identifies the start-of-conversion (SOC) that a +//! function is configuring or accessing. Note that in some cases (for example, +//! ADC_setInterruptSource()) \e socNumber is used to refer to the +//! corresponding end-of-conversion (EOC). +// +//***************************************************************************** +typedef enum +{ + ADC_SOC_NUMBER0 = 0U, //!< SOC/EOC number 0 + ADC_SOC_NUMBER1 = 1U, //!< SOC/EOC number 1 + ADC_SOC_NUMBER2 = 2U, //!< SOC/EOC number 2 + ADC_SOC_NUMBER3 = 3U, //!< SOC/EOC number 3 + ADC_SOC_NUMBER4 = 4U, //!< SOC/EOC number 4 + ADC_SOC_NUMBER5 = 5U, //!< SOC/EOC number 5 + ADC_SOC_NUMBER6 = 6U, //!< SOC/EOC number 6 + ADC_SOC_NUMBER7 = 7U, //!< SOC/EOC number 7 + ADC_SOC_NUMBER8 = 8U, //!< SOC/EOC number 8 + ADC_SOC_NUMBER9 = 9U, //!< SOC/EOC number 9 + ADC_SOC_NUMBER10 = 10U, //!< SOC/EOC number 10 + ADC_SOC_NUMBER11 = 11U, //!< SOC/EOC number 11 + ADC_SOC_NUMBER12 = 12U, //!< SOC/EOC number 12 + ADC_SOC_NUMBER13 = 13U, //!< SOC/EOC number 13 + ADC_SOC_NUMBER14 = 14U, //!< SOC/EOC number 14 + ADC_SOC_NUMBER15 = 15U //!< SOC/EOC number 15 +} ADC_SOCNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e trigger parameter for the +//! ADC_setInterruptSOCTrigger() function. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_SOC_TRIGGER_NONE = 0U, //!< No ADCINT will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT1 = 1U, //!< ADCINT1 will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT2 = 2U //!< ADCINT2 will trigger the SOC +} ADC_IntSOCTrigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setSOCPriority() as the \e priMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_PRI_ALL_ROUND_ROBIN = 0U, //!< Round robin mode is used for all + ADC_PRI_SOC0_HIPRI = 1U, //!< SOC 0 hi pri, others in round robin + ADC_PRI_THRU_SOC1_HIPRI = 2U, //!< SOC 0-1 hi pri, others in round robin + ADC_PRI_THRU_SOC2_HIPRI = 3U, //!< SOC 0-2 hi pri, others in round robin + ADC_PRI_THRU_SOC3_HIPRI = 4U, //!< SOC 0-3 hi pri, others in round robin + ADC_PRI_THRU_SOC4_HIPRI = 5U, //!< SOC 0-4 hi pri, others in round robin + ADC_PRI_THRU_SOC5_HIPRI = 6U, //!< SOC 0-5 hi pri, others in round robin + ADC_PRI_THRU_SOC6_HIPRI = 7U, //!< SOC 0-6 hi pri, others in round robin + ADC_PRI_THRU_SOC7_HIPRI = 8U, //!< SOC 0-7 hi pri, others in round robin + ADC_PRI_THRU_SOC8_HIPRI = 9U, //!< SOC 0-8 hi pri, others in round robin + ADC_PRI_THRU_SOC9_HIPRI = 10U, //!< SOC 0-9 hi pri, others in round robin + ADC_PRI_THRU_SOC10_HIPRI = 11U, //!< SOC 0-10 hi pri, others in round robin + ADC_PRI_THRU_SOC11_HIPRI = 12U, //!< SOC 0-11 hi pri, others in round robin + ADC_PRI_THRU_SOC12_HIPRI = 13U, //!< SOC 0-12 hi pri, others in round robin + ADC_PRI_THRU_SOC13_HIPRI = 14U, //!< SOC 0-13 hi pri, others in round robin + ADC_PRI_THRU_SOC14_HIPRI = 15U, //!< SOC 0-14 hi pri, SOC15 in round robin + ADC_PRI_ALL_HIPRI = 16U //!< All priorities based on SOC number +} ADC_PriorityMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_configOSDetectMode() as the \e modeVal +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_OSDETECT_MODE_DISABLED = 0x0U,//!< Open/Shorts detection cir- + //!< cuit(O/S DC) is disabled + ADC_OSDETECT_MODE_VSSA = 0x1U,//!< O/S DC is enabled at zero + //!< scale + ADC_OSDETECT_MODE_VDDA = 0x2U,//!< O/S DC is enabled at full + //!< scale + ADC_OSDETECT_MODE_5BY12_VDDA = 0x3U,//!< O/S DC is enabled at 5/12 + //!< scale + ADC_OSDETECT_MODE_7BY12_VDDA = 0x4U,//!< O/S DC is enabled at 7/12 + //!< scale + ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA = 0x5U,//!< O/S DC is enabled at 5K + //!< pulldown to VSSA + ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA = 0x6U,//!< O/S DC is enabled at 5K + //!< pullup to VDDA + ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA = 0x7U //!< O/S DC is enabled at 7K + //!< pulldown to VSSA +} ADC_OSDetectMode; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an ADC base address. +//! +//! \param base specifies the ADC module base address. +//! +//! This function determines if a ADC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +ADC_isBaseValid(uint32_t base) +{ + return( + (base == ADCA_BASE) || + (base == ADCB_BASE) || + (base == ADCC_BASE) || + (base == ADCD_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Configures the analog-to-digital converter module prescaler. +//! +//! \param base is the base address of the ADC module. +//! \param clkPrescale is the ADC clock prescaler. +//! +//! This function configures the ADC module's ADCCLK. +//! +//! The \e clkPrescale parameter specifies the value by which the input clock +//! is divided to make the ADCCLK. The clkPrescale value can be specified with +//! any of the following enum values: +//! \b ADC_CLK_DIV_1_0, \b ADC_CLK_DIV_2_0, \b ADC_CLK_DIV_2_5, ..., +//! \b ADC_CLK_DIV_7_5, \b ADC_CLK_DIV_8_0, or \b ADC_CLK_DIV_8_5. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the configuration of the ADC module prescaler. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~ADC_CTL2_PRESCALE_M) | (uint16_t)clkPrescale; + EDIS; +} + +//***************************************************************************** +// +//! Configures a start-of-conversion (SOC) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the source that will cause the SOC. +//! \param channel is the number associated with the input signal. +//! \param sampleWindow is the acquisition window duration. +//! +//! This function configures the a start-of-conversion (SOC) in the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the event that causes the SOC such as software, a +//! timer interrupt, an ePWM event, or an ADC interrupt. It should be a value +//! in the format of \b ADC_TRIGGER_XXXX where XXXX is the event such as +//! \b ADC_TRIGGER_SW_ONLY, \b ADC_TRIGGER_CPU1_TINT0, \b ADC_TRIGGER_GPIO, +//! \b ADC_TRIGGER_EPWM1_SOCA, and so on. +//! +//! The \e channel parameter specifies the channel to be converted. In +//! single-ended mode this is a single pin given by \b ADC_CH_ADCINx where x is +//! the number identifying the pin between 0 and 15 inclusive. In differential +//! mode, two pins are used as inputs and are passed in the \e channel +//! parameter as \b ADC_CH_ADCIN0_ADCIN1, \b ADC_CH_ADCIN2_ADCIN3, ..., or +//! \b ADC_CH_ADCIN14_ADCIN15. +//! +//! The \e sampleWindow parameter is the acquisition window duration in SYSCLK +//! cycles. It should be a value between 1 and 512 cycles inclusive. The +//! selected duration must be at least as long as one ADCCLK cycle. Also, the +//! datasheet will specify a minimum window duration requirement in +//! nanoseconds. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, + ADC_Channel channel, uint32_t sampleWindow) +{ + uint32_t ctlRegAddr, mask; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((sampleWindow >= 1U) && (sampleWindow <= 512U)); + + mask = (ADC_SOC0CTL_CHSEL_M | ADC_SOC0CTL_TRIGSEL_M | ADC_SOC0CTL_ACQPS_M); + + // + // Calculate address for the SOC control register. + // + ctlRegAddr = base + ADC_SOCxCTL_OFFSET_BASE + ((uint32_t)socNumber * 2U); + + // + // Set the configuration of the specified SOC. + // + EALLOW; + + HWREG(ctlRegAddr) = (HWREG(ctlRegAddr) & ~(mask)) | + ((uint32_t)channel << ADC_SOC0CTL_CHSEL_S) | + ((uint32_t)trigger << ADC_SOC0CTL_TRIGSEL_S) | + (sampleWindow - 1U); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the interrupt SOC trigger of an SOC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the interrupt source that will cause the SOC. +//! +//! This function configures the interrupt start-of-conversion trigger in +//! the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the interrupt that causes a start of conversion or +//! none. It should be one of the following values. +//! +//! - \b ADC_INT_SOC_TRIGGER_NONE +//! - \b ADC_INT_SOC_TRIGGER_ADCINT1 +//! - \b ADC_INT_SOC_TRIGGER_ADCINT2 +//! +//! This functionality is useful for creating continuous conversions. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, + ADC_IntSOCTrigger trigger) +{ + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each SOC has a 2-bit field in this register. + // + shiftVal = (uint16_t)socNumber << 1U; + + // + // Set the configuration of the specified SOC. Not that we're treating + // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here. + // + EALLOW; + HWREG(base + ADC_O_INTSOCSEL1) = (HWREG(base + ADC_O_INTSOCSEL1) & + ~((uint32_t)ADC_INTSOCSEL1_SOC0_M << + shiftVal)) | + ((uint32_t)trigger << shiftVal); + EDIS; +} + +//***************************************************************************** +// +//! Sets the timing of the end-of-conversion pulse +//! +//! \param base is the base address of the ADC module. +//! \param pulseMode is the generation mode of the EOC pulse. +//! +//! This function configures the end-of-conversion (EOC) pulse generated by ADC. +//! This pulse will be generated either at the end of the acquisition window +//!(pass \b ADC_PULSE_END_OF_ACQ_WIN into \e pulseMode) or at the end of the +//! voltage conversion, one cycle prior to the ADC result latching into it's +//! result register (pass \b ADC_PULSE_END_OF_CONV into \e pulseMode). +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the position of the pulse. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) = (HWREGH(base + ADC_O_CTL1) & + ~ADC_CTL1_INTPULSEPOS) | (uint16_t)pulseMode; + EDIS; +} + + + + +//***************************************************************************** +// +//! Powers up the analog-to-digital converter core. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers up the analog circuitry inside the analog core. +//! +//! \note Allow at least a 500us delay before sampling after calling this API. +//! If you enable multiple ADCs, you can delay after they all have begun +//! powering up. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the bit that powers up the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) |= ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Powers down the analog-to-digital converter module. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers down the analog circuitry inside the analog core. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the bit that powers down the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) &= ~ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Forces a SOC flag to a 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function forces the SOC flag associated with the SOC specified by +//! \e socNumber. This initiates a conversion once that SOC is given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to the corresponding SOC flag + // + HWREGH(base + ADC_O_SOCFRC1) = ((uint16_t)1U << (uint16_t)socNumber); +} + +//***************************************************************************** +// +//! Forces multiple SOC flags to 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socMask is the SOCs to be forced through software +//! +//! This function forces the SOCFRC1 flags associated with the SOCs specified +//! by \e socMask. This initiates a conversion once the desired SOCs are given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! Valid values for \e socMask parameter can be any of the individual +//! ADC_FORCE_SOCx values or any of their OR'd combination to trigger multiple +//! SOCs. +//! +//! \note To trigger SOC0, SOC1 and SOC2, value (ADC_FORCE_SOC0 | +//! ADC_FORCE_SOC1 | ADC_FORCE_SOC2) should be passed as socMask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceMultipleSOC(uint32_t base, uint16_t socMask) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to desired SOCs + // + HWREGH(base + ADC_O_SOCFRC1) = socMask; +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt status for the analog-to-digital +//! converter. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt status for the given interrupt number of the ADC module. +//! +//! \return \b true if the interrupt flag for the specified interrupt number is +//! set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTFLG) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt sources so that they no +//! longer assert. If not in continuous mode, this function must be called +//! before any further interrupt pulses may occur. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt. + // + HWREGH(base + ADC_O_INTFLGCLR) = (uint16_t)1U << (uint16_t)adcIntNum; + +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt overflow status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt overflow status for the +//! analog-to-digital converter. An overflow condition is generated +//! irrespective of the continuous mode. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt overflow status for the given interrupt number. +//! +//! \return \b true if the interrupt overflow flag for the specified interrupt +//! number is set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTOVF) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt overflow sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt overflow sources so that +//! they no longer assert. If software tries to clear the overflow in the same +//! cycle that hardware tries to set the overflow, then hardware has priority. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupt overflow status of the ADC module +//! should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt overflow bit. + // + HWREGH(base + ADC_O_INTOVFCLR) = (uint16_t)1U << (uint16_t)adcIntNum; +} + +//***************************************************************************** +// +//! Reads the conversion result. +//! +//! \param resultBase is the base address of the ADC results. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function returns the conversion result that corresponds to the base +//! address passed into \e resultBase and the SOC passed into \e socNumber. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC's result is to be read. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the conversion result. +// +//***************************************************************************** +static inline uint16_t +ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the ADC result for the selected SOC. + // + return(HWREGH(resultBase + (uint32_t)ADC_RESULTx_OFFSET_BASE + + (uint32_t)socNumber)); +} + +//***************************************************************************** +// +//! Determines whether the ADC is busy or not. +//! +//! \param base is the base address of the ADC. +//! +//! This function allows the caller to determine whether or not the ADC is +//! busy and can sample another channel. +//! +//! \return Returns \b true if the ADC is sampling or \b false if all +//! samples are complete. +// +//***************************************************************************** +static inline bool +ADC_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Determine if the ADC is busy. + // + return((HWREGH(base + ADC_O_CTL1) & ADC_CTL1_ADCBSY) != 0U); +} + +//***************************************************************************** +// +//! Set SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! \param trigger the source that will cause the burst conversion sequence. +//! \param burstSize is the number of SOCs converted during a burst sequence. +//! +//! This function configures the burst trigger and burstSize of an ADC module. +//! Burst mode allows a single trigger to walk through the round-robin SOCs one +//! or more at a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Instead, the source specified through the \e trigger parameter will +//! cause a burst of \e burstSize conversions to occur. +//! +//! The \e trigger parameter takes the same values as the ADC_setupSOC() API +//! The \e burstSize parameter should be a value between 1 and 16 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(((uint16_t)trigger & ~((uint16_t)0x1FU)) == 0U); + ASSERT((burstSize >= 1U) && (burstSize <= 16U)); + + // + // Write the burst mode configuration to the register. + // + EALLOW; + + regValue = (uint16_t)trigger | ((burstSize - 1U) << + ADC_BURSTCTL_BURSTSIZE_S); + + HWREGH(base + ADC_O_BURSTCTL) = (HWREGH(base + ADC_O_BURSTCTL) & + ~((uint16_t)ADC_BURSTCTL_BURSTTRIGSEL_M | + ADC_BURSTCTL_BURSTSIZE_M)) | regValue; + + EDIS; +} + +//***************************************************************************** +// +//! Enables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function enables SOC burst mode operation of the ADC. Burst mode +//! allows a single trigger to walk through the round-robin SOCs one or more at +//! a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Use ADC_setBurstMode() to configure the burst trigger and size. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Enable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) |= ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function disables SOC burst mode operation of the ADC. SOCs in +//! round-robin mode will be triggered by the trigger configured using the +//! ADC_setupSOC() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Disable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) &= ~ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Sets the priority mode of the SOCs. +//! +//! \param base is the base address of the ADC. +//! \param priMode is the priority mode of the SOCs. +//! +//! This function sets the priority mode of the SOCs. There are three main +//! modes that can be passed in the \e priMode parameter +//! +//! - All SOCs are in round-robin mode. This means no SOC has an inherent +//! higher priority over another. This is selected by passing in the value +//! \b ADC_PRI_ALL_ROUND_ROBIN. +//! - All priorities are in high priority mode. This means that the priority of +//! the SOC is determined by its SOC number. This option is selected by passing +//! in the value \b ADC_PRI_ALL_HIPRI. +//! - A range of SOCs are assigned high priority, with all others in round +//! robin mode. High priority mode means that an SOC with high priority will +//! interrupt the round robin wheel and insert itself as the next conversion. +//! Passing in the value \b ADC_PRI_SOC0_HIPRI will make SOC0 highest priority, +//! \b ADC_PRI_THRU_SOC1_HIPRI will put SOC0 and SOC 1 in high priority, and so +//! on up to \b ADC_PRI_THRU_SOC14_HIPRI where SOCs 0 through 14 are in high +//! priority. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + EALLOW; + + HWREGH(base + ADC_O_SOCPRICTL) = (HWREGH(base + ADC_O_SOCPRICTL) & + ~ADC_SOCPRICTL_SOCPRIORITY_M) | + (uint16_t)priMode; + + EDIS; +} + +//***************************************************************************** +// +//! Configures Open/Shorts Detection Circuit Mode. +//! +//! \param base is the base address of the ADC. +//! \param modeVal is the desired open/shorts detection circuit mode. +//! +//! This function configures the open/shorts detection circuit mode of the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal) +{ + // + // Configure open/shorts detection circuit mode. + // + EALLOW; + HWREGH(base + ADC_O_OSDETECT) = ((HWREGH(base + ADC_O_OSDETECT) & + (~ADC_OSDETECT_DETECTCFG_M)) | + (uint16_t)modeVal); + EDIS; +} + +//***************************************************************************** +// +//! Configures a post-processing block (PPB) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function associates a post-processing block with a SOC. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. The \e socNumber +//! number is a value \b ADC_SOC_NUMBERX where X is a number from 0 to 15 +//! specifying which SOC is to be configured on the ADC module specified by +//! \e base. +//! +//! \note You can have more that one PPB associated with the same SOC, but a +//! PPB can only be configured to correspond to one SOC at a time. Also note +//! that when you have multiple PPBs for the same SOC, the calibration offset +//! that actually gets applied will be that of the PPB with the highest number. +//! Since SOC0 is the default for all PPBs, look out for unintentional +//! overwriting of a lower numbered PPB's offset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Write the configuration to the register. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1CONFIG_CONFIG_M) | + ((uint16_t)socNumber & ADC_PPB1CONFIG_CONFIG_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function enables the indicated ADC PPB event sources. This will allow +//! the specified events to propagate through the X-BAR to a pin or to an ePWM +//! module. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Enable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) |= evtFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function disables the indicated ADC PPB event sources. This will stop +//! the specified events from propagating through the X-BAR to other modules. +//! The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Disable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) &= ~(evtFlags << ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Enable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) |= intFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt source to be disabled. +//! +//! This function disables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Disable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) &= ~(intFlags << + ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Gets the current ADC event status. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the event status for the analog-to-digital converter. +//! +//! \return Returns the current event status, enumerated as a bit field of +//! \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, and \b ADC_EVT_ZERO. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the event status for the specified post-processing block. + // + return((HWREGH(base + ADC_O_EVTSTAT) >> ((uint16_t)ppbNumber * 4U)) & + 0x7U); +} + +//***************************************************************************** +// +//! Clears ADC event flags. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event source to be cleared. +//! +//! This function clears the indicated ADC PPB event flags. After an event +//! occurs this function must be called to allow additional events to be +//! produced. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Clear the specified event interrupts. + // + HWREGH(base + ADC_O_EVTCLR) |= evtFlags << ((uint16_t)ppbNumber * 4U); +} + + +//***************************************************************************** +// +//! Reads the processed conversion result from the PPB. +//! +//! \param resultBase is the base address of the ADC results. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the processed conversion result that corresponds to +//! the base address passed into \e resultBase and the PPB passed into +//! \e ppbNumber. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the signed 32-bit conversion result. +// +//***************************************************************************** +static inline int32_t +ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the result of selected PPB. + // + return((int32_t)HWREG(resultBase + (uint32_t)ADC_PPBxRESULT_OFFSET_BASE + + ((uint32_t)ppbNumber * 2UL))); +} + +//***************************************************************************** +// +//! Reads sample delay time stamp from a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the sample delay time stamp. This delay is the number +//! of system clock cycles between the SOC being triggered and when it began +//! converting. +//! +//! \return Returns the delay time stamp. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate delay. + // + ppbOffset = (ADC_PPBxSTAMP_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1STAMP; + + // + // Return the delay time stamp. + // + return(HWREGH(base + ppbOffset) & ADC_PPB2STAMP_DLYSTAMP_M); +} + +//***************************************************************************** +// +//! Sets the post processing block offset correction. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 10-bit signed value subtracted from ADC the output. +//! +//! This function sets the PPB offset correction value. This value can be used +//! to digitally remove any system-level offset inherent in the ADCIN circuit +//! before it is stored in the appropriate result register. The \e offset +//! parameter is \b subtracted from the ADC output and is a signed value from +//! -512 to 511 inclusive. For example, when \e offset = 1, ADCRESULT = ADC +//! output - 1. When \e offset = -512, ADCRESULT = ADC output - (-512) or ADC +//! output + 512. +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation, allowing the raw ADC result to be passed unchanged into the +//! result register. +//! +//! \note If multiple PPBs are applied to the same SOC, the offset that will be +//! applied will be that of the PPB with the highest number. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, + int16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFCAL_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFCAL; + + // + // Write the offset amount. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1OFFCAL_OFFCAL_M) | + ((uint16_t)offset & ADC_PPB1OFFCAL_OFFCAL_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the post processing block reference offset. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 16-bit unsigned value subtracted from ADC the output. +//! +//! This function sets the PPB reference offset value. This can be used to +//! either calculate the feedback error or convert a unipolar signal to bipolar +//! by subtracting a reference value. The result will be stored in the +//! appropriate PPB result register which can be read using ADC_readPPBResult(). +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation and will pass the ADC result to the PPB result register +//! unchanged. +//! +//! \note If in 12-bit mode, you may only pass a 12-bit value into the \e offset +//! parameter. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFREF_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFREF; + + // + // Write the offset amount. + // + HWREGH(base + ppbOffset) = offset; +} + +//***************************************************************************** +// +//! Enables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function enables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When enabled, a two's complement +//! will be performed on the output of the offset subtraction before it is +//! stored in the appropriate PPB result register. In other words, the PPB +//! result will be the reference offset value minus the the ADC result value +//! (ADCPPBxRESULT = ADCSOCxOFFREF - ADCRESULTx). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Enable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) |= ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function disables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When disabled, a two's complement +//! will \b NOT be performed on the output of the offset subtraction before it +//! is stored in the appropriate PPB result register. In other words, the PPB +//! result will be the ADC result value minus the reference offset value +//! (ADCPPBxRESULT = ADCRESULTx - ADCSOCxOFFREF). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Disable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) &= ~ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Enables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables the indicated ADC interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1E << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables the indicated ADC interrupt source. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt. Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1E << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the source EOC for an analog-to-digital converter interrupt. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function sets which conversion is the source of an ADC interrupt. +//! +//! The \e intTrigger number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which EOC is to be configured on the ADC module +//! specified by \e base. Refer \b ADC_SOCNumber enum for valid values for +//! this input. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, + uint16_t intTrigger) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(intTrigger < 16U); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Set the specified ADC interrupt source. + // + EALLOW; + + HWREGH(intRegAddr) = + (HWREGH(intRegAddr) & ~(ADC_INTSEL1N2_INT1SEL_M << shiftVal)) | + ((uint16_t)intTrigger << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Enables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will be generated for the specified +//! ADC interrupt whenever an EOC pulse is generated irrespective of whether or +//! not the flag bit is set. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1CONT << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will not be generated for the +//! specified ADC interrupt until the corresponding interrupt flag for the +//! previous interrupt occurrence has been cleared using +//! ADC_clearInterruptStatus(). +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1CONT << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees C +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees C. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees C. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureC(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)((((int32_t)temp + (int32_t)0x4000 + + ((int32_t)273 * (int32_t)0x8000)) / + (int32_t)0x8000) - (int32_t)273)); +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees K +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees K. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees K. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureK(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)(((int32_t)temp + (int32_t)0x4000 + ((int32_t)273 * + (int32_t)0x8000)) / (int32_t)0x8000)); +} + + +//***************************************************************************** +// +//! Configures the analog-to-digital converter resolution and signal mode. +//! +//! \param base is the base address of the ADC module. +//! \param resolution is the resolution of the converter (12 or 16 bits). +//! \param signalMode is the input signal mode of the converter. +//! +//! This function configures the ADC module's conversion resolution and input +//! signal mode and ensures that the corresponding trims are loaded. +//! +//! The \e resolution parameter specifies the resolution of the conversion. +//! It can be 12-bit or 16-bit specified by \b ADC_RESOLUTION_12BIT +//! or \b ADC_RESOLUTION_16BIT. +//! +//! The \e signalMode parameter specifies the signal mode. In single-ended +//! mode, which is indicated by \b ADC_MODE_SINGLE_ENDED, the input voltage is +//! sampled on a single pin referenced to VREFLO. In differential mode, which +//! is indicated by \b ADC_MODE_DIFFERENTIAL, the input voltage to the +//! converter is sampled on a pair of input pins, a positive and a negative. +//! +//! \b Note: In this device, single-ended signal conversions are supported +//! only in 12-bit resolution mode and differential signal +//! conversions are supported only in 16-bit resolution mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode); + + +//***************************************************************************** +// +//! Configures the offset trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the offset trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setOffsetTrim(uint32_t base); + +//***************************************************************************** +// +//! Configures the INL trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the INL trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setINLTrim(uint32_t base); + +//***************************************************************************** +// +//! Sets the windowed trip limits for a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param tripHiLimit is the value is the digital comparator trip high limit. +//! \param tripLoLimit is the value is the digital comparator trip low limit. +//! +//! This function sets the windowed trip limits for a PPB. These values set +//! the digital comparator so that when one of the values is exceeded, either a +//! high or low trip event will occur. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. +//! +//! If using 16-bit mode, you may pass a 17-bit number into the \e tripHiLimit +//! and \e tripLoLimit parameters where the 17th bit is the sign bit (that is +//! a value from -65536 and 65535). In 12-bit mode, only bits 12:0 will be +//! compared against bits 12:0 of the PPB result. +//! +//! \note On some devices, signed trip values do not work properly. See the +//! silicon errata for details. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ADC_H diff --git a/gpio_driverlib_cpu2/device/driverlib/asysctl.c b/gpio_driverlib_cpu2/device/driverlib/asysctl.c new file mode 100644 index 0000000..4f3d202 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/asysctl.c @@ -0,0 +1,43 @@ +//########################################################################### +// +// FILE: asysctl.c +// +// TITLE: C28x Driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "asysctl.h" diff --git a/gpio_driverlib_cpu2/device/driverlib/asysctl.h b/gpio_driverlib_cpu2/device/driverlib/asysctl.h new file mode 100644 index 0000000..40e6c5c --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/asysctl.h @@ -0,0 +1,160 @@ +//########################################################################### +// +// FILE: asysctl.h +// +// TITLE: C28x driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ASYSCTL_H +#define ASYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup asysctl_api ASysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_asysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enable temperature sensor. +//! +//! This function enables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_enableTemperatureSensor(void) +{ + EALLOW; + + // + // Set the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) |= ASYSCTL_TSNSCTL_ENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable temperature sensor. +//! +//! This function disables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_disableTemperatureSensor(void) +{ + EALLOW; + + // + // Clear the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) &= ~(ASYSCTL_TSNSCTL_ENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the temperature sensor control register. +//! +//! \return None. +// +//***************************************************************************** +static inline void ASysCtl_lockTemperatureSensor(void) +{ + EALLOW; + + // + // Write a 1 to the lock bit in the LOCK register. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_LOCK) |= ASYSCTL_LOCK_TSNSCTL; + + EDIS; +} + + + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ASYSCTL_H diff --git a/gpio_driverlib_cpu2/device/driverlib/can.c b/gpio_driverlib_cpu2/device/driverlib/can.c new file mode 100644 index 0000000..5a33a50 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/can.c @@ -0,0 +1,1122 @@ +//########################################################################### +// +// FILE: can.c +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#include "can.h" + +//***************************************************************************** +// +// CAN_initModule +// +//***************************************************************************** +void +CAN_initModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + HWREGH(base + CAN_O_CTL) |= ((uint16_t)CAN_CTL_INIT | + (uint16_t)CAN_INIT_PARITY_DISABLE); + + // + // Initialize the message RAM before using it. + // + CAN_initRAM(base); + + // + // Force module to reset state + // + + HWREGH(base + CAN_O_CTL) |= CAN_CTL_SWR; + + // + // Delay for 14 cycles + // + SysCtl_delay(1U); + + // + // Enable write access to the configuration registers + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_CCE; +} + +//***************************************************************************** +// +// CAN_setBitRate +// +//***************************************************************************** +void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime) +{ + uint16_t brp; + uint16_t tPhase; + uint16_t phaseSeg2; + uint16_t tSync = 1U; + uint16_t tProp = 2U; + uint16_t tSeg1; + uint16_t tSeg2; + uint16_t sjw; + uint16_t prescaler; + uint16_t prescalerExtension; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((bitTime > 7U) && (bitTime < 26U)); + ASSERT(bitRate <= 1000000U); + + // + // Calculate bit timing values + // + brp = (uint16_t)(clockFreq / (bitRate * bitTime)); + tPhase = bitTime - (tSync + tProp); + if((tPhase / 2U) <= 8U) + { + phaseSeg2 = tPhase / 2U; + } + else + { + phaseSeg2 = 8U; + } + tSeg1 = ((tPhase - phaseSeg2) + tProp) - 1U; + tSeg2 = phaseSeg2 - 1U; + if(phaseSeg2 > 4U) + { + sjw = 3U; + } + else + { + sjw = tSeg2; + } + prescalerExtension = ((brp - 1U) / 64U); + prescaler = ((brp - 1U) % 64U); + + // + // Set the calculated timing parameters + // + CAN_setBitTiming(base, prescaler, prescalerExtension, tSeg1, tSeg2, sjw); +} + +//***************************************************************************** +// +// CAN_setBitTiming +// +//***************************************************************************** +void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw) +{ + uint16_t savedInit; + uint32_t bitReg; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT(prescaler < 64U); + ASSERT((tSeg1 > 0U) && (tSeg1 < 16U)); + ASSERT(tSeg2 < 8U); + ASSERT(sjw < 4U); + ASSERT(prescalerExtension < 16U); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. + // State of the init bit should be saved so it can be restored at the end. + // + savedInit = HWREGH(base + CAN_O_CTL); + HWREGH(base + CAN_O_CTL) = savedInit | CAN_CTL_INIT | CAN_CTL_CCE; + + // + // Set the bit fields of the bit timing register + // + bitReg = (uint32_t)((uint32_t)prescaler & CAN_BTR_BRP_M); + bitReg |= (uint32_t)(((uint32_t)sjw << CAN_BTR_SJW_S) & CAN_BTR_SJW_M); + bitReg |= (uint32_t)(((uint32_t)tSeg1 << CAN_BTR_TSEG1_S) & + CAN_BTR_TSEG1_M); + bitReg |= (uint32_t)(((uint32_t)tSeg2 << CAN_BTR_TSEG2_S) & + CAN_BTR_TSEG2_M); + bitReg |= (uint32_t)(((uint32_t)prescalerExtension << CAN_BTR_BRPE_S) & + CAN_BTR_BRPE_M); + + HWREG_BP(base + CAN_O_BTR) = bitReg; + + // + // Clear the config change bit, and restore the init bit. + // + savedInit &= ~((uint16_t)CAN_CTL_CCE); + + HWREGH(base + CAN_O_CTL) = savedInit; +} + + +//***************************************************************************** +// +// CAN_clearInterruptStatus +// +//***************************************************************************** +void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intClr == CAN_INT_INT0ID_STATUS) || + ((intClr >= 1U) && (intClr <= 32U))); + + if(intClr == (uint32_t)CAN_INT_INT0ID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + HWREGH(base + CAN_O_ES); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMD_CLRINTPND bit. + // + // Send the clear pending interrupt command to the CAN controller. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CLRINTPND | + (intClr & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + } +} + +//***************************************************************************** +// +// CAN_setupMessageObject +// +//***************************************************************************** +void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen) +{ + uint32_t cmdMaskReg = 0U; + uint32_t maskReg = 0U; + uint32_t arbReg = 0U; + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + switch(msgType) + { + // + // Transmit message object. + // + case CAN_MSG_OBJ_TYPE_TX: + { + // + // Set message direction to transmit. + // + arbReg = CAN_IF1ARB_DIR; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case CAN_MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Set message direction to Tx for remote receivers. + // + arbReg = CAN_IF1ARB_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + msgCtrl = (uint32_t)((uint32_t)CAN_IF1MCTL_RMTEN | + (uint32_t)CAN_IF1MCTL_UMASK); + + break; + } + + // + // Transmit remote request message object (CAN_MSG_OBJ_TYPE_TX_REMOTE) + // or Receive message object (CAN_MSG_OBJ_TYPE_RX). + // + default: + { + // + // Set message direction to read. + // + arbReg = 0U; + + break; + } + } + + // + // Set values based on Extended Frame or Standard Frame + // + if(frame == CAN_MSG_FRAME_EXT) + { + // + // Configure the Mask Registers for 29 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = msgIDMask & CAN_IF1MSK_MSK_M; + } + + // + // Set the 29 bit version of the Identifier for this message + // object. Mark the message as valid and set the extended ID bit. + // + arbReg |= (msgID & CAN_IF1ARB_ID_M) | CAN_IF1ARB_MSGVAL | + CAN_IF1ARB_XTD; + } + else + { + // + // Configure the Mask Registers for 11 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = ((msgIDMask << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M); + } + + // + // Set the 11 bit version of the Identifier for this message + // object. The lower 18 bits are set to zero. Mark the message as + // valid. + // + arbReg |= ((msgID << CAN_IF1ARB_STD_ID_S) & CAN_IF1ARB_STD_ID_M) | + CAN_IF1ARB_MSGVAL; + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_EXT_FILTER); + + // + // The caller wants to filter on the message direction field. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_DIR_FILTER); + + // + // If any filtering is requested, set the UMASK bit to use mask register + // + if(((flags & CAN_MSG_OBJ_USE_ID_FILTER) | + (flags & CAN_MSG_OBJ_USE_DIR_FILTER) | + (flags & CAN_MSG_OBJ_USE_EXT_FILTER)) != 0U) + { + msgCtrl |= CAN_IF1MCTL_UMASK; + } + + // + // Set the data length for the transfers. This is applicable only for + // Tx mailboxes. For Rx mailboxes, dlc is updated on receving a frame. + // + if((msgType == CAN_MSG_OBJ_TYPE_TX) || + (msgType == CAN_MSG_OBJ_TYPE_RXTX_REMOTE)) + { + msgCtrl |= ((uint32_t)msgLen & CAN_IF1MCTL_DLC_M); + } + + // + // If this is a single transfer or the last mailbox of a FIFO, set EOB bit. + // If this is not the last entry in a FIFO, leave the EOB bit as 0. + // + if((flags & CAN_MSG_OBJ_FIFO) == 0U) + { + msgCtrl |= CAN_IF1MCTL_EOB; + } + + // + // Enable transmit interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_TX_INT_ENABLE); + + // + // Enable receive interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_RX_INT_ENABLE); + + // + // Set the Control, Arb, and Mask bit so that they get transferred to the + // Message object. + // + cmdMaskReg |= CAN_IF1CMD_ARB; + cmdMaskReg |= CAN_IF1CMD_CONTROL; + cmdMaskReg |= CAN_IF1CMD_MASK; + cmdMaskReg |= CAN_IF1CMD_DIR; + + // + // Write out the registers to program the message object. + // + HWREG_BP(base + CAN_O_IF1MSK) = maskReg; + HWREG_BP(base + CAN_O_IF1ARB) = arbReg; + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M); +} + +//***************************************************************************** +// +// CAN_sendMessage +// +//***************************************************************************** +void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_16bit +// +//***************************************************************************** +void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_16bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_32bit +// +//***************************************************************************** +void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_32bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_updateDLC +// +//***************************************************************************** +void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Update to the new data length + // + msgCtrl &= ~CAN_IF1MCTL_DLC_M; + msgCtrl |= (msgLen & CAN_IF1MCTL_DLC_M); + + // + // Write out to the register to program the message object + // + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + (CAN_IF1CMD_CONTROL | CAN_IF1CMD_DIR | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendRemoteRequestMessage +// +//***************************************************************************** +void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check configured DLC size with 0 as this is a remote frame + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == 0U); + + // + // Set Direction to write + // + // Set Tx Request Bit for this remote frame + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_readMessage +// +//***************************************************************************** +bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData) +{ + bool status; + uint16_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID != 0U)); + + // + // Set the Message Data A, Data B, and control values to be read + // on request for data from the message object. + // + // Transfer the message object to the message object IF register. + // + HWREG_BP(base + CAN_O_IF2CMD) = + ((uint32_t)CAN_IF2CMD_DATA_A | (uint32_t)CAN_IF2CMD_DATA_B | + (uint32_t)CAN_IF2CMD_CONTROL | (objID & CAN_IF2CMD_MSG_NUM_M) | + (uint32_t)CAN_IF2CMD_ARB); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == CAN_IF2CMD_BUSY) + { + } + + // + // Read out the IF control Register. + // + msgCtrl = HWREGH(base + CAN_O_IF2MCTL); + + // + // See if there is new data available. + // + if((msgCtrl & CAN_IF2MCTL_NEWDAT) == CAN_IF2MCTL_NEWDAT) + { + // + // Read out the data from the CAN registers. + // + CAN_readDataReg(msgData, (base + CAN_O_IF2DATA), + ((uint32_t)msgCtrl & CAN_IF2MCTL_DLC_M)); + + status = true; + + // + // Now clear out the new data flag + // + HWREG_BP(base + CAN_O_IF2CMD) = ((uint32_t)CAN_IF2CMD_TXRQST | + (objID & CAN_IF2CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == + CAN_IF2CMD_BUSY) + { + } + } + else + { + status = false; + } + + return(status); +} + +//***************************************************************************** +// +// CAN_readMessageWithID +// +//***************************************************************************** +bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData) +{ + bool status; + + // + // Check the pointers. + // + ASSERT(msgID != 0U); + ASSERT(frameType != 0U); + + // + //Read the message first this fills the IF2 registers + //with received message for that mailbox + // + status = CAN_readMessage(base, objID, msgData); + // + // See if there is new data available. + // + if(status) + { + if((HWREG_BP(base + CAN_O_IF2ARB) & CAN_IF2ARB_XTD) != 0U) + { + *frameType = CAN_MSG_FRAME_EXT; + *msgID = ((HWREG_BP(base + CAN_O_IF2ARB)) & CAN_IF2ARB_ID_M); + } + else + { + *frameType = CAN_MSG_FRAME_STD; + *msgID = (((HWREG_BP(base + CAN_O_IF2ARB)) & + CAN_IF2ARB_STD_ID_M) >> + CAN_IF2ARB_STD_ID_S); + } + } + + return(status); +} + +//***************************************************************************** +// +// CAN_transferMessage +// +//***************************************************************************** +void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction) +{ + uint32_t cmdMaskReg; + + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + ASSERT((interface == 1U) || (interface == 2U)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + cmdMaskReg = + ((uint32_t)CAN_IF1CMD_DATA_A | (uint32_t)CAN_IF1CMD_DATA_B | + (uint32_t)CAN_IF1CMD_TXRQST | (uint32_t)CAN_IF1CMD_CONTROL | + (uint32_t)CAN_IF1CMD_MASK | (uint32_t)CAN_IF1CMD_ARB) | + (direction ? CAN_IF1CMD_DIR : 0U); + + // + // Ensure this IF isn't busy + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set up the request for data from the message object. Transfer the + // message object to the message object specified by objID. + // + HWREG_BP(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) = + (cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } +} + +//***************************************************************************** +// +// CAN_clearMessage +// +//***************************************************************************** +void +CAN_clearMessage(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableMessageObject +// +//***************************************************************************** +void +CAN_disableMessageObject(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableAllMessageObjects +// +//***************************************************************************** +void +CAN_disableAllMessageObjects(uint32_t base) +{ + uint32_t objID; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Loop to disable all valid message objects + // + for(objID = 0x01UL; objID <= 0x20UL; objID++) + { + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); + } +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/can.h b/gpio_driverlib_cpu2/device/driverlib/can.h new file mode 100644 index 0000000..247d1df --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/can.h @@ -0,0 +1,1924 @@ +//########################################################################### +// +// FILE: can.h +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef CAN_H +#define CAN_H + + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup can_api CAN +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_can.h" +#include "debug.h" +#include "sysctl.h" + +// +// The key value for RAM initialization +// +#define CAN_RAM_INIT_KEY (0xAU) + +// +// RAM Initialization Register Mask +// +#define CAN_RAM_INIT_MASK (0x003FU) + +// +// The Parity disable key value +// +#define CAN_INIT_PARITY_DISABLE (0x1400U) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** +//***************************************************************************** +// +// These are the flags used by the flags parameter when calling +// the CAN_setupMessageObject() function. +// +//***************************************************************************** + +//! This indicates that transmit interrupts should be enabled, or are enabled. +#define CAN_MSG_OBJ_TX_INT_ENABLE CAN_IF1MCTL_TXIE + +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +#define CAN_MSG_OBJ_RX_INT_ENABLE CAN_IF1MCTL_RXIE + +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +#define CAN_MSG_OBJ_USE_ID_FILTER (0x00000001U) + +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. +#define CAN_MSG_OBJ_USE_DIR_FILTER CAN_IF1MSK_MDIR + +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. +#define CAN_MSG_OBJ_USE_EXT_FILTER CAN_IF1MSK_MXTD + +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +#define CAN_MSG_OBJ_FIFO (0x00000002U) + +//! This indicates that a message object has no flags set. +#define CAN_MSG_OBJ_NO_FLAGS (0x00000000U) + +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to +// CAN_enableInterrupt() and CAN_disableInterrupt(). +// +//***************************************************************************** +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +#define CAN_INT_ERROR (0x00000008UL) + +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +#define CAN_INT_STATUS (0x00000004UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 0 +#define CAN_INT_IE0 (0x00000002UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 1 +#define CAN_INT_IE1 (0x00020000UL) + +//***************************************************************************** +// +// The following definitions contain all error or status indicators that can +// be returned when calling the CAN_getStatus() function. +// +//***************************************************************************** + +//! CAN controller has detected a parity error. +#define CAN_STATUS_PERR (0x00000100U) + +//! CAN controller has entered a Bus Off state. +#define CAN_STATUS_BUS_OFF (0x00000080U) + +//! CAN controller error level has reached warning level. +#define CAN_STATUS_EWARN (0x00000040U) + +//! CAN controller error level has reached error passive level. +#define CAN_STATUS_EPASS (0x00000020U) + +//! A message was received successfully since the last read of this status. +#define CAN_STATUS_RXOK (0x00000010U) + +//! A message was transmitted successfully since the last read of this +//! status. +#define CAN_STATUS_TXOK (0x00000008U) + +//! This is the mask for the last error code field. +#define CAN_STATUS_LEC_MSK (0x00000007U) + +//! There was no error. +#define CAN_STATUS_LEC_NONE (0x00000000U) + +//! A bit stuffing error has occurred. +#define CAN_STATUS_LEC_STUFF (0x00000001U) + +//! A formatting error has occurred. +#define CAN_STATUS_LEC_FORM (0x00000002U) + +//! An acknowledge error has occurred. +#define CAN_STATUS_LEC_ACK (0x00000003U) + +//! The bus remained a bit level of 1 for longer than is allowed. +#define CAN_STATUS_LEC_BIT1 (0x00000004U) + +//! The bus remained a bit level of 0 for longer than is allowed. +#define CAN_STATUS_LEC_BIT0 (0x00000005U) + +//! A CRC error has occurred. +#define CAN_STATUS_LEC_CRC (0x00000006U) + +//***************************************************************************** +// +// The following macros are added for the Global Interrupt EN/FLG/CLR +// register +// +//***************************************************************************** +//! CANINT0 global interrupt bit +#define CAN_GLOBAL_INT_CANINT0 (0x00000001U) + +//! CANINT1 global interrupt bit +#define CAN_GLOBAL_INT_CANINT1 (0x00000002U) + +//***************************************************************************** +// +// The following macros are added for accessing the interrupt register and +// the standard arbitration ID in the interface registers. +// +//***************************************************************************** +//! Status of INT0ID +#define CAN_INT_INT0ID_STATUS (0x8000U) + +//! IF1 Arbitration Standard ID Shift Offset +#define CAN_IF1ARB_STD_ID_S (18U) + +//! IF1 Arbitration Standard ID Mask +#define CAN_IF1ARB_STD_ID_M (0x1FFC0000U) + +//! IF2 Arbitration Standard ID Shift Offset +#define CAN_IF2ARB_STD_ID_S (18U) + +//! IF2 Arbitration Standard ID Mask +#define CAN_IF2ARB_STD_ID_M (0x1FFC0000U) + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! This data type is used to decide between STD_ID or EXT_ID for a mailbox. +//! This is used when calling the CAN_setupMessageObject() function. +// +//***************************************************************************** +typedef enum +{ + //! Set the message ID frame to standard. + CAN_MSG_FRAME_STD, + + //! Set the message ID frame to extended. + CAN_MSG_FRAME_EXT +} CAN_MsgFrameType; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CAN_setupMessageObject() API. +// +//***************************************************************************** +typedef enum +{ + //! Transmit message object. + CAN_MSG_OBJ_TYPE_TX, + + //! Transmit remote request message object + CAN_MSG_OBJ_TYPE_TX_REMOTE, + + //! Receive message object. + CAN_MSG_OBJ_TYPE_RX, + + //! Remote frame receive remote, with auto-transmit message object. + CAN_MSG_OBJ_TYPE_RXTX_REMOTE +} CAN_MsgObjType; + +//***************************************************************************** +// +//! This definition is used to determine the clock source that will +//! be set up via a call to the CAN_selectClockSource() API. +// +//***************************************************************************** +typedef enum +{ + //! Peripheral System Clock Source + CAN_CLOCK_SOURCE_SYS = 0x0, + + //! External Oscillator Clock Source + CAN_CLOCK_SOURCE_XTAL = 0x1, + + //! Auxiliary Clock Input Source + CAN_CLOCK_SOURCE_AUX = 0x2 +} CAN_ClockSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! +//! Checks a CAN base address. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CAN_isBaseValid(uint32_t base) +{ + return( + (base == CANA_BASE) || + (base == CANB_BASE) + ); +} +#endif + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_writeDataReg(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = data[idx]; + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 16bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_16bit(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = (uint32_t)((data[idx / 2UL]) >> ((idx % 2UL) * 8UL)); + + dataReg++; + } +} + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 32bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_32bit(const uint32_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = ((data[idx / 4UL]) >> ((idx % 4UL) * 8UL)); + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from the CAN Data registers to a buffer. +//! +//! \param data is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_readDataReg(uint16_t *data, const uint32_t address, uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Read out the data + // + data[idx] = HWREGB(dataReg); + + dataReg++; + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller's RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Performs the initialization of the RAM used for the CAN message objects. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_initRAM(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + HWREGH(base + CAN_O_RAM_INIT) = CAN_RAM_INIT_CAN_RAM_INIT | + CAN_RAM_INIT_KEY; + + while(!((HWREGH(base + CAN_O_RAM_INIT) & CAN_RAM_INIT_MASK) == + (CAN_RAM_INIT_RAM_INIT_DONE | CAN_RAM_INIT_KEY2 | + CAN_RAM_INIT_KEY0))) + { + // + // Wait until RAM Init is complete + // + } +} + +//***************************************************************************** +// +//! Select CAN Clock Source +//! +//! \param base is the base address of the CAN controller. +//! \param source is the clock source to use for the CAN controller. +//! +//! This function selects the specified clock source for the CAN controller. +//! +//! The \e source parameter can be any one of the following: +//! - \b CAN_CLOCK_SOURCE_SYS - Peripheral System Clock +//! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator +//! - \b CAN_CLOCK_SOURCE_AUX - Auxiliary Clock Input from GPIO +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_selectClockSource(uint32_t base, CAN_ClockSource source) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Determine the CAN controller and set specified clock source + // + EALLOW; + + switch(base) + { + case CANA_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANABCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANABCLKSEL_S); + break; + + case CANB_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S); + break; + + default: + + // + // Do nothing. Not a valid mode value. + // + break; + } + + EDIS; + SYSCTL_CLKSRCCTL_DELAY; +} + +//***************************************************************************** +// +//! Starts the CAN Module's Operations +//! +//! \param base is the base address of the CAN controller. +//! +//! This function starts the CAN module's operations after initialization, +//! which includes the CAN protocol controller state machine of the CAN core +//! and the message handler state machine to begin controlling the CAN's +//! internal data flow. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_startModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear Init and CCE bits + // + HWREGH(base + CAN_O_CTL) &= ~(CAN_CTL_INIT | CAN_CTL_CCE); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param base is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller will automatically transmit any pending frames, and process any +//! received frames. The controller can be stopped by calling +//! CAN_disableController(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param base is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller will no longer automatically process data on the CAN bus. The +//! controller can be restarted by calling CAN_enableController(). The state +//! of the CAN controller and the message objects in the controller are left as +//! they were before this call was made. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Enables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param mode are the the test modes to enable. +//! +//! Enables test modes within the controller. The following valid options for +//! \e mode can be OR'ed together: +//! - \b CAN_TEST_SILENT - Silent Mode +//! - \b CAN_TEST_LBACK - Loopback Mode +//! - \b CAN_TEST_EXL - External Loopback Mode +//! +//! \note Loopback mode and external loopback mode \b can \b not be +//! enabled at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableTestMode(uint32_t base, uint16_t mode) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((mode & (CAN_TEST_LBACK | CAN_TEST_EXL)) != + (CAN_TEST_LBACK | CAN_TEST_EXL)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Enable test mode and set the bits in the test register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_TEST; + HWREGH(base + CAN_O_TEST) |= mode; +} + +//***************************************************************************** +// +//! Disables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables test modes within the controller and clears the test bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableTestMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Clear the test mode enable bit + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_TEST; +} + +//***************************************************************************** +// +//! Get the current settings for the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing. +//! +//! \return Returns the value of the bit timing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getBitTiming(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read and return BTR register + // + return(HWREG_BP(base + CAN_O_BTR)); +} + +//***************************************************************************** +// +//! Enables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables direct access to the RAM while in Test mode. +//! +//! \note Test Mode must first be enabled to use this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) |= CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Disables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables direct access to the RAM while in Test mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) &= ~CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Sets the interruption debug mode of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param enable is a flag to enable or disable the interruption debug mode. +//! +//! This function sets the interruption debug mode of the CAN controller. When +//! the \e enable parameter is \b true, CAN will be configured to interrupt any +//! transmission or reception and enter debug mode immediately after it is +//! requested. When \b false, CAN will wait for a started transmission or +//! reception to be completed before entering debug mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptionDebugMode(uint32_t base, bool enable) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + if(enable) + { + // + // Enable interrupt debug support + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_IDS; + } + else + { + // + // Disable interrupt debug support + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_IDS; + } +} + + +//***************************************************************************** +// +//! Disables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the Auto-Bus-On feature of the CAN controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Enables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the Auto-Bus-On feature of the CAN controller. Be sure to also +//! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Sets the time before a Bus-Off recovery sequence is started. +//! +//! \param base is the base address of the CAN controller. +//! \param onTime is number of clock cycles before a Bus-Off recovery sequence +//! is started. +//! +//! This function sets the number of clock cycles before a Bus-Off recovery +//! sequence is started by clearing the Init bit. +//! +//! \note To enable this functionality, use CAN_enableAutoBusOn(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setAutoBusOnTime(uint32_t base, uint32_t onTime) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set bus-off timer value + // + HWREG_BP(base + CAN_O_ABOTR) = onTime; +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt +//! line 0 +//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt +//! line 1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Enable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e intFlags parameter has the same definition as in the +//! CAN_enableInterrupt() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Disable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Get the CAN controller Interrupt Line set for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! +//! Gets which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return Returns the value of the interrupt muxing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMux(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Get the interrupt muxing for the CAN peripheral + // + return(HWREG_BP(base + CAN_O_IP_MUX21)); +} + +//***************************************************************************** +// +//! Set the CAN controller Interrupt Line for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! \param mux bit packed representation of which message objects should +//! generate an interrupt on a given interrupt line. +//! +//! Selects which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptMux(uint32_t base, uint32_t mux) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the interrupt muxing for the CAN peripheral + // + HWREG_BP(base + CAN_O_IP_MUX21) = mux; +} + +//***************************************************************************** +// +//! Enables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Disables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +CAN_isRetryEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + return((bool)((HWREGH(base + CAN_O_CTL) & CAN_CTL_DAR) != CAN_CTL_DAR)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param base is the base address of the CAN controller. +//! \param rxCount is a pointer to storage for the receive error counter. +//! \param txCount is a pointer to storage for the transmit error counter. +//! +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. +//! +//! After this call, \e rxCount will hold the current receive error count +//! and \e txCount will hold the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +static inline bool +CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount) +{ + uint32_t canError = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the current count of transmit/receive errors. + // + canError = HWREG_BP(base + CAN_O_ERRC); + + // + // Extract the error numbers from the register value. + // + *rxCount = (canError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S; + *txCount = (canError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S; + + return((bool)((canError & CAN_ERRC_RP) != 0U)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error and status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the error and status register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint16_t +CAN_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return error and status register value + // + return(HWREGH(base + CAN_O_ES)); +} + +//***************************************************************************** +// +//! Reads the CAN controller TX request register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the TX request register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getTxRequests(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return Tx requests register value + // + return(HWREG_BP(base + CAN_O_TXRQ_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller new data status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the new data status register of the CAN controller for all message +//! objects. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getNewDataFlags(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return new data register value + // + return(HWREG_BP(base + CAN_O_NDAT_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller valid message object register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the valid message object register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getValidMessageObjects(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return the valid message register value + // + return(HWREG_BP(base + CAN_O_MVAL_21)); +} + +//***************************************************************************** +// +//! Get the CAN controller interrupt cause. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function returns the value of the interrupt register that indicates +//! the cause of the interrupt. +//! +//! \return Returns the value of the interrupt register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptCause(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read interrupt identifier status + // + return(HWREG_BP(base + CAN_O_INT)); +} + +//***************************************************************************** +// +//! Get the CAN controller pending interrupt message source. +//! +//! \param base is the base address of the CAN controller. +//! +//! Returns the value of the pending interrupts register that indicates +//! which messages are the source of pending interrupts. +//! +//! \return Returns the value of the pending interrupts register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMessageSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read message object interrupt status + // + return(HWREG_BP(base + CAN_O_IPEN_21)); +} + +//***************************************************************************** +// +//! CAN Global interrupt Enable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt Enable bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt Enable bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Enable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) |= intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Disable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Disable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) &= ~intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Clear function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be cleared. +//! +//! Clear the specific CAN interrupt bit in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Clear the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_CLR) |= intFlags; +} + +//***************************************************************************** +// +//! Get the CAN Global Interrupt status. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Check if any interrupt bit is set in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return True if any of the requested interrupt bits are set. False, if +//! none of the requested bits are set. +// +//***************************************************************************** +static inline bool +CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Read and return the global interrupt flag register + // + return((bool)((HWREGH(base + CAN_O_GLB_INT_FLG) & intFlags) != 0U)); +} + +//***************************************************************************** +// +//! Initializes the CAN controller +//! +//! \param base is the base address of the CAN controller. +//! +//! This function initializes the message RAM, which also clears all the +//! message objects, and places the CAN controller in an init state. Write +//! access to the configuration registers is available as a result, allowing +//! the bit timing and message objects to be setup. +//! +//! \note To exit the initialization mode and start the CAN module, use the +//! CAN_startModule() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_initModule(uint32_t base); + +//***************************************************************************** +// +//! Sets the CAN Bit Timing based on requested Bit Rate. +//! +//! \param base is the base address of the CAN controller. +//! \param clockFreq is the CAN module clock frequency before the bit rate +//! prescaler (Hertz) +//! \param bitRate is the desired bit rate (bits/sec) +//! \param bitTime is the number of time quanta per bit required for desired +//! bit time (Tq) and must be in the range from 8 to 25 +//! +//! This function sets the CAN bit timing values for the bit rate passed in the +//! \e bitRate and \e bitTime parameters based on the \e clockFreq parameter. The +//! CAN bit clock is calculated to be an average timing value that should work +//! for most systems. If tighter timing requirements are needed, then the +//! CAN_setBitTiming() function is available for full customization of all of +//! the CAN bit timing values. +//! +//! \note Not all bit-rate and bit-time combinations are valid. +//! For combinations that would yield the correct bit-rate, +//! refer to the DCAN_CANBTR_values.xlsx file in the "docs" directory. +//! The CANBTR register values calculated by the function CAN_setBitRate +//! may not be suitable for your network parameters. If this is the case +//! and you have computed the correct values for your network, you could +//! directly write those parameters in CANBTR register using the +//! function CAN_setBitTiming. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime); + +//***************************************************************************** +// +//! Manually set the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! \param prescaler is the baud rate prescaler +//! \param prescalerExtension is the baud rate prescaler extension +//! \param tSeg1 is the time segment 1 +//! \param tSeg2 is the time segment 2 +//! \param sjw is the synchronization jump width +//! +//! This function sets the various timing parameters for the CAN bus bit +//! timing: baud rate prescaler, prescaler extension, time segment 1, +//! time segment 2, and the Synchronization Jump Width. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw); + + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param base is the base address of the CAN controller. +//! \param intClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e intClr parameter should be either a number from 1 to 32 to clear a +//! specific message object interrupt or can be the following: +//! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt. +//! +//! It is not necessary to use this function to clear an interrupt. This +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr); + +//***************************************************************************** +// +//! Setup a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to configure (1-32). +//! \param msgID is the CAN message identifier used for the 11 or 29 bit +//! identifiers +//! \param frame is the CAN ID frame type +//! \param msgType is the message object type +//! \param msgIDMask is the CAN message identifier mask used when identifier +//! filtering is enabled +//! \param flags is the various flags and settings to be set for the message +//! object +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! +//! This function sets the various values required for a message object. +//! +//! The \e frame parameter can be one of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! +//! The \e msgType parameter can be one of the following values: +//! - \b CAN_MSG_OBJ_TYPE_TX - Transmit Message +//! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE - Transmit Remote Message +//! - \b CAN_MSG_OBJ_TYPE_RX - Receive Message +//! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with +//! auto-transmit +//! +//! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags +//! are required or the parameter can be a logical OR of any of the following +//! values: +//! - \b CAN_MSG_OBJ_TX_INT_ENABLE - Enable Transmit Interrupts +//! - \b CAN_MSG_OBJ_RX_INT_ENABLE - Enable Receive Interrupts +//! - \b CAN_MSG_OBJ_USE_ID_FILTER - Use filtering based on the Message ID +//! (Standard or Extended) +//! - \b CAN_MSG_OBJ_USE_EXT_FILTER - Use Extended Identifier Bit for filtering +//! (Only among Extended IDs will be accepted) +//! - \b CAN_MSG_OBJ_USE_DIR_FILTER - Use filtering based on the direction of +//! the transfer +//! - \b CAN_MSG_OBJ_FIFO - Message object is part of a FIFO +//! structure and isn't the final message +//! object in FIFO +//! +//! If filtering is based on message identifier (for Standard or Extended IDs) +//! specified by the \e msgIDMask parameter, the value \b CAN_MSG_OBJ_USE_ID_FILTER +//! has to be logically ORed with the \e flag parameter. +//! If \b CAN_MSG_OBJ_USE_EXT_FILTER is ORed with the \e flag parameter, +//! only extended identifier frames are accepted which can further be masked +//! by using the flag above. +//! +//! \note The \b msgLen Parameter for the Receive Message Object is a "don't +//! care" but its value should be between 0-8 due to the assert. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 16 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 32 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object while dynamically updating data length +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable and can be used to dynamically update the data length +//! for every subsequent call of this function. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Remote Request Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! +//! This function is used to transmit a remote request message object. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function with CAN_MSG_OBJ_TYPE_TX_REMOTE +//! as msgType flag. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Reads the data in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param msgData is a pointer to the array to store the message data +//! +//! This function is used to read the data contents of the specified message +//! object in the CAN controller. The data returned is stored in the +//! \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! -# If the DLC of the received message is larger than the \e msgData +//! buffer provided, then it is possible for a buffer overflow to occur. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData); + +//***************************************************************************** +// +//! Reads the data and Message ID in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param frameType is a pointer to the CAN_MsgFrameType to store the message +//! type that has been received in the mailbox +//! The \e frameType parameter shall be filled as of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! This parameter is filled when return value is true for this function. +//! \param msgID is a pointer to storage for the received Message ID +//! Filled when the return value is true for this function. +//! \param msgData is a pointer to the array to store the message data +//! Filled with read Data when the return value is true for this function. +//! +//! This function is used to read the data contents and the Message ID +//! of the specified message object in the CAN controller.The Message ID returned +//! is stored in the \e msgID parameter and its type in \e frameType parameter. +//! The data returned is stored in the \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData); + + + +//***************************************************************************** +// +//! Transfers a CAN message between the IF registers and Message RAM. +//! +//! \param base is the base address of the CAN controller. +//! \param interface is the interface to use for the transfer. Valid value are +//! 1 or 2. +//! \param objID is the object number to transfer (1-32). +//! \param direction is the direction of data transfer. False is Message RAM +//! to IF, True is IF to Message RAM. +//! +//! This function transfers the contents of the interface registers to message +//! RAM or vice versa depending on the value passed to direction. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction); + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function frees(disables) the specified message object from use. Once +//! a message object has been cleared, it will no longer automatically send or +//! receive messages, or generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables specific message object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function disables the specific message object. Once the message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableMessageObject(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables all message objects +//! +//! \param base is the base address of the CAN controller. +//! +//! This function disables all message objects. Once a message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. All message objects are disabled automatically on +//! reset, however this function can be used to restart CAN operations +//! without an external reset. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableAllMessageObjects(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CAN_H diff --git a/gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib.lib b/gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib.lib new file mode 100644 index 0000000000000000000000000000000000000000..62fb82036e184869d2ec9cad6588082d84765bf4 GIT binary patch literal 698 zcma)4%}T>S5T4yuEm6diJqfAwpdOkuX`3FTP{BZ;=%x20+a`1&T1nF4%_1K45qt%o zL3{|G$Jw;2TNLWR?0oZ+nQw;F&ck#x>1l?cuZgL6ORT=S-tNePKpUrg9;FFq{%9J< z4Fp2@Z9FxUTof|Co-@=T*skd~wrM%0jd69FENj}W)zCou00N)AH+~0F7UZ>nWf?$w zhUzN5ga-&JsQpuXh8~b(v|Ifwi*8sFrBJDAJ9~6N=_932l)h7Xhy`^vuFA_Ha3H2_e{bDFj|{ryqGa!hBY literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib_coff.lib b/gpio_driverlib_cpu2/device/driverlib/ccs/Debug/driverlib_coff.lib new file mode 100644 index 0000000000000000000000000000000000000000..04638f4ef8ef77f89abeb07d7c29154772f7d6a5 GIT binary patch literal 575952 zcmeFa3t(JToj-o=olKr>lAENZ6fDzHpipS@=!=JtcaxGd!z2x*Rwk2Vngo(eoILul zV0q})x=Ib$ML-u9sV#355myDosEEb&wX5QbW%0F(Ki6GBcikob&-Xm;{oa{LDJ$cy z``^>%-p~1-?>Xmt-jDm8bCzBdOZE+3T(~;qH#EjoP%J%#LWqA9V$lx& zU*mou{*b?CUJ&9(*Zcmgf+NEBw<G;nf{)8MOgn@E&uGzKNa$C zaG$Wv--FAAeWHJ_wg~$;e}S4>G3Q_WKSba}{vKT}0$KbEuDn3JuD`d9ir{Pgef2*? z5P!J~{`~d--8><3Pv9?aUZpth-=_;_ppArWCbKI$j*4aZ~2 z*3pT0GC4Um(K!*Dm_+czDqZIC9IdJD9hxv!CsM>Dc_Oh1&CN35@}Y^r z)qpRyZ4C&ft&R!``8_ZYPj)6IlYJCtTYa=I zF}h=Dpdm3yIop;%Da0oF29?{+Y2@Qj>(b4!YCw1w% z!fAE={Yf;fI7-p;dwDX3ob~J~JDVEn!WnY831z8;m`uhyhXzJth*eV4i=^qYCK*OU zVq`3qj5o*%25wDm9UYsT2q%VPs9d{6ROVikw;M&-8M`{(oJ@?gg;98lG?v&IPc|lY zj*95UaBBz2SqDK914?#7bNh(!5aYaTGB!N4W2jHoop3xkl<4<@fs7N$#PD!D*&vI< z1ceZc_=eOtltc&N);~!`HSq<{Nsl3aAB=jM~*ry}t3L4}(VBogC#GVO!{jE_<$>N@H8Wx1oeWDLq58+@3K zJvxM97>EsbjK!0(tXg8D{U{jDqT=He3a%UFl1O%uDBMY>mXmmG^CBJ{8Ojh>e|$%5 za(KdX3Db}_in1FSfn*34gvrrld|+rCJ)0Yxa%deLpNNf8UrTJPf2XQ_*<^fDyP$`w zigqQar>l-`j8D{0?m&m{`SQgk#aCk`3xW-pT?s~?Lo#2C;Yl~f_P+Yguvfpjb~Pts zBk|7NqkST(+~jbC!M$o72Cv50L~L_nw4N%U998{1HPv(T^qC40NsmL7aAcR;!>M3( zS$3t;-Jm+dt?e-?2h{|XFEpRXE)ukJXb3Utxz zONr&u!b!}`WN+?rQnDNLkflBMp{dKh5fdesj~Zd8@{4g*bE-*4ig(1lu@mzEko6$b zNn^GrS=-#MNYj?lzC<$FluRa)si~6vF~rbwVI3l<7{yY2bT+i6chf|KbeGdmI~+sW zh>&@nO)fGzv@JgW)oGr2f$HACPiz|PA4?34VsHQ}l5OnpGCbTs6FNV?w6!G0Ct4j$^T?@(Gzaiu&!7jM8mFF(SF;$+DuojwOpl$Ma1| zkBa4{#e`@YHRK?vl-1+}LQ^A-lG5+T$Oa~!V8i59LO0Gxe0*|*YF%f2N7u$q%m6Xc z=}eVWl7NSW%GRhhICyQN#Go*nXKgGeg7QzdeJ==?BwNYe7E?WM^G=L&BKRC20zyG}?iPk<|h@gf;n;b&?9 zI;UA3@>OaXgjWYl7V6w)^@LJtTsKdS7!k$|%@C*t$cc!_3fBSY!;C#uW3SS#QW)lJ2QFk9)4C#km49H4EeSKCB%YkggWI^2%Q39RbdF-GXA zlX1YdQ3fjQ9Hf%uV~j*H>27ghKqg zg8AxD1s6EM^b|fNO2lU_eqiY5At5&6Q-cuutPjcext4s%$2oZZ)b{KKl>+4BZ`DM6 z*MuSJcWEGn0BcB-R`sLAQk*mK*Bbub@$nS)jMjaO`f-N;X1)*<{)>wgu}8ZZ`N_Ie z)97^y{(el3DJE3w5jJ>GtOj1-2+{v0MJ&*6oc~hBp8y^Q|JOCY$tupz^QQ;=mz4?e zo8$2BVc~BFcFOU^Xo(``X*VAJA;$k!;IDu`)zn%ZkA zup-H43Fzw=2(kS%MKoE<^Z#+iekQMRXs6cJe~jp4658`iE? zVJ*WuSck2@5p0SiMgB>JdGqXjwtc;A-)P%U+V)pbQ&ef>1Xm9xM&hd{dq*e7W2-}gYkHD?COEl{YgxRlEXv2tBtEiq2}5r z#j~>%Lto$c>c)8QT2(-sjh4wp+g&MLJg}MR;~;+pvxVIkA}944($p}RadWC zx2kGYTURF>#&%;*d~hPPqVMcb)%oYIJFmL3YD1_izAH8!qTQP$hTPE!!dQllC9o$I z?-y2a6h#(|Vl9+NMx(;AqMjx2ZscfSC1tC13)rjz`b-jO>g;IS($(6rIa*a+-`XWa z8hIU&YelYPkB=vYCuu1wY>LZz-VLd}qp>O4*}8dSTT`@Yb7NDZ4ocD+TbrAkB2AmS zS}~d5r@~VEwQ_*9k5Vv=sGmwIe5{FX-qK#*6sgjococlflp=bR8eykU)}Z!CdBLQH z7Gb}PC`zXiL;WJJH<1_?mYp|_9piX^s1M6OVddscj`|4sc{|A^IzeujuO|V59+Rfz z(~K-Br~KyW#s z8!1p%3YAs)WmXvFSY};T*MesxOt>>lxW6-uXMAfHo;&C<(Aiaq*I;K?6<$N(20X8d z$k%W)@s2dobF_17J6;KFtC!gaLml1ny)<06u?gPogUjlu9ueByRM*zlaXG=$TQ_$} zzU8gW5h9$?+9cm+c9X3w+}X6Hu>)e+2iv#wRlBgrFTzVWF1~HSn1tc7g>*2AFO!W2UkWa zr5vjxRq|aEsh02cksA5FFtSFzFNv&`?}o@a`Q8{=FW;LY^%TsC&aP$zdv$YoOH180 zqI7@~ZMnR$wOh=)5F-r#_DS6v4T_fe2r3&}mbyFDp*CAt4gP9tk8Oo}(ZLJq$)Xb3 z)^;qYO}|8a8@3``yKP-b%{n$L6HonBl-Wz{8?Q|X4y0?C|J3l{yq5)#8eqB1>!I;_ z$k>fDwyIC4uU2- zZapv|X0@!wvs)Fum8mMc{^Cq8FZ6x>(x7>ywSZ=$mbKt4^{P>?OXRC!lwP9fdZ-EM ztY@VIH_<~3raYNjRtwm0Eb+kXeOMDwS9OVRRQpzqhFPOWu z!};yUZ;*T5fCjnXGAbjhB1$h&_~1OZEHR0I97c5n&Vpw4ZgKjZvs$97tn3zPmt{?* z7b*JJv9Vq~kD^Ih)U#s7K7q~8v6dmJStEW=&YS>-B-z^%DGY{?xx(y46fHxlrKql+ z6X0hL>}`n@2A2Sa-JXysGN(6r3?=?1pVmdo*3Ua})#tv2Jc{{W!+M1pKJWJ7B3H0C z(Kwarn8jK$DDKN@Eg2M#Sk~V3T9Tn0D;CS_fzDw4lF+P}5RY4r)|V8=LbLlO>Prgo z7L)ZQxn#%Nj)_M@DFum!>DoxHq+B5>%cklN96NT&Y{N5+&m23nc&a{^e5&V-GIW2)d!#S;nXWz9 zaA?_7RU+@EM*=hZt+PY3v$KawE{J`3>XE>}#p^)-IHRuu{o|mY1NuXZz6|t-Kwkp- z1B|{9^ansMOVrO$o*XVYCiCNP$+u;G94`5R%#Xt*FUA_CPwpAB>+_Btn8_6fXO<)x zo?>_x!;7aVb-Bp#hLw#gdEWhmrLgJHvFUvWn-3Ky8dfezJki~da|%847twRx0#M6c z`F^G4`=yreB`x1S#eRvj-N({)a;$lJUnJ0D-EJqu?G4jMZfUyt=>FPHP;LX|wm|n$ z>+mfNhrT>@A9A4akez5;**KjaTQ=3W|3a09YZp(w3-af`y3sB9yq?hPdW*`MQlrYF ztt7YKx^VUEtFvt-dGXNfh7|YBuKQ-`em-*#bZ-na7BnuQcXL7W62zWMdEAz3y?^Ge zd$ECW&!Sgn?|tT;uO42aTxOnXmK>Wia446Vrxs7`huo{hAZA)4A`Ubudc`Q7^Pzrxmy_Fh3YP6twJ<%5!a-(yE+t zY&d@3njc(zC=v{AwF^q@oRS{|=XXUq57EDFPy-{E*=1)23+()IyS&s6E(iv<1q=Qn zVh4+ZR%d!}UlxeV&T;I53b5Jv4s7`q5j(fE`?;X?T)KyUB@egDxJx65JLuT?Wx@G& z&Pj8lVBk_a#|k_xY{v=~+-Bz%tN(~AwwXl>Q1%WXb)Xg#-U_lg*1HKWP#E<0l2u%UKUpK?f|jbL>Hz57Lk}2g^kk@k zlc5I74K0NcN;ntK3nX^XT?w&HV|3H#@W?n~3&YzO?qT?DhVNnc*9^bHa2FC_!v8wM zKW6y13UypG|048N1%_b|LJD8#ukT~?T|YQG}99@vDx(dBW(r3^1eW*MG~ z7~aP4IKzL=@VyK_3#?>t#E%&M6~h7>NQP%2!>buy%P?&?(Y6CR;4tC0Bd=k?7XcfY zJ6s+|bTYgewa@U>GyE2YuK`x!JK}u|-@@?i4F46wM;U&IVcH+5lww+8!pF4Cp8_`W zJnQl};u{PL^V3 z24EBZ9WIX}?qv8zbX|t$c833&;qNp2GQ%Zk_{MJ~!yOEd0V~-YaUH|c4By4@QHE)e zeU45S;nQ?kJOoUW5$XqKTpmX}&G0c`BilXbcMbj=!%qXN@EzG}DIAqwOV`MFqXNkl z%^K4eD?_JEIYXy)jG@!soT0A(R`oL~RsyRsjmmz~#D(VN`bE`n{Ze0Ocu>V$9xe~M z5SNGi8W}jx$&5~`R3qEjj83u{I?1f!wZeo?#UD)gTs%ykQ#urnBN~CpjoLV2!`}jI z_}hRLk0W}3O`ky6@b?27{y~?=5qp76dn9c5_W>LJ8(khp+zM>k0%5~{2jjofwaJMae+{yiRw?ud=3rzTGb<0}=J@Fth;h+V)Y z9|-TzJk&>;KJ7=qCM|?bIDhZb{qj>?+91PmL@C}TErjzWU4%WlBPZlaW-Gji@eo#Y zM}&Y)S_qqPJh~%RfNs)4*zkCCM}}w8LSY*o!lr)!bY~B*qIC}tL8gS>xnkeGT(P`i zc^l;eK2(E}gFm8B2qd*fp&eK>Zwy(6hgt`HuJ$NvVLQ!7p_vA?o_yEWde|tJJqqP8 zwQ`SgK5W#UJW3UkMWHhags$^bAauk}fzZQ#3WTOq6u9zKAy`T~qd;g%7o$LE>XR4+ zLX*sl0--}bN;PC&=BGer$~DhdHDsn#FbZU@_fz0ylb-^aFZEL(bC;h2nYZ{UkoihK z1u|1^6uP-l1DPr9i~^Y{rHlfZ&+=0s^Ld=o+$rl6l|9uKt|>!9X~4oG#c=Hy>W4G( zFpU`MV>0njuuJIyL+v+U>0U=tya&}fGMFNPhi1~$PF9t>1iKTd4=IWhj)7e)Dr}rTU|IDE)r(sRu__L2yzz+(RzazRl$BTYlg>&M>g92RhemfK4372oCgW4C z4ZrIfpkMIm&t6hEWAVphs76?0XJWE%q|19JhlcxC#pvTg@8krc&~oh{b!$-=8{a+N zH!~*X-G+vt+L+O{Tf$0^#@2Oi`FRdh!>Rqr%=X9<(b_cC zgfxNoCx#~zf34wXeT(7G^xnsa=qz1hp*2$Y*X!m_{Tvx1zrm7-$5Q;oG_Rr2+wj-X z0C*zWTY>*XtSX?KtbMN1#ow2$eYpPy<*k5JPO`Ofl1-m9J>?`jRRzcPl#^_uoa8YX z_IUiYhM(oK;m`Em$A~YRjtR8iVbVtOL^dmi{pd-^82Jfb zM-Odip1gr3uqh@~>k)4Cpq%~og8$<^ifE$d{0}jH>hcbQ|C!_Pe~t0eobz|!f8jX% zFEM_a2|{};&2V{mZKgT@e(?W$kMd%=YtFw==NWOFioef-e@RU7(;SQp=jR&c#P%ET zZ`1sG4d>&pXW{pQ|542J|623YJdg|zpZ0EzX$H6!>wxZFMad-39>!1exk5~gr!~Ks zrSkA^W&BC-KZ!NOPc=WyZ^>}}2UGYzdI44;eTpv=zuq5|3>5zU3x)W*$t+~^s`-w)m_#FsRGru432{5!zE_hPICw z{F&^&4u7lm$TjMJ!NL#Z;#jCAAs)C&F;f1L z;r*3mgarLVi1(Lf5hpp-gY%a#{-@!5pk0V>jwrrH?Z@z+@SM#44Z0>3aMm>HX?W|C z0{$=3s4qR9M*Y*s(ZD9k*3v&i$?9LAs^6$W_ugk$eAc7jvkK@GpZ3m;(Plb_CED4A za!sK%L4(>7xsq{wK>kLmYxfv*wJD;UkPN0CHPH*JqkdDg>xytwv)+nd z)s)FgWGhtYjZm(a$kwi{#uN1EwJbP_NJ;W7NK%$Pg?gnJuk`2dMM_CAUfDhlo2Qbl zX0$$ad-}A;)a{>#H7E3IJj>~kpNkU92^Ha4PCrM=Uxl?;EEV!AltO-mR>-fgq(Xj$R>-eV3i%aUA-}?s3i%aU zA-_T?^$OnZf|__}AZc1=$)miOLzWauRIgl_ zt%bM>zSC0(q=ul>@*SgE?~xX$L^I`h)NANgvyGnuMKHNWKZ&OuKk)dv(*;CZNb_f? zUw#6f$OHDaaF&8Ry#Nj(My}?>G~MT)Sv;{i7pwsbXg8Ia$v7pfQ$lpVF5rDMYIH&UN>P?R6006+bb0R!Qzs``18iPDF zM%2#uK(%u5tZ;bzAiizJEtGsdeYt^cJy~T2*{NwKt7Xk>2jglv01F3hr?oUt3_X?;gjA zMg6Tf&_`Ef*P31hX$|A6arD*3M<`Dv$U%tryvtKL&P^rIPK&j$kDg-wvsmm?{nbB^ z_aDFm7O8NcYH3E6tk%|J*{!X=%{1Pj=Ip^_v|%`@YK6uq$<+FjUVd{8gWk_~Wf!s# zYfa?+yh$tob>ESC5-8<7ZJW6LLn=d7^L;kE`Ho*6Br}eHV>o#M=aR~c)^0Mg#R5u9l{ezn_)Fgu+0jBqz&fy1s?ve)&aG00PhtYIQK>Fo+Z2 zPET=qwWR$jUoTRYN}wgsUT1DNNM)tdR)to&S>sZx3F;ka{Ohs6|jdikbp zL|_lgU%sTxs~aU1qM01ZmF>bfIf}whLlG~f9QDl;a2E~4l&P#WPgYC(F9Nw)4gc}i z(|xPetX#=G>#k_k*EzYy!0Pu3T^9hcJ{?2J$yG&av1ghN$dzNJz;%7_hYsS-40VU^ zFwM1`Oet!q=x;5omvy1&*^sIW^7vwQ-3VOeZz@!`oa&m@GWt@MTm7#B-pMMgH@3E8 zODUe*5$n_Y>z)-wJC&hFxU%0|3n65C@vJDVOuabUgpd(4JAAy|i%@n0o)wOJyuef9 z`U83iZ`mn#%ys`zbUtiUY2?PDxqpT#1Sz1X3gL6gYHj#!mTN;<&Rn~VX(gVaRMRsb zn_T`LIjvc$k8A6QPZWLfbd}fr>d0RI?LuH-d7hCat9idTYZ}ICUbObVH}6-R;miB< z`=B!Be>z)M%izsfE`w-JrnzZ`st(fLv?g()^?#wN?!_Cifk|CU>QO$_Cfqp(cg$km z4vMu|-L)JP7qX*#ypbkD-Y&#;9eRV3e>h8Jk8eFiwUGK}IrsLtWHocPWI1z&0nmb4kw!lkNg-UD@Is=B-c*q$m}(@QA(d#Z!tomnoYJN{J4X@x4Mnw1&K$=l9^ zre=n6%KCQZpm;RP<@78or-?tPJ$b&f(w@#$<@8y+&C;Y%w?w$eUyZxl48|d=J>5^T zTr#h)l94Mz>TB@pNVlgWoyMr?s*cywdA@nc_`IKZPq$EhYZ4{DMU#+YGISwGA&d+; z$wD9%IwEGZ0CKXrX*(zu+L`9~$f?vt+6hl*unCUwS{}WZbCcLdNADdyQeTo6gY8a2 zcFJ*k`L8xEsXx-Pq$QUQT*Gg0Z^CbJrVxtVyreC+xukSR9d*`n!_4#-FS6{Gyp|=F z-JGXf|78aqf94P4eQ9BwG-RFKoLf6f$E`I_TL))uZaHxM?9uc3W@p}<8sbYCLVO}E z#8YI5b+eT^%$b?MK??D3?y~N~OIi*bo}NjQ_2<5jP5PXnmIE_iI=WvU=yq+YJinH{ z=qN*Vs2=4~fo*cBRvusXMEA^Mg=VHNIe13o-+SmFL(fkx4l%q^tknnc%`CPm^s$5o zW)|bh2bW$e$X^)_!E0XfME9lE6WwjnO&x=Hr5KjBjnjFNz|i7I?jVIaB55Tz)z%+9 zvb7|4fM}zNulT+t@$RkS@KIrR-*wt6Cv_jjuRu0VU;5#;54RqAayCB_+|fGy3nU!OWNBZh4S%HX>Xo3{C7)x{ehY3jfd*OGlwp*o8H~H#5z0B-JUCMfAV1CtqmUx zbYGf(bP-fZ->+&54EVW}WNblCG#3`;H!IF3IVsKk(x8=?U;!sP{K~@fhg)j~+Q(^4nPR zUH4AU9z1%Mb~|v-%6k^)ih!Mzvzzt8Ld@iaZr|l_XZrirSVXrTUHZlx;dvkPvpu zlH5ew^si%q$iK$^Eph3z6{+a49`8n8TL%x91be!2k1U!!t$9gAzFVHz_|+qe#gi>d zPDyxN1>m}GMVYv;TO2&H=szU4vXf05-1ya&XW(mJ%MyeO4&?K#O&`>_R^q$vStM$^ zbLqfFius z)9}@8v!+aEj{Z4Ht?<>>YnqQVqSRV&sHE3}%(&$cvNxl=Hp}w*qDyVn<@F_(vYFMH zM#w~Urqr!7py(QA>I}(9d^5!@OIr7f+e=VJd9l#!^KOVOD7lh@bVO^Z)qJ2akECmz z4#ol)0a}g(WQkL(_pGG4dh{rjs7jxVfANio{lIb3h;t#_I_aemzp2txlSap-yisXf z>4uo?G;VWa;^p`jmuk|u-KD%yX`FIH%yt^@c4OjcJnT|U8b9Vz{*W|=X8(D%<;f${ z8=q{QE;)F#xaHQ3AEef&Yx7f?!ajJMc94nxztV30pPRZjD!+3ur=Z@P_v5DqOzQ~Q zE$A22tn5uLwT1Np)HC^e0dJh)y@2e&iqQw5wQrrJK4ATE!=rXhhY9DuNN$$bX;?3Q;^&s6F5 zOiy%gv@(UCbDZ$)#Kx5yr)eZFe6{6HnHnkaU%3)DOZ#1}eRFR8lJEi5Q@0*!onDUI zTA^gjJ+irYxcLC)dX`6PIY49H3`Wc512ZcPokp~o+?E4sj9b<{v!r#Jddl2a`Mij7 z^s8>no8(+#Q%T-HX!e*(ZNey95VIpxYR|gV=INZ6xNRRDw`}jcjOIK|({?1MN4z&= zq2GQlW*i4@Vfp#%*e2GGt8q&CIJ$y-99(CD@XIRlh!mC|F`jd?1Z9}Q4D`_no+x(~mv8pWw_gP4BN$*+G(2VWc6`ylyp z{Lwjsujk-v`WT=OzV1vt+?qDR^&!z&pNLs;mw!V zC+4DcnJVEN8q!NYVg_-TRN_XW%E3tFE{_3r}n(#`S?^OAEn3h z@e}2vV51f&?|95N<{))%w+l<`U}>;uK9ZTYz$Y}F-Tr1`DX94P#~*$;Xx*RY9QXl_ zR;T~JJCpBI+dMa3@!3m*7MFt{5hxZe->5a0_xMFd5~=^@;T!{LKJC*S$S z`U#LwaV&h~~7QBdLA@RZBH4w_qE#I|k*Isjsd>Obb5wvY1cQ5xGz%ydN+20QQJGy>9xT|6+`S%Ql$NH4u^;97hlcU3Hz14;2VX;u zV6n`YGB1fIdGJJ2`+;1MWL`}RCkzn@Xv#q9-o4vGdfB(LOtyU>AD_WbgUzP?PpUX*bo`f{p5 zvXDy`+6!fQqiFqoj=V_Wx8w~?7Jf`MT|jj%a~f~Ue?8ovBkpUE^un^>$vcC2sOj~= zJjxqHa86*(~+V18yT9bk)e4R8JdHUq4^dWnp=^fc@!C%Gm%Ms)4Yca&2h-k zyo3zRUC0OO`iG^YC)KCdy|$6zp>>1A*a!`CxRXSW%i zuQ2>K41b&9PGqX#f1KfC4F8hh|6te-cz*L3p2u(*!zVF}ofbFVW`?oH;nLs2a1X    F;h|iQXD`FI0;@0` zag^cDGW>Oh|Bhig!{jfuJcPf4d?$H+2yEo}XP3tjzhU_6c^=Qt8K#>@jNelju3~s2 z!`m4iWB35WcQO1J!*rK}iR%T1UuJk-fyYzL@OEI8c1Mgbd@aK_G5j%x?`N0}DEWxa zL&6`{dH4vhk?kukk0YLC_+F@I8lI;Z{u#ps__@E~S;BA?!wn2?WjM+3tqecT@Q;C& z{Eql%hOK!Xy^P`08D7J16T_D>OebC3rSpgIUQ1fS5nz+9gv;ZIafYv$@9~T>d;`OO z39Q0*#6t{!p5ZSuOlKS1t>qznM3)!c^JnDwh0EiJUo!knoc>{We#-Fg87{%EY7NgB z4A(Mz1;Yu3Z)EsG41b#8Z!r7|hUs8B6Yoh3uLD-;#oY!BZ)JFh;RM5U7Qx4KUJ*V; z=hYOjiR*yNgL_;U9&tRL>li-7@cj&bf#L5l{4Wd_mU&@f`&G;4i1QiV#PC}f9%lGP zh7T}IziB_J(@WUg#qxe&liqt>9!EUL@GUrn!|)to_;U<@o8f~Q_&u57Duz3N zm29|&gWJ2lHqa0 ze1=~EHavycP&4>6hSxFN#&9pgZ)f;sh93r2vN_@@hQGz|iwwWa@O)?l8NcNW)6Zoe z)afPsfF&*A#lS}X3tb*ZT*B~5OlS?yB@A~mJjC#RU=^1mKFIJr41b2<&ofNF(|lOV zN%*H)&ZmKm3_oyr9PvEEKVdvyz+~L;e}~~;G917J-SC{ua23O?3=aY;*&MN(;R6hR zgyD}dOuuOSgiaUXdAhzm0BmG<+U0S?F^0dvcs_}vI1K++82)>P|Bc~N{Kn4kpULpW z3}4Rh2*d9LRx&%{5X1K~{0WBX_k5q!X(U{s)A-lGMuu;?JdXG~hCh9p$MbcDf5EU7 z@_0^WxSHWG!y^p84_L|Oh`(g`A%;KC@Ru2W7Wh+wj1?w4Y)MP_YrrO5{{XCb9Pu-T zzr57r`98zHVz_9T=l4{G&ttfTVftOvr=xz4x!mP(#9J6{IGyn@d^N*= z2CTxzJxmNAW%xmc>9<3l(ee-;x1=TfD6o;|J1&nSzR&QNmwP$2>!xu4p8N)jmeh09U#}V&jn10dl7g|ojM$SJ6HZpw7<#EKl z3?Dql4kF^u#(3S=P^tg{U6kF5`MSN&o#hC&K8%)5p4{g zbFRm83By|$9%T4hhHqy02*Zy8D|sA2TI{!L*$7{#W&0ekxnJ#Bmk0M9GJNlOo@|dZ z{2Z_f(-Hr~@UI!h@>+aO#v7IAp8s6q*GsqIPqi;~Z(pV`IZrN&w*c70TLP?Pj>`MB zeg->K$mQJ=Cj25$O!!!?xqcTgI;K=E9Yc`IkFM0EzZLi+_@nS?kIjV7(@t?2*{~#X z!zpLk`pYc%HnY^O>H-0g#bLl)!FpRkLO^m;d(Yt|F-{`Lce~frlU-!q4 zSM^=liT5DO=V_MDcd&d80-N&XZH@BWlrNT9Zu#=Ib}^&ZGJf8^s7{)?F^}=^I(!nN zHvy}Da_+umuDVUKJ&eE9HvW2L2q6R`Gw(xq+vNQQg>UkT`U>Nh(rD<}_PYXcsd7C2 z9ioay-65*l+VSrYRXpkrQPoDQa1Y|5z7HnckB1qv27wiix_*XFgb6p-s z)B@kF`3W2TM#kUb@;G8U@W(ViVZ%?~hK&6EE|0n!^{D2jyHO24tyc{HK48V;h+BZ~ z)%=7FKi&Oe_-U@Kc(BI{e81)=Z1^8x{ExXjSW^Q(sQC#S{;xBB`c|cQFb4)!ZQlwL zHvBI!{(p9PaQ8485ljeuxamvmusHKUAiNF3~bssVVVoVgkNy!j(8Q=v}?lkn#V$3nYK)2 z^btw7!h~xzPlHQ$#6DotehIJBJU6&>M?4B_+ALv}UJ?GZOLs(jz-y<38+ABgm+px7 z1Dm!<*znxq(jD=)z@|MCHay>T>5e!#$7_Rxcj&lIb?J_H2e4^(gx71H>s>n11#H?H z;a1J_X_xMZSzyz?2%G$|G2t+6YAvv7Q-n=i8(g|0hJimN!?(hOSLwJCF5MBg0h_i% z*zkPFrQ@D*VAEa*U#P?Rs!R8`5n8i+Uh=4WolSe8xktYCOW3rRMZl)L5H>s>UES+! z+DnM>5LR?`ud}KrY8*G=tN@Rqt9zZzSXs%!A*|?*yp!6rmko@Eu%cs30XFT0u!+l~ zJE8@2(_RQ09*^!wod?ri!iR+5;75dBdm(J%^5_`vKsW7$u;KCOXyc%pF^jO_@#v1&54veDgbj~Jcf>)^O?x41 zcs#ngL*2BOTNw{w(_ZcbHtmJ53CE*5;t1%by%07$9vx#b=%&38Has5Pkq2^`_VO6x zA*|@Uy_mZp;V5s~qIWKC;q~qgFOd{;FF1_?WiACkETsobp6jayHd--wcZaWmjbimE zYheqy6aYcK$k08(Dt795C>-xz@b$1!>>gzUY-hO?0C{&dz3DDt70&svQ8?Z`+;rnO zg~KRSLacNt0HTi`FokY7RY-h+q?p{Og3u?s6ylzs2TYOY3yG)L)ot1GMs_5ga)VKj z)FM#kVTVKKJd#=p%6yN4q%QDNkT6=cdpvY2`Eox6>AJvAK`JitQ;-T;*|TsUbDN(6 znQ3KN?8;LOnMoc-fy|T}i~^bQ`GHd)Gwo7%Jaj8L_4|whnW^j<1u|3ql(@0iKxT@a zQ6Mwr2BSdcWqt~Rg#erfGB^4ukhubsQZFuep>%naHISL+D2xJ`SNJKA`D{N0GD9Tp z3o?^DEF3V@`YDjP!B2tAEq)4Q-r}bq*eiXMwUBw(Pl3$4{1nLiK|cjD(@5hXYSqGVW z{1nJc@|3yqtb@!X52HY4l7~?sGs(j!keTFR6v#~Sc$D>!ndD&<$lT+nAP|zL+?8iN zWF~nS1u~O7i~^ZS9!7!8BoCuNW|D_dAT!CsD3H0wN7(?GNuCNfrIbUq|Q!o(Hn0vC9 z_UbBG!#SlI`RC`Uk-s$JJZoe)i&;2pWjLI&PKLuN>t#5cvO$J(3Jd3a^boXycS{EY zAu66nY3^*JGNx9ic|fU_ZCO$H4b(RH`0d8hBOd(L>A+k(?563QId~|%>*xWKi@$)i zK;qQLt(uT0d6wZxlKIU;+Dfz6fJJpHo#$(shvr)Wi}n@Ld0x^yw2K?CPSH01%j5~o z9s(Bi1(XYZV{Un-8WXUnj|=)4V51#9GBgJYSTQ{H+?$BnnA@DG?+94^coMhYm>Zm_ z=L%TOc&5i?Zf!1=Jm1HYa?@|jP0bF-0V|0o<$~Xs+nK4J&Ba4IbY!S^n~TTX!c2W@ zzG_C}!9e7er@*8u*GPTTr)qrPu{`Bgqut@SyIO%bj zo0O@K4p``{GlXMqPnNY}4jyx3GSw~>PI~<@wBii89D-B8dKyof;rh)Ios5N8r`R$S%16Ih zt$Ao>rFf{G`Ax0np;@=$Y4$U~woUU;zp8ksJp5)@^Uy41uDEW{JjJfe)W-bg1Dc2W z)w$yOgyx|ctm2_I<~KM)KpN`9=L+X1nuk_xiic`|-@L4OXuhF%sBQR7Id!@)wEj{& zF-2g{(=`u`?~12^xhi;p=AqG3@uZh&hvuQ#sp3g5(;b?J=30t}+PvRfr+EaGg><^f zN1+|XuGXq}byNMNRqf6CcsX`iY5Mu5X%u~)W;$J+-ze$)*n3GZN7%{1@d8C+(K0eW z+EdIy*CNd2ssv%KTpUKuBovO?Yftn~4##=i?ABH0T~YPTl#HJ7EzR}9=yFESc)WJHd;0Ou ztKxl$(ea53R*g?2heii5!HV}z4n&8CMp2Lo4~_0f7#!>EO~$8OTQW8}5Fb~qfu~f~ zQwDNj$C;ZLnH+?W5va_K^KTUTTq!f1cSLN?(; z9(k>>w6jdmju+%QklJkpGHfb}91m-pQfi{#CIFlwa@U1WH2}o4VYu zux~iF3MXH$4rx=hetk`4_4>-nnoy`x()cqJT66w7xRB{7dL^VD*+=v(FhxJCcxjMPlZLO)^I?}&x3NdatbEVpVEPtfd!|WxwGzb8ULNY zQSkpPl^=97OK)WScL2}QBt6A&`6J9N1bjQvdJ;{xVa$xw@Ym52rmIz0%gC{Ad^|qV zOLrsZpH!GP&)#R-*W;8|+kVov??uk32|-RETjxWd`u35O!p>FZ%p^Y`6hSd!#SB4rA{qceLXlTpm(5}!_b@i%stEyJDb#=mFY7X@i=py+pD zm7!&bv~Jwk6p40rGcnQh{$MbjHHa#)ZJx7_Net$ zMsh~07I`W)j8-G^(`ai%K^l!>DNLm{REeTA8uqBtXfxq0$8hHbeSEiBAC-S*z0FggmkC|%qjw>QO3|1`s}fCVv})1pqqS4H)rpOMVnh;K{6ylc7p;CGan_4X zK4MctU08~LX&PBd-HRCvd|g|H{f|yM81Zb ziFc%to}-;x+wn?-@w5+yI=bb1X}E4<6TI68m({g*G&T|1+*H@r)^Rz((^2q}Z+UBT zga~J}Hp%yy-DGPEcQ$Ql?0{JI!S?PB60)l+$M?6>t0C%1EV@V|AoT zzH1`Y^1VJ%Bi|QB*2woIk+t&O5LqYR8zbxGdsC#If?3ho)r?@TZVqp0soO@B4p5>k zmp8U{i@XOg6Qo%NmgrroUUnuXlYMbHbE63}Zr;k|oUJ*XoHbTu?P5$B{N?f{wh3=u zMYFmnv)k5XSd_^|N|UXqvE<|I{_$jAXMC70a5)W4BkEb-nF~_NKQiBv>)$f zQ?qvcfyVPL?A|gv^W?G5H=b92p#FyD;tRWHo;mi_FD_X;MMrxsN06kR`g)E=qj_%81jINAXNgn(ILFz!%L(texhfpM6n`XG(6=ubjGcGvXF==iV#UyLd}Zd&oTTiR9wSD z$FUfE4#NfbenKC%P>x~3cf&tSxDeQ=FrV)7IN~gZOCXFJCc{k(#~8kr;oBHK0<2_E zs*6UR6%a&kV~1&xZRDv0HvE7(7wzyhF5Qy&baF&m_TiCCQrM%b z6}Ks|S7&jAkB}-@_5ZQ3vDq3EZS%>n=2kqqlT1o0gL*CbYr$JP;tN$ z!jnSuo0zszj;U>azubr5jxGHDZB5-9N3n%(c1JS}OaH}P&`d$S_WoS&>)M~Isyu(g zT6cdA`smo7`@wP{E|$qR`*YK(2};^Ic+%-rsm4@MUbzepol=!*LYlxUn&HXBUu*bT zr8E4Q-uoD_oXLL``YsCpCHk-llTa^NNvZOYX;m-zq;H$gl`(>bp<0jD<3XuaQc7(t z#c=*T%xx9$x!@0l6pf6Msk3-G%1b}N4gWY|8+%IhT% z@54v&F&)0{eg)s}%wzmN0>1SmA)Z{OLZk2LWK8`etbdtLP@D<=Df$qeVmLqj^23-g zz#XVNPoJ(Rh)Np6Uw1aFC$!(W12s|QR!%T$GuPh#efypB=|?u+eZ7{&zF!2sU?WpI z@DSFYfz2wwN;%rlh1HTU5W9~CV$+fKO2Lts9L0^ttj1d|tMR5~HC}RA?YPToP}s7%@LbHksj}l6?T(=VUFF*nvHteh zMBkw7#b|V)#r2#_S?#DQvv%YCF!h6%SyQ-aus1dy7t}1G64}=FKGpbf%RF@%$R61j zsC(=uu!YpG*d@Zps^kb|SCt}a4Dy(S)r?#%im`}Ji4UaRUJNM_mdUK=m;TZKVU@8S zjwY=jP!UNTjaKTnB#ItQ=QB%OXqZEc-gRZodb$#_5vRX&CX19*^dsk3D2~wDkE={EFeNTtznRvIjBT#1@bbJrhY0jWzA9!S zXSX2UJ7+eLq7McCgQFvXVPJnN#@>R znNP+-mC<0IL%D3oV%`weag<>x!!czTE$%Z7)mhD~-)1?pY<7jPSEDck+LJMx;IL~d zHaw{(T?%Gs;pxpdZ4hH~pP}(OUOQz`@bQjz7_9R1=!vau+^&Ut-YV&C;`)-}81S0< zl0tfKs4vN-_eJ$-_Y{+_OKkDDfFFC%dh}yA+cE3$!_(=vgZ(>hxD@g()Mj?$=I>qV zvZ-d=Cup;qJe$@fP}c^Aa1UKNqti-@qMlKZz}#qPyD;sc=t}}ofe6O$r-3`{!eDBt`Tb^ntB=_G8(v57zI&bK9vYb~NkC@xg zRCpsYyn31D#sf3ROA(Ma$34|}!{1WQx;EUOD)CQdX5bc@&6T#7VapuyjWT3}CvW3z zykREyi>N8c4ctpdw!ei9xvXtJfem@1Z7(nRQ@l%U7{9UmQ@u+~$=-)XjVn`I|=)Zaj zPQQ~*@-m&0a~^&4n?dUwpKp2N4tDoxPnTQ~2WR+WUcqDT zuSvfPhh4yPyt{DN1w1CK^jmu7r`&~8?E4a3qP|3zn!9iu?~`;HeUf(X!YSt;sM}Ci zXga_@3sQR~Lv5D~wNozoMGD5I!nty_&r*NJ-{aX_qsedGmBxmC&uvH!0>GhKg{qqfK^048N7(K8C6LQ2C?IFkLBSR%b51S!0N%(-oBpCx(ZXV}>UHY{Eg4k|zsc znJj-dZFp!eTge%fXH*zWZ-c467)*Q82GcII!L;vea5Ka04D)oM3vuN^Q+Qo6Q`%K~ zkIL`5ua(9X;8#4yKigFCsIyH?oos|(qlnZ3Z0boHu&Gx)z$)#>KigFCsIyJYc(E6L zP5AqOP53tgn|}3HVAFpRHvD%m{ySYBb+)PL>mFhJk1_tw0-HYS>%gY}A#B3`Hsk-U z%fpqS)LD=wZ+{3LJy!@n4{Y-Dcfck;2^*f@yL3m8=7`Bd!Yb_|Os66!I>s`WZiNYx zvK3626yi)?4Fa3IB3z?+u6F5;xEO`Z@o z;dpd)-k-^n4UC7dsVB9-CQk^Pa6CHClh;1ejruC3C`Zb4RGO4}MFB8*j-Nv9+o#m) zs5B{7?*z9suwls26aaa83BA1&+}6T|p#l`6rne3@(kJmK)Rz&DcNQC^9GyF(oDbV_ zAB9eEyTDJWLP7f}NLaU@f@F})g|0kRNCv4sF$#pH`oSm=nj~cBwLxg2xaYOGXSKLz zsJUmgC<@mZquw}^A|clk3(UpCbi**2%@_{Iu6`G_j=9c8=^;j#Jp2VL%JFowN0X@R z1J)`$DMY`yMO$e!30Sl?p}g^%N3|7`Ch$R$1QfIzU3jO8gxk&q@R-lwI%^J_++p2k}9x9&mJV%YF=Osg@7AhXqhbXFg?$SKoxfPU;enVgF zl|eY-Vc6(2hq1(P)sBWp`u8LKLCLpao$0H9Yz8=$A?4eYkL(MCxukr2U@miLdvFf# z(>bHEZ@`S|eUE&De(R6K&LN?fMe4(-w6pK1((cK_K6byRmh8yb_&C#(eXU=ypI^OZ zLr5C>6?=))lKmnMtD)Xm2%{x?rCTf1Uc*nRD@!rd5~#P3IhyL0-dIIQ^YGr!cq`4o zUu*bTPiXivz4tNVvkX6j?t#KTPd7%>-i-XjdOG8$dH!?cm|{Y;9^oPn%5!`x(d4ht zlP>B-$Z-B`iX@*j>fH(c4;+VoC*vo1N-=bOL-U)g;^BXg@wWi)0RPLHpL%^Vod01( zlFulfuh7t#Vrp3(7-RSm@I8V>4c+BNrb4}ZTCAVfGG&hP@t)4FP3Vj#Zv9GSgM^COSRKtsdic{)lQ2^?X*~_ofa##(_*Q1TCCJg zi>2CWu~a)PR%)lkQth-@tDWMl)lPx5+9{AxI|Wo~rvOsz6mO|^iZ|3w@pRQrfu-7M zu~IuN)@rB4O6{~*tDP1rwbNp)c3P~|PK&kLX|Yl}E!JwM#Y*k8SgV~DE49;Nt#(?h z)J}`F+9~3fYNvQhwNt#M+9}>r?G$gRc8a%DJH=b7o#HLkPVpwSQ@o_wX|bzz3JOy@ z&5vMG+|VBG?9>B&^UyF<7F%%Ag>2E(wL{k_Geeepl1 zgI>HKU6T??rij6|_cdY$%iELj0cZw6twV<4+Ddd$a_uTwsaPd!f<}uNAAzPBRw>P= zERla5W=QGvp$&OJX0G}|?pdxbTeJ2PU|n5y{$F*0s@dzTE?cl{=GCQ*)U!KAan?xZ z6`LDmouTQVzmG{_%5uedN46`@UDlqA{mdYG*{0DL9e%I}LuQoO(Z38Qc5+A0I!EWh ze5Zy+ordRMx_Z_V?-NRCv5hX^qu9dWWg0<$DNB+j>i&|HPFXI$d$V1BKbWKZMq;}t zeduUaH_PlOzy5e%GEPTAx$Zs+#)sYg@!{BR=B#aS+BLRwq;vOZUuUvUh0W|VvP_Q0 zb<~}M{X13lNukYAO_-2!Y+!b(CO#P@gO76Jm4%NeSX=o=6k2Fmr5ouf3ci9ximFb0 zSc04U*duFex^q_R)S!4iyLD<%ykzZ7?-McPm9U52-KtJ0zj;av!OE#A3!_uy^Egilj4_tnO08uoI1KCEh`)?MRt>&>%w%zo&} z*&|)KL!?1@fuV1oy(7?lH0S94>wXaE{%FDBXPOQzn_46_?`DpbJlXWj(f!(XZNvVP z75!RultiZZdQ7+}@x=^1V|)vJ@o5|4JINOxv=!6RccTm!`kK>uv4G-Uj6ME@#*2PG z+sIsSpqcA3`}@UHT2nDC)Q4rL8&8=%P36|drM+c35StfKluzh*>kqtm?C)of?r*ty z_Cta0Bi7+(UOd!_7<05NwU9;QMNiBwo@&?+9ZzUA&RpBLzgVM<`xj{Rr>NyPg4>eD z@o$y9KVUf;I(@->J;#gCltF3X?Hx+h-lHj~a@#fadfdD)_oRhM1Dn?Rvzrkp{pLO( zz5}X-4(yMk^(SYca#fbqzEADsct@r@PkM17DDxHCXIbfLbJcKNAAQI8qFomSt&`H- zzekF9$77f!hPC~Rf(1)A27`6#_2!IW-AAIVjdu5(5-1qZjHg_3Nzl4b#cKtHT^Puh zI&#>c2?{!;B~T)2y5Dj<}oQ_v0(8;W^6iml*yL!@p&C0hW=*?*`zI zj;od74u)yjxlHm{VZ!uN7?^N3unFgCm&XwahA%7fc!n5$H^X!WkqPIE4F8fXFdPR~aynv);Xh;eR)#;!FfGFt>ogKRLzl(fz(ytLGcJ!Ko?!S3z(%&aG5j6bx4CWy@u}QK^yu9RrxC{A^$)84-=lEA!n|`AQ{H9MJY{KscHf1;H@+kGM5bV^4?8VdY?*lgc zHv)(7M<0xC#naS(!iN72V8ef>%cDLp<-m>+CH(hznzR$vU!lS;x^!G=3#`Jl!h}Qk zg9&3gr0I@W0&LPqc&X-D>e3x?32;c#tuW!0ny22SJK`!}lNQ3~YMv37?w23kr(2(? z+)Y{t=WD+n-H{4JCM}B?4`D@DYE>pJA;v>k(Un>i*{O`E&X~9ehww+`Qi-QY3t_|K z(Ro^4TOH~QgyC0*qS!o24Qyz}Daub&>pgWSQgtF8PqB$w0r7Yg+WaLRzpB$hALV@5 z=nJjKL#j@v`zckbY#2|q3YjS_L1_9~$|!4;Jd6UNDc>0dLL+cafzXr^m&a9gQtD9r zGrtYKY%4ZVPLQGc8L)IsmlW@Dk%kz$!LtEROhQu3Hf^W6GZ)WJ&4VFS#}&{N@AW|q zG4z3_1y73AZywfG3~S(_59{gX^O{8UBVf_T@zOM=XElXV6R=2u;fge#?`aCDa|JB= zXr69YA!#c9w(*t$Qb>{?*Z9_#(daq8gHp_4-|KwdxN93ezGQGr*=5hb zA$M=zAXOsv2{9$&44)TC;tXW@S<*+B60&bsuc2JjH#RvjG!jo5^`h6(Em~Vytq$Om zH)PC{x<&V(cB>)L=oWpAmG?Qo-PD_;7-|yKU}Y|+xIs-V&4e^1lWtKa{#wKTU(hXj zhxSXax1$fB@SmdA46|IlT-_70o~dc{qKV$`sh3GHp<0hn??L&ygR{}&B&h|%m~M&l z_bDg&?8TEN_Nk`UZB#-$&m4Pz%h6jM(&1B{lPR@T{u3Ujhc<6QIOE`dMf003(3BUk zy~i-)T?l^qElR54{H9|io)!3`-3h_GG&n^o8l-qO|Dj%zZS+PAdTb+vYErgOogon0N_y5_E?$mXW4 zU5!l*k*4-0914%K>yE?UwXG@Afi0T3m?B#?H%FS9sAl9+IMh8wn?@#wV-rJ(QCv@i zlhH}||E^>2wjp2Gv3I25b7IHdO&gC&)95ba(P$cZ2h)+BlF>9efdlU5Bc%L%lvz$_ zKAv7U|98OM|KJ1eidr%6bt^aykN4Mc>Kkccj?c%Y5v1{CYv0@J^|E)yofpRi-f>IR z=eP&mjZjmk{wFGtdkBli1kyDrTsW7-WEY=7qFMM)7^4x?Dkq&-OU&DYktCxxILiTj z5&UNkINL=qDBhQ~6PHX842o%MuQ_Ybm%Hj5H;+_K3tW_lKB8ux`uJKH3(e-wQy*1J z@wQVws^+|!`bo7~e)^*if3yGEfX{t@iXZL9#H5%ILt;e4Me+~$bVn0L{poH?>gPG? z0Q6_J%gF6y!uBaQ9P+@Bz!TdoYMby z1f3;eaFpRV!#GFE<=F`#4F9_reu!Z@55n*ipqn+gnBfYBpMb!$A%Z3lCVT+#!Gxa# zHhzEP^5Ef9 zGf=g$DThaj;d>aU+L?LSz6Iq?rf?|OGwA_C`4+HDE0-kqQLhoI5_qTwpjiE;Pg^Pf z0#>izQQOA#nXOf$(;x3o$58?-%W;!X?y z#5eZ}`(u4(V=qMJHFx)FD%VR!w!3!=8pKkWhh}&0Q8!1`F9-kBcK1e^{5PO}((c|0 z)rGjHF0tN5r(SuY_7%vm`xdJ80_7X$mxEjd{*dab-8#(qBc50BR^T6J2)~xKk*67d z5AX-kjP|93&v*BDTV8~4{tf)kYkt#yd3yJ-@P7sD=$%hS_U(S|XAUa}BQMvePS;JZ z3ID`*_uc`~R4Cv7QOL%Ee}o3xZtRB~@ZZ-*v@f#p%Z5i`9{YN9mgv&fR}L;6|W5Bd!Dt{ zyZ5`#IZ5jbhxzpXR-3b*{jO(S_F8MNwf4HaOC_}B#YOOM4|W17((mwY^~6QhHe>Wi z9{a+v&3NoY#spj{5mdK#opch9=Vb3QX5C6b&BgpR6*r=lVb<#qU}L|Q?_t105hQbho9&S%pUWD za%1)+pXe~RK8-xtWA+^R?9A#T$6r4&ZQvt0(gW*DH`DjEep5kY-+J&qxO(2zDbFG2Cs#*#@);vRt=?IGf>9 zf04!*S^v2)#<2tkATxLiLj}Gs%~F2WS%ZA-iuiW<@7r)>@n*k_|I_&+i(JCLyk}cO z)7ySL=Z&dg?*A_r)3e@01qj0$*BO5O(6Gp8;}~uX(TxE)-L$NUIfi&1ij;GkHq=ck znB$3p|3P6cq82$%853NB2njx0;a4eqjly>*e7C~yRd@{|?><(7Eb&~}!DQD0OIQOT z2hXK&Ck8o$GpO*J6uwX4e^U6D3eQFF#Kj?PPE&Y=!W{}+q|LPf$NmT}C- zLwVZ#8d&@%UVuNC?CFTyMYd7Zicl~f@ZZ}wob3UnFoZ-&`pJRW>xM%<9c0KSJj(aYx zt6OXbIQ1{aMVBsJ1}hk9Ov{*0;auTwEiz_oZYx*MLd_wplew@n`r z$`vg~uBr0^JtGiu3h*0+uVx2AegSYm$^1;2m2}O<1^y48=m>{BPvXzp6<)>*y-c8%6KxG_8+kM zhH2UJPs>9=WD#tZ!@=PD*C%g3D11 zy=Uv2)~xPYEWz2kFd%yu24U}(n4}BP-YqpH>h2tq3h!DMo6_i}-junUmeoy|7IE={ z4_L*z3rcPh-)5vXqPY1;b+xs0uUp^KB+>Hs%{lfh^7P)mRU+r_+a!AazFi{d?^jA3 z{e6c-)8BWRau;oXf1#;}-LEp0vHR6#TI_y}nI5}ei>*@b*}De%$A(8t;%a8ZgVBR$ z*RSiwv$vt=?p$tI8;N}4bgpe#w|+fXJuDUYICWmOZERb&V_TTducfCyk9=-l-PN|n zx(Ks367fWBiP-kOorA+81D6f&K*o&2gR*PTK$e%_WnDFJ&0-TIPBbjRJtFWn@HTN` zLfOQz^?y3-21q3ghH;F?w$u|4Q-J-42VlvO+rUT2@F`h%Uy8P#2?(OkJpp zan>i9V2{DORNcSEV&PXvXRI#9jMc@MvAP&DRu^N&>SD}TU5pv(V$3*Qj2WkkF=KTx zW}Gg@jMc@MvAP&DP8Vaw>SD}zU5vPTU5r3p7bB49Vgz)$7y+y zMqsOpG2?VGX1p%OjMK%K@wyl@P8Vaw>tf6}U5pv8i!tM7Z8Cm^bjImo%y?al8K;Xe z<8?7+oG!+U*TsnNtu97ftu97ftu97ftu97ftu97ftu97ftu97ftu97fsf!U8tBWxc z>SBaM>0+#UHTKciw_?|hZNvRn@zt!y3u0SN_82j3!)7GMwpfFRuGKD@5=P%E7!AgF z=I?0BnpRc-_oL+Ygm-DENeplDtoCmk+HqBO7%$wwh^wl!0B-l~8{O2*1I2C4BR8T3+s{U(@w8GlXH&nxq?tYOM5v$n;} zvey-DTE!KKPybP8*^C=8$Y9^2tpj8B6>HztH#&%B)pwovy7BwQw%6{Bn}k{1Y#c9g zHh$OcLl|{E6n4sbJjR=FePQu+p(0W0Siv-^S27A0*N(c5Cp$Sk9@mDcXOq}8G;^TJUjShS0FoLyy9lY(?!mV=WJ$Ra|ip$?6z|g2r-iOI-i`j z7W0@XUVyFZDUQ|!Q5GPvY|^8`LegVw07*anb_~<%q;ELpcOjQq+~iLNMNa>h2mhD6 z4bx{}^gEU%u~Lp~vx6!5Z$m?jSKRD4x!BpU!evK+68>L*A2{w(;C)7FATDzA! zykkNa?h6)3X!~V^d6pMi4)Z|y*2AgW#-3?CYrJ&9#pYef+neV%A9CtbTVONt%y?<@ ze8+1&s~Mc+?X<0Yq51x@+v*Oq-~X~i$9$8xaDH=XX>YWWDs`KI%hve~6Rq=Whg(a{ z?f1_$2R2Sr^akK|lrEXbOeFWV&o3Je5=|F(nAXz8U|v|7?CmK1QGa=&ovKvfzA{A9 zLsS)_=F-}}X7EzC)jTskzxm)}Kr=0R5-4NQvp}+Uet7yDS3ywG%*>(7GqC4Ha0xFu0BoVsoPGvkMv4>z5)X(G72<#0=w zV^!;2F8t6wPs<^3mq;|vr@OjmTFx3jL{~?uqMUaACzStJPU?SIZ{5VH0dtyuyAbG7 zLg+0R0?X3QXPWO{u)F!-k$L6=(~wH$ch4D*@sL&@8Zoch7i2dk64!MhT}=3S;M z(HDH?KKoRO7b2JA3(W`U&fGQr_T<}4SB!txjemqI==!l1Z~K2^4IQVF{9fF(x%+fk zReHNMxpo|=lJ#|$!jg+S#7t$!Pj2t$`dmNRJM(sz<=RcA|3)Eszl@$+|GlBzf-HRD^Ce19x8Ejcur zO8w2pKmPGgq$;{_Nd=$C_ux5b0-pWf@?o5d95<#a?%4OvRO+3%4`5^YG%4$orO%}* zKCv&AN|e_Wq`f|IRG&UT%KAk4tf_taJZQ&lNTqh2bH_QUAd#-lfAH^rB`>1gQT6FPVw?+=XXW4^SjdR{GKKozSU0d3#LbV zxl?awoc6}X@;5c6Zf>0Rjz$dH_`TfeU}m6+`Pz@GA|=UFZ6U9YXj27SlcP&H9n+;e z)9F&4b>N1;>T%9Qx|C~Ux|C;YUCNvB7T_g^!2q;3tO03Q+tIN0qLC|W9vWG9AosGa zfHe#aYZGl;2yXdkqqTsJOI%;+@e1_wU+wY53cp6-K83l9Nci7Tn41tp&KgYc7JSzU zzDnVT6#jz3rHHWbrz!k$h0j&^B89I~_%?;#q3}BueviWMSNMp+C*%8D;TS;r$^eZSGh2HjFq3=K+NuR`@A}pI3Me zrh>$61F%~+gCmy}=5&!;UlL@AC2ki0i`z>=PTIUi;bsg23g-%iU#IY$3jd|Tk0|^U zu!}?5{JX-O7jbJ-f-Ldde7gMtSi+r&p%=$Vo7oB<4=kKA4Au*#4rRgTDx6iAI+VrF z{R(r?AFCf=f-Ldte0*LHEPnoZ$bsH!g&$Cycc9u6{(}lrU7pCl3GBj3o1ZKE8-+RM z&CT|V5AoZ5d|m(+f9B(R%5lM2DKMyL*f#9V+KE&7h z_`D5R{QpSENt=%<{Bgy3KPpY(e^TMED*R($7gpK?80{2XrZ7iAm-+Y*U*zLc1uXub z9&*y=Y=xI7&hZ$~6aG?#*C@OZ*oBog8~}6+XoD>AVjpgg;$Itb(&h$*->5iyFzzMc z-VE&gOdF1eo#LO1m~}c#_BO?TU&u+D4=Vhi;=BcojrjjTg+Hh8zbO1~z%Jah;TY3G z9|z(gABP_U%Tn`FtY3GWw5e3M3RuGZt-|Tqk^FRp8x>v+EPis-b%l*Xk5y;U?eS!C zw$09Mk8PpFEvj21Zc(-PXY8?Ux$sLN7k;_oGc1=TPK}7<3*GrPJx|}aq+u&K&i|?P zeLGIt^n!mn{`kK4;#d6N3@m9r2<$jc-}jlgCx1VFg?|88_%{JNj??$;>b)R)r{dqO z`1b-kPTKqp@M8SYe`4|fK7U=rEy;aBpS z*e}k^J`u{Desjs+7a%_#e=t_Rx#TIeQ%Rl@H+jy>Lb+2RB>BkgKh2(V1+e7Z-N2G} z#3y>rdqO#M_XE4UfEpm+Q$6SNp*(G#29`V`7Jq&e%G0I-FOuX7vG_ARltV{3u;c}? z__HLGr!kBYr9ZK7s2s!POFYd>5nrh{YJesEiOc=7L~^%1MACn*;t)&v*8xlV6N^8Q z-05VO^rt)F5KHk!DJTI^tK?BhutJ9q~3b5NUFh1d%>2E`NpAwn9vWxcRZaosR2d{>WwtbpOHO z2tvL;vO%KCa^~YV-^iv2rp#m;#AG7`Q#cu1nePcCvYCM;CK+%$gKS}l=(52EpUdEI zi_PK4(j(dAFw1hd%^}~s-%FXo$zTw_b$KNJZEN4Dymv zcr^b5Is99}Up58*p&b5SgMZl+{BJ8hJ2Kw@|GFvozg2v846E?--YNLARC=NxWHy5T z51!Ai1dV>)(-r@fu=@w_=bdk9;Vx*+Z&mzu&|Z!2n;lc|`6(#o9)L%{|GeiHO8=dT ze+c}Ng~mMX`RoqR==i)@@jnT>g{N6c?59z2HYOsg%OQU^zN_BK2ZwQ=N$8}5!}o>e zoyzU^Apbr3;_r6fccLl4e?U0?Un%}ufdAEfZ#hfxk;CpRqH4 zLR%fvJ;;v9wmNpBTbq1}{omksc$KhuZB0{8_xjG2D{+2C*ShxZOPbcVahsbGH?_7j z+3jgLGP?&cM`m{-=E&@R#2i`M#ogTY7ne5IbL(G@tbyDAa%4-m1u#dpl-mGvWDEtH z0prq^dTt2Jku`8rV2*5wnUN=3YO3;N45d0(+FEaF@?;GrohMsjX6DJ3;!vEN*t9Z~ zOia45b8UCMd3m0!!OYK-EitdilPxuMd9riN2{Bn)_L4RAUF%w!%t;01&F17hd4uJj zQc&J(PR)}qvHXPv<;~`_Jo!?~KfR#5*_@FlKgaUVEGTa_XXVM4S^n7t<;`YMp8Q

    2T-rX$~`*}3T~ zWMkc27_;eWZC_L0z8Y^-PeFNu=`AQn%h=(u3g)?cBOBtytr*`s|lP3 zojb76aAeocu{HKkrfKk@>{}QddRfWXNZ*c8D4LWYxObY3VNb3_iQTLi`T?Ge2)7U` zuS*7Y^q~tAhG%zNpNDp~C)c9H9rM>Uv~R#}zGgezqhw*sY?QeP+cG3tR$4MLFtlUH zJro$_mZ4-Nn|6(ij!6)e);bb}AqZi5ECeep86D}rWTbDWP^v6N3rjW+jE-qajitn- zmcuOweA1bry_GNovC4?=p-r=WfU$v{bUFK4rV;p&)cPFVf;7jH7*S#UVm-=d zhUK%8i!M@izrpV;yMaEFKoV4z<0n-&1HVPtQ13RzJ4MJ_5C}KMySwcSGTaysu?fmz z+wE^5J=$*nF7o|$`^a6P4fTI74&8?O$Hd`(cSC&?s%)UIgV&W8;+0I*t;27v-B4d^ zH`LeK4fVBlLw&8?P+w~|)Yo!DeXZM2U+Xs1*V+yBwQfUwt=&*xYd6%_x()TUc0+xw z-%yXM-%t>hT+Hs0X$i>TBJG`dYuCzSeE1uk{=1 zYu$$WTEC&b)@`V-^&9GI-G=&FzoEX?ZK$vH8|rJ_hWc8+p}y8_sIT=K>Jh%(P>-wK zP>-wKP>-wKP>-wKP>-wKP>-wKP>-wKP>(A&)Z=0|)Ypa^>LJk^>hHxcIIDhFBeFgi zz~|wp{XWANJvY=Bur1a;5Bq6Yv=hcSkk)Tj27BdXD_ad(rN-D`&#KJUhg@{k6W%3) zE2ZYN7U2yxd|9WFCo`cUIdm8I1y=h)m-Jt5X4~}D%7#mr>a*4GAm}ETgW(>uvQ@h< zVHV|xt$JZ$pl3FoSI(xW`LwoZ+K_BM^+$)mMM;c&8f8oVA)AIoE`MxmBkh8{!HC8+ z%#6q;yhCOb$hvEDJZ5epmm>FabF5jW^N>>?u}nRcf;pIiWTp;c?kCDrY5ZX4R=nzW zFtjXc*1op5S$loKtcB8vG3h)oXKk*>B+UInIf60}W^UN>+l-qms|)$U44=fC|4No~ z-Z+-!3n`exAxUKU7_6f#XDL`GyQt3Scx*CWw39@ zj)85kGKMn>IxobosM&E^P~7|&4zO$?$QH^Eeysbir2j+``LA>@K^E-GaRiaCyeD;a z44GkjI=b0Bi^=XB=5|oAGAC~3dORJu;;_Nom}_I}*6q1c`<7iBN!@sY3|kzCEO25- zIQ(E8y(zNG9fUX-S#2H~jgMTsm3DL9#$QwY?s={R>JA}n?2M%y-eB?6mPIUpgXR^* z+i;C8-XNB!2H`2QQ6I0s8$O2Uftt@l0U?arKPtO2@5=nmo4@IeG3p*5t{5 zwJ_mWsGj3mB_!iwtg>N2$}Og_%}vO#h!<^>r7Z~$CyJ)M#`^!Y#4(n%KQt+?#bP8T zW!`HYOUpdlqL#~lD{^8!Q>?`N8D^iEn0Zwz6BDn#d&Bc=i<+2MCW~7#$C3qm$id~? zIfTwJcz4)&fm#tFci4Hv$}hfoJsvllfOZBofj_ppuErhPJ-e@NqOqpAdM2*DxK`nM z0M|-f@5Qwg*N1RTj&J8`{Z=>xsX#KGkbOPLvGeI(OpvdAq4Nqx6OLdt2|9xRyd?#+7E7 zKOU%kye831#TTD%AD`(_>-gLd>s9?l;1xk{4R9jUQotrRnx+ACi4_>r02|_XaCz zJ#^%F^USo(M~r~KX$nJVC$hL@w@WSPoSv5sRPLm zZKrh=+-A&?`#Y*jx6-GpeGGJXE_5BA^=FtI@I&U^UhZcvj2F z55S)XA9>(Qj?-&7NpN~=x`ydbOVx)K&NUCfr}Hn4cn2)61iS+^7a%@&hVcRV)xFj> z1>1XT7Tb{S%!v@7{gYHJk6N9>;rE2Yf58jkw-{YcH<%^;Hb> z&AhMrAMKlYU-eh1l4b71N1G3J92&pVq`b z@u}+C-j0LM%6-YNs%P|;CpxSun5sUD$SeOsbs5518u~HQax(mV{rJK5(l5N8KF`7Z z2j~Cep{B!?)_%6LzZ~{g(0;m=j`RKcJi|CH$G*zjQ>3 z$H8Ac^8A;ceB>uzYM$SLn2cY}klIV#lRkE+qVG|JAIVCF-QCT9gsMxnbFPTUT=Z{ZUlJhbh#FO5PL+to%qir67zv4IH>ZF>(@ zj64CAAg`#2X$^t4m0PHa<*7vF%)N;XaW}Cn~G=rz#T3 z>O@JJ0;o%ghefR_uZB%YI#E%*Kar|Rq-NS*D3Hl#UhbJyiHfSkteX9ak}AX>-WMV# z{~a1(oX=H>%8<_>3iIDY7#>o;vm?2S_qbCJdFguyi)^Mt{59&b>X>&ivmt8f{g}<-xGYYRl!IQA4(nRpZ3O_T$m|Lrsb)m@71$8qIB7FO;hzEvr=&We|Mi~sLX_%4OH@S@4bllW^s zo_`L!&dSr~Z$nPnd_v*FSlBO|`xXAQ!vCW1PZg#*5pg?5;bp)sK54U3;f)FpDLkw& z7bUd#XCeNjf0o_A64qNnPTIUp;j1wwDV$psKBDmF75-O+f2ME+Dj4zSG+-B>v{|9> zDupjsc$31Mi*NJKLd7q!oN|N6QG?wZp1hGG=BkD;+DZ2s^dWQfx^E77S1emmIa@!aHqoCfyJNe z6uwPii~)q4&nf&Zg@3Ma8RiYe&pL%)sqiHVk1BkP!km9R$EO4FEBt$O09c;u9U%uQ zO%%RcarR+!Pxx<9_)cKwf7)=S$+fvbmUyKP>phD9w;>1hkHYUn<1PMwNa2Tpou6s* zuL^%pVNT(k=bw>yl@Ir6VDa;XkdsE|QTS=|B(QLPqwp-uXE;Bh_C(>+73Q4B`954? zzYRQF4=jFO7;@5Pt-|#f!o9%G&$PK(;XMj-g5Xs?T;dV`yw?GX+Lk*)PTIUn z;p;FSF5%v;@cR`0n8IHLc44K>zbX79h52f^GT=_>U1j6eW7RJ7dHiB=k}9kUUs+(oT{Qi@%ckJXi`G|QGJH~bBsa4Jyprse>_^aXkJ3MwaP8~tm5ZFB|jEF88>l@ zsw<2q<0kUcm0YJ`nc|=e7P{4($cJF(Sc@wZJdp+hLuzMeS45zo{r@{ZpLEblV0_&129H&CcrT^3_q#VbokaBr6wF)W6aVn&wZ!?t&Dd}UJ6i8lAtwPF`2dMV} z-?f85mRQn>ejd~ad0ZwlpU z^B2HPRvcuB`R>7Fx!>2x)8<>il8?lTJ?FcjJZ+|-QkJ|UUg9}bp*(F~4eas)>MntM zJf|s?r_DXUl1IeNo^x*~kLOD%?4=FDXGEAs#O2;?BzJ15B#-7Q4zc7>9kApPvG^0o zomwi%qlJn??Br0x1uS_)EdE4tr5X<|O z1(rM_7JnkSQ%fazv{7-0JmOLUBe-!@gxCC*&T}wi>U1@m>AZajHg5xAw!wD)vlSIv%YqVCA2nbbAOnkG-dcp2DA9f+nD))zhezC8RsF-shEQEZO>t^G8r7tUoVL+ zzx8k$Z3C9|e2!=lVd+c;$f{5m2%tBjIfSJl8N3p|e8RY4kAa3|IvH?IET1D9LaHt2 z9{%DlZbU0c4aCXd5Ps=n+=wO+)~U(hlW|LbC)zx0E(Fx)u^^8p8fjA2AL^v}LLNu7 zd}J(#dOq@vX!hW{kqma?_ryHXKY5qasm#h^rghwW&vW?hI1ZmbZhql8GeUouA8}L4 z7XoHl$YI{c&GDX76>^woadU>}REHeqS=^lOIffiFfIBMb>br2`IbEBVx#eGa^=p9@ zpGp+1U9`fyMR-=4x0=jW1uLwb4oZpROHA`DqF|L(Uf{}Zswm_xdsfbzm0R|lCk~fA z=h@h0&v{b2f;mqr%iLci{askvrz36C*a;*cB?_NF$)f#J_Mp0~82&Km01nr`)LZAAsc))wV9aHaY)s$jDhK((*A zhP4uFZkz5omMH#trp`-rOC+R1{6^ucR!R7Ut_PHGRN<3R`O^RES!KhpzeFSPCtkoG zZ&+V_fXz*gscVb`DwkrM{_;Uf8IjV4{k+w%a@Ab~g{s!Q44l37ZK6@x)76M#?v@9b5CXA2A z$F8sG1VqiHR!OQzt1j&8(Qo7VC#0}xdN1;9GKEc#qpTexGJzVeOaND}OaRC$ z695ur0)S4L0Dx5{fU8v|fGd;<;5Sqz0Bn^B)Hr1VHC~xOjZ-F2&Ek=CH$;4dhF&n>}#}3_*sLvCHymF-+4rW$SvWISZS9;y6?#vK1i!B z4coq8CO^{xGwmd_0X9{&6Ij{LhNl^yJlkR>_n`UTnd18YooFvlEG6Bh{zx=)flVO4 z$pK2^KNEbcxq5aV7E@>4CWl5`t8m|oYbCA+a4p64UR)D7n;i6(gHn6iW`kXTo=Mnk z1CLHzaO40MnOA-Aks~*I*>zmJ|HrjFcfj;xT4^U17qiJ{M~?&dFV+HGRsntit39QV z!v*1~f#omBB31j!4k8}KTBWM`OVKjb|IIa&^RXzkJn@Pkwh+}Gxwja$r@ST=9B@`g zS==bc*roE0u`7*EuPcjAuPb+_*Hy^rb(PT}a#Ni(H!Y$?XU&Cc7^le^Mt>IGE2mq( zFvu5MP*~*_6jsZE!kTD7VLEo!+)TZokmU{)7Yql{oH@~7S%$Q647U()wzY6)#m)41 z1^C5-bmWnv^BaYqSD1~q`*sPk#3%UplmN@5-Eko& zZCrSN=U=YQIMsyN(ZKdRjKk6V1;^3_ceOMLjD@ZDCxlG z6aR_*hh8?4y9qP#f3D&X=llQPo9wZ}?mkX#Y6p^VaNJGg=)njSTMR+sC&%ak2zE{i za@3#$)20xI-Y(z|42lvs@|Igs_#=Y_C`#ZkhZ$%CZYZ3e|M^Bf_?iF7fF;@IzM|gkG4sL=(el~i=A+>)heW@F zI}V8scJF&_cFQ>h`gVR0FR#z1<$3+{7iWO4aNl0_TaPjnH?VzZ%O5flS6{!hzRnts z#Fg5SxI0iX+|ZMZ#9={IXif)ORv^3N<7G(Di^4 zE>`#j#D)G}@5?`5P#TH9U@OGW3HZA*|6K|B$2`)M{5?W-9+ebpL$uBQ{$lmZ`uj&0 zwGM3BwH5DAUH6)=@cxx4WU?>}6-y zpS`-f3l=-Cfr^^JvATu*r`6S;ciytI8Wz_tuj?Mz+c#R*xnp!}WY_kA9b?4(!y`L~ zNBYJFHk%-62XqpCKqnC&&`IPD=p>>6orDbNL?ju|Nw@)>$ifZiB>aF)B=-Y0)jb)9s#ieX4-txxl4h!}VBV=Uk0%s=3;cf^>sNA( zeqUy&_#6PS9WTLa*Etubd56M3<`zEj9lWW|FtKN0ZXv^3(p|=k09@zVqx{1mBv*_76x>{n75k6h6 zMfiNV7U2`-S}c=i%(Yl951DI$V?O<3=GipJgXY;R4WATNv1ffbA9D=twd9O1S1s$- zWN}JOPg9taITp=frsY_)Nc^OTidU^+By2ev7-<>azO!#+0289SI4fAeSloxt@GvTC zvOTNUHMRC&3bti!_j)(gDkTdMjN4}0)_1PM(F8uT^XxfM+v7=6;6jp=_yUf*E?wKA z!k5AqI^_g$Nb&wlNi0m#F_E&F$6U8|^`&Srd;#T~7pB->cVMlF#qxT-hPTB=V(u-O81#qspaVT(AwyMgT2lUM!H_-JNUNnwz@X zVkII9K{MhRUYN5X+tY&LF0Wi+5^GFH^I2Ay=KN~L;Yqg6DNGW-nsIVc0b0GQ-dV2~ ze0s6BmAJ1Y;{i29KKPhXN>k#m24RqxVm#k$385aIMMtF z&23L8DcQVh?3#=Fwl&c%VeLYR*frCxMB6nRoJ6vFUQOQm~kCK&)ZE6`Cv2QP|r?E-ziA1yw-A-rwN=qk!9cyp# zc?Mf3*oHFyZoBwRwBMxPlBMQ~7E3qRXC1n*d%u#NEbNe{mhQl5<_-GwUGOG;q z$`jG0OVusJZ^o`e$=G!$8M_W8W7nZ%>^hW;U5Aq4I+ToChmvvYP%?HMO2(~2$=G!$ z8M_W8^hW;Ux$LLUxxzZ*P#H(Iut;+4h6ujL&4RqL%|j6Q1BbBLjktyP%>^E zO2)54$+&eW8NUuCrgUo9ZJTpL&>;xC>g&FCF9niWc)gmj9Z72 z@#|0!zFmict6hhJt6hhJt6hhJt6hhJt6hhJt6hhJt6hhJE7zgmV%MQ$!gVN+sC6ha z`Y~@}tI@o1Zhm_3ixTTl*lW(SFV?~Z4ioj8;;ln*{=X_(hr%z8a2?7(Y%LCJ?Vh+O zEh|$ZXAoT*Clzp4>yl9~JV7O7f?74^kBC4OEf=#x!}f)^+LU+8es_%wxatYEsE63k zc0T4>7dKy8i=}7VfA0*imgD(;C%kO%wiTB67iMEhc#g0A-3 zM#8p9wmph&;eOB9rtHXOG>B#w3rTnftKI$EcQ%DKas!K9z|Gpi-W14wJVQMDISvsk z51c=Rz<<~B4dj=w{s=k2G2{)kc3GTD)8EHKOF7mD_hK9S79DU6DTi}{+V-xKPQur< z-Mtvyy*6gYiM+_}me}1RvAfx5w+jTD9T*uJ-fXz5Rc!rI|Lh>Xkh=zlwv4fRZuJ}p z0}mb9nsv%8Y;qpRbj7XX-%4GBeVd2(g#CXGjH*DU$3o%|@lk#HyJI1J=2%EyI2O{Q$3ptw z$3pt%v5>xhETn%w781w9kD8djI~EdG86DN9vST4}A9gT1&0kZs9eoU2LFtwe)rsA? zY(FCMY>U~#4Vv$!inb<`U5`QY(^Rx5GuB$UMVXOkHrI0Cq=TQ#iTY@{RUT7{^E8uH z^2M4Ww$1e*7StDQhTA39^wLQ>YW*D6am})WXnJ!K5Ta}Icm-PGyp9;YS6D*%YpTDF zUB}Xd<}|P%*hN%f>gU)Ox1_EucH&<-S>o>uyBPL6JG#Y@LW7w7@7g&qusQ07*w5_( z@=3BR@-D}B@b?$+W-{*!SJlo%B;;oFBzb_V6AZ1Z-(^Q*fNH>=MWedLe zjqM%h$l&sIDu~=5VZAR5B`?ftMz7h?&lboBU<*r*3_k1?A2cmT2HKucJIavfU#_%3 z37n*B@+y=jR14cqnydu6@dp+>6w=8Go+A~vyp2^9xyJspis(Gz=qm|hgHvQa${TG} zvT4{tc1Z>J3XJ+gn;&d?jq%J+DT1CMtN*vZ*xc7Wf)|5j<(Csk5+p?XS$ z2;!P4A`9!i1!8;b1?B>j0n`@({4%>agl`phk+qPd0CnK|>LPBXfl((K>(SS;@PS@7glaaaQZWtrMMR9r;pl z*OrO80dPw|EABUq60%t3TSxxoh>uPnBB^U47(;n4mksq4J&7QYDjnvpP>xoX&c__GB`_g{!mZursV@dOahrto%g?UV~ z$1$Hwm>=A%n5)dsCf)>frY?1Z^_@ox{pQZM2lw1xbstjc$fxJwxf$EX3{&csr!h?Y z12lJg>VAMBncUdqxiot|^2C!7+M~(LW4TxJH77|tCdfQ?;T0lV<&mW4qTZ%6%wq}f=Cc(9;&r!+U5>fCTDBY(5Q zIibK#LTQFw!Zl#+HvEL)>Xm%*kU+f?!#M` z>yCq2-rf3KJB~VfyUTO!rgF#87w2wlf37=zAUnIgy}5Rcq22E5a_we^cKf<%$LAHp zl{n7Nkz`GRwoqJ+vDTzjogD4|WIh?cQ3&KnuJ3 zFzx7PbH2N8)OfoO=G*;V>>Bg!Cem>C>d{oi@&$7jEm)9BEo{R9ZpY2aXZ~s?nCI_a zoT@lKn+lrp316)R;g!431Y^Z7Qo&!v8A&7+HK;7wmI`|Ft;TUg-f?H9=A4;2c}{A{ zoK)&%+YhY0;nKwXbgE+2f2301NL4i5{{2+tuW@^O;^oze`7`f&B9;2iiZhq3Xl`q2 zOI5U9v@tbfMK)QvHJhs3oT^wW_g7?770GE=T=W{+Uvycr@`{TtO9hv@I2=Wb%M6n& zZWI2X3rzm8a@CPYIjDE)Atc6oSbCJhXLDS{&#R^jejmY~H=3*g{|Fy!eLbxJtR`@tn%_5(#a0(F< zd8NYKk1O&&Q+ON$O(Lfn8NqWg%p{oVUj)Bf;rA(g7JB5uX;ApD75+PgA5r*eg%em! zDE^$NaJ#}hGfy~gQ24zHKcw(e3jbK)pDFw+g|EhhulRpJ;Rh7{gu=g4_$0iu;`TI! z7b*Nj6yjC3Yy?^2yO7^7*++oI?UNxVZGNcm|C$kTeyDH>27JVAox<(FF08bQ_-qCiKd%irX>)_ZTkzru=YYcRQut#Ee_i2UC_EkCa^la)3bz5f zxIvYZ!qmPi@;58|L4_Yt_!|m8t?;u7Cs0XN~s!mSE()wt7d9%PA6^zXtjpZ@@su*&gm;y7tDUEyB>3#Sqbz638)IIHlW!f#dh6TssCBMN^-VJ;}+ zv>ry9v&5JCc>W8pg!}7|lQzFs_$iz%C!F6ZTzkCunKq{=e5S%&-oz;ahD-b&AMO%h z@v|%Bpx#rs1sww6T(0nLg>P5*Z-8A`Y4Zhzzoami1U32i5X(7>Uj>%1eiU-j=06nv z3YJR<=Z6Xh=%9#vp2DvJc46VXI)%Fx<{Fq5A0J}Q48UYx11x^-4moMFPvJf++Yrt^ zh2Np@UntD;=UiCs{5ioqe@?Jn3gY8KOm&@%56?@Gu#T(4Lvdxf7*&~*)+Cq8STnQ}YjTl`Qnk>g~oIGu=1(q^KEdDTDCr=x`r>>3)vc$r< zJCx%Lcwkqz1X*I?d_0t=%|8RX`Yp&33+J&=j(#R^lZ|GOB^J&zp*(FW@D92gqrGaAa%<`A&t zJ2C5enCzd0^0fIdu;exIO`h|Yp*)_yrLdQ_o^6WcHF3Fj8_ECQd6tsbS(QG-lGhu7 zC9jDk4I{a$ZzZpL6^Gc#(}wk}x z`%4ADat>uZBrFY~Vq}~UXw33Z0$`Ux^BSFkxdeCYr$nbEJS>PIwwvW7?o%uB{BZf^7bR6snL zQgQZ}Y4~-P4AT7NZOky$X{O;X8D#j&+n8Z*n1E#=9MRgzH*+$7L{leAc`{%* z&JRnpb29ak!GeMu(a2e2IgJH5qJ`5wb%0^c0%3{fO`F02=f%zdFK$HJ<}8Slfz(EE zj%dteEszZA@lXrn1l);M*_7pc|5ViPc^uKCX=58~@u?oCiT2Dn)}I6TJuOba-OGHk z@=ZxtU-)cs)8IL*Hynqd#!Y9KJyhN<8Yvuyl2O=G`Ech&S6#ia?c6DsFS~{CdPjM< zG+y>p`HeZzn)#fqyUs!3O`el^#%&*whuKi8MI@8Z{f@2BqbauuO~P_}Izr3BYyNGm zv|_5I-kxFioaq$P@&dXxa;$SwPumtwL(Rzd-lk*@MWttsO-`!j*iMP>8AK5&>uuncKr`BJHB{+Qxl349`((HzsL+Jh2>_k;I6@IUGOXDdy^zLGqz z|E{$1HE{bHG{LLb*u$`QK%>*=ZYQ$8Kf~|+1v)dD|A68z2EGH9fA9U5q!oS>8?5e5 zV;lEW)9C2HcATR)V#?=KmQ7C_NF;8=W}rmkp+uq+Iq6cXq@-9Y==eJI+t~jJ>2$8_ zMIJ{Q6@oxjFbR%PBx>(KCqQ_IPT%1##i6?`!9!SwqB=3|T26>471fEQ zp{hjZDm)=##twK~HU#gIbvx*3?z2}}Rf$zrRbrJ@l~`p}C01EgiB(orVii>-RykFP zRZdl6l~t8kCXFc1ZtcT=8>QKIJxoBocrIyN-^n_NNdj!hy{3QLz^HK! z9iApzaib6*g7TicARyjf*n`($52g#%`W)U>yIj$ITYgsu)vBIivk?=pc?)Vd`UA!C zr=ew&obB8Jeb3q9ZG9s{W7oji4fjSlAGa@V&R<^SoPT?;uVBtQwZ16oO@?2`J?b9W z8{ReN*itd@P1iW<&K;Wv_G)`40Aa5qbd8M+ZyL}HFPWsMgrVlgiA5%~&X3eFmyeoe zTO2A@qo-htgDz4m3GCe21j(~4W;qzdP*70|!k~Fo5bVz{2?cVZhTrw55V)TdyIn7G zJ7g>S>Lwa5aywfO;F`!eFShiB)@!4kpQZN1*z@cj!q($WP3aK#My~KX6fZ1&c7E&I zTOKtJP26+jOKo?|Nw_m*&EhufY4vy4!G3Yu;f%MN_%iMMo!x<1QXs@lHiVW#WqqDG z59-Z^J)S%9LaVYlU?Q9ACsrz(MrHHai4J8`r)<7A@yB@H?bT-BzjfX%-w(G}X8(rV zJvMAV{ob5Cxpw@had!I>O|a}l2@B7{o&J*Sud!dkgNR4bcGpDT2GQo1k0r2I-biU1a@&Wz@}y2$g+*^T#^djk#GMUY~@HbU6-mj_0m*oU4cum%J02MnM7r>-0!VO zq)aEioszP}q9kvNMJn1^Q5x;6D04e2%A>svQ|*+fh-g#ol<=qThMOR!E!9z-?lwWp zkWCO((I$xM*d~Y?eO~UF$U?MPFzf_4!*WT(GDySnrj28|O$!UGh1;~i!D&v0aMMDa z$K13a_%#ZDL*XANOf{IouT%K73J)v1OW`_1jFU>JaW&_^`r%rSKyP|48BK=>NI6VUeZ6Co0T7q8ro> zvcx9_HqzPCfn_1Z1tBMGS`=OhEb(86&V}If73M|`=RXJ01^3uNmzUX~+yXlesG&<{ z2UtYT&aB9f#qC1yF05PkKLer&sP?$q}1vzRUnD0m-4#eSLF3SVX zMW!gvtnd<4A>c42PyyzcOZ+|aJQ=XXVa(!Y%-`bG2Zuwo`Q|1s;umZ(;Bc!9u}0k6 zJ!CAvfp^ToxVhWkazHm3a2Ph<$iOShM>0Tm+KJpa?-TwuI;WY>A2(m|x6F4p9hlqV zVl!3fgp+@1JQpYbRxNJ7bmP9|m{8+Di~jzSIhLv9c>_1v5iH~1?l02JOu-SMaG)q2 zq#BVp%GAu3ZGEGI>NwT-Z$gf#!95GDe({9zPyv3Ox707;RQyKas~1xEg{}vb@Y}A_U?rni z6vO!Zt!w$rr#(;N&s$gcoCW1e>KxX;b&b*8D^Lu@kl$4&chObz&sY4DKp6%9ZLEc1 zq)O2I%N3s;)lb$L^S?Y_vPSa{C_dNR%sRoCpHIPmzv8p%S_6J9Yhai{{{MsGv*CIj z_~%W*|B>R;{|CXpVhVnFf+0IY|Nj;I8>ZlM<)j!kv=s}C`M?zXHpM>${BywnqURS% z|1FBoD(MFBQ*04oTz3GSfJS?3e{NEIHi%^>8uQPd&jx}<^Z#7&8UORaKW>?&6)X=A zDgI|c+X{ZJX;f*xF&WwZCFD<`&~5Pkvx%nBGj(54{*M6v84~GNo_L0%$7bq&sQ9PA z|FY9ONnP~&^=rky8Jx55F8Y9X-uWYga*5+RhfIr@3#(Rcm)`-^7De=~?it9BNPY zlJz}ZtJ~VLcs(N@oVdGbZEN$TF|VyfQ%iT}#XQ$gg_0fK;}u{hZe;{}* znIBLn_WlLpUv}5_oyxyo!M|!d9a-k5Bg^8`k!874a%ItUWSLAyMkJYzEOXP5k%gO% zEY;JI_u?^1qv^=M#BG_Mj*Q&-=}7O;%|Cua9J<>di9?x=jJuZU$TFFZEDNV2ZE(@a zZ8cr+seCOmzof1UzmY%wB)7Dkj!fI>$h4h~Oxx+mw4IJj+v&(Orz6vDIx_91Bhz*| zGVP`#({?&CZKosCZaOk;rz6vTIuchu9SP*8BY|W(63|UY0@&$DTrH^VuY#3q0P2k z3TCQ)d?j-uVz;%lFp`eU@2D6#lPlmzO6VG2D6D>MMYdsQ>%g|YYfRl_1iOOnDRNu*`{-pIg~fwBHU`wbsDL!2&&(wAM&&}v{uAC}rU57`IF zvB2>l&Od%1=GY;X>@YwutC^Oj@C(?8d$l(I>|b1SLDpQr`VbI;s3GBvw6ei?%~^noQvm;&AC||%?r%5 zn=sbn@+P;yFn`!DzY_g{Nh-RcX49bgPI0qo&^-QM%%)jfoQTBxBwi6oyjZ1PFzsTD zA}8H1ik)=7vPmZ`tZg>sh7GFVn1xTa={t~oVXdNC4yGDMNPKCFH!DR>umwe1KC#7) z(hZt(gDE>N|I>XGjvdF^2ip&sbt1)P`neeS2(v8gfY{0g1lw1LaxHFOXHCaQC;m&wQax_1f#i1Nz zuyya*a8KpG`8jd~NCUrMi9-&E%=aGH;X4#&; zncj?7&*hQpK8L+z<`9QeeGcW=7CC?JDti7L!3r~+B~-*dul*34Wjm*4`h(~Kxn$1$ zx?wtVDB7oUu624q9<`O@zPWlz6}2(zGZb8=I8_sb0Ah7)1t`bcV?p4z54|& zaSQh1C+*%xja}?ZCvV`vRl@H3bNUG8aa_9U5e6CAVhVH4F6xqmeM_MfIjz?hJ*_t- zj`Cfw*$(pA!AA#=(uvIDM;UXJamq=)0qh8(ThE=k&HUDU#(eC^{aC@>8+`18Z^sPK zXYM;BCnCZAxykJHi8Ez5ujkZ2&bw(jRK31zsBYrSP_kfm^TFUWoIz7Q{=Nt2PCWC# zmmYj%eEz)Mh0iy-Ou1`4^?@_sE;us#{EIJ}un1@TY?-(c=it=2wcw@qy_x3@eQ>_N z|9kN_T7S;?9ZN??3Nc#!pUyO3mAhJzr+QZu-Kt=|N)r&PU%l zZ?~iq&yF!TAE<8P(*@Y$r3{D9o6pBrK%Vc3NqvVZu{<_?e|{3*=OiLNP67h+nTg7* z#3VNdFA3Q#hbC+eZVV+0cFzyf%-A&Z_dd>-)kpliLAMnt9Bo;A6?JHCul0n7iuVmdo{>!_N0IoZ~fQSKmiD=i+c)jZ{hOv^kko(7Vvd9**&Gea3C>J{0Dj4Egy+NpL*^V{;i_9*w$?U-IDDFmZ zKW2vTJ7V_(3`4re^qU5=*#6rCe`pi8-vayPP%n6{*=sg?yKP`GOejsjzJjaFR>(KQ z?U30G*$84Zgm4#`T(^ZeQT+Syf^jg3YfpJ%#JuSlQ(jtLR$g9SQC?X-t^8%>=a*kl z-cr6&)@XtZ!y!+25ukDg;tzKtAURQ zkI%<|Ylp{|D9mM*BHyI&%?iIo;h!t~YlWMT5aQ3L6@FA3SXk|n8J4hzuKqUhZX*!!rxT*-xZ#Y zWhmnIbcH(<-lXvL3g4yhM-~3E!cQyw6NS0_rP0PY$P#}7`2>^wC9tGbS-Ei1h9~_t zT1whH11y|rmkW$k?vRrYZ5_+(6~G+1xaW|_jTRG1SlOD!kJ5)b)sTYx3pD?(1%^eMas16so2Au5933cS>Z z`yPcqpfG15micgrxu_N<`ypWQ=kp;4b%nxzfd*7KUsU*Kz|K!(78+f_r3!Okez^~q zxZj6616ce#DdeQhLWR?4(1mlR!s~&ZpJ~&t@Q}hBuXZcIgDmkzAMQ?I@$;sTlQuUi zyd49v!g-^@4*)wqQ70(;IfXfh%bjKTzQ__k=)-*&SoSDB9dgp<#|nQFA2Jf|&lRq~ z0H(-KP#9VZd{}9-LE$Y5Z&Mgu0AGK)0~1P$0w(Vu z0>??)IJ*3u`XB9MBvKL)CUnbPTDlW&sTc?iN*g`V2M8u`f!}I zJ=Ds57X(>;e+j==@izm@x5HlGM(;nd@b@b|M&&&xZQcRg?D@pPzfXoJgLwX&~jHLve_m zJZ-YT^q2WaEdE6DwAl!`lm}wrL~>V$OL^#39AYPThZ{(}F{n7iQdjH*Zp0tsLo8uM zavW>|c{3^C5DO=g>pJ1+x)mznN2E!CDa;ntNdT;_174#;61W+Ht|HwE%nQ155&(Z( z31cTJ|IhK9NGAewVK)Ap1i-B44@`7y!nwF(%N!k>@LCdJqGJ=5gydRIyT|+o)aCLKwS^?#~qSD>#uuG z`~U=U+~Eea{(oP>&=dM@f)CtXY%<$${aI=n#O_ zJOF_beFy*^6()nxNqYc-Jrqki=3X+W zp(xMDHg@)VC*yD|m4@$4GB^pp7;MZjmwOKTnaSWx{^l@@VVh0EHz66YR?g?V-*cF< zPNzmbN4BCf7n8x*#?dw0dTkxJm1LHZ<|xW%^=kSel z9L7FwPWPPX2m+>K+?*d~;ei7QGk`nl6WP$xxo+>!7FlGJyAQ^%JsKK~t!j!^B&iJy zkuY4QWEX))^7x8sFV9)W>!rD?PGe-Zh%e5J$()~DjOIy&mREVzCvN>!?sMl@#-9G{ z?#{EJ9e&HM9sMgJ|5Zv9Cd5;vFejcu1vojWRe+J3as?>P6PIEIti2DD+DEAyOQnKo zoS#%`uWo^`?P7Afxv_wy-X!=Yjxl6&kM{S#l&@#b{=ZDDJeV^}G(;nIz-P;M{4uk)6= zA)bogD16l@3%}6yfD-b9O3Yk*H8DOr-4}s**jq^adCP937*>7v*BSE__V-{UDe4;S zt^HXQLE9yKtWF6$)cj4#nq8S^>WulJ_h0Hv&A(ppK{e}7K-UUgCz?Y1yPcK&We4~W z_=`PXvO@d+am8mx_xIrUPT~JQD?UFE-n{@P+fBj$vEuVF=beZ&oq|72*W&@-yU>_# zobM!n*68y8u;TOls1x%05q2Sh`2TgqKLFpJIm?)jzsmW0n!AMjW7j#8!JF!Gqi8y3 zY<1ahWB4beawgr2{D^j*$4-Yxw&I0Iex0>Iuoy)osMy%tw7#cvZFWO9sv>pQ5VKoi z63T9=NvgYZOo_T%W>V_zTvMvBuz?^wrMF) z1qJJiTeKo@5kdR#QMu^#0YVXqqA21oa=D6%S9~D~3L;m8{NLJpubDNEleYX!uioEj zGv}MNzu9}wT6^!=Gqd;F`bx-IJly427%z>>qaL?ixG>YWI9uD;l3ld8whkAI3-yW? zFKM&jx<(6o2D&_}6J%K}oCM?m`W2uNif0kmcktQ#Kc z8t7~9ZS2z-zm5{5!7C=t3zt+iWm_+9uHjUbU|wt0qD)hrhqS=ROxlW9rOt$(AC>xr z>)|tFbx%h-U7+eM$6lx8zV0Shv$&-$Ta#JhT%;q&)-+YkucN=^yB7 z?dpX}tynLmG6sduTv=6fRny{yuuN-JbyHm}U!M`zHESswrV2XhU!ybqABbtv|ByeS zEw}*TPw4$PJUD+sU*r?DKcRd_;aB+=!msi#gkSP6gdgQ! zsMPT<1c~r3H2x0UP*p9(lT9tRLaMyeEeiD!PKLt6BN|L=?vIfzcVgmivo~NO>bjmj zi)urb0GtTnr*W}G4LC^vOW^6iLxNxnMM3U;syaIdtQY8Xj|7y>IA>A&;AKwa>Hq>xz3B!mXs{d==|W|gF)_Sq=XS|eKEl*DKU=lL!SHB}^P7l`Q(_12G;gU9 z5ZSOXbqk!|@$HPPO~(gqBYJqYt#Nk-aOkL z3REY1`Q`E{#-c~1tXK4Aje0qrRP?e~%5?4_8FsL{XZ29k+97RL=LkU?y{U&}C}{aW zb4s7$>?sRqZxwwTAE&tX1+5B>`nIE<5_O*iJ&+(TTI-)3we?#=tRIPG$$U)3AL{Yf@QEGyO{fzw_$@H7?55I}0(%O*c80~@k0Z7?`aD=!uNQ0J z(z_6Z`GI*Xi8{ z+p;ODq*@co@ChsMcucyXdqwcUIU>ajuWBDSrQ5nM9+hTH0^f-%)dXH8#Ow=6UH{7O z_E6Za4v@GVaagkA>&_IWVd2(F3!Q$nYDe|<-O2^ZgK^h|O4W_K3#?7MmsfA!zr%Ir zvO7jDa^OIx+v`B5;Ejb_s>`)&m?T`Htgy~Bu0`zQYe(jf%o&+Ba+FnDZpU_(S8qS+ zhCL_mOrE{8zI?`ph1>0xf|W(FTDY32Pm-&df_^?)GP3`H?|gmQhU?*uBo9ln%J@4% z`e$eE&YxLL(e(!XzMZM>ZJc}LJbF@^SHC)0jhNq_B$ z6Z&hm$65+j#ajN@ZngZj-EMiV{m=dJmfyGMwfv#|#s1pudF|CVQr;+?q%WUe2+e0u z59cTMR2TG?c=W(WS`T1U7WR%c3@yv==VQ_w7*z$m6FhP75$p0j$YX&okAFOpGm zo%EKK>ZEl`@eOlE8p;VBbwkYv*3UqRX*jt)IcJ38kH^kls;`SB4JS8_KYOWmShP*0 z#-)bRsykp>=X=uPSkFJ1%93?U{Dy||hV8+4JDhl%lZp29$QyQZasHb0NT(yGE0}V_ z`Q_)IJc2yem)plTCo4zJUP{*{>&J`@wWtO9nrgQ-sQNH%gHF+_w{0Tspx*LtnCs}R zdSsGMZ^Z}Ho376%#Hx#n+E2tjA6K>8Nzq?=?c@Ddp=cd9rMta zJsq~8-yfEC!Zxq)htZRVK5z4YKaAe4>#*Ti27!2faW)#WWzyT?KaV=kI&5gYKa7R} znXrIkC3<~f!UBs)j~1tU4I2X2;GVZZ<>d-Iqs6iGI=TV2HS4fAEHYgiTwFw*Gxegg z8}Ub)0F`KLjz6UP^5L21%2;8^ykCcU?)f!&?pd0!V@2b=ZhhkLnKTz+TVsXAu>$(P zAW?W#EPqlW5zC(th>Pe?laHXcD?SLZF%yC@zC@I(k)6c2`AhlVnH7mdykl;x_~b+( zoFZKjJnb`-%jGgBSH$vDl#_{x!Yg70fWIT4W#PH|4aIS(6UQZqLR=H_>-$|6dTBS4 zucvp$ibxL+J~t2ALPVj=dx^QiFn@>NP}Yx$wVa|ETYTG{-+)Fd9=t7-`A+isw?9xJV=OjA8rRDZ7mC_`~ zzf_6GztqIj)Y9>jw415P>}IOebu(4waWgeVx|!O727z8%^CVqDbO)o2?pCzXor$)z z+Vj*#jF>gYdU~LKpGhJfC`xw&+NcGmjaqry_*frt%G$kDMhW#Y?@b1ug|@!g;H3h; zUEp?sD{(>0r|CkBuMzlqf&W`z8db~uZro`YuNC+Q0zW12bUfQK|6>C07Wn@N{BwbS zCGhVA{-eNW<2?$;Uny|Cz<DQlj~;2L-+X zSf`t^J|XZ|1>PqxjeI%F=#B8ljNZNh%z1d);iRl*1b$$w%lV2)s;S8s%}0$s1uay)csn<~Y|ooRqam;Hv~@#dw$BFYtQ>-X-uu0{;?N=OJai zBJke?ra=$7&9XCu|7vs?2X0pRPgzGhoRoEpz{U6&&z$20t`&HNz*h-;v%vQV{4-#k zAGk;p_!WU^5J08TE#b#Zo?i#%{2Y;D4qVg;JPVjPmtwqMVETMrZSqX`PbSZg0&^aI=WtTi3j+Tbb1s?lqQHqsuKXy0-zM-9f%^ph zAh6C)%KEs#cM1F@f$4*7t;s*($4&n41LnLv<#1Bg(*i$)_ms?eLf~HsOgCEQqy;`l z;8ubAfpvaT)>eVvBQSk(tT%Zkyxrva1HhctCml}8+AZ+=%3RK^0`C?05rKat@ZSV3 z!DFV*L&};WFnvC2FnJ^VUX!<@fH`lcIh>SrroczzLl1M#6?nP8!vb#?_!Gc7-IPTi zj4DhX2p?hcuv_rI=5SKh0|M_CoKN6;2j}N*fxiZ<<4;-iO=ONqi|`VY)bIzR&%w>ZxOh#M4Z4=v+>OGfR!pv^~=CVZnWiERwf#>57Z%HyMv1fiK zF!Q^CH78|l0bYPV;uB{6R$%5|3#>WXZPOVzCjL#>Gyhg#=HCviIofU0SvV&C7qMsl zSAd!SHDJxrZkx`*G4UVAp7~DzGyf@I&Cza~_@4f};J+yNF9Y*^wg7dp62}xjVUFML zwn=le+oo#6pC$OSfjK`k15tCd+a|IT#a}7-wSwOOtU20k6Sv#s-huP8Qtg8qVF0JZ1e5xY}?Cb3C+K zxR%3REHIY=!pw=G;b6NT56pHato4s}z>%k{i-FnJggHOU9l6)ON#u*~9TR}r)`SaG zp0$f5Eyq0?GPX5g=D2e0Vu@{?797G_u3ap#t!E1kVQx1lO>I*w{}+!pw2y($)udpM*y{+-KRT&WOsQ*^Pn3EE@=Tf+666`lNePlZ+bcnyN%Pt* z6vZ6hkA*Hsf;zjwoeQ);7DOS@_ca*B=0 zsCH`(*~7b?WH?lpHHU2P-DomAZLZ6wAO}lSsg3RzIv!oOwN&qE*%{iX{n4D0v_S0N zYdCZV(VVmh)$n%1q4rR7s7!meFBlHBewq`^^J9iX?X%`k{qb%;HyjHt`C`@>lnuDD zT60=mb${0aETt3};};n7XdD*>h(_)oKPkn5$-pu&F!59ds!4fbili^ho%JOH5My`% zVhheN@trw3!5@Q}*C68n1p`>+aCu*-7+>uRaR>UoHLjX?_`XO{o7JyYN9wtHb8$|f z@3I`Zn{7wro%^lDq4Rs3pd4qohIHcg(`*YO}8y-omVlZree;VIq8M-(lw{noOoio2GbGNboHf| z^z{sdFFzXE9T5SBi+_D+&-9Y>>C^! zSiiQbZ-_7^hpg)#Xdmk8wCuR@DiT}O-`{K5vDjeGn!c{iw04}4jIHnU2nu2wDI_~& z*~!>ocmDuD!X+6=eypd@8=#K!W6IA*Oq`$vI>7k*@P)D$kl5(6zzJ*=F_ht?svaDmp}a zl|HbKym|A_Jkx2hCaMhDu`*SDoBT>(84^VSLQ7x2%b zhiPp5Y#{lv4@S>|`^qe9!zlbKR7`qD`o97Xt9Khdt5(LpL-1it>wDloIST)7!KZ6K zW-7iOkHUXk@Mi$80l%Cc-?4?|=S3Z)_G#=t1Ag@={7J%IbhrE+_^U_Zn+2#;{Fh>X z+%yF}yGjw~P|OWF1M;7Pzsf>lljWyN@Gk`JlDGU2 zz8NK=LRMn`CHMo`Mux^_-cTR<9WwSh9vZbZBJ(jv%}s~O=KmrWbK|oxncGS9x|pMf zt~f0SVA<~n%`R-LsL9qYX}h@Q;+m$q>^!_+@rh2GW5LOnqOBj=RI{mr?q`(5g#RHI zU(|CFF22U#Vh+y5*E}%QiQ2^%Ju|;0F1=EFk)wh=h%PU^mm>9dL`sxPuM*|bt3Ca_Lo~U3!%$mtG~xrB{h|=~bd!dX*TLUidXG zy?~5MFCcd51*lzm0VtPV_*E{w@C%n-*gG!0fR#(H67ABf#JKb-(JsA8j7zT)?b55n zxb!N~F1<>OORo~`(yPR{^eWLVy-JKruM+LjtHikUD$y>zN{mY{q_13h;a9oz!mo1a zgsSScTxxlctU@%)e{j=aNAG0~o3+?ELeRQZJwq+% zdz%x?0cIL^I&A?pBU$&b7>>YvNkFs(Glw$+U4tF%Xg#R;p$W>40EEr#TtEf#0Ro0Q z;p}U@Imuv%H@YeMGB8n_ZIB#~2|r;I{eHrvfbO^UB)Sv8ao7*>;2N|%9>>@BcGVAb zUB14nuVa%cCDiu`D{PG3N+DeTQ6Va8fS{gh#<# zN<2bX{_m}H(ZiT63lqKP_Xu?9qK+L(*I7lnbZNiojvF)t>Sq&Op8TPamY`2XTY|o! zW*!Gi&}KYn!{z##LERuYMAg z9hQQPW*P0r(OTh?@HDIx-ru*nXU+P7F8>`JG%HP9t@K>9NELrp#ENeSE#bIT4?8z| z@2x*a;m3{L>FM!J-4Pr_RnV5vE=I@v9B)8FEK}3l-*K6@b4KqhLe1mjMrxzQ5!>ie zTe-CKwL-Abh8#9R&`@MOt)MaK{f(zDq&i2F=%o-GanX<>GG>qHtRqB?H2Nw%B=`d( zv{kote5AJOwobLf8nTc|GYK!gpdNCjQl1{M2Ce&TxJXI1r$;IW;VPxw`qHi&W9|0+ zJGZ~f=Kv!KMyM z^3YeZLFKdv=e3z!wpeh@V6J1M3eA|1wl|gkIU_ReOPB6ErBS7KCN)cMeHrHuJaMjoD;rO& zQ}&H`Vx96cI(B2lF~#b2dxL?BD%R?4PkiUR*q-sV9`&-Rqzj zF#Xiz;(T*vQ%GsJ_6@StKbGT*9t?c!2)ez9O&dGODo7UO7Zel}78DhXDLAs=?1J+O zY6=$Wp@7tk(uNk+nt1iiR@KC-E}VFEl^Q0f0iZhUt^q&o&*f9+aEtYXqm7ce;9SNbl89Cru8$Aaq>A*YW8$KgS-$Kk;QJ#rz%o(@V}PX`k{o(?8SPY26UNl-tr z(Tg;_QKLm0HBhusV?-M@HndU0LK`(Av{8dWTUza%nKR~yW7gv+>XbAEZ$g$;W$>A{ zWz`r=vjG`jBJfIqZxwh7GSB?u1inz&cSV4B6k=l;9EE1`;0Remr_47dzo*fQQ!2c=mD*}(lhZ0VAw!n?RI-e=)5`ixh_;P{igNq(> zYG(+qFxNE<%<I?Md0}Y z(>rDi_s3>u2(LkT#g;i6nB!@4IG9Nz@L705W6p&FcME(iu#P`veMI0}1g2N8dOWY4 zA>3{9a0f8Qf1ksFCkcVcYXWmVjUn-j?-TfOfu9G~X{D^!1&-tWB+Kbt<(Wzic82if zCO<{M9RG0+CuN-|@I<_SW6lWzR|$M6u#P`v^$9#AFulj486adA!Z({dTmj7S-|BEu z*6jknzu4v6Deyf4KOyj6fOT3as{pUF7>^g2UUR+8CXHYFwg9K#o?r^zY6>YFz4-Q zJWMktPX>(t3asN#sZk~x>si<5sdV+s?28R9!!OI}gAU8l^qP3GYQ!sZP=p;$u5+pR z<8;x~Iq{?FJLg8hL6hU8g{mK#RxVB)e9klFGwgb2I~+Sh*o-j>%%W!f*Mf5@{-|CM zW_|-O+qwx@bM&mfxi}{NO6(~OY?)5%nBNVoIVtOUU~ZEMbNufY{2Lrj%K9WQx1WTW zzgzG>>u}(W09dy(c7`zX_XBf&9&tGEC;-fD5n<*(1I+wq9Zt%66`0!%!p#4h;L{5u zuH!WR%&FJFv%tfanF7r5AL(#VS+M1)eJt}6{A#<{3Ll~5R^}N;uJgn8qWqj?IIrQC zZB&8y*+zu5eyq%CjvRe3V73e4lT19ljvV(FV73Ke=G^4Saqj?T{S!Xk#IxU#r{Ege z)j8o~4d?fc9A1}D*;vnnk20Kzjyz?Z3e37CJl$|A9JyDYRIjS?bxW8zu3XRhW!=se9Ku?jQZtZQw{rxCFyG(L0A}41=CoWnX4ON^ z<(V*ZT)Ce0%erk49Ku?jvNFJ|Tf!WVE0?-G@GRSLh(ph^RdY0PG{GYwJ&eVlcTO$U zE>}W&AicYi1vskkNJu}#b2+3P`g0|uA8IRI3C*cp;+4RtmwF{gh_1q&<2x6brW^_h zrj?!Ol^`>xcqPa*l^AgrGEMW*gajETO9%-v-RzOjoZ6*c38JNYojaen0(qX|l_1Y) zuLMcY_DYavipQPfOLJUUtcb;CDweo6-L{Qi{D}NOOkx2NDRP zf6SK%3Jg>dVIkvcL}=)E5E-6p=t6Fe@B8^%Gokaq-}G}2Z&4uu73q)19<%tBuP7n< zQ*ysKl&~Y0xPaT0PLdw#zEQ;5WTms+s+Cz?qsAXI7k^rj2H5 zPEzxpX5&VqgpznYr2%Gn09wI#aN^^9| zo0#`>i)l3|iXm!Rk)Mp|lxI!66Yy*LiK;hc#Of|QG?|aw-*lym2VJQ6A3OkmyWn39 zyc_)eGqsRaE#v>J;8VYLXQ^d9ZTNg?lK+U{gKDLz+v3~O;`lcL(;cjoe{Bu!~`EM5d)4{(B{IRnDu!ZSowct}fle`bkGJGz2GXARtzXSYx zsDtL)Dg|d7Ckjq2rqaT2XQrX;%o>Nr1< z&8`QUy8ttnV-FyA3HOkEuO-dQWcNHXGufP|XE#xgOP#0>3vm(ZM4q|qJ)37PCwb;_ z(wVue&vIrir>OgxPkut;=|PIrf9?OA?DY3I*=bxC9y=Pj8k>>C_4=`nZe`h!u!t%- z%C_n2bXW_<9fm|Mx3}1KX3aqV`gPXNQF^l)V&vV`0im48foFLP3BHQ<)|e0B5!%%e zO&Qa@NrdW`Rv2r_7p7*Enc%~4eVZa1>CP8~NwT}_t1!Hi1w6B2VQ>Gc_Fkm}d(t`h z#jJqu;zfcWcCBt--#gUM-q(pmRuz-FHd0%iUdmz6*j*)uA(8K4Y%Z0tbv<26yE=w+ z(c=Re_PGJl##${m*eY-}*Mn7Q*R=O8Ue^Wh7d`!bQiarelPb)`Jq(xm)Zx(OFEAEe zsHSgi&uH2Z!G}Qs&mRs2yb1*rj>9W4Q9jTHQNijTXlo}YBeYR3-BT`noWr0F43atw zsZ7OSYN}j4y8853W=wfu310WPI?@mEN;ULAB2{C84ntm#J}eqpg60OdxgKt!o7b;h zg$9>;uecwXTdomO>*JT@B3=pNU~SJJm9b9iDifV6L0nrvS?Jzgog)NYq3*D1*>CsO zs}2#kIiv;5eUqUlLd+#-6Mb2F#pNj=PDs5!#8Y(6r_f1@Xm5?p;)Rl1bUZu|)N3MD2Xb&C zw{W+$FZyECZ9QyXHHkj1KqG^Azu;c2sW77BN8eX`D)EvIgHC>MICS!#j!rOit6;;N z~{x2i_ z*uOB+i~Y|=da&O&vKsrVM>?<{d1EE*U%!<0uU$g>zg$H77usn5vkPgzubK8&U(inz zA^Oy$j=KJ>EmhYaxoT_6kJ}4cQmYDD9&O*b)jl3mini`5{%t!}GH&^5d#vRitUG*f z`?LKMTJCR8x9n@LY-zrWz`zsK(R z^D|@Z%$}E@8Jo0@*zn?r^;u#om~)Vc*iKc-8i2TE?v*oyV6}*?S7CaeFR(cz0D1$^W7zTYd6AEQX2j zPu_RzIKA#Qt>|2}y?zI2q-IC`_H@hiZd$8&&lGFK`j>?xBe&M>s6E-fdG$!$j`-4A z#0p(4w{NM&l&q0k_nf?DWdFzZr0c%DXXe=caVEqPPFV|t=GGFw(Ve+-y zKUIf1+&XN_dVd&o!%SGL34u4#`$X$!klKf9_1GTnM@BnQ$4N!MId`Y)?4yY+DNNTH zi)CDGx^6vt26JbAkRwP8fkSFYiJQ-4F-9=f76_zf&1Bpd=*dc^xz{Bxozmu$iAIJUx+G zk|=yAaYX#8UnWv>6Nz_y{B~z`Q#rBd6LiAcFS$ysB0K)$v9S{qMRz6&KTb=_PF1VX zUKE_i^AmN_MdqYCV&f)OV4HVGqUdUz8Y?JKhlrxU6NR0yVny)+H75pN0upLPPpn5b zZ%iY)iFxG1b3$_B7{`xiqST5POjLnM*QICvvFf~nQxND~#?&(t=U*zvs+Ca--L*&E zl}v+^af-rdp%I4874k6sE3&$ifPyqJS19*{BC{InTRKyy6RiW932gjrPn3!z0T#3w#VRrt@rP2v;IrY?)($ng2G2ld`G=J{eyCm{TqA z#lSkwl$8~jz8GLI9X2~d_ym*IYG97%YKN1uu8|lWVSR4OdauCr7M(|d5^%V z`8kJ^vi?nAn)Sn+2Lz_~&D!2rrwI566X%PLJY~@us+yCseuK}w=b7swjFy+S%o~n8 zWyLUvO>eMEwTNw@iZiR$WXc*$KboUwrs%qpRnxk4`OK=Zt-5SyRm;eHic{y=D?b5pUEi~6 z-6O{53;t{e>lqxT&li}%!8)k~pLIf*`L)2TlLm*Q*KXo=Y#HRH&zV^+_$z_AT^a)B zwumstKMc(AZ*e#&>;1so&Jdo3KWv#Buw(v*fi)*(-382T2;nsTu&FiinEw?BxD9z6 znA;G-Y5ZZ!Jb@kap91DKheJcD_%0gD{1#Z-(N_2f6>4RkcjQ>*1n07S2{R|(kz;LJV74jYN)yiv zM~=D!%yuNaz;ISMay{dNZAUXcW*QF7_+Wc|1(@wcnDcY5BTrdB0A?EzW)7|I!gl!s zaFvSR&Jdn!()yz#$9192V_Oi`dayDx9C^xW17`gb)_f~N<4n2jqNs5@#-{rf+zw2D zg!NAtw;|dxu3XOwVf{}*Aae+7dCE!yv;GM)$Cc|@A*}z|feb|AaXnSFYEB zWBs2YIE1;5R06a933EKIT+a$&{Wk~>VJ+9QLRkM9!6B^Wx;Ek>Snq5M7Czn%!JfG~9AkUyl4)RR)5N9FJq!A%Oo~gVD3G#fA zSAsmR^-7TEE4>m#I|&kZz6s4PA&m(M@=Uhy&MqN|m`j2TlSIrML7pdiCCKx!kT`Qm znrOu~YN3P#c?L~Nkmpk&5$nYv&s3jW$$aFwNlKhqDtf)RQ-->RhY(I18ZgWmuEs`s z^ls$igEn`TioV}zsouZMaNLpbJDcY+?6slccrwR+Yp|+Qb;!yvz>t7)xqY>87r@B$z=0;LkK@@!sNY+PYdH$ zGGE-sm>>4LRS3T%TD+UmmPPU3OgC?A<_(pTf0F5^0YZ9Z;@QVo)=$sX$9yT3Rr;9r z?JiXQ4aA`Xx1wd{Z9N10UN5kOlK);2K=+ipkRSh+u5=}Lx={5p9|M29?*2P>Sjpe# z<3A7nv{Cp^3jU?QMd%tGYxs08r%lHHdo5D?^ReF#{&vHsegK ze!>Ju{?US;M)=L(msVG4>2n?R1FSxt;Jxr z0jr>_D1U5hYb^FIxW$dd9*D(0j8pZ6=H*8VOlSCHSX(RVWL^iu(Hp=RypRR<-HDj=22Q!*-tzsH62(_#71WL z#ketvMD>_neE*U;F+zRDl!R&w8#6Va3=XyTb#z(wXQ|+NM1oe6Su!`<)}O_1MK-g3 zsCxbC)o2Io`Do|WNjV6)qFC7FL~(Cu6fPn58ZOTsPdQVGH0eyVpdVsn6$+&#-PaIR0l6qFNObhCU5hG<^+spvip7Ei8y+DskMR?< zCgjGsbc)hr)*Nej1<8}@1SPLPXNJ;VgsR)VMkS9?YgRH%>DwR2E*&F?m96d1<9Dk$ z!g0avcpWl6A@od{1V^ZzLTQ;5N>yi*1r&18K+jNDV_#?2u*&TsYP7s!VzqR&cRHjb zlU!-SwE|KpP&sf#6zWZ^xY~VyU8yTdXOj8aDzKt&Oganncs+tSP(z+e^K4P-RwyK%hcunoyOvG*bu(R7ic(LJBEx&LM#cX=zR1;qX>O}) zX`%?mI+PlgN=^fD#``%9rbzZq87B8YGUH!1oVN})Ds*Bc@Nvor|R!JRBZB<(pMWd@fbCgtZTIv=p#ue6Onl2`q zZViYg1GGt7yZSn7)^_qGyo4+tNm-t@6T4*kGnD(qcnhg7p{1^7Y2XrAXp*j38oUIe zxR*dj!Ao$YDxRjrHC0U^S0Lp20$RE{Hi!%O5;A-wWq8^e?2_qT%KLuo@>I0dix;<< zlIYrig$`rU;@Ub=oNEK3D5*}gy1#!24cXdtthbFw;Ydnm+E1}drhkEb!3S_Fo1r3= zC50lkeh)pX8wDXI)mOmXSN%)1$wzNg>Vzc zOdg^Y+)T|Dl^i2eu`L>0)6%{++cea#O6nA+e#ijHY#HiTwQZW8sR9&p@#@usT|?QL z{(%8X_(+E-0~FI~3yD{LKI)vxpet4^r>P=V`uogs#oCbE@1W}Y2dLyove~#hu(R*M zt~Ry{`!O~~dH45pT7|J>`T+>Wnu+>jy%Y7v`X{T8btmeN<%#+(i6`oh?NJl;-2io* zUnD2$Plp|f+===p<1m>%7kj%MySx}d+_A@+$@^|xX7av?OwZQu0a-<+56M@oy&Jm; zs=SZMN7ST#6&X+H_r}N*`p5Ew{;|%4etniRq5sIop|5c-A-ZJxRf^QFqv>k((&=jT z(&=jT(&=jT(&=jT(&=jT(&@B%>2$q%>2$q%>2$Sv>2&)YEtwhw_10&wUt3H2zSd=n z@YA2c-mG4VU$c5CkXgMHh*vKK)T@^QsMSmHt5z??FIF$b-dVjASgl?zziRbT{L<>B_))8uPIp!> zg+#1gnz|WZXsF%~(*42oQRz{RUXIxqqpB;N42|khPQB3Bl#Dd`Pth~>@}6}a)I+zZ zr=R5mJk+gL%Lu9#NkjOkqux0+R&{-9cC6BfUxsy(xHqp(=7Ts^Ng}Sk11SX2fLiKZ z5f!4R#6ZdrUdcK0WRsrU{ppjHd@|6k80Z?ZRDKB@wVVuUr9OnOWMuCF^u?vU&-d6{ zhDK_T&qizSC+#6Qut z45?noh&Uk{rpVD7bxRfA?6Lubdn#HroA<>eu}ob`x?$`cSTcn4`W1X`PZYh z{3P`*HD@~?ZpB>24Y%GEhi*Oov^tf{BhBinUyZo5kD@OdwpH>Dn3<}j`T(n6>!`OC z2-T~a=vo^Hj?{EV+R@tXTpMk6&T6}S?cf@%gNN{TBcvrV!}| z)I#m$RZa}v_^4Lrh!8=W*YSHAOFfskhX@>A!*5S4^*G`lB5>ou7901yEe(A^ad8DS zD%U=WKK|I&g#W@3l@aQpnOA>p{cb6tZ+_lxoR1V~S*eS-tX!$e3Rym^KbO0#TzF9T z_!TG{`ZXv4>PM`i^+9!?N<&z5v=Zcr0Nn6K0|Dw5e}HZ#Xqz^=?^)?dFe{D`JWSm- z{eo46x`zn#_6%fs!sD>FfSD4finMh&D=h8QQtr)erQqbxU5C zr{qyqOv!U;k(Rw{BQAUQ{Il#i@BH8DvUgOcDrA#Cn&!sMErkd%-x*b_=LSSrn!2qE zqWidr=iY9sS$$T_*<%TNK0JhnM)UC&noD4`Py!>d6IL33 z4diQp7UkryT7=bJL!J*F-aTytE!vs)M$MM$^3Tr3APh)r=GaR=Y3<)uoqV>OLJ{+o z9A0U{KV=of9>!v{)ye&jedl}2Mi#Ezx3tc#-9DqeW{<n5APlAL+~EX2eLxQ&f0O zMN@Krd}lfFvB0fL^N9zi_RBMJ#lR^vC7)0+q7`-W9P6(;v2HtEbP^=KR`g_9q`Mmy#!v4W8r7HP3?4ynRwTv8Gv-A39QHH?Z)<=SV*QOLHg2cIbPL{CcqQd29>c=H%0I;~W8{5- z@>uzy0&Ag)ry7g(ehT{CpR6yh-A3W{N!nkp>`@16(fRpn(jyqT4V%aq>U=TOs>Nz+ z)%jX0jaSx|SMRP)=3{}@na=rnvD)JN)#;I0Lei`x$2bzL$#SbvYZAF@gcj0Td(c$% zw&vvgk^21o3f1RtEqu1THd&v4ZQ)L{eDVGVtGC&)=9AA}`UFDek2K`(EHBW@>pobU zY`_^i%Zto0#nymxUq)=tZrgvNUI2MN5NQ(D{b=2e+S~a`nw(tLsw-RM9Fvt1!^7X) zzHrCO*f;Db=wGxwzOwPeasB$ZVf@bWh1>00<2UTtx-+?}_>b+4+mCCvkFR|=zI0)H zKP-{|%C)oVx2M{xw~>VOus=UmxCixUibWbnjY(E5eb~~mEZm{e!~Th6-Ey*yw!S~l z?{o5~^Zb72nDT7&pz>|5UFCk^^~i5=@k)ISWBMgehrNXSpVY4OdJV1ud2Wb5oWHAF zU&Z8hZO3WIIhS8uYHIgCd|fTd?~|(h{;<43>7-!?r{1vrn>+NC{G)jYS!abT)@vW^ zV!g#^XD41oi}emK!g9Mj%TcwyZrJ8S3ZvJ-CeGN~5h-3RI2*k>)L}!h24C3GPS}R5 zKQCz~Y*TNwg#87#ow!9SbK15w>F_Mt%P-fW^$4Q6 z4Y=9}yFK)XiOq2+@)G&qSiEt@`3ZZ5$2kU^joeJGG0xsNV}(CV`Tcm5LUG!Yp40N; zIPtIKNTefC7%MJ5Ju&X=y?bM+$$R%E3cv7hA~7ov8J+Pt%0?&77*~AOgL@xJj5{kf zaZ;kNBNzW?#9x(|d^a3(jGNe;u+I9sj6N$$Yg=c>rB3#9U z)QSrdiJ{O-eNS9O^Pa?*ZFHG#MDI={dJ)lcI-*G>D-wz8op`XyusvbS80|+SmZuI- z84}VLNuKsak{Ab{A{ArKC^9ZelI)u#Kj53BV4{hraI!TKPmV>duaYrGTc<(-SN-vV zF=NgJ9H(8DjGqn3kvJ|U-zAPWj|tNCi0dmP=%XYRP7FE~DUn2WD-w)vVi?VdEpdJ2 z80E=i(x^0N)#J%7Eq9WoK~gZmGEH(6G-bZB)p=u$S*Ge^b2RNVyk7Ej zcfI6t&w9y6$@P+{ebqg34E{44-5Y50|5Dpe8@2PaQJYR%TJ7ESm8o5(joM(j=@j&A z<$4vM*G;ZA_zbkp7}kx=&Jex>f7mkAYS$`=*}D!0v!n&S02jfW%LIPEz@HQN8v;K8 ztkX?dH1PNom6n|$yusw*$AbT|!@=5x0{;mQIGl$gaIuWf5%_#y9e>KYPRQ>Rc(=fN z1%684p9)-*aMPkOna7&^6FyF1D^udgQ`RiOUjRJY@Cnx#{+W(EWsyghS|v|en}AO+ ze8SA%;>c6ht%84_zy%mG$MK94_$YzT6u3p;cL;o)z#kBJyTCUIe7nFq1-?t*{Q^HD zu!XnFoabW%t{1pl;13A=?*iW=@IHYb7Wmr&|5)JH1U?!ATR1=U0yhbKp}?yIewVjb`0;4cgOGl8EKm^|cgS}zFvvcN_7KE|Ar z1-?+=VS(=uc$dJR75Hv}zbx=~1%6TBNw}+V9%#*L#vKCFn%68}EAXJe!vcR$;C~bN zM*{y$;AaJXPT&^=F2dwt&ckT}X9a$rz;_G$9|F^~YL182wr1Qa@Fsz86ZlSncMJSE zfxjT|eu2-z+ip&)QQ*Y_w+VcSz}E@9L*QEk{)E7v7Wid>|6AY@fj^B2LKuCG&CU>h z(cC*e1I&5e=WtTiLjpe{IJ+>d&N$sGdoCklL=z~>6w zCh$81zFOe-0?#+sMZ;benCl|^in*>EfH~byJDilYSKtp%b~&FB_+f#c5%@KMOH18z zPZ4+_u+C4)Y8QBuz*h@QBRJra0h^s6{B@K6_W*PL?{GLNwMLlcr>qZ^xtyH>-zV@B z0zWTs0uTBe53Q@k_$+}d1*S0vXPJBwo`rrAw#-6c&gV*pld?Jmz5pM_nbRroRRVuZ z;4cdNJ%N8GaKSV;&Y1$A1FZ9zvK9%vLf}q;=~MhU=DG-*HSsc+0dt<;<8V^eHi7Zt z)!}S}%M<3`An;uRKPvD~1%5@~vH0xE@fzf0hc3A`8h9CckOYoEYR3jDOd z^toA2C$=+$yNrE*0nGWKg+w(69-jm*1ZK`l0*@_s{qrevmoD>*MsS^*(?%-ntmT6T8Il92=I_X-_?NY;13FG$b#DnT( zp5wA=4coWlm^kRV9`IZ=71na1gO4I?p3!oji`%agCvIO(ekc!>_~UpkH8_o5)}hob z*{BkK#78&Hi6>Y5^t{FKECJSKBdfgsRO0wxsYS=c`lg3}GFom3h>W<9!P-+l%ll#kVrAIr5ZsWQ_H1X9zQgyzQ}FDuLN9 zgtZ>546XLew&(>u$K;3bLX#GG*41+Kdx2U1gsI$P%Y4a^Q%!bto&>H{l9ck-!TO&7 zS%H#kPkmahJ@v8vrw9&V)_)q9^-q}Napl@mAM1a%;1K4zLvgVF33EKITzl$c{gW=4 zLzwGGB`_UR8Lq^hIfS)bd+KBTHwX@4)_(?=^-q}Napl@mAM1aa;1CX$`7lp?g~~G? z=v+>4e<5FawCS8+rj3%!f)~EIkkU1{zSl^5lp|L%4@Vb!B&5|#Jd)FJREcSAslKeoCDDR3OikA0a`W zkMl~9=M%jWe3$&sx^FzVdvYV51=^0LOH_k54FKz z9Ez57LmQRBxJ|7EvAtWnIi!A3+`ir$XpYvKU#d5`IPWza>W9Q_e&cV1=I2iHOZ_g* z2`XTp;ZPqY7w1XCq4FBHsb@r~dbi)3L$ZC`J|BBs6D2FpBtKqpj>evPx89BY>ChF$ z?KJj5PNj)wg5q>yZ(0~2-q>#rwc>G`>TobW>?@~4ak@e|>>p>M;^pl4$rH&n{w zHhHfO>1T%H`kf2r+q~ma z?N3bcgYnQ}!L*SFR1M3FgzBI^i?rt5<{A!pF4b_6k+?qhsC;<06^27?osOC8>fMG6 zhuSF3A-j4v`ffy<>jUs;EfD)V4TpTRYPioxEJyPFfaKYL=noB=h31Cwg&F?~%9)MX!YDu8FcT8mm2wp1x->cCA{!CfnQ7*TuM}Z*@Q8_EoC}x;8jR1MPilx(0*OD05D{ z@mftCg=R~Ic>JKalb)Tkc#5AA1SX0oX^2M5>3$0+u_r}$GPWq1W-gMD@XQx6i9v>X z7w(<4YJE>{=PB(&(DthJL(rX3`09c7wO!WQj#Y!}PU&Cuj#JZWn|u1{^X62XK4;Ep z>9qC-DEH~~nWxP^&Gi%5V%>M{-ky)v+1962tHpi-w^2iHwiEEXA>@`w_Y1mHsPbaC z{BwHks*9@->7%KwkRpExYQd-YSAc)@DEx~BpY*dG{5wbC5BvCE0sot$@OKD4<^QMP|85limj$2lle`Ph zI;FYw`K;hm{3n4wZxntWb)d~g@wb70(J1_xKK^F#uNZ}2CHSQO+rj_%DEw7|Px*NQ z{D(&2-{9l_75rb1!oN@ODL?6d!_#e9Zhihl@Mn^Kz(3XSxv0zf9ur+?;@=GZWux#< z_VJ$qf7d8{8r#4d>F3zHE$bJfN4|L7?E8RC&@KH`55`1g*&uNQpE&mX}5*(m%@AAiOd(e6*p ztqw8G({$-=^ zpA`HF;BN>2L!zZ?87jKUvFFBHsHg5RgW|Bq4lvju+=_mu8?KEbDF=LYZ>8-7@O_z}UU_&0$6zER@eC-@Zq&EVfVO8mbPeA4G5 z;QwWm_>1Y~i`k~&_YdG7ccd;qVfm*qLcCG@+9vJB+F;B;GYWqH^BeA;q$FT@_PlJ-nGyA z8v0j9<&OV@f2c0cN)dHKgxL&kpuM*{A(_`3uzE`Klzzf$nqz+d$M`iC=ge!}wKDfo-P zFZw#l=gi#sr!i@~(L2;ng74od_327{Ysw8RfI(+Gg!a?KZ`1_0UhbRBkBa!8Ls>oH zQS^uB>InbSL`Cg3mknAqkGFlGO?rxt++WGRPwO?lVIPF{@xv2gT7gTthw)TKm@zbaYu*yB_ZA zDUG6sDWRz-8G+PV4wPDeU~_6M-qgNFsZkn5^C+PYh}2qJ7G{0%WSd$uHBE3^YA!#F zvIvA_*-T?IilMne(0s|#x-6xXSkb2`#XOW)8K+O1VafU_lx&Mi)=?~y_38GDlq@Ay zbTp+nD3V2dnZ-?2Esbp#XImOu8=Dtq>uMLmkmgclczsn40-Phh5Nd6j1o)Rs3l~Se`XX4VuwKzI&Xk6GJO&i8(T6_`Ob|-ZwRafOP zBveYN6|JKr9~0@qeg~m)u)>tXhRNg9TY@UzOleb!MbA^RwRm~M*Nj-huE%rDIXHC9 zVX3;;{0gN@sTFlnlHV2S>IP7^d)fi4X#`Enm}$(CINQ89TU*yubuo+^PB5WU`0{o8 zIMlyxQGX{|$UdZ5N(mSJno_5EBYf%Ajcu*jOkGR%qQxz>*)tpyd*yR0thA}tzJLW* zWoQ7tvabvem~U+j4VYJ9-Ol;1g%k4Xo}s}^*T6;n1D#gvk8}l;@1i}F`BTt^;46U3 z;7nC>Ej2IAi<|45EAYwDBvxnZ8(Ui2tOAq1U@XZtRb7;Ag>UEy!N4jf&{c5%+I8@( zjxRG>!(TwIN-0-Gjg+-diTqK;)#l4WciA~k27LkWxo(p71ytZeovBo$m)fr0_D!T5 zE7po+N-3?PeUxAuI>j6ZwGgc>rp2P0ZA)EMEeeoH!W#_V(b>iI*=o8UI|}ep-1^~^ z1TR4~kaaCBi(4>0$Y}$dPi5TjeT%Y887&&1+|u+L&To10>nwqkg z)U_;jdIllkt&Izt(MLCxqN%Pvcs}%9$@ys+ZtYpqS2sM=)i>DF-=|Ht1z9Mid=%y3 zA;-Rzc1BCo+PF$=t!rsS$Av12qem|zRF7Uth#tL!Fg>;m2lO}|*({~J7TrS`z7)?N zoNL@`Rqv{ys=2wYsWn^ITvgpv=jIu9tI=U7@J)3!ZHPPs%Q;YQ3PYRz&BX zV#SP>S}$I-sIH~05gx#o5z~p(?a$y&kCi|Ax_Y(B_fzI6%SGhc+Wx-C{GugIh{y#d)Qq)07)#4eF({pmIYo2Ht{2^}J;15CLV9ekT znPqfL{>^M7Tt?o{;_yKF39Up&jl?DsjEdJ z6UaZewG2-p*+7WHt?k*+(@E=m#Ae$2@Vw$sIlwU0(?*+GYa&KZ8-~YX$!bxoI6Wmu z7Q~u`b_jXYk1t3zkNWkRC_^;2&C5+tXIyh-h~}y%38&|Qn3L3*)@*N>%WskVeCiIn zd^e0OtU4AjbNgD{ejX+hkm8HZ#V(Pq!9M>AJb~xu4N_m%*rBz>Yl@IC#jhI}=pU%< z8tUp8QpQkrBeD!oOqB~Z4=yvN>_${ih~j3}_YQUmZrtH|LUfMVm}C^{oo7{ES*kc_ ziCxPjs1L13u2`|^TbD__CaKS>crt*Misu7Lht=8)HI|YZi#~!~B7HMy^s{&ulhm2~ z2UV-C6nWGG7iy(CK^I@&>J~O=KS3R4qcAss6^7ouRM@AWpi)v$(KoP5q#wmT{|k77 zJSMNVzkl7T_KwTwzT+*0fsnkRjs2>Dkz899!azvgx}HAO57QpHIp&yRhlJ&=qn2x~ zYPy=b`qm6}Qwi5aF&L!T6+U*JD!7X63DQ-$l{@>SJnHJ}TI`5T4yZTnW*|vD>a5Oy z2r=mk2_nsRxfLQL4-TYdPZ-Ps>Iaj1YAMenH`H#|6|_R?xT@uaTyb7cpK%hcItpMF zQD4zri%f~R7_<$mn}TVLo`ls)$?8Qk-!qZ^KKA)Ebuz+I5N1`~7#*xtMHx7NRr3zk zstMOpbETzp(Ge1;SCoJQST+CPtXdFeRa(gcy>7N?A@#PiQW#=)>f7e9dyB{JPs7fo zWapy&*d@~6!ao0+Qfe+u@2{qReczD2b6ffjuX}|o&s#S%VESx>O<4TT+~gml&Ok6I zZ>{K9(j{qn9`$FlAz^vzxbvxr3F>@irO++UzCNqE%RYhYDW&Tv`XqLV^d9WQ{^-%-sy9iBSOf!*|dXhK(M_GtyvpAEv2qgLY6nUu7}IB z?q#unueLSQxTu|0k|Y}6+dqtpE2WDox*WSidIR?PlaS54H*v9|$ycwH{7t^dE)*A2 z&4Q50ONgtEV#p=5_O@^6l2`Cf~6MEVTuC+h`l%)&K=-i2!l{fn{`x(nA7 z^1?MPi5IRZ#I3-x6K;Sy&M%M)*W8A*3*3ck_Noj~4KFlH)wpMyrE1LSdTpAg`E-5w zdv!XM8Fe}@PUDS(7pE!Y#c2wi#cA|e&f+xgd1!|4cu`P#A)+qo!P7`0-G_adTAZd# zElyLW7N;pwi_?^;#c9ga;xuKnI8B*eoTf}KPE%(0U{#tjy*N#oTAZd#ElyLW7pEyx zi_?^u#cA+s7N-F+i_-w{;xvGIaT)-%I1PT);xzch;xyPhi_-wB#c9g);xuJuahfu{ zI8B*ZoTf}KPE%$Urzz8m)0COTY0C8CG-YOSnlimOO_^Dorc5tRQ)U*YDbtJ7l$ph8 zkiJ@+2ES@?8vLroY4EESr@^mUoCd#YaT@%p#cA-X7N@~4Elz_UwKz?gvp5YTVsV-Y z_fNMh{hetD!>9+>_6*HkfY)u*)oAYTQ%|-uAe%NCWMO9yf*g^*JpQgYFRHa-Ie~NS z%`rQ(3Vm2hwW$il?B&#{)3+RjCc!hgj|9<`KGqbYv7W(dM7XrQ7mHuvvD31ri0_BE z`;$QHR(TwsyI_^Jf|`eIPepeRZwDq^g?TGEEa0&f8s6Nta+nbtsy=E%E&HD}RL@}B za0|SyZ&LH=a@h|ZHhiYVZJ+FS#L<5H&8s+s>K00l*orHow&G=>R)nv8Rg+W=P9*L0nc?<#H_JFe5h0VAN)L_u({)Tb0o7 z&S@=ARr;4%Y^{N=j;@{!T{&-D>NL~1j>e7HVjqawVmF0a%wBG;xt4BU>M=+P!tY{R zBqeZ8ShXAdo<`HF+*=ynq@qbw{RwNrJC4m|N2e-Lr9(&Dxuf}w=nx~e;O$Xc@b14~ z3-%1Qgx&1ChE*n=s@g|uLd9&KVVyS8-?I#C?rqUiLC2hs%Z^UH%TYlcBRa&0E%@E2E%>v)Uki>>L0!Yj3R*n&BsMIjHtW}n ztv#E&$e7A&3qS06LnAifucJ0$0_(u!e7w`2TOUCASMTc0*H?Q5`isu+oW1lJK?-8D zY!qIg5ksG$-n)85;ni3@Eruov{uY@?Al0xsj_-5czAs+BdIh=*bs~wa@#9Ys1wema za0=KwSN~ z0O8sPH5Y;aA>wi{H}Z0@-nKV{wgk@S3hPzR*9-WxSYf`hcs@N?IVyL~c&Kvcis*_} zYB-5%LNo+>GnxXue7jEAJw)Ipb{`=bJ{f4k{hgiaMy#W7jt;6J$x)1|buqfRf{T&% zOyDg=ie#D+e|W@&2+J2noWj@tS%_%G#{ZW>RHX~i&*yU?GEI#$j*gllM=riaa z>F+EZ{e7!@)~p}Ezy~$ljtY^bdQaw#79d1ij8?{?zNLL4mg5PDMpjVg#C+dxz|cK4 zWJJi&&j|S_w&fts47-B_UMiaB8EqQ%SfVmy#wcQBocr!rg<@2uB;b>@hhV0iIfEDR zb;b?X&4)X#Q+Y&mzVeuRln7Q2ReTjl9YOTURi)44G|=646L9nIWZ*OkpLz!Et?@6N z9Vmn*!wA=|ANhvp6hbCMTnP6>UI>5sk5dSZ&T|w(HOP6iLTDNmrwn)sVUBWycjlgQ z zldP~axjB#@C=a4hQ*VS?F;F;1nQGHhWI`r8`dc_BCN=&WFQ|I@JC!?Lry)ZL^O7#= z=^X0j2J3h#LVOjf!E(twlT{Tn=5VLWp^5SAG$jR{d^bX;qo0edTEeMl2dNxij0XkZ zO4 z3YyGp33${N1RYCATDkmSP)>7nH=gFORpdNuaT&tpXIAf-GC^!2~?K8>{!Ax#{X_ zFvp`>bKjg5Gmji&Qrz0X-6Hp1hB4%Bu!@FmWjs+ve{)(OIsA~o-x_h3IA8>-W^rEq z5wyz){DGS&aO%5gZ;iVd_0(6}yfbw`(+c1=n)yMD>3TCY zGyJ^&Z8a13CbwqdfJ^Bi)lA&7MyZ+Ja_7`7JuH&b^VLk`gqFGR-nN1@Q$1sI6uRy> zdGU4!)qOJ4IJ!wVF99%w(U*wx2Ee?UP|xz7Y^V-i$Sbyax#M!u z!#7AbJzurNeOwK$@+9Uw-r*gWd#0*zPEdm{$p2vHe>U^?aWi!ORP}sjjjvx4R@#E@?fM|?ss_3WhF45#*ZzLEuNPp|?yRm5Mh#3Q1=V)<)NoiAhl z+S5qkQ&k)yE=N)h7>DRb1m_If_9$o~Jl9Ka`a^`C?Y8?O7DwKr60M3RjTf|-d8`Q)=Bs?MKy#Gv1%WWT(wW<`q;h}-W;q#6u+!OAypls zD}Ai6A|3wGb1Jo#wpEf^F7)rc8wR!S4Ubs&e~euBuaBzx=gGOz0d?=P4qf-}xRiBo z8e#FapOjA~^0v}~5V7{hMEqvH+bWG8tG70C^|s_11kmIA7`Km_Zoe=`EAFR-o*PyTMs3?u z_v76x_l0>1DH&-R{yZIJ4vg43w?uB8T@e(1JbluQvaf@ciNbG20f}#~q*rg@4{{<_ z@A`;eS$A94z;^E zn@_KS@QBqqCvvr(9i3Vy_pn-3PsKMPfi&xFs{?};B3AB&kt;Ww$k9~${G~RNb5x%! zM?>vng`IiG&2-7Ocd(^&0T<&4eFFqT>qBmO#1?#SycaJ zJJA*P$NE^Y-dku;uYvH0)%v5z)%wfm)H=M5)vBI{LT<6t({|t7;-i;$Twuh?eJyh3 z7AF7BZ?UHH{=(&KDQ-C2MXN@?#~zR$u??q0{1Lj_nwgBOYu`D@YB%l5!D{_L^oW&S z5xLUe7M;>x9b%=cR>|9Mq1&jxQSve(R_)@*Rl7V_o0PMs5@FBAv_Ie6AZ+3c{*m*J z$S^bU=iV(sX%SneFLLW#k;^)(Y28Nkb&Y5LsZotVaSm$*i8;`{&CAxCW54@7R-TXLCp9jy!GxmIPGpg4zVgTx%?zXhhf zY_l+J*dU{zO~Y6b8}oCK8}r^=#_YtCaK2$opDBh}eAJj@*1djIMui#FeaA-AfZ{^XWAZ9$72gQZI7(rZO5FcbgC*xtpDFeuKz#h(!X(M ztFE$pEUX{}Icy;*fpZSQE~Xv3`g&m(?-Y7>!er1wxtI~#Dp?S9Z*F2ij^13(b}5IQ za`F$|Mq{>lY!qyv$Ufe7tZg{Rir6;CM{b+CT($|cPdRK7;2nZ3Ognbx`#iQ7y&c1s zGci3mV*PK9T>sbQ(!Xqzwv0LSb}VqtA=t&VW9NOqV;AS`rkOz()`Iyt5!>h1$nCQy zmwjj{Y@>*)xR-2>bJUbk&Ny`2{P=^yHe%dQPTK@I5!>ee$ZhlJLD=Sx2~-`S`2*X= zf5xHPX7C1K8#BE%r(L|^5!>Xak=x|CTsG+-=e$M>-?phe6M`I8k(9tWhi;cK+l5`w z9~K!1wq@S%i0$%vTDZCO%BBq`jgX7V?rp&O3A) z-FcI+k-676ISZ>tHOjd?yE=~8Mw=qH(RBxBqZoCqz3M+G8-<*A$Tmv7`Z2bVcXdfJ z&jkFb57v6{hnEnsbv{y96mbf-7ryla0kKE}URtIW-6ECht_Vm86uA+!+6 zRkKxc;%y$iyM>kXPUFO+-rdlM_5O><_5M<5QO5d{o0UpEYo+^r@`Py_&mCcoW~e>D zqhjoh>hko6wbHuZ{!(>uvOPUgxw5)A)^2@i*Nw4u`~IEV-}OdPvHmZ6=K^0varXb& zb8?as5(rBIA|gga1yKkAxrj<`go|8`AtG8e2_!%?5KIC@L_npAXa%XoyVYt@v{hSM z+p1MtX>FCNZMC)4T5GAbeZAH4w$_)D|L>WZXZG21P7c_bem?L2|6j;C-+kt{&pbOj zJ3D(hvt@X=Qq|^s{xrqTT^totMDXbl2yeWS^-t?x>W?YLyspbaWrY%`sXVtb)0eV%s+ zmAY9y@y_QX*G1+<>b;v)O;Co(>wR$+M_RFYkM_MsuXlKTUKA?wy(g{j@G^sA>^VEb z_BkIKabD|Goag`Oa!+3C`<;%w?d!(d51lHWVGVwptmrJo4&P{f19o4pQ2_Bxj#Gou)KfbZOE?aTW^-CL^*8K?GIAZwZreZe5{Y%`}MYGkLi}l zkMs7*53P@#OS?X!+%n1QW0nf94|^(T4N`;k;nZ}ot#|oYmEAitE%PO}jIB?*yZ%nw zCsXah?>6mG(=GEq2U_O$smthkkSU)?Zc0A;50uZ5Da-s_Z_`ZqOi5Yhe-60Jc`3{M z^MK2&Pg%y)HyK;Ft-0APQL%Y5l%-2fEFb+g?j^)O%Yf zrfz#_d&TBz=#qV9*Q+h{YGQwRxBAhgBu1zARMawL<6Lz5Yp|hiZsf_hhd> z6RMC`)?X6z8%?zD=_RIZ+fb9eluG!0Jzu#kufAgQzTHP`sKOo@oj)zU{`e+pDl9Q?qt-RIl4PTtzBt3+t=471v}fdAe)b_P(uCar~RUed@O9 zx9`6-I)A4({rcFg)3#@6`?T%T`c$7#k<%x4=VtHb#a-uh?Rsic+9<9Pd73rfEG++i z6efo16DW#ZH>Qu_Ws#$a;TOX4@5ewT(f5EQQH*m9QwMl^94RdSeiSAKSrVv+ZZD%+ z*c9Zqxgz@|-DXs6rfvUH?cn-%&f$IToo$htg8F@Ke%H2`-5;}BSyPd{+b&;`y;rn8 z;T#_b<@j2VqxV{Ezxq8chdtY(HL?1=ZeDud*RA(=Lf-cT-s5{}`-}C#8uopsHotz? zwqErwi99$SUV|#M?8$4I+^$eLj={N^-I6Frk#E+XjJdpHBTS!5_WtU7xuvCCmbqN2 zH`5j{EpAq;`L4=VFHw6^z4^6m<=d+_S7q-#*H}z?HP)rKU8Z{T9;?}RuBVrZN2+m- zU6s8{N0b|ytKR%lN^ZSEiYu_ECrA6^gN*hi8_7Evq7Bx_L`!RDYC)#BQ)A56_5ZYy z(?(7oNo8fOG>pXAZ|c_Dv#q&-_W-Wr?`%5_b*8u`+Wh4F)4UlYXO5gY@|4!83trlM z{kEsOs<&5{4PG{5TW)=|ty53VpW#(+L)*Biy3dY+y!xumFKwQ>ZP)cX&#kaq>+n{1 ziVSL<8Cq&4mYTkOx?ZXmmZBUgvah!#6m2~XXNpsM;V8FlYVG$H_ix>W_T0oYb!0Cc zk5+F{`dG!vy^BxVb`7>v`cn8XZ7Eb_a~<8Y&8umw4@zQYN=cj?Dv84~ltk(}{rlzc z{ZCvDrp8iRu%|ZGfbW5OYNw+O;{7Gaw9B?&`3CK?4t_3BOJHxrvdwCh&Zh;m5VquH(`l9=f`#z4LXAS)H2v?5e-WY| zhQBUMQRR7q@{3eFJDwAd$8+Po;(77G@yYQi@ya+}h%}H^)lPIlws76es=RRR>4odc zKb17POm2LxsY&*kDeYg4C6iBjWZtgdf=?1lrsaAf&P+ZttzV|)GNlFUwz65QT##Q|a(Z*59@mT5V9JCXHyMzYU;b-7?2)}*x8)UMn7<|pU( zuP%3d;Pd=spC<)roylpHE^Sq$9EtLnQz6pIlG6Uw%lG18jT4#hRq4Y^FQ!?AV zGjbZz-pW@hs(uNp=cyIF@riFec|AQ?EpqA6Tj7h$dc^4VvWj`pjj`Ub*n2TAQs8Gt zBDB6P=_X40OQcsnq{jLrr+z(S>Wh>biTZZwg5;(Da)9)!voq!W<&3F6pwuAmzR7vt zk`wsOPl@br@yts3M`g<9d{&mLGeIeg@ zDJ6Piex}I2o-y?WN_BCk`hL%)_le|ERm@A-WS{HJE?ANh;a3kVd6p#IR`)#_Q!nqs z5%i1nDMFBaQX;rtN($3TejP~CuIEPwNWZzjMG?!5#QR4I22egJJNBQ1E?s$E**EZ$ zE`6ssI2hvlswNR>s>!a zbvlh~8Eqf!BdM_?AJM-mz5S3LI7z4boM+djTTgcgMP^@*3T4V+OGot+p~&p(Pgjr77;@{!!|4yB!L&!Sbx8W8D4O%O^w66=S3BdcGmH_b#3#Wuiv?jS1H zzHkyxE%WG>h<1X5CY&I@4--)z(u2=0H%)$BpVUdZpr4C=!ZlA9$s4-( zbax>VD?~xX3L{xXD7!5E?MI>okt`qfXb}o9)*q#kv{UF(*%|aI0yq7&8`>Bdm;Gb9 zWhsQ5qDWSO&eixdpn=n8E)p9+At1&=3JmqV zZ;UortoQrtV*bXzM$mZl|1fqailP5|vHp8whmx`vjFIS|WOHs&%#Yr_{@vK&(e;;1n*FOI}LW5s@UXv|v|IwI)O{~dMBB2gDtA!Uv2-d$XUY2rcvF0P^=TpiaP zBCd-*L0ot1W+qDYH%`SwW#sBJ8VcIFD02D_wgrjpsH; zeKX4PI8#56Ws0p|AnQJ|LL)jke@ebCyqYyjMg$kOIzv&_jP5j+mI$fxuiFG{Rou2Ki=Xw6_ zZh5vJWwO&lffDjOFVEj2t&YEWdHx<}(|Ml1yR*}UE}B^PNxwNRx)4PZuRqVz#VeYU z=Xp840FgXT7mR44i##-)WWH3T{boDQ(}f$F=pqeGbU}uuvF1zBg%+CVq6$ryn=eHd zOK7S!U;2&G7WJ2@QIQ0Gv!_<*%O5^&7b(?Zc{0A2TRv0pIf54o{+{3;3Vu%Ti-Jd^ zVzd8of+q<+RqzhM_X~bV@HYh?9u52t6@0AV;{{(Wc&p$q2)Flo-y--I4E+yvjkr(c&Ff>3*IMqI1Zldr$+Eag1;#EM}mJM_-BG& z5&Rp$9|<0YgFWYay5RMKcMATQ;QfM!_YeHc72GcP2Ek7W{(<0U1-~fxWx?+WK6F5k z?{vWz3cf?|mj&M^_#wgH6#Ts4e+V9qPLV4&!5ajBR`6!QTLphX@I!)M6&ytei}N~0 zaHZg7g4+bI7JP}|%LLyh_=kf3Bsd$xMsW!7MzO?Eaz1q z_#PI7>s@<`d+xc*?*=^n9Fc1m}8soG`>1p@XQf`W|81a1m7U|aj?nDS3eQF zM{t+m*l~eA4?NSxN$f=wO^JLk$2rVtd^KEfpOJy)Xu*|&7Yn{j@Xdn1BlvZ&iN{y( z3s%Pm_H4oV;8`|)V%)*k@%ILE{6{;DuSN*&dqSW&R`688O9gKfe5>Hc1it|`@%ZX5 zf+M2>dt7iI@EjXI@iZHM0hr@I&S`u#O7OtZfo8Pe8G`EsuNJ&b@J_+s7raMstR%?m zSg?uNR}%%#5Ik4#8Q_FnN8+h=9p{629alJwuQ~*uJ0{R{2)_3C<}E ze2x%2Q*aB|#O$j}1Yaxodcik?YwS7_^LD%i%-{>S@3@ej*biT zLj<2Fc#hx|g0B<&FxbTGt6hR$7W}H<-+^oGIui4Cd=t#;xX)>PrA}nMul@vPjT#^D zAi*Vqrwd*rc#YuC3;w3yUkLsPY-09R?u38`2`(0V40yg>N8-=gx_T^_poyJ$c75tMaf#y$wv&#beQG!nco4kB=j^K5I?-KmH;12~K zQ6Bi2EqI>bv%u$h3X_*0?vHE4m=b4$dA-&+jjz@TURDukHVM94@Kb{S2sU~7>LbBL zm4SVX;JJd&7kriAdjx-9@b3jjs{;Q=3N918Q1DX0%fa;?6^WN1{wPAM60Kk^pDj+~ ztIrF*Y-*snP4IUFzbtqk*yQD_-qit*5L_*|QSf@fw+nt;@Gk{_BzWMoAg_sn&lX%S zcrlpnsZf~^)BOfai6vkzldGJ@SDzESO=vEg9_Viq{2jqB3;s}W&WvE$V+79?yjt+> zf}arlTd-LdUwt6B&&WT z@zn`}2hR&MlLVhBc%|UGz$P#BwFJK=_+!C?Y6Jab!F7T!75rtvy9EDM@W+A&oe}sy zNpP9qYVfah^X4UpkJV+R64St3KIb}(uNnk53C)c8f&Lu9OTfmzua<#dvw0DpVe?up z^qZW-d_}`05S8&nyTuzZU!v z*!V=B|Ez!u1osEOVe=*4VDlXS=6uIGjjtvM9(s1587Fv};IjpHf=yn&x=QdC!CwHs zY2zVYYvb7t=6Js5G`{+#;M+eFXdV*$wBTO|-U~K)`6_l!zE4fLbI$f&~FfY zJJ|U5)q{e+Dflt)2Q~&`-Y*^pa}2LIjjvu4{KKX|^DDuB2OFQhiZ2ehkKiKkhc;hg z-Y@!tIo}ee@zprNhc6Kt!E?aIr?2V+HwnG~yw~PSe4nRh5-niPceB&@>RQ2TmIj*b zf*%(AqTr9fCNH$x%>fq(?hpQ(jfZ%pjb{Lu<0*3*Tyqe7^7(;guHa>0;}hqYf;S4@ z4F1UGOMJb}_i8Zbd#}^@>MMe8xFFCxAoz!ZUl;7Pa9+OZCwQRXA>fZ~Jj7fNj{tK# zlbr_l@&u1q7HCcud^Xtl#B*+fFBH5QywB!K%=NGn%=v!aX?%5q;0?=#M)23b#;32o zFZf4-p9k-^`4V$Id;!e)zUwr&_AdB0t%2qrf(NV!>|+Ig25j>3Rg2&@!JS~G>wuRa zUTy2cMPQESZm03py@Kz&FwlHM@Xx@;r>}l5_)mi02S;qa#9aSB0CT>B+F0YOA%X|A z2bvLrr-6-6Uo8-Pp5R7smd%%#>wgoN^S#Vze07E33p)bMCc$?I{!ep2uc!2N7I#2n8L!5q&Xr}5R> zf?rx6Xg(0!dqZG9PH+v_!0% zmjwR}Z1VC|&Se4j7EG^;9^ffVUV@n8DFSmmlbps^rwA^&JkU%NTqk(7;G4lFFJIj+ z_-lgc)yM;FJjB;%R*7$eIi6oRjjw(qc=yIY^IO4x6`b?gKywV(^77RSf?pO)ufiQ{<00nl^%|Jt@vdYI z&V>bk1ZGXarhtzXJVo$Au*u6;?Sd~7ydFHn#zV~8YXg|`y3=WV^<}}=UlnNX5&W3o z7X-ftHhKA~OK@y+V5ire7Tb7;d3)u9Ii6#k##bW+7hN4_P7pjzaD(70z$P#B2?gIK zm|pog)W$=6t7etB8_e-M?KHl6M({VT2{gL}|3UD6!9zdCdHHIr;7Nk%RhPqTJj5JN z8JOd#a~jlV!HH`F%~HXa3cgwJ6JV1U>a*aN1=H&tkFoI(^Y(fT%<=r)X?*oRg7<6* zH2)NQ$kxCswkw}rQkZjSAf~i4T5hId>6RX#zV~4!0!fg`8@74xOXFXm(bjIQ=tE@;8(%MKhA3e ze<+wA?#@iT(J2k7s z95DM|;xxEcAh_n%K+`CAwcyQy?**H@&@UDIq+oiH(L@^$@nRd#55Y88p;CC}!D(>r zEcn^mf_Q!-_yfUxZfE~EPZWH#;0StszoxFAs#9@%p08u5qn|X{dRwOsMiYge{p1Qi zdBV@ZXbvW?gVB6id3{=b4kqS<(R^C*d|H0~lQDl=x^*8N~K z2ea<~UxN*f_VC|n$Npa~!-J`Z2ctQdGW?`|a>RZuk8yoqH^=KbCG+i0-y8b(@JIEe z5TCrPj3*m*KAuutGX20hMR}Rye)!nhojxCWnHMj6uyLBc*}<>ZpOGJ}7qw%bbXn5} z``7Z~WwVek_a$VXMD`{6Lc?WC<QHb$+dn)KY|cCC)Un_`);{ zZ?4H0|3%jSF!;%~JOUiIJPLfA<#AwhU#U(_1S@Ml*nEds{b5*?^C|{&UPpt?Id7e! z_4*tBXn!0{U!Nc^AM)2}87xcn{58w89pAJ(6yLL~Ps;aWYo~noS*G=6&1CR?Yp=j} zmR)u__$_Onh3`F<=i&Pu%Lh|F2OIND5%UMuKgIl^Wr~?KlfZkey$s(US)PXPH!RP= z_uH1K9p?6j+KuyVUes>OHpE=_tJCAmm}{hU>Tqbd49A1bwaPk0dDU7!rwe<7uwNwj zU}G@XitF^?^aHH_BjAV2gzD!&Yo~3Luv{bT3x$1+U^>QeJ)t&}>(U`$u1kZ#+&&b8 zxqYCz)XU~|9GLfgs>8hBjRo_5HvxQ{)t?0BGAsvk-J|$E0Vp31~%d{qxN+sjK3v%V3``lU|etF_=a@JI0wvwj1Z^&7!& z;E%3L+=x$8H@pNf>u&|K{tl<{)i=O<@JIfMS^sS?>mLUjjjvt=oA$&@5VQUzp?}3` zaNP;~HvY&zG3!47vwvy>j0Vpmp{|*Jj+Y>2eLk4=R2PiK*VnMgFZmxP^uvYzc(Bp< z`uEeO&*mk{guY7Xr-O|Kzexd8tmL1V{O=!ZLvuTBOl^Mj)T4F6M6|^)@Ok^ zp19NaYA~4gH!6Q())x!?FsH%qbHV0V<0Xh$f3nb*IgPJs!9~_TG3yry{W(tKs}*2# zJoOU9tnU!|PN%^$8(?#s^%BIar}4yieXn;KJU0dAd&_ca{O6fqw&>1usJ4r31Zd{7W!hR z!E>8nYBy>760?4y(4XuyzDj`2G1^NIv%Xg77dQ=`X9Ewn{)t(?Lg+i3##fub<~Z&p zh*^J)&~J4bU)>Ep-ufqI{k=l}6{o>H6tL-6cnMz|nQ1Hrs~Y4}c~@l^@fT+{Fp#H=4D^b?)NSF^wq zt$$+HCxpJ%X?(R5e3I1@v!2GX<9Jp$jjuL>Pqunu)^8H}Yn;YccYsf|dSce!E%f&~ z4Su@>F0*=K);}fmyPU>XuYfD8o|yHo3H=*RgJ}xe}~ZD?KF7i4P0aO#H@c@=$~>LU%dpbwR&RKzasRn zISqcd2%c~C#H`;d^dC8mukv&F_uyWFnDu?ZyuFH?2IGx@&$j-FS%19HrIYgUO|XZO`HV1+UzKg8^3gtOyX0hrHCh*>ku+3{N> zFrSYQ7n4iW`6g%g)n#Bl2O&PnYCh}ic$N>$=N-hXp+2p#<6Hym&NYPQIcN9Pe}Vb@ zf|z4|&)MsUJAQ)?9$+=Ztf79RvHR+);DJ^{Jly(u$k~1MGML&6+NQ+p=M`u7)qjJz|4+;s z-S^YW;+YxrAGps?%y|uTc09WaF1C4Trfjj@%beX;=YqL!Ph6}eDpBw3c!mmGYW)xo zwwevj?yH-?+~+4|KeswNo{a%>KcAR2)CV(mJU<2=Zu25$4fVB*-B8y^)|~9@zB&uceRX2ioa5}ix(GbZQ<%I2G1t|#&W`6r z!Q-ulnEl-B?7sRIc%s!1A4x8;y&iRT^hLoZSq(8=|0T_<&hD$fgSr1qe5}=c?CkhW z4UUi8XC|g=*_aYXIy=UP1ee*oh`ElP>g;%46wG~N;-S{hVrR#1I>6i?CZ=n|m=c?u z9luosSKGXZ+0WOV-B&*aPq!Lk_Cx&yW5@HNVD9S@(|rQUYrnIjU5y9*L*l7cGs4;N zJQ$e!z{KolxwGS#3+8?=G5fj6*?sjYnESfKta;tpas3K69mgi{*;Yf$dHt8OV~m1cLI0Du%=#&DcC?vb?sF0^ zu$mRl?kgJCy58nRJjZH&a0B6T<2f*B)BxcP6&hD$q{Gbm>e1`Q? z?d<5sf|uHOi0Qrvro=7I9_}k*cX7`O_62jlkr3MCD=d0AH_q=n!t{0 zys&e>k(f1s-P~v4e&dZoLu~B0)&bs+Kg#P4e6k;6W5@MIu(I`>m^FbN*Zg7Uej_n! z0z1yTVds7$F>3-lu6@DI{YGNe1a|ZZ$!_D(jCo9nz;5mVali3JB(fi3W5=-%%>71U z)&zE33x%Egjl`@8>}UgF=YAtGYXUp23Bb<%Mq<_kc3hW(o%@Z%tO@LBPq5zHZzN_- zU^n-txZg6WG!Iz|Q?fV%7w9v_G(Ozmb?VfgSA+>@-hxjF>fn z9qkY7+;1diO<*_Yzua$}C^W>zZtk6Nzp+ech>acX519Ln#GF@PNBaXi#YZs{vnH^c zb8XW}Y>r=YAtGYXUpkAK1CyNX(kRj`jz3?l%&%Ca|OZ zfxQfW6b~_L0=v2A$oSQv_If_>xY>A1a@=nXra~6wIkLL8#~$`aHG`_vnH^k{egY4)ey5Lu%rEf zeW}$DvnH_1ej|>1@Ri@G~=zNm(yHkHF-`$ zPw-G)c}{bS)#N+PM61bnnuo2Xx6{zmS`<%jr+L9@`Z&#)5|dXSt{0ai#O;4Q$gSdg-Cf7xV%iCinbD$;TRMmtykY5FBBQ&B`hc)%F9>)s<*Bi^rVdQ zg90Kyc$UF#FLV4tpCZtpfJoENX-vCH?|gH9P(T!Oq0`v$1P~KzN^SWRIn4$ePyaxJ z5+gtTo#tk%84zeth7`{Lr+L_F4hb|UL(&}LH1ystng#|Mlp*Cc&}rVXnnME(N|pQ^ z>NI_@U(qxu(4d@2GstO9w3@>L4a%AFI?QS2TFu}O+%9#v zTWTyym6kf(Ej1QpNJ|+DE%kZ3)R15)lp!rOBv=Y1MoSqBE%i0K)Dgi_w$>ft)`G4q z(^MR2Y>5>+&6`$pWS~KbQSL`N%|ESXXrQqrHq>bb;;Ji6M+F*NVn;a*J!wJHus~yL z<}jx@&uWf#nsK%akJcJ0`Ee-2{_rC#D6wH-3rY+|s{yFB*7GreXIsaPak9#C!LNwnmL~nqgLRe4w!{+wo3wveldrXl#j{;577f1x=#@jV-ZJ zPSa*JqXUgCvC&RLSHNj12{g8jl{n3PRx>8h*g7`GX?9snX`n$lQwvb)G{3T%u}(AI zwti!s<~^$!7ierbk8_%=m<}0(yK^~@M>$hoCu$AV)$z8i8y{HgemWtrpu}(y3RhaP z?9qHY%7-kI0t-rmJf9R;u z2cEGAc@`GLOrC`WF_ULuu`vsajk&^ko@8Sd78|p$*qDXI#w;v0=E}gcjagW1%)(-0 z78V<`upnk?$Euv?F(oB>n@Y zQusMh-<6S;@w!x{WrDtfFD(<{BkX6Ae&egqpyP68Sc8sBW0Iv*El#qG)n_cy&p6eR zq&ZPtm}D8R+LJ63^wZ_i&qTE$Ni#{8#%V!mprb(hvb31`EG?yI=faw?dJ9U;IK2g> zS*euwWKM6zo_loYlHn5)!5L{V3|5SX*CPmsp{y74%q25lsL#9sp+gY>J^eH zWg2TWIY==Y+tm_EdNz?JI(P3*L(e19l#9QpS45vQ8=C03Lz;TwuRG0sRzv-O?(+Jv z)lfg6JIx=hhT5R+^2#-r1N8AS>J1_#{=!qS)fB+oou3M;p?0b}KXm__CLe#@#oTE% z{W55_TMcc^?&6{Q-!$p1ptpPKdhM~A{?K*jCyOctrUCftF6N`G=8z1Ua;q7rHR;QF zq1Dhn)?Hp(twww3X1%^^HS}y+ciZAORx?;@j>4y{EFhjD_Cgii+mCwbH78ijkPMpB zt%ja8=x)7MSWR&T&9zoTJ=CZ-l0NYlo*uNCp)hx+dC_WUjk+tJkF91{2F*~~(J>v3 zzo<8kK4~^IRa?z5uy&VMqtzUnL354O4A+|Uc|Bw`BQp4T-fE~%-(5T(SdA{>ZrX%? z)PP|+9)I2Wq5J(boq)gYG;^$m`fc55+N_3t57?b%yVamO-mQk-rA-s{2)pz13#&nw z9U9%5(ITPgFIF=a*6!+aJ~iH$^p^5;Yi11MbGX&eSx0y6PnFeB?=!0X(9teDEw>u# zLq|Pog;MwBFIWwoDRt-PNvpvLL$`k3vKqR6Y}P$Bo&q{3VVaD;s7EbcYCI=e&BI>ER#T=mm1#AvSWUUsRHW7Xx7AQ; z)JyNDkPgV0C^hP(_fujuRa!$^#8x^GPjjqhDhyGN_72-jvKR#UAtRNAS2uC1~3%z!!S)!>uP!o$@IN^6>2&->y(iQ3e3kmH)llh0y#*0|YKWHOX}8tT*>OaBq3s%;-nJUL z`eZcJ28E}5TV!9T4XhJ#lvW*_J^m7t%lA@ zjE1&rc)H1IPIY-59~NNl0jrtfG_=o$r>Cu^(rHp-{PvR->Uh z9i9%Q!w4oiqcbRzuf_jE35&@bs$H(6vgVNiDDRBt2z_S%d47N8ZP1llR>IoXE9@WM^jtd$`u{+T35C$ za?YCDYdUM18XBDwh-*8$71xHvHk8`ct%;>5g__QAD5-WGN@eS^6%ET9o0l(8x&RSk^S}qUDRGwzajkRW)@qE$RrDN=;`KE)3{ZuW0UQ=RA{wsqH41z^+#{eK73n zK+%|>YY!yTIi(F6DQ<-mD_h!|5>0K*t*$DiB%j&b*s-*#c~x^`QyZ^1MDuE8&1aAw$a|J={))Qf;=PRSYGYjJr$KStmD!q2+`2 zGi25^@&F5RTN+xB8=jy=4JF(5rkhk9Zc>AmW^qxQlG@miSbGaMTA}o$P|>c2lEa}U zr|JUA6e@e~wrNe5*};i*-WgU5>2AlCZE`5b6j7*UPL`%?pFC7Z(RE)}t) zwAi7=^%^HN>8XP5TJL0KO=tSHHdU9};-+e3yPKR^dyqM$Yui(OWzNZMa(m25US8}q z-6+Cse(Lh_h>)C`uKiEehzMMZo~%he79^)99}z<7;p0L|Qa3Gr(lH{mSf(RIM_a@4 z_GQf-W5%NwN4w*k*5&$ekB(uuDM?XgmW?evScguT-eFtQqNe6mIQ|{TU$QWxJC|v< z>ucRPVS0CZucvaG*Sw}FTwr>CPoHEP8q@>Rj|wkn+L>+=U6Y()QPjV5eiyYaU);Q8 zWm}W2pW$3xs;!;fq>6o{8->_Ix>3~XbBF5Iwq*?+-AK&oMMg=uUFz14Y$m%A%}dOf z-O!FxGu@vJ?K`eipqbawu&T*OnqY75IB8USN1NVJ8k-ibTvFH4yc~7FaP#uTt;`Jz z7q&I6a&y?_mf$sIwy)-LkR@x=QuaAnTaz@dqNdTfJmj{q%O}@1Yfh{}QcBtF>UP1D-8I=^s6r(hO25XKwDWoEh;L;lYmX#_V|9mh|z_F9}ysmEsn?hr38)wBA6 z4Wi;QGf$r*0@RNQ9f`ZeS7gvv34J~IPtf02Iv}JbUPV*xf^cM>~U5K7g4Z93hY9R8bgo*mJU%gmr;t|^n zdh-K9v(Qoax`{rLCh6b&7|aN0TmKgN>J0wP4||NBE~j=K!2eoN-|C@1VVGG~ewGPM zBpRf2!u~Gw=h=8lY!dxQh;MCOBbGfL%Qj)7-A;Ej95mF-P!qdS^Mw>7P3Z6Cd;w4|hDbwgW|onKr!aqNW7 zM$EM|;Tmh*iVK#EZfrxhw5_Fi;b=|`EVlVugi!EkRS#vdXi@v zQb}$l^*|v0l=&y!ede&7H-oN=rwLA2nvwtlD`}Fu()bffOU6tru5IdUXfK|DzD?W8WlhUFh!?fCt!Qm)=xAzGUY~{7BEdnx^Xh_` zC=DYMrLk(1_f^Qe+}TrSS5{A}n>DYde0JsBIkh!&XU&>gQ&*Wdqi*h;S!dzaW(Gy& ztnx9+Q`xhdmQ^lZVx6=u?`Ugn!DgM;)S@C3j7Rm+Wi>4|t1&?~X;Mo?7A85I#ZM@U zTV)otQ|HyzRi81ZvUbMYIpw(J$t$4~&a9bHJGHK=ytX_DN+e9JtW=RS3na?1+*xST zd39@>+B$|EIcQ$eswzjq?FOt)aI~7fh#fz3Uv?(t;XC>}f2tzz)HKo*b zP+I%a);2&a5Lru3PV@3`f}YRGX=%loUqmcm3_00#bt@qmTMEaKqp_8jkgRf@XE$Zi;U!%WTs!6-7iawXm zTQD16tqFWawieHwufLB>luw(A#UopXmd~DBHI-=2)bd%g=AKD-)QmZ`S~qM)bqyJg zo-tK_A2XlkW+moLJ)>$a!isF2J%26*SzBI1(VVfse9tehp{UNpEPdmv6kliA@3YHm z#$xs}n5FM?%4^2q>s-vz_j%OEHSyQ6p z7+o_)e~+yx)!!3p#_I3MHRJU6l$sOucV*3Z{XMN_g8rUaQ$cQq&#SG5+Y71_XG||Y zn=Er-shfUg)r|S7_g&d|64mUebj7_=pK0pGub!HNy418DY7K7S@JQfnQ=luCClzU~b4XgVtfBn^m%=kh=xl3R;_Q}TUe#_IsyQo{S!cmKk~^TByLd6Sl1U9_Wh+I` z7JEgT^$wMHG#((ctrQkB{k%~BiRu8I_{lnuM%L4HVUpM5mEl~^TZPJiiy!uIU<)yr zk9g6DC|B>j&j@5<5OPIMEX>Df5Ss- z!M07)H-=2nNtoQWX=FXUZJT<2+g|EDMwi&r8}F)~-+0d*xRv(K!SzdX zx<#jYb#4v?F8Xg~*IMQ}d`fSw|5Wo#*I3iVD7W`;+KxpV=u_pL($8)0=H<;Du9u2b z{kuN5--c3qdW-+O=eM{Y(fu8{cj`S!8feSP`4mBFvC_p%Pxbm*p)1xUO&v3+WIGx< zR<={ID!NGM-A|_hc25gSdb)5Ajr90&?(B%S=0I)X0Si~}IHuH08)rDR%(qf`s$Qe< ztFWLz=QrcwEP7zAys@#Z$^P{4C{k)?8H7Du{tJ7){MSeHu?SaUs#_YCm?nv5sN9)# zQSc0vcY`e~oxn3lSkvCojvnDcTq?EOf@h0{n$q8d-`fR+TG`sxrk_}nrB4@OlS@BE z*wdwdWzU!XEv9Kfkp-pCGgSJ_T#{NPt2NF*(L(Ev7JmGJTR=grGp&i*ntnb0fc1FJu7_S9tjEtkh4pwOv>hU$?JzX79V$ZGA>y{fP`e!}{^jkE zPxUBLHN?~(-iG%V6rl!j{pyocn@lbGSVv!x-F4l}Azox=L0*G5VrF((*UTaDNL5ai zwtZAzmFG;A@Nq3|<3MZ*@O=_~5#g05Xjwet;Z)oV~Y?#p4&BK(5g+yF?;`1&e83)l;bj&Bjr|w(we$0j#7`N`OoY4*i&NT&Lz1>?ftioW_1zxIJ$XCxy3WM9(wfpX zJ*|(~rXyOb5o2E)qbd7RZ7T`chHG0QWE-MwD?+xS(00?U30jp`Y^(A*eP{0|*kiY! zY#oQCtU0xpvUMy>TJt>HT2lGH=1O4bs1X%FX?m{I&Xwu88ap>h&$ZdPQr&v? zb9-&6-D_*yUYmn9wM|pSD~%xld)G7A=0WLHK1{tW`k-qO$T*os?=)bTq!(< zQut=Wf7w!a)Rw|y4R5wq+*R>>`3v_A>{99p^~n7Nk$Ufudp;j&@SfPQZKK}L=(t&M z-GZ(-*8bi;)i@5ky|?P#Y~)D%Be341mv|#m_UNTmn|Ec?9!B-ci&PX)4Z&LxZArzp z9P{71vgzoSjr7=-?EkL1*R~HCy^Y4`F0B~Pr3r6YUa1zU<@jvJTpQ*)R5L!?Ft-Al zcJLyMqg0~*tyT>>C7iw(=@ZphjDXaM2WU)M3zl!tKI`D;0*o&+8fk6ty-MfP0$K=L z^0MhP6z4KTu^3)P;oFQxNAH=6D$g5~U!>yM@tk-(o*VBK&x;R^PmWKCSH|&UV00DT zR1Yd#ce5%lTpKyBa9z1fYZPe#(&-F<@>G2zrwl=aRDUHseP1>5smZUT~&$Ib8B2vol?$r_H_KC#%R7B(#0=jTYq~Mq| z0X-T)K=(!Z6t#stex*FpuU{JdTcqC^>C^AtvRH0=B*%}%XpK{g>8dD#y*n1WD01{6 zVb?otpxJ%yM#0Mu#Mv?>Qg~b%cRz<#~PcaGx&{Q;}ZL_>8`nmf?}BXiUw( zE|*oH#^w>kd@maBn_ZZ9Sp4Yt)n(9U4^Yu~p-#*h2F%Ml71sDMdbwO2$Kr!A-)j`y zN8`TN&zq93eP3P{-&hv=Y+2qFW$`P^Vw=kHt}nx_raUP`2;Io?)5-Euy!Fl~%i~P@ z7}?4BQ}Xp%7mSl-(04Lc0;4ExxYW}t)$cL@l@VH-O+Z?$&1D#+por#t?rZ|H*4#!T6F>JxjVn#mkkUkrCQZ~p(nO6RP1Nwo$>bQJcSPb~ zNfTbWhR^dYpNwXZ=E+Xa8#13Oc#+^A3w~bk@mN7#c8uT$1XrRFW=)OYTLs@K_#VME z7~LVEmOkDAK(j{h&4Rxr_@{#ZBsdE#0OvJS@F`#u z8(s(`n4ULSU}GkJ&BivUXmYZHVM8@@H2v67yPl{L(v$S7<_evV7ecE zwvCPWr#7}@z%APDt7%T-tJ4Hm;eIP?77M;g@J_+c3H~$K4gKB z5`PDCUVRE!gBLvtrUryHg9T3#JYVn%!J7o%CHN`9zXqGw@S+95ber-#8#D2lHs(Kq zIi4=3@m17ky|4ZXW=#=pe=&~%8=tNI%ipx|E%&F-Q={|CYQ1s{t0DC~0t z*yQUgy1!zMJ6?j=4osgY5&F4KLY}cKbo;k;q zxC+cK-@VUieD#3fhrzrq_uwGM{FLBd34UMj$6%8$USN+5m+EZm^b7blTmGbW8sLxp z&_gop2fMhlWA{3s{TQJiF7%(&j>Cn^7tOZImwYDhhZ7(DLNZ!UOo`+1!DU`T2C||L zP=(JL&0d0-_0z$upXD^>rC;V)<0a~ap0+>hsho@kFE9qr#~;N*%>FlkS-%l%H0H%x z-2UGv^tTHA9bj&szX9epnV9{58_fP6cN+8Zs&g<;@w|vn*1rU1{VQOj!3&JR++Gp0 z{sW=k>on#CQT3Q7|8dlJ*5`xSe_ycC`1-|3+&&Bw`r$%X7v2ZY5&C+eZv^xHLY}keLq!rB@M-Far}<}zoU{AtQ83pB;t^K! zU1#^z@4@G2yO$uIYc=%p3uE_HX(ZV0#8p;9FSg)g%_?xc^+SBB)m-H4c#$)Bq16zN zvYKx>yRYc=5WG!^kF=UUI6IDmQQk&gf|%EfUPzp7+hxN?i}r&T0^ystBXL~Y%?lBY z-MkQyx8p#eAvShj6@z&@60@JcZeEDU+i|$i5c75{0rPewWgsM|4!kG8S{kg)HMRM@t4vorpOq#lSKi zb2CDg379)KWT7P}_Z*iyT{fiL0}H+WXJpudtSKg;DK&#t3JV0Y!x{wL5Vjy_%02FK zAA_JNcVR)$wC=)!plRKO1wqrA1QvQF53RefU=dn(VL{Bru;jYjOA+(2VGCl0E2%-u zm0=5FJ|k>F%uB)+gm+Qcf|xgjEcC(~AC_J&9(v);ps)ooQ~3xDVy30?f~64ikgx?Y z(^5i%n5k6rgQXBNvXd6Xd{Wqgm}%XErRW7Sw3USgPRykO^OUd!G1G(kfrehPLhX^TAm*m91u=JqEr|Kjumv$+ z9kw96Yr_`AO#NT;nl4(e@rb!!*n*e`ge{2qh>(R|pppkm@Zzosh`ARm=A~TZc>-cC zlomJqy?H5@{5?1hn;6g&A4!w^4R{o3X*J?^-_!=D(~#S~^nrHkDe`LlLLZd=XZfsH~&jG5AdN^E3%C z<>N2vQJqND{DuUWXxm4)yeOryCpMe`S{q2rg)P#p?SIks4- zS70>tVFBg_Sq&W-yVH!e8fyKFhU!OnsT>5SlGwg^@sB}{$*9OdrHMA*dd)91vwtSo3)gHxO#uN1d=TpO+G|`?)$5&l*lF~M$(HC2d>@VGWl+ z7kvlTr~BR@j4!)31A}Q7W4#d1R_X|1`iuF}eGQ7AreByZ{Ylp(N2NB4p)q6L6?*DF zHA4SdnK5$F72A2T#_X|z7za1Cnf#a29F9}wE98HO&=({9QRs(d&`%J0I%D}5`so?; z{1R2ln)IV^+SQUl&&PSv({X$u^jkCNZxHd2elzsn$e`!rHud#~(z5)G18T5P%CqLBpoR3cGM^>M1 z`_lC;o~8m`hkkISv82^*blsJw-BBjIWE9JGoS@V$>wmgUqMz~c z{>%LcN_r5>-Z~ol%QPdz$&;SAy`q`liFj^9zNg_#EqRjq_l5pm2;ate+_z_#B_`Sh zS%2_j>fBe%dw-9OsY8c{MLNL$iw4x`TZc^+jG+@AQ0Gn5@90LVzUL8ypo7KDnZW?{&T|!+0lZ=jHl6pa7JWC3o^5PF`HF< zBt8pE@DZm`{0eC{UWSjX;;A%0ljalnIJg0c7D6coBx>gc|J?zJ3Li$TioXJPS;fC0 zr^y2n73l$qiu8a)MS4J@B0V5cksgq!NDoLds~%z#8idO)HgJ0KCh?SMoeJ0KB=2P6WT0f_*5Kq7qW0g3R90g3SG1|$OO0f~yt zfJ8-hK%yc~4@gvG2P7&o0}>V40f~w{Js?q$9gwKV3`kUD2P7&o0}>V40f~ytfJ8-h zK%ycuAW@MWkO=wf0g3Rf2PDF`9*_v%dO#w4>j8=Itp_B+w;qrP-+DkIeA9qL_|gLs z6}bV4U=afn<*&oxl$r^g0#ycs5mEojs|(wE=wV-Tv>MY>zsEK1&(goeU5F9s6dfk& zG-1$@&X)ESi&`$2zQ&l{9FkToY*^XIY7k5v7*hZP0~@1dA3tVH@(a`2M*GqWog2^e z*Ci_7!9raOufI6;qmFFIKs}6*;ZS3sZDWU9#fT{@F-F+nAi<0oYwdL9+Z%8SeX9Ho zxT;Bu>Y=VN_;Fi#TN~cVLQ^>@bc9KXJ-Xo=dUnI#pnn9Mw1F@LMT1`LGpH^YjCkj@ zG%a7!u~bn5TW7hOt(&qmbQh;zd`+`)*sM~wJ~9e#+dN~S4bIWsXbZ+Uhml|uul(ik=z8}_x$!p|LvwdcXMg>`P5xEeZxJV zl8Rd8&BlEgDrDP0hfA5x%}pt%B==}BVK&BA1P?ME$0oW(godXHx7@sQFMhY zMj4^YCZ0Y7cO&Z20y(aS3;ZlEU9Toh^@V9Isy9X?r#GsZAw+bkBpXxfd5lU>c2MX} zr8i)y~sckXd1u?I6aR&{# zT+@V3yM7#k_lLY6;=&wl5F}Jk_mw8PwrAQKw)SYTU*=`^sQ;~IjIq@Ae3k3H>$>gc zsNw?45QLidA)E)+7|Sg4Hq=&;Y+Bn>B6WhY?sob z1#&|V7x-Oi>v@_YOl>_X{`c_FyqCRX^{^ zqvKNbYPy4CnnD~vw`M$5(1LzFt$*lLj!K7Wm@b)6N{<#zw8w_Dp|kU)7#{8*3+EHo zu!4tiUx^Aae41o)FHAh}frnxH3n6Jp@s47sl{;!h58mpie__SKqdZ zf?oJ8#&?UQjsJ6cF6o4 zYUfVxPz5jci#i(c&IK}=D*iDdQVhm zt6RLSJ1_tlZ=*65(bkBzX4yRgcmB0CD`fRlTwCMXYU|ISV%1k$`)aGLEwHB6*IW!M zcb*-$>K(@(xNK`#O|0RaZN*!Qb$UeEHFv7GvTN-ueO1NgceeH2+E*`83@`Dm zam{7mtgTs^H>j#?s--lrS`gJ@7gbP7hc*OdQ`k_f%exrm-MgVoa~U|NVT0xk;H-L6 zo70ript7{vt4wdN?|z-iY2%x-yp375b@a_D z<&CJyPPZR!-2cSY$?J4$uuisy#dUuFy9R-4$G~sRxO=&j4&N9!?tjw&b{zX6L{8TX z=@;u5x-N3CL)YOvQ5CMIq3hP2Rk%JplpJ*+ZQAL{Y1GTHY4elQii5QClGEt2lU;7X zCrP7@zg?~-dAUq!nc}3UPmIq?)+YO;rxZ-u+V#n4lY_L2lGCbO+PX*u5-ES4rUL9b zL@JZg=oXTVB{C~1EqS?Oc8Kqz-E!-$^f3M)jloyA{+Up|$=i{}!;h+;V@c0b{r@9F z?U~CR$gv0ezqAWra%1uRoQBhzh~e4}DNG(;?Q$BfZStO&*O{DhyGgk?=B-Xnx+dE$ z6zNxxoc4E@mYTIMj2eBzX;bQk;u^|&CbQL&o7BjnF`HGG4H6<;D5(aM1~Z`VsmUXy*`&*!*s}((Qt(|k-~nD#Jq*s z5gKXK)>@r>10_%XgWJ6SSB>`PhVc`l{bd?r(2n*;V-W^2H+G=&RuGIG*!?(!eUnBG z^g|;D_A?^~7V^k}MZw5{{X-)M4v-@U-i;QAZa?99RQ*XGbWEj*+FhFX7*MR|%#~L{ zIu_DI$1j@roAq>jqKS@0G|_Q~COXE@M8^f1=-5FM&(kr1CeGi?afD{1!A@=T(eE*% zAJQ+kY2+4k3o-e6lso3Lg}q+zI;=QrE*E?!jxTIK9L2(Xyx>y769k_uxLk0x;8}uC z7d&6^2Ekhd|4Q)dg7*mCk{ygLLi|3~8B<~_nAhb?PUEW`f-lVpG&c%wq9q85$yz*2rd_Vw%|6wor38Z+=bewmmrRqiknyu=Jnd{G`_l7@EY8fX3ggW ze@XDS1V1PEcY^;aI3KrZO+3CjT=00orwi^7Od}lfvh=WNqg^lJF1x)h1#`?dIE}Av z5xfS^LbB#_g1;pATY{ex{5!#a6`YSpA5A=1FTvvlpDwsv@I`{@5z57Oy@;FadTju6 z%r`oXuWl852_B$f&Gmxs7yJy^`1jQ-f?pR*&+#p_F%UP~82$ie|NEWBSCKxf_tjfq z*8Ed2y>5l=C1B&$oPU@rz6|GuJ;5}8jI zOrs#OogR-`ZsQ^5ZFC-(^IGmSzG@RZ8wUy2Gzz|0@U?>P7W^pKDP+9*2!M_6={}_E&@JE8_`GEO02I6yV3|(OMIRu?5qw&>H!N-7E zQ-BT{^H9O3f_d4wg3l04H`W)}7>MbYZkQ71fZ69-r}5PW!5f8UIqo5|{!+oWfsKER zt||B%g6aPA*)|5^xi*H!!0hwqPUEXz3Vu~+zI%9}fARmY_a^XFRp;9H+UMkCVn{Xt zLQpXxD2fA*R$7p*SOan&ie}dBCtu{ zSAP{aju*2|&X=^Stq#OaheBYd!_$+5*e5;M}pm zW^QRwm=0|pZqdJ2F=OrTOULxj7X4}LDx{m*?!%S+X!=G1skw5oEUpe&Z@1zvH7_jH z1CH#6Ga)zqxkZ0jdK*tY%KkY6OryidmT3*gSf+K?#2TE-HbY3(W8=nS0|k`g9FtAxOdr4x)e?st|3OK%c z9(aqbPvU7BtK^G<|8l_b)o2XtZp$Zj>C>8o(|>%x!QvkwM{i@vpJDID8Znj%49RD( zapUVX3h>AFC7!IYO8yypBZtL!=;Ou|u}fz{Aotbjz$^8+UXs}9IV+I+Y7wv-JH(FD z5XgOfKiX{5;k~KjYy>uPU%d_3jS*s}^9_L<_v65;Z92q`^PxcQtIq?wu|Vv~#rAdm zpY7Oc(;=R!u}Xd~kYjBLyvA~fIUgY;Uk&8GdMnz<^>bp!sSM=4x*6E@ZQ}Vhop%Rv zUp)%!`ZKZP91P^XdJWk1Vd6%c&YuH0JQT#keoK71!0<4Lu}-} zF1PEStOJ)0vFo4AvlV|Fzr>Cc%FQ)#jpeio4zZCNi^Q&fZWJ71BlmSXyZ+fNIK)Qo zYm1^hhx%;8*6BlRn%Vxj`rlQa%Sq zOgXd?OdHPQqY@OJWfz<|<}HMgAPP?TOc)iU47(;e<bMWxQhN-*Q@;Raz$$U))BF*bM^_aHY2V?z!KPflnlm$sm}Iu7mG&OzD7 zMI|UZuNH!Xl5!m#TCbghl1_|DP|{PP5|orPuQ&_kx*#e+DVTC-1$Pc~X3C+2wxCan zN}%(pQ3-TrON+ChGfQf0=hD9JT&uH?Kxg)8A%V`PMJ3RgJx_3;b5&Gg>$xNtJG2E| z3XYIK=c!Q%bY}es4s=H1QUaZ;qY~(hN3`f?Zk*Bg51)bS~LIRyx8$yDtnY)lcXVyk2 zp)F{pTe~C^0`6WE6>Pr)(HzWhx2KAUd|#R$4}hL%;7x= z18YC-jpvq!k>D&3a)b}Z`HW3xtmb4c*OQjRejoSViY-eR4bG}yF~o7N5?j`IGubNInH|EIL)cy7Jt#;EC%Y9^4R;+InGL;t{IOjzI2YW3^;+YIvw_;XmHj5 zIl|-KbZl*92%571$Qft2{^P9v=^FOFBF+w>v)rd!+@tM249b+?tauwIGkbg7qfNi`;H>y@o{D?-V#~1}4M%J`oO_K$Vzx&#l-O$J3}85Hm1vk|Ih;2P zhiw)OZ?zoGV}`>vi-uK}6I!cgUyO!!%i*j(Twd2$PH1VF{WTi+D-(v$sx$j*GSwJ2&D$BHuk zOwPt-{*jlCO#LmB6Gnb;qlFoNHKJ$vb8R+NFfX;Lt+QjDGf>T6_e6fBE9lYRor;KP z=^_ys%NSu~E~%iTmNyy|DYb}tqq2v_!^BA`R-{Bs)Vz?0NHsenqS9=oh&U7~)%b*n z&1iW-#5=19QBm;Q{eO-D?64~YnwlYi+=HxiKgy`C>z2XE){2LghqbQ{(`rgfQ(8mI zqV3?)(uO01NwPPzM!jzRW@(Ok_Wb#CXU&;EYu3E-@>%5!atmwK3+B(Ct>vwSU&V^* z!MA>@V@id4`rxcl)61y~T*0kRzhvpVORiIN%Q>>$@5#U~w{dda^26OyO z`&~l#vc0BI^s_0joD6-g;KCE(M`jo3&%=4*>cuO|<`XSR?8+;`13vF_p$y=5@Nc%4 zQCD@6Z@*E|r;z`3@IN&I-+s%X`Q_ODH~3GEz<;06hwJ_M)0Fz7#6|GozPD$CE5{t>~aJ`-@s8W@2;U9=bZZQwsP0)L6%mxKRF@C$L@ zz>rCQw+3T8)BipAXIOrMLIhbqcZu{*M%+0#=?cq7SJFZ9=>^S&^8s!G|1QhVwGop4 zl;HC@*btRU2^FFa*SSK0!*>8*fl|-f^l>AmgS5{4E0O+I;6^lB6BR?4VRn)J{};hO z3F#l4X-Q(oH8;mQL!r=T7mi=R?erYGOk)3FaQsRNRxVQBRO}O#y}j+5VI8kW<(C%b zjgIY##oi7ZF|pVqvDl9>Qcc3yv(C)vaxK+U|BK8sk7-4l4QHPDgQ(K@1*})^9?)QW zxTbC?>@zp4tZiz+y?^9*PD=b-T4)yhd1#ZZ7tY0lZJF!J?cMDvc7S=4dl(kRHZUv=4du>=4du>=4du>=4du>=4du>=4du>=4 zdm0wTP8$~X1H;0Q2*bjKAH!27JxqeO*0z>f3u`LiI}4_+Z~K`W`)BvAi6eVB8b?r zUeAS!(`$>x5MP4|@8~jF8VKRlCSK2AoG&e3ACEIlqVFhNd)4Wrbu=F`c~OpuZR~IF zS<$w+yR&1KeQjtv`EZtQ9A-PqN+PCHG^m|{cMRUzv{CRV}~il+)s#Un-0 zarDG#N{@KOB}SxUiTLbxtn0JfvA*c_JCj6Vr+_KrjC}&;j9pg}9d3?7`x|rBVG-&C|JtZ+o;NfA;3uYN$pW3e5egm(@*1}y{?2v>#&YEJDB>3L}j;vF3)xabqIs3VFh7` zu9quSF=Xu8b(lf<24~rBEW00i9Y;jC4(FQ{uVfOpYV>Bj`_Ro19TSKY?GcU3Zi8&g zc7t61|8|3{#0{!$5KJ{@g3?!6Hb^=Cf@`se%Wi|*p6v#KEzxZmFJf=d*Ks*BjEt+6 z%;RTA+q!jFX7rkcl{)~}Uc2nz%Qzg5VvQun9UsU<#vR{QdL{hU3*+wXm=2@OoW5KF zQ$H3;Y4dbqc00i5v)uu{@%MLtuCz6#UfHCJv(O#VGZ`lD43l!^&LL-Mz1}Io13~td ztypBc-jcRHVK*tqU(ij`7}@O~uV=e|6vY1S31VIN1ci@eTEuY{dW1+lHMgVg18#!Y zikI%L$y1h`Y;Zok3>rKoKD*6*Z1ybHnkD7we}8lLhU;=Y7R7NEnp>ovn%hw~clwa$ zgK!M_+p$1%?a${V=6WB!QD#Tr4RFvAh9hRTM^t3HM>`sq3TSXrz;~ z+Yu&a&#tgpO3e8CJHk<~?z1pW9ChCR@Py%v`Ce{}`R2Bj5AC`<-FR=#k?I{)!aQax zOi3zjM09GucS?L!bxu{DUqCay%A4FzbDF7VTs_#>i{x`CkssuRBJ0c^k`zz7j~%Q&dBBBcz2- zM^bbdR}kp(XRS-&NV=R5m@=*#C~u-JQv-?9MWmRgQyeu?inYP{b;k_tWQuix#HCmg z=%{v$RJx79nJ%r4K;qIGf0Svxo_6Mh;LM#zbh+XqmFw8R=&`FQyhTo_`!L04BCW<= zT0IcoQ!`jS@XeuGY-jDM8>}5TzA4^uU{&q$Rk<~*>n^M4hnbVrwUy4tTV6%M=9v^bwq2fj97Jd3sUKyAsbm;_Ca5dY&qJa}0=@t1q(5=K5hR(nknP zh~7@Kj;AHO|BP6Cgqh8M*Y+OoJ?^H2cU)@RYa_(%rESNCf9cG4;umz}#|Jx)yCg%h ze;Vo357KOD15eGQ(W61^#TgR*)rhgLCPvWsPMST{*`{f%O<6ugTca18cishwg7XuJ z*_T~*c_Nb;(d%jYbD5we3YM%+BpP=l3QkXWH<=24GtFQ+8I2&mVokXpr!`#)v)2B4dxT*x94>Lwl6tBK9at zq&>4L%S%k@!s%qfF`(}N5qXJcn_ zk&f{7Z-{FxKG%cYDvMVMe5t@~0%M64@E;NQOcd0mGf&_f1%`FifCFC+0X|P){*KUy}G@Q{l-az%HHkfCC$w0x!!AIco*pA@G2}_X_-oz&{Z9 zWr2^+bGrFzvA|afe22gv6quh3~+1CFo0D)2q%zmD^uz)uPM zg24RAo8y-WJX_#}0=Ef#Be2oaSDzI48v;KgFby*~{uF_y3Cyp3PO)VtJ`w#4AvqJ+ z=~)qQVCzQUdcipbufiSwe1R7NoAiCfPdaAWyohhJc`XBW=dKGl_`Scti}A`Y;0R3n zkWPM=zz2Y5>b!jQgup)#nBPyBpA2|OVrS3rXTUDaR{{=fRtWr4Om>d*s=&qg2*Al_ z3Y-KsdHJeM;0*%v1A;Sc{SZHA>t_qFOY89(53oSOvxl)#S({40TD zckGyT9W{ksB=uRbL3t)(I7 zUV*}GCfxzv+^R52<0^cO?y9MU^q;qWj6Hl`G?*(@0|69QE)mH@m z1QsEVb5P*l2+W^qJ5H&OA`Ot_WApPUB3S( z;P~ph0zZr&13S)-1b$6mA5YF5=VXCv1zs=kJAsWpu)Qqs-2(Gz{9A0D6Q6DC{2pLu zW9spM<15;MG<;uu6UIfHKEDt+ACGyRe1^bp6?nD4HwgSGV3+;@fu9ig2LfXmWv_$A z9$mFAON+K`vE1UL;c$&Hj0T{Uhi8 zBjw^WZ2EAEzRxgyqeXv!ZRVC1bs{)soSHf}*VYzo4aZ!wTJ*QIX5G@FP6pqs8H~+F zb6sfB-^rT!wnhKe%dOvLfRAp^kUR|=H!fxYyERx1uu0!b5<7mq;5P&uW0%S3FtV*e zx3<}Vb4|ItB(Y0>7qHXkhJa&iADOa`Y^%_4jIBab4 zqk!Y97lBQCjclvXT`%%6cbYc!lEg0k(ZH^}#R11xv`=XI$;h?}-F#R9zUfON+bVQ( z(Q5E%*@f#dVy6#YGX(mq3plWa1zc(Q#E!oM*y+D3;P{%!ae_rh^5@vPzDJBp7(?<| zY+QeP4cPTJVwe7(1G%rpBYoG$h#jXiki+g7up#RUoh^YJcD;aIpCNYXyep8y_W`i$C&Z4kKal(CAh7Ej#E$dLK<=w&fn9$f zcKZA}ko(%MziD4DIRv>&hkgu<9QO8sUAq%=?m$SE2XfrI0at1<#y+sAE0tUr$fNCx z+w0)^h-G`w*2K7_Wk`l{Uq5bkZH*;Qz#%qrV+YT*b-CaWyE%mOm}_fdmscn^cJN$V z&k`JBBR6*NTw5;?9AY;=Q~BuHyzFwEV_?z_UUdZg-M^5ZZ8Ko04N}xY7O??andf(5l-5IARc1-OvSjma*!l z&zfV-3hlgoSD!FC*azf8Yk8C_D?@muDF}Z#oWh1VeGiK?RW$ z+HjkV3S!Dag6d$O2yL&;M&WV0D{Q9G?%edK1SREMAKF!$gOZ*rC4nt3VnuO84;rgVltzQI_K*j0+$-ZYO2Cn`@W2r{9LHI8 zDA1g8Zt)il&XNNjo*|u+u*GB2l)$IG45RQD_sY4&Uo<>pIb8Y2J+?u5I?hT1$JlUr zIm-;}AH#8+HHIS1Dd!e{(cmmFa9$WL9cOic{VeYB8fDfJG9_nefjuwoosX@VJtW6j zS18e(%Vku6orQ!6nnN22GlDn=oD~t)T->7_ksrCJVDBs^;2{Ldm7%wW))F|P;@&Q7 z*&fkQW~(f;1ZA($f;P)?LQ7dJe>Bh%t_idRbtR5y_i4+vo_RfO&Gut7`Qr)md0OOm zU`7=EDN^tioA|;lMV9_eQ$R@jPCkf9`Jg(G5BGg-214W;%Se3M*LIOuQ<8M8oh2gv zI$GA0lt=1IMnr2(#zcQ*lrd&xU64RpJ*Fg+QkyBU!`11qv`EcnV5QY>2F}scviX@S z)iWsu7QDhAsIz1yDfLe>2^FR-GBzE==p(Wezv+8JdraLO(i~HHV2|mns3j(2m8raZ z?wr}e9@7cxA=qPjYLil5(1Y07V|r0cgr_0~o~_dYXI5T)bR(q1c4y$1TaLV%y3;c8 zD;!^3Ssg#qewPsPJ)sNdV3ol1E0!2Zx1BSc{*=Dv$k=n%+|MOkN+_=g1w~@sodod@ z!QZvo#Jj8|e|ic(59^(ekH9})@cArfKKS1nfqzj7zXkjkN8tAeKGzpFfnRJFvaac+ z{!-`)}Ue-ixTz&{K8FIv7^cS!w@ zje%qXtECJ4S1g~a8V1RqE%>}QI~i-wZT7;>RT+ci*9$)H72gg1Vav}{-nA+G-+}+~ z2>hKX{6$#Oj&IRw1Zy9u&j$scUHKmH7mUDvNbs?QR{YufYRh*+S*HK2;17bo75tA| zK38rGlAq%$0dm&oN6v>m|5gA57bW>qoDlJE!CxLW-K_u!E=uy}J0arh@%J|H_qGBc zxG2d_Iw9hxt2lcZKFA1p*_#>E4jElDtlXJ&2qJslQruZxE!w43jQxLw^h=DCJTS&?|EW< zkaHErXHFRhY3x1dIo_xh$wjcXRoB?EvblC?a^=OiZxbRkfjpcYJz(_O31^rRjxdoukz&K0+lZh&rt>P5Kl1*BgeDVsL1ggH9B%USB;4r&r@R~$7iXc z$nn{#SRU71*wBE74SB4XmD^Zb4ekByohrtfj{OIEzo^Hi^m=S+j?`mQbEF=dnj`ht z)EueDrshaJHZ@1;v8g#yk4?>ydTeTr)MHa~q#mJ0q#kh`sYe_~>Ji70dc<+09&sG0 zM;u4$v8mbAV_36I%{8@kl@~Uwgy$1oxyHtKF-T)Y1s;7Ou^lT0_25< zAI4##`~jBgd)UNdg!wV${Q~=#Ir5bE5{`1rQCt;tc5T_9VnP8Ua2dfe9?akUH%`$R znZta{WcoyBNiI~MXIp7r!TQcF8qdoqSl6``<{gQ2ygkgxnOKE{3pXRVM0pPrO|7d^ zZAq?FTaqi)mgGvcCAm^2|k}IVpxl&_EuGCnPE7g|dN{uDCQf*1DR9liOHJ0Q` zwI#VyYe^1!Ye^2sT9N~DmgE49B{=|XNe+8$Ne+8hlEXHzBnPZ5$(0&Qa;4UiT&b}n zS86TEl^RQOrPh*Msj(ziYAwl?8cTAe){wl3b~=Bv)!J$svDj zNe+8$Ne+8$Ne+8$Ne+8$Ne+8$Ne+8$Ne+8$Ne+8jlEY40k}C}?$w4A4$rbO!lSod> zc>GY^wPk(B27NW>A_#`QBJyl~g07bkv%Rb)f3epW_mXR1LtOFNZS2OyV>k44_I9uB z+*E(H5eG+cZ*{ku)i{H;1V?f2^39xgILozYgk-wcbo9Y8n@ijtAfjs>9&B9Hv952U z;t1Ae6U^awXDck!2cjKo+P1E9Dgr@tO^|g|5ky^`q6tLXd)hY`ds;fb;AoO=O!>SE z>L_oLSlaMWazrpORWLnOa7Lq>81#_rW0bST}*!4Y~!U&bzj7Bu$0M(h>ojmi6mNZaxKLPWsF8WF*X6qMn04V&sV zydz*!nFpVNA#_BVm$9a~Qe(5)WZSdbWbgBKWNfmlaY?T0Y}?RlMqzN2p=HvW0Sm5Z zCG%B~SEh%FD*hvG)mh2*A@XpwoEDwcYW_%etNGD4y_&~dR&1&{gX4mrJL}=aw#Y!r zYIT1*yVd=ocXfKN&d_xs+R@j(x!ZJdjnaE_<|~Bl%|-tQukl!e8C@!{qV=^vUv@H5 zvRcirWVf0p!&qZ_J!4kS#_YilRA9&EcO|C2ySqAR2zFW57T!m%~V*4sd}U9-_l^H$~%uLoWHZY~9?r{-Um)b-kwL#W5HDecNi}CIwYP6c)g>YZd0S8W=C+P4=wyPKA_MKJwOw2ByuwtK zh7k657(oX|&DK6!Etp?y;Uf}I`g+nR5lM#e!QSg$uVZ4<-=*6TU|+{mif+!qL^AGJ z@hq`peV3jCH+S@z3O_bvq>V22c>S@RO#)Z{h*zfS@Z8ivKj{{E_*MxYV7aJ%q-Ezs|IRp&b+FQzFx%1o3fP1tj-Fb%kr%7 zUC-;zI4f+?^SE9HYJ{1<4N~3n-2wXY)hUk+AiBzRX7zPW8o?2Jz8eZADmX$^uS+yF zhn`?`$#KCKrM90AH(`@uZ{bFtj*f3G7i-%)`rBup9W*W9=!I*7o^~0Z)zTpwrU!mpo^*E&1lRu zS#HeRW8M}2-QOD{I=0kqhLhEb{Yg$XA3|+ZzsVVHwh!MQtTb+Kesp!nX3E;(_h-Ecjp_OucHn2XbIn$!dKu|-TW6_7pZCgYskI% zsoEo(M@sicl3RDAGjobR&v7=qt6@DmucLhEnNYHOw9xvY&*Voe!RNNB+b&n<#@JTN za=lY3hmu9P8z?(Z%XY=~OgIzB zb31wbR(%Z1^0~`zuh=v6!TsM^cn4w+KQOcqmf#_efBD(v&;EI&G(Pr(>#>h=K6TKiuOg5 z`o8qkCmk7zq(12-9*3z<`ZJVTen{;0fbkFNVt4`WEgze;Awr*m!uJm!J{p1S9 zSLJrPdeO%<;jyYdH3RF1_FIeare10XX?=e5k-EEU?yW)(Ys`?t z1wl&Y9J5_+(@73|ZD`?O5?a*{E}FS`=8~BWGZzjlS~(v!@E3cF2a20Y)>DI;o0l}- zKhOv*_TIi>=w5sFlETG>mhD-#eAu<;zM;A9=DmXr_NtM|@aR!GTf83^u{0{}OD6_ADO!CB}Av8H0= zv$T0P@@W{@ixihO->maoTFBV{L@ie4n|!Kb%LjHpee=(%2bqt_W63~nYkbwB{Kbcs z4JNwcs}|=k0%FeNjwG*bM9wN!KP74N=Jm?-vE?%{$LYM6H@^${C3W7*n{U;5FE3=Q z$@{_qn|r)^@Lf;e`m-?a#(`0-^z*PZ|B|7G>GvJ_#CMi`x_(Mwmy<2ivIfWobl+q> zG@u@0x^5e6IU5Qod2M6kKs|cjLRY87EGg5{Ez-lI#lqL8tsWEZ)T`KVuSRS&YLe z-YLtbUowQN1j@K?N_{r{)=YUoxS)>8w&kH#%K zJU6rhZB=X37HoTQ)Pv(b@XiEkSKZ+B0QK^T#*_Vmf_m8GVo5$ zo|jBLkM|)qze^d%`g375fIaUfud?LoSTlS^lUsR=#FSy%HK}p@ zpuoiS$LdnjoF2q&Uz>VfYY?|Jb~z#|6a0bm_aKEwj?>;8j~x059dgX#Jtv1ILg0_% z)AWI{KHKT7Qn!rtsX5$FMv%sx8PfP(Bn>dmO-uq$T7K<`V-D4e6^xA) zj*S(8H8z$%E|ypP@{2FW^2a8;fm}FBK-V!ftN-I>%Q;jsuCr z-l&#N?~JHYos*b= z*bgN}#V^DD%LyM_edctYiKE2(+1CnQP82gHF~*!Zjb}oV_=s*y{603)n4jao8B7$g zr|J|FW%28NtCM@*`T_JPbc*zH{RC%Ccr=kX4=195jVe&HEPkyy_pVqGn&XO>QAHUm z=4OmLCa__+1U_gIh!svuBy`u!pv5Cdq~Lw&YIhE!^)HV$(}|_XbV5m>xrb0ZYE;Rn zMa6jXlcNtXttM2gFrKfyz2G;-3B}k%k(#S%xxN?AFU~C)bxi*B{C8F0{XyPD70)+m zwkQ|F+;V0&T(IYvOvA$w_Z=5HI=?-efhMs4%Tbb)C z@^7d}_dQdTi58?5_^~M-kv7V?yYWNXNQD>|(uVhnQ({PgSDf(?uQ(HoSDcB?D^6+X z6=zb!D^8j8igOqj5xz)A`{^w=T>3D$%edQfnZ@AtTv{=38O7kvdl#P^{OAtZMJyK?OfIIwIk@K#KDj&qB^`viVa;Kv329k9vQSAP+B48HDl@+ksO z6PUlhzQ*cIY;Bk(X97EYssoO%779EAFCiW00)bZv+yiXV_to_Rzf)lTu=rZ51Mvo1 zZ+n1U`uhV8JR1po8(uy;&OU)368Oi!CVgMMAn?lq^LMv9tq#OahyMn4>5nUN9A8Zo z_!wZvIU=x+%b}A`6SxA{QRBeDKLM%dA-$v*m+^0#~qjc%K^t%uL%6Q;QSgF1jqlYz!OSB`3!+8 z1-?Y!E`e_XHo9RP3H+eIKNtAd0`pgr@37?}J_&O%Lh?mmr{^eK^S2l zg!oK>mk8V;@H+&4zrddr_z8hu75MmxVP0<$c$vWK1%9W%_W--HJS^~20{>Cq($bJW zN8l!bdj!5+;78;0M{+j4r zw!Flyyk`KrveX0|SjiW7soF{DQ^hb(+8z z0GqPF`O%u5m)N0moN=5cu)wA?I0vj{uuAalJb!#1jPOC)FJ`U*bla@3Fux-+2KC-Zcb1 zUvQ?J9P(!iycF1^@2krNUMDcWN#102Aa*)z0(LrFA8>qilfds1oXs;r{w{$(0Bq97 zI#b}!3d|3AH(MQu@38goWnibnj{=Ubo)-AvDIwRvzX&|(RF@a7eFE1AyjWm< z729QXBkr@hEeCeGZ3#HO>JhkKa4wq}^1B7T1=ytTs}BnNMS&j{n4g1QY4ss~yVd9G zz)qjv1RSi-1^)hNA?G=P|0M93(?iZFz$PzWohxvK!2DFQ*Xlz|U{!#SYUoExYg=FY%Mt__W?VPN?#8+zWTPnpE)zk_v-@x zSm56aTsX_+<*Q=^K22cy>@fQHDh9pQYTa72CGq!IT!{VWEq*gOapdXrDFAl*j1u~c z1@6EfTJxy%9|Ptl%Rid*kEXmwlMbJYIsN$z&DCcDI8zyMs~vD~YZ9D`rFtO8B`c6) z3J>HMMu8mNCy>t-^0S3p>Ypb#vfX_lm-?3r`H8@;T(aJB1&8hUw{VW8evT%uVxa@u z!s&peXi!&JvITNX!*)JtQJ8YbtyX>>_M0uP z#@_YAM&K?hUm+NaD24`*vug#dnGg+4aayTH0?ODS3<)vUI|Tq7}+bK;TW%kSE3AD z=f8-pEAPv|uDq`R8xHP0aoy|1G5I5TB{Ur4mC*Fzk-ZWcj;|_^{#7=8Vzx0tvIf}c zQy*~Pu?%>-rg%wWELjH!T*-v9|krYUp)i-Hp?e=>HiAYmG}98gXgrs9K)=CV#ntN%<*%84F{g{ zfX(>wlEjWrFA9!d9&mg$518`;(X z-Gbj2aNsc!_}!LI?D)3`{+@sXFWSJjSw6Aj^Zkn}@BIPC*UTKfjU|7Ey_q*Wjqxah zA^8k8Za#Sp*v%)zctpUE{4+Lg4w-;{$)Ar_8t;yISX{%OWO-WLG7aZP-(>Eaoasj(BOMHP%=ZAsZS0(XqoD!dFITHgpyo3T@ujO8nc)I1#Lxqv! zz6sckN8*oK&elKVk7tUwZe@lUN>Ai#71tsd%7{jvN{g2ksI%xZcHr@9AYEKbqd&x zDPosSC^z0c-I%Hu9AYEK7zcJ^irA$S%8hqVH>R2ehuB>=TY=qmlh~yb%8hqVH>NfU z4zasFb_2UHMeNcE%Gu5;gHE{YYKs?h4J*0jF zM+{>E&N=$Xc}Qj40d5e4Kh#+!ozVN~(}p6wpQ1XbkMVx$JgxE`T1ap?;Zp?R>l9Ts zDJnV3T)hMb6Z*_32Ze`9G946^r4?tPU@Uv+MU~HAsE?39=jl-iF0P{>5nfcGb4gSJ zow?Q#9O!&vR05q(k4m63Q#QU=SwC~2FjE#1=**Nu$z15nl!XL3Gi4!x&aBn(_)x}p z^POvT782-O8s$J|u8;%=IQKS!DGSen&f}sI=*&4$aG*2(O9^y7FDik~MUYGmQl1Z;OQI6!JT)qT&TolI zpmSYR0-f_9IVMaQIu}PJ(3!a(8*-p9a~Bfm%-n?pIxmVy_^as4r6lm9e4I-ek~x}V zB+@Tr3}?nYY*K>s1sO+NMvn0Rhy`Xw4wHS28w9Q-<6f!8sT=3Fk+l~0CUKieQO;K* zudc&!oPWjw&EeQfPv;_AUOv@~dzm>smc!Y^cyVS4qrpD0*YkMXn}Eo4&Sz~p?DwYZ z>H6@Fi-Em7?y+a5bN*yG>@jigIBXO6iw5UQk^KxdK(M9u(J-40j=)hD_t0^5KcyrL z^_HVG@yqYUoY13oy3WfjhqJm#hwT~-?Uuupp5bsDMnj+FgdV=r%l;0_ z;T6rK!@d{|cUlftDTc%G6AhoS9A4uLhy67gzHT|CSall?$4@l;!g3TjY81K=y@_vM z)ZdY8USmvdNHcxf28Xatr;nwrH7!UrA>@P+yH{G6X01jW64Fr_O<-p}$(dKlcwQuO z81o^{t#yjULLnAq7E)PqAxqR<=Jx<$?w>~rk!`Z5}mX1YC z)P#0=MEV&nEo&+@{S+6`4(H^(ednIh+t&j_{pyT$?Q6DfXo16zc85E*tnYHTZOxjV z_Ws}qR^2zW_XdXMQmar85T}XN(GD7I65Q&bMQN?0rNh^(j!tcDEp!>m)Wa^MDYElu zL9~LkC}X2bvMkUr_R@v3vp4kfzP)#CUuWp*{SE!R&ss2VemO&H;a63;_Vd1Oz41nj z+12}?o_K!{%(qJ6gB&%Hi|3TUbspEkx{sv9Rb=3oTaH}YyVEl9D;!^}^Bq6aewPp) zw%2Zo_>~gVZ&+dor`wf<)1T7$Rz}RC-!O|P8p_3?{n|}SxYoZV6Tc!np-rUERq==3 zfd5Xx=RL{i-hh9%;ByW7)i>ZjDEM4wzYPAyivbW^)s~c%RB3`Qu%sLB0onzc~ke)bib3pX8q|_*?XC@|QRvxLkP-f}a{Bzf15ZgIIh%e(`71&s3kc3jRj$YrszpGW`bx|EnO5 zPhSq}uMJ!p&x`q!Z=mmdE5?`AXQd?-L(ch=;SrJk77X~&XyoQr9i=MFPCvhKe3;-0 z!Z@UJH7hkG6yw1U*x*I zh~FzzCof#tvAMk`qy2IIn5rcsBTH4iwtH(IwSi&RTgPWVj{$E-%zC;V#iDBGHG$>8 zP~?n}KZ%|eREJ(s!JAm=T>5!sWv0>xF|mY|-rkpN@9F4ThdA^2 zU(|UJm;EZQdo!wh860h-_wyKiBOUV?P+tk>Fr#>!NJjJG(%AF ze8|VEy1Q5k_X)faimoz-A!ol?cE1_T@}7*%@(2_+tvxkrkCNR zSxb1Bp=Ees$dC%eJHqo)l95*hv=Jt#letwTzs6B`!SFnB^@wlBSc-Fms**8Kcg6PJ z>b}kvW8NCf$g$yhES6WmF0g26ZBt8iLu2)lmKBW`HdWWQthjguK5EJww`keQ#ue4G zhdtNC&rz{q&Tn2>*`VUXL{?tdtYE!1=$Nug##l0swUwrJvZ;1Ob!7vJfd?O{Nr#bh zMmiIQfrdYGLAu6ava`>|L%2}qWY9rk2dVJ_EC{>;RB83fhL)PzRf|x;%P&MFs1#vx z(X#5s3zw}-V=r2^Vr3<4xi5o?(RAt>Dp%A)x2QB(*|c&|jmk+8*HtcE)Nrv%q=?C0 z)~Iq*#MMZ81yadVxwiY%wD)(cZBMrKv~6z3WAwEu){n-R(BIXuPUWrX>grTpEU&j? z!oja@weiI8L^d3hc1lq)0jab9jq%T}P-XXE_X zzoJ@m!^1~$nAh2bXZtacpb@we=g#4YzjY^?!#}wb%QZPC%fqc(8_v$j)xezl z7L2&ObzNK6bhaZ#XJ2j)b8;rGL(2JGpyZVIk(gQ+rCt)fpwwGlS&wZ~l6Xauc-@L5 zw(ZR;v0cy2h7~JkVYhL`%Gua;B&)H#qDk*M>&V?)!|j$8%}cTCN@5$^Q{K2r?@vfp zF094ru{~2Omp0ba5-qE(Y-nh_i10*=Sk0TZsIG~E>5FRh{-jkrYDliAy|AVcYQ^>} zUDZe>S5`Jrn+u!GepO`?wYmt0++#NfyNm7qlFFvJIJ^{x+^?=|nupzGIOP8F%BHih zYr!G+t(8q@W7md5?$=Z{&Btyn4zZ8znb|Z;>v3k&Y`ve`G)M2}H_g@i^P1-A{RK^D z>3wz6*?PaQX};bsZmME3GghpuL$aIdk{8xjUP4JDBrWw9)ht@2#=QfpaNFbgzN5N( zYq-Mu=KNi?)xxQMorT%KAiy0nr z(%;tEv97MC{YuNwMU!HXujsHkF~JVbEGw#4G#OcN zgs6=?xTvODMCl_$Z7@+6MdNsg$n{vO+52}>_TUha?R~RX24`sq;W`MDE*lLYT&sok zRxe8HnfjW(Ibi}CLf8gjkbs5|wrZhEfKr`6OW&O8h9y{(+mzjryaCe>1-~a=61Rx*9NsK5^K)5BZKUo46;vUkUgYj zbt|S#;}VCj>%B?t=wp#18ej}{P1Wn?kyxYGtCW@Hb1G6}mf-P1Pz!y*6#>~RzNigu zMKMtYk=dTBo{QyXJBx`qUiYw*)peOCs~wrdQ2?dNYr$o}(CBm|8_o zGkr-viydwpp~EB_8uSlc!X9eQ+nOP*+cL<0oF*0fHxJ^n-35=&ofGa5G<$w@M#H~x(>%r4ZKM3w^!dG0g zQe%R*0{9k%{W?4+?cplF#*mEkJEqDMh91`DHni46*-18X6S_1Kg~w3seOTwK=7>0Q z2EVZh$I|e(1$+-8H4f|H3dWS_v8Kj6J~d@jgx5gOv=Qo*p%D_YJwE;|`{U!UIr>FP zcrTWIYj)kRk#gC=m)2pknB|0?VDzKlvW1LRW6qv7Ty5K#l69{8+As?fOUri6ClXn| zS-2pfU)2sR&ew7ndw0_W&~ok zTVQSWTj0y41-iq>?|iY)B97U~ao@MK-Q3q2$j&V|spph!VD+iu>9`*W*6q=I5mquk zx(O$dXnc0-cB6VaFU!-%M)h2tcU>7ixs>E$)JbADp*6F=pt$-unyU5crxD6%8IshIWIsnceZ5#j>V;>vV z0dQ_B4Q6~)I}FXSjzQI~bcd)){hQ=W8am+InpV%GD@^0kRH?sMm!`iuJhZcVusHdv zK{_a<`%}lugUjL5;64)Hk>k9on+>xZOq)O4sz#lf@{D?MMqTbxQ=%G@adXJH{?~`q zuKl}E7pI`^cHL7HZ}r|E>r$rftP|uM>&O(Yl2Jo>ZRJCs3sNw$ajmT59p5{6__d*G zxW%pgqq^$g;cpJ@-yL676W<5PT+}1VzIiS+*TJKhnvy*DT&+0J{f=5u=W*AYE9fW z{z>nYgSq=B;gjR{EF8LjO3kV&RXJ2Mg`Ayx?w``Ws$SLaugR^?u7f$nDx24(MHrTaa*C#CtZ_CDVj|An>3k*wBvjBpYGiS$FIB7HHbg^ zP|nmNHB*u^m(OgPd0^FrUL3td?TNqV<3(&?+$P_)M)w+1zd3CyXTCJ_TdyXU9Lm^U zW1l=Y>90eR`%86CoZ5fi%umcvyU4kBlG=4&(HW@0)4qGKLf6d9nt`2rl6QKi)UZBV z)q5I-mfx8iXgb6;UY@`2P}AV5nX3j8O(h#l%14IIM~gQNuoVstCT^REQ90DPs*s$Q zHr5>8b^JGm8V4_EDr{r=jkg~>{K$|8_sR$F$U|$REpXh3o^#QwQ@fjAJ*E5NS5NI$ z80n{WcMP!v`TeubdwAfI!KwX}PVJt7?J3<_pPv+E;SQ->8qnh*BvMvz53O$qc3~4XteJ618swszdC+&{ef|# zTV9G*#r8W#R~0{30dpYnXP2Q5pcf5XuqUVWz^WBqqKkOf(2Btuo?WbP-VFAl$Kl-Q;Ik{d zPlM0n^5?Mrz}XE-z2Cdbd%pEQKK*QiH}?6B>-YY~Q{z8bxF!KvcpO`&?ov&-&b2WFt2(XY{?FFJe#bvCtoa{nb2 zvCYM&Tv8d^Tz<-onCa;}HyjU~M<@3mShdnyInXim(IcOJ_Te15H?EpeJF{-)!kP6m zqjSN3!d0%B3z*KN$e6DR=7TDX?ploQs$g`-SMATQ#R!;!xoGE}MT3|}53Bg1I~VP) z9lNjS7egOWRVk%?X6Rd}bM)GQWrIu5;x!lx4HyecF&3smW26xDq(Y1X^f`=K^f|Pn z?jg8VvgagjoAxBwaZ}PIT~6;KLvdRpwU||)*PUeOGGW9|M(N7Y-X2ExU-k6}WyK8O z&S4I&XQMaTUb=YZ;$xnVkK15+Xd!wg;`DeNKl;F`h3GYKbPdMK8yRCpL0#eG{yNNJ z@eK)ybkL7m&cV(f9P8d!o^SjQax%Mj-)9XnID zW5etA%lKw*HBLnjGBp+ErdtI$x|o-Oyk&cp;XJHoQgR>L)jU*n@P|RpKM!*L zEpj$%Ip)k-uEC1vG`%9q3)WA0di_)rtecK{8`UF>J>iv)GsU51Ca!DY; z`XZ0(wW=veDbs6?sws6^b})D7J@<~SnsR|Yx_`#83Mp~j^77PGRa53cTBuV;T02qzdrU%>NO$Xcl(3OBR zx9O*Cc}>r>z0g%P!1Daha+19kPO`UZ=iPMc-2->oe0uXgs|>xc7ugH@oqehk`mcrl zcnquU>%Nh@Z~n5_1wK%rtL8=6OF17ZP`)HZ&U0 z+#V^8`k3>sO>-O0hn+UAIn|A{AH-ePm>S1d;8vH*QseOG$)(v|va>2uA4N8<5qnu~ zel2FwyC%lWWE@|f*tng{i|ykAznEcMRmpW?>IN!|E3-kf*s)hw%w8>wzNPV9NH^~moEbcncm zE41`Hb@`j)qT9R%q$b(&(k*_|nY~PU-Rn#iB=iRUG(0FL#&*ZzV`K56gx8r1<36a{ zz+3pw$0Oc{m*7Hp6^=%|#Hg{GV>xN(X@AkT(qHr;oLLg}2d*RU){)vA00Ssn z(q(^SyWrF-WARCeF^8{2Qn?V7m<07!C+R;K%NY*^;w6U=P|4W-2u;oZNCw+n{2!N? za3$*TN}V9dKv6Gib4T!(VTU+`jMJXF-!?#H;Lf>)y0iGm)p)y2&%KD0TJIINo?5e~o{ zHsEuKF^P$XIup}2CFX8QBzn;VIyu%r0@YoF8f53lVLc{Fpo8x3sD&pxzoYeH$qwnt z8+)iH;cxCn&9fpgD1feHyZEu3$!yJ7&IFW^U2a_BxJ}r{$0f?h%^iOzF(bZt6QyX= zlfmjtl*IS%+=L9_oZNq$jfRq4sY}V$L^=iEP31rEi=jYq#{ zhr-#1`FG_ZbTOuNIFX1i-4q*BuNyS=^mi1FN%)w&HgDFaqt2-u64D6Du?#Fv{6eHr zkui;LB8|l3Y@Gr-`Y}mo82!K0Jm!;+9176?`NwfkNDNsn{(zxR{Bt`u#m27=((#=8 z_E^MyJB+~7eS3~`-=0Ww-<}(~Z_f+;w&xqa?FG(ndtvCwT)JaV_p?4KGcn!M`Y@j0 z17hH7J>m&|csJ_85Bx|j*@YkYkd~gQ@B=@5mck3XBLyi19_2ImfDcGP8MEO7{y{7q z_@>&}U(!IoBqib+o`Gw22CmT=xaMYXd$;cAx{rZtT?VeB8MtO<;QE+>YhDJfMH#r3 zW#C$sfooC*u0I*L)?{$$>y?`k>1~eQ8lUeU)fhfXu>X+7=ONu~8hc6N*(RSPt;XJM zITr>TUtKKlWr9Nssg6&d=MJw2Ht8GRC|Bz=y(DdotjGBX$<2a)3$Wq9Hom}bi-&3M z75MYOj{gmTX>H5NX{KX`&6jwc&G&o2cWXI(K?WROy(;jpQGt&0n!sfVm!_{y6_`Hj zOOf3CGziHtz;|ottJ4Awe0d0b;^>ewU*M#`8wI{r;5!8V z46xAwejEfoAUHo2_!)tJBXB-`_3CsUEAS%%e_h}n{4&h(uM)Tk6QYwpCh*S$&cpTB zaV84fByhLDTLq>scz5nen3Q)b1}{nMd|aLk>^K($9A8xnJPW@PFz5Q}B7wIHyi;KQ z!0=|97coD%M@ZfXe7AO%s5OmJ?-1;p|15%_?>KNR@C1fGUpEEpXyM+wYd z=iQ=p@RG#VvR`sGu*<7H;P|RR;N^mI-o%jKEO58Ly9NHZz@G&+I{1n|LA%xJL;Q&x zeUSXJ;6D~{eD$QjKNOq?aS?X;mkWH2zEIG0?!3D_3x`o1>P?3y9K^a z-~$4GPvGYS{t5o3W0#^%sk-(P;%wNmxQ4IL`81VC0D3VB@o{0A8q~^{B42x<^7;e-%Ap2 zu=zd#?9%*0z`;6J;1^E}IR(=~e4@a!fKB>Xy8_>7^CI41^O`UCD*_I#i2|<{oTbyl zysi-VMuGPMo4kB=zrg$``!1^kafj96v%s#rPX-)c{XpQK3eFQJh5Q!;&N(@hPXIP~ z!5=hmkIk33(B^xr;Li^@zB*6f<7c>YeZ}u>`)oSIQ*AmY0XzMd1RP&A3cNyaX#LWp z1HXa5{WeYFzi6zI^}x>mSG>JDHhzenIt3H*@2T#J1f$JCQQ+H{!f zM~C?XO_x4@nCa3Vi?f{0#lWuq%YYpR)3zPsE!wx9liwydKNt7~f&U;dz5oo;JPq<4 z_@mCVu)WUW`PjeR;ycBqbq=2UM#OG z`#4}%b_`8>?Jz#jZ^kk8#PABnIPoNkF^97(ZXB^Jrk;&IL^qZzAb0#4!LJ8)<22OY zOAHf8j6U2elMuPJPkV>MPurswowyy3vlFR-aY`1u8P{5^udH{clGe>-r@ z^zX&i@$UzA=|2E$IPmieZ0Z)@+X()*1pjcrfuCRCUHD`A&tU7){}r%H|9RkD_~X;B zzhG28IJKq zyW6IZul$1cS}FL=z=mV|GMm0+{4zUzIt9NQ*l>Jx12Ef(`V%|;Zo$7L;J}|FuvsU2 zN#Ys$T$TK|;NKf?eDy70wms7)F4tHk>5JLb{}TbnSI+|vXpWa8cKW<1_%8<>_+`Q5 z$o|Cii5;Im33us_4mj{<3T)OAUXs}HrwRUyfa5FrT)xw$Pwe;=f?pGG;4>8XF3Tr& z{MCZr8gR_h)*Q``CF@ZxGp;?2%e7o3mjrUtzGf_&_QmZ3Lvj;1M((TYf!(#37)x=@ zxiOHNc68&K?dUk1+uc}x2-uBf;&PkLBZ1skKLg&OjalMpHXVg} zFmhj=0KChlL(KURA<1^xr6K&f0=uz5jHMJqa!DZf6`$F@U5h>a{I*aUEHd2qB0kr0W(IQHzW}>2 zMSK(L2qD=X$bI$OoNycw`hI%FLq;L zf#47uxw&4uu}~p6#BMCq1Mk8g=QLuMS133Bi+5X2QgDck-1skkyX7L3d*f`8fZ)vmwQxg2Z`lor9yoKmwo^bAw=NjI;fx%0}0vojvH@dgR@XU zIfw~;0nbKtu*O3Fyt7gGiBSoP$`wG!p>JYd%Y_8xIzK8w=U5h%pj>#dftGeU&p|2J z6NCh%K;lvYoq69G`re%bomoFZ0-YP966nmH7jo#ExGgGy&fQT7bncHzp!55q66pMe zs02D6h)SUIe?}$H`Sqv-Ivf;54@D)=nJZ|K7j*t{R05s3QVu!vP5fU`33QHQwIVpsc^t|f`bs_vI&Xrn}G{&7?SoqrjXK?4FKn!%j2z*4jq`XW4wH4>(|CQ0dt|1EYO4dU=y8uvCeuTk z<#4SL_jsL15BB}3{x&Gig?WZ>w@rs@h2cCtKWI73WjL?L&g&U_%y66`n+~tv!+CRd z-pzOgjeC>1#a}cyk7m4L#XX;y*q8{#_=|gdBAU)|p38I!-VAW;NkA?*Z)F^H zaZl&yqJq8iP*$Qj?4!1z0Yj;8+oU;n#Jx%p6GG>SY=Y+S3oGUq4S%xfa2&=xetpH3 ziw5U$j3Yem?ZGy^e>g8=lQgHETl__X^DI^dvGK4Rjpvc`CZ=0Tw^w@Eod+?lRN~&o z^h6+WUcP_2=e!wm-i&+nXXtzwhE(SfO!o?pKEcw1^8!|m zsJQnCw&`ug@39!lu!@W6V!y=*#J0o^@z7&0+anrIvYcF|qod|o39nWrWwvxQ)LRaI zvTk!{D@H@B<%Is7(@Wue9CHm|@^atyg=sk-$Dwaxws$mq$mUfN=);i^4WG6g&gv$w z^xp6t%Tc;EoS{gQ4oa$CMLazkFS>Yc+lt=xfz^*xbCJ#($nd6793!w76536ZUZ6s0 zx~;S@F3o&f7!?{Uld`~hjt~ZR-2OlA-UYCZs#+i4b5735Nz&IeO(~_6Lus+RN|W>n z6_Peh(~!1@z9^-TrcK%gLQ<2o6lhBel2E zLg3uo5a;5YAm`}pkOJ<`rsX=_GVD4=Vb}L}Z0UFIc8g7g&wv<9qM4Pw!Xa*5Ck-sIPdDV*2W+wy9;NLS)!AVFVB~-liT@3V%AK1F=Sv^YGJ_BYVw! zT0VXq^FXKw_>AFBbqYK`M zf5jW{FJdx&iT}Yj;LEHTTgSE0M~yCVE=3O*8F-3b2h zNk*7Y|I30;G?cL|7YY8k&~-O;Ewi>d!J#`uysd(~4Hq%`WFw(5H*Lefq4Gl8)#BWxkbgOi zd4Osiq{f*a_bpjEq?sVzZUpv^;iKSJ=I8qaeN!Q4-bS)l{9WB`ekcp%2yitw@eS zU&-o1)f68>^`-Y8pm`O`GMUzf1@*0Sn(7xWoZHemAH%e4*_jwgrmS$zhPLi*EFv7E zSiIjk9ZQ=Qw=S8#a&GIiDYMUBI@fA(((0NST5KY8;+m<`v^Z|`FWrFt+lHR5_9dN{ z;B!JBhW65J$go&(ti2r{Q;Hp<$o5u!RMOSi-C;h=hk)24$SbXZsASE>{XuA4hXx{j z?xJ<;(2|nY5_htdxyx<9m(F@SH}>O02(ctA8A0ZhzZbhi`u%i#2OWPDyV6lGprmB& zrr!FHtt_CB+0rIsaY#y>7I{_1?vT`(W>aE`S++HHzqW~t7*UH|`AqC8^@pj-?1!n! zLf@fEmSum8sVw*~RT+PnDj@NPsmjcUse%CWVXBn;FxBmdI~9DG>JvCjq{+u4XjlHM zKK>#0W%hGbfj0ZODyzfGQr>fGQr>fGQr>fGQr>fGQr>dgQQ&pMIQ&pMIQ&s8D zQ&pMIQ&oBNd8#V?d8#V&d8#V?d8#V=c`E$c&r<=}&r<>M=cxeA=cxen=c(|kKTn0< zW0x!J-RG%*_2;Ro%;%}9?B}VfJpFm9D*Jh=D)V`&D*Jh=Do=l&s>*(zs>*zxs>*(z zs>*zxs>*(zs>*zxs>*(zs>*zxs>*(z3i0dDQ{h*Co(jME^HliNpQpmF{yY_a_2;SZ zt3OYLU;TM1{L<&C@S{IZRpmZU1&R1P)zGhC&V{NYlwMR_i#yudUB#g*bLzu*t%Vp7 zEyrovlG>=2AvNk-g3s~lico)o8{cU}e$}-y)#0yrz(N+r_k11)}?tBzUdTtr%54thmKMR14xvl zIVKm`7KIXtdg~^U@-ZS!r;DRarSPD6Su!m+y*^`yB?I7oqa)B%5-$McjAkXw9yE}>!tovAy%XbdV919`p{dc8uKSz zk&4iCvb6JT`sNljWDVuX%CMXShta?osdN62+|;RG+uyml1L4II$C4sVn}?%KoA3WG zPn#4*r$IH?IKOcbK10>fdtqDe1v+tPlEBkrghH%HQ|Bkqrp{mf1*xN*_f|^|O@m-L z`k&#>DEYk?9lga{7WA!OT)#jki>}agWflsGG%XHBn-)Vo-GAuaGP|v>!whyUMqi<= zx3}$L^%ONh2BKfl)zQ7ae}mHgwHOm97xkF2trlBMbzUC55O2*<4B@4DG(&tzr-`dm zaRs@^;%3lZNtD4wV zQ&4FbSIO*{$5k>oQdfN-VprX6T$R5>Z_gvPuHw&YtWgiEhwwR#)!svQzX!{s+fPZ@ zk8gAr4eiPw%AcXA+YHAqPU_Eb%#6{|oV|lr4>6zQz!Js{_#}Zn+CH?0w0Ljw;M{Eu_n1YDS?fxzb?)9#s~fI(e1F<#eyrh&hTYzA-<$CK{dbKW=VZUQ zX1u}M59=ZJWET>!Yn<#C*G#eOs}OhU;Jlo;cj~z3?X6sWykRCA$4=C!;fnpq$HzA8 zZruCq%?-Qf?tT8|;XS7~&Wr*a`d~%L!8u#QSNIX@w_&SK)aSwDAD|B-#12Di&l4;wR`{GSN42$pyB3}wUm!@Q??X~faB5S zcjI9xcU_O>%q>U%c-P^cySm*pzjXN4w?7L@n>Au}}CmTxd9(&W? zuie~OPN9EXM=2N1HKcoNUfoAIsnjhsH?H{F-kU@e!;Tb*5RC5%RH_PlcopSPumP7{{F3|(A(7uq~e4gHraHcT_V z`nj|STe7vdAZ%`h-#^gOwkIaMPluL{#k!+c(VDgS0zQy8K(CWK1*a@{Z=!56R_^?H zNTCk?9xZFD!#CWuZNps&uQQkPH{vWJ9cOPiHG{u|H!GKQJFRMaICz)ag-YpiHj3no|SzEh_dh_iLwV1{+LAB>4_ubmwt+%SDzc@E#%8$t!U7M!dvkGG~d+(n`-8R)MM9RIt`2RxydEDk@HcwA`$4OR{ zR4G=*%tLcaRf?4{g9S7bSJqWrRhPQD&MkXs*T$SRNbAD$BvVwZJf5=7syr1}kK2tq zc6xe!(yGe=C>*a2Tmu+S`QGk23{DTDBj3B0uwMBQa=W6%cKF%)ds;F_{%87ipodI`Mmk#WQj9#>{s3YMH<*1zs&MJ-fktdK;cG zmV$P;RN#>UpDgeKfoU~L)^nr4Hw*j$fj=nlT>^hx;0FYLOyK_~Z~}v2j`w7NrwV+E zz^4oRMS;H|@Y4c+Pv9R3{DQ#c$O>%3;R3G}c!R**0@D}s@VW>#FGKhqqzAUlXkgYk z&2fBnioi$V9w&3A2s~flRRZ@4e2u^#0X8=H>N5g=QDC~Cda5?f%MkvMwevAxwt-f) zG#p?3RN$|mNHOR80{=$fg97`wC&>JF2;2zF`p**hT!HC+BHg$me-i$dwX+?Vb?$H+ ztSTXJCnn>Wvt8i#3j8sF9})P60{>ayN>r}K9$$?Y_;`Wo4%_M0X2Q2yo2!A@o&}EM zt1|^&E;y&4f@1z6fjb1gRN(gr{7GPAgRdSF_(_53=25-1lklz9&Tj*Aye~VBuYM=+ zp9JUog9H9=1onmmavH3%&XWaR0BmgV)p-K93rx3B=2$xkvp+8YW}R0%j<2p0c#q)p zqe5r?wF2KE@Mi@6mcYLOHa1|T7J*~9jlgocrGTfPuz4B6KeGNT1LkyP zM}gU%XC22^&k6jz;CunIo6P@~z|R5KYL&jC8Bn}-h|S9oKEcNIQ^9}LaeVcf!2b}O zpW;<4j_WT1$1#Oy^!tjY6Q|p_2ydE*7_I6wRanDYZ+ z=Dg(738r2C7VI#+CSitr8 zqdY^H;|k8xN~oM||svjPdF z`(XT)In9(3M}#DlzQ=_mw0;bo6|9s~U2V#nkl;;>Sz!(?gU&K5<>)nLa2a&9LIR`d z6%HYR(PXn(J4c@dqeq1$Fq&)@92k9MNJ4AFydx}u&Buo&i28)E1U6IbgPnh9Z5WDO zNMJL?E+nv-ViywFOtA|IY^KyYgQHZn0a;VhBJxWWm zKD^y;4>6zzhvxBeIp4IL3eBOip38aJawvbqy-9gF{DvBpxsq|umXF;Z;e%I4!t)vE{Df&K9Uu2kKTRc_ZEYlSAV5Kd5erX)WaI@b*2cooZ3Tp|lTg^f)|iR4xkX@u)yx zqf%LjQ)xL=LmCd{kMMS)IN8Yz4|9j+9!*7sJPMdA|)M-$}rRZuLD8m1h;4cAw4E)!N*zV>N`0gV|1QDb2L8{$f3^t!Yl8o7@SndF~kH8;agnzZ*SAu^K{8>f#w+jCA;E&&dGGqDq{Qr5uzXSZ| z;iO$f_|FMGmF3Y_DD|M_=kxzx1s_SPF4=|hX!&+NAynRniq1TeO7&ie{Qo@wZ29=_ z5d7KTbYG>ZpC{xt`2lDlKL+b{8b<<2medf{(S!bfZ*={ zf5%tqKOg+9yYW|qPxs<^qw<)! z4&|!|e}dqn>QpCQk33g|KU46RfF{7&%D#|4bHwvJ8Lw!Jk!xPtOMMRt3=g zA879^KV}1@{@sF4{=5bJT}AZYDflbFZ$hQ`U=jX9g5L%H>)^jwg#T^9C;iXvLHqR_ z05%Si_P@kJgjeJ5nj6s`72)e;MoAeq^3TiQ_gj8G{~Rd>zr-K07b|-g;h&ntKMnkk z6yYz);%@-|OGWryf=~75UhtnS!oO1R)8Ky&{NEPge^Bt}ga1F^m;4X_8@pQi|FeQW z5}e)dL3?NU`TY5H!CwddL*Ta*(f>=qC;wl56UuK9{jX*5?*;#+BK!)jR{|dpU zIhheRYiejm_m6nHQ;c^;l`8cV__M73*DXn|1N0uDe;m&JA`(BM`iS%GzcVoxG@V(pX(hw3$Al6H-lWO$93WcC^{$zY9`B(D(@ka&%lq*)^- z(b@`7J*~B0#Xb#V67J{=I0{ZPE69KyEE)40(St+kx$DCjr0X>t#nUNRpS0`8n3&A+ zFk>L6n9R|5V!5lZtIOD^3}ZI&DJpZg1c&i7xkfAJHD|sgC zunS>q>BCy-S4pX}1@HW0Nh3UnnyGKWBdBNAH(|dxLwE^prTKb|8DFn4IbGzF&_D~^p!A=6oW};{}b+j+;SRast477ft z;YH6)9Rb4}BCwYN^`c)c3Vk#L?@v-t9^(+S)x{jB)RC&;VlJ{AN#;qx=xo6R5>(Ek zy{hOyYvvMoaYtJ_#OCIeHZ2?!Y0}>sZPI`HUz_xAId!*f>YQOxlWKb8N_%7yeul|A z9Au7UD!p%<}x7CRDU7bRR4{)wQzwi zQrvP}TS+4vPnE^ck+l9<+<}_~+HGm+HY1MIX?QCuQvJidqJ_m-8x6_|B$4#9X*s57KbOs~Vn5rK!woPIuJ3(wHI^M7sh__Uv7dhy zE7k-bvbLjgjPde)XgFk35pps;Fu+bWEr|<`)W@$z?Bi7YU*lsvtAJ(fN3oAh8E{Ud zjC>gRIH!$plt}$NHXdzTQ4{}H)fu|`qf+-Du074(vsDhcd6{%`R(Pa7-WsuwZ!79! z)E93wU3UnpZdsStk;5yO(q5GFU6YH*GYxqU#!(Rmn$+G?hLXaVmZL zP1QJj*}7b#Gd|pX+xsXP$qD4R&;Zr~ysqNpmB%8^$x(8$kxsjGoS9G=VI0?YEISSp zCToT7bOE6$Vbn$cnu!#osK6yJIWyN^ERwZz^C(o=)hcPx+e!fuY( zaUU$|IG%r^OYP|6X;s|JV8L6;n7;OGsvOV#ncPQO_!gVKm&_9*$eA1#sdqmWv3I{* z)VpuVc{=B*vV|vT=gCns>c4fJ>)~5Gx=J4AXBD_7Xu~6QWIP#d`Tk+D*whk_midbF z57+clN(cK-juG21LJSJFJe@3RKs|z=AI(j#^bp_n)0GyzoTw2=Ji}xyX z4aky%u5WexvttfCUDeqKn*xKJB&Q*ef;!3=mH$P1RW|D+E`V&W$s%0I(Th3UxaKk< z%}0Yuqs>P*lpe}_wDy9I{_sOhIx9Ib=ca#kYMX({?IyLaJ2`)9bH)2W!PF*3q^W&( z#Hl?ekBl5<)B|u zJR&^_>}m#A(K(5%8t}+V_~A%>i$XG*iBWmK$xe^pH6FCy^xk*4*3h$7)b@mfBF#W+ zQ_)rz*QGo>BaUE|JxHS4 zw>*!@%B0jI1S!x}1q4Vp{iLON&UvBD6JhD9ywdaYO1F@-5^v*DgHw-tyrGQ2bM9)0B4HZm8k4aKJbt9Biafan zmCR;S$%tGU*3Wqt)P6_Rk%oC%Br{!3l~YIgK;%OG&~7*a2eJfBlX|tS&)St7iFIu zh${6|w<=qSN7YbChy*atARuMTDqp&y$PJD(aXKSToXg7oO*3+px|LUD&&NJHQ^J17jlKHKZJp+Rfv)6qIg_q;lt?}Q z#fUxsi?>@Hy@~q9^>bZaP=W5oeikPyv;1Gz!A`rq6tFKb}+H zB;RhE?L;7%yTs@Q1tUc2g@s-*%jweS9!2G4Ixm%7g>E*oin#qp4ys>!0fONpB2iY# z6CP<v4Vg+wFSb7XJLcmbSkBOdHLr*tcs!qT+dH+Z&!QYlH%~;m@N4Qe}xc zor-eqRVL#KPR4wMNYnAoh|}?lQY4L}`wLXaXKDAR2BAo0)wh{V=60YS0OYHX zi4dvlpNZJ@_Akc zpdv^=_T-Yxb*`L5CSrlIe4$Rnva{#vM5Jc4v1?P`21u3CBX*t*GU7;+>|GHj*=H)= zX0?eKKi!9UtM?DyL^@n#(&6`b_Zf96wOETg-nFTtuYW#GyI@@w3a7LP2Su75UynFF zUVghp=uMOkH_&jU!%5yms^~Y!RN1?+#zeO3gC~^q17|r&^DlTjX&~bCNe_CPRb1rh zqf3P<`~Ljw^bxNf=;ueWlE(%|T6$^+McV+KHmF!_R>bu=`Mz=lRW7P*+ZoP{G?mPA zv7vr62Sn<+xb#fAJ2*?{jus%YN9>hk_M%aG$;02*%;z^K| zl!!b@MXdyx6Zr(l^${o4y@x8PB1n(3O|kg`T4>ukG;LbL1q5OG>!q&I7GaSVo+lzs zk=NdCtH32Bf8qJ3UICC*T7l6DP3>TwHz z2z~iXmnxZydhNX_DnWR-A?Wr7L6H`q&WO`v=bK88L+b2NSfmd8MZ^w#{;-aPVmf+=t&Yo^N zg+=*LrSYfx!nwhbx^eW7XnR*D4kZvTvd%`&M$b98=VhJ1c3WSqvej;BgSRd_hlp2fJIp!o_264v5s%S4ZsXTZ_8- zt@yE0H{q)6zp;Kg+{SY#^vK_aHoQS-9psnwMV4g}J$?TnTZ%99dTuF->V7xF6&qE+#Xgok!8^Wwnf|f>_ zNdFyiBK`f)<#s!lx@@&}8lE7@^%)Bzb=jby(YAYs4LxMt2kWwH+O*5iKge|%3nO*e zu@Sqh=8(JWt828&GEHY^dM@hdU9^s>QBgW&K%}ml9kJ^c9CFvaj&*lXt2qzRqYCC5 zUb-0)@<<(bZp4o3Jamq;?fC6z0Yp1(9t6{m>+ubvMQ~)OEzjaa>d?y~cIb^o9r`Bv zprGi72(q4VG>1jn@}doP9l5-c9u+_b^%tlGkU|*8a%ZZKJE~ZjHW(LV6CzEQ4@aCX z_ZLlh-#xR3CfgKHN33o$zTuS|+UCWYh7M|rVPDo3$KHgm z*Wq4lA*3ol#=BIkq({B~o{4G)T|>5x>z$6q zUhJ zbY+z>_L+BTIeYEOrm?ekKRcvl?2AL1$2KJ!Z<+hPhTSd6{kI&zZ*%hW0YXj5msYnV ze~JA4;_CFkAai|nqcjnv5HHV(~OuJ zipGS{te6^-*}0oydd9_+v?+@8d^BZn@}5x#2U-XAeT_P>wLl64Km zHzCd*Cm%PA^^SXSLc=X{-e;`KW?$jhP01;3!%!bpx23V4)HWIW6WZ#qpV*ecenQ)7 z?8mij#QvzZ9oUa)+k^e#ZFgcnvh4xvE88B$epuVn*bi=d0sHc{SFk6$t`jj)?o~I$ zyqjQOldiwKO zmNsfj8?~j4+R{dCX`{CE5fM`b@?Oj%dz#Ab_Hbf95Y|4{#s}! zk4JYMe-JSpy}Bv6uP)WaSF`_#I+Ps98l-H8k``fya}n#YSei9A79jn?U! zrew>Ftpj&`d;dG>%997@X4T(wN;q#e>ojcEY1pjOuvw>JvrfZiorcXi4V!fuHtRHO z)@j(R)38~mVY5!dW}Sx3It`n38lK@|Qn7}ybN3EzYfhG|jsd57S}cmA&1e|goE(lc zj_WkWH5_@Kuh6LHQ6-O>&lDE0KUIv%xiMoP>|-R=#8KErw)+G5aV zSR^IZRe4&5k2s5?%oF#zSdjJ$P@B4(Y;r`IO=pv$lppft;U7pXqXvFzTCwMxH0l!i zf{3ZimC*f9tcJZKd(s0cjhbh*ytZKo313^fz_lHo;5-`jRUGYNLRvU49^<5q$#QXR zrW{VRS63Ojx_t+}jWQ~)w+>e~Jd~FE4&325#Z$M8rOtf1Y^iFuna|)V8J_Ro+e8sg}bzb#Wc% zz6OeWgi7@6n?sUe7K-~CJ}@Vwd2o*Al0frptGS+j>y(LMqKhGIW1!kG z->8Fn03%8{-G-r05LG{8jEkkk`mp($u%93==qHmVD+c1L=_RIzRl0107yS9d8ysa@=iahy% zlMRctXs@>D_OwN}r!BfYZPD#%i*8R_bbH#O+tU`^p0?=rv_-e4ExJ8z(d}uAZcj0; zL(HFZu{0*z+8UCrZH>G4FPPlbcm>il{rEjCIxjX{p>9BK9P&7>pYxmPSvQSsnpe_= zb4GirsiC~9X?8*%4O1mOBu%NNMlDJ1A6u;@$~&n?#rA7W$Wzb^FFVcTw`|QNs%b7X z&nc|g#HGAz;NS9t&DOW3$8dfs$ejzd9~WvrF4TTpsQtK5`*ET6<3jDnh1!n`wI3I1 zKQ7dMT&VrHQ2TMA_9MpX@MEuwWhrv!kzEUuYaaHFn=>$bY{O%V_j|F%$1sLU(g@c( zuKnSKNfQ!#IFp<`&^Wf~F%veXXJK+}!SmJ?Ja0Fyd(gp_JDcxmve$0<=Jz?PhQ%`a z+B5pvGy2*y`r0%4+B5pvGy2*y`r0%4+B5pvGy2*y`r0%4+B5pvGy2*;<6>E?uRW8* zH9i!3SYP8;apn5Dn|Id??8m5O%|jlpIvm!rd;i!mJ#^l>g6FL*a2}5Wn|0hl$=11O z)TIM7w}P++s^3Z!*AM}ZYPGbkH%)KPoHspmUP@8+ zihcKZWesB=e`5d5UaWq3vuaMhx?06d{>+}S>TxzjopKk6n1-#Mvp3$BLhnXBeAnJO zJsL8jVCv(P>vVIYz5@r5>o{l2*6O29W7IwA`$SCPJ~P>7N=evW>Q|=p%$2nGznq>H zo!6pkPk%0ADp~!=@_Dg%5B46lo2HMk|A~1|m9(jtclZd5KE2~iE@~XRFj;|I)Of|N zy$$y~K5JppJA5Hze?<{)H`a{H^dRN8r<*&^y#;Ehxb`jH1ac%KEC!$R^a|a&!Z4+>1 z`xXojjjH$6jSd~tY_%UAnbnn9h8dSpTaa(u^R%-f>a=`L#8kKzPureqcAiTP`d8(- zAtENWGhthshOrI0Zl*aMY8Uh6pc(Fbo)=qRt4lT%z zGMa5PvlvFQ%S!Uud!y45wY~3iF>x;?u-Ej^ss0TtHZrpL%b&`g<2@jBMLQe)tc!_8 zi5NA&!sctp&-->?{+(O5m!TvFlB*zTO8U4Tv9E>ZOU-znMrx(VZRY4vopT<(F87{K z`KesysNWCdV?LG3L|;B1^W|LTsK4jc86U!_ zH^|(-8bbO?4rce%j&eM@H@Vty_5G<-aDT91UuljzJL)`ghKPxK75O}Lz2li{q5N~( zo_$xEs}IjheA#iMoY{HY#WFN@*Vy>-=GeZI?n<7zya9PIqjO$Ea@oNCrw)9Z?s_$0 z?6`73vqqk}eC5E$_cq+}vAuI{Y1q%~{g35q6aMI8Ne_(CT4M#;1b-;!3}(g)Fi*%~ zsshY;j>&VcbcZuv`mD)e?$fy|ANNYfjXHPTAYwuq?4L8>9bT<#Rm|VSZ+a}Bb@#Y) zhQ=uTWVJ!{s0$T7fUY*FHL4r?J{(cl}weUQmL|3d8#5cCUt7+^wgZxJhKKSsCuJE!z(X)zpAg?7Hh1$te#%D;|)|7 zHa9Db9(^?DZC{KaCC^K{ux;nPm9TN{yzQ&A&%-K*9N(7gu<1eArtC0U2*cQUaqLV4 zN;{{zux)+W=N;+7wx5$7c0>?%c6QidE^OPf?674)SZoObr7i6)Y%U#&^*wU;pdTNk$c4dXpmy0;;vaB$Amd=LJC4|y_WDrKtg~I4f z8+%?RJB+^AVZ$hiLgzj2!nVbJgh1)DJ4D!RSz)voz0rAT>=RjGTV2>Cu}iYTw!5&4 zV_UPrXeBcY0gs4|f870dI*@=~#DpamnW zuVds;s`q%KmojYF)gD!98!ETgS6=otS{qo}m90aD(YxDLM-SA8&MRhf6k)~6M%vk# zThG#aRP3X9S!q(NoUU`{ZHu*MofpOR71LSF&PC47?Xd+}cG9z=_SzRx`i;eFB5|~n zxU1o*34^i6uim_9*YwkIBx3ZF@ZvvFgA<8!W936)!-mExhQ~^We=||G^N)$dfrR(9 zWGqJ3Ir5Ge$U8twl${+b^%GvKbZ9o`HV>ThoWgIix^E`D+HCF%#62fgK0M+5HaqO< zxDKlr604|8ls%b9#LDoyJ(2hW?Y;lb=HK@wZ2KW`&e8V&H?BHSruW{qY+YZ-j$6lB zDCTQQ1}6^RmPo8fjHpdi*48Ex(-UQ}L5IJx^W2?xCkDgxR}y8ftilzP4r73C;pKQ^ zcLLU(i_1kKFt6wd-=Y(6IhB7zN~DHmU&X67csP<0QD+C=o;1-7-*$H%V_vtRLt;}8 zhdr^f5qU_TDm4ZWiLykwA1fb<$jWmfdof^+PL!=m4BieGl~#s-%SOg3s&M)sKik$X zr4Z5OF=U3Rhp*D-pPd-8Ju&#~9ms2RTpsh`vsJOm!*Kra;o0ZkQO1VW!qDxpGUT{C z9(%^obWBEZYG|VDu2>lvmh0o2%31ML7*8g^lrnQhB~GGDoA12m?Roif{%b*4taM2B zrQBR$V#Jv_`Sw#m*oU&uyK)fDL+*kLDFt4M4H-$vup?1+Zo;3r;uQQ#l*QN8#E*{+ z@e+e~B6ZAv1jEzVpPd-Ko%Vyzjisvc1&2wv?$VruykQ7iK?y;ToU8Ky_BKVy9+a7~ zb14QLk7H~%X)YNQNls?_#SzX$In~NNLlJg2xdByP?Z`wKO6bnJVyO|7!|CEKr+wAg zA59Ft0_YQo!TVMf3H5el`}r5cOytn6uW<0t*wCujU@8_vaxA^a2l=C9jUf*i78_Cp z9>{}p$R8XI@=Eerg|D5qlAKnyGL{-1mf$KNKRd5)UM3~ykdgv9dT%8NC}TTg<&@>i za?JQ55nM)sqtH}P{d{hoN_@u%aJ9E7(^>8}chdQ&Q&PjHCn``ku1buJUm7d*5*1q$ zi8XoZnU_fo+8tBRtb#-HT6Sj@Xs8dlIx3?UD)$1uOSCH-4OIwQf*6W<;&N@y*@@Bd z?N4Z9TJsol&q$nZt{(}EGK5AjQFa+BW71J}8Coc+z;o;OKhTNJJbfZsv{-2sa$v%b zrBEBj%0?Q5IwPkN`}$!rV&lx*HhLh3h3Y*|J@V;M#+rOJ&<|{waU`+|D*rr{-}Q&f z3qpn=T3Jqy;A=#4si(CiVks0oG{K`O;d08~Llmm>U+rir`el`| z!TA#LzpWOOm7H4e`mrX4eCOR|!{E-G^Bya5-j9Rx@?^IiN4ZNLiOZ_U$t54QgrH~S zB~+|Do|->wXI)CESVGN5A38o%)m9KF@x3_Ohn^QJa1S$<$J@u(+6plSJb6;)g`X1tGKEzb#-0hn!1Xc>afmznIt0S0<`jc zv8*MbZMjOp~(U#VGrN-G` zn(?BIX18dYYJL>WTG2)`RJ74-6m84Q4`vz7Ml(vZ(d-dzG*d*Id6!hFo#s%{=!`ZR ziP1*0IJD8Ils1~3p^au@Xk$LjzR*T9Ews_B3T?B^j~h|b%m{5X3qsoty*D2+AV{+S zw9%{uZEW8bbEp>=Cdk*v@$-2!%BRgN)u0p~(+Hn7=4b!%^`$jSDH=`F#(tntGHu!C zWgj!2Mys^Z$W(47C&V&I2zTf)sgJo|_|4*(_}y;tGJ#hL{Di>I3jC_TCCGTJXSl$l z1fDGLX#%enxJTek0zV?~eu2Ls@FraB>-ysH9X#OIU>~;3W?;7MTF3D*Vb6SDbtMAM zbpk&i@G}DcPT(>)m-SB&xDMFZ@Cra9l?UJRR8B=Bp-w&lb2<;0|D=?e{W-DW74>tOI8K7dwux zwh4T0S-{yM@Lph}(^t0$d^>Q=#znZ@#&riU$Mt~Y`07D{Zz>Ns_X_;Dz&{cAFTf@) zU%f7H46Rd%wSn+DYeO8EZK!e_UmY&+-vnnkDstwZAaH}gcvi#4<*PLUZvakO8wl51 z8#;km=QhXj)lPx05}XZaIhlWjz_$S#{l5CJ!25txHeSM;Y`h->W<6hZ9AAA+;QNOJ zoNo&JD}lYCtlw9|1s)~vSm1JN1K~bv!%@I&!*s{-)u{rHL#4@_(*#~Aa6hook8&sQ zbpqcAJjmKW_+@LuUSQV$VaM^+-2&e$IM?|B|2~1A7WhvBk3yr#`fCJk6!>g`dw`9d zzS<=4rNBe1{e(AI`?mtK{+k>JWl-ST1m_AgZp^=3;4cdN17H)EuYN4>&w+b9k@H>H-KS$vCz{734gt-oB24+2L9miMe1zv4I|vJ{ZURQv^O+;LQT>1vc@bJ`s4I!1n`> zvbGWah_&qjV2^KtwJQ3LF^wlJRrvM*o<05>z z^}|$P*3;}bzFH`7&9MPzfxzp5jZR-(C~zO}L>m`j8Vg~|^aFETS2>Qab_;yLI|9zN z0^cq0SAdOv^o0ce7Vz;lUc&FR@jeC2@xI_VzIsvMUklFHCkFf%1wIID^!uvhxB!;} zpJ?MH+z>O@TLH}RPH-Gw9VhVc;{#5$z{>@`T;NX${G7ml7P#^Rp%d8H=BwEPHwnBD zc#^fB@b9eO76G&U7dVcudIVm1V!*jr;13G?gup)&*gGjW_b6avgRdqFJWb$Pz>}?= zgcn&qzZ014Jlk=6b*{iolLF3qf!{6gX9Rvm;J*qy_T)g%=>ne%Y;5yYx4@SPe5JtG z0b{ipY+i;ieaQ@4=6YbhmJd3PuRbd9wUYzRJpw-^@Sg=9Q62Cn3)~EBZ1B}N0>4Y( zs|CJI;7<$ud4V4Ro?@?y@a6Wp9tGy>`kv$X>W2bFzEm~eQja6ngFkkO^j)U>0zze1ZoGyWH z5cp#Pe?#D(0GoJGj{(oHHW1!yZTN-YA9Nh_`KK}8S1$vzon_Mle4M~@1zrkl;_?-J z#`_c-FX1gV-g5+hljHd6Vu9Dp2;$l)@COC{vcLy`Of2b zx#ZM<|2}~~EATS{|4!htS;4sz1fDB!r@+?={9#~YKjwJ^{(`{tx#T)~jf9`D>HZa9 zzQ+G@9AEuZ;3wZ1aDF9l`Duatc!8S*?gTdR`sxyacL+?M-<@r3BYc^)?P_4Q?L&^^ ztGfi=b9%tJU*M+%ehJv<_tk3x4+xy7Lm$A}K)BTAfg~{7aHQk->S%$F6`YFtfPcKe zO#-hKc)P&w6Zk=apAq=?z{XBrPy91Z&JN`CCDukyVe>MCAJJ>~P5>t+UGdFx=-Nu&JQ>b2>cCTqtjPU3ryee%hTaudm)E@I?aChw&C$+X(Nme%KDow%zDBzIv~~?-!g) zTLS+31^$A--xv55U=y#eyafR+6_~yTx76B3_&#gf5MZ`#yyN(4qQHX}2AmTGK11O3 z0$(BUZNMg8UwuO02L+}tqb;|#5$5vsMPRn=JC5V4?+N@P!FhO5!2hwp{}A}_Ou(rH zHu3tZLEvVA=|f;EtZjrZw0=7im~C6@ZW%qPG8^HW=vmwT4k@7@EJC)Qecj2oa6ZF zSb>Kv4LBzVJQvvL^wk*x(}$7HvvCpTd5p!t9M^is@zn(aFIpCG&KGzWu+fRR2!ZL# zL91fnPotTRjm_DPc>uJz$Fz#P|0j^nG} z3j7Db`QBLp{}qADSFnCx4HKBYPSbAVCERc0Jq(!Ro$NTinj-L+vjff)ffoq8PT=jp zCN5v?5|}>jvd-E-nD0GZ2h29y?l`{skid5f&NV9o{@nsUA@B>pCN5w7LEyg%Odmek zVC^A1-TLGpFxxZu9OmF&fWRYxne!)shpYC>%+U!r~V?J~O zGv{@IN45r>F#^+9A-Zi`gllbF#{jdQ8prX~G=WE~4mc+ZJRjKT^wlDPmjQ3IaS`UY zmIHHK9gc%%KLnoF7I4-GycO8!^ws48(^m+3J%!E75I$97mAMv}SzzXWS>Ue%o3iX>2=mVaUuH) z=`UnY9dxokXOn(W$Ff}3V{f%w6td?~mAgXv->QH9UHquy{df79+9u9FqeQ+cbiGl_ z3;Cf?yl*vM71C3v9xKHEcgf%C^-e^ZnmW+S5FUd+Y?%|W<9^^|V8g+D4)8(zQU9DU z^QnGjehaYS_-Zw<(shxSANy9Cl=9btV znvY?7+JOzn*M0mEmQVeC=5H1J9l(a;tDAsF;*abh%=}w`S^uq$IKDanJQ{z*C(Qh(ftmlTNvRf3QT#6^b={ekJ{cnSVg= zpLQJF#|NHd`GlGOlHmW=aWDrP=Vwm53}NP%0CRe!9LHBgn)ePV% zmQR@Zvjo4+aeTEDc$(!CX8sDnU*$Ny+6X+u@(DA)U+}j$j<2o?Kqg51#Yx_!pxr`__G|xR~cZcA4xx9<}Vfe6^?^v zBY~SOpD^<`3Vy%i`05(q7Rx8h{ObjOkK_0XUpR611PL?$9>K@=N!&fYM}ad|KVjzY z7yKt32lqID7h67I=D#5LFFKB|{s(xe z^&#*I%O}kII>B#n9Mp%vD=nWe^H&M}YR5r+2)xSj2{V6-;BR#t)Q7<5Sw3Or-z50A zI1cJV;MJB-nECY17hms#j)VFTc#Y)~X8r-ef7)?S9|BW*O!<>A^IsDD-#QNJ!z9n` zqdo*?ehDz!lX4u?hrk=Ge!|R83;uY=L462(zU32U{w%?#ch(FC^&xPV6POlPR!$JCDL(#()%WT8`b&WlZ zPtsUrb~w4OJ_a1K`U#K6AGXYW*crL6o&x4RKVcdhV9R_5JMQQIjU-kNVYc%hPVVb| zU&?Z*4@lz*Y?;G>jojCDbBX0pJYA$+{$eA&rOKZ^Uw z)Q_V1AZ(dm0UJ5qiJLFaGDJpZUlly8du<7f18N%Q9rM?aS`UYmO44!9RQwe zIfUD+o{dh9atd5yIfS{qf5*vv^><+IuM%d?K_|yEDyV0sSv`d3+PF?|a@YergY5x6 zn(c9NU;PI#_eBXa=SC;@)&0QS|0K+H%cq>&SN{dfeNMvjY+OHaa$k)@9av}WACrA4N++aC`xm@%)Icx@|x{1ml;hEN+PdPcpmB3AwL%7aze&giu zb1LX75)PH=L(V*Va&oj^z}(*>Tx<3G+{t}aiOH|!Ru5s;Gt$X@bqeqb%OO18>UpP=`|3Pk z?#mJ8>uPgyJmU(?{WrqQ+2-WFx*3@JY=oKfJ}39pr-0X3dk8b9~qgxTir zIJvL>2)xd62y;FEs*~ec2uxybupGi%M~!fDU!4q0Z5!n=!V|53YMk6xX908Hi7?x| z(#i46ByhLYLzp?6o!nRN2Ht2ngqgF~$?@C{aIfVMX3i&^9Pb$cb6;9!0y)-9fSmh0gjr7@$9NWU?(-04P9R5L1@a-*X2Q$~T{5DpNBAW0y+A+kaM4hFmnPq#-5OKpNBAW0=bzF=RVKVfUBC%9Q6<6rf-A#M{oi;>L18SFWEzw^#pR%Kag{uhcI&jxw*%| zeV#3XL)ges{{VBJhcN32q1gqah_QU5@`5r3qIFmnRAxi`dpo|goNu#uzw z0q(~i=^@N|0y*j*$hpr$m^pzQ^$*6~TdW?!%n9VO&x1b5fWj9SXd9;YG_kj1M^cTS zGrpx7l0o>x7gq2`5*l$+FDj5wzn%K!fn*AfW`!hEaa8Xl04hy8Y^5%)X*i;|N?lyj zaYS(ik{LLnxB>}{m`({vswbPVR=}yoWsv5S(_D?q7y?OIAi-tOQ$j+5%bIjIY$khz1U4@XOKjd473hJ@qredo*t{Stfz4-yB-3Ft`7k(ZI&AI=ORUX@ zySS#?ydfm8nc@->*i7jqB(S+VEP>6Jg(a|=^2X>OE}Nf^aFQ7|KaU9{u$j&}GLTrC z#|9E>vyi}Myn=Hg|?NGp(Nm2R2_4 z=D_Cng(a~0_OJvte<&=0%^wR(VDl4U32gpGSOS~B9g)&eC7Gggf;?-g`e+tsn)-N_WV-r9mSl!b)1!lHubHXSR7lVew&E-) zsn)qyN@}zZ#|3)O5YEO~QZhxSvXo5KPq9hKG~Ie0BlJwyo|lptdM->#X6n05LV|`6 zg#|6BOVcUUdiGgLYV?&#Nv&={#*4G2=rv%aWU9W>34$|C*TzyZU3>Ld!I`1GAtf{Q zER>L-A*6a$N~(2RASE@r>_|ziw&xu|Tv%MB0eYlls%p-XOw;wDYlWapdox$_$)MpbT?IUYIF{l665EIfz8vV=$2Yars`FArDU4E3MrYc{Uaqa)VYXV zN@nV`I4+0_4I$-BDXG?;my#M?Ye|W*`FNqn*eoSeb(%_vu~|x{>(z^;#Mmq)#?L~6 zhHwLHmXd0HT_*(g%&5`VB_*}GXC)<5bl*lwrmFLxSxTnqeu9)t*Zl-3G4;lYBKDa& zb|FDSxEPwHq*~`FDXGCX@WPy0eO)I7nrBYYnx(|}SxTnq6qFKE1}6zUrVL7nDT9He z2JImA$E3vg`DCZ3X0mAqCku(G>!f6g_Pmssc2G*D=_{=kdZz0um692{oJz?|-AfS? zw1d>|tqJsCKuG;wDXGzVq@-5&52a*^?%PPoRNa%25@U0%h|Ab4CB|kcF*XYc+Cl2Y zO$qeWRHG*tmKZ-z6&#Z{rU}Uut!KKBOx2PZLSk&5DJ0Xi$4(KF8G4*6B{TInS4hwf zlFg?EXJJ4{HHnlMn`a4*vH6`sGDWvLQetdAO>m6OrwfV6&vim#%3!^an7VFuAVE7w zHqQ|fW3!YPn;V$ZxJ1v3(A{imJty^dZ0Uy%+G6;Ndm4szliJ(*+pHvBh_j}zk54Ko zz@cy&&C`~|U)*c5h$O*g@3Ui`ggEoCCw6#SX%A_BDDI8Go~#dV8|@)(If9eMK9@s% zOxkeUtssYb?zG{y8#v>z&(-q)5wH!yU)(zdd-6hfJ75nf&Eg)q@_9JFvK%V&ac>Fs zxpDp7a;RS$_oye7%Q5$f%&b`4quH5Uj(vX_^9iKqh`gLdHa`s4oWt^RF0h9r!7F^qfU?Oe{)Rz#^8_sHA1 zoLjAkX7S?Q^VsKJ`{yl(?#ai!JMwa#vz)Z%Q0~t4&tEO)XwBJ*y`8NE;%z8Z7}&<) zFYax}K9}CTULovfOPsRF@aZ^Sdnv(pT{K)gLITeDqHy``lYyYg}%+j3vb=21_=bf6fF0YTtJE5XremQ(3Cxz|q5deTPo zbwPdZ;Z7Z}(bGo#W)%{5i{^@q3}`deU+RI}Y_2!rPB6hh`57 z>3P|5=sud^(D)&|y=FNyLuEL*b!Hh2g0T&A92#kax3uNZy-}lw#$e&?RLh}RnnE@& zv>e}YXmk|b+AW9f9UDE{!UP;$W;ry2S17LcS`N)08V>b+!`t1KLw73-hsG-5?emsH z^IC>O{mAh4P0OJV>nv*dc>Q98X-&hXazc3u?!GyOGnvlRo^TvjAz7dH1 zD9fRHWQKEx2sN9GalE*rt=&v$osvz`(_BI- zsZiI{)7QUbQ{TppZl}OX7kBh^^s~}Hw&}u-Ea8%k9UblSLfrY?{SBRcZELzZ=Ja&; z_x5y&QxG<{yI|0g{^rW;GC|G zwq9XsL&xUg1gW9{GmA@m*01l9?&Q;hz~XUqNymnx@9N5PDty@8u~xbXC&7nn^U3Sm z+k2OUk`-hUhSOSJ6!fp_T%X@1CM-uGU$O}ft8Sd%xG3LgfjrD-T@4HB^PMJwO%4=> ziZGj}@&zKz>NmG_O0T;U5f-*aqz9#E{n`tJO6j%SP^mPtNv4+!S<(?IwB(h>u1$R# zvZ7hs@vcoBef{$n7LsRY6tc~pl(!V*W(+zbf6i#yv?f2@283NkdNLRFn#9X87xKoo zOB>AWQ!eSMuh-PSq62J(Hb0~YkO zcZ4s{B_DF=hBg#NnU%;SIz{M39?FuyiY!T{>Fi9;MIF71)~yp~I%&5Ma`c(DwHI{s z&*|CJ-5)NHxNhe3Y0Ep-_H_64pE9Yhzqhj+CA+<2&8GFOU7g*q(%{bSbv=yR)~xC6 z*zAsa+q&0x^eNM9^@pqRkdWilR8ekl3fE&HzUGm;MD`*AiC7nxDw0c?sdP=A&pyYR zsOxnOL%y?_M{3IQpbVmjb#Y@F6B(}Ysab}3jpu2)`wvm&HJB!0dE5N--sv&+=lj35ti z@{(bQUE~wGQVz|oXGkmC6l%Rg0k}SD4M`?!Hc_zO5P&OQD+)$dh0YhiSwWNnX8|?W zx}9%rZSCmo?dff8RpZxe>g;Nt)YgxhaLuNE)N8f^Tt^LtD&O4EOKroXo;By6oW@o? zeR}QWn(31#Pfe#MlOVKDr)y@`8gY7c`D2)s`0{C==-h>|su^AE@NUyXgNwxg;dtP` z=$T3(1f($(O@PQd+RRAjPS&cl4U~7ci}CB2FYa_RKi}^TA*306-oB2>WwK|5ovj&U z1K55#l;c5~i~hBpUA0vGldcPnt_z?d@gKl{$?B)`X`}gHE8@4^wfsM^uf}ZPC_6*o z_>eQ7X0&`Tps2~}x0C;lUw<43OXn+Z9DWn^eSIAlV#L&| zQiqk74vOuF#V(JwqS}sqFC0h z?K`=Fx)8YT^wI@OYHKFXA;Z)2YSVL0o^!$p={cw+)^~KLmvwh;NpG&HnKW%u^`w@i zOAxT};@-~n8~W1|*B+Oyo;h>cNi~zJXQY>QY-#ID&qpt%7p+8hKjF1Ky&HRa+xk1& zm6zDu)7h@#YkDvW^M=q!TA%wM=v^Ty9_Tug!q^XKZ{W0%uWOJ>R3Wetm9R&39L<%`J3rS*%+ znq@1@@ACS^WYt+Xq+k5h;OA`nyRv?9Ee_AYA^onZUpxgr=i-ol&#PZN6+f*wq~F!` zi>KkI4Tto*rhf5s{H(H&Rv=M4AXv{2Ys$WTxMUb>Moz*aZxhkQxwU(Q

    =&ne@o{Y zd!!2*)j8gGkOf-vb0R8-L20j!zCxMeZ7-$T3s<>s;_COcd;qVc;gA+DisQBS(St^) zR5DeXN~OwD<*AC)nAEAM(^GR&^UO;~+E3V#t17p@U)AIHJ@|{Oi?H`RHES^T_|==I zB6pdNCxJ!4xT`{ ze5a>k!|e{gFkJDb`BY2++>j1liR?`P(w=3U(s7s7h-Q3C0~6Dj)O^B z{=C3nM3R}t&dU%UY#f}SwRw2msqZ@uzKtO8Pk~wIV=%zzG3zC;&WVW8-o?sUYnJ(B z72CfPn9n6_XKFLMoSdHK3ix!rYy-8>e6DD%^_md5aq+vAvOh&$j`|5fvWzyeJnot6 z)&jAkCs=4hP5_5`Fu6SLbD6v7)a&A&7M*D}?$=N*h6bQoZfYq#Xp^<2>jD8iH^m#_2i}0+!esms zf5UsnI)q+pG&~ zzXktC4MxbNUHbD2g8vlo6nao7Ym@vZMOYnh47>N+qHSu!AiduFXk#N>hYB29Nj##) zR2RRsI*$KCLk;h9NMo;b#q9dUt&5f|%`8LrTFJv26_ba!tuGJJft82jz z=iIw@Kiad~-nNvswA%s|%V)ZuZNVSiFM4aX?aG!~1#(%zLbYXyZAmG$DWrZtVkD>q zBZ>IKZ7NFqp_ups6D3h80b__JCH^K+3Ghq*NPXU!cjlcrbLMWvEVt?2_ssLo$1`)z zoadZ--Z?|6)88Cci~P+kD)%?H;>rIuQ}MB*4<9><8!W0quQSSigUMgo)ZBIF{>_`4 zW4orNr~8^?d+*peg_btFW+ptEd+umX#s!UxkBv<115Y8w1x$>MO!ZMWsA{|I5e=c* zuy!2fm7>ee-RM2a)`yF>A~-fVs!JYJl?X$F#&mKKk3loq0nD~II zL=X`lFvJVkP_YFdz9?+LkPshGSpUvIw-qG2#)%#0OQi0BtqZqT7Y|(y-dtg^5RgsAbd~ z;Sof{hYaxowyoF#5MLIyV4DyhQdtCoxZau2;Sq)=jhkaUg!*`5!>9`J6+yKnE=)Y~ zW8yf*BZ!C(8{!3wCpT#Uh_4J=&?m%)RThDkI7U3em^hB{0>m>H_BSEEDy%kkVd9Y= z6UQ-LfOrCvT0m}1Sj#{Yxu^Gxji@X_z)T+|7}5x1W;loo5YJxNUxnG)u+G?pnMHog z3=N2&iT!)0Keu~KpRWoaPhZjm(C!VJFvPS+RTd$ZHU>1pm^KdK0yNy59`Cz-axeC$ zJ-cudPi+V*EZ{_#9C3y&IBp3FLd&lS3);#!b`Mk0#+JBOQNeLrP!KA*E-0vfGvnBa zOhubo;$B4s$G)H-RCGgFP(S0?Elfo>wZy%O3XTIoL8$1Ku%JQU{r(tjZi#yp6�x zf>2R^SP%_1RpiEKuqEzQRB)u7K?*`e!(lG2d! z9pcou=Y;trkmDXi=d3`FJ1i9B=tEY{o`X}RBF8-xGh9KBdmx$=3UY_>83|w1UEs`m zIpx5lV=rbcYTPS=uLR;9s&NN~avZ!_H+v3_w}^2M1@D3y_dwaT5X4ULDINl<~JrukPTHFKCs8EbstRS_)o3(PvfqBPX%v+SWR|4@4rMLq_ zEe_r+nmq@{Ta>tmTHYA%I4koOE$%Y%yv8yayje!49GG|P#k@s`yApWn;wnImRkP=S z%z+N~An+;(aSvo(qQo5*>TK|0ot$!DUa=SR5*hB5P@=;f8VYf+X3^|97}g@gJ;<`g zXqM)qy;y{}%UDp_PKl=+h;=B%oo7mmJBO4QPdRvXu^M-tDLHN(l6pMl;MK)~+%bjORmpg})Fi$ynb+Iyco+)YW98%gm<>1xD z;@o+r)VXy?%JY|~y5Nql=yL&KX}%)Q1!KOV&MlM@=LwwovNjhd<}1=%AmSS;bBm>fx!{hk z=yCyJ6=bAXE+8z;SLC>0%vaR7 zg;HWXfiqv$;^KtzLn$s0@eP%@#Zp3CaK~44xPY(zbDFH6H<16}GKvE|(0{1FnjcpxM65HY_ zg`L2?idbM<$CSRdcuHO;aIYd(*VZv5t}UL@)(PCJh^4i4Oet%|lfpWIdlj*+wvI_z z4F^wEcdv$ct>MuozUi&!+ve?)JIwF1n4swvB(9{5a4v@%iQKFSC+&UnLT)D+tEGkW z?axW8;S0GLZm3#mZp@0NQWR$a!jc|00w zd8r2vt}bK6JRS{oMX3i5u`XlfJRS{oWvK@bv@T=SJRS|Ty3~V*TbHqB9*+iAdD6d5 zl@GcuW9>X14YjV+!~c1@cOH+1T5o=DlXhqekE>;+04}e}0SKgW0H^kH0BdBF1H*Wl zzF4_Y7bA$SC`U$BM}%Mo&un=w;#%i!9iD6Op z2qV31ZVxOi#mu#Iy%aOooy$rwbB(sV6f@T|D@rk={jZ2Id7@%v1Y%&#-H$6%P(R+1 zRx;?6Ye20|L4$a|Ur8==t#(xk>c<=Z61fJ{x)d~scm0**GWSu|ry#87$iJ`3!H3?U zT)3!DLD21G5MT49Alx8JK?ACmg76$_1o=;+OsbBScmwauF7}Jbk8_89NTsVK-cXAY zIL;e7|KgT-L*)q^=M0^{yCvRGJta6jWq|Xi&cCE3-ay1@%%AdG{`Ho4LoG|-mjCjW zctfp7;FkXtE%An0S>c z)-ud(V=Zeo*0SbeEp>GgYbp6mAZcf=gD-O(e3|Ru%UlOv<~sN?*TI)L1z+YS_%b)a zm$?qU%uVoRo>A~+u7fXg6MUKL;LDtYFY(R6m#{ea5|$0VglU2=Vd&sXeCyy#d?WZ0 ze_ik;Y#n@=o8ZelGr^a6rh_kY4!+Dy@MX@ymwBdxFLMsQ%uVoR&cT-4wu~aRAP)0ZyaUrFHp?81P_3a@UjNtx3JQe}GutRZXfrnyF551kM{nY3B$T9t0Ko_>JFD`Ij|L5cGYjZwO?H`UmJ9c(_SNoyrzOk(G{KVO|S+XY1 zj`w8O@3^FXu>R@M-fJG2IDM}3^oh}%&)q$7x>~ty-<_9e`_(sIe{-(4S{Z-x+}*eB z`~0Q3_7`9K$%R*Y*F5s|58E%h?9rP|iF3UhE~yg}-RGa0*gw~9%f<`$PK-Y(rGNMT zD1CcL>Dv>fPn_+ZRh7}+)w31+T{+u^zsq&X(%FgE)ur>_{9tD8G+LaUTk_t_+&5uW z=9auW^WJP$nd_Z+=F-#WZ=P$vZQnRpZFqFFU#Z&1?Uq%1rk1x$ofbD|647 zzM}d%b$yF;efdYOkNVNn`08(|?2R~X%%Trj%S9hB54#T?XL`|x<;M>#KQ&@k4A3~K z1jY{kFBr|2obQohzG8jjcxt?=jv_~vsjEJgg(ke%SX`qM(^^*T>#o%f)Vd~~tJUuR z#SN7!m({ZC+bb1nmGgO9g-)yLB~E8D-|5Cmsnbj3^yymnjpOw1mhoDxdU#W1$#w74 zvdYq)V!am=-jyz_jPX6=owZ@bi^W)vp;FTeS?EPC(6!Nm8Evv)MokvXXy1f&FxF!E zfevk;oX*Q#LZi!fOs}-D2zOYpzy`N#u~~N`f8uew?nbx2?goX4>yhzRU!XmQKD1ZT z$9~h^MjwltEnLrP!>r3e3qjGk9JGq@C)mCfd)_D6{-bBV;n{zIc(*=pd-h$BmNxxf z&pw7j%ch_3>@NIFWYc>*`vPQ-P5+Z;uLK#J{)}h;$g?ka_C?Qr4bOC$6|b`?vcC^L z_)J}ZZOeSe`P9`vJo_!&pte5mdUiW5^KANB&mQ*dDbKzKwrN9M(Iw(K-Gpq4>~C>< z?)UspIiI?E!m}U1RgA6olxIKd*)Mwb?>zf&p8a>&rVV(XJnZ${9WVH7uIBcTZQfC@rk?ivf9ibd>gS&Q zOV8(pVQJ5=J^L-s{=l>8HDRXSx*`RP-4CB^itIz&C!MhES~MG+PhD;F>>LN6?T70; zd%I`fH$u@JBn)0$e66&*Y7OJQ3sWOw2}K6?Eh%ViZ3EElq^kEGYt2BcdqWLqCeH~Y-hz-V9Hgum8@ zY?EGBn9|(1kZpY=-REN0BicB&QNO{E*5je|cA%(`g6T-F>m(_dDD+$XI-C!t1??j# zI54#jy%EBcgF{dIND2-jy$%SyEyVb2MGEz+q|jPJw1$wRAS6z&H{_*Yrd|^IpwYcy z3K~sJyj*BBwbDz$W)&&)1`pGoJ~W!zrAccIx(+6n|wN zI?I2&>pt;*je7l$RTCXZtY&u0_fYx`uarW2Q_AN-&SKVmqVbGB-{2(L&#GB@d+2DV z5A`hGW{G2PsowVgyu=$d?L+Gc?e<}9+ZAshQc%tt5l#tz;M5*`SF`Q-YmN?1)?a_+ z4Oxfk79ZC3`sPuhwTV)?P(htF^XTul1_ewzk){);_G}|NCZUcW39EB&XD1FaHjl zeEa+6H{U$=+u7Nj-PyxW2u16gP8u>Z=nb64y z$k;#eGm46tvAW0myJs^q)ZhQKF*EQnGmqKW|F8R4W+wRghP}&t$6qIYF9(^Aet%o- z{8BEcWXb-lp_^F0zvj1@)z|O2A22J4pMUvkHkiM_NB6UTKCQI(a2fNd4cYnx;3tf*iaEVMQ(4Y#+48p9mNqM_FIHQ}hLQ#iHRbLyI7 zGG(l=IaUKxt&O^=+T0wQR^Jj1Max@b;b^p@Emj>1#X8)atHNs|v2a!R+>UU2OwBSH z4%x*zr8(AAUTkOC(I#oj>&_0>i;^@nw}jP%5CW6iD2F*H?2i>SC- z$&R*$P%K{Nx;wy~nh71)j8D3!cqZAVKe)*NZ&UQ}FAR2%DP4J%GoTvWZZ zwlN$#Ez%m!DQyY0Hs-v|fQhyFNiVPUH6b-|7+QX!*4zCTh zHASLf5#zG69kyMjc-!?Yq2{%km8Au;C2OR^vtmb8(9jUYArWp@bVW^}*4A)~qABc% zw#O8FN;K4_K;C{OMFo}dty+RTA#?ADhO3(!TSG03E8})R$;l<$KzVChN31f^5`r78 zXSTK|vbHT04Ht2LVZ6a>6}J|Ob)j>@rP0XRipr&u(iT}4juuDOwX#K(<;$sjCwGKe zn%6YfyL+C;ph+u34br^Ljn_CwcV)9{vH+EeH1bxkQx-Qzamd=fWotcoSB9g_kp@vN z{*g{rnxxh_q9i&(^($W%+7LoUq=M>e-9>FO!SHgg!klsw(guNFxrutd z8?Z-FQ1mKAf2iD*C%3lBfS=d4KE|yO5L1OOy+FWHiXxNI$C07q1Fb}RE-c_ zqoPs#!%g41wmCkn$WBYT5_>Qbt)YUbF=*h%P|NbRaFn}{W2~~Mwxcx~ZftHxcje^A z%Ar>}+?vSA9pMfblxq0(T2zJO#EE$=#A(Y-iheA+wkA>wnNzzc94qWtgEJYo;)$y4 zP@~FQ+hd_tbkmeOb;RD>L-u)yjvf*baY3l0A@}(iFHuqZ*$buEPlG}kANt?9Fj)h(e; z^4PG<28U?4xig$SCvgd7v{Qj)kyfn^x`B9xs0oVXDXZN!PR{WOZAw46I|pG+S7|h~ zHe9{FwO-cDPVHo%72HW$6_*rUWEI~d)y*61hJsG)B}FH@mVS0p+-}tyw68+dB-+0+ zKcy+dYm3%2^4_Uh^tJ75snDUki>h&QbbGC8oX_0IiasOJH?C-{k3^#-(P$(p&yGsU z8XCND4{~ynxJC|s7sqx}C|VGWhSoFEBov_oV2tJ5|*D5CBPA0@dQ_Er!(z|WRC=7Kp z@KS(%3Z0`{LXE7txYQmRa8KdGJXI@B`62Yd3>{3Z?bA7VI9%JgN_8lqu}S=}@sN~c zC>4{OPC8%~<&m}pd5LqnvH*qaok9^t~AQeng=YF4NdH>;Z!j`u{l#Wf#N#JBqT z_M%t|&VwzqYXv|t3OZ!J=c&2GnFvp%+}rl7*BS>9eRhw-ir z46v))!r=zd?@K+k0eP~WoE%=oA_K=9idI>n5&P>sZ}^j)ihy@+7xMN;Cf^Rz3fosVMBcGvFJM58*$`wrfRtW`?NF6)pX*+Da7Ro zi?l;d!IciqL(y}T61b&fE2<02BJDAG5m&yfh%Wd@ThiLl7HMwf=edH;P;-k-ty~u^ zrQu2mAJ32$JEgd}y*`2=Hm>P}!cLCbw6r8Niu1VS(qUd5=7`E-X8@agpdyP%tVM!F z^%94uR8*FoT1ms=<*j5ABNe+5MeWKu>Xba3XqceUB_&zbvDPkeyR>Oz>=~sb%WD=@ zW8{L)Nj8~QUpnp!;6|`Xr7UgfXm28bbi9+rCYsB(?WqLxHU&i#&1)0MguP8!$TCuM zsp^_YVMY-&!JNiZYapcgQqAviI0@vz;$8! z_^?w_r^3(7ZaO;(*|a!^v~%>^?RIr+ zWjIQQ5}k7@n(HKDs|pLMsIR1p>ZLdbh{1)e#SIuuSubu<;ToHtg*g!x`BgV*WRuzk zmUqNJb#1UvL;Z|M-Pz8q_w2cIb7$quot2#v461kA?R)Xrb7tqv<2T(`54o_UqSP=9 z+(C4urHm0#Eb}}E58$ls{E_jRg6`bgo?Yw|9Z9|F zL0``n-Z||;*<3rDNKIm&aX%6(?R`fHV|2Fi;K!3lYpA7x|&}Tt^uc99d{k_nS ziWK%xo9xQi$J=99#;d$Nc4fTD+hbS8yP=})Lsqw$g{gbC_W0Sho~)>{-KlJMDcch| zsdj#}c+vFY>1x}(r_``y$G+}O+e&u~j}%SMiafQlDCJQ48yHW2hmL`Ev{SzSmF4@b zEZ>K+e7_0(7InKvsoNo;((X-FzSYK!W`x~X)V+Iq$u)bniq?D^Ey!QQzB?Q5!y*dG-c{sv>g z%-+v?D>72U!QOdV{4ytg8IPZ@#QRn*@)f5QXOS#TE6qagern?izj1ZX?RSr7?5^>j z_ul>dT`%m)5-~k{OF3g%0)~j`**l?g3(C#dOxDCAY%L38tAo|CR{U)TiUP-2GyX<_ z+Q4bYc0J2sv-rPtEW~5H@oNx2kL9wttcx|sv@J*<;x=nx=N#4ueFM@qvre8*3%2T@ z)6*v6gpjhH&A^Yb)A38e4}XvNc6!dwe|CIT5Fnj2bcCB{(S~8%n?`r;t4gYuSFETh zU%sq1JEyR`hB3>yFD_;d#pGMY{S4J`%#X}ie1E8FUsn(+$GpX@hT9`89ds$geC7jo zG1!@I+RNYHnYR7=FWultYpw>tFwF1r0xVr#TvA(IzHCuNNo~op;*w&N&3w#_DlRWA zEvYJ5R#T4A^CruD+*7#Br~mUX|MtDV_GG{dCvJW6lcUdk!Y&BgguG?D{pPH1cV4pS zzU`j0#w8%2aM?zHs)$LA+GQ)27M4_HQ@L_|l)9HnuW zedW@O~P zVBB$Den+b(MF3|NC&i{s-7QnLFZ+u(#X7QG8)K%Q9qDrK8PmHV`&*R{dAYbMiN?_8 zIAR>DHIKhI|BYq0)_a*wIb@PlHpNYH{hu!PO+W4aQ@lxMQ@!b^(RivcR;g{79mAYT^&JLZX=>BTeCylhWxWU^G%d++{AVdZnb+ui0(wx%V5TdrmbJIXE2Wo!3# zW_NF$?PWGZI_NHVN{V`bo_N(eJ-q@#80k zq4r^(8YGoclEW|W{MffD{T0$XbYIZ6qVD4)5B+9zcCxcIXEsIFhG%xvwRW_Jqcda8 zGo#_QNc+tCoLRGGt;0l<#A|Zq<<9MD0OIp=wQc7#&TNR{PC~S$xo)N%>uP9pOy@(K z@dhb}`ug^n#o@Y+#@dpC!g5wq9;{hfotrbOh)Nz@lp8FXSu}lmum~5fjp5ediq__? zU}sLwj5#y1XH?WwBcg3Rrfi#H!D;nJ2eaqTpL1N!tn7Kgns8UBJxDVIQCya^#%LQi zLfayk<_I@1!`Fh=tF6V{b|hL`%Z3@bE->tUW!T36!)f9GHa0c*p$B85`_YPY`fYA6 z#Psk=OkLt^Dl2Ok_ZYV4>zqMyK639S_Ml;GG>pnRl!)0oJjL96fk$CY;01m3K)V5* zi4VGC?=k5HxX$N8NNQTDs9}`Sp10M5xYz61ImQNkryIr@xHD@Hy6uscOwXdvLN|8Rveel zr?IYoA^xPc;tyk+540z(My3ayCwTa~rFV%59V)^f zTr6*G2zN32(u(>yq32I6D(dqR_lg_#vsd(=jK)c=#UI9ge4zdC3}kxH`QcAoKlDCj zN=-~PHjEjD^hGaWP~EY{FgkU2#2LD+txn##vG48}=H?jYgWJlQ`O~q?zOIHoO8Sb3 zSD(nIH^OXLvpCY!LEr}HDr;JbI^`U$ozkgyRbu&h`gG_RyAZz=+`y!U zH(2j561Z5QV6Z`I@&>vD!&q44Vq626f_t>02ty7?5yW7e7r=r?qIC@4J-%UNia^!!6Ld#TtLWiX|?AafebC>p6yEo%^Acw(w=kdiBVi$E>uBm7<7md5T#2r4{jy zRK#1%vBpAQznRea)*fSyI?_t})Eqrxmu2NzY30*z zv5aFy6>juYVc3^eh5JnGqy^jFdZ)5@((iv~8HbAE{TDCZYxsNMIsoVBJ1`v#zg>*U z#NHGf(1tN#XeJBz1F3;PAT2N?kRF&ASP)nkC<-jX6qFOF%N%{d4Xj}F##2XMP_SP% z=rU8-*sykgZO~X>+Azt;6ySffE~_0IUFKQ)X@kzqq8y#(X|RDC_vJwhP(~WQz=(09 z(+>?y4P2g&^Nw$ZVT|?#=BFQ@z99XCLlz#=8bDIe&GEi~l4PVY%7{-!TAtJ@54Hv_ z%@2Gv-`bL&zCC{!dgDCDhPCA)gN-yU%Rgj)Y^PJ9xb5`5Z2JNujjd$ef1q{m!)RLn2;$Qa!z5InjpQ+VEM2BH?w4Xm1SW{icj z3h=_tTFl2pSzz3d)S>1WDC=|Pb%pAhnL&3VQVhQw{{qOMDpJhfW0dR$6N5#{fecX~ zd<3L@E+I^_Hg+1*^zqw|Ajt*=!Xd~ijs$MPc8h|^ecbX|{PMu9pT*8cyjy;YZ3Y&%tjV6mE(dnY zXR&VJAbu1m{(8vC90|M=+cfh^f#UCkbjxe8dw~ln5`p3$f?Ujzz>i~liGrWOc8!9c z$My;Zzl?2qsDc97dmYlPub$!KrME2d8Oxh=$WOJXFKOG(4Pb_t?+S z@CXf$)bJ<`kJfOehR3j-p8UpYc$|jEYxociPhj8j*gKRx=D`6ieximC({PrCCuumy ze&De`S&KiMz2b>KLc>!uJXOO-YWOJjj>q0K4Ii!HV>CQn!^g5eNPDZ{#-nh&q=>GU z_hX~be~pls`i)WOUnWURUQcmHOH8MgQ8-@cM3)I2&b-V*mrs3NCJtEY;|OO;OnnMr zI`$}j8cB3+(@Emi9GN9Men{d`|4qCUsn_k(O%mc0PtBJGk%Z~AOX;aECCu{y7S+c& z1mPn5d`C)&PJm++j7ucs63-}5nS3WPJQD_q$3xZ{*jOm_`BI+?J;lS`xl*169$`Ah zN#emCE>o$pcKQODK2N4cIe2==m6Q&W+krfl(nB^$xlYPUrMyAP2c&#h%Euv{{0e1$ zIH~aRqP{#o$Wtjl$TOv!Na=y6OF2u**-{=ayYl=X&!BuD zS4-JU>4CeXJYUL-rQ8DP*e#ZJ=SsWSPuwnKE!l&tm-1#x5Bx1DsXYk4Amxvwd=1jE zUnr(%@)YI`tcF6C^&Qy{p&s?crAoa_neznv$Nc{y;zfJ15Oa1*)zgOzNFZFLq z{qLmy4^r>P!AJRyCrRx?66KjM^-H9FxzvZGzFq3qNqx7}-y!w8rT%%Te^ct;mU`+8 zDBn>ek?&ZN$oFWeUm*1hrGB;4N2R_~>aUghJEi_^seexDeq+8T#fkJUa_{B;yY?`Hq(u{S1%C0G7w2AK>@|iE*5A ze4@lSo?w>wFnAgv?Qx7bWR78vV_ffW40{~IILENZakj*YJ=>0*-cD!pad`9% zR!XZ;zZtP`S4{jpUccJoaa?O(-FY}6Dkw@R zeviC{O8%@yhY=*cH729D7z#s&fD%YYRW0ox=70mJn0oe5h!cnLc(oaELy_FvYA|k z^etE6c#f-byocv3-eR7y25$jT?PF11`}QWe)mK*&ucv;Ae$-DyhI2f%L;K?a*w46NGQ1@N>@l5qrStgrIcU>xu$MaW>= zqj3>!BbtXG&fDLW+azrLrP#L9kpAc3eba6vQpj)(q{_Q+2*!Gb4c;CUr7?oKMdOcQ6WbD6n67b#lsqJzC4g~UDJ79Rm zgU;KOB(En)ULY&Ed@K6k(J`aeV;gvMtm;AMJp~>egL=?;hfZRQ`UE}bysv<_UMB(T zyw8*5tqUfX?=Qi-3i;^a`%tLu(ssDGw$phpYrLO<7t~3>I`6MZ@(!7toW1!;@=oo8 z_cqFCDCJ%c-jNEnH{ZsF%DV+T{ErK7L!ST6t8r~p3Ejz3k1m!C2QN+G?L*y`S1|H-zgd| z6W0#op(mc*7ZC46jd!fVL-srnkM4V@`4)pW4|=j^pO%Q%1s?E)*yLd&cxpOQ67Mq2 z-WKpkPxh#u6cX{aDZG(_mXLRy!ow+theY;vD!kGC@OCS_Ooey7R*(C^v)ehXAKnkZ z%SSxb7pH6G;z%jykh=)@)4~ckP3U6pXybr)zg?O@uQ#%id?B!2~{~?xm!#PXr zk3Cv_cY^l;9G7@xhXTp(YP>BV(0(Nz%}h~9#Jf)6jT5wlyxj_q+M7ZmdygtSy6;IL z5$^{I52tJ%i1&h4kJl9*4$(e&A1J&j{qX*x@a+C5QN96rPXKhMA56p>ukdg?fd}Hf zrPX5^c%&zL(>P0Doi|J2!DV?!WN)6rgNyaa%U5`Coj!SG3XkrgP@sJ2-aPsxr+=vg z&)#30B>&Jod+HB^5}ys;NoofRJxsBo8gF+t{4)VB)V{vGKGx!_XE4xO208O{0{fj)Zvy-M zRXV67(SG~WOLQ#T@08LZBU7kvdAeoc?@DrZ-*0)kY>)kc-tu&l4fK|$%XHt`q=QqI zTz$*arSg)y{1f24l5Y&s^KkaDT92aP>S1tR->mT{k!5g7Bhv>}5J^S<`^iBvw*&oB+(1fOZLQU_6dK;x&%>kToFN@HXn{_y!k_>i;J7bbUej21%kkbR9vDj1@?IwbY*?_4J}N@z0a`3#I-BslP|+@0a>#r2Z#T z|1+uolho5aDatpUB=S9iB<%C~ROshR{b^F)LK6BmsoyO1JEWe^_rlJ7QvW@vf0iWl z$hNP5d69Ew=QVV$%~@jKZZ5SY z{m7>&40JD7umtaC*dKbJ>nwHu48ut!UscEiL5;T*$JgO9P8B+@wGSSh($s9O0?)qI zRPE`!o#4^&tB2#EQ0+YqUb9XDF2N5~Y_p@L!mlwLjSHtkqc+zn@ODC%f!`4PDA2VQ zo&T^eoU!s>z{8>B2{;7!yC|wY1&OFXB3mdA55(JypURsE-X>Ixcy@V+cP)O%%E|X8 z^mB>E=y!rg_JjCQco@8s#isL@+U-94R9-4F`HsU78^o&*wL0VTAc8YS&rQ7E*zCF4 z*>i{(9C(cWAr%6_9;44Njx%Vzv6QRWCR%T7&+fvE)DX~4+A_5@#sZ%gXBF-)%PRAy zVwI`0oK>QjS(;VhFU=UyEY^1_yQHW4*%J)2EVV4lFiTTK>>t+9nonLEUyHLbuGu)c z)Sur=YfP1P8{2xWDcgE+@1Eo8dwWjQEq<85;!|-J59JmMdS^+SJw3i{WO0{&^2%LV zWm|W3_r#U;1CM39ej}U9w)T8~&lb6g)dhNae$P`;d(zrltcqGG&9v9z%I9l#J+-oD zg4pWmUbt;))!$ar>TPZsKVP|Rwp@LzXM&MgDAr=z+A{%e>ge+sr5lBnze=;7TDin{ zYGnnFv)6uW;b>8JYL%~fLY2RXO0kyfGOo%m+_QUChQEWVXNv>n-HUIo*xq~7(jAMtdv98X zzbREI%}=dd?(;>KbuZsh2JN%GCv&-QTjh?W-32?Abr+O4XlU9HkD?ihf4h^p`ckRTm2Oti}v5NXLo5v z%Id0UwrhIl~ zd=etB82Wj|`Ag8I%q-3-%__@UoF#lncx1YBgapmX3|~_vKbnU++EdV~sm;OOVUDJ+ zyfPv)ds%*2)(9z4pHYiAnvZ4ti@XN<<6D!5)gekN)w)X5T z!*)P!FUIyzxm|htUDL(B+_R_n`Jxw2>$Uf3&z>u=*M@vvetzlhV(hgttfc4mAU)20 z2%5{Vzn1a+^{k^Um;3Acj%JzSGsP$q`OFB%XP}WDX8R14k$64B%d*P1up2Y5k5WUy z-nSi#W!Q5W+h|?N5k~3O;#4YKdAAkvp$943?c;l#a=mLh`RblMv`0n#c>WVMBloTS z)G@>9CDl6ODLB{{c?q8!>1e*FI^u~(na5z)5o3LslUm2q9j(0|&u}zfR2@4Vi-TRq zZ#p@tb=>7>?K#bS5A2dD%{08(!ku zoD!FEe7l2}`3tiuw~C&+d`Efr6tvbfQAYpnWy4!aw_>bkxVo~fbk6I+*|KzN&vaW) zXS5!F*;a9mo4m3otGt_fO8@8TxQJTx1t;gld@QjzBegNuyU)><;4GUKGOK8>z36C5 zyHi5!hE24_thw%F8uOHNn^h^R*_A;9{q~g@acteLwCC?bi>dM}YiTrTQ3VajLNMRwEr}|F_o5 zt;aiSt(co@!tm?=+FHMM+3QjA75Jr46B#wCnY*j&<>&*R)Mn5&%Ad)S8STE|)Az1E>bxuu)wm7W8iubo z)vm$v!o{^Ur&gBK)}V5h&oC0jU|r*-%WFzd8(&HSLe(l}TE5hTF*U2~#6HV61g%K7 zrDYM{_)Ami-mQ1atE4cbeT>$2AXGdlgN3-TzCI$IqZ-TY~kv6Jo_hwuV%~F*gee3w-@+T zSF?Tfhv%EWoUy0Kn+)c8qD=pE+iqWTnr@k#YREZFx<@OW$6lw`n~S;vur=Tcz)nUf z?h3$ucLm_1+}tj{`J;Dl{=?)op4`l!y|@*hOpyf(NB0f!n-~A$Xry*BNVl1OvY;N) zmt3^sYoC7okS9s+(9NK2MYX*0={-ds&B^$K*RpLuSe^!oua4P2888f+{Rbu z#T`0t{DD?KcG;diFwnfXn{1$YahK`NbJOI2^agca+@)&s;xySP`S!ZS-X^zKKaOj1 zdqrKX$!#mDU)pQHdZ?DuDs~sU17{UkmO)#Q4fpD4gn*fYgKUC6J+W(%&L3Mx@z9{1v4JZh+ z2PRmgF(kgb?5vzfOER|82RH3rf!18~B!Xh2o(j4R%?({@qAp5ARkjT&OD583%6~X- zjM#zpH9GAbY$pXDtwW%@ll*KvwKCP&FuoG!ags8qes|Nqn%_;M7GVe6@92@M|3CaL zH>a*S#v7UHY#0y6`<+%@DKHOcA_t;zoQ{LW2YSG{tj>c9ejRA&*xEp zM_*7?Ppwp0!+4K7oEkT%p7x32Y4&{w#nbGI)4tEFb|Tf&>{LmeS;gZ|;|{cIQMLzN zmo`DV7JcoWzTZoMDry)hCLgg&{h+$kSTmUqoABZ&-(x|^nLf%AZza*YDF<{!PY)^{ zbgogLxCWM9=)i}lC{SGuW0vh4GG-9{1K-d70^B1F#kTB1lc#5p!gFhYu2}iUBp6%c zJHQ?kLf!|R2Q{M=smZa}3%(uCzx$4AVmgjI=yWY+P(A2t1}+G_Urxda>g;;@dU|Oz ze6DlZ25l3@bG)qfr5qOXhpMI-OUBsu$>}`h`Ro!D>l2W=>Y{CGqII##Ci;AnVyCl> zG}Yn8997#9t6tw)uWDkk%4o!64Bxg6H)gAxC}}))&TT(?oyury!&ffqL$rvgQih15 zE$NDd@##i<%hQe)2aVG2regOg{qArtq=(#;*vSOlJ&i`B<$2D877tlcn0cU&v<75) z&>d+xo+C}RGBq#N)-ZO&?SVl(+MY@LL5w)h!xyXiaXcJ~I0{q`r!l41!=Y){Jly*^ zG#X^m@vPjLf$BUbTgT1mh<3E`M*$t*?V-+aLpcUSPNKMDgGL>S_osUyy)&i6(wS6& zQ@oHapp;meTlClC4<743(8HTjWO~pYGBt8|BR|X@!xzmu+G6rE?9|LuYs1(_hfYGy zpdLbhjvw;C*Ee9Ixu_-ToUP!MUU!dkNK{hwB0dUoS0SU$+Fyb{cwgo~_rq@>(}T{b z%G`dqqit!py*<DthT6|jZJjOFG;;=0=H_PbD#GsQBF=-M*jT@| zfh=jA_J+0bx~@>PPNQ`qhoV@t#VH3Yc6h4*O-!#t+>t|f?UnwQ);&=my%?;(BLV$C z#~;RCJ#6qz1$2hvYv@7x}4ZIH(iZ(XXaVLZ-nd8u)OdhGNXMl8Xx6V;9#eqgB1 zjSC038QrmC_G2*Q-ui{Zh6JRp1YW!jI@Nrf%W5NYeue9H_HU%0bg_eRlHv-Ggrd9Q%!M#a6EtTC$8$T-r)bIJ}w*g-=6*jf44l5 zr@M1y!qcnbJbloo%Iev*|GcN$&(-zYn=7P$jo!RgG_K<5wAdJ3vf}TcjUb$7(Qfir>=^A8}!WRvt+6_A( zwWOszWdSUB8%`RA?;&%TWlgh;-}$i?vtjH~i}lw-zqDe#W@cJr8!ao(O8dPvda;#u z_M_IMv#il!%Vx z-by>u$|$hX?tRY6m}nV~h_=kYdDPwebH21vUWAj*A@5sbH&|net+B+_?Hjjx%75SnMEY6hT0hF4V_9=ved9M)`XtNx`2{an#s|WI@B0@imasFEmIpf}+UYu6^W})V(z2~#mlixW z%d$SQj7g%D-n~EMODpAbRLXhLjTf!4(#KiW!~aXdct8}AX64=U&zI+-f2Kmt-upV= z^KV?>c;~-L`ECd#F5d&5_B(K6bNvv1g37lXC)**TtV7DJ)D~;lbSu?NAM<_d7+Im7u>)KMsKVheL=x~*_iCu=v=+OHfUiMQI5{W{k1`h zY)BjD?5_=4H$mDsb$@Np)6}v}SM9HjiLQ;)_SZ(pvC(4I!pQ#kM}uRd)2!Q18>Nno zjb`zF+Mw5CM4LvqvvXCpbFY`J$k2 zhGC5M1?Hz8pT594;gE%gv<5JGQk3bolD@-fj`sx=J0p!zM!YT33VY?j*1)Ctfv@IU zTk_Ml=i^znlsw0VwdEp%jWjOHr&TrnaoYn~_60^7TgkTn-}z8m*!yIlcKes#BkAO$ z+^f?2@~SUr-~T(Of942vTd&Wf{|nkrmg5os&S^h-(u1@020r(Eao%?z^BSoC{^Dx& z@0^@-VG0IG>FIn>gGD#Y43?Wt!yw;Se3;fA>R@o=Kptzk-)i^AP)k&gq-b{Zcju?#s?}$!JoBxcs*RUEbRvQ9NC`+aXarU6$J+Q9NC8 z+aXarT~6B}Q9NBL+aXar>Fkgwo-T3ikSLxmU+s`6o-R%8kSLxmJMEAto-QfvFc|T4 znP-PY_URJN4vFIFvd9jJ;_1@M4vFFiN>7(Nc1V=|ABiVl6#h%Aub1F%AU*7)uN{7b z!=lBxZI{zB1Ol`~Rn-Y|NmcydOC~cOyl;YtI zgVrQe8On-!E{T?%vq{>bX>OCyidkNgvfdMY`2aZ~&?-STE#dk#L~jJ{g$n?h;xLN#ss%ttPVTzD-HxnCbB8%|Df& z@O3mwGTBK&?`qje)VGL;1v5;0ldwX~-o^Fk@z_=l)Lrpr@)aT6W z3e`0;BMl(M@Z%u%233(_{vOZnxxvKqWt2mPR1v1Sk5Vvsr5#Mu$3IX-Z!b|GoDVsY z00Lp^;DZDZ2-8{?b}-Ep{_SozeG30xxSL-Ji-3HTOhEh&J29kbTI>o)H@(HWf!*{L zyB?T!3c@RMRw;#BrLw%q(u*~`FgeN)-%z!;A3 zV44B;U)UPq;57C=w(UWIX{NE?0^28H!XE?EePRlPKZQJ=BY{oqz!Mal2E16oBY-Ou zJPz32$EG=iWdXbS4`EY*-TDq;#{yH|NrCvez;vWgAbdRV3;{VV02U90iuf{MxBlsD zIk1~wI$H_s);FD<2|U@cm(Ci1=PURe;9>>i&Z*&l)3{&yt%8*rgx ze8*wwG=6s<|vi{>>i(^*jQknnu2m4s92dA)&9*psT2m9H59-PX) z=fMH?ng^$`-+1s4h9QL$d}ca3+=GX*lRS7BtMTCBtj&Wn*cBc;g5Bf6BiRoX8qU)2Bn<~Oe7J@u zYxoEaPtovH4IioDqcl8C!$)iQ7!6O?@Ua>`PQx=aJX6E7*j1kP&em{_hI2KXr{UQe zo}=Np8lI=&`5Hc6!wWQgf`(7j@JSk8sNsAK7ihRp!$le{)^Lf2OEtVm!)5G7Py3f^ zc(I0;Xt+YdOEtVq!^<^Xso|3~T&3Y^4cBORg@#vZ_!JGV((tJoK25`?YxoQepQ+)q z*lthz*0P5^_z*3AwT43)uG4V6h8r{-*6q!8VzsP@UTu;G<-Yzt8VGVwxFh0tXSi}!!c@j79_#v#s6Q99Om$;P2r?Z&EG!Zb$9LcVhxQOG?>`sYk zB4ZTpKRhWh-IyO`j$>~~49KXw?|I_Kvd<-^Yvxh7pEN8$OtEa;D02imN@7u;QEaZn zA#g_F{!yvKBEK<=ptV(eFgg=Aa|XgF63fINooDN*d9BOEJv6dM*Or;MAR9w+ropKA zl%DPh5s$9Dh)3~+>Dq%Z-LoM)S>iKE;^q?#x1IbEpDyF+o*MD#+KtlFH5*}SC&GtI zJVj!Nuoj+aMP<}MgM)v6bDPhW&@R1VR?Lhb9NYC2| zJgProy5?5PeT2kxZ;#^X8j<4ZS~(MA{x8%XZh(HF_E5?FwYN>yw_DctCRty)%u)S_ z+L79W?yXS!*nV`9#Q8Gb_8;1B#G`9tN@wp^x)vr}LJ}9s+|R+|`x$zDKl6M}a{Y23 zyFu8cd~LtB{Y=k?{Fr$BxIw=EEDyK&5HMGOa1nmKE2aFJlvhcK2IuitONoZ(_!=p< zOL?u7JEZ)&l-Eg#o0dG?4N~4HC3Ya!<0dATH%obolsl!oRm$7&&>@xgSB%dE_#R{I z1_O#;OZ{)8{&B|E%6gqEL@JCM9xA?bWY z`Y}=-s@nU#w6|BE!#d%=cNDFOEB&FJwKn8)T!D$C7>E1yU}Sa=DbW zza6`Ol6Jo@?czA*b|JaHL2`eC97*MZ3`$9}+k{V&vPep5N5}pr(*ASOKKci4ACmhI zB=IXyr3c<2 zXDA0*EY zlII8M$?vZ+zvpFs=vR4ukUSsACaNFgRa9Qco28_=1;UR@`GS#xk^f!Ya!ezCEvfm7Xdr=Kb7|PN&7f2aQl$lKOnh( zke=*7ZjzGM5BLs=_egmkq+|c@(*BFmKF&AXJ|y2iki6X>c{@S!c7mk26(8htQj*^} zc0ZGLUy^ol{^E8ad3ho0s9hkpQF=(4`yol|qLO?F)EXMFY!(g?9q37)k zeFtIa;R0NLpXC3C)T0aF`kzbvTT;)<0Xyd#h=-kvNW#u;lF)xw>YtSQA4>f%rT#ss z|BKWQp?bj1aFVb?bDm`9c&Vr7iAaB%)VD}|o77(__18)LO;Ufq)N}uU{qIZte@p$J zNJ9TtsZXc=7x~g08tD%wiF^yCzDDX-N&Pyhzf9_{l=|IL|6QqnQtIE9`aekhCsIEa zgKElm8cF0!b2OB1fz($^{V7u4CiNFf{iRZWqtt&(>K~B$=cWElsefDQ|0wkqE(R#y zG?K`7DoK=QuGBA(`ZJ|IBK7T3e~r|CQ|k9f{gYDvBdLE?>VGTsy;ASP0G09`PZIea zLlWhgA@z%-{#2OYYB52fC~#TDf{nk4caM-t`9 zmii*8UnKRbr9LY4ol<|f)PF9~1?u~{TBe&+a9i7_7L_$Lx$T+8um5@TG- z@lPebTH@Cw?w0sx5@Wo_`8a5Kei)~5{D#CBFLC^)#2Dvr{0oUO9^n`VJ5P^s1jqj+ zG0yiKzb!G&uN?nUVx0dten(=QuQ>j1iP70`{I0|}KXCk>#OTL4eqZ996913Hw@Unh z#J9=om~V=E2-LpVt<1MeVze*EcS?-*<#@NmXkU)^NR0O7_%4ajz8v2zG1`~odn88t za{Mic(Y_qtD>2%aV|1<~s9b1Yj_;Qk?aT245~F=N{0679t$ z+KEfF50_{cF3}!bq8+$I{kcTFxkP=rL_N7g{kTNExI}%pL_N4f`ME^7aa!ps)RbqR z6I!%*ZrQmNaZlq;DVkD|&FF6qkMlf(OX^%6naBUmj-$wDJ&8DnQ|9u&^Wur(K~Eyi z=alSOLS%EQ`s6KfvU5aiE|0aJxaBdTDA}_GLFAe(vdx|+lp=>5kwcEGp0JoB>XRd^ z{-H4_AFs3dzLVjJxkcio+XTB&l1+MX9;uJv!p%8#ic#lsk5cM zY-!K-QQ7e^+ZC_Fj#Au-;WF57O&O`QW^( zPWYg_8=c_6cs0^}5I&(cuFlE_4CS|(5~p(?Z1=_|e30Fxs1L3u)XE3d-8lWhbT`KH zAiAqg_~3b5bo_(nGwLI)?Xlx$w8x_KJ@6TPA(h(Z)-@4(yQR4`Y;TLNcS=&It}Ytx zw4-9{+rsTOfHiwFgeB@5-I%tHy4KKI;Oh15MX{FJhHy)0JwJCS`+#G;3CPP8j@*Yr zOJB8@E~L|h2a`6TOWE{t-h`(6X@yslYVqPN+C}O=dXQzirYhR zyki`edmVe2#ybnRI029HQS-&6JF7~-J6Yp>418JwUaQ7i2IF%Q@HT6_&ETnZw(E;q zA)fNlyFK#~*u$*@50Bo#*_(j(w8s0ki8+7-yq{{k4Y==mMFQR@8qbgWqYvAKmvNMA zG<2l4_wVDlkBQq^POy_4t?_muK_Xs>#@h_XNW=?iyruwSZFXkJ-QK)N=1IsN1P^b6*J)>_=xP2zN9?ZrZS`zj?L#Ot767~4WTuj3y!F%fXe{OwPRyz&mXTW2H&7%g&{EMkWc~C(GrW zrvV^?5KJI-2s`Fg;^ZTGmK z=X=gd#xN}q7j$0gDU4w{Aui~=+rYzZ`M99-YF4@LMyh0;_qQZ@J5LqoTGbY9>-PQw zgO_C5FLZixyo@uF<2?c1(|X|&l<)jA@vKS`yvZ2YVcH`u==J>xc)Q|Q@$GV6ZF2br zS9`|?wrM@zr<3HZ4l#!5nz*3b8&ik=Ks``piu1MO_l$b)csHdF-p(X>?lDv8013$mv32;yepFA{U}LZW@B>YTa_g5rX+c9C&`=A zlwA3mlH}c!B=4g>cw4pOEw9;IKKnq{d0pV43ycdo?^W=SbzIPSC!C!e?~WvSL(lPE z*V+Zp^IZd8GUa;-JY*dgbbIq!lH=W$ByZ^2<7=BzZR`$$KnG-Wy5sK24H$Xe_zE}|+}88G3%q37 z@2B7$nS{O1z{9PnxS;2IbXRh`72wT^vxaMN&9A-!UTzY+N5M;`9&aUCz9H+~wR+U- z_44I`m&|@U9lT`r+g9)r)t5i#ja%Y&S)S;FNB8jX-w7XqHzE`J1P3c#vE^X|{=N-T zn#01z*TgfCbS>|b`T*po8gGQcOHp|A-jr%DsPHU>ccR9d1>ShXQ@*JRuUg}kfj3R^ zs9Y3CwrIRI@baN2dv2t<@>qD`+>q6&RK$&g+^EHjo;?l%TRbHX}l(dNBf@w?$4Jf+yvsD+N8rsuJk?{A!ncFDnyLL%PZ z6`p;(C*q}ayY}*gxrFwHD!keK@G=$NoPKx{72e!_cvBP}?LP{M>T#^Xn=fbyd3g#C zQwTgHvUh^QThI@$SmB+}53fSuVM>CBMETYzyp#IjouTj+_QPvXc=`SCS`=PEKfIX2 zE9{52QQ;N!!`rOziu>VRq3}xj;cZuVrTy@3Qh19LUZZxr-2t9`{9;Ox2ik8s?{V<* zp{L{WQ2Zz);{6@GGQ<&YB9Rah@rti;d6=T)ArbEig_qS2?^W>f5l{JIDwBsq_AUITcm5l{9G?}yg|UX$ca?uU2mwK#W4-Vy!q?f`F<^_jmACOWxFecxUVo zgC44fJ-$oSF8dUoJswNMJK^iDy=ndAdym39x*y)e>)d)A(+_W>!kgX??@jRR_Or*^ ziRzJey_>H+&QHYK4xVjqMnCy}sPJa?!z;eQ^*=iQQ=oj;S>E&GcJQ|Og#R7FS%SAk z<4w8Q9e0-Z!^=~6i~HdfE4(HB@M;uZML)a-g}1aHUQFRF>xZ{l;Vtinw_V{?_QShF z;ho$M??HuE)eo;n;Z^s;dsX4p^uv2s;jQS0_p!oT*$*$}7S~@+>4%r8@W}ruke|l+ zpTawpvl8?26y9n5@QM{4ret|Yly8l~v*#HS@fs8!rds>77gKm=DZJ~o<88CT>*|NM zUE!_ohj)j<+t3g1L4|i-KfE4=x3M4Is|xS@et7RHybJo_eXQ^A5n zi1)F=!zFm1yuT~FtNY=l-0J3wp)U`K@*S%1FjVc6m#OeDwCs~NQQ=`I*e7p_!ov`+ zPu{T#4@0*;d3g%&x_)>kD7@?Y;T0=940(7+)P5BT@5X+3H45*het2gnyl?cwYfyMN z#qyA-d@TwOU16WRn8MrH4{xKw!zK@j^4+ZPZtI74g~GdC;XRGx4gc*fn{5Ygf{a(i zk3qt4lm(^oUhqz#0x7}3_Rlq*br+sjhE5H{t8WR-h}4}uGbls$+_|~4a^}v;&Itx* zah>`%7@V6oA2AeG54o_UqLe6uG;e7uOsV?k_8!#aTzng8?Bub1pFj`pp@ z7k+M>w5>R+q}x|ztzlPPy1sCCN`zgt1#)s{uUWXY__zftSM>Hgz3+R)#}#fZyrgva zf|Whb?|b3dtO=c$e(vYb+2M8>Ldt({dhzj--Vdz~0^oL+nA0&(XMB|0JSU~7qM){> zpn6GdHm$tX;^G`;Sms(6=VEblv(?3U%x9Sq7tdxXmf7awIn1)mb6q@_`7JZ*;(099 zGTX&1L0Qy0U)xvJRQ%?dK@`p@s>w?jYCmUL$J#o4-Nt9e>?*Nuf+f>_XKQ2ojc;3@ zdD0rRzA&n}O=MeDzGzWNRc-b1(wb8Ws!FKBS9@X#ii--esovMbsdK3M+vC)^)C$+e zsq?5YcEqVmR@P9fd|i(y%%;Y4|8ZFGH{I+q13^M*Ke9+p5cZ;Vq@rb8_ACOx7k zo26UkH{#SeY^Y`49H-7@!z}ZbICUNyZkapd)Rbw4W!|bs6lb#$mU&y8I){z4%-iGC zxonhW-VvwHW1}ten{jH&G}AJ7c_LPoFRRIBhgs(CICT!ovdlek>RdL-GVh90<5;!K zyW`ZevBk7A}<=0kBY^C{+7%X~O4CVLh|9cP)3#7FT~ zm|>ZZ#z*mHm}!~c@kG_Y)+|WN>-$}MxRS5N#xw%9VC@#ss63MzTcmRRPqaWTAN6_)w^xEQ{Fms;j?aWQ=V zF0;%Z#KrLayWBGWGcJbj-%87T-Wzjri6~pOW$ufM;bp6_%opQgc-dB1=1ZQK>f%!2 z$+edGa$F3zw%Rg(?1@=XDGG3oWxnQ#sIDxpSyg~0Wos?-bv>#|M73Jx&-AF8RfUu) zVwpeJqpCzyn`OSCN7bwPKh>Wnlui02d}ZRDyue)ihM^SV4VUtJ{9LMwIB4M$0Qq~rCg9$In6U0z~) zb7O0`Az0rOiZa8`Kkg;@pLLD>#U&4nJI>4RX!WEB@F`rGV$-JXmMPnp{l%MN9oepp zF?>$#NVhcijOpEw{jJJ}yxjJtNHm5MGM`wNR%;%AasC_2Zmst+opQ(|seH|4ndJIE zUGAHH+Wn_^lQg$-({yiD@)|}xbjYOD?|26hKF2gqkjg*MBolO&-FNp()gza94Yx$F zQUX2&Lw92(@tdLHZ_WEv(W_pfV_Bp~g&Bva*WNN=cbe&P^MDjyXq$jg>u@n;q! z``s~5^h__FndW7CY9o`Ss{8ovuM}23_q*L~-ehZ9A|ZG~3V+B#W^mcsy`9F1v_(c zX3Uw9J)@$g8WC;l(Zw{yg461c4rb4vKj*ldS=sY~HQ}yMd$1hKd_+6ehFfE_T_1_I zMWR?PqJbG9(`mdxtD4hz)PU423|dZKQX~2r(28^^gO~GbL`Pp8>4?^cslvR*hLN2x zez3fWH~A?>mtj=K+{-Kb8q6?G#zG4Gd}N=oQq0X4v`6c!!!1?eMrQXj&~9vRYF-mt z8ER3L=Or)-?grheHI=u(VfdTEzuiXH&G-;0guH$xVHk7^B!$KJHWt|T5(c%6kfm6a z8h;I6_Atu|KWL@ZZ?de=ar^$qGLH6}CJOiquu|Bo_?w^xgIK^OD&8R47o8d^g>0ta z*Nc#Xni|H0p_we;52OYHfwaJoKzd+eU_oGEpeV3N-rk^+ao-+&!40fnbXUXZ3ksMq zlKBE7#*I!tG%z)Ad44)5IKi9aeSz{Ij{A`Y#f~&a;WP0L!#4w8jrRpeE501R@Q~KP zrTKxc=BIDTPv4$D3{9Ws*s!)-WU#(IIPd+iywClxe2VuI@|O67yx;zW{FnRXc5EBX|TEN1$&4kA|cl1;U4jP5zhGC7tBKrt|$; zQu}b)Ki(5>u~HBAYdBTI0nZu{K78Y(){}k+|1N;7^5L7q-uQH8&uJ0Ihi}4ocBJpqqbzO`V9yIH=Wa_wc@lRS|~a9TfvZ@AQBQeiD&@XwW! zukj4b*Jg&S#SW)U*W$hjNg9N2=iO zCJ8(Dkc9q+QvXY-r|;2_{u8MWpf1E8N)q}>B$02n)X$dsSaT?7xop3;=#g4p^Oi-#%TSV@ZytW6=Dre{#RR2Fwr>X zz%31zxVz&^JlSh>^;5tve?6*$W2GSSA^MSzQOFa*`D^7H*DI{z-P%9{z^87e_;*FdVg%fTy8z^l`EuY%W{fJf&n z)!vDt7z-xgZPa*Yf;T+@?+WNJkJn~LZ2>RW28z55+jJVV!{gxPqacSuVUI_s-@6Mx z_~?Z;@9&62x9tfyjj+e?Q}uyNF>j7)d)`}kLF3W87j*t5p1se=p3a*FUcTg^YvzG? zZ{Vlq+XUVSRE+GQ9e5z#hxn;^OiokbC57G_oW zi?c*NDL~5{6acDpP;SKVa4iov&BHw`VtTlK4|j-%n;Kcv{Y1#9dO2iPy%(C$xdkOo zK})ISJ%g9GXnIk1O4Z0lwBVJ@^sOv1_5_%*=ZrnOsU5cOEgC}cA2+clgT2FLdu-;` zig$bMt>yL#dD|9m?Lqr7pJ>bCOMXHv>mal&-+r&BXK(Q(!CpT{e*#Kuc{8^RdnVZ{ zzNE+hEIb9RA<<8O(8?0M2ZXkf=ucT>b0(g^j$m{j##RTb!+K#ItQ{x{97C@<6I)?) zc@b!5;tTgVa6|gHj)i!PH+~J`=b=xWi|4f)WZD*_4{@8duyYP;guVf3n^`B%rv+Pe z(CKLtaq972I+o4kPmR+%ZT}a`UXR1>Wc);roKo+y3g|?8}TOrUbYc`0N}@B2|;P}KW~_F*ooKmJQRc($Ec6nigdKb!qIkI zP`+Yk-Pc@>lQOm6xg3XF3&M7=W_C}>*U^ie6;VQtN!$t#ooOsCS0=T(1c4$fjvQ_PPm*q_nzPU zv2g2^-gGqK!c&d03T(@L%^bPK6Z1fQ&K$W!rye3jpEE~J3ZFW2lrrGVk(Tj^{1%Auz4Ng&=peNSJxY)_L8G=1eJ8)*8&r8>Xsmc(flyH9Aw*i4pv z(B^0`@}vG6czi2BRD|C}?PihTGd+PoVl{{y+A<1wgB!?Ejqi-Se`$++jgL#8+;D2MEm z4yDLqhq;VZ4Xexjcg4BQHFfi9+G^LRf@Z!`Zea(gF06#L>$3yKi#cWwm}vt12A* z=8H<$hUHszL5l@J%Ub55$P}$pqT)crbs&*`4uT6ZwM*R$J8hJkSuun9YdxQw{Z(Nt zIXlxh`BCl2ImV8|W11jVeq1~9Q`(WwYDYc~^3+oNIL`R)?)mvxntB`oD@ znN>AwL8~fU<~8LmwS2nt!K!mN+Yc7%ess_W!G#Tuo>s_s2&_gtkC_;&^23w=yR~&@ zr*OzsmUE=CsKz6#EX-@lJ&%>e@afXZ@{!ESf>wCl`o_kJnzkB8&yU1ape-4wjC#~w zW2)@q`1$V5Jae+bw}8;Cb?X>JddStSN~v44Z4_25W;Nwr%BmH5bZO1{L_0OBb&aZ7 zdQPvMnq{G~saYxZrT$069DI@Bw0p)X&o0WbGQorwZslC}TF`JEX?{1YBjp>vavqy+ zt|R?K5(`O3dhY-Ft4G6RB~UWs4qCEqXR@Yw?z1T@-E-YfBe7v=6&$o=y`z%#>>DGu zZM(^HNBU*6LkTuX+8C_VPaKjedm}-ZIbK+ z)xnX7=vYG?SeRdx#yHGhl%KgE-(QSBV#8nT}!QD*4)>pgXxKQI5bfVg^Wz{aupRJ~LasF%( zwTts-Yo}eDKU*^G;{4f4X*UuVe){>X)ZYw~`K516fa0gL5EYsBrpgf5VgRjqL;{&c zKVHs>YmFVu=yH^tve3+T(u`h;Mj?ur`E>mbNtAETYG|X-_#Exe8S=W zLhZPZ>93jrUaC@rUDsy)HeL_i&3p!s16*{E-%) zw)mqgex&ocNPMH52O@mF#TQw8vBj4-zlg*)#p0)0{4|R{&f=$A{P7llg7XK7k1hWIJU@RGp1s)svOUv6Q2mQTQH| zqaoCI;tHUIU$;n)63X_MJik_v^6L~SzebVr>l5ibp*lU-E1~rB!$L>#_NM>h_S5AT zkFgIDqv1;sCW(Y9ieZSN=;9Schoa~Rp=ey0mgMoWKN1;Q>q3A=T**%qIfeskiG%+0 zg|clU|6!px`9$%w$sB}7htxnkR@bTUNS6u^`XPn`tr6Or;lZnWdV<7%l7v52!XrN_ zJg5o}s=|X#Wq8mEq05AxCv=_A4WL2#P8R(WML)_(=?AT6xQ6q-V1B7TI>X+q}y7-e^8be`H@18 z7CI3$&{rz@CW}7Yf29vp=>t{zKqoOg=t)9P7rI0!%QetDQ}p5iQ0YW{QhGs`GM%8y zgz^I+`4fef3RU)g_5CiFeYQoi&$bM9rV(8da-|<~r5|#R6)68aDdhK(LjH)zpA) zME-k`za#SegdcAoQt08(mFZFCgm|&@MagSK-bxDjMv>nj^4%i;g2?xX{AVIp^|Q=z z{zv3FNncMcDdfkHBHkGyFBSO;k++C^gUGKC`7I*pvL@)t$^ipbv;c|Y_6jF=R}d8B62iAPO@0`{i5Ade2MUAw-k@H?(7TL4k>=B@Ms4VKTUW%uZl;9q40R# z6hB>fJSVFC9qI2sV>_$(QNklW#g7&q@hN_c@Q6?GV}(b2ibqG$5B-5bH2)=DL&_GDDqVlDIK#G`>6u8_hUz2 zdDT|v6Jk;xdRS==J=%GNH2~o&YbZ2cQA1()N;(NzTiZ^Ugd>I;a5h$VZWWJwu4j=L z-?zzzi3}IUDOfv;vsCtiZRY=y<$myYz~fM@u$tIaG2+=?b&P_HDjD%Gt7XI^yz7$= zjotWuTgUc}Z66)CHknShg?xXoacKGjr*UYOBe-+Hqv;Nu#xbm^ZyWe!0m}Cyy8wSC z?j`VFriVDKZyk6OcO97d8YF&XKPJ~YzZ}DyO%HKe-%a36eKQjNo_ZViMZv*axt+M! zpp`(P<=@1$A$C&etIt3`Y`e!T+&OrmQtvMo(8fKMkNxI4G6QSle$q?cM+^)vZQM(J zkdG|%E$xr-Ytm8{qwj|WnElK`-(T@gtH$G&N;`dvFn&jRi5eo0g+kG zp9PNd3%1Jz$i(GioS(Kq;BDM7S>jI35_fKvxE)#I?#UAOcssbmta5oBI22)qvvK|K zel$JNjDzT>mRtppCQsu|AKcP((JG8xXsJ(MNxKY>Hl&v0ta#5hOBMP~6zoZ(JF zeiMdt3UKQ@zYZ=EIp0h9H7?J<-7(33AD#i3ZZmRmz0$%x1KbM8iGy0@h`ZdvO_}V^ zFAw{VSyKE_8!`cvSb|6(P;&qskX^F=vv98a0@oxoAf zcrgS}E)I92f#cjYT^w$gfx}Qixj5Y22JWy9a1R(b{T(t+-$MotLyvaj-DBV|r4iu% z$10b{fMa|t7yZ4E@!Gf-fGZUohHlEm;nJ9NDTOcf^;Rgq{A_(IfLkFr4DpnU)3*n> z8wJ<51Kd(PybA@_uLIoOz%3OVhK$O^#mh4iw7vlb4xff2^=ct-yC7qJ^9>y5j?MbF z4=*%K7jeToz&V)L(l`vslw8hRIqQpl7mmaI(!k+Txj5Vl25wphxK|Avrcm3}x6i;$?*R9XfjhnfoP$K^ z{GMRoPD8n%-wE3LT;OzjCNM=l1Y8nVX%UVDZaQS9L(`|u&@*voBk|2KxZ1VrT3d}1 zygIX=R5Z1)cuJbC^Ygo2kczI)?^@)XF6Vb`UFM(PHKHcHf7i0IzQaKGfDQ(I0dxSU z^CACyuQX^r_)^dm=nBw;b-q{X-HHp#x0FRrt~y?w2UT%R)wTO?-ha!U{dZTV8h8TN z30l5v|INuIyK{DLzvTJkk~{M5dc5-bksF4nGokiA(RWYfLF1g#i z>+zSbuR@Ie8C!dYl_D*2J>*;ahixd|j?>3*-qzlWDz^8LtJ&KJ$<@E&`CDsohF2^8 zO~P4Vjx!2>{s=SY-$p=C7ATE_ZUlrqirf=@yi*z?HE?GuDV932Jvb^1_g)T;3PLGM z9S#y0N%f%O3?eTGpM+;MG~&3PIk0D>ikW$)1szpgG7w!_ z9crD0%8E|pL=$Y(Z>?FouCab0PMWH%f!Qj3po8mv*!MZJp{cHUV<=C2bYt5Zpw~1v z)&U zhh?oK*S}>}*}13{bbg&)8V~5=D!uXlw<>*g_gCpdveUlKs?u|L8q|U&n8aOt*8Fl+ zul?TpVzXXbs4lMDx5plTu?BrfWm64J4C;Xe+UmyUjg~OBNsbB3<~TEScFk_eA3VI; z{grYKZqXq(czDCAl#9?ctE$M{y6(MZRaAamTmhett$=H5HZgK^(?KVV3RqWP+fq-v zj1f5wOslJJthvAvZd$i-?cxiXY8SWEhB`2?fUQeWy?9OC#-M)3R^^yvuqwx6UpK|UMi(~%_Pb!uS-j46?@ z@b)u#=f8o2R!;e>=UwTO?VdZuk(P;^x(+AKYwCN!-1Y*!BMlXW7CF%sUytG<^#?PyC*r1BQXn^>FV=1 zaLPf}b~XQfmPOAK{}s;X(1%wfqK8)`!^10b{KG43i>Ez47^hY6Ins{91q|ij{P|U0 z@p;$oK>Rz?&u37((YWyA=NvD0;rSy+`($~}^!qqY|An}Wi76@`7l1jf5)al>0{rgn zE9U#EjkVsQsGQ#p{Q!KIumc3+;BGiCf@^2SFiCJcAA;A+Ivsi52ff~j=R|`)=%3@91U~f7arkZ-`s3gt@PqM3$MYQ)fMN-`a^%mz6-$SX{4&rmJ)ZjV8tO}_ zHM4^hn)sC3>lwzMf-NTOr#1XJp4IDJh~EYtODdEj{|UJ!aj~ELQwGoTAIvq~NtDl5 zBK}F|sR*B=?89jh&wuF6&yeDhh;MX+@8Oh0_&kfxxA>kG-^=2ATYMkql!*Sm7T?d} z`&;|~iyvt51r|TZIV}?3V2eM@;)huLP>Ua?_6UdNcet}EqCeO2A8zqSSo{c!KhomU zYVU3s-$={w8f9H_^}p$wDXCGzHt^m-r|q3_z4z&tlDGD^s_x4famo; zM8D7HIFAd@=bYysykf-9^AY|eJlk8Ir@$6II3EEEPJ5EC@YkMt;5i*l{-4FQ7oKYf z84urB84sUz^6X>C`^ojsH@FNk91f-SrzDXu#SamRfQrYWD}K&R;v4;Wq$3@tnM$z8 zPRX%|PRY?IHH*Ghq3Rq1=;zvE#>4$Vq&$}(2#>}_g&!^9kq#9ew3gvOR|~z5;lV#F z^l_o=fGGbtXrLF1@swUP*eYGfm(mNW(gVt8BMEvB!-IZZ=wm{EEc9v6KyQiY9V>cK zPD(GRN+&2kTyuZ%M;IP-htR8pe#+E0Mf73)yGkd@Tj>K;`{O}ts1Ni%7#{SyLe)NW z@GlDgd!cWF2I-w9`~T5Nunr`r`lmo8AwPvYj6>bF@VLzaxeG z4&-48+>krZn_xO7u=qs zcqM)vJS4WYvmN3e+a)@5@e!xnDei-^aZ3!O#_=80#O(mTE(SNl!m;0t!!5ON=R$d0 zycbxwJ;3dROgo)E%6N_LPPv7+cvP-QwEQ+)>oAn}LH{%peUR<$gTTZsKtZW7rv2o@@1^p32ql&q}AB36I^RQoSmdIX<+U2joz&l2`M3(W2JLCk*Dc&Tz@-g;eQD!{V9c2fZhDru zrCH)OwS)U#B-FfbHv)%Yc!sladw|36I>Xtx{{oI3c<%-d{KXQ~xdS*e9OcB>dzl{q zj&kOM`J{`(J!Ihe`>&oW5}e4!5RV+;jtnB5xNr$H3|Ki1G4#$2A7TpVtVfjg!H+&Tk?X_9vJZ8C7Woo2ivkq^&kU$z3L@0X}k zWD0O>57Q#N3AjiD3l_K5;aO1;91>-pRYY9vy7g@hYwKI|cGu4Kx=x>3T$om_^S!Pd zGtue2t`lJRKJjkZ2<&6+27 zsg8nFpIy0V0b)(MOWVUOI%EEOkrFT5{?4{E;MWV`C+1%WS zZ;)!pBS5`7EedRHSlv`#m-hFSrBw4Ec)emaieKLp36ZNB6A7_(>otv|ubcl)G{i>g zUf$;50}vZB!QMA$|K_4EEc|K|i=7fJZI0`yR{%kp8$*L~$O+ORL3*gwNfPAKf4L$# z;p_*_j4E$vQmQ#x6kOeauMRzO#Y_K);sVtwKo2!VApy*dp+Q=b%a;dRJcsAZ)Jl0; zhK@+@(1=8o3_=a^W@^pmt=%x^{(GNX-2b#ls2qQrXS*9igJgw8)XB!sAcSP3q!@Q= zc;_2K!*K6qV`vacWhAZAmgA{0vJ~>mgTA?ULdE2~Xtsm9!VnUyhgqZU{aD$;AN=v| zbi*-&)Nj%Y)YQ`fwn3&nGC%!lTrt6tjsz31P2JE~MAA;hy^ zleFtCo#P=2a+dcDKTHh8OK(Tf(+bOp&s1+HYuC5xj&I$2bKsdzHxCDfL|KL?A0wv2wuO! zo5d%&#(k{k{@L7Oq0`n)y99J=;rEYW+6s}hC0>u$Jon>%>Rv|5bDUq}w;Rog>eQ){ z>!PQ^sv*eWX#Blbo1*OFWbeQk2fFT`?SibgKb<=8Zc&v+3)xlnFF%;;?f*IJhn_Z@ z*duBTG1oVSn5T^)=6^7jm+NUn+@gs5ZS~SDp zxkkAx!Y7;$Mfjw1VT8|du8i<0i|=9axoVx94w8h8Ja!)1B@_7;-_zoIId^CBw@+D#B^IH+TXZiQD`2Nll5&S^Qe}MCgh<|~_4|0AV@gHpQhed4sagD6L!K{>A zW6PeNYh-(XdMU99hHqDXJ@D72Zi8Pk*HP=wlXw>d%t_*=H<9+i8aaaTom|N=7FF`T zkW07?LhFE|9)1%d<$0QVe@^6Yi2P3?$25_OcQ7f^GmI4ZV#}PwaJY~Z^;hwDpcIe#sGfsfvSt$gipR$= zexC}SANXrIZgYE%Yb8%xGiB;o<(uMrirD3n%FIt>nVp^qHV65#m`;0TbSejJ5n?zQ z5_FCkiSySF>Q#g~5C44jK1l2SbgnWoe~4I|VZG-cp94B`tUz8r7wnsC+#~|TY1~Ng zCT=D8u^J?PWXt3l&75-E@w->9NwoZQTx;Ew&jnM6Ho$fthQP#aL55VHXaQ~9ACWQD z_jQ8nf%k9Kr&+jjt#}*Jrd(!W$lAC+0e5p2xGT_R-I@h%JjMX8#^Bg*o8?k~F+qia zLo=(Kja%9dj(Icn-3;7h(P0uB_aoqznE<)AaYv(pW?9+J#$65E`8Ejr)%Y{hmq4G< z5QAgco4E6UOJ{+*q8;45mcDy|)8D>LwKncq;Mix`?qLX$#+o8d{gl`s@IS?$epcu` z12_uCgJ1}$9Q(ZI@P}?Oa5FG=L^rDTLm?jJ&`mo3z#kr+U~Nw|aAr6HiR0cCQ@#Q? z$}vQUtaY(*YYbdZVCficgr#qtkv`ov#o@LCSBmhAmu(bX9PTmT7Q&A>`qPneJZa`* z2*$u1!x5*O8REDP(!{O97@6ftoVmuv#%(olctn+>zJ->)odym`Z5Ox8z#*vtj(fw* z^gRF^<6-&+`!L1ZxQ7fJE|p`rjnIeu2lZeNJmc12d>lB|pR@|;IKLteGSiX0+QPks z%J-QVTwP7AUVfogR%EdT!#{33i}S{>Ykv)foHw42H5mPHzIX~W4Qj8!$bUEa(k!PU za*p^3Y8A%)kneh>;0vjhJVX3MC9Bx+);0TgR$ae;=hl6@bGPoVx<2u$;{xe&-Ns`t zRk_Ya=MO0DjmekhI9L82#kA4cxcgfJ`tCmb;{84A@3*8|7p3Z`eZJB@azp4}vEwd; zdg}>i|6SMa{?S`E4BN2d-4xp8HP}PPl@*h*%3>wn>DFT}9oJb*R%i5qf?`NqW-JkKOJq*an2^E4tR!b#9xilxg2`Vb5=uM2cHJKFEXA+T&;x6 z4jYH5gQi+p0Wu0j;rC4cJ}X zhyol=j0RGje0@Ytsa{>7*2zk+XMS>F;>Ah3%cH?`paO4#)~golN+7*bA`&RfM#sx9 z%)|u?DY9685rzvwWwHDs2=(uCxwBY)5tdf4{KBYWE#GmfUb*nkCq-_1LLt@ClfzPV zdM$^!R>EAh5k?TM!Z;Q+Rw|acY9oYZw`wE6cjs~5oJo_kch$FBcBZu`B8&*T=%Y{V z!CJ7#zAu%aZGBVyf>o<9F;?BuuogMRBs~6Hx0v_e^6kPZQ0tuSwz=-Y z=)v8IofBH>SJk)FH`UfJX>M$*S&i|ibV57_GlGU-b4Tb+P4yd%tQvYY;*@X0N3Z$x z>_>nNy|I{sZ@vc07df!C#nU&{tZZ0b*RWxg`gm?YDga3>!H@q=c955UT#IDn;2nau zyStWu_>VgaAY5IsT~>bl)m-_Zlhr*Ze};W*m@FQxIemF!@yx4VKWv-l4$1Pc#nH&x z!B{WB$JSpj(U#z%i~m2@OZ=;!u*XhVyWzM%GY#jDFnPthtldal`2HLi@f)h$U=cYc zK(Xi4D63^Bu;XP9Oqeunj?0!W$4$AM7qp!zid*-9ZLX1Z51b{?b7frjFdn>~i{rWn z&P(f3AwL!TO#IQ2KM{16;(T8FQN(o;RpLj&brK6Ad;&8Zp-V#FMIj4(PULJjp569| zh<^`@&viZ>@z1mPe2edC@x7coBjI~nd>`k_5&yo)%oiyE`clw1&ZqL!l*nAlw*#b>m4{@&R0c#2Ul`L#DNdPoiFrk;K-}9 zzCia2uNEun@R)~G;Ri~1#HYf8sxz)YYZwkxotXuy&ddV+H1bQiI&%s15#iN30`NZo zAEXn_0HRduMA#xE50|s9z?>rTa*=ark%WAW$QwnzP2@L<{AQ6qB=W~a{-nrX7WrRA z{x^~Hd8hs~DIQvN))mq-Q{?KbE6CM44#@d-OuRbl3i6A|L%vJoUnYh8L6QGlZ~>Be^KPGh`dJ< z{*VtPh5jQ*fj>#)3q-zHj&y;RRl zUs-IdDS|^}6$Zu|sO|h?{imDali*iB581B6 z;8@Ajw-Wpp18u$^*=hJA4$YQw{lI)fu1U1K64yEnls^vUWjy<~TLgiL`yw)=`c4aI z;|@nBuKLJMaOr&M<1C!LuHz4AQ!cYGWNqBJ7%<+D1AVa;-$1KeaopT4wl8-ZJE(o(7I-v7L=O2@SZJK8^nvF3j{@ z0vyLYw%ZATiF+Nmv<(7p$KMe!0|o8 zcHe_QKP&Wm0Ju^JsPiZa;E**nhR#!*|FaKcz*1cDJ3Zo2j^o+a@rOqz`2JpqKHCgO zAaQ@kpDE|M4$7%7AAfXlxC#S@?pQhExZc*(Hy1dLA*oNdO>ww7;7SE&uEVhP-2vPh z!BGz#>ETwqy)c$ohw@{*9zk%#9c$sX92UP0!^T}{;PB`vM|~$*`ffIGNNT&d`wSf4 zGw7(#Uf1ymaFjD27!D~Hhudr5a2epZUK{xj>cJE6#Op(b+W;KvPg;C_58NooOh=aI zPn) zE}7$0qzZvNHI-a3C-quwZekYgk|TV6aMdfg>Jwa*r3TfM0q0%SZ{OY#Wjmh1)c|$% zGOh~L)myk4j4Q6skW^oqnd*$!f# zU6fPvttI7&yk_sJ5&QODQ+EB#i7WTJJIk*x5AIl>MgCoQRpqDr8XYc?C>z0W>3!uB z_g=$LyZeN9+Si{j^nbWr{XJHs_aE)@PE)rZ14HTa1@y0mUz+1(>Il*ysA=lAOL@ddL0z6Sp6chDdc6Y%*Ma25{ZP z`n-zr#q*ZWtDLuB(OJu@=FcoIuUx#is%&m0$8;MazGp9(Us;45d5Mh~;$oOSPi%^a zXPq&3?s8w9lk^f7U}Y7elr(*8?UGX;e*LrsX^4U}rTnDSuWfF*U~yYb+xk{a#ckHf zcODLd=iT0P^MAdayFU`#eG~v>>Fa(n7R{VDcX1(e@l8XZ(*LL-P$~bGAt+&L_ZWgH zPL7xOwjr46cwXW=fuN$$NqLFyhJ2CJ!%OV-`SQ6lojzXTd;V!`lKXF;wC}eU&d+-; zl6*h+NHq?bS&xG)l8Nu@Y&u1_WfJyhLwo(?f6jU1tw>mR3INFZQ+}k2E6b}FELuL3 zng3}-RL0x)vxumix9;hPsDefCOhi=4Lil+^G>gUXY(zAhCGm@hXbubGml08wlj|j( zi-=Bj^1Q^aBBIlrd@u3qh-j|U(@Q)b5zTXYd5Qmwh~~q-SK>GRP)`c&<+kC^-}{rV zzYr-jzrYvQ*S0mcptOIhOID4YC1CQ1;vIdSST{Hl(B;G-O8Z_v+J%c2RHMKvD_Gq3 z`LZ+Shf0HpRZKMk|yF0P!X;#ZHtM{TKk9zGUH)`T@b zYIKiBi;y0z=X&RI8g-BvzRH9E}wIwg6Jf}}$jU_LkJk=-Bpye1OhUwVc z@X5W$Upu%pk`6x~Xag74w6<<+ZmC0BkdbqBqSZ=pxj$##SvdN0S1-MCJah)FRxhnK zmwL?=P$xe4<_|wS`g;Q@58ydzt;N*r-SEmO_4N<_I;vSK@HLNu8cE12BQN{f7sfsL zhlu9<4$qnj640ZQv!+5|JgNgpSs8aUGtwFJL0rwKKXnkgcMq~=UN5XPqENcs6pN=tr=(a1?iizxo2H%!#9UU zVpE0I*|}Ch9MRl#cCJ+zELd21beJ4-g=C2AbcJLH&2EKcfbXTxwaRFz%yX>*cuuG1 zS_ROsRP>{NZa8A;s-<-5HMbVUiP@VjTBCH(mPm5iHT*=-=@Lm=f03@CtBS%XZI*by zL$TDSpcvIV$m;qw48+x#MrYP_Z*uipi;d}`+NX+qjdO>q4k}vfzZU3s2Odq-QnOax zlk|88(hDsO*y|7}OV53v$a#9HK-btn^O*P%YFLQZqH*P(L|>mgT%T67&+-_+P# zdmigf5nf4D5i`TCTcp|?%eyP93?`GfGtZ)u*@yuPU}kQz&9S=&-)tMd4FmD^BU zJZajbqDgbB7pKdc*Im%kuzF2fdR*=JbkXt0Pn%d=STsFdUB9WOHC@%z+SamuZGBT4 zuWOrI)-|`(wAI%+ZZf9I6-TSwN31HRyt}r_ee;7^<#?Q7_YSZ4`Rb5sb$_q#jlMOimPNo_TgU$1 z-oRe!jyWQ;M)gMD$WQh`?b5F;TtARH96vA(+wHaLkZipgtXfsvZtInF<0_Vo@7k($ zM0?}?u57=!5Vw2#NiLN;d!*TkC^~LSl#H#4xD8S4HMJhj+`l>oSF` ziojo@?YYUDlD)lx3eT(kgXfO-_qSdjNn7E;OWRkGHm~i;&w1{Xe#-VlQZ}LcQs#eI z!jcXa9!jmKw|7{*S8$bgSe@ssN%ZLZXoHt`ve!G2>f4Y=4Z6zfnQZu^=l$}PS6=zO zmsbzsxxe@G@a+#u9{!G{F@p~<6E{aP(T!Eaz7c!5alFmT`^g&wbOcebLknIC!ahk*OQyd6i=-#sm$}3##mXf#2>kToHCXUDfy3uUx+xr^qPh z;)D5UT)o#b82BAq>`lx+P@5I}!Y4ZB9jFd|<N2*oO7V*;5(7%SazT~I7;?)Y*BVmy84U`uPWV?yR9_$@=|YmY0v9Q zu}v;#ijx?U%&kgeD6{<%*Xi$myp-EokQ6N!6D$4Q0q($_hv$yTy`mJa;K@m@J206` zsj@24mAZSLGE~ytv%PdPB|Dh%)IXJrZjC9p8{LqrZi~x1WoQsryS40nx?3N(xPqt0 zw@PF^G70;Ui7TpP_(0}Fs`=ZYIDhtv+8u~Ldm`=P!c(SQoPTHG{V6M7LtJ?FK-$Imvv<*MBrg2&;flan7!&DF zTl%{Ykz5h$qqqdjMA_dai5?rEx$+`FTT4;0LIw*AxMtW-0Y9w=Iy?9-%rhzc5d27* z5h60@&9sCu@bj0Ax4*?OL>L1i&dp0gD^3xh6!Gn=@>1Y5b4BmYTU zh5kL9Pk|5pdnlU@Lwz{H_i%2H;B%dOBKTZoYl`1l=@PJw^$_R)#rgcVaIN?I(*OJ5 z!~Eu}{p3Ree7^GxuKiE844AVF0P=8P7HSnwnbcsYyXPo^AF3v`-U+_whN- zDZ+CEHvsMXS;BL~HURB6M%s>-hP@Tgf;N8-pvg1(0))vC92fEs$3CS1p4vYp{<-2$ zz4Z5+Q~wOSOCd{+bR0!T2^}pIovM;!D5vPrLdOXmFBC%><&RF6aVF>c=g1_d!=@l3 zTOjgJ%Pn7V;rwR|M;ssTDK-VyS(6vHaO+6T(oXdD;h#r)a(gUjWfGRzpN)M>g0~*m& zEqYE8Jt$|T2UO()^gQMV^g~Ps=t`l~8MT6aC8j>?{8jloMfBl*D}A6UU7#vmpvv|mXdU%}(gtFXt}{hXspvs{QF=gCxvH zJ)kN*puHI$bf6g?4=~4F$#Su2dA8$l{yqu$eIkE=6!Pap{)Wi^B=Q@1KY+i76nef$ z3j8x7|GmgL=Am5Kf&~8Xq>n$66!J1s$g4%ZROAnc{5vB5zR3599K$meZ;BLpW|KnC zSt9?C$S)W9r$v5?$oqOe{wUINjO$6EXQ9YfihPyGFBbXLBL9@g?-BVUBHttO=S2R7 z$p0jAHY`l%08+#|m=y7j7x{@IKSktciTpf~H;eoVk>4Wn&x-tOBLAVte=PDBMgC`z zzb*2D9)5bpk|I6FkRm-ZL_S~Si$uOwpt{?AU zQp7uq6!D%Y@_8aZUF7RTeyPZ}iTraS{|}KrB=TR0{7sSX6M4TpKi-j~h<7Y0;yqd9 z3q@Wn^7SIWT;x}X{5Fw)N#tJ@`QsvgUgR%`{BI)fmG8&fkCgYF6!qamk)I;+YLTxJ z`MDzJTY9oW&ZZnGXH`}TKT7yn!jBeyw(w(wpCkNO;j4r{TKH3iA1C~2!jBhzuJFeQ zj~CxUrVH&1sukwU{r6n$CCr z+SATIZgo}0G?bo}vL~FfJOgy@aq2wK>FW1*^;=ZvlOmrK`=rDt{vo18{wbnG>KM_v zMZS(AUrCX#rP$X}>}x6ZwG{hWihV7`zLsKNOR=w|SZT>Tnv^T(jLoESG^t4K%p1Pe z>{_gknoTo&+L=9zK}6=VGX3q@u^2>q8e(R@jL@;OT?g+}R=Eva)@El}*H8KtSqr@* zevyJuKH;rXHz?f2t$bsPzzV0f{+Y29XT}m!(9x4)|6TLMxN-Z%9$)i5NQdU~CWiG% z)r(1}LB=B$`ufd5)VIARAs!W}WmY_*$$n1SK}9uHS50cYVC~B0#z{4e4K=Nf3RK6{ z8_Th0wBF-fjMj}F~p#Ob~eL%a-J+CXX?=M7AKc#RC~z7no+Ct5hZ z>pVz+IE};WV?^ILc*NnFE!=N_!%!k{THncQ z7UuWQ7H$`CctsDKj<-K9c&+cp^T1)~6*!IK>1n)%w{pFbID22NNwmCFaN6rJ;I?Ai zX}ftAZVo1R)clAAv~dsi#i3+6G6QSl-sms$9R`M%Hg0l(%tLg7``qB{aD(viL(NBY zqVK}PWuBoE+|#JwY965z+(~JfALs=4sgW3GXHkCN!?;?#?_2uLvhLe2$Ht#CZR5_t zxcg>H7g-zkHgGp(fx8+H$KEV(XJ9=4y)1CUFwWnV1@0SJ;?Bls%ntV~a4*N`HAZbxYO`Hdu|r`zM3WONW2#} zW})wjEOBpViL1qcBb#`C0^EnQNZ&-f&o9mbw-vZg#o)GD_hS&|1sY;-S6H}(;m;$$?ZnH*CxKii=zgG&0hecl#u3D7zVUR(azvgB%5M}VZkd7e z3|tN(HF1r=F+BC@u{U{st1)qHzzq=`--+mmn{VN+H1yG*jEduN z7`P*SSS;>U1DEaqx6i;G)dB7u12?h*oKxnfoAm`#;L0%{U$^c@E^xZO^yvVX2CfwT z)YrEI+zJE7=YlRS-d(`WfgkntCkQSM_o{&#;KO2Zh2^2XfgRvB0k;tTj2EwR%EiU| zn4xb_2e^J1glT<)JHV{~t`z=^_plCdy9^xf3mwzP_x3iFFs zCFSC9{R|vlmD3C0nH!0B;;z!Vt`9R53L5uOU%`4kw=#r3fk?qMW; zS`4mkZH;NJC*7I7o|2+zMa5~l75Nue&Yi_Qo!YsuOdE2Jvt_04qwV$Va&B`H@0N{7 z?@#x09(5lq>pQq6y}z_yS>FMmD?s~zZUxN;-36Kg-2Z`z>W*;vg{q^xWhJNqJEsv)?Ng)H4gP^6g6c3#XbslhPIe-)+R%3<=422ycH_u zL{2m4kp2G{wt@DAQt!^%RdKftmr|C6rYV~?BR9<2+b>Z@`#|5BwReDARqP!STn&?} zVH>tVQ_i~;7ltYDHC2msoMcUUQL2IIIYUV*uGxLKv#)2}?!))@&0RTLaXE@h)f085 zqyUy{uGxR{GuM~xsJP~3{La4SP1v*XttMs0woZj|5q|gGbNZ%MQ`7m90y928b~C=# zAig<>@2%_0x99qKyQpG&o?Nvb@0F2wb61}#aepGKxUZ79=X@w%#dOJk?!B;ldoPLg z)DQIzq!ruyT4}M%d$;I1uX*>kuD@XS5NCh+{ky-3tG}fC?SA5g{qDluZ>9TfYIeup z3x8Of%Ds2Ue&?Pa-TSzYDpjZiP^JCq1yw%g9_YFE@q2#cV^%0k5||bJ7B^E*d7t~n z4RP*)rW2QhxUCA81KierryxBy2I;}oUv?>955Bwl6{?tSw9-S=9)(H)wWr?^&1HM} z?A_J3U)^1O_u{!rP*3JveSb#FRYUfFrEJHXYxdsg z-^JW_=iEKZcs?fu&*z*SFQ-y9b1qBocS>LBJ7~q69dBtq=P!MGugFczQ5LiM)Tk@s za=+KN2jYT}8PqpE^8*y7fWMdR-7zcmy~`*)4E*Ou{NS3I*XJw$!M^`8_ zpReyQj-i%+AMwXCsr>iu9hRt2SBG0jKaF!P+nbuR<1df@<3}$){^pO$M$AD<_AX;g zvr_z>v*Vd-@@k$y{GlwT+2^+7dHz?k@3hvb!92qn)u8`tro9$v{|u%Aa#S92j%%Fh zo_oiz8ELS+DPqs%-U zW#iUoh-u5lU6moGg(r7)hM0Dq+%*~E$|cn>bmTVJ9%V%^cI2L$Aufi&Blo-vaS4nb zxs4g(DKLEGuFViL(tOWtvOUU+U;@c)&JY*F43fJpLtKLMUflCD#8Y6B%5BLIGt$1E z+iH7M6gmAow=F|l?DY5C^%>$4XMpE!$PiC)272zs3^5}u@Z3!ikEK=ftBaf?Ja==3 zxY!xtxgW_8mpDgy?v@NOhCQBpVTO3BbCl;^6cJZ0Jab;r;sxb1ozb4VHP)*Pt7P3v zGQ5gasIi`VX{=Y7bF}APmf=;RLXGp>kH&hHIpaO|V;NpkRH$P-cU!DinKQw2FVFCr zszM#>x!YsC%AARw`|%8~X)4qt&)pI0Rpw0g+$%D?j#HruJ@?93uQI2|b3c*cHC=@& z_S{d#dX+gPo_ke>*YPUU6wlom>s97V_1vp7yow4{uxXxqO}t;3bDZa1o9X9QkLjL! zUA$kJbG+w%D$~!eASZb4_3?gX&WWCTL&UEd4?v+);klpA5EnU>o_kY44|Z6zhdOcV{*Ob!y^IRr2xPV-FH>wh;aGL z>g8pXv#aLMubPi(3>Zl?eJbZypi@u$087I|#RFS=Uia|#(rppNDn(UIFgwt)eq9@^ zC(;nzV>%7aB+Rl%y8gHK({oQ+IQQ$3;3;mEAMPf8o70A+WUZ^}TdE~@?y$rQx(t%a zu0aq1%*?^}MV+2xeN)ZK#`+);%52@R#P9S;n#tPcrd18A7dLFKSC;FBC0@~IJ12Fl zD&aI=H!Sgoz_X>kp{c>o6TEVVC0+}>R<3VpZPOa_hb7(!e6&XG*=tzhzXH$JmfAC0 zYSwALKEo3G0>8TY);80#->}4=Bc42flNlH=Eb&(00gYN-Ff8#GQ(mUh*jB%efd&st zyz|UYE=;^QX?J;&QAK4NFwqS_u%(h^N4ARk=ZNV@IS`M^ircJ)>M-1)foU-Dj zNZI8on|wvnmbW=a=ds*NZx2EKA;S(Q^=m9Cz*xTLtSytuHiFg?2@T|T*d!UWj&sjFXI-;_S1 zsbN$4eKGvgh|&u;rF3dqFc}V?x~eF`!e)VwIur|?OXoRiXlSJ=EEtPvsAFDLW?lEl z@BnQK(?yk!CBDWPjZ?E-ci~E;$UIX0qKLp7=_j~Rlu&f$c1AVpvecD@)yJ${qJh>KGwb7B3oA=&eOu6|sA(rw7UtM>Kb(vObZKR2ODa2PkzofckHX?vy`yK?XaOby zpozT*!n2#6Br;_5Qa!<@{N+6BySp}xLEML2ZQ3NY$)DR4+dSBHOUDeS+(OKO6PlZX@#qeZMs@H(SQDN_r3AwvK^oBE1R0f)-!l+ z;-eR^ZbgJ~HSofSCLp$;_C-QvQ~Qj{$aUrhdoQb+=%zOPeT7w3PkExPwCfjYZ-86n?eZ5@On zGiod6{8RiK=s4f#?%K))*@s+hH$=#&5@c2 zfpqs4va@={S7xIDn@Bb+mhg>ldep-ocF&0lgTW4$0U26Ur?WOHQxEKgS{9uS->StK zlNgt4AA2#*4(*XK2lh$$q^`z~zw7598wkA?$;ffq@XH-NJ-Ww+oca>P0thW#-bMp_ z!#(#k-?ZKJ@C%bQ_@E{03YrEz>5roqdhX~CR>~gpKBy`CT}H~-O?(jU=5JCcv&CKza?c%W8hO+YXs?5owx3{Gzc+L9 z=C?+iT#SX$!#-H4d&5uNHl*&<(}L7}28A2eyMtGDm(x1y%+0sHHDbwWOTy&+B9grG z4%)4~gUL%I`zP}HUgY(@DA8jOEDc|j=;@PupY-yH>F0ULT^DakzUd^elr`BG|2_8t zzh2xC$y(k)%i3;sE61)$<|jtF8}7K{sXLDG@+MBha{6QZbpBSQ^I80|``h1b>0E;t zovs?ay&pD8MUtI^kREbSano2z&yRZB};p^B`d!RZvxi0Bg zf1o-zDJVKNAE*va*NBcp1(b{i|6c9j@}*hp_{;(7;JcBpV?$ymbYRhIRT^)HzLmsG zqoTfT!Wlzp_7gz?|KQjn^*Xbl`hMBA{C7M<59Ho=s|D9X(JF1X=cya4#2(i8idtdq5m;eWs&WHXnQYAqjk4zZMp=7Cjk5Ogjk5OEMp^rO zFpRQtNTS_vTwo>^&YyVX6^9$zb%j5N0NTarXZNmMoIks6?c)4rXiv~Me|@fa6+Bt<9biBa+{KeT`g- zr;!=|h{9I+Dq4pvWB1hs65I7#-7e$62^?4_K6hBZ$QNf%dl^hiS z`E4)?48ClIAbx_0f`ShSVNr87JqpsZy^OKDY_uN1$lwx*gjz73R-DgsONDl{;mWV0 zy+lBMruGD-%~tNx4E=MQb0YqpI!7|}_nZw8|CDnDc(o@3lr~j4dCIS}bmVUU9ilj& z=YtU9eVeKwA8%82a1cIM*;M8Ipi3ljoo|8aJd^)E_)uS-vZ;C)!Em&>`V6RU49Nc) zJU_(Ik$(v^44481k$)TXSjGALySNU^t0zvU@a_E(LYu6;z=!v* zr!x?IVGzEjGYov0!5;;FiNW&>|9XR;41SZrPXm9Y!Jh>FI)kqOALg%@a~k;Ye)Vz| zfe+KyOPy&RmTxa-1^g!m`g$q5Y@aarCiw3(`1Rnma}&Lt3&HENh{=D<@TW~$o(-&B z67~DD5kBdBJ;LWWPe*vq`D27nIeB=jwWCd1HkR5YQD2Ua@OcjH(`lE){aqd5dpcVp zd@tv^2;bYeJ;L|3_Y{6LE@u=qh1KiJ|Av-lwvKh)xfIrm4>f4IdDxA-G0 zeuTvzY4K@`Kg!}qTKp)BA8qktEPkxTAMHFG$(ODWaoF0^p{%x zr#OF%_|LTXGK(*__zH`!wD?&TKilHxSbUYmpK9@^Isb^Hcdo_Hv-tTIzrf-bTKwr2 zzsTYjTYR;}pJDM!oZc9*&~X4uo3v@+*$2|*?G)jOp^e*E#eRxOu1_+LQBXKM*h8x#OIL1R9#~cjDc*t{%L0;#phsbsLXt~NS@H$@; z1UFH_PbaN^aP<8c&4bg#t{y1y%V4 zRknaZo2UnrwvI_JF!iDERQW9weW)KwAE>&Yph_>OvMCIz^nhMUeW0`_PI|r2n@#=a zivH6@KkA**5BeeA7tk7^8yFt^$An%d^md_l3;iN!P#))r{zal6^;zi$rCpySsEP-4 z8^eQsO6VOzzasP@p^t(F`Wr?6V$qN1MCk`r`azX`&{Bp6T_Cht=-H+|Jn*W#t3@B4 zH>D3$)qhY`|3PVgD+$W&KBUWp@`arI4xyhD`k>Iqg}x~C??P##oZ%)3EfIP=XprA# zv8jB9KOvHAavWt77jk727jk727xLerT}nc}j}-E^NFhHi*Oyn3LauD!LcT%d+eLmQ zDdczO`}l8=0{2(o-bzc_Lpf@>-E!Ao43jewD~?7x`C3 z{&kT*EAm%G{-(&^6?wnje!K;wD2J(}NY8AMpC$1RdS?LQKU~%q)SnxM^U6h zQN*t(;#G8(P{gBn=tpzFgX(YajumZ&iH+%0{kD4&eE zT6#@YUKw+<^zuy>e=uz)&n@;XFqilim`i*M%q6}B<`UlmbBS+(xx}}?T;gY^#LrKO zZ^yYrX;Frlkz>%}s99WVW?d|)W|Y1y54Ou{qp}E*QTkz^jM5Li?3r-e$DjGOrNKN7PfSGLq|aKsdA#857*scLy(k<||rSYr)W z4hOjjMd4!N@NAmUSEoIc_{9|RsvJVrpUYQ8VB9hDn@U(b(dW*VAM$rTavKkz8f0E9)_GwRSlQwYtr2HFhcSM}9f|m6K93Ra%x5y$@^w{4Z}hnf)XG*k972>yJ3yf8sSD1BdQ5 za2m(&6{fz;;Kv52us_C-B7)o14sL;k`+hsPb1mGP;4w@IoKD}zATiT763nRqDoo#P z7LF%#VR#rgt?#QA?pN^G6re(VPg*#B+qg0Y_d5&s8{kgRk%=FJy<_2qo|8(#Cybgv{M^g8M_-w|!^9GW1OyC37tn(2n+SAqyPsq~4ST z?jKp=Za_nljlLo@2D`F|_ou+!oCR(z-g$1#0@oAoLfPPU1IISUc6K?>!MoJ2Z4h`H zH|hk;!DNB^5pZmCY*%5`g9q@AhS#mYp}A4c#=Vs#ZaO}KWTS6Ombg7x;&M*PF5Wp= z;;zgR_f(d+0=%gRxYvNgkR!v{xc;-kwOA(D#+?Y<1QQ_FHf~jxxT~{__hI11W)bg;z>UuW zmybEaFV!qY>XP7iTy7H*A!%cn9p;yz*Fb^$j8a+V)H2`NY1T^8;k;MPG- zTrY+4^?e68RPIsPAb@-xS~|r@r9=jKj?^a7T22t1xgQI>5~}a7T84 zt2S`y4sgp1+)*9i>I~e-4seYIZd3=jHUl@h1Kbt^r=Rz@a{j1+8*AwMops-?1Wwl% zd{R=5`fS`Cz?DMI``ZtHbaA+sfkV|-xc&+ikDIbM#0}^G_fZ2kumjvP2Ckq3-012s z-a#GU+JIXDf94lc1j@zb_Zb6sSO>T%XN3A#-gI&Lt^-b&-%uYGi+dTkUGQi6h8eg& zTle>)OR&BN4JmPb3|tOm=5zhTS^j+`Zd?br=MCKW4sdT8IK28R$Nbvy{-1%<{cs$v z*V$qE_^psG4maGuVJbnnINY%YZc+!h83se`9pLUWa2V1m$8xdL_lSY3>;U(Kft%Fi{>yz|HRfS7G2d zH%-TM*y)>V;Mg9~#o?+A9EKFi#o?A2ICK&1;_3_>n)G&YjRp=)aJ#rR1BWKFUECG} zhbA+?&A@%bxG@+HeH6H1;%}1qz~R4>7U8YHT||N5Ff?_RSh(TK(J#c{>T7G(nTESN zv)es=O5yaha-G}lPD=)~-R=okQR>_6M%NSA?M^TB?RJ-f_Njq=V9%(T!IM3d8rg{}~oorSItpJ4!KT$mKoLRT1~a|>M|wlfP|Au>ou zXBN7`APv5SE{;W{>`bd!Audp@0<>#2D+rK$Z&tIyaPP%xRuC$u6RTMvFvv$IRMflcp|ic#qqE}O?zAcG$$yP+BG$>*_f+lS0zMOo!6*3M7Fk= zSL&hzb!rcm*(`p54woi%YBr1Kh;?6Sv&2Uoilv^5VpJWYxpYhCw!nQ_*ZmAk7gax1 z!`C?fnT;u&kxZvrgx|dtfm3^j+~c=UR|G8Ms*DVhSjfyW%uT3TkOAn*s!;2k7;|v7 z*e=oIyx22-*V4L)MtB+Zm#-Vf(W{(JP92V)55z&GHzFB182qadvyI{1fa!xje&>iJR!=XTX8Z$`ftrmYZ3JNb6c-RGz41tcKH z`2~}K^mNbZc43)y(KDb{_`;H)a;lg|;$F$?#D}qB3Vevdpp4GKU`5IVq6F8o)q372qOd|aG zfiL+SXKRE{S$q$R&yB1vg%xy*&$sxV7T?QZSE5}K=YvG~KF*!m6EvCV>wG1`dzODc zi|_C3iQorX{sWvJMf?jaevtF4i2q=VKg@Yu{8{$~pgheR%>DK3#|uFD9ooYr8awg= zd<6BoB!55lrI01@=B6k<_;9W*S>UhrN#cVL&sgE1ElQ3LUFXst9|D^sT#Hb(4-|S< z08f2M#t*8_MA6~#0ZfJOC*cvF3J+StaG>=}TOag2i42BbvBxbdjT0U&-~JGTi=^sNBy=oo!A z?sDMRKiQ7sRCKHBwEQc;m1xGGKg6|uRw#ZII10vt=rwih*M5q>Jp5_*D*8io(GI$2 zHO8bIU8VEi_`{d6=-U~Q}r#_BR>B!r-0t44mp?ur`OW$zdbozAL zM13}H3UH;6GhVh)baA*g;136U= z+_44@kDhYGaZidF?+gQnB(#g0Yv3>>4{&E%`j!F5c$hv6`IRGY(@4{dM|4tijOavmR7Fw zH4%@n0O0hRi2k^Pqrm%ZV2=4&oJm#fL!!ga;sMO<j@emoLqqEQAVUUhLi-)*CwR{#I6XtNkocr&6a&iCD(h!9KI{8o?0t3zZ zL-jGC>M5Ih*3~wAb7-dO&ORNtqrbCH$6>I}J{^b1PCp%oQ0vq2@pzh~V!K^5d#j$+ zT9hb;0Bf4p)=yr)vT1#5eaqywhRH4U>zZ39*A^ER7H+I*sTY1#@${18Hr0V^tgmUU zU%u|V)syR58aC9oG&Zc9tbIet!TMUu8MGXA24Ku&I~oSJQ-Iqaua^A|J3Mzx?iHo% z=-hD9G~rK=CiV2F<5X9rtLH5)DK0E$fu(1cq{}ClPneJ{$48#k^-bwBni@8xHxw67 znl`Cu(%kCB@K|>Nj6<$zOOLA^pDsH7_-PZ13yY?wtLrz_w5F??aHzuiwe?MHysm9- zS=ZcB(^g;C$rL1p1Ws-7^i4G@8yuINY07G#nGO7DXU{)!zK}Y!4`!P6|24{*0m>0 ztE*T(0Cti72vOKGo+$L>vU~;0>0V9p29}@0^7C1KBg^k)`GYK{?`TN>Yb^f-%Rggz zGWs`^Z#q%vKb9!)GgwY*9Fv^B(I$B#%Uf8!o#kTPJ?OcS<+K(s;eSLF@@H6%Y-0r) zKiPWfn$1hgm#Ps2x#~--g+zK-LdL5kp+N+%Mp})ehvi1fOK9bhs^-S2m5mLRScilb z;Lxphc{YGj)K=59ys34Kl^bd4lJ-`ybV*x1AH}L5Q%-eBf8^5?rc2`ds=B7jR~=I% z;eLVhVFv1J>Nr~eRa`d)Fk;{q;`%zqzz`e3pRVuB7&v<7(Q#h|jvigiVB&58j;>!b zsPP0P{~mA+iqU8xj!{JCxoRBzG*gRLho|8{udZ_7Zi5Vur_S>Y_5bPihjZcdlRpIx zmw+eWQWCpzdgMq%?NJ*3V2=od+m1gSHxjrDP*H?a_7LtG{2?nR-|KP0{rczM1djAa z@JHd>z%7%9&M%#Z2k@uk==%SjgOCS=t8Ll5$+v%=9f@R!ez^V{iDb{7K1+7cd+wjt zY?b+_{`vRNvIh3&UOTQcbmeicbiMG8?%e0Pt}XntwRv=BL-$3PQ_M4(bL5QXshF{B z<>n1MfoNXdz~hMK=M5Z3v>BQn)GJr7}QZdYcg@`Q%F$0@1)J&Q7z|ri#gqC`-{#k^pr9+RpnB+J6IV)$)8xYAgy@v z6RS#+lACed?}=5#0dQeEPn@&BuybQ~$&|g%+c(yA?|E*) zl%lIn@BV4`M#OZzxcB*@-N9WX@49v;YAPI+_ck~00cSujSrC8)MLP<@dC7ZszHnZ+ zSsizscL{W)>@Pldfye$|rYZXu49Fqd2IQs|ja{_c-eoTzv7t!lS+qNNQ}@k#r!3mN zv72b|?z-;1J1V-nUb^cBiRe0SaC1R;(G<$H7-)*$*ewy#mag-52rqH#IV|SV&k%Fz z^LBR8JbHLW{s83}{q`5_DHyx!-Qe5BR>|arlNU{vej?MAigf9LBIMY$JFq<5K;>92 zq-iWAd_QsApMEdyT2~N$W<5z|x`J@mI^t3UhEhH7c9(V6Sed44_gy=?uHHL^&duHd zdmqOtn49Il%YU0Hyq_!+nuP@;>g2I~W7ia!0_$fwDQxQjpeZ*>HN073gR8o1(j6PA zN;r2z(N0)rlZFT0x8AZgU-4U9X`6?>U1F8&wr|$86z#nHx0K($p!MFfz$oOxD5SMn zBHsyE@9of#i>&|czLaaJYq!0;q^I0>lw4)svS+|usHMG+k4Cx4+I<$))aAd$tEuz)mzqVn#D-1wRO>f+k@TzOkwQ7q*@H zfT!aRT~7MlGyj{7Z`bdtkAM+FzSM8BE9u7$d^3=~V(p6j^3saJvek?8OBYoXl&q>i z4>T0m;~SNQ`CkEg^Pd9+oWtFZ9@)L}{_D3yAaZg@Ua_?;zr9iEEokU$sHttmL-gGN zWsz9DiFN$`p3@h6wZT8Kx+;A5U*uAXw$*XQ5;=*J!tQ-o#Z z4V!B7FoKld+|kr7zI6%)A6G@P{((|(F>g&t`q8!l{Z91g2z1M0HnByeOY_BfC@DZ; z>0AVx{bJ};1Y7)KrsJJt@GQTW*;K4nzZk6cl@toL`9)#XTI|Q%?iV$4x)lxuJN%+D zvu0b#p&%OMd2ad7{W$IDscX}I?J2*k!~DkP>N6cT32s(ZCC2Z$`m(S8eE99Je5Ic! zd7wW$8eVdNw4!)Lesl$1=pQGl@FM>>QHdA($IYZ_-0mMYo9gi^{&ATZRFjv)h|Hq8 zyfjASbgE2r0#0@-^QMPxX>a?+Eth#}Lslj#!CRe|sj3sNdAT}|9JXWR2i1GldlcAT zM-HgY0d~6Qs>@%xxGZ;hVMQ)E$C#5fLHu|`dPTs!SFQTX8ve4SBZVlm5rIdi2<!A+Ti~7&fbGsBK-^(caQQjW>HzKpACS>#EBQ z&nUeud%I{O9yVCa=xfv%xTmR95!=Pp@LNY~7+sOZwAtI2o178OxkvY?o*q}@?5 z1xSt8g-)SNVA5xYw*{L$1&8SQe+CxLB^XRdK9uyBACKh$lZ;{NBpHc@)_X z$&2NzD1+dke4<&-)owFt}C~!aCA*?oT^1hQIs%eG5G4!(#y$U1Rr)|8k+DPv3*6u#-_?f5gi^A zd?cj4@C&w~d)#=Y%qwtg%9!AzZc-Z6L?k*xq&96#@OvTE#}2kv<+rzr#uQQMV}jog zseUO%If?p>3H~6YdRvI04uMkGe@yVPkm@{ms&_)_%SHEBJaCk!dZZW0f|Ox3{7r4} zo5w?{D#bf6_M7uoWdH5_y8qoi37+CS2@F(P(@3rURdBzw;N1Hjdg4x!JMd6MX^Ax( z!h!aWI~&4*rS>oz!UZNa8^XmqFZ9({$rDi$t_yuOgqx!0*$^(ar`ZrL(y^nb*${4$ z__HBgoTEDaA^}c<6n&9^P_9~e0IOp-HFMUidq4anZ|8q_PJ4>GNI*FEv7y0_ul(%u zg<^d{u1|gLg_B!q4|6YEpi>St_kvzQvFatS9yfN;zAN7F8YBxM7YPXEf1`51o3nqH zzfUj7_viim&77y2CV11iiv)y=lxFdv3+JZK^l)kb<%J4II48ohhxO43&&aB>)^RwIaNcl6Z=9C*lGjeu5eWzD_y z<*|5iMI$wMk9L^NRtX;9+5$(S$KH3fO*KC7aIE#Qs74-hqwoD_I8Pq}Q02Dm?6 z^^z~5w^QBTh)-*Om?YL3sNvy2)vdud<>#BSkhnC(wwZnF9yDHc*jGVvaK)vJ=q6MtC{t!xJ@d=twVOcBtyrsaqvBS?5XhOL-%V;M&Bi9(8r$B|q zM8j|_Oz%2Gzp(ET6xB4~XQ{5E?-~?dNGQsYgD97_2t_*B@L>Glla@YrtTD*-uxn#( z(i}_Ne9BsD+o~%Y*{`U~w!OshD+AKIZgsl9TeUbAs)uFUKD{1OSy!~w*4DW8tH)(u z$BR}1*tR%YqJ5L@aGG!S1Ir7f%f&cn`kXvT4jo1qwqqpGHY z+x8UcJkd8+f$LrGnVTH@##t+e4AoGfZ!0Elp9V0xq4K+l%31b(-#eo(3J*JH(|c!b zBSkJIzh<`A$nkFYm=@i;u2q-f>sl?;hKe~4@jGTdxWpWbzH7lch5v5F{_o$~*ug5F zR;;YHwV_$w{bU1nw&Pst$$%lf>tJ7r;b6kNL_Ev~n3#*nwrdcYwZ0u>pp}dcyS8g6 zs!`o2#aVM^XsoEOtZCltOa!3Inrgtd|LHhf+yuSrev?w|cH1tiLUU%RL4Dg^SB=>v zJRv|$MZwcSqngd2=0Et|O}DkyZft1743(vIb!e#_t-zk+qZZ<`{q$~a+uBr3eFs*f zJ^yY|_~@w3ZKAe)(nVhreh(fr$H=no>+@!J9CAJEu89Y=X4mWDc%$4=E2^3bZrkmt z{@0Gg_3jmLO{%>m;VXa~xaUUsATEJu#fdrWF`^dfgR;JD#B-4EVdt=KXbx-4k&>*a zY%02Kzm%q2)*sosPWzWMyVJ*MX=GW>=CW?(>0fBJo5lPtOU;wA1KT@l#UvOtb>;w@ z@v~J6Umo4WZ}l+&>bDp+B<9@nMSb^uC-?~Dd)PU*-U;^37@}IHBGbalG}|0^Z7-lV zeYqN6xt{Ik%AU2M)$AufPd&HR7aHwi#sj<F=VIGXjlzSf zo15wyHg>eu%DGdbj;X|9yTCWTcO9(Wwp)EXjHWzQHuAhKH6aTQw$0NShT!a2$Sq>t znV89@=8^!uxxK2awFX@meQ2PwdQ(fTA?tuFPnSizEPa8j4UW^;rp6vgY@Aox)H#qk zaY-BR9O!#)Cr&-_axYB`+0jH9!kCN6S)Y^3bdR`mqfr~~}F7_B`+ zXeCvrZ2npUPUen%8hiT(r zPn2isO)N==#ErNK2UVB1#ToKfFOdx;EN`B=z)GmKT4Y}+-A zy!{Z?*cAg{*vWo1c8CqTj|`(zd7gPH$*_Tk&c|LK1jA0*6SDv0XV@V;m473{sK&NQ z!|w20m4~p!=pIZp))q>gJ#OT*apOXviG?9MFlwkY^G1)Ehp_%W8v--W{6l#t^~~$B z$D_3FCXaQ8uo7Px4(m?pJTW7bI`>Z@`&-hyt3Bq8?7OR?8W|%vH!Rv7XYB_e`(OZ$En6|MjlvWc;U84B)Wueqy`ub(3 zQT(z~gK6uRof@*&$_jW}RKPFr+jrd=y)V%>JtncA$${<G-M`qwBlQE(t<{%m-oX8 z@ore59XaV&=k!Noj^!Xm22)BRX!CbmXj=!p8&=5KX{#4>_hfZ2Ww5<7XA~Yf|8HgZ zcRr{?azf=3fx+0cZ_tRr_7Hn$y0gk|aH?$&r8*yC&q<$~KCefw`uF(}s}mpY^>*+( z;vJ~RxjDsbZDRPGw)b8LFKILu-%SMjV@2Mq^w}e&TT`o;Bt@$<6%IwaxrsNk5H+CH>{%)dSSx)dRmAd;3uzPX+O* zhhXH(H9DmJn+ksM)HhSXFJ8Yt`o+u7TBHWQc@e2Cpa*g`Ru^( z&c%GULP}{#1Zf3*Y^0-&S5gFaO{T9u9I*fE9!fx8PfP7I<=;sVZHsuRMJXmYDNO6N zS;Yi&4W}sxeyX)eq_Z5YG^0`n$9+*m`M5=(iD$8s$~Q-pA_IT2&@}T$PvQTLhtf=R z(wL?3zU(LL@eY>Wj63@MUh94ln`y$&oM5hHPkUvO=_=4(nRCF*U;*(oPh_^n7xFQY z0M@!+4~m|w2*mSH0rMg2Y#hl?ZV4Z zr#+h2j zEB*}}U!n28!ST%+{{fDFr15{mG3_y_(tnQQe`tI+j%klj6(8nf;%)48N-w)k7qOB* zLW`%p8pe3|fOWEm4_f6OKFMnJ@FD9;45Yp>4c(0and4>tHA20zr`hZ+2EgFnLHM;QD_gCAw^qYeH@ zgCAq?M;ZKB>v>Q4jyCv+!5?Gr;|%^-gCB436Ab=1gFoKjCmQ@DgFnIGCmZ~U20z96 zxu?8S4St%zXBd2@!DktKw!u#~_!$O2)8JICUGWe4X z{uG0sZ}2$=pKI`W2A^;61qNSe@I?l{z~GCmZcq6Z8u2Aon%iB+vbBp0zSQ6s8~hT3 zUuy7W2EWYUmmB;FgD*Gul?K1c;8$CtJmpzq@M{hJRD(aw;MW=adV@dR;42J%gTYrC ze3ijh8+?s5iOWNM{UNx&ouZYG?nA`}znXb^b{K-ax#{!|!;hF*%B#))%K;^OWJy5yI7kySMG)Qyw6qcsI4MQa?C3>yg&xj~ZZzD=m+KAFLHlj3jjVMi18-`41I@&N) z7EM1Jh7J-f%sLE!UeeL}_BzFg)CCWlB@Dh^Kj2L}{`W z(HofF#gyhok(?$#5v5s9L}@A$QJSwrlqMw+rI|-W|A#5fAtIh83K9J)Q*r>}>7kG) z^=F788bR*)v>ivmOy2uEizzDbB9c#MI)mvFA_64R40 zeoOiqcyFo2ytnKbEI*UwOL$Lo*we~()xlV@kNUDiM+GE38k9Dw5_%gsJx+KNr9(MH zdQj>k6Tg8ez5gVh_HJ_0Z{qZ2oF3&D=|QPa9R#IwOmse_2VKH+1=F>uY9x%UK`JhtLNq^ni-`0UbwrKr@-nWJ-Ic zJLPR*eJfZW&a2P|D#{6ZCfNxp$_Gl*(23v3l=fP8^qs}}%2^-$L+ArNo%Dc;a)XNc z0~PfLD)fVT>JN!U{jFqu@H3$gROkT}~I z57bkCn_1tftPj_-&<856E6^I!2YLh91G8 z=^m!fGJT8bKbannn-A$-#c%jup*a^VNS3qJs!7H1~;H;6*Mmng~Ue36_e$%#TP{15VXSpGiC z#rc4o`r?HDGg07=p?Zcqn<(V7h(i7&mcPpKpR+ub>KFJUi2^Uq5AYkP{vfCQ$w}Tx z6!N=S{us-jWO)+RBk)HM1%5P9;8(D`mgNmB|2@mQSx)67=qV-&J*6!F2%Qv? z?Xx!i9%k+@>f~@F3W$%@}cO=5q<(u;3pA9zFFwUki38>Z62viy3M-_7#- zS^gr+-(vYYEdLA3QwPd?`x8aJlZe8ec`TpL@=BJsv3xVjuVeXMmfy$nXITDomj8<7 z|6ut5^gF4%Lx>{Z=_^C*wtOPEJ_1iz4Zlt=K3 zm`8a8U&_2z9wA3L1cm*A!frufub{9~&?2U=OYpEqP}m_T@)s2O3X1$})LV=|dyy_I zS(??laYeirR#C5}#^;YO&9vw@%UO%Td?7`#*-otS0*WH1%SithP6U|Yq&9Sm7fghh z=^(ThN)$26iBL)T1rkNhb|T}xFe2z2QAlj5LQJMCa;95mZ+iLGNFcLig6WdXki@mt z|J{*DIZI+^OCs~nlKE$Gm1l{#ESX1^%p*(Yku_7sNiEnNhjeC1E!k2_w$y?RcPK7f zXenADPbX-W+E2ElRMoMQBdp zjWC?T8|gi%#)oO~pz{2C5&mb|i}Ah{)Z)yyfKwr8YoAM7={7WNv^+cT%H4Py8=7jB zybjCgJB)YBU(YVVwEr)w!pi$i8*8yyuhiCp-OZt+OA^mZ;19t)J zFs{I9b6k+h1 z(DQv3{CEfD_Rr8Y_uxJPk8Y&!S_c zZwSUQ=ovxK<^v zISyl@36!I3QeyV)oy=pNJ>=VOD&C>s9Gk(cmk6FI#Tc&vG;u%0v!xij?E!Z`o+-tc zY!A4>c$O4nh6e6w!(Xn*ap&UbP!l&e*RpQW0eo!Y?g#GX1aJ%UFh-mJ?l%eIw&B?} z5q-na7$kzbKS3Prke7(Qw}AU*0_DB5$g*xt05<{8>R(R)*9F}53ESH_Y?9 z9%BN(_0dQ3tMudr7&AZ>Iw6UVOx%tHaW5o@8-y{6MDi_95O;loxHl5SMKE@fhOkG2af?a%|W>bChkMvPIaT5BNJD+1n+X4Sogrh z-40y68|@sKxYVVI;m%4B_lpE^xn+svyEj4H;AM&F+nONme-gx%po4mbQ@iegSrH%X-RH;~afp_|<;{*Wkpu2cH?Z;&RK1xY5p$iK|Z#wGBjLR!`*1$iZvV_Aw?j4Pa3!l z8jj*A5T$1g-M%dvPRR+k-@xtCaA~9rfpAk$$toSm_Gq|t5+D$6g@Jog!}Sv=i95%@ zy{_TvMe;nr!m zV>QDILzN+EW^OPU%W(}7?nIib%?$vOr-{FUQOv9=Bx*zTZ4X5s}ez-R@ zoVx$};XcxEGh{J*%kd8lH!}{dU$a}!v*O^!Xt>#Na3^ZGIdO0&X}Gx>u0MQ3zt5Cv zI1D9-K=oqc)@e9A(#OO#YB)Sv$HZ;Za7*IgzN+Dt#=+gJ;i&zf;8%`&HQX`@^Tj=; z;g-k2y`bUnXefeTzHex_@;JDUG#nlsV(R;chC`P-CazzL>woCdI=G182V;OEyQw`` zBVmF!apN`I+BmoqHJln>A^oPl=^E~|IQmY~aB3XJPhWwCTOUVXsfNR}F%kUqm20?) zIJk8hZbKYgjfSg?gKN}q=vs>4XJ5O9tB!-)rs2?4aP&=wAB432>2~1M{f}XS6aj}@ zh|?Fn6}U~1=>fMVYl(qN?|?t~;A+pRZJF9!b;h)a44JcLWoKl~%E-)$L^6a(|BXa4 zGiGE+$%eG^3rmY=ku()->pwit+yxOCGhJ9a5$_#mS%Lj|V|M0He7wr#Q;r#{Y=5Nazo6`wR%flP2D=lkIfVhGqtwG@i z;^zuJZ|B1Br(+AQ%74Lnvip|3&lg@dB9NE7cW2iNRz~4-dv`E*9^x|!uN}s5-7irb zbLU-x9Fu%zdH}mnx?)?Q?%mtPkbAI;%Eha~cd7`^mi-~A4|J}VE zR?wJfJ-(UVWYyxR!>YpfEFD%GxK{A(82Orpqgp)HHbXiMU&Lo&#wGpRY*mUFZ+so% zXXCkdmbJyI;k1oNUnz7}K+l=hM#yWBwgK;(DW66hRY7K^^~2O!X9;Vjif{9eh5gdi zlHMJ6@gw(5eDS>qL{u!{AED0Xh8nq$1H%Tdx$_r4yJ+?n4=h;K+}wx{u*LH~10U&l z{mO?{uDja{qy^qSqsfyZMZ9t56c=2uyK(&0 zOFs9e*i5=B+AXXeaGd3o?%v_uXJ_75_K+9bR^Qy(PHQYpbCKnb{bbIsmfT+LMLKqH zl4S7;pAEU;v&(~%PknH;H%SBb5{7CTvSD1!kcUPcz2WVDdU1|wksw)&wQz#Rh6X>r z^0UtudJ+UGDmnnooQXn?Ny=49#aIrfQ(HKB(>bYzhjNu>u|@}{>MVZXo)=dPUgSv? zY;49oS_a6z)OL_zYER=pr< zqbzSaDu_rmJXEAKTl9#@1(|+!dQEl1b4b@$`_)s-G+`c;T*x-uQr?!<~yZSzUTbq(-;on9Dmq4X#OlmE;cG zjwmhqIZp6$q>tFxmfqTAL)`b|jk>q8sIG3CR#02jv9Y2sH?IWWSw_kiugK2I$j{2a zEp$P4B!61|CkUGS>r(7*e!1w@8uWj|~o2BS!*r8t3fV&j^!vU;Ce_Y7^vs{V&29I6C`pz!d zEp+Y5f?3s1eS67{KQ0Q{A4%ix_ZZhl>-STona2GZ>*R;d`XH1#|MpPmavx$}DlMkB z8cEhL{Q4|xPeSqVd7$gLQ|CsmalLKjfvl4~66sW+8=};)W%I%6pw@}k>ki~X37(Nl zB50%K^2X6i8;eC<(@z>Te^e6<=K+3zDlWqzZoV%H%i317q#o}O`AzcoDRU8j2QO>26N2TyGY1>$L- zM9s^fH9a%H52r{3;%9=o@k!!a5H~)_%0s*w@1`|Ai@}e>9|hv+-PG}dlYBXjX?%?W z#nU^B>4KAd6^>8Rc)X6aay1^q=1#CN5VghOFuoqJ#rhda6h!&1Q4DAh<@uI}PqKdE z;X|G^LTL@hH$3s)HAI7fR3kpkdf$UjH~4-A-{0T|82mu%Q;)tu20z%~htTc73BkZn zXFX051~CfijUQ(4!wvojYm7(VNF#oPb-X8jl);ZS_#>^E9{d=CKg!_8I_rnhbvp$9 zvQA4+Yp&5cLKNt_AA<8sEdk9PO92fH;x*Rb)HoD8J$(!V9}6ed$+fjE0yc=rAc7*H zptyKwuq-%^*VKXYi|=;Om&4njVk<#f(SzKZ4bEN^7_B`m+5ImfuJe@_SkSAj|2S zHIl!>^7mPuLiGaqXrjn>EK%eu*6xBlpXCc!UQHBonmb7Ntt`KZ<+Kbn$;J7Do}aS( zH!OdTDCFHN9~_kU;Y1;yNfi2vSzgNW4J>bEc_+&+XZbBGzn$ejVEIp2{!^BJz;c=k zLw3?dMEMRUihRY|O^{D!InB!o9?ffZz|RFAVIKY|_+yxdp9w$34W6!5x=sWSClfsI zf*-}ahF3ThkJA$?&>9!Z&uVSoe8!6CK|itNf?Om)E{7m~<&p|=MFqK_f?Q8QE~gM< zO$edNT}?rJxUAMYF#8z%RWpgBhLyZ=-af>kTL6Gf^_t@jR>$Zb^}Dgxc3ALC;pN?wa&rJLj<5s`~_&J1LWj$4a@`+e7I;(m+@5d8o{ zp^1A1lh4F`y$9T7{VYq|uMOOJhJ6JC{l6nMaX$u*?$c&4aTRE+Z!tmOO&qOT_3Z?3 z_v7K^7$4kD$n<)C8Mp!sr%sKDqjg^s!L5mbyUxh>X5iHGjF!D+;+_X?oetn*6L&oB zbJTw{gNgfEg1El}rZa1kV==Vj#&aB=JR z_`@aZgg4NiL03uCA>bmU;I}_2S;r-zp984CDPJbs6yVULoG%jMXAE$9I+7Fa6hq%c z;7A_9ADRXc{BRi>PCfVg;bv>N0h+!gM!q?~sd7*oPl5EAxHZ7#Kpw###Z&OZT@TzE z#6|F@%I$~y7`QUVrGZi)9Ia=o(vd6&&uxGfq^ zjl1~ac4#;>4I&Wk0wdq+H5`f*6Sqghp-3@tk7_u5{ynW9s@Kc2z>z%>{NYdp;!WJk z8jeP)Dfr=D*KlJcOyItWd_$T)zXhDKpJ9T~UL%#OZ33k;e=^&D{$zIctjw7a3O&!C?5dGgsri%tWj!P2Plm3vKF5Nt5AWTB8Iv1q z&x}c$Uy1m?$BIwd@6M-8-Vo`=xXYFB-cCGa?jE>2xgpYhq9YmCnYYuP6kL^`(sjo@ zBfCGo`}upG>l!<{lV&J-=Sh;LQ?+yj$KO2}>Fm8n%v*J8w>X*-ys@tP^zOYoA^|Zk zGkn)&_dIv^^WPlH{L@OW*FN|$+c&OrJg3|{a({RJ19y#O{wbM~N-pP#k~Lq~(qV3? zO?ldZuIpd8VRR?WEcK!v_d$1sDIY3tH2zmU_&`kUSclyygR+IR|1*a65djyUx08?` zcc+ypOUyI4+Ck^EN0iv7js>U!?Gr&EQja64qPs0 z+~&#|x8Y&?1ZrRKwLF2h_erY%=C9K^c`UUj|JmByAZEL|=R)Rpk)hvW{TA!@o)4Mk zKRJyBYse~P3t|7Y=F-+-<}J<3t;fW)Kxp`)A=#_B@hKm~w0N)e}MwM7}n z=#G{5ILmt!9!~qPx~a~q}cQxB)soA?UsWD23y{;(?|F?5|Azxn5Xudk>Q8g_Bf7356bS-991)w*|y7F-}6Fx+5PHbyI&PdwbVmDruDZtPs!?eI;J;zk^;3Y zI&BQ^q?S(ePI|u)rtc#0Dy{F`kw(D}J9ng|njLra4lYnNQ<-i19M>JakY0Aj%VWEv z>q2U@B&PdCLt}WGPg@wq+X#eteeZ1}knLgTZKpWiR@+pG@1o0EYwK#;tLsH2Q;BW+ zM)oxW(952-SALTjb>H=Msu=ErvgwT#y_^gmAxd^~-@6aJnmz2?C&zIgwZ(_-KU8Gf zew6*kMD(%){kWGLh%O4tn$hGMW>p8O7`PAF&^oi@>vzTqRUG|0Fv}BtzweMYreD<)rY0*am zvWG3(91Jgs7KaLJ+d~3oTrambqybKiT+ame>!(PAD7`M8_ZI|MVyjq`L(Xdsc(L_G?* zQQpCAnh(us^#1WoQ|vsp&oN`@=5`W&CkGkcF3riMKzjVa4L36C#q~2?Tx>#X3x%$k$_r$}p zH{0ZR;^xXTYl~W&H9`Y-^<}#ce$Ql+gK4NBV_+FjCCAr`^#h4pS*_M;M5o`$aBOY ztg-*3g_l#i{QDt0 z;%D2TJgGMZVcW?cPTU*goE}Qs9%b8}_!8RovoCSIeflM?x7|t7->!DfskebUl-KDi zWZQzLzBT?m=R&>B)4=uR#ZZl$5opyG{Mx~}ux-V@51u;X!ZXUs8_QO%3fXhRSc1m3 zy^V0+EHWqWsiuwpq*dl}KWN<cO8s(yBvqowp-}7n)`uk+W!dCUdOM`N_V~5 zJrrG$Udo|{mXcO$CZfY2CypKHdVMq}m)GlCa+Rq5mOeLq-odXL+jr~J_FYa%wmmdGU9KmLcL8c)+@N=1+$48l+>l%tH$2e_ zri^hCCd+klQ`9=Ssb7wDa;dMU0=-fa4=w!eljJ?c(>+%Ozx33HQ^7Bu`e!Qm#mmVf z65$t5{VEmw;{UJd>E5n_pML7csNfe*eH0b^;;H|kf?vFz|3m=g`Js>f7T^&46T!f|D-P`!bK>>E)nQN}q3dkj_gMF|6$c)8u*&*!x5!)&k9gb)n{KNy3tM0)#+Q9$l>dI+9}Pji|)Y3^y0&c?C+qaSo8? zGr2(TTpV(GsgCBbxG4Q?lRp3ASO-rN4_v(Q(%j9QUWB?Z_e~x2Xl16CR4z(?heEh7 zWLask!UJie;J2}aRQ zCy6!D)HOrvMz<(1XaMU#Uka+$p(6f2Jn>=cPVjDiVe4*Be6sZf__!R4HHyZh;iglRX^r=|L#|?o%nl%7dwHu#i4X1$s4uL?rHNg{~ZecYaCjZ0-`@)20#zZ1`Z(Id542A9@PjN`TUUi(V2HsF zHTYo$KiuGtF!&J$Khoew8T@F2KhogG82nKNKi1%nHu#9O##7#741S!!A8YXA4Ss^b zA7}8#8~j9rpJebS82n^|KhfZ)82nU&pJwnGR*k3pnFgO_@Yx1G-QZ^!{7i$NW$?2N zevZMsa+3_jQ3^9(-U;0p}C(BO*b|{>Wd76-oY$a<)^_( z!qGDil_NqFLh6YRLx+RjWmVOZqiB$DG{ zPt`{lJn5(NK>CFp&`)-gemb9|KNg<)h=db(;B4>~_V}dVi}4p6&lCm=9#2t%;z>qO zJf;YWf(Uv7)5%OvWIBcERHi7Xz-KVc#3UffZ-a$BoI&#}vF0e2kdyK%mghrG@vw`Q z9Uw}5Iij@p1bjl^H6 z>#JjZ3s@h{kI)Ay^nnU}pyiaF%(~#`ang!fr@$qoj~b9r!$?y zbiS^yp7oWmKKP5!2P)1Zs5ppDXVf0kSiI=GDYjcI{@BRUBA z3Zjs&CJH&tjwJclSWYtnNlwq!B&RjA2|t)9*dH_7vfLcX5mR8EqMb`NrDr%2E3EdK^k$bZ1{pRio) z^8)$1EdLA3|4tP0k>n51a{^K5pGp++9F{L<`6`xEU!L$6v;0z)?`65z-vxS}VEKQu z{EtK-|BU4+Nm9>fqL7azihSp?yp-i-EN^A`c9!p8`5u;kpXEPf`OjGXKFdF1dH;~i z_h_QX_gJFHcNWV_SiYF$RV;63`4*P%X8D~g-^21BvHVq*|D5F?v3x(vF$^K{MH6QQ zm-9X~<7M9^2xrY8`2^<6na6!k;8!w_`<38VF^~I?;Nj#VJ??|9__Z^ zPh}pA;7?#S%XLq%7e1f0J zJjy5dSB4=}?F-%WUb2!QzmZ!MP3{N`wb+d@b^rq5cR6V#O?IJ-oC(vzIL+b({w`Izd zCC!u@GiA!1nKI?pOqp_TrmPIw#;IsUX(rPwxe*g@$E51m`$eJLn@7cY>YujeX|3E; z*U?nX-?@3~-#6a-8pRjlJqytg<6J}o%rg>=kSb*5N5^_zibO}dCrGaxzw;BFR(s(Q z9qGR2h>p`=ZXB}xuGkISFCC>ow@pgilDG?e{@dBGbVl@v{nvE1FUP)OJvBhIx0oNs zXoO@r7uO6UB?2)#Nql+d%p1&>JaVfO~mQ^^MmX z1Udn2TQ^lTH%`SOvz2X@NFwF}S2Q*>;gTQ~l5c3LYu0)8G8a&X`;8|>Wou>AMl3_A zDQW4bY61!}%DJ|>y`i~jYF%UHMo8M)TiYwEKvaV zHE|IQsc^>{ICPsWKODMO9)0cLF(l&zr4QX&5AHGW=t?_5;Vy)Pj#W8^fk79~2?}>7 zBsz|sCDG+{g2Fvx;I<(GT~8+{+N;u&$Isw5=@ebvD2Ps8|yrcXgl+@^j!ZmIxGP2A1_JU-e3?hZV}i1E%IaASt@ zIA#yHdxm5GKvfwU*0gWbNbI|t0B+4_9#7PC(V?mDhA|j}Pe9)*V|o0q2YvmIu`DsJ z*8^@o8VE5?*8}eRcrMl7$tk#5j%9fM6ysY8z|_S33eTZpoXWucx8YX{aq(VkV2Cww zKLPHB1aNhDeoX||4csjW=(`z>#?1-fX5+ay5!}86aV=Si>FbxB7;aC3xB@gniIn3l z;1a37b1^I-=re>QGkk9)Wnqmmq@;y z!1N;MpfxlkZ|^zK-${9R4Wy z;oj14$4Zzl?tKk6J`V0<4L2bU?sE-yTpXN*_uHx*c%>_XUpZ1V+{8GzK^ksS9Nb6^ zr`lh?d?Ol8wda1gi5gDbAN+6`8g5D)`(|r6JkpEcr!Pmtss1+MMjHN73>=1Pgue`t z>O{SpxDCMNFm7lZ+-(|eSRCA2z^!3@7*Z0!&%W6!-3VZOL68g6tP+_M_)$T+x>E8Tp@#KF}Ar|R#hIJhT)dl2zde;67Q!LPh6 zt7QM4a7V|%y$;+4#1k%pKMJI8qTyGwS6kMjxCan!Fo6&VH^;zzyjISOAY3Ma5d3h~ zsV*){!hCUqG+cHZTtvf7kAut5a5LiIax@%;s(kGKwQq2VttYdGABW8&V@aJc2f z#C@#c&?LpgS*N-FhbAN@ZjgqxEu|KOD`s_Ov6$8L4o|# ztmh3H4wtA1ez+D5hpLQ;yFkO?FeYx7hFcd0cbkS=ui@4k{_-GjWH+@hr^mrPs^Kc) z;GWcQ8{*)e)o_(@a4&1PsyMjUHC%NZ+*=y1CJyd>4Obfn_pyeni-Y@I!)=U%qd`4& zKI-G(QZ!sc9NZucr^cN~zv%}fHQbq+zO&#jcn)&<*%9DIbG%M21`b_v=bkqgxKBu+ z1slhg8@MSOEbAJ`^gy_cEe*|6o2$;47Lg%y)~xJ|tXUbE*^x+w5b3{>NOpGi%;`eD zA?^Ia(jr=sOa*-HYPp7*28%N1NHX9-@GbNY5(x9-4vIyf5EoA zv6RwU9^OD&<^+h#3)_zf37}=n9Wpb=TOtcH6tQ zi}d-9g(HQ9XA2EOnx9xz5FAUtNk`IeXe9mi8&1Fdhcp*V9@Lz_JFq;ZDzN;ImDcj# zRocrxsQj!sxcv8(Nz4CG`Ehf>?xf1RtH?IWCv4dH9bY@6>tSJdZ(d5{5KlcQPSyhu zIjN2P7$IfJ&5Ea*10px2agaxc;#6H;BF>h#F8`R2jaHy|tg@)<#TQ;$(;ciV#-wY< z0x8>2Jle*$XnZ~$T)-+0(|JtWU*epHUk`zxV88B}Z)y3$}ogz0?Qp&5a$GjGL@={tCP9a~iZVK)y z9$UOST5q+ZcS$%@8R_0{FBzD;G184MkNA3`5{%rnaO}b<-LSc6tUYN-IH!BwDk__P zeT?fYz*Qj2RIsyHTo0-w-g?`q>Gob@lvnbuOsC%Rx`!F{Hn7Kflh^YJfxLlfm6P$C zj8g4!ax}fyo@ACnUe&{t7l^A`amo|P8&arE8Nh7=v@GbhZtA95o!TjovZU<2$uYRxOS? z@MfS1zir@J!M9rt_-zH(0!$l@tF0`I7Sg}X_%MWGyzzC2pN;XlS=JV;1R>)ZfvOZb zE1>60Ya`?}NZVj_ihLSzR0Wxt)(^7XIxgJ!J3GCD~TLko}r2nT};o?VsU`5!3+JPI%I!Gj?x0X^N+Ig0fPY zS~}X7bZoMMfuE~NwCG_%Rcz_bC9BF#c-E8Dre42o2hRyFC@Wc7QBbnHV)4>~Lewy7 zH@MA^E?rrUIu4#|!L1#==WPk35C7}Z9FN|hRM*fdr|?<9;Cb(I{?_Gg+Q}<_GrWB7 z?D3wo_7woYrWa)HB}>XH*5HTEckm}(8J+Uri(VO>_25fh8J+mx%U&6s``}M4i=HpJ zin6YlA0GF^%Q8IX$f6W(X|HWMcHnh=PG#jl<)Stsrt?R9tHM=0H8cq z%lwzE%q^{0v35y5mFF5wmc1f(aan0073o?{Jd?#J)peRUSExX-u9rh>T!bI~_D}P- z41UG02+KM!hqJDsx{@YUiZ3XF!5fst78%JpHVl5{+rt8zzvC^%c3F!1qz(B?mlsy# zm#q|M<$gm}kzbmdN#%IJ8<9n)=0QUy!6?YLyVufDCUwdg^T6W15dO(ebm;=P{EFPX(!v5d8~^Ev zDO@5WP>wr1raiZ2^GoMWtsCUgE=|jYi!^WK%Dq#WVIAw5_U^cgAGvShi|=_7r*t+q z)L7#4axTH(HFy5vXBW-h;(;YqH8(d}c0jyCW8fnluV4Al%5`^pfo%;Nn`&z!)%BIF zmK_#zH5vcUEl2$N;%|-cwjfCzO`a4f;_U*bxZr}_jpMIg^0_yM&7`}c-3o-o8!pD) zJG}es%=^k7@?zWSn_JuA54f*6r>Oj~pUnBylH04jNXHINk}MXCV&yk{c6o5}sSmF9 zCTVCAs;9WBYlb{D>gWw`|I>?eREq@3V%{e!er#y)<10V=e4!^nu%e;^(9D@A&n8=m$yezylGbMZCCX==8JGYpNR_ zALW6HDvF3wCxygoP)5Hq{PC{I1=CW!Xiq(HvSi&?@A*nz*^mFQr^TDBuCciiUY(>{ ze%Yp{Ix~0goZ&^*Gduhu-+W zTZihR4v`w&l4CCK{4}^G{Z*1{b*QxH-jm>kPM@7~J@(d4QexDCx_Nj>-Al`pS68=9 zE1)IHD++V-O0W_}qglIDE4J)AX6;WN4M=|Eig;nB(Uk|`Cb5RL#iXR z{qtyY0`IPb+kGFq%m8G5*j=c!9D;Z#X=sD9tU_0~h8#vrv#{;=RBLHMddY7@lUQ$k zAl!z0Ks6D{Clnv*FRY}GG5WUM$V9$}ofB+RPJpJNKs}r~Yr;~IZ97xAKop=i9ibWv zUv^@1YuypB!zb91rIvcWHa!FUHgco9%C_3vnwnNi^{)_dHj*x`Y&%nTtF2yjA=A@? zD81PNWeDe6*yqj{LB5Bb^DS1+x6#k}sK_|y>THX%69w#DCp=T^KdU=o!af(}O(?7G zP1IKn%NZiH;d9?MWz&)QVdqWfDsK|K91KpicC5>+r2*S6nR=TY4)T~P0O+Ymddzvk1T9Z>gd3;XJF zEPkMhm5|5L`wL5~6yCQUM{lJLJCD0hc^vMl(eF#BqN&)nJ=#_cTr{e8T`$|V+s&5F zUU!!MZpTtDfey$g&%!H}lBSy4Espyk`Iff&hPw9LP3^jHvwv<;-fG;N(@}HbnN)|? zRjB5^^;Viif7p5JwaQ!3K1TZ?RWudbw&&T(BUD2fjqY8qT@mfIUx0IxAL{KTRCY!= zY?ND~()8Q57;2*tdCPjB&)sqkay{(a^4rQS%|^7WwzZ+TMpQKw+_q2iZ$=r{yDqsk z+9mD4_STw)&W4)WR=vGD_%0*0pslqVG1{o>J2)TJ#%5?tKTK0FENge4yX;|k-@it4 zSv<_Nw>CF6*0$0_15wNJrhlR1tp=ob9rb!2N43}CEmW6h)T?mik&`wHy+k-qT+dcXqTs_H@H8g4CII_um-f=KDws-yOJ;%S;81*pBUKK6f zwy9&w^4g8!9f$_@dj}HzI1`c&B=jYRyPte_fAme%rxLc+O9d9oCc0ayUnflHz%OOp zH(T2C>ucnRE-_pIzjpBPWbA0a_JiZU9pO9rc0;xkn{b#LH|4y0_3I(gD2L?_FrLGUz z+ojF-d2H^ROT@P}?;$@dkSBcg_d=l`gi=@kG!(i61e|;N@BXqF{5~062!r!NsV{{> z`Py%erZ}_s9_X9F759VF>p<~=F9^-}_ zy1M%n88`c>_g0Ye zcPMm4j2cWkbf@@vGI7Gpg|o)Y{oCmwd!#(UZ;2ZGIezJ8*f(7mxBt*LeWdXyT{l7! zZe19J?>Ed!38y5dq@<*#q@|>%j7gc7GCw6hWx+_`RG`6g?F`@iG zbCnKpy z8fr?pBq!z4oY0P(^s965h@Ujw(Gc2kp=||I2HQJxM&Z$)xWV>ibbR3Xq?bfEr}S7k z9lUNTyeLIX-CtBG=8x*R9A8{seOIc!%gL#~-uAeV;}w07)8Sbv_KH5Jzb{WtPAimz z_BB0Swy$V_2U^)^!_e*?fhJK(iA@?0Ha-0mw8)|3tdgN2|7uUp#d`RPc+Zu7wJI@jdD9seF3+W08?OKlGha5k75- zno3EgjB{Z0Z3@A}5VG-M#Y6{1A1^qlsEPHY(Z$kSa|atW|Cz9~t|LGQG?UoD`b~qS zZmERQv`-!CP81_WE{-;-aBxwx&cq}VN+70NIXLq*xAQ@Pi>C=M4nF2=jj7Nq?WLIr z4&KzSy+)_c24xC*5v->$UQv?K6C5zTpVPtG+am(H^+B&$bfEhdfN;4-;Rm};+jJ3! za@*Q!H{pxORx4#hT5`X@a0sijW^bviYOrjY0G?!r;VWj)MM;4_;=$Do0SrHn1>28B z#FKF<1Oh?vCJgPG2*l6D5luCsKzt6Un?A`Z0#80fA%O2ZOF^mPDG*N=yqi8G)=N}2 z1@N`=>4+ahUV3FQjHq%t>CG{N`d&TpmZTqApQbSDkBBrF9oIRfdcVY zfKCydkjb8Iq}IBjX}EUldW%omvaY5UouvClG7Ux8PRav+dmy$yaI{wNUtJ5aYiQ>~A|yXPm(`iqB8 zxAub{ft`N5#rlJXPqhZ%l2joW zNE7>FyL`Gu`s&r`mm4L)M<#~A!LgFn{b#~b_vgFnvTk2iR%yXLWP zlEI%~@RJSxM1!AVJ>$_g)!?TYe1^ei8hn<)XB+%d0 zk-?W5{9=P&V(?21zRcj48T@jCUt#d&2EWqaR~h_jE19MhaR>(182nm;Kh@w*Gx&7| zzuw?aH~0#J-(c{S247|H)dpW-eo=_;zQQo zJ@Ng-x|<>NGijdeu&d>Imcx=PD;azUH&!JlHzawO<<#Sgho_ISh9Oa`bg|@Q9_2&& zDSzsVP(BJzeL+9FO!+XzQD05B)6`4)Ngwqw2q$mH==CC8gufsvR?sO-(U}xH7P}D? z1r-!0NKka%1jPqwf=*{TgXv7BI6)#Foi(b{V2#|G~R3 z-%{3>#ri;nK2V_#bPc5k-N>|&Db=fE-zL^q#`@rQt%weSiuwa>AUi>?ru3k9FvWVV zg1=wa*Tnjku|D{(&<85?feL+~bUuTiUuF6=rq}8Enpxj+)`#mr=mXtIc7al#nkemo zNc0A#!anfSXC?V}biFOCcLnRkbtUwIR*^o?I;ONP0P&YI-NlqXuyE?}EY?@f`fz;; zeW0h49#EkdbTy?1UB{G$9~?bM1Xr|zD_IY&Z=nZNoL^9JenCqpJ?K(BeY<@A39gdQ zk-;`Ruv7k!&m;=@T%wSR>lN~|Sl+>M+P9SO|BvNAVfiO4r|X*Zq!NXmi--a*`~&jq zS^hN3Un2_nFIZlPMw;-ei9&uFQRumhntCD_MGq$qQH+Q3j89L)4I$guVndN zmj8g|Pq3W!RV6*2v-}?{?;n!#qlrS#u|%PNCd-RiUdr-1mTzJCHkMz{^1E4nKg+vV z{xg>UlI4G3IW^RjZxT`Ddkj(7na%Q9EH7dCX)Lc``PnT0D$94V{M#(=V)?Tyf1l-l zV>vBuO8E}PO`GyPmMH8wo+#w`EMLj;wJbk}<^RF*ud)1FEPtBiKW6z`EdLYB|IG4q z+uL zDDoXo6!y$y`COJSWqBpbYgvw4s1;l-_vWGdso>WzkNcwF*D{a$n&7b>A#Ne!z9jh5 zn1@jC>zK#=K=A9C&te{f5F&jx^A*fbXMO|oX!k_=O6F%WU&TDyArW8AJlYeugB8S} z%pjtO6#PldqdbDghovGOEtfkMan=hJt3JUuKg&10-kUXr<~u53|pcG=qKQSmg9520&&{PZCFJOS6Ps3!_PD4;9k397$=Zgdom`gAHN+*k;7 zeH*}!Q6P>Zmh#bY+rXo{=me#&3=$ppCiol&CF6)~#Gj5E3#Q%&cd3E91h_kWa9=lY zCj=~uY*c~rqVNd*^nC9E4#N{pP`IBPxM6tiMEBhZ3ilTS*9aUvo2#I3qi{gS>b$)P zoL|25Jg(zP@jU8RFG~&FcY*WMN8=%+55*K=Jf1JNkbr}dcQQ`NZ-$}g;915D7aO<{ z=-`X7MFVK!zA_lkt|~JPYvLXqim}rKaE}j{V?~-OacJtBJ5r9#^@Q6o+OotLodGoU zg)xCajJ@@MYdji$kU%-!JjSxbSXmGHzB=Br#28o)xMPp!F|8hOKbvG(VyvnMTq7C{ zF&5PW?nONFi7_VwcctMkN8wrTVgp00iMtKBn-ajy!?WV`3E*A@?mrX2b>La^#sqK! z(I9>|0o>ETeJcT6JDy?hPXIR#&$iUonZc~T9|3oZ2?B58PRFzH?FrzzflDOcTk&jt zM*{kC@vA z;%-Y2_fCSii5MeE#JzKgF?NIDrl?@zHUg*LS5*QN_Y!dH zRHQ~t+~oOkj9!C?LlbumaMbrPgNd_q64Q5Pg1Fa!OC;ai+{E&|2e?G^jmS$(--QX{ zK1>j|GC#5N_ATHV%##8BVZ*OR!|DBSKQeF^0~hhpXX5Ti5chO~xZfm*`~U2H31C&l z)&IS3%SIA**^Cc@EP{}QRS~l<5CSF<5s~C&0iq$nBp@INDk6<*gQZrj)lWsKw%Tf~ zySB#Vvxv6RR_oeItqU$yT&hU^zcb6dbLZW>JgJ0!{5$Y+?m6?DGiTO2Gxy#ZFV-ld zu`e}BTyB)OnkaD>MTxsPO577s;@*l9=f&EtTmHSE)q_;vFcb@OI&Kzlqry;zq2pEn zhoM-Q({a~FiF*dPabeoRDNmazyXeaL*_>8J=*vHQbvDE}oRZ5$;P3_a$&+Ag6TD zdphI@mx4l*`bicnxAU(T3E&8KvWA-m9F-I4OT>>H;T8dheA>VS_)`R&s-NV9TdwJ= z0FLCOFNhyGH{2oxH=M&+aI#-@E4OljY?yPyl_)qlpK`-3QgCSz^ff3r zEbVj|?>YsS5dn9Zg3FA6yI#Rfih#RQ!A*{Udsx9uiGbUw;HE~vy{h1*MZoPy8PSh%~ide94#T6y1^9RW8?!Ieb7jaP7UBH(5yxY7u?5(PIm0&bClqkfAV z<%^!)1_gHtL%HMDDL4!jm~+#2nSw(X+$HXM1&6M%OWd6b4qaE5xQ7)Sx|%L=I~5$d z1`GFFtscAz9Ho!?4eH;>5wGL+D7e!Z${n{?!7Yq{+o#}AWtnq}cfW$eWtTYLnRYsG z*(I)*f?FH`*I&U^M!*eIa8(g-BNbdI0&cv5tB!!1q~K~I;ASYeS_Stf)B}w7t?_9d zaPs~qV2r#29R6El(Z#^^l@kg9G(kVsa4V3=uPC762)C?x#ktETG*zE9G00r{)Tx6Pqw8Yx=^j2 z2y2I6=c+Pv*C)c-XovppPK33Cb$24HjkHgArOAM>Ts;xihBC`-JiV|j@a7@fN{hGE z8W@H(^<_=V>n7qQt(7fx%@bSeCpOouXlj{QL#L&l8)~i-{F01mnNwHSf@`S5DRY%8 z&R#mPwz+;)U2{Wy^+f4wOKJ|&DXd4c-0qLRE?b|Guv>uH$DrMfti6p4)819X!#B?G z%8fI6ZoiDk-`CT`&-%WeR%gP$u2=h0{o8u_mRZgn5!mqJTlr(?LO8F-r}2Kr8lxBA zrpd7@1@U@3Mu7~>_*e}eBl>s#?Nop;_;WT<)cu)cERw=Ikk$jnuHwgJ=A-_h*uNU(Bh5T6|-zDUGg#2?M|4PV{U>E5R5`{hNTMO8e zE#&1wei~88*|#sipC{xSg#22fkl!ifcMJIwLjFe~e_6;s6Y?0Wc~QIxM4>;GDD+Gg za#{l<`9dLQ-v9x>LdZ7>IlUi1daf06+G2wA{6@&16mmq{m7{l@o60g9W*1GCZ#PDM zleC+cN1aNddS}n6kzUj5<~_U!Z;EyCW*CL|j^6O1yrdu1X>xMT$~pU4C$(NR-wF3J z%0qXoi&KP&xS_CiqsZtoh@YyDzM~mV9-0e+S8)wp;OKUy;w}eHu4Abxb=(cWQTx>$ z&1F@64+2-OgTUwGha|3$Ua6?Ra=k&yh|-)x&8`aIZiFluKe>KP^JBXEp)9O%@;>0u z1RM@c$!NvTAx9wUk4P8nVUBQ{@KbSvfZK?K5l-4exF6t$sH}LeL4muC&u;^c^at@H z_epGbZ@&snuM*cGu|LrNIH*>^xW5*72a9&C;PfpB^ zw!HSvt2(yDH^q30Qj(ei_?yt=$KTkdypHXG&qAhWd-7+YFPijNiUMh!+4Ju(3U(B? zn`JRoIc)_2b8J@Uo^5eWUeETFoHiNTo|ALhaxN-p-*dxj+uD$hM}8Tel2y#oc!aAE zR+bst12P@wGT(W^r{bXOPwP~5pE-Z~x3>JzO9QN=)Drk9v&>{US@z>oer&o-XPxA3ZAt3 zG_41i)||H8J5ToPNXknQHWhjsa))>fVG-j@BQLPYVOLC5urp{Dq^qdoMRfle}3DSw^Na!;(iSX zA7VNyq33L4Dde>XTW_pl@igG78Ztes8>SxmYp|yh^|tfzL+4I^?|5SC@;8!C_&NxN zb(+*enY8?bQG0JQrZ^+FGVj!i({oSHEy=IU%tV)I_R+J0wUZwQ}2BL)10=;o#Cud1N_-ib62Ytwt0LF!q2t_6Y6gbCA~iF-Q3*{ z^?oZIJVXo|;~h{tS7dXfNuE%CsE+TWu^aWE7)c&s%QfBxz& zbTO3fvCO6nr)7~NF4F_ZMY<){x8z_g4@VN#*HT(pVoh_bDQmutIYgC@s`oNuqG_(f zX|~m{NIfC(e22i#UxlCriXN>7ls`vYHF!o=gT{L0lRH)uD7~hc$tr-;_Yl^B8f>~l z2O2v{oDSk_S<_O}aCXsJt6o63qPo7dEYxb(6&yWRYYp+_Fpy3PbEt!09nO@S*Id_9 z6T(Jv8+= z;%d*yqW09*w}e+8O0j9~qUsaoe@N@kM~AfjP&a_b3O!wah9lA=uKv&_i&Q_b3xw76 zl(&XjSGKTBrZk)87qY!~fjp#jsh?@C)$h5kgTvOkqIoy{t)1 zjZ5m6u57N;NBET0lycKNf!C(4fQPh36}j|Fs8OrK<^ryr6~_EwGuiI?ELPL_+dZ@w zYmY9Yq#(bKxSDpQdrix2XsS8eIs2sKo90}%>ZYL&X`MUMG*|2QLe#lcVRa6|)_;3i z8CD;)#Sxkr(&j60^isrOK6-sCGlAw!^!{LSkDTnv*FO;@CON1}_-lH1(AmA?{pKh9 zMAu(J>SOPskXc9dm|1+4$~J2ftXlY*r*~gZucROO6GzXWe>k7Jb>!oo#AJV5#dUuF zGk)^|ZuMRNAy$7t=Zc^6nkTvMQ<~AAsU~|-=C?RZ?wNDN?Z-QIM&C-ObZ5VJDUK2M z`}yB3bZuV3v-Us5&RyJ2I_})n&YS*2^79L_GxxnVf7~U0f0p=bj^delgTu(4Iqlr7 z(66ILf6|9%`QuLU`_HGp=6Y@+y*0+$zX$Dq#9?dy50ZtGAO4HqYz^S0Vbin?qmJqD zW!>{+*r^{r>Nnd1SPnMLH&~AS34h73o;d^C>c|h#?VG(}i$`V5Ayp%B@omqqrU#n* zeByPd9PIhTwU&-nPc@V{?C^Ab7B}IfqX!ZFHqcqz=U-xG_gmvx2u1xiJe>`>Ltm6< zd((1`NY}E1O&6_n2_5wZtAplnT*unVgViy@(y^}UV08p79WLjCM<^o-CmoGfl`>i< ziwNHa6$derKV;`XcYlJdbu#L=J!3k-I*GRj&S&nqlZ=nVn7Xe8-_hyTJ$gFxf6nQ` zUF4o})-YaF$FYa{S;Ky6{66Q=!+!fCsQ^EEI7T^o7<&Fg&m5-Pp>*_l0-Jwfs3l#k zya09cr`woxZvOl!14p>|(=A6jH-EaFNayBHw+iXp{DaaH)Xkr|c$!w-&ss^+cfAi=jLQT7&B%h_)s~;Ua$qH~

  • VC|wfs(bH{w*M#t4pgfa?c~;Q^C_WGvtV;%)XfgJJepmL83;(r95-fkyH{EeUq#K3txe&aUK zL5$=4&v6}8_+R0AjKV*RYdd_vcmn)j%RgW|i|gSE|9f2X$Kj+uV7vt04j*ICT<9nZ zA7i|YYuWJWT;C7C+vOQ+>;rGx8*6+GK8PPVI=2@yKLsCW#DTZ-Ki=pKUOE%!4h~Xy z`qq^81ecD!6`kbZy~Z2|?=$GED(Sq)PulBNI{NnXrw%^Gc-q0o8gDyz*vp$9Q$gqE zraSlqBg?@jYJ8H$Cu@9fjqjuJeKo$H#`o9w0UAG$ogHVV|0s})#Q-Vqv~s_`Q={#cD4rSYRRevHPC)%fF#I!F1AGw4h|>FAtf zr~i13KVIV}X#7NtPt*8xjnB~dOpTvpY;@Q+Mf0D`&Z@KRpQ`cGG=93qpP=z4YWxh1 zKS|?fYW&IUyJFj(ERE0B_#BPT)%ZM(&)4_@jW5*rBIBnb|Hi>6I!E;}!4GFV&e<0H z2*$@69|@iYe|>R(!hhzd&+Lo-Vx-`MjE^(21y7*f2s>NwG&rPlSeFZ)27`Uke-Yas zxEN4B1~Ku(*+Vo}&|*~|z6@mc_3w@|(OdlxI1Io@B1)WFXK`RBV74$4s-x)$* zfzX#O^ntQ+24&?8x{AVsUMy&vpjWB-Fu0}hm$#6QW4((Eql$RQn}r@A)@|T5tuaF-QavIB#o?%3xe*#g&n<3<-LS7~0wL-pD$S)J}tAzX(A*X$| zNza2q{%0Y7SI9pQ@=hV|L-_#w0HUyml_TuQ5ptS|k$f3Z$kz%vo$W#L8-)CBA-`A1 zpB8f3LxJ?aCglGT@&vRik|z^|9y*ho^ydnBp^z^X@-;$E`*0He2SR?Ekl!KXJB6Ii zgCYHY6Y|f6JQkfh$$Jrnp5a6hZ>Eq>74lPryhg~E3i(DMZx`}yLVkykKO*G65ppzr z!&@ZIeH<&!fh-n0`Z4A|OYrD-7(ZL^U>IK_c(ixM&k;P@E#pfCk9NoSxq?UgVf;M7 zqyDr09FwfxWEbpV{A9ty9>z}*JnUioRKY_TrEI!!7 z_!)v%>|t`)!6@Qq6!9{O_!vbzj6y%7(90w(|o&U(rMib{g(rbO{S84p*G$wT}Fm>gjFDThKeF4e#30p9-y<8TEY){t(A;r6^ z1)we=+JetvJF1cLJ1kR3=#m{IcFhQvLStBGu4qYiLD;WQ*`J1n>(JW*JH1_+ zfD_=_7&M5p4cIk2B1~&4N65j4bibq@-9O36byv>W_tO{%blfNj5`M%UEv}_L4E2p? z$U``Jf5xrdp>G5{9+n{CM=Z_Z)p%bAgXyB>q`uV}E(7Ds`4-Af$5suu1-Kj++}#@P zS>WaztiVaH0*o{NjGykN zXt<-}Fh`;YG^gX*;>8@j8{GGM83vnkcY|A)jBzH?qB}j_GyC$nXm_~l`XirZW+-4? z-zx(RgUw|X3|;EDk%J9`%~89-H4eqOOHsu85*h-VQ)>EhwDMRMbU(LG$Gs2S4>euH z>bMJs$oV2&6~ zyc?s$bpTi5l8!U9eD008D5j5LPRE@L+@dfP_9N8vT?gD*QQ-WT^G1VfiW2v7l(<~X ztsA1S?=Ik?v2QTu=F#9TiW2t$aOb$#N89kI?PD?40P0z%iF>*W+(lYG{{uL6ye6|;$0cHI22C@}>9{GtVL2wu>9|JV zjtfKKo~PM&4RB~8VNSCEhu6Jp;)e27D6A1T} zhPx5CK|-G&lpNs(!8kSE`xTrV%M)&@hI>K5(Hwys;TCAPcN84?lOuYbhBL6HC+(B= z5bl38+#m%PPs-p3w+lGfyMYPtCk;5MN6HBIhNf=@a3rUErufOZ;qnyRU=DM|l_4ns@k+~QrN;D$xO)halei;;8F*P!51ILsB-s^E@^fLo{Ff(nkF<*NC=2{>84 zi4kzu1D6GVDvzWHxL1K&AaKbMaFeh`EOFG%$WgxN_FV?tJjf~DKKPMy!@a8DFlAxR z4L2T>JgKi=1l&3WhpA1M`gSU~0TFP+PO{_06v)!osg(zvCroXX(%VbH^+so-mRkp& z%~HM*ZbSs!ZUvVb0k=oNjf{ZXr{FNuXO8k&x6hYl+b8dHZn*vm4nuS1+;Afm+?WWs zNeXUk1YDkiJ5Iq3*YdeS!Qrt7b7Y^6tIe|0JB`CwJ=Jlo3JzT`b8h-JDL6E#E^${Y zI5dGSaknTqRM{?Z_bND4#V&Cj3J$Lsbcx%o;81le+$1fZ_W(!vK=m1y%n`5S_Ga0* zYz|}Lblg4#mlFZEU%}-@!1)lFv`@~v-0bV6;PNBr>#yJnBH)H8xWWjykqWLz!4)B& zF|ODkM8U3?|y&v>C^a$ zNZs$RULi6pV@ybw;@-WL_KKJ}0{Qcn)N5o7yyS z)q&2{`1?)gO8ou0vl)NC=xoB@k2)Lh_l?ea{C%u*3I1;Atij*T16B0*n=|R}*9+i6U$4cq%hS^QDA9f?#nLEE}V_Ei=VbvSUUJ1pP^{I|6`(0@JMsqCo zh2MBv^1Gq!*k%2Jkf-dykgx2a(4MB=Wsin}Wsilj${r8B*0g=75!=6-{yu|H2xH!s z{2;&b+?ITQX!{n(eA|=n3q9S${CnSqYjzd9E%{#VpS3;tm!V%b(Z1cZ&-W<&CgNvY zyJO$qdhOV^2fw%Rdk4Sw@Y{>uhxmPr-zWI(!|!wazQpe>{Qi#LKk$1OzxVO`0Kbp$ z`zL;%;`bSTU*PwzUOPT}vzIw<$G$gv1&pDqKJGOB_K1=8wh_S2=wk=Y&xUVy`+=(- z@66ejJ=93@F3XACXdJuBXi~9+>`LZ2Fk;nX^RvC#?QfPPE~Py8&d)Y?#2Se^&V2Ir z?0AxY!FJ5Q<&lwzi@6n%=iBUJZiVu8vx~V6w9?VdF6LGU zk&tM2F}K5gn_bMUP%I(c?P6}D9jWPV7jrvUce|L|$ZmHrx1rJPVs7DMJWdFL1{M4$EQGCtxDoFYtz2H$*h<$mP0cHsnz8?PtzmlT9b&um#S1)P#s6Y>@jIbC zQ2sAlIc2w$zKp;8BHlR%{6un zQT%(Lj@*VG!H(P6A(4GPzIaKG#|}ev7zhiFxau&}Q5|aQmV{O|v=)ULYa8mCDa#E? zbzk#trC6Mp9;g=2o2$L(DOS|i&Bpo%e=m! zp>AoYVeX1L3^VGR8r2FyN$+dE)IGQdYRX&YT4T?DYruCln6wMEad~}sq3?C|?}2ju z66G9wc-KTOGdd zXl5OKfP5Gx5cEv=NUICpUpndn|89t7GNsluhbvV;c=kZapUSssu9u4yr7M?LV}K%0 zQJ@XMBlxX{UrQc8&!g6mQ(pvH2aiI1N^%~XlFSLUoNZS#9Mz%?HT=cW7WsLYm}FBu zR6Kbe2|s$dEkF|+!}#mrsj{Vr`iQHtdmL3(%o|uPQ*ur7Or_3B-yW#6xBZ{3wAQi# zy&a=eW=me+lshUpy~PojgFk%5;V^Gv{v(*-GuGlS?S0#~XLbvgU4z`8){hE`j5NKE z(bmg-{N~$y$Kd}g<6d+c_oyT1f<2sb{JDs|3HTIbT&X`Xt#o3DqOX)@z8=#68S zecDL~pON^<2F2TLzpx=4AVDf5+j?2=UW<<>lYfyW=`muRK^CG};zAJS9-_ZTCj!d#Lv@`Uh36l=CN&#Bd+o_F^QHha zW9MLctHucqf1-MyZPipCfJFb@2ik(2^Au&Pe%TW%c2enS9%LB$q7Mz~l zIpL9>JJ}Y|6CY{0PCy*%{cSQHzTBaN1G+oznyA86;y(Z1wV59Bvv#HWGh zZ(E^s!1Gl|iTAQSyzTH_qrws1Ybq0|!^snl z_(wn~&&Uzq0ZLVh9Pz&cr931@{2xG%XB_8W#x>5Sw2hq$J1 z56O}LXP~Dsj`RC*y1Y;ifB85K18ZY zc-jY@_6C)X_Cf!igZCP@Ie4G(xP$i_uQ>Ps`_|gl7h{azEtQG9*teYyiI>jni8Ic0 z@bN~ggHJH%Yy#CXf@xwKKgvO_8{7B;-hyBND{3wkdt?^?teyqkHr}5)7e!RvX zukjO%#~t=fWZ%Bq^(9gBPt*8xjnB~dOpTwU@sl-vipEdX_-PtH-FU@e|B0Ia3C7zF z{}~#8lE%-}_>(n0OXIUOK1btoH9k+{^Nr6O_7!M+p~e?!e6hyQ()igLU!w7IG`>{h z=Nf)-bEGiw%|$D8);uD zc)I8HMSpgsBYX_IH~Db`qx*jU3n>&RZqPBHe%xs2Uf|y-_Fdn^AE%Q)-P344bstgi zbWiLLqY4C_CH#5!%lA3I1Txxhno-;&8O6pB} z?->R=yTqGs7%ddpA|XFh$YD^6i1%DU_fAk_SO8JF0}9Vxb55#Poo& z{lP(LUmq{1kHUk-37V|x2?;$Y7-kRhndt##;X!H7IWH)U`K|b?MY!1_9Lj}-18pQc zD1FpH6t`zPT#X2an|%w!UX&vX2O1(gD6=2*9q?9swIbXc5f0_f!hxPe;XqlupaH~3 zd@nU#yqD5M@u2~+c&Cc+pe$Zc7B48>yS<>d3;Hub**!&;;}W57uF!{icP{A%ttNXw zY0N_O3JMRpUC>7bW&74cPWzdV|KCBa^e*G$Rqs5pkNHwQp7cU~GQ|UVE>Xzm6NMcA znY=;BHw*bSLVmrF-!J6P3i&P}-y`Io3;9<9yimw%gnT7Y z$kzxtjlBrZ$`SHk2>I`Y{4Ju8|3k=WpAEwIL7zzS0Ynk+6rzyRck(1J5%MY_Zx-@Z zLVl@`|5(Ux67q+H{5c{2y^y~rZpG@|IQ7+)rM z2pL~4c=R8PuMj-?1IC{!c(iZEqcSmlXt#_%P4H-sj9(ylv@gb=E_k#T#$)2g!lOR3 zei$1~^cMCpeum%yVmxkO%pdkKex~4IALCKknLq4fe3sy0ALFwH5BnIOBY4=y_*}um zKE~$>Ua^nKVHcyYhf&zUDB@=n@iL0|7)3mcLO-L>i)tI@Xig>N@$vDP*QYO^Th}@} zqj70h%QE5nncM3(&LtT_PGUQsPiB9oC@QVx7y?aY-qYCM>FjTM8Yk(T@SW4sGdag~ zrgNp~Q@D`pNasq@xt0vBC4+0p;94@cmJF^XgKNp)S~9qn46Y@EYsutVGP#yav5Py` zlF7AXaxIx$OD5Nn$+cv1Et8m*@NLoMgKFoeZ4>xT)|RI;V|8CEGj$JTElc;()~G185-YE9_sMPW(tez|NS;=V|reuyS6v?(fC$+uw z98-L{dS#vEp4?*JGTgC_+C>J7m-uww|Bvd@f6^}KR?*q{-(1(A7miZPlnuqLuzLM* z!^l?WqTOnF6~z-;)-11XYM2mes1LR94cTk!s#h+pY^ZOnQ~CPFB~21lC|$9#x-qnzWE3;r)y78|6P7fDmO_G0Lt8`Dpv%Nn*gdQ(0o~W=NB2K+ zxFtKByzj+8s^f+zNQoP%;b^YwhQqDbp$|hN;{blrNqv|CI&d@|Un@bvkJwe>TBhSo z;Aku(oz(XO2oDGYN`gS8T;FFq2jk9c{B)Nq^hxwLvE_QUU~>tCibx$GGojuH)tf4dcg}E@E}u2T|hM zh8xCjqtI6}!Z7ZS0_RILjGLpt-3HusQQ&gWF-3!W4Y*%Kq3;SjMvVq{@+jVy=qmMm z-VYqIFwE)uX9q_cMwWt-O`9 zO^zlVc~RoFbb+JwLHxJePT(+Y4|6*1Yv2mPP<*{n)t7x-bht}^TNZ`BkASO)0+)+N z_-c8`AbL731rEyrVNS7M#Jw0L?$a)Cbp9g#Tdp4( zC9*oq>9{Q5pfb$qxJKa6gu|SU`yp_s`e9DT{T4X<4|6*1p8!n@Lt*c7Exlv078gyt z6~N(tnA7!b0tj7xnA3500EaF*%-sn4FeF_eJzfM3%YR|+KH%h7l{{n9@yA8-ITLBz~Yz!ymgroIp z$%8evDDlRV0FH3eHQY781tF(+6YwKPxKn`(DEqV0KJTi2iCd!S>i~|zlRi10B3{Ss zRB%H{8Jrt#w}Qjak~ufrs|xPu2)I28E+qnPuY$u+l{vR~_bIqw1l)cFH#`E)cY>XN zBO>5>DL4!*nIrq?+*-Aq`U5BHOHu^fc;K?&Pvw>z0Z046OB~f}a&Gb730x8UNM9cU z!MWk~DL71lm~+F;z|EZc7t+^{!(8>XDmXb0cGGvKf*TM)-yYzy;7{>lO2wR;zLA(r z&x0@Fj^Z$P`+%zwI4T!%q;IoUZo7dS0~zT{BoG|oeyHL0i)R>w!%&|&H(W3AY=dwZ z!gq-qrr>11>ZWhJf*TV--wXveHUh3h!C@%KoLjt$6r8+|xZxTU9EMt5>RYGaxK&m-==pI9zs#dsV?@MZoP z4MJpG2AsTKNf}XkP1y??BnIxTEUa6QKyfCn-_>wcs3f04raHpauc#3_ya$=DYyhj)7l;dkudA$I?E zaFZIMD-AM+lE7}J5pyfcW=~W8xcqiXb^L*X8!1<0%H~)p+r8^mSUn~5*!*I14lMGC z@Oc+?1fEP$CA$Mf4u0N6dw?iy?;j%65F_i#VJs}^zSS_tK6y#OMS1g!jI7R%m?u*L zO$BX5$OTVR@wnplHrNz%0~D+Yu;8 z$!jD3f&l&9!pb8brA6UmmIgb$CY710Az#ywmqNaIEIiMZ;`MncIk)EoVyc3jsaANO zCoef>Nw5=d-Uy98PbrfeYe{%crWnOMCt+PNav{ib4>^_7RvMVpSrF5~t_or{#_dVT z3lzj`irb#j%acPX`fW~|=_x(_#QD47GpVyEW_wDk@W~4lA;k8Scnety$)>n{(6*^44RmI~Hn>b&T zv^}M;-Mrp=)sBtZ1GgprGgRC@I%JN`d(u0<(AxpKV?N(BvY@?BD5s4iln)&-p12)o zM}rK?akQ8~_WUOeuBC7riw}Qy2l5wD{`1n;ZNAj9k=uNk#gokBjzeI%tiQb06Il!GAhf^QG1@0;tVcMhuHLco?_yPxfR(Zm8GZ7F+6_H)BI_r zi0jqgKfP(t%6D=darL4oD%Py1t86tqzGtL8#)U9JgnMSxD{%wv{lj`kxVVb}h&6qm z25Op?FUQu1hMDBsXKg(cs;zCVYiYsOyQ!We-)EM*Hq;tAH=V@3B;V&waR!M4Nxm%W6KfKLh1+#t*A_^_#3HVYP%a&$D(4yM63XdzzDRBgi2}+G@bxS~# zZ_X(5o|Kj4fSTz@s|8QQtuGA%5u&{%W8$s1{_F3~5VVl9QAUvHr7$1bVaClH*!Wf5 z*q=DU#Qqb2B-1y}^v_$_nzM4r5_}D14)l#TrTt#W3-CCbu@3Oj3t>qgS=$mN!7S>s@c~WBs`qJzO;pNmDKhT%% z2*OB4`s(YgJPFY#El8Vsl%QR*7u;n_TpnCF> z8$UDr7tl=3YAF4s+CHRLE%Ki~PM_nM$u#_&k+9Qzk^KRXmw~%iExH5@r0CeX{o2KC50C?TDWhzg78I zIs;~buvAUx+x6$2IOq5)UT}nt2}-5LCw4?5|F+_j?W@}29niSX0O)P{UI z6qfztsFnA;5%>C52Q==-C=c8_US;J`o?n`mJ9iG1$!juoyiDMcotMWl8aI*G!#wk{ zE3zqHa4UJk;aQeHXD)Iye_qMyTUT3yRrD56j^mVT;y(|0pI!A0VL8*lu{w)l9Vf5HHx5fDC z9niSzdA99g*;baHJ6~km-(})hwvmUDZEuHpD%tiAhiA#$-0TuH*WQudj$HfXjZ5CX z;qwPRbQs5St*owQm6~hs%5#xfVp7Y z)K&XC0tw7-PRr7=(DKTX)+W~G2c`N3+Cv<&PyotWn^#O5Q1{z9FW(i!uwWyAgQ@Q+-2CdGB%Dwtwc%x8Y*K*R)P zK(^{H;_S2FmY4r@;k4BbXi_(ag;@i$r05O{v+-f46OFOcr5+Y$hv@#WFdN(5VPQ7X zvZK4h!t5aR5f2Nqah7Tppv%L;tN^{#!@~U8wS9jz_?W7{ePd+UIU`S)a1>H6`>?P; zwmgPRtp#!x;RqEIl*-h)Du;#+D66YJ38$IRv9?L8itf5&S9zb=ju1)RoJ3}&ImybT zZcZYzLWo@ACz1JcZw)2AKJDGy-D)n$p5I{-%Ow_SK%k)X#Zf7xOKo$C^0L&oIr)?2lHo&u4spMkKbc z_z=M~pH}uWmO`sB`J5-b$WIhZ^Djy$OKJsUAGeA|c*u@mJ7TMYhkxErBR4rNG6tH3 zazx{h8yBKf|C`eXd%&5U(`>o8qKU5;+r!;HX0BWqqI~ZH_1{wXw~m?Xq7>{|MISRy zu3Ckaf{ijx!*f;977o=d!oCU7jVSpDycu~HA{XuZM04HJ`WAeVNy%mDHO)_5d=Jqb zxn6!;ht1Euk$1p1%|*+^QB!gPhC>-5o#e321;184fsywze-caiv_3Jp(Tx**1tSa~Ijs;oQMa3EU--`1cRGiUNad7{|Diy89v867% zLz->seut{MV9dG9C}kC85pD(a0N9Yvhf#Nyu#aYC*FoJ+m}I>kOmr}}_H;d=1>i$< zmpoh(DKEXW$?F21Lx>0LR8J_e0dtK!tw)C(!s=3E+-k1Iy-6?ju-ampi>V8tHQ4+{ zc2t(M*7R&zCEpg1bqlgqf?KB+LC{QZ30Q*YY9COn=W>Y_UgtH}wOU6U`4>@68h7<{ zMWvT4kGP7;4#q-<){OTH)QU=p4VZVzqNj?gLJny~{gc^>TGY~gO+{7fs;ZicWKEUp zbfR7x7Vp`#f>l&0aIL88bTvS+v6-a@g4JXNp3tgw{#-|uEv6dFwsz{#dBJc*dc;-P zyG7qB2W{3YfaNhIIbgodD=eQf*nmS?Z9g|xp^mxKT8LnRRXNZJuUKN8HtLuoIDx2H z>)erRF*u~haIzN$a*ZCba_V$E@pT}NZ&}I>l&=KR)R^^?l_ggHM}tlwEVG1EW5YsIpBfe%!nG^p3wwrqqX5#?ORaY+ z<%h z-&BXOEqF~vgC5eVy`EKVs!PSexL5W-p?gN+oqV{-C|| zbjzqiq(@xKh!rh^N=j7sg65{>cH5v-2h2^5w&4msq^;w@|F#aQ@^)jP))Al^F?Pek z&u6@fzb+@|9ja1M9&{k$Llg_!6HuNbYntm>LR)(_q1I!2IBa$CX|i+eeg32e{Ql|Hr}*Q>_!Fn6`s0rECwN;+{Qj5yaVPy6 zB7dBxcc1D~zkiM2Oyx;<+>wO-hb;-4y-32!pZk-3fkTcr`xDyyaW($LsU!SxBPkIV z`~406xD(%l2#M(5cd_5U#cz(_X}FcWQg%K5_TczO_Nj+xQq!SrX^!&NXwp8>3#$LyV8cw_lV%rgel>Ax7w@gtg<&@Y94MVKIk@?c;^pNAi<%Qc=nm`-fV1JzW%<}8?@+MeRU-PU zjD%@}c=tpIpF_j~`MJo(1QY>7#K`r<<;HZvJ#bm5v_E^8BGAD^9|X z7WJ(!MF>XwB60|Q9wH%KeY_A|0OdV<1US};fnK`LCnMwt8!s#=uZ+`IXWSHeh1v;J z9ykMKjIf~e(kz1_VfrhdHi}-Ev{B9%{%jPzuO?CIt5g)@7%N6P{mn+{@2?Q{I15W} zXGpA_1S|anW*>qA21n1&B|7ZkE&=F+W)7uilM?FkxQxK#EHFK;kzm*72L%5PP76oT zS}y#oaK90>e31;CMLOBR#~AtGrwN(I6Kl-I^*n{AeIEG(C<-6T&asxwfp}`VITk(+ zyFuCeLV9pEX+8Kt#lH#Hy(~W7Sn1#s4BDZ__V2}ZY@%+KoCjwye-D&C_a;aDRiKHC zBRasC-x+wmtE z&x5z)Pcr@lo*EfBk0;4^4U}pLIpX(#PG%hE-^cX=g{NI$suliU;+lx*Nv3J0<>+kf z7zgh$hB|n!G10;M*!e0_ffr}dE^_z>jB_1)jB&Yxk2P*~@Nvci4nE%aqk~T{K6UWD z4ElmmIxq5foP$p?W;ys|<8%k#N8|fyd_RrvukiykexSx5rSXF_ez3+5(fFYnKTP9~ z*7y{o&XK-jG(M>D!!>?{#;0ohNR2;M<40-yXpJAE@nbdqIE^2t@#8iAc;g&LdM9Z7 zM2%0=_;iiW(D+P^pQQ1VHGYc5Pc_bW*f&i(8@{*ZKV9Qb(D)NIeul=Mr13K~{$!2M z()etR&(Zi?jnC8geB(!s^cHIV1;#B7|00bq*7#W(KU?EVG=7f8mumc6ji0CSr#Q}3 z@_NcNzFgxgH2zeLpRe(!Y5W3>KV9P&YWx`*zewZH)cD256C%HZ=p^avaCvq+-Glq0 zzx+fg4>}t>0pkwoh(B8Jbf2cP#g7;KaK^_Qxq_!5a9`X{7YM#L`sqF%pV1~f%Zq@ z=(|Ib4C6t|&rt0{Lt^nGgIRdw2MZ5c zN#Q_i1kI%I;OUGI%f7`Te4Yr8d}QH47g9LT#e$BY@ZiU&;VVV>d=Vb`&%%SU@SrR_ z=*<)!bcY(gN`x;E;m3;bpe#Hn3lGZ9+y-Um)XDM*iSUIYJj$EJ4_ZZbgVqYVn&Jn4 zm7v=Ny+cqs%iGGAYN5AC=tccudO@p6A1FNnF1%IXhj9oY-|K7|MUO3-94 z=cykc`4CXc-a4Uow$O|A!t{bNJ3*I{UeJ$7ALs!=y`&F(oT_iBIE%i7_a)vXhCyG8 z)7j*kh(f-FDC9pC@`r`|aUoBm_<+wL3VZ=k;LjHF^+JAukZ%+6+lBm2A%8~5|03kC z3;BK_r?~*>?@JW=KO~BHX(M}*`-nn5ktpQZLY^<=i-mlJkhco?_k{d9A^(Yx`+Z!` zQADACC{gIo5%LNlUm)bmg?xjMUnJxo2zjTFd;MI`IHIugB%;utE#&ise3_6p2zg0> z;};VJzM3fPxlG7!5c2;K@`r@{IU)bOkiRYDUkdqtA>S0k^=~5z{nrv*Vi->d`5%S+ zWg-7W$bGRKA4?SYqlqp>IS6^CkUuEoJB9oOA^(?;gnWgNUm)aLh5Uy?ezTDOO2{7&@?ApyrjYLu@-Kuu zE|J@V7nqnmqlv@_j=7rI5!b z@py+3Ex}lYDDvk-A)h1UrwDnAkY6n1-xKm3LjI7DKPKe6h5T(He^1B*Sa+uM4kC(p zhY>}*6NNlm$n%9fB;+kZey))JNXYLH^1Fomc_II+kpErC&E7oTenb)PQA82%cp;xD z7ZwvXCLcU+f2lnCij3Ekp#uJ4-`9gl0 zke?ysD}?+)A>Sukoj}?5G;Exl0x!}hM zzC!SbjKzlmYZ}>cyx`{xeu7~HNIr?5dqegy9*bwl1~$%O{1m~%KE_WKJnUoqG{M6@ z#$%$u!oxnspCEYH$M_Qk591g=L-4SV@h1sh+Ltcmm^d*1OhI8c<6$qOu#-{P$0+P# z6!tI*I~Ya$j3Qn}5g%@sUAc1mws(CIvQIuD=D6{K?w>0CuR*OAVZq;oA9TuX+q zfosX&S~9qn46Y@EYsp|*3d&*igx0#%t;U3!ChS;xg5$x^WkKsJUz-DZ`d! zR8}yV&~SpCQP$%Urdsi^pDplMS#;{-5D|bqB(WcV*i!Xzhbq+{Z`gizl$L!;++mL| z?0_zhD{N2K#}gt8>4f?E#-)Zhubv-huO4>qILDqdq3Y`9x>YiWIP;!+L7S9YC*5-& z>y&#cG`Do}Ph-M9QnE6lQrl2Z@u+WM8#YJ{@`HZjW$9XI)*8ZclAw;~bN1slD`chk zP}u%xAuN==aT$48&jh(4_D%zm5C1@g721ERH~(D6uEF0`^>){vc%1$#`#uK#lhWFjq^E@FVsCaV_(?78#L49>Pg| ze*~}Uqcx!{2@-z9ek!h|zPEvUhCGCm`jT*=>iang=3WT`mAG*lt{Q6z&${4d2^^wh zZamfw)O?Zh(*;hdcpJFuG0xW=t*PO^^?W%I^SRq~5O^K;7H~I2fxBR4bhu;i zd?lKAp9b!UDB^9)!g_fWxYBI2Bh(??oe!BR{xSz=D=Hv#hs^1?8M)EnHb#l-h!PhI zQQ~$-i5rw3oqdbCz~KZ%M|s=`+-XXA$V(mf1#n}er$TkyF$K}#3Zuj| z0k=?zPhRTr{%@4H)WYcWtp{$gj7*_=yst!wn_h(bs-j0;>iTYu5|>yUoxXE{YmkvC zRFC(qC~xc zPL#OiQQ|I-68EzxanE&uyGJXJ4}eQm%0XW0xZYS##*%25({b5R;+laQ8>S6oF3rB{ zfEyPD?kV6#MS@|!PQa%{Z1F*y$=3WL)&PB+x1UPygcpI)a2sBMl{|a23;E4=dz}s6Du4Q-x zGybLFW&lTW!UganNBkfJQuXC2xEO}wxC{+f0$dUNtMDT| zXt)mG#t2+IC^^Dy)^K|jTmnOJ9Bq{=^^>^&>3kkqh3j4_qsdf;Q;vEK@Dt{a}l2_rEiXS;Q+%pPpB!{`;UQlqyM!>zK z;AFdVi}y_hH#&m8cNE;12)K_G+}H@XFBKf7e9XDoM}rrVSK%kyu^TQ{!O8xEaO1V| z=ndQ;p-)cx-Ed=o3kqCcP;zd#A_dov!(4I86kPuZxGlhC!M_T>0r-(~i}x7?H;}_z zaj|FE`mlt-oSVKP1xNWq&JDLk!42jxSKKqep$W5e42ggXVu4KJhDN}xR&ZDnVb0CI z7Zlvl5pZM95*dq%-gzeUas_mYB>;|Vw1I|>d<9n87mzEp7X{^f>?t+mrjYp&$naDx;amQI*+ z!;MjJcm&)fZkmFds^I7yC$--#QgB5Pa0?V%aRl5l1&1L#bCeD}-qi|jb_CoO1&1Lc zb8h;sQE(V)b&0!O!C{EfCGLI&hoMK8xMvjHya>3L6x=Ba?i{T=-T{u%SA}0$1l-38 zt~>(nO9fXE0cX_N@tzt17pvgrN5J(~aB|*H>C)3XNWoG6M$QcvRB*T@GUtXHqu|i> zcZo|=aOi@$Fh=rX&+Whppxg63!NG$v91 z27~ESGcwbrkw;bhhWwHO+CxS<)41HQIgBZKVbBOSiCHnmc))wV*K;5zCD>_H8IPLx zDo{;(I_Vx=81PnrDtwPYUn5tms4Ibl4+?~PuJvlKu+Bybx zZU{&HT1O2rHWJErAa|Xr?T;2Nr)}@f&Y$EyyLa0r7u@Gg+&?7FXghhuCoRos+rxD4Vd-|J z=LH2ty7##1c7_?|mzo0+%4f2U>Y{v3vv4_W`*!{Vd9csL&MPdGjPq-j?|Q25uyCYp ze;3-GvQV)RQt*b3>LLYZK<0c zXZ(6TwOCT=h6 zM?vJb@7|WvRsfu?D^NuxGR;FHrkp_TBBFXt(a@JvJ;(>=`54 zY@Ud7rXqQwGk;qiQj+i6-db?}jxmNOx1wKFUVE_2xAck5!fm~q@^Sww+Lqs5bi;w` zz4LdNMOXW;FWly1^1^L}Nd?E}#3aS-Xfv-}(z&>^W#Mzi$P%LCp!&L#vfhEyTVNG9TJ< z0=rqCk=I6Lzq?{s)!s$2&FyXXlqFZ~xA=~Bzi5xXCW*-j>=fa10{fKS#~I_#9WlOY z$7sG<(YI=k6~mr(Z<)VppT(=%_jjp%uS5GDTYK!DiUCS`kiy=3D|%IRw8vNNR^pKM z$Q0zEXV+7z_bZf->DJsV5BaFX>)R7Cmc7D4_gDf43T~G@Eyc3jilv~9N`Uvcz9vrd z0>*CYp$pnxZO`6T(3Th2cP5u`{{o~XQG_XI+aoah&oo)6SWf}w*m;2tW>K7jD`?vt z7F)anu^BC0xAuRdw05_!WN!p(?G$lqDRsOSM6x^F#$K%c&mLDeu4o+P6<=u>XU%@q z(%aKsACfIV*73dVvr%V)W#0P7=Hr0UakIwdk2|R;f5GmytJ|OGEZA0%HEeltdt6n4 zs8f&4FE$I>(Kl`>NZOv9P?guVyDh)HK!46{${!cc>|y9D4R)`R$bCy@w_k>ma?gcN zTyr5OAnWL!cC)Ou%Fc;dVL36wkrP8B(bRG~lWlGCiytW;raVhOQNO2DJ>0pWapYziNLCtZ%{3N69dJZ{7O!?E@!2 z+zmd#tVunbX?ixBiF0yu%I8()FQ~{bE6pyctXNQ)TQWCyc4hh8Q_FJmX^Hg` zGl7GOOS=Mj{GKh)I}=((w0qZl_3`fCZ#W?ckri#soEnO(Vs$Q^s#M;zvbmGM(jRg_WB1l_ll#a!Y0#NJCsC*c^ZsRL(0dHN1XL0#ci8 zM}GDz38@J)_cb~q7pX;*dV&*8X|0;zePiE#Wb0#tdOH&=Rfi?GA@ifV?)+x)N=KYB z!2{KlXmwXf@KKRql;AR!U{vEl&IC{Y#X}o*+>x-#5xJdUy(SMfrL}5;udY9ER{Njd z`=v9%QZ-NTId&%hJZE?Blg_{RdyY8GRsc}K_sNtXvGeAZWS13JoL*U0TwYvSSec(! z$Qtag-7p2&B_$RJ3B4Z)&9Wn1&^~%69h5Y8!EgBJUMDUDRq`Rnn6 zZdi8T;#-~Rl$yiR`Gc3*@A$mols`D4lGjV?eY)Nesk6N*>3qtRMylxyTz>hPuMD1az?n{|nWuBTowbdh%&RnxnKH%^rMVFR zl;>G82`Epi6E47)#rc)xrSY#z4mUPq+nc>o~Q zBa~FTr6n)BBAaeKsokZy46i}=_Ir*+g6Zu7(MSHJ=G2+}US4~VBW^3f>aqh~kbN?Lch}ufGm0qQS-(*U2)f7L!b%5`^<+HVh zEVYMK@WH|1TgN}P>0C#&vVyOcDM3SyT*24K!Uoc}ENS?Ufe=k4!ae$MjCuUO=WRF?Bkl~hM6=R3N= zQ8^>MwBwOd&STSF{@=y3?|IJ=b$EJ}a{ieq%~ezE{dCz6{yh2dtQ{JSzXwevW88mjZyA{rx09NaUkOem!Sy9=jp6_fq}J=M`6yPi5)c%DnuNY`ngK zCcM=hBLIUi@WRGNwk`L3eco;7KKSvi4qIaR_>zwE&+h?1+FucA&nd1bubh`(R(aaovb@S^)R13w z^}<#bLBHoUcfTn{mf!Qbs~@(qsPcQ>aQB;JZ1j8HboI;3FmCjF{%RQb`bu_^(?7d^ z;nmk{8stck$ici&Ybd9_wPjvi^Jz`ZwaCN2$qZ2QFztc)mpnRh$>q*Gl!|#C(hJ(6 zTR#7RwDi<-J$^@wo}U7MJbYgmo;!EWyzJ6E8mg4eEoIebue%q#bxCc)D?aZ z4m!26B>S|=^85;_Umu72XIuWLUjKAVU!KmLSAA^mO+Rp$Dyvu1@)e=RT5My%>X+B^ ziA!-f!w}1Fm|2fX=lB#)jec#TmZ#Fh&pY`j#Nsc(FN2Hc>fk;9b z#ts#gvra9qC@wf14Wp!_a$$biT*|KtMd#`QDK9R>dymM8O#)MrUl6VZRV~Z!*=!iO zwozX{bW`?*D|gO!7$xdV+3NE8rH%QkTk9HIu(5&Yh_}des9EvoKY#q%w1L$xII}`3 z=UG7&Lo}4XZEhHs{LlxVI%4%a0syk&Co(G>HK#nktQboh)G1SD+~^9@E6+`?C}-vQ zA6JaC^4#L6Jnv@hAM(qglP_~vZ{=Bd<=HNitLE6a@h?1Z@2RVDojE2|^BjBD&ar;K zd9U)<7kjH5ahlKZ96Lh}KrlUIi$6u#rKR~L<(2uR**PWoEW;K_44Pmr_eZZ%**Wg|h9K~&{3tu7=d5gKt*_w;o)>Cvt*0$S&_7QyrO9fl0cW7pFWvZ#tpvXkJ9hGLD#Mu6JxvG`s6leMF{w!thnx>1U zI3l*jw$Ab`Go_hoN-zD}jlcTK`GYE)DV2J8N@d?y=zzbCgV-zi4G@5$@R zcd8NN_v9nl${6v4=$bPEDfoc zm&Tc>R-!bjr==I{_C8J`b3~wwbmlD!wbZdGBa-w7X^xtr=H!Q-=(Drm7tRz(y*x!3$VZW) zuP%7^XB&QU|AUSQ1Cs%W#mvF<)v&ejvO-#dDQE~SHOzR=tJZn(Ug@1zzpB2rt{I1P zq?$>d*UWRK-ueEgIc=8<09#A1SWVuZ!JgMmxlXQnmoabeV9y(-TwdnhxLYHBz8nt) zzG0p>O}QS+5fx5^f0*a5|Bt=zfUl~^{-5`f7ea3VX-cF>5g~;R(gjgeBoR8hRQ0IRa|%1uIOTKsMs5>|L@E__uiTF?zfHbML!vCgMK8bQtQfv3JJ_Eh+7zA4J@Te?DiD&Z*Zv`ccGvaE2cdp_{4I z7PUUB>#?zGh0$u{dFuWS?w2=DE=NC!xGk)A(nl@ceR+P%_HE2ganb4lQQz6 zeNH{ruq|a92q}@Mh$iT(Nc4}&*6*&ocdr9fOT_n8)FcG-RZ`R&p9%UZ*;UcFNKt?z*nyOoN(o83+v{(Pq));?mOj zGxPH2%Eg;IY?}KmU9qTC#b!Snk+4Cuh0mB@RHE)v4=R!SGdd~|4jV*UY8)BfGgW+_ zP*^g%VvZbs7&>Wwcg&ZREJjIg5^d#EoS^JJVSjMPW& zk479umdQXcY~wTX&8G|~BefkOyZZnksQ`~?{JU~w*KZqb7jMnEcug~l|@{r8Frpvf$<6LG* z(+%A=OnR(?QC=+F)uN7sB9}=%>zEm*-1goH1~ugZ$7Q+(yUc!mXD4u(Za%~5Dc0AB zwcY)`4s-{2Ob?$D=MKqjqdmjjA=W;+zu(zT8KyhHVS4$Dcz3ARE_y(SJEXRa_V(SO z+_@WfouPimXrHKiiyi1I8BzCs((skpuY8|*&bg1~7#-rp7sFRFqi*l%zH;9KuPwg% z!kbPpeZ^H9=POy)7i>9t^6zgM<;BunE#fxeg_kiMKizt3>d=o3YRWng5bMWBlj%-r zbm@YU3OOe>i5}wj;QWd*y0s{uP*kq+5jmPh4~?FB&9;xO`L5Hfqef(i&+&)< zbN=TGR(Chs(^VhWp4b02dEy-{u5N3T8%uY!=j`A5YDB_OUw>%zJ_DIU?%TP;bv4 zVk>97GUs}3Uwba zH8_?X?MEsn#!MQgt@se9j)^`xBXbQZZPa8m&I2)hvk)H#*u1hwunThN8LK>E&TeIu_xa9 z=z?F&7IwAAweY`2ow;;lk8NKY#m3TIE#fLPAhqy!CmoVM=iwnw8q}0)Bq0)=6Wqc@ zyoI#}jI@oOkf;GMna&Mtz@+xkVyywS=cWJXdR5`1UymJSnCCZOPI2DCLZkgkqHc}! z_WP~-8%Mm=t=XMs`?<>F+VB2>PkeU&30uwQrLlBZi`ra;+VA5|D<8VE`#(N43~aiv zw5Y&20hVaZr{4J1>!%K^G-&l_mX;P{Eu}UgBH}{}-aP-oqo&<%66I7>SdflzjGNgM zwdn)#-Bq{AUw|jb+7+p48yvb~#fl4yyIg$uFXk1Cr0(ezBATMMP9pBQR(~$ZymR7% zCbxV}X&G+8VtC=t^P}ALFAaL<@aytTre_CTQcra8FS+8!bCUKy=AJ3$C0K+>)d%>z zf))?9?KtCuKTMvdT3t|2ZQ4s#uWy;O?ff5qImEaib^7!Lpl0?*B|9XKbd};INv{s> z?T2}tcU7y{NLRBuPLxV>Cp+V+Sh}lBboC2Zc<|kK{3ECNp$4^naVa);kH+*~y(zEB zdjmfoZBBLdy(&9b7*?!*;%U2qg}0fo!wAqUMK6Uu4)w<>uT2P ze8Ier21Tz;8Eae>OLvutp2BO?zDpVw8cvZF|~IUHReaH9^bhCm_GFl z#b(9nvU<9o-f`NfiO+p~>wNRFS;eJ!@aSaS^0VeWwJ`I-v-_FMg3<-J`w_{>`cORZ z{0}xhvw7>!CRG}p?(=&Kucnqmaex1c4Y^}B-TdI@FU+vyhJd)RwC_0!e@L3z@D;ys|>Vv$6(e52!2v zDlWtw-1PZ#XZI;6D_U4sR$Mf*kDKeKI9na$qYBs>tcJ?S&oA#Yrf}wh+0zdiIchx4 zze~?OEGIiFW3;qAeOz|>=su(O-#>jcrp?)fCFw_%6ji1#%*yKBzjtQu3As7Qn7_EJ zX!e|n^zQjR(lZAQ>VH61M&`iu+``Jd@^rc5f7yb0g(Vg8-}$9w^GnO}DhdlkB&h`V zNdCzIjU(AUh`4PZ@qAn~jCx&PQ%#{aw`}s3dt$T8BgdSVP>RY&!3ig0Gx-8pTUFgi zWR@Y&V*IM?fB&As^vyPtc5Z*v(6o=Wfb=H+@ZiZG-Luj zim2lXoKeH>aHEww#Cs`fBw~IrX#kkwI8C2Ar>PdFky}YR?e3fa6W}xVk1Q zk;t@pSoa9`1)#Xe2ni<{j97d)N^%GB%9gs ztZ#kKGAT9eSAT@~mHUQoV!v`3JLFgWcD-NikxS))o?p?*XH4Zp`T|e-6)l(>COKn1 zo>Rk~)jG*$xf~ymP%AwkY3n0-eD^NArFGkIkDKiJdyeBQe**ocEBQ?vrH0)mquSl3 zY}dQZ9=S$Z;JJ-j{)~6OAg7mLm)qFEG#QqFyDP+$9)4h zaB53L-l19UfL-r(?a%{zT(HXUysoHxQstz=yaM@Zv9p(JByv@f`=HgGNL)@0``Ink z7^d2)3e|UnT$gsJ%7lgPGq!qkFf$7c|x;%PPPJ}Z;0!j$_f7ppMklIz0MZuq)D z4^z2uVd}+X9;RGQ4g1*}$^4KH-EB&C{W^M&yn8#*TSu$g zveD+-(b99ARnd{;IYF!%cAn|6z(o;zbJzV{c;K2S0e6R%L`Uv=kJ}@kPs;BPoE5ec zg(g+1*Ti$oU+>7DT>5eAEF*3uzM_Ub@#1O^V>5TXQ|*yq4BP7JU)0GL=KUXW_)+X; zJ&Kv68g`xggM(OsxBr8?(L-STil^;R=&D7fc;vAeB_OVUX z9-itJ=hfpli5BOE-@I*1a_-{1=H2GwYImF6usGi%A95RubL@#3zc`oGjzoU#8`zAW-8dRCS2iW+vR1FPMscEdg29yvQ2_k6jP=IxwZjysd%5#&ee z`#h6W!>%(ecy5fpnXBG=K4(TeXV=e&ozdod+=~Y1c{3s$$ctKPlNjvcSybx$3Pn~u z5-IUrEs$Bm{*THYGI zGO;^ODJrO#<94xZbH^#qP2`jYzlL4&s$kcgFZWt9>FQTL#>dK`y8sMUPJ_nVK%Z=5?*jZ(vI^G&t8&2D&5E4Mb-<8Bg+ z2eoR~Pv_TK&eosOb7Zx#(<*ICqu!!`v1sa<6CZj>$UcwA54~X`aJkCAD%f{ne?hbie#jao8?~#w& z7U|1-dNV%Yv?u9$&V#q3b=Olr3ksmuun*2k;DdPCNNx!x+%u?xy^pgj{cgAYaAS}3 zJL88NlPcMsgS0!p?{$lOuS-O(VV_$S>~r28mcl(UAkgXJX*=X~yWz`)zG(bCZbfH& zxiG0xzK!ATLF(+wFFj7yJQBH5_qcds4SU-o!QM7g9UkBw5)kNVCdJarvSq!+Zt$`_ zGPW@{-|Z(mM*qJrX3)zk-OCURF1QR_C5|#tfQU zOoOM}8uq-Fse$*Z@l#`<-^J5*$m@1PY}@l^(A>}&w1@6-yL<*cDA?P~ z=`qmLOp2wK)y<&Q8QY8*6fZw&laoJ#F46rYja6%U7Fo&1WCp%N^PtC(c@JjqYijR>R(QTd=pub8^T|_o(qeXA9uf`Py#SGQjXP z?Wb;WzV?LgYw@%i_O%zQ^fmX?@2Y&w|P-QYNT;CW5{>`1sFFmO6E7?!hGa}|t6?0TP)zYyKy zd}_4mQ+||@tt@LCiF~O0luxK(pZY!^3`L@=mME8T!(*IN1^5su7Bx>s_+Vp6HU-C3HzI z+M(J));$tg8|;rBvxc4VzTNDM{*h(cqS5qFxoS(1vxpFNL9=>(G9MQ-y{VhuQ9D8N zQNu|C$u;b!&s6EB7tH%;Q1sfAu~i05m$<`0(_c>31x@^7e0E`V{(2!UXnJ1eg+dtt zoS^wqus?dt8g|D2>}F?77&Ltk)q>{TyM9{lg`V2uR+{&D)4JNTMy}Lyik1{guN1Pv zk;tcxTbkK5?2EBTpfk!_Y4tjvC~NxI)6F-v{5cXi9$y8PW2eq3rDX*o>d+4U|v7{%^!E_=W3 zvd+H1p3BM#MkB2H}qoTX((Bjz+P2 zoX>va`7CWlh_|SmpE9aumUWIqGRbY@C^hW43nGz)k;p{jxnv|VE&g}bh_>{T#qh7F zEwkm8As*YKi3WtB%n@{ys`| z#235X-(|sjoWFnN`MY}vobK+j%8|%Pr@y&tNp zW_F_c-_7XmQ)<}X8%OJ+dy0%WLexd~>hX6T-F;t{tt{I*C6X3(*5K~(E^hpXV?0w#0fsc_B za08anXo$E+9on6?Dv`D^kZ<#o2DQ%=+YDK5U*c!;pOozD=f>^9-ObO7-`8C}Xz|se zO!+)ZndP3Fkzp{XAH5&E^h0jSK>R_M?)uTw2gUAjqbE6j^iX%JW|no1L~i4w$EDQp z=y|W!j2^0R;OL3laNHa{+=;c(gP|8R2=+sx`@@8fJ~@a|daK?!Y1a>ep(uEd8w4xj z2Z44(o@#1Y??~hmJ`i+T4G)ISNr|SCvFaD;&Qwy?w)>AwZpm$#XetTflCSA6xuHSA zrV{T*`+)-@@$S^-$ndo2$9Z*;C3~}$NimKp>R}MIj_{@nIY>yAyUg|Uv2zdQ7Jx*h zX-iYcxN-tY8G=7T9JT8QU^a@~;|Ac=_yMT>N?$d#tal``e-c~j>9iUifYYr8;GwPe zp0(=151zLffG&4O2cTBzzyauaxjwMkqXDf3R=Ppd%JK$QSD)cN9rTK1gGF2NRXMQa zVk0FBe}s5y*AJ{ID0YtrirKR&{=H<^7@`o(ul;CB_ zZ{Yl)%dk)>D0>s!dud zgB?&Vrzqb_$C5FH#d(YIrhd743`Dt3#m7`mEGkj?;$Z(uGF8i*;Ag5*)zK1V3+7i) zD9S;8%4GZz;+9=MiYKAiJ#G}=9zTjFsRMVlQ7kJSi9F3mvB9h1QQSP)ViadxU$Euq z$-lp4F^XL(xvAayv?fNe(}-%!B_73-LPjz2%u%dqG)FP+_Dbi?&nqdw&kI#N8H9fI zN3nCAKZ-}N+?=A>B?nbj6qc0B)4a#ATs~9}M}EqY_#;GXJc``KPa{{N*gbBjwnZbd zC91jQyJ~G&^+=>`vir??_!TugY~M_dlm$<|hvm;Hp~?69-zHDIqs7&26D@0lsY{DW z3JNQ|um0sk9rsGXV()c?k#TvIUf!svjG z3VKI-Wla8#%O8Q>mnmv=%J;|gyx{%%J2T@qw1MpnwH__JFg!zvW}|3hRjPe@X&Evp`hY)KRu*cCM#8Lo<1M275{ zQ+iH+saYcYh=Joy|a-4Q@6JLy%`zIew*l?Wu#s$4~`5lq$7NRG7%YqPC=57 zqKpyj*`TlC6I?7;j0rBDnK)|+vQp&yg=2g%*Wo{WcG)+WxhQOpiwtt@#Z~}06UQHx zC*P>^4kMB^k3?>u4)eapG>J7F4}Oa!THu>z{A<*iOE>n|_I08)elXj2b@Pr|`;it~ z+-qZu=2h<&UH*2d}?#4hiPNasHKUI$GH`CGPv)E=G1x!02u;w6B&ZB=ky@?+tbB z#fbQ!&Lf34)Xf;64RtdH@MnVu8RqbzJ|4L#G8zbRGX75%3-LD+iHJWNOA(P7NDwvT zcLnk#quz6J&6}lVwX)6rR%_er?NH0ocH@e#Ak z?9OJpG1#tbf;Jm@-w(0KwxB_w)>_NntF@N>QEM$*)1tQe*`u}AvbS8zYF*U$Eum%dp>6lwxQ4u> zCH!m_i&&(@X|pxR^S_1NorXOt9LwaBtJR);=DfZ;?b{;l8;O=Xy|%U7_hcEh z9NAZUTJGEk`CP4QxwT|jZEd+nYi-ND6xecC8PQ}{MqnQ1K9}|tz4~OV{%}0}c*7a8 zrg=?vV-!9=3iHNad2XzJ@1MLo`CDpD>)kKSEBWHh+!e98se@iSjDHeIv zY027S>YoWseWJFR`eM@mnO40tIgzQ^2&H4J2Sp8FqV~yt)$C@8m6stcu z7F+2pS#PX0#@^<<10;=|2V-OPi*-9|y;w-b$e*KAk`o6)e5Bb`xobFFF8bPL>?;$F7(WG`fxqe!#dD1l}{}|gl z>0~%sG`3Xf`uX>yrP0)glNyUAw~a+kb^6e3m9pK~D(}meo6ssNR;*I3(o$BuetfHZ zzarNB^q-@#mN7I(+n>-X-^E(};&X`F~nRnpc-4 zlXkW))uE%dv}twJrJdKN%ckzmHmwdj_N0EPj=EHbe^iGZ)uF@pk0m?pr`2Icb?B&$ zx^(u&?UKBm9k;bbM|HGmb?A^g-Z*pRlA@h$)9TPs9sW@rI{NzUQMR+~Q5|+vhmJj| zF4fTrz|n z@cVYjPT$YT`$L-NChu%})D}DB57DVEC+uup2KzcHcUH$}PshUONGREvd-YM8juAVl zqqf)~cLAh+S+uilD)${B9rJcphuj98bS&9f9ofE)6L(g}6i-KGR0g4)@ejHGkyDq- zs0_+GqhqC~qbz#LPU={t={R*Kb>wy+qvhI21Y}F)=HgLB&9an zt7XIXsa;dg8PQOPq~4K8%cRsn4F@+I(r{?o;cZJ&aVhB0Hc6@4CCwu(BJr2WRCQ@= ze0oXh=_69l7!f;jM8k_mV4t7lzMhWQnWscV^T=5v+ym zaQmdL-Dh6Is z7u4MgRPX^_2gH7{u+6B+g-N?+qGrwsukZ(kEvvQ3)`@v z^HnOorq!VQj<&H#O3i9Gu#NjwE52NHlKg~NQ<2?JeqWo?(oj{eHLmq(sUB41`dyIQ zu;DNi(qKO^9&fHR?2eQUG1rnt8U(4af}WjCG>F`$LvXDS%|=F=?bQ`0tuOa&n>LXD^DL^QeIKEU|wNKh5UDZY1#bJvb>7I z0wIrsQG57{WLd2G$oFyFPfg^@ce&h8kp8Oj|5y8}(l6iNb3Z#{Usc!FwEb1-ud4o4 zU0+pxP1nCF{qkLO_Y>5A|7(6#^{*;_f7dw3Ap5Gyud4o4<@c?k{Hm_6D!-=nS5^N1 z^?do>uKNk{kE;AjzF+Eog08P>{8x3odTHAU7|qBBc&f_`vND?=v@NxF@-8^QxS*(fQstz=yn@A&Btq2YR_>VETup5i4I$4Q zo|9Kzh(kx^C%hpTS%wN!2%i$8UaBG3Vdj!G5dS;;BMrXO%9AR+V-620D=RG@$ zUm*`Omml9(W*XP3vdrTOCEc>tI1O5U>}pNqkXqyPIP(a1saysmr`9=!OqhW9BWhxBROnSauh5PohYbUX2= zbU|5up`?p`_}{5*1+OiQ?UKA=ua)U&KzX5@ZJY}OVomUo~U@k8SG0Qs(-8&Q052177n>na?LoU$5k=7sK<`kFa z&$T1tv}Q*3+h%@6T%V%j`e1 zs6qy6X}JhvW@qV4e?2kLuy|2fQAMGt)TfS!r-t|}|cFDzP! zR!dM?rgz;nq1Ww5VV;G&C95dRyUr-g_nW&73%zAPPSFx4ZN91z+Iw&e+njd3hCz=U;J4@DxsVt`{maY>y7+W@rse3D&8{k>x&`-$+aa_VqUs(}8{cjl?YD`o?0paeZTP znvvf`tTFPNh#QRjrs8p6-@c||qmkcCd|_PQOnhtPHx~^sfc@*6i{{RNR!tC%wh%pl z{ra^K8Ag6fG0w_)xX{S&AZ|1AJBWLX{Jq5sz`lKZi+>sU`-m@%{C&iCMt(=p3enBK zzN6>>?0%xrba9}OpDxB2`TL4IBY$5p2UrF!`H4pN6{Wyk9H{U@V7bteADMp=u=|Nd zJBf>deS12ItBm~4V!e^ySv+mzcM)5R{4U~CVBelD;%ne8RA4mPMf?ct+tWpC2X;Tv zXjjoPrrXn1v;%fO(dd4npOL?x7;5Bq6H|=*ZsK?&zq?pqVx7V7 zFYY(+0P(1S2a3NLc#wD=*td7Ecp2FDufgJV;C;RF2a9)s<C_ z(H>Yn`jek%bd2Z>e5eBz-XHjI4QB)U`VSIAfc^E(L1Hwpum2!%D6p^pAdv&?uSds< zV}ZMQ`p1fVV86Y_in+i;wfu76Lo~b;_%IEx1fHVdbASspd=c<04POO3Tf;X17i;(q z;1e}`KXAE*9|K;d;irLDX!u27zrN$dE5N@0juYvLapHSm zzdy!_-+`xU{G|Fq6l%C3uwTD%q9yPgEx$eRJPmgSF4OS-z!e(K20lr{Lx4}w@Mz$M z9zIwc3hb}94i-7UZMFPkfhTD=-?)Cfm}^`=UX&Zxj~7dU{q`9zRsy@9Nc0eK4)6?0 zkoY1kKPeg!R~R@d?lo|dc*(%Y;xhxsM7;)XX?R@=lW7+N*At@*oGPXpxV~6n;0EGS z12+^88Mu*n$-s@pmj-SkQr*UfSxM2RqPu~ciChCW7v%FYpv-sS=T|^^ya#H1W6+H~RpE$(8-Nal2cNb?GxQDpOz&*wD2HszM zY2aR>K~oe=pCqi;dKkF37;WG_;y43mh)M%zii-@KCDt1_TYO;PzM`QU%wR)Ow4cZ{ zaDQ>Mfd`1?1|BGGHt-fahLd@92$8D7QkX$+sv@EHuB$?#bWpUv<&46kPRT!znM_zBrGkgQX zH!^$^!#6X03&XcEd>g~JGkgcb>lnV1;ky{Vo8fyHzL(+q7`~t32N-^k;lDEc5W^2M z{0PI3GW;0B>luEW;U^e=lHm;u|Bd0N7=D`JjSN4-@Usj*$MEwE|DE9%7=DrAO$@)p z@IM%Snc;sj{4a+8&G0J>zsm4y48P9s8w|h6@LLSO&G0)6Z)W&ihTjt(8}aEs3~yoh zeTF|^_(O(2V)$c*KVkS&hCgHYbB4cQ_)CVjGW-?8Uo-p-!`m4Cmf`Oh{+{6<82*vr zpBVm`;a?d3mEqqQ{+;3N4FAFKe;NLhVG%L?Bf@Z$;UtEW8ICcW!f-u?QyH$$a07-L zGTeya#tb)MxGBTU7;esR3x-=VoW^h~hFded7sG8BZp&~xhTAjTf#JOw-iP6i45u@^ zFTI>R#<&SQ8c!}$ysFkHy+EQV(@Jcr>ThEHI4F2ltP&ttfR;nGNBBOaZ|^5;j| z82M!kmor?!@B)SxGQ5c4N`@CRyoBMU3@>B&B!-tWd@{o;7(RvJQyE^#@G6E+WB7E2 z&tUjWhRGkguh*D}18;p-T_p5Yr9zLDXZ7`~a|TNu8T;oBI#o#8teUdQmA4By4@-3;Hu z@VyM*$MF3OKfv&V4F8qkhZugC;YT9fjQH~?!;dk%p5ezCeuCjA8Q#F~-xz+1;inni z$nY}^Kg;lQ3_s8C-x+>^;TIX+#PCZD|AXO|8U823|6=&x48Owgs|>%!@aqh}!SI_5 zzs2y|48OzhW`^Ho_&tXI!|)b{-)Hy(hCgKZBZfa__!EXdW%x6OKWF$0hQDNZE5lzg z{58YhFuaZ7ZyElM;qMv#f#Dw+{)yqA8UBUgUm5<5;olkF&hQ@$|CixE85U79-bA7U zDE{=pZCeYxzjHX@T!jx7a|z3LT3X=y&T|OMcT8H~eVJPbk5c$R@i^gC3gi6_!t$qs zEutgDcZ3g9c)VyrFVD15cz`&7u%xw!4irZixW71&uv6Y}aRy;|8`>h8C2l7SD4OA2 z*awXKzTyqS@|~I%c;Dzd!cP6NMT=JQO6O-`E$}|k0fc)Ytp(m^8%bEcv(y6bryWIj zw8BG0G2uxHA0*Bs?9^|NxP|aal|NQIV_ZK>z+{nzKX|Q0#9qPfG!o+_-$dz2#FwvS zNWOd>LGlx&C(@HBeMj}|C_hoTiPCpe|BmvjtK1#clgLi#*Ro%wn}+r4&hir3nJ7Jx zoptHq{ZrHJlc>KEr6;ndDn4Gf6tP$RxFlcCNh`*?C{p5Lo-bb?O2Z3pGM-DGs~@lV zDm^l8NxxQlN)qSG*Pc8*;Dwfl7yLr=VT>FvX;tw~u+#&de2w0V+h`v*4$IefWP7Rl zqn<8L#&wyl>ViLi1v~PJ?T$wIV~_y{57F92n|&}1U* zNYe9uRN$Wq=Sc~?m}ID4EF$H)Ds8M#zxzvra@Bum6xA+oN7cKvX#g`N4|oYl6_?Q7 za@@&&kn6uR^g{EPkPp(5{d8%BLcaX#=Z@iQ! zF9NB4bBVtz@qg0mB;O$UCds!*zD@ESlAB4sOY%LE{~@`Be>bkZh+mUQfvIEJzBWjE%{T2~(r60|Sh*IfXzf<~l zN-sh>`B^#1Gm^x<33?TG@wAR{e=Mp!7j1`yiElkbBGPA$yUOJ8MZi zK-ZT<`sR~9#1o|tQt5$2SBWG@*-lckkh0d$QdN}lGg+8 zM{<9X(oV1aVx+H(^dY_}eUQpNNM#?SvQJ{E2U6JwY1o%S`pQY)7Sac)?1NPHK`Q$o zm3@%PK1jp9dZe#{^u15|AXWcDs{Vyk{R^r37gF^vq|v{rq;CP~`+)R8s{Vyk^@dda z3#s}SQuQyS(Z3kf%3l_ez7I(sq#C!77}_EUQu?iwvq=_{l=}jC{ed55D}9SdALbF& zACTxGkpzjNlpG?j2R?-45hRb&^))1Ym81{zkeuPJ?ysy`rAe?Y4KfK>efsrm!b=#R#vZwcwc{HXLns{Vjf{Q;@^15)(|r0Ney zqd%IEzNMrO^Q_Vbsrmy_^#`Qt4@lJ?kg7i*js8HeR{gPz^kKeM`lOWo0EwM zz^WY~k0d-rZ$CVoQ~FLKeVF%^K1kKSkg9(nRsTY&{)JTi3u*LkbJB+m1ysEHlJr5U z{)JTi3#sgaRQ(I7`WMpZ-xj3rWYULqh_Vk-wHqWttw@5D*Gaj6q}+!`;-cbSCBl7!#f&moncLn=RqRDKR=`1xL>Zx!joI#B6@RDKSr`U_I|Ii&J)Nag2{hM%_~ zeW#H=tS6N|NTm-_>4Q}IAeBByr4Q23*Ov61PWrwleUNhflq509<7N8;&m*b&AGlKQ zk9MT*4AO`7ZMp1sNY%fPm=YCM^Axa}ry$il1!>Gv?MdI6qz~(4r4Lg14W!Zwsm2YY z8aI$?+&~)RrUU6ai}Yc=t@J^v{)JTi3#s%$Dt(YjAEcoVPN4kyY|{5L>4Q{uL8|&f zs`^5z`a-JuLK^kmhxDC8`hFpOkgC3rN-w0c4^r6&sqBL^?1R%Q`&N^_Ur8UNsxPFf zFQn23sq{fAeUOH}bkcV&>HCfJK`K3vY8?VON%{$79!aT3;$q!j_9cDik-pzaAEeR; zsq{fAeUM5Yq|ygz=<7uK&L@4_Ngt%DFQn27sp<=<>IAoq|ytSEA>F;lbl0R>hBD`f z(g&&ZK`MQaN*|=s2dVTy8v1Y(r2P33(uez5r4Mq3j4O~T?nA1057}GV1*zgaq!I6X zkiJVvUlQqqRQe#5K1ihxQt5+K`XCK`xam{&T}JwnNgrgMv=36%8*;F;3vxWk!%50^ z@Y-*G(sw!Oi;+G^r4Lf+gGA9H2~yf4rMfSJ9HZ;&Mf$EFeJP|5QpJ0TrJazfKOj|q zK%OM^LY_+UOkFQ-N>#nDB)#=WFC=bBMG~Z1KR~K_LLMjeK&p8Jay8+9Fl6j0#@Zf8uL{j(z}NA)+fD?%5F$yH>7G$$it*wNVQIZ zTt--}gMiNf_WCb_^j}T-8<2iTwLXJX>q$rzFCa^$K1kWVQl3llB3&;Q8>&67A-xSr zFQkf>kg8oE)wqXL;~sLk)CVcsSIRXcuh;cwk^XB*eb%5F$y zH>6=V292_NE$MAcdLie^{)1F@Ln^x=mEDlaZb)S}q_P{*u)8nmzmD`bA^nhQJVO@9 zav;x^^@hBH3@Aag&Dd~k&dLflwNVz^ug1nOCZ6xm^`2eJ+w?FB< zf%G;by^#6RPRQ9LpOe=EzfSUFl3$SA2I=V?KzeT^z0FB4j#au&&FlKhb5 zXC%Ld^z;rSy*H8G7Ni$a*$b)cg;e%JDtjT7y^zXYNW)$PE#((Clirr37gE^^sqBSR z_ChLqA(g$5%3esrUIbaC_ZHHN=Z$KKEDtjT-`T|m|FCbOCgH(P7`KW9UNL3%m z?+Ld`a?-O&4kS4Y(rdRNWXG*!2cCB-J0O)Ekjf57We23P15()msqBDMc0g{HE7 zkY4={Bs*>=JMes0)gMyX0jcbORCYirJ0O)Ekn3c*kgt*anPewf9?}mdnM3kuy?g|3 zgI#{pz9NmV|uDj#yCEC=!$l8=&ng{1Ujncqm33)z+A7?LwdE+=^v z$;U`;Ao(n$*IvWP-gRUzo_{NQA(g$5%3eriFQl>;QrQcs?1fbJLMnS9mA#P4UPxsx zq_P)M*$cTs+6B3mPvo{%LZRe8Yer5?xuB#$Gxgyb5M z50QL}34!gAcn^lL~eyMg~n_-m4lWcwk#Imx~Bb{tK1-$Qoe`xVuWkjnocmH$EJ zOM4(yoPxZZu$<>)`oBqjOR}XbAL%MyLdxxIB`zZ=_h6LxMv_mF+(PnWl5#Iauip=f zs_$Bp?v1GLNRzM#JPFxJNIzdnq+cW@(x0UCe^L5tl#WMEiZ5h;fRClQ;ulH@J&P!P zDW%^+>5owQ1v&TbTxk>{Vhs=S4yO- zafS#rZxwU&bdwT#_LmZRj;8dvlwL~dXHvS{J5lnlq4fGGjvl$kp-k^6CG;FY z>3Ni1Na@QdUG70B`4?0AZGx6k ziy-W(rEjHl`5QCohdrePzqgd&kE8UXDg8J~-$?1NQ~KMK zF5i`wdeWtYo-R^C&w-RK-<6i>Ih6iaN`IcxH&Oa8l-{6~!*3!b^mLOF`Ug?^fs{VF zwUd67l+b^)l;EFE>6cUb8cKhV(x0RB7b(5O9?%%NC`cEPAzFq&JWf>HVdIod;9;1WGTY z^hK1ul+rJt^y?}8W=ikAkE3U>lqh$Yl+a&9=}Rg7WJ5qyD0r>N`H;g-=g%~ zbVvUzDWU%aDWU%oO238D@1XRJl>R!UzfI}iP*VnFlM?pyloEP|Q~HsVeiWr|rS$(&dbG2{?0eQL%6<;Njg+vbgOt#dN$I00eH^7vrSuahy@b+Fq4bL={W40wm(ri6 z^yeu3LrVXV(toA&rrjKS_LUO$bd?hJ45IWyDg6jaFQ)Y6lzu9uUrgyYQ~K?c{tTtR zLFw;M`X7|uw7XMoODR!qwv=ekgD8DGr5{h}^C`W8($ApuD=7VHN`HjXU!?SxDg9eY zPwL^6TTe=q+f7Q8JBZQ`r1VLYUO?${D18N`Ur6bfQu;%b{&z}$iPGPv^zSMCXG(9> z(~DgAItpG4^;l)i$}S5f-alzum*-%shi1oYh(QSU0s_q-IopYR)m zA0YfD;Rgx7Mfk6T-zNMJ;dcl>On5V4+$3bka^EHVDB<@AKSuaJgx3?^LKrs}>iYKy zKSB5d!cP+Zknje=9})f=;g1PFMfelKPZR!>@J7O)5q^g7=Y*dn`~~6X2!BcVdBR%> z|DEtxgkK>1HQ^Tte?xc^;cbLpBK$4ke-QqT@XLh1C;U&sKM?*G;U5YAoA6JBUm^T6 z;a3U&LijbpzY@kxp6ZX^2){x2cfxNH-cI-}!uUQ=`Pg8n^A?| zB^)9A9^okA{}4_hyoE4sV%7EU6UO&J3V%R2h46=j>kb^RxV8xa1K za6`hl`Bm-Hi16ox@w{GL{{`VDguf(==jJLOH_hsLJnvTcE5gkQe@z(AkyZXTgz@}W z;cbNRoL1p)3FCRG!ru{YP567lc#f#@e;|zKc?$nX7|+8L{)sT2V=4SIVLbm)_!q)> zzM}B2g!iWRQPU%8-)R|tQe<4%moVaw!kq{s{wUm;FyfEGT?ixoDBP7W;*Y}n5k~w` zxEo=_ABDRUM*LB@2Vuk?g?kc4{84y+!iYZ#_acn=qwoQQ5q}i!O&IY<;XZ^Be-zFj z{0ZSq!iYaAKZ`KpkHXo65q}i!OBnG-;eLb>e-!Rdcq`!ngb{yK{y@TrKMD^bjQFGQ zV8Vz$3J)QS_@nSp!iYZ#A4nMSN8w?F5q}gOP8jh=;Sq!pe-s``81YBpQG^kH6dp|& z@kik?gb{xfK8P^lkHTXKBmO8njxgen!Uq#Z{84y3VZqwrM1h(8J+O&IY<;bRCR{wRDbVZ;pv1C ze-xfU81YBpJi>@S3eO~r_@i(>VZP!i)pNsI?2F%Fc3|0@ZY@S__vbqYbD{&O2Utog#RiDzf}_cswDhWN%*Id@Jl7(k4nN1m4yE(3BOYk{-z}S zOiB2clJF}f;ZI7!k0O|_5`1#UXO?7-DPNR5YhJ(s*Ih<;nUE>u-z>`I$6Cw0Y|3ND zSj()wl%>ufG>@&8+5P-%=giNF()sGdQkmJ`EK)mZTILQg3T2rCeZ7<7&WDy)4Kq{{f?lO?CG(@cGxVb#}ZiN0=2sLJSvD631{hCptjQYm%U2k`<@FYWltd z9O3kGU(Igs08uaW^wS24cB&_xUo4gO)B0RH##3jwqeWFgKhjuTZ&qJB@L1&<)%QKN zv^Wn(`z}@$>8Dj)v%ouaSm`kw!aT!R4siTyfa6~S94!MJEdv}a z0~{>_94!MJEdv}a0~{>_9W4VLEdw1b105{`9W4VLEdw1b105{`9W4VLErT2_gB&e` z94&(!ErT2_gB&e`94&(!ErT2_gB&fH8IGFF3`b99hNCDm!_kzP;i$^YaCBv6ILb0J z9Br8yj=IbY(&x==qz`kO?2XJ!(w9m4GD%-1>B}U2nWQh1^kF7Z*JqKwEYg=n`Vi}# zeA1Ui`m#u07U|0(eH2ME5lYo{*`yEg(!r!JoAhOqzHHK$P5QD)ABCJuiaD7SbTScj zl)k>CuP^EAOZq5CWcDR}2os8rfZ#~7uOHdhkM#8;eHfGukM#8;`}&c-exwgWMDhA7 zePeT+RTgBH=v`4*S>gO0d|3XdoQczm%17mu7f#MAE-En6`C3d}N!K_N$b{0;`7`tK z=Ngwevq#bFl7lKM3QNk1N=taQxfavaQjywnOV4!*O^~UI9bZyWSXQ=Regy?e{c3+L zrl+dt8Gf0&_R=qN*BG>dnN(@ik=7K!naWVMe$iDs7i%Gxt+aHm(q*nk^lWA&R#JMd zX(h{4?Gj?8t2*JjDWD`Pt|~Zjm5}YvR||^E3nvzq6_uKf8^wCE?@a(NnWv6>j2kQ1qCmnn7*JjR2)TLEwRi*i={YP z{8BBB5?V}^)vba+$FL`AEPcHcXPBqjTkJ53HaHVesQg6Pd^MyOU@nGuj=!eSbJ$WS zE-Uz|in6?t@_9uSnf*rnvyb)7pP2)H`!h}MN0~ehEhX1Fo)s@I(|-GNl9U`ahV(QgYvvc8D#p3ye%88DqvstGkn^yOSu#bYnP$niA{oBqmO;yOXG_pvMQw zC-e#1f9k7G%ZgTaCt*HVWerq!Cn4`(ylL8-X!T~|OAdWa5ylHs=9O55GLILi%$)6Y zTa@qD-APRMmP*EoRc|SeF{#RX4YsmLphXW%##H8&WG=k})fg+^-ncUUPQth?*ooT; zi#v(w({sm9pShr@xL|r-1#V+zE~t?A8|91VRpiYSy~_%Vb>nG<@*nH6d}m#qFk3mZ z`7Jyz0TlN1mlZ)K=nr`r!!aU+pv;I{h%qhN(_ogP242;ddryVgi}8F0Uce~Ka=DCS4Ab%ef@-@eEO(1Z z{4_YYRBOI6BD|`g_z(H?r^u}6IG*_=Ii4N(G?~$;0rZE)jN!C%2myA*KUroFWsZulpWr zJ*05nejdx+qu$xWU*{bIP7rSh)3+i4Z!+WE42+-Rc^}ul1xV4${ReOm??T4IPYVL= zyNB`cig+OJCC0-m(t+jTClrQ#CxEB7wX|J+lJO7uZ?`|L0SKxGUO6{-&jJVO!>ir~ z?>FF}{=h5J1}{At%v;EKW5Elu?^4DqNucj3#=AIyzV{h#eFA-dGTsLXcpZ=qs@Kk` zNx|)ht)UFwQ1F7y!Hf1@SInyfYJ&EBA%b^{oeQtaK3i$UOOZlkuX-!MrH0 z*YzEofG77k(s}2B7gUeYjQ2nS-VDZj8$3Ct-H%(36^xe=3+An5ywkx8^83Ft-lGY4 z+ZgX_@aDM2LAv&}gxz|(Oil?dH-qucPQaVOcu#;ARPGYS+Yf;_sJ@pmp4`7Bi1#q# zotJ?37UMmYfcF#Q{gi;$678zDU(eKF`}#B9@dk{Z2#CV&*o9Yy${<`Jn zFrM7sry_tikMV8=@ALrP*^Jk_kr1l_csDcNec%P@dz$eEVqc#ieg9#+_288Sl)Ihr zdN&c`_yAs8j0e4)SA$m>z?1tv>AYm@^D`@ecP!(b0Nz~zyptHOO*0{G4B%bMcqxRKYuUDc-y`}|x<|CYkl*Nb?V zuGObenh?v~Or*H!Lx@K-ads;qp6cl$UmnbO6Gk|D(fbVNU!3>YNIJ8J5jpRL(Ky%5 zHA>@h-k%5289N$B{*&{v4tDl-XS6upd51WA@>j+CWCEQ@z=*uujz`d016A-QA4z-6 zSHatqLua~F!TaMVJALH{LfED_?!)VGBW|Ry{cGHZ^WL3iSKqYhbjAVG$n~9`M`v_Y z!Fwm4_HeI)Hxj|XrXEY?*wy3S6YT2Id7cncEZT2Lsa<_vKGCke{V;i`vqP$AmyHXB zxXQx5>5GNhJDI7A8%JL(wQJ|j%kA3vm=$*Iyy;Xs-mud!e^}J_uV>heqh4p*^~Z&) z?RdYOXIE~?U+na~dXXJ(@TGKC1M6TuE^ofvj@RNUyK*b9w&T5bEuDo>g?*E*x8psF z$y`1g;2&P!zPH%%uD{LB@87w@j+cf-Nv?%`bMU|j+b_j^csTeS11 zf5*A;7QCxA31^S>D(Z30%fi_+y$asqf7|IRdd*JXlsAP?d!$!U?j`Tw%vL`kNJecoBcII6(jM>f2s*b~WycRP4C_Km@w zN;bUrz_TfLG4^D#;iX}(CYy5avg93%y`HX#YvuU(_X&75<*vY9Q8v7G*h9*u+=s!l z(KiWuP}%UdTJlcE9#%H`(y_Od4ewD)UT$kUeP3Jh&cxnYHuiPGo?AA&^_INJZSC}J z1JB0q&%vHwHuG;6>;<;g!k;&SXH(zf@kOzXzW;(}qwjL;MP{RK;68Tx{tcduzOs%u z8^NMony1_G?g05%>|Vm_aW8l_ z^__+<@^5#QXp-wo*)Jj<(DL1Xa^9oh>Ce#<@#b`k2!w>V57)OGd)V3VF2){rcgJaq zZ@CH?f!A7>(yH^*OHt_S&=I&9LO%XvzD`lGh7+0NU6$-;(!$ zCGQtY-camKXk*_BOWsCHUMluNv?+IjCGP@D-m8|pHrS)l#=dEmytS6Rk1ToJv3I16 zeZ`i%dn|cBSn>v9PfHv7mRa&PSn`swho()r2V3%1Tk`&C$xFlDo;LPPwdAd_kNa@mmzKPo5qA0>v*dLiX{YZTOWyaEykkeo6oxV~_-W!&@;p6Pey~UE(6nm%J^xGm! z-hV84LnhhrZUE25zQ#Fr zyhWD0_bqvc=Gv9}pe3*4QFi*yvgCbl$vbYcUAfO$@-nB`>AT937n^FQuhf$FmL+fW z(RStDY02B`7(0EZSn|FEuh?RJHRV`4-qYaOjJE@(+3_v|Z%crEOWFEw(Q!EQI)HaN z<81*i-GV2Mx8tQ-@=S7Ljv9utgN+)`ibIT4X*p>G^``&sbjS?asSQr|}KZ0h?RcsA|VvB)`dm{*1O#}VKS z7QFMovuWq`;MuhE=ip^nl-su0jyE2>K^FQ>1#f@_?-B59+GQ(vHuY^g&#v5w z;MtVB5#7r#y!&7kCI@bI7ax%GyK zXakf4j{Eb}RNxO8Z-d55rmH1S?n|WWdsE}ZG+tN6+oti{JzS)|v5c2`qi3@#bi}h8piH##^EB8fm-%!gyOWp7ay>k@dZX@qW>G%@xbx{f+UO-Q@RM3yt?7 z<8{|~Ej3;;8cA=L5gIQ|<8^1esT!}9#ygtv=4-sx8t*K|J5%HBrSaA=-dgawBVUdq zIiBQ4w%@Ca_q@hyt5^;%iq6*SyG`S@(|A1?ug%SVJGa+(hcaG<#_OQ*iW%=(>cUKG+q~tcQfOq-s1O1SB>`^+Ld8<4Hf1AE_^k z@#bi}9*X7gau{!g#_Or^mN4Gs8gGA%cOB#1qw#uayp4?ayv92~<9*6_TQpv8jTb}k z(%a=1jn_xxb!NO~xBC5-q47pBUU!Y>u4807=P}+0@Y0bkG`Uy|qE z*GS&OjCZD{&t0EL-p7o0tESIg&q`iX1Z%xr{;BD6*ZGn+gz>g%`rP|q$tz&IHn;ip zb=U8bcLC!K1g|^NWqsZI2FZJb@n&c|_ql}Ry}@{AYP=!HmmkUdk@4=)c<%ER$!m?t zNpF`oHJfp70cmm1rO`clPO93 z0-j!fnJ)GH!Sp5H6;bK39@s)keS&z6G~Q()yflq>c?hqA#=9bf*G1#Gzk3d{ub0Mi zf9D;<>#OnBgp@l}<6RxX8>8{ueFlQcouKjD-$w`Way8!CkaDMKyz4@E1sd=A5MHsy zyCH;Eq491E;Vsj6H-+$4X}p_5c&jzuEg`&%HQucuyfqr{wh-Qp8t?WH-a3tUM+ol$ zjkhj@w_fAj8N%DB@$L%YZPIvmhwxt2c=v?xHfy|lLwFx)y!%3UTQ%POA-o?n-UA`L z?HcdF5MJ`#e*F7u2(OXGdnkmLrtuyQ;dRh>kA(2LXuL;5c)c{Yw5 zJcKt!<2@0=o1pQY4B_Q!ybU3|X&UcuA-n>O_f!b4SmQk%!mH4D8$)=@G~P2Iyj2?S z*%01pjrUv#?_!PjdnyZPa-G2;ptg zcrS6oc>fCFeWdaJ9m3nH@m>kx{h;w)4dHFqc&~-uAe7_ z@TP$`f_R68@YaAgk$8uP@V08aBSLsX@AdUbz49a1oxC2aHQtem70lbL@g{}vdfn%j zn-juYrtxw^c$+ldQ6anz_xt5e4&fDRyeT2P^%`$#2(Qrtez`}7@TO_JV?ucAG~Tfx zyzLrqS_p5#gT8&oh49vByyHW7TQ%PF5Z=(g`sL0D;jPwqc_F;b8gFI@uh&EV{ds-} zZpM4uw;8+@r0={C-n3^U;vV9iAHr+&oU`wswC{ot z-UHyte98Mu2ye{uKJUU1-mBm}O!_Vg;jR9=UyqA5-rj7TJ@f^<7um?M?@*1`oAHWY zkBDYe?temf%QW7W5Z-Ey_kIX(jmG;Rgtt!PeHg-9ukk(#;ce1*ABXTZYrIcFcw05z zry;!U8t=0ZUZXes{`fqE*Focb5yI=G@xBb<4b^yCLwFN3-d7>KX&UeA5MHsy`zD09 zOyg|};jPwq--htkXuR)2cr=A-rB1@AnYiP>r`egf~Is{Sm^Ort$t8!YkHze}?duX*>~eh;seH z1c5gtuAarG)UdYP@UK+1q2ydvyYZStppz#`q@TO_JCLz3Hjn_1Uw@l+T3*oKSc+Eq2YcyVq z5Z*eC*D{2+UgM>O@HT0@Rw2C28n1N-Z>z@JD}=XQlF@(2FQC%@lFomZPIuv zLU@}s-YFrxts3vt5Z-o;w=#s+XtVEst3r4kG~Q_;yj~jb^bp=qjdw-}Z-T}UOs4B>UqcsGUc{vUha0$)XOwm-WkdvcNh3HOT#M+5}XkQ;Z9+z152MTm%s zCMQ>-A;BaBL=;3+L@kKade>TuptiNG+J3ECw6yxQ)cUV{ezw|bt*y4Tt!-^@4h$i^)bCkU2dFPpTZtu>{&d%)Y33+!aJZ!y9$a`4fVT)Qq-V+KBTR9T)4k#pDbD1g^T;XNO~ z8>H}l9Kai?@LmYuja7L6FMxNN!uv@8uR!6w7{HsY@D2y?N)_J!1n?>p-b(?zN`?2o z0lZZT@8tkqox=NR0Iyl$VTmB2|8*!lT*@WnZBlrcawp_%Q+SvfCFI?p@Nf!C$lIgv za0n#i-Kp^KGa>JOh4;$<-opy-jR4-G3h!3|yeAain*qFo3h&neyh94_HvzoE3h%7| z-m41l?Ev1J3h%c8ymu7d?*e%5DZJkY@IFv@?*#Bt(5d!${|^DYJ__%T0lYy9?@s}| zkqYnK0Nz-I_vZlKX$tQz0lWf*_tya4Y=!q;0IyWx{Vjl3q4545z^hbv{|Ml%Qh4tN z@ah!aKLdEp3h!S5ybgu;?*QH=h4(=KZ=1sVPXO-*g?A)?w@2Z11@P`vc=iiC=s3{l zIrl3(19M{v#B0F(*;1Zcd>FhDJl6YX19%~*qEh{R@LnD4 zuc>Wl%x*v zhGPtyduE!2*vdDi^OV-&u(gxD*LBmuTMykW@XXnbp?NlfC+#jhy;W$i3{ z?_hZUh_0@KqXvU7a@#w~m^HbJ9od`to7mp)k7M|4?#=uO$&|gB{}UV0x%Ei+Bb9%> zEdL~@{AYI^JaFjgX-*9Up6t{?;8R+89m4yEy^9j_THyBq{+nvTcKO%i*Qm!2Wj%O( zP>&ZshI%~i=?Bx(4`V$2Q0(ak)9HsXvLA|%x*z(GADN}2g#Xxm_)z8`c#!R1{WNb9 zUi2?s`r>fcO$$dE=EBU3m@#o-xUg&CsEApbTFQ0rSC@v3iTj7W-o8cnt+AKX# z@^tCxsphN|WuumcXRTN;YE0)e^h@Nu{rf6X_wOhRi@tI-3&O%Xt(_C%IJQP`#=y>k zIF79moGispS9TrLyz_PR>J9MD$dUP*ie;PF$53i4+Er}O@k2)swHejD4D~GIbuUBR z%SM^9?q!+pSC8oonWd*&JIB5^|C9$O&02w)J%8xOdq?fxKWoK#U3WwHE(wWt!nKoeNVJhxK$u(r4gOiz*e6lXTp{!q1}hk zxG`d=)~lHUht&FFMOfC?ub=I@E<|0arqrir_7iG(|DGx&5|67hmDau))Dz4ruw0bYr>Rl%5U5t8sN;Jz}xSY?h7MF`u!Y!^CP;^ zm>73NuP)tjFib}n`Ili9XOf5PaazjSIsR`4!*q5FBi`B>{#)rjIX(nhn~X2?w6Zm< zo=s-!SPg5z-*%uj;0}C+V={i#<1G!X&`xHxcz;R`|8G5u@fdG>1LCLS-6_+skGM{z zZASVSw^;={7qdp_>yWmIb@F_g@v8V$NXF>-h7|n6-`g6m+VIt% z6?%ve+UQt=JicT}F17Yv+}JyqZ<`+VA+}(5b$0F9<02Ag5H7^Ojdu zm7Tq~q_TX;;-U&F@(^$2Im^l`=T(&!RTfcchxtX$D=EQo92(&lx3mc9&!y;*sOU_$ zfX|#?zw+PL*WDF`$|;~-(aQSvjzz6?_2`uo4ZAArWHTm{{wweQ=}TLuZ}8BAP+*WyVL;VB;`hBN)|2h34rYe=3#%pf;lW)S zbHB9oF)z1$b!%G(Isu2I<1Up?{Ak82i$7oMWjf`MNmAKZH_2^(yFN7OyhqOQCTVKn zrcZZybpsw7KDzpi|9E+hX`UceZS2kkUwP>H<^9j}CTMPLX+-y{jrYY^zh6xMZOLIT z(XlL2r1CdR$_82d;`mW#9{$X$o)lJ9)jE_SKM(CUGNr_}%HJd<(|v2!|Nf%znU-O24NQhCW;{v_A*fy&ZDdmnrCcN3v<4#Gb6!H`O3)RLTZedl|jl^HLR-l2!0wiUIH zlRQA0F(}A(G$*faT~j}KT}{in_WHKT9Zi$l>esfmPp-|&$;nwCYpa*IA#ZyAv<-DY z&GoVN`l_`TH%_i=YwE0TYi_EUY{$A9c@a+MB%F16D3jXS_Q|F7HR~Fy<`or}v&!;l z<)Y>Jc{wFi_~`unXvyS~Nt2=_7}FZ-TcT&TG;N4>=H+Ei&CboPs9cVSwU@RvHLmW6 zPNgjnoxznSS^&4XC(ejq|j<$7c>RUSKcWrCi+SayMM|~YLLak`Ps;c_7 zw$`?)D%RJ?cY$Gdmth|Uj7703(wpr~ZC-smw)@FwNO@LnZmqqzq_w4?sgY{St7{l} z@sT~`dX9fL8k-DbDd6(@+K#5ymUd?Mdy2X33O_wYP}_4xqvYW#UIEPVd)-Iskn?eO zY@Xu!$hsEIOQ^zz(JH;f6W!B(viBqVi5N?dg`ZR(=YCS#x@JvNN8D)gW$7oL=$`hI zUw>pj5#!0;V=$gve?0ohes?@+ukTpe*4iNkdel`sKWrF(kdESw?`coTHH41$)V#!wW)n|Q$xp!ShK3!xF*(qv8LP5R^O(0<5{*KkENO$#tg%CSs!9gyY2;s z(FxaWi`la#$3+ZdRjsGY_KFhCrhNDbeYc~2&05DQSeN>nRa`O?EfbzjZN#=71D70+ ze2+VqyxQZEJ}YU|+EjDHs8?LlhuG6Dd8J`&@VKNqk&p99d%4i-lWqd;l)i)FWnM3| z4e4G;i)r}4!7=c{E0OPU=Y^m5c%ie*No`E^HH_;N-*cjS+T(th`220G>af>h?G;<{ zwKdLFraH3qz`1)}T=t5GPC%1|x8M(s++*OO^eUj^&O;}<9@^B>)ZwfpP$N@?4dX@I zMLqF7?W6roemUZvcs+xhazb|Xx~GU&Je3>+Pr2!M^prB!QyS|#%E?(eVjb(mi^!

    j+Pt)H#+%vbfaY+H(Jru+8m?R z%c8ovw)%GAOjK{fs4?vxah)lS-qS9%+2oTm+;=K#jy0+$zbkxnn_{vScFEy(8{0eD zae-P>-{z#Y#-M_X6&wSXqSsg*cjvHa9+xUhPFuX^P|XeF3qGFXlc1-4=fA{o zr27e--F$Su!;xos!Wu#j#lP^9f^9%lQ-gK&C4n1_6!3-Dp1Dt3N4HP2SIb#@C31YFh7er<7kgIVwfY=|*Jd3`PGTyyl`e5-H4TlC+w?|%0!%L>)!hQ^tL z49mz1n&tiDss)J*%|j6eM0Ih4FEFEpN)JYSUjkxx#^ zzicQa|HBmgH{-eI{@_#Q?|I5R{8+a3A5i9@g_gCz967|wIL}IJKiA3#UB1$?YMwl| z?Sctb--&;EN&JtBTrxg1+{}dAoFW>3zo#O7k7Y%^WuozC{a}KXG1W>dnL?E)u&g;F zKd_7wL}Bms6gKNv7WOw(*pk0sQ)SxZD=n+aGDe9qe&18Zk;k%(*M;C2HI}u=95>X; zsI}5I*HELzEUWQ~hDlc6(;lyJ{)cNcPYj)C4uor*Dr)kirzWQ!%bL81nppMbgrPI6 zzBA2mruuKrFMkQmFHwODr-e>4Pe28xiwb<(Q-Qo=S%KS9P=WR4gdtYn;+MpK^Q`{n z2}4Y)zty+BtPRCqKGz&M$1==*{Y3FShvt8Bj%D%RNXbI+t+bzf{_rJM#uw;^m2sD4 z?YE3eL}BmrwDp){S=ehWwDs9m+GUpYnq_o|^4+hN@7Olx7c6Sb`>c#&pLU#wnNA9u zjlaD&`H?dZKKtqU`Be|);GI6vtPMThg^+^wG>j2_2C+yuk{XFb(jw`RjL68ytjOF* zNo4*o@a#~H9|NzrofQq-WL`M%ilU>jL7QuA8#PC1D9VPiwx(b}Nf6LwuTA7x!={aD!8WNti48?>+}Y-}`l9;FRhPm=8sJKFZ3 z1q4}_#Yby{E+u6-&L$h!+g%>Tb#;F{T97q#V8#iNagpl_vC}q`Z5RVXkr^2?GiGJX z9zJ(?O9V+lH;08HN|OG@03$vbX+=^>cuisC+QN+Og&BJa`(mIgaBNuHuQXUF(%;xo zI2>yWg!&uT(eF=l;tlV#p4G#xXMLK}NASH~ZN2iSJfeERC%Vt;sE=2)S@+gIrm-QZ zyqub(VC2il;KLUl;WrgX<6g9h1MyY> zJZl&k>6lGZAV}%65Q|3~ij1tGONWXYG_1nQOo=)p_@QbHYwjKQ9 z>2z!dns$ozr$;6h;9@}Dbkg>5Q=J8mwnHmC&z5eonvm())Jsfy_D9&Ht+R?v@2*aw z(xYI4N_!W*RG-~+-XyfQ%$vk#w-Y6yO+X?S+6d%L;%rhOqFYDWkD(AfTLp;e){*YV zD@^YlVxrPBX(D&J=jx@#-T(6@pgU^b1aWtFD1qCGbSuT1z-LjPk`$eYKb7UopapZQ zsJ*>@4Iam8W09fhseMd(XGm?{^bN6^CT7r`niL}p7t({ON-_V8b#}&1k|YyL${48l zLyx2)OjEH_2_O)rhcJPp6y{6cIFuze7jW{5vdOExGF zUI>}bk-%r+_bdgk#P3B4rv2YB1vlWgn_mi^7*_L3!E?=O{Zbfh*l_EY!nOjt^-E#b z0lW1};olZ=>zBelhxjP|Q84ig;@yzscoYbK5i*A(fgi^25(R%9zt2|ixA0p$a1H1hdVf2XZIfBmlCj-Y6d@At83eE+-Lc!C4 z-SVWdxxn<0Ed|p|V`adu|D>@+z;5}{SS4_gpmYBDzzY;y1AL)^n}9D-@LFKEKhoHG zVAp@s*%iQUf2Xsnfu}g>)7cHcZh6w#&A@Y&czV~cc&35slg>U5T%*MA1Fl!_SAaJt z_;KJX6-@8Yyk5cd?nwK4Tx6f#nMh*-1=Gx6^sc}G0&-06$fNOx0>!@$Ok)BC!t_qG z3;}`rFnSkQx`X>NdIuJbF%(R*FZ%%44p;|+k;cs3JBuJ+XDL=BJ9@MsN3HGGnW$7uLu4Ug6E zI1P{2@F^Oepy7!cK9$|%sox|GpQho{HJq*C$r{elaIS{)G@P&D0u4{m@KkoUr~K2{ z!ycTe#ZTAp3=PlJ@GK3_*6;Vh8JsiiH4VI_$>CKr~Jz_yj;VT8a`XYD>QtLhF5C%Tn(S6;qx`T zO2ZehU&-=s!mv32=i`4!Ow;xO7=H)JYt0!Phgq(~bYV0A=ZD1-U&(QV#U!S4*Z|C@ zIwhtHtpPaS+$1p|%fi@whs4!9-eg~r_$H3i*)tN?aU5bVdH5;pcM_k><1_e0qJ>E* zo%04^!w6l}1>qB9Jk6{$1r3b!I%9~X?*GfC6+*+z1`jOj#(WCuTkx6mv+`j zJMaT;2eO*V0a+*I=O{h!ol@SX+PO~JX_0o|N8Ao1Z)Zr}&XA)iJtXxv$x~H3JEWaf zX{S=!f#mHB$=ex{=71r{A}Qyqb}&%zen;c*_JJRFP&+}crusnA8$n1eqV$l<)$}*W z^q0u=@PD2jlBb8{=^;<2^pJT{PFL;RDDAXKJ2-y09Z23!ki4HDD=0lAZBurRgPn{G zqjI;4F(>pH^e18HVVdi2A_@I7Qh!+LUzYkjsweoRBw>eE9f-eC>gig9^t+_~1S$vk zyk5}f5(fWVslS*c^sQ3Q{R(_~6qEF~NIgA7Om@C4_1}^DpGy7jrT$M+pMi4(@lPZP zJ13DuzSE?>Tq9zd-8Glllv#ev8!amik+y{&A^)PU;Uy{hLz%cd7rE)SqC9d`~Bdd~->n9p*{> zIZ}VV)UTELtx|uD)ZZ)hUz7UBrT)iK|4XU=wbcJh>ib|Ir+l+WBHz==T8`^4ylXwuZ{Jb!*w!lCc%J{BIuro6r9i@V`^|->LlXH2!xw z|2u>K&CL-)q|Oz|b4B`GVIWsn$Q34Xg^gTcBv)9;6ISwM8HANQVI@yk$rD!cgq1vD zB~Mt%6ISwtm3(0(Usgp}$ro1gg_V3^C0|&{7gq9xl>%XQzlG4XyU?=BAc<`*#DLO>{u4rlzgF(~j!6bZvdR4Pedw8EcERG`cZs@$xg+ zXt(b*c^X4@GrGp7aotFt&XJL5K%Y9gDV+{+RmwX?TqAKU>Apoul9YR7ZZhQoL8

    %iex zLl1(p?Dk97bi`^{HeUYcDZS!xad93ui;ML*TwJU+5bD_?+UI!lv*L5i`q7+YFfP(F z7R1GBgQH$fM924jWjQrxO>1*@thp(M#-&tZh!ew_i$x#1SUP~KkYk^#a7H#)<&19G zl(Tp#MRo(8qNIN9Xyg6bzFPiDH1~#g((Y%R5fe_ALdmcq=Gdk~p!*b_aw3eju z-UEKlhevBLWw_pW-(k7--qLsr(coijBQlPXQ68kW`=c2RUq%r!*h%Q# zqRRUkcu|`KY4hm%Smpf$ylfv{qvWA^MTmI&!`637o=rOd-gvvPwi5CxjrW^=SSz4{ zXhG+#zy%0jGwX)8ae!RQ>V|jUpyYTz7{VA|)9S`v$8g5@npHQvR4k_QHK}fRH)1iB zuQ_$Yn|zX7Q|g9y?#YbtHKT5L_l}cmL*4NHdJ6Uo*qyI%^?sXls$AnyIP`O;<_DMK zLiQ?+87_jT~Tl>~1MoSu$pJ?P~-X)ljKdn3Axm6WXMGA+?*uukpw*2 z*dZ*A8BD zTnT3 z03N0$aY5((za)A825(ZFHO6#%ZH#59FB zc8R$6Pz9Zx9+xg`1c1sbP? zQ^ceD(yF}q80z;uV93dTr(k{5c4onvV3uTdvuA0X))Ezm38_3Vyto72aq;^X0v+@S*{{w-w$= z0laq=-k1R1`wH*m03KWF)^}_GFQV{pDaV6fyJRW6@d3PH3J;fj3GGD{-h=?&1cf(I z;niyWn*-i3#8dxf1@IPtw?Ojx2k>?&JS-9LK<%RE`?A6t7{H63<>rf}1RnhCtyXx0 z19*=pJS;gRwD-Qk8ydhXT;`UK+L3}^`L-*(;ezJNdjY&c#8ZEa2;gNcck?|VfVUF7 zLd26jEQ#hXUoc(gZ&c$tF6%ePJAMR6~g{DgS+`HSr7yc~sxB?lh-c!dfN zO9=^iOBJ5Ie&%PdTH#F&u(wv>r02n}z6TT@ zF6k5UUQl>b72apH{(W8Hl?CwLRe19Qc=SMq?Jo-gcv%XsJb)Kfcnbq~ISTL00A8WO zs|esNRd|a6c-0DTaR6_v!o#VF2kKwFKei}544DaeyA&RVE{C^I>)(69qkQQ2#Zbco zVV$>6;bCY<$a_TLRR-|BsqnBpC850o3J)%pkoTOz!_S1g7Zl#g0N%?A@7w_1>k99@ z0N&dQ58G>a@N4IH72c`<-unvg0)i!5;p1c%zZo>!eTu@!D&f+z*3CyZ<(LL4MARWWNnQ@=B4J{cZ4nvw!iglSaF6 zOX(@&@#4&W_(o|~TXAMOWE3(CnFDFYnDb>+`-|NC%f`!6tD{{J=c}gp&MCgjd~n3c zES`0;!%7#dVO`&m{9zw-#q;}z?61ml{#D;Q#0vLsVNap7g%4zgs*O9$R(1zAg7WXR z#;4!pq%YpVZhz(>(5^k@Y&nMnCIQA3PUvUzsvyw+v6Ym~PueYsb(ez=;rGx*oF7ls9zDN%mcg3NFe#m|yo-=;JR z!+BkMM=kgQGe`e@=!(5;|9)dQzP~-Oc*lNxAD-Pbzw7WV#XCxOckOx=^5CIiT@^n# zcuR4Z(u!~5&bz#HpEv(T#Xeg$ELJvY-tMx>Q=3Gp%w-?M%CvoCc&aSS?l5-k#kYy=J}P7;*P2|LB991@rEqPEM{BSM*G9Nj`p<|c z%i`KBu9e;bZM?sxIbWRiDao+!borEI*nhfwN;2$7mrqHCz1HPZ5@@L;{QJ@T%jTk8 zXe7XspVG&Rcf7fK%dRcULe-@sQrJ7rZv(#zcNH$PV(;vZ?uznw6HgHGal>In>|?~y zWU=BM@9fUnmBmv;VI{IF!haXycgn65{(B264U?DBH<#T~VGp`2mD@_gV{Y3Fj752S zN73GWV}<;8A%3UEw(#Fu@H?eic(YF{jVSc(uR`8mPkxQsY15`JJHXcO_zgzo^`SRPnK7|6>~|b)JMz@^dY$fc>m)ra!t?vT^?m4ed=t6} z_w85n6Vw0Ave%;Q)i`yF)v}aF-~7w)o8B$n7loQ8CXCMNMlJpthIwUpc}aOyS$Wx# zs>+qPJhIHKs)oK-ZC<5n^6-sZbDOHkXCceHTGbS=6wACu)l9(@#JpD3Ol4uq+^%Y- zu~f^vPSs3j5zE}6YG$xB%e-FIV0Uo3W!~UX<+2RRywRh|V|^_1GagkwUOj8>^r#A0 zKg-oxE1xC^yzN% zX1g=g4q6l&b>aiJ|8%A&vE4y;xmhn09dx&<;T?33s^J}Uud3l4^m$doJLo=D!#n5; zs)l#a{i=p{&=*w=@1VV^hIh~dsz!9sK97ob(0-4KchG|#74M*jJSyHn4|`O+gTCZZ z@eca3r-SCyUv}0n?mqEXo;Kzkw9L~%U$HxbzrR5CuKE#gr*~5WKjQ7sQo8www@dVV zk~`r?yj{NY#2Kpr3*y()v|bp8c7Be{T3wWX7>>Mr|vqPwIA7YK4`X-~mRRdMskfbA;PL1LwC|aE zxV|NZm!aW8mXh0Wd_ zDTX22<8FASHv>|e*EO|kUP9G1j8WW6ys73ZB31< zJE9Y6Cq{E;%$Rz5UQX`xXl4C|SbMY_k8`)JTT|cCLBDHT+t#+W#X9Qim=P*=9BBF4 zSZ#fP2kp^3$e-V%E_Cn5>_U@!+l6Q++Hp4q(W{1N+{e?lVtHEm9xhebFuoeHSG4_j zJ?b(~erzs7lX*Pz@~O*w45NOG8s5_Y|tCVdRpdxDh?*9kuLS{y}!nii}}y+tA#;wzm1=1sk1p zIw(79V(aQuMF-x-LnT+frR`nI!`jZKx~9&iI`z}qR5^7~5)Gj)@1%Jl?X*=Ee`tcu zk0bAL1nmRoYR^K~OlZS%@COe<_qNj(A=Be-KJ_E%wCmfNI_gVS$J&b8+G3aT2B!KN zMvOXFi|tYO{T%=JyVre@Y`)*Q)Ey@{Z?EI!r7CdUSM zH`R~nM5=fyo*)x0>0K}BXRGx&DGjdDrvLQ|JtGh<#2?0BMU{I#t< zR_AqQs;*(&6Cc^5zWh>vFWWcUKa?-qiF(7AJ(FO?mwi`r=rNlxjn4SGLvOosDKb6o zT$z?E$y>$gue_zBzO8NDS~2^i3LC~R{Gxl*oj-`5c488-5gSm-_$#Io&KlxIR#Z+M zS!sq4F2Nth&ggCLnTJe|JMW=4Lz8>RIhEIasK$noV)znz)PcqrJ>^0C79t%NjGfin z9z>5&9d{m7DLsh4^-c~x%EAfN*)UEu>_eV>$%opb-gK@Jf2HF)55xc^Mo(D*yU=mN zl7(6+6TZHH;YIj^SHbtTQyrJXQloUL+UELLn=>dWZY74M7$2H^Nj>UNm-XoI#J$aT zMTt+I#Nb5(cMA8ol%5(=+-+%;&p7<+shp14_Ow#zXIOD5rWFpmqG4kzcP(4rqu#X3 z@R|K%&Bbparo*!k<2#7Ot-4fI$ueaQf0%&=WIuE;(FAXzTh)7#kon``3yBs&u7X$D|!|;h2iNboW%`>uVO-APbUR~ z^-xXtdvCF4P~>9V3@N@xNm-}&N)g1SMP2}l8i!d%=tZNiWsR|ne}+vH&9KK)tRcs& zSXZT>Sabep8JCN4efASluDeCKw%{Iw-e4yBao90yup7c?u!%b??cZPg$J=WzwTy*gxOmP}x)YCC>E6IIl-AW| z+CZ!C{np@9t-ejxz`j=BFIp#sI?ObKt8PgUVYG|79Q4#>)G@2eJ#-4Yj@M-mIIZ7L69jy&2 zleDqoXl+DY8y6m}4ch4~%dzrU+MrFJvK-5fwj3XajgO;WXs?i{%f?MdTNm23A#7~e ze6%*`X1TO+>CxIKb!==hi(%wwjyYNlmVIlM9HkAqQ6byZtT;*=f#on0j~`LwZ3kLs z9k`jsk1MVF8Mw3F*Y+qR@-E0N_;q`$F)Y={4Em*4(~lL@6B5E(h+4Hb)8ah-p$AmCr_N1Gg*EHoo+)zn0+=T zm@*bHBjXI5sjcy>9H;g01ZYM&2~%eQ;%zxaM%K`A{qQpEEpR+a$yjB1v~tn%{Jfl! zyquhz==}U>$>fqrlkjj}U43JHOZ4oPrVY`~ypR0+4DG|_3wpR#vIAWU*}*TK<|lUW zi&w9!{Nkf_Vo1Muy7sWc(Zthy-wuB1yNmCx{4|fZgP(nxquaqRp61_n@QbIpwH^H8 zX})R)zj&Gx+rclsyYw`dwS!-Jwg1O}DExoG?k2-XE(8s2`Poofrx>T5?J=8Ww+xJgI zw+m>?x=oDVaP8Kc_5<5Izum0#iZGEi?ftZwzB?D`ePDu0oBV95&%QG%soP4ldCMmI z?kXbsDEt$)X%CJ~w|9yVV~oR~4HgQ+*#bbUq7(6_vYZ)1Ag!YI_WCt=NWP6lhNh?X zF$Y5_w{0+kw!NkpVH^|Qpej<#KVuor4JKBlbEUMZ8tFYDm#pyuDw+D3b1Q0mAwJ%+Dm1> z1$OPFvUh>)V44y1iE0n;&s93aG}G8{_*Oy%l?Aq(g zZUCm^m4a#ZWj6z#Dj>(V1J6+K=Yie&^yA-$bM5tGUqSpy4!%eaPGud0f)0Ox?0+%TGZ@`%j&SD<`yXDWq z%TC?zkeFr`-l#0bJxW5jKd{?gS!@{aWW^p04{rWhj9$m%_D2>w9oRm{l0ACd^h_oF zEMT|({aG=v+aLW|Ij~#b{%k3*n_qu+4zOF_{_H|v*WN%@4{Qg+9K_ZDUnmuX>AO>Q z2w^Y9Wgcv@n>;wg_IYp$JK(_8V z;6CgQ5AMsp?!o=ok32Y&z3stS%yOr?C{KSj)`JJIsUAF#Re10qcD@G>(eO|W57Y2) z4Uf?92^t=$;S)7HO2eZy9M$ki8XlwJlQle6!{anOUc;wocmiwmwAVxppQ_|fqv2c)=V>@!!vz|iqT#6;o~GgH8lIuynHrv@;n}R+(|&U_e1?YSYPe9t zMH(*FaEXRXH9SwlWg4EZ;RPBl*YH9OpQ+&r4KLF0Vz$N8K1oi=i z;RX#iYIwDVn>2iphA-A|vxe7bxJARQ8eXg6OElc3;dTvoXm}la%+o%d8eXsA4H~{w z!y7exnT9uM_;L+jq2bLM-lE|vHM~{BS7~^ghOgG}H5$H_eNVOzt$Pf>{PTY$rge$| zm>>O7Vwy7z!1*}U67z*3j{C3?5{vjuHd$g?hZ%tR^c;yxIqt{Kl6V})1K0%;1F|g4 zO&T@aDKV{U3@``s%fvz8VQG$8^BJRk)q`Hf+>qq|A$^$2zd(FrkIGNi2!!bk4TNb< zOqj0q2-8~6pj15JOA>8D-Qv_2Jh~dAF^EFi1 z&q@8QQhy2bvfTK|%YPntRF4a#?2?l2-n7%-Ceydc^r$aS4@uXkA;>BzGtkI{>07xZ z=^BXSIBI;`-tE#}yR?UPCP9Ho~-cQUl=g7EaC?v|$qpp%XGppRCR`rD1IharlJ_qpKQ17tKSPk* z46CMyw0otr zi}9D+g&_X}hi*@2|BC6Xsfc`~F^ zu7|`rX6Pz$ZVo*t#}nu`QMsVsLK6B1NJ9T#Qcr7eq|d-NZkMB=ifU{yeF_ zQ0iNy{z|F8TIz3=`Uj={%ToWG)c;KCe z>Kml~Dyjdh)ZZrc4@v!#QvbBnzbf@Kr=)!UBK0(%p?t@ag#J{LD9=KvUnTX`Qol~> zua)}irT%`Ye_ZOnCG{^#{ja6|w^DyZ>a%bnr+f#IM82n!M0w^)eTmeskowh9-z@dp zrT%uQzgy}LNc~Tw{w1mZyVOT8pQC*HkVL*?Nh05=Qa@Ab&zJf&Qh$lmUoG{YllnWP z{t>BvM(V#W^{-3)U!?x;QlE**9OZiwNt9B*r+)@l6tAyySSd#2D{5zFA_7TO99^7~>4bpOqNn1-h4ou&A3Q z+lS*SiP1hBS4&(WaZF;g509^r812Jxt;A>_j_V{w`*2(@G1`aY28q!=95+gg_ThN7 z#AqLmFOqMTf!d|aYj7>*N#%JSTn zma>|byp0`kH_ykGjIGFJ^fym=U6A}N1gZ1Y_rNIn0%=Npr#tbdaAQ;X-)a2sbjkF+ zDNadda2h_AMj%&|CRY@vsonq1IA`XI1O-BfjB}^*-1Ph7oIlNu^4t*TQKF2#cffhP zC}N%{VxDZUJf3l$C`O(rMxH1}o@jtP(E@qX1yfkb7gq9xm3(0(Us%Z(R`P|Fd|@SD zSjiVw@`aTGVWmJ=DG*i)gp~qer9fCI5LOC=l>%X-2sgsJ0m9Ym8y?)4xD5_&l+T6+H_~?lgBxvc zSnz0^4GP(Kzh`^L%xt`(y{V;O)d5I?}oP68VAH`YTD{M?Wm4R z*Veb&0M_iEv9?%CqZ_k!T}=yYwDTj^+eQiA7({B{DpG{j{G^I&MpC+6M@a7j$>47W zaX(_Ey-q`toR<6ah)|o=^)9VT+z4-PyL!Dh+?cqobfbFvi14`gQ5+sg91&GjmE~16 z>zbPDs$v~D9BbBf&~ej#>6(sM4a;t;Z+5Hi9cMjJ+F0v})5cpZ&VS6+ND0PW4=Zl$ z)nmQmuP4@j4E9jmgW20Cy61TkY2N3Fi}OHFY`hnGqWwJ4L+~BEyd`(WXiq|DozW({ zvYb4jrnNa6pLvVHFNi8eYcWE*Sh%N)rSG~5IgGmsXOMPP&Ops`uCMKAYHi7G;BR%L zlLdFl_SN!NqKT@mr#UVCqd6{x0wJ8g_M8`&fN{L34$GYz)1ETb9;VmMJ{+Rk_9!2f zw+lFj2r}3_T=sZ)2Y?Il&ki;Z(|!++fLa%uhs#e7uOI>M0gbmBya{%uGLGQW^0(c7 zyAtqT(Rkkk&#%7!(s*x!hb2fS0P@feKj^oeFYTY)D&t7lyi+vZZ@}yH;n99L)!wQQ zW4QEof^F|yjrS&axCD2C&Fj#3Eh&s)>D~!8?`i+$LLAv3cHA>!(=!Ul~njG&N zW90paZtT4?mN9-Gp&Q=kPhpJT2k3^^dMaal9lsmi%+uxid^fxeld-=tiT?OjE@ON> zy&HR(82tG9csIQD7{vMdcQ?EzrsD|!pYqX-Th+~9o5|Q!nk^1BUd=4NL>|x7c>e_N z)_4}b5v=BW(`?3WOM-XmoaF31lO*rFGm^9Smn3;R<|b!vOkr~M{Wf@aC($nF7BO}x z3EsG3#-2-p_XqI4o&@jSlH_>HOL4pmXI-L`A%ycY0q$rTrL-e^t!DQ+jwAOIvGg6Encew}B!X z!NdPfXa?_*zKs17nir%t3$hiYG>3(~V3_0#1HKObkPifE8gFcqSZ5_(A0i=8-RZl2v=&n z_rSC3F_5zakJf477ufA7LLW?;(rh3l+1sqy8wQ@8uRSjK@uCXP9vA$06BOQQ0r}=A zJbV1`vo~GgWe3|*SHmprmdfy$@nyHw!~=PZBTy$Wwc0PkIecR~QK5Eol^ z`LLAFgJ1b}DLlH@N5PNxy28VfKM#JqoHcH~qXT$bz*~!WYUgMG?_Ka#OWsKVyp=63 zZ%hF10C;x0oE*T*YIS*I19;U6Z(IQH5%5+bp6YAQPyE_1f<{>&dG>DVhhr_RCRtWdXcGg@+~Pg!YyyyafTgYK2!G zz+0>E76$OPD7-TRc)Ju{MF8(!g|{ex_lUw2c^42Om44DaeTNEA*aTNUOyG!9+B51z6dlg<=0PhinhoOcCzkClUJh((c-U|v3 zKONp-&7WUKB;`ZnbElwjtn=PhcDY zvfw0re0c434QsMnYc84`6(M)pwEUdBX*s$1(P$1=sehx<{JiM}LQ|c-d0s`C^NBX( zX|Nmd&kfUS#qR=M+6nAi?7x_KqG(~PmlAGq0!8Bguq zz4b_#r5q{QR6L6MoGnYOj&@ZWY$vWefX8$i6GJOXQi@air|sWya0D|(bZ+xWu`yAK zVO>W=itv%L%jbD=xz$NSdCcQ^l#UwHS-Rukp{~E~-yT{~7T)`VgSU+6yaqYOr~j6d zzU%~Mq^^#3ecRE*TV!2j0k)3Br5upvl;z*NEa^dIImxtJtZa958I@&>qp{1PSWM*> zGlDE)*Np6gvJ<*Clf^PeV_O{Pl#y)-svUOfXttUhjcsdClD7UCmvXR^a`O>huTW6E zMuwcS$d+dwPw$v}AW^SLrP!yPxfvhrc`HsP&0XfQa5cq|eXG^}ReH!^`!ATcO7aTR)|4LF#GdY&w`#vkyB+z``toYlil@Ho z@oOFK^0nY^J5U>N2kz!g#;r9P3tqTq)R?D#bVd|_ zPDy+$GH49JAhkKXytHglRatpO<-BE8SedenEgn@KGc4muk18LdsIk?fDqtbYzEn(>wA#p~A8;ANX3bDLd4zJpXIuleu4X8gMLufOsn zH*SP6!!U33WWKz7aYh#TZp_QJ}sFkV2LpG?&Eq1ZdtxikqdG_1;-`{9#_9QmyL{+{j@-Ho_EUGG7vTRXN zWmWFfs^W4~CdK@Ed}Mwek2F%u$HbcoWeLxm@U!&mfAeCQClgV^CF?rYuIr#@2+CU9 z*2Fqc&d2RC@fVUx6TcpF)i=I0;rX{bCQ>_Fn^4qoD6ORRUwQveU)nl-gNK$<)7sk1 z43j_HDv94%_wvri&R+GPm)PFa*iv5?tz8{!V@4S6>KOjdh9N({>Z?Of_wv`Zcv3|8 z?LV2rmMy!R$L?ADzBk2svR&1|@OskmuJwlpcWuo5($dGg-1gP2Z5?oN9Ar*8Dxdh# zj8_(azShfh${~}a^80PFAh-SP`p~5F9y!OG1Rpae)2F+p>jpeFe0232|MBu1(>y^c z->@zXKQS=$?#{oxztEE)R8_SORQO2;8<|pM8|61BWx7kIJ^cH>7Vo&xo6bo!*ebFu zt6kf<;42S3zr6pMo>VE#t$6+n6DOssz8LHGi|M~DIqW4m^$;mM6-bM z6tW`lX{tzxZB?y^{Q-DyI;sdyHP|Y%E%W=3vib!ZGwN!ao*eE;#VZo!WlOR6T|CKt zbMTV~CzVc4^Rhj)k;zh3k9z3p;-%02ao<{RvWDhX9Aah)znv{JxNgleow>VrOz|@7 zTG!!q!z?95J!t0aeBhdQs$5{_lmLA&s*sH&r2$eI;rrC#{MP}5J zoOFHXd!dyXFOuG&n^D_}+Q&&Aj`UU>Sw(KDo5MW?f^|yrSar zUVCM~5u%3!+$S6R8u>0T?9MXmgMhJAvo~9toM#~Z9e1ssj%MUj5&iAT<*)X;#`^5ODuP|$p8!wql&Y0KXt8- z{y7#Sw90lZ`Jif?Z*361<&ExH=ep{cJJ;>K?p#s0^l^6zyUTViJd7+Hi(iA%;Y;;3 zjGKjXd82#QxxQc+8K%Y4T;L~Qgi8b9>W zc~cqs`T&N-wuArI>)uJ%sK=dm9**lHwjjM`%x&6`IH?i%cyjXGS!D!wvt=ouQqP;s+j3U?L&Z+k+P93+XM(s?s zHjIBd-W*5jSvO8IKh*GB=dK9atA`)me|?N5<+yVA{c5idzqD|2+Tk!;dVT?5SB>^S~8l`8w^z;wsrR{FfKfY1c$7oVsst>Odcys=DuRHB= zIcGSeIBiMmnzdq9yP&CYb>(Wz|5mp)*YW12${R+Zw0I*~M{AoHo3#~(_dISKN9Ue$*<2c!AGC``WQ{hf#u}) zr@ij6$K^cYRn23Cug0$_&}2f)C5DKN5||0QbBTC<&-(9#59hy$*9ktl8z;7%lsD^> zWHGN8fZGkdy9RN}@i-h0Mlw?H{sXa z9RGCt(}(E2K%s}+d`OYP8DiAujZ9Sz8&@eu zg+l1rqvD%Jr_T)$-MMiu#6Bn#S5EGr@JT3dj;II9#<&CJ(u9*090sEC`1FpJksXH? z`uI~LZOIoT&wcVSj@o;RlSXF8X51nv?K5*?wWX=)hzpAccIh#T6l|2G#Q=lh%j*!> zOhdt7J=ClGwZ7S_WiG}Z{7AvBU{Qq3UMYgyDZ+~&-WX~bp_|RVmUWtC{3UFfXot^v z$~ENJmFpK&uBCq*`yI;|`w1)B`*B6P^^?+SdqQZn)xW<*X|~%wDP?<{m+g1|bIaJv zoj(1{QVtVyyr*NB`Uj4)r?oFS4iCiLE^p%xhBI4sW4H zIY2jug(6Cl{>A_!J{f6wQmZ`L61k=@a&4ity)a`>VPA~81&$4C`;`XkZ(LVMhv0{| z-JRu7q`$F)Y==M1huXsKlTX|2Q-8x@Z5?NRkU@hKA8RrajWr+Bh;Z~drC?Oe$Pl9{ zhTTk-pFx9ZXb7{%T7oHK0W&hrz&LD;XXTjWgeO2V(n**)3lLA&6&YDW$MwVOg|=WI zrIdL4VtKT3(enJfoRYkpoSf+V{AkJKl1Y=IC9QS!jrA?jvs;=rL_0tF_Jfhg3pc?K z#2pv&CcJPbu&VG0CQQJ7=(b%UM zfF1nO&$c5W=>~x4A9|jz46BxWZCZaAZLCA1XT2PnXNi@p(hW9Yjvm}`c-}QvFOeR? zaERUoUn0`0Cxu1Y40c21WDdwNC!tMqW>&$ek%hnMlcg>O%!l$})W||>JM}W%@v0_hr z3Om~qpTf@f#9Mg(24fgcc`)%jdWZZ?!oNZmhuQ7G_PaPK{$5}^m}V;8x})+_ z*>~(nNYjk4mpt(i_A0PzFXH*mi)p5@5E{(QKaHgWyZkgvrriuoGo9sl_~~q#ho8>Q z@bEL(`5t}-tMSD5Vb^%#`>-2<-TeEoJ;42C5lpi$y8~D}N=o(Z$L<3b_v!`S4{VRR z6i?q?o9U$Q$G!n<2Lq?e?Y_eB9IK;nMW~UF~f%(4TpyR3#`ggnshgpRO zr?QJZIKsAja2lhd*A5}H_lq8!!T#>SeOMF+l^sH8pV=PVkFE6JOxEbZ{WUy5!vi%u zNW+6QJVe7oH9Sni!!>qso!V~M>TwshR105WDSqi@Hh>R*YGJC zo}l508a`FSlQevqhEHdkJ@w7j@MI0=XgF8Hc^b~waDj%WXn3lIr)hY)hG%GaCcD8? zpIPj756;r!XKQ$lhR@LOTn!g$xJbjr8ZOarsfOoixJ<+IHN1d5;Hlq2Exw$6%@cp7 zhAT9@NW+UYyhOuGHGGzamuYyphATCEwuV<|_#F1Mr#>q+e6EJi)A0EkUZvp+G<>0k zt2A7#;h2VNG+e9UI`;o$eQ2IA0Oy;xB&M150F1}~QRXZ11^mN5Uc4@K{#QUh}lg%etUb5w(jZcGc*+*A?gHB+4J~s%Npvr6z zrj5MbXk6OdF$kBtV@O(Jli8qD#@`h)2os*^q{qZhoZd0#MA(XdAxtK?#HAOP=twRx zkL41R3obEHAN%(x#UQF66mG;mc z+#ckGWCxPwbR)Ve=>m}O1**LoX>Xpihj!)mAh|tAZVz%BrH8y(%3Gzp8`7z7 zt+ZDr?V*3TJ;;lxT#&6&K1}I>zb)ktr2Mgz{{!jRt&?`=OS|ZAZWpqS>_O6Zl}YZR z^pN*RdB2nos`l!oy#>-9{D#|u!#qrDSLh|DWvYzZh-bU#md3!>>C2>Yb=(D68 z0_n8F#nS#_X&>VPw-3qfLvs6&_mMqF-cOLfkeIFoNI!_|L*__1Mao%ferv=xAwo;U zN>QkpF?xq^2>P8Qp}(0V^iN3r^HTp4sb5I-1)q;Y;PY_^{A;EDHj>caMH2dVq#o}- z<$9CK3;kr0u*1h6@aIYW3aO`W|B{_%soyO1H%a|xrJnm6>^v>?v|K{=e@PPhze@c- zq@KS2L;BGqVgF>3;M2kc>FIkuq+cZU7fJmlsox^?yQThqsoy8{-9WLc@j^S7z;q$KK}6dRTAU)M73C`K&&@WeK?*X zG3vwdREbd^j;BeC`f!YiOBUHdeK?*WG0s06W3hwBqdpvC-zmo^49A$La*XG zhvPFOMtwM*D{+p*g%T_E;XKrXOO&5Wl$%SGmrInBOO%gGl#5H0hf9=$OXSZb^5qiw zVfaWCD$8?QHgt3pESp*qzZ^ZbWNbw)qrZ6~(z6In`h21HE;>_0fr#)fGE>A9Eh2tV znOIYKuG1WD+)^@;raRHv(lJHO;1+Uo98RJYV{h$QrzNwJSEX$y~2!JoR5oB7UQ$Q zZts|x-QLlLH{Y;qzJ?=OuB&N*jdtPfqNqx7l!qW(Usc{f`Kcob2l&6@NFJ{^3a?7Sk*caH%d2YEH8s~& z#X8`{HS0Ra-P$i*(-Es-*=_aBivN4Z7jK+4#&{#OaV9~e&sY=3j2~~}DEgQaM@TsC z1TeiW<4cSme|%{P#~?2|ejM_PR}TK{%5v(qn%3s*SaVYhok$79h$KcK7YkoquQf|-o-xluF!ak!Q0@&yIt~-9S_feN7v$n{0V7X8$Djs4`hVK=;IaPh&{1H0jk#+oi)=j(>| zBo=)6x?MNC-NP8;>v7%iW@Am6udj8(`}2v6@%6H9cuz$c71xt@B*8lo*O|%i zz6su)N!Y8*!}?Sbyg!4NjJ+H4le2d!2K;35eKtv69j>>NDIe|fNhaUBz`H+*b}7Pj z{g;#A{RzA`eR$7nesvh@1EmTN!xs-aZy44OlHsjNl6P;Cyf>5NO~ATFGUaPdlJ`iG zy!VpiO~-mmGUeNpB=10yyp-Ag`M#q0!2<9wbi@Unw;sGzaV*Ak-izSTTtyE$Z`PdT zcwb18mx1-GWb$oKlJ`oIyb`RJC6n(%N%963CTH)mBzeCA54Tj}g5DpCijw1f1H76z zYmEI?^Q+;-4Bw-Q5ASKbt>8uDX?(vIs7|;qN!~L_^4>_2XO<*azA;Jiij(BkB+1*F zB=5c?dCw%tdm~AniNP=G^rHJCWP0b%W5C1GdtA_Y<={<-V_{uhvv&!2n2N;(op*bZ zyzhcX*K~T&?fnxxzwuP(O_;~{x1PGQcQ$y*LW1Vd@kYblzXV!znH< z=)BX*#QheXsPoQEz#E8u3yIIPa}!sC=U2Xo;NgEKd=tD!B8+_#n(b1HOB|L9QkuiU zSh_^qe{Fyc`S5^bY>~#>qVQ4_-bEVkR)uFNylXYyBjAyrQodn@N4wY6^1ZCsqcsQ$ zRKCL+?_I?n#Zw^pH;p%Jshh8z5Ao>UtBombp~Ax@DG$V3pz&6Nhf6qKj|@TM`L=4j zEs8x{y7EBw?$UVsz>7jp?a~+jC=l;SjrSaQInWaim$*C-@8{s5JvU1gdmlWtUZf}9 zA2oX^X9+#oi{c*zKVBb&caos_@&+lqF#)`h3h(3q-dKezqj1_ba9f(IAmJS?5?K;_f(9fZX-n>Q$cSEul>#KME0y+^@YiC8M%5JBU9s^{Bh zxts6M0NyI_YleTc>OT=tK-S5;C&NgEZNIac%wDm9yA`s6E8b}cfZ1$9Kd^2;pGJI4l2Cd z0N!DRmlwc$Q{m+Y@ZM8+1p&O2bKQ2C62Kdz@a*{x`Jdj-V-+5jI(YEo6)3#v0lZR$ zHzR;osqpN15#^hs`9Yn+J5#Zz^Ewn>MF4M`!dn!;+oSLn2k`D!c$iY~;8%}F72eVS z-a&+aqv>1Q-c9;iN<>pjeD67uYGM(c5BT=lcO@^PMemWlQ%6VH$NK9;X3tiG&*H! z!HhhvuTI}QucFL(9U}5H*p2w-hKh&8?*d-h32e48%P@}=kBWBT%hgXAj~8dA$D&@BDpKcbX?%#261gp-le?{Z@ zlXU*Du6rbZSl4Uu{O{}hLu~Z3UGcnMIXr32;iVj*ugJS4u5rF*U(CNhpSA3RSjqN? zDDxHD;%a!E#%JIc@A!bXg>L(+E_cV_c}La+*?n2%mK|yKxA(E)E+Li@KI(h8syYi|e+Sdq*w)0y9Vdedvm% zY;X7>89STDp0zs^%UTw0BK{n%Dc*5#ez=+N861aJ%nP4&bK$P8yY~NZ{^t;T=#j4Z zKR9>`^k!sN*$?L5QoQ5Pp+7@+=oUAh{ripKrK5^>lmhDHLx<1UF{920RQKHPN zx&4K_%oVa!O3hR60tq(iW<*`2OPlR3T!(Ic{tV2iEsePD7K+n;l8&dmy0SyhY(3W7iuk{}3V0TKuhLV&1f)*FaqGn;{; zq9P(LU{pj!>sEz|b*W2h-KtcrrM6Yu+G@2`+gj`AQnjD$zcv5ootbm)oVhobQ))s# zemzRw`@HkaJKH;R=FFLMjw$Pk<6!Pb&!zAJf0JD=92W&Kn@c6}e_3=M^~Qp2g+uQe zv%fcShp~I_rn~%iCq`qm8E=qxk-rvgHO#`3XRf>}F}fkW?*vD`Z$c8=*IRhY-jj=Z z8~XOH7BwRN&fB>KDI|P3|JI^Cl)}<5Da>&!sWF#HJ7vAk_AS_1hFlfzESa=$(xOSF zlNR)rROB{3wQ`}cus5kZwSjU_v~5x4zTTzC#kJS0>Dwb?FN#|jN1Trug>8&0YwdU` z4fFk0wa~}33Rzk?f7`V?OJ%H&8%yFStsgZkoK)Pqup+fFa!SPcs6kjNuK34V5i6xJ zQaTjpV;ScP)YZ^07jK+DW@;ZZ%XvLN=G4xTNlSWt<#B87UA?68vN!HreeI+raisZT z?Xup|o#nmH_btNTz8wp9-n;tVGoM#SAXNo#l3|)=W}1Zilg4PjHkV<@+zM8vN#GAX|L#&srw3dUjD{azX_(jv^T!mnCM%%IOg=e(((7a z_{|?JxvzLkT&t~H!gZz4^>W{&dMHIbn7nRFWjRaZNb|+orM<=Qz6ExjCQ(UIrzWMh z$f;9mxwJ3K&s!!-hIZiR1*~q$-m`qt^4=(3vgMUmpfu&YWXmge@RBW$qfk+@Rd&gu z3U^-d#tx-q%X&vtFW$Ou!bps==!avBiA%hd9&sC4H&3StziOe=oNdG|FDt2$jzwu}WXRUV76jAEB+28*?f5|;{(1;km#Lboo1#aqTAw=NUU{urfhT^8P9 zYAkl^ve{6}SmM@AXNi`v)UC_GGekz2OE-T-X(?%!q4rNfGsq^ISN+yGzkfdK4ObII zQNvX9P}7tKx&uwPTUKt^jmf?fY~b7e-~E4iV_nv5uGr@HcmtcOmGsM<1~$)hsi}d@ zvs@}_V6)1lq6RjrT`Fo|TrdQEsJxOI*sOJ_sDaHomx>zLtaquXfz5zRMGb5=xKz}@ z<{FoZH?XkSEiRpGV6)YwEt)q! ze?@5pJJvGW+%2DX`G)&%OnG9stL=Epm%Cd29K&v9e&bB~&6@}6?tI~kzgD?oo0l`{ z+U6LMg|hOc6;)+ROQ)3;=ks<>57lQ-%Z_#HGdLekFfLS|LCucI8pHkw+lSB3_{9ZV zUi$NVS6+k<0Xm zNWUn*BEPD%q@tp9Ue&xMMJ4%I2(--WmB50M1$GFUV;6EpYojuWtDd^@)CV77ces+^ zISaJZH`cV!SG9fS4ThZ+{_MYu`}?sMKYH(km;UIA8`s_1ST9}^Bx%W&cmC=Z7v=T1 zXwkK;Xi3B5&+SR#qg}6Ue|W{}Z@P&cjcZy0_33qMYucIN=j-f}|IeP`zq$B<5huI( zT`jH{G5n6KjIn7`Z_~JImwe%laW2`e>STBW)CtU~nSI0hHe}pe_OP3ak4(0AVr;{F zz+qNA{^J?1FS)JG&2;i1qeS!9U&)Nz@cHGwNvGex${nS#g`39Hf_C%Nr#w9B*y^|c z>E=16d4y=bzg-%BJk|H{_Rqgq=!$^vEp>sKk%K}W9hGkz<$Ks=Jo~F6?s!hDVOG9v zneW(;u`ash<9BcQ%h(22EMK~9Ol_>D+PO=k$4~EdQ4P9#;j`&}Q`|<8##4Sct7p@1 z+h&BuFr651X1ehrW8C!X^?OeF$%&PrF`}FpSbrNIjL}_u-#sraPhRAT5#7{^=desm zHT{j6p>O8>sqj@d(P;<~!_^W?UO8dRqF1kSpOj@wWM%S}D73ArE%DgQU%ol_nU?Xc zlq_lq9&4C2-?q%(pC*f*y&=B7uJMUcu2{Sv={#>ymO382JM4-5lZvLsy4kMM$Y{}O zm$>JWg0km7+|%Zc*3i^igU%DBI>u$q&va+>Zkz6A*0*-y6>}^qO6~QhZhw3K58n9T zf8A8dbb63Ki8+n@bVbpDyB>by{fSV;;~!tOOt8m}m~>LnO>J2*$6en2nXfYb71BF& zU%G8YZDWt)Nh6$28Xu_7B+9oRaKz9 zy|ulniVZQcg21rb%CP$Y1_z7@gI3va5&k~BBd*eEWTndi{r#aMP+-Hj&#*mT=M2!d z1IWGC;;9y6qyFiukWUj@!>Li&F@x;}Ba!G4=LYH04df%3xH9CGOJy~T1e01{2^!GG zA8C4NeBB?Be}+@2J$ld{Hb40=wha8&K{BW0Ov#v1TCp5&i*8%rj?amArcbDwn4U3X zM$XBZ(=zhXD*`<=9qA=_+PuB1IndHczw27t+gkDMw?I8Jd}F19*w5j*J>&%LA!^uw zx=7|%>>~6goIyR6q`@zbxG^MCy2zS9r&wHC-dWSx)xkR<71%JoZ`$io)O~f{fV#|& zzcQCeN4+t#V*r4*rUv-BXN{zlcUVJ z?TwuQdOtxyQ)}HiydH&?vw7E~VjISpK604wtO0eKR-ds!pS&8z>Uv~V{n&8m7g}8m zOP}D-?jU7?Ll>-^qmQCP5#XnJn|J}_pq|!-A<-l5w6;PzTzjCVKCHh{sSRVZvsgtf z7nVGrZnx9-6-}FMuW}8v^lXNoPU4K6KG?$;P2-O^ucDVPgdL!kw6-`SnYakw7k(tO zi393YPY&8(<`*VbR|FBhJ;LQH#>m3R_zm8rN{| zqM{l`hC5&Y{i%+fW^{&3+|AAHO&x7@P3wv`F#FyEX7g?Kjstshf?=H1OgHT9`}u~s zxvjRbvmDE3!FcB8R+{9mYOL>E8}V9TV{J`Wy%P@}`?Zh+q1@m~5sLNgfi){@nz{mx z@etRxP^-#i1U;LpKspC2kZy-6knX1{FbB{t9xCY?>>-zSP#kgnpeH!w7NGsP@1UIg z_N-yl$e!Q?4QO9D$LI;u7rI0Hg1Na<_j7n+$knaeqeI+MySk<2d&Sde#8u$&fc{MU zp=T2Yc>t!(9Y>twohltq+~O%|>BMc6uC`8I!&G3ySWnKU2M?$N-Vk~@i!pTrHapDc z?|`%i;}B;H@huci^`2NjKMiG!&HAtRdw+AuyN4+_f}P#+o{W>3pkctV>_=QIAvl|gkR z+NF8KInuk*k=k0D@Mh~ZauJNLf7I~TQ1iN`q8r9>hP}{0ZqH}Jy_13YxO9U3x>@ZdH(SWmOZ4hWm(#SudxI&P9sY=q?hWc-bVROv z-67Aoo$?+-W_CeiX9urfDz9NY#0McQct8iApBYA5n8Bxop9SrU5ez$F28|81H66iK zUv$fJ?QY4M(`A!fB>SJizPvaUX&-SX z%#Wpywg>70jopEa9LGhexQ6j7*G$mO8c*VWv--ZgFO z=gb%4#66C`+K*qsiMt)oR+L>~k|u`_O&i*dpmzhc_dloPw<;n`MQBOSKMQ{t8+3;+ zMxsZ$!z*Jl71uCgO?w!mR*?=bSp(|ud8W}6GBp274!l_JP)5A5cbk+H=JxLy<=K1t2kY^xrNdwYG)(Xh@Zph3k&1B*WE9?hB(jh&C|MBC zZ1N0P7(sE;GJN;>hFI1Kmho4=X`&kFS~-}l;fF0-S41IOr+&E6GB*BaW$Z3JW7j%0 zX2ORi9JU(!zJ(f_@oUSt)NdMS$^Vpmy{YBvMyI~0&mBGw`;8yg^ozn!~NL?`%9$=yE6ovgc+|8aHqic)vT-MIg(0p!=QRCn*c=2Y8mSBFR(v;m|J z>EdwC1ewTJ)pd7%bltY~RcBOfv5c91(}#iNdXR#rgu|D=-{Cb~*4*pv{4|)gy{@c{ zJZx3>H_BT6`&R5K%i7BSUT*)sln=;sYW+{i>}`gJ%s%X@*})s7b*KCxGMjpeWzGJx z6}!x`W?8W_`QP*Ozjimj-<9#h=MtYewY<`@D&0O|dkLMY$urzNZ0KQgNcvu0WG`PPu#R$8Mq zKoeBB0m5jeU z=6H$;WZg#R-PpfdNfcrY5i!S6OlYjTEn}Ccojt0veR=qX#)o`~7=NtTZ(7M?tk~Js zs7m@_6-_y{&@w&|d3`|5>pu@)UVrUNvWAse)^S$sZY%j%D|XI0p5J3FYyPKJY*wvh zEwzkfk?C)%nPy3c&Hc7v);|p6&r~b+b}RW9WV*!~8ne`*1{I2sVt-327|G9}^uD6B8Q~7ZV?I zbj-|{IWdJX3&ca@s0tkPBx>sUH?sWHjVn^m&p#v^WKY^yc{pvP1@lpUsQLIRY|wiO zM15>nb*TBEtsAmVmmjK)VB2mu5 z0`k-IFE#R0H<*>MlzPGQ`Op*3@%sq&(!sM2+I^td+t@12xommtLv%-8)=_gv`3{SX z4TqeMoM2fx549|`fl|~*4^^wXeLU6&ZBY|8+RbZWVzkP&@f3R?xzuHH*_;e|6AK}6eRzA7}w~uh~>GIk>!iBH410lnO z(`Ax?eS`}?So!D@&pyJ%FSY|A!-dnOnSF!{ zueJjr$Ks#xZ+gr9JlrjzEqD4m+K+Qs^b&NNr98w#7K5hfMc6h;eVT<>^mP*i_#vL|fPn@??<;h)_h{v?NAuJFS?vqN<9H({RMNZ7A=`vF3V zLR-W|6nbZY9Ys$;jd8LQgWf7;$LQyoC`uyTi9qj$QX(jCHX7@2=)E}#$9c622uhRC zOHOQ-{tgae(l;$Y!9g#yu$f_B$3V|n3M#$3z@~L&G-aLJBt|+7oA|z*`O{nucxNAkr}Z7 zQHCGGfPSc|DDxBSISd{q?gCR9$x=o5c>K0cRD{VN?8C&qj648((1H%av&Bz|qu3Js z3Wi6q3Rk$rzit=|xA0BI;9=q`N*B4}`}rrwY=&t@v)cjeG7#Ql2SS==4EsK0(0&Yi z-W49p-USZEk7e(>!s8g#VK9CizA_Rdm}Wei033`T&!z%X`_Mt*Il!3m@WV6{*r~ww z#DZ`UFm*>d2rmMrZbS#+a$xZkv%seTQ=QX6;nl#w{0(7ifP?7|VJ*P+iNrLAur6Rs z)c9eVL)k`P%-9@!G4N3e-UduQKnL-!20mFpj_DgOtF{DVt}(nFb_`z4%$m$!-3PC@D%>_kzjZ# z8;9^E*;V3SJEyP;eda zxeBJYI&M<%Ilx;KOs^ojQo$DhU#;LRz`_2J#;ybojxTA99-$cR@YC2$z`^z(#%>3; zC#og}xxK*0Is9Sle&AdMKMG9G64OEaCxH_M1Rl^>d|BO2bEM_!te3(eSYvPS@~p8Xl|R<25`^!{ar4f`(7j@B|G{ z)bL3fo}}T)8a`RWQ#3qP!_zdJq2WySsH^_7G@PyB=^D<_aIS{)G(1DYr)YSlhG%K` zR1MG8@Ei@#)o{Ls3p8A);UW#s)9`!^FVJwYhD$WOP{WJZv#$0i)$n2sFVXN)4VP(n znTE?Xyj;T-8eXB{l^R~9;Ytmkrs2~ye1?WsYxqnJpQYg{4OeTpM#Hu2r>^?0V{f|f zXf3>6!vPI9Xn2i=*J`*?!)I%Foraq<+^pdi4Yz8zO~dDCxLv~?8t&9^mxjAFe6EIj zG`wEJ8`z&+^}kUI{~G(NEBrhSpReHyG`vZ}7i#z-4PUI`%^JQ$!&@|bsfM>|_%aP| z)9~dQzCy!SYWOM*Z`be+4PUL{UJYNvEWa}yzof^Jg!@D$mgNAR^@J$-t zt>K$Be2a#^uHjoXe4B=E*YF)0zEi{B(C}RvzFWh4G`v^C-(tT zN3v5S9?$Uzwpe0X98JOeyUG=R2y2y?7H3m1pW7xe&Dm2h-`_1UAWOnr`!0!B^Y8@r zki@hYn1buYA4#0UaWZ>XVp<$dF;f_p6!;`JKu3gDKT_dGIi69=Xr%%^hX(0C(zrT3>@#z|j(x+=zN}q-;CttY0q%{cA z)3uHTOluH?$4X4?OPH>8DSV2=h0&=;OZ8E$^hF>i8mrB`75_Y+NAb+-hkiVv3v5LPK8+yBac)deUJSq?O z6Xf6K)3r6l>o43uIA4Xt-wW~2hbNi2td_Dy%33Mwq^y@RAZ3G;YouH&Wuug5OSw+U zCMlbxY>~26N>mij$2n5AOW7f1r<7gTxkdSYiZLX`eA^joHt^$VssFyz?|`1dQ9hXD z@^tVBpCzRMXCWL-PGiS^M#jHd#;=y~A!+T-2YIHH6pt{i5s^Gf%Htp%d(TRHXlS0F z8fg!b=LeGK2Qrr8LynY^Zt@U5UbVMh+Pg;DtCjX3xgE$_1Mwh7nLd2uX%{CBUXSoYZWpqS>_O7nDM_j?lC<_la*>o}Qm%w_?7krFUN7x7NV|~S z9^^W*3rTlSNG_MMQp&Sbdq0%+c1e5aA3UFs4P*!MY$+#FeBeAO>8Xkh$`^k@_T|5iS>l2-c+l8zodyuQ8e30S; ze_zUdV@O)F^+A%~lH~OdN&e{Adr8{6S=z(+#qB{>QN2KN zzk@u1>_ASJl5XD-o~zpXiL`f%w1-OP_8@D>9wcv1$SD*blKTTBZ&%1-)!t8~y{}7q z7*Dx9NS-f9?!S<9ht~(m`x_+r7vU1s-p{1HTctgW%iJC$@2`;by>=huR*DaKy_DaT zlGa*D&;0`O_rOklzAWwEChcRq=k_6axgoh9L(U@qfm|kKK*~#`yi-bA%Ou|GQvOZK zkx@dQA>~pjo29%+%1foZ64J@%D>9$A%X}h}JfHZ($9+iNUXbK}KFAxSyhX}8Asu_K zN_%%mdpNHl3iCno{sl?*fCxWF@ge^p<)5YeM78&GY41*H59dd250cx1v-p)Zan=0RF=y!T&Bv z@P8-upGy7zNf5CLBB|dZ^|wm>gHr#9)W0nCbZtcT-;??; zr9LTI=xH8G=}sVt@}45~v!(tFsc)A0bEN)aslQI@Z;<+jr2aXne^Kf`koqsB9=CaU zx?@Qq-E5L~V_cT{#Zq4-^>tEzfz)3u_18)L15*F2)ITrv?@0aUQvWxpPly%ijvYtJNUrYT5Qvb2kC&!6&k0*(APb7(SXG;BI zsb41b4N~7D^&6#rr_}F}`h8OW1F8R|)W0tEA4@%M=kRp>B$4i98khEn`f@XVvMsK zKOr&3O^%tfAM^EyYfY+ej@L_!`sR3p#HeqMza}y2o8yfVqrN#lPh!+J$LC9o z`sVloi5n!|Br)onhhHc$>YL+>Bu0I6e6hr+Z;m%hjQZyI5{a86-XbyTn}=U2G3uM+ ztrDZYIlfF{)Hlc5Bu0I6e7VG^Z;r2!81>EZl@g=AIlf9_rM|fy^~@#emrK+um#9xJ zQIA}r{W53z3zw)5E>RC$Zjln@<{0JW66NF)<>M0N;u7WI66N3$ z`8VJv{Tvk~87(CRnFZ6EmWS*Z99KB5G=tIKOdh7}6C`C8SE~C0Nt?~J`aVDknQn); z_We;v4i5>x&yT`$dAPpoj=#d2g7d;hw|C_cWky&FDkEbWr}VQ?k8EU!y2!}nRg#e< zM79vqg~$;iSBN|zW^j=?O$b?|!b+yFk}0fY3M-kyN~W-qDXe4)D_O!ymavi~tYir* zS;9(|u#zRLWC<%-!b+B~k}a%c3oF^eO17|)Ev#e=eSj;bFT*FgPT-?f5~8ZXuM>PtORN06}h9b?KZfszI&3B{dil zvIR956lTk5Ffi;E(_nD_TS`MX`diV11bgSE+~OGwaBmR}(TDJDLvm|pNCaD7*V@w2 zdCHWI&USqAfla9o)OM|@YHVp}wSVJVGXeW|LwilL18Qn(+XLNpQ0Mx#K!*)r&Hh<~ zcjvDOhO~9nw!lUQ9|!F`%FHY8YnHhqjZIQi?w2|f32x!I0O5YN>MAM77o`W^s42}z z?;;e&8Au)04Je?02cS^hA4wPDiT@o5Fc9*=?!O~}`=b*f9auVWi2kb`30&R!5QYU0 zBSBSFMM+g{S7TFsRZS;`q1vua8ZSE5H+R<5vMKF>reGP>Q=lurbsBVqgq#ZXQ1|K3 z6&i9*MEyw(y%*&D^NR?h6@WD&o*kGI>SY@!zxP1foofvrqnbw*1(;K zEKaWCgc`)6R|T=`azTYW>jo9hIW?$iv(KwjDCGeE9^8}${z+OoxAUIVu~z=-=Q1r+ zP1khvkFN3P$QHu+YhUw4L!J>BIf1Fg&_P zqVl@?;ce1*ulB>cS>t6!;r>pTbRXAvw}3}&ZXc8$z`5icVtg6^fMyimt2_?(i#+7-hsQI<@82IJ-D6KcKk{JjJPcO+ ze)~b}J&i$#-#%wONKtDA9_7wA&B2UJQ!~u21$NjS|jTA-p2`q-)}w$?<72I z!|x*>gx5Yp-XA^)?|U=lecprcZk>(ij4*cShhC183mN10Pc@>>``J8szwjWuXNtY? zzP*Ssen0ad_KKH;w|9rue`hSi{X@+bL7n$Fc-VRpa_GF}<+#rr!V0zbfk)mY%Ng6{ z!QL?y-gpm#cZ&ym%U5{ged3X~eWf>hC$I8Wf6sw;tA}zlR5Esx2cB^nWA}RCeaj>7 zjMH%++k?HdGZ=fw1Mda!yp*GEHJ;N9b3W4j^ujY4+vg$OlQGG8*aPov@E-NRy8-vl z_ITjsSBtr$PSwlt5Afd6Nx=7M{rtBz*cYbo>>*C)jjQ#>TkDax&m-?+kG$+UZ~5!- z$a~x)kJWoix5y)JD|lrd+T%6wNO@ zHO6#%KljL+17lv&y&F6)=_ar9W^X-sUhKW&(cU6lgnF^}ut(mp&ED)?=8^X)ct|?r z(A%x5#ap^R1ka1T>DV9PrCz@7kr#{o6<*Tq^2qxgcwX|i2>Up^r28m%7l+g`V=rp` z{FHXF?@*`yT;tsVUb;>K)_Ko*G-gNLP>kVEI~ z1#f%^i!q(|l1F==fp?Mzdt%FBr2fT3UeujSOV+?0;ajXF^od3mv1gdlF2Cq69_eu<`d*UA*N%%+ay@};W z{Q1W=v7dh*AcFW2gTIqBUfShBUX;R{r|~8$JWJu#X}ltZ=T~?aYP{9pr6Zj37p?HV zq472EBwx^YyOnh9dLZ6M8t);67e~f$5N{X?Z^t9u0q`b3QvTvefrEIbXuQwB ztAw6-3HV0`@yaz`=@sHVWW*anBpk$}_xGsjZU%28^u!yAe{>LUo5tI%@De#o@b+rF zhZG+92_0nbMU8hr;laK5LA?Lbc<+Kokq z%bTX~R%yK53U8Rg>(F=)DZJqdZ@b1j03MZ(@;5@^?bCR#D)uO!bWpq(z=MBdm$EoM z08cGHX^HnM&E6MEy7o92j>oPF=5M-4BCNd_g_je7m!$A=Bk)Elyu1j!bcHt~0&jxC zv+wVQEAKRgH#360JcTza0&lLuJ2e8YSmEK82|vQ+uT0_1iNLE=cylB0suf;-1m0SO zR}g{Mrtk_Q@Ol(pQ3T#5g*Pt(Z>z$aAAz?+;Vp>3+okY|Bk*ojcqI{ddlcS6h4&|| zU)~R%Jq{fef%gJ?D=uH zdamxpyh-v-j9~9+@a%F-h`>v_Cdiu@fmf~Y?0I>({N1ncCPlEvt__xBas*yAczX~| z?QwDhUd(mDa!iT9t5kSXBk=YpylD}5Uw~JPaLQjs1m4`8!Tj0RT~vR6)B5iY@Om)U zBYW6V!4Kla;Uuk|mt$@e^JU_d3L5WkI&Y-HTO5HmLE$Zlz{^v3OC#`#6(0E^9pTDR zsqmHwT3Fs%g;ySd*Q4;3N8oK$coh+NyAT z6y9lq7MAy(!aF?z?+b;8TfF=Tmu?Jh{w5)m{Lj7*5{@@g;o%l9Kf>`QC_LP{?U$FQ z@Twy4iWOdU1YV`WtBJr{tMF`{2P+Z4gx zcNE@*5qK{syo)06UQ>7%N8r7u@HR)_eWCC!iNK559rV8~5qKjN-lY+E6BORo2)sOn zcUc5pvBJX=20y~JTcyIoC3wHQwF>Ww2)rJJhfB16?QKBDow0`*>cvSy1USUeX55hX{V}*xPd%wId6dq35 z{qoq&!E~>Wz>86MyCU$C6y6OHcq0`ahID>}D{s2OL)Yt77hDLnk_mzSsT zZi&E~tMI-afmf{XZjHbzQ+T&U;8iNT+avI*72X{Ycxx5joe_9#3hx^ccs&a5t_ZwM z3h(X+ysZjvPXyi$g|{~XZW+K9#Xs!5b~ZRZ#&Rrok*-Djx%HQnbnt z`!-f4`9k(-+}Ei-poMpkRBk6K~HNzl%yGba@EQsE_ZU1PtDIDifl{2#MDdI%I zPT?fg(myz>VB5O~`YtHknN;@f&dnMxx;niN`}L73#j}~|V9NAIe$+>Cf_bDE#Y&9% z{#VDib4Uz)f5NtT@$V0?O?x+?E+(Q*Hr<`*t2S;jTe1C+>Q2@{)R#r)6>g+jqZ*1v zP2md@(t^;XR8t*qd}aTEFZv2!+`n_)U)j0)4?N$ucdKt@k?$^OMt75L^OucixAeZB zMpKC>uBeg!$7`Q{`&mq|#%uOY*tB!kO~qr1TCMFdFYouWn|wRwkD2d}sxi&^iT-Lk z+}B#*FCJrUANsQINx`}+ab&f%J?&*<;(q_$k#P5`7xe8LQ?#;x<@XhhA^<4Iu>o}$ngie4PehIVvS>`%q-B%JCq1=tg+cFJWIKFU-q(CvggD zaPrUg&*e2Usi^mY9c8@U4$|AD9bjGOoVX#e%m zXl=9w@KSirs?W!^RenCP?X=HNYGdf>C$%;9Q3+zYr_Fq__w=1(yGc8?Z36yIY~wi| zjd!V1>3EO#@zQ*ejG0sW*l+hf5tqQs zy-y6~A?ZAXID0XU5KI1^OTW`l2ckb2W&3v?(@H(d#IKQ#-UpQ2Dq8feF_nEE)fn)B zy?gFT{HVs1zuv6bi#!SYkm5J&i{F&Dv;_3zm^+_H;W-=5Ig~SE*tw^8f=fC(-)a1p zV-+QkzcDJ=@%QrIR5FAuwVHVem;S9OoNZA@_dFGoaF1`{m@`lZ^HE=`KSLdVChEAR zcmK|_kV-LfTlE?0__GlS=6goe{5p^qxfS2rOW*_WqTV?>qN<-- zx!kZ?>G!6-J+P!hL7IZ;u*0UQ~ImXJHR$M>2yT~v4klll<>J`04`S1Gne@VWFzBKYn z^f%G}DtjlOp5fQ<=v4>4M4gRo8{K{ST(dc8;_3NjbNa*yrtox%8|)7>j*jkrYGs8{ z(c9Q}`2b7)8IAvjl(=UCgvy$rTblyp(6o$oLEe6mL7VN^lB zb`gV@2|a!^N|%oIHqg8O$B311k9yCSvPO7l96S?Yyg#NT zJhgHGyk=n>F+N^PA)*(|j~m@RAETIW&4S(sYZmlI^VE=^Nu#^RcaQB}g504Nb}m9$ zicrc@lyR{vqsYPN?o7K>Jcr~Fqq`^AI*iIAWJyJfQOSv8m)kD0T4JH2@)ENcdE}w_ zLz;?vJCOZZZ>WAV;;C^fa?e6-^Nv?D+7 z^_J}9sr4>|#JQ?>5k_Gia^N3*G+y!0NoqSb_St89Te9taK0bTcL;3Z;%6@K#=#p&X z?2i_+`wqu4tTFCcxy<&Fsy{KT18!KimBmcMW@9@=3{M$eBAHmnj*@x}(ATBAVuF1!Kxo9iMX)jG51M`~7`a?-^P! zW)4UDCLGORiRLXIk6l?XCL7u~ZXLGzgsqdf&W?9HNBbs>wBz+rypgTUEEqGaHL5(J zHmdxU8diR9jZywkjamM9jjw!v%_prEwEptfYog14Tl0QvK`)hODt39d;*Grl{OV%0 z_}*R@>i}v8?!+6hr{Y%tcc5CKoyzL4H*6aJ?_5^HL)_sF2+zYlpIp|12Qfrg6XMr! zn^my04jcWaBCH*@yLmcI_*Dy?9yc7P4i>t2z9`3da}D34{(q|s9c(>nqYkBLLjLQ} z$$x}@QTT_y&F`GN>POQro|g^~Pa3+OG+&}0hOa)huxv#|$>MqCRfVNX3l~)_U%H~a za9-8&({M+_@-_4mT(YEM>GHx1eEQ0_HXRsGQ53&4r~z}B9$2zuc||^6 zc(erNH;3z?^GoxW7o+6n2tA}Mzr3QP2xT@$>Ou4K7nhWt#w^Pmr3X>0B}?Hq=4d^r z5J@eE#c0bs%7+z%U^VtU{r8yW`3tAJsv&Cm`i{cRrmCVqcVk_k4Da1&4&V(nb(m5d z?XxS6-?^8S`TMaKKYH(km;UIo64%|@ST8mPOImW}oxl3UMR`3gn!mQSwTa=?1CxWf zdbI1c?GLY5{Y^Kqqj613pgz5BZB08f{OIpaWB#*e_-`(LV8qF8epibtMhxGhC$q9? zQ*YC_YnOcCj&Uy8uIgl_pYNZQ+$oc&uUm`L<=g30f8;dqaGEUE>p@T(NjT(s|yZEWY(t zvfmx{#QsS|Q)At1S7~IlXw{?cxul@%`49KBxuZ2SwbsD*qSOT1pJ64xKkw61T}+EJ zc_~Ij*W1SUr*37wE^B_KJEM1-yIcF~Tf6X4V-^*q_O(;DzrFtlZ+!5-t`tOpgZxR% zam1%9iVocM@Eh+>geo5Y_*pf^JUEA6mn2MJGb#(;Vr*<|@Z4b1yc1*3yoHlLRxi#$pi5oKWvT}Rsftms}9f7L0 zb!(>9w>NeN+M60{r`n-GjaXj|XjxMpo<`h>cP=@~O- z&cq3Z2gH9RPs$a|g7;T*Iqg$QWG-Wz{eb8E*29hJKTbe^qk+L}(I~Erf z@d^F>n#QKC_CQgf6E8PI@1=uEZx~f^_IP>FNCWK+fjD?W9M9Wt4@3W_JC;YBH@p+< z|G1P1biyHc1yf-Sqcu)8x)V0gZQM<5EbjTH27CNKReOiHlPpfaRPGV@H&BTkt`o73 zzD?#_zc+RiU}~}w?@biFoJyQ#TxECiu)G0k^t!gLPFho#vX=E48x5nZ7CB?~Nj}Ql ze7;Lz4W}03Z@7|^zJY3~5VuG{x&xKiVRMT@)h+ldM3-WwiaGze^YLa&Ue{FaG~-ss zDMDET?;3l&xQ3HM)xA+Zh6}hrdwXkpRTZDh_>+0L=xu8M^`U=%j_;$-v^jMj@)}#J zYvDo<_fHyl4|-w%JZS!5@SrqQ=Mgsw(Ff=p=jiBcZR5+#yq8jW(~Q4`2_1N!@fpU3 zgPxIaiaM{et{o@St^l(aw1SJn>R5#3P<1S#S*$;mmy#-Au*V|WrFX=6QmNaMYT7%4 zu0#b+GbS2}FFD}@?@W0E>r8Z^<{!nKiC%F#*v>?!)FaNB=zFw5X9;wc1=<^1>v$Xo^3Dhtm*9P;1y1VPcya}Ay;Gl#2I*hyE=@&gCt(rE+lML!L50yK=(9by}Sz2m?z&T4b+ zr`tE)L!6B!U0Ot_HipJjF8vZv3H}qQI`{{bhUm z6`XESfeoWHT<`!no3mt7kM%>DuDFeaY%-tIN%|Q`X~i)}3SH(P2Z|bsKY04&FbrPH zknWM@K)&vv1EE#;xWy}&3Tqfm_AEv=rb8KM2l}?rjSIgz+U8W!QoO-6n+mJl*coVU zQ)wGoJL=>PDZ3CDp?Y}arCq`KnI((X|7{rZUB7tbe)(Z=yZj^3?dZ!9L7&R+>Ir%t zl{e0K%x<(WtbumEPX^EV=Ay88$Cx$v7mTrJfg^4-8;OdP4nv;@qv3;BFcsD?{$|hU zb;>|H)bC8=bQ;cDTN)bIsDsqTP}PRcjI#0~mDJOjscE|FI@>c;N@oY|p*5|mXf0_e zY+5&u*4ml9n+T&`dvjM)r>Z!ozOj3GpvhS-1E;NVF_G*AG-z5IbWKZJQcvg;a#)`{Gev~<%AulenPbC?o(cB2}-k;d`mh4{*bl9RQhTvb%)QmzroRc>tq zwtUHJImJMrGo!-ItB0n{Wv`BFiq&*$J2SOtHPE=DRdbCiT2*IeVd*05D0OTpvtU|p zJoq_hn8Fg56ic1c8C{>+7R2m|E-!42zB^=-5+>N!hiL8&(R?dJ^8{(Cs_HWHdTMGL z@mbIA26h?lTkE z4bbU2-%@$~#vjcv!2>-m4v#Y0!j6mQhmMOILq@@`g&B=D)Y0M_c7iLNe?3N|cG^#) z=z8!OPK+s?9jfwNK1?dCZr9M%6*3xhhKvRsp`$^2q|tzu`0Sn`yq}hkZH?CR(QIX< zrHqzuY=(%_6{5kTpc?0`5Y77`nomMBc&3>7Prx6>9trlvLAz$B7oQwyebM}`+81dV zh(94hRZPV-jAQLB`J(xG=s@?x`=X3?9~N-joeY|It z6Xa@oeMRn6S9s`hM7}GW4>Dr$WgZ2{;ncM%L+^{T1DwrV^fEGA>0+O*1oVG(O1DG8 zmHKSxEgA+Gn}c)dV4p>ck?xV!bA1J4oQ9VdJ3#`zkGdFjjJ?9MJIee+r=GZ{uGS z`xX8gcnewI5EA?v2a16@P1n=YU)W@gV_++aCqX5! z!}mtw5X&06+wAu(W6OVF z<{s8EcQa}=3NN=1t$LVi?r+H4h}me^_glEzQPbYy%HZI1)_&b?uZawvVp-!pY?y5s z8^g8lVb0-m$f0%0hn7(mE^|W;Z_n83L*^!2YZ)Ji%-!*y)V2>&<{Cb$TJaF?TEG~W+O@U)S9I5YSG zWiZ!@U3GT1H6+kr#ZI?|-1N!iR&1d)O$MJm{CL9O<#&>rI@}%RJv&;nNd{rRw}9_ zE(PH)z4X#AT7F_$iKcHT{(lMePufl^xwYMlN(3G7W&G-}M*JAf6EzxEp&n*hL#<&{ zy~i{|`ckY>#Pz4WWKHljH_ zP6z>(g`RK@5=N?&JJTnAq*#eRMz*7n1~Qu1YQ_6XP)IXrVTSaDW()>W?+hckokPzJwe4OwHxB(5=Ilf*wiWE}m5 z&X0fi{Rpc0p$lrvwAGeTD~hpz51+H~cktFD-1F-JT9O$2MGyYEtv(!4m@dQ`qZ86t zj6WtiCMG5}CN3sE=IEH2F>_)HV;0bJjrKt=l}SDSMwSmb4*%@<@gC#TvtQxjM|+GP z-A{ZYLi~}4V;>{%gQuUmaYgF+`K~f}wL$lQq>Zw}X@lBD!9_W`O{$DT zu|a)H+PEO3F3kS>DWzo}w2d?Mf*V;u>iOR@@>83AJ`+`vdcpsLaj$tg+BODBTc1Rp z+I-^;%9VFJYX75s8^TVzdDS7-PqAZTqd5(7>A9UYP z!)!o(;Khk0>9~KAZ1`f5Mx@3c6*E5O^0^o_eNzkr@86see@gsJYu2baqgrBcnWre@ zZ6z~Ak?U3a?s~HY`^u|7F`UtNmK`#UvZss0RK2r_ynpK(DE< zs63Y5#Q)dRaeVAQwdOpH0r9#!^D)3_^QeE%hv$rPYH7gxiS8DlE;GltIgvfr9*Cd*mj(F5SsqrX*nf{!h9e; zUYyD?VNf8=77|$&&V!gC3}^PFfgs*VCLs^?j{}U4pN$yNC$JJca1k>Bnxh@Fu?hq! zZYDzUrp0_CX~cLuUYf88QwFk&cP|Xmds=By%5SUUqSZd=qSQXZg(K(A5iXoAD(xd& zI9)W_N4RjhAheG|30E&b!o{bFrhSA9rwcIq2p3KlSN0Jue1aVa87`bIitHm?I9>GE zN4RjhSg?<9;dHTLAK}93;=?||h0{faeS`}ywgVxqLh|Z>A)cvmso4oeELu zh3X>Hw9m;!4c*L55oiOsh(NEVb43W*Y)<^~4xe5`=Hdr;pA+!}hgcFybY6i(%%Dkn ziICf*vvHk>nfM0=4thU~i-^5h{k_^GSS9rK4_7R)@0V{Tl#fl5@nFtr(;Y>S8^ByU z)rmP4|3JY(&*m#kX9pjJ1kSOdIBTp=(K4*gy-zRrLypk0SKeCJ-UCgva|OjCm*ycR*8aIa&OY41cJ?_)qc3` zcN8K282qUyVFtaW)5`DY2sGm*@a-&SL|k-&Ne>mu=l7UFr)UMhll zIK3PB3QwmN4{)>W-0{)wV z#{z$;;EBK%(x8LvPXivN;9THJ1=FdeTEX*xZ&EP5K=11crg4($(6)a%@QVtr0Y0GM zwZOkpa4Yb~3Z@r+e5&B{fPMI9+uw}e_SDZbQ`qIeEg~4@OJTjhn-zQm@U05I75H8S z-wphLg1-g)9R)uOOnsIPvi~^n4+P}+S>RtO_(kA%6#O&be=7Jj;5eszDeNs^d?=6~ zWd9Gql@33Z{SR=xfaU zcO%$J;9z-1urqB$d=qeRd>Fwl1-8!t z6#pvVvlRYyzySsC2DT5w9Leqku9XVH`;>4Wwh}++!X|stg?;RG7mlJ&t~iGe=cAD> z>}Odn9L*|RIEHn)a4fshh2z-WE*#IEcHsnuPmel>594>V?F`WRFkT<$!ig-`g_BsB z3n#M%7fxXpxNs`F-i6cHLoPgw{nCYpv(H_41RE~i1JCp9L;a6;;n5mCO2bEM_!te3 z(eSYvPS@~p8Xl|R<25`^!{ar4f`(7j@B|G{)bL3fo}}T)8a`RWQ#3r4Ww`2hnuaqp zoT=d~4QFe3x`uN!oU7qH4bRZE0u2{xxJbkEG(4Z3 z>ZT@-#bm382_?a3$OT$$fuGVmkhHEukr{Q`H2Q=KE;WZjwtKmispRM6_8g9~X zvxZwV+^XR=4WGjTuKMlJ!rNJ!E4)*~T^jDz@VOf9(eQc=Z_x19G`vy6=V|zS4PT() zO&Y#X!xw4zVhwNB@Fg1FqTx$5yp>(xs?Wp|l2ktkiOTW4dxhUC+=c^dSzyq=a|h*#Gl{wBhR zbUjJnyQTb=lynV8dU_{RT8hEwJy0ZR{eUFB=ZWIe+ntCv6nsiIiQ=LBv?fA&db>?p zvVpG^3%p&*x1@Yu%1@-EH`Gu(x<*Pv;b^TP4aVsjEDaY{)Q)K|o=+0xo<|aiE+&bE z2f7waL*tz;aXm?tA6eseD1Vesx<;dXo=7rYwr>(1Wd!DHZuq+y|9s6-wn*8^*cQ^a zNqLTx?NW9~*(oIo&iPox;PPB)r$@^5Qf`p)Yf^5M@;oWem+}HBH%WP+@KxUr7`~&7 zeBHqK8W4L<>YtbT8^yW`l?Pel<*G+v39ps%11bLk>BN6Q#>b)yip=Q4#ymb`3-KY_ zrKFd95gtm;Xs7=}8GpBokNV^BA zDJM{TU|KUGIZH}_TQyd`QX<$puoS(jNR7ROW-^`Ge&7gUqJ*kn|BG zlEqRkfpqNsRNA{k+C#tK_8@63)CYNvl)V0dDLD2o!f=v{twCRLpD)-NS;r~b5%R9N;?>+;o{7P@q*idM>l%pV>di#aU?_QZ-jE6kGki5K*yu6UVqw+$2D&;WBKk$iC&X97El(a@h;jL0$ zDCHI@uYh#&@k^PHZ_0dNJm&d;tRg>vtdsIKN+0;UQvOWJPozvH`v^Zt%0ekCr94N< z>!rL;%7>(U4ARNhYcgN=$b8}a!1D#k>jjegKjd+gJ|x}NB1w0jNK!v_?EOmG+b8Ye zJj3llo=xS0|W7xcV+q2DX@_e%cL zlK-;Q|3d0NmU>$2B>R4nurrn<>|{%Qp42aq`f91Km--&5-zN1}N&P)i|Af?kU+Q0x z`rk|apQIk&(dOw6CyD%wCW-valKLf5UoQ3SQomX1w@Up@Qh%@1KOpr#mio7({vD~e z{36{EB$4h>B$4h+sb4Jh%cQc1xSbgf7HTc!R%seeT3=~{&9ldeI?{%@t;h!*-( zlF*MJ2|JUeezw#XNd0Q5Z;|?TslQz6Z(cTO~$)a(tP@s85c!NsRjB z_;QI+pB!HyG3t}!D0V6O;}YfK66N6%<=_(e=Mwqm68XjO-QQ7BlF?G$wrugL_LcTl z82ydQa)(U+yPd`rjw{Vz^f%MC;p}k=yPJuqSv*2^aJy6J9wwqq4-!K5EKzt)Fg&B7o%VP(3oGF@1i zF04!!R;CLp(}k7k!pd}EB}Z7v5ms`9l^kIuM_9=bR&s=u9APC#SjiDqa)p&#VI@~s z$rV;|g_T@kC0AI<6;^VEm0V#ZPguzlR`P_EJYgkISjiJs@`RN$AZjcQ#u1Zooq@)$&~h*=7z48I-xm5_D{Xra=IPZf9G}4oNg<$VLPuD6xwYy zLP)pO!h_v5B*5vmdWh3)wSa!Qt;P!Npn?!?E1)X`=EaUaUF+=4a|JkC`*dx8bZ6_H z7Qy{$)<}VJYo3dOT)Vg8>7gMn%A11Mm3MTWGNq%ly|HBto5CM^u4-&)XtjSgHMRuo z-wkj_2h`Nowg^t=pRE6Z( z=><+Dx-`L^jzJslS_yvB*@-AyI~YT>z7y_h7g_b%Cj}gCun_<4$j-Qe9wNViDSXli z_-{uR@5a}=s@rAt(2!0Mz9YMOZI=8vA(&p zrj|`<4>V~F9_BO>N(w!dgmRSANw~n^DJ4v3&>KSo`}4?9W|-59Lz2URYwj1U4Sk>q z2??H2bc+aaM#(VIoI$alu;B0*LI^#5UwhJY;Bp+&{VUAJgT#udsN3-`K!MR9bHe?MD&lYk?6=4 z!ue}oGhrzrgcswmg4b558gCYGN*LZWjkg4Nco^O)jaLsmGz<@y@vi*gGMr5b!^35$ zi+3yVxG+2{H@kRPJ_yVEp~ia;cmn>}hh2YfL!s6)ZZW#*+UEU3;}s!btZht&5v0Ay z6vu8iy7x7k0^~tqbj;LvcLJA*ApY0pt=4#-0gnm8>(+QFSOdL14DSk!_Yim&h2ece z`@FUhXl(rk$&)lz zjLz{kbyn@TRO6k5&PLA&=!edGegyW-d*FR{l)T@o84R&^6l3ptuy@ZfSYNdZso2!* zJ#(zQFRO6qr_S?_756taS_rQgg8{#fsu6X2y(ftKks2+;-dh+9R6n)(y1kPpVb6kx z@?LVXykBV>l2W&4V1VWKLk_|#$dvaN55oH{oSEN8JP0o-7tg_9onAlm{7uA(f!|-# zh&u1#IgIi9T?gT{7Rvir2jM+9Pu{OO2=BuM;{K^d3u)gu3&Yp*HClh$RLa;NbYs9e zuVFFzr3ao5C(Ii?@NNcgw+G&grQUcy2hU6X+HsQc!b@Dn*liy2cRzTyd*GFqdrS8t zkGw0EGrlKEPg-xctO{@Ccon>dbYsA}y{#)4yT=1BYb9g1gc(nDdq2ZOYKI42&1sCi z>?PgP8GF(L?-TGI^}yS6hPV1FS&iqWJlIP*6Ze(Fl=tgezg&G5?$avv?5T&&+wGC} zhDYAfRXA^XNVnP}?@o`r_dN0@S9{A}n@8S59(iAQ7L9`NSd zfr`}aJ?YV&8DI=UN64YuI}5zEAuPsp-g6##QyRS4+v$<_rAJ=F8nM?^FN$7{pMvM5 zym=tulo@j9_O^l76v7IvzrTWqp)%yq?Nu~-v-dQ3XNOn|P4^^_Fa(Aidb*c^=f&Qq zAbIhtrR%(v<9pzFsh3fxWZW7LIUdvc?i^ux&$Xn)-caBHi)gE~dc;x-eBkvQByyRAo_2-ed%p>m{ zkG!k<;k~N$j|adzIZQv&d2fP;OXZM5=M8HUZ)?$sI&UU;SV9OnbY25^86hmjbl&yg zP4mEe9=wSjcprmzk_X=CbG+Fr1TV*fz4hREDepJI^OC<;!8^f2x_<}HOT8T5?#*5a zcwX$agEzrL{%!=%i=RFZUX}-Ye+O@h2i}B^@a^#~`jJm;_2pJh120^c-5X+JHb6~UB5Bzn&XsM5Zq`l!P?_GsQ;dGFsJ>x3x9}3Ub z6K}1?OS>ePZX6lIK|I<6Y{w(rWQ7+`3LM0{L*o@Gyadh?ydP`4)!%g+52C<&E9K@y$l&S z9PhUZFEaw~J%wlce>i&|E4=Io_P$Vf(R^b&!;I%2dq6oYmg*Q*({Z8vgo4~XC@8}4;UEs|{IE@FmmBbJ7Ki%GI3h(F$ zypdaj_Ku0btNj1$y$N7d#o0bS=iHo|n}o209Wh+?J&>>qNC&Zh7(+u`j6uMF{I-;j2A?#QJN z5qOTiNzg+F@jll2+fMLaHtq7_(ycs*hgT>0=Dig+dFzM;?eI1zyrOn^TNK{Hc6d7# zUU56Ty$WwpJG=u5ucRH`lL~KfJG>t&ywY}fuPeM$+u^;Z@M!#?Bd9(8q3}+#X@R`R zZm->zw8I;q@Rqj28>8@W2}>S9_RUmyxP;XvuSntH5>}hM6$t&yv^g?CXqyds6Sy&c{Pg?Di~ zybTI(M?1VN3h$D3csmu|rS0(cD!j|u;T=$Tm$$=vQsG_E4)4bb52qON2=eFG6&{vk zZSvkzcsmu|D6Jp;13b!y=6x(>vJWTCv z@}de4Q*oQTF$(X7c6gH&-i__>W-2^PCGrTWzg&ffF5f1vNa3Mr+T@ifJp9=vZ-v79 zayz^=3U5z4ybTKPmUeiX6dtYb=m@HpEeh{en-<91q3~{NhqqJV-QEuGMum4rJG{LL z?@onx68aJTcZM)=H+ar@7Sp6C0SQ|~BFcf^0k1Kc0Sg1NT;pZIsIw8K9>iZD-~9Ui%wcZWyE{kNe{b(! zN9@UNjK|J#!`|IFmDyJ!@5rGAt@6G^=DlEd?=|CWX1FkOjQp$MvgYt}nFYHFcfY!) zVAuTJZ|=#cJIUqDY=g5C`6M0E>+N2yx1MVz$aJXj+naZrH=0Y(Vz-N>)M5pwy*cf~ z7VM__YpuIEP`7cT(T;9Cwk_T7uKOR~%Y6e*W&l@}AWTR~7CkTygLKdDQ*kg5>)%Z{Gc*J%y{eNFS3rS3}RaVm-nuk+vG| z_@;bn@Yh;|>1l&Fc-JBR%Yq&D4nqHLz_I2pB!;jP0@6NY7sK;l_Q%DV5pdg|r{H#J=lMUbmI%o_7I z#A<7+YVg+Ik%nW0+!E)+lfV7WzXshiDdbCR(Aw89@ZCFUSb5Qs)k_zyoWFYd)Olx= z&xdK|BrPU8XQqrYEOW9Jl{0O+j0#z1HVmHw)tvX^mk(|lU6=cjFK=mh`35}nx}mP7 za%uI}D%hT5ICf&tb<@wQ$$$9uyRZ1fm)@fFM%XYH8lhNaWxX)Eo5jX=X8-c7+-GY? zn)E14eqB>-qcF_jW_NRuao&sv|MY+Jc3o$#y`a&H!uPpLyeLX_>biA!oQIO(OWBLv zIA4K&JpSb0_WSdT6MY6bEm2U_P*GpKsj;pe1u8WhS$3lKezGaUO&EJ-Y0&|jsjaVofxs^g0GIw zIV0(YdwiNLI)h0v%+rlfMN@qqSMCb0auGUDtwhxC8E!?Hh%HfTA62~4jm7K3yxhNh z|6lIg+c$iUFL$RJ*`b#<#u}R%P?KjGjld^G%G?M0wrtIQsO&L67hSO)u5V!sbeZMf``N5t zm)=w1XS#N9l4LQ$OLFTc*M!EeeB^Y0l4|OVmc0DSMpR}zHgL$AxBuhkxvFJ?WcfS` zC-`3P&__3X@{eL)g5=e!n?TK;jzSJj%5#*;_snxTr|d=>6vh4bQ-!kwiO|zp#ZfUdWn~T2wz>7m32+{#EnQw zQhV;nH@w~a+?#*?yPqme@c83B+n*^fcwzrzZ@%w$2B-hGa)zPTZ2ntlMcOMq^+{1j zi`vE=924kGXI$%MoW8|QCs?%f!Pb48a;T_im{d@;wrTz9`FZmeChX&RMu^_;=Dm&} z-I(G5!)YsbF2rdoE@vdHvZ=y*bj3=i59!cKR{!i871l7$GaS#?IdO76a_o+t;$5f1sX3v^6 zePYh!?3vN>sx7gG=t8{Sq`qlmRc#~vT~SxRsjfcOSXC(uEEOF$Sh8gvs(m@0aj%s1 zYdgY~nj@&JxVpmCwky<2t9;I&1%2TT(Pg#OTcVqDj;cG92fD-UnmeehxVpnW+Z`HP zyMq?Q?$DIz(SepDU2bOH!lMJu&#{NHq$*bF?jOi8f(mUIQ)rF|qQuc7DnyB~Ri7#h zV-?Q5N3H_%Rpvm?@KHbKBedLo2v^QE%%S&-HrmbXkv0}PLoRYD(ZOX%u^ z?n3Kwj#uwX=Gw80DVVDe-Z2x$}%ItzGVH-Fx7LmDrII&dyMf%Wcyc7wTF% zrdb%+}h?Q&C*X_s?3`Z6N96kY&?u`b^pM|d-gYMBac7#FlfiL2x7F*bM1@fz&S zJ7?!D(Dhn#wpP?Oa!Hj{_XVADN!n5nBH^PT?aOpImvlzK>IQFwE32xlq_-5(L4`Jq zeg0Fm*3`JV=HnfjhJze2c-plc*eO!0Q80ueD-&-jVA#H&a$}-L!7k}?n|KsdT`mu= zAlqDpnsz+yDW`etWs&D`%#5qUy>`4fT*Ak=A!vXuJI2}5ZsEehQ%}d%ME%BC{khWP zsL+P-mb0_(O}~C>TwU(dxVW5Cqz;X7_Ol54z8K?;P%!yL5p_nT7iU@+?eso6ytWE;$R|%N}}ueRX41 zd21K#Z;+4rW8>vq3cbfdA?h&>b5i1u}0+$_e8I2Dz3+CD2K=QYdt*ltL=ci1zn-!U`o z7Xr3bziOqNvir{u@BXu8e95+NpU=Jl$IQNek$nxnw^HU^xo>$R{#nN9wuN+;wpW8a zj+uq~3|Kh#%T~(dPc7?h%Q*4)GViI5n0M^j_boDSCAIG_EbB?j=x*2ESJlS-cjAU$ zz2~+V8J4yF*H+3$R+{#MrJYxqsveCkeSiJ7lQpl~fX zk}xJ1#-MI}L?j$Zjzl6Uk<>_9WN>75WNsusvS0vs&OukudvCu@)2f1SsirBz-6g9mO5x_gY7u$$nDs26v|@j zz&)c2qu6TdWrQL<`}a;eAu=*@O)jo+hO!K!cPKI|?WDBXX>$h79atMd5kNNwgd$3k zUPgw|IvIt^q}IY{ZRE<_$W^)4&fK({bJH==PIYxyJ1;RrFXQUmf&YKfoko=@>m;qM zItfL38M~-f!bem?T{I`xrxH+qT{W-6^~$5#G9%4!w4NX>WU)pd#r1faYE|lcR2*jqPoq{nhWt3RhTZqpQ~V zoi-Z~&xYg~J^PRBj#qE(z@SCh;EBnF(elMhr{qk|&zU@Va&*CzX#S-9@#AreUS-w# zs@kJ=v({kbB~JjcB5@8{aX3dj;%OD&96|bNhIfvjc$&SPBPgC`X6NWkJk6-i(V6sW z{==Ziu3x(0cs}-r?5kb=yCi8{XtU^kRF9=@o{~jv@znh*;?Ye+wm!Op&CwTha}}{i zyKK4`$rrSjvYFjrucxI@I)r*4ab!fWp-Zq*p!aBNDwsHwESan;Me}=oN z>Dq^*+P6DTrSqznHlQ7ve}j~Gc_-qhe4#Mz;p1A4#L+$di-QTn}$Ov5{GFf%kNd>*ihno@V94QL>vHi&XY_tBEAmn*%uLy z15+K+LGj;*Bu}S%?|%P&Rz3fRjpMf?uf%P&QKC*I31MSOsG zFTWJ=39y%6iuerJ%P&QQ;1FJZsUj7a{EH6LOvPeWEl;W#0E{_99;TTl@bs>r#V#F$ zNBQ_^@;mht>}VN3)tA1T{PvTVzMGimOW#c_1oqN*6J@~8VPFznq2Q2dh_ijz#9jFg zn;yOh3Hs)fbA;fJ_xi9Up7r6d_>B)Ii+}rYL=3dY4yiI^rikf2oGQwFI8D$ulbj=D zb`zKRaJry7xtt?p_Rw%o4foP;hK740neV_*?Fv6OMC#eYUq^ljDFPzkpo@CaO%6dL;xXjnW zITq`oxs>donf!RW*B?CAxoJRFzcUuY7`$t<&3Vv!=_r?5l=NIZ?@be1z% z&SW_YdoZMTwf)V7&;lVgQl@J-JjUTg25Dl%$}7`D%Jh&jJ)}$z=}TY9=@)T&)YExnKjd1< z7m~h1Npdyi4_V8yf#n6NJy?)dQ~DCthx(TKAXk$f$O@KcPWC4D!`)wiDYm9jpxztjgQ^+8H~kkUR#X&w_OjeULFKCu9{%`qm!dbu4LZL-;(^K2)BpzcSVbf0X(lrG1dnK1gXFq_huG z+6U>g?;O^58ta2!OMQ@Ml3kFpT_9!sLCX4ryoKz8yo2ReR6EaQy-Qdx`iayFDg6#o z`W@spN)LGr%iCDe_qZthK1jEH&;aX7s< zp7;|3|<{7ep)^-X#>{7Mer zOA_I--jMHO9R4E?|1XjVpAxe5&nF4~LXrsI%;7Y)Q#gH7k;3oc@NaVX6CD0Bhri9? zzvuA3b9f2{UDA_I5_+N}QLY>gpU&ZB9KM#r*Kzoz9DXy0@8$4^Is6$8Z|3mVIsAPN z|A52OFz!>nCz6CcLrGFSaQJ)F&J@IQ0-M;xAt`IPb5MUd$oLhEr!YQ)F~)Bh zzmhS=TZzwPjPX+9Rg5v-NqiP#j8_t$%^2egs$Yb#snL@p?3MUr#;{jnESO|G?3H*f zW7sQkE@Rj$aUNsXEAc$Wuvg-I#;{l70>-dc;`xkWuf&Cn6?Nak+P8PcWd(~UzlB&J>!hiE?9O(tF6xw`6EiQ1^wo5oVwvj;ZtPn zRE|}*IVpCUjGZojXUN}~@^_Z}&7N!vJBREX8`&DOr`pKYkZr5TwsmCNO0sP&IkuJ@ zw$s*Ws0q3imhdet!0X>Ws0q3imhde zt!1jzQn(bAmep9brP2O9N#9YHaU7~vs2Z+Tr57HwL#)RtJHlR6&<;{}T@sZrkGNzyms8c$Z#*pU=B|uF?rt>wtHyUR}O$_1dQDn#$F& zM!5FcrbhC?h6^?}#@33g`l=ew|4IQc%S z@kZeMD2Vr4jkg0lEQ{R3(f1#X_f#AD`XB+NaoTMV&X zq2*hyweNXjgt$!O5Y%~p1Mij&@U9u#G2XCo9pil)yxTjFZ~1s3?(P8ZZ{U5U1H3&r zQKLN^{m|=W+Qg3WUhN>S0h{gj>zM-U`3}OlVn=vC0PlYT^wGG8|J~zWoNMB=%sntX z$V2D7*FoL{oU3+3-=+@ozSTkAKRU>pgLCJO*tesDyygz_A~;9yNWM644dl`OpxSOX zf`=wQ3R!xEfMcjR#{co=$H9p42{UB=xF-pdhOmjUx~W@D)=eh6NQl6n*NOa}n3z(0$_ zkxaa+@pdXa=Ny7~Nyt>ycelc$b3i(XH%j9@sqiSC4w6M0?`4JOiOc$Er|&W-5^;?*cT=X^Pc*QoG@*y;lHZBuyBc6gU7yrJ#zu2p!$+Tq=-@Ng<3 zkDzkgq3}ku!@F1EjckYapu!ua@cvh8w{L;x^p76x@Lm8f7xC1-)X(Uka_IWHE%11~ zBrBL#qVRC)Dvuz2*Me7uSjxAzO$*HTO@)V3TzLfPn^5HG>)Q@*o5JhY4(|np*S{U! z;DuhkRNr(2*;fM|m6iStBodAwUbDg*WYZ+?|FrfUT#RoUVt^%m*m95u=}SVG+OM0j zu|(}kyfKnx=d1HxRd{3D;k~2q#qv`&KrXAEl_xq+tF99@NnuSk05=O3J<4BF0ZfFZjA~ruN~gy3U6LJyqgtXemlH- z6`pf`M&;1$`LYLHU*_ zywhx2Ag^5EEoq0hO5rVShgYfa%G=@9D75zf<1N#qC3B8D>$BZZQ+TDX|cK?fCUF-Y`oM zYU0-p-5^8luj(1Io1Z^;MM0*Gigq{8A$Ibb;xK(Vtpqq+SF+Pa&D(8O0YdHX#_9Il zcNlx_XM0MdJtb_<0mYu?=kxcdwv@QGG(TUkCtSyt>@HwdK5QxIPS(&@3;nh8F6Sn{ zD)_uv);x#4Uub{r&S56U)Njh=?~b4*ZGHs&NS%WYzVP=Jr_}T%J~e%g`-M0)eUg^` z-<)2xlXA!1s%T02qTL$K`CuVF+hKOAbMbuKHDo5$iQ5j05j&i3Fsc^dsS(yu7(O^a ze72&6G+(ELirZUmT+xymOOtsN?ryp9?3U&q9eA;M4pI~)<9m(KmPnE;`LhUFXonPW zNKl?nE84w0pHV{XJd-)k=I0B4>f~m$%8f$Q+`1j2FFFddFta(cD6=@T#8>0JO{cuZ z>{O@Lt|-c!x9ipJC7JJZFU~9q7w(;ZYr(FPaP!_5AdACuTj;N%@Ox`Y!oP=qzk@IS zb+gNtn_5#iNEj}D-ay+$TT0Ye)4_&GdJ4nWN?-DO!cDGSwpC8=ay28Tf_8I4td>(j zSodyfTReBbEgt3;MSDIIvHuPq7;va%bxZRPg4*q0tx`7cRns-!N~zSbhVmO3a`K}( zF32>-zB965Z~m>ebvpYpmt7Q|8taMiC_5I#Z&qwFe#ggh@jE6~hToB~HTWGC+l1dC zu^spw9J>*}17mmNw_ofL{PvDLgWsO9m+_k(`yGB$V;|v{?7BwDiM&@_XBs!dz9Kn( z8DqtDVdG}SQoZ-#o=&&tkfnvv(n4uzp|rG6T3RSAEtHlPN=pl+rG?VcLTPECw6suK zS|}|ol$I7sOP^M9N`vp22H9J*+v$gW>k46Wua--M8fu4KhOh-LGpJSnsA!LGIX+f$ z8oH(^d@wgshfrwvqOp5Th4nuq0eT~7jjK#vsn~MEc&Xc z?%(&i7RS@KA9Qm;+b_mw>Uy&65h>ixc8iif1o`kURV@QrerwNSxVt$)J@j`FFCs@V@~lzI))O)QvPIh{+dwN(rNCX@TwiDlw-$%Hp@rd8rEGRT9K)sS z?JM2E7hXaiRm+=;(q;JC^56@1xt#V}H|AR4tf@#_kRNPs#XR`J)5s-=d%Me>hp#FJ zbDmH*_KZxL^f{|r*sHhr&RKnwocf|I(&Q*XYwfb|!IDtTj;GAJXRsbhmEqL0KWw>N zl!gm3DLx4+h#exmu3*qJA{D<;(HFlxMFxH+iyn1Yi-p8Z`!iRxe1iE=82fvCK+@db zLcXX>vm{&w~Y&cOPNZ9n7bY zp2AK`;}2=dt|Oe$lJC=;-b!>S3pIYc=J8XbeqI%oyZC)sJYo>&va zYn?IJ&839vuz07xo)F$2~VN)=m9#2XxaqGIFT!ZdzHZXAgL;fk%vja41$7PKHlD;)eA!OJuE<$oaHH z&Zi}EJ}r^+X^EUqOXPf7BInZ*IiHru`LsmNrzLVeEs^tSiJVVyUWc}O(#@qX9E%l% zSH}u>H7}lAQ+OFHiavLsMEYXEW%zzFR&~#z{N$_TZ+1T}$}C!tRD(2w3{g~&T2nO7 zlBlOhs-w_|C@Pd8;pWV286u2{b;4|xn&4B=j9PXzQ@!b$lSI*cXwGk2vz?bP=sWGH zhl;sw?G?j05vOi@;=G!?vsBh&sjSCRS&yZ%9!q6Cmdbi8mGxLE>#py)^;qxbQV#Dtv8FV<_9J5+La@qr>PyS+Al$hE4cStiR~Cd*zX%U&kS zUM9<4Cd*zX%U&kSUM9<4Cd*zX%U&kSUM9<4Cd*zX%l?>~%Mw}kvM|c{xcQVU;}21C zS?=OpIW5gNYgzlafl~Y9N_I784z8ng>)K3L(MCGwEU;MS?e%QwMFTEup}iHv70~#W zB%Be#i;zAALMb;PVe+`=lsxHdpRpbZ++sdFxB-5@zdm5 z&EX$>;X}-`sd9#QQXG8Yw>1?j&H~NEbpgEPSzTHl*uSK5XPD%Y!u-fsvr|P zVvxBV_tHqV|$rAXNaGF_E2)NZ7*Wm%jo>iwLQGCa2JhC z#=ueVMSE_c5)@}*Bnub!2vrw{%{u&r9T8(}Svap{UUD?01m2Y%!#>Al2M-u21)0x1 z-@L~#^OhHj;_xSHglYSyzGGGA+7$1WJ73AE=bHT8p;!c~8}Zcs-MR8?$UY0EHBPE* zH}|aXg+uT<$FtSh>ONOvp=`PMov}Zpxf zG;9nkMcCirK{TuBJ%3V~(|h9WKQok^daCCwc}dt4H3kmBnKA7%7G!3y|Iq#k&bV{! z_#TKi#x7{FIre&p7&Pt*GswR-yE(?&zqTtm^-#(dx^V*LbbIf>z`AWDN_KE@hVQKU zVD2CvrrqjZ{xh@O6lU1xWi%HAo%g)#S`qKId|k<@?NL0+D^=a+!rc<(bKRAk96K$Z zZ3;3Asf4vkX=7UVy*t|q!pb;oCPoxmM+{vD_@)ZJ;lZua%7 z?xe5vwaFnakFG7QvAOd4RK&YJ*ydU(-%TBFA6ca2XbBVSLmRij==7e579M5o=p*EP~TQNl&%mpsf z*?XlcoI&lgwiWZB^sXT86)rd4-gTXl6WX9Tzr`4sEk{-C--K>{HpsdIZkiq@#nUq- z8$=!6`c#F#n(&sJTKqNu)dM%;NrOrFs|vR{*CBM0s1P|~vi$FS5tA|g_;rY%iTj{u zh%KU$)7Bt;OzK<>J?Dz`2(LuiYJ3oh@~OdJYZ0cW4dRe(cw!lL2>F)NBuLy7`0lXF zo_J`?i+_j$P@x3fCt_``tF9DcB>rStuNC+H>a|N}ZiynurG?hk)z#2zvFPqRCO*;h z`VEgQTlFZB=CyU#YDZMp%9fmHE!+DgFGWT3?EYyg!js?AWopX2i{<|L~_c zpLDNo6nJOaD9@S)`?hS&eyHp*Keu5+U40|H3xATwEdSomX8pSKo(ezHwS$u+%eU9E zA-8^VO=$eeM^5)Asjii(>4tXZ?L2W{Pce7R+diJT8ZSp^%$^RDPYmTcss!C1$jM%P z=_2!gvJU3^lR1g{B#n3U%A5N+QDw$s1Ba}6`#-)!A-5RPxMcZ+Gbi|7@6bm#eDaTC zUji7{_N?hvy~#&>Za} z+HEo=N4Cj4N0(~C^DzPp?pWH+9=K!q5bKoQDmyVNrjGPwSI5h_|7czu5h6*l@WE6 z$@l4UQ%v2OR#{Q~{eeEJtly|CMv||R-|74P=J5rSQv7V!87T!POIADW16Rx|`_Tsn zHu;mStEr2jdnc)uU%m0!&DpzmP4hD=>zeSQXpxkpj!P%s@OJZaZ~po3eyTLVGUbg)ytO7TUc9J zwdHjB9wrr4menxM(qiKDEhyWkcge2+H&su`p-%t^r=jr~)-4n`zqWEy9nFPG#Ab?+ zmRD6Ssamf_HB!{_SWS~pQ$2+)t={Sd;zO9*DbSZEeJ|5h?P^uN$eM~OQXt)FtUy|W zh3&iE={<`H8xfGLe3^Z`#-56bhDilgYn#@uo}V{wVZy$|VT2B-PP(KjR!Jq5MKz2& z9Di_qRTARrsxKXVSM88fUer`QQ@Xow7E-pS&a@rf2~=FM1CClKE3m87fx$^|^!P+<+@4ENm0nTH%sTwSQq=-f<{MuW;w>G*kx_71#6r0aP{f$bd&Ya0uy z8)DdP$*-$ztjA_B9aLh&xQfP>)`YnF$Ng>i2hRJp((qPTwbswSv8^(9ohy3wzb)h%n?n2Yag9LqKAfYGoc<8w6 zxzO#d3t{2e*wi4amP%?E5!31C_Bh0ZxH`{j)2I(RQ!TQ4LUrw+z%;c!{jQS&8;dys)n8`Q{wW zH`OVU3Tzm=0$tSM#nn^4V+NnYwdsxIzM8`+&LbCCQ>F9JNoqm|HhQI0ms@_%aGi%2 zSnifJRWcRXFn(tGR#+}0u8#Az8N3AV{1Pi{zdI}^(SCD6SM-}{uHV>eCf6y*ZK%YC z@d>+)Mu@A|L_$a1YwS0&%uck|&Nw=zT<8&VAO{?&Ek3FB7PKskk_yQhi5b#no}{Y{PNdybgQ>%O7Pml#5b_ z%kg7>D=?v}A-YJ^i&cNEe=u;S`xS0@=; z0=KfTr$l=Jt^EvFe--1LOTZZB zIRlb;ImGw*c7Cb7dVeDb2aAM->5%;v=5zbXV zGNP)%cjrO7w}#6Rq!&4g=$GgbgziZ1a-K5K=PAz3np9N7c+_%EqwQ4;H5M`A>M`GM z!(%!$w~&Vm@lv8a<4t7RmF6uftE;KOZKqZBn`1Rb@n>E`1lW?Q$-Cn>*M!Eou9!GeJ_J4WnDK z|D?_1#MP~@OFj~}t~j@<(f9aXC-zT2hil5ct9{Zn-%PY?KGGFk^S5odrZXc`p$+5y zK-Y}>oSYvqHn*{-FGo+OH@Rb)bKj~Qab4GR?p!sDvz1ZP2@Ra!5oq7f8mtM?TZ2`} z$F;I}X(IdeF}OxX=#P)c<%ln1 z#rNnOM}aidTJCe@_S+Fk1Hx7Xgq;%*wgq9~3-KdFYAC^%9kwIWF6Y|ms70UmI%77K z)-d+_T|4fB^~;eqo+V%pZtdFqkO8@`<-nAYr7GS&+D!&2VS3RW02n5s_!^@ z5ZUNP%Fg4&C|y7st8-DWUXPG(TJU!W8RYK|GRWT@WRUC)bZf>jxTkL(GVOA`LA$4~ zU~!&*yr)7NMl=OI#_>cSC$7W(X(^ptW7}nL*EjIm*4tDFl(!+2R-LcWExM^d2zsz1 zp?jMHkZG55FnWg4?>zPm>9UHc#D-C=c^4Dn>RK14#PO0FtxkoYyR8%IKXj{nm-8Qb zklXJ+{G^PmV=A&?+@v{>!-%T~9f+p~+204RO0);jB;4gZXoKcKxc@G1bFA9F(S%BD z7~f4%w$9yo&LzgxkKX;flU%#AS$pTu+L=l&iXJ`_KSI2dXh++DOuL+;{h_s^Ip-Es zUc+cfab7H{j%aYRxSwU5mfESajG1)%pKxBx>YQEp*8OdIBTf_i$-%UDfAsXhn?Io2 z=iL`H;{NUyXu>{S`qDQO?Mt*5)8z)T z$8BFy7kp(+_HBApUc>l#Y8w+a(c&{hew~s! z&m!;w5X-leo!hvi@&fm*qKexF4T06tZ7)i++jhwt=XbPr+oe_f+EDw(`O#@@_^sr{ z)p5^G`@C~7uk*_5W3>(C7i{X_dzM`Xbk5uq2MiiF?c3>#6YYRoy5hLG*mgj=0#R7g z)UZMJZ7Qi@oR@}~*Ncd&t38(XIp-16Z3ADqTzdy!$cqQZu|=Khcgw&$V?q z$66cUSl%N)RAg+)wDPV5Jns|j_BrRsqv~SRt%MkyXcwag2D+S!4Qb_K%3D#W#D+1Y zn}7UbLR`nNQ@RDujDdcnO?BZuJwYq z@Chu6oE4u&%1WQFeXPVeHiQL>q?aAF=%7UzUZ+k(azQ-hcPlc{hbGtq-nmps)Q>T{mLSW^uiFr@Dp$U3&q^>!;Bq%z{_Mt8R1MxWzkFZzXt z9EDFX4R7rs&Yg(lBesh?q`QbiiK~x1dE`El@K=Cz$x(z~0YdxPn1WgjAU{#OBN4Yj zzk1|;k?T6fs5{z&*&+M=koE_YhPUuiqFe8Ez@oTs|3 zmM^1{kBBJ#8OEUQIJId_h^v20=-$RvuA}_@(A-2XUKgTDyPOl{+lyD{sZwX-h01Ce zr*u~~UQ|k49q6<+2ADQ?T{<%IDBF3tC|kG)KSK0Ov=4R3_uKWheQ0rAWtHPU_M7dl zQvJt?j;rt7(T4AI#6`li!W5z*(LS*bnRdBxWwY%Q&ecVFcz8n$ufwFv2Y6>U{u#z& zG&=<_;_4x9wlzKRO=6BctuB2!_B%sjpi3c8K3%*x)^M(?K^c3rTNLT75n+2LDK*h< z*Co%V(rve+^C=o{$k%uS<}c)IZg^Z>?B7Q+2-&w`M85Ebqp&lVW_tskN79_3TMsyc z6C77x=-=ZA&X&ILg=MwXTcVqDj-D^zWJvRcQRE9wa9n*M=g55_;S1I-IZN<@wXEoj zvbyuD>Q7xq>k((7m`DDgM#a@979Y7!B>c7QUGgM`U)%0BJUvl^*B9fTVVvc2iQ4!+ z0#ZDxr=ps=+$juyEX+9}upbqckEA>Ib5gMl<6`oTHdt{TJ8o*jQ`+1p zL4p)gI0{CmcU-iC(-p8IMp6Yc@yg`hVuB#F)VH4HHm%RHpHD-6cOkDN z(MUNW>+T6Lp{ZeQmi^^MVc{$Uufj7zZ;5ovnsnQT4>qo_Qs!*1tTQa5JZzdU>uxZP z2NUl!VB%z$xWX}Ug=Gx3ZM@mF(L^A{oy_$fQ$BB85Cd0hpws}^{&~vLT;~d+Y-Nmarm8JS)&N2K7ij)>XVl7E!*-t zj}y!9N^u-w3aWb?I@Ai=K>wV6>^juXZ37*bMOB_|rA%Mv+IhfNk;%ub&oz&5!LG_)W4EYdKn*(|OJDV%I+%yKXza?AnvY z^~LMmKeH_o0lyg17^)h^aAj+0^?=z(I* zIBx^SIV#r-D}CbhRaI86p;mep{q`L?%}Sqyze4HRR{E?FZN?cB?1K5XeU4pwz1tH7 zlPe?HUYFm24{%<8e3^Kl7fhT+Godu``Y&B?8CTdQKH+nZV|T`NPXij`9S zv1Pnwo3`IqYsaqJe3wkaFlR5<(fO@h?3yCTG74-ADdE-nFG8+2Ig#&r{-45@JW_6+Dch%S=m+^mg>W;L80w)t+er$HP$i)*me7m z&v%bqFFVi=rt_|XJiUa$Ns8uymp|^z*@^#W4G+V;l3}G|j zc&W|n2ena~{!Q#&$80|OBN;g5Cx5-&GCnxIdhqTOV42c`kC&0+iP>hTm)V2Hbj_jJ;2hZO-iFEK81;j(OFIG+=z{p3~oPoK)K5WS2ZU zonox4yvjW%JznbVFS6cnR)3sr#9y09?RorNAlNVM`tZ1`uV;_b`udGiUwlEuKbRf6 zi)A~8z`yunnPsdxzE(e9CF5qn$@n&r6Xjsm2fuXHPP;df0!JXK1xFH2z40`Ew>}~g zjwDASk(5YkBrP&HGCMLik{?+>Z~bx(da}9q_S-~W@2zHG@9lY=(Xl|$F~5^Ks93fg z+m=9u=!_jvSI5?~kEM=bt{vOfbk>fOJRMs)t7C?zqp7nx=vDJ}yVRSfK}l!YWtyvF zYeQ%4Am?ZQIJ2`lPVjV`(ODh+T^(DObymkRPlve_N;*@gm9CC$=Gso`xJc1)VJCIm z;Of|7Ue`$-%UvDY%<@j^pa*c+Kg^m=>bOMFad9Vg^!0R5({^ec>*wj9>gbdXdUX!h zM_Ffe(5r)32X*~U+3}{UW2^ZFlyt_|>C&ui$5!*sPU@fyXcb#+ZCG+Lm6&&3(?K4&$p2v+ead@tlL+h|>FFTCZ=v%E;?|kx5R{`{EzvA>600 zgX{lxZR(&7dNDGWs}9z5%8sMaMqNqA(U^OqZo72;e28A{<@oFZ-Df-KA4g+7L(kmX zc5F2(J84H(@{glYmZQ-w^iZ?oAB#KLF7(_g>nNr1!?47{C>{~-WrQL<`}a;eAu=*@ zO)g%B6v{G;-l52>w3E_ir_C8ScVKMi{P1~89 zc5`kz?o^oSYOr=*Vu(dGOxtdVB&I0Wc?*Fuf)~h7ddr$PE6>i{zW_eztK)#j1ot%%KV~7 z9myKK1GN{=K6Je5PGpZvWL{lyMo47+B{HwB*j8VZ=}1PruIYVUvs7Pr`jL2g;%cvJ zdS4<-mB_pj=NDh(^#4Zx?TYQx=^oWXOi7d1f%@SZj(x3%U}ywjTG}bNgp@Q&EX1`{ zYc@h~eJ9W8*?(krA(D6CB$B8?lrM~yFJ3w&XL5edCRT?2ugpF6A2j< zPj{p`M^HT7ZR#9B@zb10$e?(-OVl}n;^_`h=Lm|YyE~mDD1Mm}2^kb$d6;;*ti=*-v)^IY&_Z;l>C1%Ne$Yp!D%B z|Kao>&VIVv#W{lPr#o4kV<`Tx=l6Rc<{Lt+#tYdO)>c++IlaER(f-<0)Fs`gla^G) z?CHc)MBnZpMbJavrdrz6u&JunCJk{FW&24>sv4>q5ov$q6LC1Ew4yX^wCx#&SerA* z&sn;us;bg?(fnwaMc-y+ix$>4@;8U`>uMY8>+HTX%B9ZrQSI+mt4yy1dwtBMjj_h2 z2B;CjQ#LDrqADBXW;@l#WDA{F=S!_#X>xpA+r&1gvwc+CMjv&AYr$C_)nO=Qn&|S@ zc|2-eKR3UoDpoJeo!};*4|j0oe3TRoU0YRQJN0mvL!X}aGDkyKC^S#iC?74ava;U! zK8MGlua$eMh~s#^=T|Rz9JMlG+q&xYFiMDV_y-b>TRg7PP&U=c-DAJm4%@NAEA}rv zHhpu|uhgTZhTI}~G)J44cYv?b#~5Xy9810aGRMo?b&$n*%J=HM>N+Km>U^Y}D#=q@ z6~Kj$=53Bu+kP|>bZ~II6HIjq=H-8ZM^u`C+&Qn}T&Zd-er=^i9#?HzmF!vYO^@u> z0koDi+5YKuj*EhcORHLq;Kd%3+N!XosbPaO(QD3S9)(QgZ#ge4l{Bx^tJ|P?eax%% z!GT<5r1IvW3O`ltL>_5*Ym(C}-q={}ClxiVRh4C*c7DCmA-#H` zkIr)kXIf#bsRl!CY%Pz1o;O5;xvJ}W`747ED^_%R#Zd+rrm5;Yo?@r=(RONRukDm+ zxb^qDiRv{=u2&rO8_h(bvuDKOpby7!{Wu@urC_fD>9e;?aJ}CD(bi1xZDsVWQl+xp z59)c@(f2EvfzH`J!TI(c+2fT;G1&bk7k{TM>KdZVA}+~3qY0c-oq`2?%E{~gig)PW z+93<`sF39gg+VJzE3cuUY9lalKC;7 z{PqqLFHWYFXg3ZbJPdzR7#)PE*~nMuAe;p`MF<$)3ihrq_Y!4cpEUe6CH#vgY@`e zu?yJahs9069zQJh0y}kPn#tlWVCPJL@P1%wCpri}1Q{iOgYdT?z4Q@5Z;~89kvL2< zBA$h$ah?vsKY^Sik&R!*-!m2bOZ@HWOA&7Yd-_tuyTCN0&|#V>;?Iy1B(m}U;qPe* z{ulo4&QSRYZWj_DvN%fXftqKVZ+EG;t!Zmw%cV0i5IV)5LfmznjSM;dC*} zhr5ehAMPO*0MB#v^$?}L_?}{!FTST(1x!9ihiUc{6~Jq4DDgSI^u5G+zVyAs7GL^a z;$q+xZu(y0O5jQbUk7}lf^P=){4GP=4xI1CXNa!=mnirk@M#Ku1bC@}p8#H`;HQAS z{4&IIz}G49F93V((_6d(oa@H-7H4p6nL>s z2fvT_5Af* zJ4jpzyhcfXDR6~?uLkzocaXRdxLS#)(*dvk28n&ZTa|d)3ZOTn&_VV*2)xgR64R3N zD+>M&@YfXl1K{Ts{A1vsDws}PUQ+ODz^^FyE#Nm4{Ci-peoqh|0Oz{#Cx}mhJ%2wz z90Fdh#D_yd&IuG`nkR_vz%eDhAMhpxX990m@F?KR6`TdUQ^C`LZ&2_lz;`OR5V(hn z2a8hR-U?n0Ob__bVVZ-**}z_Z8Z6cUZ?vOjd@V4|QFIW0Gw>E0O1vG|vwyI-68KUj z{(9is6ubxcD+=BRe4m2%13#ePhk+kf@Z-Q<`L*jY1w7B?XNungd+n7eJ^-dUnGVy;6rTcn^XU+A2-vI7AtIb)FV$@R5YZjj*(o*6 zA)+6!H=hj=nZUE8cG5pYi~`P8a2BvP9!JG=U}xvfG^64aV6QwwMIo>^-VGI{z+Qa~ z6U%|U@(vSc1Jjy^4$~Ya)&VcJp~SVo-uOC9YzAJb#BT@o@*gg)1TJvnhl}fhixs>F z_*4b&13p8+`+>djWVm=3nAT8qnC5WtIPiHkl=vy&ixm7ku;-7%#f!jR{f!W>0q48? z5#lZ2g$n*XuxIZG@d2<`{t@C+;IkC|Az-h5M~bi|l=>Yhx&wRlIa2fk_Qs2mA`{rN zZA&^*KRg0(<^2L5%XHpD40?=_iWmz+V5EC{6+P z=Ie=~5ZLplEKv&V`BRoy?n|E~&Ib0@KUrcOaD`jHS)vx$o6obvW?-+rCyDLAUil`8 zD}g=xCW-5TJ^Ln!J-+ml#XjIcZhn)+eqVgHc-V(?#N$3ZMLgxhQ^oT>JWad^?A6C~ z@fxsq{xn^@1)S;TKVAIZmwtx$0N5+v4DqQiex^9&!?Q#BDoxC?7sqWclzZV!98{6{i4u_RSTAzW7{G3hW$)nJ1PjIE0UcuJU11oae(KafJ^j ziQ9bG5)b)sSp2|;lf^H6I3oV)!zrR$#IX*yu9&G}h!3ZUSw7rNEc4-XvB`(Ki)(zi zhxn=w_Y}=O+)KRU!x`EXQh^5LQ4S|1)J?)Ty0;u#+vA>Q=ik>Z~| zJW6EXz9Z)dnWM!7A08v-`tVq>+=s`BdLJGyuJhpu;wwHpQ9R+pS>h!ho+SR@!;{4! zAI=tox;fU8|K*4oK0HN~`tVe-&WERo?LItR-0H(K#KS&3Q#|d%v&64`_$2WcAD%4^ z`S2Xk!x>CqcE~(gjPT)8#7rNaD^~b$t~k$!^TZAx&ew2(hUaUzP{Ru}T%_TJ8ZOrG zA`O>lc(H~{HGHau%QSqNhL>n~sfNonyiCK(HGH~;S7`VQ4X@PjnHpZD;j=V+wuV=0 zc#Vc*8eXg63Jq6kxJtw8G`wEJ8#G+4;d3;6u7+zgyivoo8m`muCJmpb;d%`>Xt+_s zO&Z>;;qx`TMZ*_pc&mml)bKV9U!>vf8opS=J2ZTWhA$P@`uhK68ope^S7`W34PT|< zof^Jc!@D$mjfSt)@O2u#Uc)zN_(l!iq~YBf{*s1o*6^1#yhp>gXn3!NZ`JT^8oph_ zcWC%d4e!(NT^hby!}n+d1sn?5{G_~Vl_zNO)?hLbfM(Qt}}Q#G8X;cgmE z*Kl_Y_t0=p4foP;hK74|4i`?V>|z; z;#0;8C4YvnsGvCLo{S9KPa0)R_t0jTNn#S?VG<{cxs2(WeTF$flrpA!pfb!8#cIZH zN<2t3F$R=((qGJYfQ*ldn;F~ojTZ+QpCscW;wi?p5|0)?XH3`VGtBPd4~*#^i45G| zi7JqXt?y*f%ZE=ACo(=!^1F#CzW6DkfU)gglf-hyQOUPN1!KGXBgIz6%Vc~HaV_Ih zC7vtxGp2j&GR%SETRuEZJkOY}(P!ZPuD2N5%9!pk$}q=@5OoY3+4z@XP8NL_ z+vV*ihB2o5x-)Qp;Yp065{E?*;~5gCh*gZ&Njyu?<#+2-A?UJgpEpf;F9c!of5PMk zghw(yQaDMt`-lllEEKBh^CO@V4ejSV_cOgC%J4m0d|MTKgSbuIC`af^H zULSK=e_k8<=Wsmb6I4FEz7{fnQ5$^S-ox=fZ++=}JwH8OFCX~@wI@wWR9@-_glT*r zT*SDT@!|B963-N370Yv2(s)kcdVadSGCl4Yk?A32dPtcbQqNycuj|i6zEmC>AE-Q^ z*B^BKN1Fa{_8;x|Bh`1b%iE9JgXXWG{-xXdd9iMk~p ziBnjnvP@&yjb%E^?kw@(kWAN;WiOT)EPJ!;!?G_+JYXc#^=CPN2(5|BJ&fKsfuyc`VNWkNo8xKVH zy^zvgNNF!*GNp&?#*&^Da`pU&^=xB3@PDZX@^rEb@=TWFC_V5bmh_B}tLG5wxrp_k z|42QMvYe2zoRAYJJtVy)gX9cVPYdhW&U(=Qq#nqXWC!HgEPGRW-~lW%RXxJA+Zhj< z$@WD5m3kmoQ+mh>mg6Zs@JTG`Eg6L8tNIMqw}bUz9FY1Tr9F^qNgw1`N)I`c<;g7R znJKrvOxAY^>%({=^+C#dhm`dWc@w3F+{5w?RZocZT*`Vd9!Wir(k@787bLw}BLqqH zO_J<#?ZE?P)qtVPSdYniAlFd2AS+o;r1Zd2A0(C2)nl=q%UKV`Lun7Btar!?(gP{$ z9da`1gPgAF3A3InSWgn`fs}e6r5?zslpc~EJSR!*=h_43m*v6(hSCo(9!q;5r9VQ- z@cex=Qr}gq597Mj2U$hsf~;m)M(Kg+SvQiEEYDH(rLex8tPk^p z)CXBfdLTEjET#0o^nwVIYgukk_2EfxY2VeX5A%%F2PySIN_~)fDLv%sU6adb_h;Jdi5= z2lKMj3n|AnNa;tAa-4-k5k&~nH_rB8J=e1y%FyovQ-T_W{B%6)2?W#T)E%kkg^^hL(2Ib@@B>dSbmS?%PeKS;Qbod&95Kl_hrrx>pPhrq|6Ue<_9VD zLdx<${*?4W{)Xj8EJGnXJi@X&q?=!V&TkLrhjpaP4^q|}q^vhc*^eN7<0PC`*844- z9_vq;9#Yx~Df=a)oOdB})$-y2W|@93r^mWgriYY%1u6Xsat@UTlEw?yemJR2e=DaS z!091n{*W?%$Wtjj7MSXQh0PGEhvvA%(<4^pnPAY;R)i;>+ z-Ol<3u|7yyK1f+UNNEpbJ?ViwpXEiWz7tvB9jxyJ)(0u=f|TPmWDcc=%wt)|lEy{1 z{;-&m^>-)h8_fD3WqBc`UdTHsJ>-Kdzrm9H&((*)Nb1|i`c7nhkaFCIlzs)dp3*~Z zW_ck?>hG?;DC@h6^<}a?$kVAEAkSne*9X9~{-W?AmNcKb`i8Q;yIJ25)(0u|K&~cz zkaH)i;dw-NX8#tPfJQFQjZ=$c2<1as|t?SW>&Y_6=u!UtxViSs$dd z3sU+sB!(stf~0YpB&y2OgULX)!&h0)FxCTk29*!;ES8HYJ@6`)F_zRmu3aNp-@UAF zIO~Iy`XHq~Nb27qNZH>Y%Neg!^^IbE_p!batPgS(*##-<4^q}U)X%zMzTIgsSi@>gOvRMavAA^B)dqiQT2^sefP7zQLGPA`U#|L4@fkb2tmsJ204TA z$*Mk_EXeja!1_kBK1gX7WF?gw5<{|-7&@eci+SyU$zAF>$a==G9>^G_hpb|Wp;cl! zU!rhYAGqy_MY+`THP$nh^+3w075vU_B48o^h-PQr0`9EFYv? zUqE8279mLTTi2e6tmi@2GoJN8NId>9 zvIA1~b4cHL;3U@bFzcDfdLX60LrQ;#r1e$^au&-|SQbFK<(tgv57MCYkYSeHR6Q8Pr9IzdJvpogQtE+} zdLX49NT~KiAk(w@gy&s5d}xq|8iQu-%k zGL;9C>>x?~#jPI<3R2JGtY;eQft2k9xq*9xIs9Uh2)~=d zALa1JIs6wK{s#{K6NgLxp?aWtr+Od>J+dDoyo|%kIlPf1!ms4;T^xRp!@tYnPjmRI z9R7O_f1ktu!{I$>U53_#~2;=`@9A*4A&h?=T+D z_+7>r{G|ThGaktpgO{uytTSc&dyGdj{v+ctjNfNGmN5oBnI7venf}j=$20y5W2}c{ z{0EG&zLEGt##xL%VvKc#jQ^N1)(H~-l`-afiT{sr4&%Qup2GMO#+W}P|5L`(82_E| zbiST5%Md-ezsu`BCox8Umv}Z~^mmEpFh+lu_+-ZD?-HNF82w%1xs1`@CC+7x{w{GI zWAt~4=P^cqmpGp>`n$vhjM3jEp3fNlUE)H<=zmcZnA=Mt_&Mm@)dh z#ETfCze`-g82w%1#f;J4B`#%*{x0#UjM3jEE@O=TF7auM(cdLr!WjKs;-!qy-z6?* zjQ%e1GREld5-(?r{w^^ld)dC|?-H+IjQ%e18H~~2C0@xG{axZS8Kb{TyoxdUyToTP zMt_(1Y{uyC60c^A{x0zv#^~=7#~7o(OT3mb`n$vxjM3jEu4Ihp+AT-0btAc0^=Fc*r5ii&u{ii&sIYD+;BFSXu9rIu3LQZFsmOR2SrcUra8sx8X< zo1K~6XJ_|J=F|U+eLwwo`Ed5kJl}n0=GkXv=h^I;g;SbAGv$@kGqH8xO@1EyN92+d-#XDhhMmR_=CHLAGmv*e@xTU zZIx4;=GrOw6Hht5UVr7opoxPj9L7IW?q`AfS?GQi`LO%y2Tm2ck`ni`)cqXgemePL zCv-VNnIp70LY-425TU{mIvk;WEVL90EyY4hvCvX1v=j?1#X?K5&{8b4 zln5;)LQ9FzQX;gJ2rVT-ONr1@BD9nUEhR!rsnAj?w3G@hr9w-o&{8V2lnO1SLQAR8 zQYy5J5?V$HEu(~%Q9{cop=FfNGD>I}CA5qZT1E*iPQFm%@45 zz1op(?MT0Nq+>hMvmNQ$j`VFuI=53G+biAMk^b#S2X~~0JJQ7+>En)caz}c(Bi-DQ ze(n@X`$HLoLen+~$BmLiz9l()2z>!_Rk$u3CoxqX3z>(d+k^R7t9l?=3!I53T zk$u6Doxzd4!I9m;k^RAu9m0`4!jWCVk$u9Eox+j5!jav=k^RDv9mA15!;xLXk$uCF zox_p6!;#&?k^KYj3v|cal>nxFKT@)Pq-6g{$^Ma&{Uas&M@sgOlAO-Tg_a1q<;rAR-k$Bw$UOM5v0f|cFn>4~%QLua+ zgn9*mUni6bQbWeI0C`FW~f?Y%4BG5UK}MxevDwv8Uq+Sbz0gf2U;uC{%Cbwg8qv-;lH z(1c-K<@G)K_YHDj+>XxWf+qsMDT2%tt)YqDpnx^@_WN~|K6Lhqy*YJ5xD!dUF z9n}K2XSlshUWqh^KrZY?hAfex4u=n`VNX-adzE07Pa`Eg#PvAkCNf(&Ig-Iq2N~XZ zY2qqzeUV*99!k0b6=M)|uW-oI&j+$p3-InRQj@St0*x4Dkn4{JNGMkd(qb6qT~Xw_ z?uW18DC8VbsDWiYC@siJwU z7SuptBNIcX96xqJ;&v^O#oCamubb}0C;#f^i6>uMwBaByo zQtrz%1;GOTJ2?&vZGOKA8`K;4qD1P76qex}{daQA1MSgrNK@mZXDaT}WJVB`|KG_m zY!sXeqaOz|)QrZnAH80NGym5o$AOvdzc5p_m>gGES5B#}ZEt9tS6$PFnR#t{8=peA zp1Y{6rk0IpscRJN)UQ`zfw-aL5mI1tj5#kuDZ96?I|O zrRrKjYvEmj(jBBvi*%);NOjd9HWX6@QD(GQ&k%n%a-dk+>PUcUcklhAD_Y$Dp;F!? z@vh@gk^a;=y(q#Bcx{6*Pw4Q-bIy-Td(!FUk5-=_L;{vjNq#gCB?{ap($%Wl2Hwmi z0+5kYlYFSTmnrL)%*1YiR2N`7Pa(2od@Gxdr~8KgYngLb3Bc)pHGe zjU$~~<55D!ll=K?%56jX+gu#xd;=Y$y=O$^~GH~M*BxO7~TYgvVcsvb< z=r~aBKfsl71#&~u-7dx_|E~1$=d9a=$o*8@cQoz+a7_{1BN~^)bIuzgIQ|?uEtkKm zabX0vTjTQa-16uMjw_@37J@5|;P9wffV&;shzJgkI0d-pz}*$W;nAW1$DfCOHiE;W zHvw)O49=gmR~y9cc8$i3hC||UH*Zs4@6)*1SZ`>vM~Sj{@&%3K@3h(#!F`}{Z-9%d z!oaJq{P!9ByYiPeyD)ZiguZ?nmy5-Y_%ozxQ~C-ut`yuL1!1o^{`)~%ZWXw}5gh;B z9OW(s_oz}r^exr6(OntCV`|=}zTT*DOS|D6xJpR$J*aW7VC_9T_U>)!kY8!s3wWRs zkGp!C;@;G_9Xl_v(drB!I++`YfG#2-|KZ0AYaj${f8NofNara^|rzpRFS>vw6Vqzah z==(t9mi1-q&Im4sae|vc^^buEM~@r*G;RmDsD4zcaeoIFWtXWMx8V@xzQ0{nQJot8 z`w?2d(+_3r6$N3hxMdob!UgZa2<|$Kdk0)?1h+}!%KJsP_h%Z{l7@RzDUWGMd|@afNBP$2IP(G~DwVcR9GI_P(WY4}$wH^Ec(E8R%%Vy{8Uf45+s$ zE>Ch8R^6=)+~XdFYn}W)RB}o*VjyGdQ5StH)wtgriFakI!U(K$#~p=tT&uzi-0q=_ z@!zoNo38I_OkUjIHfo^GeGeA}{0uX+>D&{>^2K-LOo+|Sa1Uym{^-eYq0KDU!9F* zx-nPLH=WCAw)4M6EC4gkqJEoOv2Lja_m_6OL)wCywUn{uw*d=;nk=D6mpTydt7Tlk} z!4*QAuJ6*P7`r({h0E>tH0Dhf++&v9jIDO{`w|?DlT{V;cHHq3J8sG|j6r2+)Ae=! zDP!m&p-t!R2X{+|3fphWHaqT3a2Se0n_lknpE35m5EU->(Cv(U--3G*+(Q;z%g=*x zk2*xJ->_#HyF&@dUgv%d&gT5K{~~yQQmNGS4fv&N&<4f6 z<8OlZ!_w(H=(mhvC<<+Qxi5jU@zW)^Nod3MdCAT$zX69!S7_7gcggR9_s!G+I#&W` zu^I1wZ^>Qwik;v0f%Dne0T+3T_`nv44 z7iL4UTZ-vUc+vnBVjC0F?6B!%PhIeEx8?*T#t|K z>Q`yW-E7J2vgDGV*wt^IC3h#dX%^SFFD&(q{i|L5R#8}gZ5{TeN~`z^UoExFRa+tqJ*8tzPOUbhw8NaFYEtImA{Zh;b# zz0S@0Jor4ELUryZmfX-U?DXAW$?XHzs47MFdi~D+(yrW>EV<+UVOQ?mmRz5I+STtO zOYTE(Hg=h{*N*!sxP`>N>Z@+&;a}NtH(7GAukG}mZOOf4$sM=PuG~$QTrWHwVq?Ga z!P%U*_bv5JkJ**`q$PJG9>%n3$F-K+KfzTgXCiyuuV!V~aX+@?y5r`ljh)Z4%OKwcIoxUG}v$0Fh&UX6F181Y}T}yqZ zbg?V<2}|yX96Np2SaM&2vuST#u3fp$gR{{$rmG#d5uA;m_UvZIooC6tZONV7-LBln zEV;vb*y+0(oQ<8o1V``dsUh`jZJu~cPw}orC0F|;8n*#lQVGdk=eApN?^tqK2iTQ6 z*pi!U$<+T)ic?%97h)$!)jf-m&DedRyAhlACPF z)mw6_EV&Jq+;&Uu9ZN3jKuh~sa+58&dP{DVCAYzn+iuCdW65P5WNAN3Zn7m;Z^^B) ze z+y+Z-yCwIIC6|SF4OrRFlACPF)u-Vu)#i1pz#T#6bLy+k-3@M#5|X{nJ#VS+Q*eh9 zJ?g8jug@WN<&FV2SScZUU0)5jp+v5}>fCB@M=K%O>)gZOY})avr9S>n&S9iH^;Iu- zBsiOPoNmco3T}uhjO_Jt?*Zo!x%#SeuY=21LbBJnZg{tb4RL+!Mk5<$}I*rTqz-YUEf@AHs!7cXXEz| zgR>g1z}cKP{z5*R_6`GQbKYiwv$-BEx8&{sXEUz-!jk(0oQ+-j4zROJ88{n1I0u|f zxi^EeY427`?mcie=dIU3yYp5GZUFIj^;P%#)4)U8q?z5KM``~Q+ zwAN|62C;Nm2`72IN62*=^z$E2VKB=hxVtp&4RHBV zUmoFhXk3q(F*Z(e{RsE2#!Vw!f5OGlS%7-m8gNOZcsta%k5k45Xx#mTQ}Z3p9jkFK z5Khg@Id_)EeM~qt?sM)!jq5SXuis$E`Np|*8kbMFBV9^xk89jC!VMwZiyF6>a7Pht zkH)Pb+|h*N>mgA)-w#gtv%3ECb_~_Htwf)?UURNYaqbh1TR}K=9p+pv z25V~PHH0hV%CK>6h{oMcxFVMlT$#q*Pq<>j&DFTA;F6GYJC_h{xyHRg^pz6sT8;ad z=o>}2A8A~V(|kLRCfv_8E=jmCgxjTY`GgxwxKA{09N~^3To+sv>G_yOxMK-7P~+x+ zOG3`=cO2m+YupN=Zye#~g2O!JLYc+ZfTQ)``P>iMG=1y9@qAwHN)BO*;?@)HQh`Ns zn+dndz&%K~%M9EW!d-6Qwh`_M1Gj^4R~opTguBYX?IPT21Gk%SR~xuJg!{IE`;>6k z7`VNJTVvodPxt-cS_79$xa$mDZ^B(~;PME!*1!!S+zke97~yU-aD{}s$-s>z+|35A zjBvLYxC+AEYTzmfcbkE$BHTIyH;-`NF>sB9`>ug&Bi#24+;YO*Zs1lD?hXUDnsDDY zaBB(o0|U2?aO(}+dcytCz-=bn1_SpX;Wiq$Erh$%z-=SkCIh#FaCaHForJsF!0jU3 zW&^jIaQ7IvJ%qd0znLytDjrD-7H`!c8@B zn+bQ4f%}wjCmXo2)qeeWyZIJnzm?#WT}}~LB)5}rry96Hb9{Z%4O|=HDh=E=!p$&n zy=#0wooV122{+5YZ3CzLnfDXEMcFU6*5^(WSR_|TxYG^XI>Mb{;C6#k=dH@X70&g! zGY#BIaB4g_%fRgdw-|EXkE#t^#XO&zW8k)c8wWYpS7YGz60X+3jji+b%{6e#!72OA zGjKZyS7+ez>V19n2Ck8C^9|eub!nGN=2MO11 z;Pw)3iGeFS+ppiZ4BTqMEj4gE!Kw3hu7MlW=$E_9z%_zX`pz?OTZq2p1}<}vU+(z^ zu7YqE7`U~BQ#akB{Aw5BRv7dRYVzBAk%4OiR}MKJCod-4T5bNf1>6g9!A&6C4>fM} zIsX0AZ3b=~;eKY|HWO~Uf!jj3pBuOxgnQP&?IPSS4BQ^V{nEhgCETwJTyBeRza0iH zk8r;>aKi}qoPirlxaSRA1>s&Wa8-nR(ZDql?l%T*IpKb5;8qiEr-55XxR(svX2Si> zz-=Mi%LZ--;a)Lty9oEHf!jm4*9_cV!u{UB<+l3%x68og5$+ELZW!TSH*jMK_eTR) zLAW;zTovK|WZ)VJ_ojhcPPn%W+-kz@HgM|*_qKuCOt^Op+!n&UYv6Ve?mYvyi*WB7 zxIKjXz`*S#+=m7(x6SvzJq9k1aDO&%!wB~m12>j%9~rm`!hLMustEUqfomk(Uk%)H z!u`#_ttQ;325ueUJ~MEe3HNscw}o(@8@L^W`@+EOBHWh-ZV%!9Vc_->?wOu`J_A=lIEFbJ-}pRHpNCZuE@t2w2^S~a!`i%VIpHQ5xYdN4 zY~a=r?sx;YnQ-L>ZVTb27`PpTJHf#1BHW1vZV%xq4BTGAO*L@2OML%3$-w0i?qmZu zjBwKo+*rb$V&EzWcdCJ_BHVNX*GRZZ1Gk)TGYs5n!p$^r>j;NOf834tBi-*e6Aq7% zq~*2{4u2v~%k3Z>{*;uK+eJ9sQcuh6AslXPr{(q%4!5Gya=G8~{SUW<({g!)!!6vj z+%Ur7mTOvWEa7mAG%Z&_INYjC%T*B$w-(cKjfBIkz_i?Q!r|6kT5dJraH}mXw~lbQ z<&~D(OgP-4O3Q5_9BwJ4<#rGbw|3HUy9kF{F=@Fygu|_qwA^08;TA?(E_bQ#f4Jq4 zmdhhtvw<5%xWxu;Ea4EUr!BXFa0sc=a#e)G)Hf~HNH|PU(sIiQhf7IXZZ+Z1<6qJZU^C(8Ms}9JI}!FA>48Ux0i6|8@OClz6V;#?}uGr;PMD} zp@ADlxD^I&Ea5IPa215R*uYg0?h?ZNLYvn$g5%dc-rki4u8nY)8o1?zTV>!@67Dhs zx0-O58@RQEyTZV&Bixk+Zav|yGH{y-x7xrxNVuyF+!n%p+rVuj+%*Pn2jSKjxSfQ% z*1+u|+;s+SH{q@~aC->1*1&yAxEl=IUc%jI;4(4zD8IkSz~vI|W&_uoaJLw^Ji^^- z;06)yHUl?|aO(_QA>qDb;KmZ}y9Ta|aNjd<6@4G8MwWKd)UBbVp65X zzefyQF5woln1Rb9+~Wpr5aFIMaKi|<#lRI3?nwhTmT*rQxH7^$ZQv>hx7EN^ z67DAku8MHa5bh6{*CojBHRgdkL`>HMpC5tCKu%KTUI4D;fB?d{+RruaV@z6N-NM|G zx|Y_4=B5$NwF^fku{k9r1^KCxe5W9p%;y<_&t$T2R6((uot)FtXsE)C# z-Lh3FTV;8LZf%FKek_k|8ZzgWircc>H3BkSF!Sw!mppRMkmue_BI#yvjTuXt8|E?h zC(sh>IeY!9zq`0}X#k7YHa9o2Slsno31X~;CH`UEc&RtN`!eUwO zZ@(n})zX9haLJGQ3=i_{O@Sk_-Cw=SBUY@qu5r-XlfDQZ@hz^qx{bxN+?8S^yZOL< z%ba_rJrrbH7c{rDu~@=gBSeywTYf$2_b1&kH%NN*kcV_~m-mo|-16B~8ADIMe^&62 zh9+0_aHf9xoH_4+hYmh$&YNEaIZw5FKqqSKCFS?s{oM4PCk78_Y;Ky*;t6WJAJ%kx zz4ZNwJA9>RXpSbhey8=hVs;k>ki-HvFmlvO?w6c_c+~Z?jetq0C zO-BTe^Nu<&W3tlhE>s~cRJbf>-rR;K4-Om^=haHOb<0e+KVz5l?gO9PHnePH=O7(u zjXbOqJ;!%nI$_$+|8nQz;9>QR%{B0bOm|%cS-=&Go>}5tcV$tKoY&l5+gQgkGpQRN zbIqIEezt4R=Rwr1xz8Viz9Ln}MlNVxR5!A{wyC|fu4QCf!^oDp#m%iF=ce-W^S@Qo zQYX{(snUXyrSp(#tgC6Qt6qHe{E_oo8ZZzvHq?$(Qa?wH5aOx1_&YFL_Fl1hyz9^s6r zsGJVL;&WRX<}YYV4w-vY(it_Xcz7z`DNR<^Ev;!yPHAdwYiVCp*VM+p&uwm5+}u*r zRyU8uKK-T*$guG<_Mc|R_~)?XOmQ`-o?q8i(NHT>yv1&lV=+f{;%IO``Ihg&g|Q1V z_|=o)TEy$r8=w3Nwy!JS@#_xH;QwQ5@tMi^BW_$UHVEwZilSJ|2k^WWK4Zrw65SH9 zXR_kBgvUCpINsliqxNCTL<2HohvfEV*;(10va_>0XLrfY$($0x zveyN-vhmo*da{h{9({V{9GZPZ_EqC@+^iVS>KQvAMzZ50VzFKs**tet&gh&mImaD5 zCE1j{YFzeZ<8m$^m$P;ppM_k0QH=GBT`}%puIC`A7VMNHI>8_$b8?PF5gB9f6(%1a z>(S>3cjE9(jRAS6muqR)Ns+)N##Hfr2zElw2Mhkk$!PE8^mu-HDyQ&v;>?Y2ZLM2` zk-ddw_vz9pH+~>8=cY=R*3>qzSZ5?MV_DqWw2fwE#y^2``dbE^pqHOy8S!{vov{pD zZ$<{>2{tB>&eGDIv~)I8zrWyzWyCwP%E0kmSZyGkp~-WYdj3`%-&K?6GWDFNkauHO z1oUbT{w&HyWrj1e2>I<4#ADw{9Kvei821{F6Z0jejYfU z=6{Rf`@hQl7xZ|zUti9{AGvd6-~R=AC*D8_`y`v`u`Dj_&0n=DD+!hNk*vCcif}G}Wo^^({4v zyhKfHZA;w}C2Bi&ab2rQU_PS0*0j_#&G#jXF@uAS)^wwcbrl2U{R{QAsA6?><&^5$ z_J+oJ)irHxEe*BpZM-3^=PqiisbwQ7r|_?}&5a{!8XIaLz??H+Ge0fr=ci@m{S0YX zKf^PdpXHg(ExB%P8;@-38*AqCI<>X9b!uH8zom1Ba6b1P{-666-wMUf`&7P#;U>hv zg}qI2hf7Wg#^THI@Lhf5KCO=7vP;0Y(n7S_aQi5hQ8@s0ZztH9YT68{?q!M z1+F22Ytp!%gG)wm=WE=%;P^PDZ&xD&r*yH(?}c%!Kqbij2l$R*(c8+wB~jr+k<(M= z^6~C&{Ku(MKR;j#aD4lo) zbYo^S|2FByvTm`Xj^D>_J8aE_{sWgxTCp*E#j***H&#trkr5v=bH+ZN-uB#%=Qs4v zh?iZlv1-iB)Aw!2y8D-R{c2nPLzb-iI?G!3gyBNthW^QYY}ur)o35NRdqbAe&8}g~ z%C7LWul;|}J}yH0xHQ@)-PpC6#V7PXxH*o`gPJq(*~`u8(L8Af+qdcRPii)-K#gM? zyMI)(;c|S7Z|MH#nva@e@eTbaUAJ$|rr{g1#>^~3tCHtV=(Ood_7r=#%x%}~ees&u z!yB*1=TjT56Sm^zWxM5dam&m7m&@aJ6eVtZhUVY!LeEi|W;AyoAQ`ES+P6 zlxZ+VIV=%>yCbOjc>bOc*qth`*}~Crunb&EY0z8HxCNozw|% zYl12SYf^!+KM{Xlr>2~Q^Tm&JaQ8bA|3H^dteD^yQOM#Df2fO5zlm=BG9cX(l%_-# zu=9{LA!u|O~{BOEg8YG2aG7m-i$VSmT@Hh|Mu&$${7+ph4N`z8I}zU-lopFBz%IT) zaue~dI-;aOfPSr`(jce|r2Dc0eWJLU8>CPe1Y(@vfV@Pn4lL3w5s!s1&m@KTTUa6< z4*|+1a1zKfLUL)8LWH7;IBwnqs!=Mcf%D^ArAGqeXGfSc3)rj>ixMY@fdt}CAu%^h zkuVJ8*_wQmULzRhfJD4=2=fe6#9{!tga8=Ebx52a$a6w+RI^NsClKcb#f}_Z;WfTt zdMDytJH(`6z;+9<(l8iOAnqO#bHfx1!$96clgm-ouMrG$P$J$lgn5Q3#x1=>{D2Uk z3@dG==q+!4w6k?@eFtkA2M-$7@)GrYYKO_5g%n{NTGm7YcO{tUm*%THW43#5S`!kmtn=SXFm9};Nsu)4ulmM zVj|#%Bvad$PHb+fZ;&lsUR{Dw82kW+KQRn>vjY)? zRfGv#5l9#|H4LDdejs*|E|(Jo?6^O`COF|IcK}JFfSeX4rBy^Ac1l>z&Ekh*r|N*5 zKFIpOE^xT%VaT(Kh{YCZ%0O zJa$@G&h6qyWT)#uFeZat(9g~YL!MnkNLCdlU>6dUof!tCT|`)RmM#wlX7Cqu@9GX9 zX%~=l!lbl|2+L~1a&8wtFss#pU}OfnV04)qhCI87xNKgSP9>I1sy=L%^)ufld{bsBwG=dYcbhHIuQ)Y zU=;*S7l$EX6%mqM5*90~z!Px%$}k|UB7(9@b$L`&wyFb&Tg4B{F4O6#xa@KriVDoG z=l~++A~L&Dr=vo%t28JwHe1~RM9M{QcC}7NMQ7jEp{VfenhqdRF5RE)M(hoXYC8#;hUxrowk)aj@&?Ish%oK(keJ)UkJ6sdhM+InG&5X1M zdi+m9ptOew&z=d1xjp>o?5CPMDmdE~Vmy0@*z9K^K-oitX4^w@X%7*Z{ah1A1!m8h z8EFs1Wxoi4D9aDaei;&Td-ze=uQYj7P_`q)c=ix6*{?$Y>_I}Z=R$JS(T~WU4~ioL zvKP#Zv#YzYtRaH0-65&6hKRl14#}l8MCkR7CXR}{ z-ZeAa8h+sQo(4z7UGHm5RM_=_nIVND>iSTFqk^tIK_)Wh`m>oKg(Bqoiv~wUTpwvn zRKWGInIVND-ugs?qr$DfYD`qL^*1v^3PrH>sRl>ITAyi5RH*fLGeZhRr1iN5M+I76 zXiQX`^`)61g(A%QhXzMQS^o?&kwMm8GeZhRjP;cUM}=5lBgEoQe#^gyRebhI-L4-z zcS0ak5Fr-2KaH^V#Z*|qevF6tO#9y~tEgt~g#i z(1I%yzweJ*LU@YAh?MiE^SVVNa*|%b|G3lLh?MgO^?F1j@^26oe5T*ih?KJgo*;=v zF!YNSAsp;wM9NtwJV+9aV9XX;FnK=Eh?KL=cy=Tjkx#``@UXLw5h-Umcy=Tj@or{f z;(D+VDQ8{r3`sO1pU9}-;q9SDq?~ofGbGW7^cOt+QNi#0_v?r%XFc%{Ni-$B#?^(p z_J?&um9t)WkR+OtzT@h`{B1x-R5?2kkCjAI(t})GxaEC#M^riMgXc@4Dd|V9F3h8j z=!hz32jkI_Xo@~#h1=Rkc0`r4L-ABeG$nn?trw;|M|DJ%vwnE8B$}en`ryX!(2l5b zb{HNiiHm3X{PD>BhUca+%;ZN45m!U#L<=z!g)kK@#JmW?f@on8emsgtHKK*Zc#a#- zXoQ4fx;CC=L0X(fI)Qb9v?L_OXfE%IWJ6w>R$jz9Lp~}>F5~7dkdIC)FJd{6kBO4Y zxGER&v1#Q+tSjWlM9JmUyc^`lrj-}5?vNiBlJj6m+yev{Kg1G}BpA?q+kH8%SU~&k6bBJ4SeIPzQojAq%LR_9s zT)+;7cuG2PAv*-(6QaZ-a6c5{6Vr)PEDz#}bm9Wm58|om#D%Os#3x0G#SOi~AU-*r z7%P!ro-jR~7xu1qIJ5C-v#D6za50P)OpV%#@|cvd=b0j5ECsv(^izt4d9w2+uS zZdk!OfjQmCl(TFwXQW|pU38yB>_$pLegktt`nV5-wFxE{KC zx`LTwWXf4LFf|bje-sRJ2UkybFttXeob>=RHw~lg(-X`*BU6qaz2g~&G>o!OFEI5+ zrkwQ#Gd~TZ>~kQP1xBWv9R#KUzd#)2Py1hGKY8o=8=HbZDiYKFDNXoc&Sd=R77xHJ zjH~&5x)q-=(Z|&j|GOAheDbhF2P;1LU|{{Gv@1UOytmAcSR*R!ickI#9k2N0vmLGY ztCLHsQ*vgU9h@ncSle%p9*Yr(0jjD=i^bi%Pq`ln;9C5J#k4U&=c|Hbks1 zmC@n)QvPxN`cj!4t}o>sr0LB zdAdxR&wF)Oon|!pvUI8awIY@Kd)c|D87|5DX(gV2*K$jxx*u>Z^-N5(a|MnIx)wPwstQ{ zOA-b~ufRQYZe!tDE0t#ju?QTIH_Vz z?pyNOMy`v?U2tkm>)G^bd0zPNM2XwP;&0rO{v)Saqm(Dj#d5MOo-es3<_(U;UUR)i z6YpQo`D#CTj+jC5H6D#?hknNe+TGU2SeI{P?NBnX;*8>nFCe_sWEkH7sT@)Mm0V2#re<$d2z#QOXntKrHRt>M9b4L1dB*#F;W z!+UuRrzN_MID!9jPDms&77dMeAG|LSi}&az%=v$&vahA7Y`ilT|5-08`$yNZzmwfZ zTbp-(4jc<)`Fd+=M?)uSKs1GafcuCxm%<$HhPVn=c=_PY`GT|>ZoizkY%jPANnocAMHQ8>` zE2J|?LfSFPMvA6E_g~H{RRT_OHl!FI8LA@wEJ-0gCeZZGg$R z4Xk3+s5@{&JeuE+qIB?H2`~LfkJU8?qF;{smEeJ*r#2#V;q+kq7ggrLfJbXnRZi}= zb-lZA?bza&m+`euySgcn<_o6#@(gxZK%U|LJ;j%2x@(*I$7eD;mg23ei9bIx9`|5< zPfQwaW|em0pGfl^eOn>pQLBwJAXk3-#A~5eUY0I>3V$6@X}dq z5x)E7XR$V<{qnQec}V-^XR(Ws_RG(5*9rH_&thvJR~ug!{YI6*p0A7kU?82rUI?T! z*@uC20?)1Z85wws%i)1^wwCU!rMqb994(!zrMt3`0sY;ybayS?LreG6(g$eiURt_0 z<13k{Edz_u2h#^>={{Pzua-WTl?U`4!e$22oizEOS~^cl_tVn-we(?ZZb1J4O`c>; z0r@~JeYln$q@|D0(u3Lg0ewem=^c++Z2&FzC4i{|LUv{}W_>mCTF z@5}su%KWY@?~yl*@A3awnLk11&y)E}Wd1Ulf2+*jEc5S|`9GEUFUkB@W&UR} zzf*}QH;3<0?r^?`>^PY}QRdH;`Ry|QT$z8Z%>RMR-zf8+mHDs9{MTjvUuAw~sVFy_ z?@?|)zDKzuWqyIopDOdKW&T{5&mU08I7+_Hp^sQMJ>zJZ?km$nWg7k8Nv%tJEzdmpGEFxvHMx#ewMnQqufs{=H(tNj&{W1jyT>C z3LK%q5h@&^!x2gxp(T|cc;!X98N2(=iP1_LoS_G0ff+dwMa;m7RGV>sbMM%QZj#Ck zG{();D(dD%G)*Z8MLuqu<@-g_LBuZj^Zhqv?Ek(kAbnN@H(ulZl7{1D&~ht~SRA2mna1&Vvqsf#t>l!7zL*c4i?Lka z?mz}FS8dmhmUB;)A@@4>{1`dM>wrrgE9a6Oa95AB)A#WNIXCP;-{?tl4ybYWAWhrb zc06MPG=?X2?gnt&2KuIR#pR5BUx$#^xmPT?WmCklx=LN&ktf)3JHfrBD?|D*{HJz# z^hC_X38(H|>D*pRZd`?(zLl2TvuU{PT03&5Vopukp}y+eVc=*#O2?gN$-QjJ6`T|t zH`0}REjXL{{TUqZ`}(#M8T9;KbaM2&bok$RDE9%lq^=BUo$E5qjyu|tJHe7$n1L<<$47CO6RrzbzD04*5-vwzkzDpHzua5{S5CODgqy0h_i}LMa3J0eKDXf;uisf3 z_rmGIKR9yG7|^XZYpv^TM|%t_R@|4!RrXnzeQ$2{+Kd zjQ{`u literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib.lib b/gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib.lib new file mode 100644 index 0000000000000000000000000000000000000000..62fb82036e184869d2ec9cad6588082d84765bf4 GIT binary patch literal 698 zcma)4%}T>S5T4yuEm6diJqfAwpdOkuX`3FTP{BZ;=%x20+a`1&T1nF4%_1K45qt%o zL3{|G$Jw;2TNLWR?0oZ+nQw;F&ck#x>1l?cuZgL6ORT=S-tNePKpUrg9;FFq{%9J< z4Fp2@Z9FxUTof|Co-@=T*skd~wrM%0jd69FENj}W)zCou00N)AH+~0F7UZ>nWf?$w zhUzN5ga-&JsQpuXh8~b(v|Ifwi*8sFrBJDAJ9~6N=_932l)h7Xhy`^vuFA_Ha3H2_e{bDFj|{ryqGa!hBY literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib_coff.lib b/gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib_coff.lib new file mode 100644 index 0000000000000000000000000000000000000000..861e1b2354ecd85666e1aa5d5fdeb02b1d4ba299 GIT binary patch literal 375766 zcmeEv31A$>m3H-vW;D7zk}<|1W-tZ}2CTy;5Ukr4NY;2H%MJm?V`(faNE$JcY-0=v zW5D4w<_Lk1HDGLyO|pR;n+pQOz><)JB;?v9A<3U*caz->o8(V+m;C7eULD=9r$@Gv zKa<@*yJf5Ut5>h9URS-UuJg^Q7beoZn=UF|5OKR|=2e(qBay{5OO`5@^~FMnp9wK@ zqx7VZt;@{sq>YsJyG?DXf?Y{}@{XX?~`!m9# zzrQ%*{C(;p!aCl+fBmJfj`HU_xmry5*Yd3J9naq_dxS5KfBre^#qagEexdLm>+h~} zgrEK%`{wWe_lv(4{^R&7So&dc)W75oQSjgFFOZxo0wdqd{);y>H^oPjV;!l!q%fXn zw6QxqFw#CSG%z-5Q`=UxgF0mUJ2!5`gNoGDuqvKTCi*&(qoav_#6*PAGb%>Sl3u$Y#h-Os|=ay;dou`hJi5?=UC&wST`ga?pKt)fziZ~!rFnc zO>NC8xv_L&cywbjo%O7pKk=Hy>=hmI_(&h3Zf%gE)XG<>f%7K1LnX$(bLnEL>*PzgnX?lg0q4B}Q*g$GnDP40zQ+#ZE zILY;?xv8roK0Z8{>b>&P)NryEUJ=hC);Preg}iFC3_Dj2vmxovo4d@Pz8OhCD=7IB$-ab9l}WlQ49WNSJ#)E-6QDbh%4OETS@ z+A=KSE23?kBxeHzN%bq)4b5&Nq63U`^>|`%VBD1t0GTkJL z!$gG`jQEDsJdj2MVe6kHLrq-KGkFj+#S_s)Uv}J6MS>S)+-#b>O zVupK>sgfmUdr2X>(X;bO@lz2v`Jm#>iV`nlKV<3&MVK6>M$`_{>C1A5y5x+?of@7n z4SRe5#n7J^>>Np^Wm&CE4ELd6IEzY;Qz*I~luIhzO``B1{kELMwarO*cxWI;T7Ail ziSfZPCnQRrykV5x&=4d;v>=QRr<45yqiEUe=u|-4@aR}#nA%!mW9>Vs_UiHExDG)J zR}=3}QA<}FUy&SZ9N&lr-+9WFniOAsD_IomgV~*8^eH5Br5GKzQ|#z%?20=2)xEVf zoft}XT|L|@;wnsjj_`4>S&WZYb7Cy9DmC0l3Mjv-Zl1c@sd;*hg2cROs1lBCwOcq9 ztuD*%Y`Ps)SG27oLFJ&Tpn3|`C$^OY?HbsI{I-eR9->Ot6Fq8ta$s}PewpmIwUh7O z+5ue|=r!%KO3DsaQnaShLkYCwosQ=PYSIy?7{M_sZL$QHmIM{=lXV}Bg2Q_ldtE7UmaPafn~VNii? z>U}A(Y+5vpo|$aTZBBaaCjH6M5BH*~%eE06C7X{bVV8Oq-&M`2IvrV$BkdJk=m&tT zKQdkP&2}VfpE?xpv}U+Bl}@*$)2Vd!TgmnqV(7lGjuBLR#j>90YHIT~(?o=HYw1%v zn83RcA$LEULS%BNTfG0RqcE>bUhn6HsIo7K>YQ#!rxW-@5slizEE2?NOpK#h?P_i{ zT@KZeNT6|dk*P+j?j*?3DZ~Ta)TG*lXp2x*#LIP3lX8d+#u4-i(5^w>sG}=;R|%~! z6p!c2M?{mLY%g@|crQDTz@lGMb^Vz@vWDqLrYHzJt)=HLq~-JqdG%=1*dWpygsygu z_NuOb!}!){dpoj%hpy{xa7ca0L0L+MVGNJxCc*WP9i<%^v?K@bnEPQcwWqdpjUhGtXqluJ1qeXOuMYp6|WIxXpQ#8?gC8;)sk0x=RNLP}&NJyDt z*F)g8RqjNk7OY^B)0-H7b|%QkC|g?x$44<(RQZI=9EN_oB%}8>u^5r;@?=@j(ZF7d zCCBqkNe{)c-^IjeDmCOFsg&2`1Y%QP93`du86z8*_zN2*M+xmTW69C+A=0|8#?I~) zUFZSgOQ$ncQb__H7nH48O>l5+qnANpwoHq#S&Qxm#se8`9}YG{T)8X!9&CM)a!ydQe(*)qGC z@iKVhURE(=M;-}oNZPfFs{*S9JfVioi2?LhdXj0}bl1rQVA?1Lm1YjI$@+7LXjETB#(?DHd;yVk#*0K>?|G>W@3$8jYL+aitFB#A zU5iBpzOJBfB(h}TLVI=Lc~K@_x#(j9C!Zw5*_iJaV#0b@-v3cv)rCTC_A!En({K;r z@4T_(*0HSMkLTczXrA->P-4fyUvKy~jE-ip=k!i6>NbX-E)jy{8L3i4EPhC5U{uai68Ss({M$nMQ|2`HR2L1){pQwl?YdQbhjQ``n zVZ6{x&2Qdq8XlzbA~&pV@*1;*cn(b8)BI&RjGi<6H#7dz!CzI$2s!xgWx-2y_-Hb{U~FJPIysUWUC>)wU0uBe6K&eRv36QJaU^~xlCc}k(TcXUBaNrShJba!;s)mAr=*pU@=k){Pr^XEsJ&?xpN zha+o-2ew8w*Vdl5_`I6)+Pk|DFmg3!tv8KD=JlQxsadvc@wv6tHA^Gi$*qae2+gmg z@lhNeBaDI4ND8w?$v$C);_)OpO{p!yvf?%-YTv-9rb+Zc6s}cBD;cqtuFm!~-EEz# z;x)C6ZQVk6$cu?wFA5}kax^tKPNPlX+ki;QDW>2P6x~1Dadvbzx5T^JR;_4niMOn3 zZfVw$N_ul!YimoaWmR_@dfpQ%RyDaQzlOd~Q>+wM&<9Pn-bWWH64qGatJZWhw!~_5 zd=917!&4`GSx;f5O{Ip%)E7bcN)dZGB@s;FQnooY&?f>LQmH{<`2wSu@=f+dFtL#q zRxmI=>>`8$TPP$xMq%i1rvU;Elcp2~2GFzR0n%Ss5RZ=o)hx#IzSod;f#dxtyn(?K zmTPkVDGF>~DSYK8;}Sd@7bju$ph-YIxsaZu1eCXh9_^t=lk_M(5s{A- zuoqy|!obGC6lQOH1%bZQI88MI$#Cs0D5$WaD9#FNb;C+rV^P9gQNn#)QCySjx^dk| zm;SEqYTPz;b=TlF5N*Qs{V{nPY$e{IX1We{t?R%og{klg-|k3fkG!86ZCKHQ$9=o! zG>|$GTGi6f-rl*E;Aw5Ex+UM-w$>OCPH$_G_cMCP*B$@>Mdh4Q{Uwn*NaVvFT{MQn+@ zUmRQsi}!Gf2q|Y<9NRv zTd6CyC$nNJb;VYQy31pmW-{8W1=C&+%cimwJo+A6^g$PvD7gqH9;jropQT`+`)M*r1Px&mQr`lQbIE|GO|JUMW`1Ncf9BfZ^OLb z$jSk^sYKA19+RvN0SsHo-=4~1Fa(r}w;^*97;~prYIXD27i1?_YOUv~+2JO&@R_oB z#nVq6n7#5y>z#8pTW9%u_W3in9tiF$Y%a>&_`+kE^ABTiaA@W`lh)mbzkKK`FU+Q} z)}qX<`-4Xw15Jlg*pb<@Ha~M)5b_Utb$NQIv9r3#)Yyz2@7k;|>KB9oJok5`KjuF*Re0CO8Fdz@ANS7y^(jWJ0QD(<38F>Yj(LK}GKXU6MH;%lX{=t!;*nMR7Be%W~-1>d7d-Llr%vO}=K!1+%>t>TjsnN`<6C>pA+yT#gAb^S{X?r<6&+u_%!a7xEG`gGahjaAovz~@_Ab=}Ji z#L3g4-igiEsp46MLi3AJgjklSDZ>?a=`4}gW+4BFTuPhMw>6kA(-B%tC z`jC5;umk_rLg2PX9}ATEN~Ucc@o&FqIsO8H)qx^ksLB_b=D#-OE1dR;U{nfinN#-l!ymT%p=rUYl6Qqp58YOe@PZk_ zAF3*8L%$?27qFz{B2a^82%;3u1Lb7+L+1fpSh~Da#!`gVbecaDwkj=2xv@U9vp#TB zeaX%Bp?GJFQZ z^BJyYIL2^-;f)Mm$?(Mi%wWkpv7&@OgLi|AUIJ`nc%RJ^7IB7`B6AH7WwgP=4ByP~ zM;QJB!#@C4GK9r%82%l@G?1F1S(J8 zLMux64K3Rbf$8%?wc@unPguOo@EaHh8QFfr@Cj&541F=foeXbecqhaA82&V{k}WJ~ z$ffc&j+t=tE^*n}H1f{_J%T^D=sCC;`Ky6VJS%}sSrCrk4-Ru34u2HbMAT1lW}OZeUXv2uJV-7rhr3!~X!V(NzjG?aZ~n=3NNCn*#Cd1TIGY2Z4?J zgwMwxT=ZdFjLfeA8<`1jz#m-nySNxR7o(hwoP*3Arqh6poPpjzZ)w zx=WzcfICk92<&~LgRtqjVXf@8#bhqn{6L!b&P$A8 z052NCc9twL+RrU5% z5uA-1wUF74Y71#Nucd}(eGdMJ4&*iVX#DktpVeN&pX)xsh-g@BN4-muXD2leaHgIa z`H4o@xKjaoHLs!3-S8jx8lZm?sj7$y@-{Q0i@!HtW60kBj3q$7T*LC|H7uWN$tvi} zUc>S^Ygj(BhUGAsH7p-ijZA|0mShf;$Cm2{|Lb!IFqe zJ^p@uhVeP~2nA?2-vHbn!{6AMjG!UsZ)3sLz@PJe$_3|7Wbw~JN3y3`5w-X({w<83 z`rq5YpY3@353#`2z)u~6{|k)&65wu9iY&+D|2_*_3H-BT@c)MKQ}1>g&tM(K<1aIr zfH3MY|I;z}=Q4ikcV3FihNI+X1LHpd{7->@_$d5q8UGCMzfOr{IWGSe#!uxHqAq`y z{c@eL{Q${M+>V)@!-=PNHwI_}?x-ySf1UD-fC*8u;I7aFpdZ|GzW-2f%kR>h6oW64BU;oZ&z2UWAW^TDlhz$kRkIHOIYD zyg#d*MCG)(M{jyp+v2gK$mREUP|jL+gU>3WgTozNE8?wm^fTVo4Nc0TwO|8?C4!Q1 zv|nz^?7n&gJ4q;^FvSw0dC-Cg!7xpIhG;I(s)2Gk@pm>}9PfT_v?bn+p{|_*qhdc( zM`w3Su18|)gwOj(Y+d&{^N`<`4=19PbkCDCBtxhbmua$dRj4~xh3?K(VRq-L(CJ(i zn$DHOWI9)cs&f^T8-3J%pnXUx2(t1WhR=CSb-lpt>=$~O*d6cp;Vp>#4A=0#;}V)A zMBY#lN~|DKj%&CIm(WSL6zWc#lY;KV=_J&SA)4-$Nht4y@D@Z!0m7Hz652qByrDr{ z3L;mLe>3^F<06wV-9dLcnp#+Bx`TywcThcLcL$y4)PAf`_$w6u>$p_Py+@UD?@^`P zdsHd+9#zV{N0oB#Q6=p?s#JTAD%IYjO1bx_Qtdsev}o^9rQCZ|srDXK%DqRGdhZeL zdhZdC-g^XO_8tMMy+;6Y?-A~D?-B0UdxWdK_Xt?-J*rfDk1F-vqe@HeJ*w1uk1EyP zqe{K^sM3;qk1F-vqe`{+s8a7es#JTAD)ru@O11Z>Qtv&gRC|vq_1+_-FZUkdF83bc zF83bcF83bcF83bcF83bcF83bcF83bcPJ54VlY5UU?Y&2!u)RlR2QU{z)twzYrFN3O zu9mbkzyk8xI9KOu1gYBoE@uM6mZlc673u2Gc6PG^W;q+5q0Jtk+?Zrtx$dty$A&(p8k6jb>gq z?Ab;^uYA+I?*nctlKq-Ble%-S>#F~P)-%x(oyzea{e`wdY+wC-w-o<;+4 z1yR8fD7)p0;M>VPf6a?`~u(T(2`=D{IioH$=DN9(v z3hPoCz0w2)p&Uv^+P)Jl8aq9<;MadZs@rHMOJw>rqNmZCgsDp@Jr7jEXuT zdDYD?ab0+&6uuwzs;+hQs=T21=@+cq!X8d#!;k+(gQWfna9ZcfxfMR#%XZ^ zxfCs$L(xdzy`>%-C5s+XaETBb9ksIy+<2zbN+kA@`>H%8tBq$-`O;*ar+jsIUQ4;q zm)|DnVxP4&XA`tJZ>8M*M=WJq!)CiR?6^yxCg)K4G~UXp*V;N9l|D`FdP`qfkIQT6 z$MRhI_x%w|pC&SnqmJjL^lxydecYvgu`2!GiQdw8EaZ^}&|-jB100^bYQe*K)`Bws zR0GbuwE@&Q@P1|SP5vXc4awvE0z{P-^r1Iu+JKyf8A%anRl-q(oNRg3g%kYw{T?*? zr|Ru{bRkz?-}`-@PP@Nw-l!J)!YFr{p)<-)xlCozB&8hH^U%EJV|$+Sarg1(BkL#8 zOf+jlv-?9=c*a)V{HECwW%NmAs>Yz28Yjp4#)DC_r2sZ8Z`Os+E3Jb5kI5Bh_7jsF?HwK->xY0OhY%=k=>ZfLPa4SLj?iR?3D zJV#3dROWyfaixKpsmq+D3hO*Yzg{Kh8guo?@s*7KX?Jq=c&y(^PIbg(YIJCtDc<@V zDx{{}cm*w%8bM3U=t0fKjxN#&Y2k`lq$Pc*Cl*=1vqSS*QZMGYj{m|x#q1jUdGWIY&=@#&W2TwZ`%0ny0uIg}#mME7GVX2*-#-#Y}WzHE5R z{L`0Hv5AttQ&h>yi7jJj7(sGpu_{(qP+rUQw|Oqp%7Xu=@1M6)PM0e=qU3WCm5VSe zL1swZ2BO`$nUf{2xjHLv+XvNL!lHcTs(+3vSG~r%DQBHNo6cD;TV8YbJ$cUEctNgq z2(7zn4CI80f@mPJz9YJOCVcN??tFYt>k9=5@!-TmzLfB7S$*l`zCFHJ!TO2K5zC*N z*etBQH|`HwJ&%hQI)62k9oG1z#yyj}_uklef5ZI7ARSI^oUOPUgD=d^=H@Z&c!v(K zK7HuvM+@HRKGOXBnq8}Ij_zo@ZvX6tYh$-y3!b$B59R z=1+)MgQ;gXi^>I)qCRuyzCBiKW}O^ z`pUssVxl5N+@KylICJupl|7G_WgaCYL!UkT<;OekOG z#zQm3v&})GiifP-hrV+7%j+fsi37pREHUlC?1nvl$XU3)aZknW%w;&n`;4d?G9(tuh+%lP2kU9Sle1~5t6t_)g&cyL!_$qvle_;9KrIYZ< zW5zF@N=IS~-r2Y7;#)Fz-uQYFM~M$)_U#hBm5-hBn-hBui2ZvGU-s-|C|0m>|DI8zE_ru%&vWVUYN{WzW=h!`E>Ah zC$u1QD{>oewSP8JMnPBtIXnwHnxF$OWEADz&diN(5A6?%J4&s4ckNvL!fa^IA-wsc zE9JA7PEK2$xmjt*wxzLfne0Fvw zvwQVRvtR0*9D3;xT`8UW%f&+#yPrUbOrH#k{j)QNi=lhg_jc~td+Cc8W)53Fe6-@< zH$J|nAmP6Y`@d7-wah`%g`J3r%7*kC5<ss4acJ$%@D@X)LR@nYshXc2aK zJZM@u-#hzmYd`Y%j?B%gZf$&?bYH|WyJjXbhpHw|7nz%%4<1}qGW6VhYO$V2$*MN% zOS218U+j6#dj7FPXraE8+40UZJNEB!4zt(4`rIsQ`WJido>l+q-FuerK0Wrk_0OS= zvwW1obF=CN)nL@HBUC4NUCJC3pH}S)Y87hVUbHDxs}7(wv0gjn8R8c;lH;}mvL(*k z_`z4i#DA>c_sXPrE|V#@Uf+v)ST24!`TM5Pd?a(L1p@?PVt++Aku8~$Cxp0Pka_si zJ;#46pPFRj>H+j|`Rl5#Z;)q}P1s{j*ezBA9l39)+J2kAp=z6Nch&axs%yW3!~E(5 zzB$7uAEj+46lWtH^&e74@Ohdh98nHanzV_tmvzOsM*AQ{1X+|yQ2P_=_zs=`s zueuHbT>o+d#b+E%NNc`Zh)>JxYj#Pic08D8XbB_NGmwwHp*e%7o}y(f`|IM?dm**hpNa
    +//! Polarity Phase       Mode
+//!   0       0   SPI_PROT_POL0PHA0
+//!   0       1   SPI_PROT_POL0PHA1
+//!   1       0   SPI_PROT_POL1PHA0
+//!   1       1   SPI_PROT_POL1PHA1
+//!
    +//! +//! The \e mode parameter defines the operating mode of the SPI module. The +//! SPI module can operate as a controller or peripheral; the SPI can also be be +//! configured to disable output on its serial output line. The \e mode +//! parameter can be one of the following values: \b SPI_MODE_CONTROLLER, +//! \b SPI_MODE_PERIPHERAL, \b SPI_MODE_CONTROLLER_OD or +//! \b SPI_MODE_PERIPHERAL_OD ("OD" indicates "output disabled"). +//! +//! The \e bitRate parameter defines the bit rate for the SPI. This bit rate +//! must satisfy the following clock ratio criteria: +//! +//! - \e bitRate can be no greater than lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The \e dataWidth parameter defines the width of the data transfers and +//! can be a value between 1 and 16, inclusive. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI operation should be disabled via SPI_disableModule() before any +//! changes to its configuration. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth); + +//***************************************************************************** +// +//! Configures the baud rate of the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param bitRate specifies the clock rate in Hz. +//! +//! This function configures the SPI baud rate. The \e bitRate parameter +//! defines the bit rate for the SPI. This bit rate must satisfy the following +//! clock ratio criteria: +//! +//! - \e bitRate can be no greater than \e lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate() +//! if you wish to configure it separately from protocol and mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate); + +//***************************************************************************** +// +//! Enables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SPI interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. The \e intFlags parameter can be +//! any of the following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level +//! interrupt (and RX FIFO overflow) +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SPI interrupt sources. The +//! \e intFlags parameter can be any of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW) +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base specifies the SPI module base address. +//! +//! This function returns the interrupt status for the SPI module. +//! +//! \return The current interrupt status, enumerated as a bit field of the +//! following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF - RX FIFO level interrupt +//! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +// +//***************************************************************************** +extern uint32_t +SPI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified SPI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e intFlags parameter can consist of a bit field of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF +//! - \b SPI_INT_RXFF_OVERFLOW +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive +//! receive buffer, so it usually doesn't need to be cleared using this +//! function. +//! +//! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + + +//***************************************************************************** +// +//! This function can be used to transmit a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 24-bit word of data. +//! 24-bit word data is divided into three bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay); + +//***************************************************************************** +// +//! This function can be used to transmit a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 32-bit word of data. +//! 32-bit word data is divided into four bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to receive a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 16-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 16-bit word. +// +//***************************************************************************** +extern uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 24-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 24-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 32-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 32-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param data specified the data to be transmitted +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return . +// +//***************************************************************************** +extern uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t data); + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length and 'N' words of transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param pTxBuffer specifies the pointer to transmit buffer +//! \param pRxBuffer specifies the pointer to receive buffer +//! \param numOfWords specified the number of data to be transmitted / received +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return none +// +//***************************************************************************** +extern void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SPI_H diff --git a/gpio_driverlib_cpu2/device/driverlib/sysctl.c b/gpio_driverlib_cpu2/device/driverlib/sysctl.c new file mode 100644 index 0000000..f4708f2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/sysctl.c @@ -0,0 +1,1469 @@ +//########################################################################### +// +// FILE: sysctl.c +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cputimer.h" +#include "sysctl.h" + +// +// Define to isolate inline assembly +// +#define SYSCTL_DELAY __asm(" .if __TI_EABI__\n" \ + " .asg SysCtl_delay , _SysCtl_delay\n" \ + " .endif\n" \ + " .def _SysCtl_delay\n" \ + " .sect \".TI.ramfunc\"\n" \ + " .global _SysCtl_delay\n" \ + "_SysCtl_delay:\n" \ + " SUB ACC,#1\n" \ + " BF _SysCtl_delay, GEQ\n" \ + " LRETR\n") +#define SYSCTL_CLRC_DBGM __asm(" CLRC DBGM") + +// +// Define Timer1 and Timer2 seed values +// +#define TMR1SYSCLKCTR 0xF0000000U +#define TMR2INPCLKCTR 0x800U + +#define XTAL_CPUTIMER_PERIOD 1023U + +//***************************************************************************** +// +// SysCtl_delay() +// +//***************************************************************************** +SYSCTL_DELAY; + + +static void +SysCtl_pollCpuTimer(void) +{ + // + // Delay for 1 ms while the XTAL powers up + // + // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles + // + SysCtl_delay(2000); + + // + // Wait for cpu timer 2 to overflow + // + while(CPUTimer_getTimerOverflowStatus(CPUTIMER2_BASE) == false); + { + // + // If your application is stuck in this loop, please check if the + // input clock source is valid. + // + } + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); +} + +//***************************************************************************** +// +// SysCtl_getClock() +// +//***************************************************************************** +uint32_t +SysCtl_getClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + // + // Don't proceed if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning the INTOSC1 rate. You need + // to handle the MCD and clear the failure. + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (uint32_t)SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + if((oscSource == (SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) || + (oscSource == (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S))) + { + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) & + (SYSCTL_SYSPLLCTL1_PLLEN | SYSCTL_SYSPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_FMULT_M) >> + SYSCTL_SYSPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier and fixed divide by 2 + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_IMULT_M) >> + SYSCTL_SYSPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)); + } + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getAuxClock() +// +//***************************************************************************** +uint32_t SysCtl_getAuxClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + (uint32_t)SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M; + + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + if(oscSource == (SYSCTL_AUXPLL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) + { + // + // 10MHz Internal Clock + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) & + (SYSCTL_AUXPLLCTL1_PLLEN | SYSCTL_AUXPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M) >> + SYSCTL_AUXPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_IMULT_M) >> + SYSCTL_AUXPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + clockOut /= (1U << (HWREG(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)); + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_setClock() +// +//***************************************************************************** +bool +SysCtl_setClock(uint32_t config) +{ + uint16_t divSel; + uint16_t iMult = 0U, fMult = 0U, pllMult = 0U, div; + bool status, sysclkInvalidFreq = true; + uint16_t i, tempSCSR, tempWDCR, tempWDWCR, intStatus; + uint16_t t1TCR, t1TPR, t1TPRH, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t1PRD, t2PRD, ctr1; + float32_t sysclkToInClkError, mult; + + // + // Check the arguments. + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Don't proceed to the PLL initialization if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning false. You'll need to clear + // the MCD error. + // + status = false; + } + else + { + // + // Configure oscillator source + // + SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M); + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure PLL if enabled + // + EALLOW; + if((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) + { + if((HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) & + SYSCTL_SYSDBGCTL_BIT_0) != 0U) + { + // + // The user can optionally insert handler code here. This will + // only be executed if a watchdog reset occurred after a failed + // system PLL initialization. See your device user's guide for + // more information. + // + // If the application has a watchdog reset handler, this bit + // should be checked to determine if the watchdog reset + // occurred because of the PLL. + // + // No action here will continue with retrying the PLL as + // normal. + // + } + + // + // Set dividers to /1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = 0U; + + // + // Get the PLL multiplier settings from config + // + iMult |= (uint16_t)(config & SYSCTL_IMULT_M); + fMult |= (uint16_t)((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S); + pllMult |= (iMult << SYSCTL_SYSPLLMULT_IMULT_S) | + (fMult << SYSCTL_SYSPLLMULT_FMULT_S); + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase + // this number according to allotted system initialization time. + // + for(i = 0U; i < 5U; i++) + { + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + asm(" RPT #60 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + } + } + + // + // Configure Dividers. Set divider to produce slower output frequency + // to limit current increase. + // + divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + + if(divSel != (126U / 2U)) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | (divSel + 1U); + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the + // PLLstartup sequence. If your application has already cleared the + // watchdog SCRS[WDOVERRIDE] bit this cannot be done. It is recommended + // not to clear this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + tempSCSR = HWREGH(WD_BASE + SYSCTL_O_SCSR); + tempWDCR = HWREGH(WD_BASE + SYSCTL_O_WDCR); + tempWDWCR = HWREGH(WD_BASE + SYSCTL_O_WDWCR); + + // + // Disable windowed functionality, reset counter + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = 0x0U; + SysCtl_serviceWatchdog(); + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = 0x0U; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + + // + // This bit is reset only by power-on-reset (POR) and will not be + // cleared by a WD reset + // + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) |= SYSCTL_SYSDBGCTL_BIT_0; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_SYSPLLCTL1) |= SYSCTL_SYSPLLCTL1_PLLCLKEN; + + EDIS; + + // + // Delay to ensure system is clocking from PLL prior to clearing + // status bit + // + SysCtl_delay(3U); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer + // counts are off by +/- 10%. At a minimum, SYSCLK check is performed. + // Re-lock attempt is carried out if SLIPS bit is set. + // This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will + // be aborted by watchdog reset. + // + while(((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) && + (sysclkInvalidFreq == true)) + { + EALLOW; + + // + // Perform PLL re-lock only if SLIPS bit is set, otherwise monitor + // SYSCLK frequency with timers + // + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_SLIPS) == 1U) + { + // + // Bypass PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + SysCtl_delay(12U); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) |= pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + ; + } + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |= + SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay to ensure system is clocking from PLL prior to + // clearing status bit + // + SysCtl_delay(12U); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR); + t1PRD = HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD); + t1TPR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR); + t1TPRH = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH); + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + + // + // Stop timer 1 + // Seed timer1 counter + // Set sysclock divider + // Reload timer with value in PRD + // Clear interrupt flag + // Enable interrupt + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR1SYSCLKCTR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + + // + // Configure timer2 to count Input clock cycles + // + switch (config & SYSCTL_OSCSRC_M) + { + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INT_OSC1 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 1U; + break; + + case SYSCTL_OSCSRC_OSC2: + // + // Clk Src = INT_OSC2 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 2U; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Clk Src = XTAL + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 3U; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + + // + // Clear interrupt flag + // Enable interrupt + // Stop timer 2 + // Seed timer2 counter + // Set sysclock divider + // Reload timer with value in PRD + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR2INPCLKCTR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Stop/Start timer counters + // + + // + // Stop timer 1 + // Stop timer 2 + // Reload timer1 with value in PRD + // Reload timer2 with value in PRD + // Clear timer2 interrupt flag + // Start timer2 + // Start timer1 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Wait for Timers - Stop if either timer overflows + // + while(((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U) && + ((HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U)) + { + ; + } + + // + // Stop timer 1 and 2 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + // + // Calculate elapsed counts on timer1 + // + ctr1 = (uint32_t)TMR1SYSCLKCTR - HWREG(CPUTIMER1_BASE + + CPUTIMER_O_TIM); + + // + // Restore timer settings + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) = t1TCR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = t1PRD; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR) = t1TPR; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH) = t1TPRH; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float32_t)iMult + ((float32_t)fMult / 4.0F); + + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & 0x3FU) == 0U) + { + div = 1U; + } + else + { + div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + 0x3FU) << 1; + } + + sysclkToInClkError = (mult / (float32_t)div) - + ((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is + // off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) || + (sysclkToInClkError < -0.10F)); + + EDIS; + } + + // + // Clear bit + // + EALLOW; + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &= ~SYSCTL_SYSDBGCTL_BIT_0; + EDIS; + + // + // Restore user watchdog, first resetting counter + // + SysCtl_serviceWatchdog(); + + // + // Set the KEY bits and make sure not to set the WDOVERRIDE bit + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = tempWDCR | SYSCTL_WD_CHKBITS; + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = tempWDWCR; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = tempSCSR & ~SYSCTL_SCSR_WDOVERRIDE; + EDIS; + + // + // Restore state of ST1[INTM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x1U) == 0U) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x2U) == 0U) + { + SYSCTL_CLRC_DBGM; + } + + // + // ~200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + SysCtl_delay(40U); + + // + // Set the divider to user value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + status = true; + } + + return(status); +} +//***************************************************************************** +// +// SysCtl_setAuxClock() +// +//***************************************************************************** +void SysCtl_setAuxClock(uint32_t config) +{ + uint16_t pllMult = 0U; + uint16_t counter = 0U, started = 0U, attempts = 0U; + uint16_t mult; + uint16_t i, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Check the arguments + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure oscillator source + // + SysCtl_selectOscSourceAuxPLL(config & SYSCTL_OSCSRC_M); + + // + // Get the PLL multiplier settings from config + // + pllMult |= (uint16_t)((config & SYSCTL_IMULT_M) << + SYSCTL_AUXPLLMULT_IMULT_S); + pllMult |= (uint16_t)(((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << + SYSCTL_AUXPLLMULT_FMULT_S); + + // + // Get the PLL multipliers currently programmed + // + mult = (uint16_t)((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_M) >> + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_S); + mult |= (uint16_t)(HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M); + + // + // Lock PLL only if the multipliers need update + // + if(mult != pllMult) + { + + // + // Configure PLL if enabled + // + if((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE) + { + // + // Backup Timer 2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // - Clock source to AUXPLL + // - Clock divider to divide by 1 + // - Small period to detect overflow + // - Interrupt disabled + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = 6U; + + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = 10U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK / 2 + // while using Timer 2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = 0x3U; + SYSCTL_REGWRITE_DELAY; + EDIS; + + // + // Lock the PLL up to five times. + //CPU Timer 2 will monitor a successful + // lock and break out of the loop earlier if detected. + // + while((counter < 5U) && (started == 0U)) + { + EALLOW; + + // + // Turn off AUXPLL and delay for it to power down. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= + ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically + // turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + SYSCTL_REGWRITE_DELAY; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLEN; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. + // This is used to test that the PLL has successfully started. + // + // Reload and start the timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Check to see timer is counting properly + // + for(i = 0U; i < 1000U; i++) + { + // + // Check overflow flag + // + if((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) != 0U) + { + // + // Clear overflow flag + // + HWREGH(CPUTIMER2_BASE + + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + + // + // Set flag to indicate PLL started and break out of + // for-loop + // + started = 1U; + break; + } + } + + // + // Stop timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + counter++; + EDIS; + } + + if(started == 0U) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass + // PLL). + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) = 0U; + EDIS; + + // + // The user should put some handler code here based on how + // this condition should be handled in their application. + // + ESTOP0; + } + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Reload period value + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + EDIS; + } + } + else + { + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + EDIS; + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + while(((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_SLIPS) != 0U) && (attempts < 10U) && + ((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE)) + { + EALLOW; + + // + // Bypass AUXPLL + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLEN; + + // + // Wait for the AUXPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + + SysCtl_delay(3U); + + attempts++; + + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + SYSCTL_REGWRITE_DELAY; + EDIS; + +} + + +//***************************************************************************** +// +// SysCtl_selectXTAL() +// +//***************************************************************************** +void +SysCtl_selectXTAL(void) +{ + uint16_t t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Backup CPU timer2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Backup AUX clock settings + // + uint16_t clksrcctl2 = HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2); + uint16_t auxpllctl1 = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1); + uint16_t auxclkdivsel = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL); + + // + // Set AUX clock source to XTAL, bypass mode. + // AUXCLK is used as the CPUTimer Clock source. SYSCLK frequency must be + // atleast twice the frequency of AUXCLK. SYSCLK = INTOSC2(10MHz) + // Set the AUX divider to 8. The above condition will be met for XTAL + // frequencies up to 40MHz + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = 0x0U; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = SYSCTL_AUXPLLCLK_DIV_8; + SYSCTL_REGWRITE_DELAY; + + + // + // Disable cpu timer 2 interrupt + // + CPUTimer_disableInterrupt(CPUTIMER2_BASE); + + // + // Stop cpu timer 2 if running + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Initialize cpu timer 2 period + // + CPUTimer_setPeriod(CPUTIMER2_BASE, XTAL_CPUTIMER_PERIOD); + + // + // Set cpu timer 2 clock source to XTAL + // + CPUTimer_selectClockSource(CPUTIMER2_BASE, CPUTIMER_CLOCK_SOURCE_AUX, + CPUTIMER_CLOCK_PRESCALER_1); + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); + + // + // Start cpu timer 2 + // + CPUTimer_startTimer(CPUTIMER2_BASE); + + EALLOW; + // + // Turn on XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_XTALOFF; + EDIS; + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + + // + // If a missing clock failure was detected, try waiting for the cpu timer 2 + // to overflow again. + // + while(SysCtl_isMCDClockFailureDetected()) + { + // + // Clear the MCD failure + // + SysCtl_resetMCD(); + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + } + + // + // Stop cpu timer 2 + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Restore AUX clock settings + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = clksrcctl2; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = auxpllctl1; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = auxclkdivsel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSource() +// +//***************************************************************************** +void +SysCtl_selectOscSource(uint32_t oscSource) +{ + ASSERT((oscSource == SYSCTL_OSCSRC_OSC1) || + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL)); + + // + // Select the specified source. + // + EALLOW; + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Select XTAL in crystal mode and wait for it to power up + // + SysCtl_selectXTAL(); + break; + + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INTOSC1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M) | + (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S); + + SYSCTL_CLKSRCCTL_DELAY; + + // + //Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSourceAuxPLL() +// +//***************************************************************************** +void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource) +{ + bool status = false; + + EALLOW; + + switch(oscSource) + { + case SYSCTL_AUXPLL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_INTOSC2OFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M); + break; + + case SYSCTL_AUXPLL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_XTALOFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + break; + + case SYSCTL_AUXPLL_OSCSRC_AUXCLKIN: + // + // Clk Src = AUXCLKIN + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (2U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + SYSCTL_CLKSRCCTL_DELAY; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_getLowSpeedClock() +// +//***************************************************************************** +uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz) +{ + uint32_t clockOut; + + // + // Get the main system clock + // + clockOut = SysCtl_getClock(clockInHz); + + // + // Apply the divider to the main clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M)); + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getDeviceParametric() +// +//***************************************************************************** +uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric) +{ + uint32_t value; + + // + // Get requested parametric value + // + switch(parametric) + { + case SYSCTL_DEVICE_QUAL: + // + // Qualification Status + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_QUAL_M) >> SYSCTL_PARTIDL_QUAL_S); + break; + + case SYSCTL_DEVICE_PINCOUNT: + // + // Pin Count + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + break; + + case SYSCTL_DEVICE_INSTASPIN: + // + // InstaSPIN Feature Set + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_INSTASPIN_M) >> + SYSCTL_PARTIDL_INSTASPIN_S); + break; + + case SYSCTL_DEVICE_FLASH: + // + // Flash Size (KB) + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_FLASH_SIZE_M) >> + SYSCTL_PARTIDL_FLASH_SIZE_S); + break; + + case SYSCTL_DEVICE_PARTID: + // + // PARTID Format Revision + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M) >> + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S); + break; + + case SYSCTL_DEVICE_FAMILY: + // + // Device Family + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_FAMILY_M) >> SYSCTL_PARTIDH_FAMILY_S); + break; + + case SYSCTL_DEVICE_PARTNO: + // + // Part Number + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_PARTNO_M) >> SYSCTL_PARTIDH_PARTNO_S); + break; + + case SYSCTL_DEVICE_CLASSID: + // + // Class ID + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_DEVICE_CLASS_ID_M) >> + SYSCTL_PARTIDH_DEVICE_CLASS_ID_S); + break; + + default: + // + // Not a valid value for PARTID register + // + value = 0U; + break; + } + + return((uint16_t)value); +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/sysctl.h b/gpio_driverlib_cpu2/device/driverlib/sysctl.h new file mode 100644 index 0000000..8b263eb --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/sysctl.h @@ -0,0 +1,3531 @@ +//########################################################################### +// +// FILE: sysctl.h +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SYSCTL_H +#define SYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sysctl_api SysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_nmi.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_otp.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + + +// +// Macro used for adding delay between 2 consecutive writes to CLKSRCCTL1 +// register. +// Delay = 300 NOPs +// +#define SYSCTL_CLKSRCCTL_DELAY asm(" RPT #250 || NOP \n RPT #50 || NOP") + +// +// Macro used for adding delay between 2 consecutive writes to memory mapped +// register in System control +// Total delay = 3 * (DEVICE_SYSCLK_FREQ / INTOSC1 Freq) + 9 +// +#define SYSCTL_REGWRITE_DELAY asm(" RPT #69 || NOP") + +//***************************************************************************** +// +// Defines for system control functions. Not intended for use by application +// code. +// +//***************************************************************************** + +// +// Shifted pattern for WDCR register's WDCHK field. +// +#define SYSCTL_WD_CHKBITS 0x0028U + +// +// Keys for WDKEY field. The first enables resets and the second resets. +// +#define SYSCTL_WD_ENRSTKEY 0x0055U +#define SYSCTL_WD_RSTKEY 0x00AAU + +// +// Values to help decode peripheral parameter +// +#define SYSCTL_PERIPH_REG_M 0x001FU +#define SYSCTL_PERIPH_REG_S 0x0000U +#define SYSCTL_PERIPH_BIT_M 0x1F00U +#define SYSCTL_PERIPH_BIT_S 0x0008U + +// +//Keys for the System control registers write protection +// +#define SYSCTL_REG_KEY 0xA5A50000U +#define SYSCTL_PLL_KEY 0XCAFE0000U + +// +//Values to help access shifting of bits +// +#define SYSCTL_TYPE_LOCK_S 0xFU + + +// +// LPM defines for LPMCR.LPM +// +#define SYSCTL_LPM_IDLE 0x0000U +#define SYSCTL_LPM_STANDBY 0x0001U +#define SYSCTL_LPM_HALT 0x0002U +#define SYSCTL_LPM_HIB 0x0003U + +// +// Bit shift for DAC to configure the CPUSEL register +// +#define SYSCTL_CPUSEL_DAC_S 0x10U + +// +// Default internal oscillator frequency, 10 MHz +// +#define SYSCTL_DEFAULT_OSC_FREQ 10000000U + +// +// Mask for SYNCSELECT.SYNCIN +// +#define SYSCTL_SYNCSELECT_SYNCIN_M SYSCTL_SYNCSELECT_EPWM4SYNCIN_M + +// +// Boot ROM Booting and Reset Status +// +#if defined(CPU2) +#define SYSCTL_BOOT_ROM_STATUS 0x0002U +#else +#define SYSCTL_BOOT_ROM_STATUS 0x002CU +#endif +#define SYSCTL_BOOT_ROM_POR 0x8000U +#define SYSCTL_BOOT_ROM_XRS 0x4000U + +#define SYSCTL_DEVICECAL_CONTEXT_SAVE asm(" PUSH ACC \n\ + PUSH DP \n\ + PUSH XAR0 \n\ + PUSH XAR2 \n\ + PUSH XAR3 \n\ + PUSH XAR4 \n\ + PUSH XAR5 \n\ + ") + +#define SYSCTL_DEVICECAL_CONTEXT_RESTORE asm(" POP XAR5 \n\ + POP XAR4 \n\ + POP XAR3 \n\ + POP XAR2 \n\ + POP XAR0 \n\ + POP DP \n\ + POP ACC \n\ + ") + +// +// Device_cal function which is available in OTP memory +// This function is called in SysCtl_resetPeripheral after resetting +// analog peripherals +// +#define Device_cal ((void (*)(void))((uintptr_t)0x070282)) + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setClock() API as +// the config parameter. +// +//***************************************************************************** +// +// System clock divider (SYSDIV) +// + + + +#define SYSCTL_SYSDIV_M 0x00001F80UL // Mask for SYSDIV value in config +#define SYSCTL_SYSDIV_S 7U // Shift for SYSDIV value in config + +//! Macro to format system clock divider value. x must be 1 or even values up +//! to 126. +#define SYSCTL_SYSDIV(x) ((((x) / 2U) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M) + +// +// Integer multiplier (IMULT) +// +#define SYSCTL_IMULT_M 0x0000007FUL // Mask for IMULT value in config +#define SYSCTL_IMULT_S 0U // Shift for IMULT value in config +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M) + +#ifndef DOXYGEN_PDF_IGNORE +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_FMULT_M 0x00006000UL // Mask for FMULT value in config +#define SYSCTL_FMULT_S 13U // Shift for FMULT value in config +#define SYSCTL_FMULT_NONE 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_0 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_1_4 0x00002000UL //!< Fractional multiplier of 0.25 +#define SYSCTL_FMULT_1_2 0x00004000UL //!< Fractional multiplier of 0.50 +#define SYSCTL_FMULT_3_4 0x00006000UL //!< Fractional multiplier of 0.75 + +// +// Oscillator source +// +// Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(), +// and SysCtl_turnOffOsc() functions as the oscSource parameter. +// +#define SYSCTL_OSCSRC_M 0x00030000UL // Mask for OSCSRC value in config +#define SYSCTL_OSCSRC_S 16U // Shift for OSCSRC value in config +//! Internal oscillator INTOSC2 +#define SYSCTL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) in crystal mode +#define SYSCTL_OSCSRC_XTAL 0x00010000U +//! Internal oscillator INTOSC1 +#define SYSCTL_OSCSRC_OSC1 0x00020000UL + +// +// Enable/disable PLL +// +#define SYSCTL_PLL_ENABLE 0x80000000U //!< Enable PLL +#define SYSCTL_PLL_DISABLE 0x00000000U //!< Disable PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setAuxClock() API +// as the config parameter. +// +//***************************************************************************** +// +// Auxiliary clock divider (AUXCLKDIV) +// +#define SYSCTL_AUXPLL_DIV_1 0x00000000UL //!< Auxiliary PLL divide by 1 +#define SYSCTL_AUXPLL_DIV_2 0x00000080UL //!< Auxiliary PLL divide by 2 +#define SYSCTL_AUXPLL_DIV_4 0x00000100UL //!< Auxiliary PLL divide by 4 +#define SYSCTL_AUXPLL_DIV_8 0x00000180UL //!< Auxiliary PLL divide by 8 + +// +// Integer multiplier (IMULT) +// +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_AUXPLL_IMULT(x) SYSCTL_IMULT((x)) + +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_AUXPLL_FMULT_NONE 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_0 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_1_4 0x00002000UL //!< Fractional multiplier - 0.25 +#define SYSCTL_AUXPLL_FMULT_1_2 0x00004000UL //!< Fractional multiplier - 0.50 +#define SYSCTL_AUXPLL_FMULT_3_4 0x00006000UL //!< Fractional multiplier - 0.75 + +// +// Oscillator source +// +//! Internal oscillator INTOSC2 as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_XTAL 0x00010000UL +//! AUXCLKIN (from GPIO) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_AUXCLKIN 0x00020000U + +// +// Enable/disable PLL +// +#define SYSCTL_AUXPLL_ENABLE 0x80000000U //!< Enable AUXPLL +#define SYSCTL_AUXPLL_DISABLE 0x00000000U //!< Disable AUXPLL + +//***************************************************************************** +// +// Values that can be passed to SysCtl_selectSecController() as the +// periFrame1Config and periFrame2Config parameters. +// +//***************************************************************************** +//! Configure CLA as the secondary controller +#define SYSCTL_SEC_CONTROLLER_CLA 0x0U +//! Configure DMA a secondary controller +#define SYSCTL_SEC_CONTROLLER_DMA 0x1U + +//***************************************************************************** +// +// Values that can be passed to SysCtl_clearNMIStatus(), +// SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and +// SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by +// SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus(). +// +//***************************************************************************** +#define SYSCTL_NMI_NMIINT 0x1U //!< NMI Interrupt Flag +#define SYSCTL_NMI_CLOCKFAIL 0x2U //!< Clock Fail Interrupt Flag +#define SYSCTL_NMI_RAMUNCERR 0x4U //!< RAM Uncorrectable Error NMI Flag +#define SYSCTL_NMI_FLUNCERR 0x8U //!< Flash Uncorrectable Error NMI Flag +#define SYSCTL_NMI_CPU1HWBISTERR 0x10U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_CPU2HWBISTERR 0x20U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_PIEVECTERR 0x40U //!< PIE Vector Fetch Error Flag +#define SYSCTL_NMI_CLBNMI 0x100U //!< Configurable Logic Block NMI Flag +#define SYSCTL_NMI_CPU2WDRSN 0x200U //!< CPU2 WDRSn Reset Indication Flag +#define SYSCTL_NMI_CPU2NMIWDRSN 0x400U //!< CPU2 NMIWDRSn Reset Indication Flag + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_clearResetCause() +// API as rstCauses or returned by the SysCtl_getResetCause() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_POR 0x00000001U //!< Power-on reset +#define SYSCTL_CAUSE_XRS 0x00000002U //!< External reset pin +#define SYSCTL_CAUSE_WDRS 0x00000004U //!< Watchdog reset +#define SYSCTL_CAUSE_NMIWDRS 0x00000008U //!< NMI watchdog reset +#define SYSCTL_CAUSE_SCCRESET 0x00000100U //!< SCCRESETn by DCSM +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_enablePeripheral() +//! and SysCtl_disablePeripheral() as the \e peripheral parameter. +//! The EPWM Clock enable bit is also used to enable clocking for CLB. +//! The EPWM and CLB clock enable bits are mapped to same value, +// +//***************************************************************************** +#define SYSCTL_PERIPH_CLK_CLB1 SYSCTL_PERIPH_CLK_EPWM1 //!< CLB1 clock +#define SYSCTL_PERIPH_CLK_CLB2 SYSCTL_PERIPH_CLK_EPWM2 //!< CLB2 clock +#define SYSCTL_PERIPH_CLK_CLB3 SYSCTL_PERIPH_CLK_EPWM3 //!< CLB3 clock +#define SYSCTL_PERIPH_CLK_CLB4 SYSCTL_PERIPH_CLK_EPWM4 //!< CLB4 clock +//***************************************************************************** +// +// The following values define the adcsocSrc parameter for +// SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource(). +// +//***************************************************************************** +#define SYSCTL_ADCSOC_SRC_PWM1SOCA 0x1U //! EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT, //!< EPWM4SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT, //!< EPWM7SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT //!< EPWM10SYNCOUT --> EXTSYNCOUT + +} SysCtl_SyncOutputSource; + +//***************************************************************************** +// +//! The following values define the \e parametric parameter for +//! SysCtl_getDeviceParametric(). +// +//***************************************************************************** +typedef enum +{ + SYSCTL_DEVICE_QUAL, //!< Device Qualification Status + SYSCTL_DEVICE_PINCOUNT, //!< Device Pin Count + SYSCTL_DEVICE_INSTASPIN, //!< Device InstaSPIN Feature Set + SYSCTL_DEVICE_FLASH, //!< Device Flash size (KB) + SYSCTL_DEVICE_PARTID, //!< Device Part ID Format Revision + SYSCTL_DEVICE_FAMILY, //!< Device Family + SYSCTL_DEVICE_PARTNO, //!< Device Part Number + SYSCTL_DEVICE_CLASSID //!< Device Class ID +} SysCtl_DeviceParametric; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setXClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_XCLKOUT_DIV_1 = 0, //!< XCLKOUT = XCLKOUT / 1 + SYSCTL_XCLKOUT_DIV_2 = 1, //!< XCLKOUT = XCLKOUT / 2 + SYSCTL_XCLKOUT_DIV_4 = 2, //!< XCLKOUT = XCLKOUT / 4 + SYSCTL_XCLKOUT_DIV_8 = 3 //!< XCLKOUT = XCLKOUT / 8 + +}SysCtl_XClkDivider; + + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setAuxPLLClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_AUXPLLCLK_DIV_1, //!< AUXPLL clock = AUXPLL clock / 1 + SYSCTL_AUXPLLCLK_DIV_2, //!< AUXPLL clock = AUXPLL clock / 2 + SYSCTL_AUXPLLCLK_DIV_4, //!< AUXPLL clock = AUXPLL clock / 4 + SYSCTL_AUXPLLCLK_DIV_8, //!< AUXPLL clock = AUXPLL clock / 8 + SYSCTL_AUXPLLCLK_DIV_3, //!< AUXPLL clock = AUXPLL clock / 3 + SYSCTL_AUXPLLCLK_DIV_5, //!< AUXPLL clock = AUXPLL clock / 5 + SYSCTL_AUXPLLCLK_DIV_6, //!< AUXPLL clock = AUXPLL clock / 6 + SYSCTL_AUXPLLCLK_DIV_7 //!< AUXPLL clock = AUXPLL clock / 7 + +}SysCtl_AuxPLLClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setCputimer2Clk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKPRESCALE_1, //!< Cputimer2 clock = Cputimer2 clock / 1 + SYSCTL_TMR2CLKPRESCALE_2, //!< Cputimer2 clock = Cputimer2 clock / 2 + SYSCTL_TMR2CLKPRESCALE_4, //!< Cputimer2 clock = Cputimer2 clock / 4 + SYSCTL_TMR2CLKPRESCALE_8, //!< Cputimer2 clock = Cputimer2 clock / 8 + SYSCTL_TMR2CLKPRESCALE_16 //!< Cputimer2 clock = Cputimer2 clock / 16 + +}SysCtl_Cputimer2ClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_setCputimer2Clk() +//! as \e source parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKSRCSEL_SYSCLK = 0U, //!< System Clock + SYSCTL_TMR2CLKSRCSEL_INTOSC1 = 1U, //!< Internal Oscillator 1 + SYSCTL_TMR2CLKSRCSEL_INTOSC2 = 2U, //!< Internal Oscillator 2 + SYSCTL_TMR2CLKSRCSEL_XTAL = 3U, //!< Crystal oscillator + SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK = 6U //!< Aux PLL CLock + +}SysCtl_Cputimer2ClkSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Wrapper function for Device_cal function +//! +//! \param None +//! +//! This is a wrapper function for the Device_cal function available in the OTP +//! memory. +//! The function saves and restores the core registers which are being +//! used by the Device_cal function +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_deviceCal(void) +{ + // + // Save the core registers used by Device_cal function in the stack + // + SYSCTL_DEVICECAL_CONTEXT_SAVE; + + // + // Call the Device_cal function + // + Device_cal(); + + // + // Restore the core registers + // + SYSCTL_DEVICECAL_CONTEXT_RESTORE; +} + +//***************************************************************************** +// +//! Resets a peripheral +//! +//! \param peripheral is the peripheral to reset. +//! +//! This function uses the SOFTPRESx registers to reset a specified peripheral. +//! Module registers will be returned to their reset states. +//! +//! \note This includes registers containing trim values.The peripheral +//! software reset needed by CPU2 can be communicated to CPU1 via +//! IPC for all shared peripherals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Sets the appropriate reset bit and then clears it. + // + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) |= (1UL << bitIndex); + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) &= ~(1UL << bitIndex); + + // + // Call Device_cal function + // + if((((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0xDU) || // ADCx + (((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0x10U) // DACx + ) + { + SysCtl_deviceCal(); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param peripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note Note that there should be atleast 5 cycles delay between enabling the +//! peripheral clock and accessing the peripheral registers. The delay should be +//! added by the user if the peripheral is accessed immediately after this +//! function call. +//! Use asm(" RPT #5 || NOP"); to add 5 cycle delay post this function call. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn on the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) |= (1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param peripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn off the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) &= ~(1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a watchdog reset of the device. +//! +//! \return This function does not return. +// +//***************************************************************************** +static inline void +SysCtl_resetDevice(void) +{ + // + // Write an incorrect check value to the watchdog control register + // This will cause a device reset + // + EALLOW; + + // + // Enable the watchdog + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + // + // Write a bad check value + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = 0U; + SYSCTL_REGWRITE_DELAY; + + EDIS; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while((bool)1) + { + } +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! \note If you re-purpose the reserved boot ROM RAM, the POR and XRS reset +//! statuses won't be accurate. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getResetCause(void) +{ + uint32_t resetCauses; + + // + // Read CPU reset register + // + resetCauses = HWREG(CPUSYS_BASE + SYSCTL_O_RESC) & + ((uint32_t)SYSCTL_RESC_POR | (uint32_t)SYSCTL_RESC_XRSN | + (uint32_t)SYSCTL_RESC_WDRSN | + (uint32_t)SYSCTL_RESC_NMIWDRSN | + (uint32_t)SYSCTL_RESC_SCCRESETN + ); + + // + // Set POR and XRS Causes from boot ROM Status + // + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_POR) == + (uint32_t)SYSCTL_BOOT_ROM_POR) + { + resetCauses |= SYSCTL_RESC_POR; + } + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_XRS) == + (uint32_t)SYSCTL_BOOT_ROM_XRS) + { + resetCauses |= SYSCTL_RESC_XRSN; + } + + // + // Return the reset reasons. + // + return(resetCauses); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param rstCauses are the reset causes to be cleared; must be a logical +//! OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtl_getResetCause(). +//! +//! \note Some reset causes are cleared by the boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearResetCause(uint32_t rstCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(CPUSYS_BASE + SYSCTL_O_RESC) = rstCauses; +} + +//***************************************************************************** +// +//! Sets the low speed peripheral clock rate prescaler. +//! +//! \param prescaler is the LSPCLK rate relative to SYSCLK +//! +//! This function configures the clock rate of the low speed peripherals. The +//! \e prescaler parameter is the value by which the SYSCLK rate is divided to +//! get the LSPCLK rate. For example, a \e prescaler of +//! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter +//! of the SYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = + (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + ~(uint32_t)SYSCTL_LOSPCP_LSPCLKDIV_M) | (uint32_t)prescaler; + EDIS; +} + +//***************************************************************************** +// +//! Sets the ePWM clock divider. +//! +//! \param divider is the value by which PLLSYSCLK is divided +//! +//! This function configures the clock rate of the EPWMCLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an +//! EPWMCLK rate that is half the PLLSYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) & + ~SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF1 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF1CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF1CLK rate. For example, \b SYSCTL_EMIF1CLK_DIV_2 will select an +//! EMIF1CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF1ClockDivider(SysCtl_EMIF1CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF1CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF2 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF2CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF2CLK rate. For example, \b SYSCTL_EMIF2CLK_DIV_2 will select an +//! EMIF2CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF2ClockDivider(SysCtl_EMIF2CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF2CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Selects a clock source to mux to an external GPIO pin (XCLKOUT). +//! +//! \param source is the internal clock source to be configured. +//! +//! This function configures the specified clock source to be muxed to an +//! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a +//! value of one of the following values: +//! - \b SYSCTL_CLOCKOUT_PLLSYS +//! - \b SYSCTL_CLOCKOUT_PLLRAW +//! - \b SYSCTL_CLOCKOUT_SYSCLK +//! - \b SYSCTL_CLOCKOUT_INTOSC1 +//! - \b SYSCTL_CLOCKOUT_INTOSC2 +//! - \b SYSCTL_CLOCKOUT_XTALOSC +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectClockOutSource(SysCtl_ClockOut source) +{ + EALLOW; + + // + // Clear clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) &= + ~SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M; + SYSCTL_CLKSRCCTL_DELAY; + + // + // Set clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) |= (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the external oscillator counter value. +//! +//! This function returns the X1 clock counter value. When the return value +//! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external +//! oscillator (XTAL), an application should call this function to make sure +//! the counter is saturated. +//! +//! \return Returns the value of the 10-bit X1 clock counter. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getExternalOscCounterValue(void) +{ + return(HWREGH(CLKCFG_BASE + SYSCTL_O_X1CNT) & SYSCTL_X1CNT_X1CNT_M); +} + +//***************************************************************************** +// +//! Turns on the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns on the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOnOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Turns off the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns off the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOffOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn off INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enters IDLE mode. +//! +//! This function puts the device into IDLE mode. The CPU clock is gated while +//! all peripheral clocks are left running. Any enabled interrupt will wake the +//! CPU up from IDLE mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterIdleMode(void) +{ + EALLOW; + + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters STANDBY mode. +//! +//! This function puts the device into STANDBY mode. This will gate both the +//! CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is +//! left active, and an NMI or an optional watchdog interrupt will wake the +//! CPU subsystem from STANDBY mode. +//! +//! GPIOs may be configured to wake the CPU subsystem. See +//! SysCtl_enableLPMWakeupPin(). +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterStandbyMode(void) +{ + EALLOW; + + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters HALT mode. +//! +//! This function puts the device into HALT mode. This will gate almost all +//! systems and clocks and allows for the power-down of oscillators and analog +//! blocks. The watchdog may be left clocked to produce a reset. See +//! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be +//! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin(). +//! +//! Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHaltMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + asm(" IDLE"); + +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into HALT mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HALT; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +// +//! Enters Hibernate mode. +//! +//! This function puts the device into Hibernate mode. Hibernate (HIB) is a +//! global low-power mode that gates the supply voltages to most of the system. +//! This mode affects both CPU subsystems. HIB is essentially a controlled +//! power-down with remote wakeup capability, and can be used to save power +//! during long periods of inactivity. +//! +//! To wake the device from HIB mode: +//! 1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the +//! power-up of the device clock sources. +//! 2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the +//! rest of the device. +//! +//! To enter Hibernate mode in dual CPU put CPU2 in STANDBY mode first. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHibernateMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + asm(" IDLE"); +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into Hibernate mode when IDLE is executed + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HIB; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +//! Enables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function connects a pin to the LPM circuit, allowing an event on the +//! pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of +//! being connected to the LPM circuit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) |= pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) |= pinMask; + } + + EDIS; +} + +//***************************************************************************** +//! Disables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function disconnects a pin to the LPM circuit, disallowing an event on +//! the pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) &= ~pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the number of cycles to qualify an input on waking from STANDBY mode. +//! +//! \param cycles is the number of OSCCLK cycles. +//! +//! This function sets the number of OSCCLK clock cycles used to qualify the +//! selected inputs when waking from STANDBY mode. The \e cycles parameter +//! should be passed a cycle count between 2 and 65 cycles inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setStandbyQualificationPeriod(uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT((cycles >= 2U) && (cycles <= 65U)); + + EALLOW; + + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint16_t)SYSCTL_LPMCR_QUALSTDBY_M) | + ((cycles - 2U) << SYSCTL_LPMCR_QUALSTDBY_S); + + EDIS; +} + +//***************************************************************************** +// +//! Enable the device to wake from STANDBY mode upon a watchdog interrupt. +//! +//! \note In order to use this option, you must configure the watchdog to +//! generate an interrupt using SysCtl_setWatchdogMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Set the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) |= SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the device from waking from STANDBY mode upon a watchdog interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Clear the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) &= ~SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the watchdog to run while in HALT mode. +//! +//! This function configures the watchdog to continue to run while in HALT +//! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the +//! system enters HALT mode. By default the watchdog is gated when the system +//! enters HALT. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogInHalt(void) +{ + EALLOW; + + // + // Set the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the watchdog from running while in HALT mode. +//! +//! This function gates the watchdog when the system enters HALT mode. INTOSC1 +//! and INTOSC2 will be powered down. This is the default behavior of the +//! device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogInHalt(void) +{ + EALLOW; + + // + // Clear the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the watchdog generates a reset or an interrupt signal. +//! +//! \param mode is a flag to select the watchdog mode. +//! +//! This function configures the action taken when the watchdog counter reaches +//! its maximum value. When the \e mode parameter is +//! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog +//! interrupt signal and disables the generation of a reset signal. This will +//! allow the watchdog module to wake up the device from IDLE +//! or STANDBY if desired (see SysCtl_enableWatchdogStandbyWakeup()). +//! +//! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will +//! be put into reset mode and generation of a watchdog interrupt signal will +//! be disabled. This is how the watchdog is configured by default. +//! +//! \note Check the status of the watchdog interrupt using +//! SysCtl_isWatchdogInterruptActive() before calling this function. If the +//! interrupt is still active, switching from interrupt mode to reset mode will +//! immediately reset the device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogMode(SysCtl_WDMode mode) +{ + EALLOW; + + // + // Either set or clear the WDENINT bit to that will determine whether the + // watchdog will generate a reset signal or an interrupt signal. Take care + // not to write a 1 to WDOVERRIDE. + // + if(mode == SYSCTL_WD_MODE_INTERRUPT) + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) = + (HWREGH(WD_BASE + SYSCTL_O_SCSR) & ~SYSCTL_SCSR_WDOVERRIDE) | + SYSCTL_SCSR_WDENINT; + } + else + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) &= ~(SYSCTL_SCSR_WDENINT | + SYSCTL_SCSR_WDOVERRIDE); + } + + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of the watchdog interrupt signal. +//! +//! This function returns the status of the watchdog interrupt signal. If the +//! interrupt is active, this function will return \b true. If \b false, the +//! interrupt is NOT active. +//! +//! \note Make sure to call this function to ensure that the interrupt is not +//! active before making any changes to the configuration of the watchdog to +//! prevent any unexpected behavior. For instance, switching from interrupt +//! mode to reset mode while the interrupt is active will immediately reset the +//! device. +//! +//! \return \b true if the interrupt is active and \b false if it is not. +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogInterruptActive(void) +{ + // + // If the status bit is cleared, the WDINTn signal is active. + // + return((HWREGH(WD_BASE + SYSCTL_O_SCSR) & SYSCTL_SCSR_WDINTS) == 0U); +} + +//***************************************************************************** +// +//! Disables the watchdog. +//! +//! This function disables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdog(void) +{ + EALLOW; + + // + // Set the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) |= SYSCTL_WD_CHKBITS | SYSCTL_WDCR_WDDIS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Enables the watchdog. +//! +//! This function enables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdog(void) +{ + EALLOW; + + // + // Clear the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~SYSCTL_WDCR_WDDIS) | SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Checks if the watchdog is enabled or not +//! +//! This function returns the watchdog status whether it is enabled or disabled +//! +//! \return \b true if the watchdog is enabled & \b false if the watchdog is +//! disabled +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogEnabled(void) +{ + + // + // Get the watchdog enable status + // + return ((HWREGH(WD_BASE + SYSCTL_O_WDCR) & SYSCTL_WDCR_WDDIS) == 0U); +} + +//***************************************************************************** +// +//! Services the watchdog. +//! +//! This function resets the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_serviceWatchdog(void) +{ + EALLOW; + + // + // Enable the counter to be reset and then reset it. + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the first key to enter the watchdog reset. +//! +//! This function writes the first key to enter the watchdog reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogReset(void) +{ + EALLOW; + + // + // Enable the counter to be reset + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the second key to reset the watchdog. +//! +//! This function writes the second key to reset the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetWatchdog(void) +{ + EALLOW; + + // + // Reset the watchdog counter + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up watchdog clock (WDCLK) prescaler. +//! +//! \param prescaler is the value that configures the watchdog clock relative +//! to the value from the pre-divider. +//! +//! This function sets up the watchdog clock (WDCLK) prescaler. The +//! \e prescaler parameter divides INTOSC1 down to WDCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler) +{ + uint16_t regVal; + + regVal = (uint16_t)prescaler | (uint16_t)SYSCTL_WD_CHKBITS; + + EALLOW; + + // + // Write the prescaler to the appropriate register. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~(SYSCTL_WDCR_WDPS_M)) | regVal; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the watchdog counter value. +//! +//! \return Returns the current value of the 8-bit watchdog counter. If this +//! count value overflows, a watchdog output pulse is generated. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getWatchdogCounterValue(void) +{ + // + // Read and return the value of the watchdog counter. + // + return(HWREGH(WD_BASE + SYSCTL_O_WDCNTR)); +} + +//***************************************************************************** +// +//! Gets the watchdog reset status. +//! +//! This function returns the watchdog reset status. If this function returns +//! \b true, that indicates that a watchdog reset generated the last reset +//! condition. Otherwise, it was an external device or power-up reset +//! condition. +//! +//! \return Returns \b true if the watchdog generated the last reset condition. +// +//***************************************************************************** +static inline bool +SysCtl_getWatchdogResetStatus(void) +{ + // + // Read and return the status of the watchdog reset status flag. + // + return((HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) & SYSCTL_RESC_WDRSN) != 0U); +} + +//***************************************************************************** +// +//! Clears the watchdog reset status. +//! +//! This function clears the watchdog reset status. To check if it was set +//! first, see SysCtl_getWatchdogResetStatus(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogResetStatus(void) +{ + EALLOW; + + // + // Read and return the status of the watchdog reset status flag. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) = SYSCTL_RESC_WDRSN; + + EDIS; +} + +//***************************************************************************** +// +//! Set the minimum threshold value for windowed watchdog +//! +//! \param value is the value to set the window threshold +//! +//! This function sets the minimum threshold value used to define the lower +//! limit of the windowed watchdog functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogWindowValue(uint16_t value) +{ + EALLOW; + + // + // Clear the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) &= ~SYSCTL_WDWCR_MIN_M; + + // + // Set the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) |= (value & SYSCTL_WDWCR_MIN_M); + + EDIS; +} + +//***************************************************************************** +// +//! Clears the watchdog override. +//! +//! This function clears the watchdog override and locks the watchdog timer +//! module to remain in its prior state which could be either enable /disable. +//! The watchdog timer will remain in this state until the next system reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogOverride(void) +{ + EALLOW; + + HWREGH(WD_BASE + SYSCTL_O_SCSR) |= SYSCTL_SCSR_WDOVERRIDE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the NMI Global interrupt bit +//! +//! \b Note: This bit should be set after the device security related +//! initialization is complete. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableNMIGlobalInterrupt(void) +{ + EALLOW; + + HWREGH(NMI_BASE + NMI_O_CFG) |= NMI_CFG_NMIE; + + EDIS; +} + +//***************************************************************************** +// +//! Read NMI interrupts. +//! +//! Read the current state of NMI interrupt. +//! +//! \return \b true if NMI interrupt is triggered, \b false if not. +// +//***************************************************************************** +static inline bool +SysCtl_getNMIStatus(void) +{ + // + // Read and return the current value of the NMI flag register, masking out + // all but the NMI bit. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & NMI_FLG_NMIINT) != 0U); +} + +//***************************************************************************** +// +//! Read NMI Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMIFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIFlagStatus(void) +{ + // + // Read and return the current value of the NMI flag register. + // + return(HWREGH(NMI_BASE + NMI_O_FLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI interrupts are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Function to clear individual NMI interrupts. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Clear NMI interrupt flags that correspond with the passed in bit mask. +//! +//! \b Note: The NMI Interrupt flag is always cleared by default and +//! therefore doesn't have to be included in the bit mask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearNMIStatus(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Clear the individual flags as well as NMI Interrupt flag + // + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Clear all the NMI Flags that are currently set. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearAllNMIFlags(void) +{ + uint16_t nmiFlags; + + // + // Read the flag status register and then write to the clear register, + // clearing all the flags that were returned plus the NMI flag. + // + EALLOW; + + nmiFlags = SysCtl_getNMIFlagStatus(); + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Function to force individual NMI interrupt fail flags +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_forceNMIFlags(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Set the Flags for the individual interrupts in the NMI flag + // force register + // + HWREGH(NMI_BASE + NMI_O_FLGFRC) |= nmiFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog counter value. +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns the NMI watchdog counter register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogCounter(void) +{ + // + // Read and return the NMI watchdog counter register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDCNT)); +} + +//***************************************************************************** +// +//! Sets the NMI watchdog period value. +//! +//! \param wdPeriod is the 16-bit value at which a reset is generated. +//! +//! This function writes to the NMI watchdog period register that holds the +//! value to which the NMI watchdog counter is compared. When the two registers +//! match, a reset is generated. By default, the period is 0xFFFF. +//! +//! \note If a value smaller than the current counter value is passed into the +//! \e wdPeriod parameter, a NMIRSn will be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod) +{ + EALLOW; + + // + // Write to the period register. + // + HWREGH(NMI_BASE + NMI_O_WDPRD) = wdPeriod; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog period value. +//! +//! \return Returns the NMI watchdog period register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogPeriod(void) +{ + // + // Read and return the NMI watchdog period register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDPRD)); +} + +//***************************************************************************** +// +//! Read NMI Shadow Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMISHDFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint32_t +SysCtl_getNMIShadowFlagStatus(void) +{ + // + // Read and return the current value of the NMI shadow flag register. + // + return(HWREGH(NMI_BASE + NMI_O_SHDFLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI shadow flags are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIShadowFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_SHDFLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Enable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_MCLKOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Get the missing clock detection Failure Status +//! +//! \note A failure means the oscillator clock is missing +//! +//! \return Returns \b true if a failure is detected or \b false if a +//! failure isn't detected +// +//***************************************************************************** +static inline bool +SysCtl_isMCDClockFailureDetected(void) +{ + // + // Check the status bit to determine failure + // + return((HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) & SYSCTL_MCDCR_MCLKSTS) != 0U); +} + +//***************************************************************************** +// +//! Reset the missing clock detection logic after clock failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Re-connect missing clock detection clock source to stop simulating clock +//! failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_connectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_OSCOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disconnect missing clock detection clock source to simulate clock failure. +//! This is for testing the MCD functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disconnectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_OSCOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the sync input source for the ePWM and eCAP signals. +//! +//! \param syncInput is the sync input being configured +//! \param syncSrc is sync input source selection. +//! +//! This function configures the sync input source for the ePWM and eCAP +//! modules. The \e syncInput parameter is the sync input being configured. It +//! should be passed a value of \b SYSCTL_SYNC_IN_XXXX, where XXXX is the ePWM +//! or eCAP instance the sync signal is entering. +//! +//! The \e syncSrc parameter is the sync signal selected as the source of the +//! sync input. It should be passed a value of \b SYSCTL_SYNC_IN_SRC_XXXX, +//! XXXX is a sync signal coming from an ePWM, eCAP or external sync output. +//! where For example, a \e syncInput value of \b SYSCTL_SYNC_IN_ECAP1 and a +//! \e syncSrc value of \b SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT will make the +//! EPWM1SYNCOUT signal drive eCAP1's SYNCIN signal. +//! +//! Note that some \e syncSrc values are only valid for certain values of +//! \e syncInput. See device technical reference manual for details on +//! time-base counter synchronization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncInputConfig(SysCtl_SyncInput syncInput, + SysCtl_SyncInputSource syncSrc) +{ + uint32_t clearMask; + + // + // Write the input sync source selection to the appropriate register. + // + EALLOW; + clearMask = (uint32_t)SYSCTL_SYNCSELECT_SYNCIN_M << (uint32_t)syncInput; + + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & ~clearMask) | + ((uint32_t)syncSrc << (uint32_t)syncInput); + + EDIS; +} +//***************************************************************************** +// +//! Configures the sync output source. +//! +//! \param syncSrc is sync output source selection. +//! +//! This function configures the sync output source from the ePWM modules. The +//! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is +//! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc) +{ + // + // Write the sync output source selection to the appropriate register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & + ~((uint32_t)SYSCTL_SYNCSELECT_SYNCOUT_M)) | + ((uint32_t)syncSrc << SYSCTL_SYNCSELECT_SYNCOUT_S); + EDIS; + +} +//***************************************************************************** +// +//! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be enabled +//! +//! This function configures which ePWM SOC signals are enabled as a source for +//! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR +//! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Set the bits that correspond to signal to be enabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) |= adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Disables ePWM SOC signals from driving an external ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be disabled +//! +//! This function configures which ePWM SOC signals are disabled as a source +//! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical +//! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Clear the bits that correspond to signal to be disabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) &= ~adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Locks the SOC Select of the Trig X-BAR. +//! +//! This function locks the external ADC SOC select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockExtADCSOCSelect(void) +{ + // + // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = + SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT; + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the dual ported bridge is connected with DMA or +//! CLA as the secondary controller. +//! +//! \param periFrame1Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 1. +//! \param periFrame2Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 2. +//! +//! One of the following values can be passed as parameter. +//! \b SYSCTL_SEC_CONTROLLER_CLA +//! \b SYSCTL_SEC_CONTROLLER_DMA +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectSecController(uint16_t periFrame1Config, uint16_t periFrame2Config) +{ + EALLOW; + + HWREG(CPUSYS_BASE + SYSCTL_O_SECMSEL) = + (((periFrame1Config << SYSCTL_SECMSEL_PF1SEL_S) & + SYSCTL_SECMSEL_PF1SEL_M) | + ((periFrame2Config << SYSCTL_SECMSEL_PF2SEL_S) & + SYSCTL_SECMSEL_PF2SEL_M)); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the Sync Select of the Trig X-BAR. +//! +//! This function locks Sync Input and Output Select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockSyncSelect(void) +{ + // + // Lock the SYNCSELECT register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = SYSCTL_SYNCSOCLOCK_SYNCSELECT; + EDIS; +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeriphInstance +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheralInstance(SysCtl_CPUSelPeriphInstance peripheral, + SysCtl_CPUSel cpuInst) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Identify the register index and bit position + // + regIndex = 2U * ((uint16_t)peripheral & SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Configure the CPU owner for the specified peripheral instance + // + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) = + (HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) & ~(1UL << bitIndex)) | + ((uint32_t)cpuInst << bitIndex); + + EDIS; + +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param peripheralInst is the instance for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! The \e peripheralInst parameter is the instance number for example +//! 1 for EPWM1, 2 for EPWM2 so on.For instances which are named with alphabets +//! (instead of numbers) the following convention needs to be followed. +//! 1 for A (SPI_A), 2 for B (SPI_B), 3 for C (SPI_C) so on... +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \note This function is retained for compatibility puposes. Recommended to +//! to use the function \e SysCtl_selectCPUForPeripheralInstance() +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheral(SysCtl_CPUSelPeripheral peripheral, + uint16_t peripheralInst, SysCtl_CPUSel cpuInst) +{ + uint32_t tempValue; + uint16_t shift; + + if(SYSCTL_CPUSEL14_DAC == peripheral) + { + shift = peripheralInst + SYSCTL_CPUSEL_DAC_S - 1U; + } + else + { + shift = peripheralInst - 1U; + } + + tempValue = + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) & + (~(1UL << shift)); + + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) = + tempValue | ((uint32_t)cpuInst << shift); + EDIS; +} +//***************************************************************************** +// +//! Get the Device Silicon Revision ID +//! +//! This function returns the silicon revision ID for the device. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the silicon revision ID value. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceRevision(void) +{ + // + // Returns the device silicon revision ID + // + return(HWREG(DEVCFG_BASE + SYSCTL_O_REVID)); +} + +//***************************************************************************** +// +//! Locks the CPU select registers for the peripherals +//! +//! \param peripheral is the peripheral for which CPU needs to be selected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockCPUSelectRegs(SysCtl_CPUSelPeripheral peripheral) +{ + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_DEVCFGLOCK1) |= (1UL << (uint32_t)peripheral); + EDIS; +} + + +//***************************************************************************** +// +//! Gets the error status of the Efuse +//! +//! The function provides both the Efuse Autoload & the Efuse Self Test +//! Error Status. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Fuse Error status. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getEfuseError(void) +{ + return(HWREGH(DEVCFG_BASE + SYSCTL_O_FUSEERR)); +} + +//***************************************************************************** +// +//! Sets up XCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the XCLK divider. There is only one +//! divider that scales INTOSC1 to XCLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_XClkDivider +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setXClk(SysCtl_XClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) & + ~(SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M)) | + (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up PLLSYSCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the PLLSYSCLK divider. There is only one +//! divider that scales PLLSYSCLK to generate the system clock. +//! +//! The \e divider parameter can have one value from the set below: +//! 0x0 = /1 +//! 0x1 = /2 +//! 0x2 = /4 (default on reset) +//! 0x3 = /6 +//! 0x4 = /8 +//! ...... +//! 0x3F =/126 +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setPLLSysClk(uint16_t divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)) | divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up AUXPLLCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the AUXPLLCLK divider. There is only one +//! divider that scales AUXPLLCLK to generate the system clock. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_AuxPLLClkDivider +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setAuxPLLClk(SysCtl_AuxPLLClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + ~(SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up CPU Timer 2 CLK source & divider. +//! +//! \param divider is the value that configures the divider. +//! \param source is the source for the clock divider +//! +//! This function sets up the CPU Timer 2 CLK divider based on the source that +//! is selected. There is only one divider that scales the "source" to +//! CPU Timer 2 CLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkDivider +//! The \e source parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkSource +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setCputimer2Clk(SysCtl_Cputimer2ClkDivider divider, + SysCtl_Cputimer2ClkSource source) +{ + // + // Clears the divider & the source, then configures it. + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~(SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M | + SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M)); + SYSCTL_REGWRITE_DELAY; + + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= + ((uint16_t)divider << SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S) | + ((uint16_t)source << SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S); + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Gets the PIE Vector Fetch Error Handler Routine Address. +//! +//! The function indicates the address of the PIE Vector Fetch Error +//! handler routine. +//! +//! \return Error Handler Address. +//! +//! \note Its the responsibility of user to initialize this register. If this +//! register is not initialized, a default error handler at address +//! 0x3fffbe will get executed. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getPIEVErrAddr(void) +{ + return(HWREG(CPUSYS_BASE + SYSCTL_O_PIEVERRADDR)); +} + +//***************************************************************************** +// +//! Check if the Internal PHY is present or not for the USB module +//! +//! Provides the USB module Internal PHY presence +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return \b true if Internal USB PHY Module is present \b false if +//! Internal USB PHY Module is not present +// +//***************************************************************************** +static inline bool +SysCtl_isPresentUSBPHY(void) +{ + return((HWREG(DEVCFG_BASE + SYSCTL_O_PERCNF1) & + SYSCTL_PERCNF1_USB_A_PHY) != 0U); +} + +//***************************************************************************** +// +//! Get the device UID_UNIQUE value +//! +//! This function returns the device UID_UNIQUE value +//! +//! \return Returns the device UID_UNIQUE value +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceUID(void) +{ + // + // Returns the device UID_UNIQUE value + // + return(HWREG(UID_BASE + OTP_O_UID_UNIQUE)); +} + +//***************************************************************************** +// +//! Delays for a fixed number of cycles. +//! +//! \param count is the number of delay loop iterations to perform. +//! +//! This function generates a constant length delay using assembly code. The +//! loop takes 5 cycles per iteration plus 9 cycles of overhead. +//! +//! \note If count is equal to zero, the loop will underflow and run for a +//! very long time. +//! +//! \note Refer to the macro DEVICE_DELAY_US(x) in device.h which can be used to +//! insert a delay in microseconds. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_delay(uint32_t count); + +//***************************************************************************** +// +//! Calculates the system clock frequency (SYSCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the system clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the PLL +//! and clock divider configuration registers. +//! +//! \return Returns the system clock frequency. If a missing clock is detected, +//! the function will return the INTOSC1 frequency. This needs to be +//! corrected and cleared (see SysCtl_resetMCD()) before trying to call this +//! function again. +// +//***************************************************************************** +extern uint32_t +SysCtl_getClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Calculates the system auxiliary clock frequency (AUXPLLCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source +//! (AUXOSCCLK). +//! +//! This function determines the frequency of the auxiliary clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the AUXPLL +//! and clock divider configuration registers. +//! +//! \return Returns the auxiliary clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getAuxClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Configures the clocking of the device. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x) +//! where x is either 1 or an even value up to 126. +//! +//! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or +//! \b SYSCTL_PLL_DISABLE. +//! +//! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value +//! from 1 to 127. +//! +//! - The fractional multiplier is chosen with either \b SYSCTL_FMULT_0, +//! \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or \b SYSCTL_FMULT_3_4. +//! +//! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2, +//! \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! This function uses the watchdog as a monitor for the PLL. The user +//! watchdog settings will be modified and restored upon completion. Make sure +//! that the WDOVERRIDE bit isn't set before calling this function. Re-lock +//! attempt is carried out if either SLIP condition occurs or SYSCLK to input +//! clock ratio is off by 10%. +//! +//! This function uses the following resources to support PLL initialization: +//! - Watchdog +//! - CPU Timer 1 +//! - CPU Timer 2 +//! +//! +//! \note See your device errata for more details about locking the PLL. +//! +//! \return Returns \b false if a missing clock error is detected. This needs +//! to be cleared (see SysCtl_resetMCD()) before trying to call this function +//! again. Otherwise, returns \b true. +// +//***************************************************************************** +extern bool +SysCtl_setClock(uint32_t config); + +//***************************************************************************** +// +//! Configures the external oscillator for the clocking of the device. +//! +//! This function configures the external oscillator (XTAL) to be used for the +//! clocking of the device in crystal mode. It follows the procedure to turn on +//! the oscillator, wait for it to power up, and select it as the source of the +//! system clock. +//! +//! Please note that this function blocks while it waits for the XTAL to power +//! up. If the XTAL does not manage to power up properly, the function will +//! loop for a long time. It is recommended that you modify this function to +//! add an appropriate timeout and error-handling procedure. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectXTAL(void); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the clocking of the device. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! device. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSource(uint32_t oscSource); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the AUXPLL. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! AUXPLL. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource); + +//***************************************************************************** +// +//! Calculates the low-speed peripheral clock frequency (LSPCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the low-speed peripheral clock +//! based on the frequency of the oscillator clock source (from \e clockInHz) +//! and the PLL and clock divider configuration registers. +//! +//! \return Returns the low-speed peripheral clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Get the device part parametric value +//! +//! \param parametric is the requested device parametric value +//! +//! This function gets the device part parametric value. +//! +//! The \e parametric parameter can have one the following enumerated values: +//! - \b SYSCTL_DEVICE_QUAL - Device Qualification Status +//! - \b SYSCTL_DEVICE_PINCOUNT - Device Pin Count +//! - \b SYSCTL_DEVICE_INSTASPIN - Device InstaSPIN Feature Set +//! - \b SYSCTL_DEVICE_FLASH - Device Flash size (KB) +//! - \b SYSCTL_DEVICE_PARTID - Device Part ID Format Revision +//! - \b SYSCTL_DEVICE_FAMILY - Device Family +//! - \b SYSCTL_DEVICE_PARTNO - Device Part Number +//! - \b SYSCTL_DEVICE_CLASSID - Device Class ID +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the specified parametric value. +// +//***************************************************************************** +extern uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric); + +//***************************************************************************** +// +//! Configures the auxiliary PLL for clocking USB. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clock source for auxiliary PLL, the integer +//! multiplier, fractional multiplier and divider. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with one of the following macros: +//! \b SYSCTL_AUXPLL_DIV_1, +//! \b SYSCTL_AUXPLL_DIV_2, +//! \b SYSCTL_AUXPLL_DIV_4, +//! \b SYSCTL_AUXPLL_DIV_8 +//! +//! - The use of the PLL is chosen with either \b SYSCTL_AUXPLL_ENABLE or +//! \b SYSCTL_AUXPLL_DISABLE. +//! +//! - The integer multiplier is chosen with \b SYSCTL_AUXPLL_IMULT(x) where x +//! is a value from 1 to 127. +//! +//! - The oscillator source chosen with one of +//! \b SYSCTL_AUXPLL_OSCSRC_OSC2, +//! \b SYSCTL_AUXPLL_OSCSRC_XTAL, +//! \b SYSCTL_AUXPLL_OSCSRC_AUXCLKIN, +//! +//! \note This function uses CPU Timer 2 to monitor a successful lock of the +//! AUXPLL. For this function to properly detect the PLL startup +//! SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +//! User configuration of CPU Timer 2 will be backed up and restored. +//! \note See your device errata for more details about locking the PLL. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_setAuxClock(uint32_t config); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//**************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SYSCTL_H diff --git a/gpio_driverlib_cpu2/device/driverlib/upp.c b/gpio_driverlib_cpu2/device/driverlib/upp.c new file mode 100644 index 0000000..a3fb8da --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/upp.c @@ -0,0 +1,298 @@ +//########################################################################### +// +// FILE: upp.c +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "upp.h" + +//***************************************************************************** +// +// UPP_setDMAReadThreshold +// +//***************************************************************************** +void +UPP_setDMAReadThreshold(uint32_t base, UPP_DMAChannel channel, + UPP_ThresholdSize size) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Set DMA read threshold for channel I. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEI_M) | + (uint16_t)size; + } + else + { + // + // Set DMA read threshold for channel Q. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEQ_M) | + ((uint16_t)size << UPP_THCFG_RDSIZEQ_S); + } +} + +//***************************************************************************** +// +// UPP_setDMADescriptor +// +//***************************************************************************** +void +UPP_setDMADescriptor(uint32_t base, UPP_DMAChannel channel, + const UPP_DMADescriptor * const desc) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Sets DMA descriptors for channel I. + // + HWREG(base + UPP_O_CHIDESC0) = desc->addr; + HWREG(base + UPP_O_CHIDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHIDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHIDESC2) = desc->lineOffset; + } + else + { + // + // Sets DMA descriptors for channel Q. + // + HWREG(base + UPP_O_CHQDESC0) = desc->addr; + HWREG(base + UPP_O_CHQDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHQDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHQDESC2) = desc->lineOffset; + } +} + +//***************************************************************************** +// +// UPP_getDMAChannelStatus +// +//***************************************************************************** +void +UPP_getDMAChannelStatus(uint32_t base, UPP_DMAChannel channel, + UPP_DMAChannelStatus * const status) +{ + uint32_t cntStatus; + + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the current status for channel I. + // + cntStatus = HWREG(base + UPP_O_CHIST1); + status->curAddr = HWREG(base + UPP_O_CHIST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHIDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHIDESC1_LCNT_S); + } + else + { + // + // Return the current status for channel Q. + // + cntStatus = HWREG(base + UPP_O_CHQST1); + status->curAddr = HWREG(base + UPP_O_CHQST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHQDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHQDESC1_LCNT_S); + } +} + +//***************************************************************************** +// +// UPP_isDescriptorPending +// +//***************************************************************************** +bool +UPP_isDescriptorPending(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the pend status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_PEND) == UPP_CHIST2_PEND); + } + else + { + // + // Return the pend status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_PEND) == UPP_CHQST2_PEND); + } + return(status); +} + +//***************************************************************************** +// +// UPP_isDescriptorActive +// +//***************************************************************************** +bool +UPP_isDescriptorActive(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Returns active status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_ACT) == UPP_CHIST2_ACT); + } + else + { + // + // Returns active status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_ACT) == UPP_CHQST2_ACT); + } + return(status); +} + +//***************************************************************************** +// +// UPP_getDMAFIFOWatermark +// +//***************************************************************************** +uint16_t +UPP_getDMAFIFOWatermark(uint32_t base, UPP_DMAChannel channel) +{ + uint16_t status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_WM_M) >> UPP_CHIST2_WM_S); + } + else + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_WM_M) >> UPP_CHQST2_WM_S); + } + return(status); +} + +//***************************************************************************** +// +// UPP_readRxMsgRAM +// +//***************************************************************************** +void +UPP_readRxMsgRAM(uint32_t rxBase, uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isRxBaseValid(rxBase)); + ASSERT((length + offset) < UPP_RX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Read one 16-bit word. + // + array[i] = HWREGH(rxBase + offset + i); + } +} + +//***************************************************************************** +// +// UPP_writeTxMsgRAM +// +//***************************************************************************** +void +UPP_writeTxMsgRAM(uint32_t txBase, const uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isTxBaseValid(txBase)); + ASSERT((length + offset) < UPP_TX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Write one 16-bit word. + // + HWREGH(txBase + offset + i) = array[i]; + } +} diff --git a/gpio_driverlib_cpu2/device/driverlib/upp.h b/gpio_driverlib_cpu2/device/driverlib/upp.h new file mode 100644 index 0000000..128d077 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/upp.h @@ -0,0 +1,1574 @@ +//########################################################################### +// +// FILE: upp.h +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef UPP_H +#define UPP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup upp_api UPP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_upp.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines that can be passed as addr field of UPP_DMADescriptor to +// UPP_setDMADescriptor(). Since the addresses for Tx & Rx MSG RAMs are +// different for CPU & DMA views, these defines can be used as DMA descriptor +// addresses. +// +//***************************************************************************** +#define UPP_DMA_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_DMA_RX_MSGRAM_STARTADDR 0x00007000U + +//***************************************************************************** +// +// Defines that can be used in user program as start address for CPU/CLA write +// to TX MSG RAM for transmitting data & for CPU/CLA read from RX MSG RAM for +// receiving data. Since the addresses for Tx & Rx MSG RAMs are different for +// CPU & DMA views, these defines can be used for CPU read/writes. +// +//***************************************************************************** +#define UPP_CPU_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_CPU_RX_MSGRAM_STARTADDR UPP_RX_MSG_RAM_BASE + +//***************************************************************************** +// +// Defines to specify the size of the uPP Tx and Rx MSG RAMs. +// +//***************************************************************************** +#define UPP_TX_MSGRAM_MAX_SIZE 0x200U +#define UPP_RX_MSGRAM_MAX_SIZE 0x200U + +//***************************************************************************** +// +// Define to specify 32 cycle delay between software reset issue & release in +// UPP_performSoftReset(). +// +//***************************************************************************** +#ifndef UPP_32_CYCLE_NOP +#define UPP_32_CYCLE_NOP __asm(" RPT #31 || NOP") +#endif + +//***************************************************************************** +// +// Define to specify mask for setting emulation mode in UPP_setEmulationMode(). +// +//***************************************************************************** +#define UPP_SOFT_FREE_M ((uint16_t)UPP_PERCTL_SOFT | \ + (uint16_t)UPP_PERCTL_FREE) + +//***************************************************************************** +// +// Defines to specify masks for enabling/disabling uPP Tx/Rx control signals in +// UPP_setTxControlSignalMode() & UPP_setRxControlSignalMode() respectively. +// +//***************************************************************************** +#define UPP_TX_SIGNAL_MODE_M UPP_IFCFG_WAITA +#define UPP_RX_SIGNAL_MODE_M ((uint16_t)UPP_IFCFG_STARTA | \ + (uint16_t)UPP_IFCFG_ENAA) + +//***************************************************************************** +// +// Define to specify mask for configuring polarities for uPP control signals +// in UPP_setControlSignalPolarity(). +// +//***************************************************************************** +#define UPP_SIGNAL_POLARITY_M ((uint16_t)UPP_IFCFG_WAITPOLA | \ + (uint16_t)UPP_IFCFG_ENAPOLA | \ + (uint16_t)UPP_IFCFG_STARTPOLA) + +//***************************************************************************** +// +// Define to specify masks for returning interrupt status in +// UPP_getInterruptStatus() & UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_M ((uint16_t)UPP_ENINTST_DPEI | (uint16_t)UPP_ENINTST_UOEI | \ + (uint16_t)UPP_ENINTST_EOWI | (uint16_t)UPP_ENINTST_EOLI | \ + (uint16_t)UPP_ENINTST_DPEQ | (uint16_t)UPP_ENINTST_UOEQ | \ + (uint16_t)UPP_ENINTST_EOWQ | (uint16_t)UPP_ENINTST_EOLQ) + +//***************************************************************************** +// +// Values that can be passed to UPP_enableInterrupt(), +// UPP_disableInterrupt() and UPP_clearInterruptStatus() as the +// intFlags parameter and returned by UPP_getInterruptStatus() & +// UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_CHI_DMA_PROG_ERR 0x0001U //! +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "debug.h" +#include "sysctl.h" +#include "usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16U + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16U + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10U) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0U) || (ui32Endpoint == 1U) || (ui32Endpoint == 2U) || + (ui32Endpoint == 3U)); + ASSERT((ui32Size == 1U) || (ui32Size == 2U)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint8_t ui8Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1U) + { + // + // Get the value. + // + ui8Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui8Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui8Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USBA_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0U; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = 0U; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0U); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0U; + *pui32IntStatusEP = 0U; + uint32_t usbis = 0U; + uint32_t rxis = 0U; + uint32_t txis = 0U; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Do-While to make sure that all status registers are cleared before + // continuing. This eliminates the race condition which can cause the USB + // interrupt to stay high and never get triggered again. + // + do + { + // + // Get the general interrupt status. + // + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + + // + // Get the transmit interrupt status. + // + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + + // + // Get the receive interrupt status. + // + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // + // Get the general interrupt status, these bits go into the lower 8 bits + // of the returned value. + // + ui32Status |= usbis; + + // + // Get the transmit interrupt status. + // + *pui32IntStatusEP |= txis; + + // + // Get the receive interrupt status, these bits go into the second byte + // of the returned value. + // + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while((usbis != 0x0000U) || (txis != 0x0000U) || (rxis != 0x0000U)); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << + USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) + << USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0U); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + if((pui32Flags != NULL) && (pui32MaxPacketSize != NULL)) + { + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size + // has been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change. If they decode the returned mode, however, they + // may be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size + // max packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change.If they decode the returned mode, however, they may + // be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOSZ, 1U); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOSZ, 1U); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a given endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0U); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0U; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xFFU; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8U) & 0xFFU; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0U); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0U) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0U); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16U; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2U)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = (uint32_t)0xFU << (ui32Channel * 4U); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4U); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0U; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4U * (USBEPToIndex(ui32Endpoint) - 1U))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(15U); +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/usb.h b/gpio_driverlib_cpu2/device/driverlib/usb.h new file mode 100644 index 0000000..ae3c7ad --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/usb.h @@ -0,0 +1,560 @@ +//########################################################################### +// +// FILE: usb.h +// +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef USB_H +#define USB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup usb_api USB +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001U +#define USB_ID_HOST 0x0002U +#define USB_ID_DEVICE 0x0000U +#define USB_PFLT_ACTIVE 0x0004U + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FFUL // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FFUL // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080UL // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040UL // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040UL // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020UL // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010UL // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008UL // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004UL // Babble signaled +#define USB_INTCTRL_RESET 0x00000004UL // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002UL // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001UL // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200UL // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100UL // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFFUL // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000UL // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000UL // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000UL // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000UL // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000UL // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000UL // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000UL // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000UL // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000UL // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000UL // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000UL // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000UL // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000UL // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000UL // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000UL // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000UL // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000UL // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000UL // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000UL // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000UL // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000UL // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000UL // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000UL // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000UL // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000UL // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000UL // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000UL // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000UL // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000UL // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000UL // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000UL // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000UL // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFEUL // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000UL // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000UL // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000UL // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000UL // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800UL // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400UL // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200UL // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100UL // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080UL // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040UL // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020UL // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010UL // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008UL // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004UL // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002UL // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFEUL // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000UL // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000UL // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000UL // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000UL // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800UL // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400UL // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200UL // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100UL // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080UL // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040UL // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020UL // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010UL // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008UL // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004UL // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002UL // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000UL // Current speed is undefined +#define USB_FULL_SPEED 0x00000001UL // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000UL // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000UL // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000UL // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000UL // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000UL // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000UL // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000UL // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000UL // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000UL // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFFUL // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080UL // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020UL // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004UL // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002UL // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001UL // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040UL // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010UL // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004UL // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001UL // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000UL // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000UL // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000UL // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000UL // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000UL // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080UL // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020UL // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004UL // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002UL // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001UL // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010UL // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004UL // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002UL // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001UL // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001UL // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002UL // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004UL // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008UL // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010UL // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000UL // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100UL // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200UL // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300UL // Control endpoint +#define USB_EP_MODE_MASK 0x00000300UL // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000UL // Low Speed +#define USB_EP_SPEED_FULL 0x00001000UL // Full Speed +#define USB_EP_HOST_IN 0x00000000UL // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000UL // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000UL // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000UL // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010UL +#define USB_HOST_PWRFLT_HIGH 0x00000030UL +#define USB_HOST_PWRFLT_EP_NONE 0x00000000UL +#define USB_HOST_PWRFLT_EP_TRI 0x00000140UL +#define USB_HOST_PWRFLT_EP_LOW 0x00000240UL +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340UL +#define USB_HOST_PWREN_MAN_LOW 0x00000000UL +#define USB_HOST_PWREN_MAN_HIGH 0x00000001UL +#define USB_HOST_PWREN_AUTOLOW 0x00000002UL +#define USB_HOST_PWREN_AUTOHIGH 0x00000003UL +#define USB_HOST_PWREN_FILTER 0x00010000UL + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64U + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000UL // Endpoint 0 +#define USB_EP_1 0x00000010UL // Endpoint 1 +#define USB_EP_2 0x00000020UL // Endpoint 2 +#define USB_EP_3 0x00000030UL // Endpoint 3 +#define USB_EP_4 0x00000040UL // Endpoint 4 +#define USB_EP_5 0x00000050UL // Endpoint 5 +#define USB_EP_6 0x00000060UL // Endpoint 6 +#define USB_EP_7 0x00000070UL // Endpoint 7 +#define USB_EP_8 0x00000080UL // Endpoint 8 +#define USB_EP_9 0x00000090UL // Endpoint 9 +#define USB_EP_10 0x000000A0UL // Endpoint 10 +#define USB_EP_11 0x000000B0UL // Endpoint 11 +#define USB_EP_12 0x000000C0UL // Endpoint 12 +#define USB_EP_13 0x000000D0UL // Endpoint 13 +#define USB_EP_14 0x000000E0UL // Endpoint 14 +#define USB_EP_15 0x000000F0UL // Endpoint 15 +#define NUM_USB_EP 16U // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) (((uint32_t)(x) << 4U) & 0xFFU) +#define USBEPToIndex(x) ((x) >> 4U) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000UL // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001UL // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002UL // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003UL // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004UL // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005UL // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006UL // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007UL // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008UL // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009UL // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010UL // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011UL // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012UL // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013UL // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014UL // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015UL // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016UL // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017UL // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018UL // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010UL +#define USBFIFOSizeToBytes(x) ((uint32_t)8U << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102UL // Normal OUT transaction +#define USB_TRANS_IN 0x00000102UL // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010AUL // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110AUL // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142UL // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001UL // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081UL // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080UL // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001DUL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009UL // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011UL // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009DUL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080UL // OTG controller mode is not set. + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +// +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0FUL // All Interrupt sources +#define USB_INT_STATUS 0xFF000000UL // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000UL // VBUS Error +#define USB_INT_SESSION_START 0x40000000UL // Session Start Detected +#define USB_INT_SESSION_END 0x20000000UL // Session End Detected +#define USB_INT_DISCONNECT 0x20000000UL // Disconnect Detected +#define USB_INT_CONNECT 0x10000000UL // Device Connect Detected +#define USB_INT_SOF 0x08000000UL // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000UL // Babble signaled +#define USB_INT_RESET 0x04000000UL // Reset signaled +#define USB_INT_RESUME 0x02000000UL // Resume detected +#define USB_INT_SUSPEND 0x01000000UL // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000UL // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000UL // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00UL // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00UL // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800UL // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400UL // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200UL // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800UL // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400UL // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200UL // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000EUL // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000EUL // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008UL // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004UL // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002UL // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008UL // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004UL // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002UL // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // USB_H diff --git a/gpio_driverlib_cpu2/device/driverlib/version.c b/gpio_driverlib_cpu2/device/driverlib/version.c new file mode 100644 index 0000000..ced29c1 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/version.c @@ -0,0 +1,54 @@ +//########################################################################### +// +// FILE: version.c +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "version.h" + +//***************************************************************************** +// +// Version_getLibVersion +// +//***************************************************************************** +uint32_t +Version_getLibVersion(void) +{ + return(VERSION_NUMBER); +} diff --git a/gpio_driverlib_cpu2/device/driverlib/version.h b/gpio_driverlib_cpu2/device/driverlib/version.h new file mode 100644 index 0000000..8a3b431 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/version.h @@ -0,0 +1,101 @@ +//########################################################################### +// +// FILE: version.h +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef VERSION_H +#define VERSION_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup version_api Version +//! @{ +// +//***************************************************************************** +#include + +//! Version number to be returned by Version_getLibVersion() +//! +#define VERSION_NUMBER 26000000U + +//***************************************************************************** +// +//! Returns the driverlib version number +//! +//! This function can be used to check the version number of the driverlib.lib +//! that is in use. The version number will take the format yy.mm.pp.bb, so for +//! yy-Year, mm-Major Release version, pp-Patch Release Version, bb- Build Number. +//! example, if the function returns 26000000, the driverlib version being used +//! is 26.00.00.00. +//! +//! \return Returns an integer value indicating the driverlib version. +// +//***************************************************************************** +extern uint32_t +Version_getLibVersion(void); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // VERSION_H diff --git a/gpio_driverlib_cpu2/device/driverlib/xbar.c b/gpio_driverlib_cpu2/device/driverlib/xbar.c new file mode 100644 index 0000000..008145a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/xbar.c @@ -0,0 +1,255 @@ +//########################################################################### +// +// FILE: xbar.c +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "xbar.h" + +//***************************************************************************** +// +// XBAR_setOutputMuxConfig +// +//***************************************************************************** +void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)output << 1U) + 2U; + } + else + { + offset = (uint16_t)output << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR output. + // + EALLOW; + + HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) = + (HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) & + ~((uint32_t)0x3U << shift)) | + (((uint32_t)muxConfig & 0x3U) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setEPWMMuxConfig +// +//***************************************************************************** +void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)trip << 1U) + 2U; + } + else + { + offset = (uint16_t)trip << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR trip. + // + EALLOW; + + HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setCLBMuxConfig +// +//***************************************************************************** +void +XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, XBAR_CLBMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)auxSignal << 1U) + 2U; + } + else + { + offset = (uint16_t)auxSignal << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR auxSignal. + // + EALLOW; + + + HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_getInputFlagStatus +// +//***************************************************************************** +bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_FLG1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_FLG2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_FLG3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Get the status of the X-BAR input latch. + // + inputMask = (uint32_t)1U << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + + return((HWREG(XBAR_BASE + offset) & inputMask) != 0U); +} + +//***************************************************************************** +// +// XBAR_clearInputFlag +// +//***************************************************************************** +void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag clear register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_CLR1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_CLR2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_CLR3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Set the bit that clears the X-BAR input latch. + // + inputMask = 1UL << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + HWREG(XBAR_BASE + offset) = inputMask; +} diff --git a/gpio_driverlib_cpu2/device/driverlib/xbar.h b/gpio_driverlib_cpu2/device/driverlib/xbar.h new file mode 100644 index 0000000..02e4e68 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/xbar.h @@ -0,0 +1,1294 @@ +//########################################################################### +// +// FILE: xbar.h +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef XBAR_H +#define XBAR_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup xbar_api XBAR +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clbxbar.h" +#include "inc/hw_epwmxbar.h" +#include "inc/hw_inputxbar.h" +#include "inc/hw_outputxbar.h" +#include "inc/hw_xbar.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. +// Not intended for use by application code. +// +//***************************************************************************** +#define XBAR_OUTPUT_CFG_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUX0TO15CFG) +#define XBAR_OUTPUT_EN_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUXENABLE) +#define XBAR_EPWM_CFG_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUX0TO15CFG) +#define XBAR_EPWM_EN_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUXENABLE) +#define XBAR_CLB_CFG_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUX0TO15CFG) +#define XBAR_CLB_EN_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUXENABLE) +#define XBAR_INPUT_BASE (INPUTXBAR_BASE + XBAR_O_INPUT1SELECT) + +#define XBAR_INPUT_FLG_INPUT_M 0x00FFU +#define XBAR_INPUT_FLG_REG_M 0xFF00U +#define XBAR_INPUT_FLG_REG_1 0x0000U +#define XBAR_INPUT_FLG_REG_2 0x0100U +#define XBAR_INPUT_FLG_REG_3 0x0200U + +#define XBAR_GPIO_MAX_CNT 168U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following values define the muxes parameter for XBAR_enableEPWMMux(), +// XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and +// XBAR_disableOutputMux(). +// +//***************************************************************************** +#define XBAR_MUX00 0x00000001U //!< Mask for X-BAR mux 0 +#define XBAR_MUX01 0x00000002U //!< Mask for X-BAR mux 1 +#define XBAR_MUX02 0x00000004U //!< Mask for X-BAR mux 2 +#define XBAR_MUX03 0x00000008U //!< Mask for X-BAR mux 3 +#define XBAR_MUX04 0x00000010U //!< Mask for X-BAR mux 4 +#define XBAR_MUX05 0x00000020U //!< Mask for X-BAR mux 5 +#define XBAR_MUX06 0x00000040U //!< Mask for X-BAR mux 6 +#define XBAR_MUX07 0x00000080U //!< Mask for X-BAR mux 7 +#define XBAR_MUX08 0x00000100U //!< Mask for X-BAR mux 8 +#define XBAR_MUX09 0x00000200U //!< Mask for X-BAR mux 9 +#define XBAR_MUX10 0x00000400U //!< Mask for X-BAR mux 10 +#define XBAR_MUX11 0x00000800U //!< Mask for X-BAR mux 11 +#define XBAR_MUX12 0x00001000U //!< Mask for X-BAR mux 12 +#define XBAR_MUX13 0x00002000U //!< Mask for X-BAR mux 13 +#define XBAR_MUX14 0x00004000U //!< Mask for X-BAR mux 14 +#define XBAR_MUX15 0x00008000U //!< Mask for X-BAR mux 15 +#define XBAR_MUX16 0x00010000U //!< Mask for X-BAR mux 16 +#define XBAR_MUX17 0x00020000U //!< Mask for X-BAR mux 17 +#define XBAR_MUX18 0x00040000U //!< Mask for X-BAR mux 18 +#define XBAR_MUX19 0x00080000U //!< Mask for X-BAR mux 19 +#define XBAR_MUX20 0x00100000U //!< Mask for X-BAR mux 20 +#define XBAR_MUX21 0x00200000U //!< Mask for X-BAR mux 21 +#define XBAR_MUX22 0x00400000U //!< Mask for X-BAR mux 22 +#define XBAR_MUX23 0x00800000U //!< Mask for X-BAR mux 23 +#define XBAR_MUX24 0x01000000U //!< Mask for X-BAR mux 24 +#define XBAR_MUX25 0x02000000U //!< Mask for X-BAR mux 25 +#define XBAR_MUX26 0x04000000U //!< Mask for X-BAR mux 26 +#define XBAR_MUX27 0x08000000U //!< Mask for X-BAR mux 27 +#define XBAR_MUX28 0x10000000U //!< Mask for X-BAR mux 28 +#define XBAR_MUX29 0x20000000U //!< Mask for X-BAR mux 29 +#define XBAR_MUX30 0x40000000U //!< Mask for X-BAR mux 30 +#define XBAR_MUX31 0x80000000U //!< Mask for X-BAR mux 31 +#endif + +//***************************************************************************** +// +//! The following values define the \e output parameter for +//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and +//! XBAR_disableOutputMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR + XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR + XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR + XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR + XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR + XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR + XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR + XBAR_OUTPUT8 = 14, //!< OUTPUT8 of the Output X-BAR +} XBAR_OutputNum; + +//***************************************************************************** +// +//! The following values define the \e trip parameter for +//! XBAR_setEPWMMuxConfig(), XBAR_invertEPWMSignal(), XBAR_enableEPWMMux(), +//! and XBAR_disableEPWMMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR + XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR + XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR + XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR + XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR + XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR + XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR + XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR +} XBAR_TripNum; + +//***************************************************************************** +// +// The following values define the trip parameter for XBAR_setCLBMuxConfig(), +// XBAR_enableCLBMux(), and XBAR_disableCLBMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_AUXSIG0 = 0, + XBAR_AUXSIG1 = 2, + XBAR_AUXSIG2 = 4, + XBAR_AUXSIG3 = 6, + XBAR_AUXSIG4 = 8, + XBAR_AUXSIG5 = 10, + XBAR_AUXSIG6 = 12, + XBAR_AUXSIG7 = 14 +} XBAR_AuxSigNum; + +//***************************************************************************** +// +//! The following values define the \e input parameter for XBAR_setInputPin(). +// +//***************************************************************************** +typedef enum +{ + XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs + XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs + XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs + XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1 + XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2 + XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3 + XBAR_INPUT7, //!< eCAP1, X-BARs + XBAR_INPUT8, //!< eCAP2, X-BARs + XBAR_INPUT9, //!< eCAP3, X-BARs + XBAR_INPUT10, //!< eCAP4, X-BARs + XBAR_INPUT11, //!< eCAP5, X-BARs + XBAR_INPUT12, //!< eCAP6, X-BARs + XBAR_INPUT13, //!< XINT4, X-BARs + XBAR_INPUT14 //!< XINT5, X-BARs +} XBAR_InputNum; + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setOutputMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + // + //OUTPUTXBAR + // + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000, + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001, + XBAR_OUT_MUX00_ADCAEVT1 = 0x0002, + XBAR_OUT_MUX00_ECAP1_OUT = 0x0003, + XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200, + XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201, + XBAR_OUT_MUX01_CLB1_OUT4 = 0x0202, + XBAR_OUT_MUX01_ADCCEVT1 = 0x0203, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401, + XBAR_OUT_MUX02_ADCAEVT2 = 0x0402, + XBAR_OUT_MUX02_ECAP2_OUT = 0x0403, + XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600, + XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601, + XBAR_OUT_MUX03_CLB1_OUT5 = 0x0602, + XBAR_OUT_MUX03_ADCCEVT2 = 0x0603, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801, + XBAR_OUT_MUX04_ADCAEVT3 = 0x0802, + XBAR_OUT_MUX04_ECAP3_OUT = 0x0803, + XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00, + XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_OUT_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01, + XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02, + XBAR_OUT_MUX06_ECAP4_OUT = 0x0C03, + XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00, + XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_OUT_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH = 0x1000, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L = 0x1001, + XBAR_OUT_MUX08_ADCBEVT1 = 0x1002, + XBAR_OUT_MUX08_ECAP5_OUT = 0x1003, + XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL = 0x1200, + XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201, + XBAR_OUT_MUX09_CLB3_OUT4 = 0x1202, + XBAR_OUT_MUX09_ADCDEVT1 = 0x1203, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH = 0x1400, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L = 0x1401, + XBAR_OUT_MUX10_ADCBEVT2 = 0x1402, + XBAR_OUT_MUX10_ECAP6_OUT = 0x1403, + XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL = 0x1600, + XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601, + XBAR_OUT_MUX11_CLB3_OUT5 = 0x1602, + XBAR_OUT_MUX11_ADCDEVT2 = 0x1603, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH = 0x1800, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L = 0x1801, + XBAR_OUT_MUX12_ADCBEVT3 = 0x1802, + XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL = 0x1A00, + XBAR_OUT_MUX13_ADCSOCA = 0x1A01, + XBAR_OUT_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_OUT_MUX13_ADCDEVT3 = 0x1A03, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH = 0x1C00, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH_OR_L = 0x1C01, + XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02, + XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_OUT_MUX15_CMPSS8_CTRIPOUTL = 0x1E00, + XBAR_OUT_MUX15_ADCSOCB = 0x1E01, + XBAR_OUT_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_OUT_MUX15_ADCDEVT4 = 0x1E03, + XBAR_OUT_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_OUT_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_OUT_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_OUT_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_OUT_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_OUT_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_OUT_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_OUT_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_OUT_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_OUT_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_OUT_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_OUT_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_OUT_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_OUT_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_OUT_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_OUT_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_OUT_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_OUT_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_OUT_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_OUT_MUX31_SD2FLT4_COMPL = 0x3E00, + +} XBAR_OutputMuxConfig; + +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setEPWMMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_EPWM_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_EPWM_MUX00_ADCAEVT1 = 0x0002, + XBAR_EPWM_MUX00_ECAP1_OUT = 0x0003, + XBAR_EPWM_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_EPWM_MUX01_INPUTXBAR1 = 0x0201, + XBAR_EPWM_MUX01_CLB1_OUT4 = 0x0202, + XBAR_EPWM_MUX01_ADCCEVT1 = 0x0203, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_EPWM_MUX02_ADCAEVT2 = 0x0402, + XBAR_EPWM_MUX02_ECAP2_OUT = 0x0403, + XBAR_EPWM_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_EPWM_MUX03_INPUTXBAR2 = 0x0601, + XBAR_EPWM_MUX03_CLB1_OUT5 = 0x0602, + XBAR_EPWM_MUX03_ADCCEVT2 = 0x0603, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_EPWM_MUX04_ADCAEVT3 = 0x0802, + XBAR_EPWM_MUX04_ECAP3_OUT = 0x0803, + XBAR_EPWM_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_EPWM_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_EPWM_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_EPWM_MUX05_ADCCEVT3 = 0x0A03, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_EPWM_MUX06_ADCAEVT4 = 0x0C02, + XBAR_EPWM_MUX06_ECAP4_OUT = 0x0C03, + XBAR_EPWM_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_EPWM_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_EPWM_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_EPWM_MUX07_ADCCEVT4 = 0x0E03, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_EPWM_MUX08_ADCBEVT1 = 0x1002, + XBAR_EPWM_MUX08_ECAP5_OUT = 0x1003, + XBAR_EPWM_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_EPWM_MUX09_INPUTXBAR5 = 0x1201, + XBAR_EPWM_MUX09_CLB3_OUT4 = 0x1202, + XBAR_EPWM_MUX09_ADCDEVT1 = 0x1203, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_EPWM_MUX10_ADCBEVT2 = 0x1402, + XBAR_EPWM_MUX10_ECAP6_OUT = 0x1403, + XBAR_EPWM_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_EPWM_MUX11_INPUTXBAR6 = 0x1601, + XBAR_EPWM_MUX11_CLB3_OUT5 = 0x1602, + XBAR_EPWM_MUX11_ADCDEVT2 = 0x1603, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_EPWM_MUX12_ADCBEVT3 = 0x1802, + XBAR_EPWM_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_EPWM_MUX13_ADCSOCA = 0x1A01, + XBAR_EPWM_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_EPWM_MUX13_ADCDEVT3 = 0x1A03, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_EPWM_MUX14_ADCBEVT4 = 0x1C02, + XBAR_EPWM_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_EPWM_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_EPWM_MUX15_ADCSOCB = 0x1E01, + XBAR_EPWM_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_EPWM_MUX15_ADCDEVT4 = 0x1E03, + XBAR_EPWM_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_EPWM_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_EPWM_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_EPWM_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_EPWM_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_EPWM_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_EPWM_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_EPWM_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_EPWM_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_EPWM_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_EPWM_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_EPWM_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_EPWM_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_EPWM_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_EPWM_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_EPWM_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_EPWM_MUX31_SD2FLT4_COMPL = 0x3E00 +} XBAR_EPWMMuxConfig; + +//***************************************************************************** +// +// The following values define the muxConfig parameter for +// XBAR_setCLBMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_CLB_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_CLB_MUX00_ADCAEVT1 = 0x0002, + XBAR_CLB_MUX00_ECAP1_OUT = 0x0003, + XBAR_CLB_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_CLB_MUX01_INPUTXBAR1 = 0x0201, + XBAR_CLB_MUX01_CLB1_OUT4 = 0x0202, + XBAR_CLB_MUX01_ADCCEVT1 = 0x0203, + XBAR_CLB_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_CLB_MUX02_ADCAEVT2 = 0x0402, + XBAR_CLB_MUX02_ECAP2_OUT = 0x0403, + XBAR_CLB_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_CLB_MUX03_INPUTXBAR2 = 0x0601, + XBAR_CLB_MUX03_CLB1_OUT5 = 0x0602, + XBAR_CLB_MUX03_ADCCEVT2 = 0x0603, + XBAR_CLB_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_CLB_MUX04_ADCAEVT3 = 0x0802, + XBAR_CLB_MUX04_ECAP3_OUT = 0x0803, + XBAR_CLB_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_CLB_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_CLB_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_CLB_MUX05_ADCCEVT3 = 0x0A03, + XBAR_CLB_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_CLB_MUX06_ADCAEVT4 = 0x0C02, + XBAR_CLB_MUX06_ECAP4_OUT = 0x0C03, + XBAR_CLB_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_CLB_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_CLB_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_CLB_MUX07_ADCCEVT4 = 0x0E03, + XBAR_CLB_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_CLB_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_CLB_MUX08_ADCBEVT1 = 0x1002, + XBAR_CLB_MUX08_ECAP5_OUT = 0x1003, + XBAR_CLB_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_CLB_MUX09_INPUTXBAR5 = 0x1201, + XBAR_CLB_MUX09_CLB3_OUT4 = 0x1202, + XBAR_CLB_MUX09_ADCDEVT1 = 0x1203, + XBAR_CLB_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_CLB_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_CLB_MUX10_ADCBEVT2 = 0x1402, + XBAR_CLB_MUX10_ECAP6_OUT = 0x1403, + XBAR_CLB_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_CLB_MUX11_INPUTXBAR6 = 0x1601, + XBAR_CLB_MUX11_CLB3_OUT5 = 0x1602, + XBAR_CLB_MUX11_ADCDEVT2 = 0x1603, + XBAR_CLB_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_CLB_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_CLB_MUX12_ADCBEVT3 = 0x1802, + XBAR_CLB_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_CLB_MUX13_ADCSOCA = 0x1A01, + XBAR_CLB_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_CLB_MUX13_ADCDEVT3 = 0x1A03, + XBAR_CLB_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_CLB_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_CLB_MUX14_ADCBEVT4 = 0x1C02, + XBAR_CLB_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_CLB_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_CLB_MUX15_ADCSOCB = 0x1E01, + XBAR_CLB_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_CLB_MUX15_ADCDEVT4 = 0x1E03, + XBAR_CLB_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_CLB_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_CLB_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_CLB_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_CLB_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_CLB_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_CLB_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_CLB_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_CLB_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_CLB_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_CLB_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_CLB_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_CLB_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_CLB_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_CLB_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_CLB_MUX31_SD2FLT4_COMPL = 0x3E00, +} XBAR_CLBMuxConfig; + + +//***************************************************************************** +// +//! The following values define the \e inputFlag parameter for +//! XBAR_getInputFlagStatus() and XBAR_clearInputFlag(). +// +//***************************************************************************** +typedef enum +{ + // + // XBARFLG1 + // + XBAR_INPUT_FLG_CMPSS1_CTRIPL = 0x0000, + XBAR_INPUT_FLG_CMPSS1_CTRIPH = 0x0001, + XBAR_INPUT_FLG_CMPSS2_CTRIPL = 0x0002, + XBAR_INPUT_FLG_CMPSS2_CTRIPH = 0x0003, + XBAR_INPUT_FLG_CMPSS3_CTRIPL = 0x0004, + XBAR_INPUT_FLG_CMPSS3_CTRIPH = 0x0005, + XBAR_INPUT_FLG_CMPSS4_CTRIPL = 0x0006, + XBAR_INPUT_FLG_CMPSS4_CTRIPH = 0x0007, + XBAR_INPUT_FLG_CMPSS5_CTRIPL = 0x0008, + XBAR_INPUT_FLG_CMPSS5_CTRIPH = 0x0009, + XBAR_INPUT_FLG_CMPSS6_CTRIPL = 0x000A, + XBAR_INPUT_FLG_CMPSS6_CTRIPH = 0x000B, + XBAR_INPUT_FLG_CMPSS7_CTRIPL = 0x000C, + XBAR_INPUT_FLG_CMPSS7_CTRIPH = 0x000D, + XBAR_INPUT_FLG_CMPSS8_CTRIPL = 0x000E, + XBAR_INPUT_FLG_CMPSS8_CTRIPH = 0x000F, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTL = 0x0018, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTH = 0x0019, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTL = 0x001A, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTH = 0x001B, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTL = 0x001C, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTH = 0x001D, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTL = 0x001E, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTH = 0x001F, + // + // XBARFLG2 + // + XBAR_INPUT_FLG_INPUT1 = 0x0100, + XBAR_INPUT_FLG_INPUT2 = 0x0101, + XBAR_INPUT_FLG_INPUT3 = 0x0102, + XBAR_INPUT_FLG_INPUT4 = 0x0103, + XBAR_INPUT_FLG_INPUT5 = 0x0104, + XBAR_INPUT_FLG_INPUT6 = 0x0105, + XBAR_INPUT_FLG_ADCSOCA = 0x0106, + XBAR_INPUT_FLG_ADCSOCB = 0x0107, + XBAR_INPUT_FLG_CLB1_OUT4 = 0x0108, + XBAR_INPUT_FLG_CLB1_OUT5 = 0x0109, + XBAR_INPUT_FLG_CLB2_OUT4 = 0x010A, + XBAR_INPUT_FLG_CLB2_OUT5 = 0x010B, + XBAR_INPUT_FLG_CLB3_OUT4 = 0x010C, + XBAR_INPUT_FLG_CLB3_OUT5 = 0x010D, + XBAR_INPUT_FLG_CLB4_OUT4 = 0x010E, + XBAR_INPUT_FLG_CLB4_OUT5 = 0x010F, + XBAR_INPUT_FLG_ECAP1_OUT = 0x0110, + XBAR_INPUT_FLG_ECAP2_OUT = 0x0111, + XBAR_INPUT_FLG_ECAP3_OUT = 0x0112, + XBAR_INPUT_FLG_ECAP4_OUT = 0x0113, + XBAR_INPUT_FLG_ECAP5_OUT = 0x0114, + XBAR_INPUT_FLG_ECAP6_OUT = 0x0115, + XBAR_INPUT_FLG_EXTSYNCOUT = 0x0116, + XBAR_INPUT_FLG_ADCAEVT1 = 0x0117, + XBAR_INPUT_FLG_ADCAEVT2 = 0x0118, + XBAR_INPUT_FLG_ADCAEVT3 = 0x0119, + XBAR_INPUT_FLG_ADCAEVT4 = 0x011A, + XBAR_INPUT_FLG_ADCBEVT1 = 0x011B, + XBAR_INPUT_FLG_ADCBEVT2 = 0x011C, + XBAR_INPUT_FLG_ADCBEVT3 = 0x011D, + XBAR_INPUT_FLG_ADCBEVT4 = 0x011E, + XBAR_INPUT_FLG_ADCCEVT1 = 0x011F, + // + // XBARFLG3 + // + XBAR_INPUT_FLG_ADCCEVT2 = 0x0200, + XBAR_INPUT_FLG_ADCCEVT3 = 0x0201, + XBAR_INPUT_FLG_ADCCEVT4 = 0x0202, + XBAR_INPUT_FLG_ADCDEVT1 = 0x0203, + XBAR_INPUT_FLG_ADCDEVT2 = 0x0204, + XBAR_INPUT_FLG_ADCDEVT3 = 0x0205, + XBAR_INPUT_FLG_ADCDEVT4 = 0x0206, + XBAR_INPUT_FLG_SD1FLT1_COMPL = 0x0207, + XBAR_INPUT_FLG_SD1FLT1_COMPH = 0x0208, + XBAR_INPUT_FLG_SD1FLT2_COMPL = 0x0209, + XBAR_INPUT_FLG_SD1FLT2_COMPH = 0x020A, + XBAR_INPUT_FLG_SD1FLT3_COMPL = 0x020B, + XBAR_INPUT_FLG_SD1FLT3_COMPH = 0x020C, + XBAR_INPUT_FLG_SD1FLT4_COMPL = 0x020D, + XBAR_INPUT_FLG_SD1FLT4_COMPH = 0x020E, + XBAR_INPUT_FLG_SD2FLT1_COMPL = 0x020F, + XBAR_INPUT_FLG_SD2FLT1_COMPH = 0x0210, + XBAR_INPUT_FLG_SD2FLT2_COMPL = 0x0211, + XBAR_INPUT_FLG_SD2FLT2_COMPH = 0x0212, + XBAR_INPUT_FLG_SD2FLT3_COMPL = 0x0213, + XBAR_INPUT_FLG_SD2FLT3_COMPH = 0x0214, + XBAR_INPUT_FLG_SD2FLT4_COMPL = 0x0215, + XBAR_INPUT_FLG_SD2FLT4_COMPH = 0x0216 +} XBAR_InputFlag; +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Output X-BAR mux values to be passed to the output signal. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) |= muxes; + + EDIS; + + +} + +//***************************************************************************** +// +//! Disables the Output X-BAR mux values from being passed to the output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values from being passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to disable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Enables or disables the output latch to drive the selected output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param enable is a flag that determines whether or not the latch is +//! selected to drive the X-BAR output. +//! +//! This function sets the Output X-BAR output signal latch mode. If the +//! \e enable parameter is \b true, the output specified by \e output will be +//! driven by the output latch. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setOutputLatchMode(XBAR_OutputNum output, bool enable) +{ + EALLOW; + + // + // Set or clear the latch setting bit based on the enable parameter. + // + if(enable) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Returns the status of the output latch +//! +//! \param output is the X-BAR output being checked. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! \return Returns \b true if the output corresponding to \e output was +//! triggered. If not, it will return \b false. +// +//***************************************************************************** +static inline bool +XBAR_getOutputLatchStatus(XBAR_OutputNum output) +{ + // + // Get the status of the Output X-BAR output latch. + // + return((HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCH) & + (0x1U << ((uint16_t)output / 2U))) != 0U); +} + +//***************************************************************************** +// +//! Clears the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function clears the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_clearOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that clears the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHCLR) |= + 0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Forces the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function forces the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_forceOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that forces the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHFRC) = + (uint16_t)0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Configures the polarity of an Output X-BAR output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the Output X-BAR signal if the \e invert parameter is +//! \b true. If \e invert is \b false, the signal will be passed as is. The +//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output +//! number between 1 and 8 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertOutputSignal(XBAR_OutputNum output, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) |= muxes; + EDIS; +} + +//***************************************************************************** +// +//! Disables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an ePWM X-BAR output. +//! +//! \param trip is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the ePWM X-BAR trip signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertEPWMSignal(XBAR_TripNum trip, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) |= + 0x1U << ((uint16_t)trip / 2U); + } + else + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) &= + ~(0x1U << ((uint16_t)trip / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the GPIO pin for an Input X-BAR input. +//! +//! \param input is the X-BAR input being configured. +//! \param pin is the identifying number of the pin. +//! +//! This function configures which GPIO is assigned to an Input X-BAR input. +//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy +//! where y is a the input number for the Input X-BAR. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setInputPin(XBAR_InputNum input, uint16_t pin) +{ + // + // Check the argument. + // + ASSERT(pin <= XBAR_GPIO_MAX_CNT); + + // + // Write the requested pin to the appropriate input select register. + // + EALLOW; + + HWREGH(XBAR_INPUT_BASE + (uint16_t)input) = pin; + + EDIS; +} + +//***************************************************************************** +// +//! Locks an input to the Input X-BAR. +//! +//! \param input is an input to the Input X-BAR. +//! +//! This function locks the specific input on the Input X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockInput(XBAR_InputNum input) +{ + // + // lock the input in the INPUTSELECTLOCK register. + // + EALLOW; + HWREG(INPUTXBAR_BASE + XBAR_O_INPUTSELECTLOCK) = + 1UL << (uint16_t)input; + EDIS; +} + +//***************************************************************************** +// +//! Locks the Output X-BAR. +//! +//! This function locks the Output X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockOutput(void) +{ + // + // Lock the Output X-BAR with the OUTPUTLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLOCK) = + ((uint32_t)0x5A5A << XBAR_OUTPUTLOCK_KEY_S) | + (uint32_t)XBAR_OUTPUTLOCK_LOCK; + + EDIS; +} + +//***************************************************************************** +// +//! Locks the ePWM X-BAR. +//! +//! This function locks the ePWM X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockEPWM(void) +{ + // + // Lock the ePWM X-BAR with the TRIPLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(EPWMXBAR_BASE + XBAR_O_TRIPLOCK) = + ((uint32_t)0x5A5A << XBAR_TRIPLOCK_KEY_S) | + (uint32_t)XBAR_TRIPLOCK_LOCK; + EDIS; +} + +//***************************************************************************** +// +//! Enables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) |= muxes; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an CLB X-BAR output. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the CLB X-BAR auxSignal signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertCLBSignal(XBAR_AuxSigNum auxSignal, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) |= + 0x1U << ((uint16_t)auxSignal / 2U); + } + else + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) &= + ~(0x1U << ((uint16_t)auxSignal / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the Output X-BAR mux that determines the signals passed to an +//! output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an Output X-BAR mux. This determines which +//! signal(s) should be passed through the X-BAR to a GPIO. The \e output +//! parameter is a value \b XBAR_OUTPUTy where y is a the output number +//! between 1 and 8 inclusive. +//! +//! The \e muxConfig parameter for OUTPUT XBAR is the mux configuration +//! value that specifies which signal will be passed from the mux. The +//! values have the format of \b XBAR_OUT_MUXnn_xx where the 'xx' is +//! the signal and nn is the mux number. +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the output signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig); + +//***************************************************************************** +// +//! Configures the ePWM X-BAR mux that determines the signals passed to an +//! ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an ePWM X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an ePWM module. The \e trip +//! parameter is a value \b XBAR_TRIPy where y is a the number of the trip +//! signal on the ePWM. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the trip signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig); + +//***************************************************************************** +// +//! Returns the status of the input latch. +//! +//! \param inputFlag is the X-BAR input latch being checked. Values are in the +//! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal. +//! +//! \return Returns \b true if the X-BAR input corresponding to the +//! \e inputFlag has been triggered. If not, it will return \b false. +// +//***************************************************************************** +extern bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Clears the input latch for the specified input latch. +//! +//! \param inputFlag is the X-BAR input latch being cleared. +//! +//! This function clears the Input X-BAR input latch. The input latch to be +//! cleared is specified by the \e inputFlag parameter. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Configures the CLB X-BAR mux that determines the signals passed to a +//! CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an CLB X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an CLB module. The \e auxSignal +//! parameter is a value \b XBAR_AUXSIGy where y is a the number of the +//! signal on the CLB. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_CLB_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_CLB_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_CLB_MUX03_INPUTXBAR2, resulting in the values of MUX00 and MUX03 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, + XBAR_CLBMuxConfig muxConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // XBAR_H diff --git a/gpio_driverlib_cpu2/gpio_driverlib_main_cpu2.c b/gpio_driverlib_cpu2/gpio_driverlib_main_cpu2.c new file mode 100644 index 0000000..7379e19 --- /dev/null +++ b/gpio_driverlib_cpu2/gpio_driverlib_main_cpu2.c @@ -0,0 +1,40 @@ +/*Gerardo Marx +16th July 2026 +GPIOs management with dual CPUs +---------------- +CPU1: GPIO22 and GPIO97 using bitfield approach +CPU2: GPIO52 using driverlib approach + + |-----------| + | | + |GPIO22 | + | | + | ---- | + |GPIO97 | + | | + |GPIO52 | + |-----------| +*/ + +// Libraries and includes +#include "driverlib.h" +#include "device.h" + +void main(void){ + // 1: init uc does not required for CPU2 + // 2: config gpios + //GPIO_setPadConfig(52, GPIO_PIN_TYPE_STD); + //GPIO_setDirectionMode(52, GPIO_DIR_MODE_OUT); + //GPIO_setControllerCore() + + // 3: chnage state + GPIO_writePin(52, 1); + + // 4: finite loop + for(;;) + { + // control task + + } + +} diff --git a/gpio_driverlib_cpu2/targetConfigs/TMS320F28377D.ccxml b/gpio_driverlib_cpu2/targetConfigs/TMS320F28377D.ccxml new file mode 100644 index 0000000..79dd5cc --- /dev/null +++ b/gpio_driverlib_cpu2/targetConfigs/TMS320F28377D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu2/targetConfigs/readme.txt b/gpio_driverlib_cpu2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/gpio_driverlib_cpu2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file

    _hR*a&I}t&p;XvRsfuc`>6r3I?N(2Ib z% zZ4VUPjtI8nWzI(gg;h%eMav{Xfv1B${Nfk0Z}E`;B6|)A7r7Fi?h97_?WZpYl-wBz z3`k)%7Wk0Hzii(Xm~m^M>ZgICI|5aBzd+FiO98G%mp)MBf55*h5ctQSFXT$&TLnnt zXP%dvE@OP@Iy=TsQ;fb6M05e6c%W#b6ZID@6?L&I>Rm^R`o~#Oqugc0=AI?|<2h4! z+7IC$m_qp9IVt4Ij$3t%?(Fy~m34|@JOL%M6=e;3B2cnBWPbd5dps~Bfvmo6G2N>^ z&2k!E=&8)WQZej4Fr&jkwm zQK7az87TA>&O$j}5ID&{yf{#}lJ4>BIDZRyj~3@ERHt?aDxRkLIx|r5Bk0+tUFxl; zvUd`Y) zsFWR*%{GlvuGnn*EEO(ODbv(xy09^oQt6mVsdAZ0na)h5hN!Eignf5q?%48O@R z8D}%`yv;Bjbush+!^I3&Fnj{Tvlu>w;WmcXF?*vPQk<_U{?86F8bJUbYE2w24#7LPDY8`xNpkn`+3hA(8eli^JaPcVEh z!}}S29$39sSo}4^v!($A8h~dvM{56Ju#4y>EF)~z?IGC(et<+^l+o?C`_a%IV)}_-JKiR-iJYmty z@Y&clYvNzda2Lb<437buc(yT2+izR741^EqJih_h#Q$NNCoJ|dd{ddj^C5;m#_;nD ze~;l`FK5jp54~zKY>p3_r^7=NbM6!~ekWB*QbXY1YUy7g*&_SkPwL zZk<-=J0GoF|#pVf%(-;oHfR5ognc*6SS2Dbw;W379V)y}uKg#eChQH77 zzcBne;FuIYENHV~RAMVi*u0k?*vR~DnMfz*vLH3<_U{)7@mpA2E%g>!^;_t zF?q#B3iKoNn35(SX_b{IGvAM|buVQ#3!`Cr< zAH#$S{;TeZHO!uS{3Jg~vX@JwtI zFmay4@N$M@3||4P(t@4?U#8O~++*~d@$ayC!s2Fzha*n9I~cx?;e!l+5?G}b7M}yY zLXfkfgxhqwp9eO!JYn%8hF>|=N%swgf64Iw0XEN`BTSzvE^Y0pdJz}+{EFN0 zhn*SH7MszTd7wZg$a!q-new80t7NgFgqKPz@QVVD{M42xp0L;ston5r7XU}_2N#{d z#k}uMVAJ>eF!06rqx>O!vcw{~7k9(I4_NVp#b7C)Cui;|&zXxpE;eVq*{E<9_7fLLmzr)?|W180f9-RZMzPVPEu;H%;Hv9{1 zp0Kpy)Ggz*qU%AA==l2>|0ZC?6UO3-Y2U0UVUs^Q8UHSuCoDb;yiUhYc&UzmFXN{% zwc-hj*MKk8{DdQ#|9ikj{?~1uu=q9bWtyMxOwIpqjQ@8wPgu|odl>yEY~m-I7AF4b zHV@ix;PpCw!Y2M|#=p?!!B_xzgXSk}@@FNmiND?ELH_}+Kwf>(AK*?pO=V5^bcsdu zN4P6G`cZfnqyL1j*E|869u_wM8=WV-O!H6~89o0Tu+dw>=V+d%ZF*R|32f>D;SSC7 zk2XCl>hLZ`p9%MAp2apjEItTqbeQn_G|z)JJuH3+Z1k4!2F*ir8m14~?KgU8MF}gq zh_1EiSg8g!{RhHv9Z$xlheZGxuJp}{5G9XC9L6+JBFGI|wZJcNy2%>y=iML2{%xTr%9%lSW} zSJenKJcLcVx)j*x6=B2U(8Ho0bfZ^<4Ua<)OSz0*tz;s=y&`OQ96H)+ z(AVRSuWtS=_^MqLYUSujCuXvRN_>n0p{e)bSZl4RRW@-M z1wvEmi~^zOxG4~tQfE9!`a(AaLX$Q#9td-#n*yOzE=nz;9d}b8^9)ePLa5GX$c*6@ zr)ZfO4`hzGc_1^rd$AJ_WS#~}i9>> zO@YjmW94?t3nBAqZVF_c@1{UzB*&kE%t($?APkjGg%dMmrXGMpS%gT=byE-tgycN% zLI6&I%n?wg*)cDI%xAbMcmxy8sF_B`7C~lwT9A)61u_?dQsqz}Gx1D!D3F<2fD>%W zV#qw*O@YiO+7xax&8sy@TI6tZ^{Y;kJk)}C-@QST!jk8NoIJ*! z9@S^RH3L_#GdA?95Hw{T>a<7~r;5ke$|Fhq)=A!kKr#02NQ37Yop@v){TcX4}D=3 zkGHOVO7l=VHkHg@*F4nvDIU@Qw|hhL(ARS+dH#>)acp^e->ZxoFgR+BRXkKT+-|Ps zp?-_vsdqELw@mZU_e=43>vL4|(6?Lhc-xLEHIE?u5f8ve_GdQ@)eTi|wJm_>I^`rA z?(>adqHG%_?oh{Uk%umATDhpheL2sVX7T9LBys0J@)Qi}%=#38HH%^O#@IQhw;WA6 zwk+5){0vxbvOed>0+|&vM$LKB#T)KDufcd+XOFV!ZNqL;J%5;)^{kVQ>ZmHu99i%= z4gWYH=H!%C5<6$LodKgej&?}OlqXgUf3~jir`(5(WC$w<9m5nFX5xoDQY)pOmAo!u zNzOjiXUA;xQfZcl?5L~T>f4m2ot62R-oZp}+s@UwZ96ZjUV;#EWRbpDTBLslpIOze z8QadL??H{r+4%cSj;|1Xzp0NS)eLv;BD%eE(X@y6*-UsY{(8gD`fr9m*L{K!(fzdD zKcaI)@&AT8C2;2JW#lIsVdLm)Qbe7cEElPF2p@2uAaVov=TK(_j{2D7xGh}Xl2f1U z2JpwS`9Y`rB-gBN^7=VkPu8+CvXt5I$5=oF_&ea=q2s5%208P-$8QVw?~rrqBapXW z)h6}rmE!$b*}^^UU)BBwDwb8))ZP&9Zs@usUW1{9?V(?&wmtOY)V2q|OYL|Ti2}#7 zSOgr;5)pJfOKG}6#(*QP=EtlzAo)^~AxN{h))N@l=rm((D^|3`;$5As-D?|SEk-U) z#&2yj)MT*|t=34%`09+XjJD9o%xEn=-9~ta+E`=WfzfJ3p?WVys}ms)ZJ{Xg&?uGS zY-&@DDDlv0MX85YC(1mug`(U;qf{!gsm(QFnuk^^!X8?ksPxbliYgC{Qkm|euEUR6 z*NAs}XtiRthgK&}@z55Eh=;aFoa&;rMAvrIARRH+L#`$A=^k<&k9{Yh2{6=2oS3aSvHWvff2r6ICf*>7sT;+q%~^ zAg{zwHa({3!`bxib&bTI%BIH@eI%RSy{?J)uga#!6g};tH?=p)61qN{D&J@#n<{hV zhHR=Vo*lYrPY?9>!_KMiEo#@PH4i?6ONq2W9?&+(18y7SfovP(0mlY;z}O&nn2Zhb z04y!w2VR^2=`Rdu+u#me+XgRC=Es#W@C(pyDIoLX%G(aFe9&0@c0X+_eg}-j?|^Ob zTRml4{4SGbz00Io?=orDyG)w(E|X@x%cNQFGBWF3rp$VmDYM>X(yVuxGV5I?&3czf zv)*OOtaq6->s_YJdgHFmdIM>*-ay8zH=r`>4Is^W<1Wp5;|{alxY}mDfu&jRGG*4g zOq=yCQ)a!(v{~;mW!Ae)oAoYJX1&X_S?@As*1Jrb^)6Fpz00&&?=of9yG)z)E>mW` z%d}Za+6{O$PF(isf%=OU5s`pSo-`-P@HMB%6+xqdvtQZ!zo| zZ5r4(){_|2LB?19F3NoT&hx}U{0_B$H-6dLf9d3bJ$@Wq7kAx!wLc~9+I97u&4*gRp8WVi#un|L-cd?Ujj zVfZr)e~aOt04o{P?|~Y5=0OmelZW%{K{NamX!7=2VDl{D*%XLpCveHdPwP%bej2Nr zXU(`BB)Lb!`)u~wJH_IxY}3jBm9e7m*&5Q4T&rPxhK9!fIeFNu483tK9+2&s6}75H zy6JUhb_9xmcxZma(OkoAW^~lb3C-!4c^t#x%$iUR`7N3^@j5e80>uGO1XnXZ0;pX= z-?A@@su^qp~HkRBvh6(Rn->^S$k~LRU$D9e=kb5R@ieGtKytsCW zoCuUNfo1Yn-rBHiGgrR7nF;)r&I`JojlY{!)556E%o5iv!|?GO{1F|<_3UW;^@gA6 zoZ-)PpI}723rg6WqM|;Uh}aUX6q{j(W>EJmue<qqac^v0o%|hP`+;|Lr+U;lD0|37Ue~Xrf-jf`knH*Ild8OT! zw_|29pclDJQapcdWBlI$t~QY}I_Lioqf;HGAK!gM$8RQC4S&N~VCZfW)*Rde4WpyU zAy@}Xi_nS1g{8g;pKk|j#`%2D`h3$-l6q#cAaA|I4S$X^lST1(GBG%q+Jb}KaT^mA zt1Fr&(XCJhD}*6xys0}@jj3r3G3{p{X8S}yl2hZuSX&xZKh0G}j}|_ROQ{@q2KB%* z=pJ|mvj?6*XW$t$15by^3_R&qt}yU)0`$O>|GX8Bt&4#3^Hy}CBB%$Z&U1QT8sG!d z^UZ^5U`j^#{gKOXExQtz!m9|8x9}QV{E-Rr-$ee~aFI!vA*?$cGlUJAA#Bhd!m6k2 zA#AxE!j{V+Y`Gl5mdhb*xg5fl%OPwz4PndG5Vl+mVaw$Zwpp2wSd)u;pq9Tds$& zp2wSd)u;pq9Tds$&#hr$*xXB@Gxjlphg$-egd(eL&P47(&Zye}vQu^MW zO2A;`Snnp;#!>4`1KBB=^4d^U=grXTAhm<59jkhz|LXUtVA8c$+)Ng zeU4pEr!>78K8-pk$QJoqW64CANlP%QUQQ5)*@|rDI<~LievFsm^a3xQ05syIs5$s$p={hk7s8G}{&X8~0|)#oLp@C+;Y>?js9{Pd#xka~oNL+jkgz{v*M=VH?rse@)&C{6CfVp#Rsn zOB-%CQf&9Z%A(JAWH#Lke6PuS(Dzf^e~maZH^SQFo{L{t`B>{Mb2iUUSg{!iU+j|g zb2ex8`ktx3!)M_si>x?4{Cwut`wj=6v3xX*_VDw?&zzAWE-MFDz~(A?rb=>&99#u9 zSLm6{UTG=v*84Ile&c`m`TM@4D6=-t+Dvan<2;&E@e9j$ypwm-5|VweF5LN;n3@9H zPFauF-WaJeg~zgylN2oLc5(xSwI#G;8?N3~yn0JHt0Hd<(<3GkiD0BX~je?)U*q zVA?7I7rhGDq`TYZfdL(c$>5IRxrgDy3_r{8cNzXU!_a*@o|70pm*FOcqrgh$u%N!X zn#HlAgiqA+uVwu2w|T;1nBj}jBQ)|~#&AEdiZhJGWIC=v4nHgboY3(PGyWTFp0K!y z;RNP9P5fIJzJuY%7=9jDrKJq<7))I>H4~!@@tDKgWQfO1od4M735&mD_*u-C8X3OB z@INu^Ll4F9gn?CBVL1t-@1Y^S6rXxq=GnkTX2OQ&RGS_a?*TS)67JXW)Z29G-8iyAJ?*lfxQ(2IQLN?u!w+e=mhJcPY@n7t?grO#TFpuBL7rPaY#>!MJb z-0Y$(g0IJ>@abkWSD4PnCCl+C=0EOIhWR?U6FftE>23WM<*-+%3pEervENcTr%Cp0 zwMM9d;K}~tsK8OpgS8Ow(B!R|u+;&$U9TaUQj!NXw_a16o0-xjeeql0Z~_?mkj9jP z-&%^R(kR9v4r-5c$iXZ35zXTq%%D7SyVtZgXdhhh=JiiCPY5-Z>YLF(O~%i%t0kJ| zmVu2uwJB$b2D3BHAk1F4agA*m)fsp(;uLd0f9Oijl=DS$=*NcE*+a;zq2V!>hl+cL zMn*^33Q^6HC3V%cOR8(9S|3`rtU7yr=sFBoPnUUY)`#@RRMO7I_5Zi^p}UR7;658Q zfYyi3&~gX)(XvNrj-A|*dc$E(xhwxkxGg>gzy4Ur z2Z(>uG5F77?a^NFKM4M9dOb#c0PrC|9#G>%?k07U*HS!tKA6r|JpsG9;ra70-O^Gy?%!+B$71)Cdrm-8^ab4Z864zLia2Ko;mBVQX>As;Mwgk6ccyZS&Jh;mh9^B;$5AJe>2Y0!`gS%Ye z!CkKK;4W8qaHka>+~f*RiM_%D3R~eRJOkb8rjBS=mtNy(9T>!t=1No`S;eVs#bkGG zhI~yM=_V$BTNQNzQER(pMdfk}RRgu$Vp*4sCWb}^lhJf?v^O!B6jaONSv1SKLQ&QZ z4EJGGnek|f<=c79*e1lWDK*%q!X0nOS}&7bVkaB&BumDdvXc#ECChkpvLP$xBqM_z zZ>j2-7tX|2$XlfCcnxw>6*-0Hxy0AyZF8zF@h$&NOZsp2r*m5K2V-;t9)N*VY;en1971mRQSF>ly zt{0ChWJR5aWuW6Nr8!ee6uuk%H(pFJG(@s+sLSmx92u17A~~GzB6)p^>Nu3xO7BNI zw`If1{3w#XWN$i2T{t`3MWKebFFBaFngwegg0_up8S1)vxVJ0atKw#U1YbQqn$$^m zZR*>iG$M8(P+B_l;JK)$m+5s)}dPBkhPi#D8rZ^jeVAEQn9jVrL+YX z9~1heua*TX&TPGB&gM5?`7wS8Zt`J&&q3?Jm*2eqFn%|$An_)C8P1=2b5^~WwYm7! z@^9R~{e)LPa_#+VY29q!uFS2E@7a%Mt*(N^>oea5=j-@wD|+trnUimmPZZGhc$v#0y;^shXcPv&w_=^1@`D-7TWcI9)`JFYg0%wgZpw`HOuBEZUulm&$?zbG_MwYx=#{`qHduuOR#Qz@l<)y9=Shrzsm&7>^h*?q z9}5ZSgqb+&8NQt1F@|qvIK%K~flZv$u~XCER+R7+D0?bjTHG>=J>Rx@!s7c3e;(7~ zMxJjm{40hlG0Sdv7BC!Rc$ndv8Q#zE5r%)nun#>R6aR_8>Rr^Li+Qhkc%cZr72fL{ zT+Dk_0~`L8z@}UX>*;mOGC2HEn+H~YfsMWqj^Gb2+J}pYe-p4N_X%KAj|fNb2N&Im zi{ak|Z1kA|QI+6)(d%(F??QM!k@4&fT#WpOfKB{__4g(EQJWqXF9Mr)BzzYB;G!?% zV)Wq`z~;ROzZ-vW(O=?X-h~K8HdG@!|7pI_$VoVaKRCIlX5^%NHF6R*JPutgsu?*W zjEAt1a~`mfldy@$p{r0OXZE5Rb(h^IeQ4^`q13?#C1#c;X;BU8#VCv5qcj|Al#Ah` zcT<%A++{ZN-GMmFQSOjKLxtri^DUAj`*N{Hl%rGGZ0pxNXbh(0xk>Y&vVw=^z?BYY zvb^1`J!s&;L+c1Dc(BA~W}I^0Zyof66XCF?QVLTovzc>E&JvpU{lBB*ahAu-cUuSG z_RktR%XMBJbDG3C3FR)2#mEgh33YLQMZ&Tw4XIfXj@>QdPgH4$qW zJp%j)-gS|VpV|>}hX43izWxr6>Xk2lzGg*?`u-U%epzJY9tWJFYr5MyVE?G4V@-QQ zcU$MGj?U(mcvp94w4t@TCAO+%U3YU!Q>>+<1=c=bv*{@O-Iun+I-xRCF~!!bYK^tD zkRlaOJk&D8TZYC56JrCZ;SMbC3Ey%^RZ5}->6cUfg!VkN*^ZjU@i9n&8Y#_oC~qgc z$7k;BnjGpo}+mIOx;pmp>d}Sz_LwW|Gdy93+m01h0&%<*zOa6rQiP!cVo! z+%s`@95y(RYiyUfWli&k!d9iVymab)<$pZ$8*;{71YSf2g2ez z4F4^|KVq0pD;a(|L}T!M4DVw&!|=x#z5{~MkO~SGCHy|50T;a!*bMHUuzAAb;|xE7 z95(5Gg5eh!rrq6!=O@4_Ej7tu(w&C{&7{RSz$V>lV8ah+58QXybW2Vo=)q9*CY#O& z&}x^yk%78bCSB9j0!a?^y=j@j_kZqyI9rz>FP!PDQlHarQFj$ZljTeY8yOEC>SCL2 zwZmvSv80K9i@LF1XF9IbclKKmTq#Dk+o-+Hz|k%DUWC)YaowejOWr?vr9Hx%@;mSc z4)Ugq?-)b0;=V+$8J@|J*D=Rvif=nZZ|nl{(jE@_*0tSC^R3VQ63uiVSvwq|1YxnL8od#u2J3O_0zbnQ7tZ` zI{8n;C<}=Im*8E$uH!dKZ{GL#$7p|#NA(yjUpog$eg6!HXa5EECSoHYHYKVN(5Iop ze%nX=IA`Bqj-8A2`DQy8Y5D8;_A6GQnz8+gbKxysgiC;acj5QhujrQ>7u6_?j9CGp$%znXo`=G4<|b}Zd9ffhh%d_4XqW=5tyg3lxk~g z^R-7tMSrQa&1_mC&DUELu{SiG+?Y%!hkKJfsll;Ce^QW2<0O3+HDs-myOi4OheNp@ zzH5qy5qTfWX8PU8xSLek+BJ7>b6byG*|Eybqe7sqCQl#A-2BT|CdK6LiMKMLiOI}+ z=WPBuj!^pkL0EJI-MZkBJ(-&_Pva-dx2S&~coScxE#mL-(b{tRn}`SW{a>uC_~k2N za{oPg?aWqt2`vKpTRoA`TAa`>-fH2!0W7(f%9O!(g zoFO3XzwnnWoae7x^)6o|9Q0vxjrCuB^8}42Z>>j1Qdp}o)M35z(x%h6PsIIm!s&ITL$LkvI9@DG8_NbIK!S0I1X@`pNiYGj)S zI{m?UmdH&!6bSL)e9>!hHO~^(%UjV2oBroDdX(P=yqnvZZZvh1{T6kkRsL`;)AdIo zfQLH&ro-=WHEKwj>$j+b?RBP0O{0dXMvrm*m@|5G*BR5)Dz=FUpV$M4@npKUZ$skJ z)UX*(=J*KyVFSq=5gl^`**iMKhmgk_LDtkPs;-qoNLu9!OM8qDoS}Z@&>2C7Q7Mh1 zVrx|c2}6>1Ga|_~f*i@gAJI?e8bRjbuQ&XEzzA{{8ZG0JIA=%k|4wi6*ro%F{NyEU z+%kY~dl$Q1=k4YjX55K?#SBK!FjDW(S{*3Y^*?(I{(i`zj`J^M{OiEC54yAdboGE~kPQFvkH{0yL{%{g0{QACQ*+QO z1zxO}mxL`@n9Z4(K068N!>`w<1f>tZTf=;dM8NhnSBs$IsS$1k6uORNOhF5^pj|CZ-JP*`gArBx8?(ZjOpfUAW+Slnw-}MNztsq>{VR;z+P~6> zuKjHyq+Uh)FBU~E|0SZ><;QVGm%l@ly8Nrq%&Pq8O7@PW@M9IU92}+>FS-F2g>IvK z_>Pkq(O73U@}s5MS~`aZZGE_pB0U-X8~s#k zdsj<`e8N@(heQ@mjj%(Bkxi*|61@u);4es0ilt}~F2RrC67r*lUy{7K8uqkK6Q4o{ zDQ*Zl1PS;~^RbW`p+oRfPrlO%SV*l2siTk}3#mhgRjN5EQZz9-x+RtFL#kMvhYVp7 zr0B14DTsWP{NE%${Sy2%d0IE5PwR%sG4Mx|RC0ZlyY{Td7a$R;tswmHM=9r8=!!sZZ-xs_Cyv zeOk9toz|_?r*$jUY28YFS{La{d#t$2)4I6J)4I6J)4I6J)4I6J)4I6J)4I6J)4I6R zXb{l$VW+Hgz;pg{P_=w|x~XjwvhuZ*TpygQ42tZ=C=T@$=ej9DuAc|3l%`wnV4#l z1<;=ylj`3(m>AuJkDc!LP*tG5z5I%*+AsxYehcMDo(tuNa%;_~>Pt{B0zWe(`xO<| zdX09wsH@Y-ew>ILPYRlh!c4LDRantc)n}xBM_l778YEd&G|IC?*(S`-xiTGny5q`n z7hire{LMUP_}enWu`7vsvebvAy-S3V;Tqk@sICkweFHXKcm~!Ux7KEJ<~I}lR-SY5 z-PW=7_U1p9-j>e6kl2;&E`5Ydh!bGslLi}Xy zz!0^#T}eG8p!|~?J**<^a#3w<4zB!WUt_+r@4YJfw$b>9Mm}+g&}z#2`8K7B=H)F> z+J`w6nPF*V!N{9swAjJ2EGJ)nGcA$tOxui1tHPIBtp&E+RsYrtM^5$~n7!hz$d3KN z+R6R11F8MN8{Vh}IuI=F+aDCW56%=5>n8vA`UAnb$?21)ZOz;mdiB0w={JgTEr0dl z;C;c&!EoY8u;s4kTQAIRxhwY8YeBkqzx7kxe;o|m)$`U7X}J37r&{h3PKp!9m!khD zDNd6qR_YX|+bPb_DbCp(xNGFCBlE=Lvo?zdkKE(GTXa3yld)hRdspDDvA6IGbJmf^ zGBf7%TsnCep}wx7^?|$AzqS9|Blq-9T6Z5T4+VD@|u}AG+#V(WRHJ$=F9`Z!xc~V z?6>xVcPFRtgZMO3vDad^cn{R)3RfG-@E{yjAbOt0J(y>;9rgPpy?A9wBXB;# zxEzEjy>8t93N5H#d>aURiEsGRtRbuJIg-q0Yq1IO! z&k9WU`N{)tMFfcr@G#STcBvSub^E0&$97- z5liF5Jf-3Pu@B4bRrf-GdxO40mx=MmePz;6_}k)6SpUBLdS9`8nHm18eIYB`;K7ZW z`Lh-=f9*Qt2&|7kWg!Qo|4!sXaE8wp_HVy)kAK`(;ECZ)OC|R?8N*kvJ8E)AH1oen z=DT!q|EiO_>$+nn_q=}bUhl(rZYU|)C%mZW_FZm7Xu2BYM)B}nz0tkGWhG*ovJw$CRw61LD-l(EYXenw)O9#~`n975i=4Sr14Yg(GEH^o zjS2Cq7}b`DGl_up(D&ndn#O&YKR;b#+Er)pj~E_-aE3n4FzpXA^y?Yk$?yjlz81Z3 z!@q;!TNu8b;ky~WpW&Y~{1(GCcv%zwVumkZxSnCMOkwy38NQj}y$l~=_+^H_#_($l zf1lwWGJI*kNq2zZ8yLQeVX}g8x-KI!@ow1;#yI{H=xYmqE7-Fo|kPNtb;TB zN$gNCJY@3R;GZ*Gh^awCpUv=mV3lrI(Db3&K4L`)8yRXD|HU>>Sgc}r5oW$j{GALB zGQ5l7zhL+YV3lrI&`gD|AygmbU_Wz zyMR@?VR0(MG@VgW)}lX980ThW~zsKgRHj41Wt)r3-5y4AT_FNje`0H)(l( z1Z?7e$L0wOANC?C{;((nHax##xCrBKL!SX`_)lh-#^|T&bP3n!bWZ~|&n~xl!lH@c zm5iqv169M{$Z!X+ia#u9Fss^PD@r)5)9MB`+qu#Fn8~%1+BSX~Y35!j@MrOjgQyU#*{3A9`SWEz$awM!bnRqOf zn6jX4Peu<38~(k(MxK2(Pgr~g*wh!ohW`tU|5=+SEM5aP^_{Tc{~oZ3|8<)uEZzcE z=Sw#vmFrY#nLTMFt>2oipK#yIzA}7N!9zRCRNdiRW^Z9Y^3d)= zv!l@AGW*Razx@{NIP*HQ$BgvdZ>_`C>@0J5sl_DcY*F==**eWbnyG%I!pk$Hc}Ncx zkGDK_X&%zdsdygOJfz`M@jS129E(5Rw0@v@%ItW&YM3+VrA_yGMJ|S{^`;ywHLf*}TntBvBgeG=AGqN- zM`q>BCil{=OLliqmej7m?8P;AV2((0yr+65XGtAnt90K`f^U?L9CN31?ZU;?5puLs zxnxVa?}b?ODRh^JB*t2EEmy!-trrkX*u}o4L|z| z82()M2}b-V!|9p$LLmOeIf{6T4m0wT*L*<;Q(t9=?)Z@3xJbQ0_>~g}${+JNcnp5_ zD1Hu8h$F|~@5ze)hq}Yd$gZ8wSFr&4>iows_{|rJ9$SOIa&!yspGQ9DKstZlHM(V^ z@VD^y8SsBo^CNqu<2#uj(KNcvg6+_*pdl}> zmss#h;Qu%kzkEW93TN6}!+-ocnTPQzN)hw7lNr^uSBm-Hb0hQb(Eq~b(T;|AcdTv2 z3RsEi>TK;^+YoD^&8dvs(A?A@HL~9O}tsO zTH45)MXRIDyjiq`w4pbPMyX(1ubbM0pZoC8YH53K7GIqx^UxNGau1DCsmP`_*NABz zTCE6sXmz5}Lt7}SJTyvWx{JE5ZB=)Tc(;dED`tCWb>b8cZJ~&GXp6+DE?NtIQlO@* zv#CMM%}H+*r+etNlK+gH^hR-}hh8W7=jEg~inBcQg_8g5ob*Q6ap2`h@-LG7=j5a} zigP{m#ghNLob*Pqz(Zdm`Kxo%8%2$WzEtwp=A<`@IuCuBQvc0o~BlYSHYW)rb}ktyZ+UXdO+BUD1Y)b)^3* za)rbwWTiKxQ9aX^D?~nXu`8sjxwWIFwH-Aoo|9fH*5{_>O!LKz_|cwi1C|W{n+R0+kieun7&m-<>;bVE9fF01arKhJKor` zqHWcxwpA9N?3J(8hm8_9x}fj@aqRa}rxIWf0E}@T(tR>>AjXlt(7$hu-uLHc6T- znG~6hPDlBNX( zDVHpq=#d?0CU+qGY1v9WtfStqZzKM>f+$<_eJUxhRP8Bs)r12*oO2T*o-e#Ap+pywNQ0 zvSYG&l!7*;hBprMM-%D95Kel?<8j>{CG)`UrGiq67C9f6UL6|loRMEIYBGks!!OI}wp9ig4|cc9C(olVjzlm^BR4x+~qE_%a!?~^Z}tttok@RO35?v)-KZL;H$0k&^Ct%;z7$}z*^l#uy=$wJDmC3aw5GxGiUEvM^q zRucS5*qG@6P=U!JbWu=`pxjRJ7!L~6&QtsAt@GYnk2bjClr_vnK}|CeXO*LqN>(}Q znpS}oJ*OP0`yk7Z=I?k*Cj;_YemCd0{2rdF{E%<5(_|MPCrnv-zMWgC_}ovrD8FX` z^HgQ|a>CTb8*`;8A9PVr!O8E`aN9Q>tAD7-Wjk?l%TWN?|0fNg32d$aG9a%CurI#~ zFh`xv@V2yLdOWCyXL@kx+qqr!092jU7}@Fl#+eAJ(7nd^PDOwgR6ipNMdRtW%SpP0)({XcbrV9sC=dwY zCJ0olTJ1%{rM_tWQ^ml7y=d!bUx87R&_U5%-^8KEfdCqyx?ncnB zOTYj7O|oZx=b7is%z0+coH;YkGgEy<^d(}xj}4{Fz9dWBa|74(&T&n0F@25G=e%Atydr0hO?4$?knT&6f`cu|^`?DS z>LGy;)h3>i$*&$1Qn#>s*V9q&ra1Y~)Vl{`r^LM-@h3k0Z1)}8HpIHNtt;!o&W6|c zI~z_uGAgeyS$h!2xpVeDyyubhzHNwQqv9(7 z-^TK>t&|oxPuYW*e4Ylyi5L99lg4??daci=k9I0wM45ob`Bi8awlZ@t8Fh{^FJFj|Gqu@ z?kaeH=k>k2b{^{WM8~G>H_;-4>1+Ew8-1cr*Fzmu+tPP!zpUd^M2#Wdj>z#{69@XV z{!f&4bwtWR>xc~Ksu3YYp#S~he?Id3!+(5)uK3Ai6vyC|KkaYX{a5~?qqOni4(y4E zT`+&zulqfx74(n_-B{2Hzh5_Uc-{N^ul;aK7s^RMdTV>;G8bl>%TUkE3$NATJd=hX z)#y`r2(7=2_ej^#vqaaO4}UC0WE{;pdg-a96ss!M-Rx9VTpgNTu?~bss=TEY`(Osq zv7W>gwr$lN8?zXmr^{pGdW9AR8^t&`&@P*yf(n!{TL93br%0v#H>|aJYGXxcIxyIx+?dJ1?%kuOZ}|)^NYJ z_WA#k)d|~(9Kq&<**uFA&om`37AM})n!Tm{Ne!wV9x6D}tJ98J2y*m9lVhK{d*tXz zCPz=MbUFrYZ!%Z~xK;~%+AtVHWmXg3a|wf^c=IwY6S%j)vnf6@JXnMTF1mr68?;BkxM3kIi3j~4|Yox_(Y7@G0zx*YXxo;c$L7n2z)27 z&Vy^wD4^D9w3CGIGWoej@PFUqajks*yy~u z77Z662+mFtwspglECc2|4EA`i%dfy8M8Z5L2s}aHIRdu}e3QU;3;ck}WI(>@N_=Z3|(J zeC35LS{_Gu3q08UoBRB&_=YR`N8DjNBQ2VO*J~|Nz%^d zHtmPNe7}TKCZ7Es9gP^A?2{xE#Z@|DoSp?>B)! z<{`}Wgk;J0OPG0ly0%Z@`yDBG2=o0;0OtE8%<=eidB2%w+tjU(A_1l?E6X&k;|lQwSly?xd2XzLHsn5Oa!I@Zyp zyT<;?c;d3%LxzMd4|u4&^%EgEe`QXh*2aw?6-)NLy<~WN%MQA?p!=seE%f5aE)TYR zDgFSSlg*t(Jf3X%j4?b#9#61bNnePpHkQ>dyz1<+zSV{|9jpcfRgH$hhDY@V5VJzm zP+=C;pK{I$(nFM4WF8~_h=vqiPIdGm>m0Eld3PgdevSoE2}7K#n>~V^LvvH(QfcUL zBs+&OW5$hzkprB+@ADaWOmx}uo?_IFu{#}rt#g=0KD{64Syr+of^Z3Hm@-_#oXfU} zS#t4LGQVi2m_L`lQ4pzBWw#3tFU7x(8WlKn&6MN((+OdA)Mh+H4OxauRQiOQeP|K+ z8Svj?9#{R2MVv^JF@Wf_IifiRR$HCHK*!lrqq_s zS(nf@&M9zMA*(=N7u?19T%=P%iA8qf5LGKOhs}!2;oyqQ{yxY}dL81hzan#(S7i2? zctz&0QXdQZ0a~3bu#0mXbzSV@d?HSdZWm|TKSo`smB{Acv}7R;k(C?;ufFW3FO|r` zy!vw3TYXt2?61BYQ;RLf)MCpqwb*h@Ew&s}i!I00V#_gFY&oVETaM|)mSbwM<(OV< zIi?m{j;Y0#V|uaWm|AQ(W)@q9Zx&kyGK(z(@nXw>da-2ywb(Lzwb(NJQ|DMXdW$Us ztHqXMda>o0S!_9`b;e?5vE`UvY&m8YTaM|)mSbkI<(OVBW{~X0c_YuNGT|uNGT|uNGT|uNGT|uNGT|uNGT|uNGT|uNGT|Pm3+XQ;RLf zyv3G55sNJsb)s!i^*L*IW@^f)4YpIc!}B!rU|OQQDUO-=&-Im;sGbLRZKmf~Prw$N zS@X3XPqEpx`KumJoEmtXr8o8N+IqPAy!4H|yD&*u+WGL-!2Zo8N4W&IVY*D!S8jP+AoEG?N z0-uh`!u;n5+$3Ubfr>|MgC-sc@TJ9y$ zwLU%9XoBqbLU{PD!y&`TzV5&FJ6z{IBRQ|1N!>-qrkK${B*yoyL zp#Bc09%#1XJ}0$8j-9}fVhp-@=G0%&Aeisl5KiBRHI2(g*PgS2t@?8}{2%RGEq7c; z`l?#ovf#sfRgD@oc8vO{QeRaOWj+2MC~*BG^H-Ig`O_jf9p3mHHHPb-tX)QkRznW{ zgb9>2?SuF$ng1hvRgL6`$w!r^{LuC)=2ZEde>x$|ZV*6&;bj{6%zxBhB@XSAsUs@L z*LvE`RQyf(TKTi--?62VqrMD6=F1=y{4xl6rXuFcAmo1;g!s$AXW}n|kp4381N4_c zNL!19eYz$TssQfK2SeE?B*gvskk_BrS9!asST?=x2Na!BbaN#dlaT*@cl4`S)h>Q5 zP&1$1{PTdYe8`S{6Hbpr(0v@I)Ew52oY#Co%lVdR@fzpNYinL<_1I>$ELqTMMVptd z`cQiVPM9!el;38Rs5Yw@6B&9em)oqpB8Svwol0`baQqBQaWYFX2YQGD8+xGo<>kh98=Vsf5s*`)q3Bnr$Csb{6wXHDo1vxJ=_oe?_(7Ra{NA& z{QGo}IuqJ|8vQR+fcf8bk@bQs_Sc0WLjTc zdqE1DMW--Zl#7i0z^uYqYnE5HFJktZmX$5@$*#AF;yMl0%Z^e^sp^@tXVha6is>_J zCZ%R45n(pDX68jRdf-o~uuzVRX4TJ3rf5v-l1Zo_g(}wimc`8zu~krY>xw1DEcjcL zpCZ&C&QI;kYISqdYLF|sL7krf88?`VOrLK#xF=vwyBy?Ea6O(ZFqN=8Q|StW`K8xnE~VZ9y0?b@J(h0 zVDi!2W>&~(zR|3ZvEH2`C~&U{y3JL18FR^)dR0AhdJ=1!sEr7<@G=4>dWDt|P|f+{ zD#}sSc$rZ3sJX4Wb@9^1wq{JCsO=GBl#4W)WG^ezld0O7RW+%ZGg8$v>g)6XEY~b# zFc_MgR5xuV%-Bs~XNA-7ZOSllh4YxW#^<aJQ%|8Uk<8xmWma`zYUb?vEE9k*iI|+Pi|at=EVw~L>W+P80aGLuZO(rr%j(Uv1-<&K#j=F5iIcBJhPLj zYE*ZAcX6k>zI7aZSXMJL<8?&BSp{#Ckh9*hcB*o!a%RGN8NXaMg&LMlzVt zXg>y16?2EH7`PS8SrU_0Hp4hQbPpBB4)ixnh9*s)U0YQ@jp{zVFsdfg%V@@=x%H{~ ziCjB!@~FLAt1qrb4aka0Or_{*KPfnsG8XBVQznYPk3;15_;@dM7PK`lo3>=?)wJq? z6~zZf%A+{*SG2Feu3uFY7E)mzg~KLNSb+?iXkq<|mCbEf3}WGu#zl%DGKL}!lAYyv zRWG`V(=JkR2%1A3ATZ#)LTN;)JCG7Ir+r>^dz*TW5nMtq_moefQ199py=f^>QxHb& zIL92PcNIcCnt94~{&}H^^B$8yq*E{@<(_HWuL^eUt+mN{69)1zD5 z;BLN9&r5v^r{#xmD1M5g;P2SrA_@E*>+K3!s6J?QEH+B{=ywTq)x?#nCazpHapkIs zD_2cixoYCdrHLz7Ph7cr;>uMMSFWD8a@E9@t0t~oJ#po#i7VGkT){UJS3qXs3Wz7J z0QJNbfSS01uO_bGW8w-&Z{iAAOtA>SFWD8a?Qk*t0%5pGjZkWi7VGkT)BGU z$~6;LuAaDZ&BT?fC$3yGapmfXE7we1A$>J*1z$~E!B-Pk@YTc>d^K?eUrk)WR})w8 z)x;Hinz(|eCazp>;tCWoaTT8iZ5q|6=A5`ft*41A>O*IR=WF7MzWbZ3{7qcx_&?!K zT+xHzO`<4^NddxdSUWb4m>v}xR~agk|ssd>d(2ZB;+&sEl+Qr4FQI7)I{ zb7A|uWZQha$*j*&sCQNhgWSbStGoa{DYY8_CrY|HDYY-0Z@wti+lWtkO`bJm2)<0M zaa5+>+4+GpQm^#GXlTSgyMxXuQdHVB-FZk&cIv6lLzwE^cRyJuhTh+KZL}+W{pQWI zVc4m^IC%Ko?%fX`+&1YAYgPZ1u_xk~9KGF%J+b-WpFFzZx$C=2x^_SOlWm(jqFq(n zegfVqoZa5Bc}sePy?sGT|tX8 z=U&@sW$r$To36O|#bU)-)iJ%%t~;&q>(BqxE`Mp7qJ7~-+zWWp5A-Ta-`Hu=uvUHj z`6oj+BP_kS;J^RdwO*>S5-(kgU#0cMm)!$jeAzni1;jeFmExjYeEntXIcpWi)`{5c z?VX!FGnA3iAt#grGv2LO?ApIlygpNfTtC-?n za%`sf^~(gg%~J!79&%IrqBE}`dE_Yx)kdoXFvJTH;%I*&9KJ3RDv~Cj7h`<-S&M)#wqwsSoc*n2t@C>u*tu&xp;v(JYg>zu$K%9z zUmGF{^};@9uWSex|HYVnhDv*fqnpCT{|LoOv6WlYUiYeV%`5(|eQhX?fVJyFrDe|g zSN?<@(i~foRN^on{apDg≧rT!5|EoHtsLENFMeUvVA|AtRt|Tl$Kk{juy7=f^fO z1lq5cXug+0ORrrE%BKr)f6kXS0EdcKf+_6mT%waGc7EEM?&I;RLNU7E`+BP_++b?^ z>Q$i_>2eM8`H3tWlBn1}TK7@vUe zOU8o)E<&PAj|;q6;M)X#2qR0(e^}rF5uctA_$vZqk5up4k?4AIJmUoZw!l9S_yK_r z3jAw<{~>T0gv{}e6nK`vWOU0s9Rhz{;70}iyTES>{I0;zq4MG^6gVa@Z8FB`eo5dT z3*03z8R;_rZw2myPhF25V|5%m`CH&tUAL0I17@DrJs#J3Tj1YAFN%5I7PvRQ!kB)R zz}3K*AyajdzSOj8i=8CgOIP;f`M|8k)a3EF)0fpy+o>lA^<2wWxbOo3+$Og-vT)cvN^QWA`*H_e#((u}Dm&3GuVmemKVTd_PV z!O!v}JOMwrWDO21&#AzCUlfSP6AqmxlsTtGxI)pb^@#!*t))C;%h|a?m{&qlQG*%U$jKLZD<${O0 zW!nRkaX9;7fHEFuG$riEd^XPB3Q#8CtN=3bc}RteHl6V)WHd$_&jHD~IC=cbfcmYA!mdSohdtmGpq)=@f{QS~tN)uZal0xYxJ z4BeGw%^%8&Y3zhidb1X#Z>M!vy3o{WJ6zUX`Kl2qd8gy|f1B>g9Fc#rFe2TRgLpZT zqx&Hz8astG)lx$(BdFeHxJ0E-;75rl)CkfGKhsJ62Snf%zz>1{M|f$H<4P}eSI*Z# z>i8s%v?THgC?#_IK+62j(?RM;4JS5G&T^7}sR*S9?+)-UHSv4-0iE#C>#qDKvW8wL zTtU7ROH_4lQfcHXiGPcdVUe2VDKJWg1vK#3JU^jz3L^!XN`?i#l3@WW8Tw4DWLTh; z4E+GDWay+){_@q^(55>6X(vvLzl%foK^zKSjbI7HP{PgG6yMAcMJR893n)l^SZ zP4z@+swb+adZK!&C#t4;qI#+)s-}9PYN{uyr+T7lswZludf=O>9w0N-1H@B3fO@J2 zKuz_)S5rOkG1Y^kH`N2Irh1}!swZludZK!&Cu*j8qI#+)YNmRkda5UCrh1}!swZlu zdZK!&Cu*j8qI#+)YNmRkda5UCrh1URn(BeCrh4G3sUG-hst3NB>VdDOdf=<69{6gi z2R=>pz*AE_QE#dT6fxBk`7ZhflP;W;q^TUEO;W8^hgVN7wV0TE$QhomktcdhHenav z{Kj8zud~hS*7OMIsUF+DOuy_cda}%mA2ZL_UEQP=Z7?0MqS;ax1SqzBdDEJvMOY79 zU#M}RS^ByZ)n6x2=q2!oNT84w1yzbXI)23;pp;Ob-nJr7quu7xn6?BOC&|`DjcqOM zYgB1b*V`|xV0eC|d0C!IYjY2!rPT>gJ*zBgXpDM+I!BRsp%XJgNg?67wK{m(lKIW6 zWw<6#p&Mm|_O{k}&5~o5rsOK#q?cxuwIm})g@GIeLnm6O1TsS+SZAovzA%s-J zLLXzOR-FU)-M_PA^5#h!?Yc-~=S{tzKG?7O{cx*7m|VCA6Aw(^(9QIX)-FMRz@t}M z_AKUp)}tn@{WsI3ROi6Shx&HyeAGJd>1W>f>9)hx$n+!k{72s>u#6_~o!4x8wEOYi zn1tH4jrfNkgY*^cK>qz>y{)21QDIS0QE^eUsHEtGqH~MRE2=JNgIJ+|%SFLwee|GHs&dMvtM?!@(vKxjPm{T;Z9OI?vHD;LuI=(qzfp0Dl*5-hb zqq71m3=Fsy=>gYb9&nBN1Fj`E}O z6V>-Pb%AUBMBs-6J}fY;*}(iHb;ePF%LKks;8uZ)kug0mVkZfc#UWfW3e0g1@p!Oj zyTEb0L78Wez@HTO5`mWpe67HD3Va{1&W~%+8(Mex?Iht-kZ;P{_kejw>K7i5YyC># zA41TawebN=ZICPBGJ{?EXH^FI=p z`KJPNSrAU(2bZ-j7t4nNQ50SOvtf>Rcf9RIgL;P?p}LxAM>Jh~3$IH|6( zeCW%J;}>6PY6yQkuIr*)!y z$~c@22~cPVj%4rikYvsZP$uAvV%I$X-eEDigKWp&@~B)Gh9W6sJN_Qm!(#MBPTWDq zV-9#w5D$$yoE~Jr**rsuDjxb$&vr`<>4S#FHW(g%SS&l=+YAp$UJsoG@Bc8uX%Otn z1vAfInoN3wV5VCh?C9|zSk6BCM;ryq8JG825KR9F!(a;*H7>tGn4KPJEuV4Y#)!3i zV#K>erEXTi6bZP_gYO-#~sl88d2@ueE~o8^#H{*mrW}Fa+#|Z)TI3a)8^( z^*CYNj1$K7IAPq36UOy8Vcd)p#`QR1+>8^(^*CYNj1$K7IAPq36UOy8Vcd)pB7HSZ z2w#m8!dK&j@YOgWd^Ju8UyT#OSL1~6)i@!18YhIO#tGxzI3XxvoUr&y=mzV@(Ch(9 zhEC+@^q9@-^VZ3A8Cy@TT^*MP#;VQ5{ctXV_kCU2{{DAHpZt7;05x zOZ)Qn#&(Pa(zBHk=NJI?q8Jc}5M#j{g$m#kj3A5af0Gek=_Hc9ReTUVSX}^1so|<= zUA2TtMtvu6(fA>GE}3icT{0aXR5B1)4 z^IDCsKmu^y$mf^sICgOfJNxbSHKE9uP`Er}vl!<+OLIK!w6AflU5`CwLWN^OkxafR zDw_XO@H=LTjB(z!XoHxVP?7EY&-zfY?R>)~TtoZPyhXdysN}*lYFc31<+N!=C@_5L zWDTDl?P_XJGyQn%yqFqJHX6y9QrJbM+#gkaI?T0 z1-=!Si0(7kEFgj?=a1{f&P(J4twyiT@BV zkC6V(<8iHL1%42(Gmif`foTUEu)*mOSdBke36l9MaTVV$VN>6-lps0(bHT&qMVR?7 z1LpiUcs#mha$Wr|&^d2}2jd5q`~wc0A5zKV{16_hSgd5kqr28{V9o>KDTap>2Du!G z#Ob1lJh{$;-|;&7J1boV`twALCPx=Y8NY|ernkMq!& zj$_kE50CEnd_4Ar2Nygv`o$w&KF_rVl5`!LMu4*2ErvwnO^!VhM_m?@^Z%F=+8IHQ zv}Wh~KEvaW#%9atpyBChRQEN6(}-=``4gJkuEvOM{j@Wo1-M|vlBSQDZzb8o%n|JO z*K-7lPq2?RqN_W=BAOhTG9*7EM;O^%xU{8J4D2S3G_pHt?5GJ^!I4&J@2y65PesK` zD%tYL?gn}!j5{6vuc-QGII7W93+0pKvFHchJ0*}XXY#2sByJ$QQv#Ld>`d{58B$Jf zqo7_Qp61bg5Pw}$)>S}V5}{J$NhX_Ov0IkHa5 z@9aoLzAX^^i-6xq@YTLA`P&8mQn1WJq}Q4T`($$o^H)(m>!(>Z zB^<6=zPx$yyhRwjE$SOBjD! zZAHWxRtFPj=U7GJ48|PA@^q9Hm8YYv5_vktipkTl_@oKz9FYoUG6kT-}SJD7=Z{`KuqElOxj2x_)KyF% zu>}Yuxd4HL7a%}>Ch1A5u^<(eI+(UZ-@+D3pHeN1;$g5C&_Q2&;q0nfwL})DuLxsi zRZUOQDnNp1yrG#~D84FMTno>azG1UwRZ}A^V5Qf<>W!3oQF4WwD9z{ngsW#_1+(hp zZ12WBLaMs9Y7{5U)X{wR9znBl+SRRC+oE|91dh#wDN#zQ@GVMjJYJ0EMyh61)y|xP z5}Z{vv361o-?Jf4nxUy&fK`xS>q31aAw<%PVk)e~!Bz7t5u>Ud394#GGF7!BzN&VF zRkeL4R@IJZRc${&t7?a(s`h^BwxvSNwp6Iu zmI|6}snD}66?(R%Ld~{R=-HMEHQQ35W?L%sY)gfjZK*J`E%4233y_&@0pi&fKt0<6 zpk`a(tJxO#m~Fw)n{5GBvn>^Rwxz<%wp8fZmI^c5QlV#CD$Hz4g`RDxFtaTcdbXv) z%(hhM*_H}3+ft!tTPn?X+&ranI&+pqaZ(7;r?Od;h zs+YDbv8dXo2w+MD-n5w(HOxc-EVJiP&{@n=#ynq?JPi~n&C$?CRMrq;4p7SMI>a)) zarsqVYU-r-NhDt@_CtKvD`mh)wyBw=-@+INi#*vlUl?rACz>yBKPEepU{_XV!kxM#smZgOIb9CY#$@TIZ9*loD$X z_0(|XS74XsTVQK)2#l0xc-1`hi1Uf=#mVY9kAqap%_qHS$P(?qh6-Q8cm={JYY|45 z=o3>3H`oYdFyvRRpU$^jZ_6cDvMt2D(CLGYx;f!an>p=GQ@Bp5O)Q%n70aOmkN$XP>A7=Ai-_Xbx2JO; z#WJPay1o0B^!5F_?i!&vFX`@#>@L+gNN+;Cn-3o7|IFbZr_+ZXd-U;L13M#CxW>8V z+&PzY?~3ewc+VqSK+_bR!~NGspz);dq~@TGX;%kwI>JU?F6kb;va=&Sv1swmP3iRP z?q1JO-U?fHsR^#B%DwjRkdXLwtKtYixU@HN3r`wP1Uw)!9CH>Cv}fQ zJ<+Ap+2PDd+XwHa+B6s?w70{#g{0`GnZ7B#iSyIznRDmt8c4NaZnx85g+i?bp`Du` zrwB?%Q41P6BX*J~@fHW8apE)P&y+NuRW}$JK8nYtLZxCEs?>9cUOmvw1?mU zA+3ue8QDthHJWrIBic*hOFF$ni9Qd$oY*zC-!Z*M-+8{u> zk4W_Mqg5rdaW2zJ;GDu5GUzf7lAm5o#NU{~pD^@>3_8u05&xnLIt}Cyy$(LvhdLHn z6G21oxMQNBXT}qdWS&~})$r zDc@r!;FjiP2JN7r;h(#^=Zk+x^0*)p8W_0Am+27`3l!L6(|g*thbI_*UM9+RD3#H+?NW zQ>rOOrJAC$AKz42bX{fmGnFORR~Fq+8RqpiOL8-oWHH8$!04^unRB7f?1W2Yd{C`a z`SX(XVk-+MQkIXiXzyEB>r?h(eaZ@7pR%{qr=+J|RZpVSUtk9}&Uu(B@N|Le1b$55X9O<9kUhuK zN8kYhCj>rK;Nb#~6u1m3ZKo=k+eyNoK^ed$%Yiwq(>)&7I#b|Yn3Z9kAp(yVc&fln z0&f)f3&1)Lu0=CFy52#f9{4nqpRI!b>mCnQND%mYg6DQjR&d_-3jA$g9lvYQgvJna z?}V3|w0Iz0*}YFW(s@` z21%J`mcWYzzCqyIfpuE0MFXs77&#DTedN0Y{{fE&`pW|UT=3kF_L=kW6M+u{>-b%Z z#uatX(oPbdXYTPy!T%4B$F<%R7<&kK@xLW-3=J`-n-KU+V4aq0(eT_*bB}~CFzJpH z{7H|;wdw^v7Xwcmf33iu5_pNgYk+lHu0?}Zr<-&MUt`kUDEPnR@wnFQ0f(0vcPWu>pZv?jr=4`eh7~<`FRhRb+;>yV;+&l3Re8|2B`uweAJx_X}Z;{~Ln;TOJRd z9bm49gqiM5T&0i9WmFDYk)mtc2u*iYnR6LY z`7;k;ey1dW=|^QmKJyT!AKR%6R#@AqFwaoXG~HGA!DU4E#5{yG-BpWra~Vw#JcPN7 zDuF3p%1hR1c{gjkA*ilrcCP7NAi1o)w@_Z6^u&@laj*M1XQO z&d>>i6$ht9S5VG;3N74?mzJQ=!rgdPNXjU^{+EB%C}g@{kO!HjyAV9cH1U*psgFXY zsfGy(GELHm`#i`r#Um)lH07tv=Rv0FsqiVIk>^1{3i3>~LGwsk13X5sIKd&qN&5nP z9_8i{HU$Me@KChnbbzC0)3N!>Rgt^{l`=VevVccFF^V7#^#)V@(pEAe(7?sUNB18* z=Vdd1a=oEO6;HyP1--k>Db*OqPMEWx_kcN#!S5;0&lnzbnZZM)lI>V;zZ5||rNz4X z=%Rv0Kb@H|v3@?u+p*E<%i&nZosgDIckt) zvA%t8#j_O0le6O4WUizduC1D~W%MP(Lr;_DNo2+IRm0<3K4sUlhYe56izoZupEo?d zl@%VQ4EMU>p(nSe{Lnj(T<$~~U!GW(?Ap(j_Tm0k818Xn)GYp{-392XfL zY9Vzz!Dr)6gp<|Rs=A9N*Up~B>vZwlUO;Wa%sYh1DrIzyf$MgBZmKolM|kY7_QUSNh0Ji1>F9x0f6P0lF}FQ|tr zeEE2B2lA-ug%{*=AHhEFiZwp||6B^IU6+K2lps?;BOzG61+C2YdGBEgAB10{;iYqSe7{F+|Kz-fRCPoJ`O+QJ#ov^#S*E6@<6gx!jLiG@ae{YLj|xI zMlh7kFhXpG5%SD1^i`f2hJ}q+oT33mrxe{>iQZDkpWAWt{D!Jp)Ia3;1nT4Io;QC_ z^EZKf%BTh(+ny;s6G2B`+VobOdiBUDE0*A`sM~eZe)rgDskXjlbdzYY5=XWv9(ndS z-Dpvp<*GKT^kmDbR$1aU>m+`#L8Ufp@&`P_Qkp6f9G2$bPnf`5ZB{P+O6LCvZPp;P z7VKU@V?*(Wj2-V16Toc{of2k;&m-$%>P%+1M5RxlFF1BodWVj{KZ}{+Qy={k^l_Ep zWcz$lVZl%Nf8+@KuM2+q_I=?9{G&vDdl~$N z_!>B!K1tyc>WDG|55HrM6Xp8=@L#~c$1u{jEjd}fW<3%`e;3EE(MNKIll{zOe9ZQw5W2rHAgl~);fsC;u5F0xJYGX$LW$XxF89Ty< zu_KP2u_LfDb}ZG#j-|%fu~Zv7mKtM6Y=>S|HyT;K*!Y)J)s4aFr8p)3vZ}hV@IHl8 z@-MHd8wW3iQ}P?C>c+!s#3}jns_M>$*Mw8}#@G?QGIoToj2+=CV@LSP*b%-mc7(5t z9pNiuNBCsy2u~S1mU_mHpa^5f=*bwM^IckDba9m?vE+-N1~=S07wQ zKVO;9s6Fhde(RlKNGqQ9bzXGU)T=E;_RbJ=^}Lq$I`nyU2%o^_W4_lAP!o{yPfP5} zRSIfb6opFcIxk8^_0CG{c^su?H;I+V_;1RLzk&7fRc`sD#BP|ccd^lAjj?$z3et*R zgI8R3Y2t$xtBFo-YhJdZc}de6Rr1tN$yM^1ym_q%i}G6$zI-ey0&36d#Tf!tMUzSV zm)Dq$Sv4jzNmbi2iByAHR<_K?LLnJ7t3FrF8mDX4lNgqun$^6d5o?TiBR#4vQ6E#+ zrOeR0)}DLvTYDbtsrKN573(`KT&~6Eo#AQDY7sDuWq4IlcxPoah>GWRI6g*6s#r=S zTddR-*J8~I&Z}G>%dcGj@-L8UohQi*xuPczxfWd%({jc5;It*iWO^1B4PLPv;rb)W zR+XQGpMxo{@_jSE@~zN@HyQ80?Alod89`RX-^V8zi2=Rc#?+dW04^AWHp4jp#>5t`E(o=I* z%Ma+5W!KoAdst;OpuNO3<>+^?^K0h39W%$7b>x;G`d zo;rM9C|$Z`N@!8&!a-f++ZWP;-!+lLx22~!iw^g%w02j87wz1Xc;-<5gtfb}V9}tb z4+1H!yZ3fn-hKGM-VVjv?}6?;Fg-Ke{hsYkYi=Oo*7@xmSaY|3kC5jb-M4HZDcm$! zNu1>^LN?XFyz9Ks?y6sI3op9orUcSQt|)Hgsge|8@F0=mnuDpS58883j&ah*N3O-Z z>2ov}ogP-ASHhR^P{%VDoqA5W=+qwPqW2U(z4@5`hv;oP7WE%&+v;~rOqcxOIN$W= z&t%^+AErOcPJzKqcQ}5_sm|I{=!er#Nf}w_ta~&ZZqGD~8H?-2(si?q&ldz^DD63h zH_0Gp98$U@TzsCg!MP~Y*5@8#nLJ#DSF7Vv95b`>7;#;GsS4M}TwFgOtDsTHarQRJ4LSD%RVpW8~u1j zHDNaT$+?Jmwuw%_h^S{19c)1=cBzc%xvMza=9K!jIc3r|ryi9S10isFhKmqAg5>Ct zBS((_IeMhX(IZ5T9vN~RPLG6ia?XtO-Du9N1;^nA(^&WjgI5VmI-gAcw7_Je!1S91 zF2oHmy^p|^0?!n?Gk!aBr0VA%g#WkH@uU2>c05YI2gV{|b)>dfEav#{KwL3;YFvcMAMXV4aq0(U;{ZCSAf;nsk34_$LEU0H0>kC49)FI|P_@?9caj@Qet29vVE3bB@5P z1>P#~UV+K(hOd1dSm#08Xz(*T6#43>@|L|rD?baB2{bN;7#JlaNs>(X4o zf0^KK0OtCz6nGGR=*lDsbNubV9RF%y&Er}(0`oIMnE5{^_;2xeTx$m~mpftR-wDj| z@Ai0H>wCalUWA$dM}q%=$KzUEz+9gRGyhY-9RF`T9{t8bGY%I@UV|f-1z|H6pWNut zUF$o*EPuii@qk4InblKRuwSImN4_w zcy!mIsRx!PVWSh4r00q2JWWZm3<>u!Y2E12Ve16Uaw9y%@Z9OqgR;V_!>iBbz$`by zMdn(cuI&_9Zd4}BLzv~30A{%nW*(oepO--hqxv}%N9G}{>Do?#*GF=FYZ_6+W(Z+)mWSWM#1rIWf*QB&KK&GkA2^$1th9o8^$TVJfh@JC8 zwgcrJMQRXHXXx1KV^KL|JCZXwl96L`A6t>U!z_bH){afG%XZ5QsTjUvbKgA3N3Ae9 zlB{EMzg>~M!)}8}j*d;T%XWtiiAuVs{Jd^>D7TJHC7113y9O^+@Q{8D)zhFG1S+{O zevVB#R!h{mJh0Xc<<_y^l|ddp*Th3PaqPJ`vVM)nVx4bze2w~SSuZv`zJ`DHz1?7V zsAg*I^lVvw+3@%p{@L~8fZ_4A_p|f!8^hyk!e^KLpAC<%;h$ZuCHm_?J>5Fb!MaGA z`_LV1A3tI2nx>iKS)-nYP=ne6nIqQfq5D`a%>faTV`4>wX3iCgpse{W5!Tex=y=aO z8AG~~G1r{ON89q{$ivP`S~;gsR7loM=a6n@F({TCVpjA_0V`sU;>(em)uZz00&KR^ zY+({kuSRTiNRO!TK60Gckw$Bel4;Kc>S1N=(Z85_O~ljj`@cc-Qdr32|*yM1a|ZlegOO@nD`SWKx&V=;9<87*S?BExI=eoy*HgK-(iBE zlnJlx$5;ElR(;MwaczymXp?Uf3#{5UGJ-Qk-5fu@xAYZzjesj>I63SOPP5%y4 zh(c`mqEuh-Vl=HDZL3aZ;Hg|e;5Q9=&I@vc(O&IGvx9qFDV`P>ql|)}QARiD~EjKgVxG1~C2Ge#TcLak}~DZWsjl09cB zZ95kJ0!P8-9l?0myrY24I|@AW4wZ1iGw<-PYr3Mb&9aNI{Cia`)@LP6RBS_#Bs?og zc>b&;j?HuHafBvnnbt%t)0(JdN)xrrzOpV^ji5!7iFa`g9hc0SI~`st_A)LrnyB!N zCMuB8Ltsv}9uc4w<2y&Y`#Qgyss9UIkgzB(>c$1Bxwu{thQ$K`aiq66@4>dRYfRfu4# zig-kEh~Q%&t2KF3kP@Z7%Us`+h~~e8qFJ)I<%6Ul zf{%d!UOg59cnbn3z6fJS{)0jd!W?Wf*4kE2imUXXs3kuF^&*4k7>ENsvSX0S@ldOB z>8k=7XOE$M@WrCLh)NptDI}#~f{sD<1|1V2%!Ux~Mr+|F6`S(RLz77zJHN+kh%uWK zcJ)|+A#KjhHxGQvYqU1>eCrv*wME2d_*I zjl?UzXjxD1PhS?g%DF|xA41X-;nsueW%80#q*+-BhTI6aq3E}r-Yxi-`Z~7 zo__85Sm$ehh*{s+{o0GM^lLB2cE9#VP+kT8AK<^j|2xiK1AYVeE%^V9^A~_$0)7Sl zpK$(X;J*O>Ew<~mf8hLeoWF_lw`1wopNrYa^lQ(>B02MaNw?0IeaoKB>5Yk5r3>S; zPPxL`UOwylSg*YM%ezM`=-!>!{c!r^{;g17#A^24w{+i;zH#@^Ws%OU&YazL`m((p zHdeR?b%ecrL3ihfgSRd0PAAfj>^^xHR&pb?F;Vn76TRZevlMJFlp& zp|NwLJuJ~}ZQNBhzOfU$4UM6?OR<9doW_V%UN^llQ8%@*vaT9uodc|*-t*`<0$1T0 zdso>gjY7N1hBbEH2wFjB*&yPj@bX<{$La9IuClleuk0*?t`+3py+IuxP{(K0@h|H5 zraHc(j_;}C`*hsUO~(h+krWZnTKN}sd{Z6YQOEbx@qHWvGW}FyRzJw}oGZ#_oxNZW zR27Ys66wvU?#{<|pKPt-zn1Pw)Qlk?AZK67mt)rgzRp@@-`)bbFYMlZ+TIR|WAAJK z6}u-O`^>sa^@8dzjoQ&%GZy9!eUREC&A+jujuWkfKCxnb`25hsifeW|ljYzPjpk7} z_3kB|dgDY70eqPF#+&Qtv8lw59erz2d~>i${A5}w9>1BB=F}joy|PA0qb~N>rR1p3cN?)ZwUMyfqx|M zPXzv%z>f+1l)%3g_&I@J6!=wv|1R)b0>3YC0fzASzM=xt(B3d3H^L=GZZ0s(%I$o9EPIwwa}RYrg1R5E0TnZO+4c~x@(;yFs&0m-0%}7JuA566ps$wNrBHRX5Ak< zNf?c@;-Br&UF%|jD^Y<@Q!H4=6u7V9uL9=#N_jl4)g-b%ZzDY-!v-h0(3cNyKnrqVKm{Qt1r>Oj-l#bAFgX!}@*QJ!&6N2$j&^5o- z|4JzSY<)@1qxG}6jHZIuOt4|p-@o4^FqcIG@G$(Sjy2%O{PTfXK34#19=)cu&a<6d z4SE7UxU4m;HIHlEhCnWB!W{n{z#RV$kH@vX0j%%cP7qV;k)-9+VZDH1ByS2WGhuMiWFX>C?5o zB+HHNm3auW+!DYnH^R*0)3v@N%WbIOA`ybKR>1X1NjO zczn8k9$9Wv1rOouI>zg&k#;1-T#TQu9XVQ^N&Q5Mfp~nq!m&8(gP*T6NWBHhu}`7? z2T?Tzz_V;Au{Lh>H7NTc#9!^0?wnKsdN2^;=MI8|McpxQ*#S z3ZhL0Dai1wAO*KECrCj9eQ}V2OkWnHAk(P;g)}JV1u4jLbC7~OUlF7r&sPO0$n%mQ z1$kZ;q#(};P)Pqy%Xu{NOwX;LAkWi+6y&)C6s`4nW;=HC#u+(0e9-k%FmRA7!_nI( zCy!VSj#{`}JQV2=I>6Br?bvvw=WvyVRtVp*kE5fZ_+F!d^prSul^-Aw>)TMB?kTNK z!%sPJY^uxIZoeUs)Et|o73BMkImHVfJX9k|nnCwBa~g;5*uTWJElM|_)Zb698WL{7*g(iYH--0CO(gjr%ilAmpHXlhJbLod%&2#+O=Zs8{ zqt!es)M}pg$1JrkgXOJ2yg)P&r=z}hW;b)5KBFogRjd6&R}TJ!36^a(Uy+NylKDmZ z&HTCije;s-*Z^hG|OFgi-rLZ8SN;?C8DzG<5s^3vV@Y^v)nxS*3kCp6Wwo zDJ4!lxRDw!;~-$q-RPkpko+@55VCL0PhjlBG+iv(M5WKP*oUfLatHXw8GbHG$$zup zKNEP!AoNTOKZ{QC-zE6_0dEBV#UBv=1A?E#_6_ha`+)dqoS5BkfYF1oBIyV4zroD# zN8xuP_&@sr{HsI$1qs~XAHl!X@RNMWNqx^=;9>W12t10;!3+AcSoJz7OxB;%1^<)4 zlXX{~qfox&pCI^?2t6Kk^UvrHk)z%yIp#llea|A?imn|6h4~u&Msw4oviHAA)3eNf zQ)V>3c3@sP_~JQk2a3_Z(!3-BR~TBsZ>fiN9Bo$Q^YeQmZ~+tb6=gZ~Lx~DLe1nr3 zDxp4MRqoT0)p(ICZ*N@E)NI**L*F75APKhWI`4~%=)U@)Qs8F z(RYm!Q~jEy&8c=PvG>tav)QGm{)aWD+4fD_#prYM$2sgDZUJOkz z%3NFHUdSY zvw;i!Y;0B8pd1v@#;oOGdUmR+FQ78l)td<_WLEtwzqU{a5p>9;dR0$UJyszgsF3Pf zJfvL1DTD|rWOD5k3MulgA%Y62n>DAVZjuU(dZA3zvCf=5qkd9dEkzLXSgM&Sd8QIi zX(rE9^O(^Skg9HPOVu?mq=GpCvgl8;=ri@f5IV>_$%d}_PN!!P&cW1PS!0j(Ij0xC;JwN#lHnQ%f1DVs^Y1g zSzT3|;|>H}-#}e+(@Jpz@6ZiUhWp)%LnLt@<-HhVAq6Vhi8E)`o0{mC0TVrr=`(94 zk>LC?AQnZ{iB4>7ZAX)~cqz;6M@XhWCDZR@93qLKI2O^qyMtAvvZheP)@Wo?y~hF} zidU3~%ERl-DgzX!xOL(z_zp6mB9#I9reuDJH!=blRJ?&((T@6|9x2l@j&wD;(faI)eZ&goQ|4dF5pg3nPSg^dgJyqS>)6nkwQ-^x;P!oC;N6bAQ zuZ(1%W|0U(BK-?-h{th=8MB#K&}=4_X*Lt{&1Pb3Hsdp~*-WfOna%hC>bx*2&1M!M z)u?Yavks?`#OHCezkx$Rh#=nLF=I;O$7M`uOk~=2=6hgPk?GT)Q#5blP_AlzNg<-9 zg6L1Q_ZR`GeDW#3{WOF1C+_l05Z85piOQDXp@@(%H(E%Hn|y~Ol}4!lbZqBjbfZF5+K$+aYS0*>`VRD0`XL19qOl}5flbZp?7PHWi+F7-eW)zZTa-@*4d;_G-tztYv8veG^#pEs)|9$4)L#t2V2aN<+uKoI38* zh)q()eU_3)2F(dww~~AQ>S8`YKs)j3HT+p`r6Gp7cnXY z4f|$gXb}ZwWT>w_m$RU*<&(blJe3JWRH(0Ar}CgECO65p=5~Fb1Wu$$LECa$d+B=8 zhF*TPs3*e%^+bl|wIJ`!Z$0^yy$&U{mW$%Z6$R^}W)wosnqptZWkD^l_q}N9nWc!T zV37K1RUV3zSx?Rk))P~4RUvXcsmsXDqMY@_%T9=bId7(xS&C@t$vl+@MKQUV6{shu zt;C6*vtQfk;pbFN4uKEnVPQQ&G1hCC)`t(LY!Pgt~xX4|0@`D1mq7+e6Bjhvo1{LCB;OVq3jF z0b!Gn)$EQQ&QW6%Bw#fxttFfloLBLlVCPr9pM)t&&-MSZ#mg6J8PGUP$~(iGSW7-t zE1wOVp;cUGg6aZ6b-l7vS9t|(zV*0l5&idL7UNWlb^v>{}^iq)_FlZU6O0)dS zn9k;2lNp?=Z}rQwhPVQqrwpdNmg=NDm+Cbz_tRyRs~6RCsa}}zO3M9)yc`9jhbIZ3 z#MjKD)!B8AM8m%JtX2MyBz+*I#JQ*mk)y2%b2GA*`)xUoa`X_zNuaM?ud}0=IcFDA z7f26-s*L%k=xb%XF|#|ICsynFRf5?Ws$X=qsXCL}S{M5@tSV5$aDn}h_5OpfMjwL@Z)N6}|{A+8VdN@Q4oR^~pqL%eo11|~Gz!NJ~ZNnjq z8N@JpVPPwQU);V9n~;45%RgLimD@KUJj1<04+jsxq z{X0jD?5_Mgv&&`)`g|`}U+q z?7Qm^2kq^ti!|(j{nlHJ zdxxLWy0_!xMthhuXOENKbg-~<;9VVsZ(Kj5v@yM7@cx5^q2lzW&hZ;p_Cr(NX+0RJ znsdk+y!{UcDfRStd(J)9gKM9P9J=Wb1NUFMw`2eH5o_m&efN`f;=Vom?n+-fcsp_J zv<@Cj-_?2O-n(Ypeg5@D&p!0nD~7@XEpaAsfW6WpfW?vsFo?bD#xjY}?%*GTN%7 z1)1C*eInKcxgalh9JHU@a%lG@4|b$)eCV{jrPDTcmK8Vb>KN7-?b>qi!5jBNE^jy9 z-7y%_DC%~-!rxTSE{z`Hh+JjxmeZ{LU#pu6d`PUzZpL;tRtIlr_jySEkoa$u}$ z%T4y}d$&5b9{dvW`{dmnoa0>sQJ(6`Nh9>NyCM%Bnta-?AA9!ksfXrv_icRf3kM>5 zP)Y{}cHQt?fgb?h7nNo@Da zpytrPuB~_Pij3`!b?quYI53^wRk*SE5AZt+uPfd%Fwtd)&YiRM?xzM8b#;PkZ{e1K z(Jl(zh*09buK2Zqf7lf3Iy8LCO$UcV0}=I+w5mUho{5WMajJpI2FDFcW+lburd)H`vt`*L*fqRk7}7r@7*qM-cVT zt0-oCNO_LFn}~ldd>IeD9=!b2c=4>3@vtrfMK;{+#!gUS+u0 zS$W>YDnDldhR-g4~v z5X{i^4l;CpC9ZGB^R{AxnsQvCn6l1f3Bs0~+MQc_Ve4a2UX z0(F9?DPU=c`Dh9a$6;MJx@1DsSO!MQtTF1c!YoU~B5dh}SfTQMoK*oY>RTq346@Dw zCFUC_#L2pW*8`1U~rzC#7Hg@dK#*PDgW5*K$#*QaS zW5-%F7`hWvKy8O|+_X}2PL7&?a@1Utqvo01aP1j`33CEZ$E1xM>5G$$8C!7FO+1Xh z(D>@O^`hO3zar?53QU^->$L48;nP%{R`NZM?qYE+Kh8nGT8Y|D60SD{)HahwQc}r{@nuqL*Tareox>KUO9Yip};YLU4i=uJV4-tz^4d&y1-`% zJXYXy1pcJJNrA5vc$2`l3;aES_Y3?}fqy3OqXIuE@b3ivFM3WsKLy4&fR|QS;Hbc50w)Bn6nKHaHw%2Lz_f`9-`6gI9}@V_ z0{6nyG4uBmm^M*i`dI=`6Szs>YXtt1z~2`5Hv+#a@DQi~a9YCzK2zYa0+T^2^UoBx zP2g<;?-TeXfnOE)ZvxXMEgb*50{4Of0@KF{e6heA1l}$1R|URb;O_~%Pv9p7ena4s zFpJN57$Wd6fzJ|ntiUq`zFOd&0(S}grobmaQGnB(Ebvl+ZxeXG!2d1q%L4yd;J*v} zmcYe$Cv&=`0@I6~>7Nz&Hi7RH_-=vI0{=?j7X<#Jz<(9^ZGqnx*opc1DH1p?Fc~Iu zo)-&TSc(sN^-i&qgomQ7hf5X#Gye%5k833aK1J{pz`lt2`wM)wz!wR;Sm2EUZxwj2 zz&{iCC4t`+xDn>F zxHo3Xm}j`a69sMp*72jyCNRyioz8LqevIV+%yE9!<8iIe3*6qv=lQ(Ay9EA;z`qmt zHGxYp3B_p*75Hpmoj2E_iK>LjC*cNDS3fEEFZOs`>r(>H6Fldm!^vqi3A{<*I|aT^ z;D-f%LE!fV9*8Lzj{h8iFA%s%;57o@Eby0r_5HdQP3xR$?wv3#MGTj`6POL{f9UbJ z)&l|`1m^sF4V`Dk4+;E|z#&WwGS6`WpDA#yzzYT5DDVz}e<<*y0>2>eI|7H%Y1jAb zsyeIt{PUGObbo%nRS5wwo(Rl5=0L!!y#O zV-q%DmKEV^T!|;5^qhm1&R3>hR37>0t3OqVqf^aN{2rxgV<-jZx z!bSMOsYM%DCM4s*ifktdGmlS4e+G2=Q8|*&JcQ{-b&u|YWkQ&Fe7fG`ie)lV@DOI1 zOaT6W$a@#~D5|r6{LIYmW|I&$O9CP)u0Rz<5ds2gTN84DXdvq*B3d*F5Fi=|O~M@k z!3&}-8WGfLr3%4_wtel}t9Qk=QmnDn*0y+QOIvMiwJlcLD*OLF=Q8um?gnVzuAl$! zedm+ReCIjeIp>+@T;}Y|InSYMC@sP!9#0+>rH~t&5H=i7&TW$Fkb%NHM+zl4!=sl; z#^H=w5RWq+XJ`2&bXMw-|wy^g>urn(7IYKxwkRlJM!TD3X{Ok6p^f zr@T_TmyyG!xl%dJ#Gz=ZjM7GB*s&_GSEZU{W>e+FEJd}^h<(R%^cj^4$I8snbxpe7 za4gDi(%!$Bsi%1mD}Bfc{_RG6ik}+bP|Zs>(!H94pA_H>#y&kBGp)2ha>}qzkH<_U z?Jqf_GIIU~DQ)QTBP|r24DpyLpj6JVoEL5!ovxJ4Of$x-2ykekabB82r)degz~Ip2 z(Dcnr2c~9SxJMEjdgt`^f3%iHXJHy8j77VnkXgI49{ia^nrc8zzl;-Qo=LDnKo4I z-}J43Tjs;drTsDuH1r!*4;Ia!xeW2mNcAR(xL29`k%F{4k9o5j;99oHM&)v0hy(hRt1Jt0Wd1LjvDE78`f=Sre6y|R@l0Lo)>zfhiMf%H*$Kk(BnXs6C>2e#Toc99mXGT=CVxuQp0DDI>XO& zT*riM?8#Gu-xC!7O>-3C&$@Xq`jeC%>t>^Sdh`Nw<{e|D9@bGw0X66Qj=vEUFqMrJ-?B{uRj8xe8`z?J3u%1udGxOJSF7D z^*Ed(Rs3J&bHut1*=FTWE1z5!Z>XG!x!}{`%x!`sH%b)4H}L?Q@!i{Yi@c_nFd294U=7f@RW3_|w=<(buD@ zn)|3rOle5Dx}l~nUS0#21Nv4oQKo?~vmstR9i>U%4QMHe1t^`TQW8tCSEj^LDU?`3 zCgz$BiKSTYvy{%sDBDJD#1gNqDN9t>U(%4MuB)CtrJ=H73NlFF77wo~tEq7bZX!B` zcw1`|M!K&M_G^^JCYA;)=ceI{!z989T#3~D@zR(~(f@;`0X^NqR)ya&l?`>5Ooyij ze{loLEpZuGVUtVs%d2Qv*t!*q=9qFvzQU~e=u&*;i9u zNZc^JwxOc3rtA`Anr^pJ2s(7IxmDF-b+#>re?hcazo3NQWeHENuCHr|S0)-Ru1!=l zOmef%FUMl_FO@_=2&Z3pQA17H#SL}v zxl))OSmp+LW^G%z7+#E87R^_79YhKpVp>tqAF4F4+)wN(w1=^5zWte@hQ zX*bvX1lgcfCK9y?e0_22u{%4}G*p90M;dZs6iuLUsBbv`qPqI(s!Na=H8l;FRwmHV z)@3M9e} z=onB1aBW5{iD%M`HuF<5*vwDJWV6KbG@DhEnxD_}Y=$SD?6XWQn?Aj=rmmrKdfDWf zN>5YdOt}g}@vW&WudlA1?vjk*)kO`{%IYqttYFc3mk3*zmby!(O{+}QSHn-vOk%o` zdOZg`XBRXrTGZUC%=;dxOrvp3YSS*N!S!0H`ipBD;$?`C6mxUhN2!#>f|1;kKMm_f zw!kX}B^GaL?`)xE6NP<05-XwXW&kxK2IYTwa)WXP&vdV&uES5tKkv zKQ9$mS5=Q#^-c}(>UU}gD!A4;HDsJ{`Un{>0)2#>C4zl~Oc0?yLMDnFbHlE2C(C(* z_9nXHukkycT2@!tfc8~A@!X0MmvYKvSp$UIQKCjGzM!e2Sw7x{y&91fQH*kRztGwJ z@l(s0L#d%}NZp$%?MhAj5rYD-j%`Ya%dKcx+A^0s>Dj}r(>c`yXr}C?*GunfHvJON zQ5rF4B_zwCzC33^tXODOprh*cBiR6T$Q6-?C~m!<8>IfU;_?v1mA!JeSAdv9)FD=E zf0)NlaDEPTZauyiX7W`&{*k#&3-RE1g|dJQpL-#8f!GY}i#|i=P1uEQ$Jd%1r-OQ$ zI!Edf{!GabCi#`^?QQK9&7D}gQf70csO2-)ZN-`*! zG52BY05Zbp8=`p#%83m+!Q;wJo0AH0Mfs?)Xb)T8PuRtW7pQ zoNLK~nHJ(KZdoMzSIS?FiP@Iy3}MbbNV`8c^TZQy@hB;|8Sw3(@H_2_nt$xFsyafj1N0uLUzqeQok` z!sQORGx55lpyg8MS32hO#7@g1?XN_36u`=(ZmYMFsT7+6QNLV1GIU#&gU`Z6lMSy?zj z{^lHA{)RKrxG+NrpniBCB_QD|0mo2|Q$FV=u?xfk196VYS|T@s zUFiF?b9CRZylu&%PW7x8s!yQ$j7IJ(?rhgRx{eyS($U?5bE*4~9^@=!-A=kWMGsK7 zydguFv)FV^6){L%(*`c|%6LkTRz8=Hr8}eh$$bmEKYrF zzf)?6Q*K95?M!z{?9{ta^Z@m!)9zHpZtheOQ|=T(bEk>rneG(J|A`{HpWGi~7l^$= z=daTFudxd~fKeIYf2oz9qq~W$n_#a!Os9~ws~PLvGGB|TY8;a}9gAB`X;*zUBQW<} z7q6byM82AcX8Hwxq}!yM%iW7zAoc?GMK96$&#?Pd zu;&mmY#c&*B;yb=jK_$uf?j|;&&lBqA@h;vIi5qv<8T^?QA3R=V(I>|Sh{~KmhK;mrTfQXa{pMY+&>m8_m9O^OB@T! zD)*1Y(*0wxbpKea+&>me_m9Qe{UeUr{UeZe{|IEr^ELQFxi?#d5V&(p^Si65LR_-5*wfo0n<^Hi)yMHWJ?jMV_`^RGC{;^oQe=Jt+ zAB(m7$71FFu~@r*MEcVGBaYJjBaYJjBaYJjBaYJjBaYJjBaYJjBaYJjBaY<$5eMo1 zvDkJ02nlol7zvVTYF6@zpJ)Q;#Y1Kc8wVlPMHn8&9s`>yp}VwO$+ ze6~&h`p0B?)$aHIi?PC z#@ivv=g4U$pY_;yjO$YGzYwk_dzpHjM#yq*kIi~+FX=0{-S=<8|2htnX)ed_Yx<<@ zdxIvTRwAvs&hlb8k=}`Ur>L$b7FiL^Nz~H*C1ry!TYgTBTJuno)gm4$P45(ZGtq<- zQe=Zrl_{$~7-h0rIi>dJv?S@idTMx1+46MmzB~HA zkZJ>2JsmdfQ5f^xbH|E5l-5we`sjdr%1?=RWb>WqDG`d~#i zh^sHZG#*8MlVh@sKQ&XXo0svr#*X&+GIl-kLypEtkqs&(!;6BvacSA32goB_hzZ2f z4_7yP3?a+e)06e=dF}rf*&_#5rDo4rWOz|<UN0o8iwiaxs^370Vg+ znv;Bl@JwSt_#lQ%lMi{(uO748Q<}PZ-+&g7h1iaNH3a$a+$?9_v4Lzidanem_P#Q2 z+MET8bd94SOOy>v6t(JG;mBzjTH&fuCJ83Tp-YZQj z-M&G2U-&P)Znggr?7N@jzf~HFNJZN(?W?!sXT6^BT9Z@$K2w~m z&VtzEcLoIwq7RYC!iOhk%0hQ2B1l4z&y7qu=&`b#fmppF%PG`_4x54Aozn12oqwM2 zFxlskc4xYhZm<@WK?dM@3(Yz!sJ_%mFFuz_%xG)A_(pwef{aV6ZAG&+Ub(hJS9 zEq|SLTmCh(E&t6iZ$W8H(X**y&w;XJYj^0SZTr`RM9+rb;Oy1aSc7b1&!+NQySqdp z)R^15W#5VGa(jbqVTr=MJsX`F_lLXp?%ca&E9d4leh8))`XNFO`XmP->DgeN`s^p3 z|H_`Bg#U;X`T6r*dnAYC3SXMs*|qc5XOhrq-OjF_eeWiF{?KzqEGg{nNThM+t+Beu zf?fM8(X(+^SN9hW-Q~>avAVYe?{eCtbRAabDk#kD*<{^0FS+OTkoZr;*Z)5ppV9B~ zw`=RKyMCFxN%ZUO+L!$3-c9{_ z{{UHd|DM6gwSVYZ*!ax4U0tz+(^84`)hb4nkD5HHY?SET)wR9;vn@Z~wB@obUC$(Y zHtwt#wXnQvDAuCG+4CPI`!xj;c}<~2xT)WZJ^KzhcRs)N(6z~&HhC7g^Z9#{8S^c})dk%tefo z5o55avMUg;+!|`@c|g2GD*!&T&U$5g+cRD3^j(SGytW^2>Um(xWmt31CWiIOGq}IM z&8zIX?vPo9u4ltz4-e?QZC~>J0lf$I-nO-8qzE6VKejQCWbfqlzO7`1Z`Vf}_jDCV zxp+74#h3Qx_ujpA|E;%m<@eq{>9(yD$NR|vy$8YH*A;9GzxwQufC#kVIQXAQxe6h2 z%09H?x?Mw`?g})%gM4t>-Wej+0sZdhUE-y(t-C^hxs3GOwMpgE-mZR45`*=tuClGx zOS?k$?8Bx7Hjq}bPqyx!mKdjY)lhkmzJ ztrY0q@kaxCUs88xzf?cE@$HTBo?p*k%lb{fz-;Kgky%L96MZMtXcHpH0s;(*?t@7=aFuQ$AZ zTUXBz5gX8Z&sJisMauVV%?A=mD{iEe$GEaH} z!i&09cuVH&`^bamy7HRdNA3DqmnGYaKdTV51mWJl?|on9@-2IFd*9!RI&{x1d-HnV z0eT^M3+n$nTdD53wg1q7-u=)B?VYv1et6@7qpJM}x|~Fgto^1wr`B`RDo|P#dwMo` zJrL@B(CcDyEPtf6GmF79TNr@WmYj+sms3}Vctw=m1pVe`FXLO2 z9v}UZO^eT-QFN8NdZ}5&PDM%YF4FmpK0dbty~s=B-{_DXZathG=wqI%H?41q8;L=`F!p+=TI&PDWT40T3pi(6l3vC zdw?Ar6teSui*LR~OL^+>B0Kk(ke%xb|BhO4)cGii$g$$+O^Y%l^1LSfG`P*VwV&+} zu{#s-bDDU|fNh|Buy9+dy4yA3n$R}qANeZDu0?6ItpU>7KFL|N?Mu$mZFFma0km}L zfM9`bp9qwXl}2r+Fl2{)x096S_%|;60j;ZgbSe4`__d=?(SPBcVY$?+^HvzE)M8;+ z%h|SUTQImiU^{Pw$$Vd5Mgg|-N)9aUd}kHyzZ=-55UnKZBv(U57AXuy?EqGt1#;FR z66d0Abd3JM4itUSS+UJ_ih~1fX8_8Qs?FT9y9ygTKxcT+D5>dT_e&b3I6lv)Y(oQQ4XugF=21cN6y zYh^j}=icvv$|O(dlF{3VcW$u2AH!G$R^IXUWm1AWd=HD(T6XYsr)k?aoX-cP4W0Ko z)CJe0+^GwabPKWyeIbNm=3h+r%@AdJa1fICuQle1mr)7T6?@je7&QT$-v-9_1JY8? zo>iob?YxY2h*cV2R}v`oN8;GQM&}{2VIV+Jwk+jOwOYN{y`TG8JyD++Q9j&%2Z+tH`FOWr@ zN0&*}q3CPjZO-{PadrnmORYs4`pHIP01{kUD^$b<&im5d z)Rx`5Vw>||KgjLCM(54t+nl>m)Bh>9IS;IY(D@0DY$R+`)S4q8WLr$4#3bGv&xSFhB!<2+Aw&H0+M&G|L)weA^PmWx%(@*HlQR=svxmA3=3RT-4hJlwJ>tyRG_fg#WfMxbl9 zr(E$w>J?stvdc6m%a5`_c`&3*a+hvU{z?rB(hC$xyL^-EV%m@gbsKW4ZghTtHd2-N zM^++ttoCin&=O=jjK7dN^taolijd)K$mmHriJ-YpTl`0_e^kKK% z_yM(`vfZHSX4}OwlfQL1wFjkkQDoqA6u2Gcgg!`F zEwqi+*3NUndi`i8WvOl~OR1LX4yG;D9WqOG=Xh&$hrPwQbJgP9d2(^?Ap8QERl57} zb+2Wz8%o31lm^q*f+;-%!Gta+aAOh+kOc>O!}Sx{}pmiJNgYr8_Xp)`h7^7`E5wQ{b(~hbET2fZ#3G>k$!{G zW{%tCnUEtg3DR#S+UU0sZSkQKZ*Cw8FhVNx~7sJI+-tdoQ z_y&eQ&+z*Uf5>nPGSS4dh~b|yyr1DXjA{56F&xH>LnAL>cmTu4FnmA54>4SfLSy1N zmSI}B*vOw|xDvnbjQo6t|IF~;7~YZR@p~8^gb7+Ep5qvfG5iUJuVeT|hL>afjfv+f zhW9f30>dvc{4<6RGJIlz7v~g)7c#t+;inmXm*E&jxf|W4F`QudVumkccs9fH8E$3x z28O@E@GluIz!+hp!&wYp%J6!Izs&I082%Q+k2CxX!?c*NN$Yurf6wqS7;0-clNnyb z@K%N&WB4tG|HSZL8U8!NhZuG+RM(^%W_UQmwG3ay@PiEhoZ$dQD4ICWVE7V-H!%DF z!@Uguo#8_aI~cZV;?HHcKf^@~4`z5A!wn4I#PD|*KEQARUiz4H&t`ZI!f1&ILUAT4_y=g z2@FqVcp1an8GeD`ml*yT!>==ZfZ?|o{u9Hw7|CPw8PD)6hSxHD7sKCW_y-L4GW-*U zf5Gq@4F85<>WmnDPGz`;;TDFw7~aP4T@2sL@GgcQWOyX}R+w}rGW;oqCo?>S;Tnc7 zWOxC;oBI#li_<9-ofyeV3A~oBk=5G(jCU|c!sMOz7SZY6&2(a zYOYR~Fs;giEk2X+*SMUhSkLeh4DUASexBi73_r>6kAPKLQ9-_vR6o^<6V@wf#ec^5 zAG#bg<}t&Mig$rcy16HLco@UyGCU1fr4<$ABB&8Ji1*%c!sdSK8GohAiHbE0e|DIc z)+UDUWB5^qe+aD7iVE_NGh3%i*xc{Sz~){)a5+)&A;WJE_c*~39v;f@M24$@XUnvr zg51JfuG1y_M@yc>u$Di!QIR;qi78Mg1 zCVwikw9bUz)H;6(*x2eKmlGA2FkE_y$GMo{B@Exr@YfjL%kY~F<43TY?oeQ*TU3xM zkVRTg!hg_ueuD8!T~1U~Fg*HHFV0Ga8yN0n_(q0zGW-a`KW6wK!?~v!J)?r$T3n%Z zCj6Gxxe$1hlt;yBz*lHIn&D$cd7RM!wEYLa=Hg-P1 z_=j9hRM?{pKPvtJyh+>NKGVa;Gdz~zsSM9%csav2GyGo+e-~Kk85J~VeyP@(@IAV0 zJkR)Vx}2zZo8g~~@$~!)!~Ms4^3xcOGu#ZU(#3lQ;PqMu!bXQy#=qX>M8%B^FDdcT zx`p9~7=Di7cNh+gGwDVJ%~@{OIuJI`hVjs2I)g@#8(tB!=r5Ud-^dz$z`= z3-B79E@6}IO^m<~pqpVWZE}z(${6xtyr@EyFKQ@;L7@ zoPV|_KbhfLV3k%>T*2^ShH19pVyzEhS^*7Pd>OFO=MI+>6?ZdyFXMEbh~eKdoO_5j5;nNwWDPSwLO$a}u+s|>p#wPVHCn{z#Jhjy0%wzZ(hVNzghrlYWsCbLvcNl&T zc)6g>iW7cJ>+?5YqtBo+!-eC>{sTo|&=?fy0_1-=yjlwYOT8$QhA@}~kT4$3pI zx)&=>*ziea?A+*bqOy%q_h`kby*VEL*y8kjF#P4fiW3z#0XO2G^dW5GzZux@$E;fH|@zn{xNxdm>;^%Os0!;dlk2$vHT zJnk0Kn?{EfgS{+nD5 z@(Z|Aa*$uZV>JJM#(&V|!2ZBXHJ@-y^Irir@$YvzQE?D>x#kl#@qfVhAG#d;zOzjm zYsCp0J|-Br@t^K;qJkW)tk&@pHujmx__V^c;-EYOQynII5{^kM;x{w?7MBwh4+5`~ z94k(Egyw&h@&DW9p#211ula;yn*S28vCk_m2k%vYuhD$MraT;E{104C6st;@Hr9$0 zHvE3TCjLT~6O}Osfqc`as)L;eXJPcyKRN5%EPvo(h>eqz%W-{i`p;;X=O zrPzuSK1pH`|C%e0iWh-RyFnPQ8fc4C88&SNl}Xc95Jopra{lSc(GN#nnD&9N;f#0X z=+gq5Hi59=(05oRkBa+%O*=r?aJpT2RO|;<_1cOPE`lD|;`FUn$)n;OM!Bn zX->5(kBT#LOntQCgw1`8aph4_8uscb;W;{5n zn0iOpa6EZb#2`2Ij>Mp2%EG#x#}Y=Mi}WsN5dhkM z<2y{f+sHVCl{_kL2BvsPAHqf-Pac(ZdZp&v&NzgXJSw&Wn`b3q6OSj4iu)m7gMUhk zu;F-ew6~D2!#{Bd8;&QBif=)_o+#iDHXKhL6;DEb4gQJqB=&|wSjnT}`@p8&5jGr8 z&g-2Jhw#f{z8FzHq6ROiC=NlGB0CN#&D;3bmC$A8$BjK^8TC&3FGDamy? z6Cj~@@?8mDhDb?)E13idwIlsq3AOO_%fOS29iyI$Oai6ps)&0P7Oa+6F$t88`8iOU zt}67dg3^>0lR#;@ib`9w$E57O;<4ql%}gZNeOfw2FU>TsuJjYieCbq%l#7Q zTpTE;0#p z{+yo!o#{6p<3Q)z{SxSWr(Xh{M?g~KT5KG2hDuxlovAE(obe#!K~n5qH6A+m^Gl%f z$$kkUK~(%I=!{oRTmqfXgk+!>GjyiZnFKmhJWK+e3n3ZgT?N9iKFL|o`8dA>I?wb= zpfkmDj2q8cNSfkd66j3vFbQ;~rxBAt=aV2A?8O6}$r?-oohSPx(0Qs)G66c*`X$hL zhF=1m=ldnld7)ndojd&!=uEAxr_TiFOy!VCpz{X51Uhf@OQ7>6pJXC*zSS>*&bRp` z(0K?X$GY~J2%X73Oah%p`X$gA9U5F|+JuSFnOaCDfzD)kCV|cr&vD*W(0Q~g0g!o4 z$Kxf35a~kO2~sk;vw1n$k2V|sjwPXQH(ENEP$H)<&g_m3b5WoV4uyYGlR}ac)@T01 z9DRyzDfB@nH^W9bLmS25Sc4=^-R;x@vaDkbP7RjlPiiUEdB-BH(zmy?i1Nd+GV2`C zcB7U8gS*osfn<{A6i80yv@X}2{*ptvo4)Dq>GJ95SeZGu>v*WnJJzY`kwEed&50g{ zL%-8#8-Rbu+KxSy694vh%_)M|u~3vVY{%)#iY2E4`}BA|twjSRrz}G(=!a_#<+x)} zuRJ}TwOVwH-my?cGsIIsl?EHN zt&W9?onafLImb&*=CUzGbEx-#@%tHK!S6LKrv8LuJ%OTMoyKd^9I9E4RZ}U%pLGs; z)K!`jlN|kZ&I^|42F*E1a$dpy{1gVB(wak0SX-u&UOxU?bErj9=6ppmehk*tE+W>gQ=Ig=ai-=_e@t=G>&6t#p{JhWP#N-X&6<D}%G|Y7X_06lZ%H=Qo-|PY}hS^6K9($3kxOOi`Tl@;XFw zs6VebTEL<@SBt0zt2pU)uG1XqYbj0zi$TG~nnTZS#i6?D-!^Lw^_mnXz3tegIrK|G zankG9_cVw4T8cyMi+?+yIe9K8J)RsbqF+ENp7i`0sX6^zj?NsN+!Y9~uO8dEqUD0x zMU$`W!%q|U-sJholF#&WbeLITGJWN%jI{K{;e0f|JGRsy=F!U+l)Cs9UncFa#L48( zl2*ga#Bxf>H&==}@fKTxY+ZV}mf!!CQ!t?gq z7e%cVkU11y`8>C7eNw!&iT!!v-cE{h&&&~Vx8Hp+j(9u9b-phG=@ia$WR@Prs>$5u z*-Pd(w6-j27NZqzSv0TB;HKGFS7)hvhJ{+^H+PtN=-w`O4xduv++xSeX9~xyl^Hm0 z8r)j?`qW~n#c2gn%iXB_t`~JEDmAOQo{;(O)56rMqQ$B8+pT9h+)X~EtfvMmEwsn# z^gva5wcNC8u9Z_0OPi- z&~FoZGRjISCEjjK27XKj^WUT9icI`c!)L!u4L{Ry9TU=bTeFS84+)C@tDjI3dOJm% z(cfSx#O_@D*HdRdWs8-1f>9onZ$|bWfnUk^)T6(Yeki1DJpLvYMryx(1pc**Prqd* z(2tCijmO`^!l;LM#S!>VGk!VnPmaKUmGMcRSwopXL#|Jf1yjDb4DmG-}CZ(FXJx~*%i9;;p2_LH_9LrqdYw2?&Qc}Z*wT`c(Gy0G9bHpjhk(T^ z+FRx?=!}h=b82kt*=J8Uqh!q3NwNCoO~!$?MoImFX|*br>%W)TYFPy^ITzt z8ycFMT3g$eVNQI5i%E({ot8;N-{P&DX_eE;tEM#6)FsNMmDf(MPt?}bR3;kA;}3g8AVK97D$OlOLKzrTHCM|j2#Hh zZCiqROo%Rs>C-^KOJCh)xX_Bj?uFKcWmB`#i1o$j{Ox0d1$R7?!pS%FRGh44TrWk_V&%O+8OeAQoL+RB`&vb9#%H3wxW{I z^vbfDn%avA4zHeGFL@)Xs}dymM0KS+o;-ujYT|X37gf|kE&JwaGipi6`mzLRbJ0w7 zoKcn_tuDqX9dRhZ;Sznkv@9_Wr=P(o9cPs##^Z1qPU(1gS>h}l8gNR-#J)+Vmw0bxhtlLc!BZH_JQlPNP$0J<59npB24Apt^Lv4iXgx>h|-(kb#!% zLUDHXR`xXw{AH?C;MIk0;gvzzxoyqD3n$i9rA}&tUxcjp3trB|x!lcgnJ?}cidARx z!o@0OiK6s#$`W~Z*i_^uwpYJv(9p>oR|sa$VnbYqn`kRnJYgvwbzKht1e2Dq|nP2nU_9 zEsI(@-L4_!Y&lU(&iX>LowYyCe%40S^4Pq(s3(ludUoI`c=-Aioh*%*dpw4BXd}*V z?yM#|b~be`QKNq76`J*3>Pcs$WZRU-W^dhG^W3@gs7#sQrq0k*#XFSE)bm8)XhIoy z8^*?X)|=7N*4jkBV9MssZEx0ttK^eIUV9i~wv9bI`^H|YjE#31RkT{7ykm2M@@k+o zusOkVph=rb^34hO9i1KMdCkTvNo{v?s$2ft?_$W2XVLPu_V!9zVUe4jUiw-orcWbg z+w|9G-}GNlriaNq)0>khDmWgLxx?`q*E82e^p-N+VDxr4)nFN@**4jI**Dp@4`Z^! zl*-gDBn^K@FSL8;u%*_yXC}p=?)zwUwFd@^jg^}h9}MC@(pI@S4irC_2Q&r< z|3HO6g$H+qE=oT8n7*6D^G-9v5Y(GBYiTT1rXamuwzM;v@$)VVW) zn@1eHDEZwV{_ureLwkBik6oeNdms40o}v8ShArLE)vvKT6x>{KF!^W76UvW0Pwsmv z2l-TSaCetykG@OAN%Ed{M~29I+KpTo+7_|ha&h~$ z2W1}2w@%f0uwUlEf;}P99IxOvhu%XTWemSGX-ciUzexVv?#S8tuDWqo-J!FZPL+4n z9XUR$(9L^2rh4aJ5htCb4 z7cLK@J5A$v%|7qhCeBprt*uz=7fD7%4IdHmO zJbaF`rs>=G|K{hM&rY15X}8nFyFaq zVleodZ`^z~Vk{Wbxgr6XWPZ8>zp{hC35S$*}>ei z?ffXY^N*xz_+z@+O1i1zPx&0oGv{pD!AOf;BauRM?S#~8OK@qqwC*r=snhOWNmrej zdeyIJA(BrAb02e7-gr|mzr}YKspR{DAP)-WpA8r8tC1JYV29j$PG#RgQCHz!jvEed z_Qwqh7Cb%4nLTl~v&#KPJZIb(vh(n<*fZ+&l*);zZs@;EnWsw+zdv8`3F+d~mxuN= zN9^!e>V%8(t5NfUp8xfb^1q&A+^&a5gZ0UN=kYb>fvYuk}ui27)S~=RN)uGMEsWqdGS})p6%!a3=My@=bUoM64goxv%8qY%?RE>Lvmo$c7 zWcVix|AOJOaZ~16n$2NwIm1&KewN|A48OqeT>R)T@pLe}oZ+h&UKqs48F?@Gb^xqL z?!?Knxryf*mxGzW40qy-so`v47`G%n&2Zo4` zWBeMIgIVGXpO@#w*}(7`hVN$hI}HDr;ombHzy~g)=Sd8Y1y*`S1$_il^}>o1?$I`% z#Q2xEoT#{r;fwI?#Kgap;X4`rHpAqZ-SB@7tkR7N`UZ2pwi{vNVd|HRZ)0kg;zUJ= z;Uut$^CWyCFu0uIW`?h0cpI>ZlRht0XdMXuOxxj$jQ@3)6BXZPco%+OnsmuSy1}nA z{7;4lqCqj7(F|8I+`#Z+V5M7B(3|w>T2I2{eFR&48RKtuIZ<&d!yE9j)}(tM!(Rth zaYhBb(5=_;6V{{c;*T=^%PuD>e#Y=?jPpZGYcpy6iDB|=Zsdc2Ra)>m1RU4t5;mS~ zPhk8{x*T|FV7QWTCZd~b;;&_RKEqctd<(EjH!A2g;S8+<;WM>uZ)f~(x*XVw;U^jA zVZ8G)Iy?!i;*1J<7e;R+@iHP#_%a>;_kfM3n>Sq!JUub|XJ8ZOZw7hzBZddy<&oi> z0Ibqd9yCn5Iufbl)dy{99=l9CS&BeY7YG|Z$&8*E13>Tyo`6E=MEUS#4A zyBv600XF59u;Cxi_%W9QZz;etb^L@4e>~&Uj9SHkKG*_sZ^zf+Xvz}d3HZkr-+-Md zKi>dWWy6XSz5xH&;@`&3lo|As-7-U1*+)nZW#-vb2l-TaDZFe0pCPe`&v51NNCIri z2I1kFv%!_as}8WqU&5c%oNiYh6|V!EGDFzh*RNc8R1CDed?#%58SKj8B?{Q&HQ~`Z ztx8vp@(*nCm+&Ob>2T%nS^_*n%Hg#Hc#!7ocI8p=IIzh_!V@*;DOc{#yAZ-n`%nlx zS@JFEwI{5v_2kNfkI6?WBZfoR;_esX% z>`b5JES!z?NhaXzY@dWm7douW*UTiG75XG}#TcK2Ji<`yo`;&TNa!5D1WJF}FM-lj zs@PRf8eLD=#@y*xL|g2aKxxvFad1j$F$t8W`p+a#dWug%9%1m40C#KBB9Acr{SxRr z01}$5s(tZ5=fQpnbf(<#yy}!d=aGI1bROlGKxb+-*j3P(tjZ+NnR3ySkVlw-kkG7G zrO!C%Oj9qI1Ulo7OQ1954&xwN%2y@9ouhsU6eg>(tDrOGj^|@&JaneqVG`(E1c~QkXgqX2-Yssd&5IPdJ1XzAQ7$?bSt@<2)FLV| zjzzXh-0y*3v?K7_RdOKN-QP^9SlPGi!=s=*ugL{_Q4fRA2XHW;;=BaV(nelx{~e zV=pK1F7B&7oFQaZuq>wmhmd*r+!3#W_)PsD)IV^zuR8G->lZ7o^vXYR&OHAf(^> ze9fU}lS(T+zpm9BY7Z4By_^{@E!1i$PI@`}wvNa1=s`8#+sLCUc~YoYc45`r_!aK7 z^$a8X&1`WM#E1E%g~Yvq*lA%I2HvJ|GK~53bJ&Cfe}Hd{nm-8RveJePr7<#$!ARq< z(Oqd_X@g$;4Btq8J<<4Iono)-pXqMQ@G_n^OvZA>NSPgt$fu$a`pjyCzL_0Hh_o~0 z9t+Ko|0Wdol)?Tilv$oh(`XioP4Ij8%lX!h!5 zH8OL$U)3!U2~WfSQhE%hY*dHoX($UtO4#-c{FvtOr@Of<6Tj5(*^}PzGac74A@5a` z3=o3iKlcPhXwy8SKb`XSXc*3aM301&EmrCY$R=i^HfYcwbLJg6zswWMHv&VCz@NeR zBY@|E-$sgIGg-sqZ&5*VAH)8^BgDTxh5z;u_}dwuo&l%hnVY(CeI8+f#BV$T|EG*k zz2YrL;J;&x04}{@+6VqBZ6C51ZH2ZfpM>A1o!$;WegIwgQJP5U(Z)8*RTU`^$kO0BYCh)3`}$usf!d;(yH>ca zyt<*Px~jIJe&!ey26l=m&-}DR*!*-HzDhIlcoE>IXNe#`oghN|bfU=Nr;|jOpPnsp z`6=E;(e~C#dFikDWmCx_^P33DUf7b@~UKIW+PwEqRzl_Fw?~S@tA4iAu~-pa@k!$FM! z`n7C&?r^mKR)b%j)yK`)Y)vRtPqRy`)tF2=n>=<jCv6G&IKb}XLLdgauWO6;B? zX!-1>C36iM2%@E!H8`(jz7lHO&zdD8qa_|xwEe8vI!wwmjt(P}iu_ODO%T~tx+*J& zJBYIO_NEo`aVr_p=qZ6&wR}@{Ex%1p<4v_ZW^2gXK8~!Wplw~=+Pr9f=K?`3T7$-! z%p2EX)Z7_flwQeN(UX*sH{w+q8M(c=X|CVKF(ODC`@^zo;(M}d;-4JW#QFbW6T>wT zmE+g&CX!67oWfNv>TGUrU$VFpfo6(prqHaK`L*nt`NNE6#w2t+m1(w2hiVtxvy4U8 z4V7(!duAq~PQrUxvYU2aSKWtM(}J^V*Fe^$DyqhLn3{r`+D80GEt^XNtjMx*_M$GV zYzkux#nzIKhCWDHweV?Kw(unxEu3CJqpEV}eGjko$qsYi)qM4WqQFvkr>j{v+?TJ4ope5=JsCSwPkC6 z@y{f_gC_b*d0y|9ed5ILB_oM{Hkt7E5#FHbnM##_S;kJR;*Q71c_b@?h(Z4SBCVJ0vE0Dgv$f`}Y8`YX(1& zl-CUYC@HTQd?@K&Gx+tSz6Qu#le@5|EN5X)WpH5+wCtG@Y~6>@eH6c&7WB|*l_D)_ zPiQQjgL$2Yo7IIEpYBG#L5kMiDK5+_%Z~%ow^FlFWumYO9L*b23Zptm^0J~e*IP|R zYrj|K4<|j`@YyPyry0}Xl;(6`o~8+FOp((YWQz0Bqm+}r#Gi%Z8+ec7h#v!4mN@=n znWg2vQ_W)2vj8`QO^xWstgBy%f&knFI$sM`1}vOEzw%Ulek#rfI)7PNDbKftuEKeN z^S2e1kajjXS2juc_qBY_imyv~$VNe8Q-`+E{HbxN(ythgiN?L0s;#>NMSI!h~qxfce5qk_3pUDDWi>=EZSmn?;WYxq0Jn5Ge~k3kD6XZ!?b8n z27QRbcqfU^#as4sHNFJO7<@UyqrflrZ1Ma78>(_1_m zo=Wy1JV)zuGO)S!lP(8SK^Q&}FQ*KrgyAU+e}>^UhF1ftbfaQD!}P*yoYsdh4L`>g zzX8~!^(B`R6+0Qe4sUV{=Wd3-#_)3tzXGh%iVAuQgfW5GtT^FIb-J%J{s%56Dn4ZR z4OCE*?)wZE;2nsO4`;XpSfz!9Qh_n1QKn1y44v-Tj9>3^FbtaE%NS=e-U^ts>KSeT zR`Ev#y*Zeu(;_@ur!|l9H@F-up3HC?en^}6uVeTwh9745DPWaWRM3y`GjzIyYjwKc zXZ%-O4$3^k-^7<_lkN{0{td(LGn|K?qbjYaC}fy^rk<*GAbgzG;TT{u&100y!NR`` z_s4HCqeG10QNSurOkYIYbu#`2Ij~gKH7h<6GTpYOO#w3Xu>u^U8)4n0l*8qXZZ$3^ zD!YE8a86~Fo&_<2s3VQo8U9>g#fi#g1daVyLmtCFw)i^i4F4KnW4F72&%{5)PxyF= zMSMGshQ9+?anzKav67<}Yc={m%J@$LD-ISp2R3z_u;IT1Y~p{#<)|q=rf$B;_-`}* zyTGPS3FNIQ=Y&oCsZ)AP`NXB}^Nxmo39C3oe4{Imif;fL+Y%nF)1u*vne2(jsatnYOa#r?Q!lP=YfwPfS7@ zQc3kV<8gM9PePhdJl;f$2{@y8JPBzy&?g~V(EC=8L%l>A!0b(#ps6WT7MKL)%k@j3 zbb((2rSTBrS3zmghs6V>>Asi*N+0W&Kxt~l7zav|&P)QONkeby1x-yMYcL6PCViL$ zIv4vT(3w(a9Oz6jd($dtY6`{7B+!{+W)kR3F*6BtrkI%oI@6QKn~XtIQwseO=uGxu z9O!(UE8#;NQHe1y9lMl`4{Jn6J~M|6WeoJep=e1v+Q=e~HB92v-Dz5oBRLdX`c|ez zR7)Idcsc=+8Cpu^%&|sbpMG;KnnU^FSTTL(KdjfM`8f8)*{(U1AALti||Zz4guKE0abO(dYQ=xydxfRe0RXNwPU1r7JFonAe) zb5gq*?oXcvQpQxs`g@M~+Twm1@QcgUcn`l&ewkq+|3Cs3kl|A!3r+oS&VtfD@3OFr z-`oDZk@jSjR4vjBA_W-}l_44K(L|w*Cr{JvNJ>+(M9TcuG;v9rA7R*gUdP;d3;DqJ zBduk2R!PZOF}cyW_k20-{W;WWRSC_w_lLalCda*>jAkQsqXvZY zgt;seztr&A!@}@09oI3TY0OFVWhhDU-$AV;Hr1u`k8?H;8Vaw%{~>DOQ?^*CCopl4 z1kX&diCX)Vjq{&iVKaf>2LJ0iQQdX(jnh7#@jFnxEAXTkNG&fmdeG5k>`!<$?ez8? z9KT6Vjg*b^7qhUDz@LR}T6FxbK9CbW`f=J1fbPhcv$ociEben;8vm;XY9IAVR}Y{x zSUGhSRnst{yQUt?TcP~<&atqR?|d9qd*b}@$fJM~w6tPSi1rg~)9XAdhKl09ysmnB zc|%oMU42S2QjRr)d~r)*iHM~O$6+=sPqluXuZ=-fe=i()uZ1Gfk0%FYn_*SXXi&3dj%5NfVxfqo?{Q#%^a#1Tn zgRwih^{h?8Q^P!yjrQJ8_s-nvwBy(&5CIdBx~Sry1}$pvy;GTh8#`Kkgr zF1bLCOD>S(k_%{Da)BC`T%g7!7szqR1!`P!fgG1yAjc&asBy^!a$ItO9+!-x9+wQH z$0Y-qamj#cTrz+hmyDwvmy9FEC1dZ7O9qzXk_*(hCeF3{tW3)Hye0zEFd zK#fZ-(BqQfmY9~UD$wJSv7QMnTUDUPCBtPlEn8Kf$0cKh5?Z#ZK#xmC`f^+{j&fWw zj&fWwj&fWwj&fWwj&fWwj&fWwj&fWwjx;VA2RSaez#W$i2^*K3TZpz@7HKtpw!CfO z;wCJG*VZl@JbKVzs0>y8wD4?wVx`{298sUOK{G1;)!ryWD(8BnvRo+xLyyM_sz3Uk z$I_VO)$0CBgk+nOJnM2fZl=+VBF~HB1Rh16l`t1cvN_4KE}SRZL_y7LgT{HZTmbyi zD>W3%vu3MM*^W`GsoC7O?w2kgIp@1Cu=vNR7@?%cOp?0G(!voWcp811rQ z2h!N_Jha(Zao-MT(6g?)>%_!2W^|vZw7WmB6WR^Ln4YzVdM+E-ixi!m(2gW;BnS3( z0~gVVpLIpO4*(ZST->|+_ATd;Z)y4wNiWPDQFYYbj;VlV@(N51k?{)LhKk~dm&v4- z82a&yD^ZOGlFVi;S%CPlxg$$9$RQ3GfUwn`f4(!^F0hgqgz)NBqab?Ksy-d#FLIsx z*IX-ykvwLNIz8#!jlG>40qsFad(W;u{gJ#L-NNNeum)^BxX1h8NPwx zARY{cQ_S$O3=d^^D#NtWsJV6)!%YmA;-wnB=R*aF6V~r{;$^_*+RwP0sAyogBII!{ zVYr>)>lwa_;s0j%2MoW#@ZTBEL*GN`iLar+>K8DakOAKfn_`Pcfz4O9Q7#8xKp8H^ zGtb=DsSKAfJcHpY8Q#F~oeb{+R{E%~HAc6QP-?JLE!}CN;g=%ZwLjxm0GoT6>T;q$ zrgYlz*MUu1gz2X{w)n5GGx1M^ZA|=xKPf39PIF6*JxRpNv#}2yP5gv$o3zQVTqb_H zKNCM;!|~)?=hQDfpTHH~SDX@@jrK|COHZXM;jeN~Meq(6yOfQ;zCkh1%wex==)N<> zL(wWbnD_ftBud-Ns}>Y7#FN@eDEj&OD)sK3UYHQuznND;s9uPNUJ99*J>F~$$@Y## zFH+LC#ag7^?~lZp&JjjktFia~I$iIrn&Z7M_TT?LgyXI5k}C{vg!gu2TTf+(Yw^*rnPSxFP^l{|v5kg#Yj*^(9Ilsn` zaXbnCBhY#@ABI1V@u9w$N3BiD#^Ybb!l?S}I0C2(WW~03L3HYfSzhCvKNHGTC@V6uIVg304`(kACI!U^;GnqKc#ro zP}0WB^Jd1UYadQ;k$rsK4UzGz!~Rs%mEVwqO2X>k@{j(lbv=qMJ;?Bg4rc2I1)9G( zGKv3HFRd|W1ijk4y146Iq;guk{u1?pmG@KB!}rB@Oj>a(NtO2R|^ zc7$3!JL24DN1XfYh;yGEaqhDt&V6=F%v5&d8dOwPm0eU*j}bc3xIX74>rp;!>J=#C z#uK&m4e{EVG4ZKordVzRPT@AxR_HpELZ<)> z;-WGo7X!CxWcvV0Gxr7T>`2hux%_%kQ(a$QQ`t~Cy`s8ox{gr>Os<|{q?U@VdC}aK zrbV;{r~NaElVZvpj-5hhxM(6!RDNj*Yxgi=zk8T)s(YBQ=N=|(+{1Vz;~plAsibfZ z;|0j`oDg>pa~IMMdG28z#AzV*7^$`oyWAgPXZ;>K$0lKpEvyf4wAGmg$>_wD_n5(8%EYyA8JrF{2fN&A6NULkb zCQ~H8(G2EYe>Kjdw{zg-zzR?uvZ!|^f8%>e^MpLA|(G=-#G)3wgO_BaaQ>4Dp6zOj? zNMC-V!BKvr!BKvr!BKvr!BKvr!BKvr!BKvr!BKvr!I8ev;2^)z6uIAMAYtEVBIn@8 zA=Nm)?-=U-;$6N^p4HAo_I$_4z6yNDINEm%m1^}x#^JtWq}cTx<5;s6n?{hDzXtcr zu`XZOHn&+&v(z9FqFFw>r8Cjg*(_A#`UC;X<~DUUUEDGk9#N=5Hh8Cn)@=DXV7jYL zp_Opcms0nvkZCi+r%j>O<|S8~LaW&*qoUTz6k3g5;`x-QcRG-I&z6XM8^2<7p3`6* zc}LXEqaQbJX>dcbS{|CR<_AQUhtFDTGM0zcuFX@*1B!|E{ z&%pc*DhpCWvziSnvYQQe^py>+=LKnO_bijOJueN?s4jQlG0Lj* z@rIqOnl^mRZ`QQntlITU*|qCa*|%%Iu86X0hS7s$S$aWW$=oC3XCP(OzRzXXzHeu; zZ+hVzNRtID(f_Y_OF&l0I0Tc7CEH*5xXnn(s;LfU*HlB`>LPPf>(>@*l=X^ zjRDHQi`!b^se1nOwngOfv7Ua;G|jh8=LzSsK87(_UF)|v-Aahb^UE1EfunC^v7tLpPmLe;(W_D`3 zpcT+}?~@c-GuqP_J_+6E~% z7UloWa#4QKvN|&s<#uT^+1^WppIIjB{KX92ZDVe+pNfrphElW4AFf@IPnm%+TwZt8m6j1FPD2 zBg;C#x-{tUtd@pcJG(uMNw&54KU^BxOfICBhLvvq%T~ZWqgKGp|C9#8R~kw_p3*>H zxzUNKMoYn4`f(+0<3Jy*{Vlx?%xYOE&2m||)b69x(s}eP{l8V?(_8v_nd1MjrI)W+ z2Fe;P@-N0)P*%5DX42PU@5imK+aE`M&dzdv-fCNm{=;>9VPAE7g+RW4bIJv0iXY|Y=Dn8x zi@g0kH%{x?GdOwAGlP?_W88G(Q$s{dym;Hz-TNY<=QF$ay_-C%sqoGRzSwid?yhH& z$-8=HMIOI*=C-bR$(~d4dT*0{8w=sLG2CnY{I>J@i@zrGJ?VnT7!Hf z+Pt&Lpa1BT+t0Ip)?fT7*-yNjysv9u(|sFNYFEE@bgA@gysxXf{_pe15959CF`1Iy zI-cG~>n3lyYpqIe=cfEu^Y+u7!;|Fe>kmD?{_*R`yJPs!j&%>ss`>mwmtC5?et*w7 z*T1@B<3qD5w^c0PdD*r5;brn~*NxgS>xmgn439m$YiRYx9azHc zw&eHreKmRYYdt^MvCkIWcTBy$>b|R!-&^y-^MA&8^__cP*eayg%LfHKUEcLO>6Nl- z5Bx&jr{vvIeqbxb`PjYv4n4H)p^ZB(x&HMVU)wdS`!jW?IFDa*)rL|1#i8UwvmSyL zWnpL%xPJeQua=*;W7f{g=$^jRmDfaL@-GOV|CNc!YWz?AN^ToTriST^q!)bUCbAo> zM(O0~bgp~-2AR%(|Tp zYfrH<#cyA`|9W5i!6s+MlyKGFK$|n8Dm-QHMjhvljXj$l99by3yB_S^`TueECV*9x z*W36zGr2c6dnSo&Y7Dr6yKJJMCL|yz%OxPbLN@zo;mM2%Xqx5(#N#AB#or`;uTKJTI2qrM#aR}rZR@qBqpeSqOyd<=^B9~XDfVX; zVt@MaI7KO+chGe_PV+ty+79_{n-@E?tZ>!Uc3I)dYn-ye6?SvsN(i1s)Xk^MWKd1& zfXqTe26fzu3kuhinOB45?!Ml>{g%8;M|K8ChTy>5!o?!1*o?taX+R84rmd_8Pu1bA=JESsCcb|fHu8-``r*?orM^ic0ON@asiC2x;_+|9m+xw*xB*ZgPx{o zN2iAhon_NQ8FNCRVWEsF`Fj=rjX&xOI$c-*>J0fiOaA^OlyQH2B-T4Afp13r%up{* zP>Y11yh^y!7Nm#^z&I5njA8L0Lly)0V=1P}cOm;zS%8 z@nf@QsMxHTCN^u<2~bb5PYbLwv!(8}rIE`^Lsyh$U0E8rsx-8&G;3oi9u#LMCuSL< z7j`v=6U_{$M18r*Xr4AN*}N`kUZVMd`Bbi&PgP*%Qx*F2sfq%zUJv54t5%}nQg7^{ zZPp7t0-(iochn8iLR}s$)V0wiDN;q2;w&;n#MnBE+QXE%|Vz>lTa}4Jch9@z63B#)xzJ=lY z8E$8IKf|9hoQYROOu9!fJQNpEzWq0fu(8kA8i(cz3g(c>UqBf}@50vY{hFbh#-0}#euv>N8O}h*`WfR>tXaizMIVL_12*Yq75MmYhKDmep5YpXS227e!}l=! z6JTQly(BPH+f4XXUEd#N{NH&TSL|cBt0`u3XQRh)#d3z% zFisUZeZybE@J5F3XZUG`=|jWjSPD#O@SzN!!f-XPvKj3I!}Kt5q&^qI=3Ev48=aSX z99OJk_&Ua!-^b@)!SG!S?_l`%4F8qkT-^FL=^o4QD2D5RmCdeL%rHF)8>Y{NuqjI` zfsM|aJdP{A&+sw~=nUsthVNwfF@}G~@c%G;fZ;+sj4?V-2UfPZqMTuRU{k7XCT#qF zHn5pZJ;UQ*mOjJtfQ|mK7&sbS&G2f5f57lV48OqehYY7vffkQ#n+gSCx!++8yri9joGYD_*0+fz=qmiV`;bm5kryaa?f&uo;69HvEl@e~ZU)#Wr9w zb|P%}6o=c`^AnGQZ#w{+aR_0OPc((qpxGF%9SPYDDbdE-^7n8Z~bgj zmaHh@owv5(pcO5bn@m*S7^1JGLKDWakP8;&nmanMa(k6|3bO74m%u*qw}MvpJY zcQ7EQW5^!DhU3ds`)u-h2ICMm*GF@KOzsgu@@7gvaw@jSL;g{i>nW;&5>%~O zK?w@?f}jLOFAqv!^va+FMz0M@VDz;?35>ozD1p)0kObqh_YX)YE<1V5=M03+bQFuZ z4x6bRVG`I(o@Wx+Oh>VJ>ah9npaeFP9>#&qR08~X>I1dSOae#aW{t?Bshr}7@*~Dk zTy|;$m;^TCrUsY5W?X)A32dga#g2l_xcuM}*i4%9{j^|nW>5l~^MexD+%qVF&7{Zm z^bCg0q=!jhGwERx*i3qu1U8d@3Vc1<&rAZF3xXWj+$$)7%@|y2Jv`Kh4QaCIGd#Qp zn&IRe7SbcF6Ar}QJyPBbxcwYjaO*N#h+tQ znMhnrs0`e00jEbI0g@8!4$|OQR00wg6B2`JLT4Nk27^kKV-+VVfy9KeD3TlsWZYl|ut7C-uaV!oDW4z)I&=^3Iqex#&Blw$Tf zR&)G__=)9yn&$YC^%KkeJk9Z=_)~ceE-N*M+8Y{;;|G8z~~{VI}Czb-f(F`Q)GGEu+I)m4jxRDpj-{de3#jS+RDvOL7? zL(NWDO0km{zg+82=FeOs1h)czJ$VLdU0gri?lKFV?+?4-Ut$|J z-u=X}IY$X`rMAZmQg~FZvzdMh9C|aNc+ELY=`bBBFK;s$pN22#C-~_Z#Q6&ue=Z1{ zP?q=6H7S-7`KyM=lo#JTD%Yf57!1jy)6!D)zL#pAX313kp9;*CPoIjNysW;wp|)za zoRnx`Dh1zmc2HB2Syfe2U0YkX1aC4`d6=Z=ue6L%MwN*MP=!gzHH#K4UWoa4mNg4X zaGdVk0{bpRDYYWy(Q~Ja9gmMxl#iQOeoocoiRV_9kE)t{{$w=I$@h(&FlFN8azwZ4 zazDadb+Uij6a-gtI@wuv?lfGthA8EE^J^AWmDkqIx^!~g;zhIYEsDqCGb;~eE+Oe? z<*3Q!Wr)v2-`a>*?eD~gH#*;m_j@|uIV{m)UoAplr7@eMi)!j;Ro7zrs@+IFraOvO z1THO~GOns()YP$X@T7C$1Q92U;zJ%2&z*qpX2k6nJ7MyaGR)hU0270HMvp6-JO;J} zrO~p=DPs|NDo#AQZ2Z`9=ZjFBnAj60ig28`9I7WnOS%Z@f>}}1IB!->6dyd8U(>K? z-YjAF$Eg*_;8I~7Tq+z4E)|XsE*18JONC8vDW7D5ONCL05nRgOA-B^*Jh&7U?T{Z_ zsvetR9T>_#P6vk42dYR=x0(ah=6%>Kq{^25oKax{Lk0Diz))cm7%C)z(((lz>jjFE zhWLS^d_6R=7};ASBS#g<$WcWya#WFw991MEM-|D)QAHFvsz^nSDpHZ7ie%)dA{9BR zNJfq-l98i|ROF~489Ay*M~=c;M~(v0k)wc21|-j=~y|qwwoRjsljE zql#4Is3ILXsz^nSD$1Ytjw0LJP; zw}UVR@EqLA(q6$emTZxwM`&nfQN=OGdV5ptlG>EJ3_-5xFe0SoIMz2T05F9$vrRAWsh|%E_O^=_V%XQ0biuNEWc%2-?0(v zM13_HC{hvrnGl9V8(RSPEg(q#_}N zOQdj&HjAWVNO@z!Kwp7`u5~eF-tiK;2Q{IOQwhIk!CIItO`y| zUIo{fdLs*=*+3CmjheEkp=P!!17-s|R#i7pxyE&$JjB~_tx5B}dMgpgD-#PMRhfj6 zNR=f?QA9QAv@BkbQ10T&5k0Q*OG#YGL$*f|iJ2Y``5aaLs6&jGtxY0(A&HFcDa9YV zKZ)$GBTMqJ~95nlV zNx;pTmTF&yLMgAQXNJ1=We+vz%}Vd-xeS+R)}{ z)`iMh@}#CFZV8?Z-YowappzH?c%)=x}5@y*eJJ zbR>SRV@-aPw(j0hkWELge7Wtp10CUL+a@}u?YXBq=(CZ8xsB%75_zoBiVzOaLpmaR z+7Qs8Pvg7}I!7&$Hj%D8e6F&sk1hH%Cfgg@aKfIp(og1_6qI$!va;s3<;EYB*66VG z1}q=h9QzF3_^hWqD`i!A^R7)5&F!1omXY;j&6Qr5lYWiUI$DYks!o`g_Nh&@_&%k2~;Pz#E(! zCls4A&4p*ahG%-(N)o$Q+_0^eXc||H@E9}1OLtz_ukNm9YrvWtV&}*19oOO95W6sK z=co9q1SVTS6O(_Ozi~^nl+wYAFQGUCp~X&b*;~ z)0vfFoK3$yZOvy!BRGeCd#ufE&p**ozL7rr8T-87LUC&a)&mxf!tXH)M{nBp*)a?I zHJ*Fxy_>gvcI3hs{`xdV8c!O&v-zw|{Tj&*aclq0l=`;M`eFZoh3yFWp>lIxha=C* z+WARGjzu}vW6zyO-+OFZ^Y$GDc`cu3XKy|FuE#U8t>IM4w(sbX7yCRnd(5V5-b39u zIre#8_BHQih_Ra{evq-H?Rd)nvo~!)NzZ@3RNRBI-iopwgBB_g+1V#{h&N+9GPAeu z$jzRxmE@G`*^&{HHOa%JQXcE6b9;MUw$APCc`p1zCH^0%FPZR=!cH`;j$~8kV9xSel5EP` z=$l40_eV|+SXj{s_+bS$+N(>mVjXcw}yqFz$jsMxd>HHCTvs>waGN29i8?i7!RThaQ5 zi9s!;DuXS^^;YEiHr-mrbbny_i9U@Zk4@V%vU$P`WxWGWQx1{MWHDOdTgcDy%uxIL z;2cY2+r#*1--%BtH#NTRB=!@kM5oQq6<>8^)NKQAWPeL+Lp|6Qs8@X&GsR;aBb(Eu zHN|_{j_uQUBtC9TXMa|68(Mg(E2EmX;;g6-7>#Y-3-oC`5&aF>>e$pykyU@wlAiL+ zzSd_Z8Tvd&$@8S6+HYyYIhr#J>M76E=U$dsTi%>mnSP0%LodSKJDX)6jJDX6%yq0x zQZI2|aa-w#`LcHji(Ap!qohphaH_X&57lk&-?Zu8{6 z@L3&nL{xtoDXx!Rb)w_w zHWAlH_x6+OTkN!1g)2w$XjNPvT}0AxOXBp=jmo6@mO7bT>7(ambes*q)1k{RlAnt; z`Oz$N)j;yenIp4CWsc4ooq1N)Sp1y@IX|A;xgbn0<(xqyX-mxc?*x4^H#uQeimqX1 zEnM6{uY;UGZ!e`Pk$QC=G6_Gv)cK)MAz}di(ngdV=a$v@jgOu5!wACj*l9(f-hbSO zz(|dI8$t)$PEWukdu=CopR;CfsQ0pcp@Xq^WrH0ma8~SH(g2;;E+?Iztln#fEA6yg z+nI(qN`Dr6m)enoY^MMU_N}rV%UN&PVM`JU!2eMgTT8I{#v2WG*j<+9IRBefzxY+e zgUWDjYN(geGzUlT$*M;xx6el^pySY6)1j`xPV2c3R@zQ4`J20MpB*mP*I+wt{FyzP zfipX(A(Uh146?(0oZ9+*&YXI(E__fZbRcY_wzD8oUsyRZ-46?pBFwRzP4o9^Nxd}h zr}JR|JOCT=mf{o}5Ik!VMZLHaKhQ_bGooR9|nW6|8WU?QK}?H0<5C|Bcu7 zhmLTbUJX0ou3uaAp`6#2+396cMZQD%YlHBedOJN=>P^et_kkVCmF~|a5YDyJ3ql9k zS%r2e|9kjz8lc2ZJH}4ScUJ9v-C0#noDlgnbO;^c{f9W58!CjmaX_S(+)=O}N9^6_ zEZvKIK~X{0)UR6OEZ)0s-@dm(uI=Q#PTuKdACn)-b8cI`7iND58?6R;zCX|0+aO)L zYjM31?30357Vm{AUOvgmLn%(YwF=K=hBe7cb?Qt)PO^8!kiH*h?H_LLQP#%MZEBC{IH<@1h#&q;uZ@3}w94 zfO=Yw8v0f!W69F}&howc-;k31Z$P1AEe++pLALisa`msix)`z7#^QYJoU`H1{CH3P zk5Dz??}a(A#d5B$RrTQSg{mI>uy!vD3iX7>O!7vg(9VLVi$WQ%k#F*m#}n*K1cS5F zD&hl&Jw>@x2&?uk#o?iRkTOtn@$EcT72lR5=qj8>tq@A);(BK(H6tiQfJ;#6UPHlE z#TR?h6PmSOP$)4dIG<$LKWWX}N(AV+AV2SfL3qR^*2mlR?EOq}uvYJWK1rLyXNv2dQ2^ zPNTk3E;P`hg$7o%&_Ib68W_<+0|;7ZU_%QHRA`}r2`w}bp~djjmU`D6sUf~8zCta9 zuBgSjT4Nf9%+h!U!}l=!1jCD9xZy8h_z1_B4`4VAr)c<13~ylg=M4Xb;pZ9N!*DL% z0WmuF;KasD`>iP99eTKSXca!VS2^ve65r4EUoiTgr(dS zUwa%E?+O~ei#IfV&c_UA-~}ynEQRqhcqqf8fK|G#pclHTv<-ykX&c5d{w$A!@GcD3 zGR{=IwPey-#PHP&|B&Gy1FLiqwh0*T7-O-bgqs|>5q+5PpY}Mec%I=sjPq!gZ^QEp zzr*ks4CkQ27@H4g_!NfEX82NuH!yrJ!@C%Mo8f;lOd+~Vx<@fQg5fB`H4Lv}cq7Bx z7=Dc5H-MFIUGZ0j!}Ri#bTe*2G2EZw6BwqKrOuOlD@ypss$q!^0XF9{&f{RJKf|Y? z(J`DT!*dy?5MYLLE5i>k+|KYmhX2BF209v}r-b3tfR+6SC&BO{hOcCJGs8b-_}2{o zj^WoBrWac#YF`naqJ8x?u(9n6kAphSFzyI?oPRQ$kNL0W*!~QcGJFBU%NYIv!xRq8 z=y{3Zj~LFws}9P3R~*CeNet8L5R>#d5-!#4#wox?f2GH9#Z-pR!WFCGdCre{1XG(pc#zh=1lSyVi^p-rZ4BRp&dPAM0xLbPpvT1*YMq2H);jM6HvC;4#}&^o z{37E#(ZlDz%J4sdm439)dOyeT|H?3+?#rs=q;F-v3iE_hrX_kDevF?_ z0#+Oq*2L7)Qpktl4@#}#h^pNBu&X!=4VA&-}=4zbt%}2tMeky2pef5JwOFISo^CQGf{@ss>xD1CqhmItYIhtU+;xV5?U^G89|=0+Lg()juF14<3#`3h1EpoQf^d zRE9fgWCH7J46R|X|W=*^%6M!y%7!00~(B{2HKpae!Ak2>k6 zP63IA1SPPUuG1I?HqQx4U^C6dWgOUiV^9K{zaNyq=7)k3*!)OP0-JXQC9wIafP?}P z^~QPmL6io;X38%nfz6cnOahx{LgEKe8U(`fpaeEI2PLri2SEvJzB4F+%?|`6uz6QN zLIH_>6O_Q_mx2=5{83N>oBtM+z-9;D@Xul}Y|aPA5A!q_HWvjYu$kI@#(~YHK?!W8 zvg&h&z~(|o{NPYSU~>*6eo&_&u$eea0-FyCN?>!JpaeD_5|qGZ3T?vlz~+*m1U4TP zl)&a=0+OMy`S_p&HbclX4~5N0j!R(k=|Kr>9vPItW;%C2Sk+J{!9^gKz~%v-ghzX@ zA*FnaUwDKEr!x+V>Od`EGCibM_mXIzh(pZ81l7?+v&cBasQw( z<&a~IW_x`2iH4MCjzwiO(Pk4Zfjr|_R38!-8Y$93wXQRpO_YNI$)Pw0htVN{#YEm9 zuQ(RP-ncukpEgYN1FB<=MQv{4LL*CBsLngqT>O^cFSzI+@@NlD0H8!)o4`*Ik3)GM zTz;a{l7WQeF1*wx7eD-vxwGmYxkqy{Jk3;Mg3E`R>p>gIlD!l~aaB^3!FNNcEB+HhL%rEd9pxCtqwj)|L25~tCd*4O1h`W5kbP6OoX zt?A$%@4eszaqunbgxv`*3nwuA6ld4WTzp9tz6D<+bd02V3+B`rTs?E{6ALYyg!v59H)wytL+r2cg@bxm;#wSLqN%Uq1x zw=fC6M00qLXAVooFExDD`x$<+brTcv9&$aJVA3BxSP^d1JYzp?5;jW@fG-o93{g^M z7{P#e)G{AM2gNNVrM_T{59PJTxNi8f8K0;tlku57bbrPy)RS&Y#xFGtA#U}d?45UZ z!~Z$slm0#3@J(+_hq?Ispd0?@ti1gN{LG%XChA8=`+XUYA@p~(Oa9V*xi7*0-Qh~u zTkqrfo5%Ez0-k3`Ob_QD%J|d3`7wsCwjN&5NR}4E|K>4-u0%;x6(cQ_qIZX=IhZBQ z`+q8ckVQAQtju$x(W;8^WmV;4$|g)0HLhwbN=m$J5(ahYT39}pK4xAk?9*_#OFA-E zduW}9nmu%zhgv*DBOZ&s9jDTtGN!U>^4JSTRSg|H^86{Iv<05@hkrD0`{A65!pL`jgC!*u?M1t{oBJuHgB7S_Hh>6eRlT3V`h>FkS?@;l1(s_Iy z3bvl^$LDzwn`tHFWA_vMWPDDDHZ$__hLkJFKR3S{J-0vWldKt}Ee*g{ zBHMl%l2}!pF;d#~3`*5JP}Q@IlXF04R@c|4W>F&Bx(MY}w)E7-SD6jly11U&S87?S zB+9ccl1I=d`l=+#L#Pma>{@$Le_3jszbSc{@6`DSl0k81s7tKUIM13f%Zu|O#}oc$ z*ZaE2xQF91PN!AH(k-MxGG+}=#jQKaym|G0g^1QHm_2X7C6sr#D+St}R4F@Sr8EQY zNNol_k~{;GH(FgbQS>~;Yu*a!zABvi6z+M(yRB?i!@R~Ca;?0+OYU1uN~vpirq;E; z`;WQyPVQRt3c57QLaA{f-Ry?LkHF1gzbT@?=;u`<3hDgnMVCsC%hD{z*PXFa>hd>I z>+-+-$6UUhyIhy%oZq6!Ah#{TsHSr1`1(sK%f?Hu(k%qlzz24v)RhNP>&iS!`f}0I zk=}qtV+?7k7cHt@Cg|#+NS*irwlit6cUauLF1EgHlrEtwtWx?Y*(?`7t9d{1aJRR!&Nq%;myfZ!xkcmGD>r2t{I-(v3^Jseg zS0+yScP8ca7@h@VhM}E#VpUlyOYhP7BQM8H~9(7eIb}*v<^> z_^rU6Mc8wOv*ySF74p|vb^5e;1s#~(6PM0>nNBF6?hep0=7#M^K)O>)(*x2sl5)Q! zgDxV2MxSw}v-XrG5k-4si+zMgc#0ZIG^Ez7(SEX2@FqWcpAfF z@Q#RjEM-LruR>m8iH-#}Hq>|=luw2y;D(^#%wl*c!|NITA;Ujq_;FxmgDdDJqk3d& zMG5PVg++HU{(g_+inkeV$Ae*G&pw7fVc5#>IXxIYmSLLHrEI_)0ATe9&WaM=q5X3@ zdIxq@y~sds&>DB72KV|q=z{&jPnv+-7@yP$M8QH z&d1fc;S>X_bX`GL?T2a`2vZx1C3+;|(>yN4am5)7ABIlZ=p4*2b=F2cgW*PouVHu# z!;dih6vHn98yo0inC^dKoE9bgQ*ATN%QEu~{>S6E;x7!pj84wj_5s6RGhBpgH^VuG z;WHVY!ti$(UcvBMU}dLzm)+RhAC~JrIbn{9;g^DA+C9RCUjb~+ag4`N@06Q%X&U4u z_`?#t2tS5D1K6}1OMy+k6E^zkoe9Hl@;GWvi>bdiF#blyzXjOTwQazvoLf=CM*n?` z{}YdcPi+I6xCwcOquh5-(bph4L z^BduaKGv73xgW-FlqZHm*z}<#z{YQc4ab+O`eOXnpK%BqznuhZ{6^U5@#SjnhdRf^ z&s;0Hnh$3DR?74cHhvoeZ2U&pq~*)G-^`qiBk-Z%lfg#kf$MNHM`9qh=r)lr8HBA2 z{Q0vu24jo->Pv=T3mqX+HhP9?jxRX{5=zUT*D(xRl$I|!6Eb7D;cvz{*q4;U z-iD)Eo{U3k$)mK8-JN~FR<-=W{7pj z=qF`HgR-XBGTlTDJq)LXO0VK1`jOt2qJ?UT;w0vo97bLQj9hk}dC58Prn7#bn06$4H6mfR|1gs43_M<7$0U1r*~xDGWR2}r52b_8 ziV}7QpKAYmABUxrPiASSuY<@P!5j2a6mWx-Bzv$fckuM|sY|)a1m)VS;Ap}9hk{s+IW1Rqi-gT>fS_(b~A3-w<0jb_VV zmz4Ur!iTaSxvU%h1&mMa>UG`l`EELu?OdRBaeLM={d9VdcEi7m@#%aY>xTbR#;2C- z>2CPD8K3&n*Sq0=#Q0|cpSXkxH00;o!FE#_+|dpHVBL<=VTa)F`EK|_8K0^`Xek{T zT(~`x8J|X@2Y17#Uezp=zvp+uzk>0p{M2;AH~kN#LHxDd@bwix(Ix-RZusrY9NgPJeDeW&N}cRE zu^ayPn0{)PhIhl?%=o1L!fyCKV*De(zoZ*Jy~Au4x^lR`8~%RAC;fZ7;afC_*UQOR z_g!wb{B=pGkNYt`2Ag7SH~dn@-wJ+fH~i_0Pv`sb3O{XwxIOi8{GMhIZ^&44{?&}1 zhJ9t-@b6;$%=4gV3wr}pR0ZurkJ{xI@6o?N#8v(1m`NoT3-%k3Q~3|Iv(3_2r-4@Jkt=u8$6;PzZ4gx4)Y4dw@5n8~$3x zKOX$5ZuoaF{^8*Nyc_<{82<$DJG$ZTVf>!pU$_Q8aSK1+KQlg^@73M#GwH%lFTJpS zxEub_j6WRwce~+_X8c3Jzpx2EaSOM97UNTUcym)68JnEHnDNiRzB{|&Z({tTz(4dd z{KPF>|09gw7rc4h@Lytlx+}K58~&deAH!SmRyX_{a*AHg!TN#knJs_K?LUt3sXm^y z*5?_-`4x;$@Z4_r=QBPPz3OiG6wcZ#bn5fE;a|b7U$)`cdhq|M+n=wrB0g(wEz^G* z2Dk^W7vk5u6mh5FV@+dCT5e_h@fOZ^qmuJqetm(+=-xu<-gPtD+ZUDSalOaz%V@wn zWvsCJVI3-~udkUulRhFI>6w|HZ8zEW_wZtyZ9ie#_ao~ad32hSsyD}Qc{xia@&DAU zxg0qcDx~K^g@SXTLh*Bc6BjDgRtK@Xv(Pi9bW(~zv*~0~ zYV!na+9hY=H+KSl!W6YImo~!}<3}cFW>5w7ni*8;6X?QD3wblB)KPjfEzLg;QzPix z=eaZ}4e!Jc-q|Y~hu=wMWAIxUB|JGwc=qHderu*p!7t`g<*B(;d1@|Io}5dSr{+@S z$+=W{axPV#noE@@=ThbAxl~x|xl}-UE)|fOO9iOrQUS=hR9MToR9Is!6@IzQShr(iV;n^^0)R9MToR9MToR9MToR9MToR9MToR9MToR9MToR9Mqo zDy-yOsyuHl6(npfRn`_XT2<#x9yxZw?3$(L(L1cNAvg@bRdMo^wm#ES_S&j!+}2ww zEi1Zs-k^cRdC`*YV-BdHXvgQ(>#AKi~5>0)5 z(o>^0v9p18%1N)@KDm``&7eKfwpjt&vaL$m;~C=Z^(5KW#l&D%cpN6nwq_DbS>h4Y zX0}yB`=lk_E^XHoPj}o23%3|$#1ffLqQCS?N+n)fmj#F}Amlj)ccrup-Im%i^x}WF z4E>A6L>6wZPn`vuD)UN;`)U(3sf1Q@e-yq1b3vgguI#B67rF?y7N{>x+!TLcWJb1iO6saXtg&g zYiOc6Ep%tkbCMFL)I}n769{BWT!0A#ojb|G4Asf>$!kFahboP;t&6A`O4>X|HRnmj zckwaO2l6Gi`I?nGzhaAysxBAx;DhINyX^ZP;&NG!tLX7hlEj1#E zvaKl%oRg2VBX1M*OQzOIi z*eTEhc%yUdmv76NR!R2|-u{$2_4yP#^^aXTH5Gk;?04~rVm#*HeSqgqayQ-PHSSiO zfVVrP-u^tr-i|n372$u|+w%G{d5=pE571=LtJ%EC@Z3q>mN}Bp8+eqIdc4?4ZLct} zOOJQeXvkqqCoQ;(i)M1`%HGng##O9`rH2V#I~=z^r4C)0Vu#+|r9({-HfQXQ8$F4> zpXP0QV?~Ctm!v zIf2ZQ_f}QQ;f+$%W>-~1wl~I~B3TB?9yfW5L~kZq?&0(+B58QIj7&smS)(pK59#T! z%)?GNDb2#SQ=El|r+t(Dz_=z!W%|F9g);Np(^VE8jpq?@^{}G4p?XT)C70Byn>zG@ zQ9?CjoRnta@U+x+Fjs%;EW~X!<_vXjjS2qkEbji{M3g72Zql)Y^<#;owOBXNjO{fa zOy-`XipYBlUs=vz_GD8ni-@JZ-ZYis@5c2sA% zrYI@Ry24Ou8{~6B|F`jzWp>m6PCx^q{`_sr2lRUIc?#V_8`uFaWu2|OvpR`O^3 zb-Ui5Qnxwb)b>q#!`AXH9UO^D8=$6rt#HFqt(l5>+nX8M`AM2RO*0zXJy>qQ@gssuy7@rI(ziJ5CO|d~VXoodem;;XSN*^+?xG z)RX8d3vb&?#*^UT2btq-Cu7JLqmn+RkuP0&C*jpsPeKo1pq)9)<1m@FGTv1lHGYSF z9W2gO9z9O3ub`4%UAcEr1rU*kG1WjdD8_VE2}~0{*VGd>`1Tnottr{*sjVs3rFZ!> z@0-6BC^K}{r8Nz~cea9JQ>{{1o;!a_ru*x3S)YOyd&Md!?y^)-Kj6-jLybxp)t*ky0NfO;7(2fRMalc3qDB?|e(3?@Am7lQa5LkzZK#F7$F=1NNP z*L9}SzNE!Oc7>ivUc2H+vaJhD(#A%Q#BDUU3ynbmk~C2l_@rH4e*7El@`hl7R9+<~ zNaYP?_Y_qG`wWdMf~H-gd602MFy#$eONxu&?udog;AATyGuJCUatmcbj_SO;^mcm^ zyws_xH7kOwp<+_6F*6w)q?tm<8VN5o)82JHV(Y#TPE9bAwL#2Gj2u0tv?)mYR|=wh zVZMk;4J&a{h#R7bLR`||!PY?f6_LX*s}~KS@iToFL|)&Rq1$kx(Irk&MoOE-l8n?g zi<2_GZ6~Wocgkb_^@H9vY&K&qw?^vkuneYGXS266lO?fVlqNXb8$$WlO{!vBejj?RVlcp!N zCTT?FW0hf3mPRjasGPmbn=9-ITzO$D(jOn4P&g*n=$XN?1x{8vBqOE8|W}+&?Zpcl1OOsy5z> zbS(4q?v&=upzPH4TxWEdHztV1HE23?!KFtz=3cbC^<_$|*^yFrOii&nmUih5JQi6= zHv+xJ!0RDB2`F-E40*%v!{rus$#6rRbO*9YPujP4|D0d;?J^Os@se9zJvdYMSVa2J zXdrLRofVn4^88rFr~IzUwJFZu`~Fk;+es$Mj7XY^-QPUv;vTcS9VQ~ZD!r^4vv?-u zu&IfG32SU$N-N{86lc~K+28h}OV>DA7reSEw@?}7`*5A)i*=};+p zyVRzh)|USCYg8^*gZe{M($ZXjk~9dV)Ng4hW>Pl zUGmB|a>-5SbC;O1kgTwneJL#`@21!(fB7a(N#AvWbjs*O)$?m6ES^8JMozXMr^pE} zW+)uDKc$X2kYdMV|*`bqn-e3v!wt<1le|N}bjx zH?`xHB!%`VXe7GO1rvGh;zHSIsMsY-dUxdq#>KJE?2Oc7N^tZEh2}YRX&s z&WokT$JfoSN$PF0Bc-0cD#f0@txHeqn+8dSYT8MW`Wezm=B5X|qd2!3lTOupGle|&ZQrT%Rvx#h~h zh$6DGT4oyEzobG;O>}VNETt*UppR3WLI3PBgUon&?M&$iyyB7Q2O~_W8?y6K+e7ut z>#AEfZdgA{x&gg&q8p4brEWMX#cmk*jok3iZ0UyRnDe7`OKKKPoHHj_Gx&~_x?^OD z-7&sPcXZL{%X!EmvJXuLZUuY(SRno6O`B)(l)7npirqBt-*uB3Kt#Te$#QU$=^NGC zQss4v5i3>CpU;Nl0`CIHaZ>8OH7R!Aja|C$U+E*sWqwyCJ&13ucYZfd-aa>O_aEYV z5`C;vc-Yz-H7 zTdcJ>^Nn4*emgC8MeNE8I^NB_4;)GvscheV+L;|~&ph`mZMPL~zc+Rop=li-%!qA& zZw6U)b6aeSv}HZnqRx`ras!L&){Yydb);9{y|$$}>-F}hwms86qNQ0}7fFkavFtHZH|EgRn6%hfwWW`1zPRJF zCtAW)&}B_(`&Cd|rqtH)7kH{e>U_c1DFQmxmdqXGjV<#vwqEAvXs6bqd>iG|3arKE zZT&?P&vjKU{@IaMM<^|>OsKto*Lx#!uiJ4Ma(RX<6D`FR;ZU{Pu@(}iPHeEP*tVAR z*m^2!`(;^6WVD2>sdtMKd3+yyG70QH`54S<-0PDL5BEu9@_$0U~Nf~tPd68(d}6?V%wCDT9LnPPi=dFY7d>Wmaio_$_Vn4B;-3BzpfSKpykE3 z)5GHKb+PrM+bdvqW_2tUs%{NC)s}77*>+2@T_<+NVnvXJknx~~-L#lFEmD-TDGz4Btx@U=QC3ZY`AL`whwb8Z-TgSDZePwLR zTkug!^Ojg_Tw3k+{!PNE+ur{P5j*YPW2v6CY>i#Ny_azA#dMiiEU&txLs;AMBDA)* z=Vi`_opw?*To*g7BBw!s?N zg!0~+L*=|Rd*gCQ%38yvQIY{yq|c9)w}wmPb{cY~f0WuB^2~rbrCsK(r#(w*NBg6+ zmu_6n_4^w0J&i?LBl)tmxd2-8@!k#LHnMNrj;Sq8znt3gL~Oe%N63W{JFleDgAy1X z-Bz&`g@J0Yje>upuN3* zJM6UV`|`roREO^o?Q6ny3Xvzb&^hCbcRaY`-W_*E4#cjR+CD8j<$IM^#>VH*kKJnx zn6fW5Qg$&nqSam<)s z(^2aV?EIec@Qw#tieu}~-in$YhNVw!Ya%PR`&KrGw3XH3fUPxa9{B~ z*WZ0jG&})T=1D8(Xgh4O61@tgHtUgGY2)l9`({2eu*2H4eKHbo=4=Bhj_mF;uI`qpB!lG_SqP)mkAC>61?g88bKg0Hr<>Rd0ZGl=p(j5^)X zaWDQd$zKD`>Y!e&r5HWe$!#NI_?9AC-?bNX#J2oo>K5yPsax#rQcp|qnD$+}w!Dy5 zEo`ed@^XtcpsZs%&NsFetyJ~p&6n+`9{;Nu!lv?3(SAWkYgqLfEyYe?#e<7duHyJI=Yajb!LUtxfA%!tHtX-1atVb=!Y!v?CX*+jm{|#^sw@q;}{=xs7ep zJkw<++?t9-423YI*!^L*~9c& z!H!E)+){HCm1||?$sHIs9iL|ppL%Wwd84Rf6v}`#KwK9^kJs+Nxxs2KYf`e2hZ~;k`~N9@5bX2L#7O4Vr2XES zPq+1XNcVlzGf|t?oBEBC*1RmVX1s6uVMkLG?XQ&Smg~6}J4$7qd2QKqDt)8tAgwDS zpsOT`vdZ-2N7J!wbj(n7sh#@b)^HBS2|t(eac`N)lHlJ_>j{;MS%LtiRxoYs+sdR*%DXsA=Nk5p+kZ9WkeDD8r@ zmv*K-*q0^Oj*{kSC*PKOBcRxpiuSYMy;0Te+fudtO-G&YB7-_sz-J zrenSvC#TtWB*&|YGK@Y}a-q_Om!pSsm0%X?Vw-551_AWP@2K zh>W*i>s?-3xN4-YF5utJ>aZyTQRw6T$=3SE#mReUd3^rSY%H>8KGxhnG>6Z#vs(Fw zmx&Yf{)w5Rvhc=4puEtGc{+At=IE^WHmNf^NH-lb4QqZr6z7EGE8^tzbdltEG9KXb zvd`_M&j1kr!pyPKUY^ELdf%KlU46B@I!=DDmS2c9_ZiK9qBLZgvgb&r@pP!Yqy07j zmv@%O{9HJ{v$9Ti=t=)5tcRkJcSJpqWr=w?_{CZ-R%)kU$}~dMC5e#byk49W3iS-z z>12i{{WVE@gfVdD(#?lJ`T-7F(ijS@31zHwR@xyeY=;7@7OgRO?AF6nI(C42)uE6U z$ESWr7}CpZCpX@J^&#x|i?hN`v+T5jP=+1uDK|nP+c^lEA=->2ShOw;huKbEsJF9b ze<-ws){UWz&sI1q8f~Yi?G%!>96KF4oTZJSoYkO*NqT@a8z%?}B>z4_o| zY5XXu^y#G1cauv0)CYQPr_a02^8F|q@mcXPmD%3$(x+fQ3Qch+<0EGo3Yi@_G?ejH zDCb?&kuXYR@NBO~63Nc?!E~84v@EqVT{{bTlofEtFC#f9sG-3~AiF4(`KM6E3M%!r zb~e%oX6KfJd|hd7*vRb+tg-NjdQrod4 zj;nN+Qf3`&hYD8ES@(99p-qD*+$TPPck`voVAh}QoIIytKYqiu8!+N_s&sbv5Zj4U zmv)%5V*iSGmD^mRN1*Z(J3HT5w4Z)gH7=vS_^ki1fVhqu%J?5=schwfUfD^lv+bZY z4Yny?QEPg&baSu}Hc^voI|rjdUxbVcg)Waj^oJQrWhmo4-LM9e+@@S!LZvXhz|Jfp z$LGO~p?qi#_fn@EZ1P`5u|$J-Gzcg_mNP>py@`CE2U(~vl!d%N1qfw1tILnBRM3c}P1ySG9IQR|IXBj>}A`)5$ES<@(K@6Z8VP~(g07vy4e#lb<=Yg!uY z)iz~;`$2q$Kd7bD{L=$OQKFuVVNXj0}9g#B}rzk{j(`A-C!MyJQkfSii zXB{A&>-th$ez~;eT2~Vm*%%1Rv9Nr5T#k+LF-5h|@SYaB9YKrPR(!ZniRI@N3DWHu zTFz1{`H@S4<`M+XmkV9m(qi-({qbwFpKfo^LYLgM7@pbR*_tjvX)*ihHUTY0kJ+YM z1hmjC0b1x504;_`mou~+r&hw)KTL0%^P@{=TIdpz7ULgd2l<;8v!5<)X`xG5TIiCM z7P>s8#atfJB_=I&NlA-2AG&0u1UH;KRmwU9}YECZ39&@}oFS;z_i;~+> z;)UcznJaI(SsLGowWIO<4DV)mKf@n0{J#ump&%JOy%`?P@YxJU89tZc3mC3qcs9e2 zGu+1T#W>k#<;h!7!XvQ{OSB5u*tW>yxT2BabKy9{X<+yV3_r&3?-~A-;XF9n=o!TD z6o%^e`dsd0{D(Y_D;{O|F~<1;3W~AkXAHm2@BxNZ^*F9*W%xeExgI^D zv0)p-j{+juFv_1;V?P_b8KIRPX<->v3FhKEq|`$PH&Y!%G>yiQ%olH_NnKL0<>o zpwlIMo<84u8UIO-NYeg5GLk7Brn;YMJUt}E!H(vN8y2)An+Rx$o<9tZsz!`CCWqOtQw3_s8C z2MmWX7&81L86EBj3{S#9&~O$qd;`PV8Gf4K z4;cOju(H7w2NSX@SDKO23NcX z{HdVDiV}W6+w(rKvA+XYaa`f__3?+mhLh3H#{(FyV0b3Omoa=Ju+dMS9{mK?kUfMS z)AroL_z!y=^bri-g9`^^PaDJUFx?FFDHBeH(03ER*7^z0 z)%sf*|K}bDV-<$)INI0$ONRF{{5OUp{Y_e~pidBX=yVAmtJBQ`HhI+75y$!Z$1;3AusUB?(0BDd*XK@ns;$m_2IH^vIId`7_|oHj z{p%Tikm27m{5OVs;o{un<4}gDFua1{A2NJDu(H_|^u@EkYx@abr0su%@%MNfSNx9Q zU!CaN@Fv5NlYIFJ3{PNqA;Z@*d>_NFF#ILMStlEtT|wX0dS2U4c&)a-0ND8FXpiHH zV;RmH=yOhBcnZVI8Q#qB!wkR7@IM$nbdaxq1j82rE1O-hh~ae%U(YaoCUGW9OxkG(< z5ySKmq4)JU5>}7CMf6}`bB?EY9E_0|KI#;oGm7Ck3}40Yc7~r}_ydL`!+f2+ft78p zpwG;_t?eZIkZxB?82?m{(L3ori_j9IIbAW@C3#g zbcWBbWOyON*D&0|a2vyaWcX`_4>{AMu(9WSkK>Bz z44*a9=geXFa)$3>_+em`mMbXM{p&hi!iU-_-CqKmbYJ#3uJ}E}uQATA%6) zcZJUx#PB4B>lnV8;jIim!SEhnWxp#Za{R0MTnN9feYltLKlM1S_?+P{8RyMWzMXh8 z-SflYqkTM*;Ta6CWw?dmp93q~TtPw1pVoE~-m2|8evIMQ8U71!Os4A! z3MbvFZ6JJyw&CxH~eSQhU zCjl#aTtN|JAJw)I{-d_-6viL#aa=Kp;h~d!{pT{=!0-(WZ)f;vhTmt{uJm;l04v*E zLE%$>uI(gj?osq+{1ZKnD+Vz!%t1|Id3z3fZ^Wf`kVp456QG#LGdfM>vRbps?$A*@z3@+u9(2^ zDN}u&qk)wkS5UOZA8DP057RowGyYtU0@$u+r}eidc7*PK$80PU|Vgf79c*;vI&cyU^GF4#QtD zTy&Ao=?kpV!dMjeWt}eJMLOO7j6dAtxZ+HPD;Vd<>AwC7hG#O|#PChPDqZ9S@O9b- z!bfTwHZy+AyX$(+F%hD}g@} zv{+HX>6YAxt^zhXuk|>txPjpXGkwk~V5P?u6lm#ct&_0Pc{$_X*lQIo+Mkvr`b>A)LfO0)eF8-60Hi(|L5XLyp}|2naTv zbSG&H-I;!b=%6-c#UbAM~^ zwf0_Bb*iKH`!avr`o44OS8M%h?X`C8+O=w*+I0w@&3@jj`0w+a*xaS?4MV}^`xO2N zu(KH(dL7X9Y@hHlw*PU(|B~m#=Bo|o;!eV z#E05*2fl^B7FhV*z>b5lT;Mn1Lwv%*M|b7^QM`4)~q;5T9^~AnN~@_!9o}z>X7}TD0qT5d(a}Vt)>>@aKC@Y)ZiIVLoBu zFID{Io)epP;M8 zjE4iipZSDK7Mt=7z{0=Db8vitKgfK-V*f+H!aw9WIKIGlGoP^VKdbm(@Ejap;Cq-) zSolvX{xhC~;|qL{`Gkf4OT~ZQb7K2&<6-8TLf}^ci~qI2j)UAA_+I7{7W)eozvMZw zsRwqsUsNV6{AR^(_ng>t1G~H~Dianyjg5&vWzUJtRlpChKZJ!(&$bDFm*>Q0AMnSR zPq<{UDPO1f`#lHaQNVJICM@>vQ2Y;gPHa93{7JS?SnPjX@gMXY9ADs1F`uy5e_HXM z@f;jq;Lk9h@Is4m{wn_So)ep@qWsnzl?jXeT41T4Ii3@ng}|R@`-FvGQv9W!6Psq> zhnY`!Is4PD_!oFiY_0(QBJ&B0{i}e*pCQkQ%_Q(+%qJ}TeTsjb=fvi%z>hPZu<&nD z{98RIHXj213iAmI|B&L}=Q*+YEU>%wMP z|BdYv7XE(4zrk~2b1SgqMTCX_Ud6w|b7FHJ@ORigVc~yN@jvc4v3V5uS>_WK{+AX1 zNzXz31OEr}370H3R$zyw;@n$QI%3sG??0gg0$zyxoNUr`<#i6{{$zxlWlAlw(ik&|LJ2`&Sk0jrY z%7jmW4oi7~m&fKD;I~_GR3_YJu_@E@J5Cg;nUckJzkFcCg2Y;hp-&eo4p)kXux+fhp=!S@bcJDUUUz02#Y`8 z_HsP?3Ve_`gvFm+8-S+!eXc7<+y(VzLzE*HcH1M;`A>7QI&v|)lehvH| z%ptsyIluLC%yF0@Ia^dF+{2vny&U75z&~U=gimMA-+Os%J^=hv<`6D1=WZ{L%@=@w z#vH=<*_4*@7ri_-vuZ=$Mfhyy%=L2oZUy`cE04;Ar5(~7A}7Z)A;7<44&hd|)8pl_ z`5(Z)VGdzAzuxHOvH39YZ<#~*9JccjFGt@C`~q_b%Q;B%jGR0+{|i|1CBm;`JHPYt z*o@5#ITGOs=8SuJY<>j%2QG`S#Qsw+M=l5aN9GU~&L6!T&z;T+`43^?#9of;Ah6^- zgoU%r%VS##x)CgH-k*$@&WGfBE04;A5hg7bJ2~zVAh^+rqcUOP1UbgdAb%5c2n&a> zlgGCIcr&)CA6SlW;ShFmY*ie>PL8}6SaKf1VkgKk)(81*_)uAd zg%jj%y!UqI>`@%TPL93{_)g{!7CS+Xz8!MOc?b(9$lX}+2caW>Zo;>42s=5h*T8q< zLma}w337}e737DB0uEu} z1i2fdzLz-MM;{0*IS*m66XdwpgZ!WIp|S`IC&=CS_5;j$N^uA~Ir3rPk1>a^ z*a>pnCqn)|nL}7Ogq_@tjZ4n+oZ=96^4L5N{3(3MXToA9$k8uB{u!cxLs&RLj{YPH zIS*ms1i2e~mz<|oaR@s(?oWXq=CTNjoghd51Nj%3Ls&RL?#AsOXHH3R2s=6YAK$7C&lycAuOCAcfU2b+y?!R;t+On^gqCo^AHw0L5}_h@@Kg$ z!omr1_dA8;Jo^=gu#=}ye|dp9Pbm&zCwKSbzhllbibL4R(fz3>s{5Ef35gM-E8JjVPP9Ln35B_u7_nu*UmZ>JSo#0!!(Y^_a5+Ob7t&G&n)wp;Xe3Ms3h-o0C5 zL6E@d+2AP&oTeyF2pl*~mX!p~5a-0efz!lM5;#2rl9K}mPE%Y;0;h>{O5nh0;si+} ze5SHWp3}%aD+zq2@lz#%&x?~1_)Pa&iUXf1_Qk<6e4d|_z~_08ED0R=JO`4O1POem z*n^}AKG!8B@R=+t4tzc(DS^*tCMEEBc~SzOS0yFzncC=5?@tqaCJ&VaJ|73knSleJ z7bGOj@Oed20-tGgBka`-pFz_S_zaqsz~?KH68Jojl)&fhNeO(uF)4x1Hzg(T`R0VA z1@Dy)PDC{BfBg)hAoQBd1(5&-K9t$3jWqGxY#U0-xzjY4WPCuN&=r3Bqi{f?&lQ;K2wja zB=Gs%qy#=wSuLR~_)KLf34A^wDdBo<4SR7t2gz#qOg&PY=d6a$bWD|m>$yE};4>V+ z9j>&o)$p0@tO*kMOf5l4u*=e<1U~;wQUagp=v)x&z-Kz{LDEoPZ|!JFgFOfT#_!co z-)Q?oEori&v|7?^_qtH+)nfP3l2*IdOBJWhwmL0ow{1*IR@+}Dlmr*cixGvEG}sqq zYe}QQBc};YlNnA)n(eizBly$Mg6n`WTGDFII4xTBn81v0_Bm+U&BIMU+qE*|~{1bY>PKs)6is7mMf$k>~Tr znL}5aVno)m%Tp|(p0tSnny9q=f`xQu7NZT7D4d|oT9Zx zP7q^Nj3~P7(#IUSiWH+WvII!Rm_xllUOnH)oCTIs`FP#I9O@JEj_Cu;q5dw9^B8kZ zn#P|WGKc!RVnj8NUH;6RQ=rN#>qKrcbZyRyy@@$=#meKnf;n`g@;D>Rp}sYb^G4>- z6{{G{$9H!5C+5)6%(L?m=9Dalt^wKQOUzjeRWYKYmR-KjoFz~dqsn$7>Qt~$pID4= zF{`jFVGda+M${U!O9yi(cPU19X9K=L4Sko3R~ zMVDQ^$sD9X;85?8U4G3RBu2SD&#HF&Ayop0dYJ68j5+pbMr*PJNY*n4=@jhHS)X0D zGv|D$^3LTc=1?ic=)$ZKNZ!qy3oM7uj_mRY=1~4ujOeV-F5h4dl~RnT$IC9iX3k5Y zDn`4q1W4xcWxvC6US5%NE^|69r*d0e%bbfWhc{BzE@N?*uR=)<{%OoE-Ig;SHa?#uVCzBV z%thu|uvW4;$JdxM$8)l|%a55u*}JoIR;H{MnL{H~jziujm)U%XN}jVcNx;@3=Fr%M zvy<)XTbV=mo{p34J9?Qz<2H_yEo+oH3q6N}P+sk4PQB-3`?A}aLwBsMtZYB^QRdLt zm*Zq}j>nm^z;m*B(lgAVaS3N9dkuSzIdtFTIN5XcMdr}BgyUqdPqS-XMO@@L+4{l1 zR@sH_g`J&j-@1}Ht2`&0mvl0R?sJ`;>@mHRIdre*INAPXlsPmG={VUsypB0EuH`s) zt0V5}wb#l3fIp=#$wtgO94&7}zJK4VMtIS#JIobZ@JIq<_Ioa#M^UR@f z+Pv70Fo(vd^EfBa4HK4?p2LmBiS759%sI|;viAmSm~)!vWb3DoIWz|A{K>ZG9n7Ke z4adn|Q(woN<2@%^);}<(#&fc9-NBrho|Cn6h&eN+;XKG38jW{8XYawj#+)-eCtKEc znbYMt+3VBKnL{I-d3E>)=3w3fbF%k)^SSG%F=}Tgn~Set&gq_$_4z{P)Oij!I@Nyq znL}euuB>ccGRB;fJSSV$jm)9n3!I(o`Tic}(0HcfP^Oq%4l`$w=Vbe+&oF1U=VaT@ z)=}WKh^z%$!co$@<*HoaLUA zZDZ@1bE@ZLkHwYDp%G5!Pcnyo2lV|L8>U{qp=ab3TQ4^Q1NbNUjiW=u`z{?HnH*Nz zy~Be;#tu!LPn>f1W#zGJhsQUMRub;mp`@GpH}nlpOpJ_;_74B;)bPY)QnzVrXjn=lqq@n+VS;+Q@bZ!9porE(5yCZuiPC_S35>_rVOPT3B}SqwXJh#XuK~| z0j$VYp&VLQHI=GB7;7=Q+CR2)=k9ccYeMJtSEsxbZN(5OJ4@1}r|ZWDuNlT!ux&W4 z*tmZ4`rT6#yQI|Axf;%t^P!yglpipX^-e;}G%rz<2e-d^c(QA33g>3x z& z!&+9DZTevPwly@oZEEMh?vYWPYz~i%?idq1xNY0`@Ls<)J~+B_c*3~G%)LL#v^{)6 zDD`ToDjw9cRAYi~d8vMd2qY3)Qja9pGS^kOW0T%TA6L<#N99(hEv3#Jt)hbM86g(< zN-7<>i2LN)Ap)sn+D=!3jhN1U*Qqc?4j^sn7^wwl8Fv6$wAPiCHi`XuT@*qS|eQkLC5;+tw!#Ph{(>g?i^k;Lo)T}^2-o1T!AJkXVgoPj$7 z-P*{MTpp#bkRsG&h(yYnG*j{bqN%)!HsPEP+pCaWkq$1oR+RS0@4@vUbx7XIsmKP{ z6>-km)yE`s)?S5pbpYOrgpFidLxz?-Ik@?%HslV9&0IEKY|9F5Kn^e0wrVF7sc6%Q zBSk1ap=G+gq$<1uCl*~#h^%~0lA%Dv+qq{WYU&zIB6dz^N(m3B3$_=brQ4=Pb`Px_ zoSYmV*)}za&WwA#9dzM0dxysc-Vp zT)Jx3BY2wOUoX6WRW?@P$I*aky3l z$(X8W)vmE?hF48(8=aaM9$z&%vTA&I&)CGO?Tz*I_16xL5A*hp#`dPReM8v79mB-% zz@As{Ts1U4f>yeFWZNpy28lG^?Y5Z0F)C&I_K8)!&Lc!#>fhAY)L7p|u9r46mAY1S ztyod&Lf^1+c(ioM=*Yg(-p0n2tt%T=_Vo8bvFA18BRh9ZmX>cnyVS6Hb?bSJ^$qQ% z{^5Ot6Qzx#6O-e(HjGXZ-aaqW7;Yw`LUCeb=jiZIY5OkR zNJTZpsnLX>wsegF2d&#Ryu}N#J8nL>J*OzzpHevIX z*rfFpoxROiU5QOvzpAsh1*-vU()y~--d3yzu}SM~oxN>XZO10og}VT^)}db zQ*WbPxAivJ^_t#hyMAeJi(Pm1w%YZE-Zr~_S?@(;W_e%#dYFCn`tl{+otKkjGb97u zm#*Eo#Z-M2XYUqwbr{$=JlQj{jknwxjqm7NXaWP3ImhTs4Ci~pvF}ovqu0-%{tHna zUVhbWJ@{2_DK_cV21Rsfr_NbmYHMm|)YjI{tesUmyLMsin%bAvcGYf3{sTI7(8s?X z|D2BXE%+48wfL@z%xnHz{<%C<8A_FxwO26aGYUhW^_~8V1L;4GYzbTLRMCZaU#yE5cNItlc#UuQkX?LnwxF9PTBfAo2_5HUS=>$w*GQ=lGsY2Z2c4N?Bq&vD`|kbc?sbM z75F7q>ZUdwzeD({*$KbWdcP9hukbGXNK5`aLXVbUxy-E+*)GK*%b5V(*&kmL**ZPt zB+CkbcN~S^BV??J|J+gdyA+=~m<#CCngo%Pjg4 zT0>O3^`g$+fz6lnmoGsYZuDlODd!;y@!khzxy{Vco9*bms+@Xi za?jKxhF?r!JKUK^KGpo59D4y*jNskCrc1Wg*AH}UD);p@40QGPZY;y+Zsl+eV_*_2wP=%P{42i(1P;9bv^bCbGW#h%DN7}6cw|Qx0SINqW#U-~(^O zO>0^yfw!1KM#q6Snqo@T?21L{A@JIyxxQQ$2u@RV+K z+5-fBT+)NpA@CLxWt0fqHYQYfMhBPHx^q0KYT%9yM>Pb#AW>`u3J0Fyao{+|Gb#$a z)dil?apx91K;S1PJ!lAlx0)!Ul)!PsGdd0&=XgrRJr~+r2>j$^u~`ZSp5bxeILA{e z?!ZDR2=3HmDNO^|yKi$>r-?EeL}pJD9MX)ABg09YQgPRW_8KBvm@G3(;m9&PjtmZD zRO`0(_g!{zm%U!4l-zv<7ZCQMqzf$^_C+SjXe4YL(2S15#wnaqwGQ;HZCKyakM^{A z6TK^^lq@i%r+|rwD|Cw3mM{d*mn03fvmVXE6|{6(y(%b0T%9n4g3d}9YOH5H8j&k# z`LudfP>R@)Foc56Ng8ToJ(`6p=-g@bs-P6HDPaf&txOtfhQ3iBqxxy}s-P6HC1D5! zH6{(w!KQ-zF>0PxuL?>LsWAjYD5y1Qh#CXw{V{5vR<8<55vef*Ln!F{grO#C45atR z=z?kWs-P5+8bdIIg76TuN{Ba2?c-l63p9yw9woyy^DuT6y@kG9E=?T^=D&muoT*_0 zPuGTxc1hN0pVgA8(*|b6a;9##8YEG-Ta7+X?;ju8W3%*=QT{w~qUKKW9Et8M-2&k4dEHN=4VPM2_xt$s`^1%GtCc_)ImV=t_%TFO{P!C0t4- z>0ZZIDXggC5Hsh{c?1qR%i^d*hOR77*vS;#EBO+~q1%+S3unW7_Z&ZQN>#~l)MrA6GS3|%QX z?vSE;T`~d3@#YLVkHB$fSsZuB&y@v=JDH$+WimrY+?+})f{#1o=SnMa<9KIx<+wwJ z?srV)--w$N=sW_)on@hjWO}YFP~6G<+$)m_I^yO`S`mEQAw5@G#GT5|l@d-R6Lis~ z(r?7g`EwqDpTL-on>*{AvyOJxa;B~5E^IFih!LHxw%pyu2gcalpI&c&b=;~dm}E+o%0AB zSC++bh16VGsF0g`Z8AAW)SO5wf{Qw&=1L_|<7iggk6Lj^&i#(5?AvGOc?60&nVx%Q zUViQgc?o(RL6yZBx@YF4=t9WN(entZEKbrrGcQZ`guFC8kD$upJl!+%5_M0=%hdA- zsw_^`Ju@#?_k_G;J&Ν%wbB^U`%s$jjIB2&ybj*gZ2ZV;4eh%AQA1WpU2#nYl?j zF;vQakaA?ojB6gI^!R0`_#Cy+f}uT>_t@rV8`(Q67(EB$IJP7Ai;hzJr631H<_J_E-yI`dLM7d&4Ussm6`_~{7Gi!tjbNy zbMzc9=jDOK@rJZKs3_iKRxY}{q&(<-ydftKN+26=NXdha;|&?PsPYo>96iU&`FJ34 zydfPIRbDn8^w>3#j0X)+Di;qr4k)DJqRPv}bMzb#C*py`0fjs~s4Ar4qRh*}gWg3O zlJKAbveAYdJm@&ukb;XUF9XlfQ?$thT!?x3x9IcI?;O1~A?79AqR-2> zbM&epPPc`amu<5?H`&h7tAaS!7GiFy4T8$FN07nJqYSoY1*NgC#>+~0G}`vO1M7P> zxLQNZo=Cq0oKIqoQ!lN*{&FK{x`UmYr zM`3iEGu*99XnYpoQMag~0ykQf6-bpTD{zsotiXFSDl1w|bw=Uxj84qpNV_E&$c&5z zeIeiQ*5>M3%*;wUzLA=ht7|c{E9p2vpOdR=!BhI_2;e8@h4XTCEv7D`qs-e46wI%v zb9dEoMV-3?J+7k8-K`y8QRnV#7F5)^yMPn2y6_Cfi5VphpBo1`DNogi|1C*Z8Sm9( zPRUa>n^P;P++Evgd8$UUFi+KFPR~;{n?;pWZbapbJQd#Y$iKdZlMivxUbwx_Qz3(| zq~g23JQW7b@>ETxI!}dXSTid9{7R3RF|EGa)aK}M?XZuv%$!!=ZD!@@aow={&z@G_ zZRX_Yam}#%&z)A^ZRS#R86;e1e?`7$2085b3A!R zH^*}s<~rCN-DW#B?T#|XGr70S@vN3Pp4EPir`yZV@eKR939PkscG72^o%C5}Cwmr);S!XAG*11Wab#~Hc9Z&kinkRh% z@uW{6ne++hCVc|fNuOBTNuO9_(kH(Cq)%Ww>9fvF`mBrGq|ds@PWr6lNuPCY(q|n{ z`mBrWq|Z8@^jYU7eb(`$&pJ2hvyLZy*11Wabv)^_&Q1EP<4K<=-%k3(+D`h!+D`h! z+D`h!+D`h!+D`h!+D`h!+D`h!nkIc>WhZ^s`AMIUs7ar*A43mpA1cBdGd9}??Zd4T z&3mBfGH{qC090Tc+i4faY{n-~>*$MKUx>%awnft$e(rVvnIm#Re=&R6PAUmZ-+E<=o}jbE4i*>0e5-UnLc-E1hP$q0%45 z`<|uJ6Qc#$I!~yNZI$0}jH~>Bt@1(pGvDaoZbLut4TQ}^<5IIIL1w-}WUs4#jhuR-O8mtv@4$Kq+Dg$(0!5Ko@Za*P z2Q@zxcd#fKqejJsxz#gQR9D~HRyg&znnHoR@w#V?SC-GB%n ze?vztDlYR*imLEVit6xAikh>`Mobl+vD_4E7gl4a-U67Lxe}5K=Dc){H8<-oeRaib zO~kI(chug{k$uC(91J-GXXm>2UCi76hRAwT_eKEH<5^ez;tQIlZI6n2{QybQ^P@XuAaLE%<~ zuS2&l{5L54_X^*v@GT0@!DUwVJx$?t3im6#7Q@H$>~V?8gwaB1DX#+-JApM}*p(X_y1zM&eIWcM_F;|U<2h93;Qxme?nIg{_ODd^uy#y&iv_}}xK*!)Q0pDE5a@fR@Spfjm~^3xHi&v7!9d{ii`xCd~iq zQ9cb=UQR>*-03*6X;b)&_F!|3!u<*l0?WSCe@J^He6o$#WL{b$ZKDHvX&Z!vzZO`0 z>-HS?zw~k(w<`V>ihmWb)cGD@sdK_&e-c>i@ADk@|L{^*H!1#G75^4si5Jknbm#TJ z5<6knPa69&9*Os#AeVRv^M5In>HURH9^3ylml!{(IG+ZVxSj@(`@#W;P z`9HuC3*mF|!BTz^UzPl)SLvKe4D{jTi^M{>mc;xLAc=+QQeq)2oFK=4m_shH5Ef35 z<3G$Hmski3C&=+1=8#J)goP92F{E-V0;w%A@yI6|R zEtExXeQ_;HlkevZRqp!QpgI`Hk<42$iG&L3LB zE1I(P_`IW_4a&a_Wb3iU_3e0(RzBx+=7fK2$ktIKbHcxZB#FW6W)1gG9V{T`QwBY KVmQi6u>LRp$|r>Y literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib_eabi.lib b/gpio_driverlib_cpu2/device/driverlib/ccs/Release/driverlib_eabi.lib new file mode 100644 index 0000000000000000000000000000000000000000..1464424a687bd967a299d6872969a911df13f136 GIT binary patch literal 654036 zcmeEv34B$>+5Vh!?zu?_d)P(1ASj3e2|I4tA<7bxu!v~5NiHOs&6@>KD^bu=+z=6W zi^_Jv)}__jRxK)MwbZ5hSr=-nf7{RQws!HWwfR5qoSAdx%)Lpjt$}`gonLO|yw5!I z&U)s|nVB;)@{Dk_vihtZ6GMJ8NfDiE^?xWdb>@^Q4rN6T#@MeI8+^I{x99`L{*~V! zUSURG=Kq~NfEntqb_X-of5?nG$9Dev{m+<@;Afs0VrKac=ePCy%%tBpn!VpUa7*%M zEm*-i{oVN?vpV|yGQ_MTeu48gvhMuZl|N&j>-YKwW_R%mo_dJ!--4wq_<4Un+Q@=Q z{8HvT!8-lj@j6TSKlV$zESsg>a6td%(V99Yka-PN5qVuSf3E6O zT$~HBac)grO>+~=%b5=i^;PpCO-#@w5Yy05{s4R4fQK)R^>IcP_E5wKu(04E2~-FyyDW*a>uc-rWS5`^41@*;C z=9Qi|A8Atbl!WUVSzhrX6k{YxF)yfVsSP*RG}QB2l%JDV-rQ0jQ7Tz}Ug^B@Rgvap z4fT<%!rE|Cb-~gCQLL(4W@m0CIrB7ME%mhxl^1iR2!L@-(Fp2JQ-r|MNL{$Gx*-~I zTs(HB%a(D9*Iii~uBp?s%*zouStcqx%Xguis;Ve%iAa-zm#)alG_q(YF6YW z(Qu<8^872v%PEe})dG}+2)!j5DXm#mAFgE_j4ObGg#}zeQGH`eb8$m$7}aPklW1N; zU1K;J$>a5f@eD6lsuDYHK6WJgPlKS$XB6MQ~%yK`3wmQJaaIu=OGb%4SbDS5e7}0VRrv zqE*SG3SAhbwynN$Z6b!>(XY|b;b%nZshM-5$=s{*s>sT4OKtOvW zaLXDNwnSQ>P{63ybw~=A6MN>Va2{KpSF~f9of=|)=wbOBqI<{*YhGn;X|Z<$m#pDM%`~{QxM*IOlFjR_Py=cz6T6mm7{}7ua4Xf= zhzJI^Xr!h!k~uAL4283sfcXveS{if(@eC&=h>|a^GH=|F<2_1BC!xDHVcD9(Xt*v? zy0*Sjq)hsD1JEMwdM%0biYBszmq=;Nr81*{Ii;jvqG{=*km8C}&(Mw{RhFoHMR-b9 zM(XlbuHvmzsngarv3U-L_|7iH!_jNCO7T4N9OriEh_-Q2ePu&5S`dvkM8(rl@mWTl zH(rC>kcy+|*YUPq@}LAQa6%Py4T^)|*M5E!gjF1G4KEVkaeRANPIMiB2Mcl)Lc*trIO_KCxTQG9NEmb@g zU@xI(bZvMQE6p#IT?1ZIcsEZ)okxBcZ7@RvQ!eXt))d^XO&n4yl!HhTzioUZ#T#Nl zG2-1?(%guLCK@K{m6lN#DeROcIjMKJqfSXM+!JLh;KbSL1%>-PQD|}52OsgdzP2f^ zxfajCS}IycKs0h%M7!rf`H|L|%1CjT8i(d+O{HWvp|e@pytFK5t{+*@R4Kago(^=d zOB*ARDyQ8SIOPG=Wa*tMyec~ZxattK;<-v#UR)Oy7nj#G1bMoJD)RE%{eI3)(D5`!G}kP$8$7N zfh@tB4xU5NiZ|jj?~oFCRB>&xZu)lUK-&N#YF}HoxGzWqDZXS4vW&| z+@b;~o^xI?b&D6&lS=edWF|VPo6}OEgyA|v1@$h;%lwu)8RI6QQ_3hAB_<2XW|yMp zg2qW?nU-F2;h=}C_33IiKIeaQxGDKlwB%Z z*05?7x_16RoV;+$fWlC`Be#|0QJj^GR`qLY$f>lYsWF0{9>U`y-BpTeCC|MQQwmzf z+{p!B66fW3)r(Y%%=U^EIV7U3l%iBfIaDel=9ac}^o0YWlV@)BxK(N8N|`RDR79An zE{Yy9(H~z?+4Coz5KOImOS^Z!j33hD6$(Owkl^0->2^w~silrrKeqydBkwU8wAa+J#gQo8 zO7zT`TT>wtfYZ5nasRpo?+ii_N#_sr?jCr`?nJ}GNPD5Q?I%dz;(teKOi@j>?$J=PV>Ei?=RL+_3; z*!9el7@INH!KbhgF2=H4mcyQWWcP?U2MTW()oP5h7VofPn|23xq~xc?)*rk-Hf!Gy z#`X^RN4s&;z8ClY;NS>yD@==R+7&!-KQQ4+ZU;sTYklh4AoRtqec@0xi=F(!p*9w4 z3$?d3-`l58IMmKs?(LHXyAAe3i+8by7w_sBXh?m^YzRD+a^nNmfeVarq4xInoqdLe zci+5sd|RotV((bQ|Bih(Ki~R*m0kMq;+SFKw`=R(t*g#rC3bjJ>*=rDw9O0o$-O-6 zWusaV9>SeK;lVyZgx^<$f7*(a8^3NH*yx0~tIwG5^Q~XEMmD6}_>h7Q1Nx9P2`Z1aH;_ij2ET=N#&+mBwvL3Q8BuT~t=IV19XKR&G%lW47^NoXa$F$+nG$P%YqFsPEV3oQJ|C zht`Aux#|O4Yow{6wuL&v%rYOA(O}~}zqPmiq;x=V^&8_cmA>*nhw=UY_8SDNVZ}2BqYIKr&qLTmSu>I1^uN6P)=c0ogZAKBXi5|1;i672i<+dAjLeJ_>vJJ;vSu5G}(g=w?Np8AL0 z{rx2=&zdLuh=>+qH8~5hI^N2ax)|;Yc|(24I(1L;bDLlGdy}391SUznYAwEU_woy$ zNeMOkYq3=2)MBL;?F{#Rcg8RCUiXDzyIJfc#+S$QUpr~Uxv$@F*yls!F;C5KD^F@w z^Y}Zb|M=bPXX?lJ{ZSrsUjqY$QnQ+z+Pe-V*^ACs z>Yi!M+_Gt^pIOz=Lc_g*fO`9%dE@&B4j%r^U;R{ybjaghh}KTDw#LNjhPueamWuk8 zrbu*RbIrtPq_LrCVrAB(Nt0G%7DLD@vt~@5zNQKipZqCrym-~bswiGlqqQ{^6Q!$% zP}i#xDPYX(rVuJCn9?(Rir+& zsJ>=Rs5L8V!n6sQ6Xuqc!l7|3W(2F7Lt`t)g)(Q(oOW8)q|6zivdEfnQ-}tjqv-Y4 zH`6u7*%})#iXN##ds|)}K_?s2dF};4RW(fnki~8=-5l<&^m{o>xlHYIcZGEHa@x8H z`ACmlyfpYH$z_@iV}g;8&`q_@$@MbBxZE&`D=-bpWFul2%NrXjMCU+0?hSLpr5Mg? zoKwRm_nB-!fv+KaZi62W7!_QpY_9^UQrWWz7-gzX*;EIN6{<=J+tiStw|Jy$&;2u~@4`D;oHEl%o2o$QmZQDFLI{fy-!_ ziieh92vfeF$X5OQ|)C zCQ-YjOSe|7*NjW`MlQZ)Elp5a>|8`PNN?JVwH)bc(GP(hgVkbcz%VXM&|1V-p5=;PIph)W`IUnQwpQ_JltW@lQ`-x05Q|!2j>j*+ z2H-ypw-OKEIrrpm>?T@(E-rw<+ZS80OWvAt5TkFoI-%k8;tSk6+_72g?eZAz|ocC}Z6nEGOfNFB>Z});*uY z__)#M)k8fxSI=diPY=ag8hUoSdU7+q^cB-wl5xcgIi&HQNguWQuD%6Myo`Q^mD+c3 zM*4B7V^XipPRB!V0<%)j7<%^5`c&{S+GY;1Qj0=xaH#!^{)R%gCKyJBl}hN$^jYbr z+vM?@?9?x3+Z(gfw`QYh4NP%$*c-1zn`wL{d+0x-J3SfQo3e*qPwInTP*CX|C*z0( zMfr=s^h5=a_37zOwxfI$5#?wNLOD8aRC)ndOefJE4cGMavp@`<#ELQ)OBoAfxT`Hy z5kX2j9j=%q$T9j39@Cq#^fnYEDPl)#0EKQ<{_w*sEzMYY0Xva9-HOsAa;IBNnndn& z%Sb~n#7_7$Ofwt30nxdLA7Y@p)1lJ)vqDw+9He%n%cIvIg(o}eL>l3es8g(v+zwq1 zby~`bm@x>porA^Bbr|A{vedynQhJ&L0aj+sSQDhx`@km$HTS`qJVcX+ zYVt7l2cN#-n)`9=?>_hAHF<<4pPE_B}v$aLNn_&o{vO8hLencVIpY`kr7836>z zeI#QwWDjPn!oUS?7LK1NaNLY_LeC|_4ueN}Bf`E8%>&6>V7va&6mh+{VYz>V&;7%u z@q7z5g-7;c@(=rbVTV;cxS_coGy+@?;?MQKKA-%d%3WekblVa!fq1wT2&tkfZ8bwtv5B`7Fy{D*}zu|{4#;xEAVd!{96Kl zMd0rX{1*bxq7J=U`@b3!zhXQ|9 z;C~Rfg&UUir;v?&4v|geF7RmrpD*wg0b7W1k^M6*t-Wn%JC#84h!)0&G2lC$6gsMnI3$4&!*}%j#)>%j7 z^-5ZoEQN4IMKsbXrRKGb_#{pE!IYuA#8T$^Rh~;DrdXk)N%l3BD5~Rk+Avqbq#miv z@TKgZ$eAQEqrAMVsJx=3rnag)+>F_)ik4=|vZl3l&EX0*0kh2simI%L2o(*r6YzOl z7<8gJ<>!={Cp)qBWRWBf5C!W2Zn1fgTXYjBWas;d2`jPwkYd^#7racgd%Pdh1#b@8Ki)sl zc$BAVI-W-RI#T11sPoXt#fs1g{U;^V^c(?FR3?1iWj2sp;K_ ze(fBEhetFwI`5Svc|*|YQ|og_`l`W86zp7&I~D!y zi<98pnk3I0#@Izk=&J>f@>DnX0#MWYNARd0uA2t{sJ!#hPY>xN$U5(`Bzbox$@^{x zyzgr9dj~ukThNWp3!-0!u2`JWc@w}J6USmq=aqt|wrkSM4{(9*Z=;l3z?&=u#eNUh z=%%}74|v7!m<=RTpwyrGC4Ol_ChHUQ+Xz1iKXf~}L6gYZ@e4Ax&OsPU4f*{MPQ1P- zTvguy@CYY;z3?NGh&Mds@zAB@CJ}G6!b6kUA@5X$N9iF$`a)X#ri7gLJBputJS5`H z1uq*M;*mRh;Vr&TKoaU$LTg?C~n`i3h!M3o!T zw-)iUmHToucxZa#%(dX5da#giISafCfT@PWn>F5@Na)=Oc;TkCO_j~H?sqI*eZ!J9 zGfRBV()Bki`zc{C@*9?ZXptyy0vrvfOVcSyjG||Dx-{LT8C@(*_lUlQ<{d6g_xSF* z+Dg8dy~CyHo{z4VrhDA3mZp15Hy&LrP4~QDkuuH0orY`_Su9tPhX8pzS2g#L!k=Tp zgIwV4_aGOGPw+I$wbOp0t68qdKE?B)E_(Lj!j}$ncE^jJJ+@DOSBsuKZ(S{V_L$xx zW*YnunW8Rw_NYAO9{()VUcv9SMbF}1twhwiZFao!sI7aZ$3&+qYPuvC{V@61cd$D} z%?xk$(sU*!EjclH+(6`p=CI^*od64S67u=z$N^2Zef?ky zAJoj`nw)ddE^D%tz?-2L{0)L2X;Li&DzXbl4!2c}p6m;S#+;p#!ic;UYeiRx>yeNbv`=T#ek$=Nm8SF zevLGc*TqO(Cu4FQjKLknu{4?SH0Jge%0oBQzgEkq7al77zR`#wjkf^z*GP>+VhBG~ zUtSw65V&*lW`x&cUP5uJ_I$p zmV&n(7`-3LcPn}aq~{;n7xx|Z6Yy{=`3!C`zV=eZ1Mo!c5$QsFxFOyK{8Zj>@Y;|t z;>q|B?-u+JlpF3{Xy+33(RYJK`a}4Uc?`UT&ZYaG^6f$VR9*@K`L@e&E{Indu6O(A zA(*cE=#yv8n40W&=9@2d!jXOS*V${#{73ADom&bI2Ey!)wmZ!RX0BeitbNB8vm~&h ztuDZ}b4NJr+~C0xI$PCr z)j#OF^e6W|d0*fkWe4(~S+sHfHN{uuUa@OL&X-EQOdrYb3Jz&E*tP|+Yd@{a*~0z{ z*&DV>tT1~e*s#Bq^`F?zvST;w*kY6n3FmK#WvA7~_B}ARKZ^}%PhmHmzBsl%b|1<6 zW=Ul45B3aWZG9Su4Rqh0A?+v3S-i7X>^{2UuKV}B7`tKL_I!K|zGn!_rWEDh?|f6w z+8imie(w;rKR-w)yVKab_Xqo4T-t7jcL!s`Sl`_va<*8AXUdA)Eqyk}mgDRE2X~J^ zh&j81ZN+mI@9vo&+bpif`N)o&&%SAPTj9wC6Q4V6&(a6B?Anx5{M@$P zhb(q=d#vq&A>V87c{ny}_k*z;_8#iPzT6(07@M^h(!N6}?ArF&$=Fo@QXg~YSI%x< z)((m99`M{q`qDk{j~yG&`Eu-r^@k(aAz*iG$3|w(x&MT}3|_pO?b@<$`Tq9QlEBJc zTlTk`4XJnRYL2x9N{n}}{HaxA-C;KD-jZ|0m4|cJ=xi3-xMRz~_Sglxmd9q% z_w*Z33u2p)+ep=}5eOLtVKC(IFx>yB0|#RcvUNdh{ik)ig6#U9#@3A+79Jdd+Oroa zzi$rryR5zM!q_!VjoCedd_KQd)}P%Y$S2Rg8}^?cyDv86qjq*v?5dqqKBu9MJh*>E zEVg;!^CO;L&|dfaUiwerZ0pVL?6dg+l*oYger(r>*uEa9d&Zj^wrpSa+!?Wb#=H0R z`Ja_Lw*gm+!@>3Qs0injCXhU`K=bC zefK$W^6JYM6RUx4tg?BWj5qH?%|fhhPJO$weS6z;XFBouD5>}q@*H{qHQ=AgA(YEw z#!okF*}W9yf?U`hS1$YZxw(KE9b50zI0`SeePDYUN_X!tjLKdgGMe<*;|9I-EU0b|8DzaaBdYCcbdy8)xmi@|2Th87*rsVG{ zo<n}12>X+fa z`Td|-W#djs8>jkCmpX%_RQ(it=GD`8t$8*2FyU@sW=Qf?&0qi1@9hf)&Ku*`EEPDK zzX~-X8GG*d^yfF7eAx(}X5&5(kU#AyGJh82o>N|SUU5Nr8M4l{3?q>X_AQyWpsaxM zDv*FsvJ^WDSSblz%9cvcmTmPw8PUt9h~hh+R2M$8>APq8qG*Yn#?H?opVJMQ7BxFI zzccZt55M*DZ~fUJRXW*mq8FAr_~>TzfA+<2I`rPo3SA98x>;w7!AG=~vN$&$KeR79 zd&T>{;&k?t;JaKLAIO$lZ1C3sQ43yw`Ag<|6JmLOZ&1%Y4Y0>cy&Vm7dU0}x3&lVu zy^x7eP}Ds*0{_$=9JaRy$H`u3SKaf`2lxDO)Jk7yW=MV$tJdS*`_DKv^!AxC ze?688oO(d3KI0?s(Ft?me;jvRYLx2PN+pK~vdz(2K@hwbglX^JGbA5scw%VRyK@A}R7t^TZ(dYr7J!9j8Vb=O!wz4KS1#P9~uO`pLXy@7tS z7WpUkPj&WgHH`o2=>sfzS1?9qvBExH95y8$mmrV6R0S2_kC-J_4_jM+-1{e`44u4$F8S}u1M{mOSX z)Kf6{yNi4qfu4Hqi)xo!wSd+-%YNM|Zf>|3yt$Ej_ddWbJX!@`s@LUZPK3P5Eg~de zMFZxBbuvcsttntcya>5I%?+135mJyVM1;JX>B2hg9>Gl*j#j954emI2%WIC-x~aAA zqXK5XJJPNDBm{a4-bnN;x{rvTfU}}&H#Gu;mPa+6(ry?7d8eI@RZ2+g){38R8CN9eBVF$ABVm(4t;{d~Ej|~49)q>`$pp37IbW1=nG$UnC2=*_VRUQly~Q-vBxv+n zKS%AA1G5Qh@4sGE-Md5%3u7pw%i4PmW$Tfzy>k%g|B>439HL9POo_(KYFzDg7~NWX z&-vGDZ>MeV7g&4c1XMD$cQ$1!yYoo5y)=1!4A$Oz;@e)Hzm#0Vc*4;74c)a-pEC#2 zo?r)Jyhz2528&0weBDX5w@~pfcMZC3Txam?qqW;d^zCT+u~|KD7uAzauaie`QwCFV z4P&k)Cj+ROs+?|ZST`s2E~HdSIi-&mZhsBDu=BSidLMVrQmR6hl?TWjf4meHD^^V+O;UY#ie zK4~FWlsWHXnCXz~8_)ubH zTn~dcF0I=0ktp^4rUd~(n##x8xg%Yn2O`j8utN6|64#p3rWd zNA&G)DDJFd@F7HVjMVWEr}tu^ShS^49^6fh38mXG4t2=s);jao#E&2>Ld&a-D$@u0 zl-LTvkQ2N%Re5^|rH8fQ7vQ_p8b;hvBi)o5vDHL1g-_XeH~xD^hNSlbgt%~Hbno~N z55qmpxem}T2@ z?4FO$!Z9HYGpvS6+kW3p+hO;N*lA|!AgjvkW#qtZ?F>8Z*YKBmve|bqoO<@N?frJz z6M%vP?6in&f6we4`i`}3#!UY2X6v$VpXnUY@eNh!KK!pQqD^Pe9P~wd#8Hd(VLI_72hqN0yltmPl!2o z+Qq1Cmyfs8CffGTPqot~aM8KADQNaZLU#O{B;=ML60#I`M2`$a^3ozZJ=3;-Y+W+G z)yeP~e9`*rh%Mc@Lyl~QcT+1xBgCSKa$AUdY~;h2>~!2t)}?3K=_uA6_gxb`#ZEup zwr6uWKVYJSe|PyJd(aX)<3>AenVn%>HpWgnLvhNuSYZ2Lwh@5cJ7+p(K>Pg=;kiUfK0cQ5a7gIbqqd9_L8 z72TS2w0eLY`_0-9sd=Agr(3C?p{A`t!*&`Pwq?Ak{ps>E?LlXwNxNbU*%?u#MT2Oq z9mA{G7VAv3a;NMKVvi@oxLtj2{p|?1Y3SRc8;}2nb!Q5mSHG~+?zVe<^OV=JojahH zuT+oBd1yzY!JX6#1!!AuTNeZj>*33%22AT^>jFD{1q#fzzH|A1RiHVg1LC%+rS<7? zN47atO6v}sc$bcr>W}xV&2s9|*VUM@QAaIiPp0;=d+oGS&O>*4%`J9{)$3F1vV~LZ zp;rAwJ0*wgh5uf8`PURZFSq;hGIZ4P@(}gqTkJl!(_6|AyU#b!AF8f%$~&9in$z+B z$i0oa{k(4K3#o6r-4uk|x=_Ap=LH%apF8M`0H9jHWaF1{1)V#1`4t&gKD-A8bC;ho}Hey|ZGYykW zE7!x*dTG6$*5RG#7$748o8rau3-)OIk~yD|c+$`^S&>&?F>tQpwWc{Y;|gTZx)*Yi z)ko=&h88WldC$*j`5DJ}bPb+7*C%aqn z$Vtz|b+UP=)?b=KcjKbg-^(g9E~mtz;)&{;w0O(#via-6zaAkc9G*u_F`SLZoiz0H=HnX}nv#Zk-qIv;S9^2+j63;} zCXs)22iipL)H{_XkvsJ;rAg#Yy+mmexl`{?nndo@vy&!~yR$0CVI*>=9+xzU+zFE= zk$YGEsV5}ONw{#zmv*P2^FC>|S>HK@*tCt1!=x=kB(sC3jGv@L={&h>rLKhmYq zx8#1B`yDiWkn03Y6XqVNgYQJa=Ic`(FZ3y<>P4)@&^{v^>jps|y(Qv%A8d8a^*)ao zLp8E4@z!cxU|MO0ZUn*>*XsgAC+8Xfg>rT^`%a*w5m{& z5-xTlx>pReo=l_1FL5F-UM-+?Mbe9J*$dIUh|tOsAFYVC&(T&zbbbl}-CXV|1ZfbG zJ^MSAq5@-LOgRHK`6WX#-7)E0a^w?m-A|Ee_c-!HhWL~s;*cRZ6E>9z8Iq|5k*y@j zXF{GvjxZ$W!FIm1aAf+VjaGq@p|i%R1*9`1$dJ4gwilko${~*;M;LNn3EK3Iyu6S{4#9HLoy`40ecRY9Qh}> zE>h$Va4pZCGBHp3Ysj>J9T}4U2;0-2%Kis(HhyHt9XrXg97p7G3S>`T8ly8CJbh_w zAY`w6)7WsxR0qhIW*R#Y@>!0^`$0xZ+0DITJuiEL}!c6eDd7;^0O+u`>`Lp7w&R=%ryJ4J&?Wn z){i|1SsFT57w3A6EO^)7Z^E zxd)5+8_hm&sxgV?c$r+kFK$8b*@*qtf ztjR+(d8j52)8ykcdAKGYugN1c`2)~;d4Jvlb31o`I@|3lP}QZ3pKf1 zlUHbRSd%L>xl)s>G&!QlD>ZqQCRej(eCe;z!Q0c@6uKlK#GUcKuYy^k&^3{g2-ZIh)HSKW~ekXw*mRkN(e4@$jcU zOnej!sI zwm&~`=OAj-`yYmNpuOgp?-XS^pE-r*@>^sMhe-{*O&KI2YlD*;|w_H z^t}dri+3BLp^SG$uf&y=%^0_Hgqb-u{!xzHKkSv{5B5dE-cSA^Kd1V?R`{%xg z|EQ2`t#D!tSl=xk>1$7kY4?aXql<99|1HuOF}{l7HBA zUY;9|Ey90;@IO!Zht2)L=Jg8p81fH$yz2jE;lEM%$9>Jiht2N~*!=#0eFFK1O?uq$ zw+jF8R0r5Xd%*p}=JAKk;{lt;A2xkLNxWIAo^9fs#HctY@fPGC=>yL70jF^T3;5jv ze~@h8^v+NCA%VXu@b?A&SAnNdeuCeNZ17Ja8~W)TnD8?M{(`{Y5%^C99;A3vJjn)s zIN8v{&o2Z%Tj1vkd^y>`>jfSa_|*cxRp2zjM|vI=`11ni^$z%d3;cfs{u$Z8Gb~5{ z7_t$cabyEOQ{W2(UMlcLfnO!?YXp9q!1oIL>jHmS;O`0i=K>D|oNxz`jc{?OkCP7q zpDpln1zsocbpl^6aC(+f{yZx1Zwve-f&Wb49|-(2f%mbUa5Kn8dQT-Add?DfuE3WF zyhh-40>4J!w+Z|%fj=nlrv-jc;O`0iV}buw;6sB>xZ}x2K1?JV@mV17u)re%zf|DY z34F7_V*>xKz`rN(HwFGHf&Wh6R*DnuK(Z0;P_hwjmca7`K1bjy1RfQ5tH5s+cue45 z6Zq2te@);&7Wi)j{ttoE@D+tSoNVO(1hNsIEP>A#_zHnn3H(&LADf(UCM(++kFzk4 zNPQrBo^$sWA?FIYRmgclUM=K&A+Hf~fsoe}Z+nXqhaM;%J%dXqoJ2ne1qp>}Z+nXqoJ2nc`@f z;%J%TXqh5%#L+Uv(K5x+GR4s{#nCdw(K6N1GS$&C)zLE5(K6N1GS$&C)zLE5(K6N1 zGS$&C&CxO~Qy#k899h#mE79cR1lJ|OWTVf~n_SdkKAEV39ZVkjDe;qqiQS#a!NhLP zWMD!!C*?fN>SUkCRZuax=ea49c^;T>@-EIfezMM^_$KExSf7lW(D`A@&fx)q6&e57$BVZHGd2gmwv*pVcR-Ga9GdDFp{@_Ns|aa|)8s zgx_RKdcysQ$uYjb94~Q4LJ%wpE50-oN0COcF$p;+?`R1 z+=E(%c{N|j#((2`(04;Q=ZHHuXKhV=MBZJU+>lA!gI%0!9*xv`nTCcMH<{Du`WzDE zrq5le-4i-FDcwmG`Ba-APZrtX0V3%h5SA^C2f3{c4;dQ);RJ^X&Z!|2kU!1g3O1ps zT3mI|^GEz$oWmw}sqcD?N8@n!5kVNq`x<1rmio3@SpOnP z!i~fi#I@wnSny_Y5Ju|zIb>DecfiAIjB6zCQ;kROo%JruOGiI=Q1#sb9=ffrk@`;4 zcz*=%6qn`c%hh;vHaopjNF(*pI1OFP^y2*Ig!#NdP0C-t4P}md}nePam zBQf?ac&qWQr<>O)@GnC=tk#lA0)?iLufycqgIq@v+b@ zcz>P17$58Gf@f!nG0iS`vnGqN%Px44sbY+>3*M&bVhmE_y{6UE12g$>r^aGT=gpbL z*u8PAc-}9;`=2Cu@1M@tx02x9eumT5=~O*_6=yQGM<+qnc|Gs|ps`Th=)A(S8JnC0 zZ*6vR`X0?eyOxB$_i}M$auU2@7#q1;PXuH=9p3_v+HBqEyzdv_{?JK~bzVgwV~-@k z8-THxWb}O#B6#85ko%(5~r7 z-v;oK3HSTpWxLus4mTBJQN>B{mV$?2A=h*izi%eV>x(h3WYW77ykydQ7kDe&*ma!V zzb6@PKE~j(lhC&TykydGC`o-iG1iwTy|hM7t$)SfO;qA1FLmBJ@YHhai1$vCyy+Nw zOh(_$;9VpGQ*1qcpCzg9JXF$T!hJMJUO$W-C!?<}N!|;GLWV?{)CTB*FV1@X*DNGkW|^#mn@hI2P7*Yw2AM z-l<9OHYUmYCU|(2iZgn+ZzsuPn8QjYey4($O#UqdFVS;Vk6#;j$>j4lz)Pll-|iq> z+R7HMNbZ1u4yCG4{kttf_%~DSj9_;fCb% zHQoV*2emHmGL3gg;q_8@Tfqx5h8bVSybhik4?-#2otnO%Df(pjCE|Uk@J@1qNT}~4 zg(u4;k-kq9-q=p`u~lCFjq8M$s_LFPv59ccuT>P={Qm09W?#*bUSz-;Xy(1>#y)= z9c`MB$=clDtRW%ZG=Wn(bl!G_H@y?yLke$3C%pX%Z)PXFR}|i?PIy04co^d2CQ&** zQg~-{!lNfFJs&AwFvQ1AB7J=o9)|cjxVuhF632%kM z%j<;KsPN>tM526YQ+Nf6K3aF_tA7d)T^?>opU&H^@RoJLdr0A(-wAKO!jtc=?mU4;jUUC z@bKsMElvS13m#QtKp3m>mLpQ?_s7I1US(}~0?wS77!oFP`t-?@vZhbUnh^?3;+XnB z6q-J58eGV%=&`O~ZlQZB1J`#w*Gam`)QXPb6dv2L=!Xqwv9>)Mjd9jyYjMn4*1mg- zRT5aqZoFo#)xd7txOPDFjhEjJ@>FFfX?A=H`@_<&>UVo=Mxt)_QUlGirCgqPqKyLnYPuhc5^La-(YU7>1iJ zp5Ibe5sBiHm1dbFzCD2O``w?g-_>7#?_=Xszo}AVfK;-bK{u#xZ(7xK=g;iV2zP@r z_JDv~+3du!q-gf+f|Bym1%+ixa!Lv)e{S-*7EE{c`UypOiB9}3?`Cy#OWO6ylHXn*}nL;in+vdY@E>p>6tZhCL z=Q534#@XgK;#{Va%PF?`%{Z4C9n5XPq+dLTO!V@;vHlK@g;pIEeHlL4k;pIEuHoqU| z!pnDoZN3oa!ppbVHed9+EG%&1R%)Av;#_##%53w8aV|V=i)`~HpG#?ep;ME~ZS&PQ z7p`rEZT`sTvZ&aJz{R%thR>n2xTtJt4ziTh+2)(NQ;FkLZ<}xFPGw7T$ybAIzO6fz zI8KeW`Ht>Xwlt4?U1FPub*B=?DQcTP@j2zq&E@5~&Nly_?!Xh%ORkXX!%}0v8iTNeWWT>SsjitBgkk-RPg0#$$oxIz0XG~-!M%0XlvV2J9_K< zPy9YslkW0nh7aaX^0YrNu>I1^uN6P)=QdS0M4R#a=2H_wYuOV&ocYfDdn^4+Hy*-E z3LEVyzx~hGTH}{Jw8ZZPCx($~8XXp@e9L|3!pBZaTh6{_dIcG8G*U%%n7&xcuF-hx<6&O-hTxALS` zzOqvI`_Ab`Z0cguCIZCLaCY0=Lug^E={khta);%&zD8f3h}rFY(DEF*dGjh z^1%4~iD`beFEzqjidx3|uFfrf{&#yC{oYpAHiS_d0(`ni1n`x*XIeA2Y?|t4RyDNX z)KrE~NNMC>P|v*a{R0ON|K_iLDv!CxzYtw&!8f{Ve|o%lR3ciKj_R%uDw`&jL~0}9 zrbu}~PHqu)a0r#nE1jG*DKBf%q)DOKlS6qE^Tv-4PVi|T9Egj%z*CQO@< zIbm*DDI6NtqD`u94vnoG7s{MDbJ}THlQL(7$|7sRO`)QCtTJz@i_|yMb!9`eu^}36 zj#Q!DC@+tMYik=;GxvfZd`dz9S*#r64I+oTE&Xl|Q!WobCUe@VKt9s@6uxCBa~>b1 z4K2~i2ql@P*)TE_x_4Kl*eD2|p z@}_8IX{5F!vPwDGv81WGW@Yo@aIK4pQ(|e_BfvLcOK@-oy%yfa2{cMVgd=n$o>wVp z$qrsY4J#9ef7IJ)U$gCBPI~ss&Z!?i;cH20qDYU#-R_hwstavyh1HkD9+)y=;9nB>jRL<};9nE?_XPf|z<(<6KM4HK0#8TY zQMkvGjrfct8}XSc@Yw=CSK!qGzf|B?2z;}^?-Tegfj=$q*987!f&WV2e-}7yLdx@# zY{X{*+4yA%yiDLL1%8phHwpYMfo~W1;{tzC;4caM_X0Q2V3B^CY@~N6*$8*Mz$Xek zU*L-czD(fM`?hdBiEPv>ULR4$P~nqN9Xc|!SHjY=ip<50i=6Ea`2Q^b7r}|TLB3Bf zKi9{mzK>Ot`0_My>&U-0m7mae5RN9EJlW8*_sszdanI!0!SW4Zrj9Yght9hN|zYxbH@491?Zje(>%} zg0~zu-+Kvovw^AMX7_W}-$<(S&W0zC#%lvFBuR>`^R|PxTyd9|I`8k`$#oBsLv{sz zYWx=U_vWWnUY*8!3cQd?5Z9M$ym!GHpMZBAFia^nN~bh*NG3}`vG2n*JvOB|1H5cR z_&5O6hap4l-d_ArN8S0(%Ln+^e-ICk9rj)P(CoWrBY1=(dz@)5*d+e|Kb5x`JbGRe zPnKCC-X8F>1rJR#H^h4fKULp{#6!YJAM$}4;{66cl{XfP>nMH1lQ{7{Q)FDS843?w z6K;st7kMT95jY1t!bu;hHa8@X1`qLd^RF1ZMDxYdz@zwvxKG9|0`J@6T3Vp6vozj` z$hYb!q2d~qg5O|n8{x}GoINH0V%a=tj1<*?ZL{jJQfp2EiH*E2J=eRr?e zCiACTW4+m@?aXA?_cm@B5oAw3^1zp<|P5$t-?dY#(=>jQ2Ftv|tj z>e?W*lD1od;Ft$SkR32z=XTKi0QR4tGq(Q8M|NyE=ir?C3%@+7b$r+;85A~4&RsF8 zHMZS+D*JkLx~~ryL)r~?_cO6gx9kf(WtcQuefKjxo;s<4SVjVt?XuFI%HS-PfE93A zsZYhWQy2&#=IEF5-Ot?etb+_|9o9;zT8O-J>Uy9uxO>~YmlyX40ix={+YFd^hJ>T{coeb;?7PW724_1UD5ors?ZNFBO&14`+1=-#CTx){3mh`xdN4u|eN zzB^v)4EA?8bnp4-dg$Kcb~SYGG2M7{HFWQJ>3rzkz7P_;MX7LZo1y@kH*)zuYrLaskx(x0yngPGwk2tM1e}Zq!u+I-`@Ulua93n?pJ=z zQh}rS6fYv`T!@=7ysWyK3-Q>#0_$on#PinGT!_c?<~C0CVy@1Gc+{gY7gF(mc`oD= zbSy-r?!LJYnZqc3-VyD#kdE4{ll3X`k)FnU)3Cy#!Uau~Sf1LTu~c*EwlQwX=qf({ zQGuB^cTyr?T*zhF;MjQ4fSH0m^${(5dMP*t%bxZzrxIQrt!a*UWlyOM8W(FW-CFjS z8J8PIv9Ih6V|imsZEb$IIn3l^Bw#G|)d$ROxg7Zb!h#ZCZKfBQAYNc#MjYvSL)G;d ztT!V?y`e4NylO*<4H{Qb_InQ9T5GP4Z!vhSX{zS6M)rdAR)p6Y!IAwZo8Fb3FGP=M z%R<97$6yWFBWg%xL;cE{Re8>v-rR<8)x2Xz|e~dapbK!1>$(^Tv6Dyk2?y>v5Wv5NH`%Sd%r9rIPGK|~R z`2FqZ#qZZx6>YDxjfJ+Ieb-%g1+ijIi(ET~n~{fNT+8UbiT?P^yUOTo+r`gbeeSvZ zFNir(!^q)1-`7RS9;p==B68h$Pdd#42A7aBzQUuAZ9g|5U|P>xJ1335Xl~KOQ%{|^ zDqz^XtQRjoH(=Vf^{924=5j!|d{=ducg=*KPMB~}z_4Dv{4^&MkIqt&if&#i;?^L; z7>!Jn>qIh)VLb=1)L?2#YHDg)YLC?P)ZwY8r=FdfmpXd@<+d<1)}C?29T-9NuQM^s zj{Ogpo?%nRF=HM4XI$}RV{yj1=b=cANB<<_K|P5?@i3E&2R&NccwCHlWTO@AXIQCy z2WO-ompUf(+U#^Zb|+xM|H!O+>4r5mU(jLlpJ(+>H>4u@L)rNfp@6qU$aa+P}vVAvuYKdg-jGqzmy1OILK`NJBRiZvqu}=e5^iByy(;FU?3?IR0sf z#94ymdm$pCN1}IWNz&c}L#`%zagrpjZ%>L&b2&Q|PAA>IFJRddpO>J($pp+lV4PY$pKpKSZ~ zG`4WY+-9G9swSstat}>T_svyXI0KLRdeYFDvVOU@Cil_gzM70Pccn7emf2sEGc#Yn>!yp@ZdjAFRnkG9+2VJ{z5DMTVLIT8B17$aGuN8HjYw6&bpX`=h?nki`HD zIXkd&h9Jh9uY{YGCTy%PdXHp0&G`BtOqkb@jF;I8@{G2E<9J)(I0B?Oep=^tiLm)u zXpqanC;TtM{=4cQo1Ad}NC5Yb@VS53+&^sYANFZz1}J`6!kz)!jR$VL8VVPk4z36B z=Xzi-qi|uqr`f=K~6Jl zjYRw@KEQc=fOCDoZxQ%zvVrd-8~6c%zaj9q1^#P+)0{o=>3xCt1IUJcewG<=#!;0*%5QQ-Fqe5b&_Bk)54e?{QG6!@nCZx{HGfD!^8p`59;kcQDD&&(A_bKJc^9fagk_ z>J5e|F}=?3Lz;22(136m_Y;@#AmcLb3oc{v2A5IK`F-9?tPjL}%w;SR=}UUxpUYSb z!e#j9G6XIw{-r<3mplV{IxtvgxaOj{la}VqcFqP8=OOXchT;SwemzxNdFbnvh!ZCK zqtPDd^*TJPgI>mwT)pTUJJ$xD{R5$$jB_2)Y&rUCCh1rX=iDc)u#btwlyslakM0{X zQyk0vFYluiAUf|Pm*u#Th)0)?w+!+mau7!9%Y>}z+XQ*EBndYX3&gdI-`62OLJq=6 zeJdf$YjRovVKLe&-82DEd5=MHg$f7{I&TQtDBj1=6zaSIXsdW1q6^;Ko}#bN1+N}$ zBJUGuJX#c|Mtg8S=PgO2@x^m0Zw7eVbrNJ<-<#mwodmB1eY9kF{m~aIP$MFA>)|dz zU+cXD;a&?&^*#fAs%(Xa#~3#{Zw+{JlHl!6QXj)JFp<975QZARIpBqqaOI`Ws|Ihm zbX07ecL2PL6nA;4^CsY#oQ%FrN%DRHUWE)yv3KFxm);>xUss{<%ZD}I!{CK<5@enC zYLdJ^B+2WCzDS~Q_akgI9hu;b0j8V%094-MBzc#Cr?zWSudeT_;AKij#eN0X=o&Uk z=oRoLOF^-JfooHd1L$jg1RxvOc!5*j>38^{d*zxxp}|Je#y`nMINXq&g2bX}q}!95 zzk{dxBanFXZm8m^cz2Wf(7od(5wEYpLlf5_Z-~NE*9Pn1h7=y9lMIDBR*TyiuL- z)+oFaJK?n{JlTFwxK|qfHSrt4!>t}?ZU&F;=a6u@54;>;sv(iiHKJhR?2`*`9@YAbL+`c6+S>27 z7Vj~3zxa!7`?eS*f$%See6QVV_{FenHmtSBE4^RccKN_p?)lQTCA3O>$Hv&Eom+On zuTdHZA0F~4n1^w!IQcs~r2SKpSb+9iOiNfzFnHx#j0YG*6Ij%MNc2#Tpn26##sPAD1?38ID+IWsMdB{q>|&9)M|6|j#UgRnhe)@x zNZjmlHyO{Lw@BRbc9T)kEf<9N(=C^BJLx_JX&2d~F1U6B;py&b!L`TsCBCZ#*Pgeo z7F>JGE*D&TRBgfa1TUrP9!ehHjk~-hm8{(ISkLLZelvcnKP#mkCo5N=VG&u`ZM)m> zM?xi4*kf=_SQ7i&&_2x~kGpM6oRY_s&(x*qwy=)gs_tJQC-deNmzI`0gQO+lI_Hgt z(rXy|;@rAxU607_!wFa0)rHqk#Aq8D*%^;k6ogY2)g; z(zW%KrO`@Hhq+;GOH)LsF0HOw&E&m|9dh&q#7ZROqXdihe39_*Qa27Bwor+Jhn8qD zkZp|Zbhc@lO|mSIdlFX8IcR2hMmx1L zGro3mMmJZ_;{UDHlLpZ`-4X9zPH4q{EE4~8$dOqru6ASH71IwG{cU^8#ENuIHwg1$Q0w1@Y^-2PV0moBCgg)^jHt4{EsF zcr1yJ$G@WISX&qFuBh(L)!N;u+rKHK>8<#-oE6^zXNk8hmv{&NJ(hUOxe-*=giE~T zoJ~jWRL7;k)F8v79L9M?q$|~(#=jkR8Zjxt$dvj_ci;6-b7}OpsnfJKAPQrw>w#Vv zbPrxnmbf%l=EQ;eZ;82X&*KYN^o>NiMy~mm^JQ|)H>UKtA(`?^&I_7YgG=RuB_iCA zJO)=-lHtlU94P1M$X%T~rZwQx1(z&Z13up;TiTlM0K3-bZfk3#Q#3hMlhZW0hbE`9 zZ~FB2)Z|{8+*_0TXmVdo?#K4~^!L}~3{4)O$phIBef|e&YpjEs`(RBTqRB%wc^Lc9 zr+>KSejNMQ=YG5{3G&#gjEo z;xs=?hU%%lSLu3Sw1$)0sMOp}7d9$&klfK|Tue45rK?C6`UD)ucoWA_x#_zE($get zxn{c(e8PW@JDKcX(~T|tBSPFiZZ_^8;dB46YsepLn!6>tn*772wZpFeknoR$a{q`o z_Ya%mNo%yLg?%gehkUo{f28n_o16PbdbxkteD77*JRY#A)uO#zzpDC2V@dCsw6>Po zRa%2g4WkA8Y=P$qe6hgkb&2@30>4J!)CDB`E`dKT@D~OClE6O@_+JG6H-Y!2bRygk z+0ZkZY{ZA=kqIvq_!5EhbOFCi;Ohi_2id?M5cop^|B=8y5cr1zPo;bTe;C;ampM6(X(F8T_a__pAhN-qDDWJC z7YO_Uf%7%s;5P|;tH5`W4ScV_pAtA<0}lLkf%CQCCo;y@f&=Gk!4d9IJWeS-8TjKu<6M!n@SzQN#fPjUZYF-~9MpWlyt zgbe>&h9h@}e=g&p#AU_5^e6d}hvMzX(3ngC;d59-?orR9vc<0~;`s=xm ziDlc2?j`!sy+vkA^fo%bd(i1!b=;601>lJ^6;;ANtn z0o&?M#9<8U3kbcyEGtcM|$qG7|4KtjDh( z`df+8L1C!rodVt*C0tq5I*<0s%}#>%M3VXf=+7kzcdr(|x!{GAaOI`Ws|9blbX07e z_x&V!qtRbXMqgW!yu;v~uEa}TQXfz)kHP3y)JR9gepchPffrKT<)zNso+NL7lDwaF z!26LFKk77}EF-1ZI`3rgG8K1usq>bCNBtw+=)4W!QU6>w?*p)ub=$P=eX>r1{0V-h zf`0%Wd8Bq$hEM$~Dl{}@>*$iq2k5t<$?}<0Nd3T5@sGeG{3QH(33ejhCkhWu7dMG` z^im@Ap=;P7FID03_=8FQMr!fv3mzqz;-{|1)_G&W%N9J+Lne{FYK15BArWtn!t3Fv zOQ`Qdg@-OLH>599O9!nh&qhH~I#5pB5HDBbRiEJWmx8C&&siekl!wmyzQV(0hx*=Bcp-(iQj6b* z;8A=i|3-Gg`$*x9>V)@+!aK1O9t(Nlj#hY=B7W$KtP>DR1uxNhZ2ny|NO0z66fWr7 zZ`F{v75{MiyS(d1GIkF+D2Bw!#+K%qx=2(m$?j@B_S6|Or-iubdOdcVsF-p+Hb2vP z{m&1zf4t+xpKtS>Q~koJ6X$0f+B!9aC{eLcGv%IBT^7tMUQ|{z563YV%v&@!r>tnf z{CNxV3(8B&78K_cmKBuDFIZZZUyxT)Fs}focw(S(vE7-MvSkG&3oy!TnM*t3l`NWH zSW-}c*jVN=r^#@-7=c$myW;I}r<_n8LJZxgniL%6V|hVcOKrHhrlEcwPRe7ZdA>}V zx@+(o2j6+9?-MutbeyUqO==F1YDTq41gWm}c7sfEkMFLI=XCX1$*uPG_;E{1$9geV zkLUD!biLZ!<94;$+he-%=xVjM=cV)2-X70Y-T7*7*Mm4i^KysSIf6OW|zyiJ*u{RI~&cMxW~I~b+v5ZE0L?{BX-w%m!r1mm%fq~dDv}< z^XDPuBlXR?Ex4nWm)7aXO!rZSb3*-3GnsJOzf?Z&;z-?9!MrkU9X)T|N2s=g zHrA4IclqG8(bs~Zo@u9xoVIepTKuP-FvlL5r8!iQtVzA>lv&O;qW=vf zz~04wiq{c3@>9mEn&Q*_#Y~|fdHyv#!6et-(ETab-WdI`wTy2M#DBx%K5h57&;J!$ z`%(T%L*om)j`AHV=Ay(pZXL+a7qBdXzaPl(<+=zd)4B!uu1grLTTsVL=!{RlZ1Zsv z&wo&pQ#3i1oh!*)e;QlrlY6k0KH1XT)A?Mkq|n}Ve*Zn$719y5W%kAqOrEjKKJJ(+ zm4iNSehvA-%OAP%d16xnu*sK=8u? zZx;A90^cO?9Rhz$;NKDW8v^I^!O;I3fulNb{R7AbK7?$<=Tw28CGcE<)A{2Rpa0L^ zmjG5(oNb@wo|}y&KtM#mD}sUuCSliFvI5Zn5yGa{5JG@xNMaH;kws8kD;O5{r4@mI zRjX~)DoPbGd?oDp|eiQofIdC&)o_Xe-<-BLk zoLMhqdD3BZrWl8ad$p-%fvVo6f{9BAqWxSN} za>g%Vd^6+MGyX8+&oKTx<9}t`L^Fxvb;w4%{mDkW>5PwLypZwp7@x=Zdd9ahek0>Q zVEl2$pJe=1#{b0lUl^zQg2t88$wu0Qp5lcp#(xzzZdXf&#(5{yES)uaVp(tux5Z{j z2M)Qmn1-*G)Nh73sT*bZg38i`b;fXf`XZbjdL(VMx zRNf!JyMa73lLfcRTZw1#LybeuLXEcw9o<>v!3K}DFmv!%mA4B#^*ziqvEQf4dj!05 zrKe)+@{Yp0XOZGBFBjrMmA3}G3hAlX^qy0B?}Han{N?2(8ZQw_Ky{UFXzUWzRgJ{Q zf~U4CB)$_DsQNuq30?#V!BB}e7nAC~d-21q_xgaZK^=`-5-_-x#yJ7;?@pEtB2n5i)J)L(de%HtcCqto5Py$2aTV`}gi{-0=5<%|`R4 zwTBuL*EToK8L;&E_e{fj-!QY#j5AOBUPI$$jeC1_HI}*mu6z$Az0CL{%5B*-?;+8^ zcRb#`>)#I=%{w+XKJ)kMu`9_2+VkXic)Hs0%`PKc4#kf?JMMQ=zE>7O(TE3v?z-jm zE5_@0_JeT0GgT5S`ig!>ryAquz8w&a%`?Chy~zEntQ$YM+8%oLeY3=PGY5P5`Bm0i z!y9vh!DOH`d#IEv29-IGJaRG+$j?UWecWCqzTO>82Khy?bke8sm5ZNPn$d98D8fCu6}Kndr)oXvw0|~>Zm*tn zs^-fm8%JQrZyRYA>Hzda(X@T zv?SH;JaVwzeabObq+1vri>4Vj^#hT5c}7udYdDD~4LuCrTF~qstFE*z=&|~j*RX@gZ0}m@u6vi%&%9Z*VFJxP+|AJer|AIXi@sNKx+ZVw0!=`y`VL5r=s!oi+2jUJbLI#a>!^T> zbyUE`Ix65|9To69n14U>MZY=lUorki#y=z*c$mrsazsBl0~b*}&goT&%}~`~=(+!jC2!^81ku{B*`e|2XjJj8`(gnrz_f z7{7_}yBWWa@fR5X1LJ>WT&$l$yq!a?oNi7F-!UTB-tlcr>*4SD_6}=^k*DED#>yYJPQ@cG z>PuK(sbBm&3c!YBkcr?YugTqjADtJYn_&P{-Xwh0iMm@O>b%{k*hSr}@y2QLdM3s0 z7uR{C!MjzHMNXafQVa6(wRk@UuSk(6vp!AZ<)ObjqVVLU&YKV3`O;Idb>4H}ou>H9 z%elBv%Q>lqe(?)5UM+YLV7j>ofGV#6ydgRX?yK-aRazsx9szHZbSU;6xJH%lnM2^E zBLW&vMpvsa=$aLK0HA0+6G2^!>RoVTcyb@W4=UpI|6;mMpnsVJ5bqWIRCyy6d20Xp zdm0Z1;>PSh*LlU@O+r}815{fWikIH!YP`3AHyars9?DA?;?X#{%KI3NASwsqNt}54 z-t{4nBoD70VTd^30=5@QegfV&DW!DOJ z^Vtnx-_(+9Q^=0^>{eyF?EXHRWe-@|xS8^_tB-NlevDQ$uH8Mii8xdYryxZ!Ti8|wPQ&&-_%@9Y-=gu2D8z0A#YVVX;l@^Yt7E}5J^dFr$|B?VKm zb93{jPcO(RM78diO9Q@VPo0vVfk|WLvM4wcL%-(o06bwvVPT0Y&afSGg?WmradqvA>Gh@cOX~1(bdgNH@d&saJn7D=TmJlMVsjw4`4|YM zX+7*FV_Np)!s+SAg|$}!DE-!B3P35h9#?=7NUgO`0Y(}j$NHH9j4~X@dcp(p(v7fV zJ?XnMj0DHp@49mfvyCo}g-Us>pZuSle&~%=Q<8oYNWPnUq#8>mmSDF=+xof8rrN{2 zblbAV>rehoG`?E zQ>T?=Q_;Qp;JqVlV$hIysFE= znqGlqnTtWdz1-tws%YBOV%*OBJi3{8yV#5=K8pMK0~alrk~?+UG;m9(8lby+59Vk1 zu{~w~>R;h!ANed0n_CF^v-77`Rmw-&vhI~BGp76D@B85BA)gLda!Vk*Nu3Eu?Rqy2 z6AGv2PZsfu$M{km70>czfn*I`^i0*GHDCNKAXeU+#iccis%y*7uCAiTZG%jLdW$BM zcJ6auW5LegEs|2*TXdb8|G3S)>H_I-vyJM$sI;zbS#|Av zqy_mtUnW}3_pH0p2Y&y$+1CW~EycR|KGBcww4Z$R%ku^v=n;r76p>O?$Gd_G`+g5$~d~eiS9w;!_PqDh{ z%MTHM)tAqWx9ZDhdg+Ka`tAqe(f46~g4GdmpXZ5geMH;~5LVClu;ZTb;fMPwtG>KY z335bS8MD3b_kX=G;YsVnfT|!_$bcBL?Pur6(RFne!7BUYUG+cT^n5Uw43rj1mvW8a zewp1>+U56SKgfMK5GcVbvpA#gUN*SU+PcEb59c2c67mlSImu6-x@61?B?>Lxi61^Y zkehf*#{6L3aJo`Ir~}JIB1bDWnX}}`!U(=d-qSp-N#%m ztaYZ2G}$+Xw-O_=56wwKf}LKJbc41(?byc45vnFM4fmr~NV2M5DK_qWoScN;}j! zy*gZ-=nZ-Vwsnq{>Qq))TCq5~olDs^&75F6HwL$T^=OX!^16t|FXWH}UP{6(2QHi* zr26sqc=V#@C!R_Bm~#SLE=n?k02 z%^EA&bdoHqm%YMDG~Hv%Qq{uvWWW(z80)RxqA(sdPeoxoxBA?WW#4bE7T2dbNq?R@ z`rBLGGBMRM`B$$axJ=$N(?ps4)I160@a*bCPEx_%|7(h|-*gq@Goct8g<||oD8|Os zLB$BxXx%$lF_Z`U2~ndBS~)0ebwZ8y1|Is5m=W1=8;OaRpQv!!vqs~$E1t-K$YWd9 zThY8zX=r@KTW_`Oe}48}JUN})xStvItIGY%0{Lkrd~cZ<*z^TJ;U_0gO3A_Xkt!pt zmGYpbt2A^i%kyxopX-qG3cH!K?_D>uyV)blr34%HT#N7OzZ)FW!BLsC-bYGdl*w>Xry8Fwi62?sEq!LrKc#x zks^!ZYfF3kO8;u*9)cdEq{wXtv3Ac+%uE^E+Xd)0Va*dkJ`n0^j7SkTuty+lIJoRH z!9Tn*(LKB}DY&O$vU`?giag7*(|^ZVmQ+_uL+=873B$OZRCE>3pXz97VuhzVSenD( zuhxGjAR%u4XuNrn9NvmC>>iit4XV<*HdiK%J9;u(95VCyG*ad9V-A~8xzW@YS3V6{ zMDewbEDGVrKz-7Bh+q#X@%q~}vg5fP0PJ)A$ z3{x=8sF++c?2h;$Em%WK{T^6qA&fi|loq9vA@{Mc#|W3}9)xQ@ye+0I`r+L(LH+Qy z2CMpG znVNfq<{qiJM``ZSntP1q9&6kah<}{sK2>v{rn$eRxlh;J-`3pYHFuWr7{^cV$L{FJ z{B6LUX#6waPB3U+05bGGrac2_n2Zd)f4ieTpmphFTz}h`#%@=>V^p%6-iO`syu0Gv zy#>|*v#}^n*r)`BjfHZ5AiO)3vN8XQ^^{!@SRXJFME7CKV;M7Vae4*{~SC9>S71_Y=VElf@f5N!fgBbGP zV*Fjkza$%YDw@|MCyi{#sU#ctYR1yj4x&U3dXNt{QHdmi1CLQKgjs+8GoDcX2!cEy7BfT z8|82!*+|bg#!qK_Hsj|rUd8w(#=p<_4#t1Z_^XV+#`s?uH>EQ-FUl^jd+KUjd)LEd_3cG8Lwr0DdSf$ zehcGwF#co4pJMzO#@}W9Q^vnwoW5A>lX!1zya$APD7#Ug3pf6x6A$&Za1Ud5cXkhF zH|k5_e+s)%?+G^oi}0wwggb-XsE?qA;_PQcCEiEEeYE>MVFMIyED9I?h+nv|k*#ne ze&O!RZp1I#{n(B8g}Xny5x;QbgG7W^;ukpL6*l4%HsTRB^eg$;Sah8$FDEg9M~ ze9q)qHIp(H7eG;;$y+J^*Hv}Yvm9F3O=54@T@BY7(|-rN>=w`#m=Tj1^0c#pQgqp?p) zgUm0ri3h_i4f&Dz4}S8R+}+U@?j{!Kk;^y9AgR3L@j@>EgxAYy8Rt`J_aByYH|kRA)2I+@Tn$@&Z}%A??>Qeu?(_WlJ_xq zd2Qg09nv=5#cky6Ya=g&c70Zi^qr!WUmkc7g(oj{-hA-Rm7a>N^Y*oo*B9Rz>V1|$U7C^OH>9nkG7Hb5qO!pFt~Mj{nOp=X`QO`rhwNLd27K#QAZik$EobIcMo_YqFCsoLm^uV z{tkF^(ce`KYzpJ4urC7-ZJ{-inm5|tZ%$%~xY!0>k_2EEfk$`_erQq%6N@)n;o(!i zMc!P6M}78WV#!;i@TlLEOe|iF!b1~9m{`2!3Qx9YWAWB1JTzrmly`-~Lzjie+o6@; zCh#czRDQBqN%88uUEpOguM=!Cv3Tz*JTyUtiNza?{`@TXQoLORE4I8v;7wv)*H(D< zDLm3AGO^6EA@6=X!Zz{agTH(E~ z@Sw87P&)K@4=Frcw#fTT;eERmo&isp-|?;R5*1#S!fQtP;dSP{w^G5A^*7Um)y+bm zHm)KJo&?^dz*GZK?id*C2z%U<<*ub?r?7}Oe{re0ZE4(dzcR*+$rv3W6Mx^*kC8Sq zBSk6(8)xIxyuJ7D=s)4Wq&o*JO>WxL(D{W+-e|sM+nP>I+b-_fblbLVt8jvs*lUzn z1C}PfkkquZq4}17ZoBPb>DRbE4?dCRwW)V?O`U&N*RiFM<_NAA!_I;|6ZTx#S*5kr zk>)#a)f>n@*yqnRhwOR$h86bA?TLGOHygX3+4FSc-WyglezGsM@!*@y;iATm_odFN zZUm>Xx6!=)Uf1^y;p@Qnj?_ujdmi7mVtbdn2lqC1L&j+{_dLD(nZ~`_AZ4xKg}_^z zITVd`wfG;*$vc?@xdJ%-c`@=@|;~#JMD6z|trC7-pZPFE(^3eY#=5Qgd3U z^vT}M|FNrqTf%p3s2XeZCceVu^+UX|Z`5 z2$=joFC}ksc1iKHf{7FJrVhbk_7yc3 zM!~eZsJSQ#&YxL~4KU3L-6JOhn_!yfN5Prc2-CbE3Lb&YFwM#+cqBH&G#5v~6lt+u|1|)69tdJ3O@6~D0n0`LN#lnV2ZS>W7g>&c^O8kW7bE(nMOCq zToMJ3FuG&E+9-IW(F6O{M!^(m8g{G=c+4)CQk-G*bIgmP;7p^xW3G&XM;OOC=EYGk zsw>A_6$Otnj&sb_0XV;C*5r)oQ**P8fsVO0rdN(J$T2U8^2!vUPH@b1F}-q(6CHDX zl-CFmYOrHo8q+Js7~+_hMR|=Bp-ytl4KclPjG>Nsd6d^E5$a^eydtJojxo$JuZ;2< zEkX@<%&TI0g5Zj=3?)Yn%u* z(lIy1^vW?tIp%dyUK!~k*l5RWi0zkSjB(7((SELajCIT{vHfz4agMn)+Rs&xQyp_# zY`+}iG{?L?;8%@1Gye--@#|>HFn77CB6d})W%sT>})AJ@w&X`b$r?cH#`GFtlso3`m|i1|1&+BV=v7pZT|C=Z?3njN z;nQXtRgQVDj^}`1?U?sP;o#Re<_~o|7yJty^ZqCt{94C+Ab{r<=43!ej5Ut=W8EW@ zJk~nqPjrtF^_(c)%GdyHA@-BAt)I$w zxVo|I?!mA8`>x!r+tCm0zt_7+amggln1LTR1FjzM?Lmo7^)ZC|&4Af(VZ-4kMOu-* zlI-G=ocxIeQ>GM5nTTe9bwKsWpOQygUOyGs+q_3z%9ckCMCt>AMFtA0upM6QlA3yK z@l87p|3aq07>))wr|VyxUn)GksPN%H@NfnQeNF3)P6u_br(oyS%D&US+wL2(jUCAL|ctuP(c+x@tki!s!(km5V)x`&jSFo%?JV zt4KI)Jlx0nqvu&$UQt!y<_TVjeXI{WuX#&q>*}S%%GwlF!1t&=))$^HL>BYSn9iYl_p!c|{uYJS2}k#_Ow(h?Y;x#6eXNl0>E)As zkLhD2c)kIJ>o@+c51)N(&ai;SB+wI+EAD7fX>I9Z+Dkvll**+(HyesC$-k|-J{){* zq)_*{IT4Qq>*w5;PkH429}oONAT}o=rKpmBb=vtC&0Ib6FG0ytfGe50WLUDg)wB0R zc5=6R9_rIhH=lcH-@1WiL8&ruRC;?~|HaE|Y8pS#(krE?>Fs^-Z_>YAf92Id$x?tT znYw&9z1?PS|II7w#x4&?PKvYVw3o4@w(U9X^S$kO<(9UC{iLXSPWvI^?>X&rc7~o8Z)5Ae@wdbFB1-f^ z^$cZ8$*Pi;*B(p`TkBpA=0=_;8l|Li$Lm1ilH~5$G@!z{PO18j5!mZ5Yo(AG|S8k8NjO_|$pHuMg^5!YV%r_NTlgsGHin5VsBI(#K< zH=-P=_2RZisjWwu6}b(Y8#JGGQZ%=qZ>4>Ti^MU{vZ67qOD~e`Hfkw*xOpyM(GZkx z7EqUat+*ifJi-IykU2MaoU}PljYigf*lt@!BVTJFb6Ox4pX$dVxsE%6xTd2ul?GOi zKuuj2&{Wyj7urfW4x8uu+UohXtH!R0t+Dm;LnWw&o-TPRYx+7Pu^5^e5a;WgCr+vx zc6|2~U1E-Sr->zG{5onc#RyiG-#s!_aAH6O#rHYsALTY|Zuiws__V9)4RCiO4Az$B zx%J#pAv-BhD_-o@>|WgoHPPxmFO=-m37PXakW@G48p@|QcDY0K=m@RKrU&$h`bx^{ z>dNax8M}2^y01*Wce`rT#2A&Cc`nr`qAy2&n49K#cqay+=sHUY#$Wl+IxiSQTsKv8 z^y`u4;j~vRco-XUw8Y$38qt#`^og;O;pq+)m9#WZ#x`}7?@PkxxdMznD?+pY)E|=F$H$ z_O@@m+)QuuYll{n~`(aQnua1e!thxz&6XT7#2pIl6zVSUF`)^tps_|$-TJFN|F}} z2OH+TX<)FzUOjd5S?*@2Th*L>e%Q)9&vC9Ro>5SA-IO9EjFe%EnlR(ACCq-FcD=rK z$`fat=@!^1(OdU2Qb)=;sbf{49Up>4$PtY95H!+8td`T)G3^UyI1a|m?F(^~wBwv_ zC8yE<&OJhwl`?haZP;Hoe+D+&HSP7GTOH?|vz??n?Tg=qvc0$Z)|t&SZ*zD5ejU<7 zhAg<|4l6j3v34vt?)5Xxfym%j-N%(W3cYB)i9|E3NDv7hi2>_qfQK z+~Z;Z&t&&l{mX1oSV!z0t6z0*RO|q%Z?^h%?k>u*+hym{c9V^LOXHOZZCHC1?M538 z>>b1sv+nPFZThnlGThjz@TT>w_(Q}GDP?P*!PLthTPE&%roOW_| zIqfWWIqmY_vCApdh|=`M1wI~NLgFv|q1r{7SpHOdNfXOIUU;f?q=^-tY87dY!-bnZ z8ey7F-}(+9p@F4=6`6AxB(uMdQE~% z|BIh0W>+44?gm-%V~nI__ro9TL1*@Y?PQ||YB8oP)f$OMB`0*U=o=>P)}SaJ&&Yj2 zNg5f;3W;GPxgLkyv=%OlJYmR9YnY0K%XL%1E>PSwB)vj$ldQ`XH+?8g@Z1RomVbEb zi7lL;kqdXB;(rFNrz-BV_?j%+GL2aQw`I8Bv@S^dfL<2x4~f0fBxGYB(jQ3&Y#aLu zJ{@o;7;gvMNt!!ZbEjzTPMW*3=I)}oyBdE9#FwhMyJ_z3n!AVQPSe~yHFqz~eU$Ne zApYK(`)JMGM{^&ex%+DFenx_#fVS1&=oxS)YW~M+?uh0-PIC{?+{bI~fd=g_AdPLE zp!p9nh6Vgj)ZBwL_Ylo}lI9+&xlcB}6_7tna}U?tr)chU&7GmSGmS!)Pc>|J=sz9o zO~!RQMjgAU2JMdLjn?y$p&FO=)!fQ%dIQkDncLY-H9GB^NxZZycMWe^4)#hUHx^`3 zr$`zeUV6UM@~E$XjJsdvCAhMY0AXWssIak!QP|zs#?b3q#6!ekvN4gRf^00FooC|W zB*sy}2pq44#pDmU7qWd0c;u!$lf504DcQSWd*P8#5gt{k2#@rL@UTTV*t8!D?X$Ux z!oyy#h9Ab^`*V2YLxhJd;)gBdz|NuYuxVdJFaF^i9t9`jNB%{4*mEgf*z?(@Q`^X0 ztcE{@!$&wg%1wlaeJ+KAE#$ynNa0~GR>P-r_~SS{%3FkoO>VF&^&h#@m~0ltW*#ksfqSiu9nXP2dw4FJpWO<0}}yn(jK9M8`;33Y_{n%&?c;f0N0f_A>J=aEgSds7sw>Ex zjUQpsNZu#_DsL&=eWWM*QJ6FMTFTo5PAqxzHQwFerI7$OQuIY|)3ubh502fE#D3&# zP_D^+zJ>2})TO$)9e|WgewCb&QWIMJSt!&{DeShSnt@V-F(EZWC$c)2J% z(GHHoyPn$R$g^(re1wiO4AEZIhnW-mf>cf!7u9 z-QTu>_W^h}wt=?}N`FHeczy6bAEy=ohtcyf9q;+KV#s?Cm>PT}zT+k-ybxdOJlaRE zExi5U<+VXx;z@0jR|H;G8{};QZ*C0Ueqd^T4}lj^c=A%`r4Eg~FQ3k=$vZmfwHCqwjOw(7>h2TQEF!IqSR) zZRG7}Bk$*JPX2jHRVh%)~MVk`U9bxV)EPhEE?fm*%ifmakV#Q9L;St@-W&^tLviDe5uVklnv zmO=M|Fp2m(8a%vH*Dz!}3W6GraN<#?yo&z43h!ivcZ-(a2zV5p z?k`?p!jN0%4OVz~MYPCES9qv0TjY&Zc&G|nBUovXg=2p-DBE}DJ8{I zOU}-pHkJ0sSgHF@n3kVk0+L}l7GnPvUr6b;Ie?JJX_NPjM%T8TV@AEv- ztuLwf0$>TQw>Z8HOX~e_UMO`*y>e^SHS%64+g;wLl2Yh*<63hBfkDOqRE@z71>Sy-YysB7dsy2y9DHS#_? zka-T);u?8BSiCjzKGR?GPH!hp`RN(YF6ZQ3=p95xBU68t4XuMU})t!kGy z<2)S`&QA(k$wXUQ)@l!#oG+DK~IWFbYl+*m_zVWBz zYLi)m(@kxEx@pLrZt4W5n}*%#rU`PoY2ts!bW47w9EccL-TW0QQGD;{ts8}kBgTk}s5=QBu( zZQ-18>40rpos5eD?k>ia0e4q#?0{|o&G(|O898rj9j@5sXh@d^Y1^-W2#t8NY(@Ysdz^i}9Z_{utvg zGcL}{h5SD;PUmV-ymSUN#VgM7g&f+Yknmi_Cz1_(4&xUvUd{MbjNiie9gIK0_{)sH z%J^rDC!>rh-Y#TA{&8d@-VuzCVSGB{<&0M_el_E_GX6crf5!MrjQ^VPLyTj3polk2 zHsbA1HsVcZd?e#D7+=Wv1&ps@{5rP-hp_JWGVhK>oYXoeDKtFuMDE|mVtM!^i*t}_Y!z> z6n}YHh6^=)GzYXodMb96#@h;BMDdrGt27?X1(p5Al0)`)@k13=BeA!@8zCKveJ8F_ zt$QX7@7o9xd<+md?v#q_J^10)d*fImQUBtW1PpGa@hE;Oo&_G^B#U&I47m^Dr}D7I zR=lT)C+}G--dymqz#$$~Rv6;FhMy|$4&otW#6vj#g z#vz4=SB@~m>xQzD;RFa_0*3=Zgdz7J@Q_}w{1U;7)xSLkJW6jwgv0_L@b2YnX@O#l z*LW|0S3n+$A!qsGiUnV#e>-zrrrY7&hW_n+lrb3DzugTbc|6?i{R^o*yW$p5daPD^ zc0HOIr)SqEwykH^=X*V7Ws6F&QE{RewdEA6J-dF0_&vKmH(t-K&-Bs}uV>c}(t6LX z&+|lc&+Z`qo~V7Tete`y>+S2;+`Ej}k zsDAM{<80Wjg-uYdGQ6Iwu=_%Za z8b5*4TNrZhLN@S$WFtMeRI}NOwUir9Tu?G^Nk!%SlG1u?N;q#xJ+`+SUbkX#ed#=7cq?CX zZX7h{+|322k3y7}(O~rO1(l@>NmhNWkX5&cuUaY~9jCISAL%ric;8?y%jNwB_d_>n z0Mz@_87~#_+-Ssz#w*10b)3c_X9Pc0-r^Q`^h#5C*MdjwTHWZp+rgvfS2w2uP~|-W zUWHDAJ0Cw}u||3ggkEPzhhm?DYqhv$gLeloYA56KNfa79zr0hk4P5MBMk8_#ZTq+1#c}fMm(7w;%&tbQF-y+f_g4i8+|8uBtL>5nV*1n zmV4>_rE;ToyUI&IBoBKG_kwukHOm%%l{R|Dh*2X)M##iJ!*BL*Hy+tWKMAup8`mEY zGf>?5CkHV9WbgfSlAQJB_I1fkjT<&^992-gnT@dhdJd|(Qi1dNU4`2?G_CuxVVgW(@I0slDku88Yy8g2w-;?% z6oEs0sM8Z>meL>7+-apupEEtTxUhtde# z?6DG>33hfq8YA|jfo#qiw)yt)yB|6fNMfQ$S#ibU@|@DT^4#hrReYL~y;o+*__v?U z+Y&=RySPiIlLIoWW;dHvoT9?1x#B()YM&hU8dPRvk({cKDp+*8}-? z%P_aHy6gf^P3&c|sElMNEC(NP!)HCe_u^%p0>Q1$AV5pjx~Z5nJvX`lFNy6Zif~%=cn)5FGl_=_1>ym1L;d}Q$;+oRha!kKm zQi&tX>>j4flR+OiTu__3|Dxg_olmR{$T4TSYSY(C(Bz_$!l~JLC74EyZvu)1_UZV}y}VWzwp#!O$* z=HH$BpRK1hF9=97Y4`w&m}^#%BOhh#EFIC<+K?$19GK~ zmk#)qaZ2|a(gP`LC8M|(TTGc9<9-O^ho$VOegByJ#~Ggo1ereu0a?5-DnZcD;)2Qf zIoZ?my$7bQRhIuOENPX8cXckR9I8&2wMwKnx=V!?uV|I(%FH2UUfC*9%FMwD#P+I~ z)C{*lLM;*8#5JvQM56=mj7ws&GJQ#SYS*{Q5t2|<(mq0G__u%M?wp&~-gnXUfxFhq z?ayC|t~=3T?uS!orf=Il0heGi1-ynf_e-kUcvv7ypyb`kayW$iUP z=i;wUx##p>Z+P;PA;^l?RP8FICX-m>82?%Lcu9KCci;cPM8Z9KxIYM8O#1;Rw4k>9 z!h)(v7a3+>`$tag6Gp+itNwAiJ%364ikYRA*>r-V)z|)Ulur)%g!8f|HgHd0$j<*`;yg>IqyDqZgphNqs2R6(I>WTWX|V%gFkUb=KK)xN9KHP zypcJd>7^sy$ebUf^^rNB=ZS88&4m|$kMk49EA|a#%Y_{3aengngn*VP#~3>PF@}SD z4N%7cz1ZTNOXw55e8_P?>M~`uRo7g2Ap++ThT@(}=!f&yTsRY?WL5L!c{D-ImuoIu z%|FRcoH|J9Mbf5o34L}T^YI2L{b1f8B~8QNvXWJ31dzu}6il%^<*4v{dB~xm)C^ZH zeqw1x!&RdK!IJ#3$`-~py%^jK`~2a4iewEO6zyeMKAI)|OQYRJL#bD^3@Jk=Z9B~d zKYYWXZ8*>HRJ80_P1-B}qT|^uVk+jOBeJON(@~J(BRb~#56U#H|DYbXC_+2w9hdv* zG1q^T2bQSFwpxrsx`IU6)N^Pg!!X|OaP66kDxtj;_3%BY_J>k?+yl^-)Rwz#JyFV( z=dhV4lt=e(U)@<`noDCGZ$oXa(n@ZJ%JyH#oUI*ib9R6yTaO|0tonIHwe!)I_fBP^ zliwECWCx+SfO3M+S@XHaTQ^l<_0usOv--(@efj5Y(CVj*u$72((4_j1*b0f#RMo+0YA5ByXIoi)fX)1_=7c0(qHY1EgJ`-SY6VbO{ zKdeq&>@`-hdGSZ~st^2M{YtAdJXT(8b?Iua{@_D<34*DRh#cJ=*Q9=6pSSYXkm)4Z z|Exx|z;5gOf&H|FgaF%C^MSzr)b#`VXC@K^?AKK;?|op6D^~)!Bmw!euU~^}D`_c6 zj=jCgjUvf@GL7=_`~_Ag%I^=;kPP}%E z>mkGZ)kVO#t_MlItkUXDj4wRK_bX+*zwfa!Y;}ijzlFOJGG4`B((R5}+1F93$IT_= zE3mdNsf}yr!v5TCe*!90-Z6qnAG<|U)s#N~)Ae2RN*xO3qiuDGe`bE@J#3+^e3 zdp6wD6n6>Sa}@UixTT>vqBNgU8k*yIg>=BCb1Lo(xE;+M*4zn!H3v2tEb1BrT1Ogm zCu{B$uk0vVS|=*Y(sg$>ei2Ad7vq(HJEZw{)!eCpwLmsrIzf5*ITq39R{SRrUr!_G z?q$#*I~h`cI_F>jy9uLpml^D)$A{LnQu8(qI#2hNY-+}mO-)y_skutF8_bfL}^B_~m3ra4rDjcQM{5al}u2kzVj=z7FwUWc(enfm209 z_?x!N|2x^h|4BCRC1d<@yZf5!MrjQ^VPBvkUmKZb1Zk0l%Yxww&p*OCo< zDcQhxGyW*!`xp-;xcpvZgWrd2@TW6g&Ugjme`dUyahh*T{Ly41-brLbP9ftTK}iY! zl5F7EeL?U~B^!7l*}#h!r?qT^zstBd*8uW+q`3GXvcVrhHt-zAiy5EIcxfk>Uq?3h z%g6@*dyGH8_=Ai$G5$8=?=k)bq9c{!?L#)w)1Pd_o5^?{PnEwgm37DKq`As1k{DEXc&S=I@Wqcar^BG^n_?3*`%=qn$Kfw3_#(&B9pBVo) z<20F>;_XQ`;ysaUq-QAO`HatE{2azlHo(I~-gL5o3HLGVMm>ke(6G~ZT{rxNyC=I9 ze~Fvmw_s@Qeg3@4*^AR_zLtId2j&he%y5qh$Qa>D94Y7H)2#ecWA|IS+q1{)mg>MY z=F~RS+k0BCQ0(M?EjbLVV`yoi!h+h;#VxFZpj8W8Sfx0wc_A%Va91GIESXn@V0G~p zHF*2v$G#D*ta)%(XZUL#T37?&6F46};3e6Iykv{j7Kdr=1U*A!=$jUgmS^NMbvzKd zmb?kL-e-98D~ z(Rq)8H<$g$lDryRtMd9r3TjAgC=h=c=Z0!jn2CfyrDV??p^pn)u|YT*$*BKDC>sW)RqE% z2HqwBgMppEcq;6lmU*VzIDGc$#xM?yRfd|1OS@d%VfQiL>2fQr!5fAAWCKhiX3S$v`iHGL2FvRPn z#d{5SH$d5mCv~29Cu+QbxM@_b#6z=Hm{`1#3J=Xnk2hA6m#6Tk4}%QJ(|N@T4^^Bn z#5+@yHy=F0DSfEogo(wYa{(j|pQ0X*MqE(to*vYL7i*2wh2W9?MBJdpwct$zrW$gt z(0ISX!?8XFul&ODue49^m@(rrBf`XABb7*n0VCH)4Z%~gqyOIfw>M1KoWItb7B1a! zRoZL&dpCdSREsODp}7m|Yb3s=S>kJroeKWAhi4h)bjg0hLnFpxSJT?79sMU9II3y; zv&OzlUjOHl+YTD(jnCY5<54f9HEqZBZL79D+x&bQ)>>`bM*QQEQda{5J1mHYfeJ3v z>O3xwX2scI!6&wD9+%ILnk+KdPqDhgf*&IOJT9LbZyuM=^wJS;9+w}a^?6)A&lBDH zJT5PQsqUR?#hu6Hhx7N&wf%Wqc$B0Dl-C|i4qNM99|Fh=6_#_t>AgOBH+>GJAS#JF^sR0fv}M%9SjzAr*Rdkpa^yOApEvQ&1ikUKPni*1ugM{|g z;o_J&?DpV!6T(dE(u>O6Wr&yowxryUFI^~h*^07Cbc@O6N3@Qf%fe){g=UwjvgB-T z2cujt82f_C(dSHzc_akx7K9}(;ok!~W)hYEqVgsn*{>Vj9B03ibk2j0b0A>dNv<$< z>NUl>Ie!}3v4=0UnV5#Q+FpL;$ouW3=Z_BKn0C{QTh_t(E>o|Q*%hn2x;+6PM?e}mtH$6H&`K(+^=K$NT6>}&L5He zHx|bCsqcmQb;yt#!%kl2$c=7MZx0=E4}yCjeq_i^4Q|R58FFX9K1H}(_ZVEuemwF& zo&Ct7`5n0dw`G(B+_teY;C3{3SaTdcwA?o|?Ot*C$R2O!GIsU_L1< z&G&G-pp2iXTrJyTo(9}vo(Am4 zpxWfWpEO;DhhmBF7#tDd5uXSTTZD%#!o#L>Xem8)YIuwbP#$b3EIp7k?m3KX;Nux5 zT_SuY@P{tn~R_e=49&bZi<4e>@$K7@-s*${6wxq;J` z1%!(|*?@~Z*?@~Z*?_Mhf8b(IHsE4UHsE4UHsCL^oOf8x`^-cT)O7hU7K?YGCht}7P>n_zo%bPl z=SHzGKLMDUzKN(S+rp!HVW-8Aw?>oqd+;h^@UGH$6H#YJ+Q6fEW3hNQYVv44*~u~F z>AVM8;58yFURgC##2es^kPgLu9M^c&dL|7oo(KTyS&uME@1m#hgQ`>U2s09GDX4V7 zB*OJ7ekz^?9^t(eJQi<~!b=914DsH_PnA~$9?7B~9#LUp@fLxX1z+OHIwBTtm%>XB z(%g7I!?hak`@}=JkUXjLBrgfdr}75l-A?62JUn{B#Nv%rcu;MR*GH2#N#V)ogyiYG z*$Ph`s~)DwTLd13r}W`c7;@{p8il8hRZ}|?r4LPwNZQUYeL(h0;%4Vcz(s8pe@yDv~KGuy*j#ZDssCDC21C~ab zwuB>1#&velmi_~AJ+R5dRUb?}Cg1)*8habf{hQK&y4=Rz|86#}lkCRcUp6y;ecpZw zvDFK)6(P2=^sSJ-RY>33zwwTv(A3=7|0yv4)BKd@Hir=MB@pZ|nt0&OJ-wR`?S5v@ z(+8N*c$H=Czv1AGZurLargh+kXK(yD!hF`8T=a9KIsrS5Ry2nV`YLucICRpm+sd{K za()s4B$S^@+B}v1nARL;LSgpwNhLYiQ_jRax6a1m3ixo)A=iEW+xyec7#{)T1+^y7 zT`I{bt-4^!lEw4HUXAC-NW`>#4*h7)zZ|&i%6onp2yL!}EJR$RL|jrdYg)Hn@^a>2^CYWQ_sh;LE|^K%Tv>I2E$@EOdDCN8e>hHPT&$EARWB=dx4W^e zdYMr1PT|B?uRibN6EAL<5=?xFoA_0njG`IX3NDcN)w&NS5NXHLM12!1f9n}D8(!VI zdQw0>7j4m!#WiXI*UH4SG=;&-;Wx+sx(x-}8@G)&g~2O2yY(pyKF<@~`VC+K7tk{MfWs=b*dWkHKE}vXaWWuV9x1yO_+da zk3da0&(nm8stUQeE)_B5*ECOcRYCD!XIMzs= z!f{?y{Sh+f%D}QpK{cZUmMuCbpRyi*7RQ$$`P+q{cMr2Y=<5!~Y_Dx(WW9+v+VvhR z64~%4iri{;4q4c(cT{!2)BoRx56z3D?Gyf7d~Q4JI_iq?Z2$Hl1%$Pldkiqls+@? z*K$(B_|7>zd+fLmjZo=!eQ4Y^Ix-oYE7Y}(d+bo7Gu9qEz1tX`-rKRlPiSL!s_bR> z|D}8Iq_ngLPdD?*ESmdbw&!H1;1)hsaBh_C&y5PXbEBN#Mmu45s#JoUDwX)(F;$AR zQW~0>fu;hC`#nZiq;=B7@+Ym5W*{!y@bpbrfak<*S?FIQ13VtJ_I;k;7$u3vdn{@R z`YffLLbP_9XGOxvM4xr&&XaO|$=^2IuPhg_aUi@p-fCl(Wze0Vxf3;alD7wt8-KFq zPSM<*GEYP&E3yeS z?wAij89{HCgT?}zMk>R8E<6#5yl^9 z{0+wc#`q_Ucfq}`X4GX4tVG^TIk!A&O{ zWgy%bFcxm4O}M+U8)3xrh~8#U1Yful*$uvMV*pzCD}2e5{!qJ?49y#xlb>5tH)olg zGKDEe*u-POlBzQPyjEX=wADq>*MIdz`zbHHj+-VH)h7`BDt8e-q-%M9rM}ZZjn3=uv0OiL4$^qj;HGC%8YwRufGTet+}B7F`;qfJ<(k|y zZ}(4lK6OLyIVqd`K0}7YyI3RYymL_ph<9!r-uZa9i+5`rUVSHihibfKaI5Ki33cUh z8i$-Z?_=;V#XidDynmuDq|^Cyqw{E=sv&LQ4MCgcU0oR5>+w^Ar}n_RP2r&`6-MV3 zwUM`}1>Pn|RpV^}FXBcO_^a~{ffs8Yo6ajlTdgg;U2Wur&~}>>NSW)n4VIdZ?|@ek zgV(6>ehyxw4ZQc-$P1%w7)#zmTD&KKH#kPTI&TViC$xcA58jC}c)tLK*LaQex*5C? z(xKSD$2FQ-o@oLv0)V(Y{YbpS--8=f05wa6IfOO}Uhe^eM_;u0Rs7%J5l*sFm>r83 zLPvw-;gJ_67O#`SQ|G58Knc`%)4)U2B3`81lc)1e1}_V~ls++d4x8fDd6f!}{K>@P z-L3FsdWd(FmcEa`y94D+@yhC#c!M?GHTY0S1x`FvNy5b9-JGaTJY~8hMs_WDc#ez+IbiyON4lXJa$cnI2H|CXX$;=Nnu=;=x?sec zFE}m|Nyn_f;NM6jbM&aOZJjT;rN~W{oG-W)yNfkmm3Lsk(%zeln|Jg#hwK>ExT~@E zo6YIXeVUJjU$b@E%o)x5_Z|G%&Tv-qX)|f2o|s3te!x<5h&}TzbI%>eZffk6+kAHO zo`&5+%}tFbHr_!J_9U1|EM>hdq#W4y?9aA$Ic+A*?;{y|ckk#=QYJPVH#cu;+|Z}# z`@>x3+08q`ySlh3Xj~7uoA>YQ^ZLP`H8vi2?%C&e_TLfCMi_h3X*17m-WlHW^zLW2 z0CN#Hg^z6rV=khblf3<|q@4{&=`a&%IlFnl(j5(rIf;w6uWxLe(cJxYN?Stpb`cj` zNFn^Q$e&{GBoOi^He6uCKRaP@V`J)TZux|(Q(xQDu>XeL4F_+a-0kSU9jBTn&aKiqkk~%+p(`uBK9Go)Fi(~cP9aR5$$QfwHJS*yhE0IhjRE1*~%SC^X^dBn0IJL z{~b!1?ZBK&sTp+V)Kp+cBrg@X_EJGQMY>_!yr*H;DMC9MNiXOQr#I&}kAj}KcV|a~ zJ+sl=eWi#@!KU zXzq@%Swu+cYx|!&2wtdkN7w?gBTRD5A$iToO(Q)`cO`EL4}e_k+l07jrn1|*3cXvG z9y;!%moJUr`4N>iJ-B8+{Kd4-Uxa7pWKSz8n1bV3GibKwFBO1JS+<^5fDstfv7S+Y zku=lupaP7-sh`%f3NRXH2V2i6z!)5sY(1|4blSAlqyXb^%BS^$0^s!JB*%JDMKW-_ zr}dJGWEv@s^|FeLFgiKbuT*5D(b=(HK|cpdfJ-MlWXSmq3%@liP&&3-D6}mHrqrVQ z^VhNv#dg@TU<Nj7U6U@F8 z>t=s7awqTLw|~^>=Ca>^8Hmrk#LfN|H@Roc$SxFTIaBtxD%gnW*^`UtAXLZRrof{a zMj>3Uz}a*hG?l^)Zj+2t@Ys8QAHTfYi?MRd2OO7`($_nm!hGYqoMJW8`F-#FxpV%s z>w}q=lHE*Go;b?6-Cn#u&06+AFw>X1nf`&BaMfke1>I=31pQ_J({7FaOy-nuG6z~3iI>mUVlH} zlRw4vK(_A;pf=lwVa|(>&f=Kb? z=_4}Jb2HP^(<2i{L~>8b9Xd3UTRp#gVR=<#Mpeb~$kNQr;iHFV3@+bjP{5mPZ!-$8ptb@+!x{**&45%l#p-23RBEQt*NN;Ca2RhRC#Qqtimvplqj+`!UkcIAtA@@lF8|C z^%-zvs!x7P>LXfUq&$>y)9e#lc?7F{RcAyD)iKY#a7k%p#exdAp>N1`J9az_>W{{g zt$yb?%9+ur!?h?Ku^xeyP*+8ZuoI=Sp&@11G@tRb$M%(}&dIajjbX6Zp=PUX^88*#5@=a9adA6@QyczTL14SraQKPPxng>XE z{gA2%hEx>1py-W8YbUbj&#yIP6FX#119fs~-38wJ&G|N|l#$orIu${zN1#qkRCEd* zTIIF1OKR$iaJ$Gv@H5Risa661_SLLAqczJs7iTje3DgZLyU{`>>5`&aMLtJ%z=cd? z2i>QJ>|b>-CBkry#UD%u{6>$ymTwb#rlLoAvTN9D?L<)2*nn3mQjpNTnp7N1lb|#O zQw`Y{jRtX0i>SE_f7yc#Eo*c2{a?)72dK({;O0!5z4F4yTcWV;ynTt>KLg|3$<<_ z?ag+YDZiD4`o(0oubNGdRx?elxWzN6!*%22BU3ldRCL4t;6h%-9DdV$Uw#`)mGDXJ zs|wxYszS@(ThtH=d~dl*L|<#uu!LP^$r(!d6cdm;w!0a#dym9=rkkQm!NxHaGi4fE z3CQNE)Tbb^eRb-Bs8+OIyL6+J#^09!a}F>^l`kdfYq%_t-DS>n6@s5FKsu8v~@pbsC9IgiEi3%RLkv))WesyXYB5dbLyB`{XXqC z=7YL0ZR>8{t0wN#{)aDdd(2*rbGlNrOPSR3Xe}}cpaUO8Xlh*Tv z3{1chdf2mrliW@Z>+*S}wZs1(dtU-rMRoN*Gw;pI%R&MH*~LfLcL@6?*&!MhlZdEj zNJxNaNHBy=QBY73m)fxChgwk~5U|=>YwJdB4QMH9RNA`Wj#VpGtGF-u|IVFzXYSlL zFL`YR`tkoRe8!CpYdcvO3{GTwdtXPXO?ZF9fOD=jW6v?o zF=p&Q_WQnR&NO4+58$h7UH_?_Tq?ybC$1C^(JehZfFnk9{SB5V(UCPBmqa=J%rWZ7 zCO!uvlfn)a-6ic+!7TFO-b7D_}mb_ zigTN4@;j!QOv_YLz-_82W~7#jkB5Vn#im$cu_^Aq!(tPS%fiw3glsvEaa}kXcZKuv zr*Ty{FMk>@h4bofqvrQN2FI4 z*;XtIPOth!3}NqX(`>d3S*3g5i?ID{EIoLYvC0EM0{61P^xRDbOV5M|=oA(`PqBfXoBM=!3W4_6WxTWV zOE@QIWWYhjh3D*;*#{Hf5F4R$q$qL_A;oB+vDGJ|S;X5dNM}_aC9df0=v%+^# z_^t|ns={|u_|p_Vr10GpK1JbsD11+a@1^j)wf9~5>7(#{6~3Rs_gDA<3O`Wc2Pynu zg&(5uLlu6Q_PHy)sc6HZwNZO+rT7n5_z?;}QsGA_{Ah(Aqwr%Dew@OOSNI7EKT&J# zO8+Fq|8$L>3Jd2m(iA>j;WHFIQ{l4|K3m~)6n?V8Pf_?>g+D{1K~XrLai+rODg0E0 zpQiBB6@G@opQZ5m3SXe`g$jSRHjbw^1&JnmhJ~D`0XZ4{?L5v;V!Wv>=X{9q0qsW4 zcV~Pov;TohEyVa3?IG?@b5XLN_<}2ZoOXosG}k11i$8Fl=3dE0g4WK53%C^gCDSGx zA_I(1;db68^K)!57?b@& zI$)1%uK04f90{fuH_5JDHK*mk5xb5083f;X%o!mk)FSr+q0r_`!1c89Y3U0VK;m7ju-FbLWRu7=896+i5eV}=A z_yQh&91owu!-KMLpe!Arw4U&RCWG4P#|9;us^%Nd?RFMoQmuoBd=yd0#}S2`r3dm$ zxO@qh|Ar{!f8_FKxSZMDgq$9Wksdl zcP{@2m&cfvo=!xe=TxH5Q^w`Xxco9MznjY+mvi|_F29}2@8j|ZxcpCC{u-CR#pPdcc`(+BH-RYP?L`#vj^^_5TwcKCWn5m) zd=}?JoX_Tbch2WY--q)^FXQ`i9_eL#Kh7h)jPK8Rq?hqnD7U6~kY2_k(TqoW89#{gNH60D zb6!d>lOvss_U07nVm#8rDAK_w;%5}`GK%;ZMLdi`Kf1?A4t8NLEnSpTnm#Z4Up`N~ zXJ*g5u~w*|78z!dRErF^$Owy!w8$unjJC)ai&$DxEiI|Tgqc=$Qh9URUDnawo(Q(R z<@R^BvlO|#edU(BwyWG;?oAxGpRyh0_LR1tBoEK+Cbz${z2ufFDJd;0Su($v=HgYcs_qCDmn1g_p}}Ext|{^5W{^%K3OJkZW7Cq@)r$7JKhPvO*WH zt~n_d6%;OU6|sOxWh6xITneez4k+{UEKd>2X$Au8tzD_d|7(==I=j2^ITh-by9<;z z9ajtcH(F>Ejk2hyFt?~=NqI$SQE^R8b$Q7WI+JPe;uQ;Pic2)ITaC+-s*1t*0=gI; z)nyf~yTswG^f^3Fyd&VZk|VHh6h~y=EG%ZrlGfmP6~*%@O*PdlO^X-st4KYxhn)Iz z`lJ4x+z5-Y#BMhfncMCxa1>TO%ttI$vFG2jejZ?5<#lRdKU{yFCirS5e|NV$OL- z6#9mtBl%SnxWmAmB4><;QSOY;yPjuzDWgvS8+cF?i~*t?Ssh0bu;z`(Wavh5jLVrn9#ko*%3!=oWixRgpO5D>?;@*!E7aS8^e)~p=n-V2% zL6o?45pWxodfN#cZp|>K;$8s`U0|3~adBg<7fMv1ic5_WcOGyUGQ*sz?`q&M6oxq! z_e5b%dPi4NEHKym0pdmj++LB{7s$->SYN5{}vvIWK(!GaY?x zESM**Lc%3CgS!{FDe$NCwQUA>RMOY38Qcg={?g!2`c7#ES0mxtH-mdn!gXi{cT~br zy^!-NzY*C^`Z`%KhWkvZ-x}ba@LBo5(waHa=QrHV`W}>USh7UK zHAuLj&EO77I85PfeWxh(c38rtHG?}U;nJJI`Ok3b4Yx9LR4!_~?Iav-sff6q5)Mr} zB5s6)Lz9h&%aU+8&EN_p+~j6(r4nvRGq@TFhoWT8t6bJfI9%E|dXFNO^F%hnlfu*e zaV81ih*xp9OSn9S^2TkGa8sMX-7DdyHG_Ll!cA`m_n3s6(G0FZ!kyI&?tp~LZw7Zz z!WA@wJ0#%>o53BHaA!-n38*(ynhzZTt~2+S$u!{5&1xYo44_g6kU(RJnl+hk!}JzR<~zXXOy)ay+hBMLCi9&TEt|}Duq~O)caU~E zS~8jM1Szkq!PyUNdBKagH2K$^PMh=g_aT(5gR@n$05R+f03KlJl>2u-ThQiAcYqd* z*n4OeM(q0|Vy;@Y=I(@GHqjZ{Z?XjiM;|`r@rD6eLt@LE4dL#oRbRV^Memu#*tE3Pi%{JhjL!$&VK1!q}kUv%;OA*I#jOUtS& z%1ed_Uq>?cgjsW^#g|{BsWNpb%6Ho&Y!RTh(R{(y9l8X21+PzwCq>SuVTSefmrs2C zg@-H0$xMCoU#!p)Vs7e~<;5lCnvP|%M$gAoCyV^XKT$T03qQ}^XMf8^(~8Pv>%azCiMGh(gZZ69)b=E?>pvTZlq_FPHy<%b(=(KXduZTu$Et z5I%;+W9W}33jIBZLOznq*?Y*4pU34DT)v1XdFK#7Ky}IDmNN+3r`>!KJc>RE0VEB<sB)v-=a61KwllO_k`ej!j3a;gav8v{vq6!?MZ&8W?gO#b6f&ac<4-QGS-@?DjP`-z@JEi; z`ZNNfF6_NSdiNH$lFQ+iVc)gMaz6r5e?+>F9_9$Q7Jo9XD{!k(P=pidA>1bXAu2oG z+fm_ObMzg+k^T_=$UOv{Sc_N^tK9AfBjaKa$-@G`Db-hb>Rf4t9%}LI&S7Im4o?k{ zYk7{ojVcjN%+W7FHPx?~(vWqJX5{QmXguwU4m0bt`g*++ot@Zp^QO)9^}%A@*q!7n zHXHp_fkvY$rm+raLhjJ&#|>>tpSfGxR$EuE=f@WNj2+#C-@B8{Dx99!FRkg_&2_c! z{_M5Q0mN0`clG95Z_B!;t{cT?VI#)42QltJjC-t5I02H!OXoiROYyD`H6A=L$*51< zIN7K$&g$MsRL5)CIJq=%;MV$FU&VpWY1+_w25{ zu<5`PyK5P?`72EXq2&@Z8LEGxM^Gh7U(`hW!miJaQ-&5qdHj-WUYrntKcjod0&otv81tvNan_ z-;$aYnJea2lwqpSRu?H?a|V&B3og81#l1V9?I(wg6&g)a`LDuzAPCnkuOjV~#WcH$ zv|%kByygI-TSYo}d!f?8D$)tj@+#87wzP_Lkajv+T17fRnqNgaI9oMeMbc=;>*TSv zzE6Jg`B!IzAhH9v4qo%6i=`=h`p3gvGWy;RKg(EuqdS~)@R~neXpXdIwPS1P;57$m z=Yy?6F};;CA|JeFhj1Od=F8k(ocQ{f4>AwR84-3t!!yE;YdgiCBQ(n`UmXA7zEOlO z>qhC1BITteFR1OrMRh!ygLY-UrQ^|@U@a}E9i+2Brdb6~xxAoupvr=JJbECGKUNEB z8d&EdSs3O|y7lx?%v^Z!9jnYa#YaUr>ZB}2-at6g zlvU1MLHTC|pz9SagO5>Lv#R3`W|_7GN5|OKiRlcq#VZ!it+;r~rLyqSlJc5-oTcZ; z^x38Ma4rUDgkHW-$*$;=V9%e$Bzi6!P-92r$Vx;!j!24UH=iE(^*L%Z4t|a}q0Nc8 zuykf|#S$m+Cf-njyYqOr`w58jSlwYKZadC*w`aR&MNB!?_2JP_ z9@Eaatz~-N)f>auysOVN6If~o9PdU!ThAw9qZrH^MOkHWNky66E?5~;mUVqQwFK4s zm^Oob-aQuZ$8OoarP7MxkFO+9p zf0o)ynEx?tFdzTh4JO}iRCa@D&)Pm2I61BjhIVRC!UmJU8_e9Q%6aAUmsFQ|Ed?m= zx;{>)mJ<Op2MBA9q!Y)-8aghhN@P^jR8jw$uMj!7sNDs(P!fuRgim~1a?}b#`vm|Nu zO!?OJE>_d?0v*#9$B*N7O`NIwvPU&d25G z0BH}+KB43zI?muCoXK-ZAJZIV#3h-nw)FK~)`$K`5T9hmPWG*Q%`{h92QfV6N_fW; zmhcfs_XtY&*_`$QrR27{xwr4KUi3$TM5I5{xAGa&tg+I6o1Fe{C!DbKf2rdvp9^#U zWX9fLnrE4@Pg{qXY?YIz4LxDW+peR0mu8x=Ri?R^{Wjv)D#HJkG(Jmdth2^6y-=4U3cbkFR;<9BE zC!4WZruk|{=``;qoO?Df}Vtk^DX4? z6QT@H`>S5zTSXb3W{qCq+eR6lwn@CgcZf1PEt|chVaUo z&9d`2nm>R8!DFm)8K}lQ*cB7OpEUupol7w#ev;dST(b{Hd1}&dZ;AQQ^G& zsh1Sa%imhGSO_owmg1*gOgMU_#mXPO7C<(HXzkbXBkf*xIC`w=9gf98udG-R(8DbO z^myDt=-xJ%9(o9{x+71>J~oo}y9F|AFP5M~Y$)w?3TVX5HwxmE3hit~2%_w>P`Cm3 zLjXA1jj+RcEs_b;{1*VH0AYUtKyRV?^=Q8Vur_v)7QC}ht*s;e$PwQOl>W#OPu~ED z?@EcMniX~zh^IU`cprN|w+m$C4A>kW4N9$$9PtxDsr<+hp9xCu3z8%L3{duJ599sp z{a5Qj7y0{{%`dzb%N(7VQG_eeqKTgeUVMj5{6g^bJ}x;rY zL9NEc$7&l~e7wRZD10l0PgM9Mg>S9!Z4^FP;oE9=y3*55;ZITc_6pxY;X5jPCx!2< z@Ld$XtHPhE?RKTFo5G)_@F9iouJ9=e-$UVhDts^Px32hmYx`V$oZ{a{;rl9lKZWnF z@BhSMI0D*i*X*Inryrtql>KV0EQDEvr;AEof46@HBNkt_bO3O`Qa z$1D5X+>%!h<9icXwSbjFP00|Q3U88eDb zm{EKV$0&@E;By7dhxho)iT1^}RXQ%lb2$>sD@v;f zkB**&$BU;dJkrO)gOUw3I!j?Lr*}|z@b}2!Pv_w=z_9Sh7Yh%{!hz1G@SsT)9+YeV z*zr%|;qm$?3y<<(;X&t6IM7l~sm_QWB8N}o;Ro^XC`T3^w3xzymT^k65#oo*;nR6| z44y20ls^j(%Dxc;WoJo%inA0lD%=5khlz?01{!r#EdJTALa6Z-_jFD6!E4IMZ6=pd<>VL%jFkyc@>wh;qpyf{y$uPAD2JDPKT>&~iVJkkzE8+?-B1BoyNjR?+95;IX zZy4creF+qtHlj(zJi0uTfOu?nX1Kqyu1dcu+rfZRp zSzyH841oo1i-Nlb9w7p7CvcC0r)#0F4vbg&-c@i<0Ec1Ac0!*Y7vh>c-v&eHDygoG zf_nrBU~3NrsN%jx1+g_o3%Gw`!-uUUTEJ~=#n%ii;Og-j8(SN+fP1M8Ujwv&i*2WA zY_8t|F0VbG)3<1jf?2x9t<$(Tyz(o`9-Y9Y1u_lN{-{n!_UXBtsvbUx!5Sf%{mQo*g07rWcs++Fh z0$9t0R1kO-*E>pFPL#NLQR1$N5?2=`ZeNtRzeT`ZsFol0>affWb1Lq1;IMrc=2YB# z;IPdV=2RS=QGxBeFsI`707uV-RHx!T01nIlFsI_WA`{W%w-7j*o2icNmq~VH)&S=f z?^=|zAqD;|aBrH}=Yeb{m(yCF_M0$eq3IZNw<6M5!EhP`y#qK|z705%XW)+>-;wje z-7DcR1z^q#_n?Hsc1A?pV-gNig^0KY35V^Eh`0k1PRtj*(sxk8VX6>O-ysRtRl@yT zDZj(OQTnO;#4|dISH*n?TpGtEfRgjVO~6J{8vIBfrh?3Q;Z{nx#Aa}hNw}nDaNkL| z*3IB1V2>{i{**pUEt&I7pM(?7KD}^{NjNcX67F%OoWBEZmSM#!o}CizSp`>!g%qWq z(ub)Qb6&Vo35O|EL|l!83pImVE8)5~gWD+KQkuch*%%@pm;x~8m5&D{9ER+OxCRM_ zA=bvdp_Jc235Oz&h&wFduzea4cT~cO{*CgX#_PwPs>m;bMAX+#!r?L^uBU{<_H0Dl z2nmO6+laU<2`Bn}%EzZl`4s|3a%z9r=4H+cM`x7?+_+|Nr4nv@Gq?%~H=!9^jf9)n z3~r@_JG~j)S_wC)8QcvLE=|G(a8F}6v&XHCz={5w!x&-DKX4V|!ux>RkFc^sRcIl| zd_=j&a#U7-4;((MD66hsvZ#hzBeQJW?PvB{s#T>dt?wIXmG%=&JG7^MwsCvI) zZq<2dKnpG%I(|=W@1>Ya;14f!Y|(D3Kl*k;-O-DBPb`F}?v@^7Ge|?Y6Rj|6& zZ*o)9%}ux0uiM%8l0e-i-^`tQ{p{Vf`fW@)NZ&HAsculit@E4eL-l{!*<(kop6@S4 z4E^@h2DH`r_3OHptj?cR9L#T163m}dT(?^97i!X0??@U|TnFr&Vk7_jVt@Y3;(*pV ze`;|ke@by$ekQoOE?Tf%3H=U2D1^~>Bn`8!j2%h+itE-v=C4cYPFV79y(8%q%RjUu zsg>oQR+nVLf5_6NRqXe7?Dq}!i-W2m|C0TF%YMISzdz9LswVpV9s4EwX+xHN%znRQ zzu&Uo@7eDU_;r=(1)+kDDATbES{IC-w+j~5>a9`=)o&G8<;JVE@_yMrXOq!P^$0TCiN^glO4vnS*V~a+!m))6tUUGA9W7CryuN|JuRX zs#yS+!7pK7EQIQ?1L#FXwhgkbEn6;g!r7rtY1wj_9m=rmkeO^tm^T$+W6YH-!_G$w zmdk9_JR{5oS=W{=mpS1mBhgwevqJ^MH+nuwHd}G>?8uhOY&gp|H$fKB6u5(SWxgfL zWlpe`ESEXR7A==KP{nc??d9{Fe!sl^YioYlVGxyogSXQz?y;va4D%4j%+{Gbc+W*z zus}XWALz_IVHU)VBK{N-FE;au%3@8J8T9f)0RFtyJA{WPZ2y%NS5#CjgTZ2cK_VbY zKt%i7@vlp&Pg>xegms!LsFmYRWFlZ?b;G)BhMXZM#{)Xy8}+rP_BV zrlwChIcvHJrRmfry#_E7_PeX93&}1Et8&V?u4{T^)N!czPOydGYsb>_$%(1|^pmsx zKMSjW>pc@z)RbpkU*WEK?tdIAeFy41jU`0Gy7)Mc)D-VY-@BJrRFusxu9&{4th%_S zys9$1tA9zV{0QLV&=TH3zdy!l1IKE_Ef>Qcw@*uLU=;q2ReUFI*5;!(9-OMR-Xo*z za(k-XrS6`49*1f^+p>6LSHrX=3rjHZ5GxwkIaR%cxh=n50!BRC(nmQh%l17E&F2zkziobX)sjV;Flz2^j}-aw%8TZw zO?`hR{p8S3F8$=u&vg2s^!v}IpIP*CKK;;Z3jSjHDW#wJ^m7sY&^HDCMf8KE2i!#` zrhT1(s87PaX`!oq@%11pXUedyUm$f(!uL2duO0tE?{uMe@8ofxP*XKM-~2^5(|BHIO%V72BduY`H zzitHPn{fxt*uB1Lqm^#NxAk4Rz%c2z(liaTyWjAAcEyvH5wky{n4G?&>xn2VsX2~9 zEhd_+d_#>a-FJC$^#22}f1v9ruA1+2A~JK_@8H*X&3|*n2;9UQ^e@f0OU>BbM(d8g z*^NerPDT)x#O^|s-*p9SocU2ox45dj%ZVr@smg!B?%ZnY)@^a9>xr}r+hB&#IiZ~v z3!C-7KE*Kx|8XO;-6wC}x7Vp9V&Ngz|uG*rdx4ptV!$@y?`A%P^tml*{ZB)@- zsIXBbhfj|(e0qfNKUO~eQ(I|zGx2c|Cna%x+&(!2H zJENJntesvfHk$K$m3g#fMpHPY?z3?I8Xa0I*%vbgur5OJFtg!E8n^+b*+tlT^hYh8l4t*5?K6E zX+h5Il(=;`+4xs&fqCS}KSDD)`hvM3-1@G}{j0j;!z`HnN9v+TDizRrs)>LrCaV?w zTg}34&C77kO!oEGa@%4+w#;{#!hBcYzr%c292%o=)WKq<4(DgT^g|t_a9;k@0Sf2k z-;#dXjTO!-JatUMdHGXkBAk~$br!>tHUmxh>ZC(i1Q9g&WHLPLu3pQJ?Dgo6JrZZ4{CtyH->x zLl|fAl&O&tFWxsMkpa6iS)k$@0^+HeiFdk*p8=jKk{t0fK`9J5;x7Q5%s7iL#kFXv z-$CI!Dtsq}@2v1$6uzs% zpQ^p0No@d`2II@2l|r z6u!U04^a4l3O`8U2Wzcd=^3i{4`DWTob(M-_*8`-uJ9uiex$;WQuxsdKSt~0O5a$8 zAE)r+6@G%kPgMBR6@HS!r!fnVlz+B83p-&mczUSMOh*4v!ufQ@`)xa6af~;#8@NAB zC&&&N+0Y_K)0brQ7r)`Wg*VxI`sN&~4>IRk-#eM}tiui3VTC}O^F*y?W7!v@KG)Y> zV|}kLMbkba9-}goV>D$v1{%hr2{OJ9=lfdY71@>0;qPD}bYPF5>hXPT9R7;+?|7V=!dlkslTwl*I>n zF@*!A;h*SHP&MTDfcorVzz`}#FctOcVqYu>%)gWtensenLbcfzM!mrL0KP}&D-O2Zto1=lhCx< zH_iGc)(1J=8$QT0xt!)DBwxVg6mf)<==5RtpX`tS_}Cm zaJymMIX{u}DV)cLT0;rfgY#%4jK_V?!l!W__c7zsIgk5*@fn;)J7#<)=g}?$q_;n} z8;1B9KY;UypYaIPn#a%hL7YeYj33N-#LxI4obSzfB$kCo{LCK<0>(@6GdbdA6!9^N zco>C#MxmEc=wlRm(44{?jYA{{rOP;tESBX@uDNvVnbV`PSmvx;?L}SB%$|A2(1;nS zPaS3%QnM_nrCO%cQY~9*sg^OdRLh!Ls+E#d%br^5Shpc7@iy_Jmclre9kX4cDqbv$!{qK|@Nu+tW~W(s)a^76k!D9i1;Y0sSGa69lUtO!jh_r!NnEj#f!DUj@`2V zMTX9(f2BX_hslZk8jExK!cm*+k zXpgyr>b{0Rq?P=-q2SpXNCB$2zX$o6rv=`<%IAsYP=U>fe}r-Uja8L3Vpq>QA=%Cb!xny0@phVeH}xX!>h``tNMNg zoL4!kcKZ$jM}3EI;#N^{U7;*ZfIuVRW=Dy;9k^)XJshRJo+<8rC{p@v1}>U>Gy><9 zzHYj^J$J+!1JmpH6tJFe z&Eay|3!wRwc*aQLDTtKjLmBu(Jj@00d#i$*1001X9Ql(Y`XF$KW)&0QXAy9+ev%Vz zucB`ya3m*vm?|*mg8;V`9$s86>4hABlvoNWIM zQ;LW<+5Q`*3O4S~O8Gs8^oe?lZw5#9+Nj-AIb+Jm9OYNlmw=ls4RXS@!XG&=T%Lr( z)RH+b+zr5qc$1pJHAwneH-qzI59%fOQ~KI8gF6J=430}~1~(ATE=2k;rDcxt@vc(N zrNFf|taxc^PL6P2D7cyt&ix^tv3udxO1RUQHgA0!C0wW(+%^foW;7_uYc4of%;u{JISWh(a*MNjQ3zL(WUzy%H{sp)A~Bl%FY$ zTMq&!+A)VQk_H@&iyXy=S`lqZ^*8VzMGFW?Cz^;+xOO=zi)%D>gbxi z8}3=RGqElyFlQ_5Zhcj}dqA(M-L*Z6^?tsYyL|O)8e;0Y-CY~=#Wg(>i|e}iNG zV(Zt`jat35qo&WS)Aj|@XYSQfwj6Gt*y~5>Gq-E|E;|_5yZ&&uJy-3n-E&Pq+cxO& z2gs`2v_1H+{?Bb{kdNmOWSPxrXw%eNf8MlszaL=(oydJIZDg zE0MZx8cJjH&dw;KO{}y~CJ)3tpU{YML0WEa&|loRcjtNgYU|fM)n|8N?&`Xv*f~3D z`xVDEZfw}MZa2#1>*9NAQ&1YgM&HcczU>VgV|H}Adjpk6QgO$mOR=oivOFRr>-8A+wapCmB^t_^J zXHV4((|F3-spWAUdj6@k9hbbH>540Xq9|OksH~_)Gki~r^sv|g{E~gT+D?9dTa6#SoSzvC}!i6v=r0I#i zqxNV0#igayWs4VUy3xZ(^nGs2ON(oYmklGaKhgJvTbxSbK%(zUA;y7UPAVGBpL|i* z>9NhORIp|+6%iHBw_3tiBC%{8$}=#f^qtB5r)A{1g2se|M!6NFToio!&X@W>>uxkc zfz@aRJBdoVCpF(UF)hudS*IzOt-Texb4=4kVb(5A9kPA<*YCPR&?IZMNKY#th53gQ zX26X0mEV;0yVDgW_)h>5b>9HpoUx=PW68XEFsq=q_YKrVYJHIBR20u=mC)WdNEhWw z9_Lh-*OcW}mXB)btwGh>onIgY1$o>%r+OUjl|jr)AVbx}NW zJ(i4|xAk+)ywY8dLTww;E4PsQ9-h2rgi-gXE54YJ&?0NTX&`l?kK3(L}r?eF-mwsJjL}`RpHci`G(`f$9 zusC}kqo=H97^Wt9fldzz$fZc?Nz8Bo`>_T?;CHh`;$usjXG_t<% zpi7>UH<{$YMBkrX^8A9CS^3$_FD}vd7nfh=^s}cGX6NToz=TBKU%fo1kY{3|?h&G$U57=O778hbkcD7M3_*z&V8XYyiuS7eSA8+k~@_O~!kso36g zdFD;eOwW@`?S0|xDz#7Fxb|;9`{Ln$xDv-oEx&B;Qn}PV5c!ZxZRXrRJo)*p&s^>< zHK8=D)aE{W@z!at?(61?EhZ$iu&+3HshRzUr#||NyH0aKW9MinR^4}mm0HI1>4ofG zPxO5xGRI1dJf=?1%BJ>$#`X{4=^FI><9_qgSMo1<%oPF4c}7)LP0@@c3m4ff=3|i> zIq%>8^O;Y3yq0>3JMThmSl(wn_i)D8*3b5H#TOG2TG-pOJn!wE*-$(GSDo&1L4)*q zafoJ8R>`|t4_{|pjG`?!??H&R;(K=|8y;F(DC9&eRX*pSo=8r#F|oGbI#QnWFts-dfwt+V=8at{Su4 zr8%($L*MqwCNVlg-wr;^2ytI0DXUl4R`lFB?JIXuS~m3UXm82Tw}Z6P(UPHWCrEj- zhQ1w~t(pahXz1GxkRTiS_NNQm!5VEk^GXudyj&%d;28Qg(}f9fxzUIeFM%n1HT+y)F2!vg9PQ$jJ}(%S2j#Z<{9*Vg`D zS?3iNgfgoZt*9=azn~`6cW%GXu(4xD4N4t4Y)q)IY^enL@7FG`qN*i}P z#~->)yW;O89ET>N9I2d_R92VGFJFvfIPCF-a?P?G(7%raIYtAsHT1XB^_99l8w@>x z)5Ie+U7rCFk||kto+m)!X`EySRg7))W>ugI%N4yXaNK4u6k`_tPQupXLpf5@Sd2{< z{=}rPiaj%7#Z0*l=-IlMI!1sV(?)c;u3u`k7^M--UbuL^l~nOiMc2=w=ZUoMl5Ksj zClapf7Xqz`CtkX-c11}=)!d71W8r?iV43rzORW3+dRV*k>rTAl5szP=rNk>{;IK_j z@rtK~e!b9&*6}~9+J1uO#F}4SRwE^C#ysqwFShR%Gm}-$UygSVN^9nm@E)KSjYPxF zm640!bh9^>s7QR$Ga2HDg$Z7~~HzWwE=|Q_K z@NDm8R-9se?hlL8Y0R@kln%Ir#pv+)EJBB$Avbk%5EVT8^y#?v?i~^7N!YT<%m6i8 z@0kH*I-tMq4LGK)`wKGGf1w!hBTox(3oM#vA50>)aXlNU3>3S-(iDO(s!yRTTQ9E1 z9`6}M`pMbG68H>)hA}>a$f>Sc=*%G~-vNECYYyQFKBi6X5uJKens@%FvxsHtEMku5 zEMkVI^go_kusMx0w_Xt# zOYG6T4U46V8JH6(2 z5;pdAys)Kv6wk~HfBekvksiYgXU>Y8!xfd37I*R+M%`ve~$6}rsHgheE~}Y-ow6}C8Gwv zbYQ}9N{0Pd;QtbU5{O|B2VUV-aN6-{38D&))!irz4h`ll%|3PHd$RdI-qd}U3LvW#F#NF=MBi z@xGcRW-JcwFk3ClFwM)%*vpJy5*RwM#dp4up!;<*_F~4(Os8wZ91TwQotdUDnTx9}H0y=r}WW{t#-(#in_K8GEJ? zi{o7eprt0Z^{vV-!BH<4Wm^sP5jl%rAE!gCJhJ$6y`5>EY3gU2=5X=bi(OBo-`F!J z{f^HKb*y4>id)xvqQ1pBGm&#r^ zT8rEHosZmQxa(n9l=-6-j>w;GYPlgS^1_amVQ0x$XT;C}GjyViUp`*O9Lx@bVF*(o z#E~!Zc{A4eDdMyl>!6w+ANMbx#zI-TCM|evnz=45o}D`5S5A6~aD2+Y8WRp`p-eX) zmwjZ;zp5Q4-`LvYBjw~j(H?ec&Ht4WJ|t}E93-_Z*)@Q{t8IKdyXE}s(z-EVM4*-C z3#P`8>1f?igz&pWERbo5985qGFhop}Hk@4q+dBG97=w`5co^fQ2MY1_c|In^mteC@ zL96cC5Flac%NLA~KOL7z)+s-&`$Ez+UZlLuNOty5vUT=PTXFVJyZ?@}f8-97y-0(6 z)6`rz8kB_d@~1&YI4^%1EQIs&r@=rtFMsOPh4b>K&RV$BaKY9k%sl!e%!O!^%6@~7 zVDuQ$g3xPw0ut$!vgiUx?>->_ZADr!(2G!$c_Jdc#6vIgT4;LlMW7?Rw2@+i=?wuH zEN@BowNY~FQiDhR1Q5wh@IOpOlP+>cV_*vk`lP4VUMW7QHXYuoJP2bs& zGjOiSLQpDma>UbyA2kAU#M7t7!qK@pR|*EyXBgTh7w^;RUA$j=+{K&Pt1dpEedXd~ z@JYHO@EJjk&fgWzhy3Ka_&BY|#m8%xy7*QKpQ!Lj3g24c+bDdp!nalUb_#!r!narW z4%#)Y^mbJEP72>y;kzh&SA{=S;kzmPX$l`w`0fgyqVPSmT37meDts@6@2&8C6uz&* z_fz=(+MTZW253Kb@d=9mK!qQq@Pie8h{6w5_+bj4s_?@VeuTo0)E;rAceLU^irMOO z+WQ!VAFJ@=6n?zIPf+-Y3V*tG(3PG^3ZJI%=?b5r@R+)_R=eG+q!TwL}G;rkw5OT75amF(Na6L9Jr5&LMgaem=bK z@)l7P#Fa!bs4#hF&UfJy1<(9X#gjY2VK6Btib0E=$AbZj$xr8U3|<+C%-7Dci%A0- z^Pj~1Q83IO30?=B?VrZ|u?fNaVQ|vrpU(X;38OKK(tio3r4%1{`f!Ela1;(vI_8il zYXc%3C}@^`Gzg{#`Dc1S*||ZW^GOfr4-_8MPlYJLXY%kvczBc>3lBP*!hz1=^dN-? z{|cxbK8uIP!#);2%A17;EunCr^Ef@1!h^q%Q`S~RIlgvkq3YrZL(R!tQ0wL~GOdy3?{xco6Le}c9{ zAwAb~`A@j~K`!6N<@>q(4KDvDmw(RXiByl!6Cw)zJ&8hp8kgsD`Ajaa;qq&^d_9-X zL#IJ{mJ@}Zl|-Ru2bVw0<&SguU%32zED-*b6VjHRb7QRw-M zDD;~_OCC!U^5H}w&*t)6E-&Ho8ZKYXCLm8E|PQOH*i zrSx<816=+Pmp{klZ*lp%T&^ctdfF0&o(@Ezr!SX}e`w-_PaGa`~HF{wbG#!R2jQTk-ZFit_106zR$3^7Fa8h|5=T`A@lg6PNGe^2fOR z2`)dx<^SOFPr2M|W5wHnDB|rx6!DJc@?0*T%H>sDekGS*&E?y<{5M?wD3|}0%Rk`q zkGR}Ow&HC^6!CT>ig<@{c_x=n=JGjQUd`o8x%?(B-^%6NxO^{{|CP&M94=qU%=qz~$9RoyQ}d-*Hh(ET#`oYn;$wVI&Lcj?_u@R_ zV|;JUBR`r=Z4DxfE;Onsw==K!*ZjLm3qfhqpc$M4j9j-8JfZ5E+`sLVZz#{NFCNcnPK z@+en|JR9!f0hu2b-rpQFMDg67}|9er7!sK_wHG3 z{eR!~YVg%5jwCBBD_JrhH8ihETw6zzS@L<+#S6=XM{!9>b=gwE;bU}hSzKLQIp0yX zXh}&Wf{`hO!rY>gCFK>RMa4BW)#W8iY6yih(Q1lItkcjuIskS`nsw|Ns?_u5b`D(w z!lM>S9P_+)?oBY?L!@UZLPLfBKtXQD zoJw_Ms!Ybchdn5^$E5&O+=rM8kuf{fskn16Ct`bA3Q)zpfrb$cZa(HrVt-Rssp{K~ zIThQ(l0mpuarG&Duc`&y8qB%aUQ`RX_b?Y@drmFjj`rt!OD*8u8pQXI6kI2z-Y!Dp zyH>#vtK$9%+?7$_s)t2~`z%UaO)6dw@Mte;`c@6sv}sY`oG4$ z6z@c#Zz7i6-yC)O-eBz@S9Vot?X05>BF++)DaiUQXT zYooL%aD~7{qwikeqRGe62=S&W6}LM|+>24-z6I_g5t&5Q zc*`bY&s*{rmn!bbC~@8KY$BR?uLmxgct3~|HyO`7W{bp2RL#ddzou|9|jkkd7A(e-?RB`?c z>=g-5iK@7fQR3zSH(1gmE>(RSfx{3N=2YD8fx~u3m{W1@0Y`f}s#9@oF>$0hrs`B& z25`~Dy8yTWsxt5wp+0=ld3qaw!w?tdRs&~9(x-u2jY;il$j;~T)}S;;isd|!DQ8&i z9>fkG#PwDMw*Y{SkQ2_tA34JPLBXvCfZ`#Xm{Sw(9R+tY03;_|4F1Rw|Gk2{RnkZP zDo4UY<#^TJJ#aM;R^h?_0psJ)W&(zg=0De$9su~p8T7p?)g zH24w@TiVQd;rw|HPAsRqa9O~Kc-u9j?*>U9UJr;E?*R#iC0ayW!c-@H*uJ)LyOes% z18xj%T*_~PgnLxMtu1u=18hGtNBLE88zmf;N)d6}B%J71z4SdO;jpBNsINi7^=$@s zP{Q?V26tG(^_Or5lyW&L;V^|~j`E@6{AWAmhsO{RaqT1=rsffGJtZ8b$PsZPBpjxo z5ph`(4pYmBxIzhssi2Lc=k{_xSqdDL1GOtm@t7lC#Z^eSGz-SUskj;mm);C+rG(39 z2DetiVTfhUD}6UexU6Py8zo$JGq~F&Tuw8%Z4z#BGq`&t+!P7-8R`S$yFI==2wZ3G zFB3A@ivO%nCi%0#eSxsD)4|YQhKy^#BCi7pBuBV~b4wO4l1>_I>72n)V}_-Ui1M7l zwJ%$diE{==>!bAg^;r#v)0-;l0tat7bVWd`U-K@w*H+@>ymj^KGdI-LYWaaVv5gxK zoVGf)(X0xxt6*dOI^WEl!Mgq1_ix-RW8>z02c+Zs9ej_vBu62sU!(Wi+v}P88@kc; zM~G48pQ&wN7?NAp=QVAw-M-<;CZuWg_S*UbpET8fSU)J#q#1QdNprSu2o)qP*l|GD z>eub4t^3&zxBF(+>vbE=+kI6`x*BK7wQ3z(zh2)muc_hIfc9hPOZ<`biS%9A)bPZQ zn?g(D;}6iegMlCFuSsa!c2)L(+5_L=e7<+~*KU5N_N}HHw1mdm15MxGy*{DwL&$=M z8ag(u`mlE4oF`ZBs14=&%Cr0GTGoKf0T~0*2WX8uYPS|%QvTxljTdaJeX^;3-S(^j z3o~oG;RHo+&wSsMQ0&i-D-PrbixZx&Kk$QZ%QLHfxVkB(ig8I>p1HGWO;f`2JNIwd zoPI?nGzY8d64Te!CHaf9`x@HNs)pLF8|yFVQYTdTe@$b?6c#c-yEa~clOhd5=r28q{CzPmyY`wN z#Mz1UYaV|fxpC8hrZ1Bl5AWZ!xxTL!JY3jmP8`WTj%z$($yy&NOq$bB+ltAxPvV|G zxIez}j?ITQY^sfK+&N~`X43IxQ*z@`;1ATAbAqq!?d;e5RiGWeZDMCe_p5%`87 zg3kvV?>z8cQ|*4bx@B`LxbK>R&)4q1bMp&K`>H0=zFLcGeDA<>z+Lsjdz-EEE$tkC zpWJxR%AIkraPXWX>sX%Oh78C|;_d8z-?9kmalHw^vo*oJApn@Yvd=-q1^re z$#;-6)CT5kZ-{$+A97??u`8rE9tf=|zVQGMg#MnFja(A@*X`)GYXI)|)^&Y$qegMn zad%SgoR1GQy;ryYTSvbx3)j68jXnOSbUA zIHWy}O5kJfT>M?ig>{XVL9L=uM{d8wl|JLk&2nC--)PlXf6cb5T0Kua#}7@d&~t3r z{NV=bGg_g(sTa}nSIzm9N~)l|nOovA-c(G|GdW}92dW}}DUW0MG*Jvg68iRSS z(Vz7i13i0-mNZ4vTWtIHdy8-F-ok%4ik{(H)Ft&KPS4=0`n;p)7tp4z-_h;&VZFlh zyjS>u)$Et3gFn{B6@Q7l>*ZRV^%wuNe9#jF8^7NFC9CD1?vHK!ax?CsJAb-AuJL1B zJ=gS8-2WeMrhCu6`+rDoJcJaXztayD_Ly@xs=NPituH@@-TmTzR_}AsD^Ofn4fX4t z83@fj7GtVn?alk&+5YX$_9Gvw2tmY_s5DQ~(fg6bfot?uQ!_IPW)x-5!og_MaFT1` ztfEXD_;qGc!Su89GclJm^=tKb3zSRe(RqSk<%G6`XiCnbJ+k7PPYyo6YFr2+JKC73 zb1AaI<(Xvbx1efC_1rSeFs{=@BIShdANQDlXXW5~TpD=7joPq;=Z7WS*btWRFc8kM z-RMqu`zgHaChSq^Y&a7T9z#{TlrRrR~$m%1W% za-cSzPP#}fdyAge!F?GATTi^=>g!xe^cs!T!9yZxNd1iIdFlDNh36LK=N9Bnn_QHg zHJKW{@f$BpPI_LR4MNI)isiRwEBm2kw`h= zn_jBj{YAxDFSvAwg#SS#3Ju3jxGPae`IBBCId^DYd)*12@zjXdzv%th<*rEGZC*w9`iQb?MMo1Atb4kw_Ct-0o^}@XlR!QNg*>aL%UaY>bP=Jqx7W z-*_N{rm+y2$Z!&{?~;;9or;rgawWhn{TzC$s9;6qT)Wq)(nXTB<&Kv7i=MvwnyxD! zbZOBq0|41bk+R{HICg|0s-Q+@~SI}@hgoafS}UkU(n@-rzXQt8@_YD(^8tmjSR&K7Wa)6daR z6|~Qv+_q&W$re0-b1H#NH1#ml`8@EjbUfRZc~@*BFS=1)O~Q{B@1u7X|_v? zsEJ)tHkzx6-7Vm#CXj)9-8Io~=*xe+@XTNR-4%6s2Bez!xh|5+-b@nx>4!_&cgX&% ztxJz_y~Y~TPZO>Afi-ckuGyiPXh5|IvR}cB+#>QRnl`;CD?2a!Ty`65@WyaJM-0*I z<0)~Q{Oa4wb}W13lkKjw1g)usHL<9vS~Rt)l%^J&@8b#Ao<&-DW)^i`ntWaRCy%-m z7|&aod6j1-Be$@iXhwE^(K*xevx=~}Y8r<;y@sV~A=7xx+i#SXW*V=1`lSxl=9tDC z-hLyr)u!>Lr{C~YZL4X#Wo>No9F6__x94rVb!|sij(Cw|!JvFbdClS(W!2|YRhObr z-WCNQpAI+l;hER&={fI4+LpE_Y;A<%IMS@`z#otCiid{|>#@u*Np8c9UEt8We8>}y zgJ@@@Ps^eqbK3N2Y+OC!?S+X$Mo~^~enBC1Cm)4_&MwMJKc}bw=Psk){3P5z-S$U& z`KN0t`c&qOl3tm2ZE_`5w3n)di;62t%PZ%z2IDh66&YjS-}B7+KK!iy(wJW_c4;uK zurm8CPYiYbR--OL+bJ4KE#^CKzhN}R``+6xRl~&M2Uml?{MGe;-+xI}y(@aDcC*SV zidRq-qi&l-TD9LGc|84R#=rFR?yokwheqQOEB(LY>7W6(AfFG#v<}G6PS3&(Y8p>? zB5(|I(e#|63|cKvrTpF#<#cIum;AvK!=?b)`T5iH@d2CB;F{0+k~$5aRy}d5SKbSk z+iz~$J@7t}SM8@x{=Z*cnSRl4jwHI2P_IIb^-7+md<=PoMQ5B{P?(!@F4|&VUeS5k z`O~QYuHqe(2c#f(@-*yUo5os>$;-|O*Mi27W*XOMTBehzZy&uYebrA6%ycD+*J}Rq zg7W#5*~@FnDi@bmRr1bkoydnqRmbc0?Q1FqBt81kXD&6y;{YIUcZ$5Z>b4*|KNm|q z>ewiETRlN)_1@))a#!!&o)~xaZgW-d2Wj7RexS?98(gWk3n9FE>qK_7{Z0|I{r%sI zesi^Nj!TLDj8z2Zi*XZkcec8nl0I!(c3weI_O$ejylhqivjqmNKGX6?SCf~WS(rP0 znhnG~d!YbYfs3Z57o3@$C8>3S(QRBL;05PSotm9rn43vUK15wDRCyHd*#cuVv)(CTYBwsehOp4^oMwzrozQd_mrbqG}LG#Rv zNWLRA(=;+8`Hs>8rjZrNceEB`8rjG;J+tLyv-h(VQ-<`aToced$ed5J}B^aHQv<4=9Gmf zbR*2J##_4B{IL*hqsv~KKue&D@wP6uSsYBhjEU)D9M;8-hGl|@m)f%S*Y!Hzyi;?P z8gEK$;ehs3ypU#5f73+?%awFE`L*X3we8Z;T}eW#RY~-g2#@ZWPrm6tX7Ek!sf!sB zT4c>bnzl{6x z>&GFtW}(2+{E^dW9(*;BzMD zp=$kZgjI9a{g0|O4Y66m>&|sknx`27Lu^L4>TcYw>${cidEC9>X^)=nx{EPH@yI2- z=)mN+f}{JN>n>rTH>~c?Y=7#!wZDG*X;%rGA)!UqysS-H`}og)v&pSlD6lls;{$%f z-*V+;)9<_Mv=W!*z%2m8>qcwCUr|-HsHAxA#WZ;nH)R{AVrrIEv4O(zW_M+>gIH8v z$<}(-VTzUt^v!WbTM0vB%`i6D?l|wXmro!-!JJsl7h~=Vd{rsEj|Ng?_4Yd)TMbZ9<-SKxdL?z1Y z;Kr}_c27TJ*a&w!5Ng9(*riEN^m!ux(XOs`V1|SiS@WKz>Web-e$mOTStzhH-{`b3 z|8?ihxw8KCi(HxmH(M>Nmv;;6?X-;uEv%1&uqsw*8tC}@I!(i~^`L?Eb0A@@$KT25 z-+b#ayBGtUwqeELZarvU106(o>xt=X3~HwJ1Ungnoz}D1T3(B`6MLF5#1IQ|&!#oh z5KC28)0+R{XTz?)@sR>oh1k89t7#20MD589;DHDKyyA}9?N_=RfKVIOv{LUbee>Lz z-@fdM&kPAIvgT>auRM6s$BECmH46on=6cQUys}Pv@5s*Jgm+z<1NQ=efhX7S^JQCR z)so5@8qX7rGn@)vR8!5@Ig9gf<}sf$CK+cMSN-h&vG*nLSrq60d%T+y2qfGhydo-~ z0y($@H6fe|h!7Exnu7#L4GAUzxdapx6ct3OcvP_>649#lthW}g3axF?YODTiYg@Hy zt;N<_HUIB3^X%^IWb^o4W$o~~|DrQ1!R3;dSl-u?uhxV5|YrF}1*G5)DQ z`uT*wLzgL~v=KR(;VYeK6y|ekVV6nN@n^efp#%x%zXTZlF1)_E0 zt`*htnO$aY%enRG`9aIB0crULlsAv1KDpqOxeFd1^<=0{ z>)XwhH^vR;hL*Q|m{p~ew=#MAlcR2^nEsEm#{`n+m-mdS(j^sv;;y#b9I1u!dH-LY z_WCg$?+O-*YrIKu-#6lkcklc52f?{sC+=ENEkFCiZY%z=cH{9u%dP=w`AEOGf8TfQ zLwEK6$sYsx$yicTS#B6d`Ls^6cD(-TMI)95XsKm2HB}g8iZ9-{`W{;R+NKB2m~%&v zNLSs8@;ELfm~%)HU*<92y?qJt7i0EY36Ubco#hZ~)@-Tjw{_}g!4T(@?c#a^>ysXB zc#Y}KE{)5x@0#{NkXyH)rWUupj`#wPtrk7DZ{)A1-ZD4H^wPmWlEuaz9OSxBH`>R} zzURzf5DZVr^znWo$}=D6(Wm6MUj})eX%Qe0)jT$+AMDBfDFq{{vORT`PEY_dq*xU8W+P!H>)8@c(SK8Q;iFfb*$&5~?1`?85RZ~45Q|fA)xvjLrTO-~p3=RTP zy#kdX0wp^27f1I#b^n!b1Wa>@=H`eJEp)A_CF*wL!EjWfB2<^yc-OL8qVCR{flyA| zHKvxRyJu#wh+G3rO4QxAFi3X|OZq^=YyNr5)63^pJ{}ykh!Ty9LW()!V^D4g?{s;5 z&#_|%rv{Q8ELIMdte#`LFCH`P`Hyxj3I>~3Ra1(yF{YNwr3;@~lD*}!p+RPO&0<>N zDHc<^krOxlcF(hKeDL=ml@cBI`GX8ErxCl66a70Xvz4|dl3$|CMbhv^Y%9evcW&L_ z=@nHKxSKB?S1@LhQ8X!DG-XC^&XB^KAw!15C*;Np2NxcDY`hQ`{`nQv@iVF`m&TXm zySe({x1g?Vvjtt_wV=8ROx{rEGox~Og*Z=&>uzLQ z5i^vA`+O9epO-0bxVe+i=$bB|J8OFNO$P8=nBGTCqZTMh?z32GhKg191-Y1cdeErX zEW3yTyY}EW%kFKnS<>naUbCAXY?hQ|)BIzYcPqC_=fA8~c0frv-9*!zcJP~KQrm2r zGrXo*TQRqya!G|ZYMWY9E#5|P2X0gVrum3$sENp}+-#o>z3y^?sK+bT$eTsSzfKHjmYsMUNNdiB&W{?|VLO>^9~-ahf|yw*NV^8%h1k?qrGv~v4= zI{Y5gZ)g9x?enIC-+$6$vNqU%-s1J2<#KzJUUWS-(6WVQ2V1C5Y2_BW_`k6al`V8GZfp+nv$O4}uQu3+&O=Gc5hiv8 znpZi0aV=g>Uy=in9GDRUQ8^ZR}7d!{k7 zsIt1eVyQBIY@(Q@4OeFeO}Q_!;yJE1KDE}Z_C_29P5f4Qeq);WUEui@%%jiK+=7ka zVY25nM)z8Q7yfH%@oun3$FpcLWOhFijOhv|{PtljDzq6d`YJr>X8atIiG!htwhf+U z{=|WDnu(`vGw>OhC~V5PY5sxl_d;o{d}1AGn=8XlEcGiS_sgx2IVhYrD%1V)%gGZN zTzT*ZzGK^FYg+9Me3fQGk1)p9)Goy9X5=XAra9kk(p4+GR&Gy^+UC;m_C#rzCO=4Y zKlP!ze|oLPeM=^0&O&oii0+p{+-(IP#AhM5p&tF%6wcJf8G z*Bt!zH3t#5!S=PbY5T%A9NsqtqO>XNSiK-g>)!&rR&HrClA7z^0;zDnISB9J0#x^- zh0v~S5_0T&D6fNHi5?^AY*8xf4t^V)hltx?8(bgS2L11dL~&EzP4iZ+74Kqwc@`H#g;_xM|3=@1eBAnea%GFU=i-8+7`1stvZokQ?;r zO>fXC^QQTBb2sQ(h*oZqH#iY)(A_T){|z_j?x&9bDL3f&dh~1Fp!;)wtNfEpf3&iR zPP6Orb4YH`>9d+Pc$$UWpif^Kyg{d&o940l9hFLJfAwQLWDf3d{Kt&W z_{Fv|Mq_&t_{y3b3Df*1eq+XK__g4%EJ$e8e2V8wts27u1{dtGeq{UOg+c`D)sIp%R=t25xHN2U&?*wgPnW7YV1u` zd&envQcqZ(WTiJrS@%PjviD4+tlmj2{Bx3(ij*~aEvC(%F!m#6d(mjV>~u-Yv@fr| zM4mJ@x(@%O8GW!T=V103_C79xUpkZQtJ^(|V%S-Iu{?YHmeA(=4*Lo&hO08qK@ohm z@ElnL!IsdbyH9&N7s0xubL`L4??y3fspev62=t>p5B3S6^rP3r&|95huQ(>#UUJO% zm+XXzrAxzqPRZVvxMV4@zYTQa=N;@e zdr&*^>r>=)?7bB1h!`^+)4ulnRgSYhX4!A2tiqZ60Jh9AfnH0tY}0;Z1^qr3TP2SW zAk}VM37yma6Q`3E%Yd|3!+?FpDw3UkV8ya7wwJB4?9NUX%g)3_)3l#V2IEtld&#}+ z^Q~lxw}<`oQtTm!FdsWzF2>ruv7YuavfIUSju3%1Q=oNPppS!r91hgUzHK!ka@yM; z8h=K*?2NyBYOg>{&f)fIj8^DmA0MdY>^5D?e{^ImKbc;GDt)=$N}?+LFy&{W0=J(p zFe>fSBpg}JadzoR-?FcCM3b;Tt&{ZiNeE2!y==P}`rMFoQWDlTGtH_%NtU$fl6*G_ zeVyfWMe*IcYM&^NSIm8)Jocxds?OzxabpLW$*6*_Io7naju>CV@pB!gT3zYYuHeKFt$7IW0-@cMcRyIX+A&;d# z>o{YrY{cMNG| z(SC2)Hv7(YKvryn{qE9j_IH!E+5a@Q*>|jf(tb52j&O;1;(~4VGuAeA`}VSJH`_Z_ zqc1-IvCaOojR@?kR?-ptFSjp*veDQkV*lQ9H}{mWJ8lF&z? z(|IINVbj}mh3!Ze71jwAwzAl9=Ay!WzTB;_M^Kfraz0viuc)qVN%x9Ye&Ob7$X>k>r|Ov-Np^Z1m1;Rz{y^)479j^DV81V@IZ~X?cvs)NwUUo6vM5*(s0X3 z{iUe#hmvaC@ztF?zPg%+V=p=KLiXr#Ilg)@hVfMlUEQ|>MR#$VK3Vo8i>{8wSFcTkxqFCQ-cM8h%2XzmM z9^j>vHI6glwf?7zPUpV!KMdZmm?IXR^;Wdc2Sb6pA!vQ}Mh6hNxsorvM->2Fy0t`Wm`Z6>^( zAUv(+=Q=v3_{XFbrWfK^%|lWG8)_NQGx)GPeA6cYzZn}#>7=FfpV#Ob>2ILKO!b0BNgdb1$wf=jJ}td$$>f~;lMwyc#1XH|LAy6FL8JgmoRg{HUh0Hfz-wvZnTRQPV_kvw3N%YnrBS+UF$dx79wEUSx64 zd9#yYr*!O=m3~;tQ7Ieq)8U29Fs$x&%A`160O@3sZznU;R2cRk)6B9{NINq9g!EDA zC-P{?lwbUb>xDOm}PA{_iU9|Fsjt z(9fOLY=i&BwkO58M``x#q5kJG>Qj=wQU7v?%jkc(P_82p>f+y5UjJ)h|I#%+Lfw4r zYrNCaxqc8V$1tQxPZz@(+*V^c--8$u+3hh%%1Iy5UHa3=C?-|D!pSgl)5#|(%MS}v z$z2iFr=@sMkW>4?H$D9%M3Q#2F$t?fr1yuWm*b|SodQ8>FQAvs4hn>C#wdg}jE)6n z$8JYqHTh0!F!Z7{83%2{AsU0r_l)VzS~?`jb7B58kKwv7f10OoU6{W*ClTgPa}2Hv z^KU7AeohP{EPPA$`@4}thJ|m*pYG9J7Z$!H|LtyI$guG8qZ3IA^QU`X*M<4hJ*?}( z{O7oykYWCGkLkKFf4Wz6U6?=J>$xt>pYGvY7v@j*Wv&bJZ>fIie#&*UyPs_TCqqoa z)S&#jB=Me6ekj^(scES2)tis@;-U?9{7}IaXDDSpllD9bFqO~ZiAne9puo`r?>;lp zeh9?Q#=i_li+DF5Zj8EBRtu4Nxz^V~Zy_=-Tp%(!%VY{^;axw4`hvxjo5WoI<7eX1 z*(dGNa+JQ^ChK@cAO|fE@hsCS1-@l(`G$}M@Ms%LnVMidC}Dyh3)7x_G5~#58ybo7 zoo6r)v`|rK2>%N{-~5_za$s2zGC$Z$5UmjsVm`QN1qErbptNNLC`^k5rG73=0sNda zQ&3Glob_8qGX>>-$4KUBO=#p7j=ui$v#ouWMg*TqUw&y+|C1!57SPu|MUxDZuAxpr zU0uaO?A=&vq;yM5ZfA9Ya&FFurKM$+hM5WwGn3F`=}uL}tiRwPj+<0Sd^JLATDcs{ zvJIN(!DvJ{3r}+C%h?PC9~Hok*k02QpDg+kAEz4Be^WllSyq~HA|%-)N0^>H#0kI= zJ_XX}ryHjO`}}lc7H}N@3PiYru^Gp532=$81*SZZBY)aEd6Ga9--csa%Y+>H(^l_i3MBD; zI6hm!kKnjU!B6A3R>3dec$tEKisK6v{3?zwQSh5M-k{)jaD0V=|Ab>&>wz4l?-R&v z0!jQ29Lr@OBsNSrS56eXHeny|?_^8??kMTtXBtJoJrsO4@L>ur1Ew}c zj`)><@L9&9K=>@<{6P3DV-;|j436+w#>K!#c(}81Ik2DK&c@ZiV-)}EfhQ{X7U0tq zybE}yg6{^NuiyuPsm+tKtj@;cz|`i+5#9s5QbK`W0=`heKL=i`;Malu_S4yT8~8HC z|Bt{|E0|uA`i_D>1@7tLF2)zYe*U`{wk5CFM6uARr2$iKMh-6l8J&Rr{-~?b9ry_8 zE&Tfg!gn){2BzMgoMm-0=&MlISyp$0b^>*sW%V%5RIrV22)`A;mO-n8xeo7+84Up( zGkz4nj`3yyCmFmuiZEg0U5$Yl4YIT zFxo3OKsL_LK>^&+m=?gDjD-Q5X>1DMEaL|O+}U_FfV&uf58$pw59J2YMtuwm;O@rh z0o=o=3gE*u+)KlUYq+;UhHMSHnkYxSxiP((ut5K1Rd+H9SDW12ufChL6+m z@fsea;lUanqTy@}=V&RtCu?|$u`W1OvB4H zyh6h(HGF}FR~dH(>SK-OzuI^x;D4cpFVgT@4X@Mi#Tvdu!|OG?LBp47_%aP|)bQmR zzCy!SYIu`|H*5GR4R6u#)f(Qa;qPep8Vz5o;cdoqf%3mj!`Ey01`Xe+;qPkrCJo=L z;q4l}MZ@3I@U0r&q2b#!yi>!sYj~H28#H`}hIecDP7U9s;qPnsZVlgKyvpTI^Qf5^ zpMA)9p1@f~T9O>CrU+~q0~wDMxT7(iaesl+jX8{O5V*6koN$NHlkue)M>8f}CdTuV0=TM&zQ2AiShjH zjAwn1lOAMoi z{E^Q(met@9u4Q>5?$HPr(!H7+9uqIZ?s^W7@)6-7MR-UN9&$8=hZOgcZumzz{00t> zauwkrX-!##^EpJ@TdH0B0QvsA5z2*DdL9=#Q!vhzmmhFy^8RV<&lU7F580?WKzkMA3dJd2NS%ilabGx_&%^DXp*{&ik1j*#uO3l%gq^jlU(fmnSpPihUt;~hnB>EuVMW<*8iFHcsW_{X-|9N z4<(6sC$Roh*5AweAF=*<);F@gQXb0PFw2`p;PZ1?zWokaiv<2|JIF zgq`z`u%bD5I=8cC$*4U#{@bB-*jKa3>weMmz8ZPu@3 z{TkNa$@(W){|xJY&H4{n{}LTqQNfP#tAqo4Zvwkk?=d*qd>$kA}8rJV-{o|~E zn)Sb8{Rgc7nDy^>mGOQ-67d?{WW2|bM7ftAC1PISy<|6!7_{}@T+_g&V1&ib!d->rw_4&LSG*R21L^?zY~zdn*bjO0zY zK9Pi-8LY2heI@Hxv3@h_x3c~&)<4PmAF+ORT-vW93Hysk!v3wSe}MHrWc|-s{|@Wl zW&M||&p1Nb$s!3m$C0G=$@(#@|A6&hvEJ${`FSM4A5RkLIfeCeS-+U|%UFLU>$kIh z2kRea{ZCo{3)as$QrfR33H!AqDZi|Lfb~CQ{m)td4(s1#{g?!V3D!Tu`nOpBG3yVoKJ6$OZ!eO_SDYl$lgIk;tUrbI z^I5-)^%t;y6YFnb{cWs&iuFHd{j041jP-b1SH#vyyM zan?W0`d_jB1J-}c`qch1-or>D-aaG|?{L;nV*M1>SF?T%>({Y<8|&|2{r6e_Bi6sd z`qx?iSJpcNWW1>)5$|yZx`n?`1rX@edf!XM7*y1&r@!T*>$W#@}ZAAmej+{%oOqPln1riRz=8G0I=y8pbGp zffq4G`3rm=W0b$ZwTw~z0@pD{`3qdn809bUV#X+cftN5w`3rnLW0b$ZOBtj51zyG& z8E4iE%X(d-$$(2@erIlQ1C0AO>l~(ek zl{{%BPg=?25|LK&q?J5rB~Mz(lUDMim7&tgP-$hTv@%p$87i#|l~#sID?_D~q0-7w zX=RwSGE7<-CanyUR)$F{!=#mA(#kMtWtg-wOj;Q(tqhk|hD$5MrIq2*%5Z6AxU@1{ zS{W{_3?Ioa+iUO4D*HS5Z^sU*uUJ}dh~E=hdPP5s)$}EEl@)viU-MC3xmSG>y<(q; z=e^|~Lh@3nzCxdf7ivs@MP4sAu36_2wALri7ss?G^N9I4xu(@QQgeCYokMI~~+;!b>?R$}7qi&o8d5o>yZG zlE+n*)fMjXyxP)*9w;pU=Gl=i($AU@RYg3{{hiYna8{qNE+X2!JQW?Qk^f#~h9sh?kw zs^9-E4aG`}ZuuIgo=<8yDn^vkq8Y}&;nEQ3=fB2vBEqGixVUIiaoOU^s`BE}`uf_+ zvc>gu0jXQIu)eg+7*tzP6`DQm85Us+Quy3Zq*Cx!Rx-uER#qx10S#B(n1c#Ss}7>}+z=kjJiquQGaOmi}> zb9tDu2=H)g>wSwvT$i_A<6-K?`vytnVG1T-4^t%Gw?is#zs7qGIE4u8+<3nLR`c-_ z;C3#F{RkcblFIuPbkoR#oonwzjW-ZDjCYpCTMj(kH3kVN+!Bqqw;3LNqeNlccF^0x zTq!BoxrYyFymM?k%W_GOF7Gvs_X2nuLU^BRJo;7z(+{3=?R7(X=-5r)&%t}xWBKup z)OeRUhOswm9U5*o>$R$C#yjwKh+u&iE$8#=^z9ph#Hy=~c zs4%4QoXdM#<2?diSiAbC#(NGt*ESh-?R7=@yT_#83tk`0&Fbz*jrXT)eg{t@>b&D} z`CYpfcr`=$ow^oy_YUWG=UU)RJi#!;yKyb>em9!mL2H3G{A7MNrUl-`1<~xiUKq{Z zG2{6ivlilgequD<{8Razu@>y5qT?0smbJj!jZR3sbJPMa6DNmwx2OeP3FesT+|r%i zuHMF6b4dhVKIWLkJ6oDT-QFI|HH&w#THsACiI(5{=0?k}IWJm%FI*5UzrR7JE8cl( zAs-!a0Tu5yX}rPOd43Y+qL0ux1a)39c#RQw=PWXeuOjf~V9xvc2)w^Vxvh3| zY+KLA)tFnytJF=L&bz)on!WF0Za#{=9hkent4XX)%lUN7?MLB#6_K|a&j_N}n}ufx ze~3^nC*j$`DG_)Z@a%!!Wz?Ns&Y$7gL{S9ZWIVIDHv;d=HHPs-1m2?;8OA3Ocz59$ z$fyXscQ2OjO16~WnHaDRh+uE^23!YqW59a(b-mOuu8F|A6TIJt@J4CwbB(^v#OM+ZK`cT0~y=D@-gQwo_H)roR5$&Cb zi(3?Xw@2i4+7>Op7l0QfzpsNAC4Gh0MYDG^c(dI?Q>0!W|A@$&fx+|JiXHcGrq&I5qT>k@@|aCdn_XF zjflK2BJz5DH)8okpUdqjeF;KDN9_sdTBJ$>dH^McdNZsC6@Gw=_#Ob^jBib{!N3%B!yyKe0 zihEeCoXaBet_1J+2=*S0$a@#Oya@Js-6Gfg)Tw$trhu2DlYn*JYVe}u67cIZzz{`$cZwYu&^1BPXDEWN_ykjH8Yup;nTZ49mKg^a%cPw~e<#G*3mP>*x z0q>qpXw#-YKh+WXo4`v|cpV>*&$oU6T?f{uKt8AO;tG%KkR#p)8gGcg%M>ih%ft(o;URY4%ovM|vukq4*~k z##^WG+5Jz?*zQg56O8SN?)G@ygA_I!=HF@{F4jI z?~MxY2uTa&y`k{>CgAmY*pK(f1iU#4uU`V*jSBCm1iUvC-q8toy?*GY@0bLG=GXd{@g*Ph!Z;!$|D*#Xq3Nx|+c_G7>OZAifD ztne;P!0V^*E=$16Q+OK_@Wv{<%MB!LQz4>J=Uy*)_{sr|>o> z;B8fSS0&)>PCI2pi>?37FH~rJ8%A= znzC;Xj+4tCK0J3w&hQ~QBjfQQLZkl1<2fUS4<9DVS z%`@U4^fzuXwi`Qp_g!L+8r*1nwe!~9-3{Z8?ndM8jCQ3B4Sh?YwRUG5Ml!ZLqjTwz zHO?mEz_?BE1ACGhx_{ibr?;~y|G=|2eyZ`=-g}aa&3k%x0w@1K5`N_!tYeqM6h@wPQ; z=Iyrc4OZqJ7IelQns`Atj1m)V8nbE6c+@?hb9Q=a4z1!6E+}>bXV=ptZZ_h|anr>^j zJt@EO_TDLPB30XO&-kpQp}`zb*x1nhs|@3++k5Zc(r0tS@ySSO!`g;jO;eh|DNW&& zb}n%?O%!F*UzAM>(qhisVKi(%qj3*Xv{y+{<5fF*8?TtwPEk5Lk&d0cEu>>7N~iA< zDxV$4T)d>;fjf>JHPhMD@4y+2&;8^lKfS$oLj$Gb_N3iEzT>4mz16(+U9w|KyONzr z&Ze;k8vjCdLiMrdsl87pqn^ed*uBLskLFv&5h72!GkS_V?M5y1uF0^xcCl^mbteO% zRczaL9a>4xMzoUlA#GyMw#KXWUPtMpxTvM6?JvE2cgAt0vR&@ZXph#|zx4PT*$xk< zn3HyAbS>>CV$MX1%sH@!W1b#}IT>lGJtLmj;U*3P6|9d@F9zk5K`!F+Q7*TEa24i@Z5qLiDkpY$o}DAa#;quXjl{xZ_b zcV>*_Tv#3Xe&(CqUNxM1J!`eqk}`j-T%S37vPw6T36+ow?K8 zxdpqkY&!Z=nVaT%g68VnLdo~_N`6eB=sJfuk-WJ|6qVbzt_!QyY$|l z=bjb^NFxpPSXMn9nC2HLQ^rjx96zCW@{H*PQwmR;S~UH%$&<%TFD{&RM)7G=C*zLT zF~3YiDx6%9jS@7!l3P@9q$ASyo;UUV?th3Q8ZXk=l!}Fg^X7A0HP!XCHC5PaYz985 zwXH@so#JU0oB7-QgR(CB-qN81R5R(W@g%Y?UM^z#IsaI(|EiKxhLhfl)vN(BO)JGr z=Dbd5npeyyIaX>SMh-G*rJ?M`!W_p}{-b98wJx(sV@8hl*MEPbWB&iWFD^2EHn)R-Y641a6^|__Dxl1D5Az&XScvn%>KW!YtpMTAB5&Go>jXc6&zxN`>z^CT zzZ-|jOQ2gWMHO}RQ)F#L+hW~RTC@?*QP9uBmKyJ-*@dpclH0t z9|Mu4E~%+3H;kivTBlh%UVrtX5laI!r>v%?iY}5gGs>m=(BjuNJ#faHJA%Zz%K6n5 zN$mc_{4bYweRJ)--Hs3P7gq;Dq=>m;4zXs)skh7xGQD(gkYuswI|sS$(~b7A zv+p@G7^JdVn5Ic!=9OnY(4$YuZ@&!kJkugTvRc?nCf>dKCo?*o8VpcXQ#~K8MJ>GB zN;|wY;=RKCL850_hDa7K9B^8u{^ID~r|!SAxD;Uqq8Ie1DX*p0;MQL3{@uG9*4=%5* zTvAb6RarLJ_4PG8pr4Dh;kwpJk<6W2H+VWHXk5XVNe6AaY||<(t|+alsyW~A4oHRN z5lBJ8=xTX|+*b}l!yP%j^qN?5g%Au>VVQf4EEn_0$ZLMZ_=uSiXO21{$+FkA-hDw=o zY?_yv+%i<})@~RtnOe*68ir}k!KxT?q~(sC0*%FR+e%Dfx?``Hc~0Ge%6auOORGGK zF|%x8Y2CR&)%4nm`I?4ThM2l|p%>JdK;>lIaR{2@B*fbWo8w)9<~Xgkre5|8qMRwu zrum`Y9u@!AZjsr|w@7Q<%0)7vV*DT4g{iGlCHswadPu`OCrZOC3u%~W(`dk_&6|gl z)^DwJLSqH?L(p33hNTU*)^h``Rn9d8?u@CtDetB^Qt3uRh^^gxza^V5*0JMDt=B5h zp<*p1WzNE#hCu%r^l)b_!aLED`ig~%JgZJW%DPc|2-+IWwzt8yMjONUJzvNy43#(K z-83tdwiZHc?Y4HI-q!qKU6aP;Yd5d?+R)H%U4e0+--w){)F{O6=X}rJS{1cWK7^C^ z>=b7q{#z@uLwM70nBOWYt1IjIl7d@y&a!F#!tH_r{;l0KI$5G^s6B}?8dKHoxXT$M z5=|@X9PGByMz2$+`)y->Mg7dmnyOM-P_Ll8ytblFHW7K1Dzn_W;XWjc-r6l@wQMn% zWF3zM|GeP~dJ^CYE>-ViBIQs&kyTv%DJ zJV}waMBnFD6Yy^B`v3jcyeT>yts`c1#xK19*oZyZNeV~8G#|ik%s5{hn?|1?p|x`* z(&6Alq}O%qKO5~GXXF&8z18{1DfX&UufYGtD*L?Srr68GzvI|P;$4;`%R<6mKp;Qi zhabv>Uuq-avz_!wPB*)1pp$-*le*4Hw=WpzI6E$?JPsMk>N9boy=tzxxfT^Px=bA1Jl?Ck%5^kNnVa z*30zW7f4_4Lz%uDByaesbb|J+v{y|!^?3SOZ`U4ss=ZA7qpbTrEtCDjK(dcGl*#@D zou8wJAlm4M# zPm*OKS@(O%qU-q~y=;G(A5yR8-_ptCsMGQ|*Lc_xMj2NEg4a33@ix{59=V9RsBZjBh z{IKxfH2obT#!quxVe!w17@lT3!otTQhNt`8u<&1}{LN0Lozk&eR{CKnN2P4cPsbd> zAj3`>-Q(mQ)hUPvF9BQK?UYGzct~m|Gt*S)_8`;DvQtPqGW~?~QRx)$lKhnQ`RN<- z)3@fg$EYpOv*B#G&@?)km*&$G!hhMeL!580$6qp^m9o4}w($}EpAwyV)e^R_?%8cBcA%*mAczi-` zyl`;gvB$;>@!81yit6|o)s;)*OLB4s4I7j_XmZgEcr030TRDG0eZ2qN0rBjSBZnQI zGbDRNyr^PnXDueMF#ne9)3wueVd3f8=(;d}za+!UM@>Ji zza-0_CXs132c8ma^6oX2nq<-|%?eX}*_M)Zj7OxGO@l<`El8pc_NerxUyvH|=2y>U6PU%%}Q z+V{_|-}c7!z<&LzhP!CE ztA@L2xVwgXXt<|_4>Pg?`RS$M!!_Jn!+kUy*YFVgQpRt;Mp)oz+KTgBrH9SGX6E!?Z!>4HYR1Hto z@DvSC)$nN=o@UU#7p}9d(=|L@!!tBoq~S9(JX6DGYIv50&(iR04WF&yImUUM{z7CT z6W7m+8Pk18CdLQfV@%_!OpGU$&(Vu5Cru&vmx;`?dYh)(IZ?gmZ_C_^hnZ8tB-v@(GxOMoqF&GmPg8(7(Sr)Jy z!?KX&SeD~h;^Hd8VUQ&xGA1NqNFw{^$t5l9GYzAHu3fdPuVXz1fQvXCG?t_E%mt6+ ze3qSY%^}>Au03vekgJG)7KcarMR-WM=G&0-SYArufj6n)7jyX896q1JLzYuG$OSBS zQF!3*tKpY$__H~D0f&dIqHvHjwjeo=!b4W6;m_yrb2$7M4i729LyGVuErf?$0_o*{ zDTn_She!R0{6m&fypUAhBs)@gNV-4q!Y||S=Wuw`s|XJ%${$jcKO}{-A$zIemvi`H z4v+RA!b5(W;)SecIhn!(PgldQ;P53J9_>hkhZOmT6#0i7LE#}!Qp2z0@TD9c?N5Y< z6!ixw>JKu9!b6fBFaH;C_%aTUb}Pa|iu6N@^h0){@Q}1;vKM|8ho8&g(cVRPNKt-} zqWmC5`-Kd&-!*caY?sUNuD#k2_bxW{S0EbFUqur7XGlW7pY^Y?{x7Vzshq)2CJDZ% zfAH&APh(orH;{z>QPw}ndfHo>^zXC&Bi1jYd_zxj6l9;yAF}fh>tAI3KGy$%^`Ei+ z3)Z){r5zf3kR94Xmh22;J?+&*`pK-H$NHtLU&;DytiOZx-)H?E*1yX7U$Oop)*CTt zKSmPq9zhcM%4Pj<)=y&n*{m;S{c_e{&ic))zm@e5u>Oave}(mbWc{C5-`){RY-=XZ;UY{~+ss$@=$L{~_zmBpGiONyOWYB;q}e^(V1@ z4D08xzMA#5tfzSdyF%XIP=74&JjN$8p3gX+@dCyLj4K(BVf<~zg^bT-JeDy!dAgsX z{zJrv2>^k|Gp=SlfpHCEoUek9i;Ljn{6jVj`&2o9LFpHGGGnA);3@N5}ATN=og7P6&@Y-uA~8p)Pca-@|UPJ^_P zBdz2}D>>3ijj26Inqk5w2~{W43$=fN-IN08iVR9 zme$MP6T&8)g}>{gPBQBr%A~UH6*7seQ$i+<0~BSFIG_(q3I}|`CV_QA$fU1MQ6_nH zuO^ea0YYFBcTjmn+2Z-dmDTfV3_h-^tgdj6=i!}w50sYSQ~V{aSN*a@6?HDa;~V#| zw6?T*zVEXL%L&0oo%`S*P%d1rsJ)P4_B}(Yi9J!4Aw}hf^i~1!RZ4U4jWj7S_EKus zCo3h-%D~eQ)&+{$58U)KGEq7IYv|rLP=UsZ3Ra3+_i9pY0Yab#xN!$s?bm4a5gK}N zanYpWvc;8E<;A7-^|h5{i?Pg$F{p0Y!urxOV^Gl~IxMTH8dO?USqcvtpEOk9ySLvUwv*hxm@P6Iv zZZb4F54V|~b9qN-JbJHsv&ZtU<0ojm6JTIV2oFPmK)idwqvtlRbK}J=XMjidg=$`0 z-VGY>6!5BCW9&!pK0bEK1l!I@ew&9H{m- zgSXQqLAt!-G~Te7|15;)E{~o`(6O7olfVnhFWnEiVJQ3^;B9aNk%C>l#>+|Pxf7Sr z4DZ@@e2>`z@7@kP7t#VRzZ1`Sw7~l)3;9Le=}ynb?5;eAp%Hc7%iVddq6OX`FsUWx zBwFBEhx6P+3%sH}Jjc)iZ_5!pm(T+5$4Bye1 zhdOU7c$j8x;&k4}5qXn`MzgmoA}=;9n!S>UyvHK)x(_!DOn*0Vdbuo#$lD*0hlvPd zMw3{v&x=;S7lRk2-hKn#B_Z~1*X+$78NO%z4>aD(;Kf7i>Aa64@;YK58pYm_h`ebL zd5a?QHb>;$6Os3FMBc{{c^&a^FH-q6!+Tn*-)Z3CQr*Pqyyf8G(%;1Cyj#J;rMijJ zc|QRUU0@TZ^UTrFczNJq2-C#r_U3>WCBK(|hf7=&r`vldV*1_(FG{&|IWbziN?zzEh|1@)aI#34{x?H&Njooq#t@;o;VyS$ne-UVnv0&yCgkEdj4P{HcC3 z67ZISm(M(EPvlbYuiJZA;dK(MaNcJMFEase#3Vo7tOUHJ3a@hl-opy7O9I|!3JC<`n3eW8?!|Y8{c(~;gE{s>A@Ng^FEN_v*8zM&aQW ztyz1U6&`NUn&oX*c<%KkEFbqMJlxteYwszA=l1(y_Fh(a80t4`?`?&LA-u;Mqt)-n z3J;Gro8=j&`R!nQ0$xXjhf7Yg_Tma}VglX}g@;qLS$p{k52s4AylDy#r$Dp35`{N8 z0dJAQo05RHM&Y5zg`@h_>tnOR!(p?$?Fw(2!aGB&-+RELctOUHz6yEFvJlgo&t&g)4 z@KO}s9EDej`gN3XT}SZT>jBe*SOFf!lSZ7C1Hrr0orGW=hKR;mjdvd^>k8;pN4&bZ zmHq~W@d$eq<_yh~yB4;*N8y~YGB$UQ!d1ov#*SwjE=zm)wk=zywqIyW?^)Wg;lj7x znb263`ttfMTd(P0{Ie0G+vy#IKJDeLdyPKNH)c%#XQ}J|clbA4wzp>rM!}E&py9HH zwc~F+<=Kfz=75~Wv^N{Be71YzlY6^=fj#K@{H@!}?FM%F>oL1=LSy6R{nzZ?(zyAJ zYxeBz-gx`AJ*)TjJkoe#BU!oow-e2~e>>i2*tqczsm8`XVC4O7YJUC_!?^oh<89;o zP45~{8RuUHJr-R$f9I2#8MK2O+5FixJ7M$nYsk)R8+NRvyzNBZ+97Y zj?+FEYgNUkeNbps=3#}23zKFP zPAVQhY5Zx$MYD$BtS~Q9HDU+2wW=lu8$FrpR81~+(laksHF-wNF)vXyLk-6<*Q=Ug zMv`N0P&LDiWXHTz)r>Gw9P=_&Gtx+P%#ErBZ_=bW=H&rZwvq0bR|Hf!Mmxv6GN8)E zYFg%|fGW@E;Fy~Os-Z@PV_p?d4Kq4A<`(&N7?<&BFP?cq_xm>eK8~XG%Gjo&Em}&2 zJGo+s*bMJ#w=&cUno`>P@Y}C{{e(bZt|05Xe$>-N1z9(#8mb`cW>rHKWNlY9R6*7) zs)j1a`ktzx3bJlhHB>>?4pl=HWZkA}sDiAWs)j1ax?R&}3RD#*GkprQ)0z8|Qd6DwAn{?<*0|1MC*qJpLeD(G&vG7P$p<=Rzu zqVsAuIpI!p9xc|wPINvou&-RRJJI=kZ$B})cU`kP(fJ`--iglVwzLzS&-BvK(oS@K z5V5hGBfc=@B35^z^Ld_W5g@Q#++$hx$D2O=?37@I%I)H^hl%at3S6V=c5&wozw=Lj z9dp?g!Em%)oCwt=R^VDzH(a~urjOsb>65z9YfMaTaZV~~_ogLT7ri+E?Z?YW zs>^i9f@*o~g=bv(&ue=;L3)pF#a%1nvsAXMZocPHV{$9KW;fsSiC$sK5P{Nkx5x{m z!v5Db-}7R!|CP=6yilp$O0JX$ahuHfRyW`C=px@OZNBHT1DS7W^F2RUOPlZcOn);y zx*_M3tDEon)M%UU`Ft? z7;RdXoQ62(*H+e76k?Opg4){BWt3r&W78}R@olB`#bkkBD;9w*!|syaYV_D}rBo!# z?PyK&oT`fI`SlA7w@=2x_9BSC(ET)KxV^ALld{ecB5PmxC*Q$oJ=9cNE2g=JZ2L>Q z5#>nj18?!3S$b}TSSOwen6jH>UTf-pt=e#Il{@wXT8`c<9GVHhng9p8_n?7j8?67a z+j{E3pMS#g)(fKH#hZc)yDH`f+350*ZK8_Eb?UmTA=EGZReXVDrefX7aTPY@pVak zMQ!ckMe1HEvH=Y=-K#+})K+ayXGIyv$X0Re!EP1wgryDkD0D5Ss;;Om#Uf^ts<~kx zv+|*mX}%Ta-Kx#ti;!LgyYym~i^kdNhJj6PeLRjgWRY)F4E|qp`8TXgY1*^~1GR_p z%DU#-OH7Pinh;vG#q z7SU`%Nv+y+R{UF=&SBJVink^cZp)J=reXGrjGKQtI2${71LRgL&IKa-hPUU>Z;ie& z3)?N+=gf**vGq$~vKYfpvS9eFR++7FjaQ z&9E;Qi=_PpMjw>z8oYADBpRABJ!Q79r7cHh$TVfDb!l`zxM@0wb(xJU+ua|CS@v7@ zQ8Cm0-pZro@fd*bt~~Lp*?^DR3zM+?m1*7(sHu(zw^Wpxx`=A3KdNl;6iBN_ha{}# zWtxE#@csS=H+cuK(rz}76erW)VmF8r@Uj)BGCozDfcLDBC)=YA`M0-!w!F^ivgu;M z*_9-9?=1Thbh5EOrB>_Th8)~-Q>yh2tDECYcX}^$Qr9}pB-;6jet#u?8tZ_x9+jh^a-%xR! zgf8!~ zj;MBMy4JH(7Gfu2nZ(HsmkGTaOm^Kei6^kp89dj;aS*n@%QxNM=9`A^6*2u(KW_TX zPS}Pau)hpm74x=(`Tu20nM1OD3T?`B8Ev$abkO$q_*ZMTbvJ7HS9T`(8Yyqh4Q3+S z4sM}hWf-|)w-kRb6#--Z<|&TcJS8c(TS~IrEhWX>EhY6oW49E#!njV%st6z_bLh}N zlB;%#+d4%nA6iKZVd1HFc3qf%-1UU~I{xb0{9)l+@~1Gaqc0F;{%9g*0xsG#8Pm*L zFOo>bz$J%GY|~ei(k#sjyUZq2mSBl@BPEsQ16^w9G!@ZXYj2P=G7d+3d(bzL?)Q^~ zX@=YVUXd_8AUOj6@WUsGEcxM+#JAG!cagL=29`e%He~oDu}=fOHxZ8ZwkX6= zl7i`5t5gNkH%9FhOyAaYP;fDh{rHo`-XMPZlf~X3a@L;GpDfnnbz3yy6$mdM0!jai zfc^BO7?%S3`AyOG21yZXxVYmc+B@SW@csBw#NHsjy;QL`h;J`dtas(-CsphX;@e9V zdxQA)QpMgN^emj5g}oVm3fWO0iC@LBpZ_$2?i=JhqV#`iT4B8GHBgk*V&jR z>k+^)V;E(bS;1uJ^08SO_5BuTMj28m_?KIq8!yPo7q2Z1i?xf*N z4QFY%vxd7E`vd9gs^M-L?ylh;8t$p#!!+DW!-s3Qw}$&@IBvWhNbeCE?yKP=HQZ0b zM``$I4IiW7{u&-&d>Ba2K;xeQoUZvFtKs7`e7uGSX?U=PhiEuk!#NtxHBw}MEt;rp z4b}Yf4B8ONb+$E3!^1T^Lc=39e1e8YX?V1TPt@>9M&CesPS$X~h6^-2M#F^~9;@MT z8Xm9V31XdfDxWz1X)gqN*Nt2p|Fn0(*^H@A&P0D!&$zF^ma(2OjZ!kPx6qA@X;ejf zBhVITN@7#IkQ%f7(e{@Idy*N9)w@+o#C&b?jl-Q^|w^9|;TnWY*&Xxsc;SGDN(^ z;8FZy&3MRMq?s@cZ%B$Y?_E3iNVt;1jbJ-Sudo9-hwMO>u>72*7_PYCF+m{0kL2*k zrw9)@oA{9DusoUK2OdXd=!VC4sv`Ue93JH(!b8rYaF8M$kjGGX$m3Yj^Iy*nCU1nD zQEUh0E9^ju_#wp}4v_S!n+-XP1<~-+d=&ZJCLG0A?H)NAjKXCkhEr{myYQi z9_yfpdKtjsAw@YtmQ#4h0Te$Zjr+Xt_=vd@&_0R7qdkcDAxkM7q}YQ2@^}glN%iZ6 zFXHegbNFL9JfsK*N&8jVkV7dvq}bo-RBl%@c@Ken-a`N%L5sZ$pkGPhpkG50`rAoD z|3lV4&iZs)>JKLg{t+a>7i;o^Kb!UEu)c;Q^cS+8_CF!MSeqYuu{J;Kh_(5le}Va8 zO@8R#V*cl>Zx@sCb|eY@(IjDK1nWn$ej4k`SU->TYgzvt)?df^-K>9{^-r_@4c33e z`cGKj*^%)cO%mxGND}Eeh4ph-U&8vutY6RijjZ3nda))y>^#EypR)cpB%%L3>px?C zT9VXvAc=Sfl0-R-W_>>E%UEB}`lYPj#`-&0|9#d!&-&L{|0e4{Wqoq8j5nPm;ysQe z;ysD=V^}|v^$S>E#rg|be>Ll`W&ORZ{}Jn-XZ>*o>=*Ew{73Q{{bLySV_eAiD8^$M zAI*3i<6{_)XN>b(*q^`{=c~XI8RPsDcoJirPbdb%K3MTV-%d-*zotTC2HNja2Umr5d;Ct$`3cgR1Sp?rJbk^YDEk;iT70fJYLb6Hf z(6o|=HgiO(CRrw>|78Rry}XzqszQ5hoW1D~FhrUiRzaN{lRUs~YZhZ}rxpQ7=;0#@teBh2?7p>YW6ybMg* z(muhu(|Hr(hOt#A0qeY9gV!~Jy}uxFH%G9yxo@=ey@2uMo(T3X$GG$E2)t1kk4E9W z4_;b?{2n-3&S&URQ&=_lYZ&LM{aTCz=sa47K3_4`9B&SIYJb%nZ%0Jl2jE3X-w=$) zqoi+9MBY6Sc^@~!>!y|S5ZoW&RBz&RULknYx9d*l-5ink&xpJ;ali6yJyKvj-lxHf zlD@-nb9PPydn>?;V(*s`dAYd%i(+pRcx55!J4&m!zkpX6!W*LTX5;=Y9)Y(!BJcW$ zyhkGPeif1Tc|=}M+{Z@A?+Fokvzy`3+$;V(w;Vj2a!s7hyA?ciflZvwdl9^TO;~bl zp~m|mc(^n)ak{+>+}ESaYT|U>aPZKynmC$dcteLOH$S` zECNprM^xf%)$Elh_SE%vb>0Gn*PV>Ph1pxA@Z9INVZ5aZkDgtS3*)U(cyGCk`S7LuW(rogy;%y+y{?DZ z+ote3C$RUL!t0{&?$_$0JD#)9dd-wR+}a37@jk2ZUdD3}Di7ivAy_gWI`3_T*Ea$0 zV}*yIuW(`U8YlVjy8UVxucN}lkhWQSafRph=VA7SC_D^lo3)p(@cJj^ zIhQCry2mF+>C<_O6dt`>LoSTBM&aR<5-yClS>d5+H_O|u@X*AX<=vz3(8QYMJ*DtQ zC*ZxT@X&OcwfDBd!=cA}Pb=q-;YsB{?HP~Qgd?o;K2v!4k|x6GJTl_iD@edgQFvn# z@H#5I!UVkT3eUZ-3Cl-Z;f+gRufM_@pMW<+;Z0C@U!t6GJzmW!V+43TU7*Me^f?$G z7;)B32k$-TR0mUHUv-r?3Wat=2(PYu-a>UD;q2kVbBE*%ACfaN9+&F{tH1I1h~Xph z;=;AOj_|vD!Oat??T_(de`Cjn*^N8*+D5~gzDvvj_RQO3yOSF(>-6%@y+e$x`x^gx zabu^Kcl~(lHPCE%zH#e5gK^I#w_)AdzDsuO>Galf-5bA3tLeK$hThp5;oo|$r(yP7 z(sxPb%eP^xMOgahrHz?y?E3MZYY;L&4IyvayVBURuQ7Q;qts$W+_gIp$BunS&4#hJ z?m!9}*6iHUXZnLPclME~+ZDSFsq2Due^-Ci@U1Q{BS!l+q>eOiH+Fe>CyujdRp2#Q zFW-UV&f>W9%e%L2J-O$SB%=;B5ffDt%X|6e-hH3mcTyY><1{&%HkZ(WX{~l>s>d$7xm}0X<4}3g zS~9lEDl9NCb@9ToidwwOw$4qVahV^y?8U#P|9DAwqE=XHlZqEv&M$JqSwgg62u5puX zl=@lO`uw8}pDj062LhYrGAsAW_{SC$6%>y@ZTgggqGBxKIc5?v6SMAX>Y1A(Jk6N( zfb0jkxKHi>tF(=O_{I1@Br=7kEv{d*xPEMDed+j`+J&X{NaurYnwnc8)~m6kgiFMF zG`oc*Vtrz?C1QPkla(X;`z5<(&6cWuTc>^&$h6(^60yGZmX?V1nO-_tS|ZjDf@LV^ zdlkCN<63f8a}6fgGc5uH7BzJjat#Eq{SC@Q-ELtqSD)x*yM@JEy%3yloC5VmFT3!z(hhHpc&~83x-_o4ZVe^X5BIMu z=IVt?ac#xOSaXZHdUTQRmKJmM*@4Wrw3w?Otfj?VeP)Y`x%yOXG1p>T#<_-DZE04z z_|K(cZG)@npqW;bR#nxUZ+Hi!!t-%bkTB+9K*UAdTB`|(@s%uMDrOoQwpLVg58Vo! zvLhH7)mC;%n)VMaoU!(i zR(tc0SVQ2=3;IL#rdc=ui*cmdyH+g|3voPd_8;&^`@8tHQZqoiQ_w!O3J2_!D-CoP z*KN1ldbianW-ItezB!nF?MnC~kAYqZsl8rzxKnxM1q7ae* z(S$$<5fA|d5kVFsA}+OT2A*KG*4pJ0+!AdS6>+Im)cV!7w%TgzQf-y@|DCxr_s*TX zygXZj{`oqPH}{(g zy`!#tuWt;(7yM&;jO#I<_PB5}WOO$J`DvITY-mS4Meh`UO5lvZhD_{cn}c+{6McG~ zqK}Fn9Y3Z$Kf?YxvXu{|yP{Bb{-`LX`+c;}{yy6Bejn|(zmJX)-$w_&8{bEZ-9j`> z*zc36WrgdH3pQ%8rRzi}n>5uat1cHyiw^}WO^YP^oA^=|dL^<6-)H;{-P^uTCARoh z7LT==6W_{;Jyr3oEDy%!h|cbDUE0vH1OcDEt-Q=bTMF%0=osg@C`B`kfI`PAbeuxR zYl}VUB`9Iv_n&|S5s zc{piY3cf{tlhdSO^eva&e)cz9zXQ+oYZ~)$kBUpp>}bE6Vq%D(Z-MB+9OL7`8@;n) z;=$y69*@>z6rX)F1fP8~1iu`*Nc<~EjYWJskYn+oFf2aOWAWj$`0!bL_%~5}_ziOW zuKb%FJjkSHw@Bve;ntRaQ+pXKcDm0a{hMCzl-w^az6XU2=ZUz{6BL37vzKg73ZfwrzzdO zGpj1+SIBhb{5dr;%`@*tm{VI??TLZg6yU9Vh>xe!I?lI7_!{G1;l+RsuU~eQu-}tGn01S}_3cDN`Ve^;*RB?|7_-nH z41=TRpfWB4>zuSGa7C@)Zdc^h0!QQvm_t>A))i0OBMi2n?5Lj@uEkK!831lM7` zbp!?L2M&Kk&)!jb8Z^2MRS$DVFn?ic@;Gz_?KS+#{A0iozq`Z_hkIATVTxmpaPQ$y zmiGa0B#Ztqy)qXL=fixPiBQ6c?j8=8E8%GDAxF5+@h7Ld2DlxlD3T|1o^Y|KD;d|f zhdnrVv^~lSWaA-p2!r_V~9GcL<(U~%G{>p))_>@0XC38fp zxGD*UqC2=O$V0t5dQb;kxOY*e0SEol((I_(Cg48i*TMrtyHvql3t{yBs_ckdwBYO6 zv>rNic!vElO55+E^qp&`Cf-GPQ2P-qNFTiS;4b6%o@Ts5a$WY0;QE9k!PN!*&L6BD zjgO6cEB=kRW5ErR8=AU@e(+@X(A#*&WY*(7wKVO;Tes~$oTLRW-GBI_(D2gaJMO(Z zc+UQYCqtpTf-{m1?JBvgVNNL6FYd^#%no)k>|h6u=&#>8E>Zh96z_89B^}E42WAP* zm!)6zi>q;|>`h-G(%tLq)UJIix>SPeb~iK@e=&#bTJMI< zZY8}{a(Z8_%3gohN;|!K*2ljYcZ^C7%iM2Ycl^+Ght`s{?7;CotL~dou<5?bE(zUm zEI9gxH}|Z&Z^roBa+ln5+4aX@wfnQR1NY2$bb40uqtmmEoRyjNnzrt^UyEb$rmVgs zwDwqV2gS+1?H;^+bK|jz+wOs-?fWh>Sj-9A*1n0@fne~S%OJtDC9H>pgAeXa&0n|Y zIbFLo^z`8eLf5_(e0I-aLut`NXbIt03iQ4hdeKYPu zF0um1iSLGE8{W(rw`ayZmrf!z39xkX0}~-}!u>HUjR}m(zkj_XKfvW*|Mm?` z{?vYYIQho)$8PY*w@S_F69Re9_-f4Qd4UPftm88GtP8F`&_7vgY&cMN5A^xv@uBL# zk*(WaX13AEp7_hKAdZcl8pC*****7KJNJ>*^QmO@oZB9UZS%tz`fOY0$&$VCG_CU% z?aq>ruhe7TobY7NoNS|a|IlOCT*AAy&9khkrtT|4O+8n!G+riOwrQSCw$$TcOWn0^ zu4VeQA7JRQM|}qFuSj@0?wui+mYv*`a%(Ql{hsA7bkN2>caqT=0i&@v6;9)WI+7mr2 zW?wts!?F!*PxA7Zh3)gbJZ56Mz{_JcwkLae%*gf>FOON-p6cZ>Guwq8UfzWT1@y+) z1*m;`VU{=1_*ri+{Qc8IkEMa-G?9-Q#%mtENEeN%{mgCPo&S2^@5injy3-Te_#eB0 zXGrN6l{gK2nTO39_;L@6HSkOii#6~p4~sQ$sfWcHc(#Yd8o12EVhvpGVX+3T@UU0| z&+)KW1JCua>;|6a<*^2?^zv8(U*YAk2ENkEV+~y8<*^2?_VQQ*&-d^|1J`)Cx#RP) zE-Wb4PP2>!-j*M^Vc7$Bq#W$(X*<^PUc2iHb^?fK>BpUw2dHZ}l& zuAORUp|EIb@yx=h1w#raX0dioYspWiw=R2o`RNRg7c~2}o$hvGA{Nh(XeB%6`1eW!j(dy2DLiNQ{OOHne)n17jh>vbx|m#3 zPVaIK(?#ax^3QmraLt8(9r7!0`GqjM{4?EDHUx9dJNW1sBRr`XvjIT)x7pcc?|v5K z7Z(?dpE-U?ZhqDjD$8wBV0Qil5rW3vj)IJIli2j=#`7M0SljJMf)%776c~MVTF7NN=SbqQ1jnVe|r!Kaw_fK74^zA|>S;^MiPgoICEjdhn*m${gt16ZEHh0AlQlQ-v9V{T zy?$QMtGPmet+|8Tma3YaIW^{t;SCIEn^r?40J>( z#+|P(-8cG$ekCnq_?#HHYaNJ0d3nWKHr_%Auw95VT)6zctZx-ss;MnsEUH_Q zTTxZI)ZyX9TjhnxX;RW+G>64>H)%0X`HVFy+_W98UL+;$3MdpQyR1uUE2>K?=c8r3 z`Sj@}b-YMuIye8Y%Uv6uUsR4yfuu5dX^R%;cx?f*;R)?k^!`M9_1|xAaKf9NcCV_V zu2fxFH#8%=vThNpVk)t&XByO-l;C#lMVA<1dr=)z3o!|!{|Frv>k+8%)k4)Yu{;8E zsn9c*+2S4cVkX>ug?P3QE)?8~Fs5`zMfvULMJHS>PyfH6mKnnwwWJd3`a^7x7i!6a z+f^-J)b+YBgL`chYPrnOK(Wq;T3+Sos>5udmY4r0YI!QDWg32P5c7#1El)$DC*f%M z2p=uoV?(KSsj#}9P9uaH(5||8vA#TvDlV&9w4ki&%8AP~X_Qc7#11Tw1Xt} zgkXVs$?VFyqSCqwHy+fJRPUn7a%s(ig@dxZC~{JCht3&JiefJg%MzBN*qid{6(T`5 z+AKFcXUt8d+SMkVXyv6lp_5Q~C%ei^C)%42Uni(t6?kEokAm<8kfTnH z0vl_V30)C9pFSfBHJl})2^F*KH!B`J(b_~Wd!2;Z^aR(Y+KRG@%K8dv-AD!2_1T7K zFH$Tos$Es<7DJ!kVsO-F*qhC4w^{5TV-ukWp#ah-%u($+3hRbm`=6=s!Z0cv_5FRjj>7afMAJ^hm+PK=-DD(s5~?u!aNXV4 zol-MD+}17?Ue{0es59RQ4ilqYRePu&X7P%%6T)rs+Bfi`54K#n7D}rf*-Wh zKvlOa`vqq*GJ8UGf;K}>LY*M94>X0UCSph-sK~m$G+c1IYQgO-wE%Z7%kh>(9{XfT zXsD_h7(N_~b9da0O2RD1{a0NEjTn?ZsGxXST29S^rL~oF=hdb4FB_1SK5Ep6b25gc zk4!7BSW>zuEq^|~1Y2BPF~5$k%W7&D)ZmbF58)L-kI8sM9f3swib;^DGRGm@g z%2CDmGv|(CfqPesVj+LmN6j%SD&~NBirKWHf-%>}5a?9%Z;%jw7g)Oam1!jCmSz5B z#m(k!-SATq9n3GUwxz7`QH0Ls=bXOItYG0cUt3$lBWlrSn~}mHGks62n$VlDycr+!;n1I- zpu*>+TUNy=bIH<-kvJZycBy5R`C))q*Y|pI+Vfk>=|d)R`ahG*tNQiNH<$G5KM~nn z*w3;G&87VY`Hci*b(bfrXMAf}%|K2!8!_F?`ioGr)ftvmXVzzoeco@xB9~h{xjaE9 zafuN^YWjERyr(KZPEOJFyFGbI{?=;lcTmUJ*Hh8qt~u4RMxlv2{>5)}{SM`DeTy6> zBZnz1a@g@(tHamPQDXma8r5N{Wl?WV{FmK7;@LZqVs09HVsm%`=cb)BH<=r(>v5pl zr^~Kq*ZEfbGnRFe6@L$Y?c>XSC@cLJC%8JKj`%CRvt^Z7ovycHZ?&vxR_rGBi|pc> z|Jpge$H}pQS>u8e+kjGzzo4OGt`$4WvP#)+Is1Lkiv7`dE2BH0e>JS5D3Hu z;sWu3UV$-zaer{V9rxpL640;93mQgpeg^UR0q_l;jmv)?TUdD>! zDNlTa@^ltL;M3a^;(WorxQ?d2<+ClQ?wx#~dN-iHubSWK8q_jsnrb=vc9iAPBTQB9 zk}Ljmx%6B~mAkaOb-Bq=)+253hpWe~QO2iT*>Lf@M;V`Vv_0adMwvd{-;4D1jyS+E zxtnzG{p9Lj9*}gE3FXxCh||?1OM)rGs!GF3vs( zH(nfsoABK@2$z;*!m-a#7-8?a)1|zu2^UVwCE>z_(^5#daN)GX5iVS~ynGB7PD>Ht z!iCe4Lb!0@v@{SdTsTer!i5W0m!E9Mjz6`acx{E#)GXXNxUl2XcYPDE$fh0n2;Zd9 z_px>a`Zh#F5Fai`uT4eu|kEqOZnvfm!DpJMH2F+HD9YRUv0!_m=i<-TDk@ z_kecsvDyL9eeg%lzz+0};k)r;wO@b^P#~OvE&s>iyYb_+UxKzM5Y8~-wHM&~8D-P2 z;yPBMX^TRfk4N}-L3fnG-^aB$$Bx4P4%(HMpnU;4&cP!mP$)5&8rbKL0c}6`r}PuF zM9^;h4q6w`Zu}1HEKN6l2d$4Meh2L=&~Et?wRF&K`4ichoj6jGIm1ZQ$o8`se2LBj zZ9g2O{3L3VK?_Icp3}K{!kIW&y3RwJ+C~rU(;7XrrTxM~``KBKuDlrSJx@4Ff_^TX ziT3X9q2si%9y(sT*h431i#&7(_R63uFHyVC6P~Ql9Thr7p*tybXNB&f&|MX}n?iS2 z=pG8)Q=v~$=w1qaD*NorEpMtqpQg}h3Vpgl_g3gW3f)(s&rs+y6}q27_gClv3VoJB z4^-&0H9Cu2IMX;sp$94SV1*u{(CG@Dq0mDWdYD2FSLhK6eXc@}ROnIKQBQeBYrpl- zNlN$_g&wQW=PC5}6ndOOXDW1-LT4*NL=ot!q znL=N#&@&Z!mO_^*^lXJL)4K8UoQ`6pz^=quoTeL;6uc}jmeX{TKz1Fba+=l%DVYCD zIUUbvzqXLmbOT0qA#UO{-LRx!KDe9HbOV)QSlR(j(+x=q=3}xAK#p!8QZSz#<222o zDOex;lhZT@rqKNB!v&m8cVK>JoOeKTBKhp<9i|IqXL*e zocklVj|Cp%kL3O+O?!vpjpj5Kk1TvF_ptzE^!My_f>~*w4{c7yF>X2{UcvcSa{d%e zqct4mXCe3J0!Q?f+%H5O5IvphLd37)@u%|mCa^N#L@R=O=Ob&b|2fjxR7O_mu1zZm5k;#F73FQa=<=p=%(kJ?$ zoR1nFzlg_2{j>P+nOzO|vnW3Ni4-6H6gmC^9)B8-k9K46;j?t%&!+hBe@5})Q~KmT zDa%15R*qsW2kp+}z-MycGdb{?9QaHQe2<)3F6Tln2YSQgz-MycGdb{?9QaHQe2<(( zT+VbZ2YSckz`ugZ1AjjES^I!y=g5opt>f`8;_;!cEIxeJuJD<@!B3?6fZtiJkHtKG z36BpwXYt{)_JChb>BApD@!^vl6Gy-5dHjoceDn_%AATvtgHPu_9{fs*4}TcNhd)}5ztkQp%uBg_mnE7OBs}*4B_I4ha{d>bPj=Ob zznl6W@IN6R_@9#x{yUuiG3Wn-^Q$pN5q>54z^^7B_y;)u3C@3t^WWzDzj6MjoWB$| zLL_Gc`H-`je3HZYPjLQIoc}iG|BdrM<@{{iu#lW$@*$^$e8^eB`CB-DE9c+G`Hyn` zlbnBy^Z&~Ef9L%87+e0S8b`7dz( zOPv2F&i@zZhd93zZcC`VXONHl3?Lu*$>aPI&Y!{gWY~=Gt2loR=l_87f5iDe;rw57 z{+~GiFPz^Y)|PV``AD}9`AByp=TGANDV#r-^Oth|HJpDt=kMqI`#Jwv&VQ5h-{JhP zI6o=QPPY^JNcU{=QLgWCem3V{$oX?Q|4Pokf%9+Y{O@!Aqn!UD=fA@FpK^W-76Vk? zc=C~MU-FUe2+kkP`9+*x&iV5=|3=Qglk7sY z9L$%DzKqkD_ZWRSr!jvq8XGLMwxRim(X%*>`GwJ?oW?xC=-Hee$>}mqkK%MWr!fvQ zdF;24Zxtzwh$LM*S#yE!VrJ0%Bo)5~y=qyg7JdDofG|I#198RM=jLzjW z%ERdKoJM&VoyTdEhtU%_jq)&hBBxOvM(1-HEtQAyQ4Z!K z|IA0enUDN3ANgc{9`}(iMk7DWM?RR3^qG%znUC~z)LSc#>>L$dQdv=#EN6EvOMO3JXQp|)oWNVg@V+al6!8R@o=bX!V>EhWR2 zl3`29u%%?!QZj5Q8Mc%RTS|s4CBv37)Rr>TmNL|qGSrqb)Rr>TmNL|qGSrqb)Rr>T zmNLwiGR&4T%$73DmNLwiGR&4T%$73jT(1G8)_3^16(srCN9{yN}7PM7xWXk9Fv!1Ysb&$oihR&d9G!xGVPLLTh_h-(TQ?Zfl21PA6^ z&>n}3%TDI|X%51^P;u9GZ?z%siC%mks|{Q-Hc;8V zP#d_HPLB?^t#5R=i~EJQOQ_cK`vdsCQ5*RS4dnYnZQuqC;`=~t;ATQe*?y0LTc+sC z?YMtJ)wFOb?iaxIL!VQfihBq5TlcCU&?;^N?!)#+fg6GQv&JZJ$AH@!1#SWE?{-Cj zOTl0o4ep^Rano_%m?U>po(HvFDsVsfU=;c5hWpH56u8Ht#8qMtdLRmUJ#hc}P8i%; zMX$aDZkB|@@Wq^pn}JCtHwxU2C~@xshg)ICwU+ML<1{VPL5UC1HBHT56>ud{;F_Yu z^+KZ2$g2Ym{~gy_IUWKC{~gyF?h}CU-*K(shGj*Et7`>!i=qb)0oTb%)xA)0^s&MW zH`uvSaecDc7P=EIE>zscC~^M)E}C?w$_xErFxeGJ^?QhMT2 zP4@!qA4P+^AGm1hB|a}Y+}tQ}PXf1EWM1-jDteWNeXmL>TwESdaQ6e3CITg2#k~+E z?!zc?Nf?BpNq2CRxT#U%YNEt#juLl&l(-k7#C;egE(!aXQPp27IA(uNYVWDQrAxH9 zRB@|-8z2HDU&RHZ#2p2$uOvrYs`5Sq?o1IV`6{j#_I3M9;o?%oJN*UDI)&0(X`}xfiOu)3ASyrEv?V;wAw%xCKhno<*XjWY2jiaCk(} z!o35WA#o1?mmFuWiNv}Rw^rJpfQyxIk6dWKw^#ul(qS%uUoyEQc6roalFi+pg$A32@!PC%vbBK`tC_0dScJBOJCImg1l7{u1f^mW59|0b&Y@vU~w;S-6G%$B^=cwxp3v! z4qPU}s9t*Dk6bw1YZ4AyEX;+&b-&n^cS;0YiG=GF0k>Vkohsq>Df;pna35iSq;e!l zIQkAn9(R6unXONR6Y~g_L&d!&;jksbTsYi&5>Cty;c%ZzIBcD?DldS=GwD0!Ppl`x z$?GoRuyw**I9z`TC+4MaxRDZ0%){Yu6D8d62^CaB45pYW++{g&HbrNor zgnLHOgY6OyO9keryee*=gu|5GD(+_zt{?*LmlAGr1l(&9Zb}5)dlGJH1l;Emt}p^F zFw@n)3nJjUOSqy4xc(AuS_Irk30E8eH&Mc23BX*qb}Nx^7}6cwn~EOH1CHWTf5Q;W z9MLLnfrP_Q*eY&`gu{^3DsGj8qh}-J!lk=T!d+^^!s50_IB{PcPTqD2hari%aJU^3 z4yw~CZl8q1WvjRcB;2eBxSvV5(g?W6B;4!>xL-=RG70xL=z%4zPmcg6<~0suo{2dH z|FtyE{4;QU!~&c1uw>Wb6ZRSl|{eZ}B3a_Q%uJ9J3KxkEBW zrKJsF9Qijb4S_>!&aAkV;|ucey|E)v*EVV{rD>#l~wSx~Hy!YTP|8Z;c@|Ui!k2^YkbN8c7mk=gv zo3**`(cq&g33;i(PrD}U{{_O_=Qa<(-$?SkrNgcdhgK#R61C@GN&>}R{!-K7;~{@x(>99Jbol8|)3%=V zbS>vm#7$#yZK)rINDj#e9Bu0UVW?+)Wr)hiIV?{kE2*Y;eN#_E>scQz)Y?4gXjA5g z)glEucXrOQ8k&}g`k=J({H!*R^X!J;C#a22y0KE(xyosHYFlnY^R}j?lzYm}+T(|= zJGA!D20!vt5^7BCQmSu88|-UL>QHL%t5asN{G$#G)Inkm<*{RpU8aA8{s~DLR4?7X zbgz3Rqb!wZRlD61(Qbo|2G=%a{v~us*S459Pe~OeO+?Lng_`MR*qq?K+LnFYwN(YF zB_ZD|?Zus!_O990pbuENC3tc0-hz<1C3vat(D=<~zi4glebk)3JJ5W~&S#niTANAI z@z7Z0#oFBYXcP3JE9xy&m8g9j+STw>Xxx^ZZR3jkC{6F9O%3A;11Ll9qxv09&pj5( z*}CtUrftDbdoR%L%!NN-!Fc?hwIFZXzE93t(7XP^JMXA_Ev5;puHR?FWu^}W~~P3KViPujKv znx6c}Ozj@%`d;XI5K>4Z5)uZ7wBH5~#wF}On3ynSH}R>}6Br`MdXjUU$@sx;ytVfy zCGghXpVSfcLmK}%`b!*Y$i6lUeKo`*4Pbf*dFZ?W(mBd0`c6*`QtdwE_8*i<(myw^ z6vIZz`RvSc%=;nl`%E_ajx8G{VAoU<;HFyW6}X=IMO8T2`yUM?G@=G3uG7ctLd`UO zl9-Ucj_PT@NhNFiBq?FiI_Tx;qzR44{SNe;d(dz8qTfJAwwSZ@JA5_f^d=qpml#9~ zVboy%sAWiFcPTvmz1e@A@?PvJ{f@LhW@(A}8*R#IBZ zLom~*P96}3C(x+uzS{`g=#GzxRU%(1>aG zchSFl@gD!7)63m)wP{<27UKa6#h4(E1A*hg4OB*q-BOR%_IRk@0cB7}zj6glPTS6XsYuq92VeL+g{(eHxNNMX}BU*hgT74fMErWbM5c5RO`s{(e zquC8pX4$znQPb2ylxNB@M&a#L&#YwV{XJ2}G&c4~c#Q9ar<7OK|IutYPuLpmt4`Fu z48_*$11`J2uI)oV*yrh2J?rDN{|RL`#IW3?9&H-fv;K^FN@@8^6B?Q@!c$)v->@5{ zqB$TBv^)#+tRIZ|hVp6}G)_^jKI5EjtYlyDk}(7?=Xh35iq*Wm31t)|^vcPJ<7Ll^ ztIBDJD~g%xw$Ka6@6HA`2V*Q2nz>HWNtz`Nq&8)at!A@}U%L~dJv5~xWR~vVZ`JJY zziQjP{kJ3S#G~e+CKle9)Oi+-_xgY)|AY|5$VJb}!dyn-E4Lg-wWjaaE}GtmSm+ht zjoVTZN-Aygo702TtJi79X`gkYa7TVH=x4Qp-gxwq5XFf>oH!mQNs2>AUs1wrUs0b@ zt!QMaUNpGWDC$>g7WFQTsj-SuO8rG~r7=Zjsb=_*gSaCH`gdouXWWq{|GvZ!KCvLK zo%=7S7Xi^rYx4J=P9cFKe_=cdF9@+-#<4LhW`I%SF)R8tl$81{tCfcO8qRRD0`XdtNz_N7d<|v;VaM2hAIEr}E_9rskYKbK2Aki*m-#oOUtpwk%^#E5Z3wil)fKffbE;~} zuAEl0xVEf9GtC-Ncy>SmmoTLJMFT&6sA!Exf*f+QFNHp<=4Bap?L*a(g9Ro2!4+?Hn(D@qAB=0DC^iW2{=$P}O(ql+V2}t|Hkp>u5}*X9XO4pi5|3 z`hA5z@nRRvtEsI+v$LmL99jIxbEDpvva`&Kbn?NY#IOgCJj(5#ZZHR4^1wyjD6r*0 zqG_X*F9^sKr=0}@9{d|%qf^X)`#ek-dKp}hivV>5L zc0zePVSvaR&xzH=$`X?0rmdfN|NiHvbv)k_%c`oGKNq?$H`P6*iEoYkQ_jm?pi>Sz zhNmD?UOF@N{FgT!^Tgl<8JfWgk|U(b1rerFyz!_YELImQPe^7DGI{ZZ@f3Py4K5SWhd0FMb9>jOxtlVj=C_all)#T`RyBus9m^(Pui}nzc)o6|exg3TVZC=0 zu*z!|&#tP_d_K8rp11jbo0^Y(@DEQ4c7a{|*YBE-yCbvSUI*#gJ4j_HHXbRrQzB($ ziv|}}R8^ENs+c)GD?48+&QB|zJZ)&kkR0qs4N03YG%aUv&cJ~%LsMQcw_<+Uh4U+y zq}69+{O9&*X3nfAt*WZIN^>quT;Xd6VvuLd6km_bL?@`IrSB#dX<`fr8|Z67yYShd zyrQafDQ3r45=Lv2^YRIIMvM~+%l$%#GeIt~!U@=?eQHfcRb-f^5a64)B zBGGlq^%Y`qV5B5xgkMMW$b!FoVR3&fTMHo!V>evl~D6p=d z=4%<+-c5hMPp>tNH7n~figSuIu}T1E1vrHgN56zICb}5Cq%I?;;C!s7T^@{p*JTtI zQ`8y_C`Efhk_R zr=mgZ&f!AZyAOQj(^tR(ZjF;CG52{h#Cj{ev|^n_nP$Tx9~s-L$y(^gbC^KdE3t1; zKTOo4GxpW7Jr7pHR9s#ELfi zlSV9`KD~1C;;K4lxbo?j%uyJH82(fi#7I#J7ug@ciVE=Qvq&YXuFRibUs_dJo>yD3 zP;&xd=B=)xdcm}uY3{gza1iwJD*VPTxr+I%sBbb=j_cA_VSPEf~_P$@3PzNXXG zbx;I%ZlDtT^*T1O)??%W-w zenGWo0-@pEvr5Mxd$lsAvh_E{X3t2xG|Z@q)x12aiVkHDj0sR;!BG}tyf1c?5O$m^ zTX0sl;5^@g^I8ke+buYM2gjenhT9Wi!&clBBUR?|@Ou*WtWoZ8i{nk)Zbik_^(wIh z=Do{-w0GC~F&kRT=&4u!{E5q)S>2~sxJ+l=g|!JfjRY!Ups9=N9G*3vwc^NcVWOsc zg_BTo#&|TRpysM+3o0tgT@9jQ>-q#|2hmj_FSfl^=~8=|cGX7cv`-JCCT=d>lK49_ z-8t)9(4E|qQ+LR8gIm)roy%G% zan;Tbc9|=8T0Jh?Wu1bMStW**VqU%T(h@YvP0L_R%=~c0PQzbh_!7-$wfAA*`LEi} z8AhPXM~MCUHSe42br`2d=tqFw=g0M>AQ~G>41dSVe5Uzv{6!b3^n{c&8iWz%sC@aA%?$;Wv%h!(0pCLo@wywydT4|Bovw5NMUf% z+PCG|1Nrt%LhZ$0=rDneM*TA^3g~ES-P~5ak#i=qwtuMlIq20C!e}DUTn3aCYXtgi1!~Ik zM_B^TCTuL4Vy>LLX){ab$BQN#zLX2ir5mS|m~|UB-O{k-7OSuMs};{d0iVz(TOGDc zGh(uyKVq&R%|p-?lZ}|fDbFJto9;5KMEK8>=T9_ZQmigUd?&+7o`FBJ4v`JtS%xp! zyk_Ig<~5TEVWc`0?kphX7R1=N$y~A#I&QASRsH0PE;bi$ z+_Y)atyaeuZniqSW}KC5C7E}v*odtD8F|yEuoC_}ZsQbIwxHTM~enct5+?wqTVo5sJkzD#W1^=OBNbdck>#<)L*;GtXXIcHD@oh ztQ}BKUndkW1|1>MFcV+JpJ8^budOwgE&TOw&BchE^eWoP-wCY-?F+742u(4sv^p-T z|FyZ|m0!QXgSuU1bu@fEYZ>!Rs3>&N-_1JJyqda155w$!%v|~kVW50Tq?yT9$E#|Q zp4H)V{g2qZSWzGUB1kovqkS)c(on!&8hnY?vFqT-%uXU2;$SSN9WMf0AB5 z9hYKR-6xzk*oxg~S%0^-}#C$hdo_Fzuj zt%i3Eegb+^`zFDbIaGi4xkJLHd{UIQ#OXaZVN1L(u0?#^=$X)23-|*ufj}TO5EqCK z^a_j#j0@xhCJX~kIC@h`w())=Y|<~^U}kk%Y6Lqihmm?%reEZs< zQp3g9BgChA6fPGR6n|P=cKrCby!gDh3Gw;(n*jcQTHks{-3%mm>lA-V;EceA%y?{e z4}xvyu{~@n+W1ghkYw4!H;6vK2#ks!9Y4k*3^6TB%TGgAxTubL3d~1K;#d^ovS{(# zc)DYn+a!zij>UAJ$9}z?xi%!iB)e*m-Na`t-OT`HiwShZTORRW*RXt;l)g#vvgPtt zt#ms@@wZD+{%y1C;p)b11y=9hP}b#Ya+D z02zL_yD56UW7VA*d3SBTGb8VoYu(*%TX&D~T6YgfB!-n(+t_=YF!mn*-7xk}bGLB4 zaKUzFustLk&CSAv3#YkNxNzY#cM2CSoaR2^!iCe^CS161nwx|R7fy4JaN)vfZV@hA zxSYQ;0krFfz9yK2KfYt{c`KKs(X3=6>CJNqX}^fzyfRH+^4K_fPqzimeea8e_IAM3 zJ|3|2=zFk(qSv}SD9@{8()&pC8JwL9vWn=5;(c4i%>li`AOW2x>yX4gL9)fs^J*{3 z`|y;|^c|UvrYDqMbl690Zf@xzl{bRt>B=`?5uJ7zT_1K$o-fSxLaSK)fPL@&biT8UnU>)%TBwYdI+M6bj3pCo!SuKz62+i-mjuS81! z`=EzQ^d8V;JCPiP?}tA}q8|jkS)zXq`euoK4D@Xh{WRzwOEkT$^RPs}0{SV5J_h<} ziT)kv9{3|?z=kW8#jXDs?QfvPy$gkZ4th5J$dOI=5PYgLazxWtyA3wU=nkN7m*~!* zcS`grpv9O=@q2@QN(vtU`j-+t1oVp%eJ<$tCHi}yKa=S3py^X%awNY1*U2^sI+ocy zw_g~b@K|PVl!g>?M3(}e$tas98zQcL#j+PoJ2~NTT0O$)rB!ldGyWRTZg{-52DIBB z;GC7KWJLpuKWb_WuX%f8`G>y~b2>(OS{7rX8{{%GkNpcka2=9R+mA5q@Ml1uCxyQVI$NS&1MQYCL3QBhK-=M=W3`7pbe#6GhmO}i_0X^x zj2S{W6E=pubdo|RD|APNPEqJi3f)-C6 zjm_C+zNW1qdJ=3clYc&^3%Ea-^QUkci#~=g^3CMHr?mu?qk{XdqMnKVko%u- z|DW(3c~^0Hv$#BzpUHzy>qe@NE4bf<;)BM4P0UY|Nbl_J}I`9{8KZ)`Qn)2^x?C5g3sy+{xC`p{%H74{N+48ZakPCK@VAc_)LG`UrFVFPiq_U>E@Dry1#Se zT*Kwe;c}qIOb&e3-tftemI~*;j?;% z&*~XImCuBqDaT)B-^ZErxNY>6n)V9Bo8Ytl3I6*;gWrwv2|lgm2~YP&#Qz=Vf6DpH zb~^Yh-@p&2bb+V0-U)vewHNqf$p=4^eDD`={&k$cmh*4p{2=Gw$N7(O{!z|vx`;{5HLe=q0%kn>;Q{C7D2_niL)=QEq|NH;0QPIn0T z$WJ!;;OB8Zvjq=+HRm&1@W>~#1rI*61rI#41rPq&8sb-K+7R+5a{3BRV;pATS8^KT zD5EhLF+9dOMptvXfYb9ijq!$s*Kiu+0;3mj8vUEm3ptH`$>>^6qkp0JnmNtBKc)OJ zx|q|*AEPhiH1fyj>6}LX7>x~)WRg?B=@L#Oe=PiBP9uMezJ$}rAER+VGmDS>F?t54 zrTj5I^2L1Qhxy0{^N~LDkuLL*9`lh7^C6%4kc)2LnuD$F>|tdKrVUwE6?W5+nb6kg zmm95S*S4`~+t##gYWlzSx9y5i?Qc`f4YRFy53{X!54Wv&54Wv&54WpzxNXIIIImb+ z%5b}Chud{K+?F!jmNLSYGQyTJ!j>|^mNLSYGJ>~{EoFpb3mislak$x>#q-OA>0tZh zGtXu-H@a(wNSn)H`0i%16391?6>hlAVg=%E4toNe&0v-5-TYNUTWt2K0B3Xe1RC?U zE7txvFwE=uE~`cEd63j59*)}@t_*MeIB?!RF3$e8#|aPDQp)Gw4%TflVVnEEYG#|J zwp$vytE$;|$+&j75x_N|-EtHNALiD6GSkPiWo8Us;ISLNT1$G}o7;*wPo?nY}X+IlF z5621IYz3Esdx$%*z86m5a9ixj-vO+Fv7~dHz}>0fdLjd7LZ)y6_mG0iM5Wv$Ks=1d zXZW=!$6?^kq5$rMy!SxUwZMG_+&Tf`VMN9PB;!`ZhA#&_Um=`u9{~4LYD~oqR&cvJ z^8J!FaP!dMY(Jz8+?*~rqfV+n0aw$V)m_urK865rU&XEJ$@d}Jz^#GuvHgZNaJQ#v z8rv6W1NU*C@HV8?{GD?qzrSxoUS)qxWB2K8;BJGmu={ZZH%4ieYkL&s_-r`pFA5yi zr`nE|#cff4uL9Q`1@6v~nzlCzT=pn?-&2K7P}+CPXp}<&Ve5c76?X)?naM8#+5~aLkObpS;TL4@p@-JL#<#-@U+(*FSR@ZT@$;-q;(M$*B)?cyG9;<-E zt#}Kk;+_Srs0B*XRNSfG!@gq_xaCpe-TB=`EZpPshR=Q*{fc;xd2> zm%p3P9;W@MfyuZOxNzm&1)L$JvIRIg&3hBPTREThC+`IgOIOEj!Tu$d#%#<&I?NIM zO9i(bIEs($OlJ-x+`9^HpCr#hI61=6r@V5y4*=I6e3B>D=!B!gGiBUsz-4kAg_9$n zp83eQ?wE{-Px4S~=7_!=ILOB?w(Zh@lj9MWa5aj&vn6?0A~P2bH%!8v5&<_>!u5)P z%aw4aM!*$FI4sSX3zxrQ33plq+zbhq76Df-;ZBc$tCDcNBjD;JTptOyQfZInz~PpL zwQphs+*aTwa$Hgb+%e$rpUF#(fIAxsCFFICfU5&;9+#IA0e1|zOpfam0oMzQoK+mx zIRfr3;4(Q5w}#A-9;o$q3^-Aat`Ts3u{fB8aAZ^K76G>gxJ-_tb|FXUZdTf@3Amqu zNAfxl2##<&6x?$DJce**5C|?D?j{L`TSMl;;qH=f{UYEFNVxtHaF0m10TFPAC7hTy z!{zUogc}$^-Ukv6x1`L4llP^B6Z300Tmqgmk-k$si}{OiKT_JGmxRMopSf_jvn3ps z=B?t!N;oW~Tg4SfI4qG{#m$g#nGtYR5-uwOZn=cZj)1#K!sSH3-6i3$RA4S#{T+~S zG-Z<`T$9osj{rw}YPUT6kqd`wl5i7jSXkU)2{$nU?qvy=9|3nv!cB^Rdso7V`@L}G z_&~xHM3DE1gqs`z_oalJ5&`EcaqAgN59TO;uc1A#o^jR@3BZYU0f#Z~&%n_-DvdMG z1a6v-6Wqg+N&CBkTRKD2z64Kpgj>8|fom`}t!&UH5{g3!+M#CR@ZC*`P z`LxPqFm-2S=pvtTGj03zfcvKP9!Y?5dm}zP97~Pd&+5TL8cr4*9xS zT3!yLV~NHjT^uB5R8`Ke$f;ROmb#2SMxt@PE)F6zW-qOCgK(lsfg41zrp}qOsDeeq zp(~S}Fi-h^IqE#khg5c70F%uc*`%O z+U2LU9k1?r&v$sK_qZ_+d6M&`2`RGV=ISFIf4MpPQ?Fzpz?Qtsm7Ke~U&h70%{x7k zt!oIN8yD$j+2YzPUb!W1<${|nS0d{7VyB`EgciuPk1D>z3Dwy5UA$bk?)}R>+q?L$ z@T4xPk&g`g9DCEaR2P|*jbr7_`*c!euh{22B7A8=vRpOq-+kqttiQegfVXOd0K01X zP|5L!U)gM))4$>)n$2@yfi}$Mxj>H*yjIQTxp>DM85zUV^j6L0xiQ){o9ANNGMncj zoqV)qHqVU$qXZGm=D9dWG>hP|HYbeRrJ;eG2r;tRJhM%+d2T${Y@W|Gn+b&O z-MjzZdyXeHUz!+5WZg=9Z0y--ub&t6>Xr~->y|XDRn#7i^BdQ_>4giyE&BiJYcJgN zuiJVYQZgc>$QhabSTN_K5lMgdN)`fa$#fUWm0Y$A=u}Lg4a93+T5c%gR5#Q>ne(uOkOm%D9gV2r2^}EH@#(O zJ1LW0-~DxVK5*TVY#5DnPNUcL8Kt$gFt{iNR$afms$%}!x_OS>2OY*BYV4(?7}tGz z1()NVd_UWkBZh6CUdZK$!QH1{z{R+n%PXB^EPHFT@I>n$?eMmjrhj|g*qp}o4|f2# z-7TspEq88cP+@nyJ*f zeyBCo;mCH?oL9do&A~9GSp2kNSt0*B4yDy+WDFWHD1A^t@wBv@ngvU1E9cIuOY2`Y zAT52=s1fI63`rlER$Q^9bWvLV{6%%Oi>oW<*U@!ZP3?l3+ETK&r<-CN!dEv~rsw77 zO}z*qwbiAySF(Dx$Dy~xjTenW;h^oRO`m;J+Qi496(@Qe>WHd53CE#p`8Z@NM2>y? z#Gf*d@=&pLeW|N6UP!y@%(iek6K+w?hZphi0@i)Y9FxCd)3X(3Gz)kxUOX|e?Dxp% ztv#Pc?`(xRXPlTnV1POs@UQ+S0p*9e-iPK4^8EZN<*DI=*7Xj`QOX z2VK8K&Z5@!Tg&1w9Oqta#rB7VmpEkWE;(CY4f)ox^@^5kS*We?3&-VNg}>_EcC~$1 zS~jFBEqfnpSqoK2kAr>e#1hiZQ@*t-yc;L=$1e06ffji>F$TE8b%;Zhr)9QLgYQZ` zy(QJt?Q+{4AN#Gf-9NP?%X-F&EnK%{-Hq25*ya`9WSM&zzhQ>GcAO68A;tEx?j$J* zI*aEF`K}Spq^Gf8INDzcccy)(DC5%(a=7@BY$o&)iNmLzGdlA>r_+iX^x{q{pU(Pb z%Ml-CIcTjJt{ibu#-|&faPj}s^gBkGKCO2|`g%v4!|$;LKu_$&LHb76!}v|xB7k$e ze-y{S|Jz5i<7{))c)&My?E8t4ZLQ0U-wF$E+BcbR=Lq?4{xJNncbfdy)s=Ra9<{be z2jAmmSfc~_K}P(@?zWwa{4~7!YO`F1FG(9}pM&4YJv1M2{oX_KV;qu!1MZ>uvG$?) zandRIh#qgBlAj<>$?x#pI3=G(d*Nsl#!VEQ{m7fHXfzitTsV!^!i5WOOFoUV!i9@( z@739eaN%vmr%_P2zPPZ*+OYYGaOpljSDY2+#U+$*G1DNg%I7^4R#jY zN8&tBo!Z>WTC}L5dUjPstrqAO7n5Mn^X#&WkxNQvS86)#n)&pWrx2h?94F4CXD_#a zYv7Dk(nj&k5YatA+dFU+Zfd82w(n_e`V7!QL+H%{|ynJchlA?S==~_uX!IK%0a30Y_e}R*h>nzp?DDhX>=G zQ{6d#op>h7-yi}RZE6pAXrK11hqko;_0Y(fRN*Ghd_UDg2iVyMB8rJK(l7Re$18M# zLU&N;M1@XL=wyZNsL&}2-HDyA>gKPrLU&Qb<#Zei$1As< za7!D{Xd<@Xc$A?EW z4w@tEGZjos#p84^FyJ!&NY2NAO=BRXvyl6j14lGFs}}w;}Riw~cr51*wEpQR7qlm0j!|7;!~?akuD zXYt{)`0#1%Wx~HsPCtvEF?lD-P3;MO9r@rdAs>9&vLybGIR7V{|2*gamh<1` z{I57aNw?+DdFUkPZ1S@-?R(@yem42wUrK%!%0WK(G=`htuO~lC)9xZ4{2kz=X`dyH}aE=ML)@>bLC0?a`M4vXBvaw!1<4I{)^;; z{|e{-ne)HoeERs1CLjEjoPRs#@8|scIsaMC zf0Ogy;rxGaek=wUlGA~Fz=ltWGpNxejrQ4Z&;QNse`J*`hJkGzE^RMLm8qU9&^LKOpUe14-^MAwn zZ*o4JUq|u-v39x%Z(4 zqx*1LN}utOF7uHd^N|koA)on>%Y4XVKIG`gcPoz0a2|Qlva8BwSF=Ni?K6Sf^}J?w zgf2fmxaD2EeZVg9!`-#3q0(Kt8|1kwciG|Y!o!F1yKXly++DUB>U}1C;*JBRstQ-M z)~b;B;r0QD@7+*QCG%<_wx^0+iQd;fh;KKd)J)=tUv|JPA-rk2wR$o%|F?fk?@4jw zEsbCFN8=ee4AmYd#y3otEpRlJ3x{PHa~Lu`xLKgjWFhvCkcXwY2e%gVkTAFs1@|-1 z;nJ;9aPNY~^x!y=?nZFr^8OPvrWwZx+`Zt)xI_@)xjdY*gakwxQdSaUak$?k1=Pnd$u-kLr{6_ z-lz>+73OSq57q|mXPCRAk@pGK7VMr%krx6j*K<7-_jCnAq>8%@xZP3UMyJ6}WfZs< zf!h%UZXq%kO}d?-d|RWCw=YWESgdiPk#_{R??;htbze<;Ck!qgje-A;D?CHfG9Ai& z_M+mpM2R~B+{7s4b;n>8O}Zsf;+hy3#a1N0!QDC zt4_r|1RRRe!l}5ofkPK*;Z&R-dkxW~I}AAdZ{bvVrBTY;+zPG`^=C@wk{$$ZXp2;B zTWE&F{|LApmZs6V3r7+%NB87plg%%kueAljVtKgm0=QTSoXo!qIO1pH54ZWug~RQU zaAG|c4oByu3whWUXjR@r5)Mm`R&kF=IBX-diffW^SfaFwJ1pT&iGX`q!eJ@n$lI*c z-!b4Q|5ShRHjI^D#eD)?CdVa2zzxHVfWUQ#fUA>mi4kxQNjNM)nWOe;kv|DX`a~`q zZW#8EG7(1Q#Zr~IaJV`NXMgA$Ufx3zu9GD12TDDE0^B_8`IJQM*AEnWOTm`RgU&pc1X(&X#Z^ zBH+eKxN{@m3MAY}3HP#6e=~rid{a3_MZlFyI8+gH6i<~`CE;+{Dy~k#jg5d?F5ze| zfLyqA*GRbU*|4ypt2hx)^Gwvw~7yMXH{2+98^aF{Q(G|qb%xLQL3 z;1Uqc08hsCN9Gg4;1(~M9rj$vp+nNr@E=b8#kr9g8KW{r62I+pA-mJVO*nBbWQ^%I zgX{HUO-}_69}hK+^=mez7t(cO>YfI@sByi&bQVYWYUs)iO$o*5!S&i5giOLScf=e+ zq2J#Uyq>6+6B|?Y0q>r1NvP4k|CxKAC0=l~wlTq{kJ;K3_h$1`!Rz;?2KS|eOdTgR zW(KO7A-Q?%UVpHsrteMFHWv7{`h%GXRfOq;v~;6s`{CPJxUn~NuOAXuH>MuES4-E& zXhu_TZ))6IPd)WYN$~pM+Dk&ePdoq&rHoYe?;kxb)bz~ZXNhh~-G6UzG+mX1-kTNN z|A$$Wt6Q6bJ6K-UQ(o*+%6Ylf&I>Te%WBsfo|nN>Qq+jz4|gRkAO zufMiRZgpEP{uT1o(3MZo2|M&3JT$;UJBF@BE6-v&(U_X+w@N#PR)b^K;P_}gxUUiC zjFPUs&2+6LqS3EU-=n3m_&q~9Vm9?m#_Ew@cmELQdJ4Wz;{OZ$gAeARzB4xt@o5`1 zU!#9t;$5j*58w4=H{)E zdy&UraO*Y6vk+DgQ@z*UF?2n0^4J~z8gab}Qb=ZFYMwv0IXF3{YOkN-HpW~RODOw# zZ7lT(l$Z5~Tz_73{H)+UyN>pveVd-%_dN9;Dl_M=CO&io?MWP}JH%hN7kbe6LeqKn zS*Ll;xyW~1X)tJ&?)96cx?$89Mq{c`qa6wcJA>y(I{Rai(L?`y!oal-ayB`nj zd&Ve?2S1s59_M}quHC}6)>=HL7I2L*PEPnJaqz(d=ywxW7dB1VUC=yfZE(jssH4V) z9l>CMuWEn)Rhn6|zyD)6TlU_8)Xy4s2RH5Su9^2@K^hDum8OL>eScDbd}Du7+^pc} zA%*^$;OMkM6TiuY!A;aIL#l)O??G#%gmTc+cQjC)B!@bn_h}n_`d-jLWv_z1@9jW( zzBgg(GH|l?`ZEiOhwI#!>R`@Ze;T8GXqo(X)gjTNCZkA`fTXCJK#P-TaifC9PDnx_(EGn!Tvw zglbRwW+q|eOJ>?Ztxmle`j_bg*Y4p5A4Hx~^)Y$73vQUyJaKg*Mh1+xoAx80x^W=M zUrK%W9<6z$zsA0zn%qHUMu`tTc<|nXy8_398>Tmx_=~SAS{t04TpheuA5eBECzPEU zT&o+oPvkv0F*W#LWwSQGCP!qI1`_sSnG}-y3Vd) zoKBn?Tt8_ydb%GueR|(2%H@7Hmkk!rC1#^_)MAG=G-6(%eEN^$#ND6-uq_;Y60l@-ShuAI=ErhaOMOzBl*D;Ql<8yS2w3OSN-H^JA_*3!_FF zUcSg}qR~;?Xz2QYt(ZHtjedQrG<(|UoKQOO!S#7f80E~ZPteGYF{mjxIo8vXs|o|W z=h|(U$;Rj0^?Oq>O72UUMI#wPpcTQalxlmHLS60K%Uiuujku!r_oGjTLige?j_PZ` zgb>YYjj5Qq(woKxgKYF&eMu;|z^U(V7D(vRHcOG117_N>vEYSyf($E*?5r#EU(W%{eNLnNgc zW!~FFJj|i`wsnpE<|JcYa}$la%})sFXvNazr>=c#&9+7+9kQXf!F_y2T5Z;3Vn*V+ zni*3?V=&31zC*L2w^nJqpq`M%Yt33Tr6t?fes%2kj;BEPvtga zY?yp1V(ew(G@mKDpBti85sfo@{Q)tGW$*Q`64z{W>jJqHkH#D}!*st|is!SjnIabH zwVliK5Y|oSBpG9-Ul^j==o}gk9nc488w)XGHb4K|3p6L^gvLx4tG2DFV&*j2%!!<1 z9y@*3-gUG}60=tGQ<=1KL#}1sDw~(xN8s4p|1VYt-Z^g^Rx)pdo%dG$ZC}qH^SO^^ zCK}Uv(7chhHz^*YnLIcBAhfCw<1gd!k?Zgap-k3h&RBNXPG89C!ezyJWTh2CS0y>g zg)yLoj9GSHYNm6?_xd|vo$$c)#=wuDkpk1$kXcA=Pko5b;m*uC38k3WY_B{p!(pDL zUhmV<=Gj|UhM#S`^H-xkh`Cg|xg_L6KhAV!H1sJpN7`wwx??bMU`y9XdS+|Vy>nT3 z>CiMsI@N8avjPh4$Zej0+8bZmJo$8tBzt4DhiUZk>CI1WOKeJQ^xHkcUI_&!m{rX^ zeOPruQ*wOO%{>EHD>P%37tHHheL6;$y)lickJaOLYNIAea5VjTTY|1JUCZ`LFd7&v;jXeUA{@T4ktjuT+1KT(BD<64`VZgp`vmzdO?7+-6jy!gO(H(j0;#-_m z+Mn`D+0%ThRy9=h-8$v-G!Sl#wvRk^vHbjEOB+n`@Q2^xN1hw?#+039X&_vrlaK$$ z-gm%fQKbLR?wbt>2`vFDVnjq#N*Ya2fgnX`Ld0??CL};KB$$GrDA*f{1v_>GRP0@` zdwSksxzqF1L+|vk<9T}46XpMXW}e-hop;~OdYa^Z`MV#;^L}T(^UTb%&&c-4sBUfHWR3g>N<+}&<+ zdu2bJm#SOB-(H#STygO}d+*bgd*3i?RiJn_r5XZ5YB)R^~%Q^T&SDMI=(&RqmowxiTrcY#6HSiHTa~ceU$AISF4~Kew>rL z4M-p-XXL%5#R!RxxeC%q zgHCrhb;DyszfrYw6)QR(3AzQ*cWCys%d^+i4$VH>b9K2rvb1elJGuCVYkTYIqozFf z&$aXO^fD!y+M(Icz~6Bh54+rw>pL|2R9OU{-{0rETV4eV;gx+BZ}d*j+_=~m-Jd;p z_2#`+1WoDcQKlS*J6%j~whf(er*0NXg#lwTZG$kY)i!h%xHHM-Yp%-CjZS4gGGV(m zX~skXc0736s43$Pn^JpRW!>Z&s;jK5WgXEe7}HEnr0iVPN$#!GSXERwO5Z{kd$oCC zZWraqW-ISlx2O+Lw$0^jt=E+B`Iw*&%$_ZsfNE=5qXJHVsAlzoi9f{)99hi5mhK7Y zVQ?Gt0(#F0?R|3T*lCsZ^;NYsQ!9^ctgLU4My5Jj)(#y*3C-#eeLIHt3)tel9J|8R zH3;vzYRyRMDbRZ`%e^K$9c6{y_br;%{mklh^l(;n^yQbRo%h>E^W}UGe+8KXiGaHt$}QVj!3WS zsqSe1nlkKv7P!n&oh|DtJCx9@9act)%NsstwwSzbOm*2D-Dkosdh&*vBD((R&_E8` z;Iy>!&(0TSYoX5SEk&UU!mi4fu`;HsmtgiE>`WBGaH+g;8PjDSMUNT%~N2-;e zPd>EhB#Yh|X@jn_uje|WtLl?F9;&ouy}%uh$!J#hc{jyS>8JEOVeX^eNon!R7QMRC z2HnTMY_W5=T??u!x7EaKox2``(5%k0rkVO4eo?8V`<^y>GnXF*j;pP2nATW7A0G}Q zuaT<(EbH&MVCgZ<>Mx(9nwEt;3{{3SaF-o=1asJ&|u6G;I9S7kne%>7w_ih>wOFXV0E^o(8t(;R;kI!Lxw|4pa zeUn?-x!ULuc4~-oNxxDTq34tQs(CL&A7_PkDb4FrYMIlPU$0ib$e0H2dehSYx>`*+ zu5L_OV|9aiEFk?#t$4bqLpY;Z`>U%vggaMSD=mI%qoWmG{G^|MzI~=Sz-^`jxRhq~ zfCr;J;EP{-fM28s_$tr?BsKo$wR6vr&3e{fjXvvN{(9Dbk+c3y;H zyBpiA=lx&N=e?k%hmf@MR2!V1&t2v&b%&wXvdwQy`WmRdXog>Ra-Z|wyvz9vO-viPyEipSPcIuy*NRGhvr`m|9z^J zv1&kgUQ2fnz2IPNu!Fe3?;yrCmXEBcsGG)jI;p~z^{jjEN{emQF5W zE$we@v;(9s$+9Q8_E$IX{oA;zC%h{WL2Fjed#Q=Fl5V;6-Y?YiQZAzOH26K8^hjfc z9BoJJsP1lkOS>O!=+OqdyT_B=Z**BhS!wN@Io0aHG*#TPhNT(ar?HyV`OZ!YzcH7( z+rta3TH)NcT2u9gVLqAaiabSE?7j%g%g%$Y%1<-2a=2FwCm;3{qNJt$m$txegZ@ij z?+o$Gk+Y7GW~N$O)^+VuP@2_qA8G#+JvZXjs-zCmp=W#e2y3E+r<^w;(>CZvb74or zN3@$2RB6jfq=z$_)rsCnw~n{8tvlRq1l^gOb$E`UMaY@Q#Il7`$`)1EmR0DNC1)~+A0ihPBpHOZfDH&Q_s9+xAf4V zjk;o0&=rHz{AJm02gjX0ot|c&IJtc$HtX*Jcs+-&)FZnwdBH=i^rG0{S9BhL=aRmFs_%V~m zR5#YomByvITGp|&u!_F=t0J1!1Md5&i>lmhI z^-wvhnO1eY9~i!xG}ZV^&N8$N{Rx5eRF$6}C?_g1J3mZLYNQIUV2*mJE*<@5i_RSA z<4|p|!^~7ubm|w?)ZBegNcFX>SsC1E`jO4**XL$f^HWUBYiM%nb$jkO5*=qXMNkE3 zFp13pJy${8(QaJ8j}b9fMi|=>Os7C&b|L4)Uben#9`0&(bM>QCM~ng)-W)dhFglHG zV0Fg`+btxFZXc(s@0vZ@(w%!7-4)>py>p*hi90-WsQnODy6)zk8cAr@rts1)-^B+S zL3n2_eKf?~Q+MXF`!_rtEntZ1w%x7ON`Cr^CEZ`BE2hjcP+B4Bj>vvuJko8 z!ahw!7+rbTZO>F)`E*aU+n4*BAC-D>GFv}liY$)I)$RHHj$8H)^hDnX>X{rwlaqAX zc)t}kDWPq3+F(QAO-fupa+?9w*0T21cZ1X^&DxnCl;V~E8pGny#_&^mXWnqU#UFmQ z(bcv5@YC&|v==|s^4i7v{*eZ&S)J(WpSog%oyaYta62jv=bE|wucOx6HnjA3GP`Z| zLdU_5m^``0pHepKn97Ed+D7b5%4;#H;+D09wxUkKYF2l;FvY&aDf=Wu$OTBU65cH9 zr}R|JRSH~hbZFZsAr`c>-_cyF4PN~g1^v!nEaNYIqncaRHMIE1bv%>Ste*GCPhNeL zV$tPKxjh;-V54VnLeOgI7M+0fL#A!e^Da*IylIuZOA}SuvUbmMKYL}kp5!&F&mH;S z-jXk^E32t5T{K_64Jz;O7&nTfFS^aiywv(i++L5n!qSCPj%k=$vB>LA9hwjbK`RJb z)F*dErftwCpGx-0DUIs8090ek`cwN9E=jaz^~m;FKlKieoFEUOu3ETXvcol5E|f5C z?Z}%lhJ&VB^+S9A29>&d{s!;;%k(s3@_aST!VUT%o(p^Tb$XHqi@&wB3)5H8+Mo-+ zo9x2wl$L6Ytw=IcxNx)I<2mT3F2+@gl6@xB|p`_+?n{#SuT=#KGfnbJ#GgVZ-c!Wzx3!{uSQQC>2AV6ZJH`=Sr;1a z<}#Yq-`4)G_#1WYLab`(-fb8%ZG--{CaHJxS8b4;soIv6XLy{?X;z;*=)d(jRX%Ob zAqRnzDvygF5q6s>)lgDixLLJ3S9kU%^R@iT;5#AHHt46x{bI@7vYMJoHQb|0Th@KF zCxzB?x{PM^(TzX#DV=*Ac1!0DQN!OklUH1q>iQPn2bx$`e~jnj4y`&7;@7W$=KUhu zB=J{3M^`Q|Ha^LwM=x%0vwGIHDW0|PMtF43zD4i$?F;v6gFVY)bp^yJb-NDpt$(Vx zW&MNR`cJ`XRzKLaIiGyU{>81hb_ZHs>eN)h?RDh){?0zs%ZR#`cD~-ov<*66W0><* zSNo6MsNR;9>m>P}OKMivJJ9)wH!<9c+s~O~hPfWCXBA>@OMBfe$g~Z5-7(=_Cv8ks zwyZzWbKYQQS6$t_k2bb6XE!HD=rOywJZXpemi9GT*xCktjh1KxeTkk$xw}G8rLp-S z?FylJo6Bg{zHQlm@f@OjeEoznY?v(9B#YH#u7I#U{2vTnc z5q8T%K2b~6aR!UyjuUxyY78FLW}|Plw0j@eHr@O0DcswA$V=6>tTmzT-Rw_zOEP}y zsF7Fk2mQ%guJ5knmka0JQ2ruChpot%V05X>bq2T*u=YfWVE!)kf*jmm&ppaj5{u(%39Xlj(dL8 z@SjdavyX}%P2oCWvqwkW*r&%@X@b`DSe7NWb|8Tr+36r*Sr_1MnxG3~J47rB5}LIk zAWN)hgN^amO1#yhgX3(QZd-verMGICo}w~sqsnw8imB`b1Afz|)$DX-_iY@f*0BaU z&R8dN^qc9n^FL&<)uCt6Zq>7RYgQfwwh;Mla4a&-H>jl z!=bL$3-$eutyZXWoE*nFY|*Js=3|Q-=NKpR#`l!RKdTo|v|a(vN`uvoa<)$_DRG=V zNcM3u5AByYq0iiklbjBJaxxPO`#2r)9p_#r)6U#BaRTZw+sV8paRO>WrVgI}*6Ufm za!`}m!<2ci*UkH5k5)VX4<|Y~PJ@$q_D7C0-pL%WT#0l$Ey;4N*K%GU%l+nfbvlEV z+oshlcP3eGhLc(KZ^s$xWbR(8gtDA})oOY~x$xg+hh6ypS4y`uv~>R~Zg$UhVQxkv;nurwY~8kllR3k2UQV|&(3kn%PsM7z z4)=K~R=MNw#p!?L3|_ROe+K_o%5>ZRV40r(A1u>*TA2cF{-4&nWPh|nuH&3>#6e5c zMf-onr9P#3!S-riaE*68#Qf>I*1H})w|!T~xzEX*vXA3zax%v_9S*q897WI-yY)`y z`8%M`+FzZ?OFXMlKiaj`MiFNP*2d6_~_m>^V z&hF~8uXHkpzL}`Dv#oSH8^v4^C}!&oU$5&1`yJ(E?pBphZDe{s5;h>$wF zo%Np6qojMPEEHHu+trZ zGq`K3mFe?sP^Md)%zj~{IMI52*n6E}Ph2v`*&RA18iwL;y4?lm`zpPB-?iR#^J)vm`)tWD zC-aO49Ow3Fxc5WuxJoacXuS?)Z5NpDeJ69Wo!vQ6w;%mIvG*SIUtLjyO}X_3NRM?# zId50(B6u^e_1eW2x|uudB{jDUTp_+_Jwq+sc}K^2$gy6)EnQ`I{nSFW|xBQJF__k1|f?gyvC15V~yjwBIoioeoHWXl4yIky)7&2@{?4sd{H0w{ z{L>s~vy*vSLE?l19j9?aZLO1ao0D09lAqAmlg@Ny_~107^)4}w9VTOjmTr^% z0xjy>*7MwtbGkWBnUgt{TU4MAYQ<~vMKG9CifL?O;VWup@o>NiTkrYH^*Jcnola(> zo!!OhFw@DrQ~td}{vDi{G0+V^OT{Wjyf#q!-mTVz?x#B!b$0f4iN?dw3Cy_(quZ}l z5&i3Q>ppB)rajJI8!%f=tC?*R-6lxnlsK7#oDM~Jys7-KH z=wn=JoEj%{@6T25^G(1Jk8CwZJg+0lWvA!iYBKD3%>UAN#IL$zoDPd<9+>NN#6!+M zs5=(8$FVIjIyspy+3C57m2^AeCnZs*=gPTDNoF7+R**T{(1V7VNa#T$9$i_l@qRGM%sdsmaBCq8FOjRvc-#ciPU{A-k){ zNY7}Ok&%&^(LN(9qkG1%jQui7GRAfV&pl{)eC|nCijk0d`t+FTX3?qicFg=~MPgX~Ki7WkW9HvJMgDulOut8p^a(rl`ByuCAR&&i_@BE3=RfzPv#sg5 zOP(JQ^n;9;<;WmCA%4_7W_l`9So*A(>1luOu=G2}Oi$le3rqiV{m_cYUq26SJJ`Sd zsH{==KN{uH+vCq|Pd_*P&$UCB2s`NgQI{0wp|#8ZbL-#Q>8+UkL1(hR>JQGeCgm=9 z4i^U94}Wew;+BK*^vY45T#jxr{fTy84{O&^*9Y1)&pl*0(65bZzke3JB&pk?AZ8f~ zkS?qYIWg1cq(~oSODd;((8FlYmZNe{JlnRf$vx@$kz`f9K0nu{KR10^OnanJeL}7^ zePgDl-Ot0)N7+;FtL3%AZ6ik{`(~7$V)vv#(&rDo^D>go%gEft=O#wxE}Wmc82Ask zD66v+^t&kidO77a)h*{?DCem7dejc_s<1^N8^$2^a+uL|*l z?3n4Zsa_%Jw~3j4n-uB$#Y|88JBQ^T_x#f4@}B>cCHtWhQ4YP2qaD7f93|~XX6=vP zdY_Ppse^XeBpoz<8DZ%7x%S*Hq73@jf$9`y&tWms4@;4Lrwsj-aWQCd%-L`Inv63>WSlv|Icr4LiV+>Kz^mBP;hc4{ zCAwH=kJ$eIcilhN5aaWb%-jqrf59^sQs7^;|Jq)tmubm9B+KicvYMlRYF;l-YVyBe z3u;l_KewxD(ZV*Tk$-VR{C}wM|J3>U1q=IYU(=#jj{n0W+vfF@=GES8U40g7ZkBOC zQ>CUE(>XK?O8;3Mc9v)R|I4*N%kt{cEVIVu)!x*({$HK%Hm_BF)h_R#wB+38|L_&6 zMcdHN>T-WIa?4KGf3PpKy<`czS&A9%1oK*{>=4|J?Yd@~0(I z?h#i0rt)t}e{;vvV|(`qD}Ph@)8jn%2un{(e%vE0zNz%IT*p1a($jJr_XvxpjS z7T;9)nu_;(5+TC$>q|Gn;+yh+T9)D-Vd*K%J;LH?xrlp&#W&TzH02+(Y{Nam^wY8o z_XvwupVd~3uy|Tl;T~b}v|PeH!s68jM-?M1zNzx*kMzUR(=rA32#cp>2<{OU-&Fge zWd!aKmcF+e2^khoO90#>ES?_myGL03TsIOjEdIbI;+yiXrt05R`=UqV?vaNdd_9F2 zYsqidOc{6Bl-lDe>n7Jo8ref}@D^_pXZCDK+TA13-qoyVa_QJKk8P~1 zZ;(_vze*o{ywRt6A0FJzBmC$SCN<7;Kg&_??r!XB(n>~ZT!LS!zJ963*EFav-nsf@ zsmLo-srC$^V#D=@y4q^Vr2a=SPY+>Ail6V$07ZRCJ4L>OL#TSbeY|{!1(^If-OHP+9stf`O{>gnaZjX|1USy|zlJI`bF3bLkF);G?pl$w0& z^-SVaDhKfk{~!PSQ;FD%)Y+5Te489*YLgB(evFOz8D>I#C@LEbpOv#aLFTzh!x zJ`Ae!nwy{Dc|k?v8q3{H=1G;$qmQ3!j>0_G3+Vc!DsV!O=X$95y-B*@s|4%A6VUgu zN^9rLsa7uJTfHPT-~Hm2e>y7@fl|Ar(QLJgSCBJZ%%)NqpZ*_iH%@ zdQ|P)F9_s8AC%yD)YLV#vaCYJ_^N1!em>2C@ZtfaOP{WkXyzKhZ4*0_u=-}e^3?fbp^1>p&%RdP?~Uwj@9XHIEUy_8S< zTR73Rl;53IgcCeY1Mu6u(PG=3#X-P+ zdAo>1fqi{l#LPf^j-XMmAD<)U0sH#9%5PNolw-n`J+dagS_?7M9 zoyG6)+ppiw;w51B#*A(6EM5cl_3bR)0;Y3H2gPrKq;p6I;ZGo`3DQCM3&;TyDf}IN zXLvYIe(=LDPafU}7Q(%8VcWZij=)_#{w|^$@Ln434(v{JiN7mwz81eHuzRC~;tPOh zXz@dU>73I+@%sVKQc&VCz^7|?BJf!nE(JbU!@mJOU&H0V*J`*5*spI-F(0^#7vEDH z2kf8EUByYjzWsLm%L)_VxD>G&pr{9N6|A;xl01fA$bx z1N;8iPy7JvpZ|U$4ZWMMufL$r;ZV0mhi&&4IlzAV=r6Vh_RHH}{5)V^e}SNJldr!((9qkx5og;4;uK)teud&}U_bvtLBk@yKPVEH0sHnW z64wCt^zttjHvtdQ@H${W{a|qquzx-Wi-&<}G)RYS4;D`XQy)zS;okxK_8uZ=tm~h@ zA>y?_`XPe8cj~u~q2hgDzyBF3{s~Oi6gq5ssQ5a--&_0`;O{MH*zEI%iH^WMRdS>s zCbj|g{bQKu0Zi8%Iw-z3@FWE#?hj1Y6gnt=5b)s&O1v*{rH01<`~CZHF$s8AFMha~ z4(zvw;o?YO-+zaT*}%R%hl?6u|N1ywEC3#(={pH{oQBT;K0w3g1G`58-#J{^Ppl8%{^GR& z9w0so;CzwccCNB~1!C6#E)@F)aFIAXfQ!Y#03Ik-1n?knQveSZzYX9aVp9MQ6+Z^> z-eL!L@F>eSObiKN^cMlVkC+$0`-+nTct3GT0FMwi2k z-)`VL41A}7?=tY+2ENC@_Zs*<1K)4p2Mqk6fgdvP!v=oD!0QeCsDU3d@Z$!4!oW`& z_$l#Zpg(xpz|R=?w+4RJz|R@@cLsjmz`r-}9}K*~z%Lm1MFYQN;Fk^jM+5)Kz^@qi zRRjOoz^@tjF9v?yz;77%O#}bcz#9$xmVw_k@ZSvlcLTp;;CBuD4+C#9@OuV+-@qRj z_(KDKWZ;ht{E2}#8~9TL|I@&q8TelY{@lP{82H}?{?fo-8Te}he`DZp4g8&f|6}0q z4ZOv`KN$E&18+63u!8N|vR(|dciY++z#~O4K4I|F4D1*<-N5Y(oMGTh1GhJDmVvVk z+`+&d4cy7VoekW@z&QraHE>r0cQf!d2Hw`d+ZlL!1Mgtq9Sz*wz&jbZhkp@s_010Q1GLk)bGfe$zEZwx%c zz(*MPNCVF_@KFXXGjO?qXBoJ{z?BA`ZQwZuo@?ML10QYRV+>qv;CTkFF>tMc=NtG~ z1J@b2-oOn8ZZz-$10QGLg$7<^;NuN^f`Jzs_(TJrWZ)$RUTWZz4Sb4~a340w`;Vs@ z_%s8bZs0Qve5QfVGVs|3KF7f48hDw3&ol7(23~I93k-arfiE)f#Rgts;7bgAsevyu z@Z|=+!oXJ=_$mXhH1O31zQ(}U8u&T`UvJgaEF#|tt z;3o|Hq?OCdQjA;!|4xTUX%a|VXy_Z0mZD|_I1V1VCA9LiYLx3iebSlJ)zQ5X-A`R^{yVtk{-yNGKT(;9*t zyHMQ2Sd}MN{Ejg_bI-y0thX5VleoY5oH3oY9DEZcofj`Cef`8PjFrBGz<1*0q419M ztxS24nR4*0si}eZ?Zhm`sy;i3M#ieXIpP$?v}Ps8&J$NKrZqP?_Fm#v##GE4yRY~y zV|ommV~-H8FjoHDOT5Q;n2awLKQN{>BRN=~(1jOIsQkN$o{Uv~JBT92s($;5k&Nfc z^uxqqf%IL(9LBV!AP3HI0%KZJkz)^(YdgAP!N6|7B+0Kx(wdO2qtx05l6@ItxeX31 z62x&b{wJ2OT*?xGGW-;lr?Nba<>@TXV0k9Xvsj+Z@*I}uvRuaUJeKFPT+Z?WmKUpBSFpT<<)tjKpiY+ea+X)HyprWrELXC;nk5$A$#mDUypHAdEN@_mh9G&XSl+~P zHOnDC+ZkG43yqD#DEbnLe0LuqiKEx6W17*1% zVY!~=qj(XS&N~*KRgwHr$Te|diKW7qa`;vu*Futi97{aN!!0F`WcedYTC?S)Kbg}D zOQm1R=^<(DTmo_?OIi_2m=@4_=}+PG7N<_v`IH`bke>cjPLH)N^Po0y z3a5uWgwjFEazJik{4u1L|7n~)!Rg`uvi^{=+>o;<9VES1LXuuu^3r1gpR{Wlr$@Vy z=^*eT zUdRfTeJDLJt%>u}pT+61P*bKy`hLm=IY)|Ef?8LGw%N_LkEN6XKXgiPUg??9-2U50YNZFnt z=|wJzC%^FQc>$;I#Ocvr%k+@aA0VYaK+@XF1Y~bL{e_&qGp9#CFVjOxdqPTkLVip2 zgCx6n`Cr88yKwpoIX$F2pOEr=LLNf-Lmr{$j|H>xeCBX^Tvv`IJ3z{EL&|bMPNejZ z)AaN!IDIas$Ms02hm`q4%KRb!L*<90cI}n_5>DTh)8jfO(?iOB1ac0ggOvRVWS~E} zl+$Bjv^;;f{>k)^viy*;{E+`5J&?4<*317gPLEI7%k;Qz%Jh)(yhF-*K+@}M2}n8* zUi!;9{kEJQ*ISt$QsxgS^M|Cj7ZQ-vF1_?uaQf{yJ+9L-J>;R3AEfka$oCm<*7LuT z({In|aebHRA!Yd?W%(h`rTif;)bqcJ)9=9PF)onlA!T|>bLCW$#j->REWA*gca{3;e9^)UG9#YmHQkDa9Rs!iEt02AecpazTnbTw3 zB-2C6ehpIgYmoFhZ32?chnN0(PM^o=ujBNPGCibB4_QI!A?bX0>2KilyKwsJIX$F2 zkC3t+kR2&KB=v`0`WrcYPfmXWr-zjN7^L)PNLs_4fIJe?OTUWK@5;5vLWr|-k**K&GDSszGwz9FT*Lk9f)7EZqhr@xugLrOn~lCbv@XFZV8FCgXh83y8OnA6|O=^@(nI2N6hoqNA6Oixd=^x?rdvp4SIX$H8FCnErL(;fD0oh(pzn;?%X|--pvb%IP6xdPtcb zlIEoe$ZS3R6PA1*D6y|4-*ZVkZi#->o)EqtNrab>MEGiIo~zsTX6IQ(l4{||>_N+bDsB$00~lE`-?hfm{h*}f1i{Tk&wfy0+D|2pQQi;#NI zM5LZSbNB}w{t1UmyFkx&WFN8vN$B5~B*Ld~cqxa=>jT2i;P7)e{AQ8}m)B+Jd7Q&v z7*3W?yptJ^VtfkY62_-89?keP#``lqo$(mPXdE)Xv5e1TJdW{MjK?!RoACjR z&tZHZ<8v8LV7!d+M8@Yap2YZk#*-N@XFP@R1&j}3d?Dkhj4xu0#wYD_G2>FkD;OWl z_!7p`8DGj6jaH_=j4>vQ5~I_Q_Q9ZC;wu=V^OE>V#<-YDd==vvjM3T1^ysW*{MC$) zWQ=)_jGxIE^B9SbVtgHAbn-I&^^9@xlK2M37+gtwBV$}#BwocB7h8#MVvLKP#281* z{4mIr7~^7zaZ!>O<6Mc+nMsUstHikYON?=-#2B1PjB%yJ)r{9Mp2ryDJsDra7~?mI zYZ+r4Ch>g6cQQVfF~&(UzK$`*JrdV5#yCde2F4hVNZiO6;|qxwFvfU6;^P?O`Y-W9 z#<)mGyofQb&k`Tc7}r~g(aFpDLcCm1hf{3K(v zcNzZ_W3+dPpJt5qF7Y#r(cUHgEn~EIiJxVB2IJ=#qrJ=c-!Vpem-uxVXynXzvog#2D>e;+Gj;!1#}h(cWeJpBSUPOZ*CB zw0DVLWsLSN@t+x^y-WNWW3+dP|H2sUUEX8Kb>Rypb{5 zyTorXMthg|ZN_Nt690`c+PlPmXM7#wcNn9+%lLO0qrFS~55{Qk5^rLR_Ac>zjM3gD zexLDb#vd?7dzbMaGDdrs_#?(>?-GB^80}r+PZ*=UOT3x!I>w(eMthg>|748zF7aoK z(cUHg7vnn_f6f@~UB-XG80}r+e=|mVm-tJ@Xzvn##Te~f;;$K_y-WNJW3+dPzh#W} zF7bDa(cUHg4`Z}iUrGsoloEa@CHzlH_??vSH!0y~Qo_HagkMPsf07b@BqjVuO8AYG@E0lJ zCsM*cq=a8c34f3hejp{zza>&0rQ-`m&6_syn8tw%M6Z%w6AI+tLix8y{w~rE{<<=wPK~u+lPEX&J1v z3|3kOD=kBmmLW>Z5T#{^(lSJ88KSfdQCfy5Ekl%+Axg_orDdqnGE`|9s4W=WYoXP{?sf z$@FbMy~!85hVBG8BjW>wAXTG3zquCA)7bbrsLompK_R$g9LxxhsYi{@9>yP&?I&iz?dS5`B}kD1?C zUIQKV0w;w!1>UOI?b!5FMHZ4felpeVw77FZXt3TYz%?-3-#s&iQu0v6bu9rzWpOib zeT#!#+W-c)cSV49?F8~JWp3@XE>DlfS&^4Bgqhb#1i3XB?Qc$s(Bz9R0yVdAJ2`|> zDb>EXDxK_#gKXc4RJcn?zK9~;D-g~I`5l7DTzW9?IvmVI@3;};UimpWtgRVZ-x1f) zZ>XWH-7UA7InBN5GS<$kf5xbjH8d+LP^ecIuhU^_a4T&D!a`hZ?JRo9VIkQyDxxa6 z8yUz4L}fG8$%5~>5{6uyxpr1KPhA(gtlu0cK)aZ-5)3|)Yp!{Vt5OwKFQjp$fIh9K z05UFs2yu16b(L+|=$fA*o9b$}f?n%)1Kfi$@HJ@Ez?n~ zg!k9I*W3;vCaXNU0e4c;W+9wEE~4PG^Hn7$bXZy|6R{=0`;k46OO z^;irXR*y3b-Z{Ws@!vgMeb*yE*N4Y&Vya8xID&Yb6X4--fw%uQ#k=}mG04&-mZm7*8iThCyq+QTecIsNo+95j4c>+n z`F?HiXw7Pv{c;fws%Mu?DR_Gtynm(OjWT#!fb&A?dziuNo(M1BF$S*>c;iC!(YsZ8 zJ?4YAX9({qgLh>Lee^{hUEjOlm51otXz)g(Gw2n<`_ACa1rJM@yu&*0$|Z*Tu}%G}NO5QEnqyhFXx`MjeIUO9MS?U&Zh>Gik{y!j#eE;V?a zaRCVHUv4pYE<3(@yagSQd9?Lv4RaX$6>ehFUR5Z(ZT zmzRNcq#?ZV2Jd+A#)R<74c-&r(KX6F-1B>a!RwysePG7`*Q7h1ffU*A9M8Y2Z%sm=0c8zqXyhD+iCR!S3PaJH+6< z4c-Ko1nKe)F?h63!l)45u?DXiyg?zn^92_9U_J6yYD;6&)>V^8p4Lho>S-I?b`6odB{Vn}?~d6pdWICv6Z--Z?w)dk0PM8oKj)icRnqV6YLVe2eq=J?19# zt?S9}D>uP=vlqXY+yrmd?)?646TIv8;P;H1;Qe(kevhdM-VXia<$DM^p*Viw_iqiN$vbvG z5Mt;%c4Rz1tuNvCW}C>jYJYw|wh3O@Sbh(-3ErjSh1eX!ey1GB@3l6eFLx5Zchm&$ z)G2tSCWig&X+ph++JwHR4(9jon&4#~%I}pn!K?cXzdzap?}sDQ`&I@`nEo>7D1IN* zAey`r%7uFGvkBfC75si@6TEeEaQ(oT%RJ0{??0N~%QT24@3?vVo@EofrSs$ULyyjcZTZTc7e6O(y-sC0x-eMEH!c)}yg$6CjU#>ij z-#;{n=K07tGhTaJcs9RJ*o3~kW%2Y~aDKe&^zj$)`+rU3`^`oCo?jEZd6)3}d`@4DJ!6~8~%gua7TW84|iJ_Z`& zza!TA-xt$Wn!J<1TcH#9x5>-7IUa8{c-O?xH~N-%`d*L8tG+d!KCw;+xK`3(*7p+d zu1{j&T5H&O&}~BeJ_b+R9y4F?Zi=CAZ>*n>Q;(Oxi=(gM&Up6Az`A@ixunCi%eCOe z@q>Ntj>r2ecyau+_MUjCZ| zj-M`lP6)V6(qWcw-`@#wV-hRbU)}*Pj^8&vFX+;mbeQ?>f{SIG>(R5|U6-USxqP$# z5YK);g7m0iaULzTtm~ zSH8vIjgHYio`|VWydE##5#UXUk?#dD^}QUE*ZGZj<(m?dcL8{D&hP8s9TlU#L*9(1 zZz*_(#?bdVcq3x)w)<;5-k~vhm&fG29+S7-#&~u)3cNV}yecN|L-69*ug_cYcynX& z*2d(07?aoM?Ra*n1}{#1*Tv**j>+r$w|M8b0lYZnyEi89%b2|4zsJkBAq8)eF|NB8 zyj+odn7rq}n~_WtCU4hw;_;Tmk2{ScFP*yeck zeIO>U+o$pBaV&U;$LQDo0N&9tcmw|#FW(Eni=*#*@Z$6bhkX{0_W*ct{3Z8a@p!f1 z#VOwlF?oA^9#7xdF?k<=7pJ}@U&P~G8fE$vFn^Gw|}Xc=xBt z>-23r-hi0A$uW7gF?q{l^6rSqdnqRGvzWY2-^H|FOy1;}yxN$&s|t{ zmpho#q{;g?c)Mxw?oX4qov_4SZloqnUI}=+Xz}h(lUD)W9&V&2P2PDi_1zw`d~bla zr&G4uTscyZ3}H{kVlGt;D* z?@l(plc2@BKTY09@Z#970=zi(TMk|vyF3Ek?rxzpX_oKZnEE>6Mecr@9`~oIZy0!S z@+}9ikE=wJroMAx>bncPo|+!_r>XCinE8GmlecS{CBGHx=I2T?-%{}M-AGNEywkvo zW9PfTi{l4xffvW`Z6_XYcktqzx5?ne@%y@%`CbNI9KU)Dyg2Rh-I)3^)8pBtKX`HM zG9A1)esBhO1)86@KTUsm0K7Q;={w-Xxz4n27mrs2UY!2w$e6sd!HeV1_kq{nHHIcl zyZj@jzD^nOuG9J8#W`8y-+{}2qk>JH?Z*#$m z)83ZFrpEgnzGt=_ z@Y9y?>YV}nxWW6o#&g>f@!kXv|CYEazXea%PvOM-#L$<9@1RjQ<$EfTaD?%)HQs58 z7Ru|Y@lKE6b=P=jMDTiPyfY(seKp=$5xioJcXkACxW+ptf;U>@og2ZMpz)SP@Jcn_ zc@exB8t?oFUWLY69>J^Dco#(Q8Z_R85xm73@1h9aX&Ue12;MS{w<3bKLgQT$!CR^E zE{))=(s-9e@YZR(%OiOAYP>5Vc5G~SvB zUSEy3HiB2I@otXb4cBO zyatVTR|Idd#=AR$cbdk#CxW+3XXXg11rQJr=>+r12h);BD4;Peky()Ob&7yzh;1 z-4^iN@#LroURQjFb_C*S{8tjeE7f?TBX}z`-u@B1S2f<42wqow-*yDzseEH2c%>R| zTm)~0#v32OdsX8d5W(v@$S>c45xi23Hz9(zLgP)0;JvExCPnbN;`_WK5Ks1-9KkEq zcvB*HE5M_8(sxhfMlkQF2;Mr4R~EtBtntbtczuWa`Ob>qRcpM82;Mr4R~f{_L~#Is|Jt!j(Bq;c+Y71sv>x4_&%_!@8}5L4Dd!Ep7K2=g11uRRY&kP zYP@+7yzcm}?+CS z(|8RLyv-V~F@o23q@VAC2wt_uJ1&B^4m{T`3nO@6YWfyM@QO$IWMDY4*yjLT5!!_QYBX|=u-fI!O85-{|5xi=R_j&|xvBrBNg11cLy&1t< zsqy|A!CR;CHb(H)YrMB2cpEg{+Y!8t8t-oryv-W#?-9H$8t*8azK!55)_C7V@Rn)3|3vUsYP|0wcI<86)LZPs`KV=+2toM?{MwrD&{9(>#p(kkKpyy zcw-`X!!;g;3MuoQpz+Y9r{vAhcxZYldDR*ZCQ8X$tnu(OC2yI=n-IZUsqrR8@YZR( zNfEsD8jrpqLPywn+o18LMDR9hyn`Zmn>F6l2;LTrH!Xsf4Wo5N*=b%;8o}$X@eYpQ z_0@ROBY49#-XRgZ2^#Ov2;K~hcUT0kTH_ra!CS2HeiOl4rtxM(@K$QPBO-X~G~SUB zy!9GyW(048#ycv4w^8GjMesIjyz&U%7L7M6f|rfP==xtp1h2cstBm0F)p)Zbc*8Z` zoCw|ojW;)fH$&r9MewRM-q8`f#TxIJ2;MS{R~^AysqyAT@YZR(nh4%{jaM7N+o190 zNANakykjGHn>Ait1aFJRtB>Giqmy_2uOWihUE?)I@cL@J1rfaA8t=FW-UN-eFoHKj z<1LEdRcpNCBY2B7-U$)BWg2gB1aGCrJ28T{PUD>v!CSBKmPGJ2XuPEnyp0;~LB6!_3-kA}+UK;PL2wq=} zcXkA?SmT`&!5gme&W+%W)_BVzcoQ_J^7co#(Qsx{t)5xfSC zcTogyvBtYNf_Iw6TM@xqrtvO`;H}VjmqzebYP`!Lc&jwt~3<6RxWdsX9I6T#c4@ve>FZPIwxMesIjyz3))UuwJ?B6wRg-i;Bw zG)#)z{%=(TFI(f?6v6AN@m5Fhx@){O5xia+Z*2sxug1GMf>*5ZZi(Ox*Lb%^@J4IA zbrHM?8t=9UUa7{rJ%TqwLqB@t%m_ZPs{CYP?d6>m2QUjW5C5fo}E~$87Kt2+QN}j<|_)VaFhe z)YcfhYcY9Wh%o&i-h#@ydirp3ZTZmy@^BOk9$b`PI5@v>XkK1E1qA-)~uQ=q_&VbJP_Ru1c5h;-yJy+Iu}uec-k} zFMdEI8ALh~3u>z>)GN?T>vHI-H(ons$ie{4F0ZYv7M3mFNn+vyjju1i@8B7?1c~)k zb80Fp@@CB~s}okbd^d^tKP=qltyAyXwqKCnSQAK*A>XFs6ib(0RNZUEq;G>Mjw9VO z8w5UG+FNi{MB2J;TaPceZOVN?ZvEWax&~o6^4%=fTDty)p?{rp{j4Cr=!q^d@$?&lYxBImyCcRuRfAA&qjwM@`XzL&|07mT~())%LBIWU-@ zy0&JHupQlaHDHGYv#;Gl%l8*_Umq! zxLQS_@C^Czu)n-L;;EY5g6X_e-4bJ5&GJPy&aL?PtcqDxk8U4GWmB>8WZBXj`Pvq< zH+6gTnY~62$PBUrwc%v#^mBac>7%AR_s_NSgUM!B*OtK>(&YPFoWa@io?1|F(K!Qy z%!=B^^6E;FmZrP$KFi;I=C>O+e-ot2lKcGq&{kNrHDGS-yvhNMFsm>>KmWM0x=O~g3x^a9URVKCU0GINIdlFoa|Tq@RiPuOt|}kk#`+;{5204W z+0B&8tXcH~rgDk)A318gC>@_yI&oT2VSWjfKW}VNUde!xz4pp0sjaA-Q(2RDa81?1 zyak1Y{Rj0g=s%%!8Y1Q|s;inaw;`|3tUdAyh7KLnuQ0!0NM32>!m|3j@iq7oeB->z zng;qktF~@_ZCzPICAK^Gx}{AhaL_qxd#1F%gDt14E6U6{l?@ZB${A6eWu+~vz-`Fk z#Afm@-;0Z_lM-|V6}TQznY!XHUB$L`AVJq23ZVbih4`B$X!%+iA{GS+&0bJsi!lM# zY~io9uj6z~w=EQ^$x_P;#8w<>D14f=Lv~k@k)F{mBO@a-qkTqJM)!+9eyCPhCB%Pho@l;QowUPDpmGjWE z*NKd6+qcWMyCHB^;gE%8e$GH9@5?9bgb|-5+;z1oeFq~xTe#~tReVQrc0hk8 z@B3AB5^_*KWe->t$LaV_%{QH7dm-kL1SlaA+(?FJb2!Gk$1=Z>B|WR5^z=-G5%HHV+U;g@sxN)CUJ!)Xm6>3@;KH*xsa z98PN-DBq4$KIEH668v5y5k8W`>6t5qAHw1EOo;e&FP*}da5&wAqHvnKQ}~@6PWO!| z{LdWz28Vye;qBo0#Lps0b|48py}M4~B^*AB!y7q#5r<#M;Wu*l8V>&*hrh|;Z*%w; z9G-@AL;5pFBHx`zBHsZVUc}*j$xdiW`6Ll0&p#$o^sGh4s7|V*bbP_6h4o{`)XqCV z^lzwK*r5LI9e#c4Ur|}!IA>;6&FosizpJZiD&60+>&oVNpsc*Su5y7J)v#!OWxWe9 z8gYM?)s@xE@nhy=1P2}Usd|~%MGWNkUz9gS5ogXU9Y3?Yv8uXaW?4f+T~&Ew168Dc z(Y%JTa?!tZJpC-Mt?pk|T~&q%j5z}~^RX(QkGb%E02|g1@XY21d8U&&SI%mnneFWA zvN=?yhB{fM`nmiol{+Mdlkd=f@+~@wmGJ($zD3h(lLr^}4wttp^W2Ex_%Rl~YaZm& zZW@X^6&%^m8AOx!EILlvpBX&LN7wfRDzuBiA!zd60q>F+yag~on7(mHtLJ+;cq24@ z?#1?CgZDak`nAqYV)8x#kMb}NlUIb3v6o2#o`wH<`HlpyDuh>K@SX!NFNAlZ!TSI_ z>Zi=(JOtpB&UeFe(T^3mK$AD(H@Zdd7zbV+3cMpix^O7$#+lc?VzE{Dc>k#RK z9ppj0Pw`*potCZobK<$-#G`d~F2+x>LgV35ArInpK^{796?ifnah()R;@!a0@4>AD zFYF%NVDPBCd7SoH@b2K>t^h^QVOBXCX{-%y&w~DKFzToh!t1rH_ z-R8xrE?j>D!OzI9Fdt-rtJ56|@20b2;I-Cfgk1ZldJ zwXErJ%U*d~#qn$U-PGacb9_y!d)!KzcE9;%(zROZTHS+~#CztcI9f-<);dDddUL;Z zFNm#cm##evxmjyEwJ%#uzwFhW5@q7CwA!@C>{|OV%U;uC-G;5==6-9^hfQD8V|9AB ztyC=+--@ueMfSln#c}cUG6O)k{M(zM5W}{c2im`&aGSj8`ptbq{e~ z-Xf)WH8ij2kuDyc}E_C;7zJOvLB`&mUU74Lr0CAI&<>DrBeFwnksQ)!~DjENsaR`jkwCKqU?e>?bJlcPXD;B z)1p1}v>jZH>7-IjgHqQ@h1V2+v)gU!DcsA-o{pcEWxwNAXp90&BgW>G=nj+1dJay&-+?ciBH<=?xmyFzhI_z&d_6KI<{v{))6wnzG3CI30 z!#!WJBq&0#Book`JN8E=Yy2dfUP@Vj8`_Tju^C@7VU*0GSlEdE#EeGyN@V#Gh}|5F zEmTE-@Qsn?*q=7VVrziu~1_o*G*x#8f&mcv@Li~Tsco;+)9Ug+{@6Bj7ND(H^j=d!qJ4h7) zcJU38?btsw#bSei`lCr@gP<^o-P$hDCI-zUgA^-+AX-?#_`zmzV3CfFZ6(n>lN1XJ z1Ure~+5}F5_(W1X8>JYtOUF(#qKBwr;QaVj>Fl7p4VE^U#%2LGJ&B7PN2!hk(e09= z$uI+zVGy5T#1Az~1jFPwc4iXIGt59?fzUpQ0K-U!#Q8ydR#H5QIa>86h|Ug17jW+i zukj7j)v-G?Nn^u++cAmDhC!Et=uSz|WSBw9Fo^GL#B(p}mk5U0#<9C3(LBQp!d*JY z&PgJ;hJnW*J~t_z4TF9K(Or#b?rGt_zG1d=>~2lc*f8L3lf-4ipld<&wnjAfrhbm7 z_zsS}T@npircEvxDJ;ZppA?H)%jO7oK>Q9#@myWj1m@NcS(wM%>rjY ze9xqKHVe8BMDJ=u51Kh`bitSjrSQ$k6Q^JRlIPgHqB&#`B4Z2!@@@usa6lny)YGwh z8=N7`fhVd=dpY**(Ht#Pkoy?qp#g=+w6|mL5#$u+GY8J7GVSBodq#7#OhMkuAQuD_ zBGWw`yRX41WDdMfW!l%V`$coKOhN8%kc$Eek!gR&9$;{a!70?wX})9UM{~4HK`t=J z0|N??X`y2m8XR&Y%G5ij#g1JR&CxOix!53+Bl!xE=^)1*XmH4ph~u5pA&xyLnxkb3 z@?e8Zj^ryurh7Z~kRYds9EmvIIUVlUL!&ubrXcTakjasJg~)VY#~y}RH{HnRX~pqR zef(w7DX(=6Oe+%F3}#~E!jjsW*;R8ekJ-n{Ar#6B$>rn#kPZ z=lIYer}y4+P_Ipa9PQgcz(nRIHMyXk6n7dOd$o_z3pw^09}mVv&tB`}AvBJ@*~ddM z$+K_qaX~(fD{s{T3NXd9*J%NTG|oav2Kl9ZdC!NgU%ve9?*gS&GrZEes`+Yuce`6B z-7E!vJ|rtE@%@mXSzLX}EGK1qC!*)YXKp(B>IdfqGO|tv0cIIvWy({s|CB=}hRpEf z^loeu9C8&oyBn8GL{IL`@5U!b)9AyS;T^zE=9MKl$Ag#QJRO)!^2Q!&iZ>ydf$NPn z$(xu=Kr#Jk-Xt@ghaV8+KClV=V{#KDHVT+il9_B3HO)IHIiAeoPxPjm1Rk7ld0-d# z=d@&!XBRcoD@|s&c0mh(ii490Y!@}#n{LMQ00qTiyP#bh(gca^0_LH~Oty=f?H!gJ zPj>O=dxx8Z;EWG;L9_f#GRd=xn()m?X234ml<$aS0^3DR`i?Z?gVR3v3wnc@O_10w zU>=psWV@(IUs-ZI*~Opsm79d%ybpFkXEZCB~d`YMtcu3g|SP*IsoV7sV!-)u8J zIHQAIFcq8A1c~he=GRmt&W7k}1wv`Gj~`(PK$$&N`Td3I5gzUpKK?4r&3 z<|PwQP=DH2W5gTtKG+2_vDzj`Y!@)+Co|bDYR-3Tay;3^pY+w4gy5_XcEOaaKAGg% zMa}sdk{PaD;4e_om`q^1s9E0vGoJfho`k_Jn5Z4s1c~he=E7tq+eJzCIDW#&V}C`i#dKw|PT-$&r(SGags1n(=7Q{j!E%U;Iq>H&zAm9wMJaJ*0;e(s2J_J*0>R+>huX#WW>cuZIkz!RMoT$RHX9KBk8Z zrh(Ywf#-f#4PQCq(p`p(3KU(<3P(0BoK`hQ%?qD!tEgM)yowL+J^s}EFN0QcH7YCZ zp6$&Gclq(yo>$$SdrKfIYflg`FI>ZOHT2u5riE*xDdaYCR(Nv~4}HBiDZC{qmIf!@ zobXn5H@6&NQ^Ivg9B*WzW`wsT5ui?+5Z;~?j}rRx!8?p-9+vR*3zum4$DPp}HU@}y zB@x*gYBG3tQZ$*vp9|h&#D`4j~mfp z)4wO8IcyJf5Kkr%*&b^0_f%3e*~6dvJ#EB?P5qup;&}E@Gr!*^5nOwyiQltH@oWz@ z?|aUO4x9Gb;u8@$8{ydVfwL zxb{#Jz1NcB*&b@1_ZK5NY?}9aG>7ehS>78-M7D>T<;Dk-*{uRy9GR17}bAucM~ zgB&)K`^w;iP2|3g=4hE>9`}tw4x7e(YjDD5ao1Cii4{*=@>kj_umJ>&}7ftouR0%p}uRPpsrMY37&-W7XOnT*&Al1ny5^ z!AvA&94$ob7*63a{RDc_)G3lOj@Bf04yW(~kqI<0=n_d8Cmbx638&ynp=yN5W^N>9 zoM?wNGvO3;@k$HE+T9{4<3uKw$%IpQ0nh}R)NUI|87H!^OeUP--C4yrcl$`nIMD&i zWx^@E_+$c2o_CC-j1!%(Tqc~t{(^-r6X-F-PEE1Ki7r?#6V76!rHCCR+97suQY<=uzKxQB_#r9d2Z~I@4-JdwX?A z8n5Q|xri?bjaPHsu81EU8n5Pl-4MTja=gFVZyONCBoW{o>Q3FZh#s3Nx=?I~=y9o{ zi^TSb9-k_@SnPo41Hz)!Jby<-ADAk-P;^K1gjCT*VkbmTOch-$dLVjIShTwTw=<$A zr;5ftDi|kBOBIcqONcH_6^%I?q7M#>=6eT-o}MZiccl@1NUG=}41=)5B2_frTtW0< zNzwYs$_b(!IEP1a#)%AYev^WO>!MtAnF-E}NX|IX9-JdmaBxkOda}SdGLkb+WP>v^ z1qatdsiy-tM@4eRiH_iug>Y!q8^#V&PbYB7BRS(lXK-ev;JEhb0!~FFXB=MH$AXI# z9M?X%;LMKXj1yhKnUjL!+NT>hb0az9#5Ukm;r+>>{w(1Q@#H@)zO*Lzx|NzGjIY5f zOJnfPFxL7VZM)-peTtAb=qh=B$XN{pWn14a@xR9ZwWL`{?w8xsu@qb3+_ETL-* z8h@!R*fjJ95TECr_spC*oqO+KxVxr$l6&9#KIb{_IcM&fGiT<`edfvJDS`&im!jp?=;7JlHsu^F$%vT9fntx!P?D<&qitxBq4#r#MDDb&v@sfHDosH}z+b1SJ~ z#muN3mDI4}BIVVvVqO$l)v)+4Z#}6z(H^}1$oUJ&lgfN3S+!&tC98rJMq&kU(*sddSJiMOF;IN(=Fp=kP~x^lPOwtZsPu08j7(Fa1G*tw4YjW>pgUiaE+ z_21gW+{_Cu$xR)s!-kamt@mx;zfS(g8(%y#-G-P~DN2>bo^Jb_{QG@>{T^wSXZ|ki z`y1|xZqzro-sdBl`LA)_-xAZzefxR;_B}gxpsSvlvkQIfrMGIz#}k(h)f&3fx9bKU zvBp#KRvK<*cG~who6(dcRCg>Ll(7WynooM>j|qv9WbWO;ND`9yPeb0{7>^@!+Ybhp zJC26fziF74F41vh&r69b`rOLlFgj$0Q6j&(qv&ZFMH6!4)9#5~p1GGPF_g^D2pCE+ z)7%S{7*FPBh?3*!{Zl?K4PyIVg7eZ+GcQ4}GCKFWY5&Cj16WNUvD?1?oLS+?&`P0J zcXa(;M%T{h)YP18=KUQpXihZq{#KoXjM8RdK)O<#@-fqmdN08-(`&}eHc061jYf@Z zWOmv2UzKs!3vY zO|B6Q{j)Umk9g;9;%Ez3b0W9{ReIH|AiTJMZY6Yv7i82K=Gn5*8Ri+5(J5Y(u{>9J z)hIuhv3@QG((3QdSe}OmQ{HbCQRRf7GDJ_8&%Ji;?mF=Bcz|4IP`A2>gJ?)~^p}H+ z^_N}sEdF9 z(aEmq_f|s`vvv?jSHVQ9vs^^07dNV_!E%w?7)ot78L92&2R`e2tcKFnQ=_`yg}Sha zLJBX|@e`*8lhX3J>znkS5&s>tE9$_;MrajHs$Pt?0&q$z(t$wtU<|qFGR|*MWSRh%BexhgddAVx3w*F z#i#f?hOH##&&Ma~c{1hj#1uI$gs%AfvS(R7Zc_1PTmGnirlBS}|HEYxHPJU42bLP; z_aywh_tk`7@P3f+YrJ14{5r?4cl-v&Z*=@7$8YwyGB7E~&2apgj^E<=t&ZR3`0bA0 z;r+!_1{+{0mGoyj{v5~ebo{yA*+jg{ytfm6t&@Mb<99j!`y79s<{KyvYcA*gSuy)P09Vl)x>`g7`5=lVtyBkpP|G;b5<+_aiI}0z&-d?ra!DD>UmWN%F3;p%5QF$!pr2HH$k9J6TSk@E3^7+TKD_I`)2D>~u zCgmY8EcK)PQXckpmV*`Tepsm=Hc>yOKPiuiM#`h#QXW>?4=e45UCjDnN9_7BFH3m{ z{z~~7S{`=@-2l`^4j{_RgG+!f?&q|?|DgCO#ksE#pUJr3x6^_@ zObh%&imz1sA+(kFU-lSn;EZ|4i}UDSlG%16PJ|K1Yi<{-)wB%fdK4w20GBi#Vf-uU33q@vVyQRs2(mKdSh*6@OasUnqW3 z@mCZ-qqv8IBkRr6qTWtg^l?b>#fsmk_{SBWP<)@_4=et8#g8cd6UARpd{Xfk7k9|<)>lS^M1>%X1MH3*IKgDlTAMwP;B1`fSPy7z`t#~Gm zDR0UdKBk>giOd$(pc;yqo=;Yf3xb{qQ%X@K!jylO=e!I=mqSU!M~1 zUWa!tcq>zQk15Y&@%gWBV9s^ZVF1XA(z93V8aG114=%6e8eL0P;BCFu3)id_c+afJ z7VpCKx(2NfZ}`Ky)^vE!!ngZNy}xdUL)Ycq4c<31@Mf&`yl-XT9m~jDgTZ$+L%g%# zeK!N|>olzzCphrt`p!22P1i!$&gGuGR%F}!x^hI|J= zU_I|>1iYm#34RB@G@e?UbO(5kq9Atn=vdc+&t2fvSkF7UaC7oGKP+E|*A?K^)6ta2 z!A)@ZIHi@8#%r>8tdA*;*J1HmLs}}Y%i>|#E-5WupT#rROv$^(>Blg5oxrcai}_4x zyj9>`hdlDkc1YtLvUoV%kd(%I(crX(+aOI&YL8Qv<3*KF~|o&FvIuMU$p`%!E0 zwm7^mZ4S?Q$eUG$_YI3TyA1D`#hX)xcf#WFdtu`CbKCb@i#JzTA#ab + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu2/device/driverlib/cla.c b/gpio_driverlib_cpu2/device/driverlib/cla.c new file mode 100644 index 0000000..d933af4 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cla.c @@ -0,0 +1,89 @@ +//########################################################################### +// +// FILE: cla.c +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cla.h" + +//***************************************************************************** +// +// CLA_setTriggerSource() +// +//***************************************************************************** +void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger) +{ + uint32_t srcSelReg; + uint32_t shiftVal; + + // + // Calculate the shift value for the specified task. + // + shiftVal = ((uint32_t)taskNumber * SYSCTL_CLA1TASKSRCSEL1_TASK2_S) % 32U; + + // + // Calculate the register address for the specified task. + // + if(taskNumber <= CLA_TASK_4) + { + // + // Tasks 1-4 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL1; + } + else + { + // + // Tasks 5-8 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL2; + } + + EALLOW; + + // + // Write trigger selection to the appropriate register. + // + HWREG(srcSelReg) &= ~((uint32_t)SYSCTL_CLA1TASKSRCSEL1_TASK1_M + << shiftVal); + HWREG(srcSelReg) = HWREG(srcSelReg) | ((uint32_t)trigger << shiftVal); + + EDIS; +} diff --git a/gpio_driverlib_cpu2/device/driverlib/cla.h b/gpio_driverlib_cpu2/device/driverlib/cla.h new file mode 100644 index 0000000..fee905c --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cla.h @@ -0,0 +1,984 @@ +//########################################################################### +// +// FILE: cla.h +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLA_H +#define CLA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cla_api CLA +//! \brief This module is used for configurating CLA. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "cpu.h" +#include "debug.h" +#include "inc/hw_cla.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CLA_NUM_EOT_INTERRUPTS (8U) + + +//***************************************************************************** +// +// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(), +// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt() +// as the taskFlags parameter. +// +//***************************************************************************** +#define CLA_TASKFLAG_1 (0x01U) //!< CLA Task 1 Flag +#define CLA_TASKFLAG_2 (0x02U) //!< CLA Task 2 Flag +#define CLA_TASKFLAG_3 (0x04U) //!< CLA Task 3 Flag +#define CLA_TASKFLAG_4 (0x08U) //!< CLA Task 4 Flag +#define CLA_TASKFLAG_5 (0x10U) //!< CLA Task 5 Flag +#define CLA_TASKFLAG_6 (0x20U) //!< CLA Task 6 Flag +#define CLA_TASKFLAG_7 (0x40U) //!< CLA Task 7 Flag +#define CLA_TASKFLAG_8 (0x80U) //!< CLA Task 8 Flag +#define CLA_TASKFLAG_ALL (0xFFU) //!< CLA All Task Flag + +//***************************************************************************** +// +//! Values that can be passed to CLA_getPendingTaskFlag(), +//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(), +//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt() +//! as the taskNumber parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TASK_1, //!< CLA Task 1 + CLA_TASK_2, //!< CLA Task 2 + CLA_TASK_3, //!< CLA Task 3 + CLA_TASK_4, //!< CLA Task 4 + CLA_TASK_5, //!< CLA Task 5 + CLA_TASK_6, //!< CLA Task 6 + CLA_TASK_7, //!< CLA Task 7 + CLA_TASK_8 //!< CLA Task 8 +} CLA_TaskNumber; + +#ifdef __TMS320C28XX__ // These enums are only accessible by C28x +//***************************************************************************** +// +//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_MVECT_1 = CLA_O_MVECT1, //!< Task Interrupt Vector 1 + CLA_MVECT_2 = CLA_O_MVECT2, //!< Task Interrupt Vector 2 + CLA_MVECT_3 = CLA_O_MVECT3, //!< Task Interrupt Vector 3 + CLA_MVECT_4 = CLA_O_MVECT4, //!< Task Interrupt Vector 4 + CLA_MVECT_5 = CLA_O_MVECT5, //!< Task Interrupt Vector 5 + CLA_MVECT_6 = CLA_O_MVECT6, //!< Task Interrupt Vector 6 + CLA_MVECT_7 = CLA_O_MVECT7, //!< Task Interrupt Vector 7 + CLA_MVECT_8 = CLA_O_MVECT8 //!< Task Interrupt Vector 8 +} CLA_MVECTNumber; + +//***************************************************************************** +// +//! Values that can be passed to CLA_setTriggerSource() as the \e trigger +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software + + CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1 + CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2 + CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3 + CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4 + CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT + CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1 + CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2 + CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3 + CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4 + CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT + CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1 + CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2 + CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3 + CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4 + CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT + CLA_TRIGGER_ADCD1 = 16U, //!< CLA Task Trigger Source is ADCD1 + CLA_TRIGGER_ADCD2 = 17U, //!< CLA Task Trigger Source is ADCD2 + CLA_TRIGGER_ADCD3 = 18U, //!< CLA Task Trigger Source is ADCD3 + CLA_TRIGGER_ADCD4 = 19U, //!< CLA Task Trigger Source is ADCD4 + CLA_TRIGGER_ADCDEVT = 20U, //!< CLA Task Trigger Source is ADCDEVT + + CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1 + CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2 + CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3 + CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4 + CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5 + + CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT + CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT + CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT + CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT + CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT + CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT + CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT + CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT + CLA_TRIGGER_EPWM9INT = 44U, //!< CLA Task Trigger Source is EPWM9INT + CLA_TRIGGER_EPWM10INT = 45U, //!< CLA Task Trigger Source is EPWM10INT + CLA_TRIGGER_EPWM11INT = 46U, //!< CLA Task Trigger Source is EPWM11INT + CLA_TRIGGER_EPWM12INT = 47U, //!< CLA Task Trigger Source is EPWM12INT + + + CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0 + CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1 + CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2 + + CLA_TRIGGER_MXINTA = 71U, //!< CLA Task Trigger Source is MXINTA + CLA_TRIGGER_MRINTA = 72U, //!< CLA Task Trigger Source is MRINTA + CLA_TRIGGER_MXINTB = 73U, //!< CLA Task Trigger Source is MXINTB + CLA_TRIGGER_MRINTB = 74U, //!< CLA Task Trigger Source is MRINTB + + CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT + CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT + CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT + CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT + CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT + CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT + + CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT + CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT + CLA_TRIGGER_EQEP3INT = 85U, //!< CLA Task Trigger Source is EQEP3INT + + + CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT + CLA_TRIGGER_SDFM2INT = 96U, //!< CLA Task Trigger Source is SDFM2INT + + + + CLA_TRIGGER_UPP1INT = 107U, //!< CLA Task Trigger Source is UPP1INT + + CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT + CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT + CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT + CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT + CLA_TRIGGER_SPITXCINT = 113U, //!< CLA Task Trigger Source is SPITXCINT + CLA_TRIGGER_SPIRXCINT = 114U, //!< CLA Task Trigger Source is SPIRXCINT + + + + + + CLA_TRIGGER_CLB1INT = 127, //!< CLA Task Trigger Source is CLB1INT + CLA_TRIGGER_CLB2INT = 128, //!< CLA Task Trigger Source is CLB2INT + CLA_TRIGGER_CLB3INT = 129, //!< CLA Task Trigger Source is CLB3INT + CLA_TRIGGER_CLB4INT = 130, //!< CLA Task Trigger Source is CLB4INT + +} CLA_Trigger; +#endif // __TMS320C28XX__ + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a CLA base address. +//! +//! \param base is the base address of the CLA controller. +//! +//! This function determines if a CLA controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CLA_isBaseValid(uint32_t base) +{ + return(base == CLA1_BASE); +} +#endif + +#ifdef __TMS320C28XX__ // These functions are only accessible from the C28x +//***************************************************************************** +// +//! Map CLA Task Interrupt Vector +//! +//! \param base is the base address of the CLA controller. +//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8) +//! the value of claIntVect can be any of the following: +//! - \b CLA_MVECT_1 - Task Interrupt Vector 1 +//! - \b CLA_MVECT_2 - Task Interrupt Vector 2 +//! - \b CLA_MVECT_3 - Task Interrupt Vector 3 +//! - \b CLA_MVECT_4 - Task Interrupt Vector 4 +//! - \b CLA_MVECT_5 - Task Interrupt Vector 5 +//! - \b CLA_MVECT_6 - Task Interrupt Vector 6 +//! - \b CLA_MVECT_7 - Task Interrupt Vector 7 +//! - \b CLA_MVECT_8 - Task Interrupt Vector 8 +//! \param claTaskAddr is the start address of the code for task +//! +//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is +//! triggered, the CLA loads the MVECTx register of the task in question +//! to the MPC (CLA program counter) and begins execution from that point. +//! The CLA has a 16-bit address bus, and can therefore, access the lower +//! 64 KW space. The MVECTx registers take an address anywhere in this space. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect, + uint16_t claTaskAddr) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + HWREGH(base + (uint16_t)claIntVect) = claTaskAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Hard Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a hard reset of the CLA and set all CLA registers +//! to their default state. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performHardReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Hard reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_HARDRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! Soft Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a soft reset of the CLA. This will stop the +//! current task, clear the MIRUN flag and clear all bits in the MIER register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performSoftReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Soft reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_SOFTRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! IACK enable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function enables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! IACK disable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function disables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) &= ~CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! Query task N to see if it is flagged and pending execution +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the interrupt flag register +//! corresponds to a CLA task. The corresponding bit is automatically set +//! when the task is triggered (either from a peripheral, through software, or +//! through the MIFRC register). The bit gets cleared when the CLA starts to +//! execute the flagged task. +//! +//! \return \b True if the queried task has been triggered but pending +//! execution. +// +//***************************************************************************** +static inline bool +CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIFR) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the interrupt flag register (MIFR) +//! +//! \return the value of Interrupt Flag Register (MIFR) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllPendingTaskFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Flag Register (MIFR) since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIFR); + + // + // Return the Interrupt Flag Register value + // + return(status); +} + +//***************************************************************************** +// +//! Get status of Task n Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the overflow flag register +//! corresponds to a CLA task, This bit is set when an interrupt overflow event +//! has occurred for the specific task. +//! +//! \return True if any of task interrupt overflow has occurred. +// +//***************************************************************************** +static inline bool +CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIOVF) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the Interrupt Overflow Flag Register +//! +//! \return the value of Interrupt Overflow Flag Register(MIOVF) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskOverflowFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return Interrupt Overflow Flag Register(MIOVF) since that is what + // was requested. + // + status = HWREGH(base + CLA_O_MIOVF); + + // + // Return the Interrupt Overflow Flag Register + // + return(status); +} + +//***************************************************************************** +// +//! Clear the task interrupt flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to clear all flags. +//! +//! This function is used to manually clear bits in the interrupt +//! flag (MIFR) register +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + //Modify protected register + // + EALLOW; + + // + // Clear the task interrupt flag + // + HWREGH(base + CLA_O_MICLR) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Force a CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be forced +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to force all tasks. +//! +//! This function forces a task through software. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Force the task interrupt. + // + HWREGH(base + CLA_O_MIFRC) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enable CLA task(s) +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to enable all tasks +//! +//! This function allows an incoming interrupt or main CPU software to +//! start the corresponding CLA task. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable CLA task + // + HWREGH(base + CLA_O_MIER) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disable CLA task interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to disable all tasks +//! +//! This function disables CLA task interrupt by setting the MIER register bit +//! to 0, while the corresponding task is executing this will have no effect +//! on the task. The task will continue to run until it hits the MSTOP +//! instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Disable CLA task interrupt + // + HWREGH(base + CLA_O_MIER) &= ~taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Get the value of a task run status +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the Interrupt Run Status +//! Register which indicates whether the task is currently executing +//! +//! \return True if the task is executing. +// +//***************************************************************************** +static inline bool +CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIRUN) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get the value of all task run status +//! +//! \param base is the base address of the CLA controller. +//! +//! This function indicates which task is currently executing. +//! +//! \return the value of Interrupt Run Status Register (MIRUN) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskRunStatus(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Run Status Register since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIRUN); + + // + // Return the Interrupt Run Status Register (MIRUN) + // + return(status); +} +#endif // #ifdef __TMS320C28XX__ + +// +// These functions are accessible only from the CLA (Type - 1/2) +// +#if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) +//***************************************************************************** +// +//! Enable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be enabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to enable software interrupts of all tasks +//! +//! This function enables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1SOFTINTEN register. By setting a task's SOFTINT bit, you disable its +//! ability to generate an end-of-task interrupt +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) |= taskFlags; + + __medis(); +} + +//***************************************************************************** +// +//! Disable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be disabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to disable software interrupts of all +//! tasks +//! +//! This function disables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 0 to the task's bit in the +//! CLA1SOFTINTEN register. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Disabling a given task's software interrupt ability allows that +//! task to generate an End-of-Task interrupt to the main CPU. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) &= ~taskFlags; + + __medis(); +} +//***************************************************************************** +// +//! Force a particular Task's Software Interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the task's whose software +//! interrupts are to be forced, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to force software interrupts for all tasks +//! +//! This function forces the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1INTFRC register. +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! -# This function will set the INTFRC bit for a task, but does not check +//! that its SOFTINT bit is set. It falls to the user to ensure that software +//! interrupt for a given task is enabled before it can be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Force Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTFRC) |= taskFlags; + + __medis(); +} + +#endif // #if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) + +// +// These functions can only be called from the C28x +// +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! Configures CLA task triggers. +//! +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. +//! \param trigger is the trigger source to be assigned to the selected task. +//! +//! This function configures the trigger source of a CLA task. The +//! \e taskNumber parameter indicates which task is being configured, and the +//! \e trigger parameter is the interrupt source from a specific peripheral +//! interrupt (or software) that will trigger the task. +//! +//! \return None. +// +//***************************************************************************** +extern void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger); + +#endif //#ifdef __TMS320C28XX__ +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLA_H diff --git a/gpio_driverlib_cpu2/device/driverlib/clb.c b/gpio_driverlib_cpu2/device/driverlib/clb.c new file mode 100644 index 0000000..2e79cb4 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/clb.c @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: clb.c +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "clb.h" + +//***************************************************************************** +// +// CLB_configCounterLoadMatch +// +//***************************************************************************** +void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, uint32_t match2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + switch(counterID) + { + case CLB_CTR0: + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2); + break; + + case CLB_CTR1: + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2); + break; + + case CLB_CTR2: + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2); + break; + + default: + // + // Invalid counterID value + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// CLB_clearFIFOs +// +//***************************************************************************** +void CLB_clearFIFOs(uint32_t base) +{ + uint16_t i; + + ASSERT(CLB_isBaseValid(base)); + + for(i = 0U; i < CLB_FIFO_SIZE; i++) + { + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U; + } + + HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U; +} + +//***************************************************************************** +// +// CLB_writeFIFOs +// +//***************************************************************************** +void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Clear the FIFO and pointer + // + CLB_clearFIFOs(base); + + // + // Write data into the FIFO. + // + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0U)) = pullData[0U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1U)) = pullData[1U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2U)) = pullData[2U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3U)) = pullData[3U]; +} + +//***************************************************************************** +// +// CLB_readFIFOs +// +//***************************************************************************** +void CLB_readFIFOs(uint32_t base , uint32_t pushData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Read data from the FIFO. + // + pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0U)) ; + pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1U)) ; + pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2U)) ; + pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3U)) ; +} + + diff --git a/gpio_driverlib_cpu2/device/driverlib/clb.h b/gpio_driverlib_cpu2/device/driverlib/clb.h new file mode 100644 index 0000000..37cb68f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/clb.h @@ -0,0 +1,1290 @@ +//########################################################################### +// +// FILE: clb.h +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLB_H +#define CLB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup clb_api CLB +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clb.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Address offsets from LOGICCFG to LOGICCTL and DATAEXCH register memory maps +// +//***************************************************************************** +#define CLB_LOGICCTL 0x0100U +#define CLB_DATAEXCH 0x0200U + +//***************************************************************************** +// +// Address offsets for CLB-internal memory space +// +//***************************************************************************** +#define CLB_ADDR_COUNTER_0_LOAD 0x0U +#define CLB_ADDR_COUNTER_1_LOAD 0x1U +#define CLB_ADDR_COUNTER_2_LOAD 0x2U + +#define CLB_ADDR_COUNTER_0_MATCH1 0x4U +#define CLB_ADDR_COUNTER_1_MATCH1 0x5U +#define CLB_ADDR_COUNTER_2_MATCH1 0x6U + +#define CLB_ADDR_COUNTER_0_MATCH2 0x8U +#define CLB_ADDR_COUNTER_1_MATCH2 0x9U +#define CLB_ADDR_COUNTER_2_MATCH2 0xAU + +#define CLB_ADDR_HLC_R0 0xCU +#define CLB_ADDR_HLC_R1 0xDU +#define CLB_ADDR_HLC_R2 0xEU +#define CLB_ADDR_HLC_R3 0xFU + +#define CLB_ADDR_HLC_BASE 0x20U +#define CLB_NUM_HLC_INSTR 31U + +//***************************************************************************** +// +// PUSH/PULL FIFO size (32-bit registers) +// +//***************************************************************************** +#define CLB_FIFO_SIZE 4U + +//***************************************************************************** +// +// Key to enable writes to the CLB registers +// +//***************************************************************************** +#define CLB_LOCK_KEY 0x5A5AU + +//***************************************************************************** +// +// Shift and masks needed by the API for Input selection +// +//***************************************************************************** +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M 0x20U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S 28U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM (uint32_t)1U + +//***************************************************************************** +// +//! Values that can be passed to control the CLB output enable signal. It can +//! be passed to CLB_setOutputMask() as the \e outputMask parameter. +// +//***************************************************************************** +#define CLB_OUTPUT_00 0x00000001U //!< Mask for CLB OUTPUT ENABLE/DISABLE 0 +#define CLB_OUTPUT_01 0x00000002U //!< Mask for CLB OUTPUT ENABLE/DISABLE 1 +#define CLB_OUTPUT_02 0x00000004U //!< Mask for CLB OUTPUT ENABLE/DISABLE 2 +#define CLB_OUTPUT_03 0x00000008U //!< Mask for CLB OUTPUT ENABLE/DISABLE 3 +#define CLB_OUTPUT_04 0x00000010U //!< Mask for CLB OUTPUT ENABLE/DISABLE 4 +#define CLB_OUTPUT_05 0x00000020U //!< Mask for CLB OUTPUT ENABLE/DISABLE 5 +#define CLB_OUTPUT_06 0x00000040U //!< Mask for CLB OUTPUT ENABLE/DISABLE 6 +#define CLB_OUTPUT_07 0x00000080U //!< Mask for CLB OUTPUT ENABLE/DISABLE 7 +#define CLB_OUTPUT_08 0x00000100U //!< Mask for CLB OUTPUT ENABLE/DISABLE 8 +#define CLB_OUTPUT_09 0x00000200U //!< Mask for CLB OUTPUT ENABLE/DISABLE 9 +#define CLB_OUTPUT_10 0x00000400U //!< Mask for CLB OUTPUT ENABLE/DISABLE 10 +#define CLB_OUTPUT_11 0x00000800U //!< Mask for CLB OUTPUT ENABLE/DISABLE 11 +#define CLB_OUTPUT_12 0x00001000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 12 +#define CLB_OUTPUT_13 0x00002000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 13 +#define CLB_OUTPUT_14 0x00004000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 14 +#define CLB_OUTPUT_15 0x00008000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 15 +#define CLB_OUTPUT_16 0x00010000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 16 +#define CLB_OUTPUT_17 0x00020000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 17 +#define CLB_OUTPUT_18 0x00040000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 18 +#define CLB_OUTPUT_19 0x00080000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 19 +#define CLB_OUTPUT_20 0x00100000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 20 +#define CLB_OUTPUT_21 0x00200000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 21 +#define CLB_OUTPUT_22 0x00400000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 22 +#define CLB_OUTPUT_23 0x00800000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 23 +#define CLB_OUTPUT_24 0x01000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 24 +#define CLB_OUTPUT_25 0x02000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 25 +#define CLB_OUTPUT_26 0x04000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 26 +#define CLB_OUTPUT_27 0x08000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 27 +#define CLB_OUTPUT_28 0x10000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 28 +#define CLB_OUTPUT_29 0x20000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 29 +#define CLB_OUTPUT_30 0x40000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 30 +#define CLB_OUTPUT_31 0x80000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 31 + +//***************************************************************************** +// +//! Values that can be passed to select CLB input signal +// +//***************************************************************************** +typedef enum +{ + CLB_IN0 = 0, //!< Input 0 + CLB_IN1 = 1, //!< Input 1 + CLB_IN2 = 2, //!< Input 2 + CLB_IN3 = 3, //!< Input 3 + CLB_IN4 = 4, //!< Input 4 + CLB_IN5 = 5, //!< Input 5 + CLB_IN6 = 6, //!< Input 6 + CLB_IN7 = 7 //!< Input 7 +} CLB_Inputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB output signal. It can be passed to +//! CLB_configOutputLUT() as the \e outID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_OUT0 = 0, //!< Output 0 + CLB_OUT1 = 1, //!< Output 1 + CLB_OUT2 = 2, //!< Output 2 + CLB_OUT3 = 3, //!< Output 3 + CLB_OUT4 = 4, //!< Output 4 + CLB_OUT5 = 5, //!< Output 5 + CLB_OUT6 = 6, //!< Output 6 + CLB_OUT7 = 7 //!< Output 7 +} CLB_Outputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB counter. It can be passed to +//! CLB_configCounterLoadMatch() as the \e counterID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_CTR0 = 0, //!< Counter 0 + CLB_CTR1 = 1, //!< Counter 1 + CLB_CTR2 = 2 //!< Counter 2 +} CLB_Counters; + +//***************************************************************************** +// +//! Values that can be passed to CLB_getRegister() as the \e registerID +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_REG_HLC_R0 = CLB_O_DBG_R0, //!< HLC R0 register + CLB_REG_HLC_R1 = CLB_O_DBG_R1, //!< HLC R1 register + CLB_REG_HLC_R2 = CLB_O_DBG_R2, //!< HLC R2 register + CLB_REG_HLC_R3 = CLB_O_DBG_R3, //!< HLC R3 register + CLB_REG_CTR_C0 = CLB_O_DBG_C0, //!< Counter 0 register + CLB_REG_CTR_C1 = CLB_O_DBG_C1, //!< Counter 1 register + CLB_REG_CTR_C2 = CLB_O_DBG_C2 //!< Counter 2 register +} CLB_Register; + +//***************************************************************************** +// +//! Values that can be passed to CLB_selectInputFilter() as the \e filterType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_FILTER_NONE = 0, //!< No filtering + CLB_FILTER_RISING_EDGE = 1, //!< Rising edge detect + CLB_FILTER_FALLING_EDGE = 2, //!< Falling edge detect + CLB_FILTER_ANY_EDGE = 3 //!< Any edge detect +} CLB_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGPInputMux() as the \e gpMuxCfg +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GP_IN_MUX_EXTERNAL = 0, //!< Use external input path + CLB_GP_IN_MUX_GP_REG = 1 //!< Use CLB_GP_REG bit value as input +} CLB_GPInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configLocalInputMux() as the +//! \e localMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_LOCAL_IN_MUX_GLOBAL_IN = 0, //!< Global input mux selection + CLB_LOCAL_IN_MUX_EPWM_DCAEVT1 = 1, //!< EPWMx DCAEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCAEVT2 = 2, //!< EPWMx DCAEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT1 = 3, //!< EPWMx DCBEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT2 = 4, //!< EPWMx DCBEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCAH = 5, //!< EPWMx DCAH + CLB_LOCAL_IN_MUX_EPWM_DCAL = 6, //!< EPWMx DCAL + CLB_LOCAL_IN_MUX_EPWM_DCBH = 7, //!< EPWMx DCBH + CLB_LOCAL_IN_MUX_EPWM_DCBL = 8, //!< EPWMx DCBL + CLB_LOCAL_IN_MUX_EPWM_OST = 9, //!< EPWMx OST + CLB_LOCAL_IN_MUX_EPWM_CBC = 10, //!< EPWMx CBC + CLB_LOCAL_IN_MUX_ECAP_ECAPIN = 11, //!< ECAPx ECAPIN + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT = 12, //!< ECAPx ECAP_OUT + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN = 13, //!< ECAPx ECAP_OUT_EN + CLB_LOCAL_IN_MUX_ECAP_CEVT1 = 14, //!< ECAPx CEVT1 + CLB_LOCAL_IN_MUX_ECAP_CEVT2 = 15, //!< ECAPx CEVT2 + CLB_LOCAL_IN_MUX_ECAP_CEVT3 = 16, //!< ECAPx CEVT3 + CLB_LOCAL_IN_MUX_ECAP_CEVT4 = 17, //!< ECAPx CEVT4 + CLB_LOCAL_IN_MUX_EQEP_EQEPA = 18, //!< EQEPx EQEPA + CLB_LOCAL_IN_MUX_EQEP_EQEPB = 19, //!< EQEPx EQEPB + CLB_LOCAL_IN_MUX_EQEP_EQEPI = 20, //!< EQEPx EQEPI + CLB_LOCAL_IN_MUX_EQEP_EQEPS = 21, //!< EQEPx EQEPS + CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC = 22, //!< CPU1.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC = 23, //!< CPU2.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU1_HALT = 24, //!< CPU1.HALT + CLB_LOCAL_IN_MUX_CPU2_HALT = 25, //!< CPU2.HALT +} CLB_LocalInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGlobalInputMux() as the +//! \e globalMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GLOBAL_IN_MUX_EPWM1A = 0, //!< EPWM1A + CLB_GLOBAL_IN_MUX_EPWM1A_OE = 1, //!< EPWM1A trip output + CLB_GLOBAL_IN_MUX_EPWM1B = 2, //!< EPWM1B + CLB_GLOBAL_IN_MUX_EPWM1B_OE = 3, //!< EPWM1B trip output + CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO = 4, //!< EPWM1 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD = 5, //!< EPWM1 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR = 6, //!< EPWM1 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM1_TBCLK = 7, //!< EPWM1 TBCLK + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA = 8, //!< EPWM1 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB = 9, //!< EPWM1 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC = 10, //!< EPWM1 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD = 11, //!< EPWM1 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM1A_AQ = 12, //!< EPWM1A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_AQ = 13, //!< EPWM1B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1A_DB = 14, //!< EPWM1A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_DB = 15, //!< EPWM1B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM2A = 16, //!< EPWM2A + CLB_GLOBAL_IN_MUX_EPWM2A_OE = 17, //!< EPWM2A trip output + CLB_GLOBAL_IN_MUX_EPWM2B = 18, //!< EPWM2B + CLB_GLOBAL_IN_MUX_EPWM2B_OE = 19, //!< EPWM2B trip output + CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO = 20, //!< EPWM2 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD = 21, //!< EPWM2 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR = 22, //!< EPWM2 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM2_TBCLK = 23, //!< EPWM2 TBCLK + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA = 24, //!< EPWM2 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB = 25, //!< EPWM2 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC = 26, //!< EPWM2 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD = 27, //!< EPWM2 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM2A_AQ = 28, //!< EPWM2A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_AQ = 29, //!< EPWM2B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2A_DB = 30, //!< EPWM2A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_DB = 31, //!< EPWM2B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM3A = 32, //!< EPWM3A + CLB_GLOBAL_IN_MUX_EPWM3A_OE = 33, //!< EPWM3A trip output + CLB_GLOBAL_IN_MUX_EPWM3B = 34, //!< EPWM3B + CLB_GLOBAL_IN_MUX_EPWM3B_OE = 35, //!< EPWM3B trip output + CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO = 36, //!< EPWM3 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD = 37, //!< EPWM3 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR = 38, //!< EPWM3 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM3_TBCLK = 39, //!< EPWM3 TBCLK + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA = 40, //!< EPWM3 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB = 41, //!< EPWM3 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC = 42, //!< EPWM3 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD = 43, //!< EPWM3 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM3A_AQ = 44, //!< EPWM3A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_AQ = 45, //!< EPWM3B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3A_DB = 46, //!< EPWM3A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_DB = 47, //!< EPWM3B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM4A = 48, //!< EPWM4A + CLB_GLOBAL_IN_MUX_EPWM4A_OE = 49, //!< EPWM4A trip output + CLB_GLOBAL_IN_MUX_EPWM4B = 50, //!< EPWM4B + CLB_GLOBAL_IN_MUX_EPWM4B_OE = 51, //!< EPWM4B trip output + CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO = 52, //!< EPWM4 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD = 53, //!< EPWM4 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR = 54, //!< EPWM4 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM4_TBCLK = 55, //!< EPWM4 TBCLK + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA = 56, //!< EPWM4 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB = 57, //!< EPWM4 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC = 58, //!< EPWM4 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD = 59, //!< EPWM4 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM4A_AQ = 60, //!< EPWM4A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_AQ = 61, //!< EPWM4B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4A_DB = 62, //!< EPWM4A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_DB = 63, //!< EPWM4B DB submodule output + + CLB_GLOBAL_IN_MUX_CLB_AUXSIG0 = 64, //!< CLB X-BAR AUXSIG0 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG1 = 65, //!< CLB X-BAR AUXSIG1 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG2 = 66, //!< CLB X-BAR AUXSIG2 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG3 = 67, //!< CLB X-BAR AUXSIG3 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG4 = 68, //!< CLB X-BAR AUXSIG4 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG5 = 69, //!< CLB X-BAR AUXSIG5 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG6 = 70, //!< CLB X-BAR AUXSIG6 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG7 = 71, //!< CLB X-BAR AUXSIG7 + +} CLB_GlobalInputMux; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +// +//! +//! Checks the CLB base address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CLB_isBaseValid(uint32_t base) +{ + return( + (base == CLB1_BASE) || + (base == CLB2_BASE) || + (base == CLB3_BASE) || + (base == CLB4_BASE) + ); +} + +//***************************************************************************** +// +//! +//! Checks the CLB internal memory address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the address is valid and \b false otherwise. +// +//***************************************************************************** +static inline bool CLB_isAddressValid(uint32_t address) +{ + return(address <= (CLB_ADDR_HLC_BASE + CLB_NUM_HLC_INSTR)); +} +#endif + +//***************************************************************************** +// +//! Set global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Clear global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function disables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) &= ~CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enable CLB lock. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the lock bit of the lock register. The lock can only +//! be set once and can only be cleared by a device reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableLock(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Setting the lock bit requires key 0x5A5A to be written at the same time + // + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOCK) = + (uint32_t)CLB_LOCK_LOCK | ((uint32_t)CLB_LOCK_KEY << CLB_LOCK_KEY_S); + EDIS; +} + +//***************************************************************************** +// +//! Write value to address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param address is the address of CLB internal memory. +//! \param value is the value to write to specified address. +//! +//! This function writes the specified value to CLB internal memory. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_writeInterface(uint32_t base, uint32_t address, + uint32_t value) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(CLB_isAddressValid(address)); + + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_ADDR) = address; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_DATA) = value; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_LOAD_EN; + EDIS; +} + +//***************************************************************************** +// +//! Select input filter type. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param filterType is the selected type of filter applied to the input. +//! +//! This function configures the filter selection for the specified input. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e filterType parameter can have one enumeration value from +//! CLB_FilterType. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectInputFilter(uint32_t base, CLB_Inputs inID, + CLB_FilterType filterType) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 2-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID << 1; + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) & + ~(CLB_INPUT_FILTER_FIN0_M << shiftVal)) | + ((uint16_t)filterType << shiftVal); +} + +//***************************************************************************** +// +//! Enables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function enables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) |= + (1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Disables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function disables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) &= + ~(1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Configures the general purpose input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param gpMuxCfg is the mux selection for the general purpose input mux. +//! +//! This function configures the general purpose input mux. The \e gpMuxCfg +//! parameter can select either the use of an external input signal +//! (\b CLB_GP_IN_MUX_EXTERNAL) or the use of the corresponding CLB_GP_REG bit +//! as an input (\b CLB_GP_IN_MUX_GP_REG). +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \sa CLB_setGPREG() to write to the CLB_GP_REG. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGPInputMux(uint32_t base, CLB_Inputs inID, + CLB_GPInputMux gpMuxCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) & + ~(CLB_IN_MUX_SEL_0_SEL_GP_IN_0 << (uint16_t)inID)) | + ((uint16_t)gpMuxCfg << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Sets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param gpRegVal is the value to be written to CLB_GP_REG. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setGPREG(uint32_t base, uint32_t gpRegVal) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG) = gpRegVal; +} + +//***************************************************************************** +// +//! Gets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return CLB_GP_REG value. +// +//***************************************************************************** +static inline uint32_t CLB_getGPREG(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG)); +} + +//***************************************************************************** +// +//! Configures the local input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param localMuxCfg is the mux selection for the local input mux. +//! +//! This function configures the local input mux for the specified input +//! signal. +//! +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e localMuxCfg parameter can have one enumeration value from +//! CLB_LocalInputMux. +//! +//! \note The local input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLocalInputMux(uint32_t base, CLB_Inputs inID, + CLB_LocalInputMux localMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each local input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } + else + { + // + // Calculating shift amount for inputs > input3 + // + shiftVal -= 4U * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Configures the global input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param globalMuxCfg is the mux selection for the global input mux. +//! +//! This function configures the global input mux for the specified input +//! signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e globalMuxCfg parameter can have one enumeration value from +//! CLB_GlobalInputMux. +//! +//! \note The global input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGlobalInputMux(uint32_t base, CLB_Inputs inID, + CLB_GlobalInputMux globalMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } + else + { + shiftVal -= 4U * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Controls the output enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outputMask is a mask of the outputs to be enabled. +//! \param enable is a switch to decide if the CLB outputs need to be enabled +//! or not. +//! +//! This function is used to enable and disable CLB outputs by writing a mask +//! to CLB_OUT_EN. Each bit corresponds to a CLB output. When a bit is 1, the +//! corresponding output is enabled; when a bit is 0, the output is disabled. +//! +//! The \e outputMask parameter takes a logical OR of any of the CLB_OUTPUT_0x +//! values that correspond to the CLB OUTPUT ENABLE for the respective outputs. +//! The \e enable parameter can have one of the values from: +//! false: Disable the respective CLB outputs +//! true: Enable the respective CLB outputs +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setOutputMask(uint32_t base, uint32_t outputMask , + bool enable) +{ + ASSERT(CLB_isBaseValid(base)); + + if(enable == true) + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) |= outputMask; + } + else + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) &= ~outputMask; + } +} + +//***************************************************************************** +// +//! Reads the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the value in the interrupt tag register which is a 6-bit +//! constant set by the HLC. +// +//***************************************************************************** +static inline uint16_t CLB_getInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG)); +} + +//***************************************************************************** +// +//! Clears the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the interrupt tag register, setting it to 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_clearInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG) = 0U; +} + +//***************************************************************************** +// +//! Selects LUT4 inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4In0 is the value for LUT4 input signal 0. Generated by tool as +//! \b TILEx_CFG_LUT4_IN0. +//! \param lut4In1 is the value for LUT4 input signal 1. Generated by tool as +//! \b TILEx_CFG_LUT4_IN1. +//! \param lut4In2 is the value for LUT4 input signal 2. Generated by tool as +//! \b TILEx_CFG_LUT4_IN2. +//! \param lut4In3 is the value for LUT4 input signal 3. Generated by tool as +//! \b TILEx_CFG_LUT4_IN3. +//! +//! This function configures the LUT4 block's input signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectLUT4Inputs(uint32_t base, uint32_t lut4In0, + uint32_t lut4In1, uint32_t lut4In2, + uint32_t lut4In3) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_IN0) = lut4In0; + HWREG(base + CLB_O_LUT4_IN1) = lut4In1; + HWREG(base + CLB_O_LUT4_IN2) = lut4In2; + HWREG(base + CLB_O_LUT4_IN3) = lut4In3; + EDIS; +} + +//***************************************************************************** +// +//! Configures LUT4 functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4Fn10 is the equation value for LUT4 blocks 0 and 1. Generated by +//! tool as \b TILEx_CFG_LUT4_FN10. +//! \param lut4Fn2 is the equation value for LUT4 block2. Generated by tool as +//! \b TILEx_CFG_LUT4_FN2. +//! +//! This function configures the LUT4 block's equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLUT4Function(uint32_t base, uint32_t lut4Fn10, + uint32_t lut4Fn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_FN1_0) = lut4Fn10; + HWREG(base + CLB_O_LUT4_FN2) = lut4Fn2; + EDIS; +} + +//***************************************************************************** +// +//! Selects FSM inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param external0 is the value for FSM external 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN0. +//! \param external1 is the value for FSM external 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN1. +//! \param extra0 is the value for FSM extra 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN0. +//! \param extra1 is the value for FSM extra 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN1. +//! +//! This function configures the FSM block's external inputs and extra external +//! inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectFSMInputs(uint32_t base, uint32_t external0, + uint32_t external1, uint32_t extra0, + uint32_t extra1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_EXTERNAL_IN0) = external0; + HWREG(base + CLB_O_FSM_EXTERNAL_IN1) = external1; + HWREG(base + CLB_O_FSM_EXTRA_IN0) = extra0; + HWREG(base + CLB_O_FSM_EXTRA_IN1) = extra1; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM LUT function. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param fsmLutFn10 is the value for FSM 0 & FSM 1 LUT function. Generated +//! by tool as \b TILEx_CFG_FSM_LUT_FN10. +//! \param fsmLutFn2 is the value for FSM 2 LUT function. Generated by tool as +//! \b TILEx_CFG_FSM_LUT_FN2. +//! +//! This function configures the FSM block's LUT equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMLUTFunction(uint32_t base, uint32_t fsmLutFn10, + uint32_t fsmLutFn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_LUT_FN1_0) = fsmLutFn10; + HWREG(base + CLB_O_FSM_LUT_FN2) = fsmLutFn2; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM next state. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param nextState0 is the value for FSM 0's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_0. +//! \param nextState1 is the value for FSM 1's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_1. +//! \param nextState2 is the value for FSM 2's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_2. +//! +//! This function configures the FSM's next state equation. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMNextState(uint32_t base, uint32_t nextState0, + uint32_t nextState1, + uint32_t nextState2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_NEXT_STATE_0) = nextState0; + HWREG(base + CLB_O_FSM_NEXT_STATE_1) = nextState1; + HWREG(base + CLB_O_FSM_NEXT_STATE_2) = nextState2; + EDIS; +} + +//***************************************************************************** +// +//! Selects Counter inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param reset is the value for counter's reset inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_RESET. +//! \param event is the value for counter's event inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_EVENT. +//! \param mode0 is the value for counter's mode 0 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_0. +//! \param mode1 is the value for counter's mode 1 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_1. +//! +//! This function selects the input signals to the counter block. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectCounterInputs(uint32_t base, uint32_t reset, + uint32_t event, uint32_t mode0, + uint32_t mode1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_COUNT_RESET) = reset; + HWREG(base + CLB_O_COUNT_EVENT) = event; + HWREG(base + CLB_O_COUNT_MODE_0) = mode0; + HWREG(base + CLB_O_COUNT_MODE_1) = mode1; + EDIS; +} + +//***************************************************************************** +// +//! Configures Counter and FSM modes. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param miscCtrl is the value to represent counter and FSM modes. +//! Generated by tool as \b TILEx_CFG_MISC_CONTROL. +//! +//! This function configures the counter mode, particularly add/shift, load +//! modes. The function also configures whether the FSM should use state inputs +//! or an extra external input. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configMiscCtrlModes(uint32_t base, uint32_t miscCtrl) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_MISC_CONTROL) = miscCtrl; + EDIS; +} + +//***************************************************************************** +// +//! Configures Output LUT functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outID is the specified CLB tile output signal. +//! \param outputCfg is the value for the output LUT signal function and input +//! signal selections. Generated by tool as \b TILEx_CFG_OUTLUT_n where +//! n is the output number. +//! +//! This function configures the input signals and equations of the output LUT +//! corresponding to the /e outID parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configOutputLUT(uint32_t base, CLB_Outputs outID, + uint32_t outputCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_OUTPUT_LUT_0 + (sizeof(uint32_t) * outID)) = outputCfg; + EDIS; +} + +//***************************************************************************** +// +//! Configures HLC event selection. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param eventSel is the value for HLC event selection. Generated by tool as +//! \b TILEx_HLC_EVENT_SEL. +//! +//! This function configures the event selection for the High Level Controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configHLCEventSelect(uint32_t base, uint32_t eventSel) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_HLC_EVENT_SEL) = eventSel; + EDIS; +} + +//***************************************************************************** +// +//! Program HLC instruction. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param instructionNum is the index into the HLC instruction memory. For +//! example, a value of 0 corresponds to instruction 0 of event 0, +//! a value of 1 corresponds to instruction 1 of event 0, and so on up +//! to a value of 31 which corresponds to instruction 7 of event 3. +//! \param instruction is the instruction to be programmed. Generated by tool +//! as \b TILEx_HLCINSTR_n where n is the instruction number. +//! +//! This function configures the CLB internal memory corresponding to the +//! specified HLC instruction number with the given instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_programHLCInstruction(uint32_t base, + uint32_t instructionNum, + uint32_t instruction) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(instructionNum < 32U); + + CLB_writeInterface(base, CLB_ADDR_HLC_BASE + instructionNum, instruction); +} + +//***************************************************************************** +// +//! Set HLC registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param r0Init is the value to write to HLC register R0. Generated by tool +//! as \b TILEx_HLC_R0_INIT. +//! \param r1Init is the value to write to HLC register R1. Generated by tool +//! as \b TILEx_HLC_R1_INIT. +//! \param r2Init is the value to write to HLC register R2. Generated by tool +//! as \b TILEx_HLC_R2_INIT. +//! \param r3Init is the value to write to HLC register R3. Generated by tool +//! as \b TILEx_HLC_R3_INIT. +//! +//! This function configures the CLB internal memory corresponding to the HLC +//! registers R0-R3 with the specified values. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setHLCRegisters(uint32_t base, uint32_t r0Init, + uint32_t r1Init, uint32_t r2Init, + uint32_t r3Init) +{ + ASSERT(CLB_isBaseValid(base)); + + CLB_writeInterface(base, CLB_ADDR_HLC_R0, r0Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R1, r1Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R2, r2Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R3, r3Init); +} + +//***************************************************************************** +// +//! Get HLC or counter register values. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param registerID is the internal register from which to read. Can be +//! either an HLC register (\b CLB_REG_HLC_Rn) or a counter value +//! (\b CLB_REG_CTR_Cn). +//! +//! \return Returns the value in the specified HLC register or counter. +// +//***************************************************************************** +static inline uint32_t CLB_getRegister(uint32_t base, CLB_Register registerID) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + (uint32_t)registerID)); +} + +//***************************************************************************** +// +//! Get output status. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the output status of various components within the CLB tile +//! such as a counter match or LUT output. Use the \b CLB_DBG_OUT_* +//! masks from hw_clb.h to decode the bits. +// +//***************************************************************************** +static inline uint32_t CLB_getOutputStatus(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_DBG_OUT)); +} + +//***************************************************************************** +// +//! Configures Counter load and match. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param counterID is the specified counter unit. +//! \param load is the value for counter's load mode. Generated by tool as +//! \b TILEx_COUNTER_n_LOAD_VAL where n is the counter number. +//! \param match1 is the value for counter's match 1. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH1_VAL where n is the counter number. +//! \param match2 is the value for counter's match 2. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH2_VAL where n is the counter number. +//! +//! This function configures the CLB internal memory corresponding to the +//! counter block's load and match values. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, + uint32_t match2); + +//***************************************************************************** +// +//! Clear FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the PUSH/PULL FIFOs as well as its pointers. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_clearFIFOs(uint32_t base); + +//***************************************************************************** +// +//! Configure the FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pullData[] is a pointer to an array of bytes which needs to be +//! written into the FIFO. The 0th FIFO data is in the 0th index. +//! +//! This function writes to the PULL FIFO. This also clears the FIFOs and +//! its pointer using the CLB_clearFIFOs() API prior to writing to +//! the FIFO. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_writeFIFOs(uint32_t base, const uint32_t pullData[]); + +//***************************************************************************** +// +//! Read FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pushData[] is a pointer to an array of bytes which needs to be +//! read from the FIFO. +//! +//! This function reads from the PUSH FIFO. The 0th FIFO data would be in +//! the 0th index. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_readFIFOs(uint32_t base , uint32_t pushData[]); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLB_H diff --git a/gpio_driverlib_cpu2/device/driverlib/cmpss.c b/gpio_driverlib_cpu2/device/driverlib/cmpss.c new file mode 100644 index 0000000..88f9e5f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cmpss.c @@ -0,0 +1,223 @@ +//########################################################################### +// +// FILE: cmpss.c +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cmpss.h" + +//***************************************************************************** +// +// CMPSS_configFilterHigh +// +//***************************************************************************** +void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPHFILCTL) & + ~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the high comparator. + // + HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configFilterLow +// +//***************************************************************************** +void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPLFILCTL) & + ~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the low comparator. + // + HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configLatchOnPWMSYNC +// +//***************************************************************************** +void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // If the highEnable is true, set the bit that will enable PWMSYNC to reset + // the high comparator digital filter latch. If not, clear the bit. + // + EALLOW; + + if(highEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + } + + // + // If the lowEnable is true, set the bit that will enable PWMSYNC to reset + // the low comparator digital filter latch. If not, clear the bit. + // + if(lowEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + } + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configRamp +// +//***************************************************************************** +void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M); + ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 12U)); + + EALLOW; + + // + // Write the ramp generator source to the register + // + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S); + + // + // Set or clear the bit that determines from where the max ramp value + // should be loaded. + // + if(useRampValShdw) + { + HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL; + } + else + { + HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL; + } + + EDIS; + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal; + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal; + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal; +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/cmpss.h b/gpio_driverlib_cpu2/device/driverlib/cmpss.h new file mode 100644 index 0000000..25625c3 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cmpss.h @@ -0,0 +1,1325 @@ +//########################################################################### +// +// FILE: cmpss.h +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CMPSS_H +#define CMPSS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cmpss_api CMPSS +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_cmpss.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CMPSS_HICMP_CTL_M (CMPSS_COMPCTL_COMPHSOURCE | \ + CMPSS_COMPCTL_COMPHINV | \ + CMPSS_COMPCTL_ASYNCHEN) + +#define CMPSS_LOCMP_CTL_M (CMPSS_COMPCTL_COMPLSOURCE | \ + CMPSS_COMPCTL_COMPLINV | \ + CMPSS_COMPCTL_ASYNCLEN) + +#ifndef DOXYGEN_PDF_IGNORE + + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configLowComparator() and +// CMPSS_configHighComparator() as the config parameter. +// +//***************************************************************************** +// +// Comparator negative input source +// +//! Input driven by internal DAC +#define CMPSS_INSRC_DAC 0x0000U +//! Input driven by external pin +#define CMPSS_INSRC_PIN 0x0001U + +// +// Extra options +// +//! Comparator output is inverted +#define CMPSS_INV_INVERTED 0x0002U +//! Asynch comparator output feeds into OR with latched digital filter output +#define CMPSS_OR_ASYNC_OUT_W_FILT 0x0040U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configOutputsLow() and +// CMPSS_configOutputsHigh() as the config parameter. +// +//***************************************************************************** +// +// Signal driving CTRIPOUT +// +//! Asynchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_SYNC_COMP 0x0010U +//! Filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_FILTER 0x0020U +//! Latched filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_LATCH 0x0030U + +// +// Signal driving CTRIP +// +//! Asynchronous comparator output drives CTRIP +#define CMPSS_TRIP_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIP +#define CMPSS_TRIP_SYNC_COMP 0x0004U +//! Filter output drives CTRIP +#define CMPSS_TRIP_FILTER 0x0008U +//! Latched filter output drives CTRIP +#define CMPSS_TRIP_LATCH 0x000CU + +//***************************************************************************** +// +// Values that can be returned by CMPSS_getStatus(). +// +//***************************************************************************** +//! High digital filter output +#define CMPSS_STS_HI_FILTOUT 0x0001U +//! Latched value of high digital filter output +#define CMPSS_STS_HI_LATCHFILTOUT 0x0002U +//! Low digital filter output +#define CMPSS_STS_LO_FILTOUT 0x0100U +//! Latched value of low digital filter output +#define CMPSS_STS_LO_LATCHFILTOUT 0x0200U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configDAC() the config parameter. +// +//***************************************************************************** +// +// When is DAC value loaded from shadow register +// +//! DAC value updated from SYSCLK +#define CMPSS_DACVAL_SYSCLK 0x0000U +//! DAC value updated from PWMSYNC +#define CMPSS_DACVAL_PWMSYNC 0x0080U + +// +// DAC reference voltage +// +//! VDDA is the voltage reference +#define CMPSS_DACREF_VDDA 0x0000U +//! VDAC is the voltage reference +#define CMPSS_DACREF_VDAC 0x0020U + +// +// DAC value source +// +//! DAC value updated from shadow register +#define CMPSS_DACSRC_SHDW 0x0000U +//! DAC value is updated from the ramp register +#define CMPSS_DACSRC_RAMP 0x0001U +#endif + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configRamp() +// as the pwmSyncSrc parameter. +// +//***************************************************************************** +#define CMPSS_PWMSYNC1 1U //!< PWMSYNC1 +#define CMPSS_PWMSYNC2 2U //!< PWMSYNC2 +#define CMPSS_PWMSYNC3 3U //!< PWMSYNC3 +#define CMPSS_PWMSYNC4 4U //!< PWMSYNC4 +#define CMPSS_PWMSYNC5 5U //!< PWMSYNC5 +#define CMPSS_PWMSYNC6 6U //!< PWMSYNC6 +#define CMPSS_PWMSYNC7 7U //!< PWMSYNC7 +#define CMPSS_PWMSYNC8 8U //!< PWMSYNC8 +#define CMPSS_PWMSYNC9 9U //!< PWMSYNC9 +#define CMPSS_PWMSYNC10 10U //!< PWMSYNC10 +#define CMPSS_PWMSYNC11 11U //!< PWMSYNC11 +#define CMPSS_PWMSYNC12 12U //!< PWMSYNC12 + + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks the CMPSS base address. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function determines if a CMPSS base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CMPSS_isBaseValid(uint32_t base) +{ + return( + (base == CMPSS1_BASE) || + (base == CMPSS2_BASE) || + (base == CMPSS3_BASE) || + (base == CMPSS4_BASE) || + (base == CMPSS5_BASE) || + (base == CMPSS6_BASE) || + (base == CMPSS7_BASE) || + (base == CMPSS8_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function enables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) |= CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function disables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Clear the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) &= ~CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the high comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPH or +//! CTRIPOUTH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configHighComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_HICMP_CTL_M) | config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the low comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPL or +//! CTRIPOUTL. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configLowComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_LOCMP_CTL_M) | (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTH: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPH: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsHigh(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTHSEL_M | + CMPSS_COMPCTL_CTRIPHSEL_M)) | + config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTL: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPL: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsLow(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTLSEL_M | + CMPSS_COMPCTL_CTRIPLSEL_M)) | + (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current comparator status. +//! +//! \param base is the base address of the comparator module. +//! +//! This function returns the current status for the comparator, specifically +//! the digital filter output and latched digital filter output. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b CMPSS_STS_HI_FILTOUT - High digital filter output +//! - \b CMPSS_STS_HI_LATCHFILTOUT - Latched value of high digital filter +//! output +//! - \b CMPSS_STS_LO_FILTOUT - Low digital filter output +//! - \b CMPSS_STS_LO_LATCHFILTOUT - Latched value of low digital filter output +// +//***************************************************************************** +static inline uint16_t +CMPSS_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Return contents of the status register. + // + return(HWREGH(base + CMPSS_O_COMPSTS)); +} + +//***************************************************************************** +// +//! Sets the configuration for the internal comparator DACs. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the internal DAC. +//! +//! This function configures the comparator's internal DAC. The \e config +//! parameter is the result of a logical OR operation between the +//! \b CMPSS_DACVAL_xxx, \b CMPSS_DACREF_xxx, and \b CMPSS_DACSRC_xxx. +//! +//! The \b CMPSS_DACVAL_xxx term can take on the following values to specify +//! when the DAC value is loaded from its shadow register: +//! - \b CMPSS_DACVAL_SYSCLK - Value register updated on system clock. +//! - \b CMPSS_DACVAL_PWMSYNC - Value register updated on PWM sync. +//! +//! The \b CMPSS_DACREF_xxx term can take on the following values to specify +//! which voltage supply is used as reference for the DACs: +//! - \b CMPSS_DACREF_VDDA - VDDA is the voltage reference for the DAC. +//! - \b CMPSS_DACREF_VDAC - VDAC is the voltage reference for the DAC. +//! +//! The \b CMPSS_DACSRC_xxx term can take on the following values to specify +//! the DAC value source for the high comparator's internal DAC: +//! - \b CMPSS_DACSRC_SHDW - The user-programmed DACVALS register. +//! - \b CMPSS_DACSRC_RAMP - The ramp generator RAMPSTS register +//! +//! \note The \b CMPSS_DACVAL_xxx and \b CMPSS_DACREF_xxx terms apply to +//! both the high and low comparators. \b CMPSS_DACSRC_xxx will only affect +//! the high comparator's internal DAC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configDAC(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~(CMPSS_COMPDACCTL_SWLOADSEL | CMPSS_COMPDACCTL_SELREF | + CMPSS_COMPDACCTL_DACSOURCE)) | config; + EDIS; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the high +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueHigh(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACHVALS) = value; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the low +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueLow(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACLVALS) = value; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the high comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterHigh() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the high comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) |= CMPSS_CTRIPHFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the low comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterLow() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the low comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) |= CMPSS_CTRIPLFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the high comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueHigh() writes. +//! +//! \return Returns the value driven by the internal DAC of the high comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACHVALA)); +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the low comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueLow() writes. +//! +//! \return Returns the value driven by the internal DAC of the low comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACLVALA)); +} + +//***************************************************************************** +// +//! Causes a software reset of the high comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the high comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Causes a software reset of the low comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the low comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! \param value the ramp maximum reference value. +//! +//! This function sets the ramp maximum reference value that will be loaded +//! into the ramp generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setMaxRampValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp maximum reference value that will be +//! loaded into the ramp generator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getMaxRampValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the maximum ramp value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPMAXREFA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the ramp decrement value. +//! +//! This function sets the value that is subtracted from the ramp value on +//! every system clock cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDecValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp decrement value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDecValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp decrement value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDECVALA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the 13-bit ramp delay value. +//! +//! This function sets the value that configures the number of system clock +//! cycles to delay the start of the ramp generator decrementer after a PWMSYNC +//! event is received. Delay value can be no greater than 8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDelayValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 8192U); + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp delay value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDelayValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp delay value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDLYA)); +} + +//***************************************************************************** +// +//! Configures sync source for comparator +//! +//! \param base is the base address of the comparator module. +//! \param syncSource is the desired EPWMxSYNCPER source +//! +//! This function configures desired EPWMxSYNCPER source for comparator +//! blocks. Configured EPWMxSYNCPER signal can be used to synchronize loading +//! of DAC input value from shadow to active register. It can also be used to +//! synchronize Ramp generator, if applicable. Refer to device manual to check +//! if Ramp generator is available in the desired CMPSS instance. +//! +//! Valid values for \e syncSource parameter can be 1 to n, where n represents +//! the maximum number of EPWMSYNCPER signals available on the device. For +//! instance, passing 2 into \e syncSource will select EPWM2SYNCPER. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configureSyncSource(uint32_t base, uint16_t syncSource) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp delay value to the shadow register. + // + EALLOW; + HWREGH(base + CMPSS_O_COMPDACCTL) = (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(syncSource - 1U) << + CMPSS_COMPDACCTL_RAMPSOURCE_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the comparator hysteresis settings. +//! +//! \param base is the base address of the comparator module. +//! \param value is the amount of hysteresis on the comparator inputs. +//! +//! This function sets the amount of hysteresis on the comparator inputs. The +//! \e value parameter indicates the amount of hysteresis desired. Passing in 0 +//! results in none, passing in 1 results in typical hysteresis, passing in 2 +//! results in 2x of typical hysteresis, and so on where \e value x of typical +//! hysteresis is the amount configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setHysteresis(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value <= 4U); + + // + // Read the ramp delay value from the register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPHYSCTL) = value; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the high +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configHighComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterHigh() +//! -# Initialize the sample values using CMPSS_initFilterHigh() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsHigh() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the low +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configLowComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterLow() +//! -# Initialize the sample values using CMPSS_initFilterLow() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsLow() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures whether or not the digital filter latches are reset by PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! \param highEnable indicates filter latch settings in the high comparator. +//! \param lowEnable indicates filter latch settings in the low comparator. +//! +//! This function configures whether or not the digital filter latches in both +//! the high and low comparators should be reset by PWMSYNC. If the +//! \e highEnable parameter is \b true, the PWMSYNC will be allowed to reset +//! the high comparator's digital filter latch. If it is false, the ability of +//! the PWMSYNC to reset the latch will be disabled. The \e lowEnable parameter +//! has the same effect on the low comparator's digital filter latch. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable); + +//***************************************************************************** +// +//! Configures the comparator subsystem's ramp generator. +//! +//! \param base is the base address of the comparator module. +//! \param maxRampVal is the ramp maximum reference value. +//! \param decrementVal value is the ramp decrement value. +//! \param delayVal is the ramp delay value. +//! \param pwmSyncSrc is the number of the PWMSYNC source. +//! \param useRampValShdw indicates if the max ramp shadow should be used. +//! +//! This function configures many of the main settings of the comparator +//! subsystem's ramp generator. The \e maxRampVal parameter should be passed +//! the ramp maximum reference value that will be loaded into the ramp +//! generator. The \e decrementVal parameter should be passed the decrement +//! value that will be subtracted from the ramp generator on each system clock +//! cycle. The \e delayVal parameter should be passed the 13-bit number of +//! system clock cycles the ramp generator should delay before beginning to +//! decrement the ramp generator after a PWMSYNC signal is received. +//! +//! These three values may be be set individually using the +//! CMPSS_setMaxRampValue(), CMPSS_setRampDecValue(), and +//! CMPSS_setRampDelayValue() APIs. +//! +//! The number of the PWMSYNC signal to be used to reset the ramp generator +//! should be specified by passing it into the \e pwmSyncSrc parameter. For +//! instance, passing a CMPSS_PWMSYNCx into \e pwmSyncSrc will select PWMSYNCx. +//! +//! To indicate whether the ramp generator should reset with the value from the +//! ramp max reference value shadow register or with the latched ramp max +//! reference value, use the \e useRampValShdw parameter. Passing it \b true +//! will result in the latched value being bypassed. The ramp generator will be +//! loaded right from the shadow register. A value of \b false will load the +//! ramp generator from the latched value. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CMPSS_H diff --git a/gpio_driverlib_cpu2/device/driverlib/cpu.h b/gpio_driverlib_cpu2/device/driverlib/cpu.h new file mode 100644 index 0000000..3e7385b --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cpu.h @@ -0,0 +1,172 @@ +//########################################################################### +// +// FILE: cpu.h +// +// TITLE: Useful C28x CPU defines. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CPU_H +#define CPU_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +// +// External reference to the interrupt flag register (IFR) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IFR; +#endif + +// +// External reference to the interrupt enable register (IER) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IER; +#endif + +// +// Define to enable interrupts +// +#ifndef EINT +#define EINT __asm(" clrc INTM") +#endif + +// +// Define to disable interrupts +// +#ifndef DINT +#define DINT __asm(" setc INTM") +#endif + +// +// Define to enable debug events +// +#ifndef ERTM +#define ERTM __asm(" clrc DBGM") +#endif + +// +// Define to disable debug events +// +#ifndef DRTM +#define DRTM __asm(" setc DBGM") +#endif + +// +// Define to allow writes to protected registers +// +#ifndef EALLOW +#ifndef __TMS320C28XX_CLA__ +#define EALLOW __eallow() +#else +#define EALLOW __meallow() +#endif // __TMS320C28XX_CLA__ +#endif // EALLOW + +// +// Define to disable writes to protected registers +// +#ifndef EDIS +#ifndef __TMS320C28XX_CLA__ +#define EDIS __edis() +#else +#define EDIS __medis() +#endif // __TMS320C28XX_CLA__ +#endif // EDIS + +// +// Define for emulation stop +// +#ifndef ESTOP0 +#define ESTOP0 __asm(" ESTOP0") +#endif + +// +// Define for emulation stop +// +#ifndef ESTOP1 +#define ESTOP1 __asm(" ESTOP1") +#endif + +// +// Define for no operation +// +#ifndef NOP +#define NOP __asm(" NOP") +#endif + +// +// Define for putting processor into a low-power mode +// +#ifndef _DUAL_HEADERS +#ifndef IDLE +#define IDLE __asm(" IDLE") +#endif +#else +#define IDLE_ASM __asm(" IDLE"); +#endif + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// +//***************************************************************************** +extern void __eallow(void); +extern void __edis(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CPU_H diff --git a/gpio_driverlib_cpu2/device/driverlib/cputimer.c b/gpio_driverlib_cpu2/device/driverlib/cputimer.c new file mode 100644 index 0000000..5d12934 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cputimer.c @@ -0,0 +1,61 @@ +//############################################################################# +// +// FILE: cputimer.c +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "cputimer.h" + +//***************************************************************************** +// +// CPUTimer_setEmulationMode +// +//***************************************************************************** +void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode) +{ + ASSERT(CPUTimer_isBaseValid(base)); + // + // Write to FREE_SOFT bits of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) = + (HWREGH(base + CPUTIMER_O_TCR) & + ~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) | + (uint16_t)mode; +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/cputimer.h b/gpio_driverlib_cpu2/device/driverlib/cputimer.h new file mode 100644 index 0000000..71a7501 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/cputimer.h @@ -0,0 +1,509 @@ +//############################################################################# +// +// FILE: cputimer.h +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef CPUTIMER_H +#define CPUTIMER_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup cputimer_api CPUTimer +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_cputimer.h" +#include "debug.h" +#include "sysctl.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +//! Values that can be passed to CPUTimer_setEmulationMode() as the +//! \e mode parameter. +// +//**************************************************************************** +typedef enum +{ + //! Denotes that the timer will stop after the next decrement + CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000, + //! Denotes that the timer will stop when it reaches zero + CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400, + //! Denotes that the timer will run free + CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800 +}CPUTimer_EmulationMode; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e source parameter. +// +//***************************************************************************** +typedef enum +{ + //! System Clock Source + CPUTIMER_CLOCK_SOURCE_SYS = 0x0, + //! Internal Oscillator 1 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1, + //! Internal Oscillator 2 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2, + //! External Clock Source + CPUTIMER_CLOCK_SOURCE_XTAL = 0x3, + //! Auxiliary PLL Clock Source + CPUTIMER_CLOCK_SOURCE_AUX = 0x6 +} CPUTimer_ClockSource; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1 + CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2 + CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4 + CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8 + CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16 +} CPUTimer_Prescaler; + +//***************************************************************************** +// +//! \internal +//! Checks CPU timer base address. +//! +//! \param base specifies the Timer module base address. +//! +//! This function determines if a CPU timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CPUTimer_isBaseValid(uint32_t base) +{ + return((base == CPUTIMER0_BASE) || (base == CPUTIMER1_BASE) || + (base == CPUTIMER2_BASE)); +} +#endif + +//***************************************************************************** +// +//! Clears CPU timer overflow flag. +//! +//! \param base is the base address of the timer module. +//! +//! This function clears the CPU timer overflow flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_clearOverflowFlag(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIF bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; +} + +//***************************************************************************** +// +//! Disables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function disables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_disableInterrupt(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TIE bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Enables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function enables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_enableInterrupt(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIE bit of TCR register + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Reloads CPU timer counter. +//! +//! \param base is the base address of the timer module. +//! +//! This function reloads the CPU timer counter with the values contained in +//! the CPU timer period register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_reloadTimerCounter(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TRB bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; +} + +//***************************************************************************** +// +//! Stops CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function stops the CPU timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_stopTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TSS bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function doesn't reset the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_resumeTimer(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function reloads the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_startTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Reload the timer counter + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Sets CPU timer period. +//! +//! \param base is the base address of the timer module. +//! \param periodCount is the CPU timer period count. +//! +//! This function sets the CPU timer period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Load the MSB period Count + // + HWREG(base + CPUTIMER_O_PRD) = periodCount; +} + +//***************************************************************************** +// +//! Returns the current CPU timer counter value. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the current CPU timer counter value. +//! +//! \return Returns the current CPU timer count value. +// +//***************************************************************************** +static inline uint32_t CPUTimer_getTimerCount(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Get the TIMH:TIM registers value + // + return(HWREG(base + CPUTIMER_O_TIM)); +} + +//***************************************************************************** +// +//! Set CPU timer pre-scaler value. +//! +//! \param base is the base address of the timer module. +//! \param prescaler is the CPU timer pre-scaler value. +//! +//! This function sets the pre-scaler value for the CPU timer. For every value +//! of (prescaler + 1), the CPU timer counter decrements by 1. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Writes to TPR.TDDR and TPRH.TDDRH bits + // + HWREGH(base + CPUTIMER_O_TPRH) = prescaler >> 8U; + HWREGH(base + CPUTIMER_O_TPR) = (prescaler & CPUTIMER_TPR_TDDR_M) ; +} + +//***************************************************************************** +// +//! Return the CPU timer overflow status. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the CPU timer overflow status. +//! +//! \return Returns true if the CPU timer has overflowed, false if not. +// +//***************************************************************************** +static inline bool CPUTimer_getTimerOverflowStatus(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Check if TIF bits of register TCR are set + // + return(((HWREGH(base + CPUTIMER_O_TCR) & CPUTIMER_TCR_TIF) == + CPUTIMER_TCR_TIF) ? true : false); +} + +//***************************************************************************** +// +//! Select CPU Timer 2 Clock Source and Prescaler +//! +//! \param base is the base address of the timer module. +//! \param source is the clock source to use for CPU Timer 2 +//! \param prescaler is the value that configures the selected clock source +//! relative to the system clock +//! +//! This function selects the specified clock source and prescaler value +//! for the CPU timer (CPU timer 2 only). +//! +//! The \e source parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock +//! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock +//! +//! The \e prescaler parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1 +//! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2 +//! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4 +//! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8 +//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16 +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_selectClockSource(uint32_t base, + CPUTimer_ClockSource source, + CPUTimer_Prescaler prescaler) +{ + ASSERT(base == CPUTIMER2_BASE); + + // + // Set source and prescaler for CPU Timer 2 + // + if(base == CPUTIMER2_BASE) + { + EALLOW; + + // + // Set Clock Source + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | (uint16_t)source; + SYSCTL_REGWRITE_DELAY; + + // + // Set Clock Prescaler + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M) | + ((uint16_t)prescaler < 0.0F); + + // + // Get the sign-extended offset trim value + // + oldOffsetTrim = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + oldOffsetTrim = ((oldOffsetTrim & (uint16_t)DAC_REG_BYTE_MASK) ^ + (uint16_t)0x80) - (uint16_t)0x80; + + // + // Calculate new offset trim value if DAC is operating at a reference + // voltage other than 2.5v. + // + newOffsetTrim = ((float32_t)(2.5 / referenceVoltage) * + (int16_t)oldOffsetTrim); + + // + // Check if the new offset trim value is valid + // + ASSERT(((int16_t)newOffsetTrim > -129) && ((int16_t)newOffsetTrim < 128)); + + // + // Set the new offset trim value + // + EALLOW; + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | + (int16_t)newOffsetTrim; + + EDIS; + +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/dac.h b/gpio_driverlib_cpu2/device/driverlib/dac.h new file mode 100644 index 0000000..fcd866a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/dac.h @@ -0,0 +1,604 @@ +//########################################################################### +// +// FILE: dac.h +// +// TITLE: C28x DAC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DAC_H +#define DAC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dac_api DAC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dac.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +// +// A 8-bit register mask +// +#define DAC_REG_BYTE_MASK (0xFFU) //!< Register Byte Mask + +// +// Lock Key +// +#define DAC_LOCK_KEY (0xA000U) //!< DAC Lock Key + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are defines for the reg parameter of the +// DAC_lockRegister() and DAC_isRegisterLocked() functions. +// +//***************************************************************************** +#define DAC_LOCK_CONTROL (0x1U) //!< Lock the control register +#define DAC_LOCK_SHADOW (0x2U) //!< Lock the shadow value register +#define DAC_LOCK_OUTPUT (0x4U) //!< Lock the output enable register + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! Values that can be passed to DAC_setReferenceVoltage() as the \e source +//! parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_REF_VDAC = 0, //!< VDAC reference voltage + DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage +}DAC_ReferenceVoltage; + +//***************************************************************************** +// +//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK + DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL +}DAC_LoadMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks DAC base address. +//! +//! \param base specifies the DAC module base address. +//! +//! This function determines if an DAC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DAC_isBaseValid(uint32_t base) +{ + return( + (base == DACA_BASE) || + (base == DACB_BASE) || + (base == DACC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Get the DAC Revision value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC revision value. +//! +//! \return Returns the DAC revision value. +// +//***************************************************************************** +static inline uint16_t +DAC_getRevision(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the revision value. + // + return(HWREGH(base + DAC_O_REV) & DAC_REV_REV_M); +} + +//***************************************************************************** +// +//! Sets the DAC Reference Voltage +//! +//! \param base is the DAC module base address +//! \param source is the selected reference voltage +//! +//! This function sets the DAC reference voltage. +//! +//! The \e source parameter can have the following value: +//! - \b DAC_REF_VDAC - The VDAC reference voltage +//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the reference voltage + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_DACREFSEL) | (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC Load Mode +//! +//! \param base is the DAC module base address +//! \param mode is the selected load mode +//! +//! This function sets the DAC load mode. +//! +//! The \e mode parameter can have one of two values: +//! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK +//! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setLoadMode(uint32_t base, DAC_LoadMode mode) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the load mode + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_LOADMODE) | (uint16_t)mode; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC PWMSYNC Signal +//! +//! \param base is the DAC module base address +//! \param signal is the selected PWM signal +//! +//! This function sets the DAC PWMSYNC signal. +//! +//! The \e signal parameter must be set to a number that represents the PWM +//! signal that will be set. For instance, passing 2 into \e signal will +//! select PWM sync signal 2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setPWMSyncSignal(uint32_t base, uint16_t pwmSignal) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((pwmSignal > 0U) && (pwmSignal < 17U)); + + // + // Set the PWM sync signal + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_SYNCSEL_M) | + ((uint16_t)(pwmSignal - 1U) << + DAC_CTL_SYNCSEL_S); + + EDIS; +} + +//***************************************************************************** +// +//! Get the DAC Active Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC active output value. +//! +//! \return Returns the DAC active output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getActiveValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the active value + // + return(HWREGH(base + DAC_O_VALA) & DAC_VALA_DACVALA_M); +} + +//***************************************************************************** +// +//! Set the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! \param value is the 12-bit code to be loaded into the active value register +//! +//! This function sets the DAC shadow output value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setShadowValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT(value <= DAC_VALS_DACVALS_M); + + // + // Set the shadow value + // + HWREGH(base + DAC_O_VALS) = (HWREGH(base + DAC_O_VALS) & + ~DAC_VALS_DACVALS_M) | + (uint16_t)(value & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Get the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC shadow output value. +//! +//! \return Returns the DAC shadow output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getShadowValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the shadow value + // + return(HWREGH(base + DAC_O_VALS) & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Enable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function enables the DAC output. +//! +//! \note A delay is required after enabling the DAC. Further details +//! regarding the exact delay time length can be found in the device datasheet. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_enableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Enable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) |= DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function disables the DAC output. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_disableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Disable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) &= ~DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Set DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param offset is the specified value for the offset trim +//! +//! This function sets the DAC offset trim. The \e offset value should be a +//! signed number in the range of -128 to 127. +//! +//! \note The offset should not be modified unless specifically indicated by +//! TI Errata or other documentation. Modifying the offset value could cause +//! this module to operate outside of the datasheet specifications. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setOffsetTrim(uint32_t base, int16_t offset) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((offset > -129) && (offset < 128)); + + // + // Set the offset trim value + // + EALLOW; + + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | (int16_t)offset; + + EDIS; +} + +//***************************************************************************** +// +//! Get DAC Offset Trim +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC offset trim value. +//! +//! \return None. +// +//***************************************************************************** +static inline int16_t +DAC_getOffsetTrim(uint32_t base) +{ + uint16_t value; + + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the sign-extended offset trim value + // + value = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + value = ((value & (uint16_t)DAC_REG_BYTE_MASK) ^ (uint16_t)0x80) - + (uint16_t)0x80; + + return((int16_t)value); +} + +//***************************************************************************** +// +//! Lock write-access to DAC Register +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC registers +//! +//! This function locks the write-access to the specified DAC register. Only a +//! system reset can unlock the register once locked. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_lockRegister(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Lock the specified registers + // + EALLOW; + + HWREGH(base + DAC_O_LOCK) |= (DAC_LOCK_KEY | reg); + + EDIS; +} + +//***************************************************************************** +// +//! Check if DAC Register is locked +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC register locks to check +//! +//! This function checks if write-access has been locked on the specified DAC +//! register. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return Returns \b true if any of the registers specified are locked, and +//! \b false if all specified registers aren't locked. +// +//***************************************************************************** +static inline bool +DAC_isRegisterLocked(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Return the lock status on the specified registers + // + return((bool)((HWREGH(base + DAC_O_LOCK) & reg) != 0U)); +} + +//***************************************************************************** +// +//! Tune DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param referenceVoltage is the reference voltage the DAC +//! module is operating at. +//! +//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage +//! value should be a floating point number in the range specified in the +//! device data manual. +//! +//! \note Use this function to adjust the DAC offset trim if operating +//! at a reference voltage other than 2.5v. Since this function modifies +//! the DAC offset trim register, it should only be called once after +//! Device_cal. If it is called multiple times after Device_cal, the offset +//! value scaled would be the wrong value. +//! +//! \return None. +// +//***************************************************************************** +extern void +DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DAC_H diff --git a/gpio_driverlib_cpu2/device/driverlib/dcsm.c b/gpio_driverlib_cpu2/device/driverlib/dcsm.c new file mode 100644 index 0000000..808027a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/dcsm.c @@ -0,0 +1,377 @@ +//############################################################################# +// +// FILE: dcsm.c +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "dcsm.h" + +//***************************************************************************** +// +// DCSM_unlockZone1CSM +// +//***************************************************************************** +void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3; + } +} + +//***************************************************************************** +// +// DCSM_unlockZone2CSM +// +//***************************************************************************** +void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3; + } +} +//***************************************************************************** +// +// DCSM_getZone1FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t) + ((regValue >> (uint16_t)sector) & + 0x01U)); + } + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone1RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >> + (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_getZone2FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >> + (uint16_t)sector) & 0x01U)); + } + + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone2RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z2_BASE + + DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_claimZoneSemaphore +// +//***************************************************************************** +bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S) | + (uint16_t)zone; + EDIS; + + // + // If the calling function was unable to claim the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == (uint16_t)zone) ? + true : false); +} + +//***************************************************************************** +// +// DCSM_releaseZoneSemaphore +// +//***************************************************************************** +bool +DCSM_releaseZoneSemaphore(void) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S); + EDIS; + + // + // If the calling function was unable to release the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == 0x0U) ? true : false); +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/dcsm.h b/gpio_driverlib_cpu2/device/driverlib/dcsm.h new file mode 100644 index 0000000..d181fa7 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/dcsm.h @@ -0,0 +1,669 @@ +//############################################################################# +// +// FILE: dcsm.h +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef DCSM_H +#define DCSM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dcsm_api DCSM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dcsm.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the unlockZone1CSM() and unlockZone2CSM(). +// These are not parameters for any function. +// These are not intended for application code. +// +//***************************************************************************** + +#define DCSM_O_Z1_CSMPSWD0 0x08U //!< Z1 CSMPSWD0 offset +#define DCSM_O_Z1_CSMPSWD1 0x0AU //!< Z1 CSMPSWD1 offset +#define DCSM_O_Z1_CSMPSWD2 0x0CU //!< Z1 CSMPSWD2 offset +#define DCSM_O_Z1_CSMPSWD3 0x0EU //!< Z1 CSMPSWD3 offset +#define DCSM_O_Z2_CSMPSWD0 0x08U //!< Z2 CSMPSWD0 offset +#define DCSM_O_Z2_CSMPSWD1 0x0AU //!< Z2 CSMPSWD1 offset +#define DCSM_O_Z2_CSMPSWD2 0x0CU //!< Z2 CSMPSWD2 offset +#define DCSM_O_Z2_CSMPSWD3 0x0EU //!< Z2 CSMPSWD3 offset + +//***************************************************************************** +// +// Register key defines. +// +//***************************************************************************** +#define FLSEM_KEY 0xA5U //!< Zone semaphore key + +//***************************************************************************** +// +//! Data structures to hold password keys. +// +//***************************************************************************** +typedef struct +{ + uint32_t csmKey0; + uint32_t csmKey1; + uint32_t csmKey2; + uint32_t csmKey3; +} DCSM_CSMPasswordKey; + +//***************************************************************************** +// +//! Values to distinguish the status of RAM or FLASH sectors. These values +//! describe which zone the memory location belongs too. +//! These values can be returned from DCSM_getRAMZone(), +//! DCSM_getFlashSectorZone(). +// +//***************************************************************************** +typedef enum +{ + DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible + DCSM_MEMORY_ZONE1, //!< Zone 1 + DCSM_MEMORY_ZONE2, //!< Zone 2 + DCSM_MEMORY_FULL_ACCESS //!< Full access +} DCSM_MemoryStatus; + +//***************************************************************************** +// +//! Values to pass to DCSM_claimZoneSemaphore(). These values are used +//! to describe the zone that can write to Flash Wrapper registers. +// +//***************************************************************************** +typedef enum +{ + DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1 + DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2 +} DCSM_SemaphoreZone; + +//***************************************************************************** +// +//! Values to distinguish the security status of the zones. +//! These values can be returned from DCSM_getZone1CSMSecurityStatus(), +//! DCSM_getZone2CSMSecurityStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_STATUS_SECURE, //!< Secure + DCSM_STATUS_UNSECURE, //!< Unsecure + DCSM_STATUS_LOCKED, //!< Locked +} DCSM_SecurityStatus; + +//***************************************************************************** +// +// Values to distinguish the status of the Control Registers. These values +// describe can be used with the return values of +// DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus(). +// +//***************************************************************************** +#define DCSM_ALLZERO 0x08U //!< CSM Passwords all zeros +#define DCSM_ALLONE 0x10U //!< CSM Passwords all ones +#define DCSM_UNSECURE 0x20U //!< Zone is secure/unsecure +#define DCSM_ARMED 0x40U //!< CSM is armed + +//***************************************************************************** +// +//! Values to decribe the EXEONLY Status. +//! These values are returned from to DCSM_getZone1RAMEXEStatus(), +//! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(), +//! DCSM_getZone2FlashEXEStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_PROTECTED, //!< Protected + DCSM_UNPROTECTED, //!< Unprotected + DCSM_INCORRECT_ZONE //!< Incorrect Zone +}DCSM_EXEOnlyStatus; + +//***************************************************************************** +// +//! Values to distinguish RAM Module. +//! These values can be passed to DCSM_getZone1RAMEXEStatus() +//! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone(). +// +//***************************************************************************** +typedef enum +{ + // + //C28x RAMs + // + DCSM_RAMLS0, //!< RAMLS0 + DCSM_RAMLS1, //!< RAMLS1 + DCSM_RAMLS2, //!< RAMLS2 + DCSM_RAMLS3, //!< RAMLS3 + DCSM_RAMLS4, //!< RAMLS4 + DCSM_RAMLS5, //!< RAMLS5 + DCSM_RAMD0, //!< RAMD0 + DCSM_RAMD1, //!< RAMD1 + DCSM_CLA = 14U //!> + shift) & 0x03U); + return((DCSM_MemoryStatus)ramStatus); +} + +//***************************************************************************** +// +//! Returns the security zone a flash sector belongs to +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function returns the security zone a flash sector belongs to. +//! +//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible , +//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if +//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section +//! doesn't belong to any zone (or if the section is unsecure).. +// +//***************************************************************************** +static inline DCSM_MemoryStatus +DCSM_getFlashSectorZone(DCSM_Sector sector) +{ + uint32_t sectStat; + uint16_t shift; + + // + // Get the Sector status register for the specific bank + // + sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT); + shift = (uint16_t)sector * 2U; + + // + //Read the SECTSTAT register for the specific Flash Sector. + // + return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U))); +} + +//***************************************************************************** +// +//! Read Zone 1 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 1 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone1LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Read Zone 2 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 2 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone2LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Unlocks Zone 1 CSM. +//! +//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the +//! CSM password for zone 1. +//! +//! This function unlocks the CSM password. It first reads the +//! four password locations in the User OTP. If any of the password values is +//! different from 0xFFFFFFFF, it unlocks the device by writing the provided +//! passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey); + +//***************************************************************************** +// +//! Unlocks Zone 2 CSM. +//! +//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM +//! password for zone 2. +//! +//! This function unlocks the CSM password. It first reads +//! the four password locations in the User OTP. If any of the password values +//! is different from 0xFFFFFFFF, it unlocks the device by writing the +//! provided passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey); +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Claims the zone semaphore which allows access to the Flash Wrapper register +//! for that zone. +//! +//! \param zone is the zone which is trying to claim the semaphore which allows +//! access to the Flash Wrapper registers. +//! +//! \return Returns true for a successful semaphore capture, false if it was +//! unable to capture the semaphore. +// +//***************************************************************************** +extern bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone); + +//***************************************************************************** +// +//! Releases the zone semaphore. +//! +//! \return Returns true if it was successful in releasing the zone semaphore +//! and false if it was unsuccessful in releasing the zone semaphore. +//! +//! \note If the calling function is not in the right zone to be able +//! to access this register, it will return a false. +// +//***************************************************************************** +extern bool +DCSM_releaseZoneSemaphore(void); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DCSM_H diff --git a/gpio_driverlib_cpu2/device/driverlib/debug.h b/gpio_driverlib_cpu2/device/driverlib/debug.h new file mode 100644 index 0000000..5a2f93a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/debug.h @@ -0,0 +1,91 @@ +//########################################################################### +// +// FILE: debug.h +// +// TITLE: Assert definition macro for debug. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DEBUG_H +#define DEBUG_H + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. It is the +// application's responsibility to define the __error__ function. +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#ifdef __TMS320C28XX__ +// +// When called from C28x application +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } \ + while((_Bool)0) +#else +// +// When called from CLA application. Update as needed. +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __mdebugstop(); \ + } \ + } \ + while((_Bool)0) +#endif +#else +#define ASSERT(expr) +#endif + +#endif // DEBUG_H diff --git a/gpio_driverlib_cpu2/device/driverlib/dma.c b/gpio_driverlib_cpu2/device/driverlib/dma.c new file mode 100644 index 0000000..ea591b1 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/dma.c @@ -0,0 +1,370 @@ +//########################################################################### +// +// FILE: dma.c +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "dma.h" + +//***************************************************************************** +// +// DMA_configAddresses +// +//***************************************************************************** +void DMA_configAddresses(uint32_t base, const void *destAddr, + const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configBurst +// +//***************************************************************************** +void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((size >= 1U) && (size <= 32U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up BURST registers. + // + HWREGH(base + DMA_O_BURST_SIZE) = size - 1U; + HWREGH(base + DMA_O_SRC_BURST_STEP) = srcStep; + HWREGH(base + DMA_O_DST_BURST_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configTransfer +// +//***************************************************************************** +void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(transferSize <= 0x10000U); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up TRANSFER registers. + // + HWREGH(base + DMA_O_TRANSFER_SIZE) = (uint16_t)(transferSize - 1U); + HWREGH(base + DMA_O_SRC_TRANSFER_STEP) = srcStep; + HWREGH(base + DMA_O_DST_TRANSFER_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configWrap +// +//***************************************************************************** +void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((srcWrapSize <= 0x10000U) || (destWrapSize <= 0x10000U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up WRAP registers. + // + HWREGH(base + DMA_O_SRC_WRAP_SIZE) = (uint16_t)(srcWrapSize - 1U); + HWREGH(base + DMA_O_SRC_WRAP_STEP) = srcStep; + + HWREGH(base + DMA_O_DST_WRAP_SIZE) = (uint16_t)(destWrapSize - 1U); + HWREGH(base + DMA_O_DST_WRAP_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configMode +// +//***************************************************************************** +void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up trigger selection in the CMA/CLA trigger source selection + // registers. These are considered part of system control. + // + switch(base) + { + case DMA_CH1_BASE: + // + // Channel 1 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH1_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH1_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH1_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH1_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 1U; + break; + + case DMA_CH2_BASE: + // + // Channel 2 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH2_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH2_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH2_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH2_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 2U; + break; + + case DMA_CH3_BASE: + // + // Channel 3 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH3_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH3_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH3_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH3_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 3U; + break; + + case DMA_CH4_BASE: + // + // Channel 4 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH4_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH4_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH4_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH4_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 4U; + break; + + case DMA_CH5_BASE: + // + // Channel 5 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH5_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH5_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH5_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH5_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 5U; + break; + + case DMA_CH6_BASE: + // + // Channel 6 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH6_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH6_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH6_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH6_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 6U; + break; + + default: + // + // Invalid base. + // + break; + } + + // + // Write the configuration to the mode register. + // + HWREGH(base + DMA_O_MODE) &= ~(DMA_MODE_DATASIZE | DMA_MODE_CONTINUOUS | + DMA_MODE_ONESHOT); + HWREGH(base + DMA_O_MODE) |= config; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configChannel +// +//***************************************************************************** +void DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(((transfParams->configSize == DMA_CFG_SIZE_16BIT) || + (transfParams->configSize == DMA_CFG_SIZE_32BIT)) && + ((transfParams->transferMode == DMA_CFG_ONESHOT_DISABLE) || + (transfParams->transferMode == DMA_CFG_ONESHOT_ENABLE)) && + ((transfParams->reinitMode == DMA_CFG_CONTINUOUS_DISABLE) || + (transfParams->reinitMode == DMA_CFG_CONTINUOUS_ENABLE))); + + // + // Configure DMA Channel + // + DMA_configAddresses(base, (const void *)transfParams->destAddr, + (const void *)transfParams->srcAddr); + + // + // Configure the size of each burst and the address step size + // + DMA_configBurst(base, transfParams->burstSize, transfParams->srcBurstStep, + transfParams->destBurstStep); + + // + // Configure the transfer size and the address step that is + // made after each burst. + // + DMA_configTransfer(base, transfParams->transferSize, + transfParams->srcTransferStep, + transfParams->destTransferStep); + + // + // Configure the DMA channel's wrap settings + // + DMA_configWrap(base, transfParams->srcWrapSize, transfParams->srcWrapStep, + transfParams->destWrapSize, transfParams->destWrapStep); + + // + // Configure the DMA channel's trigger and mode + // + DMA_configMode(base, transfParams->transferTrigger, + transfParams->transferMode | transfParams->reinitMode | + transfParams->configSize); + + // + // Enable the selected peripheral trigger to start a DMA transfer + // + DMA_enableTrigger(base); + + if(transfParams->enableInterrupt) + { + // + // Set the channel interrupt mode + // + DMA_setInterruptMode(base, transfParams->interruptMode); + + // + // Enable the indicated DMA channel interrupt source + // + DMA_enableInterrupt(base); + } + else + { + // + // Disable the indicated DMA channel interrupt source + // + DMA_disableInterrupt(base); + } +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/dma.h b/gpio_driverlib_cpu2/device/driverlib/dma.h new file mode 100644 index 0000000..ae57689 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/dma.h @@ -0,0 +1,1171 @@ +//########################################################################### +// +// FILE: dma.h +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DMA_H +#define DMA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dma_api DMA +//! \brief This module is used for DMA configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dma.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to DMA_configMode() as the config parameter. +// +//***************************************************************************** +//! Only one burst transfer performed per trigger. +#define DMA_CFG_ONESHOT_DISABLE 0U +//! Burst transfers occur without additional event triggers after the first. +#define DMA_CFG_ONESHOT_ENABLE DMA_MODE_ONESHOT + +//! DMA channel will be disabled at the end of a transfer. +#define DMA_CFG_CONTINUOUS_DISABLE 0U +//! DMA reinitializes when the transfer count is zero and waits for a trigger. +#define DMA_CFG_CONTINUOUS_ENABLE DMA_MODE_CONTINUOUS + +//! DMA transfers 16 bits at a time. +#define DMA_CFG_SIZE_16BIT 0U +//! DMA transfers 32 bits at a time. +#define DMA_CFG_SIZE_32BIT DMA_MODE_DATASIZE + +//***************************************************************************** +// +//! Values that can be passed to DMA_configMode() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + DMA_TRIGGER_SOFTWARE = 0, + + DMA_TRIGGER_ADCA1 = 1, + DMA_TRIGGER_ADCA2 = 2, + DMA_TRIGGER_ADCA3 = 3, + DMA_TRIGGER_ADCA4 = 4, + DMA_TRIGGER_ADCAEVT = 5, + DMA_TRIGGER_ADCB1 = 6, + DMA_TRIGGER_ADCB2 = 7, + DMA_TRIGGER_ADCB3 = 8, + DMA_TRIGGER_ADCB4 = 9, + DMA_TRIGGER_ADCBEVT = 10, + DMA_TRIGGER_ADCC1 = 11, + DMA_TRIGGER_ADCC2 = 12, + DMA_TRIGGER_ADCC3 = 13, + DMA_TRIGGER_ADCC4 = 14, + DMA_TRIGGER_ADCCEVT = 15, + DMA_TRIGGER_ADCD1 = 16, + DMA_TRIGGER_ADCD2 = 17, + DMA_TRIGGER_ADCD3 = 18, + DMA_TRIGGER_ADCD4 = 19, + DMA_TRIGGER_ADCDEVT = 20, + + DMA_TRIGGER_XINT1 = 29, + DMA_TRIGGER_XINT2 = 30, + DMA_TRIGGER_XINT3 = 31, + DMA_TRIGGER_XINT4 = 32, + DMA_TRIGGER_XINT5 = 33, + + DMA_TRIGGER_EPWM1SOCA = 36, + DMA_TRIGGER_EPWM1SOCB = 37, + DMA_TRIGGER_EPWM2SOCA = 38, + DMA_TRIGGER_EPWM2SOCB = 39, + DMA_TRIGGER_EPWM3SOCA = 40, + DMA_TRIGGER_EPWM3SOCB = 41, + DMA_TRIGGER_EPWM4SOCA = 42, + DMA_TRIGGER_EPWM4SOCB = 43, + DMA_TRIGGER_EPWM5SOCA = 44, + DMA_TRIGGER_EPWM5SOCB = 45, + DMA_TRIGGER_EPWM6SOCA = 46, + DMA_TRIGGER_EPWM6SOCB = 47, + DMA_TRIGGER_EPWM7SOCA = 48, + DMA_TRIGGER_EPWM7SOCB = 49, + DMA_TRIGGER_EPWM8SOCA = 50, + DMA_TRIGGER_EPWM8SOCB = 51, + DMA_TRIGGER_EPWM9SOCA = 52, + DMA_TRIGGER_EPWM9SOCB = 53, + DMA_TRIGGER_EPWM10SOCA = 54, + DMA_TRIGGER_EPWM10SOCB = 55, + DMA_TRIGGER_EPWM11SOCA = 56, + DMA_TRIGGER_EPWM11SOCB = 57, + DMA_TRIGGER_EPWM12SOCA = 58, + DMA_TRIGGER_EPWM12SOCB = 59, + + DMA_TRIGGER_TINT0 = 68, + DMA_TRIGGER_TINT1 = 69, + DMA_TRIGGER_TINT2 = 70, + + DMA_TRIGGER_MCBSPAMXEVT = 71, + DMA_TRIGGER_MCBSPAMREVT = 72, + DMA_TRIGGER_MCBSPBMXEVT = 73, + DMA_TRIGGER_MCBSPBMREVT = 74, + + + DMA_TRIGGER_SDFM1FLT1 = 95, + DMA_TRIGGER_SDFM1FLT2 = 96, + DMA_TRIGGER_SDFM1FLT3 = 97, + DMA_TRIGGER_SDFM1FLT4 = 98, + + DMA_TRIGGER_SDFM2FLT1 = 99, + DMA_TRIGGER_SDFM2FLT2 = 100, + DMA_TRIGGER_SDFM2FLT3 = 101, + DMA_TRIGGER_SDFM2FLT4 = 102, + + + DMA_TRIGGER_SPIATX = 109, + DMA_TRIGGER_SPIARX = 110, + DMA_TRIGGER_SPIBTX = 111, + DMA_TRIGGER_SPIBRX = 112, + DMA_TRIGGER_SPICTX = 113, + DMA_TRIGGER_SPICRX = 114, + + DMA_TRIGGER_CLB1INT = 127, + DMA_TRIGGER_CLB2INT = 128, + DMA_TRIGGER_CLB3INT = 129, + DMA_TRIGGER_CLB4INT = 130, + +} DMA_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setInterruptMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! DMA interrupt is generated at the beginning of a transfer + DMA_INT_AT_BEGINNING, + //! DMA interrupt is generated at the end of a transfer + DMA_INT_AT_END +} DMA_InterruptMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after current read-write access is completed + DMA_EMULATION_STOP, + //! Continue DMA operation regardless of emulation suspend + DMA_EMULATION_FREE_RUN +} DMA_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_configChannel() as the +//! configure parameter. +// +//***************************************************************************** +typedef struct +{ + DMA_Trigger transferTrigger; //DMA transfer triggers + DMA_InterruptMode interruptMode; //Channel interrupt mode + //! enableInterrupt can have a value 1(Enable) or 0(Disable) + bool enableInterrupt; //Enable/Disable interrupt mode + //! configSize can have a value DMA_CFG_SIZE_16BIT/32BIT + uint32_t configSize; //Data bus width (16 or 32 bits) + //! transferMode can have a value DMA_CFG_ONESHOT_DISABLE/ENABLE + uint32_t transferMode; //Burst transfer mode + //! reinitMode can have a value DMA_CFG_CONTINUOUS_DISABLE/ENABLE + uint32_t reinitMode; //DMA reinitialization mode + //! burstSize value range from 1 word to 32 sixteen-bit words. + uint32_t burstSize; //Number of words transferred per burst + //! transferSize value range from 1 to 65536 + uint32_t transferSize; //Number of bursts per transfer + //! Number of bursts to be transferred before a wrap of the source address + //! occurs. srcWrapSize value range from 1 to 65536 + uint32_t srcWrapSize; + //! Number of bursts to be transferred before a wrap of the destination + //! address occurs. destWrapSize value range from 1 to 65536 + uint32_t destWrapSize; + uint32_t destAddr; //destination address + uint32_t srcAddr; //source address + //! Amount to inc or dec the source address after each word of a burst. + //! srcBurstStep can have only signed values from -4096 to 4095 + int16_t srcBurstStep; + //! Amount to inc or dec the destination address after each word of a burst. + //! destBurstStep can have only signed values from -4096 to 4095 + int16_t destBurstStep; + //! Amount to inc or dec the source address after each burst of a transfer. + //! srcTransferStep can have only signed values from -4096 to 4095 + int16_t srcTransferStep; + //! Amount to inc or dec the destination address after each burst of a + //! transfer. destTransferStep can have only signed values from -4096 to 4095 + int16_t destTransferStep; + //! Amount to inc or dec the source address when the wrap occurs. + //! srcWrapStep can have only signed values from -4096 to 4095 + int16_t srcWrapStep; + //! Amount to inc or dec the destination address when the wrap occurs. + //! destWrapStep can have only signed values from -4096 to 4095 + int16_t destWrapStep; + +} DMA_ConfigParams; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an DMA channel base address. +//! +//! \param base specifies the DMA channel base address. +//! +//! This function determines if a DMA channel base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DMA_isBaseValid(uint32_t base) +{ + return((base == DMA_CH1_BASE) || (base == DMA_CH2_BASE) || + (base == DMA_CH3_BASE) || (base == DMA_CH4_BASE) || + (base == DMA_CH5_BASE) || (base == DMA_CH6_BASE)); +} +#endif + +//***************************************************************************** +// +//! Initializes the DMA controller to a known state. +//! +//! This function configures does a hard reset of the DMA controller in order +//! to put it into a known state. The function also sets the DMA to run free +//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_initController(void) +{ + EALLOW; + + // + // Set the hard reset bit. One NOP is required after HARDRESET. + // + HWREGH(DMA_BASE + DMA_O_CTRL) |= DMA_CTRL_HARDRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Channel Soft Reset +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function does a soft reset to place the channel into its default state +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_triggerSoftReset(uint32_t base) +{ + EALLOW; + + // + // Set the soft reset bit. One NOP is required after SOFTRESET. + // + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_SOFTRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Sets DMA emulation mode. +//! +//! \param mode is the emulation mode to be selected. +//! +//! This function sets the behavior of the DMA operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is +//! completed. +//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setEmulationMode(DMA_EmulationMode mode) +{ + EALLOW; + + // + // Set emulation mode + // + if(mode == DMA_EMULATION_STOP) + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) &= ~DMA_DEBUGCTRL_FREE; + } + else + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) |= DMA_DEBUGCTRL_FREE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables peripherals to trigger a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the selected peripheral trigger to start a DMA +//! transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables peripherals from triggering a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the selected peripheral trigger from starting a DMA +//! transfer on the specified channel. This also disables the use of the +//! software force using the DMA_forceTrigger() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Clear the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Force a peripheral trigger to a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function sets the peripheral trigger flag and if triggering a DMA +//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be +//! forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_forceTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger force bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTFRC; + EDIS; +} + +//***************************************************************************** +// +//! Clears a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears the peripheral trigger flag. Normally, you would use +//! this function when initializing the DMA for the first time. The flag is +//! cleared automatically when the DMA starts the first burst of a transfer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearTriggerFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write a one to the clear bit to clear the peripheral trigger flag. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Transfer Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Transfer Status Flag is set, which +//! means a DMA transfer has begun. +//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTransferStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Transfer Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_TRANSFERSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Burst Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Burst Status Flag is set, which +//! means a DMA burst has begun. +//! This flag is cleared when BURST_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Burst Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getBurstStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Burst Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_BURSTSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Run Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Run Status Flag is set, which +//! means the DMA channel is enabled. +//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and +//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit +//! is set. +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getRunStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Run Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_RUNSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Overflow Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Overflow Flag is set, which +//! means peripheral event trigger was received while Peripheral Event Trigger +//! Flag was already set. +//! This flag can be cleared by writing to ERRCLR bit, using the function +//! DMA_clearErrorFlag(). +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getOverflowFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Overflow Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_OVRFLG) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if a peripheral trigger event has occurred +//! The flag is automatically cleared when the first burst transfer begins, but +//! if needed, it can be cleared using DMA_clearTriggerFlag(). +//! +//! \return Returns \b true if a peripheral trigger event has occurred and its +//! flag is set. Returns \b false otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTriggerFlagStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the peripheral trigger flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_PERINTFLG) != 0U); +} + +//***************************************************************************** +// +//! Starts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function starts the DMA running, typically after you have configured +//! it. It will wait for the first trigger event to start operation. To halt +//! the channel use DMA_stopChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_startChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the run bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_RUN; + EDIS; +} + +//***************************************************************************** +// +//! Halts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function halts the DMA at its current state and any current read-write +//! access is completed. To start the channel again use DMA_startChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_stopChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the halt bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_HALT; + EDIS; +} + +//***************************************************************************** +// +//! Enables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Enables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. An overrun is when a peripheral +//! event trigger is received by the DMA before a previous trigger on that +//! channel had been serviced and its flag had been cleared. +//! +//! Note that this is the same interrupt signal as the interrupt that gets +//! generated at the beginning/end of a transfer. That interrupt must first be +//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to +//! be generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Clears the DMA channel error flags. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears both the DMA channel's sync error flag and its +//! overrun error flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearErrorFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write to the error clear bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_ERRCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the interrupt generation mode of a DMA channel interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param mode is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e mode parameter +//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the +//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be +//! generated at the beginning of a new transfer. Generating at the beginning +//! of a new transfer is the default behavior. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Write the selected interrupt generation mode to the register. + // + if(mode == DMA_INT_AT_END) + { + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTMODE; + } + else + { + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTMODE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DMA channel priority mode. +//! +//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e ch1IsHighPri +//! parameter is \b false, the DMA channels are serviced in round-robin mode. +//! This is the default behavior. +//! +//! If \b true, channel 1 will be given higher priority than the other +//! channels. This means that if a channel 1 trigger occurs, the current word +//! transfer on any other channel is completed and channel 1 is serviced for +//! the complete burst count. The lower-priority channel's interrupted transfer +//! will then resume. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setPriorityMode(bool ch1IsHighPri) +{ + EALLOW; + + // + // Write the selected priority mode to the register. + // + if(ch1IsHighPri) + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) |= + DMA_PRIORITYCTRL1_CH1PRIORITY; + } + else + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) &= + ~DMA_PRIORITYCTRL1_CH1PRIORITY; + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the source address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *srcAddr is a source address. +//! +//! This function configures the source address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configSourceAddress(uint32_t base, const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the destination address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! +//! This function configures the destinaton address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configDestAddress(uint32_t base, const void *destAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Setup DMA to transfer data on the specified channel. +//! +//! \param base is Base address of the DMA channel control register +//! \param *transfParams configuration parameter +//! Refer struct #DMA_ConfigParams +//! +//! This function configures the DMA transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams); + +//***************************************************************************** +// +//! Configures the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! \param *srcAddr is a source address. +//! +//! This function configures the source and destination addresses of a DMA +//! channel. The parameters are pointers to the data to be transferred. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr); + +//***************************************************************************** +// +//! Configures the DMA channel's burst settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param size is the number of words transferred per burst. +//! \param srcStep is the amount to increment or decrement the source address +//! after each word of a burst. +//! \param destStep is the amount to increment or decrement the destination +//! address after each word of a burst. +//! +//! This function configures the size of each burst and the address step size. +//! +//! The \e size parameter is the number of words that will be transferred +//! during a single burst. Possible amounts range from 1 word to 32 words. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred word of a burst. Only signed values from -4096 to 4095 are +//! valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's transfer settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param transferSize is the number of bursts per transfer. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the transfer size and the address step that is +//! made after each burst. +//! +//! The \e transferSize parameter is the number of bursts per transfer. If DMA +//! channel interrupts are enabled, they will occur after this number of bursts +//! have completed. The maximum number of bursts is 65536. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred burst of a transfer. Only signed values from -4096 to 4095 are +//! valid. If a wrap occurs, these step values will be ignored. Wrapping is +//! configured with DMA_configWrap(). +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's wrap settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param srcWrapSize is the number of bursts to be transferred before a wrap +//! of the source address occurs. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destWrapSize is the number of bursts to be transferred before a wrap +//! of the destination address occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the DMA channel's wrap settings. +//! +//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts +//! that are to be transferred before their respective addresses are wrapped. +//! The maximum wrap size is 65536 bursts. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses when the wrap +//! occurs. Only signed values from -4096 to 4095 are valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel trigger and mode. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param trigger is the interrupt source that triggers a DMA transfer. +//! \param config is a bit field of several configuration selections. +//! +//! This function configures the DMA channel's trigger and mode. +//! +//! The \e trigger parameter is the interrupt source that will trigger the +//! start of a DMA transfer. +//! +//! The \e config parameter is the logical OR of the following values: +//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled, +//! the subsequent burst transfers occur without additional event triggers +//! after the first event trigger. If disabled, only one burst transfer is +//! performed per event trigger. +//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled +//! the DMA reinitializes when the transfer count is zero and waits for the +//! next interrupt event trigger. If disabled, the DMA stops and clears the +//! run status bit. +//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects +//! whether the databus width is 16 or 32 bits. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DMA_H diff --git a/gpio_driverlib_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h b/gpio_driverlib_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h new file mode 100644 index 0000000..00e9ac6 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h @@ -0,0 +1,109 @@ +#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ +#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ + + +//***************************************************************************** +// CLB +//***************************************************************************** +#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL +#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL +#define SPI_MODE_MASTER SPI_MODE_CONTROLLER +#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD +#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD + +#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW +#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH + +#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity + + +//***************************************************************************** +// Interrupt +//***************************************************************************** +#define Interrupt_enableMaster Interrupt_enableGlobal +#define Interrupt_disableMaster Interrupt_disableGlobal + + +//***************************************************************************** +// SysCtrl +//***************************************************************************** +#define SysCtl_AccessMaster SysCtl_AccessController +#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA +#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA +#define SysCtl_selectSecMaster SysCtl_selectSecController + + +//***************************************************************************** +// GPIO +//***************************************************************************** +#define GPIO_setMasterCore GPIO_setControllerCore + + + +//***************************************************************************** +// Memcfg +//***************************************************************************** +#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel +#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY +#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1 +#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel + +#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel +#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1 +#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2 +#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel + +//***************************************************************************** +// EMIF +//***************************************************************************** +#define EMIF_MasterSelect EMIF_ControllerSelect +#define EMIF_selectMaster EMIF_selectController +#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG +#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G +#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G +#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2 + + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE +#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE +#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE +#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE +#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET +#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET +#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR +#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET + +#define I2C_initMaster I2C_initController +#define I2C_setSlaveAddress I2C_setTargetAddress +#define I2C_setOwnSlaveAddress I2C_setOwnAddress + + +//***************************************************************************** +// SDFM +//***************************************************************************** +#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt +#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt +#define SDFM_enableMasterFilter SDFM_enableMainFilter +#define SDFM_disableMasterFilter SDFM_disableMainFilter + +#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG + +#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */ diff --git a/gpio_driverlib_cpu2/device/driverlib/ecap.c b/gpio_driverlib_cpu2/device/driverlib/ecap.c new file mode 100644 index 0000000..4a48441 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/ecap.c @@ -0,0 +1,61 @@ +//########################################################################### +// +// FILE: ecap.c +// +// TITLE: C28x ECAP driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ecap.h" + +//***************************************************************************** +// +// ECAP_setEmulationMode +// +//***************************************************************************** +void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to FREE/SOFT bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) | + ((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S)); +} diff --git a/gpio_driverlib_cpu2/device/driverlib/ecap.h b/gpio_driverlib_cpu2/device/driverlib/ecap.h new file mode 100644 index 0000000..577d7a8 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/ecap.h @@ -0,0 +1,1164 @@ +//########################################################################### +// +// FILE: ecap.h +// +// TITLE: C28x ECAP driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef ECAP_H +#define ECAP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ecap_api eCAP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Includes +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ecap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// eCAP minimum and maximum values +// +//***************************************************************************** +#define ECAP_MAX_PRESCALER_VALUE 32U // Maximum Pre-scaler value + +//***************************************************************************** +// +// Values that can be passed to ECAP_enableInterrupt(), +// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as +// the intFlags parameter and returned by ECAP_getInterruptSource(). +// +//***************************************************************************** +//! Event 1 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_1 0x2U +//! Event 2 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_2 0x4U +//! Event 3 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_3 0x8U +//! Event 4 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_4 0x10U +//! Counter overflow ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_OVERFLOW 0x20U +//! Counter equals period ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_PERIOD 0x40U +//! Counter equals compare ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_COMPARE 0x80U + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEmulationMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! TSCTR is stopped on emulation suspension + ECAP_EMULATION_STOP = 0x0U, + //! TSCTR runs until 0 before stopping on emulation suspension + ECAP_EMULATION_RUN_TO_ZERO = 0x1U, + //! TSCTR is not affected by emulation suspension + ECAP_EMULATION_FREE_RUN = 0x2U +}ECAP_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setCaptureMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! eCAP operates in continuous capture mode + ECAP_CONTINUOUS_CAPTURE_MODE = 0U, + //! eCAP operates in one shot capture mode + ECAP_ONE_SHOT_CAPTURE_MODE = 1U +}ECAP_CaptureMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(), +//! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(), +//! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVENT_1 = 0U, //!< eCAP event 1 + ECAP_EVENT_2 = 1U, //!< eCAP event 2 + ECAP_EVENT_3 = 2U, //!< eCAP event 3 + ECAP_EVENT_4 = 3U //!< eCAP event 4 +}ECAP_Events; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setSyncOutMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! sync out on the sync in signal and software force + ECAP_SYNC_OUT_SYNCI = 0x00U, + //! sync out on counter equals period + ECAP_SYNC_OUT_COUNTER_PRD = 0x40U, + //! Disable sync out signal + ECAP_SYNC_OUT_DISABLED = 0x80U +}ECAP_SyncOutMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_APWM_ACTIVE_HIGH = 0x000, //!< APWM is active high + ECAP_APWM_ACTIVE_LOW = 0x400 //!< APWM is active low +}ECAP_APWMPolarity; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVNT_RISING_EDGE = 0U, //!< Rising edge polarity + ECAP_EVNT_FALLING_EDGE = 1U //!< Falling edge polarity +}ECAP_EventPolarity; + +//***************************************************************************** +// +//! \internal +//! Checks eCAP base address. +//! +//! \param base specifies the eCAP module base address. +//! +//! This function determines if an eCAP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool ECAP_isBaseValid(uint32_t base) +{ + return( + (base == ECAP1_BASE) || + (base == ECAP2_BASE) || + (base == ECAP3_BASE) || + (base == ECAP4_BASE) || + (base == ECAP5_BASE) || + (base == ECAP6_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the input prescaler. +//! +//! \param base is the base address of the ECAP module. +//! \param preScalerValue is the pre scaler value for ECAP input +//! +//! This function divides the ECAP input scaler. The pre scale value is +//! doubled inside the module. For example a preScalerValue of 5 will divide +//! the scaler by 10. Use a value of 1 to divide the pre scaler by 1. +//! The \e preScalerValue should be less than \b ECAP_MAX_PRESCALER_VALUE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPrescaler(uint32_t base, + uint16_t preScalerValue) +{ + ASSERT(ECAP_isBaseValid(base)); + + ASSERT(preScalerValue < ECAP_MAX_PRESCALER_VALUE); + + + // + // Write to PRESCALE bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_PRESCALE_M)) | + (preScalerValue << ECAP_ECCTL1_PRESCALE_S)); +} + +//***************************************************************************** +// +//! Sets the Capture event polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! \param polarity is the polarity of the event. +//! +//! This function sets the polarity of a given event. The value of event +//! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to +//! the four available events.For each event the polarity value determines the +//! edge on which the capture is activated. For a rising edge use a polarity +//! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of +//! \b ECAP_EVNT_FALLING_EDGE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPolarity(uint32_t base, + ECAP_Events event, + ECAP_EventPolarity polarity) +{ + + uint16_t shift; + + ASSERT(ECAP_isBaseValid(base)); + + shift = ((uint16_t)event) << 1U; + + + // + // Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL + // + HWREGH(base + ECAP_O_ECCTL1) = + (HWREGH(base + ECAP_O_ECCTL1) & ~(1U << shift)) | + ((uint16_t)polarity << shift); +} + +//***************************************************************************** +// +//! Sets the capture mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the capture mode. +//! \param event is the event number at which the counter stops or wraps. +//! +//! This function sets the eCAP module to a continuous or one-shot mode. +//! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or +//! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode +//! respectively. +//! +//! The value of event determines the event number at which the counter stops +//! (in one-shot mode) or the counter wraps (in continuous mode). The value of +//! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding +//! to the valid event numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setCaptureMode(uint32_t base, + ECAP_CaptureMode mode, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to CONT/ONESHT + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_CONT_ONESHT)) | + (uint16_t)mode); + + // + // Write to STOP_WRAP + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_STOP_WRAP_M)) | + (((uint16_t)event) << ECAP_ECCTL2_STOP_WRAP_S )); +} + +//***************************************************************************** +// +//! Re-arms the eCAP module. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function re-arms the eCAP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_reArm(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to RE-ARM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_REARM; +} + +//***************************************************************************** +// +//! Enables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be enabled. +//! +//! This function sets and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + + // + // Set bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be disabled. +//! +//! This function clears and disables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableInterrupt(uint32_t base, + uint16_t intFlags) +{ + + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Clear bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) &= ~intFlags; +} + +//***************************************************************************** +// +//! Returns the interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP interrupt flag. The following are valid +//! interrupt sources corresponding to the eCAP interrupt flag. +//! +//! \return Returns the eCAP interrupt that has occurred. The following are +//! valid return values. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \note - User can check if a combination of various interrupts have occurred +//! by ORing the above return values. +// +//***************************************************************************** +static inline uint16_t ECAP_getInterruptSource(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of ECFLG register + // + return(HWREGH(base + ECAP_O_ECFLG) & 0xFEU); +} + +//***************************************************************************** +// +//! Returns the Global interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP Global interrupt flag. +//! +//! \return Returns true if there is a global eCAP interrupt, false otherwise. +// +//***************************************************************************** +static inline bool ECAP_getGlobalInterruptStatus(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of Global interrupt bit + // + return((HWREGH(base + ECAP_O_ECFLG) & 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Clears interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function clears eCAP interrupt flags. The following are valid +//! interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + // + // Write to ECCLR register + // + HWREGH(base + ECAP_O_ECCLR) = intFlags; +} + +//***************************************************************************** +// +//! Clears global interrupt flag +//! +//! \param base is the base address of the ECAP module. +//! +//! This function clears the global interrupt bit. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearGlobalInterrupt(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to INT bit + // + HWREGH(base + ECAP_O_ECCLR) = ECAP_ECCLR_INT; +} + +//***************************************************************************** +// +//! Forces interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function forces and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_forceInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Write to ECFRC register + // + HWREGH(base + ECAP_O_ECFRC) = intFlags; +} + +//***************************************************************************** +// +//! Sets eCAP in Capture mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCaptureMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Sets eCAP in APWM mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in APWM mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableAPWMMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Enables counter reset on an event. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function enables the base timer, TSCTR, to be reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) |= 1U << ((2U * (uint16_t)event) + 1U); +} + +//***************************************************************************** +// +//! Disables counter reset on events. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function disables the base timer, TSCTR, from being reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) &= ~(1U << ((2U * (uint16_t)event) + 1U)); +} + +//***************************************************************************** +// +//! Enables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) |= ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Disables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Sets a phase shift value count. +//! +//! \param base is the base address of the ECAP module. +//! \param shiftCount is the phase shift value. +//! +//! This function writes a phase shift value to be loaded into the main time +//! stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CTRPHS + // + HWREG(base + ECAP_O_CTRPHS) = shiftCount; +} + +//***************************************************************************** +// +//! Enable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Disable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Load time stamp counter +//! +//! \param base is the base address of the ECAP module. +//! +//! This function forces the value in the phase shift counter register to be +//! loaded into Time stamp counter register. +//! Make sure to enable loading of Time stamp counter by calling +//! ECAP_enableLoadCounter() function before calling this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_loadCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SWSYNC + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SWSYNC; +} + +//***************************************************************************** +// +//! Configures Sync out signal mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the sync out mode. +//! +//! This function sets the sync out mode. Valid parameters for mode are: +//! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event. +//! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period. +//! - ECAP_SYNC_OUT_DISABLED - Disable sync out. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setSyncOutMode(uint32_t base, + ECAP_SyncOutMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCO_SEL + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_SYNCO_SEL_M)) | + (uint16_t)mode); +} + +//***************************************************************************** +// +//! Stops Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function stops the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_stopCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Starts Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function starts the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_startCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Set eCAP APWM polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param polarity is the polarity of APWM +//! +//! This function sets the polarity of the eCAP in APWM mode. Valid inputs for +//! polarity are: +//! - ECAP_APWM_ACTIVE_HIGH - For active high. +//! - ECAP_APWM_ACTIVE_LOW - For active low. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPolarity(uint32_t base, + ECAP_APWMPolarity polarity) +{ + ASSERT(ECAP_isBaseValid(base)); + + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & ~ECAP_ECCTL2_APWMPOL) | + (uint16_t)polarity); +} + +//***************************************************************************** +// +//! Set eCAP APWM period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the period count for APWM. +//! +//! This function sets the period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP1 + // + HWREG(base + ECAP_O_CAP1) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the on or off time count of the APWM waveform depending +//! on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity(), is active high then compareCount determines the on +//! time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP2 + // + HWREG(base + ECAP_O_CAP2) = compareCount; +} + +//***************************************************************************** +// +//! Load eCAP APWM shadow period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the shadow period count for APWM. +//! +//! This function sets the shadow period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowPeriod(uint32_t base, + uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP3 + // + HWREG(base + ECAP_O_CAP3) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM shadow on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the shadow on or off time count of the APWM waveform +//! depending on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity() , is active high then compareCount determines the +//! on time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowCompare(uint32_t base, + uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP4 + // + HWREG(base + ECAP_O_CAP4) = compareCount; +} + +//***************************************************************************** +// +//! Returns the time base counter value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the time base counter value. +//! +//! \return Returns the time base counter value. +// +//***************************************************************************** +static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Read the Time base counter value + // + return(HWREG(base + ECAP_O_TSCTR)); +} + +//***************************************************************************** +// +//! Returns event time stamp. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! +//! This function returns the current time stamp count of the given event. +//! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return Event time stamp value or 0 if \e event is invalid. +// +//***************************************************************************** +static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event) +{ + uint32_t count; + + ASSERT(ECAP_isBaseValid(base)); + + + switch(event) + { + case ECAP_EVENT_1: + + // + // Read CAP1 register + // + count = HWREG(base + ECAP_O_CAP1); + break; + + case ECAP_EVENT_2: + // + // Read CAP2 register + // + count = HWREG(base + ECAP_O_CAP2); + break; + + case ECAP_EVENT_3: + + // + // Read CAP3 register + // + count = HWREG(base + ECAP_O_CAP3); + break; + + case ECAP_EVENT_4: + + // + // Read CAP4 register + // + count = HWREG(base + ECAP_O_CAP4); + break; + + default: + + // + // Invalid event parameter + // + count = 0U; + break; + } + + return(count); +} + +//***************************************************************************** +// +//! Configures emulation mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the emulation mode. +//! +//! This function configures the eCAP counter, TSCTR, to the desired emulation +//! mode when emulation suspension occurs. Valid inputs for mode are: +//! - ECAP_EMULATION_STOP - Counter is stopped immediately. +//! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0. +//! - ECAP_EMULATION_FREE_RUN - Counter is not affected. +//! +//! \return None. +// +//***************************************************************************** +extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ECAP_H diff --git a/gpio_driverlib_cpu2/device/driverlib/emif.c b/gpio_driverlib_cpu2/device/driverlib/emif.c new file mode 100644 index 0000000..a862104 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/emif.c @@ -0,0 +1,46 @@ +//########################################################################### +// +// FILE: emif.c +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "emif.h" + diff --git a/gpio_driverlib_cpu2/device/driverlib/emif.h b/gpio_driverlib_cpu2/device/driverlib/emif.h new file mode 100644 index 0000000..7177421 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/emif.h @@ -0,0 +1,1369 @@ +//########################################################################### +// +// FILE: emif.h +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EMIF_H +#define EMIF_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup emif_api EMIF +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_emif.h" +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines to specify access protection to EMIF_setAccessProtection(). +// +//***************************************************************************** +//! This flag is used to specify whether CPU fetches are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_FETCHPROT MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 + +//! This flag is used to specify whether CPU writes are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_CPUWRPROT MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 + +//! This flag is used to specify whether DMA writes are allowed/blocked +//! for EMIF. It is valid only for EMIF1 instance. +#define EMIF_ACCPROT0_DMAWRPROT MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF1ACCPROT0 register that aren't +// associated with EMIF1 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF1 \ + ((uint16_t)MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1) + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF2ACCPROT0 register that aren't +// associated with EMIF2 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF2 \ + ((uint16_t)MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 |\ + (uint16_t)MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2) + +//***************************************************************************** +// +// Define to mask out the bits in the ASYNC_CSx_CR register that +// aren't associated with async configuration. +// +//***************************************************************************** +#define EMIF_ASYNC_CS_CR_MASK ((uint32_t)EMIF_ASYNC_CS2_CR_R_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_TA_M) + +//***************************************************************************** +// +// Define to mask out the bits in the INT_MSK register that aren't associated +// with interrupts. +// +//***************************************************************************** +#define EMIF_ASYNC_INT_MASK ((uint16_t)EMIF_INT_MSK_SET_AT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_LT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_WR_MASK_SET_M) + +//***************************************************************************** +// +// Defines to specify interrupt sources to EMIF_enableAsyncInterrupt() and +// EMIF_disableAsyncInterrupt().Three interrupts are available for asynchronous +// memory interface: Masked Asyncronous Timeout(AT) to indicate EMxWAIT signal +// remains active even after maximum wait cycles are reached. Masked Line Trap +// (LT) to indicate illegal memory access or invalid cache line size. +// Masked Wait Rise(WR) to indicate rising edge on EMxWAIT is detected. +// +//***************************************************************************** +//! This flag is used to allow/block EMIF to generate Masked Asynchronous +//! Timeout interrupt. +#define EMIF_ASYNC_INT_AT EMIF_INT_MSK_SET_AT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Line Trap +//! interrupt. +#define EMIF_ASYNC_INT_LT EMIF_INT_MSK_SET_LT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Wait Rise +//! interrupt. +#define EMIF_ASYNC_INT_WR EMIF_INT_MSK_SET_WR_MASK_SET_M + +//***************************************************************************** +// +// Define for key for EMIF1MSEL register that enables the register write. +// +//***************************************************************************** +#define EMIF_MSEL_KEY 0x93A5CE70U + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_CR register that aren't +// associated with SDRAM configuration parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_CR_MASK ((uint32_t)EMIF_SDRAM_CR_PAGESIGE_M | \ + (uint32_t)EMIF_SDRAM_CR_IBANK_M | \ + (uint32_t)EMIF_SDRAM_CR_BIT_11_9_LOCK | \ + (uint32_t)EMIF_SDRAM_CR_CL_M | \ + (uint32_t)EMIF_SDRAM_CR_NM | \ + (uint32_t)EMIF_SDRAM_CR_SR) + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_TR register that aren't +// associated with SDRAM timings parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_TR_MASK ((uint32_t)EMIF_SDRAM_TR_T_RRD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RC_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RAS_M | \ + (uint32_t)EMIF_SDRAM_TR_T_WR_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RCD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RP_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RFC_M) + +//***************************************************************************** +// +//! Values that can be passed to EMIF_setAsyncMode(), +//! EMIF_setAsyncTimingParams(), EMIF_setAsyncDataBusWidth(), +//! EMIF_enableAsyncExtendedWait() and EMIF_disableAsyncExtendedWait() +//! as the \e offset parameter. Three chip selects are available in +//! asynchronous memory interface so there are three configuration registers +//! available for each EMIF instance. All the three chip select offsets are +//! valid for EMIF1 while only EMIF_ASYNC_CS2_OFFSET is valid for EMIF2. +// +//***************************************************************************** +typedef enum +{ + EMIF_ASYNC_CS2_OFFSET = EMIF_O_ASYNC_CS2_CR, //! It is valid only for EMIF1 instance and not for EMIF2 instance. +//! Valid value for configBase parameter is EMIF1CONFIG_BASE. Valid +//! values for select parameter can be \e EMIF_CONTROLLER_CPU1_NG, +//! \e EMIF_CONTROLLER_CPU1_G, \e EMIF_CONTROLLER_CPU2_G or +//! \e EMIF_CONTROLLER_CPU1_NG2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_selectController(uint32_t configBase, EMIF_ControllerSelect select) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase)); + + // + // Sets the bits that enables EMIF1 controller selection. + // + EALLOW; + HWREG(configBase + MEMCFG_O_EMIF1MSEL) = (EMIF_MSEL_KEY | (uint32_t)select); + EDIS; +} + +//***************************************************************************** +// +//! Sets the access protection. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! \param access is the required access protection configuration. +//! +//! This function sets the access protection for an EMIF instance from CPU +//! and DMA. The \e access parameter can be any of \b EMIF_ACCPROT0_FETCHPROT, +//! \b EMIF_ACCPROT0_CPUWRPROT \b EMIF_ACCPROT0_DMAWRPROT values or their +//! combination. EMIF_ACCPROT0_DMAWRPROT value is valid as access parameter +//! for EMIF1 instance only . +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAccessProtection(uint32_t configBase, uint16_t access) +{ + uint16_t temp; + // + // Check the arguments. + // + + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + if(configBase == EMIF1CONFIG_BASE) + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF1); + temp = EMIF_ACCPROT0_MASK_EMIF1; + } + else + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF2); + temp = EMIF_ACCPROT0_MASK_EMIF2; + } + + // + // Sets the bits that enables access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) = + (HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) & ~(temp)) | access; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function commits the access protection for an EMIF instance from +//! CPU & DMA. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_commitAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that commits access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1COMMIT) |= + MEMCFG_EMIF1COMMIT_COMMIT_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Locks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function locks the write to access configuration fields i.e +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_lockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that locks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) |= MEMCFG_EMIF1LOCK_LOCK_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function unlocks the write to access configuration fields such as +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_unlockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that unlocks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) &= + ~((uint16_t)MEMCFG_EMIF1LOCK_LOCK_EMIF1); + EDIS; +} + +//***************************************************************************** +// +// Prototypes for Asynchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Selects the asynchronous mode of operation. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param mode is the desired mode of operation for external memory. +//! +//! +//! This function sets the mode of operation for asynchronous memory +//! between Normal or Strobe mode. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values for param \e mode can be \e EMIF_ASYNC_STROBE_MODE or +//! \e EMIF_ASYNC_NORMAL_MODE. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMode(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncMode mode) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async mode of operation. + // + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) + & ~((uint32_t)EMIF_ASYNC_CS2_CR_SS)) + | (uint32_t)mode; +} + +//***************************************************************************** +// +//! Enables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of the +//! EMIF instance +//! +//! This function enables the extended wait mode for an asynchronous +//! external memory.Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that enables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) | + EMIF_ASYNC_CS2_CR_EW; +} + +//***************************************************************************** +// +//! Disables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! This function disables the extended wait mode for an asynchronous external +//! memory.Valid values for param \e offset can be \e EMIF_ASYNC_CS2_OFFSET, +//! \e EMIF_ASYNC_CS3_OFFSET & \e EMIF_ASYNC_C43_OFFSET for EMIF1 and +//! \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) + { + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that disables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) & + ~((uint32_t)EMIF_ASYNC_CS2_CR_EW); +} + +//***************************************************************************** +// +//! Sets the wait polarity. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param polarity is desired wait polarity. +//! +//! This function sets the wait polarity for an asynchronous external memory. +//! Valid values for param \e polarity can be \e EMIF_ASYNC_WAIT_POLARITY_LOW +//! or \e EMIF_ASYNC_WAIT_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncWaitPolarity(uint32_t base, EMIF_AsyncWaitPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the polarity for async extended wait mode. + // + HWREG(base + EMIF_O_ASYNC_WCCR) = (HWREG(base + EMIF_O_ASYNC_WCCR) + & ~((uint32_t)EMIF_ASYNC_WCCR_WP0)) + | (uint32_t)polarity; +} + +//***************************************************************************** +// +//! Sets the Maximum Wait Cycles. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param value is the desired maximum wait cycles. +//! +//! This function sets the maximum wait cycles for extended asynchronous cycle. +//! Valid values for parameter \e value lies b/w 0x0U-0xFFU or 0-255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMaximumWaitCycles(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(value <= (EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)); + + // + // Sets the bit that enables extended wait mode. + // + HWREGH(base + EMIF_O_ASYNC_WCCR) = (HWREGH(base + EMIF_O_ASYNC_WCCR) + & ~((uint16_t)EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)) + | value; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Memory Timing Characteristics. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param tParam is the desired timing parameters. +//! +//! This function sets timing characteristics for an external asynchronous +//! memory to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET and +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 & EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncTimingParams(uint32_t base, EMIF_AsyncCSOffset offset, + const EMIF_AsyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory timing parameters. + // + temp = (tParam->turnArnd << EMIF_ASYNC_CS2_CR_TA_S) | + (tParam->rHold << EMIF_ASYNC_CS2_CR_R_HOLD_S) | + (tParam->rStrobe << EMIF_ASYNC_CS2_CR_R_STROBE_S) | + (tParam->rSetup << EMIF_ASYNC_CS2_CR_R_SETUP_S) | + (tParam->wHold << EMIF_ASYNC_CS2_CR_W_HOLD_S) | + (tParam->wStrobe << EMIF_ASYNC_CS2_CR_W_STROBE_S) | + (tParam->wSetup << EMIF_ASYNC_CS2_CR_W_SETUP_S); + + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) & + ~EMIF_ASYNC_CS_CR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Data Bus Width. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param width is the data bus width of the memory. +//! +//! This function sets the data bus size for an external asynchronous memory +//! to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values of param \e width can be \e EMIF_ASYNC_DATA_WIDTH_8, +//! \e EMIF_ASYNC_DATA_WIDTH_16 or \e EMIF_ASYNC_DATA_WIDTH_32. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncDataBusWidth(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncDataWidth width) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory data bus width. + // + HWREGH(base + (uint32_t)offset) = (HWREGH(base + (uint32_t)offset) + & ~((uint16_t)EMIF_ASYNC_CS2_CR_ASIZE_M)) + | (uint32_t)width; +} + +//***************************************************************************** +// +// Prototypes for Interrupt Handling +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for desired interrupts. +//! +//! This function enables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or their +//! combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that enables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_SET) = intFlags; +} + +//***************************************************************************** +// +//! Disables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for interrupts to be disabled. +//! +//! This function disables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or +//! their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that disables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_CLR) = intFlags; + +} + +//***************************************************************************** +// +//! Gets the interrupt status. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function gets the interrupt status for an EMIF instance. +//! +//! \return Returns the current interrupt status. +// +//***************************************************************************** +static inline uint16_t +EMIF_getAsyncInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets the async memory interrupt status. + // + return(HWREGH(base + EMIF_O_INT_MSK) & EMIF_ASYNC_INT_MASK); +} + +//***************************************************************************** +// +//! Clears the interrupt status for an EMIF instance. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for the interrupt status to be cleared. +//! +//! This function clears the interrupt status for an EMIF instance. +//! The \e intFlags parameter can be any of \b EMIF_INT_MSK_SET_AT_MASK_SET, +//! \b EMIF_INT_MSK_SET_LT_MASK_SET, or \b EMIF_INT_MSK_SET_WR_MASK_SET_M +//! values or their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_clearAsyncInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bit that clears desired async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK) = intFlags; +} + +//***************************************************************************** +// +// Prototypes for Synchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Sets the Synchronous Memory Timing Parameters. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tParam is parameters from memory datasheet in \e ns. +//! +//! This function sets the timing characteristics for an external +//! synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncTimingParams(uint32_t base, const EMIF_SyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets sync memory timing parameters. + // + temp = ((tParam->tRrd << EMIF_SDRAM_TR_T_RRD_S) + & EMIF_SDRAM_TR_T_RRD_M) + | ((tParam->tRc << EMIF_SDRAM_TR_T_RC_S) + & EMIF_SDRAM_TR_T_RC_M) + | ((tParam->tRas << EMIF_SDRAM_TR_T_RAS_S) + & EMIF_SDRAM_TR_T_RAS_M) + | ((tParam->tWr << EMIF_SDRAM_TR_T_WR_S) + & EMIF_SDRAM_TR_T_WR_M) + | ((tParam->tRcd << EMIF_SDRAM_TR_T_RCD_S) + & EMIF_SDRAM_TR_T_RCD_M) + | ((tParam->tRp << EMIF_SDRAM_TR_T_RP_S) + & EMIF_SDRAM_TR_T_RP_M) + | ((tParam->tRfc << EMIF_SDRAM_TR_T_RFC_S) + & EMIF_SDRAM_TR_T_RFC_M); + + HWREG(base + EMIF_O_SDRAM_TR) = (HWREG(base + EMIF_O_SDRAM_TR) & + ~EMIF_SYNC_SDRAM_TR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the SDRAM Self Refresh Exit Timing. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tXs is the desired timing value. +//! +//! This function sets the self refresh exit timing for an external +//! synchronous memory to be interfaced. tXs values must lie between +//! 0x0U-0x1FU or 0-31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncSelfRefreshExitTmng(uint32_t base, uint16_t tXs) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(tXs <= EMIF_SDR_EXT_TMNG_T_XS_M); + + // + // Sets the self refresh exit timing for sync memory. + // + HWREGH(base + EMIF_O_SDR_EXT_TMNG) = (HWREGH(base + EMIF_O_SDR_EXT_TMNG) + & ~((uint16_t)EMIF_SDR_EXT_TMNG_T_XS_M)) + | tXs; +} + +//***************************************************************************** +// +//! Sets the SDR Refresh Rate. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param refRate is the refresh rate. +//! +//! This function sets the refresh rate for an external synchronous memory +//! to be interfaced. Valid values for refRate lies b/w 0x0U-0x1FFFU or +//! 0-8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncRefreshRate(uint32_t base, uint16_t refRate) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(refRate <= EMIF_SDRAM_RCR_REFRESH_RATE_M); + + // + // Sets the sync memory refresh rate. + // + HWREGH(base + EMIF_O_SDRAM_RCR) = (HWREGH(base + EMIF_O_SDRAM_RCR) + & (~(uint16_t)EMIF_SDRAM_RCR_REFRESH_RATE_M)) + | refRate; +} + +//***************************************************************************** +// +//! Sets the Synchronous Memory configuration parameters. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param config is the desired configuration parameters. +//! +//! This function sets configuration parameters like CL, NM, IBANK +//! and PAGESIZE for an external synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncMemoryConfig(uint32_t base, const EMIF_SyncConfig *config) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the sync memory configuration bits. + // + temp = ((uint32_t)config->casLatency | (uint32_t)config->iBank | + (uint32_t)config->narrowMode | (uint32_t)config->pageSize); + + HWREG(base + EMIF_O_SDRAM_CR) = (HWREG(base + EMIF_O_SDRAM_CR) & + ~EMIF_SYNC_SDRAM_CR_MASK) | temp; +} + +//***************************************************************************** +// +// Prototypes for EMIF Low Power Modes +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_SR; +} + +//***************************************************************************** +// +//! Disables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_SR); +} + +//***************************************************************************** +// +//! Enables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function Enables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PD; +} + +//***************************************************************************** +// +//! Disables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PD); +} + +//***************************************************************************** +// +//! Enables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PDWR; +} + +//***************************************************************************** +// +//! Disables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PDWR); +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of SDRAM accesses +//! from a controller(CPUx/CPUx.DMA). +//! +//! \return \e Returns total number of accesses to SDRAM. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_AR)); + +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses which require activate command. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of accesses to SDRAM which +//! require activate command. +//! +//!\return \e Returns total number of accesses to SDRAM which require activate. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalActivateAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory which requires activate command. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_ACTR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EMIF_H diff --git a/gpio_driverlib_cpu2/device/driverlib/epwm.c b/gpio_driverlib_cpu2/device/driverlib/epwm.c new file mode 100644 index 0000000..76e09bb --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/epwm.c @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: epwm.c +// +// TITLE: C28x EPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "epwm.h" + +//***************************************************************************** +// +// EPWM_setEmulationMode +// +//***************************************************************************** +void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode) +{ + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to FREE_SOFT bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & (~EPWM_TBCTL_FREE_SOFT_M)) | + ((uint16_t)emulationMode << EPWM_TBCTL_FREE_SOFT_S)); +} + +//***************************************************************************** +// +// EPWM_configureSignal +// +//***************************************************************************** +void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams) +{ + float32_t tbClkInHz = 0.0F; + uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U; + + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Valid values in the function for TBCTR Mode are UP, DOWN + // and UP-DOWN count. + // + ASSERT((uint16_t)signalParams->tbCtrMode <= 2U); + + // + // Configure EPWM clock Divider + // + SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv); + + // + // Configure Time Base counter Clock + // + EPWM_setClockPrescaler(base, signalParams->tbClkDiv, + signalParams->tbHSClkDiv); + + // + // Configure Time Base Counter Mode + // + EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode); + + // + // Calculate TBCLK, TBPRD and CMPx values to be configured for + // achieving desired signal + // + tbClkInHz = ((float32_t)signalParams->sysClkInHz / + (float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv + + (uint16_t)signalParams->tbClkDiv))); + + if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4) + { + tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv); + } + else + { + tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv); + } + + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)(signalParams->dutyValA * + (float32_t)(tbPrdVal + 1U)); + cmpBVal = (uint16_t)(signalParams->dutyValB * + (float32_t)(tbPrdVal + 1U)); + } + else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValA * (float32_t)(tbPrdVal + 1U))); + cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValB * (float32_t)(tbPrdVal + 1U))); + } + else + { + tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz)); + cmpAVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValA * + (float32_t)tbPrdVal))) + 0.5f); + cmpBVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValB * + (float32_t)tbPrdVal))) + 0.5f); + } + + // + // Configure TBPRD value + // + EPWM_setTimeBasePeriod(base, tbPrdVal); + + // + // Default Configurations. + // + EPWM_disablePhaseShiftLoad(base); + EPWM_setPhaseShift(base, 0U); + EPWM_setTimeBaseCounter(base, 0U); + + // + // Setup shadow register load on ZERO + // + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_A, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_B, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + // + // Set Compare values + // + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, + cmpAVal); + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, + cmpBVal); + + // + // Set actions for ePWMxA & ePWMxB + // + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + + } + } + else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } + else + { + // + // Clear PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } +} + diff --git a/gpio_driverlib_cpu2/device/driverlib/epwm.h b/gpio_driverlib_cpu2/device/driverlib/epwm.h new file mode 100644 index 0000000..ada9b80 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/epwm.h @@ -0,0 +1,7496 @@ +//############################################################################# +// +// FILE: epwm.h +// +// TITLE: C28x EPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef EPWM_H +#define EPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup epwm_api ePWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_epwm.h" +#include "cpu.h" +#include "debug.h" +#include "sysctl.h" + + +// +// Time Base Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setEmulationMode() as the +//! \e emulationMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Stop after next Time Base counter increment or decrement + EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0, + //! Stop when counter completes whole cycle + EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1, + //! Free run + EPWM_EMULATION_FREE_RUN = 2 +} EPWM_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCountModeAfterSync() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0, //!< Count down after sync event + EPWM_COUNT_MODE_UP_AFTER_SYNC = 1 //!< Count up after sync event +} EPWM_SyncCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_CLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_CLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_CLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_CLOCK_DIVIDER_8 = 3, //!< Divide clock by 8 + EPWM_CLOCK_DIVIDER_16 = 4, //!< Divide clock by 16 + EPWM_CLOCK_DIVIDER_32 = 5, //!< Divide clock by 32 + EPWM_CLOCK_DIVIDER_64 = 6, //!< Divide clock by 64 + EPWM_CLOCK_DIVIDER_128 = 7 //!< Divide clock by 128 +} EPWM_ClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e highSpeedPrescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_HSCLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_HSCLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_HSCLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_HSCLOCK_DIVIDER_6 = 3, //!< Divide clock by 6 + EPWM_HSCLOCK_DIVIDER_8 = 4, //!< Divide clock by 8 + EPWM_HSCLOCK_DIVIDER_10 = 5, //!< Divide clock by 10 + EPWM_HSCLOCK_DIVIDER_12 = 6, //!< Divide clock by 12 + EPWM_HSCLOCK_DIVIDER_14 = 7 //!< Divide clock by 14 +} EPWM_HSClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setSyncOutPulseMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Sync pulse is generated by software + EPWM_SYNC_OUT_PULSE_ON_SOFTWARE = 0, + //! Sync pulse is passed from EPWMxSYNCIN + EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN = 0, + //! Sync pulse is generated when time base counter equals zero + EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO = 1, + //! Sync pulse is generated when time base counter equals compare B value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B = 2, + //! Sync pulse is disabled + EPWM_SYNC_OUT_PULSE_DISABLED = 4, + //! Sync pulse is generated when time base counter equals compare C value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C = 5, + //! Sync pulse is generated when time base counter equals compare D value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D = 6 +} EPWM_SyncOutPulseMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setPeriodLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! PWM Period register access is through shadow register + EPWM_PERIOD_SHADOW_LOAD = 0, + //! PWM Period register access is directly + EPWM_PERIOD_DIRECT_LOAD = 1 +} EPWM_PeriodLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTimeBaseCounterMode() as the +//! \e counterMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_MODE_UP = 0, //!< Up - count mode + EPWM_COUNTER_MODE_DOWN = 1, //!< Down - count mode + EPWM_COUNTER_MODE_UP_DOWN = 2, //!< Up - down - count mode + EPWM_COUNTER_MODE_STOP_FREEZE = 3 //!< Stop - Freeze counter +} EPWM_TimeBaseCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectPeriodLoadEvent() as the +//! \e shadowLoadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow to active load occurs when time base counter reaches 0 + EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0, + //! Shadow to active load occurs when time base counter reaches 0 and a + //! SYNC occurs + EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1, + //! Shadow to active load occurs only when a SYNC occurs + EPWM_SHADOW_LOAD_MODE_SYNC = 2 +} EPWM_PeriodShadowLoadMode; + +//***************************************************************************** +// +// Values that can be returned by the EPWM_getTimeBaseCounterDirection() +// +//***************************************************************************** +//! Time base counter is counting up +//! +#define EPWM_TIME_BASE_STATUS_COUNT_UP 1U +//! Time base counter is counting down +//! +#define EPWM_TIME_BASE_STATUS_COUNT_DOWN 0U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e epwmLink +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_WITH_EPWM_1 = 0, //!< link current ePWM with ePWM1 + EPWM_LINK_WITH_EPWM_2 = 1, //!< link current ePWM with ePWM2 + EPWM_LINK_WITH_EPWM_3 = 2, //!< link current ePWM with ePWM3 + EPWM_LINK_WITH_EPWM_4 = 3, //!< link current ePWM with ePWM4 + EPWM_LINK_WITH_EPWM_5 = 4, //!< link current ePWM with ePWM5 + EPWM_LINK_WITH_EPWM_6 = 5, //!< link current ePWM with ePWM6 + EPWM_LINK_WITH_EPWM_7 = 6, //!< link current ePWM with ePWM7 + EPWM_LINK_WITH_EPWM_8 = 7, //!< link current ePWM with ePWM8 + EPWM_LINK_WITH_EPWM_9 = 8, //!< link current ePWM with ePWM9 + EPWM_LINK_WITH_EPWM_10 = 9, //!< link current ePWM with ePWM10 + EPWM_LINK_WITH_EPWM_11 = 10, //!< link current ePWM with ePWM11 + EPWM_LINK_WITH_EPWM_12 = 11 //!< link current ePWM with ePWM12 +} EPWM_CurrentLink; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e linkComp +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_TBPRD = 0U, //!< link TBPRD registers + EPWM_LINK_COMP_A = 4U, //!< link COMPA registers + EPWM_LINK_COMP_B = 8U, //!< link COMPB registers + EPWM_LINK_COMP_C = 12U, //!< link COMPC registers + EPWM_LINK_COMP_D = 16U, //!< link COMPD registers + EPWM_LINK_GLDCTL2 = 28U //!< link GLDCTL2 registers +} EPWM_LinkComponent; + +// +// Counter Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to the EPWM_getCounterCompareShadowStatus(), +//! EPWM_setCounterCompareValue(), EPWM_setCounterCompareShadowLoadMode(), +//! EPWM_disableCounterCompareShadowLoadMode() +//! as the \e compModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_COMPARE_A = 0, //!< Counter compare A + EPWM_COUNTER_COMPARE_B = 2, //!< Counter compare B + EPWM_COUNTER_COMPARE_C = 5, //!< Counter compare C + EPWM_COUNTER_COMPARE_D = 7 //!< Counter compare D +} EPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCounterCompareShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_COMP_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_COMP_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_COMP_LOAD_ON_SYNC_ONLY = 8 +} EPWM_CounterCompareLoadMode; + +// +// Action Qualifier Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() and +//! EPWM_disableActionQualifierShadowLoadMode() as the \e aqModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_ACTION_QUALIFIER_A = 0, //!< Action Qualifier A + EPWM_ACTION_QUALIFIER_B = 2 //!< Action Qualifier B +} EPWM_ActionQualifierModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_AQ_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_AQ_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_AQ_LOAD_ON_SYNC_ONLY = 8 +} EPWM_ActionQualifierLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierT1TriggerSource() and +//! EPWM_setActionQualifierT2TriggerSource() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0, //!< Digital compare event A 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1, //!< Digital compare event A 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2, //!< Digital compare event B 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3, //!< Digital compare event B 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4, //!< Trip zone 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5, //!< Trip zone 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6, //!< Trip zone 3 + EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7 //!< ePWM sync +} EPWM_ActionQualifierTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierAction() as the \e +//! event parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0, + //! Time base counter equals period + EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2, + //! Time base counter up equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4, + //! Time base counter down equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6, + //! Time base counter up equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8, + //! Time base counter down equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10, + //! T1 event on count up + EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1, + //! T1 event on count down + EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3, + //! T2 event on count up + EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5, + //! T2 event on count down + EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7 +} EPWM_ActionQualifierOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierSWAction(), +//! EPWM_setActionQualifierAction() as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_NO_CHANGE = 0, //!< No change in the output pins + EPWM_AQ_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_OUTPUT_HIGH = 2, //!< Set output pins to High + EPWM_AQ_OUTPUT_TOGGLE = 3 //!< Toggle the output pins +} EPWM_ActionQualifierOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceAction() +//! as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_SW_DISABLED = 0, //!< Software forcing disabled + EPWM_AQ_SW_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_SW_OUTPUT_HIGH = 2 //!< Set output pins to High +} EPWM_ActionQualifierSWOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierActionComplete() +//! as the \e action parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0, + //! Time base counter equals zero and set output pins to low + EPWM_AQ_OUTPUT_LOW_ZERO = 0x1, + //! Time base counter equals zero and set output pins to high + EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2, + //! Time base counter equals zero and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3, + //! Time base counter equals period and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0, + //! Time base counter equals period and set output pins to low + EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4, + //! Time base counter equals period and set output pins to high + EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8, + //! Time base counter equals period and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC, + //! Time base counter up equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00, + //! Time base counter up equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10, + //! Time base counter up equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20, + //! Time base counter up equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30, + //! Time base counter down equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00, + //! Time base counter down equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40, + //! Time base counter down equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80, + //! Time base counter down equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0, + //! Time base counter up equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000, + //! Time base counter up equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100, + //! Time base counter up equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200, + //! Time base counter up equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300, + //! Time base counter down equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000, + //! Time base counter down equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400, + //! Time base counter down equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800, + //! Time base counter down equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00 +} EPWM_ActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to +//! EPWM_setAdditionalActionQualifierActionComplete() as the \e action +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! T1 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0, + //! T1 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1, + //! T1 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2, + //! T1 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3, + //! T1 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0, + //! T1 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4, + //! T1 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8, + //! T1 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC, + //! T2 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00, + //! T2 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10, + //! T2 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20, + //! T2 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30, + //! T2 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00, + //! T2 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40, + //! T2 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80, + //! T2 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0 +} EPWM_AdditionalActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_forceActionQualifierSWAction(), +//! EPWM_setActionQualifierSWAction(), EPWM_setActionQualifierAction() +//! EPWM_setActionQualifierContSWForceAction() as the \e epwmOutput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_A = 0, //!< ePWMxA output + EPWM_AQ_OUTPUT_B = 2 //!< ePWMxB output +} EPWM_ActionQualifierOutputModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceShadowMode() +//! as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow mode load when counter equals zero + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0, + //! Shadow mode load when counter equals period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1, + //! Shadow mode load when counter equals zero or period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! No shadow load mode. Immediate mode only. + EPWM_AQ_SW_IMMEDIATE_LOAD = 3 +} EPWM_ActionQualifierContForce; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandOutputSwapMode() +//! as the \e output parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_OUTPUT_A = 1, //!< DB output is ePWMA + EPWM_DB_OUTPUT_B = 0 //!< DB output is ePWMB +} EPWM_DeadBandOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity(), +//! EPWM_setDeadBandDelayMode() as the \e delayMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_RED = 1, //!< DB RED (Rising Edge Delay) mode + EPWM_DB_FED = 0 //!< DB FED (Falling Edge Delay) mode +} EPWM_DeadBandDelayMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity as the +//! \e polarity parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_POLARITY_ACTIVE_HIGH = 0, //!< DB polarity is not inverted + EPWM_DB_POLARITY_ACTIVE_LOW = 1 //!< DB polarity is inverted +} EPWM_DeadBandPolarity; + +//***************************************************************************** +// +// Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(), +// EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter. +// +//***************************************************************************** +//! Input signal is ePWMA +//! +#define EPWM_DB_INPUT_EPWMA 0U +//! Input signal is ePWMB +//! +#define EPWM_DB_INPUT_EPWMB 1U +//! Input signal is the output of Rising Edge delay +//! +#define EPWM_DB_INPUT_DB_RED 2U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandControlShadowLoadMode() as +//! the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_DB_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_DB_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_DB_LOAD_FREEZE = 3 +} EPWM_DeadBandControlLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setRisingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_RED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_RED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_RED_LOAD_FREEZE = 3 +} EPWM_RisingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setFallingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_FED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_FED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_FED_LOAD_FREEZE = 3 +} EPWM_FallingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandCounterClock() as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Dead band counter runs at TBCLK rate + EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0, + //! Dead band counter runs at 2*TBCLK rate + EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1 +} EPWM_DeadBandClockMode; + +// +// Trip Zone +// +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneSignals() and +// EPWM_disableTripZoneSignals() as the tzSignal parameter. +// +//***************************************************************************** +//! TZ1 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC1 0x1U +//! TZ2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC2 0x2U +//! TZ3 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC3 0x4U +//! TZ4 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC4 0x8U +//! TZ5 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC5 0x10U +//! TZ6 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC6 0x20U +//! DCAEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCAEVT2 0x40U +//! DCBEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCBEVT2 0x80U +//! One-shot TZ1 +//! +#define EPWM_TZ_SIGNAL_OSHT1 0x100U +//! One-shot TZ2 +//! +#define EPWM_TZ_SIGNAL_OSHT2 0x200U +//! One-shot TZ3 +//! +#define EPWM_TZ_SIGNAL_OSHT3 0x400U +//! One-shot TZ4 +//! +#define EPWM_TZ_SIGNAL_OSHT4 0x800U +//! One-shot TZ5 +//! +#define EPWM_TZ_SIGNAL_OSHT5 0x1000U +//! One-shot TZ6 +//! +#define EPWM_TZ_SIGNAL_OSHT6 0x2000U +//! One-shot DCAEVT1 +//! +#define EPWM_TZ_SIGNAL_DCAEVT1 0x4000U +//! One-shot DCBEVT1 +//! +#define EPWM_TZ_SIGNAL_DCBEVT1 0x8000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcType parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_DC_OUTPUT_A1 = 0, //!< Digital Compare output 1 A + EPWM_TZ_DC_OUTPUT_A2 = 3, //!< Digital Compare output 2 A + EPWM_TZ_DC_OUTPUT_B1 = 6, //!< Digital Compare output 1 B + EPWM_TZ_DC_OUTPUT_B2 = 9 //!< Digital Compare output 2 B +} EPWM_TripZoneDigitalCompareOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_EVENT_DC_DISABLED = 0, //!< Event is disabled + EPWM_TZ_EVENT_DCXH_LOW = 1, //!< Event when DCxH low + EPWM_TZ_EVENT_DCXH_HIGH = 2, //!< Event when DCxH high + EPWM_TZ_EVENT_DCXL_LOW = 3, //!< Event when DCxL low + EPWM_TZ_EVENT_DCXL_HIGH = 4, //!< Event when DCxL high + EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5 //!< Event when DCxL high DCxH low +} EPWM_TripZoneDigitalCompareOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the \e tzEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_EVENT_TZA = 0, //!< TZ1 - TZ6, DCAEVT2, DCAEVT1 + EPWM_TZ_ACTION_EVENT_TZB = 2, //!< TZ1 - TZ6, DCBEVT2, DCBEVT1 + EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, //!< DCAEVT1 (Digital Compare A event 1) + EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, //!< DCAEVT2 (Digital Compare A event 2) + EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, //!< DCBEVT1 (Digital Compare B event 1) + EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 //!< DCBEVT2 (Digital Compare B event 2) +} EPWM_TripZoneEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the +//! \e tzAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ACTION_DISABLE = 3 //!< Disable action +} EPWM_TripZoneAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvAction() as the +//! \e tzAdvEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9, + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0 +} EPWM_TripZoneAdvancedEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA(), +//! EPWM_setTripZoneAdvDigitalCompareActionB(),EPWM_setTripZoneAdvAction() +//! as the \e tzAdvDCAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ADV_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ADV_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ADV_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ADV_ACTION_TOGGLE = 3, //!< Toggle the output + EPWM_TZ_ADV_ACTION_DISABLE = 7 //!< Disable action +} EPWM_TripZoneAdvancedAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA() and +//! EPWM_setTripZoneAdvDigitalCompareActionB() as the \e tzAdvDCEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital Compare event A/B 1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0, + //! Digital Compare event A/B 1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3, + //! Digital Compare event A/B 2 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6, + //! Digital Compare event A/B 2 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9 +} EPWM_TripZoneAdvDigitalCompareEvent; + + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneInterrupt()and +// EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle interrupt +//! +#define EPWM_TZ_INTERRUPT_CBC 0x2U +//! Trip Zones One Shot interrupt +//! +#define EPWM_TZ_INTERRUPT_OST 0x4U +//! Digital Compare A Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT1 0x8U +//! Digital Compare A Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT2 0x10U +//! Digital Compare B Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT1 0x20U +//! Digital Compare B Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be returned by EPWM_getTripZoneFlagStatus() . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle flag +//! +#define EPWM_TZ_FLAG_CBC 0x2U +//! Trip Zones One Shot flag +//! +#define EPWM_TZ_FLAG_OST 0x4U +//! Digital Compare A Event 1 flag +//! +#define EPWM_TZ_FLAG_DCAEVT1 0x8U +//! Digital Compare A Event 2 flag +//! +#define EPWM_TZ_FLAG_DCAEVT2 0x10U +//! Digital Compare B Event 1 flag +//! +#define EPWM_TZ_FLAG_DCBEVT1 0x20U +//! Digital Compare B Event 2 flag +//! +#define EPWM_TZ_FLAG_DCBEVT2 0x40U + +//***************************************************************************** +// +// Value can be passed to EPWM_clearTripZoneFlag() as the +// tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus(). +// +//***************************************************************************** +//! Trip Zone interrupt +//! +#define EPWM_TZ_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag() +// as the tzCbcFlag parameter and returned by +// EPWM_getCycleByCycleTripZoneFlagStatus(). +// +//***************************************************************************** +//! CBC flag 1 +//! +#define EPWM_TZ_CBC_FLAG_1 0x1U +//! CBC flag 2 +//! +#define EPWM_TZ_CBC_FLAG_2 0x2U +//! CBC flag 3 +//! +#define EPWM_TZ_CBC_FLAG_3 0x4U +//! CBC flag 4 +//! +#define EPWM_TZ_CBC_FLAG_4 0x8U +//! CBC flag 5 +//! +#define EPWM_TZ_CBC_FLAG_5 0x10U +//! CBC flag 6 +//! +#define EPWM_TZ_CBC_FLAG_6 0x20U +//! CBC flag Digital compare event A2 +//! +#define EPWM_TZ_CBC_FLAG_DCAEVT2 0x40U +//! CBC flag Digital compare event B2 +//! +#define EPWM_TZ_CBC_FLAG_DCBEVT2 0x80U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearOneShotTripZoneFlag() as +// the tzCbcFlag parameter and returned by the +// EPWM_getOneShotTripZoneFlagStatus() . +// +//***************************************************************************** +//! OST flag OST1 +//! +#define EPWM_TZ_OST_FLAG_OST1 0x1U +//! OST flag OST2 +//! +#define EPWM_TZ_OST_FLAG_OST2 0x2U +//! OST flag OST3 +//! +#define EPWM_TZ_OST_FLAG_OST3 0x4U +//! OST flag OST4 +//! +#define EPWM_TZ_OST_FLAG_OST4 0x8U +//! OST flag OST5 +//! +#define EPWM_TZ_OST_FLAG_OST5 0x10U +//! OST flag OST6 +//! +#define EPWM_TZ_OST_FLAG_OST6 0x20U +//! OST flag Digital compare event A1 +//! +#define EPWM_TZ_OST_FLAG_DCAEVT1 0x40U +//! OST flag Digital compare event B1 +//! +#define EPWM_TZ_OST_FLAG_DCBEVT1 0x80U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectCycleByCycleTripZoneClearEvent() as +//! the \e clearMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Clear CBC pulse when counter equals zero + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0, + //! Clear CBC pulse when counter equals period + EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1, + //! Clear CBC pulse when counter equals zero or period + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2 +} EPWM_CycleByCycleTripZoneClearMode; + +//***************************************************************************** +// +// Values that can be passed to EPWM_forceTripZoneEvent() as the +// tzForceEvent parameter. +// +//***************************************************************************** +//! Force Cycle By Cycle trip event +//! +#define EPWM_TZ_FORCE_EVENT_CBC 0x2U +//! Force a One-Shot Trip Event +//! +#define EPWM_TZ_FORCE_EVENT_OST 0x4U +//! Force Digital Compare Output A Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT1 0x8U +//! Force Digital Compare Output A Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT2 0x10U +//! Force Digital Compare Output B Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT1 0x20U +//! Force Digital Compare Output B Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be passed to EPWM_setInterruptSource() as the +// interruptSource parameter. +// +//***************************************************************************** +//! Time-base counter is disabled +//! +#define EPWM_INT_TBCTR_DISABLED 0U +//! Time-base counter equal to zero +//! +#define EPWM_INT_TBCTR_ZERO 1U +//! Time-base counter equal to period +//! +#define EPWM_INT_TBCTR_PERIOD 2U +//! Time-base counter equal to zero or period +//! +#define EPWM_INT_TBCTR_ZERO_OR_PERIOD 3U +//! time-base counter equal to CMPA when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPA 4U +//! time-base counter equal to CMPC when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPC 8U +//! time-base counter equal to CMPA when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPA 5U +//! time-base counter equal to CMPC when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPC 10U +//! time-base counter equal to CMPB when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPB 6U +//! time-base counter equal to CMPD when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPD 12U +//! time-base counter equal to CMPB when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPB 7U +//! time-base counter equal to CMPD when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPD 14U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_enableADCTrigger(), +//! EPWM_disableADCTrigger(),EPWM_setADCTriggerSource(), +//! EPWM_setADCTriggerEventPrescale(),EPWM_getADCTriggerFlagStatus(), +//! EPWM_clearADCTriggerFlag(),EPWM_enableADCTriggerEventCountInit(), +//! EPWM_disableADCTriggerEventCountInit(),EPWM_forceADCTriggerEventCountInit(), +//! EPWM_setADCTriggerEventCountInitValue(),EPWM_getADCTriggerEventCount(), +//! EPWM_forceADCTrigger() as the \e adcSOCType parameter +// +//***************************************************************************** +typedef enum +{ + EPWM_SOC_A = 0, //!< SOC A + EPWM_SOC_B = 1 //!< SOC B +} EPWM_ADCStartOfConversionType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setADCTriggerSource() as the +//! \e socSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Event is based on DCxEVT1 + EPWM_SOC_DCxEVT1 = 0, + //! Time-base counter equal to zero + EPWM_SOC_TBCTR_ZERO = 1, + //! Time-base counter equal to period + EPWM_SOC_TBCTR_PERIOD = 2, + //! Time-base counter equal to zero or period + EPWM_SOC_TBCTR_ZERO_OR_PERIOD = 3, + //! Time-base counter equal to CMPA when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPA = 4, + //! Time-base counter equal to CMPC when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPC = 8, + //! Time-base counter equal to CMPA when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPA = 5, + //! Time-base counter equal to CMPC when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPC = 10, + //! Time-base counter equal to CMPB when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPB = 6, + //! Time-base counter equal to CMPD when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPD = 12, + //! Time-base counter equal to CMPB when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPB = 7, + //! Time-base counter equal to CMPD when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPD = 14 +} EPWM_ADCStartOfConversionSource; + +// +// Digital Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput(), +//! EPWM_enableDigitalCompareTripCombinationInput(), +//! EPWM_disableDigitalCompareTripCombinationInput() as the \e dcType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TYPE_DCAH = 0, //!< Digital Compare A High + EPWM_DC_TYPE_DCAL = 1, //!< Digital Compare A Low + EPWM_DC_TYPE_DCBH = 2, //!< Digital Compare B High + EPWM_DC_TYPE_DCBL = 3 //!< Digital Compare B Low +} EPWM_DigitalCompareType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput() +//! as the \e tripSource parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TRIP_TRIPIN1 = 0, //!< Trip 1 + EPWM_DC_TRIP_TRIPIN2 = 1, //!< Trip 2 + EPWM_DC_TRIP_TRIPIN3 = 2, //!< Trip 3 + EPWM_DC_TRIP_TRIPIN4 = 3, //!< Trip 4 + EPWM_DC_TRIP_TRIPIN5 = 4, //!< Trip 5 + EPWM_DC_TRIP_TRIPIN6 = 5, //!< Trip 6 + EPWM_DC_TRIP_TRIPIN7 = 6, //!< Trip 7 + EPWM_DC_TRIP_TRIPIN8 = 7, //!< Trip 8 + EPWM_DC_TRIP_TRIPIN9 = 8, //!< Trip 9 + EPWM_DC_TRIP_TRIPIN10 = 9, //!< Trip 10 + EPWM_DC_TRIP_TRIPIN11 = 10, //!< Trip 11 + EPWM_DC_TRIP_TRIPIN12 = 11, //!< Trip 12 + EPWM_DC_TRIP_TRIPIN14 = 13, //!< Trip 14 + EPWM_DC_TRIP_TRIPIN15 = 14, //!< Trip 15 + EPWM_DC_TRIP_COMBINATION = 15 //!< All Trips (Trip1 - Trip 15) are selected +} EPWM_DigitalCompareTripInput; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput(), +// EPWM_disableDigitalCompareTripCombinationInput() as the tripInput +// parameter. +// +//***************************************************************************** +//! Combinational Trip 1 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN1 0x1U +//! Combinational Trip 2 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN2 0x2U +//! Combinational Trip 3 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN3 0x4U +//! Combinational Trip 4 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN4 0x8U +//! Combinational Trip 5 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN5 0x10U +//! Combinational Trip 6 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN6 0x20U +//! Combinational Trip 7 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN7 0x40U +//! Combinational Trip 8 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN8 0x80U +//! Combinational Trip 9 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN9 0x100U +//! Combinational Trip 10 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN10 0x200U +//! Combinational Trip 11 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN11 0x400U +//! Combinational Trip 12 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN12 0x800U +//! Combinational Trip 14 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN14 0x2000U +//! Combinational Trip 15 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN15 0x4000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareBlankingEvent() as the +//! the \e blankingPulse parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals period + EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0, + //! Time base counter equals zero + EPWM_DC_WINDOW_START_TBCTR_ZERO = 1, + //! Time base counter equals zero or period + EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2 +} EPWM_DigitalCompareBlankingPulse; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareFilterInput() +//! as the \e filterInput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, //!< DC filter signal source is DCAEVT1 + EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, //!< DC filter signal source is DCAEVT2 + EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, //!< DC filter signal source is DCBEVT1 + EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3 //!< DC filter signal source is DCBEVT2 +} EPWM_DigitalCompareFilterInput; + +//***************************************************************************** +// +//! Values that can be assigned to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode(),EPWM_enableDigitalCompareSyncEvent() +//! EPWM_enableDigitalCompareADCTrigger(),EPWM_disableDigitalCompareSyncEvent() +//! EPWM_disableDigitalCompareADCTrigger() as the \e dcModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_MODULE_A = 0, //!< Digital Compare Module A + EPWM_DC_MODULE_B = 1 //!< Digital Compare Module B +} EPWM_DigitalCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EVENT_1 = 0, //!< Digital Compare Event number 1 + EPWM_DC_EVENT_2 = 1 //!< Digital Compare Event number 2 +} EPWM_DigitalCompareEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource() as the +//! \e dcEventSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Signal source is unfiltered (DCAEVT1/2) + EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0, + //! Signal source is filtered (DCEVTFILT) + EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1 +} EPWM_DigitalCompareEventSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSyncMode() as the +//! \e syncMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! DC input signal is synced with TBCLK + EPWM_DC_EVENT_INPUT_SYNCED = 0, + //! DC input signal is not synced with TBCLK + EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1 +} EPWM_DigitalCompareSyncMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setGlobalLoadTrigger() as the +//! \e loadTrigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter is equal to zero + EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0, + //! Load when counter is equal to period + EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1, + //! Load when counter is equal to zero or period + EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2, + //! Load on sync event + EPWM_GL_LOAD_PULSE_SYNC = 0x3, + //! Load on sync event or when counter is equal to zero + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4, + //! Load on sync event or when counter is equal to period + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5, + //! Load on sync event or when counter is equal to period or zero + EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6, + //! Load on global force + EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF +} EPWM_GlobalLoadTrigger; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableGlobalLoadRegisters(), +// EPWM_disableGlobalLoadRegisters() as theloadRegister parameter. +// +//***************************************************************************** +//! Global load TBPRD:TBPRDHR +//! +#define EPWM_GL_REGISTER_TBPRD_TBPRDHR 0x1U +//! Global load CMPA:CMPAHR +//! +#define EPWM_GL_REGISTER_CMPA_CMPAHR 0x2U +//! Global load CMPB:CMPBHR +//! +#define EPWM_GL_REGISTER_CMPB_CMPBHR 0x4U +//! Global load CMPC +//! +#define EPWM_GL_REGISTER_CMPC 0x8U +//! Global load CMPD +//! +#define EPWM_GL_REGISTER_CMPD 0x10U +//! Global load DBRED:DBREDHR +//! +#define EPWM_GL_REGISTER_DBRED_DBREDHR 0x20U +//! Global load DBFED:DBFEDHR +//! +#define EPWM_GL_REGISTER_DBFED_DBFEDHR 0x40U +//! Global load DBCTL +//! +#define EPWM_GL_REGISTER_DBCTL 0x80U +//! Global load AQCTLA/A2 +//! +#define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 0x100U +//! Global load AQCTLB/B2 +//! +#define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 0x200U +//! Global load AQCSFRC +//! +#define EPWM_GL_REGISTER_AQCSFRC 0x400U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyTriggerSource() as the \e +//! trigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Valley capture trigged by software + EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U, + //! Valley capture trigged by when counter is equal to zero + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U, + //! Valley capture trigged by when counter is equal period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U, + //! Valley capture trigged when counter is equal to zero or period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U, + //! Valley capture trigged by DCAEVT1 (Digital Compare A event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U, + //! Valley capture trigged by DCAEVT2 (Digital Compare A event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U, + //! Valley capture trigged by DCBEVT1 (Digital Compare B event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U, + //! Valley capture trigged by DCBEVT2 (Digital Compare B event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U +} EPWM_ValleyTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_getValleyCountEdgeStatus() as the \e edge +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_VALLEY_COUNT_START_EDGE = 0, //!< Valley count start edge + EPWM_VALLEY_COUNT_STOP_EDGE = 1 //!< Valley count stop edge +} EPWM_ValleyCounterEdge; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyDelayValue() as the \e delayMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Delay value equals the offset value defines by software + EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U, + //! Delay value equals the sum of the Hardware counter value and the offset + //! value defines by software + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U, + //! Delay value equals the the Hardware counter shifted by + //! (1 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U, + //! Delay value equals the the Hardware counter shifted by + //! (2 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U, + //! Delay value equals the the Hardware counter shifted by + //! (4 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U +} EPWM_ValleyDelayMode; + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterMode() +//! as the \e edgeMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_MODE_RISING = 0, //!< Digital Compare Edge filter low + //!< to high edge mode + EPWM_DC_EDGEFILT_MODE_FALLING = 1, //!< Digital Compare Edge filter high + //!< to low edge mode + EPWM_DC_EDGEFILT_MODE_BOTH = 2 //!< Digital Compare Edge filter both + //!< edges mode +} EPWM_DigitalCompareEdgeFilterMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterEdgeCount() +//! as the \e edgeCount parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_EDGECNT_0 = 0, //!< Digital Compare Edge filter edge + //!< count = 0 + EPWM_DC_EDGEFILT_EDGECNT_1 = 1, //!< Digital Compare Edge filter edge + //!< count = 1 + EPWM_DC_EDGEFILT_EDGECNT_2 = 2, //!< Digital Compare Edge filter edge + //!< count = 2 + EPWM_DC_EDGEFILT_EDGECNT_3 = 3, //!< Digital Compare Edge filter edge + //!< count = 3 + EPWM_DC_EDGEFILT_EDGECNT_4 = 4, //!< Digital Compare Edge filter edge + //!< count = 4 + EPWM_DC_EDGEFILT_EDGECNT_5 = 5, //!< Digital Compare Edge filter edge + //!< count = 5 + EPWM_DC_EDGEFILT_EDGECNT_6 = 6, //!< Digital Compare Edge filter edge + //!< count = 6 + EPWM_DC_EDGEFILT_EDGECNT_7 = 7 //!< Digital Compare Edge filter edge + //!< count = 7 +} EPWM_DigitalCompareEdgeFilterEdgeCount; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_configureSignal() as the +//! \e signalParams parameter. +// +//***************************************************************************** +typedef struct +{ + float32_t freqInHz; //!< Desired Signal Frequency(in Hz) + float32_t dutyValA; //!< Desired ePWMxA Signal Duty + float32_t dutyValB; //!< Desired ePWMxB Signal Duty + bool invertSignalB; //!< Invert ePWMxB Signal if true + float32_t sysClkInHz; //!< SYSCLK Frequency(in Hz) + SysCtl_EPWMCLKDivider epwmClkDiv; //!< EPWM Clock Divider + EPWM_TimeBaseCountMode tbCtrMode; //!< Time Base Counter Mode + EPWM_ClockDivider tbClkDiv; //!< Time Base Counter Clock Divider + EPWM_HSClockDivider tbHSClkDiv; //!< Time Base Counter HS Clock Divider +} EPWM_SignalParams; + +//***************************************************************************** +// +// Functions APIs shared with HRPWM module +// +//***************************************************************************** + +// +// Period Control related API +// +#define EPWM_setSyncPulseSource HRPWM_setSyncPulseSource + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks ePWM base address. +//! +//! \param base specifies the ePWM module base address. +//! +//! This function determines if an ePWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool EPWM_isBaseValid(uint32_t base) +{ + return( + (base == EPWM1_BASE) || + (base == EPWM2_BASE) || + (base == EPWM3_BASE) || + (base == EPWM4_BASE) || + (base == EPWM5_BASE) || + (base == EPWM6_BASE) || + (base == EPWM7_BASE) || + (base == EPWM8_BASE) || + (base == EPWM9_BASE) || + (base == EPWM10_BASE) || + (base == EPWM11_BASE) || + (base == EPWM12_BASE) + ); +} +#endif + +// +// Time Base Sub Module related APIs +// +//***************************************************************************** +// +//! Set the time base count +//! +//! \param base is the base address of the EPWM module. +//! \param count is the time base count value. +//! +//! This function sets the 16 bit counter value of the time base counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounter(uint32_t base, uint16_t count) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBCTR register + // + HWREGH(base + EPWM_O_TBCTR) = count; +} + +//***************************************************************************** +// +//! Set count mode after phase shift sync +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the count mode. +//! +//! This function sets the time base count to count up or down after a new +//! phase value set by the EPWM_setPhaseShift(). The count direction is +//! determined by the variable mode. Valid inputs for mode are: +//! - EPWM_COUNT_MODE_UP_AFTER_SYNC - Count up after sync +//! - EPWM_COUNT_MODE_DOWN_AFTER_SYNC - Count down after sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC) + { + // + // Set PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSDIR; + } + else + { + // + // Clear PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSDIR; + } +} + +//***************************************************************************** +// +//! Set the time base clock and the high speed time base clock count pre-scaler +//! +//! \param base is the base address of the EPWM module. +//! \param prescaler is the time base count pre scale value. +//! \param highSpeedPrescaler is the high speed time base count pre scale +//! value. +//! +//! This function sets the pre scaler(divider)value for the time base clock +//! counter and the high speed time base clock counter. +//! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X, +//! where X is 1,2,4,8,16, 32,64 or 128. +//! The actual numerical values for these macros represent values 0,1...7. +//! The equation for the output clock is: +//! TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler) +//! +//! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half +//! SYSCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, + EPWM_HSClockDivider highSpeedPrescaler) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CLKDIV and HSPCLKDIV bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & + ~(EPWM_TBCTL_CLKDIV_M | EPWM_TBCTL_HSPCLKDIV_M)) | + (((uint16_t)prescaler << EPWM_TBCTL_CLKDIV_S) | + ((uint16_t)highSpeedPrescaler << EPWM_TBCTL_HSPCLKDIV_S))); +} + +//***************************************************************************** +// +//! Force a software sync pulse +//! +//! \param base is the base address of the EPWM module. +//! +//! This function causes a single software initiated sync pulse. Make sure the +//! appropriate mode is selected using EPWM_setupSyncOutputMode() before using +//! this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceSyncPulse(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SWFSYNC bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_SWFSYNC; +} + +//***************************************************************************** +// +//! Set up the sync out pulse event +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the sync out mode. +//! +//! This function set the sync out pulse mode. +//! Valid values for mode are: +//! - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - sync pulse is generated by software +//! when EPWM_forceSyncPulse() +//! function is called or by EPWMxSYNCI +//! signal. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO - sync pulse is generated when +//! time base counter equals zero. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B - sync pulse is generated when +//! time base counter equals compare +//! B value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C - sync pulse is generated when +//! time base counter equals compare +//! C value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D - sync pulse is generated when +//! time base counter equals compare +//! D value. +//! - EPWM_SYNC_OUT_PULSE_DISABLED - sync pulse is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setSyncOutPulseMode(uint32_t base, EPWM_SyncOutPulseMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // No extended mode support + // + if(mode < EPWM_SYNC_OUT_PULSE_DISABLED) + { + // + // Write to SYNCOSEL bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_SYNCOSEL_M)) | + ((uint16_t)mode << EPWM_TBCTL_SYNCOSEL_S)); + } + // + // Extended modes and sync out disable mode + // + else + { + // + // Write 0x3 to SYNCOSEL to enable selection from SYNCOSELX + // + HWREGH(base + EPWM_O_TBCTL) = HWREGH(base + EPWM_O_TBCTL) | + EPWM_TBCTL_SYNCOSEL_M; + + // + // Write to SYNCOSELX bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_SYNCOSELX_M)) | + (((uint16_t)mode & 0x3U) << EPWM_TBCTL2_SYNCOSELX_S)); + } +} + +//***************************************************************************** +// +//! Set PWM period load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the PWM period load mode. +//! +//! This function sets the load mode for the PWM period. If loadMode is set to +//! EPWM_PERIOD_SHADOW_LOAD, a write or read to the TBPRD (PWM Period count +//! register) accesses the shadow register. If loadMode is set to +//! EPWM_PERIOD_DIRECT_LOAD, a write or read to the TBPRD register accesses the +//! register directly. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(loadMode == EPWM_PERIOD_SHADOW_LOAD) + { + // + // Clear PRDLD + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PRDLD; + } + else + { + // + // Set PRDLD + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PRDLD; + } +} + +//***************************************************************************** +// +//! Enable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of phase shift when the appropriate sync +//! event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Disable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of phase shift. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Set time base counter mode +//! +//! \param base is the base address of the EPWM module. +//! \param counterMode is the time base counter mode. +//! +//! This function sets up the time base counter mode. +//! Valid values for counterMode are: +//! - EPWM_COUNTER_MODE_UP - Up - count mode. +//! - EPWM_COUNTER_MODE_DOWN - Down - count mode. +//! - EPWM_COUNTER_MODE_UP_DOWN - Up - down - count mode. +//! - EPWM_COUNTER_MODE_STOP_FREEZE - Stop - Freeze counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CTRMODE bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_CTRMODE_M)) | + ((uint16_t)counterMode)); +} + +//***************************************************************************** +// +//! Set shadow to active period load on sync mode +//! +//! \param base is the base address of the EPWM module. +//! \param shadowLoadMode is the shadow to active load mode. +//! +//! This function sets up the shadow to active Period register load mode with +//! respect to a sync event. Valid values for shadowLoadMode are: +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO - shadow to active load occurs when +//! time base counter reaches 0. +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC - shadow to active load occurs when +//! time base counter reaches 0 and a +//! SYNC occurs. +//! - EPWM_SHADOW_LOAD_MODE_SYNC - shadow to active load occurs only +//! when a SYNC occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_selectPeriodLoadEvent(uint32_t base, + EPWM_PeriodShadowLoadMode shadowLoadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to PRDLDSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_PRDLDSYNC_M)) | + ((uint16_t)shadowLoadMode << EPWM_TBCTL2_PRDLDSYNC_S)); +} +//***************************************************************************** +// +//! Enable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Disable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) &= ~EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Start one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function propagates a one shot sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNC; +} + +//***************************************************************************** +// +//! Returns time base counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the current value of the time base counter. +//! +//! \return returns time base counter value +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterValue(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Returns TBCTR value + // + return(HWREGH(base + EPWM_O_TBCTR)); +} + +//***************************************************************************** +// +//! Return time base counter maximum status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the status of the time base max counter. +//! +//! \return Returns true if the counter has reached 0xFFFF. +//! Returns false if the counter hasn't reached 0xFFFF. +// +//***************************************************************************** +static inline bool +EPWM_getTimeBaseCounterOverflowStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if CTRMAX bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRMAX) == + EPWM_TBSTS_CTRMAX) ? true : false); +} + +//***************************************************************************** +// +//! Clear max time base counter event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the max time base counter latch event. The latch event +//! occurs when the time base counter reaches its maximum value of 0xFFFF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CTRMAX bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_CTRMAX; +} + +//***************************************************************************** +// +//! Return external sync signal status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the external sync signal status. +//! +//! \return Returns true if if an external sync signal event +//! Returns false if there is no event. +// +//***************************************************************************** +static inline bool +EPWM_getSyncStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if SYNCI bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_SYNCI) == + EPWM_TBSTS_SYNCI) ? true : false); +} + +//***************************************************************************** +// +//! Clear external sync signal event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the external sync signal latch event. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearSyncEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SYNCI bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_SYNCI; +} + +//***************************************************************************** +// +//! Return time base counter direction. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the direction of the time base counter. +//! +//! \return returns EPWM_TIME_BASE_STATUS_COUNT_UP if the counter is counting +//! up or EPWM_TIME_BASE_STATUS_COUNT_DOWN if the counter is +//! counting down. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterDirection(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return CTRDIR bit + // + return(HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRDIR); +} + +//***************************************************************************** +// +//! Sets the phase shift offset counter value. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the phase shift count value. +//! +//! This function sets the 16 bit time-base counter phase of the ePWM relative +//! to the time-base that is supplying the synchronization input signal. Call +//! the EPWM_enablePhaseShiftLoad() function to enable loading of the +//! phaseCount phase shift value when a sync event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPHS bit + // + HWREG(base + EPWM_O_TBPHS) = + ((HWREG(base + EPWM_O_TBPHS) & + ~((uint32_t)EPWM_TBPHS_TBPHS_M)) | + ((uint32_t)phaseCount << EPWM_TBPHS_TBPHS_S)); +} + +//***************************************************************************** +// +//! Sets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is period count value. +//! +//! This function sets the period of the PWM count. The value of periodCount is +//! the value written to the register. User should map the desired period or +//! frequency of the waveform into the correct periodCount. +//! Invoke the function EPWM_selectPeriodLoadEvent() with the appropriate +//! parameter to set the load mode of the Period count. periodCount has a +//! maximum valid value of 0xFFFF +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPRD bit + // + HWREGH(base + EPWM_O_TBPRD) = periodCount; +} + +//***************************************************************************** +// +//! Gets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the period of the PWM count. +//! +//! \return The period count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read from TBPRD bit + // + return(HWREGH(base + EPWM_O_TBPRD)); +} + +//***************************************************************************** +// +//! Sets the EPWM links. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmLink is the ePWM instance to link with. +//! \param linkComp is the ePWM component to link. +//! +//! This function links the component defined in linkComp in the current ePWM +//! instance with the linkComp component of the ePWM instance defined by +//! epwmLink. A change (a write) in the value of linkComp component of epwmLink +//! instance, causes a change in the current ePWM linkComp component. +//! For example if the current ePWM is ePWM3 and the values of epwmLink and +//! linkComp are EPWM_LINK_WITH_EPWM_1 and EPWM_LINK_COMP_C respectively, +//! then a write to COMPC register in ePWM1, will result in a simultaneous +//! write to COMPC register in ePWM3. +//! Valid values for epwmLink are: +//! - EPWM_LINK_WITH_EPWM_1 - link current ePWM with ePWM1 +//! - EPWM_LINK_WITH_EPWM_2 - link current ePWM with ePWM2 +//! - EPWM_LINK_WITH_EPWM_3 - link current ePWM with ePWM3 +//! - EPWM_LINK_WITH_EPWM_4 - link current ePWM with ePWM4 +//! - EPWM_LINK_WITH_EPWM_5 - link current ePWM with ePWM5 +//! - EPWM_LINK_WITH_EPWM_6 - link current ePWM with ePWM6 +//! - EPWM_LINK_WITH_EPWM_7 - link current ePWM with ePWM7 +//! - EPWM_LINK_WITH_EPWM_8 - link current ePWM with ePWM8 +//! - EPWM_LINK_WITH_EPWM_9 - link current ePWM with ePWM9 +//! - EPWM_LINK_WITH_EPWM_10 - link current ePWM with ePWM10 +//! - EPWM_LINK_WITH_EPWM_11 - link current ePWM with ePWM11 +//! - EPWM_LINK_WITH_EPWM_12 - link current ePWM with ePWM12 +//! +//! Valid values for linkComp are: +//! - EPWM_LINK_TBPRD - link TBPRD:TBPRDHR registers +//! - EPWM_LINK_COMP_A - link COMPA registers +//! - EPWM_LINK_COMP_B - link COMPB registers +//! - EPWM_LINK_COMP_C - link COMPC registers +//! - EPWM_LINK_COMP_D - link COMPD registers +//! - EPWM_LINK_GLDCTL2 - link GLDCTL2 registers +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, + EPWM_LinkComponent linkComp) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + uint32_t registerOffset; + registerOffset = base + EPWM_O_XLINK; + + // + // Configure EPWM links + // + HWREG(registerOffset) = + ((HWREG(registerOffset) & ~((uint32_t)EPWM_XLINK_TBPRDLINK_M << (uint32_t)linkComp)) | + ((uint32_t)epwmLink << (uint32_t)linkComp)); +} + + +//***************************************************************************** +// +//! Sets up the Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets up the counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! - loadMode +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD -load when counter equals period +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule, + EPWM_CounterCompareLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t loadModeOffset; + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + syncModeOffset = 10U; + loadModeOffset = 0U; + shadowModeOffset = 4U; + } + else + { + syncModeOffset = 12U; + loadModeOffset = 2U; + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(registerOffset) = ((HWREGH(registerOffset) & + ~((0x3U << syncModeOffset) | // Clear sync mode + (0x3U << loadModeOffset) | // Clear load mode + (0x1U << shadowModeOffset))) | // shadow mode + ((((uint16_t)loadMode >> 2U) << syncModeOffset) | + (((uint16_t)loadMode & 0x3U) << loadModeOffset))); +} + +//***************************************************************************** +// +//! Disable Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! +//! This function disables counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + shadowModeOffset = 4U; + } + else + { + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Disable shadow load mode. + // + HWREGH(registerOffset) = (HWREGH(registerOffset) | + (0x1U << shadowModeOffset)); +} + +//***************************************************************************** +// +//! Set counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! \param compCount is the counter compare count value. +//! +//! This function sets the counter compare value for counter compare registers. +//! The maximum value for compCount is 0xFFFF. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, + uint16_t compCount) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Write to the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Write to COMPA or COMPB bits + // + HWREGH(base + registerOffset + 0x1U) = compCount; + } + else + { + // + // Write to COMPC or COMPD bits + // + HWREGH(base + registerOffset) = compCount; + } +} + +//***************************************************************************** +// +//! Get counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function gets the counter compare value for counter compare registers. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return The counter compare count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule) +{ + uint32_t registerOffset; + uint16_t compCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Read from the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Read COMPA or COMPB bits + // + compCount = (uint16_t)((HWREG(base + registerOffset) & + 0xFFFF0000UL) >> 16U); + } + else + { + // + // Read COMPC or COMPD bits + // + compCount = HWREGH(base + registerOffset); + } + return(compCount); +} + +//***************************************************************************** +// +//! Return the counter compare shadow register full status. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function returns the counter Compare shadow register full status flag. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return Returns true if the shadow register is full. +//! Returns false if the shadow register is not full. +// +//***************************************************************************** +static inline bool +EPWM_getCounterCompareShadowStatus(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Check the validity of input. + // COMPA and COMPB are valid input arguments. + // + ASSERT((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)); + + // + // Read the value of SHDWAFULL or SHDWBFULL bit + // + return((((HWREG(base + EPWM_O_CMPCTL) >> + ((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) & + 0x1U) == 0x1U) ? true:false); +} + +// +// Action Qualifier module related APIs +// +//***************************************************************************** +// +//! Sets the Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! - loadMode +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_AQ_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter +//! equals zero +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter +//! equals period +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when +//! counter equals zero or period +//! - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule, + EPWM_ActionQualifierLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + syncModeOffset = 8U + (uint16_t)aqModule; + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(base + EPWM_O_AQCTL) = ((HWREGH(base + EPWM_O_AQCTL) & + (~((0x3U << (uint16_t)aqModule) | + (0x3U << (uint16_t)syncModeOffset))) | + (0x1U << shadowModeOffset)) | + ((((uint16_t)loadMode >> 2U) << + syncModeOffset) | (((uint16_t)loadMode & + 0x3U) << (uint16_t)aqModule))); +} + +//***************************************************************************** +// +//! Disable Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! +//! This function disables the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule) +{ + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Disable shadow load mode. Action qualifier is loaded on + // immediate mode only. + // + HWREGH(base + EPWM_O_AQCTL) &= ~(1U << shadowModeOffset); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T1 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T1. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT1TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T1 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T1SEL_M)) | + ((uint16_t)trigger)); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T2 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T2. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT2TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T2 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T2SEL_M)) | + ((uint16_t)trigger << EPWM_AQTSRCSEL_T2SEL_S)); +} + +//***************************************************************************** +// +//! Set up Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! \param event is the event that causes a change in output. +//! +//! This function sets up the Action Qualifier output on ePWM A or ePWMB, +//! depending on the value of epwmOutput, to a value specified by outPut based +//! on the input events - specified by event. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! - event +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO - Time base counter equals +//! zero +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD - Time base counter equals +//! period +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA - Time base counter up equals +//! COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA - Time base counter down +//! equals COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB - Time base counter up equals +//! COMPB +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB - Time base counter down +//! equals COMPB +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP - T1 event on count up +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN - T1 event on count down +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP - T2 event on count up +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN - T2 event on count down +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output, + EPWM_ActionQualifierOutputEvent event) +{ + uint32_t registerOffset; + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // If the event occurs on T1 or T2 events + // + if(((uint16_t)event & 0x1U) == 1U) + { + // + // Write to T1U,T1D,T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = + ((HWREGH(base + registerTOffset) & ~(3U << ((uint16_t)event - 1U))) | + ((uint16_t)output << ((uint16_t)event - 1U))); + } + else + { + // + // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~(3U << (uint16_t)event)) | + ((uint16_t)output << (uint16_t)event)); + } +} + +//***************************************************************************** +// +//! Set up Action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Action Qualifier output on ePWMA or ePWMB, +//! depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different time base counter scenarios +//! should be OR'd together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! - action +//! - When time base counter equals zero +//! - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO - Time base counter equals zero +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_ZERO - Time base counter equals zero +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_ZERO - Time base counter equals zero +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_ZERO - Time base counter equals zero +//! and toggle the output pins +//! - When time base counter equals period +//! - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_PERIOD - Time base counter equals period +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_PERIOD - Time base counter equals period +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_PERIOD - Time base counter equals period +//! and toggle the output pins +//! - When time base counter equals CMPA during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA - Time base counter up equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPA - Time base counter up equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPA - Time base counter up equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA - Time base counter up equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPA during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA - Time base counter down equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA - Time base counter down equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPB during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB - Time base counter up equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPB - Time base counter up equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPB - Time base counter up equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB - Time base counter up equals +//! COMPB and toggle output pins +//! - When time base counter equals CMPB during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB - Time base counter down equals +//! COMPB and toggle output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each time base +//! counter scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + + // + // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Set up Additional action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Additional Action Qualifier output on ePWMA or +//! ePWMB depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different event scenarios should be OR'd +//! together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - action +//! - When T1 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 - T1 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T1 - T1 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T1 - T1 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T1 - T1 event on count up +//! and toggle the output pins +//! - When T1 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1- T1 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T1 - T1 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T1 - T1 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 - T1 event on count down +//! and toggle the output pins +//! - When T2 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 - T2 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T2 - T2 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T2 - T2 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T2 - T2 event on count up +//! and toggle the output pins +//! - When T2 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 - T2 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T2 - T2 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T2 - T2 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 - T2 event on count down +//! and toggle the output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each event +//! scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // Write to T1U, T1D, T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Sets up Action qualifier continuous software load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the mode for shadow to active load mode. +//! +//! This function sets up the AQCFRSC register load mode for continuous +//! software force reload mode. The software force actions are determined by +//! the EPWM_setActionQualifierContSWForceAction() function. +//! Valid values for mode are: +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO - shadow mode load when counter +//! equals zero +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD - shadow mode load when counter +//! equals period +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter +//! equals zero or period +//! - EPWM_AQ_SW_IMMEDIATE_LOAD - immediate mode load only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, + EPWM_ActionQualifierContForce mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action qualifier software action reload mode. + // Write to RLDCSF bit + // + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_RLDCSF_M) | + ((uint16_t)mode << EPWM_AQSFRC_RLDCSF_S)); +} + +//***************************************************************************** +// +//! Triggers a continuous software forced event. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function triggers a continuous software forced Action Qualifier output +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for the parameters are: +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_SW_DISABLED - Software forcing disabled. +//! - EPWM_AQ_SW_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_SW_OUTPUT_HIGH - Set output pins to High +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierSWOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a continuous software forced output + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFB_M) | + ((uint16_t)output << EPWM_AQCSFRC_CSFB_S)) ; + } +} + +//***************************************************************************** +// +//! Set up one time software forced Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function sets up the one time software forced Action Qualifier output +//! on ePWM A or ePWMB, depending on the value of epwmOutput to a value +//! specified by outPut. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the one time software forced action + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFB_M) | + ((uint16_t)output << EPWM_AQSFRC_ACTSFB_S)); + } +} + +//***************************************************************************** +// +//! Triggers a one time software forced event on Action qualifier +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! +//! This function triggers a one time software forced Action Qualifier event +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for epwmOutput are: +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a software forced event + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFA; + } + else + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFB; + } +} + +// +// Dead Band Module related APIs +// +//***************************************************************************** +// +//! Sets Dead Band signal output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param output is the ePWM Dead Band output. +//! \param enableSwapMode is the output swap mode. +//! +//! This function sets up the output signal swap mode. For example if the +//! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then +//! the ePWM A output gets its signal from the ePWM B signal path. Valid values +//! for the input variables are: +//! - output +//! - EPWM_DB_OUTPUT_A - ePWM output A +//! - EPWM_DB_OUTPUT_B - ePWM output B +//! - enableSwapMode +//! - true - the output is swapped +//! - false - the output and the signal path are the same. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, + bool enableSwapMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)output + EPWM_DBCTL_OUTSWAP_S); + + if(enableSwapMode) + { + // + // Set the appropriate outswap bit to swap output + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band signal output mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param enableDelayMode is the dead band delay mode. +//! +//! This function sets up the dead band delay mode. The delayMode variable +//! determines if the applied delay is Rising Edge or Falling Edge. The +//! enableDelayMode determines if a dead band delay should be applied. +//! Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - enableDelayMode +//! - true - Falling edge or Rising edge delay is applied. +//! - false - Dead Band delay is bypassed. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, + bool enableDelayMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)delayMode + EPWM_DBCTL_OUT_MODE_S); + + if(enableDelayMode) + { + // + // Set the appropriate outmode bit to enable Dead Band delay + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~ mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band delay polarity. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param polarity is the polarity of the delayed signal. +//! +//! This function sets up the polarity as determined by the variable polarity +//! of the Falling Edge or Rising Edge delay depending on the value of +//! delayMode. Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - polarity +//! - EPWM_DB_POLARITY_ACTIVE_HIGH - polarity is not inverted. +//! - EPWM_DB_POLARITY_ACTIVE_LOW - polarity is inverted. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayPolarity(uint32_t base, + EPWM_DeadBandDelayMode delayMode, + EPWM_DeadBandPolarity polarity) +{ + uint16_t shift; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shift = (((uint16_t)delayMode ^ 0x1U) + EPWM_DBCTL_POLSEL_S); + + // + // Set the appropriate polsel bits for dead band polarity + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~ (1U << shift)) | + ((uint16_t)polarity << shift)); +} + +//***************************************************************************** +// +//! Sets Rising Edge Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA( Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB( Valid for both Falling +//! Edge and Rising Edge) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB)); + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S))) | + (input << EPWM_DBCTL_IN_MODE_S)); +} + +//***************************************************************************** +// +//! Sets Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_DB_RED - Input signal is the output of Rising +//! Edge delay. +//! (Valid only for Falling Edge delay) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB) || + (input == EPWM_DB_INPUT_DB_RED)); + + if(input == EPWM_DB_INPUT_DB_RED) + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) |= EPWM_DBCTL_DEDB_MODE; + } + else + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) &= ~EPWM_DBCTL_DEDB_MODE; + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S + 1U))) | + (input << (EPWM_DBCTL_IN_MODE_S + 1U))); + } +} + +//***************************************************************************** +// +//! Set the Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Dead Band control register shadow +//! load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_DB_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_DB_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_DB_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandControlShadowLoadMode(uint32_t base, + EPWM_DeadBandControlLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode and setup the load event + // + HWREGH(base + EPWM_O_DBCTL2) = + ((HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_LOADDBCTLMODE_M) | + (EPWM_DBCTL2_SHDWDBCTLMODE | (uint16_t)loadMode)); +} + +//***************************************************************************** +// +//! Disable Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Dead Band control register shadow +//! load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDeadBandControlShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow load mode. Only immediate load mode only. + // + HWREGH(base + EPWM_O_DBCTL2) = + (HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_SHDWDBCTLMODE); +} + +//***************************************************************************** +// +//! Set the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function sets the Rising Edge Delay register shadow load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_RED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_RED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_RED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_RisingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Set-up the load mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADREDMODE_M) | + ((uint16_t)EPWM_DBCTL_SHDWDBREDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADREDMODE_S))); + +} + +//***************************************************************************** +// +//! Disable the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Rising Edge Delay register shadow load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBREDMODE); + +} + +//***************************************************************************** +// +//! Set the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function enables and sets the Falling Edge Delay register shadow load +//! mode. Valid values for the \e loadMode parameters are: +//! - EPWM_FED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_FED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_FED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_FallingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Setup the load mode. + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADFEDMODE_M) | + (EPWM_DBCTL_SHDWDBFEDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADFEDMODE_S))); + +} + +//***************************************************************************** +// +//! Disables the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Falling Edge Delay register shadow load mode. +//! Valid values for the parameters are: +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBFEDMODE); +} + +//***************************************************************************** +// +//! Sets Dead Band Counter clock rate. +//! +//! \param base is the base address of the EPWM module. +//! \param clockMode is the Dead Band counter clock mode. +//! +//! This function sets up the Dead Band counter clock rate with respect to +//! TBCLK (ePWM time base counter). +//! Valid values for clockMode are: +//! - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE -Dead band counter runs at TBCLK +//! (ePWM Time Base Counter) rate. +//! - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE -Dead band counter runs at 2*TBCLK +//! (twice ePWM Time Base Counter)rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandCounterClock(uint32_t base, + EPWM_DeadBandClockMode clockMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DB clock mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_HALFCYCLE) | + ((uint16_t)clockMode << 15U)); +} + +//***************************************************************************** +// +//! Set ePWM RED count +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the RED(Rising Edge Delay) count. +//! +//! This function sets the RED (Rising Edge Delay) count value. +//! The value of redCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(redCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBRED) = redCount; +} + +//***************************************************************************** +// +//! Set ePWM FED count +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the FED(Falling Edge Delay) count. +//! +//! This function sets the FED (Falling Edge Delay) count value. +//! The value of fedCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(fedCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBFED) = fedCount; +} + +// +// Chopper module related APIs +// +//***************************************************************************** +// +//! Enable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CHPEN bit. Enable Chopper + // + HWREGH(base + EPWM_O_PCCTL) |= EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Disable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear CHPEN bit. Disable Chopper + // + HWREGH(base + EPWM_O_PCCTL) &= ~EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Set chopper duty cycle. +//! +//! \param base is the base address of the EPWM module. +//! \param dutyCycleCount is the chopping clock duty cycle count. +//! +//! This function sets the chopping clock duty cycle. The value of +//! dutyCycleCount should be less than 7. The dutyCycleCount value is converted +//! to the actual chopper duty cycle value base on the following equation: +//! chopper duty cycle = (dutyCycleCount + 1) / 8 +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(dutyCycleCount < 7U); + + // + // Set the chopper duty cycle + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & ~EPWM_PCCTL_CHPDUTY_M) | + (dutyCycleCount << EPWM_PCCTL_CHPDUTY_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param freqDiv is the chopping clock frequency divider. +//! +//! This function sets the scaler for the chopping clock frequency. The value +//! of freqDiv should be less than 8. The chopping clock frequency is altered +//! based on the following equation. +//! chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(freqDiv < 8U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_CHPFREQ_M) | + (freqDiv << EPWM_PCCTL_CHPFREQ_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param firstPulseWidth is the width of the first pulse. +//! +//! This function sets the first pulse width of chopper output waveform. The +//! value of firstPulseWidth should be less than 0x10. The value of the first +//! pulse width in seconds is given using the following equation: +//! first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(firstPulseWidth < 16U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_OSHTWTH_M) | + (firstPulseWidth << EPWM_PCCTL_OSHTWTH_S)); +} + +// +// Trip Zone module related APIs +// +//***************************************************************************** +// +//! Enables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function enables the Trip Zone signals specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) |= tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Disables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function disables the Trip Zone signal specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) &= ~tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Set Digital compare conditions that cause Trip Zone event. +//! +//! \param base is the base address of the EPWM module. +//! \param dcType is the Digital compare output type. +//! \param dcEvent is the Digital Compare output event. +//! +//! This function sets up the Digital Compare output Trip Zone event sources. +//! The dcType variable specifies the event source to be whether Digital +//! Compare output A or Digital Compare output B. The dcEvent parameter +//! specifies the event that causes Trip Zone. +//! Valid values for the parameters are: +//! - dcType +//! - EPWM_TZ_DC_OUTPUT_A1 - Digital Compare output 1 A +//! - EPWM_TZ_DC_OUTPUT_A2 - Digital Compare output 2 A +//! - EPWM_TZ_DC_OUTPUT_B1 - Digital Compare output 1 B +//! - EPWM_TZ_DC_OUTPUT_B2 - Digital Compare output 2 B +//! - dcEvent +//! - EPWM_TZ_EVENT_DC_DISABLED - Event Trigger is disabled +//! - EPWM_TZ_EVENT_DCXH_LOW - Trigger event when DCxH low +//! - EPWM_TZ_EVENT_DCXH_HIGH - Trigger event when DCxH high +//! - EPWM_TZ_EVENT_DCXL_LOW - Trigger event when DCxL low +//! - EPWM_TZ_EVENT_DCXL_HIGH - Trigger event when DCxL high +//! - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW - Trigger event when DCxL high +//! DCxH low +//! +//! \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, + EPWM_TripZoneDigitalCompareOutput dcType, + EPWM_TripZoneDigitalCompareOutputEvent dcEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set Digital Compare Events conditions that cause a Digital Compare trip + // + EALLOW; + HWREGH(base + EPWM_O_TZDCSEL) = + ((HWREGH(base + EPWM_O_TZDCSEL) & ~(0x7U << (uint16_t)dcType)) | + ((uint16_t)dcEvent << (uint16_t)dcType)); + EDIS; +} + +//***************************************************************************** +// +//! Enable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the advanced actions of the Trip Zone events. The +//! advanced features combine the trip zone events with the direction of the +//! counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Advanced feature. Set ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Disable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the advanced actions of the Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Advanced feature. clear ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) &= ~EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzEvent is the Trip Zone event type. +//! \param tzAction is the Trip zone Action. +//! +//! This function sets the Trip Zone Action to be taken when a Trip Zone event +//! occurs. +//! Valid values for the parameters are: +//! - tzEvent +//! - EPWM_TZ_ACTION_EVENT_DCBEVT2 - DCBEVT2 (Digital Compare B event 2) +//! - EPWM_TZ_ACTION_EVENT_DCBEVT1 - DCBEVT1 (Digital Compare B event 1) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT2 - DCAEVT2 (Digital Compare A event 2) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT1 - DCAEVT1 (Digital Compare A event 1) +//! - EPWM_TZ_ACTION_EVENT_TZB - TZ1 - TZ6, DCBEVT2, DCBEVT1 +//! - EPWM_TZ_ACTION_EVENT_TZA - TZ1 - TZ6, DCAEVT2, DCAEVT1 +//! - tzAction +//! - EPWM_TZ_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ACTION_HIGH - high output +//! - EPWM_TZ_ACTION_LOW - low low +//! - EPWM_TZ_ACTION_DISABLE - disable action +//! +//! \note Disable the advanced Trip Zone event using +//! EPWM_disableTripZoneAdvAction() before calling this function. +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzEvent parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, + EPWM_TripZoneAction tzAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL) = + ((HWREGH(base + EPWM_O_TZCTL) & ~(0x3U << (uint16_t)tzEvent)) | + ((uint16_t)tzAction << (uint16_t)tzEvent)) ; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvEvent is the Trip Zone event type. +//! \param tzAdvAction is the Trip zone Action. +//! +//! This function sets the Advanced Trip Zone Action to be taken when an +//! advanced Trip Zone event occurs. +//! +//! Valid values for the parameters are: +//! - tzAdvEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_D - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_U - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_D - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_U - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting up +//! - tzAdvAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzAdvEvent parameter. +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, + EPWM_TripZoneAdvancedAction tzAdvAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) = + ((HWREGH(base + EPWM_O_TZCTL2) & ~(0x7U << (uint16_t)tzAdvEvent)) | + ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMA. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event A2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event A2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event A1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event A1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCA) = + ((HWREGH(base + EPWM_O_TZCTLDCA) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMB. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event B2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event B2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event B1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event B1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCB) = + ((HWREGH(base + EPWM_O_TZCTLDCB) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function enables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Enable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) |= tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Disable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function disables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Disable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) &= ~tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Gets the Trip Zone status flag +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the Trip Zone status flag. +//! +//! \return The function returns the following or the bitwise OR value +//! of the following values. +//! - EPWM_TZ_INTERRUPT - Trip Zone interrupt was generated +//! due to the following TZ events. +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle event status flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot event status flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag +// +//*************************************************************************** +static inline uint16_t +EPWM_getTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZFLG) & 0x7FU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone Cycle by Cycle flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific Cycle by Cycle Trip Zone flag +//! status. +//! +//! \return The function returns the following values. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 status flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 status flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 status flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 status flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 status flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 status flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC status flag for Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC status flag for Digital compare +//! event B2 +// +//*************************************************************************** +static inline uint16_t +EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Cycle By Cycle Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZCBCFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone One Shot flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific One Shot Trip Zone flag status. +//! +//! \return The function returns the bitwise OR of the following flags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST status flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST status flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST status flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST status flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST status flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST status flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST status flag for Digital +//! compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST status flag for Digital +//! compare event B1 +// +//*************************************************************************** +static inline uint16_t +EPWM_getOneShotTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the One Shot Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZOSTFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Set the Trip Zone CBC pulse clear event. +//! +//! \param base is the base address of the EPWM module. +//! \param clearEvent is the CBC trip zone clear event. +//! +//! This function set the event which automatically clears the +//! CBC (Cycle by Cycle) latch. +//! Valid values for clearEvent are: +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO - Clear CBC pulse when counter +//! equals zero +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD - Clear CBC pulse when counter +//! equals period +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD - Clear CBC pulse when counter +//! equals zero or period +//! +//! \return None. +// +//************************************************************************** +static inline void +EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, + EPWM_CycleByCycleTripZoneClearMode clearEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Cycle by Cycle Trip Latch mode + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) = + ((HWREGH(base + EPWM_O_TZCLR) & ~EPWM_TZCLR_CBCPULSE_M) | + ((uint16_t)clearEvent << EPWM_TZCLR_CBCPULSE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Clear Trip Zone flag +//! +//! \param base is the base address of the EPWM module. +//! \param tzFlags is the Trip Zone flags. +//! +//! This function clears the Trip Zone flags +//! Valid values for tzFlags are: +//! - EPWM_TZ_INTERRUPT - Global Trip Zone interrupt flag +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag +//! +//! \b note: A bitwise OR of the valid values can be passed as the tzFlags +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzFlags <= 0x80U); + + // + // Clear Trip zone event flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) |= tzFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone Cycle by Cycle flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzCBCFlags is the CBC flag to be cleared. +//! +//! This function clears the specific Cycle by Cycle Trip Zone flag. +//! The following are valid values for tzCBCFlags. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC flag Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC flag Digital compare +//! event B2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzCBCFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCBCCLR) |= tzCBCFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone One Shot flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzOSTFlags is the OST flags to be cleared. +//! +//! This function clears the specific One Shot (OST) Trip Zone flag. +//! The following are valid values for tzOSTFlags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST flag for Digital compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST flag for Digital compare event B1 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzOSTFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZOSTCLR) |= tzOSTFlags; + EDIS; +} + +//***************************************************************************** +// +//! Force Trip Zone events. +//! +//! \param base is the base address of the EPWM module. +//! \param tzForceEvent is the forced Trip Zone event. +//! +//! This function forces a Trip Zone event. +//! Valid values for tzForceEvent are: +//! - EPWM_TZ_FORCE_EVENT_CBC - Force Trip Zones Cycle By Cycle event +//! - EPWM_TZ_FORCE_EVENT_OST - Force Trip Zones One Shot Event +//! - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzForceEvent & 0xFF81U)== 0U); + + // + // Force a Trip Zone event + // + EALLOW; + HWREGH(base + EPWM_O_TZFRC) |= tzForceEvent; + EDIS; +} + +// +// Event Trigger related APIs +// +//***************************************************************************** +// +//! Enable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! disable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt source. +//! +//! \param base is the base address of the EPWM module. +//! \param interruptSource is the ePWM interrupt source. +//! +//! This function sets the ePWM interrupt source. +//! Valid values for interruptSource are: +//! - EPWM_INT_TBCTR_DISABLED - Time-base counter is disabled +//! - EPWM_INT_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_INT_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is incrementing +//! - EPWM_INT_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource) +{ + uint16_t intSource; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(((interruptSource > 0U) && (interruptSource < 9U)) || + (interruptSource == 10U) || (interruptSource == 12U) || + (interruptSource == 14U)); + + if((interruptSource == EPWM_INT_TBCTR_U_CMPC) || + (interruptSource == EPWM_INT_TBCTR_U_CMPD) || + (interruptSource == EPWM_INT_TBCTR_D_CMPC) || + (interruptSource == EPWM_INT_TBCTR_D_CMPD)) + { + // + // Shift the interrupt source by 1 + // + intSource = interruptSource >> 1U; + + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTSELCMP; + } + else if((interruptSource == EPWM_INT_TBCTR_U_CMPA) || + (interruptSource == EPWM_INT_TBCTR_U_CMPB) || + (interruptSource == EPWM_INT_TBCTR_D_CMPA) || + (interruptSource == EPWM_INT_TBCTR_D_CMPB)) + { + intSource = interruptSource; + + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTSELCMP; + } + else + { + intSource = interruptSource; + } + + // + // Set the interrupt source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_INTSEL_M) | intSource); +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the event count for interrupt scale +//! +//! This function sets the interrupt event count that determines the number of +//! events that have to occur before an interrupt is issued. +//! Maximum value for eventCount is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Enable advanced feature of interrupt every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_INTPSSEL; + HWREGH(base + EPWM_O_ETINTPS) = + ((HWREGH(base + EPWM_O_ETINTPS) & ~EPWM_ETINTPS_INTPRD2_M) | + eventCount); +} + +//***************************************************************************** +// +//! Return the interrupt status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt status. +//! \b Note This function doesn't return the Trip Zone status. +//! +//! \return Returns true if ePWM interrupt was generated. +//! Returns false if no interrupt was generated +// +//***************************************************************************** +static inline bool +EPWM_getEventTriggerInterruptStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return INT bit of ETFLG register + // + return(((HWREGH(base + EPWM_O_ETFLG) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear interrupt flag. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the ePWM interrupt flag. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearEventTriggerInterruptFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear INT bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= EPWM_ETCLR_INT; +} + +//***************************************************************************** +// +//! Enable Pre-interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt counter to be pre-interrupt loaded +//! with a count value. +//! +//! \note This is valid only for advanced/expanded interrupt mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Disable interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt counter from being loaded with +//! pre-interrupt count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= ~EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Force a software pre interrupt event counter load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces the ePWM interrupt counter to be loaded with the +//! contents set by EPWM_setPreInterruptEventCount(). +//! +//! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is +//! is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITFRC; +} + +//***************************************************************************** +// +//! Set interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM interrupt count. eventCount is the value of the +//! pre-interrupt value that is to be loaded. The maximum value of eventCount +//! is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the Pre-interrupt event count + // + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_INTINIT_M) | + (uint16_t)(eventCount & 0xFU)); +} + +//***************************************************************************** +// +//! Get the interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt event count. +//! +//! \return The interrupt event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getInterruptEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the interrupt event count + // + return(((HWREGH(base + EPWM_O_ETINTPS) & EPWM_ETINTPS_INTCNT2_M) >> + EPWM_ETINTPS_INTCNT2_S)); +} + +//***************************************************************************** +// +//! Force ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces an ePWM interrupt. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceEventTriggerInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set INT bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= EPWM_ETFRC_INT; +} + +// +// ADC SOC configuration related APIs +// +//***************************************************************************** +// +//! Enable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM module to trigger an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Disable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM module from triggering an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC source. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param socSource is the SOC source. +//! +//! This function sets the ePWM ADC SOC source. +//! Valid values for socSource are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - socSource +//! - EPWM_SOC_DCxEVT1 - Event is based on DCxEVT1 +//! - EPWM_SOC_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_SOC_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_SOC_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is incrementing +//! - EPWM_SOC_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerSource(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + EPWM_ADCStartOfConversionSource socSource) +{ + uint16_t source; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + source = (uint16_t)socSource >> 1U; + } + else + { + source = (uint16_t)socSource; + } + + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the SOC source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCASEL_M) | + (source << EPWM_ETSEL_SOCASEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCASELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCASELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } + else + { + // + // Enable the comparator selection + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCBSEL_M) | + (source << EPWM_ETSEL_SOCBSEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBSELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBSELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param preScaleCount is the event count number. +//! +//! This function sets the SOC event count that determines the number of +//! events that have to occur before an SOC is issued. +//! Valid values for the parameters are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - preScaleCount +//! - [1 - 15] - Generate SOC pulse every preScaleCount +//! up to 15 events. +//! +//! \note A preScaleCount value of 0 disables the prescale. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventPrescale(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t preScaleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(preScaleCount < 16U); + + // + // Enable advanced feature of SOC every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_SOCPSSEL; + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the count for SOC A + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCAPRD2_M) | + preScaleCount); + } + else + { + // + // Set the count for SOC B + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCBPRD2_M) | + (preScaleCount << EPWM_ETSOCPS_SOCBPRD2_S)); + } +} + +//***************************************************************************** +// +//! Return the SOC event status. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC status. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return Returns true if the selected adcSOCType SOC was generated. +//! Returns false if the selected adcSOCType SOC was not generated. +// +//***************************************************************************** +static inline bool +EPWM_getADCTriggerFlagStatus(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC A/ B status + // + return((((HWREGH(base + EPWM_O_ETFLG) >> + ((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear SOC flag. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function clears the ePWM SOC flag. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearADCTriggerFlag(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear SOC A/B bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +//***************************************************************************** +// +//! Enable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM SOC event counter which is set by the +//! EPWM_setADCTriggerEventCountInitValue() function to be loaded before +//! an SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 14U); +} + +//***************************************************************************** +// +//! Disable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM SOC event counter from being loaded before +//! an SOC event (only an SOC event causes an increment of the counter value). +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= + ~(1U << ((uint16_t)adcSOCType + 14U)); +} + +//***************************************************************************** +// +//! Force a software pre SOC event counter load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type +//! +//! This function forces the ePWM SOC counter to be loaded with the +//! contents set by EPWM_setPreADCStartOfConversionEventCount(). +//! +//! \note make sure the EPWM_enableADCTriggerEventCountInit() +//! function is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 11U); +} + +//***************************************************************************** +// +//! Set ADC Trigger count values. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM ADC Trigger count values. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! The eventCount has a maximum value of 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventCountInitValue(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the ADC Trigger event count + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCAINIT_M) | + (uint16_t)(eventCount << EPWM_ETCNTINIT_SOCAINIT_S)); + } + else + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCBINIT_M) | + (eventCount << EPWM_ETCNTINIT_SOCBINIT_S)); + } +} + +//***************************************************************************** +// +//! Get the SOC event count. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC event count. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return The SOC event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getADCTriggerEventCount(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + uint16_t eventCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC event count + // + if(adcSOCType == EPWM_SOC_A) + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCACNT2_S) & 0xFU; + } + else + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCBCNT2_S) & 0xFU; + } + return(eventCount); +} + +//***************************************************************************** +// +//! Force SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function forces an ePWM SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SOC A/B bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +// +// Digital Compare module related APIs +// +//***************************************************************************** +// +//! Set the DC trip input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripSource is the tripSource. +//! \param dcType is the Digital Compare type. +//! +//! This function sets the trip input to the Digital Compare (DC). For a given +//! dcType the function sets the tripSource to be the input to the DC. +//! Valid values for the parameter are: +//! - tripSource +//! - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13 +//! - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input +//! is enabled by the following function +//! EPWM_enableDigitalCompareTripCombinationInput() +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_selectDigitalCompareTripInput(uint32_t base, + EPWM_DigitalCompareTripInput tripSource, + EPWM_DigitalCompareType dcType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + EPWM_O_DCTRIPSEL) = + ((HWREGH(base + EPWM_O_DCTRIPSEL) & ~(0xFU << ((uint16_t)dcType << 2U))) | + ((uint16_t)tripSource << ((uint16_t)dcType << 2U))); + EDIS; +} + +// +// DCFILT +// +//***************************************************************************** +// +//! Enable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Disable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Window inverse mode. This will +//! invert the blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Window inverse mode. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare filter blanking pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param blankingPulse is Pulse that starts blanking window. +//! +//! This function sets the input pulse that starts the Digital Compare blanking +//! window. +//! Valid values for blankingPulse are: +//! - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO - Time base counter equals zero +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero +//! or period. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareBlankingEvent(uint32_t base, + EPWM_DigitalCompareBlankingPulse blankingPulse) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC blanking event + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_PULSESEL_M) | + ((uint16_t)((uint32_t)blankingPulse << EPWM_DCFCTL_PULSESEL_S))); + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter input. +//! +//! \param base is the base address of the EPWM module. +//! \param filterInput is Digital Compare signal source. +//! +//! This function sets the signal input source that will be filtered by the +//! Digital Compare module. +//! Valid values for filterInput are: +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT1 - DC filter signal source is DCAEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT2 - DC filter signal source is DCAEVT2 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT1 - DC filter signal source is DCBEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT2 - DC filter signal source is DCBEVT2 +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareFilterInput(uint32_t base, + EPWM_DigitalCompareFilterInput filterInput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the signal source that will be filtered + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_SRCSEL_M) | + ((uint16_t)filterInput)); + EDIS; +} + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Enable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Edge filter to generate event +//! after configured number of edges. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Edge filter. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Mode. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeMode is Digital Compare Edge filter mode. +//! +//! This function sets the Digital Compare Event filter mode. Valid values +//! for edgeMode are: +//! - EPWM_DC_EDGEFILT_MODE_RISING - DC edge filter mode is rising edge +//! - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge +//! - EPWM_DC_EDGEFILT_MODE_BOTH - DC edge filter mode is both edges +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, + EPWM_DigitalCompareEdgeFilterMode edgeMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter mode + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + (HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_EDGEMODE_M) | + ((uint16_t)edgeMode << EPWM_DCFCTL_EDGEMODE_S); + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeCount is Digital Compare event filter count +//! +//! This function sets the Digital Compare Event filter Edge Count to generate +//! events. Valid values for edgeCount can be: +//! - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event +//! - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter edge count + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = (HWREGH(base + EPWM_O_DCFCTL) & + ~EPWM_DCFCTL_EDGECOUNT_M) | + (edgeCount << EPWM_DCFCTL_EDGECOUNT_S); + EDIS; +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the configured Digital Compare Edge filter edge +//! count required to generate events. It can return values from 0-7. +//! +//! \return Returns the configured DigitalCompare Edge filter edge count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return configured DC edge filter edge count + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGECOUNT_M) >> + EPWM_DCFCTL_EDGECOUNT_S); +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge filter captured edge count status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the count of edges captured by Digital Compare Edge +//! filter. It can return values from 0-7. +//! +//! \return Returns the count of captured edges +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return captured edge count by DC Edge filter + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGESTATUS_M) >> + EPWM_DCFCTL_EDGESTATUS_S); +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window offset +//! +//! \param base is the base address of the EPWM module. +//! \param windowOffsetCount is blanking window offset length. +//! +//! This function sets the offset between window start pulse and blanking +//! window in TBCLK count. +//! The function take a 16bit count value for the offset value. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window offset in TBCLK counts + // + HWREGH(base + EPWM_O_DCFOFFSET) = windowOffsetCount; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window length +//! +//! \param base is the base address of the EPWM module. +//! \param windowLengthCount is blanking window length. +//! +//! This function sets up the Digital Compare filter blanking window length in +//! TBCLK count.The function takes a 16bit count value for the window length. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window length in TBCLK counts + // + HWREGH(base + EPWM_O_DCFWINDOW) = windowLengthCount; +} + +//***************************************************************************** +// +//! Return DC filter blanking window offset count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window offset count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Offset count + // + return(HWREGH(base + EPWM_O_DCFOFFSETCNT)); +} + +//***************************************************************************** +// +//! Return DC filter blanking window length count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window length count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Length count + // + return(HWREGH(base + EPWM_O_DCFWINDOWCNT)); +} + +//***************************************************************************** +// +//! Set up the Digital Compare Event source. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param dcEventSource is the - Digital Compare Event source. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - dcEventSource +//! - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL - signal source is filtered +//! \note The signal source for this option is DCxEVTy, where the +//! value of x is dependent on dcModule and the value of y is +//! dependent on dcEvent. Possible signal sources are DCAEVT1, +//! DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both +//! dcModule and dcEvent. +//! - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL - signal source is unfiltered +//! The signal source for this option is DCxEVTy. +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSource(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareEventSource dcEventSource) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event 1 source source + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SRCSEL) | + (uint16_t)dcEventSource); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2SRCSEL) | + ((uint16_t)dcEventSource << 8U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare input sync mode. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param syncMode is the Digital Compare Event sync mode. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - syncMode +//! - EPWM_DC_EVENT_INPUT_SYNCED - DC input signal is synced with +//! TBCLK +//! - EPWM_DC_EVENT_INPUT_NOT SYNCED - DC input signal is not synced with +//! TBCLK +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSyncMode(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareSyncMode syncMode) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event sync mode + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1FRCSYNCSEL) | + ((uint16_t)syncMode << 1U)); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2FRCSYNCSEL) | + ((uint16_t)syncMode << 9U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate sync out pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate sync out +//! pulse +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating synch +//! out pulse. +//! The following are valid values for the \e dcModule parameters. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +// +// DC capture mode +// +//***************************************************************************** +// +//! Enables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disable the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Set the Time Base Counter Capture mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableShadowMode is the shadow read mode flag. +//! +//! This function sets the mode the Time Base Counter value is read from. If +//! enableShadowMode is true, CPU reads of the DCCAP register will return the +//! shadow register contents.If enableShadowMode is false, CPU reads of the +//! DCCAP register will return the active register contents. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(enableShadowMode) + { + // + // Enable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_SHDWMODE; + } + else + { + // + // Disable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_SHDWMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Capture event status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC capture event status. +//! +//! \return Returns true if a DC capture event has occurs. +//! Returns false if no DC Capture event has occurred. +//! +//! \return None. +// +//***************************************************************************** +static inline bool +EPWM_getDigitalCompareCaptureStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC compare status + // + return((HWREGH(base + EPWM_O_DCCAPCTL) & EPWM_DCCAPCTL_CAPSTS) == + EPWM_DCCAPCTL_CAPSTS); +} + +//***************************************************************************** +// +//! Clears DC capture latched status flag +//! +//! \param base is the base address of the EPWM module. +//! This function is used to clear the CAPSTS (set) condition. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_clearDigitalCompareCaptureStatusFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear digital compare capture status flag + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPCLR; + EDIS; +} + +//***************************************************************************** +// +//! Configures DC capture operating mode +//! +//! \param base is the base address of the EPWM module. +//! \param disableClearMode is the clear mode bit. +//! +//! This function is used to configure the DC capture operating mode. If +//! \e disableClearMode is false, the TBCNT value is captured in active register +//! on occurance of DCEVTFILT event. The trip events are ignored until next +//! PRD or ZRO event re-triggers the capture mechanism. +//! If \e disableClearMode is true, the TBCNT value is captured, CAPSTS flag is +//! set and further trips are ignored until CAPSTS bit is cleared. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_configureDigitalCompareCounterCaptureMode(uint32_t base, + bool disableClearMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(disableClearMode) + { + // + // Disable DC counter auto-clear on PULSESEL event + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPMODE; + } + else + { + // + // Enable DC counter clear on PULSESEL events + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Time Base Counter capture value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC Time Base Counter capture value. The value +//! read is determined by the mode as set in the +//! EPWM_setTimeBaseCounterReadMode() function. +//! +//! \return Returns the DC Time Base Counter Capture count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareCaptureCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC Time Base Counter Capture count value + // + return(HWREGH(base + EPWM_O_DCCAP)); +} + +//***************************************************************************** +// +//! Enable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function enables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | tripInput); + + // + // Enable the combination input + // + HWREGH(base + EPWM_O_DCTRIPSEL) = + (HWREGH(base + EPWM_O_DCTRIPSEL) | (0xFU << ((uint16_t)dcType << 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Disable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function disables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~tripInput); + EDIS; +} + +// +// Valley switching +// +//***************************************************************************** +// +//! Enable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Start valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function starts Valley Capture sequence. +//! +//! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger +//! variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPSTART bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPSTART; + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger. +//! +//! \param base is the base address of the EPWM module. +//! \param trigger is the Valley counter trigger. +//! +//! This function sets the trigger value that initiates Valley Capture sequence +//! +//! \b Set the number of Trigger source events for starting and stopping the +//! valley capture using EPWM_setValleyTriggerEdgeCounts(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TRIGSEL bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_TRIGSEL_M) | + ((uint16_t)trigger << 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger source count. +//! +//! \param base is the base address of the EPWM module. +//! \param startCount +//! \param stopCount +//! +//! This function sets the number of trigger events required to start and stop +//! the valley capture count. +//! Maximum values for both startCount and stopCount is 15 corresponding to the +//! 15th edge of the trigger event. +//! +//! \b Note: +//! A startCount value of 0 prevents starting the valley counter. +//! A stopCount value of 0 prevents the valley counter from stopping. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, + uint16_t stopCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((startCount < 16U) && (stopCount < 16U)); + + // + // Write to STARTEDGE and STOPEDGE bits + // + EALLOW; + HWREGH(base + EPWM_O_VCNTCFG) = + ((HWREGH(base + EPWM_O_VCNTCFG) & + ~(EPWM_VCNTCFG_STARTEDGE_M | EPWM_VCNTCFG_STOPEDGE_M)) | + (startCount | (stopCount << 8U))); + EDIS; +} + +//***************************************************************************** +// +//! Enable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set Valley delay values. +//! +//! \param base is the base address of the EPWM module. +//! \param delayOffsetValue is the software defined delay offset value. +//! +//! This function sets the Valley delay value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to SWVDELVAL bits + // + HWREGH(base + EPWM_O_SWVDELVAL) = delayOffsetValue; +} + +//***************************************************************************** +// +//! Set Valley delay mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Valley delay mode. +//! +//! This function sets the Valley delay mode values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to VDELAYDIV bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_VDELAYDIV_M) | + ((uint16_t)delayMode << 7U)); + EDIS; +} + +//***************************************************************************** +// +//! Get the valley edge status bit. +//! +//! \param base is the base address of the EPWM module. +//! \param edge is the start or stop edge. +//! +//! This function returns the status of the start or stop valley status +//! depending on the value of edge. +//! If a start or stop edge has occurred, the function returns true, if not it +//! returns false. +//! +//! \return Returns true if the specified edge has occurred, +//! Returns false if the specified edge has not occurred. +// +//***************************************************************************** +static inline bool +EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(edge == EPWM_VALLEY_COUNT_START_EDGE) + { + // + // Returns STARTEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STARTEDGESTS) == + EPWM_VCNTCFG_STARTEDGESTS ) ? true : false); + } + else + { + // + // Returns STOPEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STOPEDGESTS) == + EPWM_VCNTCFG_STOPEDGESTS) ? true : false); + } +} + +//***************************************************************************** +// +//! Get the Valley Counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the valley time base count value which is captured +//! upon occurrence of the stop edge condition selected by +//! EPWM_setValleyTriggerSource() and by the stopCount variable of the +//! EPWM_setValleyTriggerEdgeCounts() function. +//! +//! \return Returns the valley base time count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read VCNTVAL register + // + return(HWREGH(base + EPWM_O_VCNTVAL)); +} + +//***************************************************************************** +// +//! Get the Valley delay value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the hardware valley delay count. +//! +//! \return Returns the valley delay count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read HWVDELVAL register + // + return(HWREGH(base + EPWM_O_HWVDELVAL)); +} + +//***************************************************************************** +// +//! Enable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Global shadow to active load mode of registers. +//! The trigger source for loading shadow to active is determined by +//! EPWM_setGlobalLoadTrigger() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Disable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Global shadow to active load mode of registers. +//! Loading shadow to active is determined individually. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled individually + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Set the Global shadow load pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param loadTrigger is the pulse that causes global shadow load. +//! +//! This function sets the pulse that causes Global shadow to active load. +//! Valid values for the loadTrigger parameter are: +//! +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO - load when counter is equal +//! to zero +//! - EPWM_GL_LOAD_PULSE_CNTR_PERIOD - load when counter is equal +//! to period +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD - load when counter is equal +//! to zero or period +//! - EPWM_GL_LOAD_PULSE_SYNC - load on sync event +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO - load on sync event or when +//! counter is equal to zero +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD - load on sync event or when +//! counter is equal to period +//! - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD - load on sync event or when +//! counter is equal to period +//! or zero +//! - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE - load on global force +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Global shadow to active load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDMODE_M) | + ((uint16_t)loadTrigger << EPWM_GLDCTL_GLDMODE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! \param prescalePulseCount is the pulse event counts. +//! +//! This function sets the number of Global Load pulse events that have to +//! occurred before a global load pulse is issued. Valid values for +//! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7 +//! representing 7 events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(prescalePulseCount < 8U); + + // + // Set the number of counts that have to occur before + // a load strobe is issued + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDPRD_M) | + (prescalePulseCount << EPWM_GLDCTL_GLDPRD_S)); + EDIS; +} + +//***************************************************************************** +// +//! Return the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the number of Global Load pulse events that have +//! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +EPWM_getGlobalLoadEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the number of events that have occurred + // + return((HWREGH(base + EPWM_O_GLDCTL) >> EPWM_GLDCTL_GLDCNT_S) & 0x7U); +} + +//***************************************************************************** +// +//! Enable continuous global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables global continuous shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Enable One shot global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables a one time global shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Set One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function sets a one time global shadow to active load pulse. The pulse +//! propagates to generate a load signal if any of the events set by +//! EPWM_setGlobalLoadTrigger() occur. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadOneShotLatch(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set a one shot Global shadow load pulse. + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_OSHTLD; + EDIS; +} + +//***************************************************************************** +// +//! Force a software One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces a software a one time global shadow to active load +//! pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceGlobalLoadOneShotEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Force a Software Global shadow load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_GFRCLD; + EDIS; +} + +//***************************************************************************** +// +//! Enable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function enables the register specified by loadRegister to be globally +//! loaded. +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) |= loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Disable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function disables the register specified by loadRegister from being +//! loaded globally. The shadow to active load happens as specified by the +//! register control +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded by individual + // register configuration setting + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) &= ~loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Set emulation mode +//! +//! \param base is the base address of the EPWM module. +//! \param emulationMode is the emulation mode. +//! +//! This function sets the emulation behaviours of the time base counter. Valid +//! values for emulationMode are: +//! - EPWM_EMULATION_STOP_AFTER_NEXT_TB - Stop after next Time Base counter +//! increment or decrement. +//! - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole +//! cycle. +//! - EPWM_EMULATION_FREE_RUN - Free run. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode); + +//***************************************************************************** +// +//! Configures ePWM signal with desired frequency & duty +//! +//! \param base is the base address of the EPWM module. +//! \param signalParams is the desired signal parameters. +//! +//! This function configures the ePWM module to generate a signal with +//! desired frequency & duty. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EPWM_H diff --git a/gpio_driverlib_cpu2/device/driverlib/eqep.c b/gpio_driverlib_cpu2/device/driverlib/eqep.c new file mode 100644 index 0000000..64caf47 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/eqep.c @@ -0,0 +1,149 @@ +//########################################################################### +// +// FILE: eqep.c +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "eqep.h" + +//***************************************************************************** +// +// EQEP_setCompareConfig +// +//***************************************************************************** +void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the compare match value + // + HWREG(base + EQEP_O_QPOSCMP) = compareValue; + + // + // Set the shadow register settings and pulse width. + // + regValue = (config & (uint16_t)(EQEP_QPOSCTL_PCSHDW | + EQEP_QPOSCTL_PCLOAD)) | (cycles - 1U); + + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(EQEP_QPOSCTL_PCSPW_M | + EQEP_QPOSCTL_PCLOAD | + EQEP_QPOSCTL_PCSHDW)) | regValue; + + // + // Set position compare sync-output mode. + // + regValue = config & (uint16_t)(EQEP_QDECCTL_SOEN | EQEP_QDECCTL_SPSEL); + + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SOEN | + EQEP_QDECCTL_SPSEL)) | regValue; +} + +//***************************************************************************** +// +// EQEP_setInputPolarity +// +//***************************************************************************** +void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Configure QEPA signal + // + if(invertQEPA) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QAP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QAP; + } + + // + // Configure QEPB signal + // + if(invertQEPB) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QBP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QBP; + } + + // + // Configure index signal + // + if(invertIndex) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QIP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QIP; + } + + // + // Configure strobe signal + // + if(invertStrobe) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QSP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QSP; + } +} diff --git a/gpio_driverlib_cpu2/device/driverlib/eqep.h b/gpio_driverlib_cpu2/device/driverlib/eqep.h new file mode 100644 index 0000000..4f1eaa2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/eqep.h @@ -0,0 +1,1691 @@ +//########################################################################### +// +// FILE: eqep.h +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EQEP_H +#define EQEP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eqep_api eQEP +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_eqep.h" +#include "inc/hw_types.h" +#include "debug.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to EQEP_setDecoderConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Operation Mode +// +#define EQEP_CONFIG_QUADRATURE 0x0000U //!< Quadrature-clock mode +#define EQEP_CONFIG_CLOCK_DIR 0x4000U //!< Direction-count mode +#define EQEP_CONFIG_UP_COUNT 0x8000U //!< Up-count mode, QDIR = 1 +#define EQEP_CONFIG_DOWN_COUNT 0xC000U //!< Down-count mode, QDIR = 0 + +// +// Resolution +// +#define EQEP_CONFIG_2X_RESOLUTION 0x0000U //!< Count rising and falling edge +#define EQEP_CONFIG_1X_RESOLUTION 0x0800U //!< Count rising edge only + +// +// Swap QEPA and QEPB +// +#define EQEP_CONFIG_NO_SWAP 0x0000U //!< Do not swap QEPA and QEPB +#define EQEP_CONFIG_SWAP 0x0400U //!< Swap QEPA and QEPB + +// +// Index pulse gating option +// +#define EQEP_CONFIG_IGATE_DISABLE 0x0000U //!< Disable gating of Index pulse +#define EQEP_CONFIG_IGATE_ENABLE 0x0200U //!< Gate the index pin with strobe + +//***************************************************************************** + +// +// Values that can be passed to EQEP_setCompareConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Sync pulse pin +// +#define EQEP_COMPARE_NO_SYNC_OUT 0x0000U //!< Disable sync output +#define EQEP_COMPARE_IDX_SYNC_OUT 0x2000U //!< Sync output on index pin +#define EQEP_COMPARE_STROBE_SYNC_OUT 0x3000U //!< Sync output on strobe pin + +// +// Shadow register use +// +#define EQEP_COMPARE_NO_SHADOW 0x0000U //!< Disable shadow of QPOSCMP +#define EQEP_COMPARE_LOAD_ON_ZERO 0x8000U //!< Load on QPOSCNT = 0 +#define EQEP_COMPARE_LOAD_ON_MATCH 0xC000U //!< Load on QPOSCNT = QPOSCMP + +//***************************************************************************** +// +// Values that can be passed to EQEP_enableInterrupt(), +// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the +// intFlags parameter and returned by EQEP_clearInterruptStatus(). +// +//***************************************************************************** +#define EQEP_INT_GLOBAL 0x0001U //!< Global interrupt flag +#define EQEP_INT_POS_CNT_ERROR 0x0002U //!< Position counter error +#define EQEP_INT_PHASE_ERROR 0x0004U //!< Quadrature phase error +#define EQEP_INT_DIR_CHANGE 0x0008U //!< Quadrature direction change +#define EQEP_INT_WATCHDOG 0x0010U //!< Watchdog time-out +#define EQEP_INT_UNDERFLOW 0x0020U //!< Position counter underflow +#define EQEP_INT_OVERFLOW 0x0040U //!< Position counter overflow +#define EQEP_INT_POS_COMP_READY 0x0080U //!< Position-compare ready +#define EQEP_INT_POS_COMP_MATCH 0x0100U //!< Position-compare match +#define EQEP_INT_STROBE_EVNT_LATCH 0x0200U //!< Strobe event latch +#define EQEP_INT_INDEX_EVNT_LATCH 0x0400U //!< Index event latch +#define EQEP_INT_UNIT_TIME_OUT 0x0800U //!< Unit time-out + +//***************************************************************************** +// +// Values that can be returned by EQEP_getStatus(). +// +//***************************************************************************** +//! Unit position event detected +#define EQEP_STS_UNIT_POS_EVNT 0x0080U +//! Direction was clockwise on first index event +#define EQEP_STS_DIR_ON_1ST_IDX 0x0040U +//! Direction is CW (forward) +#define EQEP_STS_DIR_FLAG 0x0020U +//! Direction was CW on index +#define EQEP_STS_DIR_LATCH 0x0010U +//! Capture timer overflow +#define EQEP_STS_CAP_OVRFLW_ERROR 0x0008U +//! Direction changed between position capture events +#define EQEP_STS_CAP_DIR_ERROR 0x0004U +//! First index pulse occurred +#define EQEP_STS_1ST_IDX_FLAG 0x0002U +//! Position counter error +#define EQEP_STS_POS_CNT_ERROR 0x0001U + +//***************************************************************************** +// +// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter. +// +//***************************************************************************** + +// +// Position counter latch event +// +#define EQEP_LATCH_CNT_READ_BY_CPU 0x0000U //!< On position counter read +#define EQEP_LATCH_UNIT_TIME_OUT 0x0004U //!< On unit time-out event + +// +// Strobe position counter latch event +// +//! On rising edge of strobe +#define EQEP_LATCH_RISING_STROBE 0x0000U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_LATCH_EDGE_DIR_STROBE 0x0040U + +// +// Index position counter latch event +// +#define EQEP_LATCH_RISING_INDEX 0x0010U //!< On rising edge of index +#define EQEP_LATCH_FALLING_INDEX 0x0020U //!< On falling edge of index + +#define EQEP_LATCH_SW_INDEX_MARKER 0x0030U //!< On software index marker + +//***************************************************************************** +// +// Values that can be passed to EQEP_setPositionInitMode() as the initMode +// parameter. +// +//***************************************************************************** +#define EQEP_INIT_DO_NOTHING 0x0000U //!< Action is disabled + +// +// Strobe events +// +//! On rising edge of strobe +#define EQEP_INIT_RISING_STROBE 0x0800U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_INIT_EDGE_DIR_STROBE 0x0C00U + +// +// Index events +// +#define EQEP_INIT_RISING_INDEX 0x0200U //!< On rising edge of index +#define EQEP_INIT_FALLING_INDEX 0x0300U //!< On falling edge of index +#endif + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Reset position on index pulse + EQEP_POSITION_RESET_IDX = 0x0000, + //! Reset position on maximum position + EQEP_POSITION_RESET_MAX_POS = 0x1000, + //! Reset position on the first index pulse + EQEP_POSITION_RESET_1ST_IDX = 0x2000, + //! Reset position on a unit time event + EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000 +} EQEP_PositionResetMode; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale +//! parameter. CAPCLK is the capture timer clock frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_CAPTURE_CLK_DIV_1 = 0x00, //!< CAPCLK = SYSCLKOUT/1 + EQEP_CAPTURE_CLK_DIV_2 = 0x10, //!< CAPCLK = SYSCLKOUT/2 + EQEP_CAPTURE_CLK_DIV_4 = 0x20, //!< CAPCLK = SYSCLKOUT/4 + EQEP_CAPTURE_CLK_DIV_8 = 0x30, //!< CAPCLK = SYSCLKOUT/8 + EQEP_CAPTURE_CLK_DIV_16 = 0x40, //!< CAPCLK = SYSCLKOUT/16 + EQEP_CAPTURE_CLK_DIV_32 = 0x50, //!< CAPCLK = SYSCLKOUT/32 + EQEP_CAPTURE_CLK_DIV_64 = 0x60, //!< CAPCLK = SYSCLKOUT/64 + EQEP_CAPTURE_CLK_DIV_128 = 0x70 //!< CAPCLK = SYSCLKOUT/128 +} EQEP_CAPCLKPrescale; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale +//! parameter. UPEVNT is the unit position event frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_UNIT_POS_EVNT_DIV_1, //!< UPEVNT = QCLK/1 + EQEP_UNIT_POS_EVNT_DIV_2, //!< UPEVNT = QCLK/2 + EQEP_UNIT_POS_EVNT_DIV_4, //!< UPEVNT = QCLK/4 + EQEP_UNIT_POS_EVNT_DIV_8, //!< UPEVNT = QCLK/8 + EQEP_UNIT_POS_EVNT_DIV_16, //!< UPEVNT = QCLK/16 + EQEP_UNIT_POS_EVNT_DIV_32, //!< UPEVNT = QCLK/32 + EQEP_UNIT_POS_EVNT_DIV_64, //!< UPEVNT = QCLK/64 + EQEP_UNIT_POS_EVNT_DIV_128, //!< UPEVNT = QCLK/128 + EQEP_UNIT_POS_EVNT_DIV_256, //!< UPEVNT = QCLK/256 + EQEP_UNIT_POS_EVNT_DIV_512, //!< UPEVNT = QCLK/512 + EQEP_UNIT_POS_EVNT_DIV_1024, //!< UPEVNT = QCLK/1024 + EQEP_UNIT_POS_EVNT_DIV_2048 //!< UPEVNT = QCLK/2048 +} EQEP_UPEVNTPrescale; + + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EQEP_EMULATIONMODE_STOPIMMEDIATELY, //!< Counters stop immediately + EQEP_EMULATIONMODE_STOPATROLLOVER, //!< Counters stop at period rollover + EQEP_EMULATIONMODE_RUNFREE //!< Counter unaffected by suspend +}EQEP_EmulationMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an eQEP base address. +//! +//! \param base specifies the eQEP module base address. +//! +//! This function determines if a eQEP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +EQEP_isBaseValid(uint32_t base) +{ + return( + (base == EQEP1_BASE) || + (base == EQEP2_BASE) || + (base == EQEP3_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the enhanced quadrature encoder pulse +//! (eQEP) module. The module must be configured before it is enabled. +//! +//! \sa EQEP_setConfig() +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_QPEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module. +//! +//! \param base is the base address of the enhanced quadrature encoder pulse +//! (eQEP) module +//! +//! This function disables operation of the eQEP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_QPEN); +} + +//***************************************************************************** +// +//! Configures eQEP module's quadrature decoder unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module decoder unit. +//! +//! This function configures the operation of the eQEP module's quadrature +//! decoder unit. The \e config parameter provides the configuration +//! of the decoder and is the logical OR of several values: +//! +//! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify +//! if both rising and falling edges should be counted or just rising edges. +//! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR, +//! \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if +//! quadrature signals are being provided on QEPA and QEPB, if a direction +//! signal and a clock are being provided, or if the direction should be +//! hard-wired for a single direction with QEPA used for input. +//! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the +//! signals provided on QEPA and QEPB should be swapped before being +//! processed. +//! - \b EQEP_CONFIG_IGATE_DISABLE or \b EQEP_CONFIG_IGATE_ENABLE to specify +//! if the gating of the index pulse should be enabled or disabled +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setDecoderConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the new decoder configuration to the hardware. + // + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SWAP | + EQEP_QDECCTL_XCR | + EQEP_QDECCTL_QSRC_M | + EQEP_QDECCTL_IGATE)) | config; +} + +//***************************************************************************** +// +//! Configures eQEP module position counter unit. +//! +//! \param base is the base address of the eQEP module. +//! \param mode is the configuration for the eQEP module position counter. +//! \param maxPosition specifies the maximum position value. +//! +//! This function configures the operation of the eQEP module position +//! counter. The \e mode parameter determines the event on which the position +//! counter gets reset. It should be passed one of the following values: +//! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS, +//! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT. +//! +//! \e maxPosition is the maximum value of the position counter and is +//! the value used to reset the position capture when moving in the reverse +//! (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode, + uint32_t maxPosition) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the position counter reset configuration to the hardware. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~EQEP_QEPCTL_PCRM_M) | (uint16_t)mode; + + // + // Set the maximum position. + // + HWREG(base + EQEP_O_QPOSMAX) = maxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter is not yet aligned with the index pulse). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPosition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSCNT)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the new position for the encoder. +//! +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the position counter. + // + HWREG(base + EQEP_O_QPOSCNT) = position; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +static inline int16_t +EQEP_getDirection(uint32_t base) +{ + int16_t direction; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the direction of rotation. + // + if((HWREGH(base + EQEP_O_QEPSTS) & EQEP_QEPSTS_QDF) != 0U) + { + direction = 1; + } + else + { + direction = -1; + } + + return(direction); +} + +//***************************************************************************** +// +//! Enables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the interrupt status for the eQEP module +//! module. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +// +//***************************************************************************** +static inline uint16_t +EQEP_getInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + return(HWREGH(base + EQEP_O_QFLG)); +} + +//***************************************************************************** +// +//! Clears eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In +//! order to get any further eQEP interrupts, this flag must be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QCLR) = intFlags; +} + +//***************************************************************************** +// +//! Forces individual eQEP module interrupts. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be forced. +//! +//! This function forces eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR +//! - \b EQEP_INT_PHASE_ERROR +//! - \b EQEP_INT_DIR_CHANGE +//! - \b EQEP_INT_WATCHDOG +//! - \b EQEP_INT_UNDERFLOW +//! - \b EQEP_INT_OVERFLOW +//! - \b EQEP_INT_POS_COMP_READY +//! - \b EQEP_INT_POS_COMP_MATCH +//! - \b EQEP_INT_STROBE_EVNT_LATCH +//! - \b EQEP_INT_INDEX_EVNT_LATCH +//! - \b EQEP_INT_UNIT_TIME_OUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_forceInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Force the specified interrupts. + // + HWREGH(base + EQEP_O_QFRC) |= intFlags; +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the error indicator for the eQEP module. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +static inline bool +EQEP_getError(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the error indicator. + // + return((HWREGH(base + EQEP_O_QFLG) & EQEP_QFLG_PHE) != 0U); +} + +//***************************************************************************** +// +//! Returns content of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the contents of the status register. The value it +//! returns is an OR of the following values: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward +//! movement) occurred on the first index event +//! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation +//! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last +//! index event marker +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred +//! +//! \return Returns the value of the QEP status register. +// +//***************************************************************************** +static inline uint16_t +EQEP_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the status register. + // + return(HWREGH(base + EQEP_O_QEPSTS) & 0x00FFU); +} + +//***************************************************************************** +// +//! Clears selected fields of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! \param statusFlags is the bit mask of the status flags to be cleared. +//! +//! This function clears the status register fields indicated by +//! \e statusFlags. The \e statusFlags parameter is the logical OR of any of +//! the following: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! +//! \note Only the above status fields can be cleared. All others are +//! read-only, non-sticky fields. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearStatus(uint32_t base, uint16_t statusFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QEPSTS) = statusFlags; +} + +//***************************************************************************** +// +//! Configures eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! \param capPrescale is the prescaler setting of the eQEP capture timer clk. +//! \param evntPrescale is the prescaler setting of the unit position event +//! frequency. +//! +//! This function configures the operation of the eQEP module edge-capture +//! unit. The \e capPrescale parameter provides the configuration of the eQEP +//! capture timer clock rate. It determines by which power of 2 between 1 and +//! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in +//! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For +//! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock +//! frequency that is SYSCLKOUT/32. +//! +//! The \e evntPrescale parameter determines how frequently a unit position +//! event occurs. The macro that can be passed this parameter is in the format +//! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock +//! periods between unit position events. For example, +//! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event +//! frequency of QCLK/16. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale, + EQEP_UPEVNTPrescale evntPrescale) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write new prescaler configurations to the appropriate registers. + // + HWREGH(base + EQEP_O_QCAPCTL) = + (HWREGH(base + EQEP_O_QCAPCTL) & + ~(EQEP_QCAPCTL_UPPS_M | EQEP_QCAPCTL_CCPS_M)) | + ((uint16_t)evntPrescale | (uint16_t)capPrescale); +} + +//***************************************************************************** +// +//! Enables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) |= EQEP_QCAPCTL_CEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) &= ~(EQEP_QCAPCTL_CEN); +} + +//***************************************************************************** +// +//! Gets the encoder capture period. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the period count value between the last successive +//! eQEP position events. +//! +//! \return The period count value between the last successive position events. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriod(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture period. + // + return(HWREGH(base + EQEP_O_QCPRD)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the time base for the edge capture unit. +//! +//! \return The capture timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture timer value. + // + return(HWREGH(base + EQEP_O_QCTMR)); +} + +//***************************************************************************** +// +//! Enables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's position-compare unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) |= EQEP_QPOSCTL_PCE; +} + +//***************************************************************************** +// +//! Disables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's position-compare +//! unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) &= ~(EQEP_QPOSCTL_PCE); +} + +//***************************************************************************** +// +//! Configures the position-compare unit's sync output pulse width. +//! +//! \param base is the base address of the eQEP module. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the width of the sync output pulse. The width of +//! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle. The +//! maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the pulse width. + // + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(uint16_t)EQEP_QPOSCTL_PCSPW_M) | + (cycles - 1U); +} + +//***************************************************************************** +// +//! Loads the eQEP module unit timer period as number of SYSCLK cycles. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function sets the unit time-out interrupt when it matches the value +//! specified by \e period +//! The unit timer is clocked by SYSCLKOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_loadUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; +} + +//***************************************************************************** +// +//! Enables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function enables operation of the eQEP module's peripheral unit timer. +//! The unit timer is clocked by SYSCLKOUT and will set the unit time-out +//! interrupt when it matches the value specified by \e period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; + + // + // Enable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_UTE; +} + +//***************************************************************************** +// +//! Disables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral +//! unit timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableUnitTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_UTE); +} + +//***************************************************************************** +// +//! Enables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is watchdog period value at which a time-out will occur if +//! no quadrature-clock event is detected. +//! +//! This function enables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \note When selecting \e period, note that the watchdog timer is clocked +//! from SYSCLKOUT/64. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableWatchdog(uint32_t base, uint16_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the timeout count for the eQEP peripheral watchdog timer. + // + HWREGH(base + EQEP_O_QWDPRD) = period; + + // + // Enable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_WDE; +} + +//***************************************************************************** +// +//! Disables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableWatchdog(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_WDE); +} + +//***************************************************************************** +// +//! Sets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! \param value is the value to be written to the watchdog timer. +//! +//! This function sets the eQEP module's watchdog timer value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the value to the watchdog timer register. + // + HWREGH(base + EQEP_O_QWDTMR) = value; +} + +//***************************************************************************** +// +//! Gets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! \return Returns the current watchdog timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getWatchdogTimerValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Read the value from the watchdog timer register. + // + return(HWREGH(base + EQEP_O_QWDTMR)); +} + +//***************************************************************************** +// +//! Configures the mode in which the position counter is initialized. +//! +//! \param base is the base address of the eQEP module. +//! \param initMode is the configuration for initializing the position count. +//! See below for a description of this parameter. +//! +//! This function configures the events on which the position count can be +//! initialized. The \e initMode parameter provides the mode as either +//! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following +//! strobe events, index events, or a logical OR of both a strobe event and an +//! index event. +//! +//! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify +//! which strobe event will initialize the position counter. +//! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify +//! which index event will initialize the position counter. +//! +//! Use EQEP_setSWPositionInit() to cause a software initialization and +//! EQEP_setInitialPosition() to set the value that gets loaded into the +//! position counter upon initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionInitMode(uint32_t base, uint16_t initMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the init mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_IEI_M | EQEP_QEPCTL_SEI_M)) | + initMode; +} + +//***************************************************************************** +// +//! Sets the software initialization of the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param initialize is a flag to specify if software initialization of the +//! position counter is enabled. +//! +//! This function does a software initialization of the position counter when +//! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit +//! is cleared and no action is taken. +//! +//! The init value to be loaded into the position counter can be set with +//! EQEP_setInitialPosition(). Additional initialization causes can be +//! configured with EQEP_setPositionInitMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setSWPositionInit(uint32_t base, bool initialize) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set or clear the software initialization bit. + // + if(initialize) + { + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_SWI; + } + else + { + HWREGH(base + EQEP_O_QEPCTL) &= ~EQEP_QEPCTL_SWI; + } +} + +//***************************************************************************** +// +//! Sets the init value for the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the value to be written to the position counter upon. +//! initialization. +//! +//! This function sets the init value for position of the encoder. See +//! EQEP_setPositionInitMode() to set the initialization cause or +//! EQEP_setSWPositionInit() to cause a software initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setInitialPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write position to position counter init register + // + HWREG(base + EQEP_O_QPOSINIT) = position; +} + +//***************************************************************************** +// +//! Configures the quadrature modes in which the position count can be latched. +//! +//! \param base is the base address of the eQEP module. +//! \param latchMode is the configuration for latching of the position count +//! and several other registers. See below for a description of this +//! parameter. +//! +//! This function configures the events on which the position count and several +//! other registers can be latched. The \e latchMode parameter provides the +//! mode as the logical OR of several values. +//! +//! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify +//! the event that latches the position counter. This latch register can be +//! read using EQEP_getPositionLatch(). The capture timer and capture +//! period are also latched based on this setting, and can be read using +//! EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch(). +//! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE +//! specify which strobe event will latch the position counter into the +//! strobe position latch register. This register can be read with +//! EQEP_getStrobePositionLatch(). +//! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or +//! \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the +//! position counter into the index position latch register. This register +//! can be read with EQEP_getIndexPositionLatch(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setLatchMode(uint32_t base, uint32_t latchMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the latch mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_QCLM | EQEP_QEPCTL_IEL_M | + EQEP_QEPCTL_SEL)) | latchMode; +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on an index event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the index position latch register. The +//! position counter is latched into this register on either a rising index +//! edge, a falling index edge, or a software index marker. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on an index event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getIndexPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSILAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a strobe event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the strobe position latch register. The +//! position counter can be configured to be latched into this register on +//! rising strobe edges only or on rising strobe edges while moving clockwise +//! and falling strobe edges while moving counter-clockwise. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on a strobe event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getStrobePositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a unit time-out event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the position latch register. The +//! position counter is latched into this register either on a unit time-out +//! event. +//! +//! \return The position count latch register value. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture timer latch register. The +//! capture timer value is latched into this register either on a unit time-out +//! event or upon the CPU reading the eQEP position counter. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The edge-capture timer latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimerLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCTMRLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture period latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture period latch register. The +//! capture period value is latched into this register either on a unit +//! time-out event or upon the CPU reading the eQEP position counter. This is +//! configured using EQEP_setLatchMode(). +//! +//! \return The edge-capture period latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriodLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCPRDLAT)); +} + +//***************************************************************************** +// +//! Set the emulation mode of the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! \param emuMode is the mode operation upon an emulation suspend. +//! +//! This function sets the eQEP module's emulation mode. This mode determines +//! how the timers are affected by an emulation suspend. Valid values for the +//! \e emuMode parameter are the following: +//! +//! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog +//! counter, unit timer, and capture timer all stop immediately. +//! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog +//! counter, unit timer all count until period rollover. The capture timer +//! counts until the next unit period event. +//! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter, +//! unit timer, and capture timer are all unaffected by an emulation suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the emulation mode to the FREE_SOFT bits. + // + HWREGH(base + EQEP_O_QEPCTL) = + (HWREGH(base + EQEP_O_QEPCTL) & ~EQEP_QEPCTL_FREE_SOFT_M) | + ((uint16_t)emuMode << EQEP_QEPCTL_FREE_SOFT_S); +} + +//***************************************************************************** +// +//! Configures eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module +//! position-compare unit. See below for a description of this parameter. +//! \param compareValue is the value to which the position count value is +//! compared for a position-compare event. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the operation of the eQEP module position-compare +//! unit. The \e config parameter provides the configuration of the +//! position-compare unit and is the logical OR of several values: +//! +//! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or +//! \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse +//! and which pin should be used. +//! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or +//! \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when +//! should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP. +//! +//! The \e cycles is used to select the width of the sync output pulse. The +//! width of the resulting pulse will be \e cycles * 4 * the width of a +//! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \note You can set the sync pulse width independently using the +//! EQEP_setComparePulseWidth() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles); + +//***************************************************************************** +// +//! Sets the polarity of the eQEP module's input signals. +//! +//! \param base is the base address of the eQEP module. +//! \param invertQEPA is the flag to negate the QEPA input. +//! \param invertQEPB is the flag to negate the QEPA input. +//! \param invertIndex is the flag to negate the index input. +//! \param invertStrobe is the flag to negate the strobe input. +//! +//! This function configures the polarity of the inputs to the eQEP module. To +//! negate the polarity of any of the input signals, pass \b true into its +//! corresponding parameter in this function. Pass \b false to leave it as-is. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EQEP_H diff --git a/gpio_driverlib_cpu2/device/driverlib/flash.c b/gpio_driverlib_cpu2/device/driverlib/flash.c new file mode 100644 index 0000000..372b77b --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/flash.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: flash.c +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "flash.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_powerDown, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_wakeFromLPM, ".TI.ramfunc"); +#endif + +//***************************************************************************** +// +// Flash_initModule +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT(waitstates <= 0xFU); + + // + // Set the bank power up delay so that the bank will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Set the bank fallback power mode to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Power up flash bank and pump and this also sets the fall back mode of + // flash and pump as active + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); + + // + // Disable cache and prefetch mechanism before changing wait states + // + Flash_disableCache(ctrlBase); + Flash_disablePrefetch(ctrlBase); + + // + // Set waitstates according to frequency. + // + Flash_setWaitstates(ctrlBase, waitstates); + + + // + // Enable cache and prefetch mechanism to improve performance of code + // executed from flash. + // + Flash_enableCache(ctrlBase); + Flash_enablePrefetch(ctrlBase); + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash_enableECC(eccBase); + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + + FLASH_DELAY_CONFIG; +} + +//***************************************************************************** +// +// Flash_powerDown +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_powerDown(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank power up delay so that it will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Power down the flash bank. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_SLEEP); + + // + // Power down the flash pump. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_SLEEP); +} + +//***************************************************************************** +// +// Flash_wakeFromLPM +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_wakeFromLPM(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank fallback power modes to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Set the flash pump power mode to active. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); +} diff --git a/gpio_driverlib_cpu2/device/driverlib/flash.h b/gpio_driverlib_cpu2/device/driverlib/flash.h new file mode 100644 index 0000000..a60a2f2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/flash.h @@ -0,0 +1,1671 @@ +//########################################################################### +// +// FILE: flash.h +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH_H +#define FLASH_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif +#ifndef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +//! \addtogroup flash_api Flash +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_flash.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc"); +#endif + + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the bank parameter +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK = 0x0 //!< Bank +} Flash_BankNumber; + +//***************************************************************************** +// +//! Values that can be passed to Flash_claimPumpSemaphore() in order to claim +//! the pump semaphore. +// +//***************************************************************************** +typedef enum +{ + FLASH_CPU1_WRAPPER = 0x2, //!< CPU1 Wrapper + FLASH_CPU2_WRAPPER = 0x1 //!< CPU2 Wrapper +}Flash_PumpOwnership; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_BANK_PWR_STANDBY = 0x1, //!< Standby fallback mode + FLASH_BANK_PWR_ACTIVE = 0x3 //!< Active fallback mode +} Flash_BankPowerMode; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setPumpPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_PUMP_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_PUMP_PWR_ACTIVE = 0x1 //!< Active fallback mode +} Flash_PumpPowerMode; + +//***************************************************************************** +// +//! Type that correspond to values returned from Flash_getLowErrorStatus() and +//! Flash_getHighErrorStatus() determining the error status code. +// +//***************************************************************************** +typedef enum +{ + FLASH_NO_ERR = 0x0, //!< No error + FLASH_FAIL_0 = 0x1, //!< Fail on 0 + FLASH_FAIL_1 = 0x2, //!< Fail on 1 + FLASH_UNC_ERR = 0x4 //!< Uncorrectable error +} Flash_ErrorStatus; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getLowErrorType() and +//! Flash_getHighErrorType() determining the error type. +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_ERR = 0x0, //!< Data error + FLASH_ECC_ERR = 0x1 //!< ECC error +} Flash_ErrorType; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getECCTestSingleBitErrorType(). +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_BITS = 0x0, //!< Data bits + FLASH_CHECK_BITS = 0x1 //!< ECC bits +} Flash_SingleBitErrorIndicator; + +//***************************************************************************** +// +// Values that can be passed to Flash_clearLowErrorStatus and +// Flash_clearHighErrorStatus. +// +//***************************************************************************** +#define FLASH_FAIL_0_CLR 0x1 //!< Fail-0 clear +#define FLASH_FAIL_1_CLR 0x2 //!< Fail-1 clear +#define FLASH_UNC_ERR_CLR 0x4 //!< Uncorrectable error Clear + +//***************************************************************************** +// +// Values that can be returned from Flash_getInterruptFlag and +// Flash_getECCTestStatus. +// +//***************************************************************************** +#define FLASH_NO_ERROR 0x0 //!< No error +#define FLASH_SINGLE_ERROR 0x1 //!< Single bit error +#define FLASH_UNC_ERROR 0x2 //!< Uncorrectable error + +//***************************************************************************** +// +// Delay instruction that allows for register configuration to complete. +// +//***************************************************************************** +#define FLASH_DELAY_CONFIG __asm(" RPT #7 || NOP") + +//***************************************************************************** +// +// Key value for claiming the pump semaphore. +// +//***************************************************************************** +#define FLASH_PUMP_KEY 0x5A5A0000UL //!< Pump semaphore key + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function determines if a flash wrapper control base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isCtrlBaseValid(uint32_t ctrlBase) +{ + return((ctrlBase == FLASH0CTRL_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the ECC registers. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function determines if a flash wrapper ECC base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isECCBaseValid(uint32_t eccBase) +{ + return((eccBase == FLASH0ECC_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash pump semaphore base address. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! This function determines if a flash pump semaphore base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isPumpSemBaseValid(uint32_t pumpSemBase) +{ + return((pumpSemBase == FLASHPUMPSEMAPHORE_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the random read wait state amount. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param waitstates is the wait-state value. +//! +//! This function sets the number of wait states for a flash read access. The +//! \e waitstates parameter is a number between 0 and 15. It is \b important +//! to look at your device's datasheet for information about what the required +//! minimum flash wait-state is for your selected SYSCLK frequency. +//! +//! By default the wait state amount is configured to the maximum 15. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // waitstates is 4 bits wide. + // + ASSERT(waitstates <= 0xFU); + + EALLOW; + // + // Write flash read wait-state amount to appropriate register. + // + HWREG(ctrlBase + FLASH_O_FRDCNTL) = + (HWREG(ctrlBase + FLASH_O_FRDCNTL) & + ~(uint32_t)FLASH_FRDCNTL_RWAIT_M) | + ((uint32_t)waitstates << FLASH_FRDCNTL_RWAIT_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of a flash bank. +//! +//! \param ctrlBase is the base address of the flash wrapper registers. +//! \param bank is the flash bank that is being configured. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode of the flash bank specified by +//! them \e bank parameter. The power mode is specified by the \e powerMode +//! parameter with one of the following values: +//! +//! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled. +//! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference +//! enabled. +//! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled. +//! +//! +//! Note: There is only one Flash_BankNumber value on this device (FLASH_BANK). +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank, + Flash_BankPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FBFALLBACK) = + (HWREG(ctrlBase + FLASH_O_FBFALLBACK) & + ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t)bank * 2U))) | + ((uint32_t)powerMode << ((uint32_t)bank * 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of the charge pump. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode flash charge pump. +//! +//! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled. +//! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PMPPWR) | (uint32_t)powerMode; + EDIS; +} + +//***************************************************************************** +// +//! Enables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Write the key value 0xA to ECC_ENABLE register. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0xAU; + EDIS; +} + +//***************************************************************************** +// +//! Disables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Clear ECC enable field with the one's complement of the key. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0x5U; + EDIS; +} + + +//***************************************************************************** +// +//! Sets the bank power up delay. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param delay is the number of HCLK cycles. +//! +//! This function sets the VREADST delay to ensure that the requisite delay is +//! introduced for the flash pump/bank to come out of low-power mode, so that +//! the flash/OTP is ready for CPU access. +//! +//! Note: Refer to TRM before configuring VREADST. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setBankPowerUpDelay(uint32_t ctrlBase, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(delay <= 0xFF); + + EALLOW; + + // + // Write period to the BAGP of the FBAC register. + // + HWREG(ctrlBase + FLASH_O_FBAC) = (HWREG(ctrlBase + FLASH_O_FBAC) & + ~(uint32_t)FLASH_FBAC_VREADST_M) | delay; + EDIS; +} + +//***************************************************************************** +// +//! Sets the pump wake up time. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump +//! to wakeup. +//! +//! This function sets the wakeup time with \e sysclkCycles parameter. +//! The \e sysclkCycles is a value between 0 and 8190. When the charge pump +//! exits sleep power mode, it will take sysclkCycles to wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // PSLEEP = sysclkCycles/2. PSLEEP maximum value is 4095(12 bits wide) + // + ASSERT( sysclkCycles <= 8190U ); + + EALLOW; + + // + // Write sysclkCycles/2 to PSLEEP of the FPAC1 register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PSLEEP_M) | + (((uint32_t)sysclkCycles / (uint32_t)2) << + (uint32_t)FLASH_FPAC1_PSLEEP_S); + EDIS; +} + +//***************************************************************************** +// +//! Reads the bank active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param bank is the flash bank that is being used. +//! +//! \return Returns \b true if the Bank is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + uint32_t bitMask = (uint32_t)FLASH_FBPRDY_BANKRDY << (uint32_t)bank; + // + // Return the BANKXRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & bitMask) == bitMask) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + +//***************************************************************************** +// +//! Reads the pump active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return Returns \b true if the Pump is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isPumpReady(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + + // + // Return the PUMPRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & + (uint32_t)FLASH_FBPRDY_PUMPRDY) == FLASH_FBPRDY_PUMPRDY) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + + +//***************************************************************************** +// +//! Gets the single error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the single error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC base. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the error status of the Lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the lower 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the low error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getLowErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the Low Error Status bits + // + errorStatus = (HWREG(eccBase + FLASH_O_ERR_STATUS) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error status of the Upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the upper 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the high error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getHighErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the High Error Status bits + // + errorStatus = ((HWREG(eccBase + FLASH_O_ERR_STATUS) >> 16U) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error position of the lower 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the lower 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the lower error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getLowErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_L_M) >> + FLASH_ERR_POS_ERR_POS_L_S); +} + +//***************************************************************************** +// +//! Gets the error position of the upper 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the upper 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the upper error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getHighErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_H_M) >> + FLASH_ERR_POS_ERR_POS_H_S); +} + +//***************************************************************************** +// +//! Gets the error type of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the lower 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the lower 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getLowErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_L) + == FLASH_ERR_POS_ERR_TYPE_L) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} + +//***************************************************************************** +// +//! Gets the error type of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the upper 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the upper 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getHighErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_H) + == FLASH_ERR_POS_ERR_TYPE_H) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} +//***************************************************************************** +// +//! Clears the errors status of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus); + EDIS; +} + +//***************************************************************************** +// +//! Clears the errors status of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus << 16U); + EDIS; +} + +//***************************************************************************** +// +//! Gets the single bit error count. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error count. +// +//***************************************************************************** +static inline uint32_t +Flash_getErrorCount(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_ERR_CNT) & + (uint32_t)FLASH_ERR_CNT_ERR_CNT_M); +} + +//***************************************************************************** +// +//! Sets the single bit error threshold. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param threshold is the single bit error threshold. Valid ranges are from +//! 0-65535. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_THRESHOLD) = ((uint32_t)threshold & + (uint32_t)FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M); + EDIS; +} + +//***************************************************************************** +// +//! Gets the error interrupt. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the type of error interrupt that occurred. The +//! values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the interrupt flag. +// +//***************************************************************************** +static inline uint32_t +Flash_getInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_ERR_INTFLG) & (uint32_t)0x3U)); +} + +//***************************************************************************** +// +//! Clears the single error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearSingleErrorInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Clears the uncorrectable error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearUncorrectableInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_UNC_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data Low Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the low double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAL_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data High Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the high double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAH_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the test address register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param address is a 32-bit value containing an address. Bits 21-3 will be +//! used as the flash word (128-bit) address. +//! +//! This function left shifts the address 1 bit to convert it to a byte address +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestAddress(uint32_t eccBase, uint32_t address) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Left shift the address 1 bit to make it byte-addressable + // + uint32_t byteAddress = address << 1; + + EALLOW; + + // + // Write bits 21-3 to the register. + // + HWREG(eccBase + FLASH_O_FADDR_TEST) = byteAddress; + + EDIS; + +} + +//***************************************************************************** +// +//! Sets the ECC test bits for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param ecc is a 32-bit value. The least significant 8 bits are used as +//! the ECC Control Bits in the ECC Test. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + ASSERT( ecc <= 255U ); + EALLOW; + + // + // Write the 8 ECC Control Bits. + // + HWREG(eccBase + FLASH_O_FECC_TEST) = + ((uint32_t)ecc & (uint32_t)FLASH_FECC_TEST_ECC_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_enableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [63:0] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectLowECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [127:64] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectHighECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Performs the ECC calculation on the test block. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_performECCCalculation(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_DO_ECC_CALC; + EDIS; +} + +//***************************************************************************** +// +//! Gets the ECC Test data out high 63:32 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC TEst data out High. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTH_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test data out low 31:0 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test data out Low. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTL_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test status. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the ECC test status. The values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the ECC test status. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestStatus(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS)) & (uint32_t)0x3U); +} + +//***************************************************************************** +// +//! Gets the ECC Test single bit error position. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test single bit error position. If the error type +//! is check bits than the position can range from 0 to 7. If the error type +//! is data bits than the position can range from 0 to 63. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the position bits and shift it to the right. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_DATA_ERR_POS_M) >> + FLASH_FECC_STATUS_DATA_ERR_POS_S); +} + +//***************************************************************************** +// +//! Gets the single bit error type. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error type as a +//! Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS +//! indicate where the single bit error occurred. +// +//***************************************************************************** +static inline Flash_SingleBitErrorIndicator +Flash_getECCTestSingleBitErrorType(uint32_t eccBase) +{ + uint32_t errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the ERR_TYPE bit to see where the single bit error was. + // + errorType = ((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_ERR_TYPE) >> 8U); + return((Flash_SingleBitErrorIndicator)errorType); +} + +//***************************************************************************** +// +//! Claim the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! \param wrapper is the Flash_PumpOwnership wrapper claiming the pump +//! semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_claimPumpSemaphore(uint32_t pumpSemBase, Flash_PumpOwnership wrapper) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Block until the pump semaphore is claimed. + // + EALLOW; + while((HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) + & FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M) != wrapper) + { + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = + FLASH_PUMP_KEY | (uint32_t)wrapper; + } + EDIS; +} + +//***************************************************************************** +// +//! Release the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_releasePumpSemaphore(uint32_t pumpSemBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Relinquish the pump semaphore. + // + EALLOW; + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = FLASH_PUMP_KEY; + EDIS; +} + +//***************************************************************************** +// +//! Initializes the flash control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param waitstates is the wait-state value. +//! +//! This function initializes the flash control registers. At reset bank and +//! pump are in sleep. A flash access will power up the bank and pump +//! automatically. This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! This function also sets the number of wait-states for a flash access +//! (see Flash_setWaitstates() for more details), and enables cache, the +//! prefetch mechanism, and ECC. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates); + + +//***************************************************************************** +// +//! Powers down the flash. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function powers down the flash bank(s) and the flash pump. +//! +//! Note: For this device, you must claim the flash pump semaphore before +//! calling this function and powering down the pump. Afterwards, you may want +//! to relinquish the flash pump. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_powerDown(uint32_t ctrlBase); + +//***************************************************************************** +// +//! Wakes the flash from low power mode. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_wakeFromLPM(uint32_t ctrlBase); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +#endif // #ifdef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // FLASH_H diff --git a/gpio_driverlib_cpu2/device/driverlib/gpio.c b/gpio_driverlib_cpu2/device/driverlib/gpio.c new file mode 100644 index 0000000..be20285 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/gpio.c @@ -0,0 +1,489 @@ +//########################################################################### +// +// FILE: gpio.c +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "gpio.h" + +//***************************************************************************** +// +// GPIO_setDirectionMode +// +//***************************************************************************** +void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Set the data direction + // + if(pinIO == GPIO_DIR_MODE_OUT) + { + // + // Output + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask; + } + else + { + // + // Input + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getDirectionMode +// +//***************************************************************************** +GPIO_Direction +GPIO_getDirectionMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >> + (pin % 32U)) & 1U))); + +} + +//***************************************************************************** +// +// GPIO_setInterruptPin +// +//***************************************************************************** +void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum) +{ + XBAR_InputNum input; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + // + // Pick the X-BAR input that corresponds to the requested XINT. + // + switch(extIntNum) + { + case GPIO_INT_XINT1: + input = XBAR_INPUT4; + break; + + case GPIO_INT_XINT2: + input = XBAR_INPUT5; + break; + + case GPIO_INT_XINT3: + input = XBAR_INPUT6; + break; + + case GPIO_INT_XINT4: + input = XBAR_INPUT13; + break; + + case GPIO_INT_XINT5: + input = XBAR_INPUT14; + break; + + default: + // + // Invalid interrupt. Shouldn't happen if enum value is used. + // XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for + // a bad value. + // + input = XBAR_INPUT1; + break; + } + + if(input != XBAR_INPUT1) + { + XBAR_setInputPin(input, (uint16_t)pin); + } +} + +//***************************************************************************** +// +// GPIO_setPadConfig +// +//***************************************************************************** +void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Enable open drain if necessary + // + if((pinType & GPIO_PIN_TYPE_OD) != 0U) + { + gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask; + } + + // + // Enable pull-up if necessary + // + if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U) + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask; + } + + // + // Invert polarity if necessary + // + if((pinType & GPIO_PIN_TYPE_INVERT) != 0U) + { + gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getPadConfig +// +//***************************************************************************** +uint32_t +GPIO_getPadConfig(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + uint32_t pinTypeRes; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + pinTypeRes = GPIO_PIN_TYPE_STD; + + // + // Get open drain value + // + if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_OD; + } + + // + // Get pull-up value + // + if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_PULLUP; + } + + // + // Get polarity value + // + if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_INVERT; + } + + return(pinTypeRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationMode +// +//***************************************************************************** +void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Write the input qualification mode to the register. + // + EALLOW; + + gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt; + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getQualificationMode +// +//***************************************************************************** +GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t qualRes; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Read the qualification mode register and shift and mask to get the + // value for the specified pin. + // + qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) & + (uint32_t)GPIO_GPAQSEL1_GPIO0_M; + return((GPIO_QualificationMode)qualRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationPeriod +// +//***************************************************************************** +void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask, regVal, shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + ASSERT((divider >= 1U) && (divider <= 510U)); + + shiftAmt = (pin % 32U) & ~((uint32_t)0x7U); + pinMask = (uint32_t)0xFFU << shiftAmt; + + // + // Divide divider by two to get the value that needs to go into the field. + // Then shift it into the right place. + // + regVal = (divider / 2U) << shiftAmt; + + // + // Write the divider parameter into the register. + // + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setControllerCore +// +//***************************************************************************** +void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t cSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U); + cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U); + + // + // Write the core parameter into the register. + // + EALLOW; + gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setAnalogMode +// +//***************************************************************************** +void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT((pin == 42U) || (pin == 43U)); + + pinMask = (uint32_t)1U << (pin % 32U); + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + + // + // Set the analog mode selection. + // + if(mode == GPIO_ANALOG_ENABLED) + { + // + // Enable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask; + } + else + { + // + // Disable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_setPinConfig +// +//***************************************************************************** +void +GPIO_setPinConfig(uint32_t pinConfig) +{ + uint32_t muxRegAddr; + uint32_t pinMask, shiftAmt; + + muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16); + shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU); + pinMask = (uint32_t)0x3U << shiftAmt; + + EALLOW; + + // + // Clear fields in MUX register first to avoid glitches + // + HWREG(muxRegAddr) &= ~pinMask; + + // + // Write value into GMUX register + // + HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) = + (HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) | + (((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt); + + // + // Write value into MUX register + // + HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt); + EDIS; +} diff --git a/gpio_driverlib_cpu2/device/driverlib/gpio.h b/gpio_driverlib_cpu2/device/driverlib/gpio.h new file mode 100644 index 0000000..05ae80a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/gpio.h @@ -0,0 +1,1047 @@ +//########################################################################### +// +// FILE: gpio.h +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef GPIO_H +#define GPIO_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup gpio_api GPIO +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_gpio.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_xint.h" +#include "cpu.h" +#include "xbar.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions to access gpio registers. +// Not intended for use by application code. +// +// Divide by 2 is for C28x which has word access +// +//***************************************************************************** +#define GPIO_CTRL_REGS_STEP ((GPIO_O_GPBCTRL - GPIO_O_GPACTRL) / 2U) +#define GPIO_DATA_REGS_STEP ((GPIO_O_GPBDAT - GPIO_O_GPADAT) / 2U) + +#define GPIO_GPxCTRL_INDEX (GPIO_O_GPACTRL / 2U) +#define GPIO_GPxQSEL_INDEX (GPIO_O_GPAQSEL1 / 2U) +#define GPIO_GPxMUX_INDEX (GPIO_O_GPAMUX1 / 2U) +#define GPIO_GPxDIR_INDEX (GPIO_O_GPADIR / 2U) +#define GPIO_GPxAMSEL_INDEX (0x00000014U / 2U) // Address rsvd for GPAAMSEL +#define GPIO_GPxPUD_INDEX (GPIO_O_GPAPUD / 2U) +#define GPIO_GPxINV_INDEX (GPIO_O_GPAINV / 2U) +#define GPIO_GPxODR_INDEX (GPIO_O_GPAODR / 2U) +#define GPIO_GPxGMUX_INDEX (GPIO_O_GPAGMUX1 / 2U) +#define GPIO_GPxCSEL_INDEX (GPIO_O_GPACSEL1 / 2U) +#define GPIO_GPxLOCK_INDEX (GPIO_O_GPALOCK / 2U) +#define GPIO_GPxCR_INDEX (GPIO_O_GPACR / 2U) + +#define GPIO_GPxDAT_INDEX (GPIO_O_GPADAT / 2U) +#define GPIO_GPxSET_INDEX (GPIO_O_GPASET / 2U) +#define GPIO_GPxCLEAR_INDEX (GPIO_O_GPACLEAR / 2U) +#define GPIO_GPxTOGGLE_INDEX (GPIO_O_GPATOGGLE / 2U) + +#define GPIO_MUX_TO_GMUX (GPIO_O_GPAGMUX1 - GPIO_O_GPAMUX1) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to GPIO_setPadConfig() as the pinType parameter +// and returned by GPIO_getPadConfig(). +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x0000U //!< Push-pull output or floating input +#define GPIO_PIN_TYPE_PULLUP 0x0001U //!< Pull-up enable for input +#define GPIO_PIN_TYPE_INVERT 0x0002U //!< Invert polarity on input +#define GPIO_PIN_TYPE_OD 0x0004U //!< Open-drain on output +#endif + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO +//! parameter and returned from GPIO_getDirectionMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_DIR_MODE_IN, //!< Pin is a GPIO input + GPIO_DIR_MODE_OUT //!< Pin is a GPIO output +} GPIO_Direction; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptType() as the \e intType +//! parameter and returned from GPIO_getInterruptType(). +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_TYPE_FALLING_EDGE = 0x00, //!< Interrupt on falling edge + GPIO_INT_TYPE_RISING_EDGE = 0x04, //!< Interrupt on rising edge + GPIO_INT_TYPE_BOTH_EDGES = 0x0C //!< Interrupt on both edges +} GPIO_IntType; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setQualificationMode() as the +//! \e qualification parameter and returned by GPIO_getQualificationMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_QUAL_SYNC, //!< Synchronization to SYSCLK + GPIO_QUAL_3SAMPLE, //!< Qualified with 3 samples + GPIO_QUAL_6SAMPLE, //!< Qualified with 6 samples + GPIO_QUAL_ASYNC //!< No synchronization +} GPIO_QualificationMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_ANALOG_DISABLED, //!< Pin is in digital mode + GPIO_ANALOG_ENABLED //!< Pin is in analog mode +} GPIO_AnalogMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setControllerCore() as the \e core +//! parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_CORE_CPU1, //!< CPU1 selected as controller core + GPIO_CORE_CPU1_CLA1, //!< CPU1's CLA1 selected as controller core + GPIO_CORE_CPU2, //!< CPU2 selected as controller core + GPIO_CORE_CPU2_CLA1 //!< CPU2's CLA1 selected as controller core +} GPIO_CoreSelect; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(), +//! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_PORT_A = 0, //!< GPIO port A + GPIO_PORT_B = 1, //!< GPIO port B + GPIO_PORT_C = 2, //!< GPIO port C + GPIO_PORT_D = 3, //!< GPIO port D + GPIO_PORT_E = 4, //!< GPIO port E + GPIO_PORT_F = 5 //!< GPIO port F +} GPIO_Port; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptPin(), +//! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(), +//! GPIO_disableInterrupt(), as the \e extIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_XINT1, //!< External Interrupt 1 + GPIO_INT_XINT2, //!< External Interrupt 2 + GPIO_INT_XINT3, //!< External Interrupt 3 + GPIO_INT_XINT4, //!< External Interrupt 4 + GPIO_INT_XINT5 //!< External Interrupt 5 +} GPIO_ExternalIntNum; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks that a pin number is valid for a device. +//! +//! Note that this function reflects the highest possible GPIO number of a +//! device on its biggest package. Check the datasheet to see what the actual +//! range of valid pin numbers is for a specific package. +//! +//! \return None. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +GPIO_isPinValid(uint32_t pin) +{ + return(pin <= 168U); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin. +//! +//! \param extIntNum specifies the external interrupt. +//! \param intType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin on the selected GPIO port. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! One of the following flags can be used to define the \e intType +//! parameter: +//! +//! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to +//! falling +//! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising +//! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType) +{ + // + // Write the selected polarity to the appropriate register. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) = + (HWREGH(XINT_BASE + (uint16_t)extIntNum) & ~XINT_1CR_POLARITY_M) | + (uint16_t)intType; +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function gets the interrupt type for a interrupt. The interrupt can be +//! configured as a falling-edge, rising-edge, or both-edges detected +//! interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return Returns one of the flags described for GPIO_setInterruptType(). +// +//***************************************************************************** +static inline GPIO_IntType +GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum) +{ + // + // Read the selected polarity from the appropriate register. + // + return((GPIO_IntType)((uint16_t)(HWREGH(XINT_BASE + (uint16_t)extIntNum) & + XINT_1CR_POLARITY_M))); +} + +//***************************************************************************** +// +//! Enables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function enables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Set the enable bit for the specified interrupt. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) |= XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Disables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function disables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Clear the enable bit for the specified interrupt + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) &= ~XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Gets the value of the external interrupt counter. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns external interrupt counter value. +// +//***************************************************************************** +static inline uint16_t +GPIO_getInterruptCounter(GPIO_ExternalIntNum extIntNum) +{ + ASSERT(extIntNum <= GPIO_INT_XINT3); + + // + // Read the counter value from the appropriate register. + // + return((HWREGH(XINT_BASE + XINT_O_1CTR + (uint16_t)extIntNum))); +} + +//***************************************************************************** +// +//! Reads the value present on the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! The value at the specified pin are read, as specified by \e pin. The value +//! is returned for both input and output pins. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return Returns the value in the data register for the specified pin. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + return((gpioDataReg[GPIO_GPxDAT_INDEX] >> (pin % 32U)) & (uint32_t)0x1U); +} + + +//***************************************************************************** +// +//! Writes a value to the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param outVal is the value to write to the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePin(uint32_t pin, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + pinMask = (uint32_t)1U << (pin % 32U); + + if(outVal == 0U) + { + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; + } + else + { + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; + } +} + +//***************************************************************************** +// +//! Toggles the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = (uint32_t)1U << (pin % 32U); +} + +//***************************************************************************** +// +//! Reads the data on the specified port. +//! +//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X +//! where X is the port letter. +//! +//! \return Returns the value available on pin for the specified port. Each +//! bit of the the return value represents a pin on the port, where bit 0 +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPortData(GPIO_Port port) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and return DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + return(gpioDataReg[GPIO_GPxDAT_INDEX]); +} + + +//***************************************************************************** +// +//! Writes a value to the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param outVal is the value to write to the port. +//! +//! This function writes the value \e outVal to the port specified by the +//! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X +//! is the port letter. For example, use \b GPIO_PORT_A to affect port A +//! (GPIOs 0-31). +//! +//! The \e outVal is a bit-packed value, where each bit represents a bit on a +//! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port +//! pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePortData(GPIO_Port port, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxDAT_INDEX] = outVal; +} + +//***************************************************************************** +// +//! Sets all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function sets all of the pins specified by the \e pinMask parameter on +//! the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO +//! port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to SET. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Clears all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function clears all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is \b set +//! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1 +//! represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to CLEAR. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Toggles all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function toggles all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to TOGGLE. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Locks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function locks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that this function is for locking the configuration of a pin such as +//! the pin muxing, direction, open drain mode, and other settings. It does not +//! affect the ability to change the value of the pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function unlocks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] &= ~pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function commits the lock configuration registers of the pins +//! specified by the \e pinMask parameter on the port specified by the \e port +//! parameter which takes a value in the form of \b GPIO_PORT_X where X is the +//! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that once this function is called, GPIO_lockPortConfig() and +//! GPIO_unlockPortConfig() will no longer have any effect on the specified +//! pins. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxCR_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinIO is the pin direction mode. +//! +//! This function configures the specified pin on the selected GPIO port as +//! either input or output. +//! +//! The parameter \e pinIO is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input +//! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO); + +//***************************************************************************** +// +//! Gets the direction mode of a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function gets the direction mode for a specified pin. The pin can be +//! configured as either an input or output The type of direction is returned +//! as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIO_setDirectionMode(). +// +//***************************************************************************** +extern GPIO_Direction +GPIO_getDirectionMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the pin for the specified external interrupt. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param extIntNum specifies the external interrupt. +//! +//! This function sets which pin triggers the selected external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \sa XBAR_setInputPin() +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum); + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinType specifies the pin type. +//! +//! This function sets the pin type for the specified pin. The parameter +//! \e pinType can be the following values: +//! +//! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input +//! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input +//! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin +//! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input +//! +//! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or +//! \b GPIO_PIN_TYPE_PULLUP. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType); + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function returns the pin type for the specified pin. The value +//! returned corresponds to the values used in GPIO_setPadConfig(). +//! +//! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD, +//! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT. +// +//***************************************************************************** +extern uint32_t +GPIO_getPadConfig(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification mode for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param qualification specifies the qualification mode of the pin. +//! +//! This function sets the qualification mode for the specified pin. The +//! parameter \e qualification can be one of the following values: +//! - \b GPIO_QUAL_SYNC +//! - \b GPIO_QUAL_3SAMPLE +//! - \b GPIO_QUAL_6SAMPLE +//! - \b GPIO_QUAL_ASYNC +//! +//! To set the qualification sampling period, use +//! GPIO_setQualificationPeriod(). +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification); + +//***************************************************************************** +// +//! Gets the qualification type for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! \return Returns the qualification mode in the form of one of the values +//! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or +//! \b GPIO_QUAL_ASYNC. +// +//***************************************************************************** +extern GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification period for a set of pins +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param divider specifies the output drive strength. +//! +//! This function sets the qualification period for a set of \b 8 \b pins, +//! specified by the \e pin parameter. For instance, passing in 3 as the value +//! of \e pin will set the qualification period for GPIO0 through GPIO7, and a +//! value of 98 will set the qualification period for GPIO96 through GPIO103. +//! This is because the register field that configures the divider is shared. +//! +//! To think of this in terms of an equation, configuring \e pin as \b n will +//! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7). +//! +//! \e divider is the value by which the frequency of SYSCLKOUT is divided. It +//! can be 1 or an even value between 2 and 510 inclusive. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider); + +//***************************************************************************** +// +//! Selects the controller core of a specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param core is the core that is controller of the specified pin. +//! +//! This function configures which core owns the specified pin's data registers +//! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data +//! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's +//! CLA1 controller of the pin. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core); + +//***************************************************************************** +// +//! Sets the analog mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param mode is the selected analog mode. +//! +//! This function configures the specified pin for either analog or digital +//! mode. Not all GPIO pins have the ability to be switched to analog mode, +//! so refer to the technical reference manual for details. This setting should +//! be thought of as another level of muxing. +//! +//! The parameter \e mode is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode +//! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \b Note: The pin parameter is applicable for both AIO and GPIO because +//! the GPAxMSEL.GPIOy register configures for both +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode); + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param pinConfig is the pin configuration value, specified as only one +//! of the \b GPIO_#_???? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). +//! +//! The available mappings are supplied in pin_map.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPinConfig(uint32_t pinConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // GPIO_H diff --git a/gpio_driverlib_cpu2/device/driverlib/hrpwm.c b/gpio_driverlib_cpu2/device/driverlib/hrpwm.c new file mode 100644 index 0000000..04aa22c --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/hrpwm.c @@ -0,0 +1,47 @@ +//########################################################################### +// +// FILE: hrpwm.c +// +// TITLE: C28x HRPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "hrpwm.h" + +// +// All the API functions are in-lined in hrpwm.h +// diff --git a/gpio_driverlib_cpu2/device/driverlib/hrpwm.h b/gpio_driverlib_cpu2/device/driverlib/hrpwm.h new file mode 100644 index 0000000..2561d67 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/hrpwm.h @@ -0,0 +1,1657 @@ +//############################################################################# +// +// FILE: hrpwm.h +// +// TITLE: C28x HRPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef HRPWM_H +#define HRPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup hrpwm_api HRPWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_hrpwm.h" +#include "cpu.h" +#include "debug.h" +#include "epwm.h" +#include "hrpwm.h" + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect(), +//! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent() +//! as the \e channel parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_CHANNEL_A = 0, //!< HRPWM A + HRPWM_CHANNEL_B = 8 //!< HRPWM B +} HRPWM_Channel; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_MEP_CTRL_DISABLE = 0, + //! MEP controls rising edge + HRPWM_MEP_CTRL_RISING_EDGE = 1, + //! MEP controls falling edge + HRPWM_MEP_CTRL_FALLING_EDGE = 2, + //! MEP controls both rising and falling edge + HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3 +} HRPWM_MEPEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! CMPAHR/CMPBHR or TBPRDHR controls MEP edge + HRPWM_MEP_DUTY_PERIOD_CTRL = 0, + //! TBPHSHR controls MEP edge + HRPWM_MEP_PHASE_CTRL = 1 +} HRPWM_MEPCtrlMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(), +//! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode +//! as the \e loadEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! load when counter equals zero + HRPWM_LOAD_ON_CNTR_ZERO = 0, + //! load when counter equals period + HRPWM_LOAD_ON_CNTR_PERIOD = 1, + //! load when counter equals zero or period + HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2, +} HRPWM_LoadMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e +//! outputOnB parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal. + HRPWM_OUTPUT_ON_B_INV_A = 1 //!< ePWMxB output is inverted + //!< version of ePWMxA signal +} HRPWM_ChannelBOutput; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setSyncPulseSource() as the \e +//! syncPulseSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Counter equals Period + HRPWM_PWMSYNC_SOURCE_PERIOD = 0, + //! Counter equals zero + HRPWM_PWMSYNC_SOURCE_ZERO = 1, + //! Counter equals COMPC when counting up + HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4, + //! Counter equals COMPC when counting down + HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5, + //! Counter equals COMPD when counting up + HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6, + //! Counter equals COMPD when counting down + HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7 +} HRPWM_SyncPulseSource; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareValue() as the \e +//! compModule parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A + HRPWM_COUNTER_COMPARE_B = 4 //!< counter compare B +} HRPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e +//! mepDBEdge. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_DB_MEP_CTRL_DISABLE = 0, + //! MEP controls Rising Edge Delay + HRPWM_DB_MEP_CTRL_RED = 1, + //! MEP controls Falling Edge Delay + HRPWM_DB_MEP_CTRL_FED = 2, + //! MEP controls both Falling and Rising edge delay + HRPWM_DB_MEP_CTRL_RED_FED = 3 +} HRPWM_MEPDeadBandEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup +//! parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_REGISTER_GROUP_HRPWM = 0x1, //!< HRPWM register group + HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group + HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group + HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group + HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group +} HRPWM_LockRegisterGroup; + +//***************************************************************************** +// +// Functions APIs shared with ePWM module +// +//***************************************************************************** + +// +// Time Base Sub Module related APIs +// +#define HRPWM_setTimeBaseCounter EPWM_setTimeBaseCounter +#define HRPWM_setCountModeAfterSync EPWM_setCountModeAfterSync +#define HRPWM_setClockPrescaler EPWM_setClockPrescaler +#define HRPWM_swForceSyncPulse EPWM_forceSyncPulse +#define HRPWM_setSyncOutPulseMode EPWM_setSyncOutPulseMode +#define HRPWM_setPeriodLoadMode EPWM_setPeriodLoadMode +#define HRPWM_setTimeBaseCounterMode EPWM_setTimeBaseCounterMode +#define HRPWM_selectPeriodLoadEvent EPWM_selectPeriodLoadEvent +#define HRPWM_enableOneShotSync EPWM_enableOneShotSync +#define HRPWM_disableOneShotSync EPWM_disableOneShotSync +#define HRPWM_startOneShotSync EPWM_startOneShotSync +#define HRPWM_getTimeBaseCounterOverflowStatus \ + EPWM_getTimeBaseCounterOverflowStatus +#define HRPWM_clearTimeBaseCounterOverflowEvent \ + EPWM_clearTimeBaseCounterOverflowEvent +#define HRPWM_getSyncStatus EPWM_getSyncStatus +#define HRPWM_clearSyncEvent EPWM_clearSyncEvent +#define HRPWM_getTimeBaseCounterDirection EPWM_getTimeBaseCounterDirection +#define HRPWM_setupEPWMLinks EPWM_setupEPWMLinks +#define HRPWM_setCounterCompareShadowLoadMode \ + EPWM_setCounterCompareShadowLoadMode +#define HRPWM_disableCounterCompareShadowLoadMode \ + EPWM_disableCounterCompareShadowLoadMode +#define HRPWM_getCounterCompareShadowStatus \ + EPWM_getCounterCompareShadowStatus + +// +// Action Qualifier module related APIs +// +#define HRPWM_setActionQualifierShadowLoadMode \ + EPWM_setActionQualifierShadowLoadMode +#define HRPWM_disableActionQualifierShadowLoadMode \ + EPWM_disableActionQualifierShadowLoadMode +#define HRPWM_setActionQualifierT1TriggerSource \ + EPWM_setActionQualifierT1TriggerSource +#define HRPWM_setActionQualifierT2TriggerSource \ + EPWM_setActionQualifierT2TriggerSource +#define HRPWM_setActionQualifierAction EPWM_setActionQualifierAction +#define HRPWM_setActionQualifierContSWForceShadowMode \ + EPWM_setActionQualifierContSWForceShadowMode +#define HRPWM_setActionQualifierContSWForceAction \ + EPWM_setActionQualifierContSWForceAction +/* HRPWM_setActionQualifierSwAction is kept for compatibility, +use HRPWM_setActionQualifierSWAction*/ +#define HRPWM_setActionQualifierSwAction EPWM_setActionQualifierSwAction +#define HRPWM_setActionQualifierSWAction EPWM_setActionQualifierSWAction +/* HRPWM_forceActionQualifierSwAction is kept for compatibility, +use HRPWM_forceActionQualifierSWAction*/ +#define HRPWM_forceActionQualifierSwAction EPWM_forceActionQualifierSwAction +#define HRPWM_forceActionQualifierSWAction EPWM_forceActionQualifierSWAction +// +// Dead Band Module related APIs +// +#define HRPWM_setDeadBandOutputSwapMode EPWM_setDeadBandOutputSwapMode +#define HRPWM_setDeadBandDelayMode EPWM_setDeadBandDelayMode +#define HRPWM_setDeadBandDelayPolarity EPWM_setDeadBandDelayPolarity +#define HRPWM_setRisingEdgeDeadBandDelayInput \ + EPWM_setRisingEdgeDeadBandDelayInput +#define HRPWM_setFallingEdgeDeadBandDelayInput \ + EPWM_setFallingEdgeDeadBandDelayInput +#define HRPWM_setDeadBandControlShadowLoadMode \ + EPWM_setDeadBandControlShadowLoadMode +#define HRPWM_disableDeadBandControlShadowLoadMode \ + EPWM_disableDeadBandControlShadowLoadMode +#define HRPWM_setRisingEdgeDelayCountShadowLoadMode \ + EPWM_setRisingEdgeDelayCountShadowLoadMode +#define HRPWM_disableRisingEdgeDelayCountShadowLoadMode \ + EPWM_disableRisingEdgeDelayCountShadowLoadMode +#define HRPWM_setFallingEdgeDelayCountShadowLoadMode \ + EPWM_setFallingEdgeDelayCountShadowLoadMode +#define HRPWM_disableFallingEdgeDelayCountShadowLoadMode \ + EPWM_disableFallingEdgeDelayCountShadowLoadMode +#define HRPWM_setDeadBandCounterClock EPWM_setDeadBandCounterClock +#define HRPWM_setRisingEdgeDelayCount EPWM_setRisingEdgeDelayCount +#define HRPWM_setFallingEdgeDelayCount EPWM_setFallingEdgeDelayCount + +// +// Chopper module related APIs +// +#define HRPWM_enableChopper EPWM_enableChopper +#define HRPWM_disableChopper EPWM_disableChopper +#define HRPWM_setChopperDutyCycle EPWM_setChopperDutyCycle +#define HRPWM_setChopperFreq EPWM_setChopperFreq +#define HRPWM_setChopperFirstPulseWidt EPWM_setChopperFirstPulseWidth + +// +// Trip Zone module related APIs +// +#define HRPWM_enableTripZoneSignals EPWM_enableTripZoneSignals +#define HRPWM_disableTripZoneSignals EPWM_disableTripZoneSignals +#define HRPWM_setTripZoneDigitalCompareEventCondition \ + EPWM_setTripZoneDigitalCompareEventCondition +#define HRPWM_enableTripZoneAdvAction EPWM_enableTripZoneAdvAction +#define HRPWM_disableTripZoneAdvAction EPWM_disableTripZoneAdvAction +#define HRPWM_setTripZoneAction EPWM_setTripZoneAction +#define HRPWM_setTripZoneAdvAction EPWM_setTripZoneAdvAction +#define HRPWM_setTripZoneAdvDigitalCompareActionA \ + EPWM_setTripZoneAdvDigitalCompareActionA +#define HRPWM_setTripZoneAdvDigitalCompareActionB \ + EPWM_setTripZoneAdvDigitalCompareActionB +#define HRPWM_enableTripZoneInterrupt EPWM_enableTripZoneInterrupt +#define HRPWM_disableTripZoneInterrupt EPWM_disableTripZoneInterrupt + +// +// HRPWM_getTripZoneInterruptStatus API define is obsolete please use +// HRPWM_getTripZoneFlagStatus going forward. +// +#define HRPWM_getTripZoneInterruptStatus EPWM_getTripZoneFlagStatus +#define HRPWM_getTripZoneFlagStatus EPWM_getTripZoneFlagStatus + +// +// HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete +// please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward. +// +#define HRPWM_getCycleByCycleTripZoneInterruptStatus \ + HRPWM_getCycleByCycleTripZoneFlagStatus +#define HRPWM_getCycleByCycleTripZoneFlagStatus \ + EPWM_getCycleByCycleTripZoneFlagStatus + +// +// HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use +// HRPWM_getOneShotTripZoneFlagStatus going forward. +// +#define HRPWM_getOneShotTripZoneInterruptStatus \ + HRPWM_getOneShotTripZoneFlagStatus +#define HRPWM_getOneShotTripZoneFlagStatus \ + EPWM_getOneShotTripZoneFlagStatus +#define HRPWM_selectCycleByCycleTripZoneClearEvent \ + EPWM_selectCycleByCycleTripZoneClearEvent + +// +// HRPWM_clearTripZoneInterruptFlag is obsolete please use +// HRPWM_clearTripZoneFlag going forward. +// +#define HRPWM_clearTripZoneInterruptFlag HRPWM_clearTripZoneFlag +#define HRPWM_clearTripZoneFlag EPWM_clearTripZoneFlag + +// +// HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use +// HRPWM_clearCycleByCycleTripZoneFlag going forward. +// +#define HRPWM_clearCycleByCycleTripZoneInterruptFlag \ + HRPWM_clearCycleByCycleTripZoneFlag +#define HRPWM_clearCycleByCycleTripZoneFlag \ + EPWM_clearCycleByCycleTripZoneFlag + +// +// HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use +// HRPWM_clearOneShotTripZoneFlag going forward. +// +#define HRPWM_clearOneShotTripZoneInterruptFlag \ + HRPWM_clearOneShotTripZoneFlag +#define HRPWM_clearOneShotTripZoneFlag \ + EPWM_clearOneShotTripZoneFlag +#define HRPWM_forceTripZoneEvent EPWM_forceTripZoneEvent + +// +// Event Trigger related APIs +// +#define HRPWM_enableInterrupt EPWM_enableInterrupt +#define HRPWM_disableInterrupt EPWM_disableInterrupt +#define HRPWM_setInterruptSource EPWM_setInterruptSource +#define HRPWM_setInterruptEventCount EPWM_setInterruptEventCount +#define HRPWM_getEventTriggerInterruptStatus \ + EPWM_getEventTriggerInterruptStatus +#define HRPWM_clearEventTriggerInterruptFlag \ + EPWM_clearEventTriggerInterruptFlag +#define HRPWM_enableInterruptEventCountInit \ + EPWM_enableInterruptEventCountInit +#define HRPWM_disableInterruptEventCountInit \ + EPWM_disableInterruptEventCountInit +#define HRPWM_forceInterruptEventCountInit \ + EPWM_forceInterruptEventCountInit +#define HRPWM_setInterruptEventCountInitValue \ + EPWM_setInterruptEventCountInitValue +#define HRPWM_getInterruptEventCount EPWM_getInterruptEventCount +#define HRPWM_forceEventTriggerInterrupt EPWM_forceEventTriggerInterrupt + +// +// ADC SOC configuration related APIs +// +#define HRPWM_enableADCTrigger EPWM_enableADCTrigger +#define HRPWM_disableADCTrigger EPWM_disableADCTrigger +#define HRPWM_setADCTriggerSource EPWM_setADCTriggerSource +#define HRPWM_setADCTriggerEventPrescale EPWM_setADCTriggerEventPrescale +#define HRPWM_getADCTriggerFlagStatus EPWM_getADCTriggerFlagStatus +#define HRPWM_clearADCTriggerFlag EPWM_clearADCTriggerFlag +#define HRPWM_enableADCTriggerEventCountInit \ + EPWM_enableADCTriggerEventCountInit +#define HRPWM_disableADCTriggerEventCountInit \ + EPWM_disableADCTriggerEventCountInit +#define HRPWM_forceADCTriggerEventCountInit \ + EPWM_forceADCTriggerEventCountInit +#define HRPWM_setADCTriggerEventCountInitValue \ + EPWM_setADCTriggerEventCountInitValue +#define HRPWM_getADCTriggerEventCount EPWM_getADCTriggerEventCount +#define HRPWM_forceADCTrigger EPWM_forceADCTrigger + +// +// Digital Compare Module related APIs +// +#define HRPWM_selectDigitalCompareTripInput \ + EPWM_selectDigitalCompareTripInput +#define HRPWM_enableDigitalCompareBlankingWindow \ + EPWM_enableDigitalCompareBlankingWindow +#define HRPWM_disableDigitalCompareBlankingWindow \ + EPWM_disableDigitalCompareBlankingWindow +#define HRPWM_enableDigitalCompareWindowInverseMode \ + EPWM_enableDigitalCompareWindowInverseMode +#define HRPWM_disableDigitalCompareWindowInverseMode \ + EPWM_disableDigitalCompareWindowInverseMode +#define HRPWM_setDigitalCompareBlankingEvent \ + EPWM_setDigitalCompareBlankingEvent +#define HRPWM_setDigitalCompareFilterInput \ + EPWM_setDigitalCompareFilterInput +#define HRPWM_setDigitalCompareWindowOffset \ + EPWM_setDigitalCompareWindowOffset +#define HRPWM_setDigitalCompareWindowLength \ + EPWM_setDigitalCompareWindowLength +#define HRPWM_getDigitalCompareBlankingWindowOffsetCount \ + EPWM_getDigitalCompareBlankingWindowOffsetCount +#define HRPWM_getDigitalCompareBlankingWindowLengthCount \ + EPWM_getDigitalCompareBlankingWindowLengthCount +#define HRPWM_setDigitalCompareEventSource \ + EPWM_setDigitalCompareEventSource +#define HRPWM_setDigitalCompareEventSyncMode \ + EPWM_setDigitalCompareEventSyncMode +#define HRPWM_enableDigitalCompareADCTrigger \ + EPWM_enableDigitalCompareADCTrigger +#define HRPWM_disableDigitalCompareADCTrigger \ + EPWM_disableDigitalCompareADCTrigger +#define HRPWM_enableDigitalCompareSyncEvent \ + EPWM_enableDigitalCompareSyncEvent +#define HRPWM_disableDigitalCompareSyncEvent \ + EPWM_disableDigitalCompareSyncEvent +#define HRPWM_enableDigitalCompareCounterCapture \ + EPWM_enableDigitalCompareCounterCapture +#define HRPWM_disableDigitalCompareCounterCapture \ + EPWM_disableDigitalCompareCounterCapture +#define HRPWM_setDigitalCompareCounterShadowMode \ + EPWM_setDigitalCompareCounterShadowMode +#define HRPWM_getDigitalCompareCaptureStatus \ + EPWM_getDigitalCompareCaptureStatus +#define HRPWM_getDigitalCompareCaptureCount \ + EPWM_getDigitalCompareCaptureCount +#define HRPWM_enableDigitalCompareTripCombinationInput \ + EPWM_enableDigitalCompareTripCombinationInput +#define HRPWM_disableDigitalCompareTripCombinationInput \ + EPWM_disableDigitalCompareTripCombinationInput + +// +// Valley switching related APIs +// +#define HRPWM_enableValleyCapture EPWM_enableValleyCapture +#define HRPWM_disableValleyCapture EPWM_disableValleyCapture +#define HRPWM_startValleyCapture EPWM_startValleyCapture +#define HRPWM_setValleyTriggerSource EPWM_setValleyTriggerSource +#define HRPWM_setValleyTriggerEdgeCounts EPWM_setValleyTriggerEdgeCounts +#define HRPWM_enableValleyHWDelay EPWM_enableValleyHWDelay +#define HRPWM_disableValleyHWDelay EPWM_disableValleyHWDelay +#define HRPWM_setValleySWDelayValue EPWM_setValleySWDelayValue +#define HRPWM_setValleyDelayDivider EPWM_setValleyDelayDivider +#define HRPWM_getValleyEdgeStatus EPWM_getValleyEdgeStatus +#define HRPWM_getValleyCount EPWM_getValleyCount +#define HRPWM_getValleyHWDelay EPWM_getValleyHWDelay + +// +// Global Load feature related APIs +// +#define HRPWM_enableGlobalLoad EPWM_enableGlobalLoad +#define HRPWM_disableGlobalLoad EPWM_disableGlobalLoad +#define HRPWM_setGlobalLoadTrigger EPWM_setGlobalLoadTrigger +#define HRPWM_setGlobalLoadEventPrescale EPWM_setGlobalLoadEventPrescale +#define HRPWM_getGlobalLoadEventCount EPWM_getGlobalLoadEventCount +#define HRPWM_disableGlobalLoadOneShotMode EPWM_disableGlobalLoadOneShotMode +#define HRPWM_enableGlobalLoadOneShotMode EPWM_enableGlobalLoadOneShotMode +#define HRPWM_setGlobalLoadOneShotLatch EPWM_setGlobalLoadOneShotLatch +#define HRPWM_forceGlobalLoadOneShotEvent EPWM_forceGlobalLoadOneShotEvent +#define HRPWM_enableGlobalLoadRegisters EPWM_enableGlobalLoadRegisters +#define HRPWM_disableGlobalLoadRegisters EPWM_disableGlobalLoadRegisters +#define HRPWM_setEmulationMode EPWM_setEmulationMode + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks HRPWM base address. +//! +//! \param base specifies the HRPWM module base address. +//! +//! This function determines if an HRPWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool HRPWM_isBaseValid(uint32_t base) +{ + return((base == EPWM1_BASE) || (base == EPWM2_BASE) || + (base == EPWM3_BASE) || (base == EPWM4_BASE) || + (base == EPWM5_BASE) || (base == EPWM6_BASE) || + (base == EPWM7_BASE) || (base == EPWM8_BASE)); +} +#endif +//***************************************************************************** +// +//! Sets the consolidated phase shift value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the consolidated phase shift count value. +//! +//! This function sets the consolidated phase shift value, that is, both TBPHS +//! and TBPHSHR values are configured together. +//! +//! Call EPWM_enablePhaseShiftLoad & HRPWM_enableHRPhaseShiftLoad() functions +//! to enable loading of the phaseCount in high resolution mode. +//! +//! \b Note: phaseCount is a 24-bit value. +//! \b Note: For configuring TBPHS = 0x3C, TBPHSHR = 0x2; +//! phaseCount = 0x3C02 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(phaseCount < 0x1000000U); + + // + // Write to TBPHS:TBPHSHR bits + // + HWREG(base + HRPWM_O_TBPHS) = phaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution phase shift value. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPhaseCount is the high resolution phase shift count value. +//! +//! This function sets only the high resolution phase shift(TBPHSHR) value. +//! Call the HRPWM_enableHRPhaseShiftLoad() function to enable loading of +//! the hrPhaseCount. +//! +//! \b Note: hrPhaseCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResPhaseShiftOnly(uint32_t base, uint16_t hrPhaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPhaseCount < 256U); + + // + // Write to TBPHSHR bits + // + HWREGH(base + HRPWM_O_TBPHS) = hrPhaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets the consolidated period of time base counter used in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is the consolidated period count value. +//! +//! This function sets the consolidated period of time base counter value +//! (TBPRD:TBPRDHR) required in high resolution mode. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct periodCount. +//! +//! \b Note: periodCount is a 24 bit value. +//! \b Note: For configuring TBPRD = 0x3C, TBPRDHR = 0xA; +//! periodCount = 0x3C0A +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(periodCount < 0x1000000U); + + // + // Write to TBPRD:TBPRDHR bits + // + HWREG(base + HRPWM_O_TBPRDHR) = periodCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution time base counter. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPeriodCount is the high resolution period count value. +//! +//! This function sets only the high resolution time base counter(TBPRDHR) +//! value. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct hrPeriodCount. +//! +//! \b Note: hrPeriodCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResTimeBasePeriodOnly(uint32_t base, uint16_t hrPeriodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPeriodCount < 256U); + + // + // Write to TBPRDHR bits + // + HWREGH(base + HRPWM_O_TBPRDHR) = hrPeriodCount << 8U; +} + +//***************************************************************************** +// +//! Gets the consolidated time base period count used in HR mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the consolidated time base period(TBPRD:TBPRDHR) value +//! used in high resolution mode. +//! +//! \return The consolidated time base period count value. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRD:TBPRDHR bit + // + return(HWREG(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Gets the only the high resolution time base period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets only the high resolution time base period(TBPRDHR) value. +//! +//! \return The high resolution time base period count value. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResTimeBasePeriodOnly(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRDHR bit + // + return(HWREGH(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Sets the high resolution edge controlled by MEP (Micro Edge Positioner). +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge +//! Positioner). +//! +//! This function sets the edge of the PWM that is controlled by MEP (Micro +//! Edge Positioner). Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepEdgeMode +//! - HRPWM_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_MEP_CTRL_RISING_EDGE - MEP (Micro Edge Positioner) +//! controls rising edge. +//! - HRPWM_MEP_CTRL_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls falling edge. +//! - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls both edges. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPEdgeMode mepEdgeMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << (uint16_t)channel )) | + ((uint16_t)mepEdgeMode << (uint16_t)channel)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the MEP (Micro Edge Positioner) control mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the mode (register type) the MEP (Micro Edge Positioner) +//! will control. Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepCtrlMode +//! - HRPWM_MEP_DUTY_PERIOD_CTRL - MEP (Micro Edge Positioner) is +//! controlled by value of CMPAHR/ +//! CMPBHR(depending on the value of +//! channel) or TBPRDHR. +//! - HRPWM_MEP_PHASE_CTRL - MEP (Micro Edge Positioner) is +//! controlled by TBPHSHR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPCtrlMode mepCtrlMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the MEP control + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x1U << ((uint16_t)channel + 2U))) | + ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution comparator load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param loadEvent is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the shadow load mode of the high resolution comparator. +//! The function sets the COMPA or COMPB register depending on the channel +//! variable. +//! Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - loadEvent +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the CMPAHR or CMPBHR load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << ((uint16_t)channel + 3U))) | + ((uint16_t)loadEvent << ((uint16_t)channel + 3U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableOutputSwap is the output swap flag. +//! +//! This function sets the HRPWM output swap mode. If enableOutputSwap is true, +//! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA +//! output. If it is false ePWMxA and ePWMxB outputs are unchanged. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set output swap mode + // + EALLOW; + if(enableOutputSwap) + { + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_SWAPAB; + } + else + { + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_SWAPAB; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output on ePWMxB +//! +//! \param base is the base address of the EPWM module. +//! \param outputOnB is the output signal on ePWMxB. +//! +//! This function sets the HRPWM output signal on ePWMxB. If outputOnB is +//! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of +//! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is +//! ePWMxB. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the output on ePWM B + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(HRPWM_HRCNFG_SELOUTB)) | + ((uint16_t)outputOnB << 5U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables MEP (Micro Edge Positioner) automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the MEP (Micro Edge Positioner) to automatically +//! scale HRMSTEP. +//! +//! The SFO library will calculate required MEP steps per coarse steps and +//! feed it to HRMSTEP register. The MEP calibration module will use the value +//! in HRMSTEP to determine appropriate number of MEP steps represented by +//! fractional duty cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Enable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Disables MEP automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the MEP (Micro Edge Positioner) from automatically +//! scaling HRMSTEP. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Disable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of high resolution phase shift value which is +//! set by the function HRPWM_setPhaseShift(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of high resolution phase shift value. +//! +//! \return +// +//***************************************************************************** +static inline void +HRPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution PWMSYNC source. +//! +//! \param base is the base address of the EPWM module. +//! \param syncPulseSource is the PWMSYNC source. +//! +//! This function sets the high resolution PWMSYNC pulse source. +//! Valid values for syncPulseSource are: +//! - HRPWM_PWMSYNC_SOURCE_PERIOD - Counter equals Period. +//! - HRPWM_PWMSYNC_SOURCE_ZERO - Counter equals zero. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_UP - Counter equals COMPC when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN - Counter equals COMPC when +//! counting down. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_UP - Counter equals COMPD when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN - Counter equals COMPD when +//! counting down. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource) +{ + // + // Set the PWMSYNC source + // + EALLOW; + + // + // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD + // or HRPWM_PWMSYNC_SOURCE_ZERO + // + if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP) + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & + ~(HRPWM_HRPCTL_PWMSYNCSELX_M | HRPWM_HRPCTL_PWMSYNCSEL)) | + ((uint16_t)syncPulseSource << 1U)); + } + else + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & ~HRPWM_HRPCTL_PWMSYNCSELX_M) | + ((uint16_t)syncPulseSource << HRPWM_HRPCTL_PWMSYNCSELX_S)); + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the Translator Remainder value. +//! +//! \param base is the base address of the EPWM module. +//! \param trremVal is the translator remainder value. +//! +//! This function sets the Translator Remainder value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(trremVal < 2048U); + + // + // Set Translator Remainder value + // + EALLOW; + HWREGH(base + HRPWM_O_TRREM) = (trremVal & HRPWM_TRREM_TRREM_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the consolidated counter compare values in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param compCount is the consolidated counter compare count value. +//! +//! This function sets the consolidated counter compare(CMPx:CMPxHR) value +//! required in high resolution mode for counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: compCount is a 24 bit value. +//! \b Note: For configuring CMPA = 0xB4, CMPAHR = 0x64; value of +//! compCount = 0xB464 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint32_t compCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(compCount < 0x1000000U); + + // + // Write to counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPA:CMPAHR + // + HWREG(base + HRPWM_O_CMPA) = compCount << 8U; + } + else + { + // + // Write to CMPB:CMPBHR + // + HWREG(base + HRPWM_O_CMPB) = compCount << 8U; + } +} + +//***************************************************************************** +// +//! Sets only the high resolution counter compare value. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param hrCompCount is the high resolution counter compare count value. +//! +//! This function sets the high resolution counter compare value(CMPxHR) for +//! counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: hrCompCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint16_t hrCompCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrCompCount < 256U); + + // + // Write to the high resolution counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPAHR + // + HWREGH(base + HRPWM_O_CMPA) = hrCompCount << 8U; + } + else + { + // + // Write to CMPBHR + // + HWREGH(base + HRPWM_O_CMPB) = hrCompCount << 8U; + } +} + +//***************************************************************************** +// +//! Gets the consolidated counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets the consolidated counter compare(CMPx:CMPxHR) value +//! used in high resolution for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! +//! \return None. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint32_t compCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + compCount = HWREG(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + compCount = HWREG(base + HRPWM_O_CMPB) >> 8U; + } + return(compCount); +} + +//***************************************************************************** +// +//! Gets only the high resolution counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets only the high resolution counter compare(CMPxHR) value +//! for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint16_t hrCompCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPB) >> 8U; + } + return(hrCompCount); +} + +//***************************************************************************** +// +//! Sets the consolidated RED count in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the high resolution RED count. +//! +//! This function sets the consolidated RED (Rising Edge Delay) count +//! (DBRED:DBREDHR) value used in high resolution mode. The value of +//! redCount should be less than 0x200000. +//! +//! \b Note: redCount is a 21 bit value. +//! \b Note: For configuring DBRED = 0x4, DBREDHR = 0x1; value of +//! redCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(redCount < 0x200000U); + + // + // Set the consolidated RED (Rising Edge Delay) count + // + HWREG(base + HRPWM_O_DBREDHR) = redCount << 9U; +} + +//***************************************************************************** +// +//! Sets the high resolution RED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrRedCount is the high resolution RED count. +//! +//! This function sets only the high resolution RED (Rising Edge Delay) +//! count(DBREDHR) value. +//! The value of hrRedCount should be less than 128. +//! +//! \b Note: hrRedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResRisingEdgeDelayOnly(uint32_t base, uint16_t hrRedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrRedCount < 128U); + + // + // Set the High Resolution RED (Rising Edge Delay) count only + // + HWREGH(base + HRPWM_O_DBREDHR) = hrRedCount << 9U; +} + +//***************************************************************************** +// +//! Sets the consolidated FED value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the high resolution FED count. +//! +//! This function sets the consolidated FED (Falling Edge Delay) count +//! (DBFED: DBFEDHR) value used in high resolution mode. The value of fedCount +//! should be less than 0x200000. +//! +//! \b Note: fedCount is a 21 bit value. +//! \b Note: For configuring DBFED = 0x4, DBFEDHR = 0x1; value of +//! fedCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(fedCount < 0x200000U); + + // + // Set the High Resolution FED (Falling Edge Delay) count + // + HWREG(base + HRPWM_O_DBFEDHR) = fedCount << 9U; +} + +//***************************************************************************** +// +//! Sets high resolution FED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrFedCount is the high resolution FED count. +//! +//! This function sets only the high resolution FED (Falling Edge Delay) count +//! (DBFEDHR)value. The value of hrFedCount should be less than 128. +//! +//! \b Note: hrFedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrFedCount < 128U); + + // + // Set the high resolution FED (Falling Edge Delay) count + // + HWREGH(base + HRPWM_O_DBFEDHR) = hrFedCount << 9U; +} + +//***************************************************************************** +// +//! Set high resolution MEP (Micro Edge Positioner) step. +//! +//! \param base is the base address of the EPWM module. +//! \param mepCount is the high resolution MEP (Micro Edge Positioner) step +//! count. +//! +//! This function sets the high resolution MEP (Micro Edge Positioner) step +//! count. The maximum value for the MEP count step is 255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPStep(uint32_t base, uint16_t mepCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(mepCount < 256U); + + // + // Set HRPWM MEP count + // + EALLOW; + HWREGH(base + HRPWM_O_HRMSTEP) = + ((HWREGH(base + HRPWM_O_HRMSTEP) & ~HRPWM_HRMSTEP_HRMSTEP_M) | + mepCount); + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution Dead Band MEP (Micro Edge Positioner) control. +//! +//! \param base is the base address of the EPWM module. +//! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control +//! edge. +//! +//! This function sets the high resolution Dead Band edge that the MEP (Micro +//! Edge Positioner) controls Valid values for mepDBEdge are: +//! - HRPWM_DB_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_DB_MEP_CTRL_RED - MEP (Micro Edge Positioner) controls +//! Rising Edge Delay +//! - HRPWM_DB_MEP_CTRL_FED - MEP (Micro Edge Positioner) controls +//! Falling Edge Delay +//! - HRPWM_DB_MEP_CTRL_RED_FED - MEP (Micro Edge Positioner) controls both +//! Falling and Rising edge delays +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, + HRPWM_MEPDeadBandEdgeMode mepDBEdge) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM DB edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_EDGMODEDB_M) | + ((uint16_t)mepDBEdge)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band RED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Rising Edge Delay(RED)Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM RED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBRED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBRED_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band FED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Falling Edge Delay(FED) Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM FED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBFED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBFED_S)); + EDIS; +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // HRPWM_H + diff --git a/gpio_driverlib_cpu2/device/driverlib/hw_reg_inclusive_terminology.h b/gpio_driverlib_cpu2/device/driverlib/hw_reg_inclusive_terminology.h new file mode 100644 index 0000000..d3dc018 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/hw_reg_inclusive_terminology.h @@ -0,0 +1,29 @@ +#ifndef HW_REG_INCLUSIVE_TERMINOLOGY_H +#define HW_REG_INCLUSIVE_TERMINOLOGY_H + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_CTL_CONTROLLER_PERIPHERAL SPI_CTL_MASTER_SLAVE +#define SPI_PRI_PTEINV SPI_PRI_STEINV + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_O_TAR I2C_O_SAR + +#define I2C_TAR_TAR_S I2C_SAR_SAR_S +#define I2C_TAR_TAR_M I2C_SAR_SAR_M + +#define I2C_IER_AAT I2C_IER_AAS + +#define I2C_STR_AAT I2C_STR_AAS +#define I2C_STR_TDIR I2C_STR_SDIR + +#define I2C_MDR_CNT I2C_MDR_MST + + + +#endif // HW_REG_INCLUSIVE_TERMINOLOGY_H diff --git a/gpio_driverlib_cpu2/device/driverlib/i2c.c b/gpio_driverlib_cpu2/device/driverlib/i2c.c new file mode 100644 index 0000000..692f7a2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/i2c.c @@ -0,0 +1,351 @@ +//########################################################################### +// +// FILE: i2c.c +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "i2c.h" + +//***************************************************************************** +// +// I2C_initController +// +//***************************************************************************** +void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((10000000U / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (10000000U / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_initControllerModuleFrequency +// +//***************************************************************************** +void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((moduleFrequency / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (moduleFrequency / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_enableInterrupt +// +//***************************************************************************** +void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the desired basic interrupts + // + HWREGH(base + I2C_O_IER) |= (intFlags & 0xFFFFU); + + // + // Enabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) |= I2C_IER_AAT; + } + + // + // Enable desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFIENA; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// I2C_disableInterrupt +// +//***************************************************************************** +void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the desired basic interrupts. + // + HWREGH(base + I2C_O_IER) &= ~(intFlags & 0xFFFFU); + + // + // Disabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) &= ~I2C_IER_AAT; + } + + // + // Disable the desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_TXFFIENA); + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) &= ~(I2C_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// I2C_getInterruptStatus +// +//***************************************************************************** +uint32_t +I2C_getInterruptStatus(uint32_t base) +{ + uint32_t temp; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return only the status bits associated with interrupts. + // + temp = (uint32_t)HWREGH(base + I2C_O_STR) & (uint32_t)I2C_STR_INTMASK; + + // + // Read FIFO interrupt flags. + // + if((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFINT) != 0U) + { + temp |= I2C_INT_TXFF; + } + + if((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFINT) != 0U) + { + temp |= I2C_INT_RXFF; + } + + return(temp); +} + +//***************************************************************************** +// +// I2C_clearInterruptStatus +// +//***************************************************************************** +void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the interrupt flags that are located in STR. + // + HWREGH(base + I2C_O_STR) = ((uint16_t)intFlags & I2C_STR_INTMASK); + + // + // Clear the FIFO interrupt flags if needed. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFINTCLR; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFINTCLR; + } +} +//***************************************************************************** +// +// I2C_configureModuleFrequency +// +//***************************************************************************** +void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} +//***************************************************************************** +// +// I2C_configureModuleClockFrequency +// +//***************************************************************************** +void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} diff --git a/gpio_driverlib_cpu2/device/driverlib/i2c.h b/gpio_driverlib_cpu2/device/driverlib/i2c.h new file mode 100644 index 0000000..634c4c8 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/i2c.h @@ -0,0 +1,1386 @@ +//########################################################################### +// +// FILE: i2c.h +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef I2C_H +#define I2C_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup i2c_api I2C +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2c.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// I2C Controller commands. +// +//***************************************************************************** +#define I2C_CONTROLLER_SEND_MODE 0x0600U //!< Controller-transmitter mode +#define I2C_CONTROLLER_RECEIVE_MODE 0x0400U //!< Controller-receiver mode +#define I2C_TARGET_SEND_MODE 0x0200U //!< Target-transmitter mode +#define I2C_TARGET_RECEIVE_MODE 0x0000U //!< Target-receiver mode + +#define I2C_REPEAT_MODE 0x0080U //!< Only applies to Controller mode +#define I2C_START_BYTE_MODE 0x0010U //!< Enable start byte mode +#define I2C_FREE_DATA_FORMAT 0x0008U //!< Enable free data (no addr) format + +//***************************************************************************** +// +// I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(), +// I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by +// I2C_getInterruptStatus(). +// +//***************************************************************************** +#define I2C_INT_ARB_LOST 0x00001U //!< Arbitration-lost interrupt +#define I2C_INT_NO_ACK 0x00002U //!< NACK interrupt +#define I2C_INT_REG_ACCESS_RDY 0x00004U //!< Register-access-ready interrupt +#define I2C_INT_RX_DATA_RDY 0x00008U //!< Receive-data-ready interrupt +#define I2C_INT_TX_DATA_RDY 0x00010U //!< Transmit-data-ready interrupt +#define I2C_INT_STOP_CONDITION 0x00020U //!< Stop condition detected +#define I2C_INT_ADDR_TARGET 0x00200U //!< Addressed as target interrupt +#define I2C_INT_RXFF 0x10000U //!< RX FIFO level interrupt +#define I2C_INT_TXFF 0x20000U //!< TX FIFO level interrupt + + +// +// Helpful define to mask out the bits in the I2CSTR register that aren't +// associated with interrupts. +// +#define I2C_STR_INTMASK ((uint16_t)I2C_INT_ARB_LOST | \ + (uint16_t)I2C_INT_NO_ACK | \ + (uint16_t)I2C_INT_REG_ACCESS_RDY | \ + (uint16_t)I2C_INT_RX_DATA_RDY | \ + (uint16_t)I2C_INT_TX_DATA_RDY | \ + (uint16_t)I2C_INT_STOP_CONDITION | \ + (uint16_t)I2C_INT_ADDR_TARGET) + + + + +//***************************************************************************** +// +// Flags for use as the stsFlags parameter of I2C_clearStatus() and to be +// returned by I2C_getStatus(). +// +//***************************************************************************** +#define I2C_STS_ARB_LOST 0x0001U //!< Arbitration-lost +#define I2C_STS_NO_ACK 0x0002U //!< No-acknowledgment (NACK) +#define I2C_STS_REG_ACCESS_RDY 0x0004U //!< Register-access-ready (ARDY) +#define I2C_STS_RX_DATA_RDY 0x0008U //!< Receive-data-ready +#define I2C_STS_TX_DATA_RDY 0x0010U //!< Transmit-data-ready +#define I2C_STS_STOP_CONDITION 0x0020U //!< Stop condition detected +#define I2C_STS_ADDR_ZERO 0x0100U //!< Address of all zeros detected +#define I2C_STS_ADDR_TARGET 0x0200U //!< Addressed as target +#define I2C_STS_TX_EMPTY 0x0400U //!< Transmit shift register empty +#define I2C_STS_RX_FULL 0x0800U //!< Receive shift register full +#define I2C_STS_BUS_BUSY 0x1000U //!< Bus busy, wait for STOP or reset +#define I2C_STS_NACK_SENT 0x2000U //!< NACK was sent +#define I2C_STS_TARGET_DIR 0x4000U //!< Addressed as target transmitter + +#endif + + +//***************************************************************************** +// +//! I2C interrupts to be returned by I2C_getInterruptSource(). +// +//***************************************************************************** +typedef enum +{ + I2C_INTSRC_NONE, //!< No interrupt pending + I2C_INTSRC_ARB_LOST, //!< Arbitration-lost interrupt + I2C_INTSRC_NO_ACK, //!< NACK interrupt + I2C_INTSRC_REG_ACCESS_RDY, //!< Register-access-ready interrupt + I2C_INTSRC_RX_DATA_RDY, //!< Receive-data-ready interrupt + I2C_INTSRC_TX_DATA_RDY, //!< Transmit-data-ready interrupt + I2C_INTSRC_STOP_CONDITION, //!< Stop condition detected + I2C_INTSRC_ADDR_TARGET, //!< Addressed as target interrupt +} I2C_InterruptSource; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by I2C_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + I2C_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + I2C_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + I2C_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + I2C_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + I2C_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + I2C_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + I2C_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + I2C_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + I2C_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + I2C_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + I2C_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + I2C_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + I2C_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + I2C_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + I2C_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + I2C_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} I2C_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by I2C_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + I2C_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + I2C_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + I2C_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + I2C_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + I2C_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + I2C_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + I2C_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + I2C_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + I2C_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + I2C_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + I2C_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + I2C_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + I2C_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + I2C_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + I2C_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + I2C_FIFO_RXFULL = 0x0010U //!< Receive FIFO full +} I2C_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setBitCount() as the \e size parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_BITCOUNT_1 = 1U, //!< 1 bit per data byte + I2C_BITCOUNT_2 = 2U, //!< 2 bits per data byte + I2C_BITCOUNT_3 = 3U, //!< 3 bits per data byte + I2C_BITCOUNT_4 = 4U, //!< 4 bits per data byte + I2C_BITCOUNT_5 = 5U, //!< 5 bits per data byte + I2C_BITCOUNT_6 = 6U, //!< 6 bits per data byte + I2C_BITCOUNT_7 = 7U, //!< 7 bits per data byte + I2C_BITCOUNT_8 = 0U //!< 8 bits per data byte +} I2C_BitCount; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setAddressMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_ADDR_MODE_7BITS = 0x0000U, //!< 7-bit address + I2C_ADDR_MODE_10BITS = 0x0100U //!< 10-bit address +} I2C_AddressMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! If SCL is low, keep it low. If high, stop when it goes low again. + I2C_EMULATION_STOP_SCL_LOW = 0x0000U, + //! Continue I2C operation regardless + I2C_EMULATION_FREE_RUN = 0x4000U +} I2C_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_initController() as the \e dutyCycle +//! parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_DUTYCYCLE_33, //!< Clock duty cycle is 33% + I2C_DUTYCYCLE_50 //!< Clock duty cycle is 55% +} I2C_DutyCycle; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an I2C base address. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function determines if a I2C module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +I2C_isBaseValid(uint32_t base) +{ + return( + (base == I2CA_BASE) || + (base == I2CB_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) |= I2C_MDR_IRS; +} + +//***************************************************************************** +// +//! Disables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) &= ~(I2C_MDR_IRS); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions enables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST; + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions disables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST); + HWREGH(base + I2C_O_FFRX) &= ~I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or +//! \b I2C_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or +//! \b I2C_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel, + I2C_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + I2C_O_FFTX) = (HWREGH(base + I2C_O_FFTX) & + (~I2C_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + I2C_O_FFRX) = (HWREGH(base + I2C_O_FFRX) & + (~I2C_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, +//! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, +//! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel, + I2C_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (I2C_TxFIFOLevel)(HWREGH(base + I2C_O_FFTX) & + I2C_FFTX_TXFFIL_M); + *rxLevel = (I2C_RxFIFOLevel)(HWREGH(base + I2C_O_FFRX) & + I2C_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3, +//! ..., or \b I2C_FIFO_TX16 +// +//***************************************************************************** +static inline I2C_TxFIFOLevel +I2C_getTxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFST_M) >> + I2C_FFTX_TXFFST_S); + + return((I2C_TxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3, +//! ..., or \b I2C_FIFO_RX16 +// +//***************************************************************************** +static inline I2C_RxFIFOLevel +I2C_getRxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFST_M) >> + I2C_FFRX_RXFFST_S); + + return((I2C_RxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Reads I2C Module clock prescaler value. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads the I2C prescaler value which configures the I2C module +//! clock by dividing down the SYSCLK. I2C_MODULE_CLK = SYSCLK / (I2CPSC + ) +//! +//! \return Returns the I2C prescaler(I2CPSC) cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getPreScaler(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the Prescaler register. + // + return(HWREGH(base + I2C_O_PSC)); +} + +//***************************************************************************** +// +//! Sets the address that the I2C Controller places on the bus. +//! +//! \param base is the base address of the I2C instance used. +//! \param targetAddr 7-bit or 10-bit target address +//! +//! This function configures the address that the I2C Controller places on the bus +//! when initiating a transaction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setTargetAddress(uint32_t base, uint16_t targetAddr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(targetAddr <= I2C_TAR_TAR_M); + + HWREGH(base + I2C_O_TAR) = targetAddr; +} + +//***************************************************************************** +// +//! Sets the own address for this I2C module. +//! +//! \param base is the base address of the I2C Target module. +//! \param Addr is the 7-bit or 10-bit address +//! +//! This function writes the specified address. +//! +//! The parameter \e Addr is the value that is compared against the +//! target address sent by an I2C controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setOwnAddress(uint32_t base, uint16_t Addr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(Addr <= I2C_OAR_OAR_M); + + HWREGH(base + I2C_O_OAR) = Addr; +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-controller environment to determine if the +//! bus is free for another data transfer. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +static inline bool +I2C_isBusBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + return((HWREGH(base + I2C_O_STR) & I2C_STR_BB) == I2C_STR_BB); +} + +//***************************************************************************** +// +//! Gets the current I2C module status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the status for the I2C module. +//! +//! \return The current module status, enumerated as a bit field of +//! - \b I2C_STS_ARB_LOST - Arbitration-lost +//! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK) +//! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY) +//! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready +//! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready +//! - \b I2C_STS_STOP_CONDITION - Stop condition detected +//! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected +//! - \b I2C_STS_ADDR_TARGET - Addressed as Target +//! - \b I2C_STS_TX_EMPTY - Transmit shift register empty +//! - \b I2C_STS_RX_FULL - Receive shift register full +//! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset +//! - \b I2C_STS_NACK_SENT - NACK was sent +//! - \b I2C_STS_TARGET_DIR- Addressed as Target transmitter +// +//***************************************************************************** +static inline uint16_t +I2C_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return contents of the status register + // + return(HWREGH(base + I2C_O_STR)); +} + +//***************************************************************************** +// +//! Clears I2C status flags. +//! +//! \param base is the base address of the I2C instance used. +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! +//! This function clears the specified I2C status flags. The \e stsFlags +//! parameter is the logical OR of the following values: +//! - \b I2C_STS_ARB_LOST +//! - \b I2C_STS_NO_ACK, +//! - \b I2C_STS_REG_ACCESS_RDY +//! - \b I2C_STS_RX_DATA_RDY +//! - \b I2C_STS_STOP_CONDITION +//! - \b I2C_STS_NACK_SENT +//! - \b I2C_STS_TARGET_DIR +//! +//! \note Note that some of the status flags returned by I2C_getStatus() cannot +//! be cleared by this function. Some may only be cleared by hardware or a +//! reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_clearStatus(uint32_t base, uint16_t stsFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write to the status registers to clear them. + // + HWREGH(base + I2C_O_STR) = stsFlags; +} + +//***************************************************************************** +// +//! Controls the state of the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param config is the command to be issued to the I2C module. +//! +//! This function is used to control the state of the controller and target send and +//! receive operations. The \e config is a logical OR of the following options. +//! +//! One of the following four options: +//! - \b I2C_CONTROLLER_SEND_MODE - Controller-transmitter mode +//! - \b I2C_CONTROLLER_RECEIVE_MODE - Controller-receiver mode +//! - \b I2C_TARGET_SEND_MODE - Target-transmitter mode +//! - \b I2C_TARGET_RECEIVE_MODE - Target-receiver mode +//! +//! Any of the following: +//! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count +//! - \b I2C_START_BYTE_MODE - Use start byte mode +//! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & + ~(I2C_MDR_CNT | I2C_MDR_TRX | I2C_MDR_RM | + I2C_MDR_STB | I2C_MDR_FDF)) | config; +} + +//***************************************************************************** +// +//! Sets the data byte bit count the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param size is the number of bits per data byte. +//! +//! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of +//! bits per data byte. The default and maximum size is 8 bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setBitCount(uint32_t base, I2C_BitCount size) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_BC_M) | + (uint16_t)size; +} + +//***************************************************************************** +// +//! Issues an I2C START condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a start condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStartCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the START condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STT; +} + +//***************************************************************************** +// +//! Issues an I2C STOP condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a stop condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! To check on the status of the STOP condition, I2C_getStopConditionStatus() +//! can be used. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStopCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the STOP condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STP; +} + +//***************************************************************************** +// +//! Issues a no-acknowledge (NACK) bit. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a NACK bit. This is only +//! applicable when the I2C module is acting as a receiver. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendNACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the NACK mode bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_NACKMOD; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads a byte of data from the I2C Data Receive Register. +//! +//! \return Returns the byte received from by the I2C cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the receive register. + // + return(HWREGH(base + I2C_O_DRR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! \param data is the data to be transmitted from the I2C Controller. +//! +//! This function places the supplied data into I2C Data Transmit Register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_putData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Place the data into the transmit register. + // + HWREGH(base + I2C_O_DXR) = data; +} + +//***************************************************************************** +// +//! Get stop condition status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads and returns the stop condition bit status. +//! +//! \return Returns \b true if the STP bit has been set by the device to +//! generate a stop condition when the internal data counter of the I2C module +//! has reached 0. Returns \b false when the STP bit is zero. This bit is +//! automatically cleared after the stop condition has been generated. +// +//***************************************************************************** +static inline bool +I2C_getStopConditionStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Check the stop condition bit and return appropriately. + // + return((HWREGH(base + I2C_O_MDR) & I2C_MDR_STP) != 0U); +} + +//***************************************************************************** +// +//! Set number of bytes to be to transfer or receive when repeat mode is off. +//! +//! \param base is the base address of the I2C instance used. +//! \param count is the value to be put in the I2C data count register. +//! +//! This function sets the number of bytes to transfer or receive when repeat +//! mode is off. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setDataCount(uint32_t base, uint16_t count) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the count value to the appropriate register. + // + HWREGH(base + I2C_O_CNT) = count; +} + +//***************************************************************************** +// +//! Sets the addressing mode to either 7-bit or 10-bit. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the address mode, 7-bit or 10-bit. +//! +//! This function configures the I2C module for either a 7-bit address +//! (default) or a 10-bit address. The \e mode parameter configures the address +//! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when +//! \b I2C_ADDR_MODE_7BITS. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setAddressMode(uint32_t base, I2C_AddressMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the appropriate value to the address expansion bit. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_XA) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Sets I2C emulation mode. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the I2C operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs, +//! the I2C module stops immediately. If SCL is high, the I2C module waits +//! until SCL becomes low and then stops. +//! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_FREE) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Enables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables loopback mode. This mode is only valid during controller +//! mode and is helpful during device testing as it causes data transmitted out +//! of the data transmit register to be received in data receive register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Disables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) &= ~I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Returns the current I2C interrupt source. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the event that generated an I2C basic (non-FIFO) +//! interrupt. The possible sources are the following: +//! - \b I2C_INTSRC_NONE +//! - \b I2C_INTSRC_ARB_LOST +//! - \b I2C_INTSRC_NO_ACK +//! - \b I2C_INTSRC_REG_ACCESS_RDY +//! - \b I2C_INTSRC_RX_DATA_RDY +//! - \b I2C_INTSRC_TX_DATA_RDY +//! - \b I2C_INTSRC_STOP_CONDITION +//! - \b I2C_INTSRC_ADDR_TARGET +//! +//! Calling this function will result in hardware automatically clearing the +//! current interrupt code and if ready, loading the next pending enabled +//! interrupt. It will also clear the corresponding interrupt flag if the +//! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or +//! \b I2C_INTSRC_STOP_CONDITION. +//! +//! \note Note that this function differs from I2C_getInterruptStatus() in that +//! it returns a single interrupt source. I2C_getInterruptSource() will return +//! the status of all interrupt flags possible, including the flags that aren't +//! necessarily enabled to generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline I2C_InterruptSource +I2C_getInterruptSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the interrupt source value + // + return((I2C_InterruptSource)(HWREGH(base + I2C_O_ISRC) & + I2C_ISRC_INTCODE_M)); +} + + + + + + + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle); + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! \param moduleFrequency is the module clock used by I2C module +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency); + +//***************************************************************************** +// +//! Enables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt +//! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt +//! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt +//! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt +//! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt +//! - \b I2C_INT_STOP_CONDITION - Stop condition detected +//! - \b I2C_INT_ADDR_TARGET - Addressed as target interrupt +//! - \b I2C_INT_RXFF - RX FIFO level interrupt +//! - \b I2C_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Target interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current I2C interrupt status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the interrupt status for the I2C module. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! - \b I2C_INT_ARB_LOST +//! - \b I2C_INT_NO_ACK +//! - \b I2C_INT_REG_ACCESS_RDY +//! - \b I2C_INT_RX_DATA_RDY +//! - \b I2C_INT_TX_DATA_RDY +//! - \b I2C_INT_STOP_CONDITION +//! - \b I2C_INT_ADDR_TARGET +//! - \b I2C_INT_RXFF +//! - \b I2C_INT_TXFF +//! +//! \note This function will only return the status flags associated with +//! interrupts. However, a flag may be set even if its corresponding interrupt +//! is disabled. +// +//***************************************************************************** +extern uint32_t +I2C_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \note Also note that some of the status flags returned by +//! I2C_getInterruptStatus() cannot be cleared by this function. Some may only +//! be cleared by hardware or a reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency with a given module clock +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param moduleFrequency is the rate of the module clock used by I2C module +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // I2C_H diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_adc.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_adc.h new file mode 100644 index 0000000..89bd529 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_adc.h @@ -0,0 +1,911 @@ +//########################################################################### +// +// FILE: hw_adc.h +// +// TITLE: Definitions for the ADC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ADC_H +#define HW_ADC_H + +//************************************************************************************************* +// +// The following are defines for the ADC register offsets +// +//************************************************************************************************* +#define ADC_O_CTL1 0x0U // ADC Control 1 Register +#define ADC_O_CTL2 0x1U // ADC Control 2 Register +#define ADC_O_BURSTCTL 0x2U // ADC Burst Control Register +#define ADC_O_INTFLG 0x3U // ADC Interrupt Flag Register +#define ADC_O_INTFLGCLR 0x4U // ADC Interrupt Flag Clear Register +#define ADC_O_INTOVF 0x5U // ADC Interrupt Overflow Register +#define ADC_O_INTOVFCLR 0x6U // ADC Interrupt Overflow Clear Register +#define ADC_O_INTSEL1N2 0x7U // ADC Interrupt 1 and 2 Selection Register +#define ADC_O_INTSEL3N4 0x8U // ADC Interrupt 3 and 4 Selection Register +#define ADC_O_SOCPRICTL 0x9U // ADC SOC Priority Control Register +#define ADC_O_INTSOCSEL1 0xAU // ADC Interrupt SOC Selection 1 Register +#define ADC_O_INTSOCSEL2 0xBU // ADC Interrupt SOC Selection 2 Register +#define ADC_O_SOCFLG1 0xCU // ADC SOC Flag 1 Register +#define ADC_O_SOCFRC1 0xDU // ADC SOC Force 1 Register +#define ADC_O_SOCOVF1 0xEU // ADC SOC Overflow 1 Register +#define ADC_O_SOCOVFCLR1 0xFU // ADC SOC Overflow Clear 1 Register +#define ADC_O_SOC0CTL 0x10U // ADC SOC0 Control Register +#define ADC_O_SOC1CTL 0x12U // ADC SOC1 Control Register +#define ADC_O_SOC2CTL 0x14U // ADC SOC2 Control Register +#define ADC_O_SOC3CTL 0x16U // ADC SOC3 Control Register +#define ADC_O_SOC4CTL 0x18U // ADC SOC4 Control Register +#define ADC_O_SOC5CTL 0x1AU // ADC SOC5 Control Register +#define ADC_O_SOC6CTL 0x1CU // ADC SOC6 Control Register +#define ADC_O_SOC7CTL 0x1EU // ADC SOC7 Control Register +#define ADC_O_SOC8CTL 0x20U // ADC SOC8 Control Register +#define ADC_O_SOC9CTL 0x22U // ADC SOC9 Control Register +#define ADC_O_SOC10CTL 0x24U // ADC SOC10 Control Register +#define ADC_O_SOC11CTL 0x26U // ADC SOC11 Control Register +#define ADC_O_SOC12CTL 0x28U // ADC SOC12 Control Register +#define ADC_O_SOC13CTL 0x2AU // ADC SOC13 Control Register +#define ADC_O_SOC14CTL 0x2CU // ADC SOC14 Control Register +#define ADC_O_SOC15CTL 0x2EU // ADC SOC15 Control Register +#define ADC_O_EVTSTAT 0x30U // ADC Event Status Register +#define ADC_O_EVTCLR 0x32U // ADC Event Clear Register +#define ADC_O_EVTSEL 0x34U // ADC Event Selection Register +#define ADC_O_EVTINTSEL 0x36U // ADC Event Interrupt Selection Register +#define ADC_O_OSDETECT 0x38U // ADC Open and Shorts Detect Register +#define ADC_O_COUNTER 0x39U // ADC Counter Register +#define ADC_O_REV 0x3AU // ADC Revision Register +#define ADC_O_OFFTRIM 0x3BU // ADC Offset Trim Register +#define ADC_O_PPB1CONFIG 0x40U // ADC PPB1 Config Register +#define ADC_O_PPB1STAMP 0x41U // ADC PPB1 Sample Delay Time Stamp Register +#define ADC_O_PPB1OFFCAL 0x42U // ADC PPB1 Offset Calibration Register +#define ADC_O_PPB1OFFREF 0x43U // ADC PPB1 Offset Reference Register +#define ADC_O_PPB1TRIPHI 0x44U // ADC PPB1 Trip High Register +#define ADC_O_PPB1TRIPLO 0x46U // ADC PPB1 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB2CONFIG 0x48U // ADC PPB2 Config Register +#define ADC_O_PPB2STAMP 0x49U // ADC PPB2 Sample Delay Time Stamp Register +#define ADC_O_PPB2OFFCAL 0x4AU // ADC PPB2 Offset Calibration Register +#define ADC_O_PPB2OFFREF 0x4BU // ADC PPB2 Offset Reference Register +#define ADC_O_PPB2TRIPHI 0x4CU // ADC PPB2 Trip High Register +#define ADC_O_PPB2TRIPLO 0x4EU // ADC PPB2 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB3CONFIG 0x50U // ADC PPB3 Config Register +#define ADC_O_PPB3STAMP 0x51U // ADC PPB3 Sample Delay Time Stamp Register +#define ADC_O_PPB3OFFCAL 0x52U // ADC PPB3 Offset Calibration Register +#define ADC_O_PPB3OFFREF 0x53U // ADC PPB3 Offset Reference Register +#define ADC_O_PPB3TRIPHI 0x54U // ADC PPB3 Trip High Register +#define ADC_O_PPB3TRIPLO 0x56U // ADC PPB3 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB4CONFIG 0x58U // ADC PPB4 Config Register +#define ADC_O_PPB4STAMP 0x59U // ADC PPB4 Sample Delay Time Stamp Register +#define ADC_O_PPB4OFFCAL 0x5AU // ADC PPB4 Offset Calibration Register +#define ADC_O_PPB4OFFREF 0x5BU // ADC PPB4 Offset Reference Register +#define ADC_O_PPB4TRIPHI 0x5CU // ADC PPB4 Trip High Register +#define ADC_O_PPB4TRIPLO 0x5EU // ADC PPB4 Trip Low/Trigger Time Stamp Register +#define ADC_O_INLTRIM1 0x70U // ADC Linearity Trim 1 Register +#define ADC_O_INLTRIM2 0x72U // ADC Linearity Trim 2 Register +#define ADC_O_INLTRIM3 0x74U // ADC Linearity Trim 3 Register +#define ADC_O_INLTRIM4 0x76U // ADC Linearity Trim 4 Register +#define ADC_O_INLTRIM5 0x78U // ADC Linearity Trim 5 Register +#define ADC_O_INLTRIM6 0x7AU // ADC Linearity Trim 6 Register + +#define ADC_O_RESULT0 0x0U // ADC Result 0 Register +#define ADC_O_RESULT1 0x1U // ADC Result 1 Register +#define ADC_O_RESULT2 0x2U // ADC Result 2 Register +#define ADC_O_RESULT3 0x3U // ADC Result 3 Register +#define ADC_O_RESULT4 0x4U // ADC Result 4 Register +#define ADC_O_RESULT5 0x5U // ADC Result 5 Register +#define ADC_O_RESULT6 0x6U // ADC Result 6 Register +#define ADC_O_RESULT7 0x7U // ADC Result 7 Register +#define ADC_O_RESULT8 0x8U // ADC Result 8 Register +#define ADC_O_RESULT9 0x9U // ADC Result 9 Register +#define ADC_O_RESULT10 0xAU // ADC Result 10 Register +#define ADC_O_RESULT11 0xBU // ADC Result 11 Register +#define ADC_O_RESULT12 0xCU // ADC Result 12 Register +#define ADC_O_RESULT13 0xDU // ADC Result 13 Register +#define ADC_O_RESULT14 0xEU // ADC Result 14 Register +#define ADC_O_RESULT15 0xFU // ADC Result 15 Register +#define ADC_O_PPB1RESULT 0x10U // ADC Post Processing Block 1 Result Register +#define ADC_O_PPB2RESULT 0x12U // ADC Post Processing Block 2 Result Register +#define ADC_O_PPB3RESULT 0x14U // ADC Post Processing Block 3 Result Register +#define ADC_O_PPB4RESULT 0x16U // ADC Post Processing Block 4 Result Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL1 register +// +//************************************************************************************************* +#define ADC_CTL1_INTPULSEPOS 0x4U // ADC Interrupt Pulse Position +#define ADC_CTL1_ADCPWDNZ 0x80U // ADC Power Down +#define ADC_CTL1_ADCBSYCHN_S 8U +#define ADC_CTL1_ADCBSYCHN_M 0xF00U // ADC Busy Channel +#define ADC_CTL1_ADCBSY 0x2000U // ADC Busy + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL2 register +// +//************************************************************************************************* +#define ADC_CTL2_PRESCALE_S 0U +#define ADC_CTL2_PRESCALE_M 0xFU // ADC Clock Prescaler +#define ADC_CTL2_RESOLUTION 0x40U // SOC Conversion Resolution +#define ADC_CTL2_SIGNALMODE 0x80U // SOC Signaling Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCBURSTCTL register +// +//************************************************************************************************* +#define ADC_BURSTCTL_BURSTTRIGSEL_S 0U +#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3FU // SOC Burst Trigger Source Select +#define ADC_BURSTCTL_BURSTSIZE_S 8U +#define ADC_BURSTCTL_BURSTSIZE_M 0xF00U // SOC Burst Size Select +#define ADC_BURSTCTL_BURSTEN 0x8000U // SOC Burst Mode Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLG register +// +//************************************************************************************************* +#define ADC_INTFLG_ADCINT1 0x1U // ADC Interrupt 1 Flag +#define ADC_INTFLG_ADCINT2 0x2U // ADC Interrupt 2 Flag +#define ADC_INTFLG_ADCINT3 0x4U // ADC Interrupt 3 Flag +#define ADC_INTFLG_ADCINT4 0x8U // ADC Interrupt 4 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLGCLR register +// +//************************************************************************************************* +#define ADC_INTFLGCLR_ADCINT1 0x1U // ADC Interrupt 1 Flag Clear +#define ADC_INTFLGCLR_ADCINT2 0x2U // ADC Interrupt 2 Flag Clear +#define ADC_INTFLGCLR_ADCINT3 0x4U // ADC Interrupt 3 Flag Clear +#define ADC_INTFLGCLR_ADCINT4 0x8U // ADC Interrupt 4 Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVF register +// +//************************************************************************************************* +#define ADC_INTOVF_ADCINT1 0x1U // ADC Interrupt 1 Overflow Flags +#define ADC_INTOVF_ADCINT2 0x2U // ADC Interrupt 2 Overflow Flags +#define ADC_INTOVF_ADCINT3 0x4U // ADC Interrupt 3 Overflow Flags +#define ADC_INTOVF_ADCINT4 0x8U // ADC Interrupt 4 Overflow Flags + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVFCLR register +// +//************************************************************************************************* +#define ADC_INTOVFCLR_ADCINT1 0x1U // ADC Interrupt 1 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT2 0x2U // ADC Interrupt 2 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT3 0x4U // ADC Interrupt 3 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT4 0x8U // ADC Interrupt 4 Overflow Clear Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL1N2 register +// +//************************************************************************************************* +#define ADC_INTSEL1N2_INT1SEL_S 0U +#define ADC_INTSEL1N2_INT1SEL_M 0xFU // ADCINT1 EOC Source Select +#define ADC_INTSEL1N2_INT1E 0x20U // ADCINT1 Interrupt Enable +#define ADC_INTSEL1N2_INT1CONT 0x40U // ADCINT1 Continue to Interrupt Mode +#define ADC_INTSEL1N2_INT2SEL_S 8U +#define ADC_INTSEL1N2_INT2SEL_M 0xF00U // ADCINT2 EOC Source Select +#define ADC_INTSEL1N2_INT2E 0x2000U // ADCINT2 Interrupt Enable +#define ADC_INTSEL1N2_INT2CONT 0x4000U // ADCINT2 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL3N4 register +// +//************************************************************************************************* +#define ADC_INTSEL3N4_INT3SEL_S 0U +#define ADC_INTSEL3N4_INT3SEL_M 0xFU // ADCINT3 EOC Source Select +#define ADC_INTSEL3N4_INT3E 0x20U // ADCINT3 Interrupt Enable +#define ADC_INTSEL3N4_INT3CONT 0x40U // ADCINT3 Continue to Interrupt Mode +#define ADC_INTSEL3N4_INT4SEL_S 8U +#define ADC_INTSEL3N4_INT4SEL_M 0xF00U // ADCINT4 EOC Source Select +#define ADC_INTSEL3N4_INT4E 0x2000U // ADCINT4 Interrupt Enable +#define ADC_INTSEL3N4_INT4CONT 0x4000U // ADCINT4 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCPRICTL register +// +//************************************************************************************************* +#define ADC_SOCPRICTL_SOCPRIORITY_S 0U +#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1FU // SOC Priority +#define ADC_SOCPRICTL_RRPOINTER_S 5U +#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0U // Round Robin Pointer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL1 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL1_SOC0_S 0U +#define ADC_INTSOCSEL1_SOC0_M 0x3U // SOC0 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC1_S 2U +#define ADC_INTSOCSEL1_SOC1_M 0xCU // SOC1 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC2_S 4U +#define ADC_INTSOCSEL1_SOC2_M 0x30U // SOC2 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC3_S 6U +#define ADC_INTSOCSEL1_SOC3_M 0xC0U // SOC3 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC4_S 8U +#define ADC_INTSOCSEL1_SOC4_M 0x300U // SOC4 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC5_S 10U +#define ADC_INTSOCSEL1_SOC5_M 0xC00U // SOC5 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC6_S 12U +#define ADC_INTSOCSEL1_SOC6_M 0x3000U // SOC6 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC7_S 14U +#define ADC_INTSOCSEL1_SOC7_M 0xC000U // SOC7 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL2 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL2_SOC8_S 0U +#define ADC_INTSOCSEL2_SOC8_M 0x3U // SOC8 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC9_S 2U +#define ADC_INTSOCSEL2_SOC9_M 0xCU // SOC9 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC10_S 4U +#define ADC_INTSOCSEL2_SOC10_M 0x30U // SOC10 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC11_S 6U +#define ADC_INTSOCSEL2_SOC11_M 0xC0U // SOC11 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC12_S 8U +#define ADC_INTSOCSEL2_SOC12_M 0x300U // SOC12 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC13_S 10U +#define ADC_INTSOCSEL2_SOC13_M 0xC00U // SOC13 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC14_S 12U +#define ADC_INTSOCSEL2_SOC14_M 0x3000U // SOC14 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC15_S 14U +#define ADC_INTSOCSEL2_SOC15_M 0xC000U // SOC15 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFLG1 register +// +//************************************************************************************************* +#define ADC_SOCFLG1_SOC0 0x1U // SOC0 Start of Conversion Flag +#define ADC_SOCFLG1_SOC1 0x2U // SOC1 Start of Conversion Flag +#define ADC_SOCFLG1_SOC2 0x4U // SOC2 Start of Conversion Flag +#define ADC_SOCFLG1_SOC3 0x8U // SOC3 Start of Conversion Flag +#define ADC_SOCFLG1_SOC4 0x10U // SOC4 Start of Conversion Flag +#define ADC_SOCFLG1_SOC5 0x20U // SOC5 Start of Conversion Flag +#define ADC_SOCFLG1_SOC6 0x40U // SOC6 Start of Conversion Flag +#define ADC_SOCFLG1_SOC7 0x80U // SOC7 Start of Conversion Flag +#define ADC_SOCFLG1_SOC8 0x100U // SOC8 Start of Conversion Flag +#define ADC_SOCFLG1_SOC9 0x200U // SOC9 Start of Conversion Flag +#define ADC_SOCFLG1_SOC10 0x400U // SOC10 Start of Conversion Flag +#define ADC_SOCFLG1_SOC11 0x800U // SOC11 Start of Conversion Flag +#define ADC_SOCFLG1_SOC12 0x1000U // SOC12 Start of Conversion Flag +#define ADC_SOCFLG1_SOC13 0x2000U // SOC13 Start of Conversion Flag +#define ADC_SOCFLG1_SOC14 0x4000U // SOC14 Start of Conversion Flag +#define ADC_SOCFLG1_SOC15 0x8000U // SOC15 Start of Conversion Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFRC1 register +// +//************************************************************************************************* +#define ADC_SOCFRC1_SOC0 0x1U // SOC0 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC1 0x2U // SOC1 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC2 0x4U // SOC2 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC3 0x8U // SOC3 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC4 0x10U // SOC4 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC5 0x20U // SOC5 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC6 0x40U // SOC6 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC7 0x80U // SOC7 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC8 0x100U // SOC8 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC9 0x200U // SOC9 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC10 0x400U // SOC10 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC11 0x800U // SOC11 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC12 0x1000U // SOC12 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC13 0x2000U // SOC13 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC14 0x4000U // SOC14 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC15 0x8000U // SOC15 Force Start of Conversion Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVF1 register +// +//************************************************************************************************* +#define ADC_SOCOVF1_SOC0 0x1U // SOC0 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC1 0x2U // SOC1 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC2 0x4U // SOC2 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC3 0x8U // SOC3 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC4 0x10U // SOC4 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC5 0x20U // SOC5 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC6 0x40U // SOC6 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC7 0x80U // SOC7 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC8 0x100U // SOC8 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC9 0x200U // SOC9 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC10 0x400U // SOC10 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC11 0x800U // SOC11 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC12 0x1000U // SOC12 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC13 0x2000U // SOC13 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC14 0x4000U // SOC14 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC15 0x8000U // SOC15 Start of Conversion Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVFCLR1 register +// +//************************************************************************************************* +#define ADC_SOCOVFCLR1_SOC0 0x1U // SOC0 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC1 0x2U // SOC1 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC2 0x4U // SOC2 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC3 0x8U // SOC3 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC4 0x10U // SOC4 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC5 0x20U // SOC5 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC6 0x40U // SOC6 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC7 0x80U // SOC7 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC8 0x100U // SOC8 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC9 0x200U // SOC9 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC10 0x400U // SOC10 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC11 0x800U // SOC11 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC12 0x1000U // SOC12 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC13 0x2000U // SOC13 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC14 0x4000U // SOC14 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC15 0x8000U // SOC15 Clear Start of Conversion Overflow Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC0CTL register +// +//************************************************************************************************* +#define ADC_SOC0CTL_ACQPS_S 0U +#define ADC_SOC0CTL_ACQPS_M 0x1FFU // SOC0 Acquisition Prescale +#define ADC_SOC0CTL_CHSEL_S 15U +#define ADC_SOC0CTL_CHSEL_M 0x78000U // SOC0 Channel Select +#define ADC_SOC0CTL_TRIGSEL_S 20U +#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000U // SOC0 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC1CTL register +// +//************************************************************************************************* +#define ADC_SOC1CTL_ACQPS_S 0U +#define ADC_SOC1CTL_ACQPS_M 0x1FFU // SOC1 Acquisition Prescale +#define ADC_SOC1CTL_CHSEL_S 15U +#define ADC_SOC1CTL_CHSEL_M 0x78000U // SOC1 Channel Select +#define ADC_SOC1CTL_TRIGSEL_S 20U +#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000U // SOC1 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC2CTL register +// +//************************************************************************************************* +#define ADC_SOC2CTL_ACQPS_S 0U +#define ADC_SOC2CTL_ACQPS_M 0x1FFU // SOC2 Acquisition Prescale +#define ADC_SOC2CTL_CHSEL_S 15U +#define ADC_SOC2CTL_CHSEL_M 0x78000U // SOC2 Channel Select +#define ADC_SOC2CTL_TRIGSEL_S 20U +#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000U // SOC2 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC3CTL register +// +//************************************************************************************************* +#define ADC_SOC3CTL_ACQPS_S 0U +#define ADC_SOC3CTL_ACQPS_M 0x1FFU // SOC3 Acquisition Prescale +#define ADC_SOC3CTL_CHSEL_S 15U +#define ADC_SOC3CTL_CHSEL_M 0x78000U // SOC3 Channel Select +#define ADC_SOC3CTL_TRIGSEL_S 20U +#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000U // SOC3 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC4CTL register +// +//************************************************************************************************* +#define ADC_SOC4CTL_ACQPS_S 0U +#define ADC_SOC4CTL_ACQPS_M 0x1FFU // SOC4 Acquisition Prescale +#define ADC_SOC4CTL_CHSEL_S 15U +#define ADC_SOC4CTL_CHSEL_M 0x78000U // SOC4 Channel Select +#define ADC_SOC4CTL_TRIGSEL_S 20U +#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000U // SOC4 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC5CTL register +// +//************************************************************************************************* +#define ADC_SOC5CTL_ACQPS_S 0U +#define ADC_SOC5CTL_ACQPS_M 0x1FFU // SOC5 Acquisition Prescale +#define ADC_SOC5CTL_CHSEL_S 15U +#define ADC_SOC5CTL_CHSEL_M 0x78000U // SOC5 Channel Select +#define ADC_SOC5CTL_TRIGSEL_S 20U +#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000U // SOC5 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC6CTL register +// +//************************************************************************************************* +#define ADC_SOC6CTL_ACQPS_S 0U +#define ADC_SOC6CTL_ACQPS_M 0x1FFU // SOC6 Acquisition Prescale +#define ADC_SOC6CTL_CHSEL_S 15U +#define ADC_SOC6CTL_CHSEL_M 0x78000U // SOC6 Channel Select +#define ADC_SOC6CTL_TRIGSEL_S 20U +#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000U // SOC6 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC7CTL register +// +//************************************************************************************************* +#define ADC_SOC7CTL_ACQPS_S 0U +#define ADC_SOC7CTL_ACQPS_M 0x1FFU // SOC7 Acquisition Prescale +#define ADC_SOC7CTL_CHSEL_S 15U +#define ADC_SOC7CTL_CHSEL_M 0x78000U // SOC7 Channel Select +#define ADC_SOC7CTL_TRIGSEL_S 20U +#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000U // SOC7 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC8CTL register +// +//************************************************************************************************* +#define ADC_SOC8CTL_ACQPS_S 0U +#define ADC_SOC8CTL_ACQPS_M 0x1FFU // SOC8 Acquisition Prescale +#define ADC_SOC8CTL_CHSEL_S 15U +#define ADC_SOC8CTL_CHSEL_M 0x78000U // SOC8 Channel Select +#define ADC_SOC8CTL_TRIGSEL_S 20U +#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000U // SOC8 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC9CTL register +// +//************************************************************************************************* +#define ADC_SOC9CTL_ACQPS_S 0U +#define ADC_SOC9CTL_ACQPS_M 0x1FFU // SOC9 Acquisition Prescale +#define ADC_SOC9CTL_CHSEL_S 15U +#define ADC_SOC9CTL_CHSEL_M 0x78000U // SOC9 Channel Select +#define ADC_SOC9CTL_TRIGSEL_S 20U +#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000U // SOC9 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC10CTL register +// +//************************************************************************************************* +#define ADC_SOC10CTL_ACQPS_S 0U +#define ADC_SOC10CTL_ACQPS_M 0x1FFU // SOC10 Acquisition Prescale +#define ADC_SOC10CTL_CHSEL_S 15U +#define ADC_SOC10CTL_CHSEL_M 0x78000U // SOC10 Channel Select +#define ADC_SOC10CTL_TRIGSEL_S 20U +#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000U // SOC10 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC11CTL register +// +//************************************************************************************************* +#define ADC_SOC11CTL_ACQPS_S 0U +#define ADC_SOC11CTL_ACQPS_M 0x1FFU // SOC11 Acquisition Prescale +#define ADC_SOC11CTL_CHSEL_S 15U +#define ADC_SOC11CTL_CHSEL_M 0x78000U // SOC11 Channel Select +#define ADC_SOC11CTL_TRIGSEL_S 20U +#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000U // SOC11 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC12CTL register +// +//************************************************************************************************* +#define ADC_SOC12CTL_ACQPS_S 0U +#define ADC_SOC12CTL_ACQPS_M 0x1FFU // SOC12 Acquisition Prescale +#define ADC_SOC12CTL_CHSEL_S 15U +#define ADC_SOC12CTL_CHSEL_M 0x78000U // SOC12 Channel Select +#define ADC_SOC12CTL_TRIGSEL_S 20U +#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000U // SOC12 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC13CTL register +// +//************************************************************************************************* +#define ADC_SOC13CTL_ACQPS_S 0U +#define ADC_SOC13CTL_ACQPS_M 0x1FFU // SOC13 Acquisition Prescale +#define ADC_SOC13CTL_CHSEL_S 15U +#define ADC_SOC13CTL_CHSEL_M 0x78000U // SOC13 Channel Select +#define ADC_SOC13CTL_TRIGSEL_S 20U +#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000U // SOC13 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC14CTL register +// +//************************************************************************************************* +#define ADC_SOC14CTL_ACQPS_S 0U +#define ADC_SOC14CTL_ACQPS_M 0x1FFU // SOC14 Acquisition Prescale +#define ADC_SOC14CTL_CHSEL_S 15U +#define ADC_SOC14CTL_CHSEL_M 0x78000U // SOC14 Channel Select +#define ADC_SOC14CTL_TRIGSEL_S 20U +#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000U // SOC14 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC15CTL register +// +//************************************************************************************************* +#define ADC_SOC15CTL_ACQPS_S 0U +#define ADC_SOC15CTL_ACQPS_M 0x1FFU // SOC15 Acquisition Prescale +#define ADC_SOC15CTL_CHSEL_S 15U +#define ADC_SOC15CTL_CHSEL_M 0x78000U // SOC15 Channel Select +#define ADC_SOC15CTL_TRIGSEL_S 20U +#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000U // SOC15 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSTAT register +// +//************************************************************************************************* +#define ADC_EVTSTAT_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Flag +#define ADC_EVTSTAT_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Flag +#define ADC_EVTSTAT_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Flag +#define ADC_EVTSTAT_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Flag +#define ADC_EVTSTAT_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Flag +#define ADC_EVTSTAT_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Flag +#define ADC_EVTSTAT_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Flag +#define ADC_EVTSTAT_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Flag +#define ADC_EVTSTAT_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Flag +#define ADC_EVTSTAT_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Flag +#define ADC_EVTSTAT_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Flag +#define ADC_EVTSTAT_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTCLR register +// +//************************************************************************************************* +#define ADC_EVTCLR_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Clear +#define ADC_EVTCLR_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Clear +#define ADC_EVTCLR_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Clear +#define ADC_EVTCLR_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Clear +#define ADC_EVTCLR_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Clear +#define ADC_EVTCLR_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Clear +#define ADC_EVTCLR_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Clear +#define ADC_EVTCLR_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Clear +#define ADC_EVTCLR_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Clear +#define ADC_EVTCLR_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Clear +#define ADC_EVTCLR_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Clear +#define ADC_EVTCLR_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSEL register +// +//************************************************************************************************* +#define ADC_EVTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Event Enable +#define ADC_EVTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Event Enable +#define ADC_EVTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Event Enable +#define ADC_EVTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Event Enable +#define ADC_EVTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Event Enable +#define ADC_EVTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Event Enable +#define ADC_EVTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Event Enable +#define ADC_EVTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Event Enable +#define ADC_EVTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Event Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTINTSEL register +// +//************************************************************************************************* +#define ADC_EVTINTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOSDETECT register +// +//************************************************************************************************* +#define ADC_OSDETECT_DETECTCFG_S 0U +#define ADC_OSDETECT_DETECTCFG_M 0x7U // ADC Opens and Shorts Detect Configuration + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCOUNTER register +// +//************************************************************************************************* +#define ADC_COUNTER_FREECOUNT_S 0U +#define ADC_COUNTER_FREECOUNT_M 0xFFFU // ADC Free Running Counter Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCREV register +// +//************************************************************************************************* +#define ADC_REV_TYPE_S 0U +#define ADC_REV_TYPE_M 0xFFU // ADC Type +#define ADC_REV_REV_S 8U +#define ADC_REV_REV_M 0xFF00U // ADC Revision + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOFFTRIM register +// +//************************************************************************************************* +#define ADC_OFFTRIM_OFFTRIM_S 0U +#define ADC_OFFTRIM_OFFTRIM_M 0xFFU // ADC Offset Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1CONFIG register +// +//************************************************************************************************* +#define ADC_PPB1CONFIG_CONFIG_S 0U +#define ADC_PPB1CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 1 Configuration +#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 1 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1STAMP register +// +//************************************************************************************************* +#define ADC_PPB1STAMP_DLYSTAMP_S 0U +#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 1 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB1OFFCAL_OFFCAL_S 0U +#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB1TRIPHI_LIMITHI_S 0U +#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 1 Trip High Limit +#define ADC_PPB1TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB1TRIPLO_LIMITLO_S 0U +#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 1 Trip Low Limit +#define ADC_PPB1TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB1TRIPLO_REQSTAMP_S 20U +#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 1 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2CONFIG register +// +//************************************************************************************************* +#define ADC_PPB2CONFIG_CONFIG_S 0U +#define ADC_PPB2CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 2 Configuration +#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 2 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2STAMP register +// +//************************************************************************************************* +#define ADC_PPB2STAMP_DLYSTAMP_S 0U +#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 2 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB2OFFCAL_OFFCAL_S 0U +#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB2TRIPHI_LIMITHI_S 0U +#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 2 Trip High Limit +#define ADC_PPB2TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB2TRIPLO_LIMITLO_S 0U +#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 2 Trip Low Limit +#define ADC_PPB2TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB2TRIPLO_REQSTAMP_S 20U +#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 2 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3CONFIG register +// +//************************************************************************************************* +#define ADC_PPB3CONFIG_CONFIG_S 0U +#define ADC_PPB3CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 3 Configuration +#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 3 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3STAMP register +// +//************************************************************************************************* +#define ADC_PPB3STAMP_DLYSTAMP_S 0U +#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 3 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB3OFFCAL_OFFCAL_S 0U +#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB3TRIPHI_LIMITHI_S 0U +#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 3 Trip High Limit +#define ADC_PPB3TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB3TRIPLO_LIMITLO_S 0U +#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 3 Trip Low Limit +#define ADC_PPB3TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB3TRIPLO_REQSTAMP_S 20U +#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 3 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4CONFIG register +// +//************************************************************************************************* +#define ADC_PPB4CONFIG_CONFIG_S 0U +#define ADC_PPB4CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 4 Configuration +#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 4 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4STAMP register +// +//************************************************************************************************* +#define ADC_PPB4STAMP_DLYSTAMP_S 0U +#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 4 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB4OFFCAL_OFFCAL_S 0U +#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB4TRIPHI_LIMITHI_S 0U +#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 4 Trip High Limit +#define ADC_PPB4TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB4TRIPLO_LIMITLO_S 0U +#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 4 Trip Low Limit +#define ADC_PPB4TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB4TRIPLO_REQSTAMP_S 20U +#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 4 Request Time Stamp + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1RESULT register +// +//************************************************************************************************* +#define ADC_PPB1RESULT_PPBRESULT_S 0U +#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB1RESULT_SIGN_S 16U +#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2RESULT register +// +//************************************************************************************************* +#define ADC_PPB2RESULT_PPBRESULT_S 0U +#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB2RESULT_SIGN_S 16U +#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3RESULT register +// +//************************************************************************************************* +#define ADC_PPB3RESULT_PPBRESULT_S 0U +#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB3RESULT_SIGN_S 16U +#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4RESULT register +// +//************************************************************************************************* +#define ADC_PPB4RESULT_PPBRESULT_S 0U +#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB4RESULT_SIGN_S 16U +#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_asysctl.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_asysctl.h new file mode 100644 index 0000000..4ee1c62 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_asysctl.h @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: hw_asysctl.h +// +// TITLE: Definitions for the ASYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ASYSCTL_H +#define HW_ASYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the ASYSCTL register offsets +// +//************************************************************************************************* +#define ASYSCTL_O_INTOSC1TRIM 0x20U // Internal Oscillator 1 Trim Register +#define ASYSCTL_O_INTOSC2TRIM 0x22U // Internal Oscillator 2 Trim Register +#define ASYSCTL_O_TSNSCTL 0x26U // Temperature Sensor Control Register +#define ASYSCTL_O_LOCK 0x2EU // Lock Register +#define ASYSCTL_O_ANAREFTRIMA 0x36U // Analog Reference Trim A Register +#define ASYSCTL_O_ANAREFTRIMB 0x38U // Analog Reference Trim B Register +#define ASYSCTL_O_ANAREFTRIMC 0x3AU // Analog Reference Trim C Register +#define ASYSCTL_O_ANAREFTRIMD 0x3CU // Analog Reference Trim D Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC1TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC2TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TSNSCTL register +// +//************************************************************************************************* +#define ASYSCTL_TSNSCTL_ENABLE 0x1U // Temperature Sensor Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOCK register +// +//************************************************************************************************* +#define ASYSCTL_LOCK_TSNSCTL 0x8U // Temperature Sensor Control Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMA 0x800000U // Analog Reference A Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMB 0x1000000U // Analog Reference B Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMC 0x2000000U // Analog Reference C Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMD 0x4000000U // Analog Reference D Trim Register Lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMA register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMB register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMC register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMD register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_M 0xF800U // Reference Current Trim + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_can.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_can.h new file mode 100644 index 0000000..05bc58b --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_can.h @@ -0,0 +1,514 @@ +//########################################################################### +// +// FILE: hw_can.h +// +// TITLE: Definitions for the CAN registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CAN_H +#define HW_CAN_H + +//************************************************************************************************* +// +// The following are defines for the CAN register offsets +// +//************************************************************************************************* +#define CAN_O_CTL 0x0U // CAN Control Register +#define CAN_O_ES 0x4U // Error and Status Register +#define CAN_O_ERRC 0x8U // Error Counter Register +#define CAN_O_BTR 0xCU // Bit Timing Register +#define CAN_O_INT 0x10U // Interrupt Register +#define CAN_O_TEST 0x14U // Test Register +#define CAN_O_PERR 0x1CU // CAN Parity Error Code Register +#define CAN_O_RAM_INIT 0x40U // CAN RAM Initialization Register +#define CAN_O_GLB_INT_EN 0x50U // CAN Global Interrupt Enable Register +#define CAN_O_GLB_INT_FLG 0x54U // CAN Global Interrupt Flag Register +#define CAN_O_GLB_INT_CLR 0x58U // CAN Global Interrupt Clear Register +#define CAN_O_ABOTR 0x80U // Auto-Bus-On Time Register +#define CAN_O_TXRQ_X 0x84U // CAN Transmission Request Register +#define CAN_O_TXRQ_21 0x88U // CAN Transmission Request 2_1 Register +#define CAN_O_NDAT_X 0x98U // CAN New Data Register +#define CAN_O_NDAT_21 0x9CU // CAN New Data 2_1 Register +#define CAN_O_IPEN_X 0xACU // CAN Interrupt Pending Register +#define CAN_O_IPEN_21 0xB0U // CAN Interrupt Pending 2_1 Register +#define CAN_O_MVAL_X 0xC0U // CAN Message Valid Register +#define CAN_O_MVAL_21 0xC4U // CAN Message Valid 2_1 Register +#define CAN_O_IP_MUX21 0xD8U // CAN Interrupt Multiplexer 2_1 Register +#define CAN_O_IF1CMD 0x100U // IF1 Command Register +#define CAN_O_IF1MSK 0x104U // IF1 Mask Register +#define CAN_O_IF1ARB 0x108U // IF1 Arbitration Register +#define CAN_O_IF1MCTL 0x10CU // IF1 Message Control Register +#define CAN_O_IF1DATA 0x110U // IF1 Data A Register +#define CAN_O_IF1DATB 0x114U // IF1 Data B Register +#define CAN_O_IF2CMD 0x120U // IF2 Command Register +#define CAN_O_IF2MSK 0x124U // IF2 Mask Register +#define CAN_O_IF2ARB 0x128U // IF2 Arbitration Register +#define CAN_O_IF2MCTL 0x12CU // IF2 Message Control Register +#define CAN_O_IF2DATA 0x130U // IF2 Data A Register +#define CAN_O_IF2DATB 0x134U // IF2 Data B Register +#define CAN_O_IF3OBS 0x140U // IF3 Observation Register +#define CAN_O_IF3MSK 0x144U // IF3 Mask Register +#define CAN_O_IF3ARB 0x148U // IF3 Arbitration Register +#define CAN_O_IF3MCTL 0x14CU // IF3 Message Control Register +#define CAN_O_IF3DATA 0x150U // IF3 Data A Register +#define CAN_O_IF3DATB 0x154U // IF3 Data B Register +#define CAN_O_IF3UPD 0x160U // IF3 Update Enable Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_CTL register +// +//************************************************************************************************* +#define CAN_CTL_INIT 0x1U // Initialization +#define CAN_CTL_IE0 0x2U // Interrupt line 0 Enable +#define CAN_CTL_SIE 0x4U // Status Change Interrupt Enable +#define CAN_CTL_EIE 0x8U // Error Interrupt Enable +#define CAN_CTL_DAR 0x20U // Disable Automatic Retransmission +#define CAN_CTL_CCE 0x40U // Configuration Change Enable +#define CAN_CTL_TEST 0x80U // Test Mode Enable +#define CAN_CTL_IDS 0x100U // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x200U // Auto-Bus-On Enable +#define CAN_CTL_PMD_S 10U +#define CAN_CTL_PMD_M 0x3C00U // Parity on/off +#define CAN_CTL_SWR 0x8000U // SW Reset Enable +#define CAN_CTL_INITDBG 0x10000U // Debug Mode Status +#define CAN_CTL_IE1 0x20000U // Interrupt line 1 Enable Disabled + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ES register +// +//************************************************************************************************* +#define CAN_ES_LEC_S 0U +#define CAN_ES_LEC_M 0x7U // Last Error Code +#define CAN_ES_TXOK 0x8U // Transmission status +#define CAN_ES_RXOK 0x10U // Reception status +#define CAN_ES_EPASS 0x20U // Error Passive State +#define CAN_ES_EWARN 0x40U // Warning State +#define CAN_ES_BOFF 0x80U // Bus-Off State +#define CAN_ES_PER 0x100U // Parity Error Detected + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ERRC register +// +//************************************************************************************************* +#define CAN_ERRC_TEC_S 0U +#define CAN_ERRC_TEC_M 0xFFU // Transmit Error Counter +#define CAN_ERRC_REC_S 8U +#define CAN_ERRC_REC_M 0x7F00U // Receive Error Counter +#define CAN_ERRC_RP 0x8000U // Receive Error Passive + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_BTR register +// +//************************************************************************************************* +#define CAN_BTR_BRP_S 0U +#define CAN_BTR_BRP_M 0x3FU // Baud Rate Prescaler +#define CAN_BTR_SJW_S 6U +#define CAN_BTR_SJW_M 0xC0U // Synchronization Jump Width +#define CAN_BTR_TSEG1_S 8U +#define CAN_BTR_TSEG1_M 0xF00U // Time segment +#define CAN_BTR_TSEG2_S 12U +#define CAN_BTR_TSEG2_M 0x7000U // Time segment +#define CAN_BTR_BRPE_S 16U +#define CAN_BTR_BRPE_M 0xF0000U // Baud Rate Prescaler Extension + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_INT register +// +//************************************************************************************************* +#define CAN_INT_INT0ID_S 0U +#define CAN_INT_INT0ID_M 0xFFFFU // Interrupt Identifier +#define CAN_INT_INT1ID_S 16U +#define CAN_INT_INT1ID_M 0xFF0000U // Interrupt 1 Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TEST register +// +//************************************************************************************************* +#define CAN_TEST_SILENT 0x8U // Silent Mode +#define CAN_TEST_LBACK 0x10U // Loopback Mode +#define CAN_TEST_TX_S 5U +#define CAN_TEST_TX_M 0x60U // CANTX Pin Control +#define CAN_TEST_RX 0x80U // CANRX Pin Status +#define CAN_TEST_EXL 0x100U // External Loopback Mode +#define CAN_TEST_RDA 0x200U // RAM Direct Access Enable: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_PERR register +// +//************************************************************************************************* +#define CAN_PERR_MSG_NUM_S 0U +#define CAN_PERR_MSG_NUM_M 0xFFU // Message Number +#define CAN_PERR_WORD_NUM_S 8U +#define CAN_PERR_WORD_NUM_M 0x700U // Word Number + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_RAM_INIT register +// +//************************************************************************************************* +#define CAN_RAM_INIT_KEY0 0x1U // KEY0 +#define CAN_RAM_INIT_KEY1 0x2U // KEY1 +#define CAN_RAM_INIT_KEY2 0x4U // KEY2 +#define CAN_RAM_INIT_KEY3 0x8U // KEY3 +#define CAN_RAM_INIT_CAN_RAM_INIT 0x10U // Initialize CAN Mailbox RAM +#define CAN_RAM_INIT_RAM_INIT_DONE 0x20U // CAN RAM initialization complete + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_EN register +// +//************************************************************************************************* +#define CAN_GLB_INT_EN_GLBINT0_EN 0x1U // Global Interrupt Enable for CANINT0 +#define CAN_GLB_INT_EN_GLBINT1_EN 0x2U // Global Interrupt Enable for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_FLG register +// +//************************************************************************************************* +#define CAN_GLB_INT_FLG_INT0_FLG 0x1U // Global Interrupt Flag for CANINT0 +#define CAN_GLB_INT_FLG_INT1_FLG 0x2U // Global Interrupt Flag for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_CLR register +// +//************************************************************************************************* +#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1U // Global Interrupt flag clear for CANINT0 +#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2U // Global Interrupt flag clear for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TXRQ_X register +// +//************************************************************************************************* +#define CAN_TXRQ_X_TXRQSTREG1_S 0U +#define CAN_TXRQ_X_TXRQSTREG1_M 0x3U // Transmit Request Register 1 +#define CAN_TXRQ_X_TXRQSTREG2_S 2U +#define CAN_TXRQ_X_TXRQSTREG2_M 0xCU // Transmit Request Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_NDAT_X register +// +//************************************************************************************************* +#define CAN_NDAT_X_NEWDATREG1_S 0U +#define CAN_NDAT_X_NEWDATREG1_M 0x3U // New Data Register 1 +#define CAN_NDAT_X_NEWDATREG2_S 2U +#define CAN_NDAT_X_NEWDATREG2_M 0xCU // New Data Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IPEN_X register +// +//************************************************************************************************* +#define CAN_IPEN_X_INTPNDREG1_S 0U +#define CAN_IPEN_X_INTPNDREG1_M 0x3U // Interrupt Pending Register 1 +#define CAN_IPEN_X_INTPNDREG2_S 2U +#define CAN_IPEN_X_INTPNDREG2_M 0xCU // Interrupt Pending Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_MVAL_X register +// +//************************************************************************************************* +#define CAN_MVAL_X_MSGVALREG1_S 0U +#define CAN_MVAL_X_MSGVALREG1_M 0x3U // Message Valid Register 1 +#define CAN_MVAL_X_MSGVALREG2_S 2U +#define CAN_MVAL_X_MSGVALREG2_M 0xCU // Message Valid Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1CMD register +// +//************************************************************************************************* +#define CAN_IF1CMD_MSG_NUM_S 0U +#define CAN_IF1CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF1CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF1CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF1CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF1CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF1CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF1CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF1CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF1CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF1CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MSK register +// +//************************************************************************************************* +#define CAN_IF1MSK_MSK_S 0U +#define CAN_IF1MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF1MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF1MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1ARB register +// +//************************************************************************************************* +#define CAN_IF1ARB_ID_S 0U +#define CAN_IF1ARB_ID_M 0x1FFFFFFFU // ` +#define CAN_IF1ARB_DIR 0x20000000U // Message Direction +#define CAN_IF1ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF1ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MCTL register +// +//************************************************************************************************* +#define CAN_IF1MCTL_DLC_S 0U +#define CAN_IF1MCTL_DLC_M 0xFU // Data length code +#define CAN_IF1MCTL_EOB 0x80U // End of Block +#define CAN_IF1MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF1MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF1MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF1MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF1MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF1MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF1MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF1MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATA register +// +//************************************************************************************************* +#define CAN_IF1DATA_DATA_0_S 0U +#define CAN_IF1DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF1DATA_DATA_1_S 8U +#define CAN_IF1DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF1DATA_DATA_2_S 16U +#define CAN_IF1DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF1DATA_DATA_3_S 24U +#define CAN_IF1DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATB register +// +//************************************************************************************************* +#define CAN_IF1DATB_DATA_4_S 0U +#define CAN_IF1DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF1DATB_DATA_5_S 8U +#define CAN_IF1DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF1DATB_DATA_6_S 16U +#define CAN_IF1DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF1DATB_DATA_7_S 24U +#define CAN_IF1DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2CMD register +// +//************************************************************************************************* +#define CAN_IF2CMD_MSG_NUM_S 0U +#define CAN_IF2CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF2CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF2CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF2CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF2CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF2CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF2CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF2CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF2CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF2CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MSK register +// +//************************************************************************************************* +#define CAN_IF2MSK_MSK_S 0U +#define CAN_IF2MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF2MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF2MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2ARB register +// +//************************************************************************************************* +#define CAN_IF2ARB_ID_S 0U +#define CAN_IF2ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF2ARB_DIR 0x20000000U // Message Direction +#define CAN_IF2ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF2ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MCTL register +// +//************************************************************************************************* +#define CAN_IF2MCTL_DLC_S 0U +#define CAN_IF2MCTL_DLC_M 0xFU // Data length code +#define CAN_IF2MCTL_EOB 0x80U // End of Block +#define CAN_IF2MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF2MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF2MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF2MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF2MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF2MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF2MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF2MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATA register +// +//************************************************************************************************* +#define CAN_IF2DATA_DATA_0_S 0U +#define CAN_IF2DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF2DATA_DATA_1_S 8U +#define CAN_IF2DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF2DATA_DATA_2_S 16U +#define CAN_IF2DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF2DATA_DATA_3_S 24U +#define CAN_IF2DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATB register +// +//************************************************************************************************* +#define CAN_IF2DATB_DATA_4_S 0U +#define CAN_IF2DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF2DATB_DATA_5_S 8U +#define CAN_IF2DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF2DATB_DATA_6_S 16U +#define CAN_IF2DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF2DATB_DATA_7_S 24U +#define CAN_IF2DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3OBS register +// +//************************************************************************************************* +#define CAN_IF3OBS_MASK 0x1U // Mask data read observation +#define CAN_IF3OBS_ARB 0x2U // Arbitration data read observation +#define CAN_IF3OBS_CTRL 0x4U // Ctrl read observation +#define CAN_IF3OBS_DATA_A 0x8U // Data A read observation +#define CAN_IF3OBS_DATA_B 0x10U // Data B read observation +#define CAN_IF3OBS_IF3SM 0x100U // IF3 Status of Mask data read access +#define CAN_IF3OBS_IF3SA 0x200U // IF3 Status of Arbitration data read access +#define CAN_IF3OBS_IF3SC 0x400U // IF3 Status of Control bits read access +#define CAN_IF3OBS_IF3SDA 0x800U // IF3 Status of Data A read access +#define CAN_IF3OBS_IF3SDB 0x1000U // IF3 Status of Data B read access +#define CAN_IF3OBS_IF3UPD 0x8000U // IF3 Update Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MSK register +// +//************************************************************************************************* +#define CAN_IF3MSK_MSK_S 0U +#define CAN_IF3MSK_MSK_M 0x1FFFFFFFU // Mask +#define CAN_IF3MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF3MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3ARB register +// +//************************************************************************************************* +#define CAN_IF3ARB_ID_S 0U +#define CAN_IF3ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF3ARB_DIR 0x20000000U // Message Direction +#define CAN_IF3ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF3ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MCTL register +// +//************************************************************************************************* +#define CAN_IF3MCTL_DLC_S 0U +#define CAN_IF3MCTL_DLC_M 0xFU // Data length code +#define CAN_IF3MCTL_EOB 0x80U // End of Block +#define CAN_IF3MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF3MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF3MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF3MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF3MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF3MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF3MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF3MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATA register +// +//************************************************************************************************* +#define CAN_IF3DATA_DATA_0_S 0U +#define CAN_IF3DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF3DATA_DATA_1_S 8U +#define CAN_IF3DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF3DATA_DATA_2_S 16U +#define CAN_IF3DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF3DATA_DATA_3_S 24U +#define CAN_IF3DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATB register +// +//************************************************************************************************* +#define CAN_IF3DATB_DATA_4_S 0U +#define CAN_IF3DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF3DATB_DATA_5_S 8U +#define CAN_IF3DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF3DATB_DATA_6_S 16U +#define CAN_IF3DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF3DATB_DATA_7_S 24U +#define CAN_IF3DATB_DATA_7_M 0xFF000000U // Data Byte 7 + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_cla.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_cla.h new file mode 100644 index 0000000..0206de7 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_cla.h @@ -0,0 +1,241 @@ +//########################################################################### +// +// FILE: hw_cla.h +// +// TITLE: Definitions for the CLA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLA_H +#define HW_CLA_H + +//************************************************************************************************* +// +// The following are defines for the CLA register offsets +// +//************************************************************************************************* +#ifndef __TMS320C28XX_CLA__ +#define CLA_O_MVECT1 0x0U // Task Interrupt Vector +#define CLA_O_MVECT2 0x1U // Task Interrupt Vector +#define CLA_O_MVECT3 0x2U // Task Interrupt Vector +#define CLA_O_MVECT4 0x3U // Task Interrupt Vector +#define CLA_O_MVECT5 0x4U // Task Interrupt Vector +#define CLA_O_MVECT6 0x5U // Task Interrupt Vector +#define CLA_O_MVECT7 0x6U // Task Interrupt Vector +#define CLA_O_MVECT8 0x7U // Task Interrupt Vector +#define CLA_O_MCTL 0x10U // Control Register +#define CLA_O_MIFR 0x20U // Interrupt Flag Register +#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register +#define CLA_O_MIFRC 0x22U // Interrupt Force Register +#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register +#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register +#define CLA_O_MIER 0x25U // Interrupt Enable Register +#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register +#define CLA_O_MPC 0x28U // CLA Program Counter +#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0 +#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1 +#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register +#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0 +#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1 +#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2 +#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3 +#endif + +#ifdef __TMS320C28XX_CLA__ +#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register +#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register +#endif + + +#ifndef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCTL register +// +//************************************************************************************************* +#define CLA_MCTL_HARDRESET 0x1U // Hard Reset +#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset +#define CLA_MCTL_IACKE 0x4U // IACK enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFR register +// +//************************************************************************************************* +#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag +#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag +#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag +#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag +#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag +#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag +#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag +#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIOVF register +// +//************************************************************************************************* +#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag +#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag +#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag +#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag +#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag +#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag +#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag +#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFRC register +// +//************************************************************************************************* +#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force +#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force +#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force +#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force +#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force +#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force +#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force +#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLR register +// +//************************************************************************************************* +#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear +#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear +#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear +#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear +#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear +#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear +#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear +#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLROVF register +// +//************************************************************************************************* +#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIER register +// +//************************************************************************************************* +#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable +#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable +#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable +#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable +#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable +#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable +#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable +#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIRUN register +// +//************************************************************************************************* +#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status +#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status +#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status +#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status +#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status +#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status +#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status +#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the _MSTF register +// +//************************************************************************************************* +#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag +#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag +#define CLA_MSTF_NF 0x4U // Negative Float Flag +#define CLA_MSTF_ZF 0x8U // Zero Float Flag +#define CLA_MSTF_TF 0x40U // Test Flag +#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode +#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status +#define CLA_MSTF_RPC_S 12U +#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC + +#endif + +#ifdef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTEN register +// +//************************************************************************************************* +#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTFRC register +// +//************************************************************************************************* +#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task. + +#endif + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_clb.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_clb.h new file mode 100644 index 0000000..4390004 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_clb.h @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: hw_clb.h +// +// TITLE: Definitions for the CLB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLB_H +#define HW_CLB_H + +//************************************************************************************************* +// +// The following are defines for the CLB register offsets +// +//************************************************************************************************* +#define CLB_O_COUNT_RESET 0x2U // Counter Block RESET +#define CLB_O_COUNT_MODE_1 0x4U // Counter Block MODE_1 +#define CLB_O_COUNT_MODE_0 0x6U // Counter Block MODE_0 +#define CLB_O_COUNT_EVENT 0x8U // Counter Block EVENT +#define CLB_O_FSM_EXTRA_IN0 0xAU // FSM Extra EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN0 0xCU // FSM EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN1 0xEU // FSM_EXT_IN1 +#define CLB_O_FSM_EXTRA_IN1 0x10U // FSM Extra_EXT_IN1 +#define CLB_O_LUT4_IN0 0x12U // LUT4_0/1/2 IN0 input source +#define CLB_O_LUT4_IN1 0x14U // LUT4_0/1/2 IN1 input source +#define CLB_O_LUT4_IN2 0x16U // LUT4_0/1/2 IN2 input source +#define CLB_O_LUT4_IN3 0x18U // LUT4_0/1/2 IN3 input source +#define CLB_O_FSM_LUT_FN1_0 0x1CU // LUT function for FSM Unit 1 and Unit 0 +#define CLB_O_FSM_LUT_FN2 0x1EU // LUT function for FSM Unit 2 +#define CLB_O_LUT4_FN1_0 0x20U // LUT function for LUT4 block of Unit 1 and 0 +#define CLB_O_LUT4_FN2 0x22U // LUT function for LUT4 block of Unit 2 +#define CLB_O_FSM_NEXT_STATE_0 0x24U // FSM Next state equations for Unit 0 +#define CLB_O_FSM_NEXT_STATE_1 0x26U // FSM Next state equations for Unit 1 +#define CLB_O_FSM_NEXT_STATE_2 0x28U // FSM Next state equations for Unit 2 +#define CLB_O_MISC_CONTROL 0x2AU // Static controls for Ctr,FSM +#define CLB_O_OUTPUT_LUT_0 0x2CU // Inp Sel, LUT fns for Out0 +#define CLB_O_OUTPUT_LUT_1 0x2EU // Inp Sel, LUT fns for Out1 +#define CLB_O_OUTPUT_LUT_2 0x30U // Inp Sel, LUT fns for Out2 +#define CLB_O_OUTPUT_LUT_3 0x32U // Inp Sel, LUT fns for Out3 +#define CLB_O_OUTPUT_LUT_4 0x34U // Inp Sel, LUT fns for Out4 +#define CLB_O_OUTPUT_LUT_5 0x36U // Inp Sel, LUT fns for Out5 +#define CLB_O_OUTPUT_LUT_6 0x38U // Inp Sel, LUT fns for Out6 +#define CLB_O_OUTPUT_LUT_7 0x3AU // Inp Sel, LUT fns for Out7 +#define CLB_O_HLC_EVENT_SEL 0x3CU // Event Selector register for the High Level controller + +#define CLB_O_LOAD_EN 0x0U // Global enable & indirect load enable control +#define CLB_O_LOAD_ADDR 0x2U // Indirect address +#define CLB_O_LOAD_DATA 0x4U // Data for indirect loads +#define CLB_O_INPUT_FILTER 0x6U // Input filter selection for both edge detection and + // synchronizers +#define CLB_O_IN_MUX_SEL_0 0x8U // Input selection to decide between Signals and GP register +#define CLB_O_LCL_MUX_SEL_1 0xAU // Input Mux selection for local mux +#define CLB_O_LCL_MUX_SEL_2 0xCU // Input Mux selection for local mux +#define CLB_O_BUF_PTR 0xEU // PUSH and PULL pointers +#define CLB_O_GP_REG 0x10U // General purpose register for CELL inputs +#define CLB_O_OUT_EN 0x12U // CELL output enable register +#define CLB_O_GLBL_MUX_SEL_1 0x14U // Global Mux select for CELL inputs +#define CLB_O_GLBL_MUX_SEL_2 0x16U // Global Mux select for CELL inputs +#define CLB_O_INTR_TAG_REG 0x20U // Interrupt Tag register +#define CLB_O_LOCK 0x22U // Lock control register +#define CLB_O_DBG_R0 0x30U // R0 of High level Controller +#define CLB_O_DBG_R1 0x32U // R1 of High level Controller +#define CLB_O_DBG_R2 0x34U // R2 of High level Controller +#define CLB_O_DBG_R3 0x36U // R3 of High level Controller +#define CLB_O_DBG_C0 0x38U // Count of Unit 0 +#define CLB_O_DBG_C1 0x3AU // Count of Unit 1 +#define CLB_O_DBG_C2 0x3CU // Count of Unit 2 +#define CLB_O_DBG_OUT 0x3EU // Outputs of various units in the Cell + +#define CLB_O_PUSH(i) (0x0U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PUSH FIFO Registers (from + // HLC) +#define CLB_O_PULL(i) (0x100U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PULL FIFO Registers (TO HLC) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_RESET register +// +//************************************************************************************************* +#define CLB_COUNT_RESET_SEL_0_S 0U +#define CLB_COUNT_RESET_SEL_0_M 0x1FU // Count Reset Select 0 +#define CLB_COUNT_RESET_SEL_1_S 5U +#define CLB_COUNT_RESET_SEL_1_M 0x3E0U // Count Reset Select 1 +#define CLB_COUNT_RESET_SEL_2_S 10U +#define CLB_COUNT_RESET_SEL_2_M 0x7C00U // Count Reset Select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_1_SEL_0_S 0U +#define CLB_COUNT_MODE_1_SEL_0_M 0x1FU // Counter mode 1 select 0 +#define CLB_COUNT_MODE_1_SEL_1_S 5U +#define CLB_COUNT_MODE_1_SEL_1_M 0x3E0U // Counter mode 1 select 1 +#define CLB_COUNT_MODE_1_SEL_2_S 10U +#define CLB_COUNT_MODE_1_SEL_2_M 0x7C00U // Counter mode 1 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_0_SEL_0_S 0U +#define CLB_COUNT_MODE_0_SEL_0_M 0x1FU // Counter mode 0 select 0 +#define CLB_COUNT_MODE_0_SEL_1_S 5U +#define CLB_COUNT_MODE_0_SEL_1_M 0x3E0U // Counter mode 0 select 1 +#define CLB_COUNT_MODE_0_SEL_2_S 10U +#define CLB_COUNT_MODE_0_SEL_2_M 0x7C00U // Counter mode 0 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_EVENT register +// +//************************************************************************************************* +#define CLB_COUNT_EVENT_SEL_0_S 0U +#define CLB_COUNT_EVENT_SEL_0_M 0x1FU // Counter event select 0 +#define CLB_COUNT_EVENT_SEL_1_S 5U +#define CLB_COUNT_EVENT_SEL_1_M 0x3E0U // Counter event select 1 +#define CLB_COUNT_EVENT_SEL_2_S 10U +#define CLB_COUNT_EVENT_SEL_2_M 0x7C00U // Counter event select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN0_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN0_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN0_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN0_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN0_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN0_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN0_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN0_SEL_0_M 0x1FU // FSM EXT_IN0 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN0_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN0_SEL_1_M 0x3E0U // FSM EXT_IN0 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN0_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN0_SEL_2_M 0x7C00U // FSM EXT_IN0 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN1_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN1_SEL_0_M 0x1FU // FSM EXT_IN1 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN1_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN1_SEL_1_M 0x3E0U // FSM EXT_IN1 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN1_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN1_SEL_2_M 0x7C00U // FSM EXT_IN1 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN1_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN1_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN1_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN1_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN1_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN1_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN0 register +// +//************************************************************************************************* +#define CLB_LUT4_IN0_SEL_0_S 0U +#define CLB_LUT4_IN0_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN0_SEL_1_S 5U +#define CLB_LUT4_IN0_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN0_SEL_2_S 10U +#define CLB_LUT4_IN0_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN1 register +// +//************************************************************************************************* +#define CLB_LUT4_IN1_SEL_0_S 0U +#define CLB_LUT4_IN1_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN1_SEL_1_S 5U +#define CLB_LUT4_IN1_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN1_SEL_2_S 10U +#define CLB_LUT4_IN1_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN2 register +// +//************************************************************************************************* +#define CLB_LUT4_IN2_SEL_0_S 0U +#define CLB_LUT4_IN2_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN2_SEL_1_S 5U +#define CLB_LUT4_IN2_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN2_SEL_2_S 10U +#define CLB_LUT4_IN2_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN3 register +// +//************************************************************************************************* +#define CLB_LUT4_IN3_SEL_0_S 0U +#define CLB_LUT4_IN3_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN3_SEL_1_S 5U +#define CLB_LUT4_IN3_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN3_SEL_2_S 10U +#define CLB_LUT4_IN3_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN1_0_FN0_S 0U +#define CLB_FSM_LUT_FN1_0_FN0_M 0xFFFFU // FSM LUT output function for unit 0 +#define CLB_FSM_LUT_FN1_0_FN1_S 16U +#define CLB_FSM_LUT_FN1_0_FN1_M 0xFFFF0000U // FSM LUT output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN2_FN1_S 0U +#define CLB_FSM_LUT_FN2_FN1_M 0xFFFFU // FSM LUT output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register +// +//************************************************************************************************* +#define CLB_LUT4_FN1_0_FN0_S 0U +#define CLB_LUT4_FN1_0_FN0_M 0xFFFFU // LUT4 output function for unit 0 +#define CLB_LUT4_FN1_0_FN1_S 16U +#define CLB_LUT4_FN1_0_FN1_M 0xFFFF0000U // LUT4 output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN2 register +// +//************************************************************************************************* +#define CLB_LUT4_FN2_FN1_S 0U +#define CLB_LUT4_FN2_FN1_M 0xFFFFU // LUT4 output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_0_S0_S 0U +#define CLB_FSM_NEXT_STATE_0_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_0_S1_S 16U +#define CLB_FSM_NEXT_STATE_0_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_1_S0_S 0U +#define CLB_FSM_NEXT_STATE_1_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_1_S1_S 16U +#define CLB_FSM_NEXT_STATE_1_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_2_S0_S 0U +#define CLB_FSM_NEXT_STATE_2_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_2_S1_S 16U +#define CLB_FSM_NEXT_STATE_2_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_MISC_CONTROL register +// +//************************************************************************************************* +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_0 0x1U // Add/Shift for counter 0 +#define CLB_MISC_CONTROL_COUNT_DIR_0 0x2U // Direction for counter 0 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_0 0x4U // Event control for counter 0 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_1 0x8U // Add/Shift for counter 1 +#define CLB_MISC_CONTROL_COUNT_DIR_1 0x10U // Direction for counter 1 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_1 0x20U // Event control for counter 1 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_2 0x40U // Add/Shift for counter 2 +#define CLB_MISC_CONTROL_COUNT_DIR_2 0x80U // Direction for counter 2 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_2 0x100U // Event control for counter 2 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_0 0x200U // Serializer enable 0 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_1 0x400U // Serializer enable 1 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_2 0x800U // Serializer enable 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_0 0x1000U // FSM extra_sel0 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_0 0x2000U // FSM extra_sel1 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_1 0x4000U // FSM extra_sel0 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_1 0x8000U // FSM extra_sel1 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_2 0x10000U // FSM extra_sel0 for 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_2 0x20000U // FSM extra_sel1 for 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_0_IN0_S 0U +#define CLB_OUTPUT_LUT_0_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_0_IN1_S 5U +#define CLB_OUTPUT_LUT_0_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_0_IN2_S 10U +#define CLB_OUTPUT_LUT_0_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_0_FN_S 15U +#define CLB_OUTPUT_LUT_0_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_1_IN0_S 0U +#define CLB_OUTPUT_LUT_1_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_1_IN1_S 5U +#define CLB_OUTPUT_LUT_1_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_1_IN2_S 10U +#define CLB_OUTPUT_LUT_1_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_1_FN_S 15U +#define CLB_OUTPUT_LUT_1_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_2_IN0_S 0U +#define CLB_OUTPUT_LUT_2_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_2_IN1_S 5U +#define CLB_OUTPUT_LUT_2_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_2_IN2_S 10U +#define CLB_OUTPUT_LUT_2_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_2_FN_S 15U +#define CLB_OUTPUT_LUT_2_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_3_IN0_S 0U +#define CLB_OUTPUT_LUT_3_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_3_IN1_S 5U +#define CLB_OUTPUT_LUT_3_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_3_IN2_S 10U +#define CLB_OUTPUT_LUT_3_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_3_FN_S 15U +#define CLB_OUTPUT_LUT_3_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_4_IN0_S 0U +#define CLB_OUTPUT_LUT_4_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_4_IN1_S 5U +#define CLB_OUTPUT_LUT_4_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_4_IN2_S 10U +#define CLB_OUTPUT_LUT_4_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_4_FN_S 15U +#define CLB_OUTPUT_LUT_4_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_5_IN0_S 0U +#define CLB_OUTPUT_LUT_5_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_5_IN1_S 5U +#define CLB_OUTPUT_LUT_5_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_5_IN2_S 10U +#define CLB_OUTPUT_LUT_5_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_5_FN_S 15U +#define CLB_OUTPUT_LUT_5_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_6_IN0_S 0U +#define CLB_OUTPUT_LUT_6_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_6_IN1_S 5U +#define CLB_OUTPUT_LUT_6_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_6_IN2_S 10U +#define CLB_OUTPUT_LUT_6_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_6_FN_S 15U +#define CLB_OUTPUT_LUT_6_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_7_IN0_S 0U +#define CLB_OUTPUT_LUT_7_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_7_IN1_S 5U +#define CLB_OUTPUT_LUT_7_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_7_IN2_S 10U +#define CLB_OUTPUT_LUT_7_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_7_FN_S 15U +#define CLB_OUTPUT_LUT_7_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register +// +//************************************************************************************************* +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_S 0U +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_M 0x1FU // Event Select 0 +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_S 5U +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_M 0x3E0U // Event Select 1 +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_S 10U +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_M 0x7C00U // Event Select 2 +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_S 15U +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_M 0xF8000U // Event Select 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_EN register +// +//************************************************************************************************* +#define CLB_LOAD_EN_LOAD_EN 0x1U // Load Enable +#define CLB_LOAD_EN_GLOBAL_EN 0x2U // Global Enable +#define CLB_LOAD_EN_STOP 0x4U // Debug stop control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_ADDR register +// +//************************************************************************************************* +#define CLB_LOAD_ADDR_ADDR_S 0U +#define CLB_LOAD_ADDR_ADDR_M 0x3FU // Indirect Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INPUT_FILTER register +// +//************************************************************************************************* +#define CLB_INPUT_FILTER_FIN0_S 0U +#define CLB_INPUT_FILTER_FIN0_M 0x3U // Input filter control 0 +#define CLB_INPUT_FILTER_FIN1_S 2U +#define CLB_INPUT_FILTER_FIN1_M 0xCU // Input filter control 1 +#define CLB_INPUT_FILTER_FIN2_S 4U +#define CLB_INPUT_FILTER_FIN2_M 0x30U // Input filter control 2 +#define CLB_INPUT_FILTER_FIN3_S 6U +#define CLB_INPUT_FILTER_FIN3_M 0xC0U // Input filter control 3 +#define CLB_INPUT_FILTER_FIN4_S 8U +#define CLB_INPUT_FILTER_FIN4_M 0x300U // Input filter control 4 +#define CLB_INPUT_FILTER_FIN5_S 10U +#define CLB_INPUT_FILTER_FIN5_M 0xC00U // Input filter control 5 +#define CLB_INPUT_FILTER_FIN6_S 12U +#define CLB_INPUT_FILTER_FIN6_M 0x3000U // Input filter control 6 +#define CLB_INPUT_FILTER_FIN7_S 14U +#define CLB_INPUT_FILTER_FIN7_M 0xC000U // Input filter control 7 +#define CLB_INPUT_FILTER_SYNC0 0x10000U // Synchronizer control 0 +#define CLB_INPUT_FILTER_SYNC1 0x20000U // Synchronizer control 1 +#define CLB_INPUT_FILTER_SYNC2 0x40000U // Synchronizer control 2 +#define CLB_INPUT_FILTER_SYNC3 0x80000U // Synchronizer control 3 +#define CLB_INPUT_FILTER_SYNC4 0x100000U // Synchronizer control 4 +#define CLB_INPUT_FILTER_SYNC5 0x200000U // Synchronizer control 5 +#define CLB_INPUT_FILTER_SYNC6 0x400000U // Synchronizer control 6 +#define CLB_INPUT_FILTER_SYNC7 0x800000U // Synchronizer control 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register +// +//************************************************************************************************* +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_0 0x1U // Select GP register 0 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_1 0x2U // Select GP register 1 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_2 0x4U // Select GP register 2 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_3 0x8U // Select GP register 3 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_4 0x10U // Select GP register 4 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_5 0x20U // Select GP register 5 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_6 0x40U // Select GP register 6 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_7 0x80U // Select GP register 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_S 0U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M 0x1FU // Local Mux select 0 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S 5U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_M 0x3E0U // Local Mux select 1 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_S 10U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_M 0x7C00U // Local Mux select 2 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_S 15U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_M 0xF8000U // Local Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_S 0U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_M 0x1FU // Local Mux select 4 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_S 5U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_M 0x3E0U // Local Mux select 5 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_S 10U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_M 0x7C00U // Local Mux select 6 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_S 15U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_M 0xF8000U // Local Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_BUF_PTR register +// +//************************************************************************************************* +#define CLB_BUF_PTR_PULL_S 0U +#define CLB_BUF_PTR_PULL_M 0xFFU // Data pointer for pull +#define CLB_BUF_PTR_PUSH_S 16U +#define CLB_BUF_PTR_PUSH_M 0xFF0000U // Data pointer for pull + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GP_REG register +// +//************************************************************************************************* +#define CLB_GP_REG_REG_S 0U +#define CLB_GP_REG_REG_M 0xFFU // General Purpose bit register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_S 0U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M 0x7FU // Global Mux select 0 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S 7U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_M 0x3F80U // Global Mux select 1 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_S 14U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_M 0x1FC000U // Global Mux select 2 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_S 21U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_M 0xFE00000U // Global Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_S 0U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_M 0x7FU // Global Mux select 4 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_S 7U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_M 0x3F80U // Global Mux select 5 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_S 14U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_M 0x1FC000U // Global Mux select 6 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_S 21U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_M 0xFE00000U // Global Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INTR_TAG_REG register +// +//************************************************************************************************* +#define CLB_INTR_TAG_REG_TAG_S 0U +#define CLB_INTR_TAG_REG_TAG_M 0x3FU // Interrupt tag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOCK register +// +//************************************************************************************************* +#define CLB_LOCK_LOCK 0x1U // LOCK enable +#define CLB_LOCK_KEY_S 16U +#define CLB_LOCK_KEY_M 0xFFFF0000U // Key for enabling write + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_DBG_OUT register +// +//************************************************************************************************* +#define CLB_DBG_OUT_COUNT0_MATCH2 0x2U // COUNT_MATCH2 UNIT 0 +#define CLB_DBG_OUT_COUNT0_ZERO 0x4U // COUNT_ZERO UNIT 0 +#define CLB_DBG_OUT_COUNT0_MATCH1 0x8U // COUNT_MATCH1 UNIT 0 +#define CLB_DBG_OUT_FSM0_S0 0x10U // FSM_S0 UNIT 0 +#define CLB_DBG_OUT_FSM0_S1 0x20U // FSM_S1 UNIT 0 +#define CLB_DBG_OUT_FSM0_LUTOUT 0x40U // FSM_LUT_OUT UNIT 0 +#define CLB_DBG_OUT_LUT40_OUT 0x80U // LUT4_OUT UNIT 0 +#define CLB_DBG_OUT_COUNT1_MATCH2 0x200U // COUNT_MATCH2 UNIT 1 +#define CLB_DBG_OUT_COUNT1_ZERO 0x400U // COUNT_ZERO UNIT 1 +#define CLB_DBG_OUT_COUNT1_MATCH1 0x800U // COUNT_MATCH1 UNIT 1 +#define CLB_DBG_OUT_FSM1_S0 0x1000U // FSM_S0 UNIT 1 +#define CLB_DBG_OUT_FSM1_S1 0x2000U // FSM_S1 UNIT 1 +#define CLB_DBG_OUT_FSM1_LUTOUT 0x4000U // FSM_LUT_OUT UNIT 1 +#define CLB_DBG_OUT_LUT41_OUT 0x8000U // LUT4_OUT UNIT 1 +#define CLB_DBG_OUT_COUNT2_MATCH2 0x20000U // COUNT_MATCH2 UNIT 2 +#define CLB_DBG_OUT_COUNT2_ZERO 0x40000U // COUNT_ZERO UNIT 2 +#define CLB_DBG_OUT_COUNT2_MATCH1 0x80000U // COUNT_MATCH1 UNIT 2 +#define CLB_DBG_OUT_FSM2_S0 0x100000U // FSM_S0 UNIT 2 +#define CLB_DBG_OUT_FSM2_S1 0x200000U // FSM_S1 UNIT 2 +#define CLB_DBG_OUT_FSM2_LUTOUT 0x400000U // FSM_LUT_OUT UNIT 2 +#define CLB_DBG_OUT_LUT42_OUT 0x800000U // LUT4_OUT UNIT 2 +#define CLB_DBG_OUT_OUT0 0x1000000U // CELL Output 0 +#define CLB_DBG_OUT_OUT1 0x2000000U // CELL Output 1 +#define CLB_DBG_OUT_OUT2 0x4000000U // CELL Output 2 +#define CLB_DBG_OUT_OUT3 0x8000000U // CELL Output 3 +#define CLB_DBG_OUT_OUT4 0x10000000U // CELL Output 4 +#define CLB_DBG_OUT_OUT5 0x20000000U // CELL Output 5 +#define CLB_DBG_OUT_OUT6 0x40000000U // CELL Output 6 +#define CLB_DBG_OUT_OUT7 0x80000000U // CELL Output 7 + + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_clbxbar.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_clbxbar.h new file mode 100644 index 0000000..64072e2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_clbxbar.h @@ -0,0 +1,1272 @@ +//########################################################################### +// +// FILE: hw_clbxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLBXBAR_H +#define HW_CLBXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_AUXSIG0MUX0TO15CFG 0x0U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG0MUX16TO31CFG 0x2U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG1MUX0TO15CFG 0x4U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG1MUX16TO31CFG 0x6U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG2MUX0TO15CFG 0x8U // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG2MUX16TO31CFG 0xAU // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG3MUX0TO15CFG 0xCU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG3MUX16TO31CFG 0xEU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG4MUX0TO15CFG 0x10U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG4MUX16TO31CFG 0x12U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG5MUX0TO15CFG 0x14U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG5MUX16TO31CFG 0x16U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG6MUX0TO15CFG 0x18U // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG6MUX16TO31CFG 0x1AU // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG7MUX0TO15CFG 0x1CU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG7MUX16TO31CFG 0x1EU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG0MUXENABLE 0x20U // CLB XBAR Mux Enable Register for Output-0 +#define XBAR_O_AUXSIG1MUXENABLE 0x22U // CLB XBAR Mux Enable Register for Output-1 +#define XBAR_O_AUXSIG2MUXENABLE 0x24U // CLB XBAR Mux Enable Register for Output-2 +#define XBAR_O_AUXSIG3MUXENABLE 0x26U // CLB XBAR Mux Enable Register for Output-3 +#define XBAR_O_AUXSIG4MUXENABLE 0x28U // CLB XBAR Mux Enable Register for Output-4 +#define XBAR_O_AUXSIG5MUXENABLE 0x2AU // CLB XBAR Mux Enable Register for Output-5 +#define XBAR_O_AUXSIG6MUXENABLE 0x2CU // CLB XBAR Mux Enable Register for Output-6 +#define XBAR_O_AUXSIG7MUXENABLE 0x2EU // CLB XBAR Mux Enable Register for Output-7 +#define XBAR_O_AUXSIGOUTINV 0x38U // CLB XBAR Output Inversion Register +#define XBAR_O_AUXSIGLOCK 0x3EU // ClbXbar Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG0 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG1 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG2 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG3 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG4 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG5 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG6 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGOUTINV register +// +//************************************************************************************************* +#define XBAR_AUXSIGOUTINV_OUT0 0x1U // Selects polarity for AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT1 0x2U // Selects polarity for AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT2 0x4U // Selects polarity for AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT3 0x8U // Selects polarity for AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT4 0x10U // Selects polarity for AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT5 0x20U // Selects polarity for AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT6 0x40U // Selects polarity for AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT7 0x80U // Selects polarity for AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGLOCK register +// +//************************************************************************************************* +#define XBAR_AUXSIGLOCK_LOCK 0x1U // Locks the configuration for CLB-XBAR +#define XBAR_AUXSIGLOCK_KEY_S 16U +#define XBAR_AUXSIGLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_cmpss.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_cmpss.h new file mode 100644 index 0000000..67d32e3 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_cmpss.h @@ -0,0 +1,235 @@ +//########################################################################### +// +// FILE: hw_cmpss.h +// +// TITLE: Definitions for the CMPSS registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CMPSS_H +#define HW_CMPSS_H + +//************************************************************************************************* +// +// The following are defines for the CMPSS register offsets +// +//************************************************************************************************* +#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register +#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register +#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register +#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register +#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register +#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register +#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register +#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register +#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register +#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register +#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register +#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register +#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register +#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register +#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register +#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register +#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register +#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register +#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register +#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register +#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPCTL register +// +//************************************************************************************************* +#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select +#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPHSEL_S 2U +#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U +#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select +#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPLSEL_S 10U +#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U +#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPHYSCTL register +// +//************************************************************************************************* +#define CMPSS_COMPHYSCTL_COMPHYS_S 0U +#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTS register +// +//************************************************************************************************* +#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status +#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status +#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status +#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTSCLR register +// +//************************************************************************************************* +#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable +#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPDACCTL register +// +//************************************************************************************************* +#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control +#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U +#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control +#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select +#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select +#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select +#define CMPSS_COMPDACCTL_FREESOFT_S 14U +#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALS register +// +//************************************************************************************************* +#define CMPSS_DACHVALS_DACVAL_S 0U +#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALA register +// +//************************************************************************************************* +#define CMPSS_DACHVALA_DACVAL_S 0U +#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALS register +// +//************************************************************************************************* +#define CMPSS_DACLVALS_DACVAL_S 0U +#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALA register +// +//************************************************************************************************* +#define CMPSS_DACLVALA_DACVAL_S 0U +#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYA register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYA_DELAY_S 0U +#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYS register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYS_DELAY_S 0U +#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPLFILCTL_THRESH_S 9U +#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPHFILCTL_THRESH_S 9U +#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPLOCK register +// +//************************************************************************************************* +#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock +#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock +#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock +#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_cputimer.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_cputimer.h new file mode 100644 index 0000000..f7613fb --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_cputimer.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: hw_cputimer.h +// +// TITLE: Definitions for the CPUTIMER registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CPUTIMER_H +#define HW_CPUTIMER_H + +//************************************************************************************************* +// +// The following are defines for the CPUTIMER register offsets +// +//************************************************************************************************* +#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register +#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register +#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register +#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register +#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TIM register +// +//************************************************************************************************* +#define CPUTIMER_TIM_LSW_S 0U +#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers +#define CPUTIMER_TIM_MSW_S 16U +#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRD register +// +//************************************************************************************************* +#define CPUTIMER_PRD_LSW_S 0U +#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers +#define CPUTIMER_PRD_MSW_S 16U +#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TCR register +// +//************************************************************************************************* +#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit. +#define CPUTIMER_TCR_TRB 0x20U // Timer reload +#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes +#define CPUTIMER_TCR_FREE 0x800U // Emulation modes +#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable. +#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPR register +// +//************************************************************************************************* +#define CPUTIMER_TPR_TDDR_S 0U +#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPR_PSC_S 8U +#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPRH register +// +//************************************************************************************************* +#define CPUTIMER_TPRH_TDDRH_S 0U +#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPRH_PSCH_S 8U +#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter. + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_dac.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_dac.h new file mode 100644 index 0000000..3e3d3a2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_dac.h @@ -0,0 +1,122 @@ +//########################################################################### +// +// FILE: hw_dac.h +// +// TITLE: Definitions for the DAC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DAC_H +#define HW_DAC_H + +//************************************************************************************************* +// +// The following are defines for the DAC register offsets +// +//************************************************************************************************* +#define DAC_O_REV 0x0U // DAC Revision Register +#define DAC_O_CTL 0x1U // DAC Control Register +#define DAC_O_VALA 0x2U // DAC Value Register - Active +#define DAC_O_VALS 0x3U // DAC Value Register - Shadow +#define DAC_O_OUTEN 0x4U // DAC Output Enable Register +#define DAC_O_LOCK 0x5U // DAC Lock Register +#define DAC_O_TRIM 0x6U // DAC Trim Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACREV register +// +//************************************************************************************************* +#define DAC_REV_REV_S 0U +#define DAC_REV_REV_M 0xFFU // DAC Revision Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACCTL register +// +//************************************************************************************************* +#define DAC_CTL_DACREFSEL 0x1U // DAC Reference Select +#define DAC_CTL_LOADMODE 0x4U // DACVALA Load Mode +#define DAC_CTL_SYNCSEL_S 4U +#define DAC_CTL_SYNCSEL_M 0xF0U // DAC EPWMSYNCPER Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALA register +// +//************************************************************************************************* +#define DAC_VALA_DACVALA_S 0U +#define DAC_VALA_DACVALA_M 0xFFFU // DAC Active Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALS register +// +//************************************************************************************************* +#define DAC_VALS_DACVALS_S 0U +#define DAC_VALS_DACVALS_M 0xFFFU // DAC Shadow Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACOUTEN register +// +//************************************************************************************************* +#define DAC_OUTEN_DACOUTEN 0x1U // DAC Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLOCK register +// +//************************************************************************************************* +#define DAC_LOCK_DACCTL 0x1U // DAC Control Register Lock +#define DAC_LOCK_DACVAL 0x2U // DAC Value Register Lock +#define DAC_LOCK_DACOUTEN 0x4U // DAC Output Enable Register Lock +#define DAC_LOCK_KEY_S 12U +#define DAC_LOCK_KEY_M 0xF000U // DAC Register Lock Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACTRIM register +// +//************************************************************************************************* +#define DAC_TRIM_OFFSET_TRIM_S 0U +#define DAC_TRIM_OFFSET_TRIM_M 0xFFU // DAC Offset Trim + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_dcsm.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_dcsm.h new file mode 100644 index 0000000..c81bcb1 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_dcsm.h @@ -0,0 +1,442 @@ +//########################################################################### +// +// FILE: hw_dcsm.h +// +// TITLE: Definitions for the DCSM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DCSM_H +#define HW_DCSM_H + +//************************************************************************************************* +// +// The following are defines for the DCSM register offsets +// +//************************************************************************************************* +#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP +#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP +#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP +#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP + +#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP +#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP +#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP +#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP + +#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer +#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock +#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0 +#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1 +#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2 +#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3 +#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register +#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register +#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register +#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register +#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register + +#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer +#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock +#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0 +#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1 +#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2 +#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3 +#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register +#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register +#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register +#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register +#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register + +#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register +#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register +#define DCSM_O_RAMSTAT 0x4U // RAM Status Register + + + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock. +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z1_BOOTCTRL_KEY_S 0U +#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z1_BOOTCTRL_BMODE_S 8U +#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_CR register +// +//************************************************************************************************* +#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock. +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z2_BOOTCTRL_KEY_S 0U +#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z2_BOOTCTRL_BMODE_S 8U +#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_CR register +// +//************************************************************************************************* +#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FLSEM register +// +//************************************************************************************************* +#define DCSM_FLSEM_SEM_S 0U +#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit +#define DCSM_FLSEM_KEY_S 8U +#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECTSTAT register +// +//************************************************************************************************* +#define DCSM_SECTSTAT_STATUS_SECTA_S 0U +#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A +#define DCSM_SECTSTAT_STATUS_SECTB_S 2U +#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B +#define DCSM_SECTSTAT_STATUS_SECTC_S 4U +#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C +#define DCSM_SECTSTAT_STATUS_SECTD_S 6U +#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D +#define DCSM_SECTSTAT_STATUS_SECTE_S 8U +#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E +#define DCSM_SECTSTAT_STATUS_SECTF_S 10U +#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F +#define DCSM_SECTSTAT_STATUS_SECTG_S 12U +#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G +#define DCSM_SECTSTAT_STATUS_SECTH_S 14U +#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H +#define DCSM_SECTSTAT_STATUS_SECTI_S 16U +#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I +#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U +#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J +#define DCSM_SECTSTAT_STATUS_SECTK_S 20U +#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K +#define DCSM_SECTSTAT_STATUS_SECTL_S 22U +#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L +#define DCSM_SECTSTAT_STATUS_SECTM_S 24U +#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M +#define DCSM_SECTSTAT_STATUS_SECTN_S 26U +#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMSTAT register +// +//************************************************************************************************* +#define DCSM_RAMSTAT_STATUS_RAM0_S 0U +#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0 +#define DCSM_RAMSTAT_STATUS_RAM1_S 2U +#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1 +#define DCSM_RAMSTAT_STATUS_RAM2_S 4U +#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2 +#define DCSM_RAMSTAT_STATUS_RAM3_S 6U +#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3 +#define DCSM_RAMSTAT_STATUS_RAM4_S 8U +#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4 +#define DCSM_RAMSTAT_STATUS_RAM5_S 10U +#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5 +#define DCSM_RAMSTAT_STATUS_RAM6_S 12U +#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0 +#define DCSM_RAMSTAT_STATUS_RAM7_S 14U +#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1 +#define DCSM_RAMSTAT_STATUS_CLA1_S 28U +#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1 + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_dma.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_dma.h new file mode 100644 index 0000000..1ecd1d7 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_dma.h @@ -0,0 +1,165 @@ +//########################################################################### +// +// FILE: hw_dma.h +// +// TITLE: Definitions for the DMA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DMA_H +#define HW_DMA_H + +//************************************************************************************************* +// +// The following are defines for the DMA register offsets +// +//************************************************************************************************* +#define DMA_O_CTRL 0x0U // DMA Control Register +#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register +#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register +#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register + +#define DMA_O_MODE 0x0U // Mode Register +#define DMA_O_CONTROL 0x1U // Control Register +#define DMA_O_BURST_SIZE 0x2U // Burst Size Register +#define DMA_O_BURST_COUNT 0x3U // Burst Count Register +#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register +#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register +#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register +#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register +#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register +#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register +#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register +#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register +#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register +#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register +#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register +#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register +#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register +#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register +#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register +#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register +#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register +#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register +#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register +#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACTRL register +// +//************************************************************************************************* +#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit +#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEBUGCTRL register +// +//************************************************************************************************* +#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYCTRL1 register +// +//************************************************************************************************* +#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYSTAT register +// +//************************************************************************************************* +#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U +#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MODE register +// +//************************************************************************************************* +#define DMA_MODE_PERINTSEL_S 0U +#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select +#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable +#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable +#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode +#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit +#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit +#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit +#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CONTROL register +// +//************************************************************************************************* +#define DMA_CONTROL_RUN 0x1U // Run Bit +#define DMA_CONTROL_HALT 0x2U // Halt Bit +#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit +#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit +#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit +#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit +#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit +#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit +#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit +#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit +#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_SIZE register +// +//************************************************************************************************* +#define DMA_BURST_SIZE_BURSTSIZE_S 0U +#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_COUNT register +// +//************************************************************************************************* +#define DMA_BURST_COUNT_BURSTCOUNT_S 0U +#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_ecap.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_ecap.h new file mode 100644 index 0000000..48981d6 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_ecap.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_ecap.h +// +// TITLE: Definitions for the ECAP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ECAP_H +#define HW_ECAP_H + +//************************************************************************************************* +// +// The following are defines for the ECAP register offsets +// +//************************************************************************************************* +#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter +#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register +#define ECAP_O_CAP1 0x4U // Capture 1 Register +#define ECAP_O_CAP2 0x6U // Capture 2 Register +#define ECAP_O_CAP3 0x8U // Capture 3 Register +#define ECAP_O_CAP4 0xAU // Capture 4 Register +#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1 +#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2 +#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register +#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register +#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register +#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL1 register +// +//************************************************************************************************* +#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select +#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1 +#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select +#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2 +#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select +#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3 +#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select +#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4 +#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event +#define ECAP_ECCTL1_PRESCALE_S 9U +#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select +#define ECAP_ECCTL1_FREE_SOFT_S 14U +#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL2 register +// +//************************************************************************************************* +#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot +#define ECAP_ECCTL2_STOP_WRAP_S 1U +#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous +#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm +#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop +#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select +#define ECAP_ECCTL2_SYNCO_SEL_S 6U +#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode +#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync +#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select +#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECEINT register +// +//************************************************************************************************* +#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable +#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable +#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable +#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable +#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFLG register +// +//************************************************************************************************* +#define ECAP_ECFLG_INT 0x1U // Global Flag +#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag +#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag +#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag +#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag +#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag +#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag +#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCLR register +// +//************************************************************************************************* +#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear +#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear +#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear +#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear +#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear +#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear +#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear +#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFRC register +// +//************************************************************************************************* +#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt +#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt +#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt +#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt +#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt +#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt +#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_emif.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_emif.h new file mode 100644 index 0000000..9f1401e --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_emif.h @@ -0,0 +1,259 @@ +//########################################################################### +// +// FILE: hw_emif.h +// +// TITLE: Definitions for the EMIF registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EMIF_H +#define HW_EMIF_H + +//************************************************************************************************* +// +// The following are defines for the EMIF register offsets +// +//************************************************************************************************* +#define EMIF_O_RCSR 0x0U // Revision Code and Status Register +#define EMIF_O_ASYNC_WCCR 0x2U // Async Wait Cycle Config Register +#define EMIF_O_SDRAM_CR 0x4U // SDRAM (EMxCS0n) Config Register +#define EMIF_O_SDRAM_RCR 0x6U // SDRAM Refresh Control Register +#define EMIF_O_ASYNC_CS2_CR 0x8U // Async 1 (EMxCS2n) Config Register +#define EMIF_O_ASYNC_CS3_CR 0xAU // Async 2 (EMxCS3n) Config Register +#define EMIF_O_ASYNC_CS4_CR 0xCU // Async 3 (EMxCS4n) Config Register +#define EMIF_O_SDRAM_TR 0x10U // SDRAM Timing Register +#define EMIF_O_TOTAL_SDRAM_AR 0x18U // Total SDRAM Accesses Register +#define EMIF_O_TOTAL_SDRAM_ACTR 0x1AU // Total SDRAM Activate Register +#define EMIF_O_SDR_EXT_TMNG 0x1EU // SDRAM SR/PD Exit Timing Register +#define EMIF_O_INT_RAW 0x20U // Interrupt Raw Register +#define EMIF_O_INT_MSK 0x22U // Interrupt Masked Register +#define EMIF_O_INT_MSK_SET 0x24U // Interrupt Mask Set Register +#define EMIF_O_INT_MSK_CLR 0x26U // Interrupt Mask Clear Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCSR register +// +//************************************************************************************************* +#define EMIF_RCSR_MINOR_REVISION_S 0U +#define EMIF_RCSR_MINOR_REVISION_M 0xFFU // Minor Revision. +#define EMIF_RCSR_MAJOR_REVISION_S 8U +#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00U // Major Revision. +#define EMIF_RCSR_MODULE_ID_S 16U +#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000U // EMIF module ID. +#define EMIF_RCSR_FR 0x40000000U // EMIF is running in full rate or half rate. +#define EMIF_RCSR_BE 0x80000000U // EMIF endian mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_WCCR register +// +//************************************************************************************************* +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0U +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFFU // Maximum Extended Wait cycles. +#define EMIF_ASYNC_WCCR_WP0 0x10000000U // Polarity for EMxWAIT. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_CR register +// +//************************************************************************************************* +#define EMIF_SDRAM_CR_PAGESIGE_S 0U +#define EMIF_SDRAM_CR_PAGESIGE_M 0x7U // Page Size. +#define EMIF_SDRAM_CR_IBANK_S 4U +#define EMIF_SDRAM_CR_IBANK_M 0x70U // Internal Bank setup of SDRAM devices. +#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100U // Bits 11 to 9 are writable only if this bit + // is set. +#define EMIF_SDRAM_CR_CL_S 9U +#define EMIF_SDRAM_CR_CL_M 0xE00U // CAS Latency. +#define EMIF_SDRAM_CR_NM 0x4000U // Narrow Mode. +#define EMIF_SDRAM_CR_PDWR 0x20000000U // Perform refreshes during Power Down. +#define EMIF_SDRAM_CR_PD 0x40000000U // Power Down. +#define EMIF_SDRAM_CR_SR 0x80000000U // Self Refresh. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_RCR register +// +//************************************************************************************************* +#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0U +#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFFU // Refresh Rate. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS2_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS2_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS2_CR_TA_S 2U +#define EMIF_ASYNC_CS2_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS2_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS3_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS3_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS3_CR_TA_S 2U +#define EMIF_ASYNC_CS3_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS3_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS4_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS4_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS4_CR_TA_S 2U +#define EMIF_ASYNC_CS4_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS4_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_TR register +// +//************************************************************************************************* +#define EMIF_SDRAM_TR_T_RRD_S 4U +#define EMIF_SDRAM_TR_T_RRD_M 0x70U // Activate to Activate timing for different bank. +#define EMIF_SDRAM_TR_T_RC_S 8U +#define EMIF_SDRAM_TR_T_RC_M 0xF00U // Activate to Activate timing . +#define EMIF_SDRAM_TR_T_RAS_S 12U +#define EMIF_SDRAM_TR_T_RAS_M 0xF000U // Activate to Precharge timing. +#define EMIF_SDRAM_TR_T_WR_S 16U +#define EMIF_SDRAM_TR_T_WR_M 0x70000U // Last Write to Precharge timing. +#define EMIF_SDRAM_TR_T_RCD_S 20U +#define EMIF_SDRAM_TR_T_RCD_M 0x700000U // Activate to Read/Write timing. +#define EMIF_SDRAM_TR_T_RP_S 24U +#define EMIF_SDRAM_TR_T_RP_M 0x7000000U // Precharge to Activate/Refresh timing. +#define EMIF_SDRAM_TR_T_RFC_S 27U +#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000U // Refresh/Load Mode to Refresh/Activate timing + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDR_EXT_TMNG register +// +//************************************************************************************************* +#define EMIF_SDR_EXT_TMNG_T_XS_S 0U +#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1FU // Self Refresh exit to new command timing. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_RAW register +// +//************************************************************************************************* +#define EMIF_INT_RAW_AT 0x1U // Asynchronous Timeout. +#define EMIF_INT_RAW_LT 0x2U // Line Trap. +#define EMIF_INT_RAW_WR_S 2U +#define EMIF_INT_RAW_WR_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK register +// +//************************************************************************************************* +#define EMIF_INT_MSK_AT_MASKED 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_LT_MASKED 0x2U // Line Trap. +#define EMIF_INT_MSK_WR_MASKED_S 2U +#define EMIF_INT_MSK_WR_MASKED_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_SET register +// +//************************************************************************************************* +#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2U // Line Trap. +#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2U +#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_CLR register +// +//************************************************************************************************* +#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2U // Line Trap. +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2U +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3CU // Wait Rise. + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_epwm.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_epwm.h new file mode 100644 index 0000000..6f7bf2d --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_epwm.h @@ -0,0 +1,1050 @@ +//########################################################################### +// +// FILE: hw_epwm.h +// +// TITLE: Definitions for the EPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWM_H +#define HW_EPWM_H + +//************************************************************************************************* +// +// The following are defines for the EPWM register offsets +// +//************************************************************************************************* +#define EPWM_O_TBCTL 0x0U // Time Base Control Register +#define EPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define EPWM_O_TBCTR 0x4U // Time Base Counter Register +#define EPWM_O_TBSTS 0x5U // Time Base Status Register +#define EPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define EPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define EPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define EPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define EPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define EPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define EPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define EPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define EPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define EPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define EPWM_O_HRPWR 0x21U // HRPWM Power Register +#define EPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define EPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define EPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define EPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define EPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define EPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define EPWM_O_XLINK 0x38U // EPWMx Link Register +#define EPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define EPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define EPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define EPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define EPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define EPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define EPWM_O_TBPHS 0x60U // Time Base Phase High +#define EPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define EPWM_O_TBPRD 0x63U // Time Base Period Register +#define EPWM_O_CMPA 0x6AU // Counter Compare A Register +#define EPWM_O_CMPB 0x6CU // Compare B Register +#define EPWM_O_CMPC 0x6FU // Counter Compare C Register +#define EPWM_O_CMPD 0x71U // Counter Compare D Register +#define EPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define EPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define EPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define EPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define EPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define EPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define EPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define EPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define EPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define EPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define EPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define EPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define EPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define EPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define EPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define EPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define EPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define EPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define EPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define EPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define EPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define EPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define EPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define EPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define EPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define EPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define EPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define EPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define EPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define EPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define EPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define EPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define EPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define EPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define EPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define EPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define EPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define EPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define EPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define EPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define EPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define EPWM_TBCTL_CTRMODE_S 0U +#define EPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define EPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define EPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define EPWM_TBCTL_SYNCOSEL_S 4U +#define EPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define EPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define EPWM_TBCTL_HSPCLKDIV_S 7U +#define EPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define EPWM_TBCTL_CLKDIV_S 10U +#define EPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define EPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define EPWM_TBCTL_FREE_SOFT_S 14U +#define EPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define EPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define EPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define EPWM_TBCTL2_SYNCOSELX_S 12U +#define EPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define EPWM_TBCTL2_PRDLDSYNC_S 14U +#define EPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define EPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define EPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define EPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define EPWM_CMPCTL_LOADAMODE_S 0U +#define EPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define EPWM_CMPCTL_LOADBMODE_S 2U +#define EPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define EPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define EPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define EPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define EPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define EPWM_CMPCTL_LOADASYNC_S 10U +#define EPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define EPWM_CMPCTL_LOADBSYNC_S 12U +#define EPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define EPWM_CMPCTL2_LOADCMODE_S 0U +#define EPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define EPWM_CMPCTL2_LOADDMODE_S 2U +#define EPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define EPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define EPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define EPWM_CMPCTL2_LOADCSYNC_S 10U +#define EPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define EPWM_CMPCTL2_LOADDSYNC_S 12U +#define EPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define EPWM_DBCTL_OUT_MODE_S 0U +#define EPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define EPWM_DBCTL_POLSEL_S 2U +#define EPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define EPWM_DBCTL_IN_MODE_S 4U +#define EPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define EPWM_DBCTL_LOADREDMODE_S 6U +#define EPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define EPWM_DBCTL_LOADFEDMODE_S 8U +#define EPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define EPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define EPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define EPWM_DBCTL_OUTSWAP_S 12U +#define EPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define EPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define EPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define EPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define EPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define EPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define EPWM_AQCTL_LDAQAMODE_S 0U +#define EPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define EPWM_AQCTL_LDAQBMODE_S 2U +#define EPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define EPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define EPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define EPWM_AQCTL_LDAQASYNC_S 8U +#define EPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define EPWM_AQCTL_LDAQBSYNC_S 10U +#define EPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define EPWM_AQTSRCSEL_T1SEL_S 0U +#define EPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define EPWM_AQTSRCSEL_T2SEL_S 4U +#define EPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define EPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define EPWM_PCCTL_OSHTWTH_S 1U +#define EPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define EPWM_PCCTL_CHPFREQ_S 5U +#define EPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define EPWM_PCCTL_CHPDUTY_S 8U +#define EPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define EPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define EPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define EPWM_VCAPCTL_TRIGSEL_S 2U +#define EPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define EPWM_VCAPCTL_VDELAYDIV_S 7U +#define EPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define EPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define EPWM_VCNTCFG_STARTEDGE_S 0U +#define EPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define EPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define EPWM_VCNTCFG_STOPEDGE_S 8U +#define EPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define EPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define EPWM_HRCNFG_EDGMODE_S 0U +#define EPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define EPWM_HRCNFG_HRLOAD_S 3U +#define EPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define EPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define EPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define EPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define EPWM_HRCNFG_EDGMODEB_S 8U +#define EPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define EPWM_HRCNFG_HRLOADB_S 11U +#define EPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define EPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define EPWM_HRMSTEP_HRMSTEP_S 0U +#define EPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define EPWM_HRCNFG2_EDGMODEDB_S 0U +#define EPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define EPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define EPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define EPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define EPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define EPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define EPWM_HRPCTL_PWMSYNCSELX_S 4U +#define EPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define EPWM_TRREM_TRREM_S 0U +#define EPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define EPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define EPWM_GLDCTL_GLDMODE_S 1U +#define EPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define EPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define EPWM_GLDCTL_GLDPRD_S 7U +#define EPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define EPWM_GLDCTL_GLDCNT_S 10U +#define EPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define EPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define EPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define EPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define EPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define EPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define EPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define EPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define EPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define EPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define EPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define EPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define EPWM_XLINK_TBPRDLINK_S 0U +#define EPWM_XLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define EPWM_XLINK_CMPALINK_S 4U +#define EPWM_XLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define EPWM_XLINK_CMPBLINK_S 8U +#define EPWM_XLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define EPWM_XLINK_CMPCLINK_S 12U +#define EPWM_XLINK_CMPCLINK_M 0xF000U // CMPC Link +#define EPWM_XLINK_CMPDLINK_S 16U +#define EPWM_XLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define EPWM_XLINK_GLDCTL2LINK_S 28U +#define EPWM_XLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define EPWM_AQCTLA_ZRO_S 0U +#define EPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLA_PRD_S 2U +#define EPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLA_CAU_S 4U +#define EPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLA_CAD_S 6U +#define EPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLA_CBU_S 8U +#define EPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLA_CBD_S 10U +#define EPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define EPWM_AQCTLA2_T1U_S 0U +#define EPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLA2_T1D_S 2U +#define EPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLA2_T2U_S 4U +#define EPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLA2_T2D_S 6U +#define EPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define EPWM_AQCTLB_ZRO_S 0U +#define EPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLB_PRD_S 2U +#define EPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLB_CAU_S 4U +#define EPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLB_CAD_S 6U +#define EPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLB_CBU_S 8U +#define EPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLB_CBD_S 10U +#define EPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define EPWM_AQCTLB2_T1U_S 0U +#define EPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLB2_T1D_S 2U +#define EPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLB2_T2U_S 4U +#define EPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLB2_T2D_S 6U +#define EPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define EPWM_AQSFRC_ACTSFA_S 0U +#define EPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define EPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define EPWM_AQSFRC_ACTSFB_S 3U +#define EPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define EPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define EPWM_AQSFRC_RLDCSF_S 6U +#define EPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define EPWM_AQCSFRC_CSFA_S 0U +#define EPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define EPWM_AQCSFRC_CSFB_S 2U +#define EPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define EPWM_DBREDHR_DBREDHR_S 9U +#define EPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define EPWM_DBRED_DBRED_S 0U +#define EPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define EPWM_DBFEDHR_DBFEDHR_S 9U +#define EPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define EPWM_DBFED_DBFED_S 0U +#define EPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define EPWM_TBPHS_TBPHSHR_S 0U +#define EPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define EPWM_TBPHS_TBPHS_S 16U +#define EPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define EPWM_CMPA_CMPAHR_S 0U +#define EPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define EPWM_CMPA_CMPA_S 16U +#define EPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define EPWM_CMPB_CMPBHR_S 0U +#define EPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define EPWM_CMPB_CMPB_S 16U +#define EPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define EPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define EPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define EPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define EPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define EPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define EPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define EPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define EPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define EPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define EPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define EPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define EPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define EPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define EPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define EPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define EPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define EPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define EPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define EPWM_TZDCSEL_DCAEVT1_S 0U +#define EPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define EPWM_TZDCSEL_DCAEVT2_S 3U +#define EPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define EPWM_TZDCSEL_DCBEVT1_S 6U +#define EPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define EPWM_TZDCSEL_DCBEVT2_S 9U +#define EPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define EPWM_TZCTL_TZA_S 0U +#define EPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define EPWM_TZCTL_TZB_S 2U +#define EPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define EPWM_TZCTL_DCAEVT1_S 4U +#define EPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define EPWM_TZCTL_DCAEVT2_S 6U +#define EPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define EPWM_TZCTL_DCBEVT1_S 8U +#define EPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define EPWM_TZCTL_DCBEVT2_S 10U +#define EPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define EPWM_TZCTL2_TZAU_S 0U +#define EPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define EPWM_TZCTL2_TZAD_S 3U +#define EPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define EPWM_TZCTL2_TZBU_S 6U +#define EPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define EPWM_TZCTL2_TZBD_S 9U +#define EPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define EPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define EPWM_TZCTLDCA_DCAEVT1U_S 0U +#define EPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT1D_S 3U +#define EPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCA_DCAEVT2U_S 6U +#define EPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT2D_S 9U +#define EPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define EPWM_TZCTLDCB_DCBEVT1U_S 0U +#define EPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT1D_S 3U +#define EPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCB_DCBEVT2U_S 6U +#define EPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT2D_S 9U +#define EPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define EPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define EPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define EPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define EPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define EPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define EPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define EPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define EPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define EPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define EPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define EPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define EPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define EPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define EPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define EPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define EPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define EPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define EPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define EPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define EPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event 2 +#define EPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define EPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define EPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define EPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define EPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define EPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define EPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define EPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event 1 +#define EPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define EPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define EPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define EPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define EPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define EPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define EPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define EPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define EPWM_TZCLR_CBCPULSE_S 14U +#define EPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define EPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define EPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define EPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define EPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define EPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define EPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define EPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define EPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define EPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define EPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define EPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define EPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define EPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define EPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define EPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define EPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define EPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define EPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define EPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define EPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define EPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define EPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define EPWM_ETSEL_INTSEL_S 0U +#define EPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define EPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define EPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define EPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define EPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define EPWM_ETSEL_SOCASEL_S 8U +#define EPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define EPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define EPWM_ETSEL_SOCBSEL_S 12U +#define EPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define EPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define EPWM_ETPS_INTPRD_S 0U +#define EPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define EPWM_ETPS_INTCNT_S 2U +#define EPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define EPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define EPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define EPWM_ETPS_SOCAPRD_S 8U +#define EPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define EPWM_ETPS_SOCACNT_S 10U +#define EPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define EPWM_ETPS_SOCBPRD_S 12U +#define EPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define EPWM_ETPS_SOCBCNT_S 14U +#define EPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define EPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define EPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define EPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define EPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define EPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define EPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define EPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define EPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define EPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define EPWM_ETINTPS_INTPRD2_S 0U +#define EPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define EPWM_ETINTPS_INTCNT2_S 4U +#define EPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define EPWM_ETSOCPS_SOCAPRD2_S 0U +#define EPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define EPWM_ETSOCPS_SOCACNT2_S 4U +#define EPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define EPWM_ETSOCPS_SOCBPRD2_S 8U +#define EPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define EPWM_ETSOCPS_SOCBCNT2_S 12U +#define EPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define EPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define EPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define EPWM_ETCNTINIT_INTINIT_S 0U +#define EPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCAINIT_S 4U +#define EPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCBINIT_S 8U +#define EPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define EPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define EPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define EPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define EPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define EPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define EPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define EPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define EPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define EPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define EPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define EPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define EPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define EPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define EPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define EPWM_DCFCTL_SRCSEL_S 0U +#define EPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define EPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define EPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define EPWM_DCFCTL_PULSESEL_S 4U +#define EPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define EPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define EPWM_DCFCTL_EDGEMODE_S 8U +#define EPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define EPWM_DCFCTL_EDGECOUNT_S 10U +#define EPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define EPWM_DCFCTL_EDGESTATUS_S 13U +#define EPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define EPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define EPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define EPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define EPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define EPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_epwmxbar.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_epwmxbar.h new file mode 100644 index 0000000..5fb6058 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_epwmxbar.h @@ -0,0 +1,1192 @@ +//########################################################################### +// +// FILE: hw_epwmxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWMXBAR_H +#define HW_EPWMXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_TRIP4MUX0TO15CFG 0x0U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP4MUX16TO31CFG 0x2U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP5MUX0TO15CFG 0x4U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP5MUX16TO31CFG 0x6U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP7MUX0TO15CFG 0x8U // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP7MUX16TO31CFG 0xAU // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP8MUX0TO15CFG 0xCU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP8MUX16TO31CFG 0xEU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP9MUX0TO15CFG 0x10U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP9MUX16TO31CFG 0x12U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP10MUX0TO15CFG 0x14U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP10MUX16TO31CFG 0x16U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP11MUX0TO15CFG 0x18U // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP11MUX16TO31CFG 0x1AU // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP12MUX0TO15CFG 0x1CU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP12MUX16TO31CFG 0x1EU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP4MUXENABLE 0x20U // ePWM XBAR Mux Enable for TRIP4 +#define XBAR_O_TRIP5MUXENABLE 0x22U // ePWM XBAR Mux Enable for TRIP5 +#define XBAR_O_TRIP7MUXENABLE 0x24U // ePWM XBAR Mux Enable for TRIP7 +#define XBAR_O_TRIP8MUXENABLE 0x26U // ePWM XBAR Mux Enable for TRIP8 +#define XBAR_O_TRIP9MUXENABLE 0x28U // ePWM XBAR Mux Enable for TRIP9 +#define XBAR_O_TRIP10MUXENABLE 0x2AU // ePWM XBAR Mux Enable for TRIP10 +#define XBAR_O_TRIP11MUXENABLE 0x2CU // ePWM XBAR Mux Enable for TRIP11 +#define XBAR_O_TRIP12MUXENABLE 0x2EU // ePWM XBAR Mux Enable for TRIP12 +#define XBAR_O_TRIPOUTINV 0x38U // ePWM XBAR Output Inversion Register +#define XBAR_O_TRIPLOCK 0x3EU // ePWM XBAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP4 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP5 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP7 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP8 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP9MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP9MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP9MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP9MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP9MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP9MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP9MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP9MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP9MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP9MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP9MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP9MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP9MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP9MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP9MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP9MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP9MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP9MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP9MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP9MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP9MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP9MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP9MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP9MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP9MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP9MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP9MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP9MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP9MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP9MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP9MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP9MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP9 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP10MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP10MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP10MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP10MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP10MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP10MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP10MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP10MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP10MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP10MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP10MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP10MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP10MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP10MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP10MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP10MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP10MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP10MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP10MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP10MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP10MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP10MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP10MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP10MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP10MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP10MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP10MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP10MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP10MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP10MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP10MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP10MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP11MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP11MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP11MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP11MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP11MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP11MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP11MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP11MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP11MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP11MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP11MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP11MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP11MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP11MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP11MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP11MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP11MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP11MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP11MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP11MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP11MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP11MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP11MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP11MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP11MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP11MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP11MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP11MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP11MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP11MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP11MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP11MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP12MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP12MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP12MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP12MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP12MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP12MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP12MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP12MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP12MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP12MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP12MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP12MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP12MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP12MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP12MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP12MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP12MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP12MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP12MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP12MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP12MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP12MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP12MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP12MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP12MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP12MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP12MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP12MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP12MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP12MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP12MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP12MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP4MUXENABLE_MUX0 0x1U // mux0 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP5MUXENABLE_MUX0 0x1U // mux0 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP7MUXENABLE_MUX0 0x1U // mux0 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP8MUXENABLE_MUX0 0x1U // mux0 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP9MUXENABLE_MUX0 0x1U // mux0 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP10MUXENABLE_MUX0 0x1U // mux0 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP10 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP11MUXENABLE_MUX0 0x1U // mux0 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP11 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP12MUXENABLE_MUX0 0x1U // mux0 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPOUTINV register +// +//************************************************************************************************* +#define XBAR_TRIPOUTINV_TRIP4 0x1U // Selects polarity for TRIP4 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP5 0x2U // Selects polarity for TRIP5 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP7 0x4U // Selects polarity for TRIP7 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP8 0x8U // Selects polarity for TRIP8 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP9 0x10U // Selects polarity for TRIP9 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP10 0x20U // Selects polarity for TRIP10 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP11 0x40U // Selects polarity for TRIP11 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP12 0x80U // Selects polarity for TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPLOCK register +// +//************************************************************************************************* +#define XBAR_TRIPLOCK_LOCK 0x1U // Locks the configuration for EPWM-XBAR +#define XBAR_TRIPLOCK_KEY_S 16U +#define XBAR_TRIPLOCK_KEY_M 0xFFFF0000U // Write protection KEY + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_eqep.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_eqep.h new file mode 100644 index 0000000..7dbb33a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_eqep.h @@ -0,0 +1,225 @@ +//########################################################################### +// +// FILE: hw_eqep.h +// +// TITLE: Definitions for the EQEP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EQEP_H +#define HW_EQEP_H + +//************************************************************************************************* +// +// The following are defines for the EQEP register offsets +// +//************************************************************************************************* +#define EQEP_O_QPOSCNT 0x0U // Position Counter +#define EQEP_O_QPOSINIT 0x2U // Position Counter Init +#define EQEP_O_QPOSMAX 0x4U // Maximum Position Count +#define EQEP_O_QPOSCMP 0x6U // Position Compare +#define EQEP_O_QPOSILAT 0x8U // Index Position Latch +#define EQEP_O_QPOSSLAT 0xAU // Strobe Position Latch +#define EQEP_O_QPOSLAT 0xCU // Position Latch +#define EQEP_O_QUTMR 0xEU // QEP Unit Timer +#define EQEP_O_QUPRD 0x10U // QEP Unit Period +#define EQEP_O_QWDTMR 0x12U // QEP Watchdog Timer +#define EQEP_O_QWDPRD 0x13U // QEP Watchdog Period +#define EQEP_O_QDECCTL 0x14U // Quadrature Decoder Control +#define EQEP_O_QEPCTL 0x15U // QEP Control +#define EQEP_O_QCAPCTL 0x16U // Qaudrature Capture Control +#define EQEP_O_QPOSCTL 0x17U // Position Compare Control +#define EQEP_O_QEINT 0x18U // QEP Interrupt Control +#define EQEP_O_QFLG 0x19U // QEP Interrupt Flag +#define EQEP_O_QCLR 0x1AU // QEP Interrupt Clear +#define EQEP_O_QFRC 0x1BU // QEP Interrupt Force +#define EQEP_O_QEPSTS 0x1CU // QEP Status +#define EQEP_O_QCTMR 0x1DU // QEP Capture Timer +#define EQEP_O_QCPRD 0x1EU // QEP Capture Period +#define EQEP_O_QCTMRLAT 0x1FU // QEP Capture Latch +#define EQEP_O_QCPRDLAT 0x20U // QEP Capture Period Latch + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QDECCTL register +// +//************************************************************************************************* +#define EQEP_QDECCTL_QSP 0x20U // QEPS input polarity +#define EQEP_QDECCTL_QIP 0x40U // QEPI input polarity +#define EQEP_QDECCTL_QBP 0x80U // QEPB input polarity +#define EQEP_QDECCTL_QAP 0x100U // QEPA input polarity +#define EQEP_QDECCTL_IGATE 0x200U // Index pulse gating option +#define EQEP_QDECCTL_SWAP 0x400U // CLK/DIR Signal Source for Position Counter +#define EQEP_QDECCTL_XCR 0x800U // External Clock Rate +#define EQEP_QDECCTL_SPSEL 0x1000U // Sync output pin selection +#define EQEP_QDECCTL_SOEN 0x2000U // Sync output-enable +#define EQEP_QDECCTL_QSRC_S 14U +#define EQEP_QDECCTL_QSRC_M 0xC000U // Position-counter source selection + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPCTL register +// +//************************************************************************************************* +#define EQEP_QEPCTL_WDE 0x1U // QEP watchdog enable +#define EQEP_QEPCTL_UTE 0x2U // QEP unit timer enable +#define EQEP_QEPCTL_QCLM 0x4U // QEP capture latch mode +#define EQEP_QEPCTL_QPEN 0x8U // Quadrature postotion counter enable +#define EQEP_QEPCTL_IEL_S 4U +#define EQEP_QEPCTL_IEL_M 0x30U // Index event latch +#define EQEP_QEPCTL_SEL 0x40U // Strobe event latch +#define EQEP_QEPCTL_SWI 0x80U // Software init position counter +#define EQEP_QEPCTL_IEI_S 8U +#define EQEP_QEPCTL_IEI_M 0x300U // Index event init of position count +#define EQEP_QEPCTL_SEI_S 10U +#define EQEP_QEPCTL_SEI_M 0xC00U // Strobe event init +#define EQEP_QEPCTL_PCRM_S 12U +#define EQEP_QEPCTL_PCRM_M 0x3000U // Postion counter reset +#define EQEP_QEPCTL_FREE_SOFT_S 14U +#define EQEP_QEPCTL_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCAPCTL register +// +//************************************************************************************************* +#define EQEP_QCAPCTL_UPPS_S 0U +#define EQEP_QCAPCTL_UPPS_M 0xFU // Unit position event prescaler +#define EQEP_QCAPCTL_CCPS_S 4U +#define EQEP_QCAPCTL_CCPS_M 0x70U // eQEP capture timer clock prescaler +#define EQEP_QCAPCTL_CEN 0x8000U // Enable eQEP capture + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QPOSCTL register +// +//************************************************************************************************* +#define EQEP_QPOSCTL_PCSPW_S 0U +#define EQEP_QPOSCTL_PCSPW_M 0xFFFU // Position compare sync pulse width +#define EQEP_QPOSCTL_PCE 0x1000U // Position compare enable/disable +#define EQEP_QPOSCTL_PCPOL 0x2000U // Polarity of sync output +#define EQEP_QPOSCTL_PCLOAD 0x4000U // Position compare of shadow load +#define EQEP_QPOSCTL_PCSHDW 0x8000U // Position compare of shadow enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEINT register +// +//************************************************************************************************* +#define EQEP_QEINT_PCE 0x2U // Position counter error interrupt enable +#define EQEP_QEINT_QPE 0x4U // Quadrature phase error interrupt enable +#define EQEP_QEINT_QDC 0x8U // Quadrature direction change interrupt enable +#define EQEP_QEINT_WTO 0x10U // Watchdog time out interrupt enable +#define EQEP_QEINT_PCU 0x20U // Position counter underflow interrupt enable +#define EQEP_QEINT_PCO 0x40U // Position counter overflow interrupt enable +#define EQEP_QEINT_PCR 0x80U // Position-compare ready interrupt enable +#define EQEP_QEINT_PCM 0x100U // Position-compare match interrupt enable +#define EQEP_QEINT_SEL 0x200U // Strobe event latch interrupt enable +#define EQEP_QEINT_IEL 0x400U // Index event latch interrupt enable +#define EQEP_QEINT_UTO 0x800U // Unit time out interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFLG register +// +//************************************************************************************************* +#define EQEP_QFLG_INT 0x1U // Global interrupt status flag +#define EQEP_QFLG_PCE 0x2U // Position counter error interrupt flag +#define EQEP_QFLG_PHE 0x4U // Quadrature phase error interrupt flag +#define EQEP_QFLG_QDC 0x8U // Quadrature direction change interrupt flag +#define EQEP_QFLG_WTO 0x10U // Watchdog timeout interrupt flag +#define EQEP_QFLG_PCU 0x20U // Position counter underflow interrupt flag +#define EQEP_QFLG_PCO 0x40U // Position counter overflow interrupt flag +#define EQEP_QFLG_PCR 0x80U // Position-compare ready interrupt flag +#define EQEP_QFLG_PCM 0x100U // eQEP compare match event interrupt flag +#define EQEP_QFLG_SEL 0x200U // Strobe event latch interrupt flag +#define EQEP_QFLG_IEL 0x400U // Index event latch interrupt flag +#define EQEP_QFLG_UTO 0x800U // Unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCLR register +// +//************************************************************************************************* +#define EQEP_QCLR_INT 0x1U // Global interrupt clear flag +#define EQEP_QCLR_PCE 0x2U // Clear position counter error interrupt flag +#define EQEP_QCLR_PHE 0x4U // Clear quadrature phase error interrupt flag +#define EQEP_QCLR_QDC 0x8U // Clear quadrature direction change interrupt flag +#define EQEP_QCLR_WTO 0x10U // Clear watchdog timeout interrupt flag +#define EQEP_QCLR_PCU 0x20U // Clear position counter underflow interrupt flag +#define EQEP_QCLR_PCO 0x40U // Clear position counter overflow interrupt flag +#define EQEP_QCLR_PCR 0x80U // Clear position-compare ready interrupt flag +#define EQEP_QCLR_PCM 0x100U // Clear eQEP compare match event interrupt flag +#define EQEP_QCLR_SEL 0x200U // Clear strobe event latch interrupt flag +#define EQEP_QCLR_IEL 0x400U // Clear index event latch interrupt flag +#define EQEP_QCLR_UTO 0x800U // Clear unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFRC register +// +//************************************************************************************************* +#define EQEP_QFRC_PCE 0x2U // Force position counter error interrupt +#define EQEP_QFRC_PHE 0x4U // Force quadrature phase error interrupt +#define EQEP_QFRC_QDC 0x8U // Force quadrature direction change interrupt +#define EQEP_QFRC_WTO 0x10U // Force watchdog time out interrupt +#define EQEP_QFRC_PCU 0x20U // Force position counter underflow interrupt +#define EQEP_QFRC_PCO 0x40U // Force position counter overflow interrupt +#define EQEP_QFRC_PCR 0x80U // Force position-compare ready interrupt +#define EQEP_QFRC_PCM 0x100U // Force position-compare match interrupt +#define EQEP_QFRC_SEL 0x200U // Force strobe event latch interrupt +#define EQEP_QFRC_IEL 0x400U // Force index event latch interrupt +#define EQEP_QFRC_UTO 0x800U // Force unit time out interrupt + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPSTS register +// +//************************************************************************************************* +#define EQEP_QEPSTS_PCEF 0x1U // Position counter error flag. +#define EQEP_QEPSTS_FIMF 0x2U // First index marker flag +#define EQEP_QEPSTS_CDEF 0x4U // Capture direction error flag +#define EQEP_QEPSTS_COEF 0x8U // Capture overflow error flag +#define EQEP_QEPSTS_QDLF 0x10U // eQEP direction latch flag +#define EQEP_QEPSTS_QDF 0x20U // Quadrature direction flag +#define EQEP_QEPSTS_FIDF 0x40U // The first index marker +#define EQEP_QEPSTS_UPEVNT 0x80U // Unit position event flag + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_flash.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_flash.h new file mode 100644 index 0000000..73319f1 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_flash.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_flash.h +// +// TITLE: Definitions for the FLASH registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_FLASH_H +#define HW_FLASH_H + +//************************************************************************************************* +// +// The following are defines for the FLASH register offsets +// +//************************************************************************************************* +#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register +#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register +#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register +#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register +#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1 +#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register +#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register + +#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable +#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low +#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High +#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low +#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High +#define FLASH_O_ERR_STATUS 0xAU // Error Status +#define FLASH_O_ERR_POS 0xCU // Error Position +#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear +#define FLASH_O_ERR_CNT 0x10U // Error Control +#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold +#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag +#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear +#define FLASH_O_FDATAH_TEST 0x18U // Data High Test +#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test +#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address +#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address +#define FLASH_O_FECC_CTRL 0x20U // ECC Control +#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High +#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low +#define FLASH_O_FECC_STATUS 0x26U // ECC Status + +#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRDCNTL register +// +//************************************************************************************************* +#define FLASH_FRDCNTL_RWAIT_S 8U +#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBAC register +// +//************************************************************************************************* +#define FLASH_FBAC_VREADST_S 0U +#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBFALLBACK register +// +//************************************************************************************************* +#define FLASH_FBFALLBACK_BNKPWR0_S 0U +#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBPRDY register +// +//************************************************************************************************* +#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State +#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FPAC1 register +// +//************************************************************************************************* +#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode +#define FLASH_FPAC1_PSLEEP_S 16U +#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FMSTAT register +// +//************************************************************************************************* +#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend. +#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend. +#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status +#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status +#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data +#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status +#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status +#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit +#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status +#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRD_INTF_CTRL register +// +//************************************************************************************************* +#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable +#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECC_ENABLE register +// +//************************************************************************************************* +#define FLASH_ECC_ENABLE_ENABLE_S 0U +#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred +#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_POS register +// +//************************************************************************************************* +#define FLASH_ERR_POS_ERR_POS_L_S 0U +#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits +#define FLASH_ERR_POS_ERR_POS_H_S 16U +#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS_CLR register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error + // occurred Clear +#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error + // occurred Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_CNT register +// +//************************************************************************************************* +#define FLASH_ERR_CNT_ERR_CNT_S 0U +#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_THRESHOLD register +// +//************************************************************************************************* +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTFLG register +// +//************************************************************************************************* +#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag +#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTCLR register +// +//************************************************************************************************* +#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear +#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FADDR_TEST register +// +//************************************************************************************************* +#define FLASH_FADDR_TEST_ADDRL_S 3U +#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low +#define FLASH_FADDR_TEST_ADDRH_S 16U +#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_TEST register +// +//************************************************************************************************* +#define FLASH_FECC_TEST_ECC_S 0U +#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_CTRL register +// +//************************************************************************************************* +#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic +#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select +#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_STATUS register +// +//************************************************************************************************* +#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error +#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error +#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U +#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error +#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PUMPREQUEST register +// +//************************************************************************************************* +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between + // CPU1 and CPU2 +#define FLASH_PUMPREQUEST_KEY_S 16U +#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this + // register + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_gpio.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_gpio.h new file mode 100644 index 0000000..0be426d --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_gpio.h @@ -0,0 +1,4018 @@ +//########################################################################### +// +// FILE: hw_gpio.h +// +// TITLE: Definitions for the GPIO registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_GPIO_H +#define HW_GPIO_H + +//************************************************************************************************* +// +// The following are defines for the GPIO register offsets +// +//************************************************************************************************* +#define GPIO_O_GPACTRL 0x0U // GPIO A Qualification Sampling Period Control (GPIO0 to 31) +#define GPIO_O_GPAQSEL1 0x2U // GPIO A Qualifier Select 1 Register (GPIO0 to 15) +#define GPIO_O_GPAQSEL2 0x4U // GPIO A Qualifier Select 2 Register (GPIO16 to 31) +#define GPIO_O_GPAMUX1 0x6U // GPIO A Mux 1 Register (GPIO0 to 15) +#define GPIO_O_GPAMUX2 0x8U // GPIO A Mux 2 Register (GPIO16 to 31) +#define GPIO_O_GPADIR 0xAU // GPIO A Direction Register (GPIO0 to 31) +#define GPIO_O_GPAPUD 0xCU // GPIO A Pull Up Disable Register (GPIO0 to 31) +#define GPIO_O_GPAINV 0x10U // GPIO A Input Polarity Invert Registers (GPIO0 to 31) +#define GPIO_O_GPAODR 0x12U // GPIO A Open Drain Output Register (GPIO0 to GPIO31) +#define GPIO_O_GPAGMUX1 0x20U // GPIO A Peripheral Group Mux (GPIO0 to 15) +#define GPIO_O_GPAGMUX2 0x22U // GPIO A Peripheral Group Mux (GPIO16 to 31) +#define GPIO_O_GPACSEL1 0x28U // GPIO A Core Select Register (GPIO0 to 7) +#define GPIO_O_GPACSEL2 0x2AU // GPIO A Core Select Register (GPIO8 to 15) +#define GPIO_O_GPACSEL3 0x2CU // GPIO A Core Select Register (GPIO16 to 23) +#define GPIO_O_GPACSEL4 0x2EU // GPIO A Core Select Register (GPIO24 to 31) +#define GPIO_O_GPALOCK 0x3CU // GPIO A Lock Configuration Register (GPIO0 to 31) +#define GPIO_O_GPACR 0x3EU // GPIO A Lock Commit Register (GPIO0 to 31) +#define GPIO_O_GPBCTRL 0x40U // GPIO B Qualification Sampling Period Control (GPIO32 to 63) +#define GPIO_O_GPBQSEL1 0x42U // GPIO B Qualifier Select 1 Register (GPIO32 to 47) +#define GPIO_O_GPBQSEL2 0x44U // GPIO B Qualifier Select 2 Register (GPIO48 to 63) +#define GPIO_O_GPBMUX1 0x46U // GPIO B Mux 1 Register (GPIO32 to 47) +#define GPIO_O_GPBMUX2 0x48U // GPIO B Mux 2 Register (GPIO48 to 63) +#define GPIO_O_GPBDIR 0x4AU // GPIO B Direction Register (GPIO32 to 63) +#define GPIO_O_GPBPUD 0x4CU // GPIO B Pull Up Disable Register (GPIO32 to 63) +#define GPIO_O_GPBINV 0x50U // GPIO B Input Polarity Invert Registers (GPIO32 to 63) +#define GPIO_O_GPBODR 0x52U // GPIO B Open Drain Output Register (GPIO32 to GPIO63) +#define GPIO_O_GPBAMSEL 0x54U // GPIO B Analog Mode Select register (GPIO32 to GPIO63) +#define GPIO_O_GPBGMUX1 0x60U // GPIO B Peripheral Group Mux (GPIO32 to 47) +#define GPIO_O_GPBGMUX2 0x62U // GPIO B Peripheral Group Mux (GPIO48 to 63) +#define GPIO_O_GPBCSEL1 0x68U // GPIO B Core Select Register (GPIO32 to 39) +#define GPIO_O_GPBCSEL2 0x6AU // GPIO B Core Select Register (GPIO40 to 47) +#define GPIO_O_GPBCSEL3 0x6CU // GPIO B Core Select Register (GPIO48 to 55) +#define GPIO_O_GPBCSEL4 0x6EU // GPIO B Core Select Register (GPIO56 to 63) +#define GPIO_O_GPBLOCK 0x7CU // GPIO B Lock Configuration Register (GPIO32 to 63) +#define GPIO_O_GPBCR 0x7EU // GPIO B Lock Commit Register (GPIO32 to 63) +#define GPIO_O_GPCCTRL 0x80U // GPIO C Qualification Sampling Period Control (GPIO64 to 95) +#define GPIO_O_GPCQSEL1 0x82U // GPIO C Qualifier Select 1 Register (GPIO64 to 79) +#define GPIO_O_GPCQSEL2 0x84U // GPIO C Qualifier Select 2 Register (GPIO80 to 95) +#define GPIO_O_GPCMUX1 0x86U // GPIO C Mux 1 Register (GPIO64 to 79) +#define GPIO_O_GPCMUX2 0x88U // GPIO C Mux 2 Register (GPIO80 to 95) +#define GPIO_O_GPCDIR 0x8AU // GPIO C Direction Register (GPIO64 to 95) +#define GPIO_O_GPCPUD 0x8CU // GPIO C Pull Up Disable Register (GPIO64 to 95) +#define GPIO_O_GPCINV 0x90U // GPIO C Input Polarity Invert Registers (GPIO64 to 95) +#define GPIO_O_GPCODR 0x92U // GPIO C Open Drain Output Register (GPIO64 to GPIO95) +#define GPIO_O_GPCGMUX1 0xA0U // GPIO C Peripheral Group Mux (GPIO64 to 79) +#define GPIO_O_GPCGMUX2 0xA2U // GPIO C Peripheral Group Mux (GPIO80 to 95) +#define GPIO_O_GPCCSEL1 0xA8U // GPIO C Core Select Register (GPIO64 to 71) +#define GPIO_O_GPCCSEL2 0xAAU // GPIO C Core Select Register (GPIO72 to 79) +#define GPIO_O_GPCCSEL3 0xACU // GPIO C Core Select Register (GPIO80 to 87) +#define GPIO_O_GPCCSEL4 0xAEU // GPIO C Core Select Register (GPIO88 to 95) +#define GPIO_O_GPCLOCK 0xBCU // GPIO C Lock Configuration Register (GPIO64 to 95) +#define GPIO_O_GPCCR 0xBEU // GPIO C Lock Commit Register (GPIO64 to 95) +#define GPIO_O_GPDCTRL 0xC0U // GPIO D Qualification Sampling Period Control (GPIO96 to 127) +#define GPIO_O_GPDQSEL1 0xC2U // GPIO D Qualifier Select 1 Register (GPIO96 to 111) +#define GPIO_O_GPDQSEL2 0xC4U // GPIO D Qualifier Select 2 Register (GPIO112 to 127) +#define GPIO_O_GPDMUX1 0xC6U // GPIO D Mux 1 Register (GPIO96 to 111) +#define GPIO_O_GPDMUX2 0xC8U // GPIO D Mux 2 Register (GPIO112 to 127) +#define GPIO_O_GPDDIR 0xCAU // GPIO D Direction Register (GPIO96 to 127) +#define GPIO_O_GPDPUD 0xCCU // GPIO D Pull Up Disable Register (GPIO96 to 127) +#define GPIO_O_GPDINV 0xD0U // GPIO D Input Polarity Invert Registers (GPIO96 to 127) +#define GPIO_O_GPDODR 0xD2U // GPIO D Open Drain Output Register (GPIO96 to GPIO127) +#define GPIO_O_GPDGMUX1 0xE0U // GPIO D Peripheral Group Mux (GPIO96 to 111) +#define GPIO_O_GPDGMUX2 0xE2U // GPIO D Peripheral Group Mux (GPIO112 to 127) +#define GPIO_O_GPDCSEL1 0xE8U // GPIO D Core Select Register (GPIO96 to 103) +#define GPIO_O_GPDCSEL2 0xEAU // GPIO D Core Select Register (GPIO104 to 111) +#define GPIO_O_GPDCSEL3 0xECU // GPIO D Core Select Register (GPIO112 to 119) +#define GPIO_O_GPDCSEL4 0xEEU // GPIO D Core Select Register (GPIO120 to 127) +#define GPIO_O_GPDLOCK 0xFCU // GPIO D Lock Configuration Register (GPIO96 to 127) +#define GPIO_O_GPDCR 0xFEU // GPIO D Lock Commit Register (GPIO96 to 127) +#define GPIO_O_GPECTRL 0x100U // GPIO E Qualification Sampling Period Control (GPIO128 to 159) +#define GPIO_O_GPEQSEL1 0x102U // GPIO E Qualifier Select 1 Register (GPIO128 to 143) +#define GPIO_O_GPEQSEL2 0x104U // GPIO E Qualifier Select 2 Register (GPIO144 to 159) +#define GPIO_O_GPEMUX1 0x106U // GPIO E Mux 1 Register (GPIO128 to 143) +#define GPIO_O_GPEMUX2 0x108U // GPIO E Mux 2 Register (GPIO144 to 159) +#define GPIO_O_GPEDIR 0x10AU // GPIO E Direction Register (GPIO128 to 159) +#define GPIO_O_GPEPUD 0x10CU // GPIO E Pull Up Disable Register (GPIO128 to 159) +#define GPIO_O_GPEINV 0x110U // GPIO E Input Polarity Invert Registers (GPIO128 to 159) +#define GPIO_O_GPEODR 0x112U // GPIO E Open Drain Output Register (GPIO128 to GPIO159) +#define GPIO_O_GPEGMUX1 0x120U // GPIO E Peripheral Group Mux (GPIO128 to 143) +#define GPIO_O_GPEGMUX2 0x122U // GPIO E Peripheral Group Mux (GPIO144 to 159) +#define GPIO_O_GPECSEL1 0x128U // GPIO E Core Select Register (GPIO128 to 135) +#define GPIO_O_GPECSEL2 0x12AU // GPIO E Core Select Register (GPIO136 to 143) +#define GPIO_O_GPECSEL3 0x12CU // GPIO E Core Select Register (GPIO144 to 151) +#define GPIO_O_GPECSEL4 0x12EU // GPIO E Core Select Register (GPIO152 to 159) +#define GPIO_O_GPELOCK 0x13CU // GPIO E Lock Configuration Register (GPIO128 to 159) +#define GPIO_O_GPECR 0x13EU // GPIO E Lock Commit Register (GPIO128 to 159) +#define GPIO_O_GPFCTRL 0x140U // GPIO F Qualification Sampling Period Control (GPIO160 to 168) +#define GPIO_O_GPFQSEL1 0x142U // GPIO F Qualifier Select 1 Register (GPIO160 to 168) +#define GPIO_O_GPFMUX1 0x146U // GPIO F Mux 1 Register (GPIO160 to 168) +#define GPIO_O_GPFDIR 0x14AU // GPIO F Direction Register (GPIO160 to 168) +#define GPIO_O_GPFPUD 0x14CU // GPIO F Pull Up Disable Register (GPIO160 to 168) +#define GPIO_O_GPFINV 0x150U // GPIO F Input Polarity Invert Registers (GPIO160 to 168) +#define GPIO_O_GPFODR 0x152U // GPIO F Open Drain Output Register (GPIO160 to GPIO168) +#define GPIO_O_GPFGMUX1 0x160U // GPIO F Peripheral Group Mux (GPIO160 to 168) +#define GPIO_O_GPFCSEL1 0x168U // GPIO F Core Select Register (GPIO160 to 167) +#define GPIO_O_GPFCSEL2 0x16AU // GPIO F Core Select Register (GPIO168) +#define GPIO_O_GPFLOCK 0x17CU // GPIO F Lock Configuration Register (GPIO160 to 168) +#define GPIO_O_GPFCR 0x17EU // GPIO F Lock Commit Register (GPIO160 to 168) + +#define GPIO_O_GPADAT 0x0U // GPIO A Data Register (GPIO0 to 31) +#define GPIO_O_GPASET 0x2U // GPIO A Data Set Register (GPIO0 to 31) +#define GPIO_O_GPACLEAR 0x4U // GPIO A Data Clear Register (GPIO0 to 31) +#define GPIO_O_GPATOGGLE 0x6U // GPIO A Data Toggle Register (GPIO0 to 31) +#define GPIO_O_GPBDAT 0x8U // GPIO B Data Register (GPIO32 to 63) +#define GPIO_O_GPBSET 0xAU // GPIO B Data Set Register (GPIO32 to 63) +#define GPIO_O_GPBCLEAR 0xCU // GPIO B Data Clear Register (GPIO32 to 63) +#define GPIO_O_GPBTOGGLE 0xEU // GPIO B Data Toggle Register (GPIO32 to 63) +#define GPIO_O_GPCDAT 0x10U // GPIO C Data Register (GPIO64 to 95) +#define GPIO_O_GPCSET 0x12U // GPIO C Data Set Register (GPIO64 to 95) +#define GPIO_O_GPCCLEAR 0x14U // GPIO C Data Clear Register (GPIO64 to 95) +#define GPIO_O_GPCTOGGLE 0x16U // GPIO C Data Toggle Register (GPIO64 to 95) +#define GPIO_O_GPDDAT 0x18U // GPIO D Data Register (GPIO96 to 127) +#define GPIO_O_GPDSET 0x1AU // GPIO D Data Set Register (GPIO96 to 127) +#define GPIO_O_GPDCLEAR 0x1CU // GPIO D Data Clear Register (GPIO96 to 127) +#define GPIO_O_GPDTOGGLE 0x1EU // GPIO D Data Toggle Register (GPIO96 to 127) +#define GPIO_O_GPEDAT 0x20U // GPIO E Data Register (GPIO128 to 159) +#define GPIO_O_GPESET 0x22U // GPIO E Data Set Register (GPIO128 to 159) +#define GPIO_O_GPECLEAR 0x24U // GPIO E Data Clear Register (GPIO128 to 159) +#define GPIO_O_GPETOGGLE 0x26U // GPIO E Data Toggle Register (GPIO128 to 159) +#define GPIO_O_GPFDAT 0x28U // GPIO F Data Register (GPIO160 to 168) +#define GPIO_O_GPFSET 0x2AU // GPIO F Data Set Register (GPIO160 to 168) +#define GPIO_O_GPFCLEAR 0x2CU // GPIO F Data Clear Register (GPIO160 to 168) +#define GPIO_O_GPFTOGGLE 0x2EU // GPIO F Data Toggle Register (GPIO160 to 168) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACTRL register +// +//************************************************************************************************* +#define GPIO_GPACTRL_QUALPRD0_S 0U +#define GPIO_GPACTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO0 to GPIO7 +#define GPIO_GPACTRL_QUALPRD1_S 8U +#define GPIO_GPACTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO8 to + // GPIO15 +#define GPIO_GPACTRL_QUALPRD2_S 16U +#define GPIO_GPACTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO16 to + // GPIO23 +#define GPIO_GPACTRL_QUALPRD3_S 24U +#define GPIO_GPACTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO24 to + // GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL1_GPIO0_S 0U +#define GPIO_GPAQSEL1_GPIO0_M 0x3U // Select input qualification type for GPIO0 +#define GPIO_GPAQSEL1_GPIO1_S 2U +#define GPIO_GPAQSEL1_GPIO1_M 0xCU // Select input qualification type for GPIO1 +#define GPIO_GPAQSEL1_GPIO2_S 4U +#define GPIO_GPAQSEL1_GPIO2_M 0x30U // Select input qualification type for GPIO2 +#define GPIO_GPAQSEL1_GPIO3_S 6U +#define GPIO_GPAQSEL1_GPIO3_M 0xC0U // Select input qualification type for GPIO3 +#define GPIO_GPAQSEL1_GPIO4_S 8U +#define GPIO_GPAQSEL1_GPIO4_M 0x300U // Select input qualification type for GPIO4 +#define GPIO_GPAQSEL1_GPIO5_S 10U +#define GPIO_GPAQSEL1_GPIO5_M 0xC00U // Select input qualification type for GPIO5 +#define GPIO_GPAQSEL1_GPIO6_S 12U +#define GPIO_GPAQSEL1_GPIO6_M 0x3000U // Select input qualification type for GPIO6 +#define GPIO_GPAQSEL1_GPIO7_S 14U +#define GPIO_GPAQSEL1_GPIO7_M 0xC000U // Select input qualification type for GPIO7 +#define GPIO_GPAQSEL1_GPIO8_S 16U +#define GPIO_GPAQSEL1_GPIO8_M 0x30000U // Select input qualification type for GPIO8 +#define GPIO_GPAQSEL1_GPIO9_S 18U +#define GPIO_GPAQSEL1_GPIO9_M 0xC0000U // Select input qualification type for GPIO9 +#define GPIO_GPAQSEL1_GPIO10_S 20U +#define GPIO_GPAQSEL1_GPIO10_M 0x300000U // Select input qualification type for GPIO10 +#define GPIO_GPAQSEL1_GPIO11_S 22U +#define GPIO_GPAQSEL1_GPIO11_M 0xC00000U // Select input qualification type for GPIO11 +#define GPIO_GPAQSEL1_GPIO12_S 24U +#define GPIO_GPAQSEL1_GPIO12_M 0x3000000U // Select input qualification type for GPIO12 +#define GPIO_GPAQSEL1_GPIO13_S 26U +#define GPIO_GPAQSEL1_GPIO13_M 0xC000000U // Select input qualification type for GPIO13 +#define GPIO_GPAQSEL1_GPIO14_S 28U +#define GPIO_GPAQSEL1_GPIO14_M 0x30000000U // Select input qualification type for GPIO14 +#define GPIO_GPAQSEL1_GPIO15_S 30U +#define GPIO_GPAQSEL1_GPIO15_M 0xC0000000U // Select input qualification type for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL2_GPIO16_S 0U +#define GPIO_GPAQSEL2_GPIO16_M 0x3U // Select input qualification type for GPIO16 +#define GPIO_GPAQSEL2_GPIO17_S 2U +#define GPIO_GPAQSEL2_GPIO17_M 0xCU // Select input qualification type for GPIO17 +#define GPIO_GPAQSEL2_GPIO18_S 4U +#define GPIO_GPAQSEL2_GPIO18_M 0x30U // Select input qualification type for GPIO18 +#define GPIO_GPAQSEL2_GPIO19_S 6U +#define GPIO_GPAQSEL2_GPIO19_M 0xC0U // Select input qualification type for GPIO19 +#define GPIO_GPAQSEL2_GPIO20_S 8U +#define GPIO_GPAQSEL2_GPIO20_M 0x300U // Select input qualification type for GPIO20 +#define GPIO_GPAQSEL2_GPIO21_S 10U +#define GPIO_GPAQSEL2_GPIO21_M 0xC00U // Select input qualification type for GPIO21 +#define GPIO_GPAQSEL2_GPIO22_S 12U +#define GPIO_GPAQSEL2_GPIO22_M 0x3000U // Select input qualification type for GPIO22 +#define GPIO_GPAQSEL2_GPIO23_S 14U +#define GPIO_GPAQSEL2_GPIO23_M 0xC000U // Select input qualification type for GPIO23 +#define GPIO_GPAQSEL2_GPIO24_S 16U +#define GPIO_GPAQSEL2_GPIO24_M 0x30000U // Select input qualification type for GPIO24 +#define GPIO_GPAQSEL2_GPIO25_S 18U +#define GPIO_GPAQSEL2_GPIO25_M 0xC0000U // Select input qualification type for GPIO25 +#define GPIO_GPAQSEL2_GPIO26_S 20U +#define GPIO_GPAQSEL2_GPIO26_M 0x300000U // Select input qualification type for GPIO26 +#define GPIO_GPAQSEL2_GPIO27_S 22U +#define GPIO_GPAQSEL2_GPIO27_M 0xC00000U // Select input qualification type for GPIO27 +#define GPIO_GPAQSEL2_GPIO28_S 24U +#define GPIO_GPAQSEL2_GPIO28_M 0x3000000U // Select input qualification type for GPIO28 +#define GPIO_GPAQSEL2_GPIO29_S 26U +#define GPIO_GPAQSEL2_GPIO29_M 0xC000000U // Select input qualification type for GPIO29 +#define GPIO_GPAQSEL2_GPIO30_S 28U +#define GPIO_GPAQSEL2_GPIO30_M 0x30000000U // Select input qualification type for GPIO30 +#define GPIO_GPAQSEL2_GPIO31_S 30U +#define GPIO_GPAQSEL2_GPIO31_M 0xC0000000U // Select input qualification type for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAMUX1_GPIO0_S 0U +#define GPIO_GPAMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAMUX1_GPIO1_S 2U +#define GPIO_GPAMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAMUX1_GPIO2_S 4U +#define GPIO_GPAMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAMUX1_GPIO3_S 6U +#define GPIO_GPAMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAMUX1_GPIO4_S 8U +#define GPIO_GPAMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAMUX1_GPIO5_S 10U +#define GPIO_GPAMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAMUX1_GPIO6_S 12U +#define GPIO_GPAMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAMUX1_GPIO7_S 14U +#define GPIO_GPAMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAMUX1_GPIO8_S 16U +#define GPIO_GPAMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAMUX1_GPIO9_S 18U +#define GPIO_GPAMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAMUX1_GPIO10_S 20U +#define GPIO_GPAMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAMUX1_GPIO11_S 22U +#define GPIO_GPAMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAMUX1_GPIO12_S 24U +#define GPIO_GPAMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAMUX1_GPIO13_S 26U +#define GPIO_GPAMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAMUX1_GPIO14_S 28U +#define GPIO_GPAMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAMUX1_GPIO15_S 30U +#define GPIO_GPAMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAMUX2_GPIO16_S 0U +#define GPIO_GPAMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAMUX2_GPIO17_S 2U +#define GPIO_GPAMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAMUX2_GPIO18_S 4U +#define GPIO_GPAMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAMUX2_GPIO19_S 6U +#define GPIO_GPAMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAMUX2_GPIO20_S 8U +#define GPIO_GPAMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAMUX2_GPIO21_S 10U +#define GPIO_GPAMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAMUX2_GPIO22_S 12U +#define GPIO_GPAMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAMUX2_GPIO23_S 14U +#define GPIO_GPAMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAMUX2_GPIO24_S 16U +#define GPIO_GPAMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAMUX2_GPIO25_S 18U +#define GPIO_GPAMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAMUX2_GPIO26_S 20U +#define GPIO_GPAMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAMUX2_GPIO27_S 22U +#define GPIO_GPAMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAMUX2_GPIO28_S 24U +#define GPIO_GPAMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAMUX2_GPIO29_S 26U +#define GPIO_GPAMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAMUX2_GPIO30_S 28U +#define GPIO_GPAMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAMUX2_GPIO31_S 30U +#define GPIO_GPAMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADIR register +// +//************************************************************************************************* +#define GPIO_GPADIR_GPIO0 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO1 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO2 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO3 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO4 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO5 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO6 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO7 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO8 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO9 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO10 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO11 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO12 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO13 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO14 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO15 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO16 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO17 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO18 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO19 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO20 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO21 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO22 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO23 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO24 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO25 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO26 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO27 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO28 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO29 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO30 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO31 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAPUD register +// +//************************************************************************************************* +#define GPIO_GPAPUD_GPIO0 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO1 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO2 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO3 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO4 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO5 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO6 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO7 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO8 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO9 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO10 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO11 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO12 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO13 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO14 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO15 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO16 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO17 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO18 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO19 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO20 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO21 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO22 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO23 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO24 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO25 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO26 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO27 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO28 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO29 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO30 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO31 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAINV register +// +//************************************************************************************************* +#define GPIO_GPAINV_GPIO0 0x1U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO1 0x2U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO2 0x4U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO3 0x8U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO4 0x10U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO5 0x20U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO6 0x40U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO7 0x80U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO8 0x100U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO9 0x200U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO10 0x400U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO11 0x800U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO12 0x1000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO13 0x2000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO14 0x4000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO15 0x8000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO16 0x10000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO17 0x20000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO18 0x40000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO19 0x80000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO20 0x100000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO21 0x200000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO22 0x400000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO23 0x800000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO24 0x1000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO25 0x2000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO26 0x4000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO27 0x8000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO28 0x10000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO29 0x20000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO30 0x40000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO31 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAODR register +// +//************************************************************************************************* +#define GPIO_GPAODR_GPIO0 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO1 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO2 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO3 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO4 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO5 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO6 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO7 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO8 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO9 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO10 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO11 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO12 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO13 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO14 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO15 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO16 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO17 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO18 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO19 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO20 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO21 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO22 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO23 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO24 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO25 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO26 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO27 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO28 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO29 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO30 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO31 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX1_GPIO0_S 0U +#define GPIO_GPAGMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAGMUX1_GPIO1_S 2U +#define GPIO_GPAGMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAGMUX1_GPIO2_S 4U +#define GPIO_GPAGMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAGMUX1_GPIO3_S 6U +#define GPIO_GPAGMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAGMUX1_GPIO4_S 8U +#define GPIO_GPAGMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAGMUX1_GPIO5_S 10U +#define GPIO_GPAGMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAGMUX1_GPIO6_S 12U +#define GPIO_GPAGMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAGMUX1_GPIO7_S 14U +#define GPIO_GPAGMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAGMUX1_GPIO8_S 16U +#define GPIO_GPAGMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAGMUX1_GPIO9_S 18U +#define GPIO_GPAGMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAGMUX1_GPIO10_S 20U +#define GPIO_GPAGMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAGMUX1_GPIO11_S 22U +#define GPIO_GPAGMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAGMUX1_GPIO12_S 24U +#define GPIO_GPAGMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAGMUX1_GPIO13_S 26U +#define GPIO_GPAGMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAGMUX1_GPIO14_S 28U +#define GPIO_GPAGMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAGMUX1_GPIO15_S 30U +#define GPIO_GPAGMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX2_GPIO16_S 0U +#define GPIO_GPAGMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAGMUX2_GPIO17_S 2U +#define GPIO_GPAGMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAGMUX2_GPIO18_S 4U +#define GPIO_GPAGMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAGMUX2_GPIO19_S 6U +#define GPIO_GPAGMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAGMUX2_GPIO20_S 8U +#define GPIO_GPAGMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAGMUX2_GPIO21_S 10U +#define GPIO_GPAGMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAGMUX2_GPIO22_S 12U +#define GPIO_GPAGMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAGMUX2_GPIO23_S 14U +#define GPIO_GPAGMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAGMUX2_GPIO24_S 16U +#define GPIO_GPAGMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAGMUX2_GPIO25_S 18U +#define GPIO_GPAGMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAGMUX2_GPIO26_S 20U +#define GPIO_GPAGMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAGMUX2_GPIO27_S 22U +#define GPIO_GPAGMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAGMUX2_GPIO28_S 24U +#define GPIO_GPAGMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAGMUX2_GPIO29_S 26U +#define GPIO_GPAGMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAGMUX2_GPIO30_S 28U +#define GPIO_GPAGMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAGMUX2_GPIO31_S 30U +#define GPIO_GPAGMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL1 register +// +//************************************************************************************************* +#define GPIO_GPACSEL1_GPIO0_S 0U +#define GPIO_GPACSEL1_GPIO0_M 0xFU // GPIO0 Master CPU Select +#define GPIO_GPACSEL1_GPIO1_S 4U +#define GPIO_GPACSEL1_GPIO1_M 0xF0U // GPIO1 Master CPU Select +#define GPIO_GPACSEL1_GPIO2_S 8U +#define GPIO_GPACSEL1_GPIO2_M 0xF00U // GPIO2 Master CPU Select +#define GPIO_GPACSEL1_GPIO3_S 12U +#define GPIO_GPACSEL1_GPIO3_M 0xF000U // GPIO3 Master CPU Select +#define GPIO_GPACSEL1_GPIO4_S 16U +#define GPIO_GPACSEL1_GPIO4_M 0xF0000U // GPIO4 Master CPU Select +#define GPIO_GPACSEL1_GPIO5_S 20U +#define GPIO_GPACSEL1_GPIO5_M 0xF00000U // GPIO5 Master CPU Select +#define GPIO_GPACSEL1_GPIO6_S 24U +#define GPIO_GPACSEL1_GPIO6_M 0xF000000U // GPIO6 Master CPU Select +#define GPIO_GPACSEL1_GPIO7_S 28U +#define GPIO_GPACSEL1_GPIO7_M 0xF0000000U // GPIO7 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL2 register +// +//************************************************************************************************* +#define GPIO_GPACSEL2_GPIO8_S 0U +#define GPIO_GPACSEL2_GPIO8_M 0xFU // GPIO8 Master CPU Select +#define GPIO_GPACSEL2_GPIO9_S 4U +#define GPIO_GPACSEL2_GPIO9_M 0xF0U // GPIO9 Master CPU Select +#define GPIO_GPACSEL2_GPIO10_S 8U +#define GPIO_GPACSEL2_GPIO10_M 0xF00U // GPIO10 Master CPU Select +#define GPIO_GPACSEL2_GPIO11_S 12U +#define GPIO_GPACSEL2_GPIO11_M 0xF000U // GPIO11 Master CPU Select +#define GPIO_GPACSEL2_GPIO12_S 16U +#define GPIO_GPACSEL2_GPIO12_M 0xF0000U // GPIO12 Master CPU Select +#define GPIO_GPACSEL2_GPIO13_S 20U +#define GPIO_GPACSEL2_GPIO13_M 0xF00000U // GPIO13 Master CPU Select +#define GPIO_GPACSEL2_GPIO14_S 24U +#define GPIO_GPACSEL2_GPIO14_M 0xF000000U // GPIO14 Master CPU Select +#define GPIO_GPACSEL2_GPIO15_S 28U +#define GPIO_GPACSEL2_GPIO15_M 0xF0000000U // GPIO15 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL3 register +// +//************************************************************************************************* +#define GPIO_GPACSEL3_GPIO16_S 0U +#define GPIO_GPACSEL3_GPIO16_M 0xFU // GPIO16 Master CPU Select +#define GPIO_GPACSEL3_GPIO17_S 4U +#define GPIO_GPACSEL3_GPIO17_M 0xF0U // GPIO17 Master CPU Select +#define GPIO_GPACSEL3_GPIO18_S 8U +#define GPIO_GPACSEL3_GPIO18_M 0xF00U // GPIO18 Master CPU Select +#define GPIO_GPACSEL3_GPIO19_S 12U +#define GPIO_GPACSEL3_GPIO19_M 0xF000U // GPIO19 Master CPU Select +#define GPIO_GPACSEL3_GPIO20_S 16U +#define GPIO_GPACSEL3_GPIO20_M 0xF0000U // GPIO20 Master CPU Select +#define GPIO_GPACSEL3_GPIO21_S 20U +#define GPIO_GPACSEL3_GPIO21_M 0xF00000U // GPIO21 Master CPU Select +#define GPIO_GPACSEL3_GPIO22_S 24U +#define GPIO_GPACSEL3_GPIO22_M 0xF000000U // GPIO22 Master CPU Select +#define GPIO_GPACSEL3_GPIO23_S 28U +#define GPIO_GPACSEL3_GPIO23_M 0xF0000000U // GPIO23 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL4 register +// +//************************************************************************************************* +#define GPIO_GPACSEL4_GPIO24_S 0U +#define GPIO_GPACSEL4_GPIO24_M 0xFU // GPIO24 Master CPU Select +#define GPIO_GPACSEL4_GPIO25_S 4U +#define GPIO_GPACSEL4_GPIO25_M 0xF0U // GPIO25 Master CPU Select +#define GPIO_GPACSEL4_GPIO26_S 8U +#define GPIO_GPACSEL4_GPIO26_M 0xF00U // GPIO26 Master CPU Select +#define GPIO_GPACSEL4_GPIO27_S 12U +#define GPIO_GPACSEL4_GPIO27_M 0xF000U // GPIO27 Master CPU Select +#define GPIO_GPACSEL4_GPIO28_S 16U +#define GPIO_GPACSEL4_GPIO28_M 0xF0000U // GPIO28 Master CPU Select +#define GPIO_GPACSEL4_GPIO29_S 20U +#define GPIO_GPACSEL4_GPIO29_M 0xF00000U // GPIO29 Master CPU Select +#define GPIO_GPACSEL4_GPIO30_S 24U +#define GPIO_GPACSEL4_GPIO30_M 0xF000000U // GPIO30 Master CPU Select +#define GPIO_GPACSEL4_GPIO31_S 28U +#define GPIO_GPACSEL4_GPIO31_M 0xF0000000U // GPIO31 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPALOCK register +// +//************************************************************************************************* +#define GPIO_GPALOCK_GPIO0 0x1U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO1 0x2U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO2 0x4U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO3 0x8U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO4 0x10U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO5 0x20U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO6 0x40U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO7 0x80U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO8 0x100U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO9 0x200U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO10 0x400U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO11 0x800U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO12 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO13 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO14 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO15 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO16 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO17 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO18 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO19 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO20 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO21 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO22 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO23 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO24 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO25 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO26 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO27 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO28 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO29 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO30 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO31 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACR register +// +//************************************************************************************************* +#define GPIO_GPACR_GPIO0 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO1 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO2 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO3 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO4 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO5 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO6 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO7 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO8 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO9 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO10 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO11 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO12 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO13 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO14 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO15 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO16 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO17 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO18 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO19 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO20 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO21 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO22 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO23 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO24 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO25 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO26 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO27 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO28 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO29 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO30 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO31 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCTRL register +// +//************************************************************************************************* +#define GPIO_GPBCTRL_QUALPRD0_S 0U +#define GPIO_GPBCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO32 to + // GPIO39 +#define GPIO_GPBCTRL_QUALPRD1_S 8U +#define GPIO_GPBCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO40 to + // GPIO47 +#define GPIO_GPBCTRL_QUALPRD2_S 16U +#define GPIO_GPBCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO48 to + // GPIO55 +#define GPIO_GPBCTRL_QUALPRD3_S 24U +#define GPIO_GPBCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO56 to + // GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL1_GPIO32_S 0U +#define GPIO_GPBQSEL1_GPIO32_M 0x3U // Select input qualification type for GPIO32 +#define GPIO_GPBQSEL1_GPIO33_S 2U +#define GPIO_GPBQSEL1_GPIO33_M 0xCU // Select input qualification type for GPIO33 +#define GPIO_GPBQSEL1_GPIO34_S 4U +#define GPIO_GPBQSEL1_GPIO34_M 0x30U // Select input qualification type for GPIO34 +#define GPIO_GPBQSEL1_GPIO35_S 6U +#define GPIO_GPBQSEL1_GPIO35_M 0xC0U // Select input qualification type for GPIO35 +#define GPIO_GPBQSEL1_GPIO36_S 8U +#define GPIO_GPBQSEL1_GPIO36_M 0x300U // Select input qualification type for GPIO36 +#define GPIO_GPBQSEL1_GPIO37_S 10U +#define GPIO_GPBQSEL1_GPIO37_M 0xC00U // Select input qualification type for GPIO37 +#define GPIO_GPBQSEL1_GPIO38_S 12U +#define GPIO_GPBQSEL1_GPIO38_M 0x3000U // Select input qualification type for GPIO38 +#define GPIO_GPBQSEL1_GPIO39_S 14U +#define GPIO_GPBQSEL1_GPIO39_M 0xC000U // Select input qualification type for GPIO39 +#define GPIO_GPBQSEL1_GPIO40_S 16U +#define GPIO_GPBQSEL1_GPIO40_M 0x30000U // Select input qualification type for GPIO40 +#define GPIO_GPBQSEL1_GPIO41_S 18U +#define GPIO_GPBQSEL1_GPIO41_M 0xC0000U // Select input qualification type for GPIO41 +#define GPIO_GPBQSEL1_GPIO42_S 20U +#define GPIO_GPBQSEL1_GPIO42_M 0x300000U // Select input qualification type for GPIO42 +#define GPIO_GPBQSEL1_GPIO43_S 22U +#define GPIO_GPBQSEL1_GPIO43_M 0xC00000U // Select input qualification type for GPIO43 +#define GPIO_GPBQSEL1_GPIO44_S 24U +#define GPIO_GPBQSEL1_GPIO44_M 0x3000000U // Select input qualification type for GPIO44 +#define GPIO_GPBQSEL1_GPIO45_S 26U +#define GPIO_GPBQSEL1_GPIO45_M 0xC000000U // Select input qualification type for GPIO45 +#define GPIO_GPBQSEL1_GPIO46_S 28U +#define GPIO_GPBQSEL1_GPIO46_M 0x30000000U // Select input qualification type for GPIO46 +#define GPIO_GPBQSEL1_GPIO47_S 30U +#define GPIO_GPBQSEL1_GPIO47_M 0xC0000000U // Select input qualification type for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL2_GPIO48_S 0U +#define GPIO_GPBQSEL2_GPIO48_M 0x3U // Select input qualification type for GPIO48 +#define GPIO_GPBQSEL2_GPIO49_S 2U +#define GPIO_GPBQSEL2_GPIO49_M 0xCU // Select input qualification type for GPIO49 +#define GPIO_GPBQSEL2_GPIO50_S 4U +#define GPIO_GPBQSEL2_GPIO50_M 0x30U // Select input qualification type for GPIO50 +#define GPIO_GPBQSEL2_GPIO51_S 6U +#define GPIO_GPBQSEL2_GPIO51_M 0xC0U // Select input qualification type for GPIO51 +#define GPIO_GPBQSEL2_GPIO52_S 8U +#define GPIO_GPBQSEL2_GPIO52_M 0x300U // Select input qualification type for GPIO52 +#define GPIO_GPBQSEL2_GPIO53_S 10U +#define GPIO_GPBQSEL2_GPIO53_M 0xC00U // Select input qualification type for GPIO53 +#define GPIO_GPBQSEL2_GPIO54_S 12U +#define GPIO_GPBQSEL2_GPIO54_M 0x3000U // Select input qualification type for GPIO54 +#define GPIO_GPBQSEL2_GPIO55_S 14U +#define GPIO_GPBQSEL2_GPIO55_M 0xC000U // Select input qualification type for GPIO55 +#define GPIO_GPBQSEL2_GPIO56_S 16U +#define GPIO_GPBQSEL2_GPIO56_M 0x30000U // Select input qualification type for GPIO56 +#define GPIO_GPBQSEL2_GPIO57_S 18U +#define GPIO_GPBQSEL2_GPIO57_M 0xC0000U // Select input qualification type for GPIO57 +#define GPIO_GPBQSEL2_GPIO58_S 20U +#define GPIO_GPBQSEL2_GPIO58_M 0x300000U // Select input qualification type for GPIO58 +#define GPIO_GPBQSEL2_GPIO59_S 22U +#define GPIO_GPBQSEL2_GPIO59_M 0xC00000U // Select input qualification type for GPIO59 +#define GPIO_GPBQSEL2_GPIO60_S 24U +#define GPIO_GPBQSEL2_GPIO60_M 0x3000000U // Select input qualification type for GPIO60 +#define GPIO_GPBQSEL2_GPIO61_S 26U +#define GPIO_GPBQSEL2_GPIO61_M 0xC000000U // Select input qualification type for GPIO61 +#define GPIO_GPBQSEL2_GPIO62_S 28U +#define GPIO_GPBQSEL2_GPIO62_M 0x30000000U // Select input qualification type for GPIO62 +#define GPIO_GPBQSEL2_GPIO63_S 30U +#define GPIO_GPBQSEL2_GPIO63_M 0xC0000000U // Select input qualification type for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBMUX1_GPIO32_S 0U +#define GPIO_GPBMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBMUX1_GPIO33_S 2U +#define GPIO_GPBMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBMUX1_GPIO34_S 4U +#define GPIO_GPBMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBMUX1_GPIO35_S 6U +#define GPIO_GPBMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBMUX1_GPIO36_S 8U +#define GPIO_GPBMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBMUX1_GPIO37_S 10U +#define GPIO_GPBMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBMUX1_GPIO38_S 12U +#define GPIO_GPBMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBMUX1_GPIO39_S 14U +#define GPIO_GPBMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBMUX1_GPIO40_S 16U +#define GPIO_GPBMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBMUX1_GPIO41_S 18U +#define GPIO_GPBMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBMUX1_GPIO42_S 20U +#define GPIO_GPBMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBMUX1_GPIO43_S 22U +#define GPIO_GPBMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBMUX1_GPIO44_S 24U +#define GPIO_GPBMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBMUX1_GPIO45_S 26U +#define GPIO_GPBMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBMUX1_GPIO46_S 28U +#define GPIO_GPBMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBMUX1_GPIO47_S 30U +#define GPIO_GPBMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBMUX2_GPIO48_S 0U +#define GPIO_GPBMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBMUX2_GPIO49_S 2U +#define GPIO_GPBMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBMUX2_GPIO50_S 4U +#define GPIO_GPBMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBMUX2_GPIO51_S 6U +#define GPIO_GPBMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBMUX2_GPIO52_S 8U +#define GPIO_GPBMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBMUX2_GPIO53_S 10U +#define GPIO_GPBMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBMUX2_GPIO54_S 12U +#define GPIO_GPBMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBMUX2_GPIO55_S 14U +#define GPIO_GPBMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBMUX2_GPIO56_S 16U +#define GPIO_GPBMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBMUX2_GPIO57_S 18U +#define GPIO_GPBMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBMUX2_GPIO58_S 20U +#define GPIO_GPBMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBMUX2_GPIO59_S 22U +#define GPIO_GPBMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBMUX2_GPIO60_S 24U +#define GPIO_GPBMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBMUX2_GPIO61_S 26U +#define GPIO_GPBMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBMUX2_GPIO62_S 28U +#define GPIO_GPBMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBMUX2_GPIO63_S 30U +#define GPIO_GPBMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDIR register +// +//************************************************************************************************* +#define GPIO_GPBDIR_GPIO32 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO33 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO34 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO35 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO36 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO37 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO38 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO39 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO40 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO41 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO42 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO43 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO44 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO45 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO46 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO47 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO48 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO49 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO50 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO51 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO52 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO53 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO54 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO55 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO56 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO57 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO58 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO59 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO60 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO61 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO62 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO63 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBPUD register +// +//************************************************************************************************* +#define GPIO_GPBPUD_GPIO32 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO33 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO34 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO35 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO36 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO37 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO38 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO39 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO40 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO41 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO42 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO43 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO44 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO45 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO46 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO47 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO48 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO49 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO50 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO51 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO52 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO53 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO54 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO55 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO56 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO57 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO58 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO59 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO60 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO61 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO62 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO63 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBINV register +// +//************************************************************************************************* +#define GPIO_GPBINV_GPIO32 0x1U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO33 0x2U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO34 0x4U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO35 0x8U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO36 0x10U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO37 0x20U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO38 0x40U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO39 0x80U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO40 0x100U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO41 0x200U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO42 0x400U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO43 0x800U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO44 0x1000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO45 0x2000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO46 0x4000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO47 0x8000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO48 0x10000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO49 0x20000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO50 0x40000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO51 0x80000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO52 0x100000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO53 0x200000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO54 0x400000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO55 0x800000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO56 0x1000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO57 0x2000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO58 0x4000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO59 0x8000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO60 0x10000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO61 0x20000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO62 0x40000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO63 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBODR register +// +//************************************************************************************************* +#define GPIO_GPBODR_GPIO32 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO33 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO34 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO35 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO36 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO37 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO38 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO39 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO40 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO41 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO42 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO43 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO44 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO45 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO46 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO47 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO48 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO49 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO50 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO51 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO52 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO53 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO54 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO55 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO56 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO57 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO58 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO59 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO60 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO61 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO62 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO63 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBAMSEL register +// +//************************************************************************************************* +#define GPIO_GPBAMSEL_GPIO42 0x400U // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO43 0x800U // Analog Mode select for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX1_GPIO32_S 0U +#define GPIO_GPBGMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBGMUX1_GPIO33_S 2U +#define GPIO_GPBGMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBGMUX1_GPIO34_S 4U +#define GPIO_GPBGMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBGMUX1_GPIO35_S 6U +#define GPIO_GPBGMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBGMUX1_GPIO36_S 8U +#define GPIO_GPBGMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBGMUX1_GPIO37_S 10U +#define GPIO_GPBGMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBGMUX1_GPIO38_S 12U +#define GPIO_GPBGMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBGMUX1_GPIO39_S 14U +#define GPIO_GPBGMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBGMUX1_GPIO40_S 16U +#define GPIO_GPBGMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBGMUX1_GPIO41_S 18U +#define GPIO_GPBGMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBGMUX1_GPIO42_S 20U +#define GPIO_GPBGMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBGMUX1_GPIO43_S 22U +#define GPIO_GPBGMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBGMUX1_GPIO44_S 24U +#define GPIO_GPBGMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBGMUX1_GPIO45_S 26U +#define GPIO_GPBGMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBGMUX1_GPIO46_S 28U +#define GPIO_GPBGMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBGMUX1_GPIO47_S 30U +#define GPIO_GPBGMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX2_GPIO48_S 0U +#define GPIO_GPBGMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBGMUX2_GPIO49_S 2U +#define GPIO_GPBGMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBGMUX2_GPIO50_S 4U +#define GPIO_GPBGMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBGMUX2_GPIO51_S 6U +#define GPIO_GPBGMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBGMUX2_GPIO52_S 8U +#define GPIO_GPBGMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBGMUX2_GPIO53_S 10U +#define GPIO_GPBGMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBGMUX2_GPIO54_S 12U +#define GPIO_GPBGMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBGMUX2_GPIO55_S 14U +#define GPIO_GPBGMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBGMUX2_GPIO56_S 16U +#define GPIO_GPBGMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBGMUX2_GPIO57_S 18U +#define GPIO_GPBGMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBGMUX2_GPIO58_S 20U +#define GPIO_GPBGMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBGMUX2_GPIO59_S 22U +#define GPIO_GPBGMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBGMUX2_GPIO60_S 24U +#define GPIO_GPBGMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBGMUX2_GPIO61_S 26U +#define GPIO_GPBGMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBGMUX2_GPIO62_S 28U +#define GPIO_GPBGMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBGMUX2_GPIO63_S 30U +#define GPIO_GPBGMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL1_GPIO32_S 0U +#define GPIO_GPBCSEL1_GPIO32_M 0xFU // GPIO32 Master CPU Select +#define GPIO_GPBCSEL1_GPIO33_S 4U +#define GPIO_GPBCSEL1_GPIO33_M 0xF0U // GPIO33 Master CPU Select +#define GPIO_GPBCSEL1_GPIO34_S 8U +#define GPIO_GPBCSEL1_GPIO34_M 0xF00U // GPIO34 Master CPU Select +#define GPIO_GPBCSEL1_GPIO35_S 12U +#define GPIO_GPBCSEL1_GPIO35_M 0xF000U // GPIO35 Master CPU Select +#define GPIO_GPBCSEL1_GPIO36_S 16U +#define GPIO_GPBCSEL1_GPIO36_M 0xF0000U // GPIO36 Master CPU Select +#define GPIO_GPBCSEL1_GPIO37_S 20U +#define GPIO_GPBCSEL1_GPIO37_M 0xF00000U // GPIO37 Master CPU Select +#define GPIO_GPBCSEL1_GPIO38_S 24U +#define GPIO_GPBCSEL1_GPIO38_M 0xF000000U // GPIO38 Master CPU Select +#define GPIO_GPBCSEL1_GPIO39_S 28U +#define GPIO_GPBCSEL1_GPIO39_M 0xF0000000U // GPIO39 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL2_GPIO40_S 0U +#define GPIO_GPBCSEL2_GPIO40_M 0xFU // GPIO40 Master CPU Select +#define GPIO_GPBCSEL2_GPIO41_S 4U +#define GPIO_GPBCSEL2_GPIO41_M 0xF0U // GPIO41 Master CPU Select +#define GPIO_GPBCSEL2_GPIO42_S 8U +#define GPIO_GPBCSEL2_GPIO42_M 0xF00U // GPIO42 Master CPU Select +#define GPIO_GPBCSEL2_GPIO43_S 12U +#define GPIO_GPBCSEL2_GPIO43_M 0xF000U // GPIO43 Master CPU Select +#define GPIO_GPBCSEL2_GPIO44_S 16U +#define GPIO_GPBCSEL2_GPIO44_M 0xF0000U // GPIO44 Master CPU Select +#define GPIO_GPBCSEL2_GPIO45_S 20U +#define GPIO_GPBCSEL2_GPIO45_M 0xF00000U // GPIO45 Master CPU Select +#define GPIO_GPBCSEL2_GPIO46_S 24U +#define GPIO_GPBCSEL2_GPIO46_M 0xF000000U // GPIO46 Master CPU Select +#define GPIO_GPBCSEL2_GPIO47_S 28U +#define GPIO_GPBCSEL2_GPIO47_M 0xF0000000U // GPIO47 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL3_GPIO48_S 0U +#define GPIO_GPBCSEL3_GPIO48_M 0xFU // GPIO48 Master CPU Select +#define GPIO_GPBCSEL3_GPIO49_S 4U +#define GPIO_GPBCSEL3_GPIO49_M 0xF0U // GPIO49 Master CPU Select +#define GPIO_GPBCSEL3_GPIO50_S 8U +#define GPIO_GPBCSEL3_GPIO50_M 0xF00U // GPIO50 Master CPU Select +#define GPIO_GPBCSEL3_GPIO51_S 12U +#define GPIO_GPBCSEL3_GPIO51_M 0xF000U // GPIO51 Master CPU Select +#define GPIO_GPBCSEL3_GPIO52_S 16U +#define GPIO_GPBCSEL3_GPIO52_M 0xF0000U // GPIO52 Master CPU Select +#define GPIO_GPBCSEL3_GPIO53_S 20U +#define GPIO_GPBCSEL3_GPIO53_M 0xF00000U // GPIO53 Master CPU Select +#define GPIO_GPBCSEL3_GPIO54_S 24U +#define GPIO_GPBCSEL3_GPIO54_M 0xF000000U // GPIO54 Master CPU Select +#define GPIO_GPBCSEL3_GPIO55_S 28U +#define GPIO_GPBCSEL3_GPIO55_M 0xF0000000U // GPIO55 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL4_GPIO56_S 0U +#define GPIO_GPBCSEL4_GPIO56_M 0xFU // GPIO56 Master CPU Select +#define GPIO_GPBCSEL4_GPIO57_S 4U +#define GPIO_GPBCSEL4_GPIO57_M 0xF0U // GPIO57 Master CPU Select +#define GPIO_GPBCSEL4_GPIO58_S 8U +#define GPIO_GPBCSEL4_GPIO58_M 0xF00U // GPIO58 Master CPU Select +#define GPIO_GPBCSEL4_GPIO59_S 12U +#define GPIO_GPBCSEL4_GPIO59_M 0xF000U // GPIO59 Master CPU Select +#define GPIO_GPBCSEL4_GPIO60_S 16U +#define GPIO_GPBCSEL4_GPIO60_M 0xF0000U // GPIO60 Master CPU Select +#define GPIO_GPBCSEL4_GPIO61_S 20U +#define GPIO_GPBCSEL4_GPIO61_M 0xF00000U // GPIO61 Master CPU Select +#define GPIO_GPBCSEL4_GPIO62_S 24U +#define GPIO_GPBCSEL4_GPIO62_M 0xF000000U // GPIO62 Master CPU Select +#define GPIO_GPBCSEL4_GPIO63_S 28U +#define GPIO_GPBCSEL4_GPIO63_M 0xF0000000U // GPIO63 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBLOCK register +// +//************************************************************************************************* +#define GPIO_GPBLOCK_GPIO32 0x1U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO33 0x2U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO34 0x4U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO35 0x8U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO36 0x10U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO37 0x20U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO38 0x40U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO39 0x80U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO40 0x100U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO41 0x200U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO42 0x400U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO43 0x800U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO44 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO45 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO46 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO47 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO48 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO49 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO50 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO51 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO52 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO53 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO54 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO55 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO56 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO57 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO58 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO59 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO60 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO61 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO62 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO63 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCR register +// +//************************************************************************************************* +#define GPIO_GPBCR_GPIO32 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO33 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO34 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO35 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO36 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO37 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO38 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO39 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO40 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO41 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO42 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO43 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO44 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO45 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO46 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO47 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO48 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO49 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO50 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO51 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO52 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO53 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO54 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO55 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO56 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO57 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO58 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO59 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO60 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO61 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO62 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO63 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCTRL register +// +//************************************************************************************************* +#define GPIO_GPCCTRL_QUALPRD0_S 0U +#define GPIO_GPCCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO64 to + // GPIO71 +#define GPIO_GPCCTRL_QUALPRD1_S 8U +#define GPIO_GPCCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO72 to + // GPIO79 +#define GPIO_GPCCTRL_QUALPRD2_S 16U +#define GPIO_GPCCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO80 to + // GPIO87 +#define GPIO_GPCCTRL_QUALPRD3_S 24U +#define GPIO_GPCCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO88 to + // GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL1_GPIO64_S 0U +#define GPIO_GPCQSEL1_GPIO64_M 0x3U // Select input qualification type for GPIO64 +#define GPIO_GPCQSEL1_GPIO65_S 2U +#define GPIO_GPCQSEL1_GPIO65_M 0xCU // Select input qualification type for GPIO65 +#define GPIO_GPCQSEL1_GPIO66_S 4U +#define GPIO_GPCQSEL1_GPIO66_M 0x30U // Select input qualification type for GPIO66 +#define GPIO_GPCQSEL1_GPIO67_S 6U +#define GPIO_GPCQSEL1_GPIO67_M 0xC0U // Select input qualification type for GPIO67 +#define GPIO_GPCQSEL1_GPIO68_S 8U +#define GPIO_GPCQSEL1_GPIO68_M 0x300U // Select input qualification type for GPIO68 +#define GPIO_GPCQSEL1_GPIO69_S 10U +#define GPIO_GPCQSEL1_GPIO69_M 0xC00U // Select input qualification type for GPIO69 +#define GPIO_GPCQSEL1_GPIO70_S 12U +#define GPIO_GPCQSEL1_GPIO70_M 0x3000U // Select input qualification type for GPIO70 +#define GPIO_GPCQSEL1_GPIO71_S 14U +#define GPIO_GPCQSEL1_GPIO71_M 0xC000U // Select input qualification type for GPIO71 +#define GPIO_GPCQSEL1_GPIO72_S 16U +#define GPIO_GPCQSEL1_GPIO72_M 0x30000U // Select input qualification type for GPIO72 +#define GPIO_GPCQSEL1_GPIO73_S 18U +#define GPIO_GPCQSEL1_GPIO73_M 0xC0000U // Select input qualification type for GPIO73 +#define GPIO_GPCQSEL1_GPIO74_S 20U +#define GPIO_GPCQSEL1_GPIO74_M 0x300000U // Select input qualification type for GPIO74 +#define GPIO_GPCQSEL1_GPIO75_S 22U +#define GPIO_GPCQSEL1_GPIO75_M 0xC00000U // Select input qualification type for GPIO75 +#define GPIO_GPCQSEL1_GPIO76_S 24U +#define GPIO_GPCQSEL1_GPIO76_M 0x3000000U // Select input qualification type for GPIO76 +#define GPIO_GPCQSEL1_GPIO77_S 26U +#define GPIO_GPCQSEL1_GPIO77_M 0xC000000U // Select input qualification type for GPIO77 +#define GPIO_GPCQSEL1_GPIO78_S 28U +#define GPIO_GPCQSEL1_GPIO78_M 0x30000000U // Select input qualification type for GPIO78 +#define GPIO_GPCQSEL1_GPIO79_S 30U +#define GPIO_GPCQSEL1_GPIO79_M 0xC0000000U // Select input qualification type for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL2_GPIO80_S 0U +#define GPIO_GPCQSEL2_GPIO80_M 0x3U // Select input qualification type for GPIO80 +#define GPIO_GPCQSEL2_GPIO81_S 2U +#define GPIO_GPCQSEL2_GPIO81_M 0xCU // Select input qualification type for GPIO81 +#define GPIO_GPCQSEL2_GPIO82_S 4U +#define GPIO_GPCQSEL2_GPIO82_M 0x30U // Select input qualification type for GPIO82 +#define GPIO_GPCQSEL2_GPIO83_S 6U +#define GPIO_GPCQSEL2_GPIO83_M 0xC0U // Select input qualification type for GPIO83 +#define GPIO_GPCQSEL2_GPIO84_S 8U +#define GPIO_GPCQSEL2_GPIO84_M 0x300U // Select input qualification type for GPIO84 +#define GPIO_GPCQSEL2_GPIO85_S 10U +#define GPIO_GPCQSEL2_GPIO85_M 0xC00U // Select input qualification type for GPIO85 +#define GPIO_GPCQSEL2_GPIO86_S 12U +#define GPIO_GPCQSEL2_GPIO86_M 0x3000U // Select input qualification type for GPIO86 +#define GPIO_GPCQSEL2_GPIO87_S 14U +#define GPIO_GPCQSEL2_GPIO87_M 0xC000U // Select input qualification type for GPIO87 +#define GPIO_GPCQSEL2_GPIO88_S 16U +#define GPIO_GPCQSEL2_GPIO88_M 0x30000U // Select input qualification type for GPIO88 +#define GPIO_GPCQSEL2_GPIO89_S 18U +#define GPIO_GPCQSEL2_GPIO89_M 0xC0000U // Select input qualification type for GPIO89 +#define GPIO_GPCQSEL2_GPIO90_S 20U +#define GPIO_GPCQSEL2_GPIO90_M 0x300000U // Select input qualification type for GPIO90 +#define GPIO_GPCQSEL2_GPIO91_S 22U +#define GPIO_GPCQSEL2_GPIO91_M 0xC00000U // Select input qualification type for GPIO91 +#define GPIO_GPCQSEL2_GPIO92_S 24U +#define GPIO_GPCQSEL2_GPIO92_M 0x3000000U // Select input qualification type for GPIO92 +#define GPIO_GPCQSEL2_GPIO93_S 26U +#define GPIO_GPCQSEL2_GPIO93_M 0xC000000U // Select input qualification type for GPIO93 +#define GPIO_GPCQSEL2_GPIO94_S 28U +#define GPIO_GPCQSEL2_GPIO94_M 0x30000000U // Select input qualification type for GPIO94 +#define GPIO_GPCQSEL2_GPIO95_S 30U +#define GPIO_GPCQSEL2_GPIO95_M 0xC0000000U // Select input qualification type for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCMUX1_GPIO64_S 0U +#define GPIO_GPCMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCMUX1_GPIO65_S 2U +#define GPIO_GPCMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCMUX1_GPIO66_S 4U +#define GPIO_GPCMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCMUX1_GPIO67_S 6U +#define GPIO_GPCMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCMUX1_GPIO68_S 8U +#define GPIO_GPCMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCMUX1_GPIO69_S 10U +#define GPIO_GPCMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCMUX1_GPIO70_S 12U +#define GPIO_GPCMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCMUX1_GPIO71_S 14U +#define GPIO_GPCMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCMUX1_GPIO72_S 16U +#define GPIO_GPCMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCMUX1_GPIO73_S 18U +#define GPIO_GPCMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCMUX1_GPIO74_S 20U +#define GPIO_GPCMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCMUX1_GPIO75_S 22U +#define GPIO_GPCMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCMUX1_GPIO76_S 24U +#define GPIO_GPCMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCMUX1_GPIO77_S 26U +#define GPIO_GPCMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCMUX1_GPIO78_S 28U +#define GPIO_GPCMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCMUX1_GPIO79_S 30U +#define GPIO_GPCMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCMUX2_GPIO80_S 0U +#define GPIO_GPCMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCMUX2_GPIO81_S 2U +#define GPIO_GPCMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCMUX2_GPIO82_S 4U +#define GPIO_GPCMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCMUX2_GPIO83_S 6U +#define GPIO_GPCMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCMUX2_GPIO84_S 8U +#define GPIO_GPCMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCMUX2_GPIO85_S 10U +#define GPIO_GPCMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCMUX2_GPIO86_S 12U +#define GPIO_GPCMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCMUX2_GPIO87_S 14U +#define GPIO_GPCMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCMUX2_GPIO88_S 16U +#define GPIO_GPCMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCMUX2_GPIO89_S 18U +#define GPIO_GPCMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCMUX2_GPIO90_S 20U +#define GPIO_GPCMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCMUX2_GPIO91_S 22U +#define GPIO_GPCMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCMUX2_GPIO92_S 24U +#define GPIO_GPCMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCMUX2_GPIO93_S 26U +#define GPIO_GPCMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCMUX2_GPIO94_S 28U +#define GPIO_GPCMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCMUX2_GPIO95_S 30U +#define GPIO_GPCMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDIR register +// +//************************************************************************************************* +#define GPIO_GPCDIR_GPIO64 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO65 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO66 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO67 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO68 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO69 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO70 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO71 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO72 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO73 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO74 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO75 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO76 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO77 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO78 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO79 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO80 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO81 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO82 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO83 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO84 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO85 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO86 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO87 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO88 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO89 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO90 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO91 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO92 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO93 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO94 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO95 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCPUD register +// +//************************************************************************************************* +#define GPIO_GPCPUD_GPIO64 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO65 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO66 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO67 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO68 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO69 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO70 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO71 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO72 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO73 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO74 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO75 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO76 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO77 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO78 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO79 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO80 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO81 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO82 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO83 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO84 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO85 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO86 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO87 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO88 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO89 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO90 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO91 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO92 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO93 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO94 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO95 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCINV register +// +//************************************************************************************************* +#define GPIO_GPCINV_GPIO64 0x1U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO65 0x2U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO66 0x4U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO67 0x8U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO68 0x10U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO69 0x20U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO70 0x40U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO71 0x80U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO72 0x100U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO73 0x200U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO74 0x400U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO75 0x800U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO76 0x1000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO77 0x2000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO78 0x4000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO79 0x8000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO80 0x10000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO81 0x20000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO82 0x40000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO83 0x80000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO84 0x100000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO85 0x200000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO86 0x400000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO87 0x800000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO88 0x1000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO89 0x2000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO90 0x4000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO91 0x8000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO92 0x10000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO93 0x20000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO94 0x40000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO95 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCODR register +// +//************************************************************************************************* +#define GPIO_GPCODR_GPIO64 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO65 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO66 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO67 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO68 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO69 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO70 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO71 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO72 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO73 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO74 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO75 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO76 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO77 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO78 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO79 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO80 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO81 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO82 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO83 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO84 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO85 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO86 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO87 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO88 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO89 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO90 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO91 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO92 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO93 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO94 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO95 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX1_GPIO64_S 0U +#define GPIO_GPCGMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCGMUX1_GPIO65_S 2U +#define GPIO_GPCGMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCGMUX1_GPIO66_S 4U +#define GPIO_GPCGMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCGMUX1_GPIO67_S 6U +#define GPIO_GPCGMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCGMUX1_GPIO68_S 8U +#define GPIO_GPCGMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCGMUX1_GPIO69_S 10U +#define GPIO_GPCGMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCGMUX1_GPIO70_S 12U +#define GPIO_GPCGMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCGMUX1_GPIO71_S 14U +#define GPIO_GPCGMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCGMUX1_GPIO72_S 16U +#define GPIO_GPCGMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCGMUX1_GPIO73_S 18U +#define GPIO_GPCGMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCGMUX1_GPIO74_S 20U +#define GPIO_GPCGMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCGMUX1_GPIO75_S 22U +#define GPIO_GPCGMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCGMUX1_GPIO76_S 24U +#define GPIO_GPCGMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCGMUX1_GPIO77_S 26U +#define GPIO_GPCGMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCGMUX1_GPIO78_S 28U +#define GPIO_GPCGMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCGMUX1_GPIO79_S 30U +#define GPIO_GPCGMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX2_GPIO80_S 0U +#define GPIO_GPCGMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCGMUX2_GPIO81_S 2U +#define GPIO_GPCGMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCGMUX2_GPIO82_S 4U +#define GPIO_GPCGMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCGMUX2_GPIO83_S 6U +#define GPIO_GPCGMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCGMUX2_GPIO84_S 8U +#define GPIO_GPCGMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCGMUX2_GPIO85_S 10U +#define GPIO_GPCGMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCGMUX2_GPIO86_S 12U +#define GPIO_GPCGMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCGMUX2_GPIO87_S 14U +#define GPIO_GPCGMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCGMUX2_GPIO88_S 16U +#define GPIO_GPCGMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCGMUX2_GPIO89_S 18U +#define GPIO_GPCGMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCGMUX2_GPIO90_S 20U +#define GPIO_GPCGMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCGMUX2_GPIO91_S 22U +#define GPIO_GPCGMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCGMUX2_GPIO92_S 24U +#define GPIO_GPCGMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCGMUX2_GPIO93_S 26U +#define GPIO_GPCGMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCGMUX2_GPIO94_S 28U +#define GPIO_GPCGMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCGMUX2_GPIO95_S 30U +#define GPIO_GPCGMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL1_GPIO64_S 0U +#define GPIO_GPCCSEL1_GPIO64_M 0xFU // GPIO64 Master CPU Select +#define GPIO_GPCCSEL1_GPIO65_S 4U +#define GPIO_GPCCSEL1_GPIO65_M 0xF0U // GPIO65 Master CPU Select +#define GPIO_GPCCSEL1_GPIO66_S 8U +#define GPIO_GPCCSEL1_GPIO66_M 0xF00U // GPIO66 Master CPU Select +#define GPIO_GPCCSEL1_GPIO67_S 12U +#define GPIO_GPCCSEL1_GPIO67_M 0xF000U // GPIO67 Master CPU Select +#define GPIO_GPCCSEL1_GPIO68_S 16U +#define GPIO_GPCCSEL1_GPIO68_M 0xF0000U // GPIO68 Master CPU Select +#define GPIO_GPCCSEL1_GPIO69_S 20U +#define GPIO_GPCCSEL1_GPIO69_M 0xF00000U // GPIO69 Master CPU Select +#define GPIO_GPCCSEL1_GPIO70_S 24U +#define GPIO_GPCCSEL1_GPIO70_M 0xF000000U // GPIO70 Master CPU Select +#define GPIO_GPCCSEL1_GPIO71_S 28U +#define GPIO_GPCCSEL1_GPIO71_M 0xF0000000U // GPIO71 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL2_GPIO72_S 0U +#define GPIO_GPCCSEL2_GPIO72_M 0xFU // GPIO72 Master CPU Select +#define GPIO_GPCCSEL2_GPIO73_S 4U +#define GPIO_GPCCSEL2_GPIO73_M 0xF0U // GPIO73 Master CPU Select +#define GPIO_GPCCSEL2_GPIO74_S 8U +#define GPIO_GPCCSEL2_GPIO74_M 0xF00U // GPIO74 Master CPU Select +#define GPIO_GPCCSEL2_GPIO75_S 12U +#define GPIO_GPCCSEL2_GPIO75_M 0xF000U // GPIO75 Master CPU Select +#define GPIO_GPCCSEL2_GPIO76_S 16U +#define GPIO_GPCCSEL2_GPIO76_M 0xF0000U // GPIO76 Master CPU Select +#define GPIO_GPCCSEL2_GPIO77_S 20U +#define GPIO_GPCCSEL2_GPIO77_M 0xF00000U // GPIO77 Master CPU Select +#define GPIO_GPCCSEL2_GPIO78_S 24U +#define GPIO_GPCCSEL2_GPIO78_M 0xF000000U // GPIO78 Master CPU Select +#define GPIO_GPCCSEL2_GPIO79_S 28U +#define GPIO_GPCCSEL2_GPIO79_M 0xF0000000U // GPIO79 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL3_GPIO80_S 0U +#define GPIO_GPCCSEL3_GPIO80_M 0xFU // GPIO80 Master CPU Select +#define GPIO_GPCCSEL3_GPIO81_S 4U +#define GPIO_GPCCSEL3_GPIO81_M 0xF0U // GPIO81 Master CPU Select +#define GPIO_GPCCSEL3_GPIO82_S 8U +#define GPIO_GPCCSEL3_GPIO82_M 0xF00U // GPIO82 Master CPU Select +#define GPIO_GPCCSEL3_GPIO83_S 12U +#define GPIO_GPCCSEL3_GPIO83_M 0xF000U // GPIO83 Master CPU Select +#define GPIO_GPCCSEL3_GPIO84_S 16U +#define GPIO_GPCCSEL3_GPIO84_M 0xF0000U // GPIO84 Master CPU Select +#define GPIO_GPCCSEL3_GPIO85_S 20U +#define GPIO_GPCCSEL3_GPIO85_M 0xF00000U // GPIO85 Master CPU Select +#define GPIO_GPCCSEL3_GPIO86_S 24U +#define GPIO_GPCCSEL3_GPIO86_M 0xF000000U // GPIO86 Master CPU Select +#define GPIO_GPCCSEL3_GPIO87_S 28U +#define GPIO_GPCCSEL3_GPIO87_M 0xF0000000U // GPIO87 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL4_GPIO88_S 0U +#define GPIO_GPCCSEL4_GPIO88_M 0xFU // GPIO88 Master CPU Select +#define GPIO_GPCCSEL4_GPIO89_S 4U +#define GPIO_GPCCSEL4_GPIO89_M 0xF0U // GPIO89 Master CPU Select +#define GPIO_GPCCSEL4_GPIO90_S 8U +#define GPIO_GPCCSEL4_GPIO90_M 0xF00U // GPIO90 Master CPU Select +#define GPIO_GPCCSEL4_GPIO91_S 12U +#define GPIO_GPCCSEL4_GPIO91_M 0xF000U // GPIO91 Master CPU Select +#define GPIO_GPCCSEL4_GPIO92_S 16U +#define GPIO_GPCCSEL4_GPIO92_M 0xF0000U // GPIO92 Master CPU Select +#define GPIO_GPCCSEL4_GPIO93_S 20U +#define GPIO_GPCCSEL4_GPIO93_M 0xF00000U // GPIO93 Master CPU Select +#define GPIO_GPCCSEL4_GPIO94_S 24U +#define GPIO_GPCCSEL4_GPIO94_M 0xF000000U // GPIO94 Master CPU Select +#define GPIO_GPCCSEL4_GPIO95_S 28U +#define GPIO_GPCCSEL4_GPIO95_M 0xF0000000U // GPIO95 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCLOCK register +// +//************************************************************************************************* +#define GPIO_GPCLOCK_GPIO64 0x1U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO65 0x2U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO66 0x4U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO67 0x8U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO68 0x10U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO69 0x20U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO70 0x40U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO71 0x80U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO72 0x100U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO73 0x200U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO74 0x400U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO75 0x800U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO76 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO77 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO78 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO79 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO80 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO81 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO82 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO83 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO84 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO85 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO86 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO87 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO88 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO89 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO90 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO91 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO92 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO93 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO94 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO95 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCR register +// +//************************************************************************************************* +#define GPIO_GPCCR_GPIO64 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO65 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO66 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO67 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO68 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO69 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO70 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO71 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO72 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO73 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO74 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO75 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO76 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO77 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO78 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO79 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO80 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO81 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO82 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO83 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO84 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO85 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO86 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO87 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO88 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO89 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO90 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO91 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO92 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO93 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO94 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO95 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCTRL register +// +//************************************************************************************************* +#define GPIO_GPDCTRL_QUALPRD0_S 0U +#define GPIO_GPDCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO96 to + // GPIO103 +#define GPIO_GPDCTRL_QUALPRD1_S 8U +#define GPIO_GPDCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO104 to + // GPIO111 +#define GPIO_GPDCTRL_QUALPRD2_S 16U +#define GPIO_GPDCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO112 to + // GPIO119 +#define GPIO_GPDCTRL_QUALPRD3_S 24U +#define GPIO_GPDCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO120 to + // GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL1_GPIO96_S 0U +#define GPIO_GPDQSEL1_GPIO96_M 0x3U // Select input qualification type for GPIO96 +#define GPIO_GPDQSEL1_GPIO97_S 2U +#define GPIO_GPDQSEL1_GPIO97_M 0xCU // Select input qualification type for GPIO97 +#define GPIO_GPDQSEL1_GPIO98_S 4U +#define GPIO_GPDQSEL1_GPIO98_M 0x30U // Select input qualification type for GPIO98 +#define GPIO_GPDQSEL1_GPIO99_S 6U +#define GPIO_GPDQSEL1_GPIO99_M 0xC0U // Select input qualification type for GPIO99 +#define GPIO_GPDQSEL1_GPIO100_S 8U +#define GPIO_GPDQSEL1_GPIO100_M 0x300U // Select input qualification type for GPIO100 +#define GPIO_GPDQSEL1_GPIO101_S 10U +#define GPIO_GPDQSEL1_GPIO101_M 0xC00U // Select input qualification type for GPIO101 +#define GPIO_GPDQSEL1_GPIO102_S 12U +#define GPIO_GPDQSEL1_GPIO102_M 0x3000U // Select input qualification type for GPIO102 +#define GPIO_GPDQSEL1_GPIO103_S 14U +#define GPIO_GPDQSEL1_GPIO103_M 0xC000U // Select input qualification type for GPIO103 +#define GPIO_GPDQSEL1_GPIO104_S 16U +#define GPIO_GPDQSEL1_GPIO104_M 0x30000U // Select input qualification type for GPIO104 +#define GPIO_GPDQSEL1_GPIO105_S 18U +#define GPIO_GPDQSEL1_GPIO105_M 0xC0000U // Select input qualification type for GPIO105 +#define GPIO_GPDQSEL1_GPIO106_S 20U +#define GPIO_GPDQSEL1_GPIO106_M 0x300000U // Select input qualification type for GPIO106 +#define GPIO_GPDQSEL1_GPIO107_S 22U +#define GPIO_GPDQSEL1_GPIO107_M 0xC00000U // Select input qualification type for GPIO107 +#define GPIO_GPDQSEL1_GPIO108_S 24U +#define GPIO_GPDQSEL1_GPIO108_M 0x3000000U // Select input qualification type for GPIO108 +#define GPIO_GPDQSEL1_GPIO109_S 26U +#define GPIO_GPDQSEL1_GPIO109_M 0xC000000U // Select input qualification type for GPIO109 +#define GPIO_GPDQSEL1_GPIO110_S 28U +#define GPIO_GPDQSEL1_GPIO110_M 0x30000000U // Select input qualification type for GPIO110 +#define GPIO_GPDQSEL1_GPIO111_S 30U +#define GPIO_GPDQSEL1_GPIO111_M 0xC0000000U // Select input qualification type for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL2_GPIO112_S 0U +#define GPIO_GPDQSEL2_GPIO112_M 0x3U // Select input qualification type for GPIO112 +#define GPIO_GPDQSEL2_GPIO113_S 2U +#define GPIO_GPDQSEL2_GPIO113_M 0xCU // Select input qualification type for GPIO113 +#define GPIO_GPDQSEL2_GPIO114_S 4U +#define GPIO_GPDQSEL2_GPIO114_M 0x30U // Select input qualification type for GPIO114 +#define GPIO_GPDQSEL2_GPIO115_S 6U +#define GPIO_GPDQSEL2_GPIO115_M 0xC0U // Select input qualification type for GPIO115 +#define GPIO_GPDQSEL2_GPIO116_S 8U +#define GPIO_GPDQSEL2_GPIO116_M 0x300U // Select input qualification type for GPIO116 +#define GPIO_GPDQSEL2_GPIO117_S 10U +#define GPIO_GPDQSEL2_GPIO117_M 0xC00U // Select input qualification type for GPIO117 +#define GPIO_GPDQSEL2_GPIO118_S 12U +#define GPIO_GPDQSEL2_GPIO118_M 0x3000U // Select input qualification type for GPIO118 +#define GPIO_GPDQSEL2_GPIO119_S 14U +#define GPIO_GPDQSEL2_GPIO119_M 0xC000U // Select input qualification type for GPIO119 +#define GPIO_GPDQSEL2_GPIO120_S 16U +#define GPIO_GPDQSEL2_GPIO120_M 0x30000U // Select input qualification type for GPIO120 +#define GPIO_GPDQSEL2_GPIO121_S 18U +#define GPIO_GPDQSEL2_GPIO121_M 0xC0000U // Select input qualification type for GPIO121 +#define GPIO_GPDQSEL2_GPIO122_S 20U +#define GPIO_GPDQSEL2_GPIO122_M 0x300000U // Select input qualification type for GPIO122 +#define GPIO_GPDQSEL2_GPIO123_S 22U +#define GPIO_GPDQSEL2_GPIO123_M 0xC00000U // Select input qualification type for GPIO123 +#define GPIO_GPDQSEL2_GPIO124_S 24U +#define GPIO_GPDQSEL2_GPIO124_M 0x3000000U // Select input qualification type for GPIO124 +#define GPIO_GPDQSEL2_GPIO125_S 26U +#define GPIO_GPDQSEL2_GPIO125_M 0xC000000U // Select input qualification type for GPIO125 +#define GPIO_GPDQSEL2_GPIO126_S 28U +#define GPIO_GPDQSEL2_GPIO126_M 0x30000000U // Select input qualification type for GPIO126 +#define GPIO_GPDQSEL2_GPIO127_S 30U +#define GPIO_GPDQSEL2_GPIO127_M 0xC0000000U // Select input qualification type for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDMUX1_GPIO96_S 0U +#define GPIO_GPDMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDMUX1_GPIO97_S 2U +#define GPIO_GPDMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDMUX1_GPIO98_S 4U +#define GPIO_GPDMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDMUX1_GPIO99_S 6U +#define GPIO_GPDMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDMUX1_GPIO100_S 8U +#define GPIO_GPDMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDMUX1_GPIO101_S 10U +#define GPIO_GPDMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDMUX1_GPIO102_S 12U +#define GPIO_GPDMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDMUX1_GPIO103_S 14U +#define GPIO_GPDMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDMUX1_GPIO104_S 16U +#define GPIO_GPDMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDMUX1_GPIO105_S 18U +#define GPIO_GPDMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDMUX1_GPIO106_S 20U +#define GPIO_GPDMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDMUX1_GPIO107_S 22U +#define GPIO_GPDMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDMUX1_GPIO108_S 24U +#define GPIO_GPDMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDMUX1_GPIO109_S 26U +#define GPIO_GPDMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDMUX1_GPIO110_S 28U +#define GPIO_GPDMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDMUX1_GPIO111_S 30U +#define GPIO_GPDMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDMUX2_GPIO112_S 0U +#define GPIO_GPDMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDMUX2_GPIO113_S 2U +#define GPIO_GPDMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDMUX2_GPIO114_S 4U +#define GPIO_GPDMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDMUX2_GPIO115_S 6U +#define GPIO_GPDMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDMUX2_GPIO116_S 8U +#define GPIO_GPDMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDMUX2_GPIO117_S 10U +#define GPIO_GPDMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDMUX2_GPIO118_S 12U +#define GPIO_GPDMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDMUX2_GPIO119_S 14U +#define GPIO_GPDMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDMUX2_GPIO120_S 16U +#define GPIO_GPDMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDMUX2_GPIO121_S 18U +#define GPIO_GPDMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDMUX2_GPIO122_S 20U +#define GPIO_GPDMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDMUX2_GPIO123_S 22U +#define GPIO_GPDMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDMUX2_GPIO124_S 24U +#define GPIO_GPDMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDMUX2_GPIO125_S 26U +#define GPIO_GPDMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDMUX2_GPIO126_S 28U +#define GPIO_GPDMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDMUX2_GPIO127_S 30U +#define GPIO_GPDMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDIR register +// +//************************************************************************************************* +#define GPIO_GPDDIR_GPIO96 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO97 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO98 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO99 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO100 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO101 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO102 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO103 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO104 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO105 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO106 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO107 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO108 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO109 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO110 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO111 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO112 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO113 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO114 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO115 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO116 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO117 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO118 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO119 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO120 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO121 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO122 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO123 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO124 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO125 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO126 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO127 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDPUD register +// +//************************************************************************************************* +#define GPIO_GPDPUD_GPIO96 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO97 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO98 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO99 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO100 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO101 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO102 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO103 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO104 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO105 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO106 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO107 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO108 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO109 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO110 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO111 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO112 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO113 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO114 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO115 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO116 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO117 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO118 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO119 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO120 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO121 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO122 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO123 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO124 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO125 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO126 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO127 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDINV register +// +//************************************************************************************************* +#define GPIO_GPDINV_GPIO96 0x1U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO97 0x2U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO98 0x4U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO99 0x8U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO100 0x10U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO101 0x20U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO102 0x40U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO103 0x80U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO104 0x100U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO105 0x200U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO106 0x400U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO107 0x800U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO108 0x1000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO109 0x2000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO110 0x4000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO111 0x8000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO112 0x10000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO113 0x20000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO114 0x40000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO115 0x80000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO116 0x100000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO117 0x200000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO118 0x400000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO119 0x800000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO120 0x1000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO121 0x2000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO122 0x4000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO123 0x8000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO124 0x10000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO125 0x20000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO126 0x40000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO127 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDODR register +// +//************************************************************************************************* +#define GPIO_GPDODR_GPIO96 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO97 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO98 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO99 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO100 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO101 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO102 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO103 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO104 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO105 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO106 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO107 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO108 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO109 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO110 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO111 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO112 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO113 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO114 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO115 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO116 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO117 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO118 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO119 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO120 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO121 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO122 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO123 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO124 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO125 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO126 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO127 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX1_GPIO96_S 0U +#define GPIO_GPDGMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDGMUX1_GPIO97_S 2U +#define GPIO_GPDGMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDGMUX1_GPIO98_S 4U +#define GPIO_GPDGMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDGMUX1_GPIO99_S 6U +#define GPIO_GPDGMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDGMUX1_GPIO100_S 8U +#define GPIO_GPDGMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDGMUX1_GPIO101_S 10U +#define GPIO_GPDGMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDGMUX1_GPIO102_S 12U +#define GPIO_GPDGMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDGMUX1_GPIO103_S 14U +#define GPIO_GPDGMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDGMUX1_GPIO104_S 16U +#define GPIO_GPDGMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDGMUX1_GPIO105_S 18U +#define GPIO_GPDGMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDGMUX1_GPIO106_S 20U +#define GPIO_GPDGMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDGMUX1_GPIO107_S 22U +#define GPIO_GPDGMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDGMUX1_GPIO108_S 24U +#define GPIO_GPDGMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDGMUX1_GPIO109_S 26U +#define GPIO_GPDGMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDGMUX1_GPIO110_S 28U +#define GPIO_GPDGMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDGMUX1_GPIO111_S 30U +#define GPIO_GPDGMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX2_GPIO112_S 0U +#define GPIO_GPDGMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDGMUX2_GPIO113_S 2U +#define GPIO_GPDGMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDGMUX2_GPIO114_S 4U +#define GPIO_GPDGMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDGMUX2_GPIO115_S 6U +#define GPIO_GPDGMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDGMUX2_GPIO116_S 8U +#define GPIO_GPDGMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDGMUX2_GPIO117_S 10U +#define GPIO_GPDGMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDGMUX2_GPIO118_S 12U +#define GPIO_GPDGMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDGMUX2_GPIO119_S 14U +#define GPIO_GPDGMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDGMUX2_GPIO120_S 16U +#define GPIO_GPDGMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDGMUX2_GPIO121_S 18U +#define GPIO_GPDGMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDGMUX2_GPIO122_S 20U +#define GPIO_GPDGMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDGMUX2_GPIO123_S 22U +#define GPIO_GPDGMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDGMUX2_GPIO124_S 24U +#define GPIO_GPDGMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDGMUX2_GPIO125_S 26U +#define GPIO_GPDGMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDGMUX2_GPIO126_S 28U +#define GPIO_GPDGMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDGMUX2_GPIO127_S 30U +#define GPIO_GPDGMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL1_GPIO96_S 0U +#define GPIO_GPDCSEL1_GPIO96_M 0xFU // GPIO96 Master CPU Select +#define GPIO_GPDCSEL1_GPIO97_S 4U +#define GPIO_GPDCSEL1_GPIO97_M 0xF0U // GPIO97 Master CPU Select +#define GPIO_GPDCSEL1_GPIO98_S 8U +#define GPIO_GPDCSEL1_GPIO98_M 0xF00U // GPIO98 Master CPU Select +#define GPIO_GPDCSEL1_GPIO99_S 12U +#define GPIO_GPDCSEL1_GPIO99_M 0xF000U // GPIO99 Master CPU Select +#define GPIO_GPDCSEL1_GPIO100_S 16U +#define GPIO_GPDCSEL1_GPIO100_M 0xF0000U // GPIO100 Master CPU Select +#define GPIO_GPDCSEL1_GPIO101_S 20U +#define GPIO_GPDCSEL1_GPIO101_M 0xF00000U // GPIO101 Master CPU Select +#define GPIO_GPDCSEL1_GPIO102_S 24U +#define GPIO_GPDCSEL1_GPIO102_M 0xF000000U // GPIO102 Master CPU Select +#define GPIO_GPDCSEL1_GPIO103_S 28U +#define GPIO_GPDCSEL1_GPIO103_M 0xF0000000U // GPIO103 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL2_GPIO104_S 0U +#define GPIO_GPDCSEL2_GPIO104_M 0xFU // GPIO104 Master CPU Select +#define GPIO_GPDCSEL2_GPIO105_S 4U +#define GPIO_GPDCSEL2_GPIO105_M 0xF0U // GPIO105 Master CPU Select +#define GPIO_GPDCSEL2_GPIO106_S 8U +#define GPIO_GPDCSEL2_GPIO106_M 0xF00U // GPIO106 Master CPU Select +#define GPIO_GPDCSEL2_GPIO107_S 12U +#define GPIO_GPDCSEL2_GPIO107_M 0xF000U // GPIO107 Master CPU Select +#define GPIO_GPDCSEL2_GPIO108_S 16U +#define GPIO_GPDCSEL2_GPIO108_M 0xF0000U // GPIO108 Master CPU Select +#define GPIO_GPDCSEL2_GPIO109_S 20U +#define GPIO_GPDCSEL2_GPIO109_M 0xF00000U // GPIO109 Master CPU Select +#define GPIO_GPDCSEL2_GPIO110_S 24U +#define GPIO_GPDCSEL2_GPIO110_M 0xF000000U // GPIO110 Master CPU Select +#define GPIO_GPDCSEL2_GPIO111_S 28U +#define GPIO_GPDCSEL2_GPIO111_M 0xF0000000U // GPIO111 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL3_GPIO112_S 0U +#define GPIO_GPDCSEL3_GPIO112_M 0xFU // GPIO112 Master CPU Select +#define GPIO_GPDCSEL3_GPIO113_S 4U +#define GPIO_GPDCSEL3_GPIO113_M 0xF0U // GPIO113 Master CPU Select +#define GPIO_GPDCSEL3_GPIO114_S 8U +#define GPIO_GPDCSEL3_GPIO114_M 0xF00U // GPIO114 Master CPU Select +#define GPIO_GPDCSEL3_GPIO115_S 12U +#define GPIO_GPDCSEL3_GPIO115_M 0xF000U // GPIO115 Master CPU Select +#define GPIO_GPDCSEL3_GPIO116_S 16U +#define GPIO_GPDCSEL3_GPIO116_M 0xF0000U // GPIO116 Master CPU Select +#define GPIO_GPDCSEL3_GPIO117_S 20U +#define GPIO_GPDCSEL3_GPIO117_M 0xF00000U // GPIO117 Master CPU Select +#define GPIO_GPDCSEL3_GPIO118_S 24U +#define GPIO_GPDCSEL3_GPIO118_M 0xF000000U // GPIO118 Master CPU Select +#define GPIO_GPDCSEL3_GPIO119_S 28U +#define GPIO_GPDCSEL3_GPIO119_M 0xF0000000U // GPIO119 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL4_GPIO120_S 0U +#define GPIO_GPDCSEL4_GPIO120_M 0xFU // GPIO120 Master CPU Select +#define GPIO_GPDCSEL4_GPIO121_S 4U +#define GPIO_GPDCSEL4_GPIO121_M 0xF0U // GPIO121 Master CPU Select +#define GPIO_GPDCSEL4_GPIO122_S 8U +#define GPIO_GPDCSEL4_GPIO122_M 0xF00U // GPIO122 Master CPU Select +#define GPIO_GPDCSEL4_GPIO123_S 12U +#define GPIO_GPDCSEL4_GPIO123_M 0xF000U // GPIO123 Master CPU Select +#define GPIO_GPDCSEL4_GPIO124_S 16U +#define GPIO_GPDCSEL4_GPIO124_M 0xF0000U // GPIO124 Master CPU Select +#define GPIO_GPDCSEL4_GPIO125_S 20U +#define GPIO_GPDCSEL4_GPIO125_M 0xF00000U // GPIO125 Master CPU Select +#define GPIO_GPDCSEL4_GPIO126_S 24U +#define GPIO_GPDCSEL4_GPIO126_M 0xF000000U // GPIO126 Master CPU Select +#define GPIO_GPDCSEL4_GPIO127_S 28U +#define GPIO_GPDCSEL4_GPIO127_M 0xF0000000U // GPIO127 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDLOCK register +// +//************************************************************************************************* +#define GPIO_GPDLOCK_GPIO96 0x1U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO97 0x2U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO98 0x4U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO99 0x8U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO100 0x10U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO101 0x20U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO102 0x40U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO103 0x80U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO104 0x100U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO105 0x200U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO106 0x400U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO107 0x800U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO108 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO109 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO110 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO111 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO112 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO113 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO114 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO115 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO116 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO117 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO118 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO119 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO120 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO121 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO122 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO123 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO124 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO125 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO126 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO127 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCR register +// +//************************************************************************************************* +#define GPIO_GPDCR_GPIO96 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO97 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO98 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO99 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO100 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO101 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO102 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO103 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO104 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO105 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO106 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO107 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO108 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO109 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO110 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO111 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO112 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO113 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO114 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO115 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO116 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO117 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO118 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO119 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO120 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO121 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO122 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO123 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO124 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO125 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO126 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO127 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECTRL register +// +//************************************************************************************************* +#define GPIO_GPECTRL_QUALPRD0_S 0U +#define GPIO_GPECTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO128 to + // GPIO135 +#define GPIO_GPECTRL_QUALPRD1_S 8U +#define GPIO_GPECTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO136 to + // GPIO143 +#define GPIO_GPECTRL_QUALPRD2_S 16U +#define GPIO_GPECTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO144 to + // GPIO151 +#define GPIO_GPECTRL_QUALPRD3_S 24U +#define GPIO_GPECTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO152 to + // GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL1_GPIO128_S 0U +#define GPIO_GPEQSEL1_GPIO128_M 0x3U // Select input qualification type for GPIO128 +#define GPIO_GPEQSEL1_GPIO129_S 2U +#define GPIO_GPEQSEL1_GPIO129_M 0xCU // Select input qualification type for GPIO129 +#define GPIO_GPEQSEL1_GPIO130_S 4U +#define GPIO_GPEQSEL1_GPIO130_M 0x30U // Select input qualification type for GPIO130 +#define GPIO_GPEQSEL1_GPIO131_S 6U +#define GPIO_GPEQSEL1_GPIO131_M 0xC0U // Select input qualification type for GPIO131 +#define GPIO_GPEQSEL1_GPIO132_S 8U +#define GPIO_GPEQSEL1_GPIO132_M 0x300U // Select input qualification type for GPIO132 +#define GPIO_GPEQSEL1_GPIO133_S 10U +#define GPIO_GPEQSEL1_GPIO133_M 0xC00U // Select input qualification type for GPIO133 +#define GPIO_GPEQSEL1_GPIO134_S 12U +#define GPIO_GPEQSEL1_GPIO134_M 0x3000U // Select input qualification type for GPIO134 +#define GPIO_GPEQSEL1_GPIO135_S 14U +#define GPIO_GPEQSEL1_GPIO135_M 0xC000U // Select input qualification type for GPIO135 +#define GPIO_GPEQSEL1_GPIO136_S 16U +#define GPIO_GPEQSEL1_GPIO136_M 0x30000U // Select input qualification type for GPIO136 +#define GPIO_GPEQSEL1_GPIO137_S 18U +#define GPIO_GPEQSEL1_GPIO137_M 0xC0000U // Select input qualification type for GPIO137 +#define GPIO_GPEQSEL1_GPIO138_S 20U +#define GPIO_GPEQSEL1_GPIO138_M 0x300000U // Select input qualification type for GPIO138 +#define GPIO_GPEQSEL1_GPIO139_S 22U +#define GPIO_GPEQSEL1_GPIO139_M 0xC00000U // Select input qualification type for GPIO139 +#define GPIO_GPEQSEL1_GPIO140_S 24U +#define GPIO_GPEQSEL1_GPIO140_M 0x3000000U // Select input qualification type for GPIO140 +#define GPIO_GPEQSEL1_GPIO141_S 26U +#define GPIO_GPEQSEL1_GPIO141_M 0xC000000U // Select input qualification type for GPIO141 +#define GPIO_GPEQSEL1_GPIO142_S 28U +#define GPIO_GPEQSEL1_GPIO142_M 0x30000000U // Select input qualification type for GPIO142 +#define GPIO_GPEQSEL1_GPIO143_S 30U +#define GPIO_GPEQSEL1_GPIO143_M 0xC0000000U // Select input qualification type for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL2_GPIO144_S 0U +#define GPIO_GPEQSEL2_GPIO144_M 0x3U // Select input qualification type for GPIO144 +#define GPIO_GPEQSEL2_GPIO145_S 2U +#define GPIO_GPEQSEL2_GPIO145_M 0xCU // Select input qualification type for GPIO145 +#define GPIO_GPEQSEL2_GPIO146_S 4U +#define GPIO_GPEQSEL2_GPIO146_M 0x30U // Select input qualification type for GPIO146 +#define GPIO_GPEQSEL2_GPIO147_S 6U +#define GPIO_GPEQSEL2_GPIO147_M 0xC0U // Select input qualification type for GPIO147 +#define GPIO_GPEQSEL2_GPIO148_S 8U +#define GPIO_GPEQSEL2_GPIO148_M 0x300U // Select input qualification type for GPIO148 +#define GPIO_GPEQSEL2_GPIO149_S 10U +#define GPIO_GPEQSEL2_GPIO149_M 0xC00U // Select input qualification type for GPIO149 +#define GPIO_GPEQSEL2_GPIO150_S 12U +#define GPIO_GPEQSEL2_GPIO150_M 0x3000U // Select input qualification type for GPIO150 +#define GPIO_GPEQSEL2_GPIO151_S 14U +#define GPIO_GPEQSEL2_GPIO151_M 0xC000U // Select input qualification type for GPIO151 +#define GPIO_GPEQSEL2_GPIO152_S 16U +#define GPIO_GPEQSEL2_GPIO152_M 0x30000U // Select input qualification type for GPIO152 +#define GPIO_GPEQSEL2_GPIO153_S 18U +#define GPIO_GPEQSEL2_GPIO153_M 0xC0000U // Select input qualification type for GPIO153 +#define GPIO_GPEQSEL2_GPIO154_S 20U +#define GPIO_GPEQSEL2_GPIO154_M 0x300000U // Select input qualification type for GPIO154 +#define GPIO_GPEQSEL2_GPIO155_S 22U +#define GPIO_GPEQSEL2_GPIO155_M 0xC00000U // Select input qualification type for GPIO155 +#define GPIO_GPEQSEL2_GPIO156_S 24U +#define GPIO_GPEQSEL2_GPIO156_M 0x3000000U // Select input qualification type for GPIO156 +#define GPIO_GPEQSEL2_GPIO157_S 26U +#define GPIO_GPEQSEL2_GPIO157_M 0xC000000U // Select input qualification type for GPIO157 +#define GPIO_GPEQSEL2_GPIO158_S 28U +#define GPIO_GPEQSEL2_GPIO158_M 0x30000000U // Select input qualification type for GPIO158 +#define GPIO_GPEQSEL2_GPIO159_S 30U +#define GPIO_GPEQSEL2_GPIO159_M 0xC0000000U // Select input qualification type for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEMUX1_GPIO128_S 0U +#define GPIO_GPEMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEMUX1_GPIO129_S 2U +#define GPIO_GPEMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEMUX1_GPIO130_S 4U +#define GPIO_GPEMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEMUX1_GPIO131_S 6U +#define GPIO_GPEMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEMUX1_GPIO132_S 8U +#define GPIO_GPEMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEMUX1_GPIO133_S 10U +#define GPIO_GPEMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEMUX1_GPIO134_S 12U +#define GPIO_GPEMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEMUX1_GPIO135_S 14U +#define GPIO_GPEMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEMUX1_GPIO136_S 16U +#define GPIO_GPEMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEMUX1_GPIO137_S 18U +#define GPIO_GPEMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEMUX1_GPIO138_S 20U +#define GPIO_GPEMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEMUX1_GPIO139_S 22U +#define GPIO_GPEMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEMUX1_GPIO140_S 24U +#define GPIO_GPEMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEMUX1_GPIO141_S 26U +#define GPIO_GPEMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEMUX1_GPIO142_S 28U +#define GPIO_GPEMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEMUX1_GPIO143_S 30U +#define GPIO_GPEMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEMUX2_GPIO144_S 0U +#define GPIO_GPEMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEMUX2_GPIO145_S 2U +#define GPIO_GPEMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEMUX2_GPIO146_S 4U +#define GPIO_GPEMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEMUX2_GPIO147_S 6U +#define GPIO_GPEMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEMUX2_GPIO148_S 8U +#define GPIO_GPEMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEMUX2_GPIO149_S 10U +#define GPIO_GPEMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEMUX2_GPIO150_S 12U +#define GPIO_GPEMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEMUX2_GPIO151_S 14U +#define GPIO_GPEMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEMUX2_GPIO152_S 16U +#define GPIO_GPEMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEMUX2_GPIO153_S 18U +#define GPIO_GPEMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEMUX2_GPIO154_S 20U +#define GPIO_GPEMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEMUX2_GPIO155_S 22U +#define GPIO_GPEMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEMUX2_GPIO156_S 24U +#define GPIO_GPEMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEMUX2_GPIO157_S 26U +#define GPIO_GPEMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEMUX2_GPIO158_S 28U +#define GPIO_GPEMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEMUX2_GPIO159_S 30U +#define GPIO_GPEMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDIR register +// +//************************************************************************************************* +#define GPIO_GPEDIR_GPIO128 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO129 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO130 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO131 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO132 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO133 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO134 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO135 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO136 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO137 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO138 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO139 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO140 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO141 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO142 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO143 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO144 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO145 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO146 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO147 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO148 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO149 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO150 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO151 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO152 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO153 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO154 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO155 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO156 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO157 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO158 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO159 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEPUD register +// +//************************************************************************************************* +#define GPIO_GPEPUD_GPIO128 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO129 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO130 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO131 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO132 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO133 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO134 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO135 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO136 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO137 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO138 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO139 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO140 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO141 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO142 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO143 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO144 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO145 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO146 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO147 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO148 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO149 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO150 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO151 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO152 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO153 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO154 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO155 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO156 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO157 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO158 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO159 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEINV register +// +//************************************************************************************************* +#define GPIO_GPEINV_GPIO128 0x1U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO129 0x2U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO130 0x4U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO131 0x8U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO132 0x10U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO133 0x20U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO134 0x40U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO135 0x80U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO136 0x100U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO137 0x200U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO138 0x400U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO139 0x800U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO140 0x1000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO141 0x2000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO142 0x4000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO143 0x8000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO144 0x10000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO145 0x20000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO146 0x40000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO147 0x80000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO148 0x100000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO149 0x200000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO150 0x400000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO151 0x800000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO152 0x1000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO153 0x2000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO154 0x4000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO155 0x8000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO156 0x10000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO157 0x20000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO158 0x40000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO159 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEODR register +// +//************************************************************************************************* +#define GPIO_GPEODR_GPIO128 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO129 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO130 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO131 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO132 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO133 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO134 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO135 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO136 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO137 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO138 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO139 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO140 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO141 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO142 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO143 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO144 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO145 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO146 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO147 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO148 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO149 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO150 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO151 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO152 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO153 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO154 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO155 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO156 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO157 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO158 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO159 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX1_GPIO128_S 0U +#define GPIO_GPEGMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEGMUX1_GPIO129_S 2U +#define GPIO_GPEGMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEGMUX1_GPIO130_S 4U +#define GPIO_GPEGMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEGMUX1_GPIO131_S 6U +#define GPIO_GPEGMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEGMUX1_GPIO132_S 8U +#define GPIO_GPEGMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEGMUX1_GPIO133_S 10U +#define GPIO_GPEGMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEGMUX1_GPIO134_S 12U +#define GPIO_GPEGMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEGMUX1_GPIO135_S 14U +#define GPIO_GPEGMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEGMUX1_GPIO136_S 16U +#define GPIO_GPEGMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEGMUX1_GPIO137_S 18U +#define GPIO_GPEGMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEGMUX1_GPIO138_S 20U +#define GPIO_GPEGMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEGMUX1_GPIO139_S 22U +#define GPIO_GPEGMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEGMUX1_GPIO140_S 24U +#define GPIO_GPEGMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEGMUX1_GPIO141_S 26U +#define GPIO_GPEGMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEGMUX1_GPIO142_S 28U +#define GPIO_GPEGMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEGMUX1_GPIO143_S 30U +#define GPIO_GPEGMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX2_GPIO144_S 0U +#define GPIO_GPEGMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEGMUX2_GPIO145_S 2U +#define GPIO_GPEGMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEGMUX2_GPIO146_S 4U +#define GPIO_GPEGMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEGMUX2_GPIO147_S 6U +#define GPIO_GPEGMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEGMUX2_GPIO148_S 8U +#define GPIO_GPEGMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEGMUX2_GPIO149_S 10U +#define GPIO_GPEGMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEGMUX2_GPIO150_S 12U +#define GPIO_GPEGMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEGMUX2_GPIO151_S 14U +#define GPIO_GPEGMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEGMUX2_GPIO152_S 16U +#define GPIO_GPEGMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEGMUX2_GPIO153_S 18U +#define GPIO_GPEGMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEGMUX2_GPIO154_S 20U +#define GPIO_GPEGMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEGMUX2_GPIO155_S 22U +#define GPIO_GPEGMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEGMUX2_GPIO156_S 24U +#define GPIO_GPEGMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEGMUX2_GPIO157_S 26U +#define GPIO_GPEGMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEGMUX2_GPIO158_S 28U +#define GPIO_GPEGMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEGMUX2_GPIO159_S 30U +#define GPIO_GPEGMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL1 register +// +//************************************************************************************************* +#define GPIO_GPECSEL1_GPIO128_S 0U +#define GPIO_GPECSEL1_GPIO128_M 0xFU // GPIO128 Master CPU Select +#define GPIO_GPECSEL1_GPIO129_S 4U +#define GPIO_GPECSEL1_GPIO129_M 0xF0U // GPIO129 Master CPU Select +#define GPIO_GPECSEL1_GPIO130_S 8U +#define GPIO_GPECSEL1_GPIO130_M 0xF00U // GPIO130 Master CPU Select +#define GPIO_GPECSEL1_GPIO131_S 12U +#define GPIO_GPECSEL1_GPIO131_M 0xF000U // GPIO131 Master CPU Select +#define GPIO_GPECSEL1_GPIO132_S 16U +#define GPIO_GPECSEL1_GPIO132_M 0xF0000U // GPIO132 Master CPU Select +#define GPIO_GPECSEL1_GPIO133_S 20U +#define GPIO_GPECSEL1_GPIO133_M 0xF00000U // GPIO133 Master CPU Select +#define GPIO_GPECSEL1_GPIO134_S 24U +#define GPIO_GPECSEL1_GPIO134_M 0xF000000U // GPIO134 Master CPU Select +#define GPIO_GPECSEL1_GPIO135_S 28U +#define GPIO_GPECSEL1_GPIO135_M 0xF0000000U // GPIO135 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL2 register +// +//************************************************************************************************* +#define GPIO_GPECSEL2_GPIO136_S 0U +#define GPIO_GPECSEL2_GPIO136_M 0xFU // GPIO136 Master CPU Select +#define GPIO_GPECSEL2_GPIO137_S 4U +#define GPIO_GPECSEL2_GPIO137_M 0xF0U // GPIO137 Master CPU Select +#define GPIO_GPECSEL2_GPIO138_S 8U +#define GPIO_GPECSEL2_GPIO138_M 0xF00U // GPIO138 Master CPU Select +#define GPIO_GPECSEL2_GPIO139_S 12U +#define GPIO_GPECSEL2_GPIO139_M 0xF000U // GPIO139 Master CPU Select +#define GPIO_GPECSEL2_GPIO140_S 16U +#define GPIO_GPECSEL2_GPIO140_M 0xF0000U // GPIO140 Master CPU Select +#define GPIO_GPECSEL2_GPIO141_S 20U +#define GPIO_GPECSEL2_GPIO141_M 0xF00000U // GPIO141 Master CPU Select +#define GPIO_GPECSEL2_GPIO142_S 24U +#define GPIO_GPECSEL2_GPIO142_M 0xF000000U // GPIO142 Master CPU Select +#define GPIO_GPECSEL2_GPIO143_S 28U +#define GPIO_GPECSEL2_GPIO143_M 0xF0000000U // GPIO143 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL3 register +// +//************************************************************************************************* +#define GPIO_GPECSEL3_GPIO144_S 0U +#define GPIO_GPECSEL3_GPIO144_M 0xFU // GPIO144 Master CPU Select +#define GPIO_GPECSEL3_GPIO145_S 4U +#define GPIO_GPECSEL3_GPIO145_M 0xF0U // GPIO145 Master CPU Select +#define GPIO_GPECSEL3_GPIO146_S 8U +#define GPIO_GPECSEL3_GPIO146_M 0xF00U // GPIO146 Master CPU Select +#define GPIO_GPECSEL3_GPIO147_S 12U +#define GPIO_GPECSEL3_GPIO147_M 0xF000U // GPIO147 Master CPU Select +#define GPIO_GPECSEL3_GPIO148_S 16U +#define GPIO_GPECSEL3_GPIO148_M 0xF0000U // GPIO148 Master CPU Select +#define GPIO_GPECSEL3_GPIO149_S 20U +#define GPIO_GPECSEL3_GPIO149_M 0xF00000U // GPIO149 Master CPU Select +#define GPIO_GPECSEL3_GPIO150_S 24U +#define GPIO_GPECSEL3_GPIO150_M 0xF000000U // GPIO150 Master CPU Select +#define GPIO_GPECSEL3_GPIO151_S 28U +#define GPIO_GPECSEL3_GPIO151_M 0xF0000000U // GPIO151 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL4 register +// +//************************************************************************************************* +#define GPIO_GPECSEL4_GPIO152_S 0U +#define GPIO_GPECSEL4_GPIO152_M 0xFU // GPIO152 Master CPU Select +#define GPIO_GPECSEL4_GPIO153_S 4U +#define GPIO_GPECSEL4_GPIO153_M 0xF0U // GPIO153 Master CPU Select +#define GPIO_GPECSEL4_GPIO154_S 8U +#define GPIO_GPECSEL4_GPIO154_M 0xF00U // GPIO154 Master CPU Select +#define GPIO_GPECSEL4_GPIO155_S 12U +#define GPIO_GPECSEL4_GPIO155_M 0xF000U // GPIO155 Master CPU Select +#define GPIO_GPECSEL4_GPIO156_S 16U +#define GPIO_GPECSEL4_GPIO156_M 0xF0000U // GPIO156 Master CPU Select +#define GPIO_GPECSEL4_GPIO157_S 20U +#define GPIO_GPECSEL4_GPIO157_M 0xF00000U // GPIO157 Master CPU Select +#define GPIO_GPECSEL4_GPIO158_S 24U +#define GPIO_GPECSEL4_GPIO158_M 0xF000000U // GPIO158 Master CPU Select +#define GPIO_GPECSEL4_GPIO159_S 28U +#define GPIO_GPECSEL4_GPIO159_M 0xF0000000U // GPIO159 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPELOCK register +// +//************************************************************************************************* +#define GPIO_GPELOCK_GPIO128 0x1U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO129 0x2U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO130 0x4U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO131 0x8U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO132 0x10U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO133 0x20U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO134 0x40U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO135 0x80U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO136 0x100U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO137 0x200U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO138 0x400U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO139 0x800U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO140 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO141 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO142 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO143 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO144 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO145 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO146 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO147 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO148 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO149 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO150 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO151 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO152 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO153 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO154 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO155 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO156 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO157 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO158 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO159 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECR register +// +//************************************************************************************************* +#define GPIO_GPECR_GPIO128 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO129 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO130 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO131 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO132 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO133 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO134 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO135 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO136 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO137 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO138 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO139 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO140 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO141 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO142 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO143 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO144 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO145 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO146 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO147 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO148 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO149 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO150 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO151 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO152 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO153 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO154 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO155 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO156 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO157 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO158 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO159 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCTRL register +// +//************************************************************************************************* +#define GPIO_GPFCTRL_QUALPRD0_S 0U +#define GPIO_GPFCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO160 to GPIO167 +#define GPIO_GPFCTRL_QUALPRD1_S 8U +#define GPIO_GPFCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFQSEL1_GPIO160_S 0U +#define GPIO_GPFQSEL1_GPIO160_M 0x3U // Select input qualification type for GPIO160 +#define GPIO_GPFQSEL1_GPIO161_S 2U +#define GPIO_GPFQSEL1_GPIO161_M 0xCU // Select input qualification type for GPIO161 +#define GPIO_GPFQSEL1_GPIO162_S 4U +#define GPIO_GPFQSEL1_GPIO162_M 0x30U // Select input qualification type for GPIO162 +#define GPIO_GPFQSEL1_GPIO163_S 6U +#define GPIO_GPFQSEL1_GPIO163_M 0xC0U // Select input qualification type for GPIO163 +#define GPIO_GPFQSEL1_GPIO164_S 8U +#define GPIO_GPFQSEL1_GPIO164_M 0x300U // Select input qualification type for GPIO164 +#define GPIO_GPFQSEL1_GPIO165_S 10U +#define GPIO_GPFQSEL1_GPIO165_M 0xC00U // Select input qualification type for GPIO165 +#define GPIO_GPFQSEL1_GPIO166_S 12U +#define GPIO_GPFQSEL1_GPIO166_M 0x3000U // Select input qualification type for GPIO166 +#define GPIO_GPFQSEL1_GPIO167_S 14U +#define GPIO_GPFQSEL1_GPIO167_M 0xC000U // Select input qualification type for GPIO167 +#define GPIO_GPFQSEL1_GPIO168_S 16U +#define GPIO_GPFQSEL1_GPIO168_M 0x30000U // Select input qualification type for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFMUX1_GPIO160_S 0U +#define GPIO_GPFMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFMUX1_GPIO161_S 2U +#define GPIO_GPFMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFMUX1_GPIO162_S 4U +#define GPIO_GPFMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFMUX1_GPIO163_S 6U +#define GPIO_GPFMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFMUX1_GPIO164_S 8U +#define GPIO_GPFMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFMUX1_GPIO165_S 10U +#define GPIO_GPFMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFMUX1_GPIO166_S 12U +#define GPIO_GPFMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFMUX1_GPIO167_S 14U +#define GPIO_GPFMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFMUX1_GPIO168_S 16U +#define GPIO_GPFMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDIR register +// +//************************************************************************************************* +#define GPIO_GPFDIR_GPIO160 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO161 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO162 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO163 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO164 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO165 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO166 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO167 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO168 0x100U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFPUD register +// +//************************************************************************************************* +#define GPIO_GPFPUD_GPIO160 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO161 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO162 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO163 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO164 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO165 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO166 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO167 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO168 0x100U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFINV register +// +//************************************************************************************************* +#define GPIO_GPFINV_GPIO160 0x1U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO161 0x2U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO162 0x4U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO163 0x8U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO164 0x10U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO165 0x20U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO166 0x40U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO167 0x80U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO168 0x100U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFODR register +// +//************************************************************************************************* +#define GPIO_GPFODR_GPIO160 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO161 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO162 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO163 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO164 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO165 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO166 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO167 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO168 0x100U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFGMUX1_GPIO160_S 0U +#define GPIO_GPFGMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFGMUX1_GPIO161_S 2U +#define GPIO_GPFGMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFGMUX1_GPIO162_S 4U +#define GPIO_GPFGMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFGMUX1_GPIO163_S 6U +#define GPIO_GPFGMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFGMUX1_GPIO164_S 8U +#define GPIO_GPFGMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFGMUX1_GPIO165_S 10U +#define GPIO_GPFGMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFGMUX1_GPIO166_S 12U +#define GPIO_GPFGMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFGMUX1_GPIO167_S 14U +#define GPIO_GPFGMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFGMUX1_GPIO168_S 16U +#define GPIO_GPFGMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL1_GPIO160_S 0U +#define GPIO_GPFCSEL1_GPIO160_M 0xFU // GPIO160 Master CPU Select +#define GPIO_GPFCSEL1_GPIO161_S 4U +#define GPIO_GPFCSEL1_GPIO161_M 0xF0U // GPIO161 Master CPU Select +#define GPIO_GPFCSEL1_GPIO162_S 8U +#define GPIO_GPFCSEL1_GPIO162_M 0xF00U // GPIO162 Master CPU Select +#define GPIO_GPFCSEL1_GPIO163_S 12U +#define GPIO_GPFCSEL1_GPIO163_M 0xF000U // GPIO163 Master CPU Select +#define GPIO_GPFCSEL1_GPIO164_S 16U +#define GPIO_GPFCSEL1_GPIO164_M 0xF0000U // GPIO164 Master CPU Select +#define GPIO_GPFCSEL1_GPIO165_S 20U +#define GPIO_GPFCSEL1_GPIO165_M 0xF00000U // GPIO165 Master CPU Select +#define GPIO_GPFCSEL1_GPIO166_S 24U +#define GPIO_GPFCSEL1_GPIO166_M 0xF000000U // GPIO166 Master CPU Select +#define GPIO_GPFCSEL1_GPIO167_S 28U +#define GPIO_GPFCSEL1_GPIO167_M 0xF0000000U // GPIO167 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL2_GPIO168_S 0U +#define GPIO_GPFCSEL2_GPIO168_M 0xFU // GPIO168 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFLOCK register +// +//************************************************************************************************* +#define GPIO_GPFLOCK_GPIO160 0x1U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO161 0x2U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO162 0x4U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO163 0x8U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO164 0x10U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO165 0x20U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO166 0x40U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO167 0x80U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO168 0x100U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCR register +// +//************************************************************************************************* +#define GPIO_GPFCR_GPIO160 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO161 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO162 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO163 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO164 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO165 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO166 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO167 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO168 0x100U // Configuration lock commit bit for this pin + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADAT register +// +//************************************************************************************************* +#define GPIO_GPADAT_GPIO0 0x1U // Data Register for this pin +#define GPIO_GPADAT_GPIO1 0x2U // Data Register for this pin +#define GPIO_GPADAT_GPIO2 0x4U // Data Register for this pin +#define GPIO_GPADAT_GPIO3 0x8U // Data Register for this pin +#define GPIO_GPADAT_GPIO4 0x10U // Data Register for this pin +#define GPIO_GPADAT_GPIO5 0x20U // Data Register for this pin +#define GPIO_GPADAT_GPIO6 0x40U // Data Register for this pin +#define GPIO_GPADAT_GPIO7 0x80U // Data Register for this pin +#define GPIO_GPADAT_GPIO8 0x100U // Data Register for this pin +#define GPIO_GPADAT_GPIO9 0x200U // Data Register for this pin +#define GPIO_GPADAT_GPIO10 0x400U // Data Register for this pin +#define GPIO_GPADAT_GPIO11 0x800U // Data Register for this pin +#define GPIO_GPADAT_GPIO12 0x1000U // Data Register for this pin +#define GPIO_GPADAT_GPIO13 0x2000U // Data Register for this pin +#define GPIO_GPADAT_GPIO14 0x4000U // Data Register for this pin +#define GPIO_GPADAT_GPIO15 0x8000U // Data Register for this pin +#define GPIO_GPADAT_GPIO16 0x10000U // Data Register for this pin +#define GPIO_GPADAT_GPIO17 0x20000U // Data Register for this pin +#define GPIO_GPADAT_GPIO18 0x40000U // Data Register for this pin +#define GPIO_GPADAT_GPIO19 0x80000U // Data Register for this pin +#define GPIO_GPADAT_GPIO20 0x100000U // Data Register for this pin +#define GPIO_GPADAT_GPIO21 0x200000U // Data Register for this pin +#define GPIO_GPADAT_GPIO22 0x400000U // Data Register for this pin +#define GPIO_GPADAT_GPIO23 0x800000U // Data Register for this pin +#define GPIO_GPADAT_GPIO24 0x1000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO25 0x2000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO26 0x4000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO27 0x8000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO28 0x10000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO29 0x20000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO30 0x40000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO31 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPASET register +// +//************************************************************************************************* +#define GPIO_GPASET_GPIO0 0x1U // Output Set bit for this pin +#define GPIO_GPASET_GPIO1 0x2U // Output Set bit for this pin +#define GPIO_GPASET_GPIO2 0x4U // Output Set bit for this pin +#define GPIO_GPASET_GPIO3 0x8U // Output Set bit for this pin +#define GPIO_GPASET_GPIO4 0x10U // Output Set bit for this pin +#define GPIO_GPASET_GPIO5 0x20U // Output Set bit for this pin +#define GPIO_GPASET_GPIO6 0x40U // Output Set bit for this pin +#define GPIO_GPASET_GPIO7 0x80U // Output Set bit for this pin +#define GPIO_GPASET_GPIO8 0x100U // Output Set bit for this pin +#define GPIO_GPASET_GPIO9 0x200U // Output Set bit for this pin +#define GPIO_GPASET_GPIO10 0x400U // Output Set bit for this pin +#define GPIO_GPASET_GPIO11 0x800U // Output Set bit for this pin +#define GPIO_GPASET_GPIO12 0x1000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO13 0x2000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO14 0x4000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO15 0x8000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO16 0x10000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO17 0x20000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO18 0x40000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO19 0x80000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO20 0x100000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO21 0x200000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO22 0x400000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO23 0x800000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO24 0x1000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO25 0x2000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO26 0x4000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO27 0x8000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO28 0x10000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO29 0x20000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO30 0x40000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO31 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACLEAR register +// +//************************************************************************************************* +#define GPIO_GPACLEAR_GPIO0 0x1U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO1 0x2U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO2 0x4U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO3 0x8U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO4 0x10U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO5 0x20U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO6 0x40U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO7 0x80U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO8 0x100U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO9 0x200U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO10 0x400U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO11 0x800U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO12 0x1000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO13 0x2000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO14 0x4000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO15 0x8000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO16 0x10000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO17 0x20000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO18 0x40000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO19 0x80000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO20 0x100000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO21 0x200000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO22 0x400000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO23 0x800000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO24 0x1000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO25 0x2000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO26 0x4000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO27 0x8000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO28 0x10000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO29 0x20000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO30 0x40000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO31 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPATOGGLE register +// +//************************************************************************************************* +#define GPIO_GPATOGGLE_GPIO0 0x1U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO1 0x2U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO2 0x4U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO3 0x8U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO4 0x10U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO5 0x20U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO6 0x40U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO7 0x80U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO8 0x100U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO9 0x200U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO10 0x400U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO11 0x800U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO12 0x1000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO13 0x2000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO14 0x4000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO15 0x8000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO16 0x10000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO17 0x20000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO18 0x40000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO19 0x80000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO20 0x100000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO21 0x200000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO22 0x400000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO23 0x800000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO24 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO25 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO26 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO27 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO28 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO29 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO30 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO31 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDAT register +// +//************************************************************************************************* +#define GPIO_GPBDAT_GPIO32 0x1U // Data Register for this pin +#define GPIO_GPBDAT_GPIO33 0x2U // Data Register for this pin +#define GPIO_GPBDAT_GPIO34 0x4U // Data Register for this pin +#define GPIO_GPBDAT_GPIO35 0x8U // Data Register for this pin +#define GPIO_GPBDAT_GPIO36 0x10U // Data Register for this pin +#define GPIO_GPBDAT_GPIO37 0x20U // Data Register for this pin +#define GPIO_GPBDAT_GPIO38 0x40U // Data Register for this pin +#define GPIO_GPBDAT_GPIO39 0x80U // Data Register for this pin +#define GPIO_GPBDAT_GPIO40 0x100U // Data Register for this pin +#define GPIO_GPBDAT_GPIO41 0x200U // Data Register for this pin +#define GPIO_GPBDAT_GPIO42 0x400U // Data Register for this pin +#define GPIO_GPBDAT_GPIO43 0x800U // Data Register for this pin +#define GPIO_GPBDAT_GPIO44 0x1000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO45 0x2000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO46 0x4000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO47 0x8000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO48 0x10000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO49 0x20000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO50 0x40000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO51 0x80000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO52 0x100000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO53 0x200000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO54 0x400000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO55 0x800000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO56 0x1000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO57 0x2000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO58 0x4000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO59 0x8000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO60 0x10000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO61 0x20000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO62 0x40000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO63 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBSET register +// +//************************************************************************************************* +#define GPIO_GPBSET_GPIO32 0x1U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO33 0x2U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO34 0x4U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO35 0x8U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO36 0x10U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO37 0x20U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO38 0x40U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO39 0x80U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO40 0x100U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO41 0x200U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO42 0x400U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO43 0x800U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO44 0x1000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO45 0x2000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO46 0x4000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO47 0x8000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO48 0x10000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO49 0x20000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO50 0x40000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO51 0x80000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO52 0x100000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO53 0x200000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO54 0x400000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO55 0x800000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO56 0x1000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO57 0x2000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO58 0x4000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO59 0x8000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO60 0x10000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO61 0x20000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO62 0x40000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO63 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCLEAR register +// +//************************************************************************************************* +#define GPIO_GPBCLEAR_GPIO32 0x1U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO33 0x2U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO34 0x4U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO35 0x8U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO36 0x10U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO37 0x20U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO38 0x40U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO39 0x80U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO40 0x100U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO41 0x200U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO42 0x400U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO43 0x800U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO44 0x1000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO45 0x2000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO46 0x4000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO47 0x8000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO48 0x10000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO49 0x20000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO50 0x40000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO51 0x80000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO52 0x100000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO53 0x200000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO54 0x400000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO55 0x800000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO56 0x1000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO57 0x2000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO58 0x4000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO59 0x8000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO60 0x10000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO61 0x20000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO62 0x40000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO63 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPBTOGGLE_GPIO32 0x1U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO33 0x2U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO34 0x4U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO35 0x8U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO36 0x10U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO37 0x20U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO38 0x40U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO39 0x80U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO40 0x100U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO41 0x200U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO42 0x400U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO43 0x800U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO44 0x1000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO45 0x2000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO46 0x4000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO47 0x8000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO48 0x10000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO49 0x20000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO50 0x40000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO51 0x80000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO52 0x100000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO53 0x200000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO54 0x400000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO55 0x800000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO56 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO57 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO58 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO59 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO60 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO61 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO62 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO63 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDAT register +// +//************************************************************************************************* +#define GPIO_GPCDAT_GPIO64 0x1U // Data Register for this pin +#define GPIO_GPCDAT_GPIO65 0x2U // Data Register for this pin +#define GPIO_GPCDAT_GPIO66 0x4U // Data Register for this pin +#define GPIO_GPCDAT_GPIO67 0x8U // Data Register for this pin +#define GPIO_GPCDAT_GPIO68 0x10U // Data Register for this pin +#define GPIO_GPCDAT_GPIO69 0x20U // Data Register for this pin +#define GPIO_GPCDAT_GPIO70 0x40U // Data Register for this pin +#define GPIO_GPCDAT_GPIO71 0x80U // Data Register for this pin +#define GPIO_GPCDAT_GPIO72 0x100U // Data Register for this pin +#define GPIO_GPCDAT_GPIO73 0x200U // Data Register for this pin +#define GPIO_GPCDAT_GPIO74 0x400U // Data Register for this pin +#define GPIO_GPCDAT_GPIO75 0x800U // Data Register for this pin +#define GPIO_GPCDAT_GPIO76 0x1000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO77 0x2000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO78 0x4000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO79 0x8000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO80 0x10000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO81 0x20000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO82 0x40000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO83 0x80000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO84 0x100000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO85 0x200000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO86 0x400000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO87 0x800000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO88 0x1000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO89 0x2000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO90 0x4000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO91 0x8000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO92 0x10000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO93 0x20000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO94 0x40000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO95 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCSET register +// +//************************************************************************************************* +#define GPIO_GPCSET_GPIO64 0x1U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO65 0x2U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO66 0x4U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO67 0x8U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO68 0x10U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO69 0x20U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO70 0x40U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO71 0x80U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO72 0x100U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO73 0x200U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO74 0x400U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO75 0x800U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO76 0x1000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO77 0x2000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO78 0x4000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO79 0x8000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO80 0x10000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO81 0x20000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO82 0x40000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO83 0x80000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO84 0x100000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO85 0x200000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO86 0x400000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO87 0x800000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO88 0x1000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO89 0x2000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO90 0x4000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO91 0x8000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO92 0x10000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO93 0x20000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO94 0x40000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO95 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCLEAR register +// +//************************************************************************************************* +#define GPIO_GPCCLEAR_GPIO64 0x1U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO65 0x2U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO66 0x4U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO67 0x8U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO68 0x10U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO69 0x20U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO70 0x40U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO71 0x80U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO72 0x100U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO73 0x200U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO74 0x400U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO75 0x800U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO76 0x1000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO77 0x2000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO78 0x4000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO79 0x8000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO80 0x10000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO81 0x20000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO82 0x40000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO83 0x80000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO84 0x100000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO85 0x200000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO86 0x400000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO87 0x800000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO88 0x1000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO89 0x2000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO90 0x4000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO91 0x8000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO92 0x10000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO93 0x20000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO94 0x40000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO95 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPCTOGGLE_GPIO64 0x1U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO65 0x2U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO66 0x4U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO67 0x8U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO68 0x10U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO69 0x20U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO70 0x40U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO71 0x80U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO72 0x100U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO73 0x200U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO74 0x400U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO75 0x800U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO76 0x1000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO77 0x2000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO78 0x4000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO79 0x8000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO80 0x10000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO81 0x20000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO82 0x40000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO83 0x80000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO84 0x100000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO85 0x200000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO86 0x400000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO87 0x800000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO88 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO89 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO90 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO91 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO92 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO93 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO94 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO95 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDAT register +// +//************************************************************************************************* +#define GPIO_GPDDAT_GPIO96 0x1U // Data Register for this pin +#define GPIO_GPDDAT_GPIO97 0x2U // Data Register for this pin +#define GPIO_GPDDAT_GPIO98 0x4U // Data Register for this pin +#define GPIO_GPDDAT_GPIO99 0x8U // Data Register for this pin +#define GPIO_GPDDAT_GPIO100 0x10U // Data Register for this pin +#define GPIO_GPDDAT_GPIO101 0x20U // Data Register for this pin +#define GPIO_GPDDAT_GPIO102 0x40U // Data Register for this pin +#define GPIO_GPDDAT_GPIO103 0x80U // Data Register for this pin +#define GPIO_GPDDAT_GPIO104 0x100U // Data Register for this pin +#define GPIO_GPDDAT_GPIO105 0x200U // Data Register for this pin +#define GPIO_GPDDAT_GPIO106 0x400U // Data Register for this pin +#define GPIO_GPDDAT_GPIO107 0x800U // Data Register for this pin +#define GPIO_GPDDAT_GPIO108 0x1000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO109 0x2000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO110 0x4000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO111 0x8000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO112 0x10000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO113 0x20000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO114 0x40000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO115 0x80000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO116 0x100000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO117 0x200000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO118 0x400000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO119 0x800000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO120 0x1000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO121 0x2000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO122 0x4000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO123 0x8000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO124 0x10000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO125 0x20000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO126 0x40000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO127 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDSET register +// +//************************************************************************************************* +#define GPIO_GPDSET_GPIO96 0x1U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO97 0x2U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO98 0x4U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO99 0x8U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO100 0x10U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO101 0x20U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO102 0x40U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO103 0x80U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO104 0x100U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO105 0x200U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO106 0x400U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO107 0x800U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO108 0x1000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO109 0x2000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO110 0x4000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO111 0x8000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO112 0x10000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO113 0x20000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO114 0x40000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO115 0x80000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO116 0x100000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO117 0x200000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO118 0x400000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO119 0x800000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO120 0x1000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO121 0x2000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO122 0x4000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO123 0x8000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO124 0x10000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO125 0x20000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO126 0x40000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO127 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCLEAR register +// +//************************************************************************************************* +#define GPIO_GPDCLEAR_GPIO96 0x1U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO97 0x2U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO98 0x4U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO99 0x8U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO100 0x10U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO101 0x20U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO102 0x40U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO103 0x80U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO104 0x100U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO105 0x200U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO106 0x400U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO107 0x800U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO108 0x1000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO109 0x2000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO110 0x4000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO111 0x8000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO112 0x10000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO113 0x20000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO114 0x40000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO115 0x80000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO116 0x100000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO117 0x200000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO118 0x400000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO119 0x800000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO120 0x1000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO121 0x2000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO122 0x4000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO123 0x8000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO124 0x10000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO125 0x20000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO126 0x40000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO127 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPDTOGGLE_GPIO96 0x1U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO97 0x2U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO98 0x4U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO99 0x8U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO100 0x10U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO101 0x20U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO102 0x40U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO103 0x80U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO104 0x100U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO105 0x200U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO106 0x400U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO107 0x800U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO108 0x1000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO109 0x2000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO110 0x4000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO111 0x8000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO112 0x10000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO113 0x20000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO114 0x40000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO115 0x80000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO116 0x100000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO117 0x200000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO118 0x400000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO119 0x800000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO120 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO121 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO122 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO123 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO124 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO125 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO126 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO127 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDAT register +// +//************************************************************************************************* +#define GPIO_GPEDAT_GPIO128 0x1U // Data Register for this pin +#define GPIO_GPEDAT_GPIO129 0x2U // Data Register for this pin +#define GPIO_GPEDAT_GPIO130 0x4U // Data Register for this pin +#define GPIO_GPEDAT_GPIO131 0x8U // Data Register for this pin +#define GPIO_GPEDAT_GPIO132 0x10U // Data Register for this pin +#define GPIO_GPEDAT_GPIO133 0x20U // Data Register for this pin +#define GPIO_GPEDAT_GPIO134 0x40U // Data Register for this pin +#define GPIO_GPEDAT_GPIO135 0x80U // Data Register for this pin +#define GPIO_GPEDAT_GPIO136 0x100U // Data Register for this pin +#define GPIO_GPEDAT_GPIO137 0x200U // Data Register for this pin +#define GPIO_GPEDAT_GPIO138 0x400U // Data Register for this pin +#define GPIO_GPEDAT_GPIO139 0x800U // Data Register for this pin +#define GPIO_GPEDAT_GPIO140 0x1000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO141 0x2000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO142 0x4000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO143 0x8000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO144 0x10000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO145 0x20000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO146 0x40000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO147 0x80000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO148 0x100000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO149 0x200000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO150 0x400000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO151 0x800000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO152 0x1000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO153 0x2000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO154 0x4000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO155 0x8000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO156 0x10000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO157 0x20000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO158 0x40000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO159 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPESET register +// +//************************************************************************************************* +#define GPIO_GPESET_GPIO128 0x1U // Output Set bit for this pin +#define GPIO_GPESET_GPIO129 0x2U // Output Set bit for this pin +#define GPIO_GPESET_GPIO130 0x4U // Output Set bit for this pin +#define GPIO_GPESET_GPIO131 0x8U // Output Set bit for this pin +#define GPIO_GPESET_GPIO132 0x10U // Output Set bit for this pin +#define GPIO_GPESET_GPIO133 0x20U // Output Set bit for this pin +#define GPIO_GPESET_GPIO134 0x40U // Output Set bit for this pin +#define GPIO_GPESET_GPIO135 0x80U // Output Set bit for this pin +#define GPIO_GPESET_GPIO136 0x100U // Output Set bit for this pin +#define GPIO_GPESET_GPIO137 0x200U // Output Set bit for this pin +#define GPIO_GPESET_GPIO138 0x400U // Output Set bit for this pin +#define GPIO_GPESET_GPIO139 0x800U // Output Set bit for this pin +#define GPIO_GPESET_GPIO140 0x1000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO141 0x2000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO142 0x4000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO143 0x8000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO144 0x10000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO145 0x20000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO146 0x40000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO147 0x80000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO148 0x100000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO149 0x200000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO150 0x400000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO151 0x800000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO152 0x1000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO153 0x2000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO154 0x4000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO155 0x8000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO156 0x10000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO157 0x20000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO158 0x40000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO159 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECLEAR register +// +//************************************************************************************************* +#define GPIO_GPECLEAR_GPIO128 0x1U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO129 0x2U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO130 0x4U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO131 0x8U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO132 0x10U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO133 0x20U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO134 0x40U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO135 0x80U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO136 0x100U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO137 0x200U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO138 0x400U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO139 0x800U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO140 0x1000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO141 0x2000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO142 0x4000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO143 0x8000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO144 0x10000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO145 0x20000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO146 0x40000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO147 0x80000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO148 0x100000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO149 0x200000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO150 0x400000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO151 0x800000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO152 0x1000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO153 0x2000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO154 0x4000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO155 0x8000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO156 0x10000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO157 0x20000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO158 0x40000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO159 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPETOGGLE register +// +//************************************************************************************************* +#define GPIO_GPETOGGLE_GPIO128 0x1U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO129 0x2U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO130 0x4U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO131 0x8U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO132 0x10U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO133 0x20U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO134 0x40U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO135 0x80U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO136 0x100U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO137 0x200U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO138 0x400U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO139 0x800U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO140 0x1000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO141 0x2000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO142 0x4000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO143 0x8000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO144 0x10000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO145 0x20000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO146 0x40000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO147 0x80000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO148 0x100000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO149 0x200000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO150 0x400000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO151 0x800000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO152 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO153 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO154 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO155 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO156 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO157 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO158 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO159 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDAT register +// +//************************************************************************************************* +#define GPIO_GPFDAT_GPIO160 0x1U // Data Register for this pin +#define GPIO_GPFDAT_GPIO161 0x2U // Data Register for this pin +#define GPIO_GPFDAT_GPIO162 0x4U // Data Register for this pin +#define GPIO_GPFDAT_GPIO163 0x8U // Data Register for this pin +#define GPIO_GPFDAT_GPIO164 0x10U // Data Register for this pin +#define GPIO_GPFDAT_GPIO165 0x20U // Data Register for this pin +#define GPIO_GPFDAT_GPIO166 0x40U // Data Register for this pin +#define GPIO_GPFDAT_GPIO167 0x80U // Data Register for this pin +#define GPIO_GPFDAT_GPIO168 0x100U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFSET register +// +//************************************************************************************************* +#define GPIO_GPFSET_GPIO160 0x1U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO161 0x2U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO162 0x4U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO163 0x8U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO164 0x10U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO165 0x20U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO166 0x40U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO167 0x80U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO168 0x100U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCLEAR register +// +//************************************************************************************************* +#define GPIO_GPFCLEAR_GPIO160 0x1U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO161 0x2U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO162 0x4U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO163 0x8U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO164 0x10U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO165 0x20U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO166 0x40U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO167 0x80U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO168 0x100U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPFTOGGLE_GPIO160 0x1U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO161 0x2U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO162 0x4U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO163 0x8U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO164 0x10U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO165 0x20U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO166 0x40U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO167 0x80U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO168 0x100U // Output Toggle bit for this pin + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_hic.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_hic.h new file mode 100644 index 0000000..07d544f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_hic.h @@ -0,0 +1,344 @@ +//########################################################################### +// +// FILE: hw_hic.h +// +// TITLE: Definitions for the HIC registers. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HIC_H +#define HW_HIC_H + +//************************************************************************************************* +// +// The following are defines for the HIC register offsets +// +//************************************************************************************************* +#define HIC_O_REV 0x0U // Module Revision Register +#define HIC_O_GCR 0x2U // Global Control Register +#define HIC_O_LOCK 0x4U // Lock Register +#define HIC_O_MODECR 0x6U // Mode Control Register +#define HIC_O_PINPOLCR 0x8U // Pin Polarity Control Register +#define HIC_O_BASESEL 0xAU // Base Select Register +#define HIC_O_HOSTCR 0xCU // Host Control Register +#define HIC_O_ERRADDR 0xEU // Host Error Address register +#define HIC_O_H2DTOKEN 0x10U // Host to Device Token Register +#define HIC_O_D2HTOKEN 0x12U // Devie to Host Token Register +#define HIC_O_DBADDR0 0x14U // Device Base Address Register 0 +#define HIC_O_DBADDR1 0x16U // Device Base Address Register 1 +#define HIC_O_DBADDR2 0x18U // Device Base Address Register 2 +#define HIC_O_DBADDR3 0x1AU // Device Base Address Register 3 +#define HIC_O_DBADDR4 0x1CU // Device Base Address Register 4 +#define HIC_O_DBADDR5 0x1EU // Device Base Address Register 5 +#define HIC_O_DBADDR6 0x20U // Device Base Address Register 6 +#define HIC_O_DBADDR7 0x22U // Device Base Address Register 7 +#define HIC_O_H2DINTEN 0x28U // H2D Interrupt Enable +#define HIC_O_H2DINTFLG 0x2AU // H2D Interrupt status Flag +#define HIC_O_H2DINTCLR 0x2CU // H2D Interrupt status Clear +#define HIC_O_H2DINTFRC 0x2EU // H2D Interrupt Set Force +#define HIC_O_D2HINTEN 0x30U // D2H Interrupt Enable +#define HIC_O_D2HINTFLG 0x32U // D2H Interrupt status Flag +#define HIC_O_D2HINTCLR 0x34U // D2H Interrupt status Clear +#define HIC_O_D2HINTFRC 0x36U // D2H Interrupt Set Force +#define HIC_O_ACCVIOADDR 0x38U // Access Violation Address +#define HIC_O_H2D_BUF0 0x40U // Host to Device Buffer 0 +#define HIC_O_H2D_BUF1 0x42U // Host to Device Buffer 1 +#define HIC_O_H2D_BUF2 0x44U // Host to Device Buffer 2 +#define HIC_O_H2D_BUF3 0x46U // Host to Device Buffer 3 +#define HIC_O_H2D_BUF4 0x48U // Host to Device Buffer 4 +#define HIC_O_H2D_BUF5 0x4AU // Host to Device Buffer 5 +#define HIC_O_H2D_BUF6 0x4CU // Host to Device Buffer 6 +#define HIC_O_H2D_BUF7 0x4EU // Host to Device Buffer 7 +#define HIC_O_H2D_BUF8 0x50U // Host to Device Buffer 8 +#define HIC_O_H2D_BUF9 0x52U // Host to Device Buffer 9 +#define HIC_O_H2D_BUF10 0x54U // Host to Device Buffer 10 +#define HIC_O_H2D_BUF11 0x56U // Host to Device Buffer 11 +#define HIC_O_H2D_BUF12 0x58U // Host to Device Buffer 12 +#define HIC_O_H2D_BUF13 0x5AU // Host to Device Buffer 13 +#define HIC_O_H2D_BUF14 0x5CU // Host to Device Buffer 14 +#define HIC_O_H2D_BUF15 0x5EU // Host to Device Buffer 15 +#define HIC_O_D2H_BUF0 0x60U // Device to Host Buffer 0 +#define HIC_O_D2H_BUF1 0x62U // Device to Host Buffer 1 +#define HIC_O_D2H_BUF2 0x64U // Device to Host Buffer 2 +#define HIC_O_D2H_BUF3 0x66U // Device to Host Buffer 3 +#define HIC_O_D2H_BUF4 0x68U // Device to Host Buffer 4 +#define HIC_O_D2H_BUF5 0x6AU // Device to Host Buffer 5 +#define HIC_O_D2H_BUF6 0x6CU // Device to Host Buffer 6 +#define HIC_O_D2H_BUF7 0x6EU // Device to Host Buffer 7 +#define HIC_O_D2H_BUF8 0x70U // Device to Host Buffer 8 +#define HIC_O_D2H_BUF9 0x72U // Device to Host Buffer 9 +#define HIC_O_D2H_BUF10 0x74U // Device to Host Buffer 10 +#define HIC_O_D2H_BUF11 0x76U // Device to Host Buffer 11 +#define HIC_O_D2H_BUF12 0x78U // Device to Host Buffer 12 +#define HIC_O_D2H_BUF13 0x7AU // Device to Host Buffer 13 +#define HIC_O_D2H_BUF14 0x7CU // Device to Host Buffer 14 +#define HIC_O_D2H_BUF15 0x7EU // Device to Host Buffer 15 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICREV register +// +//************************************************************************************************* +#define HIC_REV_MINOR_S 0U +#define HIC_REV_MINOR_M 0x3FU // Minor Revision Number +#define HIC_REV_CUSTOM_S 6U +#define HIC_REV_CUSTOM_M 0xC0U // Custom Module Number +#define HIC_REV_MAJOR_S 8U +#define HIC_REV_MAJOR_M 0x700U // Major Revision Number +#define HIC_REV_RTL_S 11U +#define HIC_REV_RTL_M 0xF800U // Design Release Number +#define HIC_REV_FUNC_S 16U +#define HIC_REV_FUNC_M 0xFFF0000U // Functional Release Number +#define HIC_REV_SCHEME_S 30U +#define HIC_REV_SCHEME_M 0xC0000000U // Defines Scheme for Module +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICGCR register +// +//************************************************************************************************* +#define HIC_GCR_HICEN_S 0U +#define HIC_GCR_HICEN_M 0xFU // Host Interface Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICLOCK register +// +//************************************************************************************************* +#define HIC_LOCK_LOCK 0x1U // LOCK enable +#define HIC_LOCK_WRITE_ENABLE_KEY_S 16U +#define HIC_LOCK_WRITE_ENABLE_KEY_M 0xFFFF0000U // Key for enabling write +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICMODECR register +// +//************************************************************************************************* +#define HIC_MODECR_DW_MODE_S 0U +#define HIC_MODECR_DW_MODE_M 0x3U // Data Width Mode +#define HIC_MODECR_RW_MODE 0x10U // Read-Write Mode +#define HIC_MODECR_BEN_PRESENT 0x20U // Byte Enable Pins are present +#define HIC_MODECR_RDY_PRESENT 0x40U // Ready pin present +#define HIC_MODECR_H2DBUF_DEVWREN 0x100U // Write Enable for Device to H2D Buffer +#define HIC_MODECR_D2HBUF_HOSTWREN 0x200U // Write Enable for Host to D2H Buffer +#define HIC_MODECR_EN_DEVACC 0x400U // Enable Host access to Device region +#define HIC_MODECR_EN_HOSTWREALLOW 0x800U // Enable Host Write to EALLOWCTL register +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICPINPOLCR register +// +//************************************************************************************************* +#define HIC_PINPOLCR_CS_POL 0x1U // Chip Select Polarity +#define HIC_PINPOLCR_BEN_POL 0x2U // Byte Enable Polarity +#define HIC_PINPOLCR_OE_POL 0x4U // Output Enable Polarity +#define HIC_PINPOLCR_WE_POL 0x8U // Write Enable Polarity +#define HIC_PINPOLCR_RDY_POL 0x10U // Ready Polarity +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICBASESEL register +// +//************************************************************************************************* +#define HIC_BASESEL_BASE_SELECT_S 0U +#define HIC_BASESEL_BASE_SELECT_M 0x7U // Base Select +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICHOSTCR register +// +//************************************************************************************************* +#define HIC_HOSTCR_EALLOW_EN 0x1U // EALLOW Enable +#define HIC_HOSTCR_ACCSIZE 0x2U // Access Size +#define HIC_HOSTCR_PAGESEL 0x4U // Page Select +#define HIC_HOSTCR_HKEY_S 8U +#define HIC_HOSTCR_HKEY_M 0xFF00U // Host Key +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICERRADDR register +// +//************************************************************************************************* +#define HIC_ERRADDR_H2D_ERR_ADDR_S 0U +#define HIC_ERRADDR_H2D_ERR_ADDR_M 0xFFU // Address of the Host bus captured upon an + // error for Device +#define HIC_ERRADDR_H2D_BASE_SEL_S 12U +#define HIC_ERRADDR_H2D_BASE_SEL_M 0x7000U // Base Select corresponding to H2D error event +#define HIC_ERRADDR_D2H_ERR_ADDR_S 16U +#define HIC_ERRADDR_D2H_ERR_ADDR_M 0xFF0000U // Address of the Host bus captured upon an + // error for Host +#define HIC_ERRADDR_D2H_BASE_SEL_S 28U +#define HIC_ERRADDR_D2H_BASE_SEL_M 0x70000000U // Base Select corresponding to D2H error event +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR0 register +// +//************************************************************************************************* +#define HIC_DBADDR0_BASE_ADDR_S 7U +#define HIC_DBADDR0_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR1 register +// +//************************************************************************************************* +#define HIC_DBADDR1_BASE_ADDR_S 7U +#define HIC_DBADDR1_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR2 register +// +//************************************************************************************************* +#define HIC_DBADDR2_BASE_ADDR_S 7U +#define HIC_DBADDR2_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR3 register +// +//************************************************************************************************* +#define HIC_DBADDR3_BASE_ADDR_S 7U +#define HIC_DBADDR3_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR4 register +// +//************************************************************************************************* +#define HIC_DBADDR4_BASE_ADDR_S 7U +#define HIC_DBADDR4_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR5 register +// +//************************************************************************************************* +#define HIC_DBADDR5_BASE_ADDR_S 7U +#define HIC_DBADDR5_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR6 register +// +//************************************************************************************************* +#define HIC_DBADDR6_BASE_ADDR_S 7U +#define HIC_DBADDR6_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR7 register +// +//************************************************************************************************* +#define HIC_DBADDR7_BASE_ADDR_S 7U +#define HIC_DBADDR7_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTEN register +// +//************************************************************************************************* +#define HIC_H2DINTEN_H2D_INTEN 0x1U // Host To Device Interrupt Enable +#define HIC_H2DINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_H2DINTEN_ILLWR_INTEN 0x4U // Illegal Write event interrupt enable +#define HIC_H2DINTEN_ILLRD_INTEN 0x8U // Illegal Read event interrupt enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFLG register +// +//************************************************************************************************* +#define HIC_H2DINTFLG_H2D_FLG 0x1U // Host To Device Interrupt Flag +#define HIC_H2DINTFLG_BUSERR_FLG 0x2U // BusError Interrupt Flag +#define HIC_H2DINTFLG_ILLWR_FLG 0x4U // Illegal write event interrupt flag +#define HIC_H2DINTFLG_ILLRD_FLG 0x8U // Illegal read event interrupt flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTCLR register +// +//************************************************************************************************* +#define HIC_H2DINTCLR_H2D_CLR 0x1U // Host To Device Interrupt Clear +#define HIC_H2DINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_H2DINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_H2DINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFRC register +// +//************************************************************************************************* +#define HIC_H2DINTFRC_H2D_INTFRC 0x1U // Host To Device Force Set +#define HIC_H2DINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_H2DINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_H2DINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTEN register +// +//************************************************************************************************* +#define HIC_D2HINTEN_D2H_INTEN 0x1U // Device to Host Data Ready Interrupt Enable +#define HIC_D2HINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_D2HINTEN_ILLWR_INTEN 0x4U // Illegal Write event Interrupt Enable +#define HIC_D2HINTEN_ILLRD_INTEN 0x8U // Illegal Read event Interrupt Enable +#define HIC_D2HINTEN_ACCVIO_INTEN 0x10U // Access Violation Interrupt Enable +#define HIC_D2HINTEN_EVTRIG_INTEN_S 16U +#define HIC_D2HINTEN_EVTRIG_INTEN_M 0xFFFF0000U // Event Trigger Interrupt Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFLG register +// +//************************************************************************************************* +#define HIC_D2HINTFLG_D2H_FLG 0x1U // Device to Host Data Ready Flag +#define HIC_D2HINTFLG_BUSERR_FLG 0x2U // BusError Flag +#define HIC_D2HINTFLG_ILLWR_FLG 0x4U // Illegal Write event Flag +#define HIC_D2HINTFLG_ILLRD_FLG 0x8U // Illegal Read event Flag +#define HIC_D2HINTFLG_ACCVIO_FLG 0x10U // Access Violation Flag +#define HIC_D2HINTFLG_EVTRIG_FLG_S 16U +#define HIC_D2HINTFLG_EVTRIG_FLG_M 0xFFFF0000U // Event Trigger Flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTCLR register +// +//************************************************************************************************* +#define HIC_D2HINTCLR_D2H_CLR 0x1U // Device to Host Interrupt Clear +#define HIC_D2HINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_D2HINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_D2HINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +#define HIC_D2HINTCLR_ACCVIO_CLR 0x10U // Access Violation Interrupt Clear +#define HIC_D2HINTCLR_EVTRIG_CLR_S 16U +#define HIC_D2HINTCLR_EVTRIG_CLR_M 0xFFFF0000U // Event Trigger Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFRC register +// +//************************************************************************************************* +#define HIC_D2HINTFRC_D2H_INTFRC 0x1U // Device to Host Force Set +#define HIC_D2HINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_D2HINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_D2HINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +#define HIC_D2HINTFRC_ACCVIO_INTFRC 0x10U // Access Violation Interrupt Force Set +#define HIC_D2HINTFRC_EVTRIG_INTFRC_S 16U +#define HIC_D2HINTFRC_EVTRIG_INTFRC_M 0xFFFF0000U // Event Trigger Interrupt Force Set + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_hrpwm.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_hrpwm.h new file mode 100644 index 0000000..a6c899f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_hrpwm.h @@ -0,0 +1,1058 @@ +//########################################################################### +// +// FILE: hw_hrpwm.h +// +// TITLE: Definitions for the HRPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HRPWM_H +#define HW_HRPWM_H + +//************************************************************************************************* +// +// The following are defines for the HRPWM register offsets +// +//************************************************************************************************* +#define HRPWM_O_TBCTL 0x0U // Time Base Control Register +#define HRPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define HRPWM_O_TBCTR 0x4U // Time Base Counter Register +#define HRPWM_O_TBSTS 0x5U // Time Base Status Register +#define HRPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define HRPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define HRPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define HRPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define HRPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define HRPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define HRPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define HRPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define HRPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define HRPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define HRPWM_O_HRPWR 0x21U // HRPWM Power Register +#define HRPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define HRPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define HRPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define HRPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define HRPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define HRPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define HRPWM_O_EPWMXLINK 0x38U // EPWMx Link Register +#define HRPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define HRPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define HRPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define HRPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define HRPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define HRPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define HRPWM_O_TBPHS 0x60U // Time Base Phase High +#define HRPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define HRPWM_O_TBPRD 0x63U // Time Base Period Register +#define HRPWM_O_CMPA 0x6AU // Counter Compare A Register +#define HRPWM_O_CMPB 0x6CU // Compare B Register +#define HRPWM_O_CMPC 0x6FU // Counter Compare C Register +#define HRPWM_O_CMPD 0x71U // Counter Compare D Register +#define HRPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define HRPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define HRPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define HRPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define HRPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define HRPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define HRPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define HRPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define HRPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define HRPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define HRPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define HRPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define HRPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define HRPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define HRPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define HRPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define HRPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define HRPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define HRPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define HRPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define HRPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define HRPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define HRPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define HRPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define HRPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define HRPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define HRPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define HRPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define HRPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define HRPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define HRPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define HRPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define HRPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define HRPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define HRPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define HRPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define HRPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define HRPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define HRPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define HRPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define HRPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define HRPWM_TBCTL_CTRMODE_S 0U +#define HRPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define HRPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define HRPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define HRPWM_TBCTL_SYNCOSEL_S 4U +#define HRPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define HRPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define HRPWM_TBCTL_HSPCLKDIV_S 7U +#define HRPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define HRPWM_TBCTL_CLKDIV_S 10U +#define HRPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define HRPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define HRPWM_TBCTL_FREE_SOFT_S 14U +#define HRPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define HRPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define HRPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define HRPWM_TBCTL2_SYNCOSELX_S 12U +#define HRPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define HRPWM_TBCTL2_PRDLDSYNC_S 14U +#define HRPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define HRPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define HRPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define HRPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define HRPWM_CMPCTL_LOADAMODE_S 0U +#define HRPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define HRPWM_CMPCTL_LOADBMODE_S 2U +#define HRPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define HRPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define HRPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define HRPWM_CMPCTL_LOADASYNC_S 10U +#define HRPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define HRPWM_CMPCTL_LOADBSYNC_S 12U +#define HRPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define HRPWM_CMPCTL2_LOADCMODE_S 0U +#define HRPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define HRPWM_CMPCTL2_LOADDMODE_S 2U +#define HRPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define HRPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define HRPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define HRPWM_CMPCTL2_LOADCSYNC_S 10U +#define HRPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define HRPWM_CMPCTL2_LOADDSYNC_S 12U +#define HRPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define HRPWM_DBCTL_OUT_MODE_S 0U +#define HRPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define HRPWM_DBCTL_POLSEL_S 2U +#define HRPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define HRPWM_DBCTL_IN_MODE_S 4U +#define HRPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define HRPWM_DBCTL_LOADREDMODE_S 6U +#define HRPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define HRPWM_DBCTL_LOADFEDMODE_S 8U +#define HRPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define HRPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define HRPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define HRPWM_DBCTL_OUTSWAP_S 12U +#define HRPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define HRPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define HRPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define HRPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define HRPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define HRPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define HRPWM_AQCTL_LDAQAMODE_S 0U +#define HRPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define HRPWM_AQCTL_LDAQBMODE_S 2U +#define HRPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define HRPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define HRPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define HRPWM_AQCTL_LDAQASYNC_S 8U +#define HRPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define HRPWM_AQCTL_LDAQBSYNC_S 10U +#define HRPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define HRPWM_AQTSRCSEL_T1SEL_S 0U +#define HRPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define HRPWM_AQTSRCSEL_T2SEL_S 4U +#define HRPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define HRPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define HRPWM_PCCTL_OSHTWTH_S 1U +#define HRPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define HRPWM_PCCTL_CHPFREQ_S 5U +#define HRPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define HRPWM_PCCTL_CHPDUTY_S 8U +#define HRPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define HRPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define HRPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define HRPWM_VCAPCTL_TRIGSEL_S 2U +#define HRPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define HRPWM_VCAPCTL_VDELAYDIV_S 7U +#define HRPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define HRPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define HRPWM_VCNTCFG_STARTEDGE_S 0U +#define HRPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define HRPWM_VCNTCFG_STOPEDGE_S 8U +#define HRPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define HRPWM_HRCNFG_EDGMODE_S 0U +#define HRPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOAD_S 3U +#define HRPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define HRPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define HRPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define HRPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define HRPWM_HRCNFG_EDGMODEB_S 8U +#define HRPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOADB_S 11U +#define HRPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define HRPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define HRPWM_HRMSTEP_HRMSTEP_S 0U +#define HRPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define HRPWM_HRCNFG2_EDGMODEDB_S 0U +#define HRPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define HRPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define HRPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define HRPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define HRPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define HRPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define HRPWM_HRPCTL_PWMSYNCSELX_S 4U +#define HRPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define HRPWM_TRREM_TRREM_S 0U +#define HRPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define HRPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define HRPWM_GLDCTL_GLDMODE_S 1U +#define HRPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define HRPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define HRPWM_GLDCTL_GLDPRD_S 7U +#define HRPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define HRPWM_GLDCTL_GLDCNT_S 10U +#define HRPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define HRPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define HRPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define HRPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define HRPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define HRPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define HRPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define HRPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define HRPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define HRPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define HRPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define HRPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define HRPWM_EPWMXLINK_TBPRDLINK_S 0U +#define HRPWM_EPWMXLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define HRPWM_EPWMXLINK_CMPALINK_S 4U +#define HRPWM_EPWMXLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define HRPWM_EPWMXLINK_CMPBLINK_S 8U +#define HRPWM_EPWMXLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define HRPWM_EPWMXLINK_CMPCLINK_S 12U +#define HRPWM_EPWMXLINK_CMPCLINK_M 0xF000U // CMPC Link +#define HRPWM_EPWMXLINK_CMPDLINK_S 16U +#define HRPWM_EPWMXLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define HRPWM_EPWMXLINK_GLDCTL2LINK_S 28U +#define HRPWM_EPWMXLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define HRPWM_AQCTLA_ZRO_S 0U +#define HRPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLA_PRD_S 2U +#define HRPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLA_CAU_S 4U +#define HRPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLA_CAD_S 6U +#define HRPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLA_CBU_S 8U +#define HRPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLA_CBD_S 10U +#define HRPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLA2_T1U_S 0U +#define HRPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLA2_T1D_S 2U +#define HRPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLA2_T2U_S 4U +#define HRPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLA2_T2D_S 6U +#define HRPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define HRPWM_AQCTLB_ZRO_S 0U +#define HRPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLB_PRD_S 2U +#define HRPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLB_CAU_S 4U +#define HRPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLB_CAD_S 6U +#define HRPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLB_CBU_S 8U +#define HRPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLB_CBD_S 10U +#define HRPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLB2_T1U_S 0U +#define HRPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLB2_T1D_S 2U +#define HRPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLB2_T2U_S 4U +#define HRPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLB2_T2D_S 6U +#define HRPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define HRPWM_AQSFRC_ACTSFA_S 0U +#define HRPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define HRPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define HRPWM_AQSFRC_ACTSFB_S 3U +#define HRPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define HRPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define HRPWM_AQSFRC_RLDCSF_S 6U +#define HRPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define HRPWM_AQCSFRC_CSFA_S 0U +#define HRPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define HRPWM_AQCSFRC_CSFB_S 2U +#define HRPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define HRPWM_DBREDHR_DBREDHR_S 9U +#define HRPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define HRPWM_DBRED_DBRED_S 0U +#define HRPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define HRPWM_DBFEDHR_DBFEDHR_S 9U +#define HRPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define HRPWM_DBFED_DBFED_S 0U +#define HRPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define HRPWM_TBPHS_TBPHSHR_S 0U +#define HRPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define HRPWM_TBPHS_TBPHS_S 16U +#define HRPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define HRPWM_CMPA_CMPAHR_S 0U +#define HRPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define HRPWM_CMPA_CMPA_S 16U +#define HRPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define HRPWM_CMPB_CMPBHR_S 0U +#define HRPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define HRPWM_CMPB_CMPB_S 16U +#define HRPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define HRPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define HRPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define HRPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define HRPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define HRPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define HRPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define HRPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define HRPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define HRPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define HRPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define HRPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define HRPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define HRPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define HRPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define HRPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define HRPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define HRPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define HRPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define HRPWM_TZDCSEL_DCAEVT1_S 0U +#define HRPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define HRPWM_TZDCSEL_DCAEVT2_S 3U +#define HRPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define HRPWM_TZDCSEL_DCBEVT1_S 6U +#define HRPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define HRPWM_TZDCSEL_DCBEVT2_S 9U +#define HRPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define HRPWM_TZCTL_TZA_S 0U +#define HRPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define HRPWM_TZCTL_TZB_S 2U +#define HRPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define HRPWM_TZCTL_DCAEVT1_S 4U +#define HRPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define HRPWM_TZCTL_DCAEVT2_S 6U +#define HRPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define HRPWM_TZCTL_DCBEVT1_S 8U +#define HRPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define HRPWM_TZCTL_DCBEVT2_S 10U +#define HRPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define HRPWM_TZCTL2_TZAU_S 0U +#define HRPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define HRPWM_TZCTL2_TZAD_S 3U +#define HRPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define HRPWM_TZCTL2_TZBU_S 6U +#define HRPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define HRPWM_TZCTL2_TZBD_S 9U +#define HRPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define HRPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCA_DCAEVT1U_S 0U +#define HRPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT1D_S 3U +#define HRPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCA_DCAEVT2U_S 6U +#define HRPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT2D_S 9U +#define HRPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCB_DCBEVT1U_S 0U +#define HRPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT1D_S 3U +#define HRPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCB_DCBEVT2U_S 6U +#define HRPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT2D_S 9U +#define HRPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define HRPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define HRPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define HRPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define HRPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define HRPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define HRPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define HRPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define HRPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define HRPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define HRPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define HRPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define HRPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define HRPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define HRPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define HRPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define HRPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define HRPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define HRPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define HRPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define HRPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event + // 2 +#define HRPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event + // 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define HRPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define HRPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define HRPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define HRPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define HRPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define HRPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define HRPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event + // 1 +#define HRPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event + // 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define HRPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define HRPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define HRPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define HRPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define HRPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define HRPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define HRPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define HRPWM_TZCLR_CBCPULSE_S 14U +#define HRPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define HRPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define HRPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define HRPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define HRPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define HRPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define HRPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define HRPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define HRPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define HRPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define HRPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define HRPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define HRPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define HRPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define HRPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define HRPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define HRPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define HRPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define HRPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define HRPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define HRPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define HRPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define HRPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define HRPWM_ETSEL_INTSEL_S 0U +#define HRPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define HRPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define HRPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define HRPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define HRPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define HRPWM_ETSEL_SOCASEL_S 8U +#define HRPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define HRPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define HRPWM_ETSEL_SOCBSEL_S 12U +#define HRPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define HRPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define HRPWM_ETPS_INTPRD_S 0U +#define HRPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define HRPWM_ETPS_INTCNT_S 2U +#define HRPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define HRPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCAPRD_S 8U +#define HRPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define HRPWM_ETPS_SOCACNT_S 10U +#define HRPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define HRPWM_ETPS_SOCBPRD_S 12U +#define HRPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define HRPWM_ETPS_SOCBCNT_S 14U +#define HRPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define HRPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define HRPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define HRPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define HRPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define HRPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define HRPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define HRPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define HRPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define HRPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define HRPWM_ETINTPS_INTPRD2_S 0U +#define HRPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define HRPWM_ETINTPS_INTCNT2_S 4U +#define HRPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define HRPWM_ETSOCPS_SOCAPRD2_S 0U +#define HRPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define HRPWM_ETSOCPS_SOCACNT2_S 4U +#define HRPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define HRPWM_ETSOCPS_SOCBPRD2_S 8U +#define HRPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define HRPWM_ETSOCPS_SOCBCNT2_S 12U +#define HRPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define HRPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define HRPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define HRPWM_ETCNTINIT_INTINIT_S 0U +#define HRPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCAINIT_S 4U +#define HRPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCBINIT_S 8U +#define HRPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define HRPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define HRPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define HRPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define HRPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define HRPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define HRPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define HRPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define HRPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define HRPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define HRPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define HRPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define HRPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define HRPWM_DCFCTL_SRCSEL_S 0U +#define HRPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define HRPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define HRPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define HRPWM_DCFCTL_PULSESEL_S 4U +#define HRPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define HRPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define HRPWM_DCFCTL_EDGEMODE_S 8U +#define HRPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define HRPWM_DCFCTL_EDGECOUNT_S 10U +#define HRPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define HRPWM_DCFCTL_EDGESTATUS_S 13U +#define HRPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define HRPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define HRPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define HRPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define HRPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define HRPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_i2c.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_i2c.h new file mode 100644 index 0000000..e37ef50 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_i2c.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_i2c.h +// +// TITLE: Definitions for the I2C registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_I2C_H +#define HW_I2C_H + +//************************************************************************************************* +// +// The following are defines for the I2C register offsets +// +//************************************************************************************************* +#define I2C_O_OAR 0x0U // I2C Own address +#define I2C_O_IER 0x1U // I2C Interrupt Enable +#define I2C_O_STR 0x2U // I2C Status +#define I2C_O_CLKL 0x3U // I2C Clock low-time divider +#define I2C_O_CLKH 0x4U // I2C Clock high-time divider +#define I2C_O_CNT 0x5U // I2C Data count +#define I2C_O_DRR 0x6U // I2C Data receive +#define I2C_O_SAR 0x7U // I2C Slave address +#define I2C_O_DXR 0x8U // I2C Data Transmit +#define I2C_O_MDR 0x9U // I2C Mode +#define I2C_O_ISRC 0xAU // I2C Interrupt Source +#define I2C_O_EMDR 0xBU // I2C Extended Mode +#define I2C_O_PSC 0xCU // I2C Prescaler +#define I2C_O_FFTX 0x20U // I2C FIFO Transmit +#define I2C_O_FFRX 0x21U // I2C FIFO Receive + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2COAR register +// +//************************************************************************************************* +#define I2C_OAR_OAR_S 0U +#define I2C_OAR_OAR_M 0x3FFU // I2C Own address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CIER register +// +//************************************************************************************************* +#define I2C_IER_ARBL 0x1U // Arbitration-lost interrupt enable +#define I2C_IER_NACK 0x2U // No-acknowledgment interrupt enable +#define I2C_IER_ARDY 0x4U // Register-access-ready interrupt enable +#define I2C_IER_RRDY 0x8U // Receive-data-ready interrupt enable +#define I2C_IER_XRDY 0x10U // Transmit-data-ready interrupt enable +#define I2C_IER_SCD 0x20U // Stop condition detected interrupt enable +#define I2C_IER_AAS 0x40U // Addressed as slave interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSTR register +// +//************************************************************************************************* +#define I2C_STR_ARBL 0x1U // Arbitration-lost interrupt flag bit +#define I2C_STR_NACK 0x2U // No-acknowledgment interrupt flag bit. +#define I2C_STR_ARDY 0x4U // Register-access-ready interrupt flag bit +#define I2C_STR_RRDY 0x8U // Receive-data-ready interrupt flag bit. +#define I2C_STR_XRDY 0x10U // Transmit-data-ready interrupt flag bit. +#define I2C_STR_SCD 0x20U // Stop condition detected bit. +#define I2C_STR_AD0 0x100U // Address 0 bits +#define I2C_STR_AAS 0x200U // Addressed-as-slave bit +#define I2C_STR_XSMT 0x400U // Transmit shift register empty bit. +#define I2C_STR_RSFULL 0x800U // Receive shift register full bit. +#define I2C_STR_BB 0x1000U // Bus busy bit. +#define I2C_STR_NACKSNT 0x2000U // NACK sent bit. +#define I2C_STR_SDIR 0x4000U // Slave direction bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDRR register +// +//************************************************************************************************* +#define I2C_DRR_DATA_S 0U +#define I2C_DRR_DATA_M 0xFFU // Receive data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSAR register +// +//************************************************************************************************* +#define I2C_SAR_SAR_S 0U +#define I2C_SAR_SAR_M 0x3FFU // Slave Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDXR register +// +//************************************************************************************************* +#define I2C_DXR_DATA_S 0U +#define I2C_DXR_DATA_M 0xFFU // Transmit data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CMDR register +// +//************************************************************************************************* +#define I2C_MDR_BC_S 0U +#define I2C_MDR_BC_M 0x7U // Bit count bits. +#define I2C_MDR_FDF 0x8U // Free Data Format +#define I2C_MDR_STB 0x10U // START Byte Mode +#define I2C_MDR_IRS 0x20U // I2C Module Reset +#define I2C_MDR_DLB 0x40U // Digital Loopback Mode +#define I2C_MDR_RM 0x80U // Repeat Mode +#define I2C_MDR_XA 0x100U // Expanded Address Mode +#define I2C_MDR_TRX 0x200U // Transmitter Mode +#define I2C_MDR_MST 0x400U // Master Mode +#define I2C_MDR_STP 0x800U // STOP Condition +#define I2C_MDR_STT 0x2000U // START condition bit +#define I2C_MDR_FREE 0x4000U // Debug Action +#define I2C_MDR_NACKMOD 0x8000U // NACK mode bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CISRC register +// +//************************************************************************************************* +#define I2C_ISRC_INTCODE_S 0U +#define I2C_ISRC_INTCODE_M 0x7U // Interrupt code bits. +#define I2C_ISRC_WRITE_ZEROS_S 8U +#define I2C_ISRC_WRITE_ZEROS_M 0xF00U // Always write all 0s to this field + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CEMDR register +// +//************************************************************************************************* +#define I2C_EMDR_BC 0x1U // Backwards compatibility mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CPSC register +// +//************************************************************************************************* +#define I2C_PSC_IPSC_S 0U +#define I2C_PSC_IPSC_M 0xFFU // I2C Prescaler Divide Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFTX register +// +//************************************************************************************************* +#define I2C_FFTX_TXFFIL_S 0U +#define I2C_FFTX_TXFFIL_M 0x1FU // Transmit FIFO Interrupt Level +#define I2C_FFTX_TXFFIENA 0x20U // Transmit FIFO Interrupt Enable +#define I2C_FFTX_TXFFINTCLR 0x40U // Transmit FIFO Interrupt Flag Clear +#define I2C_FFTX_TXFFINT 0x80U // Transmit FIFO Interrupt Flag +#define I2C_FFTX_TXFFST_S 8U +#define I2C_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define I2C_FFTX_TXFFRST 0x2000U // Transmit FIFO Reset +#define I2C_FFTX_I2CFFEN 0x4000U // Transmit FIFO Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFRX register +// +//************************************************************************************************* +#define I2C_FFRX_RXFFIL_S 0U +#define I2C_FFRX_RXFFIL_M 0x1FU // Receive FIFO Interrupt Level +#define I2C_FFRX_RXFFIENA 0x20U // Receive FIFO Interrupt Enable +#define I2C_FFRX_RXFFINTCLR 0x40U // Receive FIFO Interrupt Flag Clear +#define I2C_FFRX_RXFFINT 0x80U // Receive FIFO Interrupt Flag +#define I2C_FFRX_RXFFST_S 8U +#define I2C_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define I2C_FFRX_RXFFRST 0x2000U // Receive FIFO Reset + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_inputxbar.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_inputxbar.h new file mode 100644 index 0000000..a2567f2 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_inputxbar.h @@ -0,0 +1,92 @@ +//########################################################################### +// +// FILE: hw_inputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_INPUTXBAR_H +#define HW_INPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INPUTSELECTLOCK register +// +//************************************************************************************************* +#define XBAR_INPUTSELECTLOCK_INPUT1SELECT 0x1U // Lock bit for INPUT1SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT2SELECT 0x2U // Lock bit for INPUT2SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT3SELECT 0x4U // Lock bit for INPUT3SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT4SELECT 0x8U // Lock bit for INPUT4SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT5SELECT 0x10U // Lock bit for INPUT5SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT6SELECT 0x20U // Lock bit for INPUT6SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT7SELECT 0x40U // Lock bit for INPUT7SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT8SELECT 0x80U // Lock bit for INPUT8SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT9SELECT 0x100U // Lock bit for INPUT9SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT10SELECT 0x200U // Lock bit for INPUT10SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT11SELECT 0x400U // Lock bit for INPUT11SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT12SELECT 0x800U // Lock bit for INPUT12SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT13SELECT 0x1000U // Lock bit for INPUT13SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT14SELECT 0x2000U // Lock bit for INPUT14SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT15SELECT 0x4000U // Lock bit for INPUT15SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT16SELECT 0x8000U // Lock bit for INPUT16SELECT Register + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_ints.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_ints.h new file mode 100644 index 0000000..d49c58d --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_ints.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: hw_ints.h +// +// TITLE: Definitions of interrupt numbers for use with interrupt.c. +// +//########################################################################### +// +// +//########################################################################### + +#ifndef HW_INTS_H +#define HW_INTS_H + +//***************************************************************************** +// +// PIE Interrupt Numbers +// +// 0x00FF = PIE Table Row # +// 0xFF00 = PIE Table Column # +// 0xFFFF0000 = PIE Vector ID +// +//***************************************************************************** + +// Lower PIE Group 1 +#define INT_ADCA1 0x00200101U // 1.1 - ADCA Interrupt 1 +#define INT_ADCB1 0x00210102U // 1.2 - ADCB Interrupt 1 +#define INT_ADCC1 0x00220103U // 1.3 - ADCC Interrupt 1 +#define INT_XINT1 0x00230104U // 1.4 - XINT1 Interrupt +#define INT_XINT2 0x00240105U // 1.5 - XINT2 Interrupt +#define INT_ADCD1 0x00250106U // 1.6 - ADCD Interrupt 1 +#define INT_TIMER0 0x00260107U // 1.7 - Timer 0 Interrupt +#define INT_WAKE 0x00270108U // 1.8 - Standby and Halt Wakeup Interrupt + +// Lower PIE Group 2 +#define INT_EPWM1_TZ 0x00280201U // 2.1 - ePWM1 Trip Zone Interrupt +#define INT_EPWM2_TZ 0x00290202U // 2.2 - ePWM2 Trip Zone Interrupt +#define INT_EPWM3_TZ 0x002A0203U // 2.3 - ePWM3 Trip Zone Interrupt +#define INT_EPWM4_TZ 0x002B0204U // 2.4 - ePWM4 Trip Zone Interrupt +#define INT_EPWM5_TZ 0x002C0205U // 2.5 - ePWM5 Trip Zone Interrupt +#define INT_EPWM6_TZ 0x002D0206U // 2.6 - ePWM6 Trip Zone Interrupt +#define INT_EPWM7_TZ 0x002E0207U // 2.7 - ePWM7 Trip Zone Interrupt +#define INT_EPWM8_TZ 0x002F0208U // 2.8 - ePWM8 Trip Zone Interrupt + +// Lower PIE Group 3 +#define INT_EPWM1 0x00300301U // 3.1 - ePWM1 Interrupt +#define INT_EPWM2 0x00310302U // 3.2 - ePWM2 Interrupt +#define INT_EPWM3 0x00320303U // 3.3 - ePWM3 Interrupt +#define INT_EPWM4 0x00330304U // 3.4 - ePWM4 Interrupt +#define INT_EPWM5 0x00340305U // 3.5 - ePWM5 Interrupt +#define INT_EPWM6 0x00350306U // 3.6 - ePWM6 Interrupt +#define INT_EPWM7 0x00360307U // 3.7 - ePWM7 Interrupt +#define INT_EPWM8 0x00370308U // 3.8 - ePWM8 Interrupt + +// Lower PIE Group 4 +#define INT_ECAP1 0x00380401U // 4.1 - eCAP1 Interrupt +#define INT_ECAP2 0x00390402U // 4.2 - eCAP2 Interrupt +#define INT_ECAP3 0x003A0403U // 4.3 - eCAP3 Interrupt +#define INT_ECAP4 0x003B0404U // 4.4 - eCAP4 Interrupt +#define INT_ECAP5 0x003C0405U // 4.5 - eCAP5 Interrupt +#define INT_ECAP6 0x003D0406U // 4.6 - eCAP6 Interrupt +// Lower PIE Group 5 +#define INT_EQEP1 0x00400501U // 5.1 - eQEP1 Interrupt +#define INT_EQEP2 0x00410502U // 5.2 - eQEP2 Interrupt +#define INT_EQEP3 0x00420503U // 5.3 - eQEP3 Interrupt +#define INT_CLB1 0x00440505U // 5.5 - CLB1 (Reconfigurable Logic) Interrupt +#define INT_CLB2 0x00450506U // 5.6 - CLB2 (Reconfigurable Logic) Interrupt +#define INT_CLB3 0x00460507U // 5.7 - CLB3 (Reconfigurable Logic) Interrupt +#define INT_CLB4 0x00470508U // 5.8 - CLB4 (Reconfigurable Logic) Interrupt + +// Lower PIE Group 6 +#define INT_SPIA_RX 0x00480601U // 6.1 - SPIA Receive Interrupt +#define INT_SPIA_TX 0x00490602U // 6.2 - SPIA Transmit Interrupt +#define INT_SPIB_RX 0x004A0603U // 6.3 - SPIB Receive Interrupt +#define INT_SPIB_TX 0x004B0604U // 6.4 - SPIB Transmit Interrupt +#define INT_MCBSPA_RX 0x004C0605U // 6.5 - McBSPA Receive Interrupt +#define INT_MCBSPA_TX 0x004D0606U // 6.6 - McBSPA Transmit Interrupt +#define INT_MCBSPB_RX 0x004E0607U // 6.7 - McBSPB Receive Interrupt +#define INT_MCBSPB_TX 0x004F0608U // 6.8 - McBSPB Transmit Interrupt + +// Lower PIE Group 7 +#define INT_DMA_CH1 0x00500701U // 7.1 - DMA Channel 1 Interrupt +#define INT_DMA_CH2 0x00510702U // 7.2 - DMA Channel 2 Interrupt +#define INT_DMA_CH3 0x00520703U // 7.3 - DMA Channel 3 Interrupt +#define INT_DMA_CH4 0x00530704U // 7.4 - DMA Channel 4 Interrupt +#define INT_DMA_CH5 0x00540705U // 7.5 - DMA Channel 5 Interrupt +#define INT_DMA_CH6 0x00550706U // 7.6 - DMA Channel 6 Interrupt + +// Lower PIE Group 8 +#define INT_I2CA 0x00580801U // 8.1 - I2CA Interrupt 1 +#define INT_I2CA_FIFO 0x00590802U // 8.2 - I2CA Interrupt 2 +#define INT_I2CB 0x005A0803U // 8.3 - I2CB Interrupt 1 +#define INT_I2CB_FIFO 0x005B0804U // 8.4 - I2CB Interrupt 2 +#define INT_SCIC_RX 0x005C0805U // 8.5 - SCIC Receive Interrupt +#define INT_SCIC_TX 0x005D0806U // 8.6 - SCIC Transmit Interrupt +#define INT_SCID_RX 0x005E0807U // 8.7 - SCID Receive Interrupt +#define INT_SCID_TX 0x005F0808U // 8.8 - SCID Transmit Interrupt + +// Lower PIE Group 9 +#define INT_SCIA_RX 0x00600901U // 9.1 - SCIA Receive Interrupt +#define INT_SCIA_TX 0x00610902U // 9.2 - SCIA Transmit Interrupt +#define INT_SCIB_RX 0x00620903U // 9.3 - SCIB Receive Interrupt +#define INT_SCIB_TX 0x00630904U // 9.4 - SCIB Transmit Interrupt +#define INT_CANA0 0x00640905U // 9.5 - CANA Interrupt 0 +#define INT_CANA1 0x00650906U // 9.6 - CANA Interrupt 1 +#define INT_CANB0 0x00660907U // 9.7 - CANB Interrupt 0 +#define INT_CANB1 0x00670908U // 9.8 - CANB Interrupt 1 + +// Lower PIE Group 10 +#define INT_ADCA_EVT 0x00680A01U // 10.1 - ADCA Event Interrupt +#define INT_ADCA2 0x00690A02U // 10.2 - ADCA Interrupt 2 +#define INT_ADCA3 0x006A0A03U // 10.3 - ADCA Interrupt 3 +#define INT_ADCA4 0x006B0A04U // 10.4 - ADCA Interrupt 4 +#define INT_ADCB_EVT 0x006C0A05U // 10.5 - ADCB Event Interrupt +#define INT_ADCB2 0x006D0A06U // 10.6 - ADCB Interrupt 2 +#define INT_ADCB3 0x006E0A07U // 10.7 - ADCB Interrupt 3 +#define INT_ADCB4 0x006F0A08U // 10.8 - ADCB Interrupt 4 + +// Lower PIE Group 11 +#define INT_CLA1_1 0x00700B01U // 11.1 - CLA1 Interrupt 1 +#define INT_CLA1_2 0x00710B02U // 11.2 - CLA1 Interrupt 2 +#define INT_CLA1_3 0x00720B03U // 11.3 - CLA1 Interrupt 3 +#define INT_CLA1_4 0x00730B04U // 11.4 - CLA1 Interrupt 4 +#define INT_CLA1_5 0x00740B05U // 11.5 - CLA1 Interrupt 5 +#define INT_CLA1_6 0x00750B06U // 11.6 - CLA1 Interrupt 6 +#define INT_CLA1_7 0x00760B07U // 11.7 - CLA1 Interrupt 7 +#define INT_CLA1_8 0x00770B08U // 11.8 - CLA1 Interrupt 8 + +// Lower PIE Group 12 +#define INT_XINT3 0x00780C01U // 12.1 - XINT3 Interrupt +#define INT_XINT4 0x00790C02U // 12.2 - XINT4 Interrupt +#define INT_XINT5 0x007A0C03U // 12.3 - XINT5 Interrupt +#define INT_PBIST 0x007B0C04U // 12.4 - PBIST Interrupt +#define INT_FMC 0x007C0C05U // 12.5 - Flash Wrapper Operation Done Interrupt +#define INT_VCU 0x007D0C06U // 12.6 - VCU Interrupt +#define INT_FPU_OVERFLOW 0x007E0C07U // 12.7 - FPU Overflow Interrupt +#define INT_FPU_UNDERFLOW 0x007F0C08U // 12.8 - FPU Underflow Interrupt + +// Upper PIE Group 1 +#define INT_IPC_0 0x0084010DU // 1.13 - IPC Interrupt 1 +#define INT_IPC_1 0x0085010EU // 1.14 - IPC Interrupt 2 +#define INT_IPC_2 0x0086010FU // 1.15 - IPC Interrupt 3 +#define INT_IPC_3 0x00870110U // 1.16 - IPC Interrupt 4 + +// Upper PIE Group 2 +#define INT_EPWM9_TZ 0x00880209U // 2.9 - ePWM9 Trip Zone Interrupt +#define INT_EPWM10_TZ 0x0089020AU // 2.10 - ePWM10 Trip Zone Interrupt +#define INT_EPWM11_TZ 0x008A020BU // 2.11 - ePWM11 Trip Zone Interrupt +#define INT_EPWM12_TZ 0x008B020CU // 2.12 - ePWM12 Trip Zone Interrupt + +// Upper PIE Group 3 +#define INT_EPWM9 0x00900309U // 3.9 - ePWM9 Interrupt +#define INT_EPWM10 0x0091030AU // 3.10 - ePWM10 Interrupt +#define INT_EPWM11 0x0092030BU // 3.11 - ePWM11 Interrupt +#define INT_EPWM12 0x0093030CU // 3.12 - ePWM12 Interrupt + +// Upper PIE Group 5 +#define INT_SD1 0x00A00509U // 5.9 - SD1 Interrupt +#define INT_SD2 0x00A1050AU // 5.10 - SD2 Interrupt + +// Upper PIE Group 6 +#define INT_SPIC_RX 0x00A80609U // 6.9 - SPIC Receive Interrupt +#define INT_SPIC_TX 0x00A9060AU // 6.10 - SPIC Transmit Interrupt + +// Upper PIE Group 8 +#define INT_UPPA 0x00BE080FU // 8.15 - uPPA Interrupt + +// Upper PIE Group 9 +#define INT_USBA 0x00C6090FU // 9.15 - USBA Interrupt + +// Upper PIE Group 10 +#define INT_ADCC_EVT 0x00C80A09U // 10.9 - ADCC Event Interrupt +#define INT_ADCC2 0x00C90A0AU // 10.10 - ADCC Interrupt 2 +#define INT_ADCC3 0x00CA0A0BU // 10.11 - ADCC Interrupt 3 +#define INT_ADCC4 0x00CB0A0CU // 10.12 - ADCC Interrupt 4 +#define INT_ADCD_EVT 0x00CC0A0DU // 10.13 - ADCD Event Interrupt +#define INT_ADCD2 0x00CD0A0EU // 10.14 - ADCD Interrupt 2 +#define INT_ADCD3 0x00CE0A0FU // 10.15 - ADCD Interrupt 3 +#define INT_ADCD4 0x00CF0A10U // 10.16 - ADCD Interrupt 4 + +// Upper PIE Group 12 +#define INT_EMIF_ERROR 0x00D80C09U // 12.9 - EMIF Error Interrupt +#define INT_RAM_CORR_ERR 0x00D90C0AU // 12.10 - RAM Correctable Error Interrupt +#define INT_FLASH_CORR_ERR 0x00DA0C0BU // 12.11 - Flash Correctable Error Interrupt +#define INT_RAM_ACC_VIOL 0x00DB0C0CU // 12.12 - RAM Access Violation Interrupt +#define INT_SYS_PLL_SLIP 0x00DC0C0DU // 12.13 - System PLL Slip Interrupt +#define INT_AUX_PLL_SLIP 0x00DD0C0EU // 12.14 - Auxiliary PLL Slip Interrupt +#define INT_CLA_OVERFLOW 0x00DE0C0FU // 12.15 - CLA Overflow Interrupt +#define INT_CLA_UNDERFLOW 0x00DF0C10U // 12.16 - CLA Underflow Interrupt + +// Other interrupts +#define INT_TIMER1 0x000D0000U // CPU Timer 1 Interrupt +#define INT_TIMER2 0x000E0000U // CPU Timer 2 Interrupt +#define INT_DATALOG 0x000F0000U // Datalogging Interrupt +#define INT_RTOS 0x00100000U // RTOS Interrupt +#define INT_EMU 0x00110000U // Emulation Interrupt +#define INT_NMI 0x00120000U // Non-Maskable Interrupt +#define INT_ILLEGAL 0x00130000U // Illegal Operation Trap +#define INT_USER1 0x00140000U // User Defined Trap 1 +#define INT_USER2 0x00150000U // User Defined Trap 2 +#define INT_USER3 0x00160000U // User Defined Trap 3 +#define INT_USER4 0x00170000U // User Defined Trap 4 +#define INT_USER5 0x00180000U // User Defined Trap 5 +#define INT_USER6 0x00190000U // User Defined Trap 6 +#define INT_USER7 0x001A0000U // User Defined Trap 7 +#define INT_USER8 0x001B0000U // User Defined Trap 8 +#define INT_USER9 0x001C0000U // User Defined Trap 9 +#define INT_USER10 0x001D0000U // User Defined Trap 10 +#define INT_USER11 0x001E0000U // User Defined Trap 11 +#define INT_USER12 0x001F0000U // User Defined Trap 12 + +#endif // HW_INTS_H diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_ipc.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_ipc.h new file mode 100644 index 0000000..e99715f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_ipc.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: hw_ipc.h +// +// TITLE: Definitions for the IPC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_IPC_H +#define HW_IPC_H + +//***************************************************************************** +// +// The following are defines for the IPC register offsets +// +//***************************************************************************** +#define IPC_O_ACK 0x0U // IPC incoming flag clear + // (acknowledge) register +#define IPC_O_STS 0x2U // IPC incoming flag status + // register +#define IPC_O_SET 0x4U // IPC remote flag set register +#define IPC_O_CLR 0x6U // IPC remote flag clear + // register +#define IPC_O_FLG 0x8U // IPC remote flag status + // register +#define IPC_O_COUNTERL 0xCU // IPC Counter Low Register +#define IPC_O_COUNTERH 0xEU // IPC Counter High Register +#ifndef CPU2 +#define IPC_O_SENDCOM 0x10U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x12U // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x14U // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x16U // Remote to Local IPC Reply + // Data Register +#define IPC_O_RECVCOM 0x18U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x1AU // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x1CU // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x1EU // Local to Remote IPC Reply + // Data Register +#else +#define IPC_O_RECVCOM 0x10U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x12U // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x14U // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x16U // Local to Remote IPC Reply + // Data Register +#define IPC_O_SENDCOM 0x18U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x1AU // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x1CU // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x1EU // Remote to Local IPC Reply + // Data Register +#endif +#define IPC_O_BOOTSTS 0x20U // CPU2 to CPU1 IPC Boot Status + // Register +#define IPC_O_BOOTMODE 0x22U // CPU1 to CPU2 IPC Boot Mode + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCACK register +// +//***************************************************************************** +#define IPC_ACK_IPC0 0x1U // Local IPC Flag 0 + // Acknowledgement +#define IPC_ACK_IPC1 0x2U // Local IPC Flag 1 + // Acknowledgement +#define IPC_ACK_IPC2 0x4U // Local IPC Flag 2 + // Acknowledgement +#define IPC_ACK_IPC3 0x8U // Local IPC Flag 3 + // Acknowledgement +#define IPC_ACK_IPC4 0x10U // Local IPC Flag 4 + // Acknowledgement +#define IPC_ACK_IPC5 0x20U // Local IPC Flag 5 + // Acknowledgement +#define IPC_ACK_IPC6 0x40U // Local IPC Flag 6 + // Acknowledgement +#define IPC_ACK_IPC7 0x80U // Local IPC Flag 7 + // Acknowledgement +#define IPC_ACK_IPC8 0x100U // Local IPC Flag 8 + // Acknowledgement +#define IPC_ACK_IPC9 0x200U // Local IPC Flag 9 + // Acknowledgement +#define IPC_ACK_IPC10 0x400U // Local IPC Flag 10 + // Acknowledgement +#define IPC_ACK_IPC11 0x800U // Local IPC Flag 11 + // Acknowledgement +#define IPC_ACK_IPC12 0x1000U // Local IPC Flag 12 + // Acknowledgement +#define IPC_ACK_IPC13 0x2000U // Local IPC Flag 13 + // Acknowledgement +#define IPC_ACK_IPC14 0x4000U // Local IPC Flag 14 + // Acknowledgement +#define IPC_ACK_IPC15 0x8000U // Local IPC Flag 15 + // Acknowledgement +#define IPC_ACK_IPC16 0x10000U // Local IPC Flag 16 + // Acknowledgement +#define IPC_ACK_IPC17 0x20000U // Local IPC Flag 17 + // Acknowledgement +#define IPC_ACK_IPC18 0x40000U // Local IPC Flag 18 + // Acknowledgement +#define IPC_ACK_IPC19 0x80000U // Local IPC Flag 19 + // Acknowledgement +#define IPC_ACK_IPC20 0x100000U // Local IPC Flag 20 + // Acknowledgement +#define IPC_ACK_IPC21 0x200000U // Local IPC Flag 21 + // Acknowledgement +#define IPC_ACK_IPC22 0x400000U // Local IPC Flag 22 + // Acknowledgement +#define IPC_ACK_IPC23 0x800000U // Local IPC Flag 23 + // Acknowledgement +#define IPC_ACK_IPC24 0x1000000U // Local IPC Flag 24 + // Acknowledgement +#define IPC_ACK_IPC25 0x2000000U // Local IPC Flag 25 + // Acknowledgement +#define IPC_ACK_IPC26 0x4000000U // Local IPC Flag 26 + // Acknowledgement +#define IPC_ACK_IPC27 0x8000000U // Local IPC Flag 27 + // Acknowledgement +#define IPC_ACK_IPC28 0x10000000U // Local IPC Flag 28 + // Acknowledgement +#define IPC_ACK_IPC29 0x20000000U // Local IPC Flag 29 + // Acknowledgement +#define IPC_ACK_IPC30 0x40000000U // Local IPC Flag 30 + // Acknowledgement +#define IPC_ACK_IPC31 0x80000000U // Local IPC Flag 31 + // Acknowledgement + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSTS register +// +//***************************************************************************** +#define IPC_STS_IPC0 0x1U // Local IPC Flag 0 Status +#define IPC_STS_IPC1 0x2U // Local IPC Flag 1 Status +#define IPC_STS_IPC2 0x4U // Local IPC Flag 2 Status +#define IPC_STS_IPC3 0x8U // Local IPC Flag 3 Status +#define IPC_STS_IPC4 0x10U // Local IPC Flag 4 Status +#define IPC_STS_IPC5 0x20U // Local IPC Flag 5 Status +#define IPC_STS_IPC6 0x40U // Local IPC Flag 6 Status +#define IPC_STS_IPC7 0x80U // Local IPC Flag 7 Status +#define IPC_STS_IPC8 0x100U // Local IPC Flag 8 Status +#define IPC_STS_IPC9 0x200U // Local IPC Flag 9 Status +#define IPC_STS_IPC10 0x400U // Local IPC Flag 10 Status +#define IPC_STS_IPC11 0x800U // Local IPC Flag 11 Status +#define IPC_STS_IPC12 0x1000U // Local IPC Flag 12 Status +#define IPC_STS_IPC13 0x2000U // Local IPC Flag 13 Status +#define IPC_STS_IPC14 0x4000U // Local IPC Flag 14 Status +#define IPC_STS_IPC15 0x8000U // Local IPC Flag 15 Status +#define IPC_STS_IPC16 0x10000U // Local IPC Flag 16 Status +#define IPC_STS_IPC17 0x20000U // Local IPC Flag 17 Status +#define IPC_STS_IPC18 0x40000U // Local IPC Flag 18 Status +#define IPC_STS_IPC19 0x80000U // Local IPC Flag 19 Status +#define IPC_STS_IPC20 0x100000U // Local IPC Flag 20 Status +#define IPC_STS_IPC21 0x200000U // Local IPC Flag 21 Status +#define IPC_STS_IPC22 0x400000U // Local IPC Flag 22 Status +#define IPC_STS_IPC23 0x800000U // Local IPC Flag 23 Status +#define IPC_STS_IPC24 0x1000000U // Local IPC Flag 24 Status +#define IPC_STS_IPC25 0x2000000U // Local IPC Flag 25 Status +#define IPC_STS_IPC26 0x4000000U // Local IPC Flag 26 Status +#define IPC_STS_IPC27 0x8000000U // Local IPC Flag 27 Status +#define IPC_STS_IPC28 0x10000000U // Local IPC Flag 28 Status +#define IPC_STS_IPC29 0x20000000U // Local IPC Flag 29 Status +#define IPC_STS_IPC30 0x40000000U // Local IPC Flag 30 Status +#define IPC_STS_IPC31 0x80000000U // Local IPC Flag 31 Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSET register +// +//***************************************************************************** +#define IPC_SET_IPC0 0x1U // Set Remote IPC0 Flag +#define IPC_SET_IPC1 0x2U // Set Remote IPC1 Flag +#define IPC_SET_IPC2 0x4U // Set Remote IPC2 Flag +#define IPC_SET_IPC3 0x8U // Set Remote IPC3 Flag +#define IPC_SET_IPC4 0x10U // Set Remote IPC4 Flag +#define IPC_SET_IPC5 0x20U // Set Remote IPC5 Flag +#define IPC_SET_IPC6 0x40U // Set Remote IPC6 Flag +#define IPC_SET_IPC7 0x80U // Set Remote IPC7 Flag +#define IPC_SET_IPC8 0x100U // Set Remote IPC8 Flag +#define IPC_SET_IPC9 0x200U // Set Remote IPC9 Flag +#define IPC_SET_IPC10 0x400U // Set Remote IPC10 Flag +#define IPC_SET_IPC11 0x800U // Set Remote IPC11 Flag +#define IPC_SET_IPC12 0x1000U // Set Remote IPC12 Flag +#define IPC_SET_IPC13 0x2000U // Set Remote IPC13 Flag +#define IPC_SET_IPC14 0x4000U // Set Remote IPC14 Flag +#define IPC_SET_IPC15 0x8000U // Set Remote IPC15 Flag +#define IPC_SET_IPC16 0x10000U // Set Remote IPC16 Flag +#define IPC_SET_IPC17 0x20000U // Set Remote IPC17 Flag +#define IPC_SET_IPC18 0x40000U // Set Remote IPC18 Flag +#define IPC_SET_IPC19 0x80000U // Set Remote IPC19 Flag +#define IPC_SET_IPC20 0x100000U // Set Remote IPC20 Flag +#define IPC_SET_IPC21 0x200000U // Set Remote IPC21 Flag +#define IPC_SET_IPC22 0x400000U // Set Remote IPC22 Flag +#define IPC_SET_IPC23 0x800000U // Set Remote IPC23 Flag +#define IPC_SET_IPC24 0x1000000U // Set Remote IPC24 Flag +#define IPC_SET_IPC25 0x2000000U // Set Remote IPC25 Flag +#define IPC_SET_IPC26 0x4000000U // Set Remote IPC26 Flag +#define IPC_SET_IPC27 0x8000000U // Set Remote IPC27 Flag +#define IPC_SET_IPC28 0x10000000U // Set Remote IPC28 Flag +#define IPC_SET_IPC29 0x20000000U // Set Remote IPC29 Flag +#define IPC_SET_IPC30 0x40000000U // Set Remote IPC30 Flag +#define IPC_SET_IPC31 0x80000000U // Set Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCCLR register +// +//***************************************************************************** +#define IPC_CLR_IPC0 0x1U // Clear Remote IPC0 Flag +#define IPC_CLR_IPC1 0x2U // Clear Remote IPC1 Flag +#define IPC_CLR_IPC2 0x4U // Clear Remote IPC2 Flag +#define IPC_CLR_IPC3 0x8U // Clear Remote IPC3 Flag +#define IPC_CLR_IPC4 0x10U // Clear Remote IPC4 Flag +#define IPC_CLR_IPC5 0x20U // Clear Remote IPC5 Flag +#define IPC_CLR_IPC6 0x40U // Clear Remote IPC6 Flag +#define IPC_CLR_IPC7 0x80U // Clear Remote IPC7 Flag +#define IPC_CLR_IPC8 0x100U // Clear Remote IPC8 Flag +#define IPC_CLR_IPC9 0x200U // Clear Remote IPC9 Flag +#define IPC_CLR_IPC10 0x400U // Clear Remote IPC10 Flag +#define IPC_CLR_IPC11 0x800U // Clear Remote IPC11 Flag +#define IPC_CLR_IPC12 0x1000U // Clear Remote IPC12 Flag +#define IPC_CLR_IPC13 0x2000U // Clear Remote IPC13 Flag +#define IPC_CLR_IPC14 0x4000U // Clear Remote IPC14 Flag +#define IPC_CLR_IPC15 0x8000U // Clear Remote IPC15 Flag +#define IPC_CLR_IPC16 0x10000U // Clear Remote IPC16 Flag +#define IPC_CLR_IPC17 0x20000U // Clear Remote IPC17 Flag +#define IPC_CLR_IPC18 0x40000U // Clear Remote IPC18 Flag +#define IPC_CLR_IPC19 0x80000U // Clear Remote IPC19 Flag +#define IPC_CLR_IPC20 0x100000U // Clear Remote IPC20 Flag +#define IPC_CLR_IPC21 0x200000U // Clear Remote IPC21 Flag +#define IPC_CLR_IPC22 0x400000U // Clear Remote IPC22 Flag +#define IPC_CLR_IPC23 0x800000U // Clear Remote IPC23 Flag +#define IPC_CLR_IPC24 0x1000000U // Clear Remote IPC24 Flag +#define IPC_CLR_IPC25 0x2000000U // Clear Remote IPC25 Flag +#define IPC_CLR_IPC26 0x4000000U // Clear Remote IPC26 Flag +#define IPC_CLR_IPC27 0x8000000U // Clear Remote IPC27 Flag +#define IPC_CLR_IPC28 0x10000000U // Clear Remote IPC28 Flag +#define IPC_CLR_IPC29 0x20000000U // Clear Remote IPC29 Flag +#define IPC_CLR_IPC30 0x40000000U // Clear Remote IPC30 Flag +#define IPC_CLR_IPC31 0x80000000U // Clear Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCFLG register +// +//***************************************************************************** +#define IPC_FLG_IPC0 0x1U // Remote IPC0 Flag Status +#define IPC_FLG_IPC1 0x2U // Remote IPC1 Flag Status +#define IPC_FLG_IPC2 0x4U // Remote IPC2 Flag Status +#define IPC_FLG_IPC3 0x8U // Remote IPC3 Flag Status +#define IPC_FLG_IPC4 0x10U // Remote IPC4 Flag Status +#define IPC_FLG_IPC5 0x20U // Remote IPC5 Flag Status +#define IPC_FLG_IPC6 0x40U // Remote IPC6 Flag Status +#define IPC_FLG_IPC7 0x80U // Remote IPC7 Flag Status +#define IPC_FLG_IPC8 0x100U // Remote IPC8 Flag Status +#define IPC_FLG_IPC9 0x200U // Remote IPC9 Flag Status +#define IPC_FLG_IPC10 0x400U // Remote IPC10 Flag Status +#define IPC_FLG_IPC11 0x800U // Remote IPC11 Flag Status +#define IPC_FLG_IPC12 0x1000U // Remote IPC12 Flag Status +#define IPC_FLG_IPC13 0x2000U // Remote IPC13 Flag Status +#define IPC_FLG_IPC14 0x4000U // Remote IPC14 Flag Status +#define IPC_FLG_IPC15 0x8000U // Remote IPC15 Flag Status +#define IPC_FLG_IPC16 0x10000U // Remote IPC16 Flag Status +#define IPC_FLG_IPC17 0x20000U // Remote IPC17 Flag Status +#define IPC_FLG_IPC18 0x40000U // Remote IPC18 Flag Status +#define IPC_FLG_IPC19 0x80000U // Remote IPC19 Flag Status +#define IPC_FLG_IPC20 0x100000U // Remote IPC20 Flag Status +#define IPC_FLG_IPC21 0x200000U // Remote IPC21 Flag Status +#define IPC_FLG_IPC22 0x400000U // Remote IPC22 Flag Status +#define IPC_FLG_IPC23 0x800000U // Remote IPC23 Flag Status +#define IPC_FLG_IPC24 0x1000000U // Remote IPC24 Flag Status +#define IPC_FLG_IPC25 0x2000000U // Remote IPC25 Flag Status +#define IPC_FLG_IPC26 0x4000000U // Remote IPC26 Flag Status +#define IPC_FLG_IPC27 0x8000000U // Remote IPC27 Flag Status +#define IPC_FLG_IPC28 0x10000000U // Remote IPC28 Flag Status +#define IPC_FLG_IPC29 0x20000000U // Remote IPC29 Flag Status +#define IPC_FLG_IPC30 0x40000000U // Remote IPC30 Flag Status +#define IPC_FLG_IPC31 0x80000000U // Remote IPC31 Flag Status +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_mcbsp.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_mcbsp.h new file mode 100644 index 0000000..814055f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_mcbsp.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_mcbsp.h +// +// TITLE: Definitions for the MCBSP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MCBSP_H +#define HW_MCBSP_H + +//************************************************************************************************* +// +// The following are defines for the MCBSP register offsets +// +//************************************************************************************************* +#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16 +#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0 +#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16 +#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0 +#define MCBSP_O_SPCR2 0x4U // Serial port control register 2 +#define MCBSP_O_SPCR1 0x5U // Serial port control register 1 +#define MCBSP_O_RCR2 0x6U // Receive Control register 2 +#define MCBSP_O_RCR1 0x7U // Receive Control register 1 +#define MCBSP_O_XCR2 0x8U // Transmit Control register 2 +#define MCBSP_O_XCR1 0x9U // Transmit Control register 1 +#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2 +#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1 +#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2 +#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1 +#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A +#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B +#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A +#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B +#define MCBSP_O_PCR 0x12U // Pin Control register +#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C +#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D +#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C +#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D +#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E +#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F +#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E +#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F +#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G +#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H +#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G +#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H +#define MCBSP_O_MFFINT 0x23U // Interrupt enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR2 register +// +//************************************************************************************************* +#define MCBSP_DRR2_HWLB_S 0U +#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DRR2_HWHB_S 8U +#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR1 register +// +//************************************************************************************************* +#define MCBSP_DRR1_LWLB_S 0U +#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DRR1_LWHB_S 8U +#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR2 register +// +//************************************************************************************************* +#define MCBSP_DXR2_HWLB_S 0U +#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DXR2_HWHB_S 8U +#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR1 register +// +//************************************************************************************************* +#define MCBSP_DXR1_LWLB_S 0U +#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DXR1_LWHB_S 8U +#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR2 register +// +//************************************************************************************************* +#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset +#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready +#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty +#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag +#define MCBSP_SPCR2_XINTM_S 4U +#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits +#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset +#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset +#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit +#define MCBSP_SPCR2_FREE 0x200U // FREE bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR1 register +// +//************************************************************************************************* +#define MCBSP_SPCR1_RRST 0x1U // Receiver reset +#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready +#define MCBSP_SPCR1_RFULL 0x4U // Receiver full +#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag +#define MCBSP_SPCR1_RINTM_S 4U +#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits +#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable +#define MCBSP_SPCR1_CLKSTP_S 11U +#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode +#define MCBSP_SPCR1_RJUST_S 13U +#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode +#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR2 register +// +//************************************************************************************************* +#define MCBSP_RCR2_RDATDLY_S 0U +#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay +#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore +#define MCBSP_RCR2_RCOMPAND_S 3U +#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects +#define MCBSP_RCR2_RWDLEN2_S 5U +#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2 +#define MCBSP_RCR2_RFRLEN2_S 8U +#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2 +#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR1 register +// +//************************************************************************************************* +#define MCBSP_RCR1_RWDLEN1_S 5U +#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1 +#define MCBSP_RCR1_RFRLEN1_S 8U +#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR2 register +// +//************************************************************************************************* +#define MCBSP_XCR2_XDATDLY_S 0U +#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay +#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore +#define MCBSP_XCR2_XCOMPAND_S 3U +#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects +#define MCBSP_XCR2_XWDLEN2_S 5U +#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2 +#define MCBSP_XCR2_XFRLEN2_S 8U +#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2 +#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR1 register +// +//************************************************************************************************* +#define MCBSP_XCR1_XWDLEN1_S 5U +#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1 +#define MCBSP_XCR1_XFRLEN1_S 8U +#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR2 register +// +//************************************************************************************************* +#define MCBSP_SRGR2_FPER_S 0U +#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period +#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode +#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode +#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR1 register +// +//************************************************************************************************* +#define MCBSP_SRGR1_CLKGDV_S 0U +#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider +#define MCBSP_SRGR1_FWID_S 8U +#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR2 register +// +//************************************************************************************************* +#define MCBSP_MCR2_XMCM_S 0U +#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay +#define MCBSP_MCR2_XCBLK_S 2U +#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore +#define MCBSP_MCR2_XPABLK_S 5U +#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects +#define MCBSP_MCR2_XPBBLK_S 7U +#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2 +#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR1 register +// +//************************************************************************************************* +#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode +#define MCBSP_MCR1_RCBLK_S 2U +#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block +#define MCBSP_MCR1_RPABLK_S 5U +#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block +#define MCBSP_MCR1_RPBBLK_S 7U +#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block +#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCR register +// +//************************************************************************************************* +#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity +#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity +#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity +#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity +#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection +#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode +#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode. +#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode +#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MFFINT register +// +//************************************************************************************************* +#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt +#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_memcfg.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_memcfg.h new file mode 100644 index 0000000..d5d7e8c --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_memcfg.h @@ -0,0 +1,870 @@ +//########################################################################### +// +// FILE: hw_memcfg.h +// +// TITLE: Definitions for the MEMCFG registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMCFG_H +#define HW_MEMCFG_H + +//************************************************************************************************* +// +// The following are defines for the MEMCFG register offsets +// +//************************************************************************************************* +#define MEMCFG_O_DXLOCK 0x0U // Dedicated RAM Config Lock Register +#define MEMCFG_O_DXCOMMIT 0x2U // Dedicated RAM Config Lock Commit Register +#define MEMCFG_O_DXACCPROT0 0x8U // Dedicated RAM Config Register +#define MEMCFG_O_DXTEST 0x10U // Dedicated RAM TEST Register +#define MEMCFG_O_DXINIT 0x12U // Dedicated RAM Init Register +#define MEMCFG_O_DXINITDONE 0x14U // Dedicated RAM InitDone Status Register +#define MEMCFG_O_LSXLOCK 0x20U // Local Shared RAM Config Lock Register +#define MEMCFG_O_LSXCOMMIT 0x22U // Local Shared RAM Config Lock Commit Register +#define MEMCFG_O_LSXMSEL 0x24U // Local Shared RAM Master Sel Register +#define MEMCFG_O_LSXCLAPGM 0x26U // Local Shared RAM Prog/Exe control Register +#define MEMCFG_O_LSXACCPROT0 0x28U // Local Shared RAM Config Register 0 +#define MEMCFG_O_LSXACCPROT1 0x2AU // Local Shared RAM Config Register 1 +#define MEMCFG_O_LSXTEST 0x30U // Local Shared RAM TEST Register +#define MEMCFG_O_LSXINIT 0x32U // Local Shared RAM Init Register +#define MEMCFG_O_LSXINITDONE 0x34U // Local Shared RAM InitDone Status Register +#define MEMCFG_O_GSXLOCK 0x40U // Global Shared RAM Config Lock Register +#define MEMCFG_O_GSXCOMMIT 0x42U // Global Shared RAM Config Lock Commit Register +#define MEMCFG_O_GSXMSEL 0x44U // Global Shared RAM Master Sel Register +#define MEMCFG_O_GSXACCPROT0 0x48U // Global Shared RAM Config Register 0 +#define MEMCFG_O_GSXACCPROT1 0x4AU // Global Shared RAM Config Register 1 +#define MEMCFG_O_GSXACCPROT2 0x4CU // Global Shared RAM Config Register 2 +#define MEMCFG_O_GSXACCPROT3 0x4EU // Global Shared RAM Config Register 3 +#define MEMCFG_O_GSXTEST 0x50U // Global Shared RAM TEST Register +#define MEMCFG_O_GSXINIT 0x52U // Global Shared RAM Init Register +#define MEMCFG_O_GSXINITDONE 0x54U // Global Shared RAM InitDone Status Register +#define MEMCFG_O_MSGXTEST 0x70U // Message RAM TEST Register +#define MEMCFG_O_MSGXINIT 0x72U // Message RAM Init Register +#define MEMCFG_O_MSGXINITDONE 0x74U // Message RAM InitDone Status Register + +#define MEMCFG_O_EMIF1LOCK 0x0U // EMIF1 Config Lock Register +#define MEMCFG_O_EMIF1COMMIT 0x2U // EMIF1 Config Lock Commit Register +#define MEMCFG_O_EMIF1MSEL 0x4U // EMIF1 Master Sel Register +#define MEMCFG_O_EMIF1ACCPROT0 0x8U // EMIF1 Config Register 0 + +#define MEMCFG_O_EMIF2LOCK 0x0U // EMIF2 Config Lock Register +#define MEMCFG_O_EMIF2COMMIT 0x2U // EMIF2 Config Lock Commit Register +#define MEMCFG_O_EMIF2ACCPROT0 0x8U // EMIF2 Config Register 0 + +#define MEMCFG_O_NMAVFLG 0x0U // Non-Master Access Violation Flag Register +#define MEMCFG_O_NMAVSET 0x2U // Non-Master Access Violation Flag Set Register +#define MEMCFG_O_NMAVCLR 0x4U // Non-Master Access Violation Flag Clear Register +#define MEMCFG_O_NMAVINTEN 0x6U // Non-Master Access Violation Interrupt Enable Register +#define MEMCFG_O_NMCPURDAVADDR 0x8U // Non-Master CPU Read Access Violation Address +#define MEMCFG_O_NMCPUWRAVADDR 0xAU // Non-Master CPU Write Access Violation Address +#define MEMCFG_O_NMCPUFAVADDR 0xCU // Non-Master CPU Fetch Access Violation Address +#define MEMCFG_O_NMDMAWRAVADDR 0xEU // Non-Master DMA Write Access Violation Address +#define MEMCFG_O_NMCLA1RDAVADDR 0x10U // Non-Master CLA1 Read Access Violation Address +#define MEMCFG_O_NMCLA1WRAVADDR 0x12U // Non-Master CLA1 Write Access Violation Address +#define MEMCFG_O_NMCLA1FAVADDR 0x14U // Non-Master CLA1 Fetch Access Violation Address +#define MEMCFG_O_MAVFLG 0x20U // Master Access Violation Flag Register +#define MEMCFG_O_MAVSET 0x22U // Master Access Violation Flag Set Register +#define MEMCFG_O_MAVCLR 0x24U // Master Access Violation Flag Clear Register +#define MEMCFG_O_MAVINTEN 0x26U // Master Access Violation Interrupt Enable Register +#define MEMCFG_O_MCPUFAVADDR 0x28U // Master CPU Fetch Access Violation Address +#define MEMCFG_O_MCPUWRAVADDR 0x2AU // Master CPU Write Access Violation Address +#define MEMCFG_O_MDMAWRAVADDR 0x2CU // Master DMA Write Access Violation Address + +#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register +#define MEMCFG_O_UCERRSET 0x2U // Uncorrectable Error Flag Set Register +#define MEMCFG_O_UCERRCLR 0x4U // Uncorrectable Error Flag Clear Register +#define MEMCFG_O_UCCPUREADDR 0x6U // Uncorrectable CPU Read Error Address +#define MEMCFG_O_UCDMAREADDR 0x8U // Uncorrectable DMA Read Error Address +#define MEMCFG_O_UCCLA1READDR 0xAU // Uncorrectable CLA1 Read Error Address +#define MEMCFG_O_CERRFLG 0x20U // Correctable Error Flag Register +#define MEMCFG_O_CERRSET 0x22U // Correctable Error Flag Set Register +#define MEMCFG_O_CERRCLR 0x24U // Correctable Error Flag Clear Register +#define MEMCFG_O_CCPUREADDR 0x26U // Correctable CPU Read Error Address +#define MEMCFG_O_CERRCNT 0x2EU // Correctable Error Count Register +#define MEMCFG_O_CERRTHRES 0x30U // Correctable Error Threshold Value Register +#define MEMCFG_O_CEINTFLG 0x32U // Correctable Error Interrupt Flag Status Register +#define MEMCFG_O_CEINTCLR 0x34U // Correctable Error Interrupt Flag Clear Register +#define MEMCFG_O_CEINTSET 0x36U // Correctable Error Interrupt Flag Set Register +#define MEMCFG_O_CEINTEN 0x38U // Correctable Error Interrupt Enable Register + +#define MEMCFG_O_ROMWAITSTATE 0x0U // ROM Wait State Configuration Register + +#define MEMCFG_O_ROMPREFETCH 0x0U // ROM Prefetch Configuration Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxLOCK register +// +//************************************************************************************************* +#define MEMCFG_DXLOCK_LOCK_D0 0x4U // D0 RAM access protection and master select fields lock + // bit +#define MEMCFG_DXLOCK_LOCK_D1 0x8U // D1 RAM access protection and master select fields lock + // bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_DXCOMMIT_COMMIT_D0 0x4U // D0 RAM access protection and master select permanent + // lock +#define MEMCFG_DXCOMMIT_COMMIT_D1 0x8U // D1 RAM access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_DXACCPROT0_FETCHPROT_D0 0x10000U // Fetch Protection For D0 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D0 0x20000U // CPU WR Protection For D0 RAM +#define MEMCFG_DXACCPROT0_FETCHPROT_D1 0x1000000U // Fetch Protection For D1 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D1 0x2000000U // CPU WR Protection For D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxTEST register +// +//************************************************************************************************* +#define MEMCFG_DXTEST_TEST_M0_S 0U +#define MEMCFG_DXTEST_TEST_M0_M 0x3U // Selects the different modes for M0 RAM +#define MEMCFG_DXTEST_TEST_M1_S 2U +#define MEMCFG_DXTEST_TEST_M1_M 0xCU // Selects the different modes for M1 RAM +#define MEMCFG_DXTEST_TEST_D0_S 4U +#define MEMCFG_DXTEST_TEST_D0_M 0x30U // Selects the different modes for D0 RAM +#define MEMCFG_DXTEST_TEST_D1_S 6U +#define MEMCFG_DXTEST_TEST_D1_M 0xC0U // Selects the different modes for D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINIT register +// +//************************************************************************************************* +#define MEMCFG_DXINIT_INIT_M0 0x1U // RAM Initialization control for M0 RAM. +#define MEMCFG_DXINIT_INIT_M1 0x2U // RAM Initialization control for M1 RAM. +#define MEMCFG_DXINIT_INIT_D0 0x4U // RAM Initialization control for D0 RAM. +#define MEMCFG_DXINIT_INIT_D1 0x8U // RAM Initialization control for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_DXINITDONE_INITDONE_M0 0x1U // RAM Initialization status for M0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_M1 0x2U // RAM Initialization status for M1 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D0 0x4U // RAM Initialization status for D0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D1 0x8U // RAM Initialization status for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_LSXLOCK_LOCK_LS0 0x1U // LS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS1 0x2U // LS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS2 0x4U // LS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS3 0x8U // LS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS4 0x10U // LS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS5 0x20U // LS5 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_LSXCOMMIT_COMMIT_LS0 0x1U // LS0 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS1 0x2U // LS1 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS2 0x4U // LS2 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS3 0x8U // LS3 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS4 0x10U // LS4 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS5 0x20U // LS5 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_LSXMSEL_MSEL_LS0_S 0U +#define MEMCFG_LSXMSEL_MSEL_LS0_M 0x3U // Master Select for LS0 RAM +#define MEMCFG_LSXMSEL_MSEL_LS1_S 2U +#define MEMCFG_LSXMSEL_MSEL_LS1_M 0xCU // Master Select for LS1 RAM +#define MEMCFG_LSXMSEL_MSEL_LS2_S 4U +#define MEMCFG_LSXMSEL_MSEL_LS2_M 0x30U // Master Select for LS2 RAM +#define MEMCFG_LSXMSEL_MSEL_LS3_S 6U +#define MEMCFG_LSXMSEL_MSEL_LS3_M 0xC0U // Master Select for LS3 RAM +#define MEMCFG_LSXMSEL_MSEL_LS4_S 8U +#define MEMCFG_LSXMSEL_MSEL_LS4_M 0x300U // Master Select for LS4 RAM +#define MEMCFG_LSXMSEL_MSEL_LS5_S 10U +#define MEMCFG_LSXMSEL_MSEL_LS5_M 0xC00U // Master Select for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCLAPGM register +// +//************************************************************************************************* +#define MEMCFG_LSXCLAPGM_CLAPGM_LS0 0x1U // Selects LS0 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS1 0x2U // Selects LS1 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS2 0x4U // Selects LS2 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS3 0x8U // Selects LS3 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS4 0x10U // Selects LS4 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS5 0x20U // Selects LS5 RAM as program vs data memory for CLA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS0 0x1U // Fetch Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS0 0x2U // CPU WR Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS1 0x100U // Fetch Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS1 0x200U // CPU WR Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS2 0x10000U // Fetch Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS2 0x20000U // CPU WR Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS3 0x1000000U // Fetch Protection For LS3 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS3 0x2000000U // CPU WR Protection For LS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS4 0x1U // Fetch Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS4 0x2U // CPU WR Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS5 0x100U // Fetch Protection For LS5 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS5 0x200U // CPU WR Protection For LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxTEST register +// +//************************************************************************************************* +#define MEMCFG_LSXTEST_TEST_LS0_S 0U +#define MEMCFG_LSXTEST_TEST_LS0_M 0x3U // Selects the different modes for LS0 RAM +#define MEMCFG_LSXTEST_TEST_LS1_S 2U +#define MEMCFG_LSXTEST_TEST_LS1_M 0xCU // Selects the different modes for LS1 RAM +#define MEMCFG_LSXTEST_TEST_LS2_S 4U +#define MEMCFG_LSXTEST_TEST_LS2_M 0x30U // Selects the different modes for LS2 RAM +#define MEMCFG_LSXTEST_TEST_LS3_S 6U +#define MEMCFG_LSXTEST_TEST_LS3_M 0xC0U // Selects the different modes for LS3 RAM +#define MEMCFG_LSXTEST_TEST_LS4_S 8U +#define MEMCFG_LSXTEST_TEST_LS4_M 0x300U // Selects the different modes for LS4 RAM +#define MEMCFG_LSXTEST_TEST_LS5_S 10U +#define MEMCFG_LSXTEST_TEST_LS5_M 0xC00U // Selects the different modes for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINIT register +// +//************************************************************************************************* +#define MEMCFG_LSXINIT_INIT_LS0 0x1U // RAM Initialization control for LS0 RAM. +#define MEMCFG_LSXINIT_INIT_LS1 0x2U // RAM Initialization control for LS1 RAM. +#define MEMCFG_LSXINIT_INIT_LS2 0x4U // RAM Initialization control for LS2 RAM. +#define MEMCFG_LSXINIT_INIT_LS3 0x8U // RAM Initialization control for LS3 RAM. +#define MEMCFG_LSXINIT_INIT_LS4 0x10U // RAM Initialization control for LS4 RAM. +#define MEMCFG_LSXINIT_INIT_LS5 0x20U // RAM Initialization control for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_LSXINITDONE_INITDONE_LS0 0x1U // RAM Initialization status for LS0 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS1 0x2U // RAM Initialization status for LS1 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS2 0x4U // RAM Initialization status for LS2 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS3 0x8U // RAM Initialization status for LS3 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS4 0x10U // RAM Initialization status for LS4 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS5 0x20U // RAM Initialization status for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_GSXLOCK_LOCK_GS0 0x1U // GS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS1 0x2U // GS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS2 0x4U // GS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS3 0x8U // GS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS4 0x10U // GS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS5 0x20U // GS5 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS6 0x40U // GS6 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS7 0x80U // GS7 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS8 0x100U // GS8 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS9 0x200U // GS9 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS10 0x400U // GS10 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS11 0x800U // GS11 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS12 0x1000U // GS12 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS13 0x2000U // GS13 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS14 0x4000U // GS14 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS15 0x8000U // GS15 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_GSXCOMMIT_COMMIT_GS0 0x1U // GS0 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS1 0x2U // GS1 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS2 0x4U // GS2 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS3 0x8U // GS3 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS4 0x10U // GS4 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS5 0x20U // GS5 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS6 0x40U // GS6 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS7 0x80U // GS7 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS8 0x100U // GS8 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS9 0x200U // GS9 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS10 0x400U // GS10 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS11 0x800U // GS11 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS12 0x1000U // GS12 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS13 0x2000U // GS13 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS14 0x4000U // GS14 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS15 0x8000U // GS15 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_GSXMSEL_MSEL_GS0 0x1U // Master Select for GS0 RAM +#define MEMCFG_GSXMSEL_MSEL_GS1 0x2U // Master Select for GS1 RAM +#define MEMCFG_GSXMSEL_MSEL_GS2 0x4U // Master Select for GS2 RAM +#define MEMCFG_GSXMSEL_MSEL_GS3 0x8U // Master Select for GS3 RAM +#define MEMCFG_GSXMSEL_MSEL_GS4 0x10U // Master Select for GS4 RAM +#define MEMCFG_GSXMSEL_MSEL_GS5 0x20U // Master Select for GS5 RAM +#define MEMCFG_GSXMSEL_MSEL_GS6 0x40U // Master Select for GS6 RAM +#define MEMCFG_GSXMSEL_MSEL_GS7 0x80U // Master Select for GS7 RAM +#define MEMCFG_GSXMSEL_MSEL_GS8 0x100U // Master Select for GS8 RAM +#define MEMCFG_GSXMSEL_MSEL_GS9 0x200U // Master Select for GS9 RAM +#define MEMCFG_GSXMSEL_MSEL_GS10 0x400U // Master Select for GS10 RAM +#define MEMCFG_GSXMSEL_MSEL_GS11 0x800U // Master Select for GS11 RAM +#define MEMCFG_GSXMSEL_MSEL_GS12 0x1000U // Master Select for GS12 RAM +#define MEMCFG_GSXMSEL_MSEL_GS13 0x2000U // Master Select for GS13 RAM +#define MEMCFG_GSXMSEL_MSEL_GS14 0x4000U // Master Select for GS14 RAM +#define MEMCFG_GSXMSEL_MSEL_GS15 0x8000U // Master Select for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS0 0x1U // Fetch Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 0x2U // CPU WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS0 0x4U // DMA WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS1 0x100U // Fetch Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS1 0x200U // CPU WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS1 0x400U // DMA WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS2 0x10000U // Fetch Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS2 0x20000U // CPU WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS2 0x40000U // DMA WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS3 0x1000000U // Fetch Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS3 0x2000000U // CPU WR Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS3 0x4000000U // DMA WR Protection For GS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS4 0x1U // Fetch Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS4 0x2U // CPU WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS4 0x4U // DMA WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS5 0x100U // Fetch Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS5 0x200U // CPU WR Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS5 0x400U // DMA WR Protection For GS5RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS6 0x10000U // Fetch Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS6 0x20000U // CPU WR Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS6 0x40000U // DMA WR Protection For GS6RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS7 0x1000000U // Fetch Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS7 0x2000000U // CPU WR Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS7 0x4000000U // DMA WR Protection For GS7RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT2 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS8 0x1U // Fetch Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS8 0x2U // CPU WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS8 0x4U // DMA WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS9 0x100U // Fetch Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS9 0x200U // CPU WR Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS9 0x400U // DMA WR Protection For GS9RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS10 0x10000U // Fetch Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS10 0x20000U // CPU WR Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS10 0x40000U // DMA WR Protection For GS10RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS11 0x1000000U // Fetch Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS11 0x2000000U // CPU WR Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS11 0x4000000U // DMA WR Protection For GS11RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT3 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS12 0x1U // Fetch Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS12 0x2U // CPU WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS12 0x4U // DMA WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS13 0x100U // Fetch Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS13 0x200U // CPU WR Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS13 0x400U // DMA WR Protection For GS13RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS14 0x10000U // Fetch Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS14 0x20000U // CPU WR Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS14 0x40000U // DMA WR Protection For GS14RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS15 0x1000000U // Fetch Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS15 0x2000000U // CPU WR Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS15 0x4000000U // DMA WR Protection For GS15RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxTEST register +// +//************************************************************************************************* +#define MEMCFG_GSXTEST_TEST_GS0_S 0U +#define MEMCFG_GSXTEST_TEST_GS0_M 0x3U // Selects the different modes for GS0 RAM +#define MEMCFG_GSXTEST_TEST_GS1_S 2U +#define MEMCFG_GSXTEST_TEST_GS1_M 0xCU // Selects the different modes for GS1 RAM +#define MEMCFG_GSXTEST_TEST_GS2_S 4U +#define MEMCFG_GSXTEST_TEST_GS2_M 0x30U // Selects the different modes for GS2 RAM +#define MEMCFG_GSXTEST_TEST_GS3_S 6U +#define MEMCFG_GSXTEST_TEST_GS3_M 0xC0U // Selects the different modes for GS3 RAM +#define MEMCFG_GSXTEST_TEST_GS4_S 8U +#define MEMCFG_GSXTEST_TEST_GS4_M 0x300U // Selects the different modes for GS4 RAM +#define MEMCFG_GSXTEST_TEST_GS5_S 10U +#define MEMCFG_GSXTEST_TEST_GS5_M 0xC00U // Selects the different modes for GS5 RAM +#define MEMCFG_GSXTEST_TEST_GS6_S 12U +#define MEMCFG_GSXTEST_TEST_GS6_M 0x3000U // Selects the different modes for GS6 RAM +#define MEMCFG_GSXTEST_TEST_GS7_S 14U +#define MEMCFG_GSXTEST_TEST_GS7_M 0xC000U // Selects the different modes for GS7 RAM +#define MEMCFG_GSXTEST_TEST_GS8_S 16U +#define MEMCFG_GSXTEST_TEST_GS8_M 0x30000U // Selects the different modes for GS8 RAM +#define MEMCFG_GSXTEST_TEST_GS9_S 18U +#define MEMCFG_GSXTEST_TEST_GS9_M 0xC0000U // Selects the different modes for GS9 RAM +#define MEMCFG_GSXTEST_TEST_GS10_S 20U +#define MEMCFG_GSXTEST_TEST_GS10_M 0x300000U // Selects the different modes for GS10 RAM +#define MEMCFG_GSXTEST_TEST_GS11_S 22U +#define MEMCFG_GSXTEST_TEST_GS11_M 0xC00000U // Selects the different modes for GS11 RAM +#define MEMCFG_GSXTEST_TEST_GS12_S 24U +#define MEMCFG_GSXTEST_TEST_GS12_M 0x3000000U // Selects the different modes for GS12 RAM +#define MEMCFG_GSXTEST_TEST_GS13_S 26U +#define MEMCFG_GSXTEST_TEST_GS13_M 0xC000000U // Selects the different modes for GS13 RAM +#define MEMCFG_GSXTEST_TEST_GS14_S 28U +#define MEMCFG_GSXTEST_TEST_GS14_M 0x30000000U // Selects the different modes for GS14 RAM +#define MEMCFG_GSXTEST_TEST_GS15_S 30U +#define MEMCFG_GSXTEST_TEST_GS15_M 0xC0000000U // Selects the different modes for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINIT register +// +//************************************************************************************************* +#define MEMCFG_GSXINIT_INIT_GS0 0x1U // RAM Initialization control for GS0 RAM. +#define MEMCFG_GSXINIT_INIT_GS1 0x2U // RAM Initialization control for GS1 RAM. +#define MEMCFG_GSXINIT_INIT_GS2 0x4U // RAM Initialization control for GS2 RAM. +#define MEMCFG_GSXINIT_INIT_GS3 0x8U // RAM Initialization control for GS3 RAM. +#define MEMCFG_GSXINIT_INIT_GS4 0x10U // RAM Initialization control for GS4 RAM. +#define MEMCFG_GSXINIT_INIT_GS5 0x20U // RAM Initialization control for GS5 RAM. +#define MEMCFG_GSXINIT_INIT_GS6 0x40U // RAM Initialization control for GS6 RAM. +#define MEMCFG_GSXINIT_INIT_GS7 0x80U // RAM Initialization control for GS7 RAM. +#define MEMCFG_GSXINIT_INIT_GS8 0x100U // RAM Initialization control for GS8 RAM. +#define MEMCFG_GSXINIT_INIT_GS9 0x200U // RAM Initialization control for GS9 RAM. +#define MEMCFG_GSXINIT_INIT_GS10 0x400U // RAM Initialization control for GS10 RAM. +#define MEMCFG_GSXINIT_INIT_GS11 0x800U // RAM Initialization control for GS11 RAM. +#define MEMCFG_GSXINIT_INIT_GS12 0x1000U // RAM Initialization control for GS12 RAM. +#define MEMCFG_GSXINIT_INIT_GS13 0x2000U // RAM Initialization control for GS13 RAM. +#define MEMCFG_GSXINIT_INIT_GS14 0x4000U // RAM Initialization control for GS14 RAM. +#define MEMCFG_GSXINIT_INIT_GS15 0x8000U // RAM Initialization control for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_GSXINITDONE_INITDONE_GS0 0x1U // RAM Initialization status for GS0 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS1 0x2U // RAM Initialization status for GS1 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS2 0x4U // RAM Initialization status for GS2 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS3 0x8U // RAM Initialization status for GS3 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS4 0x10U // RAM Initialization status for GS4 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS5 0x20U // RAM Initialization status for GS5 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS6 0x40U // RAM Initialization status for GS6 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS7 0x80U // RAM Initialization status for GS7 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS8 0x100U // RAM Initialization status for GS8 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS9 0x200U // RAM Initialization status for GS9 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS10 0x400U // RAM Initialization status for GS10 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS11 0x800U // RAM Initialization status for GS11 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS12 0x1000U // RAM Initialization status for GS12 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS13 0x2000U // RAM Initialization status for GS13 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS14 0x4000U // RAM Initialization status for GS14 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS15 0x8000U // RAM Initialization status for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxTEST register +// +//************************************************************************************************* +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_S 0U +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_M 0x3U // CPU to CPU Mode Select +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_S 2U +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_M 0xCU // CPU to CLA1 MSG RAM Mode Select +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_S 4U +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_M 0x30U // CLA1 to CPU MSG RAM Mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINIT register +// +//************************************************************************************************* +#define MEMCFG_MSGXINIT_INIT_CPUTOCPU 0x1U // Initialization control for CPU to CPU MSG RAM +#define MEMCFG_MSGXINIT_INIT_CPUTOCLA1 0x2U // Initialization control for CPUTOCLA1 MSG RAM +#define MEMCFG_MSGXINIT_INIT_CLA1TOCPU 0x4U // Initialization control for CLA1TOCPU MSG RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCPU 0x1U // Initialization status for CPU to CPU MSG + // RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCLA1 0x2U // Initialization status for CPU to CLA1 + // MSG RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CLA1TOCPU 0x4U // Initialization status for CLA1 to CPU + // MSG RAM + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF1LOCK_LOCK_EMIF1 0x1U // EMIF1 access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF1COMMIT_COMMIT_EMIF1 0x1U // EMIF1 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1MSEL register +// +//************************************************************************************************* +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_S 0U +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_M 0x3U // Master Select for EMIF1. +#define MEMCFG_EMIF1MSEL_KEY_S 4U +#define MEMCFG_EMIF1MSEL_KEY_M 0xFFFFFFF0U // KEY to enable the write into MSEL_EMIF1 + // bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 0x1U // Fetch Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 0x2U // CPU WR Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 0x4U // DMA WR Protection For EMIF1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF2LOCK_LOCK_EMIF2 0x1U // EMIF2 access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF2COMMIT_COMMIT_EMIF2 0x1U // EMIF2 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 0x1U // Fetch Protection For EMIF2 +#define MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2 0x2U // CPU WR Protection For EMIF2 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVFLG register +// +//************************************************************************************************* +#define MEMCFG_NMAVFLG_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag +#define MEMCFG_NMAVFLG_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag +#define MEMCFG_NMAVFLG_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag +#define MEMCFG_NMAVFLG_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVSET register +// +//************************************************************************************************* +#define MEMCFG_NMAVSET_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Set +#define MEMCFG_NMAVSET_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVCLR register +// +//************************************************************************************************* +#define MEMCFG_NMAVCLR_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_NMAVCLR_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_NMAVINTEN_CPUREAD 0x1U // Non Master CPU Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUWRITE 0x2U // Non Master CPU Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_DMAWRITE 0x8U // Non Master DMA Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVFLG register +// +//************************************************************************************************* +#define MEMCFG_MAVFLG_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag +#define MEMCFG_MAVFLG_CPUWRITE 0x2U // Master CPU Write Access Violation Flag +#define MEMCFG_MAVFLG_DMAWRITE 0x4U // Master DMA Write Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVSET register +// +//************************************************************************************************* +#define MEMCFG_MAVSET_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Set +#define MEMCFG_MAVSET_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Set +#define MEMCFG_MAVSET_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVCLR register +// +//************************************************************************************************* +#define MEMCFG_MAVCLR_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_MAVCLR_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Clear +#define MEMCFG_MAVCLR_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_MAVINTEN_CPUFETCH 0x1U // Master CPU Fetch Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_CPUWRITE 0x2U // Master CPU Write Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_DMAWRITE 0x4U // Master DMA Write Access Violation Interrupt Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRFLG register +// +//************************************************************************************************* +#define MEMCFG_UCERRFLG_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRSET register +// +//************************************************************************************************* +#define MEMCFG_UCERRSET_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRCLR register +// +//************************************************************************************************* +#define MEMCFG_UCERRCLR_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRFLG register +// +//************************************************************************************************* +#define MEMCFG_CERRFLG_CPURDERR 0x1U // CPU Correctable Read Error Flag +#define MEMCFG_CERRFLG_DMARDERR 0x2U // DMA Correctable Read Error Flag +#define MEMCFG_CERRFLG_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRSET register +// +//************************************************************************************************* +#define MEMCFG_CERRSET_CPURDERR 0x1U // CPU Correctable Read Error Flag Set +#define MEMCFG_CERRSET_DMARDERR 0x2U // DMA Correctable Read Error Flag Set +#define MEMCFG_CERRSET_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRCLR register +// +//************************************************************************************************* +#define MEMCFG_CERRCLR_CPURDERR 0x1U // CPU Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_DMARDERR 0x2U // DMA Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTFLG register +// +//************************************************************************************************* +#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTCLR register +// +//************************************************************************************************* +#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // CPU Corrected Error Threshold Exceeded Error Clear. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTSET register +// +//************************************************************************************************* +#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTEN register +// +//************************************************************************************************* +#define MEMCFG_CEINTEN_CEINTEN 0x1U // CPU/DMA Correctable Error Interrupt Enable. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMWAITSTATE register +// +//************************************************************************************************* +#define MEMCFG_ROMWAITSTATE_WSDISABLE 0x1U // C28x ROM Wait State Enable/Disable Control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMPREFETCH register +// +//************************************************************************************************* +#define MEMCFG_ROMPREFETCH_PFENABLE 0x1U // ROM Prefetch Enable/Disable Control + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_memmap.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_memmap.h new file mode 100644 index 0000000..ba0b5e5 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_memmap.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_memmap.h +// +// TITLE: Macros defining the memory map of the C28x. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMMAP_H +#define HW_MEMMAP_H + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define M0_RAM_BASE 0x00000000U +#define M1_RAM_BASE 0x00000400U +#define ADCARESULT_BASE 0x00000B00U +#define ADCBRESULT_BASE 0x00000B20U +#define ADCCRESULT_BASE 0x00000B40U +#define ADCDRESULT_BASE 0x00000B60U +#define CPUTIMER0_BASE 0x00000C00U +#define CPUTIMER1_BASE 0x00000C08U +#define CPUTIMER2_BASE 0x00000C10U +#define CLA1_SOFTINT_BASE 0x00000CE0U +#define PIECTRL_BASE 0x00000CE0U +#define PIEVECTTABLE_BASE 0x00000D00U +#define DMA_BASE 0x00001000U +#define DMA_CH1_BASE 0x00001020U +#define DMA_CH2_BASE 0x00001040U +#define DMA_CH3_BASE 0x00001060U +#define DMA_CH4_BASE 0x00001080U +#define DMA_CH5_BASE 0x000010A0U +#define DMA_CH6_BASE 0x000010C0U +#define CLA1_BASE 0x00001400U +#define CLATOCPU_RAM_BASE 0x00001480U +#define CPUTOCLA_RAM_BASE 0x00001500U +#define CLB1_BASE 0x00003000U +#define CLB1_LOGICCFG_BASE 0x00003000U +#define CLB1_LOGICCTL_BASE 0x00003100U +#define CLB1_DATAEXCH_BASE 0x00003200U +#define CLB2_BASE 0x00003400U +#define CLB2_LOGICCFG_BASE 0x00003400U +#define CLB2_LOGICCTL_BASE 0x00003500U +#define CLB2_DATAEXCH_BASE 0x00003600U +#define CLB3_BASE 0x00003800U +#define CLB3_LOGICCFG_BASE 0x00003800U +#define CLB3_LOGICCTL_BASE 0x00003900U +#define CLB3_DATAEXCH_BASE 0x00003A00U +#define CLB4_BASE 0x00003C00U +#define CLB4_LOGICCFG_BASE 0x00003C00U +#define CLB4_LOGICCTL_BASE 0x00003D00U +#define CLB4_DATAEXCH_BASE 0x00003E00U +#define EPWM1_BASE 0x00004000U +#define EPWM2_BASE 0x00004100U +#define EPWM3_BASE 0x00004200U +#define EPWM4_BASE 0x00004300U +#define EPWM5_BASE 0x00004400U +#define EPWM6_BASE 0x00004500U +#define EPWM7_BASE 0x00004600U +#define EPWM8_BASE 0x00004700U +#define EPWM9_BASE 0x00004800U +#define EPWM10_BASE 0x00004900U +#define EPWM11_BASE 0x00004A00U +#define EPWM12_BASE 0x00004B00U +#define ECAP1_BASE 0x00005000U +#define ECAP2_BASE 0x00005020U +#define ECAP3_BASE 0x00005040U +#define ECAP4_BASE 0x00005060U +#define ECAP5_BASE 0x00005080U +#define ECAP6_BASE 0x000050A0U +#define EQEP1_BASE 0x00005100U +#define EQEP2_BASE 0x00005140U +#define EQEP3_BASE 0x00005180U +#define DACA_BASE 0x00005C00U +#define DACB_BASE 0x00005C10U +#define DACC_BASE 0x00005C20U +#define CMPSS1_BASE 0x00005C80U +#define CMPSS2_BASE 0x00005CA0U +#define CMPSS3_BASE 0x00005CC0U +#define CMPSS4_BASE 0x00005CE0U +#define CMPSS5_BASE 0x00005D00U +#define CMPSS6_BASE 0x00005D20U +#define CMPSS7_BASE 0x00005D40U +#define CMPSS8_BASE 0x00005D60U +#define SDFM1_BASE 0x00005E00U +#define SDFM2_BASE 0x00005E80U +#define MCBSPA_BASE 0x00006000U +#define MCBSPB_BASE 0x00006040U +#define SPIA_BASE 0x00006100U +#define SPIB_BASE 0x00006110U +#define SPIC_BASE 0x00006120U +#define UPP_BASE 0x00006200U +#define UPP_TX_MSG_RAM_BASE 0x00006C00U +#define UPP_RX_MSG_RAM_BASE 0x00006E00U +#define WD_BASE 0x00007000U +#define NMI_BASE 0x00007060U +#define XINT_BASE 0x00007070U +#define SCIA_BASE 0x00007200U +#define SCIB_BASE 0x00007210U +#define SCIC_BASE 0x00007220U +#define SCID_BASE 0x00007230U +#define I2CA_BASE 0x00007300U +#define I2CB_BASE 0x00007340U +#define ADCA_BASE 0x00007400U +#define ADCB_BASE 0x00007480U +#define ADCC_BASE 0x00007500U +#define ADCD_BASE 0x00007580U +#define INPUTXBAR_BASE 0x00007900U +#define XBAR_BASE 0x00007920U +#define SYNCSOC_BASE 0x00007940U +#define DMACLASRCSEL_BASE 0x00007980U +#define EPWMXBAR_BASE 0x00007A00U +#define CLBXBAR_BASE 0x00007A40U +#define OUTPUTXBAR_BASE 0x00007A80U +#define GPIOCTRL_BASE 0x00007C00U +#define GPIODATA_BASE 0x00007F00U +#define LS0_RAM_BASE 0x00008000U +#define LS1_RAM_BASE 0x00008800U +#define LS2_RAM_BASE 0x00009000U +#define LS3_RAM_BASE 0x00009800U +#define LS4_RAM_BASE 0x0000A000U +#define LS5_RAM_BASE 0x0000A800U +#define D0_RAM_BASE 0x0000B000U +#define D1_RAM_BASE 0x0000B800U +#define GS0_RAM_BASE 0x0000C000U +#define GS1_RAM_BASE 0x0000D000U +#define GS2_RAM_BASE 0x0000E000U +#define GS3_RAM_BASE 0x0000F000U +#define GS4_RAM_BASE 0x00010000U +#define GS5_RAM_BASE 0x00011000U +#define GS6_RAM_BASE 0x00012000U +#define GS7_RAM_BASE 0x00013000U +#define GS8_RAM_BASE 0x00014000U +#define GS9_RAM_BASE 0x00015000U +#define GS10_RAM_BASE 0x00016000U +#define GS11_RAM_BASE 0x00017000U +#define GS12_RAM_BASE 0x00018000U +#define GS13_RAM_BASE 0x00019000U +#define GS14_RAM_BASE 0x0001A000U +#define GS15_RAM_BASE 0x0001B000U +#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U +#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U +#define USBA_BASE 0x00040000U +#define EMIF1_BASE 0x00047000U +#define EMIF2_BASE 0x00047800U +#define CANA_BASE 0x00048000U +#define CANA_MSG_RAM_BASE 0x00049000U +#define CANB_BASE 0x0004A000U +#define CANB_MSG_RAM_BASE 0x0004B000U +#define IPC_BASE 0x00050000U +#define FLASHPUMPSEMAPHORE_BASE 0x00050024U +#define DEVCFG_BASE 0x0005D000U +#define ANALOGSUBSYS_BASE 0x0005D180U +#define CLKCFG_BASE 0x0005D200U +#define CPUSYS_BASE 0x0005D300U +#define ROMPREFETCH_BASE 0x0005E608U +#define DCSM_Z1_BASE 0x0005F000U +#define DCSM_Z2_BASE 0x0005F040U +#define DCSMCOMMON_BASE 0x0005F070U +#define MEMCFG_BASE 0x0005F400U +#define EMIF1CONFIG_BASE 0x0005F480U +#define EMIF2CONFIG_BASE 0x0005F4A0U +#define ACCESSPROTECTION_BASE 0x0005F4C0U +#define MEMORYERROR_BASE 0x0005F500U +#define ROMWAITSTATE_BASE 0x0005F540U +#define FLASH0CTRL_BASE 0x0005F800U +#define FLASH0ECC_BASE 0x0005FB00U +#define DCSM_Z1OTP_BASE 0x00078000U +#define DCSM_Z2OTP_BASE 0x00078200U +#define UID_BASE 0x000703C0U +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_nmi.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_nmi.h new file mode 100644 index 0000000..efd8157 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_nmi.h @@ -0,0 +1,134 @@ +//########################################################################### +// +// FILE: hw_nmi.h +// +// TITLE: Definitions for the NMI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_NMI_H +#define HW_NMI_H + +//************************************************************************************************* +// +// The following are defines for the NMI register offsets +// +//************************************************************************************************* +#define NMI_O_CFG 0x0U // NMI Configuration Register +#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear) +#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register +#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register +#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register +#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register +#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMICFG register +// +//************************************************************************************************* +#define NMI_CFG_NMIE 0x1U // Global NMI Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLG register +// +//************************************************************************************************* +#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag +#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag +#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag +#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag +#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag +#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag +#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag +#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag +#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag +#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGCLR register +// +//************************************************************************************************* +#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear +#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear +#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear +#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear +#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear +#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear +#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear +#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear +#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear +#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear +#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGFRC register +// +//************************************************************************************************* +#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force +#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force +#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force +#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force +#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force +#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force +#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force +#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force +#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force +#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMISHDFLG register +// +//************************************************************************************************* +#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag +#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag +#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag +#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag +#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag +#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag +#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag +#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag +#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag +#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_otp.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_otp.h new file mode 100644 index 0000000..d074499 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_otp.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: hw_otp.h +// +// TITLE: Definitions for the OTP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OTP_H +#define HW_OTP_H + +//************************************************************************************************* +// +// The following are defines for the OTP register offsets +// +//************************************************************************************************* +#define OTP_O_UID_PSRAND0 0x0U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND1 0x2U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND2 0x4U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND3 0x6U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND4 0x8U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND5 0xAU // UID Psuedo-random 160 bit number +#define OTP_O_UID_UNIQUE 0xCU // UID UID Unique 32 bit number +#define OTP_O_UID_CHECKSUM 0xEU // UID Checksum + + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_outputxbar.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_outputxbar.h new file mode 100644 index 0000000..30a10e9 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_outputxbar.h @@ -0,0 +1,1340 @@ +//########################################################################### +// +// FILE: hw_outputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OUTPUTXBAR_H +#define HW_OUTPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_OUTPUT1MUX0TO15CFG 0x0U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT1MUX16TO31CFG 0x2U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT2MUX0TO15CFG 0x4U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT2MUX16TO31CFG 0x6U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT3MUX0TO15CFG 0x8U // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT3MUX16TO31CFG 0xAU // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT4MUX0TO15CFG 0xCU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT4MUX16TO31CFG 0xEU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT5MUX0TO15CFG 0x10U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT5MUX16TO31CFG 0x12U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT6MUX0TO15CFG 0x14U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT6MUX16TO31CFG 0x16U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT7MUX0TO15CFG 0x18U // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT7MUX16TO31CFG 0x1AU // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT8MUX0TO15CFG 0x1CU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT8MUX16TO31CFG 0x1EU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT1MUXENABLE 0x20U // Output X-BAR Mux Enable for Output 1 +#define XBAR_O_OUTPUT2MUXENABLE 0x22U // Output X-BAR Mux Enable for Output 2 +#define XBAR_O_OUTPUT3MUXENABLE 0x24U // Output X-BAR Mux Enable for Output 3 +#define XBAR_O_OUTPUT4MUXENABLE 0x26U // Output X-BAR Mux Enable for Output 4 +#define XBAR_O_OUTPUT5MUXENABLE 0x28U // Output X-BAR Mux Enable for Output 5 +#define XBAR_O_OUTPUT6MUXENABLE 0x2AU // Output X-BAR Mux Enable for Output 6 +#define XBAR_O_OUTPUT7MUXENABLE 0x2CU // Output X-BAR Mux Enable for Output 7 +#define XBAR_O_OUTPUT8MUXENABLE 0x2EU // Output X-BAR Mux Enable for Output 8 +#define XBAR_O_OUTPUTLATCH 0x30U // Output X-BAR Output Latch +#define XBAR_O_OUTPUTLATCHCLR 0x32U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHFRC 0x34U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHENABLE 0x36U // Output X-BAR Output Latch Enable +#define XBAR_O_OUTPUTINV 0x38U // Output X-BAR Output Inversion +#define XBAR_O_OUTPUTLOCK 0x3EU // Output X-BAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT1 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT2 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT3 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT4 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT5 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT6 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT7 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCH register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCH_OUTPUT1 0x1U // Records the OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT2 0x2U // Records the OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT3 0x4U // Records the OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT4 0x8U // Records the OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT5 0x10U // Records the OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT6 0x20U // Records the OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT7 0x40U // Records the OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT8 0x80U // Records the OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHCLR register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHCLR_OUTPUT1 0x1U // Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT2 0x2U // Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT3 0x4U // Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT4 0x8U // Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT5 0x10U // Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT6 0x20U // Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT7 0x40U // Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT8 0x80U // Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHFRC register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHFRC_OUTPUT1 0x1U // Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT2 0x2U // Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT3 0x4U // Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT4 0x8U // Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT5 0x10U // Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT6 0x20U // Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT7 0x40U // Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT8 0x80U // Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHENABLE_OUTPUT1 0x1U // Selects the output latch to drive OUTPUT1 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT2 0x2U // Selects the output latch to drive OUTPUT2 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT3 0x4U // Selects the output latch to drive OUTPUT3 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT4 0x8U // Selects the output latch to drive OUTPUT4 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT5 0x10U // Selects the output latch to drive OUTPUT5 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT6 0x20U // Selects the output latch to drive OUTPUT6 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT7 0x40U // Selects the output latch to drive OUTPUT7 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT8 0x80U // Selects the output latch to drive OUTPUT8 for + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTINV register +// +//************************************************************************************************* +#define XBAR_OUTPUTINV_OUTPUT1 0x1U // Selects polarity for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT2 0x2U // Selects polarity for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT3 0x4U // Selects polarity for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT4 0x8U // Selects polarity for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT5 0x10U // Selects polarity for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT6 0x20U // Selects polarity for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT7 0x40U // Selects polarity for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT8 0x80U // Selects polarity for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLOCK register +// +//************************************************************************************************* +#define XBAR_OUTPUTLOCK_LOCK 0x1U // Locks the configuration for OUTPUT-XBAR +#define XBAR_OUTPUTLOCK_KEY_S 16U +#define XBAR_OUTPUTLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_pie.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_pie.h new file mode 100644 index 0000000..9a4f09f --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_pie.h @@ -0,0 +1,636 @@ +//########################################################################### +// +// FILE: hw_pie.h +// +// TITLE: Definitions for the PIE registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_PIE_H +#define HW_PIE_H + +//************************************************************************************************* +// +// The following are defines for the PIE register offsets +// +//************************************************************************************************* +#define PIE_O_CTRL 0x0U // ePIE Control Register +#define PIE_O_ACK 0x1U // Interrupt Acknowledge Register +#define PIE_O_IER1 0x2U // Interrupt Group 1 Enable Register +#define PIE_O_IFR1 0x3U // Interrupt Group 1 Flag Register +#define PIE_O_IER2 0x4U // Interrupt Group 2 Enable Register +#define PIE_O_IFR2 0x5U // Interrupt Group 2 Flag Register +#define PIE_O_IER3 0x6U // Interrupt Group 3 Enable Register +#define PIE_O_IFR3 0x7U // Interrupt Group 3 Flag Register +#define PIE_O_IER4 0x8U // Interrupt Group 4 Enable Register +#define PIE_O_IFR4 0x9U // Interrupt Group 4 Flag Register +#define PIE_O_IER5 0xAU // Interrupt Group 5 Enable Register +#define PIE_O_IFR5 0xBU // Interrupt Group 5 Flag Register +#define PIE_O_IER6 0xCU // Interrupt Group 6 Enable Register +#define PIE_O_IFR6 0xDU // Interrupt Group 6 Flag Register +#define PIE_O_IER7 0xEU // Interrupt Group 7 Enable Register +#define PIE_O_IFR7 0xFU // Interrupt Group 7 Flag Register +#define PIE_O_IER8 0x10U // Interrupt Group 8 Enable Register +#define PIE_O_IFR8 0x11U // Interrupt Group 8 Flag Register +#define PIE_O_IER9 0x12U // Interrupt Group 9 Enable Register +#define PIE_O_IFR9 0x13U // Interrupt Group 9 Flag Register +#define PIE_O_IER10 0x14U // Interrupt Group 10 Enable Register +#define PIE_O_IFR10 0x15U // Interrupt Group 10 Flag Register +#define PIE_O_IER11 0x16U // Interrupt Group 11 Enable Register +#define PIE_O_IFR11 0x17U // Interrupt Group 11 Flag Register +#define PIE_O_IER12 0x18U // Interrupt Group 12 Enable Register +#define PIE_O_IFR12 0x19U // Interrupt Group 12 Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIECTRL register +// +//************************************************************************************************* +#define PIE_CTRL_ENPIE 0x1U // PIE Enable +#define PIE_CTRL_PIEVECT_S 1U +#define PIE_CTRL_PIEVECT_M 0xFFFEU // PIE Vector Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEACK register +// +//************************************************************************************************* +#define PIE_ACK_ACK1 0x1U // Acknowledge PIE Interrupt Group 1 +#define PIE_ACK_ACK2 0x2U // Acknowledge PIE Interrupt Group 2 +#define PIE_ACK_ACK3 0x4U // Acknowledge PIE Interrupt Group 3 +#define PIE_ACK_ACK4 0x8U // Acknowledge PIE Interrupt Group 4 +#define PIE_ACK_ACK5 0x10U // Acknowledge PIE Interrupt Group 5 +#define PIE_ACK_ACK6 0x20U // Acknowledge PIE Interrupt Group 6 +#define PIE_ACK_ACK7 0x40U // Acknowledge PIE Interrupt Group 7 +#define PIE_ACK_ACK8 0x80U // Acknowledge PIE Interrupt Group 8 +#define PIE_ACK_ACK9 0x100U // Acknowledge PIE Interrupt Group 9 +#define PIE_ACK_ACK10 0x200U // Acknowledge PIE Interrupt Group 10 +#define PIE_ACK_ACK11 0x400U // Acknowledge PIE Interrupt Group 11 +#define PIE_ACK_ACK12 0x800U // Acknowledge PIE Interrupt Group 12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER1 register +// +//************************************************************************************************* +#define PIE_IER1_INTX1 0x1U // Enable for Interrupt 1.1 +#define PIE_IER1_INTX2 0x2U // Enable for Interrupt 1.2 +#define PIE_IER1_INTX3 0x4U // Enable for Interrupt 1.3 +#define PIE_IER1_INTX4 0x8U // Enable for Interrupt 1.4 +#define PIE_IER1_INTX5 0x10U // Enable for Interrupt 1.5 +#define PIE_IER1_INTX6 0x20U // Enable for Interrupt 1.6 +#define PIE_IER1_INTX7 0x40U // Enable for Interrupt 1.7 +#define PIE_IER1_INTX8 0x80U // Enable for Interrupt 1.8 +#define PIE_IER1_INTX9 0x100U // Enable for Interrupt 1.9 +#define PIE_IER1_INTX10 0x200U // Enable for Interrupt 1.10 +#define PIE_IER1_INTX11 0x400U // Enable for Interrupt 1.11 +#define PIE_IER1_INTX12 0x800U // Enable for Interrupt 1.12 +#define PIE_IER1_INTX13 0x1000U // Enable for Interrupt 1.13 +#define PIE_IER1_INTX14 0x2000U // Enable for Interrupt 1.14 +#define PIE_IER1_INTX15 0x4000U // Enable for Interrupt 1.15 +#define PIE_IER1_INTX16 0x8000U // Enable for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR1 register +// +//************************************************************************************************* +#define PIE_IFR1_INTX1 0x1U // Flag for Interrupt 1.1 +#define PIE_IFR1_INTX2 0x2U // Flag for Interrupt 1.2 +#define PIE_IFR1_INTX3 0x4U // Flag for Interrupt 1.3 +#define PIE_IFR1_INTX4 0x8U // Flag for Interrupt 1.4 +#define PIE_IFR1_INTX5 0x10U // Flag for Interrupt 1.5 +#define PIE_IFR1_INTX6 0x20U // Flag for Interrupt 1.6 +#define PIE_IFR1_INTX7 0x40U // Flag for Interrupt 1.7 +#define PIE_IFR1_INTX8 0x80U // Flag for Interrupt 1.8 +#define PIE_IFR1_INTX9 0x100U // Flag for Interrupt 1.9 +#define PIE_IFR1_INTX10 0x200U // Flag for Interrupt 1.10 +#define PIE_IFR1_INTX11 0x400U // Flag for Interrupt 1.11 +#define PIE_IFR1_INTX12 0x800U // Flag for Interrupt 1.12 +#define PIE_IFR1_INTX13 0x1000U // Flag for Interrupt 1.13 +#define PIE_IFR1_INTX14 0x2000U // Flag for Interrupt 1.14 +#define PIE_IFR1_INTX15 0x4000U // Flag for Interrupt 1.15 +#define PIE_IFR1_INTX16 0x8000U // Flag for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER2 register +// +//************************************************************************************************* +#define PIE_IER2_INTX1 0x1U // Enable for Interrupt 2.1 +#define PIE_IER2_INTX2 0x2U // Enable for Interrupt 2.2 +#define PIE_IER2_INTX3 0x4U // Enable for Interrupt 2.3 +#define PIE_IER2_INTX4 0x8U // Enable for Interrupt 2.4 +#define PIE_IER2_INTX5 0x10U // Enable for Interrupt 2.5 +#define PIE_IER2_INTX6 0x20U // Enable for Interrupt 2.6 +#define PIE_IER2_INTX7 0x40U // Enable for Interrupt 2.7 +#define PIE_IER2_INTX8 0x80U // Enable for Interrupt 2.8 +#define PIE_IER2_INTX9 0x100U // Enable for Interrupt 2.9 +#define PIE_IER2_INTX10 0x200U // Enable for Interrupt 2.10 +#define PIE_IER2_INTX11 0x400U // Enable for Interrupt 2.11 +#define PIE_IER2_INTX12 0x800U // Enable for Interrupt 2.12 +#define PIE_IER2_INTX13 0x1000U // Enable for Interrupt 2.13 +#define PIE_IER2_INTX14 0x2000U // Enable for Interrupt 2.14 +#define PIE_IER2_INTX15 0x4000U // Enable for Interrupt 2.15 +#define PIE_IER2_INTX16 0x8000U // Enable for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR2 register +// +//************************************************************************************************* +#define PIE_IFR2_INTX1 0x1U // Flag for Interrupt 2.1 +#define PIE_IFR2_INTX2 0x2U // Flag for Interrupt 2.2 +#define PIE_IFR2_INTX3 0x4U // Flag for Interrupt 2.3 +#define PIE_IFR2_INTX4 0x8U // Flag for Interrupt 2.4 +#define PIE_IFR2_INTX5 0x10U // Flag for Interrupt 2.5 +#define PIE_IFR2_INTX6 0x20U // Flag for Interrupt 2.6 +#define PIE_IFR2_INTX7 0x40U // Flag for Interrupt 2.7 +#define PIE_IFR2_INTX8 0x80U // Flag for Interrupt 2.8 +#define PIE_IFR2_INTX9 0x100U // Flag for Interrupt 2.9 +#define PIE_IFR2_INTX10 0x200U // Flag for Interrupt 2.10 +#define PIE_IFR2_INTX11 0x400U // Flag for Interrupt 2.11 +#define PIE_IFR2_INTX12 0x800U // Flag for Interrupt 2.12 +#define PIE_IFR2_INTX13 0x1000U // Flag for Interrupt 2.13 +#define PIE_IFR2_INTX14 0x2000U // Flag for Interrupt 2.14 +#define PIE_IFR2_INTX15 0x4000U // Flag for Interrupt 2.15 +#define PIE_IFR2_INTX16 0x8000U // Flag for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER3 register +// +//************************************************************************************************* +#define PIE_IER3_INTX1 0x1U // Enable for Interrupt 3.1 +#define PIE_IER3_INTX2 0x2U // Enable for Interrupt 3.2 +#define PIE_IER3_INTX3 0x4U // Enable for Interrupt 3.3 +#define PIE_IER3_INTX4 0x8U // Enable for Interrupt 3.4 +#define PIE_IER3_INTX5 0x10U // Enable for Interrupt 3.5 +#define PIE_IER3_INTX6 0x20U // Enable for Interrupt 3.6 +#define PIE_IER3_INTX7 0x40U // Enable for Interrupt 3.7 +#define PIE_IER3_INTX8 0x80U // Enable for Interrupt 3.8 +#define PIE_IER3_INTX9 0x100U // Enable for Interrupt 3.9 +#define PIE_IER3_INTX10 0x200U // Enable for Interrupt 3.10 +#define PIE_IER3_INTX11 0x400U // Enable for Interrupt 3.11 +#define PIE_IER3_INTX12 0x800U // Enable for Interrupt 3.12 +#define PIE_IER3_INTX13 0x1000U // Enable for Interrupt 3.13 +#define PIE_IER3_INTX14 0x2000U // Enable for Interrupt 3.14 +#define PIE_IER3_INTX15 0x4000U // Enable for Interrupt 3.15 +#define PIE_IER3_INTX16 0x8000U // Enable for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR3 register +// +//************************************************************************************************* +#define PIE_IFR3_INTX1 0x1U // Flag for Interrupt 3.1 +#define PIE_IFR3_INTX2 0x2U // Flag for Interrupt 3.2 +#define PIE_IFR3_INTX3 0x4U // Flag for Interrupt 3.3 +#define PIE_IFR3_INTX4 0x8U // Flag for Interrupt 3.4 +#define PIE_IFR3_INTX5 0x10U // Flag for Interrupt 3.5 +#define PIE_IFR3_INTX6 0x20U // Flag for Interrupt 3.6 +#define PIE_IFR3_INTX7 0x40U // Flag for Interrupt 3.7 +#define PIE_IFR3_INTX8 0x80U // Flag for Interrupt 3.8 +#define PIE_IFR3_INTX9 0x100U // Flag for Interrupt 3.9 +#define PIE_IFR3_INTX10 0x200U // Flag for Interrupt 3.10 +#define PIE_IFR3_INTX11 0x400U // Flag for Interrupt 3.11 +#define PIE_IFR3_INTX12 0x800U // Flag for Interrupt 3.12 +#define PIE_IFR3_INTX13 0x1000U // Flag for Interrupt 3.13 +#define PIE_IFR3_INTX14 0x2000U // Flag for Interrupt 3.14 +#define PIE_IFR3_INTX15 0x4000U // Flag for Interrupt 3.15 +#define PIE_IFR3_INTX16 0x8000U // Flag for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER4 register +// +//************************************************************************************************* +#define PIE_IER4_INTX1 0x1U // Enable for Interrupt 4.1 +#define PIE_IER4_INTX2 0x2U // Enable for Interrupt 4.2 +#define PIE_IER4_INTX3 0x4U // Enable for Interrupt 4.3 +#define PIE_IER4_INTX4 0x8U // Enable for Interrupt 4.4 +#define PIE_IER4_INTX5 0x10U // Enable for Interrupt 4.5 +#define PIE_IER4_INTX6 0x20U // Enable for Interrupt 4.6 +#define PIE_IER4_INTX7 0x40U // Enable for Interrupt 4.7 +#define PIE_IER4_INTX8 0x80U // Enable for Interrupt 4.8 +#define PIE_IER4_INTX9 0x100U // Enable for Interrupt 4.9 +#define PIE_IER4_INTX10 0x200U // Enable for Interrupt 4.10 +#define PIE_IER4_INTX11 0x400U // Enable for Interrupt 4.11 +#define PIE_IER4_INTX12 0x800U // Enable for Interrupt 4.12 +#define PIE_IER4_INTX13 0x1000U // Enable for Interrupt 4.13 +#define PIE_IER4_INTX14 0x2000U // Enable for Interrupt 4.14 +#define PIE_IER4_INTX15 0x4000U // Enable for Interrupt 4.15 +#define PIE_IER4_INTX16 0x8000U // Enable for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR4 register +// +//************************************************************************************************* +#define PIE_IFR4_INTX1 0x1U // Flag for Interrupt 4.1 +#define PIE_IFR4_INTX2 0x2U // Flag for Interrupt 4.2 +#define PIE_IFR4_INTX3 0x4U // Flag for Interrupt 4.3 +#define PIE_IFR4_INTX4 0x8U // Flag for Interrupt 4.4 +#define PIE_IFR4_INTX5 0x10U // Flag for Interrupt 4.5 +#define PIE_IFR4_INTX6 0x20U // Flag for Interrupt 4.6 +#define PIE_IFR4_INTX7 0x40U // Flag for Interrupt 4.7 +#define PIE_IFR4_INTX8 0x80U // Flag for Interrupt 4.8 +#define PIE_IFR4_INTX9 0x100U // Flag for Interrupt 4.9 +#define PIE_IFR4_INTX10 0x200U // Flag for Interrupt 4.10 +#define PIE_IFR4_INTX11 0x400U // Flag for Interrupt 4.11 +#define PIE_IFR4_INTX12 0x800U // Flag for Interrupt 4.12 +#define PIE_IFR4_INTX13 0x1000U // Flag for Interrupt 4.13 +#define PIE_IFR4_INTX14 0x2000U // Flag for Interrupt 4.14 +#define PIE_IFR4_INTX15 0x4000U // Flag for Interrupt 4.15 +#define PIE_IFR4_INTX16 0x8000U // Flag for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER5 register +// +//************************************************************************************************* +#define PIE_IER5_INTX1 0x1U // Enable for Interrupt 5.1 +#define PIE_IER5_INTX2 0x2U // Enable for Interrupt 5.2 +#define PIE_IER5_INTX3 0x4U // Enable for Interrupt 5.3 +#define PIE_IER5_INTX4 0x8U // Enable for Interrupt 5.4 +#define PIE_IER5_INTX5 0x10U // Enable for Interrupt 5.5 +#define PIE_IER5_INTX6 0x20U // Enable for Interrupt 5.6 +#define PIE_IER5_INTX7 0x40U // Enable for Interrupt 5.7 +#define PIE_IER5_INTX8 0x80U // Enable for Interrupt 5.8 +#define PIE_IER5_INTX9 0x100U // Enable for Interrupt 5.9 +#define PIE_IER5_INTX10 0x200U // Enable for Interrupt 5.10 +#define PIE_IER5_INTX11 0x400U // Enable for Interrupt 5.11 +#define PIE_IER5_INTX12 0x800U // Enable for Interrupt 5.12 +#define PIE_IER5_INTX13 0x1000U // Enable for Interrupt 5.13 +#define PIE_IER5_INTX14 0x2000U // Enable for Interrupt 5.14 +#define PIE_IER5_INTX15 0x4000U // Enable for Interrupt 5.15 +#define PIE_IER5_INTX16 0x8000U // Enable for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR5 register +// +//************************************************************************************************* +#define PIE_IFR5_INTX1 0x1U // Flag for Interrupt 5.1 +#define PIE_IFR5_INTX2 0x2U // Flag for Interrupt 5.2 +#define PIE_IFR5_INTX3 0x4U // Flag for Interrupt 5.3 +#define PIE_IFR5_INTX4 0x8U // Flag for Interrupt 5.4 +#define PIE_IFR5_INTX5 0x10U // Flag for Interrupt 5.5 +#define PIE_IFR5_INTX6 0x20U // Flag for Interrupt 5.6 +#define PIE_IFR5_INTX7 0x40U // Flag for Interrupt 5.7 +#define PIE_IFR5_INTX8 0x80U // Flag for Interrupt 5.8 +#define PIE_IFR5_INTX9 0x100U // Flag for Interrupt 5.9 +#define PIE_IFR5_INTX10 0x200U // Flag for Interrupt 5.10 +#define PIE_IFR5_INTX11 0x400U // Flag for Interrupt 5.11 +#define PIE_IFR5_INTX12 0x800U // Flag for Interrupt 5.12 +#define PIE_IFR5_INTX13 0x1000U // Flag for Interrupt 5.13 +#define PIE_IFR5_INTX14 0x2000U // Flag for Interrupt 5.14 +#define PIE_IFR5_INTX15 0x4000U // Flag for Interrupt 5.15 +#define PIE_IFR5_INTX16 0x8000U // Flag for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER6 register +// +//************************************************************************************************* +#define PIE_IER6_INTX1 0x1U // Enable for Interrupt 6.1 +#define PIE_IER6_INTX2 0x2U // Enable for Interrupt 6.2 +#define PIE_IER6_INTX3 0x4U // Enable for Interrupt 6.3 +#define PIE_IER6_INTX4 0x8U // Enable for Interrupt 6.4 +#define PIE_IER6_INTX5 0x10U // Enable for Interrupt 6.5 +#define PIE_IER6_INTX6 0x20U // Enable for Interrupt 6.6 +#define PIE_IER6_INTX7 0x40U // Enable for Interrupt 6.7 +#define PIE_IER6_INTX8 0x80U // Enable for Interrupt 6.8 +#define PIE_IER6_INTX9 0x100U // Enable for Interrupt 6.9 +#define PIE_IER6_INTX10 0x200U // Enable for Interrupt 6.10 +#define PIE_IER6_INTX11 0x400U // Enable for Interrupt 6.11 +#define PIE_IER6_INTX12 0x800U // Enable for Interrupt 6.12 +#define PIE_IER6_INTX13 0x1000U // Enable for Interrupt 6.13 +#define PIE_IER6_INTX14 0x2000U // Enable for Interrupt 6.14 +#define PIE_IER6_INTX15 0x4000U // Enable for Interrupt 6.15 +#define PIE_IER6_INTX16 0x8000U // Enable for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR6 register +// +//************************************************************************************************* +#define PIE_IFR6_INTX1 0x1U // Flag for Interrupt 6.1 +#define PIE_IFR6_INTX2 0x2U // Flag for Interrupt 6.2 +#define PIE_IFR6_INTX3 0x4U // Flag for Interrupt 6.3 +#define PIE_IFR6_INTX4 0x8U // Flag for Interrupt 6.4 +#define PIE_IFR6_INTX5 0x10U // Flag for Interrupt 6.5 +#define PIE_IFR6_INTX6 0x20U // Flag for Interrupt 6.6 +#define PIE_IFR6_INTX7 0x40U // Flag for Interrupt 6.7 +#define PIE_IFR6_INTX8 0x80U // Flag for Interrupt 6.8 +#define PIE_IFR6_INTX9 0x100U // Flag for Interrupt 6.9 +#define PIE_IFR6_INTX10 0x200U // Flag for Interrupt 6.10 +#define PIE_IFR6_INTX11 0x400U // Flag for Interrupt 6.11 +#define PIE_IFR6_INTX12 0x800U // Flag for Interrupt 6.12 +#define PIE_IFR6_INTX13 0x1000U // Flag for Interrupt 6.13 +#define PIE_IFR6_INTX14 0x2000U // Flag for Interrupt 6.14 +#define PIE_IFR6_INTX15 0x4000U // Flag for Interrupt 6.15 +#define PIE_IFR6_INTX16 0x8000U // Flag for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER7 register +// +//************************************************************************************************* +#define PIE_IER7_INTX1 0x1U // Enable for Interrupt 7.1 +#define PIE_IER7_INTX2 0x2U // Enable for Interrupt 7.2 +#define PIE_IER7_INTX3 0x4U // Enable for Interrupt 7.3 +#define PIE_IER7_INTX4 0x8U // Enable for Interrupt 7.4 +#define PIE_IER7_INTX5 0x10U // Enable for Interrupt 7.5 +#define PIE_IER7_INTX6 0x20U // Enable for Interrupt 7.6 +#define PIE_IER7_INTX7 0x40U // Enable for Interrupt 7.7 +#define PIE_IER7_INTX8 0x80U // Enable for Interrupt 7.8 +#define PIE_IER7_INTX9 0x100U // Enable for Interrupt 7.9 +#define PIE_IER7_INTX10 0x200U // Enable for Interrupt 7.10 +#define PIE_IER7_INTX11 0x400U // Enable for Interrupt 7.11 +#define PIE_IER7_INTX12 0x800U // Enable for Interrupt 7.12 +#define PIE_IER7_INTX13 0x1000U // Enable for Interrupt 7.13 +#define PIE_IER7_INTX14 0x2000U // Enable for Interrupt 7.14 +#define PIE_IER7_INTX15 0x4000U // Enable for Interrupt 7.15 +#define PIE_IER7_INTX16 0x8000U // Enable for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR7 register +// +//************************************************************************************************* +#define PIE_IFR7_INTX1 0x1U // Flag for Interrupt 7.1 +#define PIE_IFR7_INTX2 0x2U // Flag for Interrupt 7.2 +#define PIE_IFR7_INTX3 0x4U // Flag for Interrupt 7.3 +#define PIE_IFR7_INTX4 0x8U // Flag for Interrupt 7.4 +#define PIE_IFR7_INTX5 0x10U // Flag for Interrupt 7.5 +#define PIE_IFR7_INTX6 0x20U // Flag for Interrupt 7.6 +#define PIE_IFR7_INTX7 0x40U // Flag for Interrupt 7.7 +#define PIE_IFR7_INTX8 0x80U // Flag for Interrupt 7.8 +#define PIE_IFR7_INTX9 0x100U // Flag for Interrupt 7.9 +#define PIE_IFR7_INTX10 0x200U // Flag for Interrupt 7.10 +#define PIE_IFR7_INTX11 0x400U // Flag for Interrupt 7.11 +#define PIE_IFR7_INTX12 0x800U // Flag for Interrupt 7.12 +#define PIE_IFR7_INTX13 0x1000U // Flag for Interrupt 7.13 +#define PIE_IFR7_INTX14 0x2000U // Flag for Interrupt 7.14 +#define PIE_IFR7_INTX15 0x4000U // Flag for Interrupt 7.15 +#define PIE_IFR7_INTX16 0x8000U // Flag for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER8 register +// +//************************************************************************************************* +#define PIE_IER8_INTX1 0x1U // Enable for Interrupt 8.1 +#define PIE_IER8_INTX2 0x2U // Enable for Interrupt 8.2 +#define PIE_IER8_INTX3 0x4U // Enable for Interrupt 8.3 +#define PIE_IER8_INTX4 0x8U // Enable for Interrupt 8.4 +#define PIE_IER8_INTX5 0x10U // Enable for Interrupt 8.5 +#define PIE_IER8_INTX6 0x20U // Enable for Interrupt 8.6 +#define PIE_IER8_INTX7 0x40U // Enable for Interrupt 8.7 +#define PIE_IER8_INTX8 0x80U // Enable for Interrupt 8.8 +#define PIE_IER8_INTX9 0x100U // Enable for Interrupt 8.9 +#define PIE_IER8_INTX10 0x200U // Enable for Interrupt 8.10 +#define PIE_IER8_INTX11 0x400U // Enable for Interrupt 8.11 +#define PIE_IER8_INTX12 0x800U // Enable for Interrupt 8.12 +#define PIE_IER8_INTX13 0x1000U // Enable for Interrupt 8.13 +#define PIE_IER8_INTX14 0x2000U // Enable for Interrupt 8.14 +#define PIE_IER8_INTX15 0x4000U // Enable for Interrupt 8.15 +#define PIE_IER8_INTX16 0x8000U // Enable for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR8 register +// +//************************************************************************************************* +#define PIE_IFR8_INTX1 0x1U // Flag for Interrupt 8.1 +#define PIE_IFR8_INTX2 0x2U // Flag for Interrupt 8.2 +#define PIE_IFR8_INTX3 0x4U // Flag for Interrupt 8.3 +#define PIE_IFR8_INTX4 0x8U // Flag for Interrupt 8.4 +#define PIE_IFR8_INTX5 0x10U // Flag for Interrupt 8.5 +#define PIE_IFR8_INTX6 0x20U // Flag for Interrupt 8.6 +#define PIE_IFR8_INTX7 0x40U // Flag for Interrupt 8.7 +#define PIE_IFR8_INTX8 0x80U // Flag for Interrupt 8.8 +#define PIE_IFR8_INTX9 0x100U // Flag for Interrupt 8.9 +#define PIE_IFR8_INTX10 0x200U // Flag for Interrupt 8.10 +#define PIE_IFR8_INTX11 0x400U // Flag for Interrupt 8.11 +#define PIE_IFR8_INTX12 0x800U // Flag for Interrupt 8.12 +#define PIE_IFR8_INTX13 0x1000U // Flag for Interrupt 8.13 +#define PIE_IFR8_INTX14 0x2000U // Flag for Interrupt 8.14 +#define PIE_IFR8_INTX15 0x4000U // Flag for Interrupt 8.15 +#define PIE_IFR8_INTX16 0x8000U // Flag for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER9 register +// +//************************************************************************************************* +#define PIE_IER9_INTX1 0x1U // Enable for Interrupt 9.1 +#define PIE_IER9_INTX2 0x2U // Enable for Interrupt 9.2 +#define PIE_IER9_INTX3 0x4U // Enable for Interrupt 9.3 +#define PIE_IER9_INTX4 0x8U // Enable for Interrupt 9.4 +#define PIE_IER9_INTX5 0x10U // Enable for Interrupt 9.5 +#define PIE_IER9_INTX6 0x20U // Enable for Interrupt 9.6 +#define PIE_IER9_INTX7 0x40U // Enable for Interrupt 9.7 +#define PIE_IER9_INTX8 0x80U // Enable for Interrupt 9.8 +#define PIE_IER9_INTX9 0x100U // Enable for Interrupt 9.9 +#define PIE_IER9_INTX10 0x200U // Enable for Interrupt 9.10 +#define PIE_IER9_INTX11 0x400U // Enable for Interrupt 9.11 +#define PIE_IER9_INTX12 0x800U // Enable for Interrupt 9.12 +#define PIE_IER9_INTX13 0x1000U // Enable for Interrupt 9.13 +#define PIE_IER9_INTX14 0x2000U // Enable for Interrupt 9.14 +#define PIE_IER9_INTX15 0x4000U // Enable for Interrupt 9.15 +#define PIE_IER9_INTX16 0x8000U // Enable for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR9 register +// +//************************************************************************************************* +#define PIE_IFR9_INTX1 0x1U // Flag for Interrupt 9.1 +#define PIE_IFR9_INTX2 0x2U // Flag for Interrupt 9.2 +#define PIE_IFR9_INTX3 0x4U // Flag for Interrupt 9.3 +#define PIE_IFR9_INTX4 0x8U // Flag for Interrupt 9.4 +#define PIE_IFR9_INTX5 0x10U // Flag for Interrupt 9.5 +#define PIE_IFR9_INTX6 0x20U // Flag for Interrupt 9.6 +#define PIE_IFR9_INTX7 0x40U // Flag for Interrupt 9.7 +#define PIE_IFR9_INTX8 0x80U // Flag for Interrupt 9.8 +#define PIE_IFR9_INTX9 0x100U // Flag for Interrupt 9.9 +#define PIE_IFR9_INTX10 0x200U // Flag for Interrupt 9.10 +#define PIE_IFR9_INTX11 0x400U // Flag for Interrupt 9.11 +#define PIE_IFR9_INTX12 0x800U // Flag for Interrupt 9.12 +#define PIE_IFR9_INTX13 0x1000U // Flag for Interrupt 9.13 +#define PIE_IFR9_INTX14 0x2000U // Flag for Interrupt 9.14 +#define PIE_IFR9_INTX15 0x4000U // Flag for Interrupt 9.15 +#define PIE_IFR9_INTX16 0x8000U // Flag for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER10 register +// +//************************************************************************************************* +#define PIE_IER10_INTX1 0x1U // Enable for Interrupt 10.1 +#define PIE_IER10_INTX2 0x2U // Enable for Interrupt 10.2 +#define PIE_IER10_INTX3 0x4U // Enable for Interrupt 10.3 +#define PIE_IER10_INTX4 0x8U // Enable for Interrupt 10.4 +#define PIE_IER10_INTX5 0x10U // Enable for Interrupt 10.5 +#define PIE_IER10_INTX6 0x20U // Enable for Interrupt 10.6 +#define PIE_IER10_INTX7 0x40U // Enable for Interrupt 10.7 +#define PIE_IER10_INTX8 0x80U // Enable for Interrupt 10.8 +#define PIE_IER10_INTX9 0x100U // Enable for Interrupt 10.9 +#define PIE_IER10_INTX10 0x200U // Enable for Interrupt 10.10 +#define PIE_IER10_INTX11 0x400U // Enable for Interrupt 10.11 +#define PIE_IER10_INTX12 0x800U // Enable for Interrupt 10.12 +#define PIE_IER10_INTX13 0x1000U // Enable for Interrupt 10.13 +#define PIE_IER10_INTX14 0x2000U // Enable for Interrupt 10.14 +#define PIE_IER10_INTX15 0x4000U // Enable for Interrupt 10.15 +#define PIE_IER10_INTX16 0x8000U // Enable for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR10 register +// +//************************************************************************************************* +#define PIE_IFR10_INTX1 0x1U // Flag for Interrupt 10.1 +#define PIE_IFR10_INTX2 0x2U // Flag for Interrupt 10.2 +#define PIE_IFR10_INTX3 0x4U // Flag for Interrupt 10.3 +#define PIE_IFR10_INTX4 0x8U // Flag for Interrupt 10.4 +#define PIE_IFR10_INTX5 0x10U // Flag for Interrupt 10.5 +#define PIE_IFR10_INTX6 0x20U // Flag for Interrupt 10.6 +#define PIE_IFR10_INTX7 0x40U // Flag for Interrupt 10.7 +#define PIE_IFR10_INTX8 0x80U // Flag for Interrupt 10.8 +#define PIE_IFR10_INTX9 0x100U // Flag for Interrupt 10.9 +#define PIE_IFR10_INTX10 0x200U // Flag for Interrupt 10.10 +#define PIE_IFR10_INTX11 0x400U // Flag for Interrupt 10.11 +#define PIE_IFR10_INTX12 0x800U // Flag for Interrupt 10.12 +#define PIE_IFR10_INTX13 0x1000U // Flag for Interrupt 10.13 +#define PIE_IFR10_INTX14 0x2000U // Flag for Interrupt 10.14 +#define PIE_IFR10_INTX15 0x4000U // Flag for Interrupt 10.15 +#define PIE_IFR10_INTX16 0x8000U // Flag for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER11 register +// +//************************************************************************************************* +#define PIE_IER11_INTX1 0x1U // Enable for Interrupt 11.1 +#define PIE_IER11_INTX2 0x2U // Enable for Interrupt 11.2 +#define PIE_IER11_INTX3 0x4U // Enable for Interrupt 11.3 +#define PIE_IER11_INTX4 0x8U // Enable for Interrupt 11.4 +#define PIE_IER11_INTX5 0x10U // Enable for Interrupt 11.5 +#define PIE_IER11_INTX6 0x20U // Enable for Interrupt 11.6 +#define PIE_IER11_INTX7 0x40U // Enable for Interrupt 11.7 +#define PIE_IER11_INTX8 0x80U // Enable for Interrupt 11.8 +#define PIE_IER11_INTX9 0x100U // Enable for Interrupt 11.9 +#define PIE_IER11_INTX10 0x200U // Enable for Interrupt 11.10 +#define PIE_IER11_INTX11 0x400U // Enable for Interrupt 11.11 +#define PIE_IER11_INTX12 0x800U // Enable for Interrupt 11.12 +#define PIE_IER11_INTX13 0x1000U // Enable for Interrupt 11.13 +#define PIE_IER11_INTX14 0x2000U // Enable for Interrupt 11.14 +#define PIE_IER11_INTX15 0x4000U // Enable for Interrupt 11.15 +#define PIE_IER11_INTX16 0x8000U // Enable for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR11 register +// +//************************************************************************************************* +#define PIE_IFR11_INTX1 0x1U // Flag for Interrupt 11.1 +#define PIE_IFR11_INTX2 0x2U // Flag for Interrupt 11.2 +#define PIE_IFR11_INTX3 0x4U // Flag for Interrupt 11.3 +#define PIE_IFR11_INTX4 0x8U // Flag for Interrupt 11.4 +#define PIE_IFR11_INTX5 0x10U // Flag for Interrupt 11.5 +#define PIE_IFR11_INTX6 0x20U // Flag for Interrupt 11.6 +#define PIE_IFR11_INTX7 0x40U // Flag for Interrupt 11.7 +#define PIE_IFR11_INTX8 0x80U // Flag for Interrupt 11.8 +#define PIE_IFR11_INTX9 0x100U // Flag for Interrupt 11.9 +#define PIE_IFR11_INTX10 0x200U // Flag for Interrupt 11.10 +#define PIE_IFR11_INTX11 0x400U // Flag for Interrupt 11.11 +#define PIE_IFR11_INTX12 0x800U // Flag for Interrupt 11.12 +#define PIE_IFR11_INTX13 0x1000U // Flag for Interrupt 11.13 +#define PIE_IFR11_INTX14 0x2000U // Flag for Interrupt 11.14 +#define PIE_IFR11_INTX15 0x4000U // Flag for Interrupt 11.15 +#define PIE_IFR11_INTX16 0x8000U // Flag for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER12 register +// +//************************************************************************************************* +#define PIE_IER12_INTX1 0x1U // Enable for Interrupt 12.1 +#define PIE_IER12_INTX2 0x2U // Enable for Interrupt 12.2 +#define PIE_IER12_INTX3 0x4U // Enable for Interrupt 12.3 +#define PIE_IER12_INTX4 0x8U // Enable for Interrupt 12.4 +#define PIE_IER12_INTX5 0x10U // Enable for Interrupt 12.5 +#define PIE_IER12_INTX6 0x20U // Enable for Interrupt 12.6 +#define PIE_IER12_INTX7 0x40U // Enable for Interrupt 12.7 +#define PIE_IER12_INTX8 0x80U // Enable for Interrupt 12.8 +#define PIE_IER12_INTX9 0x100U // Enable for Interrupt 12.9 +#define PIE_IER12_INTX10 0x200U // Enable for Interrupt 12.10 +#define PIE_IER12_INTX11 0x400U // Enable for Interrupt 12.11 +#define PIE_IER12_INTX12 0x800U // Enable for Interrupt 12.12 +#define PIE_IER12_INTX13 0x1000U // Enable for Interrupt 12.13 +#define PIE_IER12_INTX14 0x2000U // Enable for Interrupt 12.14 +#define PIE_IER12_INTX15 0x4000U // Enable for Interrupt 12.15 +#define PIE_IER12_INTX16 0x8000U // Enable for Interrupt 12.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR12 register +// +//************************************************************************************************* +#define PIE_IFR12_INTX1 0x1U // Flag for Interrupt 12.1 +#define PIE_IFR12_INTX2 0x2U // Flag for Interrupt 12.2 +#define PIE_IFR12_INTX3 0x4U // Flag for Interrupt 12.3 +#define PIE_IFR12_INTX4 0x8U // Flag for Interrupt 12.4 +#define PIE_IFR12_INTX5 0x10U // Flag for Interrupt 12.5 +#define PIE_IFR12_INTX6 0x20U // Flag for Interrupt 12.6 +#define PIE_IFR12_INTX7 0x40U // Flag for Interrupt 12.7 +#define PIE_IFR12_INTX8 0x80U // Flag for Interrupt 12.8 +#define PIE_IFR12_INTX9 0x100U // Flag for Interrupt 12.9 +#define PIE_IFR12_INTX10 0x200U // Flag for Interrupt 12.10 +#define PIE_IFR12_INTX11 0x400U // Flag for Interrupt 12.11 +#define PIE_IFR12_INTX12 0x800U // Flag for Interrupt 12.12 +#define PIE_IFR12_INTX13 0x1000U // Flag for Interrupt 12.13 +#define PIE_IFR12_INTX14 0x2000U // Flag for Interrupt 12.14 +#define PIE_IFR12_INTX15 0x4000U // Flag for Interrupt 12.15 +#define PIE_IFR12_INTX16 0x8000U // Flag for Interrupt 12.16 + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_sci.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_sci.h new file mode 100644 index 0000000..2fc9680 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_sci.h @@ -0,0 +1,209 @@ +//########################################################################### +// +// FILE: hw_sci.h +// +// TITLE: Definitions for the SCI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SCI_H +#define HW_SCI_H + +//************************************************************************************************* +// +// The following are defines for the SCI register offsets +// +//************************************************************************************************* +#define SCI_O_CCR 0x0U // Communications control register +#define SCI_O_CTL1 0x1U // Control register 1 +#define SCI_O_HBAUD 0x2U // Baud rate (high) register +#define SCI_O_LBAUD 0x3U // Baud rate (low) register +#define SCI_O_CTL2 0x4U // Control register 2 +#define SCI_O_RXST 0x5U // Receive status register +#define SCI_O_RXEMU 0x6U // Receive emulation buffer register +#define SCI_O_RXBUF 0x7U // Receive data buffer +#define SCI_O_TXBUF 0x9U // Transmit data buffer +#define SCI_O_FFTX 0xAU // FIFO transmit register +#define SCI_O_FFRX 0xBU // FIFO receive register +#define SCI_O_FFCT 0xCU // FIFO control register +#define SCI_O_PRI 0xFU // SCI priority control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICCR register +// +//************************************************************************************************* +#define SCI_CCR_SCICHAR_S 0U +#define SCI_CCR_SCICHAR_M 0x7U // Character length control +#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control +#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable +#define SCI_CCR_PARITYENA 0x20U // Parity enable +#define SCI_CCR_PARITY 0x40U // Even or Odd Parity +#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL1 register +// +//************************************************************************************************* +#define SCI_CTL1_RXENA 0x1U // SCI receiver enable +#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable +#define SCI_CTL1_SLEEP 0x4U // SCI sleep +#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method +#define SCI_CTL1_SWRESET 0x20U // Software reset +#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIHBAUD register +// +//************************************************************************************************* +#define SCI_HBAUD_BAUD_S 0U +#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCILBAUD register +// +//************************************************************************************************* +#define SCI_LBAUD_BAUD_S 0U +#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL2 register +// +//************************************************************************************************* +#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable +#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable +#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag +#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXST register +// +//************************************************************************************************* +#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag +#define SCI_RXST_PE 0x4U // Parity error flag +#define SCI_RXST_OE 0x8U // Overrun error flag +#define SCI_RXST_FE 0x10U // Framing error flag +#define SCI_RXST_BRKDT 0x20U // Break-detect flag +#define SCI_RXST_RXRDY 0x40U // Receiver ready flag +#define SCI_RXST_RXERROR 0x80U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXEMU register +// +//************************************************************************************************* +#define SCI_RXEMU_ERXDT_S 0U +#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXBUF register +// +//************************************************************************************************* +#define SCI_RXBUF_SAR_S 0U +#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits +#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag +#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCITXBUF register +// +//************************************************************************************************* +#define SCI_TXBUF_TXDT_S 0U +#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFTX register +// +//************************************************************************************************* +#define SCI_FFTX_TXFFIL_S 0U +#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level +#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable +#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFTX_TXFFINT 0x80U // INT flag +#define SCI_FFTX_TXFFST_S 8U +#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status +#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset +#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable +#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFRX register +// +//************************************************************************************************* +#define SCI_FFRX_RXFFIL_S 0U +#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level +#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable +#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFRX_RXFFINT 0x80U // INT flag +#define SCI_FFRX_RXFFST_S 8U +#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status +#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset +#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow +#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFCT register +// +//************************************************************************************************* +#define SCI_FFCT_FFTXDLY_S 0U +#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay +#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable +#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear +#define SCI_FFCT_ABD 0x8000U // Auto baud detect + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIPRI register +// +//************************************************************************************************* +#define SCI_PRI_FREESOFT_S 3U +#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_sdfm.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_sdfm.h new file mode 100644 index 0000000..d2ba146 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_sdfm.h @@ -0,0 +1,431 @@ +//########################################################################### +// +// FILE: hw_sdfm.h +// +// TITLE: Definitions for the SDFM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SDFM_H +#define HW_SDFM_H + +//************************************************************************************************* +// +// The following are defines for the SDFM register offsets +// +//************************************************************************************************* +#define SDFM_O_SDIFLG 0x0U // Interrupt Flag Register +#define SDFM_O_SDIFLGCLR 0x2U // Interrupt Flag Clear Register +#define SDFM_O_SDCTL 0x4U // SD Control Register +#define SDFM_O_SDMFILEN 0x6U // SD Master Filter Enable +#define SDFM_O_SDCTLPARM1 0x10U // Control Parameter Register for Ch1 +#define SDFM_O_SDDFPARM1 0x11U // Data Filter Parameter Register for Ch1 +#define SDFM_O_SDDPARM1 0x12U // Integer Parameter Register for Ch1 +#define SDFM_O_SDCMPH1 0x13U // High-level Threshold Register for Ch1 +#define SDFM_O_SDCMPL1 0x14U // Low-level Threshold Register for Ch1 +#define SDFM_O_SDCPARM1 0x15U // Comparator Parameter Register for Ch1 +#define SDFM_O_SDDATA1 0x16U // Filter Data Register (16 or 32bit) for Ch1 +#define SDFM_O_SDCTLPARM2 0x20U // Control Parameter Register for Ch2 +#define SDFM_O_SDDFPARM2 0x21U // Data Filter Parameter Register for Ch2 +#define SDFM_O_SDDPARM2 0x22U // Integer Parameter Register for Ch2 +#define SDFM_O_SDCMPH2 0x23U // High-level Threshold Register for Ch2 +#define SDFM_O_SDCMPL2 0x24U // Low-level Threshold Register for Ch2 +#define SDFM_O_SDCPARM2 0x25U // Comparator Parameter Register for Ch2 +#define SDFM_O_SDDATA2 0x26U // Filter Data Register (16 or 32bit) for Ch2 +#define SDFM_O_SDCTLPARM3 0x30U // Control Parameter Register for Ch3 +#define SDFM_O_SDDFPARM3 0x31U // Data Filter Parameter Register for Ch3 +#define SDFM_O_SDDPARM3 0x32U // Integer Parameter Register for Ch3 +#define SDFM_O_SDCMPH3 0x33U // High-level Threshold Register for Ch3 +#define SDFM_O_SDCMPL3 0x34U // Low-level Threshold Register for Ch3 +#define SDFM_O_SDCPARM3 0x35U // Comparator Parameter Register for Ch3 +#define SDFM_O_SDDATA3 0x36U // Filter Data Register (16 or 32bit) for Ch3 +#define SDFM_O_SDCTLPARM4 0x40U // Control Parameter Register for Ch4 +#define SDFM_O_SDDFPARM4 0x41U // Data Filter Parameter Register for Ch4 +#define SDFM_O_SDDPARM4 0x42U // Integer Parameter Register for Ch4 +#define SDFM_O_SDCMPH4 0x43U // High-level Threshold Register for Ch4 +#define SDFM_O_SDCMPL4 0x44U // Low-level Threshold Register for Ch4 +#define SDFM_O_SDCPARM4 0x45U // Comparator Parameter Register for Ch4 +#define SDFM_O_SDDATA4 0x46U // Filter Data Register (16 or 32bit) for Ch4 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLG register +// +//************************************************************************************************* +#define SDFM_SDIFLG_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLG_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLG_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLG_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLG_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLG_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLG_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLG_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLG_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLG_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLG_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLGCLR register +// +//************************************************************************************************* +#define SDFM_SDIFLGCLR_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLGCLR_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLGCLR_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLGCLR_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLGCLR_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLGCLR_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLGCLR_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLGCLR_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLGCLR_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTL register +// +//************************************************************************************************* +#define SDFM_SDCTL_MIE 0x2000U // Master Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDMFILEN register +// +//************************************************************************************************* +#define SDFM_SDMFILEN_MFE 0x800U // Master Filter Enable. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM1_MOD_S 0U +#define SDFM_SDCTLPARM1_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM1_DOSR_S 0U +#define SDFM_SDDFPARM1_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM1_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM1_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM1_SST_S 10U +#define SDFM_SDDFPARM1_SST_M 0xC00U // Data Filter Structure (DataFast/1/2/3) +#define SDFM_SDDFPARM1_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDPARM1_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM1_SH_S 11U +#define SDFM_SDDPARM1_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH1 register +// +//************************************************************************************************* +#define SDFM_SDCMPH1_HLT_S 0U +#define SDFM_SDCMPH1_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL1 register +// +//************************************************************************************************* +#define SDFM_SDCMPL1_LLT_S 0U +#define SDFM_SDCMPL1_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCPARM1_COSR_S 0U +#define SDFM_SDCPARM1_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM1_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM1_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM1_CS1_CS0_S 7U +#define SDFM_SDCPARM1_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM1_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA1 register +// +//************************************************************************************************* +#define SDFM_SDDATA1_DATA16_S 0U +#define SDFM_SDDATA1_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA1_DATA32HI_S 16U +#define SDFM_SDDATA1_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM2_MOD_S 0U +#define SDFM_SDCTLPARM2_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM2_DOSR_S 0U +#define SDFM_SDDFPARM2_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM2_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM2_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM2_SST_S 10U +#define SDFM_SDDFPARM2_SST_M 0xC00U // Data Filter Structure (SincFast/1/2/3) +#define SDFM_SDDFPARM2_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDPARM2_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM2_SH_S 11U +#define SDFM_SDDPARM2_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH2 register +// +//************************************************************************************************* +#define SDFM_SDCMPH2_HLT_S 0U +#define SDFM_SDCMPH2_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL2 register +// +//************************************************************************************************* +#define SDFM_SDCMPL2_LLT_S 0U +#define SDFM_SDCMPL2_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCPARM2_COSR_S 0U +#define SDFM_SDCPARM2_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM2_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM2_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM2_CS1_CS0_S 7U +#define SDFM_SDCPARM2_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM2_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA2 register +// +//************************************************************************************************* +#define SDFM_SDDATA2_DATA16_S 0U +#define SDFM_SDDATA2_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA2_DATA32HI_S 16U +#define SDFM_SDDATA2_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM3_MOD_S 0U +#define SDFM_SDCTLPARM3_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM3_DOSR_S 0U +#define SDFM_SDDFPARM3_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM3_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM3_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM3_SST_S 10U +#define SDFM_SDDFPARM3_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM3_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDPARM3_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM3_SH_S 11U +#define SDFM_SDDPARM3_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH3 register +// +//************************************************************************************************* +#define SDFM_SDCMPH3_HLT_S 0U +#define SDFM_SDCMPH3_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL3 register +// +//************************************************************************************************* +#define SDFM_SDCMPL3_LLT_S 0U +#define SDFM_SDCMPL3_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCPARM3_COSR_S 0U +#define SDFM_SDCPARM3_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM3_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM3_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM3_CS1_CS0_S 7U +#define SDFM_SDCPARM3_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM3_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA3 register +// +//************************************************************************************************* +#define SDFM_SDDATA3_DATA16_S 0U +#define SDFM_SDDATA3_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA3_DATA32HI_S 16U +#define SDFM_SDDATA3_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM4_MOD_S 0U +#define SDFM_SDCTLPARM4_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM4_DOSR_S 0U +#define SDFM_SDDFPARM4_DOSR_M 0xFFU // SINC Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM4_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM4_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM4_SST_S 10U +#define SDFM_SDDFPARM4_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM4_SDSYNCEN 0x1000U // SINC FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDPARM4_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM4_SH_S 11U +#define SDFM_SDDPARM4_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH4 register +// +//************************************************************************************************* +#define SDFM_SDCMPH4_HLT_S 0U +#define SDFM_SDCMPH4_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL4 register +// +//************************************************************************************************* +#define SDFM_SDCMPL4_LLT_S 0U +#define SDFM_SDCMPL4_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCPARM4_COSR_S 0U +#define SDFM_SDCPARM4_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM4_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM4_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM4_CS1_CS0_S 7U +#define SDFM_SDCPARM4_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM4_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA4 register +// +//************************************************************************************************* +#define SDFM_SDDATA4_DATA16_S 0U +#define SDFM_SDDATA4_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA4_DATA32HI_S 16U +#define SDFM_SDDATA4_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_spi.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_spi.h new file mode 100644 index 0000000..c4907aa --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_spi.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_spi.h +// +// TITLE: Definitions for the SPI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SPI_H +#define HW_SPI_H + +//************************************************************************************************* +// +// The following are defines for the SPI register offsets +// +//************************************************************************************************* +#define SPI_O_CCR 0x0U // SPI Configuration Control Register +#define SPI_O_CTL 0x1U // SPI Operation Control Register +#define SPI_O_STS 0x2U // SPI Status Register +#define SPI_O_BRR 0x4U // SPI Baud Rate Register +#define SPI_O_RXEMU 0x6U // SPI Emulation Buffer Register +#define SPI_O_RXBUF 0x7U // SPI Serial Input Buffer Register +#define SPI_O_TXBUF 0x8U // SPI Serial Output Buffer Register +#define SPI_O_DAT 0x9U // SPI Serial Data Register +#define SPI_O_FFTX 0xAU // SPI FIFO Transmit Register +#define SPI_O_FFRX 0xBU // SPI FIFO Receive Register +#define SPI_O_FFCT 0xCU // SPI FIFO Control Register +#define SPI_O_PRI 0xFU // SPI Priority Control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICCR register +// +//************************************************************************************************* +#define SPI_CCR_SPICHAR_S 0U +#define SPI_CCR_SPICHAR_M 0xFU // Character Length Control +#define SPI_CCR_SPILBK 0x10U // SPI Loopback +#define SPI_CCR_HS_MODE 0x20U // High Speed mode control +#define SPI_CCR_CLKPOLARITY 0x40U // Shift Clock Polarity +#define SPI_CCR_SPISWRESET 0x80U // SPI Software Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICTL register +// +//************************************************************************************************* +#define SPI_CTL_SPIINTENA 0x1U // SPI Interupt Enable +#define SPI_CTL_TALK 0x2U // Master/Slave Transmit Enable +#define SPI_CTL_MASTER_SLAVE 0x4U // SPI Network Mode Control +#define SPI_CTL_CLK_PHASE 0x8U // SPI Clock Phase +#define SPI_CTL_OVERRUNINTENA 0x10U // Overrun Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPISTS register +// +//************************************************************************************************* +#define SPI_STS_BUFFULL_FLAG 0x20U // SPI Transmit Buffer Full Flag +#define SPI_STS_INT_FLAG 0x40U // SPI Interrupt Flag +#define SPI_STS_OVERRUN_FLAG 0x80U // SPI Receiver Overrun Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIBRR register +// +//************************************************************************************************* +#define SPI_BRR_SPI_BIT_RATE_S 0U +#define SPI_BRR_SPI_BIT_RATE_M 0x7FU // SPI Bit Rate Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFTX register +// +//************************************************************************************************* +#define SPI_FFTX_TXFFIL_S 0U +#define SPI_FFTX_TXFFIL_M 0x1FU // TXFIFO Interrupt Level +#define SPI_FFTX_TXFFIENA 0x20U // TXFIFO Interrupt Enable +#define SPI_FFTX_TXFFINTCLR 0x40U // TXFIFO Interrupt Clear +#define SPI_FFTX_TXFFINT 0x80U // TXFIFO Interrupt Flag +#define SPI_FFTX_TXFFST_S 8U +#define SPI_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define SPI_FFTX_TXFIFO 0x2000U // TXFIFO Reset +#define SPI_FFTX_SPIFFENA 0x4000U // FIFO Enhancements Enable +#define SPI_FFTX_SPIRST 0x8000U // SPI Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFRX register +// +//************************************************************************************************* +#define SPI_FFRX_RXFFIL_S 0U +#define SPI_FFRX_RXFFIL_M 0x1FU // RXFIFO Interrupt Level +#define SPI_FFRX_RXFFIENA 0x20U // RXFIFO Interrupt Enable +#define SPI_FFRX_RXFFINTCLR 0x40U // RXFIFO Interupt Clear +#define SPI_FFRX_RXFFINT 0x80U // RXFIFO Interrupt Flag +#define SPI_FFRX_RXFFST_S 8U +#define SPI_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define SPI_FFRX_RXFIFORESET 0x2000U // RXFIFO Reset +#define SPI_FFRX_RXFFOVFCLR 0x4000U // Receive FIFO Overflow Clear +#define SPI_FFRX_RXFFOVF 0x8000U // Receive FIFO Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFCT register +// +//************************************************************************************************* +#define SPI_FFCT_TXDLY_S 0U +#define SPI_FFCT_TXDLY_M 0xFFU // FIFO Transmit Delay Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIPRI register +// +//************************************************************************************************* +#define SPI_PRI_TRIWIRE 0x1U // 3-wire mode select bit +#define SPI_PRI_STEINV 0x2U // SPISTE inversion bit +#define SPI_PRI_FREE 0x10U // Free emulation mode +#define SPI_PRI_SOFT 0x20U // Soft emulation mode + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_sysctl.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_sysctl.h new file mode 100644 index 0000000..11df8d3 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_sysctl.h @@ -0,0 +1,1428 @@ +//########################################################################### +// +// FILE: hw_sysctl.h +// +// TITLE: Definitions for the SYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SYSCTL_H +#define HW_SYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the SYSCTL register offsets +// +//************************************************************************************************* +#define SYSCTL_O_DEVCFGLOCK1 0x0U // Lock bit for CPUSELx registers +#define SYSCTL_O_PARTIDL 0x8U // Lower 32-bit of Device PART Identification Number +#define SYSCTL_O_PARTIDH 0xAU // Upper 32-bit of Device PART Identification Number +#define SYSCTL_O_REVID 0xCU // Device Revision Number +#define SYSCTL_O_DC0 0x10U // Device Capability: Device Information +#define SYSCTL_O_DC1 0x12U // Device Capability: Processing Block Customization +#define SYSCTL_O_DC2 0x14U // Device Capability: EMIF Customization +#define SYSCTL_O_DC3 0x16U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC4 0x18U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC5 0x1AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC6 0x1CU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC7 0x1EU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC8 0x20U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC9 0x22U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC10 0x24U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC11 0x26U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC12 0x28U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC13 0x2AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC14 0x2CU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC15 0x2EU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC17 0x32U // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC18 0x34U // Device Capability: CPU1 Lx SRAM Customization +#define SYSCTL_O_DC19 0x36U // Device Capability: CPU2 Lx SRAM Customization +#define SYSCTL_O_DC20 0x38U // Device Capability: GSx SRAM Customization +#define SYSCTL_O_PERCNF1 0x60U // Peripheral Configuration register +#define SYSCTL_O_FUSEERR 0x74U // e-Fuse error Status register +#define SYSCTL_O_SOFTPRES0 0x82U // Processing Block Software Reset register +#define SYSCTL_O_SOFTPRES1 0x84U // EMIF Software Reset register +#define SYSCTL_O_SOFTPRES2 0x86U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES3 0x88U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES4 0x8AU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES6 0x8EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES7 0x90U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES8 0x92U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES9 0x94U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES11 0x98U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES13 0x9CU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES14 0x9EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES16 0xA2U // Peripheral Software Reset register +#define SYSCTL_O_CPUSEL0 0xD6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL1 0xD8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL2 0xDAU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL4 0xDEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL5 0xE0U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL6 0xE2U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL7 0xE4U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL8 0xE6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL9 0xE8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL11 0xECU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL12 0xEEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL14 0xF2U // CPU Select register for common peripherals +#define SYSCTL_O_CPU2RESCTL 0x122U // CPU2 Reset Control Register +#define SYSCTL_O_RSTSTAT 0x124U // Reset Status register for secondary C28x CPUs +#define SYSCTL_O_LPMSTAT 0x125U // LPM Status Register for secondary C28x CPUs +#define SYSCTL_O_SYSDBGCTL 0x12CU // System Debug Control register + +#define SYSCTL_O_CLKSEM 0x0U // Clock Control Semaphore Register +#define SYSCTL_O_CLKCFGLOCK1 0x2U // Lock bit for CLKCFG registers +#define SYSCTL_O_CLKSRCCTL1 0x8U // Clock Source Control register-1 +#define SYSCTL_O_CLKSRCCTL2 0xAU // Clock Source Control register-2 +#define SYSCTL_O_CLKSRCCTL3 0xCU // Clock Source Control register-3 +#define SYSCTL_O_SYSPLLCTL1 0xEU // SYSPLL Control register-1 +#define SYSCTL_O_SYSPLLMULT 0x14U // SYSPLL Multiplier register +#define SYSCTL_O_SYSPLLSTS 0x16U // SYSPLL Status register +#define SYSCTL_O_AUXPLLCTL1 0x18U // AUXPLL Control register-1 +#define SYSCTL_O_AUXPLLMULT 0x1EU // AUXPLL Multiplier register +#define SYSCTL_O_AUXPLLSTS 0x20U // AUXPLL Status register +#define SYSCTL_O_SYSCLKDIVSEL 0x22U // System Clock Divider Select register +#define SYSCTL_O_AUXCLKDIVSEL 0x24U // Auxillary Clock Divider Select register +#define SYSCTL_O_PERCLKDIVSEL 0x26U // Peripheral Clock Divider Selet register +#define SYSCTL_O_XCLKOUTDIVSEL 0x28U // XCLKOUT Divider Select register +#define SYSCTL_O_LOSPCP 0x2CU // Low Speed Clock Source Prescalar +#define SYSCTL_O_MCDCR 0x2EU // Missing Clock Detect Control Register +#define SYSCTL_O_X1CNT 0x30U // 10-bit Counter on X1 Clock + +#define SYSCTL_O_CPUSYSLOCK1 0x0U // Lock bit for CPUSYS registers +#define SYSCTL_O_HIBBOOTMODE 0x6U // HIB Boot Mode Register +#define SYSCTL_O_IORESTOREADDR 0x8U // IORestore() routine Address Register +#define SYSCTL_O_PIEVERRADDR 0xAU // PIE Vector Fetch Error Address register +#define SYSCTL_O_PCLKCR0 0x22U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR1 0x24U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR2 0x26U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR3 0x28U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR4 0x2AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR6 0x2EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR7 0x30U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR8 0x32U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR9 0x34U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR10 0x36U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR11 0x38U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR12 0x3AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR13 0x3CU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR14 0x3EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR16 0x42U // Peripheral Clock Gating Registers +#define SYSCTL_O_SECMSEL 0x74U // Secondary Master Select register for common + // peripherals: Selects between CLA & DMA +#define SYSCTL_O_LPMCR 0x76U // LPM Control Register +#define SYSCTL_O_GPIOLPMSEL0 0x78U // GPIO LPM Wakeup select registers +#define SYSCTL_O_GPIOLPMSEL1 0x7AU // GPIO LPM Wakeup select registers +#define SYSCTL_O_TMR2CLKCTL 0x7CU // Timer2 Clock Measurement functionality control register +#define SYSCTL_O_RESC 0x80U // Reset Cause register + +#define SYSCTL_O_SCSR 0x22U // System Control & Status Register +#define SYSCTL_O_WDCNTR 0x23U // Watchdog Counter Register +#define SYSCTL_O_WDKEY 0x25U // Watchdog Reset Key Register +#define SYSCTL_O_WDCR 0x29U // Watchdog Control Register +#define SYSCTL_O_WDWCR 0x2AU // Watchdog Windowed Control Register + +#define SYSCTL_O_CLA1TASKSRCSELLOCK 0x0U // CLA1 Task Trigger Source Select Lock Register +#define SYSCTL_O_DMACHSRCSELLOCK 0x4U // DMA Channel Triger Source Select Lock Register +#define SYSCTL_O_CLA1TASKSRCSEL1 0x6U // CLA1 Task Trigger Source Select Register-1 +#define SYSCTL_O_CLA1TASKSRCSEL2 0x8U // CLA1 Task Trigger Source Select Register-2 +#define SYSCTL_O_DMACHSRCSEL1 0x16U // DMA Channel Trigger Source Select Register-1 +#define SYSCTL_O_DMACHSRCSEL2 0x18U // DMA Channel Trigger Source Select Register-2 + +#define SYSCTL_O_SYNCSELECT 0x0U // Sync Input and Output Select Register +#define SYSCTL_O_ADCSOCOUTSELECT 0x2U // External ADC (Off Chip) SOC Select Register +#define SYSCTL_O_SYNCSOCLOCK 0x4U // SYNCSEL and EXTADCSOC Select Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEVCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_DEVCFGLOCK1_CPUSEL0 0x1U // Lock bit for CPUSEL0 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL1 0x2U // Lock bit for CPUSEL1 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL2 0x4U // Lock bit for CPUSEL2 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL3 0x8U // Lock bit for CPUSEL3 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL4 0x10U // Lock bit for CPUSEL4 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL5 0x20U // Lock bit for CPUSEL5 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL6 0x40U // Lock bit for CPUSEL6 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL7 0x80U // Lock bit for CPUSEL7 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL8 0x100U // Lock bit for CPUSEL8 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL9 0x200U // Lock bit for CPUSEL9 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL10 0x400U // Lock bit for CPUSEL10 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL11 0x800U // Lock bit for CPUSEL11 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL12 0x1000U // Lock bit for CPUSEL12 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL13 0x2000U // Lock bit for CPUSEL13 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL14 0x4000U // Lock bit for CPUSEL14 register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDL register +// +//************************************************************************************************* +#define SYSCTL_PARTIDL_QUAL_S 6U +#define SYSCTL_PARTIDL_QUAL_M 0xC0U // Qualification Status +#define SYSCTL_PARTIDL_PIN_COUNT_S 8U +#define SYSCTL_PARTIDL_PIN_COUNT_M 0x700U // Device Pin Count +#define SYSCTL_PARTIDL_INSTASPIN_S 13U +#define SYSCTL_PARTIDL_INSTASPIN_M 0x6000U // Motorware feature set +#define SYSCTL_PARTIDL_FLASH_SIZE_S 16U +#define SYSCTL_PARTIDL_FLASH_SIZE_M 0xFF0000U // Flash size in KB +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S 28U +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M 0xF0000000U // Revision of the PARTID format + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDH register +// +//************************************************************************************************* +#define SYSCTL_PARTIDH_FAMILY_S 8U +#define SYSCTL_PARTIDH_FAMILY_M 0xFF00U // Device family +#define SYSCTL_PARTIDH_PARTNO_S 16U +#define SYSCTL_PARTIDH_PARTNO_M 0xFF0000U // Device part number +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_S 24U +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_M 0xFF000000U // Device class ID + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC0 register +// +//************************************************************************************************* +#define SYSCTL_DC0_SINGLE_CORE 0x1U // Single Core vs Dual Core + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC1 register +// +//************************************************************************************************* +#define SYSCTL_DC1_CPU1_FPU_TMU 0x1U // CPU1's FPU1+TMU1 +#define SYSCTL_DC1_CPU2_FPU_TMU 0x2U // CPU2's FPU2+TMU2 +#define SYSCTL_DC1_CPU1_VCU 0x4U // CPU1's VCU +#define SYSCTL_DC1_CPU2_VCU 0x8U // CPU2's VCU +#define SYSCTL_DC1_CPU1_CLA1 0x40U // CPU1.CLA1 +#define SYSCTL_DC1_CPU2_CLA1 0x100U // CPU2.CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC2 register +// +//************************************************************************************************* +#define SYSCTL_DC2_EMIF1 0x1U // EMIF1 +#define SYSCTL_DC2_EMIF2 0x2U // EMIF2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC3 register +// +//************************************************************************************************* +#define SYSCTL_DC3_EPWM1 0x1U // EPWM1 +#define SYSCTL_DC3_EPWM2 0x2U // EPWM2 +#define SYSCTL_DC3_EPWM3 0x4U // EPWM3 +#define SYSCTL_DC3_EPWM4 0x8U // EPWM4 +#define SYSCTL_DC3_EPWM5 0x10U // EPWM5 +#define SYSCTL_DC3_EPWM6 0x20U // EPWM6 +#define SYSCTL_DC3_EPWM7 0x40U // EPWM7 +#define SYSCTL_DC3_EPWM8 0x80U // EPWM8 +#define SYSCTL_DC3_EPWM9 0x100U // EPWM9 +#define SYSCTL_DC3_EPWM10 0x200U // EPWM10 +#define SYSCTL_DC3_EPWM11 0x400U // EPWM11 +#define SYSCTL_DC3_EPWM12 0x800U // EPWM12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC4 register +// +//************************************************************************************************* +#define SYSCTL_DC4_ECAP1 0x1U // ECAP1 +#define SYSCTL_DC4_ECAP2 0x2U // ECAP2 +#define SYSCTL_DC4_ECAP3 0x4U // ECAP3 +#define SYSCTL_DC4_ECAP4 0x8U // ECAP4 +#define SYSCTL_DC4_ECAP5 0x10U // ECAP5 +#define SYSCTL_DC4_ECAP6 0x20U // ECAP6 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC5 register +// +//************************************************************************************************* +#define SYSCTL_DC5_EQEP1 0x1U // EQEP1 +#define SYSCTL_DC5_EQEP2 0x2U // EQEP2 +#define SYSCTL_DC5_EQEP3 0x4U // EQEP3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC6 register +// +//************************************************************************************************* +#define SYSCTL_DC6_CLB1 0x1U // CLB1 +#define SYSCTL_DC6_CLB2 0x2U // CLB2 +#define SYSCTL_DC6_CLB3 0x4U // CLB3 +#define SYSCTL_DC6_CLB4 0x8U // CLB4 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC7 register +// +//************************************************************************************************* +#define SYSCTL_DC7_SD1 0x1U // SD1 +#define SYSCTL_DC7_SD2 0x2U // SD2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC8 register +// +//************************************************************************************************* +#define SYSCTL_DC8_SCI_A 0x1U // SCI_A +#define SYSCTL_DC8_SCI_B 0x2U // SCI_B +#define SYSCTL_DC8_SCI_C 0x4U // SCI_C +#define SYSCTL_DC8_SCI_D 0x8U // SCI_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC9 register +// +//************************************************************************************************* +#define SYSCTL_DC9_SPI_A 0x1U // SPI_A +#define SYSCTL_DC9_SPI_B 0x2U // SPI_B +#define SYSCTL_DC9_SPI_C 0x4U // SPI_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC10 register +// +//************************************************************************************************* +#define SYSCTL_DC10_I2C_A 0x1U // I2C_A +#define SYSCTL_DC10_I2C_B 0x2U // I2C_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC11 register +// +//************************************************************************************************* +#define SYSCTL_DC11_CAN_A 0x1U // CAN_A +#define SYSCTL_DC11_CAN_B 0x2U // CAN_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC12 register +// +//************************************************************************************************* +#define SYSCTL_DC12_MCBSP_A 0x1U // McBSP_A +#define SYSCTL_DC12_MCBSP_B 0x2U // McBSP_B +#define SYSCTL_DC12_USB_A_S 16U +#define SYSCTL_DC12_USB_A_M 0x30000U // Decides the capability of the USB_A Module + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC13 register +// +//************************************************************************************************* +#define SYSCTL_DC13_UPP_A 0x1U // uPP_A + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC14 register +// +//************************************************************************************************* +#define SYSCTL_DC14_ADC_A 0x1U // ADC_A +#define SYSCTL_DC14_ADC_B 0x2U // ADC_B +#define SYSCTL_DC14_ADC_C 0x4U // ADC_C +#define SYSCTL_DC14_ADC_D 0x8U // ADC_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC15 register +// +//************************************************************************************************* +#define SYSCTL_DC15_CMPSS1 0x1U // CMPSS1 +#define SYSCTL_DC15_CMPSS2 0x2U // CMPSS2 +#define SYSCTL_DC15_CMPSS3 0x4U // CMPSS3 +#define SYSCTL_DC15_CMPSS4 0x8U // CMPSS4 +#define SYSCTL_DC15_CMPSS5 0x10U // CMPSS5 +#define SYSCTL_DC15_CMPSS6 0x20U // CMPSS6 +#define SYSCTL_DC15_CMPSS7 0x40U // CMPSS7 +#define SYSCTL_DC15_CMPSS8 0x80U // CMPSS8 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC17 register +// +//************************************************************************************************* +#define SYSCTL_DC17_DAC_A 0x10000U // Buffered-DAC_A +#define SYSCTL_DC17_DAC_B 0x20000U // Buffered-DAC_B +#define SYSCTL_DC17_DAC_C 0x40000U // Buffered-DAC_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC18 register +// +//************************************************************************************************* +#define SYSCTL_DC18_LS0_1 0x1U // LS0_1 +#define SYSCTL_DC18_LS1_1 0x2U // LS1_1 +#define SYSCTL_DC18_LS2_1 0x4U // LS2_1 +#define SYSCTL_DC18_LS3_1 0x8U // LS3_1 +#define SYSCTL_DC18_LS4_1 0x10U // LS4_1 +#define SYSCTL_DC18_LS5_1 0x20U // LS5_1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC19 register +// +//************************************************************************************************* +#define SYSCTL_DC19_LS0_2 0x1U // LS0_2 +#define SYSCTL_DC19_LS1_2 0x2U // LS1_2 +#define SYSCTL_DC19_LS2_2 0x4U // LS2_2 +#define SYSCTL_DC19_LS3_2 0x8U // LS3_2 +#define SYSCTL_DC19_LS4_2 0x10U // LS4_2 +#define SYSCTL_DC19_LS5_2 0x20U // LS5_2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC20 register +// +//************************************************************************************************* +#define SYSCTL_DC20_GS0 0x1U // GS0 +#define SYSCTL_DC20_GS1 0x2U // GS1 +#define SYSCTL_DC20_GS2 0x4U // GS2 +#define SYSCTL_DC20_GS3 0x8U // GS3 +#define SYSCTL_DC20_GS4 0x10U // GS4 +#define SYSCTL_DC20_GS5 0x20U // GS5 +#define SYSCTL_DC20_GS6 0x40U // GS6 +#define SYSCTL_DC20_GS7 0x80U // GS7 +#define SYSCTL_DC20_GS8 0x100U // GS8 +#define SYSCTL_DC20_GS9 0x200U // GS9 +#define SYSCTL_DC20_GS10 0x400U // GS10 +#define SYSCTL_DC20_GS11 0x800U // GS11 +#define SYSCTL_DC20_GS12 0x1000U // GS12 +#define SYSCTL_DC20_GS13 0x2000U // GS13 +#define SYSCTL_DC20_GS14 0x4000U // GS14 +#define SYSCTL_DC20_GS15 0x8000U // GS15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCNF1 register +// +//************************************************************************************************* +#define SYSCTL_PERCNF1_ADC_A_MODE 0x1U // ADC_A mode setting bit +#define SYSCTL_PERCNF1_ADC_B_MODE 0x2U // ADC_B mode setting bit +#define SYSCTL_PERCNF1_ADC_C_MODE 0x4U // ADC_C mode setting bit +#define SYSCTL_PERCNF1_ADC_D_MODE 0x8U // ADC_D mode setting bit +#define SYSCTL_PERCNF1_USB_A_PHY 0x10000U // USB_A_PHY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FUSEERR register +// +//************************************************************************************************* +#define SYSCTL_FUSEERR_ALERR_S 0U +#define SYSCTL_FUSEERR_ALERR_M 0x1FU // Efuse Autoload Error Status +#define SYSCTL_FUSEERR_ERR 0x20U // Efuse Self Test Error Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES0 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES0_CPU1_CLA1 0x1U // CPU1_CLA1 software reset bit +#define SYSCTL_SOFTPRES0_CPU2_CLA1 0x4U // CPU2_CLA1 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES1 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES1_EMIF1 0x1U // EMIF1 software reset bit +#define SYSCTL_SOFTPRES1_EMIF2 0x2U // EMIF2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES2 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES2_EPWM1 0x1U // EPWM1 software reset bit +#define SYSCTL_SOFTPRES2_EPWM2 0x2U // EPWM2 software reset bit +#define SYSCTL_SOFTPRES2_EPWM3 0x4U // EPWM3 software reset bit +#define SYSCTL_SOFTPRES2_EPWM4 0x8U // EPWM4 software reset bit +#define SYSCTL_SOFTPRES2_EPWM5 0x10U // EPWM5 software reset bit +#define SYSCTL_SOFTPRES2_EPWM6 0x20U // EPWM6 software reset bit +#define SYSCTL_SOFTPRES2_EPWM7 0x40U // EPWM7 software reset bit +#define SYSCTL_SOFTPRES2_EPWM8 0x80U // EPWM8 software reset bit +#define SYSCTL_SOFTPRES2_EPWM9 0x100U // EPWM9 software reset bit +#define SYSCTL_SOFTPRES2_EPWM10 0x200U // EPWM10 software reset bit +#define SYSCTL_SOFTPRES2_EPWM11 0x400U // EPWM11 software reset bit +#define SYSCTL_SOFTPRES2_EPWM12 0x800U // EPWM12 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES3 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES3_ECAP1 0x1U // ECAP1 software reset bit +#define SYSCTL_SOFTPRES3_ECAP2 0x2U // ECAP2 software reset bit +#define SYSCTL_SOFTPRES3_ECAP3 0x4U // ECAP3 software reset bit +#define SYSCTL_SOFTPRES3_ECAP4 0x8U // ECAP4 software reset bit +#define SYSCTL_SOFTPRES3_ECAP5 0x10U // ECAP5 software reset bit +#define SYSCTL_SOFTPRES3_ECAP6 0x20U // ECAP6 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES4 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES4_EQEP1 0x1U // EQEP1 software reset bit +#define SYSCTL_SOFTPRES4_EQEP2 0x2U // EQEP2 software reset bit +#define SYSCTL_SOFTPRES4_EQEP3 0x4U // EQEP3 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES6 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES6_SD1 0x1U // SD1 software reset bit +#define SYSCTL_SOFTPRES6_SD2 0x2U // SD2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES7 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES7_SCI_A 0x1U // SCI_A software reset bit +#define SYSCTL_SOFTPRES7_SCI_B 0x2U // SCI_B software reset bit +#define SYSCTL_SOFTPRES7_SCI_C 0x4U // SCI_C software reset bit +#define SYSCTL_SOFTPRES7_SCI_D 0x8U // SCI_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES8 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES8_SPI_A 0x1U // SPI_A software reset bit +#define SYSCTL_SOFTPRES8_SPI_B 0x2U // SPI_B software reset bit +#define SYSCTL_SOFTPRES8_SPI_C 0x4U // SPI_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES9 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES9_I2C_A 0x1U // I2C_A software reset bit +#define SYSCTL_SOFTPRES9_I2C_B 0x2U // I2C_B software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES11 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES11_MCBSP_A 0x1U // McBSP_A software reset bit +#define SYSCTL_SOFTPRES11_MCBSP_B 0x2U // McBSP_B software reset bit +#define SYSCTL_SOFTPRES11_USB_A 0x10000U // USB_A software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES13 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES13_ADC_A 0x1U // ADC_A software reset bit +#define SYSCTL_SOFTPRES13_ADC_B 0x2U // ADC_B software reset bit +#define SYSCTL_SOFTPRES13_ADC_C 0x4U // ADC_C software reset bit +#define SYSCTL_SOFTPRES13_ADC_D 0x8U // ADC_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES14 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES14_CMPSS1 0x1U // CMPSS1 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS2 0x2U // CMPSS2 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS3 0x4U // CMPSS3 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS4 0x8U // CMPSS4 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS5 0x10U // CMPSS5 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS6 0x20U // CMPSS6 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS7 0x40U // CMPSS7 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS8 0x80U // CMPSS8 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES16 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES16_DAC_A 0x10000U // Buffered_DAC_A software reset bit +#define SYSCTL_SOFTPRES16_DAC_B 0x20000U // Buffered_DAC_B software reset bit +#define SYSCTL_SOFTPRES16_DAC_C 0x40000U // Buffered_DAC_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL0 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL0_EPWM1 0x1U // EPWM1 CPU select bit +#define SYSCTL_CPUSEL0_EPWM2 0x2U // EPWM2 CPU select bit +#define SYSCTL_CPUSEL0_EPWM3 0x4U // EPWM3 CPU select bit +#define SYSCTL_CPUSEL0_EPWM4 0x8U // EPWM4 CPU select bit +#define SYSCTL_CPUSEL0_EPWM5 0x10U // EPWM5 CPU select bit +#define SYSCTL_CPUSEL0_EPWM6 0x20U // EPWM6 CPU select bit +#define SYSCTL_CPUSEL0_EPWM7 0x40U // EPWM7 CPU select bit +#define SYSCTL_CPUSEL0_EPWM8 0x80U // EPWM8 CPU select bit +#define SYSCTL_CPUSEL0_EPWM9 0x100U // EPWM9 CPU select bit +#define SYSCTL_CPUSEL0_EPWM10 0x200U // EPWM10 CPU select bit +#define SYSCTL_CPUSEL0_EPWM11 0x400U // EPWM11 CPU select bit +#define SYSCTL_CPUSEL0_EPWM12 0x800U // EPWM12 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL1_ECAP1 0x1U // ECAP1 CPU select bit +#define SYSCTL_CPUSEL1_ECAP2 0x2U // ECAP2 CPU select bit +#define SYSCTL_CPUSEL1_ECAP3 0x4U // ECAP3 CPU select bit +#define SYSCTL_CPUSEL1_ECAP4 0x8U // ECAP4 CPU select bit +#define SYSCTL_CPUSEL1_ECAP5 0x10U // ECAP5 CPU select bit +#define SYSCTL_CPUSEL1_ECAP6 0x20U // ECAP6 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL2_EQEP1 0x1U // EQEP1 CPU select bit +#define SYSCTL_CPUSEL2_EQEP2 0x2U // EQEP2 CPU select bit +#define SYSCTL_CPUSEL2_EQEP3 0x4U // EQEP3 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL4 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL4_SD1 0x1U // SD1 CPU select bit +#define SYSCTL_CPUSEL4_SD2 0x2U // SD2 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL5 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL5_SCI_A 0x1U // SCI_A CPU select bit +#define SYSCTL_CPUSEL5_SCI_B 0x2U // SCI_B CPU select bit +#define SYSCTL_CPUSEL5_SCI_C 0x4U // SCI_C CPU select bit +#define SYSCTL_CPUSEL5_SCI_D 0x8U // SCI_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL6 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL6_SPI_A 0x1U // SPI_A CPU select bit +#define SYSCTL_CPUSEL6_SPI_B 0x2U // SPI_B CPU select bit +#define SYSCTL_CPUSEL6_SPI_C 0x4U // SPI_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL7 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL7_I2C_A 0x1U // I2C_A CPU select bit +#define SYSCTL_CPUSEL7_I2C_B 0x2U // I2C_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL8 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL8_CAN_A 0x1U // CAN_A CPU select bit +#define SYSCTL_CPUSEL8_CAN_B 0x2U // CAN_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL9 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL9_MCBSP_A 0x1U // McBSP_A CPU select bit +#define SYSCTL_CPUSEL9_MCBSP_B 0x2U // McBSP_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL11 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL11_ADC_A 0x1U // ADC_A CPU select bit +#define SYSCTL_CPUSEL11_ADC_B 0x2U // ADC_B CPU select bit +#define SYSCTL_CPUSEL11_ADC_C 0x4U // ADC_C CPU select bit +#define SYSCTL_CPUSEL11_ADC_D 0x8U // ADC_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL12 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL12_CMPSS1 0x1U // CMPSS1 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS2 0x2U // CMPSS2 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS3 0x4U // CMPSS3 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS4 0x8U // CMPSS4 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS5 0x10U // CMPSS5 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS6 0x20U // CMPSS6 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS7 0x40U // CMPSS7 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS8 0x80U // CMPSS8 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL14 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL14_DAC_A 0x10000U // Buffered_DAC_A CPU select bit +#define SYSCTL_CPUSEL14_DAC_B 0x20000U // Buffered_DAC_B CPU select bit +#define SYSCTL_CPUSEL14_DAC_C 0x40000U // Buffered_DAC_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPU2RESCTL register +// +//************************************************************************************************* +#define SYSCTL_CPU2RESCTL_RESET 0x1U // CPU2 Reset Control bit +#define SYSCTL_CPU2RESCTL_KEY_S 16U +#define SYSCTL_CPU2RESCTL_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RSTSTAT register +// +//************************************************************************************************* +#define SYSCTL_RSTSTAT_CPU2RES 0x1U // CPU2 Reset Status bit +#define SYSCTL_RSTSTAT_CPU2NMIWDRST 0x2U // Indicates whether a CPU2.NMIWD reset was issued + // to CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST0 0x4U // Indicates whether a HWBIST reset was issued to + // CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST1 0x8U // Indicates whether a HWBIST reset was issued to + // CPU2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMSTAT register +// +//************************************************************************************************* +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_S 0U +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_M 0x3U // CPU2 LPM Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSDBGCTL register +// +//************************************************************************************************* +#define SYSCTL_SYSDBGCTL_BIT_0 0x1U // Used in PLL startup. Only reset by POR. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSEM register +// +//************************************************************************************************* +#define SYSCTL_CLKSEM_SEM_S 0U +#define SYSCTL_CLKSEM_SEM_M 0x3U // Semaphore for CLKCFG Ownership by CPU1 or CPU2 +#define SYSCTL_CLKSEM_KEY_S 16U +#define SYSCTL_CLKSEM_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL1 0x1U // Lock bit for CLKSRCCTL1 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL2 0x2U // Lock bit for CLKSRCCTL2 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL3 0x4U // Lock bit for CLKSRCCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL1 0x8U // Lock bit for SYSPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL2 0x10U // Lock bit for SYSPLLCTL2 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL3 0x20U // Lock bit for SYSPLLCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLMULT 0x40U // Lock bit for SYSPLLMULT register +#define SYSCTL_CLKCFGLOCK1_AUXPLLCTL1 0x80U // Lock bit for AUXPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_AUXPLLMULT 0x400U // Lock bit for AUXPLLMULT register +#define SYSCTL_CLKCFGLOCK1_SYSCLKDIVSEL 0x800U // Lock bit for SYSCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_AUXCLKDIVSEL 0x1000U // Lock bit for AUXCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_PERCLKDIVSEL 0x2000U // Lock bit for PERCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_LOSPCP 0x8000U // Lock bit for LOSPCP register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL1 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M 0x3U // OSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL1_INTOSC2OFF 0x8U // Internal Oscillator 2 Off Bit +#define SYSCTL_CLKSRCCTL1_XTALOFF 0x10U // Crystal (External) Oscillator Off Bit +#define SYSCTL_CLKSRCCTL1_WDHALTI 0x20U // Watchdog HALT Mode Ignore Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL2 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M 0x3U // AUXOSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_S 2U +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_M 0xCU // CANA Bit Clock Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S 4U +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M 0x30U // CANB Bit Clock Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL3 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_S 0U +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M 0x7U // XCLKOUT Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLCTL1_PLLEN 0x1U // SYSPLL enable/disable bit +#define SYSCTL_SYSPLLCTL1_PLLCLKEN 0x2U // SYSPLL bypassed or included in the PLLSYSCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLMULT_IMULT_S 0U +#define SYSCTL_SYSPLLMULT_IMULT_M 0x7FU // SYSPLL Integer Multiplier +#define SYSCTL_SYSPLLMULT_FMULT_S 8U +#define SYSCTL_SYSPLLMULT_FMULT_M 0x300U // SYSPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLSTS_LOCKS 0x1U // SYSPLL Lock Status Bit +#define SYSCTL_SYSPLLSTS_SLIPS 0x2U // SYSPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLCTL1_PLLEN 0x1U // AUXPLL enable/disable bit +#define SYSCTL_AUXPLLCTL1_PLLCLKEN 0x2U // AUXPLL bypassed or included in the AUXPLLCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLMULT_IMULT_S 0U +#define SYSCTL_AUXPLLMULT_IMULT_M 0x7FU // AUXPLL Integer Multiplier +#define SYSCTL_AUXPLLMULT_FMULT_S 8U +#define SYSCTL_AUXPLLMULT_FMULT_M 0x300U // AUXPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLSTS_LOCKS 0x1U // AUXPLL Lock Status Bit +#define SYSCTL_AUXPLLSTS_SLIPS 0x2U // AUXPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_S 0U +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M 0x3FU // PLLSYSCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_S 0U +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M 0x3U // AUXPLLCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_S 0U +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M 0x3U // EPWM Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV 0x10U // EMIF1 Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV 0x40U // EMIF2 Clock Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCLKOUTDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_S 0U +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M 0x3U // XCLKOUT Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOSPCP register +// +//************************************************************************************************* +#define SYSCTL_LOSPCP_LSPCLKDIV_S 0U +#define SYSCTL_LOSPCP_LSPCLKDIV_M 0x7U // LSPCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCDCR register +// +//************************************************************************************************* +#define SYSCTL_MCDCR_MCLKSTS 0x1U // Missing Clock Status Bit +#define SYSCTL_MCDCR_MCLKCLR 0x2U // Missing Clock Clear Bit +#define SYSCTL_MCDCR_MCLKOFF 0x4U // Missing Clock Detect Off Bit +#define SYSCTL_MCDCR_OSCOFF 0x8U // Oscillator Clock Off Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the X1CNT register +// +//************************************************************************************************* +#define SYSCTL_X1CNT_X1CNT_S 0U +#define SYSCTL_X1CNT_X1CNT_M 0x3FFU // X1 Counter + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSYSLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSYSLOCK1_HIBBOOTMODE 0x1U // Lock bit for HIBBOOTMODE register +#define SYSCTL_CPUSYSLOCK1_IORESTOREADDR 0x2U // Lock bit for IORESTOREADDR Register +#define SYSCTL_CPUSYSLOCK1_PIEVERRADDR 0x4U // Lock bit for PIEVERRADDR Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR0 0x8U // Lock bit for PCLKCR0 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR1 0x10U // Lock bit for PCLKCR1 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR2 0x20U // Lock bit for PCLKCR2 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR3 0x40U // Lock bit for PCLKCR3 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR4 0x80U // Lock bit for PCLKCR4 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR5 0x100U // Lock bit for PCLKCR5 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR6 0x200U // Lock bit for PCLKCR6 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR7 0x400U // Lock bit for PCLKCR7 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR8 0x800U // Lock bit for PCLKCR8 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR9 0x1000U // Lock bit for PCLKCR9 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR10 0x2000U // Lock bit for PCLKCR10 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR11 0x4000U // Lock bit for PCLKCR11 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR12 0x8000U // Lock bit for PCLKCR12 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR13 0x10000U // Lock bit for PCLKCR13 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR14 0x20000U // Lock bit for PCLKCR14 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR15 0x40000U // Lock bit for PCLKCR15 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR16 0x80000U // Lock bit for PCLKCR16 Register +#define SYSCTL_CPUSYSLOCK1_SECMSEL 0x100000U // Lock bit for SECMSEL Register +#define SYSCTL_CPUSYSLOCK1_LPMCR 0x200000U // Lock bit for LPMCR Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL0 0x400000U // Lock bit for GPIOLPMSEL0 Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL1 0x800000U // Lock bit for GPIOLPMSEL1 Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IORESTOREADDR register +// +//************************************************************************************************* +#define SYSCTL_IORESTOREADDR_ADDR_S 0U +#define SYSCTL_IORESTOREADDR_ADDR_M 0x3FFFFFU // restoreIO() routine address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEVERRADDR register +// +//************************************************************************************************* +#define SYSCTL_PIEVERRADDR_ADDR_S 0U +#define SYSCTL_PIEVERRADDR_ADDR_M 0x3FFFFFU // PIE Vector Fetch Error Handler Routine Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR0 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR0_CLA1 0x1U // CLA1 Clock Enable Bit +#define SYSCTL_PCLKCR0_DMA 0x4U // DMA Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER0 0x8U // CPUTIMER0 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER1 0x10U // CPUTIMER1 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER2 0x20U // CPUTIMER2 Clock Enable bit +#define SYSCTL_PCLKCR0_HRPWM 0x10000U // HRPWM Clock Enable Bit +#define SYSCTL_PCLKCR0_TBCLKSYNC 0x40000U // EPWM Time Base Clock sync +#define SYSCTL_PCLKCR0_GTBCLKSYNC 0x80000U // EPWM Time Base Clock Global sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR1 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR1_EMIF1 0x1U // EMIF1 Clock Enable bit +#define SYSCTL_PCLKCR1_EMIF2 0x2U // EMIF2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR2 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR2_EPWM1 0x1U // EPWM1 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM2 0x2U // EPWM2 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM3 0x4U // EPWM3 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM4 0x8U // EPWM4 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM5 0x10U // EPWM5 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM6 0x20U // EPWM6 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM7 0x40U // EPWM7 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM8 0x80U // EPWM8 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM9 0x100U // EPWM9 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM10 0x200U // EPWM10 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM11 0x400U // EPWM11 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM12 0x800U // EPWM12 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR3 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR3_ECAP1 0x1U // ECAP1 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP2 0x2U // ECAP2 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP3 0x4U // ECAP3 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP4 0x8U // ECAP4 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP5 0x10U // ECAP5 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP6 0x20U // ECAP6 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR4 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR4_EQEP1 0x1U // EQEP1 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP2 0x2U // EQEP2 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP3 0x4U // EQEP3 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR6 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR6_SD1 0x1U // SD1 Clock Enable bit +#define SYSCTL_PCLKCR6_SD2 0x2U // SD2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR7 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR7_SCI_A 0x1U // SCI_A Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_B 0x2U // SCI_B Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_C 0x4U // SCI_C Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_D 0x8U // SCI_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR8 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR8_SPI_A 0x1U // SPI_A Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_B 0x2U // SPI_B Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_C 0x4U // SPI_C Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR9 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR9_I2C_A 0x1U // I2C_A Clock Enable bit +#define SYSCTL_PCLKCR9_I2C_B 0x2U // I2C_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR10 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR10_CAN_A 0x1U // CAN_A Clock Enable bit +#define SYSCTL_PCLKCR10_CAN_B 0x2U // CAN_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR11 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR11_MCBSP_A 0x1U // McBSP_A Clock Enable bit +#define SYSCTL_PCLKCR11_MCBSP_B 0x2U // McBSP_B Clock Enable bit +#define SYSCTL_PCLKCR11_USB_A 0x10000U // USB_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR12 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR12_UPP_A 0x1U // uPP_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR13 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR13_ADC_A 0x1U // ADC_A Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_B 0x2U // ADC_B Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_C 0x4U // ADC_C Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_D 0x8U // ADC_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR14 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR14_CMPSS1 0x1U // CMPSS1 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS2 0x2U // CMPSS2 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS3 0x4U // CMPSS3 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS4 0x8U // CMPSS4 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS5 0x10U // CMPSS5 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS6 0x20U // CMPSS6 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS7 0x40U // CMPSS7 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS8 0x80U // CMPSS8 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR16 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR16_DAC_A 0x10000U // Buffered_DAC_A Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_B 0x20000U // Buffered_DAC_B Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_C 0x40000U // Buffered_DAC_C Clock Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECMSEL register +// +//************************************************************************************************* +#define SYSCTL_SECMSEL_PF1SEL_S 0U +#define SYSCTL_SECMSEL_PF1SEL_M 0x3U // Secondary Master Select for VBUS32_1 Bridge +#define SYSCTL_SECMSEL_PF2SEL_S 2U +#define SYSCTL_SECMSEL_PF2SEL_M 0xCU // Secondary Master Select for VBUS32_2 Bridge + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMCR register +// +//************************************************************************************************* +#define SYSCTL_LPMCR_LPM_S 0U +#define SYSCTL_LPMCR_LPM_M 0x3U // Low Power Mode setting +#define SYSCTL_LPMCR_QUALSTDBY_S 2U +#define SYSCTL_LPMCR_QUALSTDBY_M 0xFCU // STANDBY Wakeup Pin Qualification Setting +#define SYSCTL_LPMCR_WDINTE 0x8000U // Enable for WDINT wakeup from STANDBY +#define SYSCTL_LPMCR_M0M1MODE_S 16U +#define SYSCTL_LPMCR_M0M1MODE_M 0x30000U // Configuration for M0 and M1 mode during HIB +#define SYSCTL_LPMCR_IOISODIS 0x80000000U // IO Isolation Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL0 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL0_GPIO0 0x1U // GPIO0 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO1 0x2U // GPIO1 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO2 0x4U // GPIO2 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO3 0x8U // GPIO3 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO4 0x10U // GPIO4 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO5 0x20U // GPIO5 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO6 0x40U // GPIO6 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO7 0x80U // GPIO7 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO8 0x100U // GPIO8 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO9 0x200U // GPIO9 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO10 0x400U // GPIO10 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO11 0x800U // GPIO11 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO12 0x1000U // GPIO12 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO13 0x2000U // GPIO13 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO14 0x4000U // GPIO14 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO15 0x8000U // GPIO15 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO16 0x10000U // GPIO16 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO17 0x20000U // GPIO17 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO18 0x40000U // GPIO18 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO19 0x80000U // GPIO19 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO20 0x100000U // GPIO20 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO21 0x200000U // GPIO21 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO22 0x400000U // GPIO22 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO23 0x800000U // GPIO23 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO24 0x1000000U // GPIO24 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO25 0x2000000U // GPIO25 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO26 0x4000000U // GPIO26 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO27 0x8000000U // GPIO27 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO28 0x10000000U // GPIO28 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO29 0x20000000U // GPIO29 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO30 0x40000000U // GPIO30 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO31 0x80000000U // GPIO31 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL1 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL1_GPIO32 0x1U // GPIO32 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO33 0x2U // GPIO33 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO34 0x4U // GPIO34 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO35 0x8U // GPIO35 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO36 0x10U // GPIO36 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO37 0x20U // GPIO37 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO38 0x40U // GPIO38 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO39 0x80U // GPIO39 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO40 0x100U // GPIO40 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO41 0x200U // GPIO41 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO42 0x400U // GPIO42 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO43 0x800U // GPIO43 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO44 0x1000U // GPIO44 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO45 0x2000U // GPIO45 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO46 0x4000U // GPIO46 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO47 0x8000U // GPIO47 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO48 0x10000U // GPIO48 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO49 0x20000U // GPIO49 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO50 0x40000U // GPIO50 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO51 0x80000U // GPIO51 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO52 0x100000U // GPIO52 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO53 0x200000U // GPIO53 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO54 0x400000U // GPIO54 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO55 0x800000U // GPIO55 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO56 0x1000000U // GPIO56 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO57 0x2000000U // GPIO57 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO58 0x4000000U // GPIO58 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO59 0x8000000U // GPIO59 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO60 0x10000000U // GPIO60 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO61 0x20000000U // GPIO61 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO62 0x40000000U // GPIO62 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO63 0x80000000U // GPIO63 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TMR2CLKCTL register +// +//************************************************************************************************* +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S 0U +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M 0x7U // CPU Timer 2 Clock Source Select Bit +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S 3U +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M 0x38U // CPU Timer 2 Clock Pre-Scale Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RESC register +// +//************************************************************************************************* +#define SYSCTL_RESC_POR 0x1U // POR Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN 0x2U // XRSn Reset Cause Indication Bit +#define SYSCTL_RESC_WDRSN 0x4U // WDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_NMIWDRSN 0x8U // NMIWDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_HWBISTN 0x20U // HWBISTn Reset Cause Indication Bit +#define SYSCTL_RESC_HIBRESETN 0x40U // HIBRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_SCCRESETN 0x100U // SCCRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN_PIN_STATUS 0x40000000U // XRSN Pin Status +#define SYSCTL_RESC_TRSTN_PIN_STATUS 0x80000000U // TRSTn Status + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCSR register +// +//************************************************************************************************* +#define SYSCTL_SCSR_WDOVERRIDE 0x1U // WD Override for WDDIS bit +#define SYSCTL_SCSR_WDENINT 0x2U // WD Interrupt Enable +#define SYSCTL_SCSR_WDINTS 0x4U // WD Interrupt Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCNTR register +// +//************************************************************************************************* +#define SYSCTL_WDCNTR_WDCNTR_S 0U +#define SYSCTL_WDCNTR_WDCNTR_M 0xFFU // WD Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDKEY register +// +//************************************************************************************************* +#define SYSCTL_WDKEY_WDKEY_S 0U +#define SYSCTL_WDKEY_WDKEY_M 0xFFU // WD KEY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCR register +// +//************************************************************************************************* +#define SYSCTL_WDCR_WDPS_S 0U +#define SYSCTL_WDCR_WDPS_M 0x7U // WD Clock Prescalar +#define SYSCTL_WDCR_WDCHK_S 3U +#define SYSCTL_WDCR_WDCHK_M 0x38U // WD Check Bits +#define SYSCTL_WDCR_WDDIS 0x40U // WD Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDWCR register +// +//************************************************************************************************* +#define SYSCTL_WDWCR_MIN_S 0U +#define SYSCTL_WDWCR_MIN_M 0xFFU // WD Min Threshold setting for Windowed Watchdog + // functionality +#define SYSCTL_WDWCR_FIRSTKEY 0x100U // First Key Detect Flag + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL1 0x1U // CLA1TASKSRCSEL1 Register Lock bit +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL2 0x2U // CLA1TASKSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL1 0x1U // DMACHSRCSEL1 Register Lock bit +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL2 0x2U // DMACHSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_S 0U +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_M 0xFFU // Selects the Trigger Source for TASK1 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_S 8U +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_M 0xFF00U // Selects the Trigger Source for TASK2 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_S 16U +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_M 0xFF0000U // Selects the Trigger Source for TASK3 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_S 24U +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_M 0xFF000000U // Selects the Trigger Source for TASK4 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_S 0U +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_M 0xFFU // Selects the Trigger Source for TASK5 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_S 8U +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_M 0xFF00U // Selects the Trigger Source for TASK6 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_S 16U +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_M 0xFF0000U // Selects the Trigger Source for TASK7 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_S 24U +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_M 0xFF000000U // Selects the Trigger Source for TASK8 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL1_CH1_S 0U +#define SYSCTL_DMACHSRCSEL1_CH1_M 0xFFU // Selects the Trigger and Sync Source CH1 of DMA +#define SYSCTL_DMACHSRCSEL1_CH2_S 8U +#define SYSCTL_DMACHSRCSEL1_CH2_M 0xFF00U // Selects the Trigger and Sync Source CH2 of DMA +#define SYSCTL_DMACHSRCSEL1_CH3_S 16U +#define SYSCTL_DMACHSRCSEL1_CH3_M 0xFF0000U // Selects the Trigger and Sync Source CH3 of DMA +#define SYSCTL_DMACHSRCSEL1_CH4_S 24U +#define SYSCTL_DMACHSRCSEL1_CH4_M 0xFF000000U // Selects the Trigger and Sync Source CH4 of DMA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL2_CH5_S 0U +#define SYSCTL_DMACHSRCSEL2_CH5_M 0xFFU // Selects the Trigger and Sync Source CH5 of DMA +#define SYSCTL_DMACHSRCSEL2_CH6_S 8U +#define SYSCTL_DMACHSRCSEL2_CH6_M 0xFF00U // Selects the Trigger and Sync Source CH6 of DMA + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSELECT register +// +//************************************************************************************************* +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_S 0U +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_M 0x7U // Selects Sync Input Source for EPWM4 +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_S 3U +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_M 0x38U // Selects Sync Input Source for EPWM7 +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_S 6U +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_M 0x1C0U // Selects Sync Input Source for EPWM10 +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_S 9U +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_M 0xE00U // Selects Sync Input Source for ECAP1 +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_S 12U +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_M 0x7000U // Selects Sync Input Source for ECAP4 +#define SYSCTL_SYNCSELECT_SYNCOUT_S 27U +#define SYSCTL_SYNCSELECT_SYNCOUT_M 0x18000000U // Select Syncout Source + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOUTSELECT register +// +//************************************************************************************************* +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCAEN 0x1U // PWM1SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCAEN 0x2U // PWM2SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCAEN 0x4U // PWM3SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCAEN 0x8U // PWM4SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCAEN 0x10U // PWM5SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCAEN 0x20U // PWM6SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCAEN 0x40U // PWM7SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCAEN 0x80U // PWM8SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCAEN 0x100U // PWM9SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCAEN 0x200U // PWM10SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCAEN 0x400U // PWM11SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCAEN 0x800U // PWM12SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCBEN 0x10000U // PWM1SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCBEN 0x20000U // PWM2SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCBEN 0x40000U // PWM3SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCBEN 0x80000U // PWM4SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCBEN 0x100000U // PWM5SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCBEN 0x200000U // PWM6SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCBEN 0x400000U // PWM7SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCBEN 0x800000U // PWM8SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCBEN 0x1000000U // PWM9SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCBEN 0x2000000U // PWM10SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCBEN 0x4000000U // PWM11SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCBEN 0x8000000U // PWM12SOCBEN Enable for ADCSOCBO + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSOCLOCK register +// +//************************************************************************************************* +#define SYSCTL_SYNCSOCLOCK_SYNCSELECT 0x1U // SYNCSEL Register Lock bit +#define SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT 0x2U // ADCSOCOUTSELECT Register Lock bit + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_types.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_types.h new file mode 100644 index 0000000..8c1b32d --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_types.h @@ -0,0 +1,166 @@ +//########################################################################### +// +// FILE: hw_types.h +// +// TITLE: Type definitions used in driverlib functions. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_TYPES_H +#define HW_TYPES_H + +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#if defined(__TMS320C28XX_CLA__) + #define HWREG(x) \ + (*((volatile uint32_t *)((uintptr_t)(x)))) + #define HWREGH(x) \ + (*((volatile uint16_t *)((uintptr_t)(x)))) +#else + #define HWREG(x) \ + (*((volatile uint32_t *)(x))) + #define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#endif + +#define HWREG_BP(x) \ + __byte_peripheral_32((uint32_t *)(x)) +#define HWREGB(x) \ + __byte((int *)(x),0) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_S_SUCCESS (0) +#define STATUS_E_FAILURE (-1) + +//***************************************************************************** +// +// Definition of 8 bit types for USB Driver code to maintain portability +// between byte and word addressable cores of C2000 Devices. +// +//***************************************************************************** +typedef uint16_t uint8_t; +typedef int16_t int8_t; + +//**************************************************************************** +// +// For checking NULL pointers +// +//**************************************************************************** +#ifndef NULL +#define NULL ((void *)0x0) +#endif + +//***************************************************************************** +// +// 32-bit & 64-bit float type +// +//***************************************************************************** +#ifndef C2000_IEEE754_TYPES +#define C2000_IEEE754_TYPES +#ifdef __TI_EABI__ +typedef float float32_t; +typedef double float64_t; +#else // TI COFF +typedef float float32_t; +typedef long double float64_t; +#endif // __TI_EABI__ +#endif // C2000_IEEE754_TYPES + + +//***************************************************************************** +// +// Emulated Bitbanded write +// +//***************************************************************************** +#define HWREGBITW(address, mask, value) \ + (*(volatile uint32_t *)(address)) = \ + ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \ + | ((uint32_t)value << mask) + +#define HWREGBITHW(address, mask, value) \ + (*(volatile uint16_t *)(address)) = \ + ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \ + | ((uint16_t)value << mask) + +//***************************************************************************** +// +// Emulated Bitbanded read +// +//***************************************************************************** +#define HWREGBITR(address, mask) \ + (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask) + +#define HWREGBITHR(address, mask) \ + (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask) + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// These are provided to satisfy static analysis tools. The #ifndef is required +// because the '&' is for a C++-style reference, and although it is the correct +// prototype, it will not build in C code. +// +//***************************************************************************** +#if(defined(__TMS320C28XX__) || defined(__TMS320C28XX_CLA__)) +#else +extern int16_t &__byte(int16_t *array, uint16_t byte_index); +extern uint32_t &__byte_peripheral_32(uint32_t *x); +#endif + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +/* To fix Misra-C errors */ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif // HW_TYPES_H diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_upp.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_upp.h new file mode 100644 index 0000000..9f73e9b --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_upp.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: hw_upp.h +// +// TITLE: Definitions for the UPP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_UPP_H +#define HW_UPP_H + +//************************************************************************************************* +// +// The following are defines for the UPP register offsets +// +//************************************************************************************************* +#define UPP_O_PID 0x0U // Peripheral ID Register +#define UPP_O_PERCTL 0x2U // Peripheral Control Register +#define UPP_O_CHCTL 0x8U // General Control Register +#define UPP_O_IFCFG 0xAU // Interface Configuration Register +#define UPP_O_IFIVAL 0xCU // Interface Idle Value Register +#define UPP_O_THCFG 0xEU // Threshold Configuration Register +#define UPP_O_RAWINTST 0x10U // Raw Interrupt Status Register +#define UPP_O_ENINTST 0x12U // Enable Interrupt Status Register +#define UPP_O_INTENSET 0x14U // Interrupt Enable Set Register +#define UPP_O_INTENCLR 0x16U // Interrupt Enable Clear Register +#define UPP_O_CHIDESC0 0x20U // DMA Channel I Descriptor 0 Register +#define UPP_O_CHIDESC1 0x22U // DMA Channel I Descriptor 1 Register +#define UPP_O_CHIDESC2 0x24U // DMA Channel I Descriptor 2 Register +#define UPP_O_CHIST0 0x28U // DMA Channel I Status 0 Register +#define UPP_O_CHIST1 0x2AU // DMA Channel I Status 1 Register +#define UPP_O_CHIST2 0x2CU // DMA Channel I Status 2 Register +#define UPP_O_CHQDESC0 0x30U // DMA Channel Q Descriptor 0 Register +#define UPP_O_CHQDESC1 0x32U // DMA Channel Q Descriptor 1 Register +#define UPP_O_CHQDESC2 0x34U // DMA Channel Q Descriptor 2 Register +#define UPP_O_CHQST0 0x38U // DMA Channel Q Status 0 Register +#define UPP_O_CHQST1 0x3AU // DMA Channel Q Status 1 Register +#define UPP_O_CHQST2 0x3CU // DMA Channel Q Status 2 Register +#define UPP_O_GINTEN 0x40U // Global Peripheral Interrupt Enable Register +#define UPP_O_GINTFLG 0x42U // Global Peripheral Interrupt Flag Register +#define UPP_O_GINTCLR 0x44U // Global Peripheral Interrupt Clear Register +#define UPP_O_DLYCTL 0x46U // IO clock data skew control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCTL register +// +//************************************************************************************************* +#define UPP_PERCTL_FREE 0x1U // Emulation control. +#define UPP_PERCTL_SOFT 0x2U // Emulation control. +#define UPP_PERCTL_RTEMU 0x4U // Realtime emulation control. +#define UPP_PERCTL_PEREN 0x8U // Peripheral Enable +#define UPP_PERCTL_SOFTRST 0x10U // Software Reset +#define UPP_PERCTL_DMAST 0x80U // DMA Burst transaction status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHCTL register +// +//************************************************************************************************* +#define UPP_CHCTL_MODE_S 0U +#define UPP_CHCTL_MODE_M 0x3U // Operating mode +#define UPP_CHCTL_SDRTXILA 0x8U // SDR TX Interleve mode +#define UPP_CHCTL_DEMUXA 0x10U // DDR de-multiplexing mode +#define UPP_CHCTL_DRA 0x10000U // Data rate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFCFG register +// +//************************************************************************************************* +#define UPP_IFCFG_STARTPOLA 0x1U // Polarity of START(SELECT) signal +#define UPP_IFCFG_ENAPOLA 0x2U // Polarity of ENABLE(WRITE) signal +#define UPP_IFCFG_WAITPOLA 0x4U // Polarity of WAIT signal. +#define UPP_IFCFG_STARTA 0x8U // Enable Usage of START (SELECT) signal +#define UPP_IFCFG_ENAA 0x10U // Enable Usage of ENABLE (WRITE) signal +#define UPP_IFCFG_WAITA 0x20U // Enable Usage of WAIT signal +#define UPP_IFCFG_CLKDIVA_S 8U +#define UPP_IFCFG_CLKDIVA_M 0xF00U // Clock divider for tx mode +#define UPP_IFCFG_CLKINVA 0x1000U // Clock inversion +#define UPP_IFCFG_TRISENA 0x2000U // Pin Tri-state Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFIVAL register +// +//************************************************************************************************* +#define UPP_IFIVAL_VALA_S 0U +#define UPP_IFIVAL_VALA_M 0x1FFU // Idle Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the THCFG register +// +//************************************************************************************************* +#define UPP_THCFG_RDSIZEI_S 0U +#define UPP_THCFG_RDSIZEI_M 0x3U // DMA Read Threshold for DMA Channel I +#define UPP_THCFG_RDSIZEQ_S 8U +#define UPP_THCFG_RDSIZEQ_M 0x300U // DMA Read Threshold for DMA Channel Q +#define UPP_THCFG_TXSIZEA_S 16U +#define UPP_THCFG_TXSIZEA_M 0x30000U // I/O Transmit Threshold Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAWINTST register +// +//************************************************************************************************* +#define UPP_RAWINTST_DPEI 0x1U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEI 0x2U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWI 0x8U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLI 0x10U // Interrupt raw status for end-of-line condition +#define UPP_RAWINTST_DPEQ 0x100U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEQ 0x200U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWQ 0x800U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLQ 0x1000U // Interrupt raw status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ENINTST register +// +//************************************************************************************************* +#define UPP_ENINTST_DPEI 0x1U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEI 0x2U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWI 0x8U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLI 0x10U // Interrupt enable status for end-of-line condition +#define UPP_ENINTST_DPEQ 0x100U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEQ 0x200U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWQ 0x800U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLQ 0x1000U // Interrupt enable status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENSET register +// +//************************************************************************************************* +#define UPP_INTENSET_DPEI 0x1U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEI 0x2U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWI 0x8U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLI 0x10U // Interrupt enable for end-of-line condition +#define UPP_INTENSET_DPEQ 0x100U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEQ 0x200U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWQ 0x800U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLQ 0x1000U // Interrupt enable for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENCLR register +// +//************************************************************************************************* +#define UPP_INTENCLR_DPEI 0x1U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEI 0x2U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWI 0x8U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLI 0x10U // Interrupt clear for end-of-line condition +#define UPP_INTENCLR_DPEQ 0x100U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEQ 0x200U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWQ 0x800U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLQ 0x1000U // Interrupt clear for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC1 register +// +//************************************************************************************************* +#define UPP_CHIDESC1_BCNT_S 0U +#define UPP_CHIDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel I + // transfer. +#define UPP_CHIDESC1_LCNT_S 16U +#define UPP_CHIDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel I + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC2 register +// +//************************************************************************************************* +#define UPP_CHIDESC2_LOFFSET_S 0U +#define UPP_CHIDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST1 register +// +//************************************************************************************************* +#define UPP_CHIST1_BCNT_S 0U +#define UPP_CHIST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHIST1_LCNT_S 16U +#define UPP_CHIST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST2 register +// +//************************************************************************************************* +#define UPP_CHIST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHIST2_PEND 0x2U // Status of DMA. +#define UPP_CHIST2_WM_S 4U +#define UPP_CHIST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel I tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC1 register +// +//************************************************************************************************* +#define UPP_CHQDESC1_BCNT_S 0U +#define UPP_CHQDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel Q + // transfer. +#define UPP_CHQDESC1_LCNT_S 16U +#define UPP_CHQDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel Q + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC2 register +// +//************************************************************************************************* +#define UPP_CHQDESC2_LOFFSET_S 0U +#define UPP_CHQDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST1 register +// +//************************************************************************************************* +#define UPP_CHQST1_BCNT_S 0U +#define UPP_CHQST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHQST1_LCNT_S 16U +#define UPP_CHQST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST2 register +// +//************************************************************************************************* +#define UPP_CHQST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHQST2_PEND 0x2U // Status of DMA. +#define UPP_CHQST2_WM_S 4U +#define UPP_CHQST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel Q tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTEN register +// +//************************************************************************************************* +#define UPP_GINTEN_GINTEN 0x1U // Global Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTFLG register +// +//************************************************************************************************* +#define UPP_GINTFLG_GINTFLG 0x1U // Global Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTCLR register +// +//************************************************************************************************* +#define UPP_GINTCLR_GINTCLR 0x1U // Global Interrupt Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DLYCTL register +// +//************************************************************************************************* +#define UPP_DLYCTL_DLYDIS 0x1U // IO dealy control disable. +#define UPP_DLYCTL_DLYCTL_S 1U +#define UPP_DLYCTL_DLYCTL_M 0x6U // IO delay control. + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_usb.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_usb.h new file mode 100644 index 0000000..27907eb --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_usb.h @@ -0,0 +1,4614 @@ +//########################################################################### +// +// FILE: hw_usb.h +// +// TITLE: Definitions for the USB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_USB_H +#define HW_USB_H + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST +#define USB_IS_DISCON 0x00000020 // Session Disconnect +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt +#define USB_IE_SESREQ 0x00000040 // Enable Session Request +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO15_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. +// +//***************************************************************************** +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. +// +//***************************************************************************** +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL8_STALL 0x00000010 // Send STALL +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL8_ERROR 0x00000004 // Error +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. +// +//***************************************************************************** +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH8_MODE 0x00000020 // Mode +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL8_STALL 0x00000020 // Send STALL +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL8_OVER 0x00000004 // Overrun +#define USB_RXCSRL8_ERROR 0x00000004 // Error +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. +// +//***************************************************************************** +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. +// +//***************************************************************************** +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. +// +//***************************************************************************** +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL9_STALL 0x00000010 // Send STALL +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL9_ERROR 0x00000004 // Error +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH9_MODE 0x00000020 // Mode +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL9_STALL 0x00000020 // Send STALL +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL9_ERROR 0x00000004 // Error +#define USB_RXCSRL9_OVER 0x00000004 // Overrun +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. +// +//***************************************************************************** +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. +// +//***************************************************************************** +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. +// +//***************************************************************************** +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL10_STALL 0x00000010 // Send STALL +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL10_ERROR 0x00000004 // Error +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH10_MODE 0x00000020 // Mode +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL10_STALL 0x00000020 // Send STALL +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL10_OVER 0x00000004 // Overrun +#define USB_RXCSRL10_ERROR 0x00000004 // Error +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT10_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. +// +//***************************************************************************** +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. +// +//***************************************************************************** +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. +// +//***************************************************************************** +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. +// +//***************************************************************************** +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL11_STALL 0x00000010 // Send STALL +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL11_ERROR 0x00000004 // Error +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH11_MODE 0x00000020 // Mode +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL11_STALL 0x00000020 // Send STALL +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL11_OVER 0x00000004 // Overrun +#define USB_RXCSRL11_ERROR 0x00000004 // Error +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL12_STALL 0x00000010 // Send STALL +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL12_ERROR 0x00000004 // Error +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH12_MODE 0x00000020 // Mode +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL12_STALL 0x00000020 // Send STALL +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL12_ERROR 0x00000004 // Error +#define USB_RXCSRL12_OVER 0x00000004 // Overrun +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL13_STALL 0x00000010 // Send STALL +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL13_ERROR 0x00000004 // Error +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH13_MODE 0x00000020 // Mode +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL13_STALL 0x00000020 // Send STALL +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL13_OVER 0x00000004 // Overrun +#define USB_RXCSRL13_ERROR 0x00000004 // Error +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL14_STALL 0x00000010 // Send STALL +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL14_ERROR 0x00000004 // Error +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH14_MODE 0x00000020 // Mode +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL14_STALL 0x00000020 // Send STALL +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL14_OVER 0x00000004 // Overrun +#define USB_RXCSRL14_ERROR 0x00000004 // Error +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL15_STALL 0x00000010 // Send STALL +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL15_ERROR 0x00000004 // Error +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH15_MODE 0x00000020 // Mode +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL15_STALL 0x00000020 // Send STALL +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL15_ERROR 0x00000004 // Error +#define USB_RXCSRL15_OVER 0x00000004 // Overrun +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_TXFIFOADD register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_RXFIFOADD register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 + +#endif + +#endif // __HW_USB_H__ diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_xbar.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_xbar.h new file mode 100644 index 0000000..7869257 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_xbar.h @@ -0,0 +1,271 @@ +//########################################################################### +// +// FILE: hw_xbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XBAR_H +#define HW_XBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_FLG1 0x0U // X-Bar Input Flag Register 1 +#define XBAR_O_FLG2 0x2U // X-Bar Input Flag Register 2 +#define XBAR_O_FLG3 0x4U // X-Bar Input Flag Register 3 +#define XBAR_O_CLR1 0x8U // X-Bar Input Flag Clear Register 1 +#define XBAR_O_CLR2 0xAU // X-Bar Input Flag Clear Register 2 +#define XBAR_O_CLR3 0xCU // X-Bar Input Flag Clear Register 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG1 register +// +//************************************************************************************************* +#define XBAR_FLG1_CMPSS1_CTRIPL 0x1U // Input Flag for CMPSS1.CTRIPL Signal +#define XBAR_FLG1_CMPSS1_CTRIPH 0x2U // Input Flag for CMPSS1.CTRIPH Signal +#define XBAR_FLG1_CMPSS2_CTRIPL 0x4U // Input Flag for CMPSS2.CTRIPL Signal +#define XBAR_FLG1_CMPSS2_CTRIPH 0x8U // Input Flag for CMPSS2.CTRIPH Signal +#define XBAR_FLG1_CMPSS3_CTRIPL 0x10U // Input Flag for CMPSS3.CTRIPL Signal +#define XBAR_FLG1_CMPSS3_CTRIPH 0x20U // Input Flag for CMPSS3.CTRIPH Signal +#define XBAR_FLG1_CMPSS4_CTRIPL 0x40U // Input Flag for CMPSS4.CTRIPL Signal +#define XBAR_FLG1_CMPSS4_CTRIPH 0x80U // Input Flag for CMPSS4.CTRIPH Signal +#define XBAR_FLG1_CMPSS5_CTRIPL 0x100U // Input Flag for CMPSS5.CTRIPL Signal +#define XBAR_FLG1_CMPSS5_CTRIPH 0x200U // Input Flag for CMPSS5.CTRIPH Signal +#define XBAR_FLG1_CMPSS6_CTRIPL 0x400U // Input Flag for CMPSS6.CTRIPL Signal +#define XBAR_FLG1_CMPSS6_CTRIPH 0x800U // Input Flag for CMPSS6.CTRIPH Signal +#define XBAR_FLG1_CMPSS7_CTRIPL 0x1000U // Input Flag for CMPSS7.CTRIPL Signal +#define XBAR_FLG1_CMPSS7_CTRIPH 0x2000U // Input Flag for CMPSS7.CTRIPH Signal +#define XBAR_FLG1_CMPSS8_CTRIPL 0x4000U // Input Flag for CMPSS8.CTRIPL Signal +#define XBAR_FLG1_CMPSS8_CTRIPH 0x8000U // Input Flag for CMPSS8.CTRIPH Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag for CMPSS1.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag for CMPSS1.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag for CMPSS2.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag for CMPSS2.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag for CMPSS3.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag for CMPSS3.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag for CMPSS4.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag for CMPSS4.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag for CMPSS5.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag for CMPSS5.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag for CMPSS6.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag for CMPSS6.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag for CMPSS7.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag for CMPSS7.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag for CMPSS8.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG2 register +// +//************************************************************************************************* +#define XBAR_FLG2_INPUT1 0x1U // Input Flag for INPUT1 Signal +#define XBAR_FLG2_INPUT2 0x2U // Input Flag for INPUT2 Signal +#define XBAR_FLG2_INPUT3 0x4U // Input Flag for INPUT3 Signal +#define XBAR_FLG2_INPUT4 0x8U // Input Flag for INPUT4 Signal +#define XBAR_FLG2_INPUT5 0x10U // Input Flag for INPUT5 Signal +#define XBAR_FLG2_INPUT6 0x20U // Input Flag for INPUT6 Signal +#define XBAR_FLG2_ADCSOCAO 0x40U // Input Flag for ADCSOCAO Signal +#define XBAR_FLG2_ADCSOCBO 0x80U // Input Flag for ADCSOCBO Signal +#define XBAR_FLG2_CLB1_OUT4 0x100U // Input Flag for CLB1_OUT4 Signal +#define XBAR_FLG2_CLB1_OUT5 0x200U // Input Flag for CLB1_OUT5 Signal +#define XBAR_FLG2_CLB2_OUT4 0x400U // Input Flag for CLB2_OUT4 Signal +#define XBAR_FLG2_CLB2_OUT5 0x800U // Input Flag for CLB2_OUT5 Signal +#define XBAR_FLG2_CLB3_OUT4 0x1000U // Input Flag for CLB3_OUT4 Signal +#define XBAR_FLG2_CLB3_OUT5 0x2000U // Input Flag for CLB3_OUT5 Signal +#define XBAR_FLG2_CLB4_OUT4 0x4000U // Input Flag for CLB4_OUT4 Signal +#define XBAR_FLG2_CLB4_OUT5 0x8000U // Input Flag for CLB4_OUT5 Signal +#define XBAR_FLG2_ECAP1_OUT 0x10000U // Input Flag for ECAP1.OUT Signal +#define XBAR_FLG2_ECAP2_OUT 0x20000U // Input Flag for ECAP2.OUT Signal +#define XBAR_FLG2_ECAP3_OUT 0x40000U // Input Flag for ECAP3.OUT Signal +#define XBAR_FLG2_ECAP4_OUT 0x80000U // Input Flag for ECAP4.OUT Signal +#define XBAR_FLG2_ECAP5_OUT 0x100000U // Input Flag for ECAP5.OUT Signal +#define XBAR_FLG2_ECAP6_OUT 0x200000U // Input Flag for ECAP6.OUT Signal +#define XBAR_FLG2_EXTSYNCOUT 0x400000U // Input Flag for EXTSYNCOUT Signal +#define XBAR_FLG2_ADCAEVT1 0x800000U // Input Flag for ADCAEVT1 Signal +#define XBAR_FLG2_ADCAEVT2 0x1000000U // Input Flag for ADCAEVT2 Signal +#define XBAR_FLG2_ADCAEVT3 0x2000000U // Input Flag for ADCAEVT3 Signal +#define XBAR_FLG2_ADCAEVT4 0x4000000U // Input Flag for ADCAEVT4 Signal +#define XBAR_FLG2_ADCBEVT1 0x8000000U // Input Flag for ADCBEVT1 Signal +#define XBAR_FLG2_ADCBEVT2 0x10000000U // Input Flag for ADCBEVT2 Signal +#define XBAR_FLG2_ADCBEVT3 0x20000000U // Input Flag for ADCBEVT3 Signal +#define XBAR_FLG2_ADCBEVT4 0x40000000U // Input Flag for ADCBEVT4 Signal +#define XBAR_FLG2_ADCCEVT1 0x80000000U // Input Flag for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG3 register +// +//************************************************************************************************* +#define XBAR_FLG3_ADCCEVT2 0x1U // Input Flag for ADCCEVT2 Signal +#define XBAR_FLG3_ADCCEVT3 0x2U // Input Flag for ADCCEVT3 Signal +#define XBAR_FLG3_ADCCEVT4 0x4U // Input Flag for ADCCEVT4 Signal +#define XBAR_FLG3_ADCDEVT1 0x8U // Input Flag for ADCDEVT1 Signal +#define XBAR_FLG3_ADCDEVT2 0x10U // Input Flag for ADCDEVT2 Signal +#define XBAR_FLG3_ADCDEVT3 0x20U // Input Flag for ADCDEVT3 Signal +#define XBAR_FLG3_ADCDEVT4 0x40U // Input Flag for ADCDEVT4 Signal +#define XBAR_FLG3_SD1FLT1_COMPL 0x80U // Input Flag for SD1FLT1.COMPL Signal +#define XBAR_FLG3_SD1FLT1_COMPH 0x100U // Input Flag for SD1FLT1.COMPH Signal +#define XBAR_FLG3_SD1FLT2_COMPL 0x200U // Input Flag for SD1FLT2.COMPL Signal +#define XBAR_FLG3_SD1FLT2_COMPH 0x400U // Input Flag for SD1FLT2.COMPH Signal +#define XBAR_FLG3_SD1FLT3_COMPL 0x800U // Input Flag for SD1FLT3.COMPL Signal +#define XBAR_FLG3_SD1FLT3_COMPH 0x1000U // Input Flag for SD1FLT3.COMPH Signal +#define XBAR_FLG3_SD1FLT4_COMPL 0x2000U // Input Flag for SD1FLT4.COMPL Signal +#define XBAR_FLG3_SD1FLT4_COMPH 0x4000U // Input Flag for SD1FLT4.COMPH Signal +#define XBAR_FLG3_SD2FLT1_COMPL 0x8000U // Input Flag for SD2FLT1.COMPL Signal +#define XBAR_FLG3_SD2FLT1_COMPH 0x10000U // Input Flag for SD2FLT1.COMPH Signal +#define XBAR_FLG3_SD2FLT2_COMPL 0x20000U // Input Flag for SD2FLT2.COMPL Signal +#define XBAR_FLG3_SD2FLT2_COMPH 0x40000U // Input Flag for SD2FLT2.COMPH Signal +#define XBAR_FLG3_SD2FLT3_COMPL 0x80000U // Input Flag for SD2FLT3.COMPL Signal +#define XBAR_FLG3_SD2FLT3_COMPH 0x100000U // Input Flag for SD2FLT3.COMPH Signal +#define XBAR_FLG3_SD2FLT4_COMPL 0x200000U // Input Flag for SD2FLT4.COMPL Signal +#define XBAR_FLG3_SD2FLT4_COMPH 0x400000U // Input Flag for SD2FLT4.COMPH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR1 register +// +//************************************************************************************************* +#define XBAR_CLR1_CMPSS1_CTRIPL 0x1U // Input Flag Clear for CMPSS1.CTRIPL Signal +#define XBAR_CLR1_CMPSS1_CTRIPH 0x2U // Input Flag Clear for CMPSS1.CTRIPH Signal +#define XBAR_CLR1_CMPSS2_CTRIPL 0x4U // Input Flag Clear for CMPSS2.CTRIPL Signal +#define XBAR_CLR1_CMPSS2_CTRIPH 0x8U // Input Flag Clear for CMPSS2.CTRIPH Signal +#define XBAR_CLR1_CMPSS3_CTRIPL 0x10U // Input Flag Clear for CMPSS3.CTRIPL Signal +#define XBAR_CLR1_CMPSS3_CTRIPH 0x20U // Input Flag Clear for CMPSS3.CTRIPH Signal +#define XBAR_CLR1_CMPSS4_CTRIPL 0x40U // Input Flag Clear for CMPSS4.CTRIPL Signal +#define XBAR_CLR1_CMPSS4_CTRIPH 0x80U // Input Flag Clear for CMPSS4.CTRIPH Signal +#define XBAR_CLR1_CMPSS5_CTRIPL 0x100U // Input Flag Clear for CMPSS5.CTRIPL Signal +#define XBAR_CLR1_CMPSS5_CTRIPH 0x200U // Input Flag Clear for CMPSS5.CTRIPH Signal +#define XBAR_CLR1_CMPSS6_CTRIPL 0x400U // Input Flag Clear for CMPSS6.CTRIPL Signal +#define XBAR_CLR1_CMPSS6_CTRIPH 0x800U // Input Flag Clear for CMPSS6.CTRIPH Signal +#define XBAR_CLR1_CMPSS7_CTRIPL 0x1000U // Input Flag Clear for CMPSS7.CTRIPL Signal +#define XBAR_CLR1_CMPSS7_CTRIPH 0x2000U // Input Flag Clear for CMPSS7.CTRIPH Signal +#define XBAR_CLR1_CMPSS8_CTRIPL 0x4000U // Input Flag Clear for CMPSS8.CTRIPL Signal +#define XBAR_CLR1_CMPSS8_CTRIPH 0x8000U // Input Flag Clear for CMPSS8.CTRIPH Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag Clear for CMPSS1.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag Clear for CMPSS1.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag Clear for CMPSS2.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag Clear for CMPSS2.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag Clear for CMPSS3.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag Clear for CMPSS3.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag Clear for CMPSS4.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag Clear for CMPSS4.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag Clear for CMPSS5.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag Clear for CMPSS5.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag Clear for CMPSS6.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag Clear for CMPSS6.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag Clear for CMPSS7.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag Clear for CMPSS7.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag Clear for CMPSS8.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag Clear for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR2 register +// +//************************************************************************************************* +#define XBAR_CLR2_INPUT1 0x1U // Input Flag Clear for INPUT1 Signal +#define XBAR_CLR2_INPUT2 0x2U // Input Flag Clear for INPUT2 Signal +#define XBAR_CLR2_INPUT3 0x4U // Input Flag Clear for INPUT3 Signal +#define XBAR_CLR2_INPUT4 0x8U // Input Flag Clear for INPUT4 Signal +#define XBAR_CLR2_INPUT5 0x10U // Input Flag Clear for INPUT5 Signal +#define XBAR_CLR2_INPUT7 0x20U // Input Flag Clear for INPUT7 Signal +#define XBAR_CLR2_ADCSOCAO 0x40U // Input Flag Clear for ADCSOCAO Signal +#define XBAR_CLR2_ADCSOCBO 0x80U // Input Flag Clear for ADCSOCBO Signal +#define XBAR_CLR2_CLB1_OUT4 0x100U // Input Flag Clear for CLB1_OUT4 Signal +#define XBAR_CLR2_CLB1_OUT5 0x200U // Input Flag Clear for CLB1_OUT5 Signal +#define XBAR_CLR2_CLB2_OUT4 0x400U // Input Flag Clear for CLB2_OUT4 Signal +#define XBAR_CLR2_CLB2_OUT5 0x800U // Input Flag Clear for CLB2_OUT5 Signal +#define XBAR_CLR2_CLB3_OUT4 0x1000U // Input Flag Clear for CLB3_OUT4 Signal +#define XBAR_CLR2_CLB3_OUT5 0x2000U // Input Flag Clear for CLB3_OUT5 Signal +#define XBAR_CLR2_CLB4_OUT4 0x4000U // Input Flag Clear for CLB4_OUT4 Signal +#define XBAR_CLR2_CLB4_OUT5 0x8000U // Input Flag Clear for CLB4_OUT5 Signal +#define XBAR_CLR2_ECAP1_OUT 0x10000U // Input Flag Clear for ECAP1.OUT Signal +#define XBAR_CLR2_ECAP2_OUT 0x20000U // Input Flag Clear for ECAP2.OUT Signal +#define XBAR_CLR2_ECAP3_OUT 0x40000U // Input Flag Clear for ECAP3.OUT Signal +#define XBAR_CLR2_ECAP4_OUT 0x80000U // Input Flag Clear for ECAP4.OUT Signal +#define XBAR_CLR2_ECAP5_OUT 0x100000U // Input Flag Clear for ECAP5.OUT Signal +#define XBAR_CLR2_ECAP6_OUT 0x200000U // Input Flag Clear for ECAP6.OUT Signal +#define XBAR_CLR2_EXTSYNCOUT 0x400000U // Input Flag Clear for EXTSYNCOUT Signal +#define XBAR_CLR2_ADCAEVT1 0x800000U // Input Flag Clear for ADCAEVT1 Signal +#define XBAR_CLR2_ADCAEVT2 0x1000000U // Input Flag Clear for ADCAEVT2 Signal +#define XBAR_CLR2_ADCAEVT3 0x2000000U // Input Flag Clear for ADCAEVT3 Signal +#define XBAR_CLR2_ADCAEVT4 0x4000000U // Input Flag Clear for ADCAEVT4 Signal +#define XBAR_CLR2_ADCBEVT1 0x8000000U // Input Flag Clear for ADCBEVT1 Signal +#define XBAR_CLR2_ADCBEVT2 0x10000000U // Input Flag Clear for ADCBEVT2 Signal +#define XBAR_CLR2_ADCBEVT3 0x20000000U // Input Flag Clear for ADCBEVT3 Signal +#define XBAR_CLR2_ADCBEVT4 0x40000000U // Input Flag Clear for ADCBEVT4 Signal +#define XBAR_CLR2_ADCCEVT1 0x80000000U // Input Flag Clear for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR3 register +// +//************************************************************************************************* +#define XBAR_CLR3_ADCCEVT2 0x1U // Input Flag Clear for ADCCEVT2 Signal +#define XBAR_CLR3_ADCCEVT3 0x2U // Input Flag Clear for ADCCEVT3 Signal +#define XBAR_CLR3_ADCCEVT4 0x4U // Input Flag Clear for ADCCEVT4 Signal +#define XBAR_CLR3_ADCDEVT1 0x8U // Input Flag Clear for ADCDEVT1 Signal +#define XBAR_CLR3_ADCDEVT2 0x10U // Input Flag Clear for ADCDEVT2 Signal +#define XBAR_CLR3_ADCDEVT3 0x20U // Input Flag Clear for ADCDEVT3 Signal +#define XBAR_CLR3_ADCDEVT4 0x40U // Input Flag Clear for ADCDEVT4 Signal +#define XBAR_CLR3_SD1FLT1_COMPL 0x80U // Input Flag Clear for SD1FLT1.COMPL Signal +#define XBAR_CLR3_SD1FLT1_COMPH 0x100U // Input Flag Clear for SD1FLT1.COMPH Signal +#define XBAR_CLR3_SD1FLT2_COMPL 0x200U // Input Flag Clear for SD1FLT2.COMPL Signal +#define XBAR_CLR3_SD1FLT2_COMPH 0x400U // Input Flag Clear for SD1FLT2.COMPH Signal +#define XBAR_CLR3_SD1FLT3_COMPL 0x800U // Input Flag Clear for SD1FLT3.COMPL Signal +#define XBAR_CLR3_SD1FLT3_COMPH 0x1000U // Input Flag Clear for SD1FLT3.COMPH Signal +#define XBAR_CLR3_SD1FLT4_COMPL 0x2000U // Input Flag Clear for SD1FLT4.COMPL Signal +#define XBAR_CLR3_SD1FLT4_COMPH 0x4000U // Input Flag Clear for SD1FLT4.COMPH Signal +#define XBAR_CLR3_SD2FLT1_COMPL 0x8000U // Input Flag Clear for SD2FLT1.COMPL Signal +#define XBAR_CLR3_SD2FLT1_COMPH 0x10000U // Input Flag Clear for SD2FLT1.COMPH Signal +#define XBAR_CLR3_SD2FLT2_COMPL 0x20000U // Input Flag Clear for SD2FLT2.COMPL Signal +#define XBAR_CLR3_SD2FLT2_COMPH 0x40000U // Input Flag Clear for SD2FLT2.COMPH Signal +#define XBAR_CLR3_SD2FLT3_COMPL 0x80000U // Input Flag Clear for SD2FLT3.COMPL Signal +#define XBAR_CLR3_SD2FLT3_COMPH 0x100000U // Input Flag Clear for SD2FLT3.COMPH Signal +#define XBAR_CLR3_SD2FLT4_COMPL 0x200000U // Input Flag Clear for SD2FLT4.COMPL Signal +#define XBAR_CLR3_SD2FLT4_COMPH 0x400000U // Input Flag Clear for SD2FLT4.COMPH Signal + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/inc/hw_xint.h b/gpio_driverlib_cpu2/device/driverlib/inc/hw_xint.h new file mode 100644 index 0000000..677c2f9 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/inc/hw_xint.h @@ -0,0 +1,108 @@ +//########################################################################### +// +// FILE: hw_xint.h +// +// TITLE: Definitions for the XINT registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XINT_H +#define HW_XINT_H + +//************************************************************************************************* +// +// The following are defines for the XINT register offsets +// +//************************************************************************************************* +#define XINT_O_1CR 0x0U // XINT1 configuration register +#define XINT_O_2CR 0x1U // XINT2 configuration register +#define XINT_O_3CR 0x2U // XINT3 configuration register +#define XINT_O_4CR 0x3U // XINT4 configuration register +#define XINT_O_5CR 0x4U // XINT5 configuration register +#define XINT_O_1CTR 0x8U // XINT1 counter register +#define XINT_O_2CTR 0x9U // XINT2 counter register +#define XINT_O_3CTR 0xAU // XINT3 counter register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT1CR register +// +//************************************************************************************************* +#define XINT_1CR_ENABLE 0x1U // XINT1 Enable +#define XINT_1CR_POLARITY_S 2U +#define XINT_1CR_POLARITY_M 0xCU // XINT1 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT2CR register +// +//************************************************************************************************* +#define XINT_2CR_ENABLE 0x1U // XINT2 Enable +#define XINT_2CR_POLARITY_S 2U +#define XINT_2CR_POLARITY_M 0xCU // XINT2 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT3CR register +// +//************************************************************************************************* +#define XINT_3CR_ENABLE 0x1U // XINT3 Enable +#define XINT_3CR_POLARITY_S 2U +#define XINT_3CR_POLARITY_M 0xCU // XINT3 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT4CR register +// +//************************************************************************************************* +#define XINT_4CR_ENABLE 0x1U // XINT4 Enable +#define XINT_4CR_POLARITY_S 2U +#define XINT_4CR_POLARITY_M 0xCU // XINT4 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT5CR register +// +//************************************************************************************************* +#define XINT_5CR_ENABLE 0x1U // XINT5 Enable +#define XINT_5CR_POLARITY_S 2U +#define XINT_5CR_POLARITY_M 0xCU // XINT5 Polarity + + + +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/interrupt.c b/gpio_driverlib_cpu2/device/driverlib/interrupt.c new file mode 100644 index 0000000..4d628ce --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/interrupt.c @@ -0,0 +1,425 @@ +//########################################################################### +// +// FILE: interrupt.c +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Clears the IFR flag in the CPU. +//! +//! \param group specifies the interrupt group to be cleared. +//! +//! This function clears the IFR flag. This switch is needed because the +//! clearing of the IFR can only be done with a constant. +// +//***************************************************************************** +static void Interrupt_clearIFR(uint16_t group) +{ + switch(group) + { + case 0x0001U: + IFR &= ~(uint16_t)0x0001U; + break; + case 0x0002U: + IFR &= ~(uint16_t)0x0002U; + break; + case 0x0004U: + IFR &= ~(uint16_t)0x0004U; + break; + case 0x0008U: + IFR &= ~(uint16_t)0x0008U; + break; + case 0x0010U: + IFR &= ~(uint16_t)0x0010U; + break; + case 0x0020U: + IFR &= ~(uint16_t)0x0020U; + break; + case 0x0040U: + IFR &= ~(uint16_t)0x0040U; + break; + case 0x0080U: + IFR &= ~(uint16_t)0x0080U; + break; + case 0x0100U: + IFR &= ~(uint16_t)0x0100U; + break; + case 0x0200U: + IFR &= ~(uint16_t)0x0200U; + break; + case 0x0400U: + IFR &= ~(uint16_t)0x0400U; + break; + case 0x0800U: + IFR &= ~(uint16_t)0x0800U; + break; + case 0x1000U: + IFR &= ~(uint16_t)0x1000U; + break; + case 0x2000U: + IFR &= ~(uint16_t)0x2000U; + break; + case 0x4000U: + IFR &= ~(uint16_t)0x4000U; + break; + case 0x8000U: + IFR &= ~(uint16_t)0x8000U; + break; + default: + // + // Invalid group mask. + // + ASSERT((bool)false); + break; + } +} + +//***************************************************************************** +// +// Interrupt_initModule +// +//***************************************************************************** +void +Interrupt_initModule(void) +{ + // + // Disable and clear all interrupts at the CPU + // + (void)Interrupt_disableGlobal(); + IER = 0x0000U; + IFR = 0x0000U; + + // + // Clear all PIEIER registers + // + HWREGH(PIECTRL_BASE + PIE_O_IER1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER12) = 0U; + + // + // Clear all PIEIFR registers + // + HWREGH(PIECTRL_BASE + PIE_O_IFR1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR12) = 0U; + + // + // Enable vector fetching from PIE block + // + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; + +} + +//***************************************************************************** +// +//! The default interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_defaultHandler(void) +{ + uint16_t pieVect; + uint16_t vectID; + + // + // Calculate the vector ID. If the vector is in the lower PIE, it's the + // offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT) + // divided by two. + // + pieVect = HWREGH(PIECTRL_BASE + PIE_O_CTRL); + vectID = (pieVect & 0xFEU) >> 1U; + + // + // If the vector is in the upper PIE, the vector ID is 128 or higher. + // + if(pieVect >= 0x0E00U) + { + vectID += 128U; + } + + // + // Something has gone wrong. An interrupt without a proper registered + // handler function has occurred. To help you debug the issue, local + // variable vectID contains the vector ID of the interrupt that occurred. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default illegal instruction trap interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_illegalOperationHandler(void) +{ + // + // Something has gone wrong. The CPU has tried to execute an illegal + // instruction, generating an illegal instruction trap (ITRAP). + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default non-maskable interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_nmiHandler(void) +{ + // + // A non-maskable interrupt has occurred, indicating that a hardware error + // has occurred in the system. You can use SysCtl_getNMIFlagStatus() to + // to read the NMIFLG register and determine what caused the NMI. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +// Interrupt_initVectorTable +// +//***************************************************************************** +void +Interrupt_initVectorTable(void) +{ + uint16_t i; + + EALLOW; + + // + // We skip the first three locations because they are initialized by Boot + // ROM with boot variables. + // + for(i = 3U; i < 224U; i++) + { + HWREG(PIEVECTTABLE_BASE + (2U * i)) = + (uint32_t)Interrupt_defaultHandler; + } + + // + // NMI and ITRAP get their own handlers. + // + HWREG(PIEVECTTABLE_BASE + ((INT_NMI >> 16U) * 2U)) = + (uint32_t)Interrupt_nmiHandler; + HWREG(PIEVECTTABLE_BASE + ((INT_ILLEGAL >> 16U) * 2U)) = + (uint32_t)Interrupt_illegalOperationHandler; + + EDIS; +} + +//***************************************************************************** +// +//Interrupt_enable +// +//***************************************************************************** +void +Interrupt_enable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + // + // Globally disable interrupts but save status + // + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) |= + (uint16_t)1U << ((interruptNumber & 0xFFU) - 1U); + + // + // Enable PIE Group Interrupt + // + IER |= groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER |= (uint16_t)1U << (vectID - 1U); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} + +//***************************************************************************** +// +// Interrupt_disable +// +//***************************************************************************** +void +Interrupt_disable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + // + // Disable individual PIE interrupt + // + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) &= + ~(1U << ((interruptNumber & 0xFFUL) - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR(groupMask); + + // + // Acknowledge any interrupts + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER &= ~((uint16_t)1U << (vectID - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR((uint16_t)1U << (vectID - 1U)); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} diff --git a/gpio_driverlib_cpu2/device/driverlib/interrupt.h b/gpio_driverlib_cpu2/device/driverlib/interrupt.h new file mode 100644 index 0000000..05a555a --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/interrupt.h @@ -0,0 +1,497 @@ +//########################################################################### +// +// FILE: interrupt.h +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef INTERRUPT_H +#define INTERRUPT_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup interrupt_api Interrupt +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pie.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_enableInCPU() +// and Interrupt_disableInCPU() functions as the cpuInterrupt parameter. +// +//***************************************************************************** +#define INTERRUPT_CPU_INT1 0x1U //!< CPU Interrupt Number 1 +#define INTERRUPT_CPU_INT2 0x2U //!< CPU Interrupt Number 2 +#define INTERRUPT_CPU_INT3 0x4U //!< CPU Interrupt Number 3 +#define INTERRUPT_CPU_INT4 0x8U //!< CPU Interrupt Number 4 +#define INTERRUPT_CPU_INT5 0x10U //!< CPU Interrupt Number 5 +#define INTERRUPT_CPU_INT6 0x20U //!< CPU Interrupt Number 6 +#define INTERRUPT_CPU_INT7 0x40U //!< CPU Interrupt Number 7 +#define INTERRUPT_CPU_INT8 0x80U //!< CPU Interrupt Number 8 +#define INTERRUPT_CPU_INT9 0x100U //!< CPU Interrupt Number 9 +#define INTERRUPT_CPU_INT10 0x200U //!< CPU Interrupt Number 10 +#define INTERRUPT_CPU_INT11 0x400U //!< CPU Interrupt Number 11 +#define INTERRUPT_CPU_INT12 0x800U //!< CPU Interrupt Number 12 +#define INTERRUPT_CPU_INT13 0x1000U //!< CPU Interrupt Number 13 +#define INTERRUPT_CPU_INT14 0x2000U //!< CPU Interrupt Number 14 +#define INTERRUPT_CPU_DLOGINT 0x4000U //!< CPU Data Log Interrupt +#define INTERRUPT_CPU_RTOSINT 0x8000U //!< CPU RTOS Interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_clearACKGroup() +// function as the group parameter. +// +//***************************************************************************** +#define INTERRUPT_ACK_GROUP1 0x1U //!< Acknowledge PIE Interrupt Group 1 +#define INTERRUPT_ACK_GROUP2 0x2U //!< Acknowledge PIE Interrupt Group 2 +#define INTERRUPT_ACK_GROUP3 0x4U //!< Acknowledge PIE Interrupt Group 3 +#define INTERRUPT_ACK_GROUP4 0x8U //!< Acknowledge PIE Interrupt Group 4 +#define INTERRUPT_ACK_GROUP5 0x10U //!< Acknowledge PIE Interrupt Group 5 +#define INTERRUPT_ACK_GROUP6 0x20U //!< Acknowledge PIE Interrupt Group 6 +#define INTERRUPT_ACK_GROUP7 0x40U //!< Acknowledge PIE Interrupt Group 7 +#define INTERRUPT_ACK_GROUP8 0x80U //!< Acknowledge PIE Interrupt Group 8 +#define INTERRUPT_ACK_GROUP9 0x100U //!< Acknowledge PIE Interrupt Group 9 +#define INTERRUPT_ACK_GROUP10 0x200U //!< Acknowledge PIE Interrupt Group 10 +#define INTERRUPT_ACK_GROUP11 0x400U //!< Acknowledge PIE Interrupt Group 11 +#define INTERRUPT_ACK_GROUP12 0x800U //!< Acknowledge PIE Interrupt Group 12 +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler. The Interrupt_initVectorTable() +//! function sets all vectors to this function. Also, when an interrupt is +//! unregistered using the Interrupt_unregister() function, this handler takes +//! its place. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_defaultHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default illegal instruction trap interrupt handler. +//! +//! This is the default interrupt handler for an illegal instruction trap +//! (ITRAP). The Interrupt_initVectorTable() function sets the appropriate +//! vector to this function. This should never be called during normal +//! operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with +//! an appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_illegalOperationHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default non-maskable interrupt handler. +//! +//! This is the default interrupt handler for a non-maskable interrupt (NMI). +//! The Interrupt_initVectorTable() function sets the appropriate vector to +//! this function. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_nmiHandler(void); + +//***************************************************************************** +// +//! Allows the CPU to process interrupts. +//! +//! This function clears the global interrupt mask bit (INTM) in the CPU, +//! allowing the processor to respond to interrupts. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_enableGlobal(void) +{ + // + // Enable processor interrupts. + // + return(((__enable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Stops the CPU from processing interrupts. +//! +//! This function sets the global interrupt mask bit (INTM) in the CPU, +//! preventing the processor from receiving maskable interrupts. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_disableGlobal(void) +{ + // + // Disable processor interrupts. + // + return(((__disable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! \param handler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via Interrupt_enable()), the handler function will be +//! called in interrupt context. Since the handler function can preempt other +//! code, care must be taken to protect memory or peripherals that are accessed +//! by the handler and other non-handler code. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \note This function assumes that the PIE has been enabled. See +//! Interrupt_initModule(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_register(uint32_t interruptNumber, void (*handler)(void)) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)handler; + EDIS; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! +//! This function is used to indicate that a default handler +//! Interrupt_defaultHandler() should be called when the given interrupt is +//! asserted to the processor. Call Interrupt_disable() to disable +//! the interrupt before calling this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \sa Interrupt_register() for important information about registering +//! interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_unregister(uint32_t interruptNumber) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy default ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)Interrupt_defaultHandler; + EDIS; +} + +//***************************************************************************** +// +//! Enables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be enabled. +//! +//! This function enables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enableInCPU(uint16_t cpuInterrupt) +{ + // + // Set the interrupt bits in the CPU. + // + IER |= cpuInterrupt; +} + +//***************************************************************************** +// +//! Disables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be disabled. +//! +//! This function disables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disableInCPU(uint16_t cpuInterrupt) +{ + // + // Clear the interrupt bits in the CPU. + // + IER &= ~cpuInterrupt; +} + +//***************************************************************************** +// +//! Acknowledges PIE Interrupt Group +//! +//! \param group specifies the interrupt group to be acknowledged. +//! +//! The specified interrupt group is acknowledged and clears any interrupt +//! flag within that respective group. +//! +//! The \e group parameter must be a logical OR of the following: +//! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3 +//! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6 +//! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9 +//! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11, +//! \b INTERRUPT_ACK_GROUP12. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_clearACKGroup(uint16_t group) +{ + // + // Set interrupt group acknowledge bits + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = group; +} + +//***************************************************************************** +// +//! Enables the PIE block. +//! +//! This function enables the vector fetching for the peripheral interrupts by +//! enabling the PIE block. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Disables the PIE block. +//! +//! This function disables the vector fetching for the peripheral interrupts by +//! disabling the PIE block. PIEACK, PIEIFR, and PIEIER registers can be +//! accessed even when the PIE block is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) &= ~PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Initializes the PIE control registers by setting them to a known state. +//! +//! This function initializes the PIE control registers. After globally +//! disabling interrupts and enabling the PIE, it clears all of the PIE +//! interrupt enable bits and interrupt flags. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initModule(void); + +//***************************************************************************** +// +//! Initializes the PIE vector table by setting all vectors to a default +//! handler function. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initVectorTable(void); + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_enable(uint32_t interruptNumber); + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_disable(uint32_t interruptNumber); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // INTERRUPT_H diff --git a/gpio_driverlib_cpu2/device/driverlib/ipc.c b/gpio_driverlib_cpu2/device/driverlib/ipc.c new file mode 100644 index 0000000..8d6982e --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/ipc.c @@ -0,0 +1,445 @@ +//########################################################################### +// +// FILE: ipc.c +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ipc.h" + +// +// Macros internal to the IPC driver +// + +#define IPC_ADDR_OFFSET_NOCHANGE 2U +#define IPC_ADDR_OFFSET_MUL2 4U +#define IPC_ADDR_OFFSET_DIV2 1U + +#define IPC_ADDR_OFFSET_CORR(addr, corr) (((addr) * (corr)) / 2U) + +#if IPC_MSGQ_SUPPORT == 1U + +// +// Global Circular Buffer Definitions +// + + +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_PutBuffer, "MSGRAM_CPU1_TO_CPU2") +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_GetBuffer, "MSGRAM_CPU2_TO_CPU1") + +// +// IPC_CPU1_To_CPU2_PutBuffer acts as IPC_CPU2_To_CPU1_GetBuffer and +// IPC_CPU1_To_CPU2_GetBuffer acts as IPC_CPU2_To_CPU1_PutBuffer +// +IPC_PutBuffer_t IPC_CPU1_To_CPU2_PutBuffer; +IPC_GetBuffer_t IPC_CPU1_To_CPU2_GetBuffer; +#endif + +const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM] = { + + /* IPC_CPU1_L_CPU2_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = &IPC_CPU1_To_CPU2_PutBuffer, + .IPC_GetBuffer = &IPC_CPU1_To_CPU2_GetBuffer +#endif + }, + + /* IPC_CPU2_L_CPU1_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = (IPC_PutBuffer_t *)&IPC_CPU1_To_CPU2_GetBuffer, + .IPC_GetBuffer = (IPC_GetBuffer_t *)&IPC_CPU1_To_CPU2_PutBuffer +#endif + } +}; + +//***************************************************************************** +// +// IPC_sendCommand +// +//***************************************************************************** +bool IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data) +{ + bool ret; + + // + // Check whether the flags are not busy + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) == 0U) + { + ret = true; + + if(addrCorrEnable) + { + // + // Update the command registers. ADDR register holds the offset + // from the base address of the MSG RAM + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = + addr - IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + else + { + // + // Update the command registers. addr param remains as is. + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = addr; + } + + // + // Set the flags to indicate the remote core + // + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; + } + else + { + ret = false; + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readCommand +// +//***************************************************************************** +bool IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data) +{ + bool ret; + uint32_t addrReg; + + // + // Check whether the flags are not empty + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U) + { + ret = true; + + // + // Read the command registers + // + *command = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVCOM; + addrReg = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVADDR; + *data = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVDATA; + + if(addrCorrEnable) + { + // + // Calculate the address form the offset + // + *addr = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(addrReg, + IPC_Instance[ipcType].IPC_Offset_Corr); + + } + else + { + *addr = addrReg; + } + + } + else + { + ret = false; + } + + return(ret); +} + + +//***************************************************************************** +// +// IPC_registerInterrupt +// +//***************************************************************************** +void IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Register the interrupt handler + // + + Interrupt_register(intNum, pfnHandler); + + // + // Enable the interrupt + // + Interrupt_enable(intNum); +} + +//***************************************************************************** +// +// IPC_unregisterInterrupt +// +//***************************************************************************** +void IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Disable the interrupt. + // + Interrupt_disable(intNum); + + // + // Unregister the interrupt handler. + // + + Interrupt_unregister(intNum); +} + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// IPCinitMessageQueue +// +//***************************************************************************** +void IPC_initMessageQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(ipcInt_L < IPC_NUM_OF_INTERRUPTS); + ASSERT(ipcInt_R < IPC_NUM_OF_INTERRUPTS); + + IPC_PutBuffer_t *putBuffer = IPC_Instance[ipcType].IPC_PutBuffer; + IPC_GetBuffer_t *getBuffer = IPC_Instance[ipcType].IPC_GetBuffer; + + // + // L->R Put Buffer and Index Initialization + // + msgQueue->PutBuffer = putBuffer->Buffer[ipcInt_R]; + msgQueue->PutWriteIndex = &(putBuffer->PutWriteIndex[ipcInt_R]); + msgQueue->GetReadIndex = &(putBuffer->GetReadIndex[ipcInt_L]); + msgQueue->PutFlag = (uint32_t)1U << ipcInt_R; + + // + // L->R Get Buffer and Index Initialization + // + msgQueue->GetBuffer = getBuffer->Buffer[ipcInt_L]; + msgQueue->GetWriteIndex = &(getBuffer->GetWriteIndex[ipcInt_L]); + msgQueue->PutReadIndex = &(getBuffer->PutReadIndex[ipcInt_R]); + + // + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + // + *(msgQueue->PutWriteIndex) = 0U; + *(msgQueue->GetReadIndex) = 0U; +} + +//***************************************************************************** +// +// IPC_sendMessageToQueue +// +//***************************************************************************** +bool IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->PutWriteIndex); + readIndex = *(msgQueue->PutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while(((writeIndex + 1U) & IPC_MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + readIndex = *(msgQueue->PutReadIndex); + } + + if(ret != false) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + msgQueue->PutBuffer[writeIndex] = *msg; + + if(addrCorrEnable) + { + msgQueue->PutBuffer[writeIndex].address -= + IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + + writeIndex = (writeIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->PutWriteIndex) = writeIndex; + + IPC_setFlagLtoR(ipcType, msgQueue->PutFlag); + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readMessageFromQueue +// +//***************************************************************************** +bool IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->GetWriteIndex); + readIndex = *(msgQueue->GetReadIndex); + + // + // Loop while GetBuffer is empty + // + while(writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + writeIndex = *(msgQueue->GetWriteIndex); + } + + if(ret != false) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *msg = msgQueue->GetBuffer[readIndex]; + if(addrCorrEnable) + { + msg->address = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(msg->address, + IPC_Instance[ipcType].IPC_Offset_Corr); + } + + readIndex = (readIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->GetReadIndex) = readIndex; + } + + return(ret); +} +#endif diff --git a/gpio_driverlib_cpu2/device/driverlib/ipc.h b/gpio_driverlib_cpu2/device/driverlib/ipc.h new file mode 100644 index 0000000..8da7688 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/ipc.h @@ -0,0 +1,880 @@ +//########################################################################### +// +// FILE: ipc.h +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef IPC_H +#define IPC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ipc_api IPC +//! \brief This module is used for inter-processor communications. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "debug.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ipc.h" +#include "inc/hw_ints.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the APIs +// +//***************************************************************************** +//***************************************************************************** +// +// Driver configuration macros +// +//***************************************************************************** +#define IPC_MSGQ_SUPPORT 1U + +// +// Number of IPC messages in circular buffer (must be interval of 2) +// +#define IPC_BUFFER_SIZE 4U + +// +// Number of IPC interrupts using circular buffer (must be same number on both +// CPUs) +// +#define IPC_NUM_OF_INTERRUPTS 4U + +//***************************************************************************** +// +// Values that can be passed as parameter flags in all the IPC API functions. +// +//***************************************************************************** +#ifndef IPC_FLAGS_DEFINED +#define IPC_FLAGS_DEFINED +#define IPC_NO_FLAG 0x00000000U //!< NO FLAG +#define IPC_FLAG0 0x00000001U //!< IPC FLAG 0 +#define IPC_FLAG1 0x00000002U //!< IPC FLAG 1 +#define IPC_FLAG2 0x00000004U //!< IPC FLAG 2 +#define IPC_FLAG3 0x00000008U //!< IPC FLAG 3 +#define IPC_FLAG4 0x00000010U //!< IPC FLAG 4 +#define IPC_FLAG5 0x00000020U //!< IPC FLAG 5 +#define IPC_FLAG6 0x00000040U //!< IPC FLAG 6 +#define IPC_FLAG7 0x00000080U //!< IPC FLAG 7 +#define IPC_FLAG8 0x00000100U //!< IPC FLAG 8 +#define IPC_FLAG9 0x00000200U //!< IPC FLAG 9 +#define IPC_FLAG10 0x00000400U //!< IPC FLAG 10 +#define IPC_FLAG11 0x00000800U //!< IPC FLAG 11 +#define IPC_FLAG12 0x00001000U //!< IPC FLAG 12 +#define IPC_FLAG13 0x00002000U //!< IPC FLAG 13 +#define IPC_FLAG14 0x00004000U //!< IPC FLAG 14 +#define IPC_FLAG15 0x00008000U //!< IPC FLAG 15 +#define IPC_FLAG16 0x00010000U //!< IPC FLAG 16 +#define IPC_FLAG17 0x00020000U //!< IPC FLAG 17 +#define IPC_FLAG18 0x00040000U //!< IPC FLAG 18 +#define IPC_FLAG19 0x00080000U //!< IPC FLAG 19 +#define IPC_FLAG20 0x00100000U //!< IPC FLAG 20 +#define IPC_FLAG21 0x00200000U //!< IPC FLAG 21 +#define IPC_FLAG22 0x00400000U //!< IPC FLAG 22 +#define IPC_FLAG23 0x00800000U //!< IPC FLAG 23 +#define IPC_FLAG24 0x01000000U //!< IPC FLAG 24 +#define IPC_FLAG25 0x02000000U //!< IPC FLAG 25 +#define IPC_FLAG26 0x04000000U //!< IPC FLAG 26 +#define IPC_FLAG27 0x08000000U //!< IPC FLAG 27 +#define IPC_FLAG28 0x10000000U //!< IPC FLAG 28 +#define IPC_FLAG29 0x20000000U //!< IPC FLAG 29 +#define IPC_FLAG30 0x40000000U //!< IPC FLAG 30 +#define IPC_FLAG31 0x80000000U //!< IPC FLAG 31 +#define IPC_FLAG_ALL 0xFFFFFFFFU //!< All IPC flags +#endif + +//***************************************************************************** +// +// Values that can be passed as parameter ipcInt in +// IPC_registerInterrupt and IPC_unregisterInterrupt functions. +// Please refer to the datasheet for the actual number of interrupts available +// for each IPC instance +// +//***************************************************************************** +#define IPC_INT0 0x0U //!< IPC Interrupt 0 +#define IPC_INT1 0x1U //!< IPC Interrupt 1 +#define IPC_INT2 0x2U //!< IPC Interrupt 2 +#define IPC_INT3 0x3U //!< IPC Interrupt 3 +#define IPC_INT4 0x4U //!< IPC Interrupt 4 +#define IPC_INT5 0x5U //!< IPC Interrupt 5 +#define IPC_INT6 0x6U //!< IPC Interrupt 6 +#define IPC_INT7 0x7U //!< IPC Interrupt 7 + +//***************************************************************************** +// +// Values that can be passed as parameter addrCorrEnable in +// IPC_sendCommand, IPC_readCommand, IPC_sendMessageToQueue and +// IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_ADDR_CORRECTION_ENABLE true +#define IPC_ADDR_CORRECTION_DISABLE false + +//***************************************************************************** +// +// Values that can be passed as parameter block in +// IPC_sendMessageToQueue and IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_BLOCKING_CALL true +#define IPC_NONBLOCKING_CALL false + + + +//***************************************************************************** +// +// Internal macros used for message queue implementation +// +//***************************************************************************** +#define IPC_MAX_BUFFER_INDEX (IPC_BUFFER_SIZE - 1U) + +//***************************************************************************** +// +// Enums for the APIs +// +//***************************************************************************** + +//***************************************************************************** +// +//! Values that can be passed as parameter \e ipcType in all the driver +//! functions +// +//***************************************************************************** +typedef enum +{ + IPC_CPU1_L_CPU2_R, //!< CPU1 - Local core, CPU2 - Remote core + IPC_CPU2_L_CPU1_R, //!< CPU2 - Local core, CPU1 - Remote core + IPC_TOTAL_NUM +}IPC_Type_t; + +//***************************************************************************** +// +// Internal structs for register and messaage queue accesses +// +//***************************************************************************** +typedef struct +{ + uint32_t IPC_ACK; + uint32_t IPC_STS; + uint32_t IPC_SET; + uint32_t IPC_CLR; + uint32_t IPC_FLG; + uint32_t IPC_RSVDREG; + uint32_t IPC_COUNTERL; + uint32_t IPC_COUNTERH; +}IPC_Flag_Ctr_Reg_t; + +typedef struct +{ + uint32_t IPC_SENDCOM; + uint32_t IPC_SENDADDR; + uint32_t IPC_SENDDATA; + uint32_t IPC_REMOTEREPLY; +}IPC_SendCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_RECVCOM; + uint32_t IPC_RECVADDR; + uint32_t IPC_RECVDATA; + uint32_t IPC_LOCALREPLY; +}IPC_RecvCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_BOOTSTS; + uint32_t IPC_BOOTMODE; +}IPC_Boot_Pump_Reg_t; + +#if IPC_MSGQ_SUPPORT == 1U +typedef struct +{ + uint32_t command; + uint32_t address; + uint32_t dataw1; + uint32_t dataw2; +}IPC_Message_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t PutWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t GetReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_PutBuffer_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t GetWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t PutReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_GetBuffer_t; +#endif + +//***************************************************************************** +// +// Internal struct used to store the required information regarding an IPC +// instance +// +//***************************************************************************** +typedef struct +{ + volatile IPC_Flag_Ctr_Reg_t *IPC_Flag_Ctr_Reg; + volatile IPC_SendCmd_Reg_t *IPC_SendCmd_Reg; + volatile IPC_RecvCmd_Reg_t *IPC_RecvCmd_Reg; + volatile IPC_Boot_Pump_Reg_t *IPC_Boot_Pump_Reg; + uint32_t IPC_IntNum[8U]; + uint32_t IPC_MsgRam_LtoR; + uint32_t IPC_MsgRam_RtoL; + uint32_t IPC_Offset_Corr; +#if IPC_MSGQ_SUPPORT == 1U + IPC_PutBuffer_t *IPC_PutBuffer; + IPC_GetBuffer_t *IPC_GetBuffer; +#endif +}IPC_Instance_t; + +extern const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM]; + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// A structure that defines an IPC message queue. These +// fields are used by the IPC drivers, and normally it is not necessary for +// user software to directly read or write fields in the table. +// +//***************************************************************************** + +typedef struct +{ + IPC_Message_t * PutBuffer; + uint32_t PutFlag; + uint16_t * PutWriteIndex; + uint16_t * PutReadIndex; + IPC_Message_t * GetBuffer; + uint16_t * GetWriteIndex; + uint16_t * GetReadIndex; +} IPC_MessageQueue_t; +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! Local core sets Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being set +//! +//! This function will allow the Local core system to set the designated IPC +//! flags to send to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; +} + +//***************************************************************************** +// +//! Local core clears Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being cleared +//! +//! This function will allow the Local core system to clear the designated IPC +//! flags sent to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_clearFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_CLR = flags; +} + +//***************************************************************************** +// +//! Local core acknowledges Remote to Local IPC Flag. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being acknowledged. +//! +//! This function will allow the Local core system to acknowledge/clear the IPC +//! flag set by the Remote core system. The \e flags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_ackFlagRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_ACK = flags; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Local to Remote IPC flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Local to Remote +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) != 0U); +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Remote to Local IPC Flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Remote to Local +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U); +} + +//***************************************************************************** +// +//! Wait for the remote core to send a flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the Remote to Local IPC flag mask to wait for +//! +//! Allows the caller to wait for the Remote to Local flag to be send by +//! the remote core. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForFlag(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flag) == 0U) + { + } +} + +//***************************************************************************** +// +//! Wait for the IPC flag to be acknowledged +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask for which ack is pending +//! +//! Allows the caller to wait for the IPC flag to be acknowledged by the +//! remote core. The \e flagsparameter can be any of the IPC flag values: +//! \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForAck(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flag) != 0U) + { + } +} + +//***************************************************************************** +// +//! Synchronises the two cores +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask with which synchronisation is done +//! +//! Allows the local and remote cores to synchronise. Neither core will return +//! from this function call before the other core enters it. +//! +//! \note Must be called with same flag mask on both the cores +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_sync(IPC_Type_t ipcType, uint32_t flag) +{ + IPC_setFlagLtoR(ipcType, flag); + IPC_waitForFlag(ipcType, flag); + IPC_ackFlagRtoL(ipcType, flag); + IPC_waitForAck(ipcType, flag); +} + +//***************************************************************************** +// +//! Initialize IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +// +//! This function initializes IPC by clearing all the flags +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_init(IPC_Type_t ipcType) +{ + IPC_clearFlagLtoR(ipcType, IPC_FLAG_ALL); +} + +//***************************************************************************** +// +//! Sends a command to the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags to be set +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit command value +//! \param addr is the 32-bit address to be sent as part of command +//! \param data is the 32-bit data to be sent as part of command +//! +//! Allows the caller to send a command to the remote core. A command consists +//! of a unique command value, a 32-bit address and a 32-bit data. The function +//! also sends the designated flags to the remote core. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! The application shall use the function IPC_getResponse to read the response +//! sent by the remote core. +//! +//! \note The application is expected to wait until the the response is +//! received before sending another command. +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is sent properly and \b false if +//! the designated flags were busy and hence command was not sent. +// +//***************************************************************************** +extern bool +IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data); + +//***************************************************************************** +// +//! Reads a command sent by the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags sent by the remote core +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit pointer at which the command value is read to +//! \param addr is the 32-bit pointer at which address value is read to +//! \param data is the 32-bit pointer at which the data is read to +//! +//! Allows the caller to read a command sent by the remote core. A command +//! consists of a unique command value, a 32-bit address and a 32-bit data. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! \note The application is expected to acknowledge the flag and send a +//! response (if needed) after reading the command +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is read properly and \b false if +//! the designated flags were empty and hence command was not read. +// +//***************************************************************************** +extern bool +IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data); + +//***************************************************************************** +// +//! Sends the response to the command sent by remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param data is the 32-bit value of the response to be sent +//! +//! Allows the caller to send a response to the command previously sent by the +//! remote core +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_sendResponse(IPC_Type_t ipcType, uint32_t data) +{ + IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_LOCALREPLY = data; +} + +//***************************************************************************** +// +//! Reads the response from the remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the response sent by the remote core to the +//! command previously sent by the local core +//! +//! \return the 32-bit value of the response. +// +//***************************************************************************** +static inline uint32_t +IPC_getResponse(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_REMOTEREPLY); +} + +//***************************************************************************** +// +//! Sets the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param mode is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! \note This function shall be called by CPU1 only. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_setBootMode(IPC_Type_t ipcType, uint32_t mode) +{ + ASSERT(ipcType == IPC_CPU1_L_CPU2_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE = mode; +} + +//***************************************************************************** +// +//! Reads the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTMODE register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootMode(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE); +} + +//***************************************************************************** +// +//! Sets the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param status is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTSTS register. +//! +//! \note This function shall be called by CPU2 and CM only +//! +//! \note This function shall be called by CPU2 only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setBootStatus(IPC_Type_t ipcType, uint32_t status) +{ + ASSERT(ipcType == IPC_CPU2_L_CPU1_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS = status; +} + +//***************************************************************************** +// +//! Reads the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTSTS register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootStatus(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS); +} + +//***************************************************************************** +// +//! Reads the timestamp counter value. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the IPC timestamp counter value. +//! +//! \return 64-bit counter value. +// +//***************************************************************************** +static inline uint64_t +IPC_getCounter(IPC_Type_t ipcType) +{ + // + // Get the Counter High and Low values. Read to the Counter low register + // saves the value of Counter High register. + // + uint32_t ctrL = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERL; + uint32_t ctrH = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERH; + + // + // Return the 64-bit value of the counter + // + return(((uint64_t)ctrH << 32) | ((uint64_t)ctrL)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being registered +//! \param pfnHandler is the pointer to ISR function +//! +//! This function registers the handler to be called when an IPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! Unregisters an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being unregistered +//! +//! This function clears the handler to be called when an IPC interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt); + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +//! Initializes the IPC message queue +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param ipcInt_L specifies the interrupt number on the local core used by +//! the message queue . +//! \param ipcInt_R specifies the interrupt number on the remote core used by +//! the message queue. +//! +//! This function initializes the IPC message queue with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e ipcInt_L and \e ipcInt_R parameters can be one of the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e IPC_MessageQueue_t +//! instance, that particular interrupt should not be tied to a second +//! \e IPC_MessageQueue_t instance. +//! +//! \note For a particular ipcInt_L - ipcInt_R pair, there must be an instance +//! of IPC_MessageQueue_t defined and initialized on both the locakl and remote +//! systems. +//! +//! \return None. +// +//***************************************************************************** +extern void +IPC_initMessageQueue(IPC_Type_t ipcType, volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R); + +//***************************************************************************** +// +//! Sends a message into the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to be +//! sent to message queue. +//! \param block specifies whether to allow function to block until the buffer +//! has a free slot +//! +//! This function checks if there is a free slot in the message queue. If so, it +//! puts the message pointed to by \e msg into the free and sets the +//! appropriate IPC interrupt flag +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is full. \b true if the message is +//! successfully sent. +// +//***************************************************************************** +extern bool +IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); + +//***************************************************************************** +// +//! Reads a message from the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to which +//! the message needs to be read +//! \param block specifies whether to allow function to block until a message +//! is available in the message queue +//! +//! This function checks if there is a message in the message queue. If so, it +//! reads the message and writes to the address pointed to by \e msg into. +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is empty. \b true if the message successfully +//! read. +// +//***************************************************************************** +extern bool +IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); +#endif +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // IPC_H diff --git a/gpio_driverlib_cpu2/device/driverlib/mcbsp.c b/gpio_driverlib_cpu2/device/driverlib/mcbsp.c new file mode 100644 index 0000000..4b23940 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/mcbsp.c @@ -0,0 +1,1621 @@ +//########################################################################### +// +// FILE: mcbsp.c +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "mcbsp.h" + +//***************************************************************************** +// +// McBSP_transmit16BitdataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit16BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_setRxDataSize +// +//***************************************************************************** +void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word , write to RWDLEN1 and words per frame , write to + // RFRLEN1. + // + HWREGH(base + MCBSP_O_RCR1) = + ((HWREGH(base + MCBSP_O_RCR1) & ~MCBSP_RCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR1_RFRLEN1_S))); + } + else + { + // + // Set bits per word , write to RWDLEN2 and words per frame, write to + // RFRLEN2. + // + HWREGH(base + MCBSP_O_RCR2) = + ((HWREGH(base + MCBSP_O_RCR2) & ~MCBSP_RCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR2_RFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_setTxDataSize +// +//***************************************************************************** +void +McBSP_setTxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word XWDLEN1 and words per frame XFRLEN1. + // + HWREGH(base + MCBSP_O_XCR1) = + ((HWREGH(base + MCBSP_O_XCR1) & ~MCBSP_XCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR1_XFRLEN1_S))); + } + else + { + // + // Set bits per word XWDLEN2 and words per frame XFRLEN2. + // + HWREGH(base + MCBSP_O_XCR2) = + ((HWREGH(base + MCBSP_O_XCR2) & ~MCBSP_XCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR2_XFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_disableRxChannel +// +//***************************************************************************** +void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableRxChannel +// +//***************************************************************************** +void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_disableTxChannel +// +//***************************************************************************** +void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableTxChannel +// +//***************************************************************************** +void McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine wheter it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_configureTxClock +// +//***************************************************************************** +void +McBSP_configureTxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select TX clock source as SRG or External. + // + McBSP_setTxClockSource(base, + (McBSP_TxClockSource)ptrClockParams->clockSourceTx); + + // + // Check if using SRG to drive Transmitter clock. + // + if((McBSP_TxClockSource)ptrClockParams->clockSourceTx == + MCBSP_INTERNAL_TX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setTxSRGClockSource(base, + (McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource); + + // + // Check if SRG is clocked from MCLKR pin. GSYNC feature can be enabled + // in this case as SRG input clock source is MCLKR pin. + // + if((McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource == + MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); + + // + // Check if SRG is to be synced with FSR that is GSYNC is to be + // enabled or not. + // + if(ptrClockParams->clockSRGSyncFlag) + { + McBSP_enableSRGSyncFSR(base); + } + else + { + McBSP_disableSRGSyncFSR(base); + } + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKX. + // Output polarity if using SRG as clock source. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); +} + +//***************************************************************************** +// +// McBSP_configureRxClock +// +//***************************************************************************** +void +McBSP_configureRxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select RX clock source as SRG or External. + // + McBSP_setRxClockSource(base, + (McBSP_RxClockSource)ptrClockParams->clockSourceRx); + + // + // Check if using SRG to drive Receiver clock. + // + if((McBSP_RxClockSource)ptrClockParams->clockSourceRx == + MCBSP_INTERNAL_RX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setRxSRGClockSource(base, + (McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource); + + // + // Check if SRG is clocked from MCLKX pin. GSYNC cannot be enabled in + // this case as GSYNC feature can be used only when SRG clock source is + // MCLKR pin. + // + if((McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource == + MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKR. + // Output polarity if using SRG as clock source. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); +} + +//***************************************************************************** +// +// McBSP_configureTxFrameSync +// +//***************************************************************************** +void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setTxFrameSyncSource(base, + (McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx); + + // + // Check if using internal frame-sync source. + // + if((McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx == + MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Select the internal frame-sync trigger source. + // + McBSP_setTxInternalFrameSyncSource(base, + (McBSP_TxInternalFrameSyncSource)ptrFsyncParams->syncIntSource); + + // + // Check if using SRG FSG to trigger frame-sync pulse and GSYNC feature + // is disabled that is FSG is not derived from external MCLKR pin. + // + if((ptrFsyncParams->syncIntSource == + MCBSP_TX_INTERNAL_FRAME_SYNC_SRG) && + (ptrFsyncParams->syncSRGSyncFSRFlag == false)) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setTxFrameSyncPolarity(base, + (McBSP_TxFrameSyncPolarity)ptrFsyncParams->syncFSXPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableTxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureRxFrameSync +// +//***************************************************************************** +void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setRxFrameSyncSource(base, + (McBSP_RxFrameSyncSource)ptrFsyncParams->syncSourceRx); + + // + // If using internal frame-sync source. + // + if(ptrFsyncParams->syncSourceRx == MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Check if GSYNC feature is disabled that is FSG is not derived + // from external MCLKR pin. + // + if(ptrFsyncParams->syncSRGSyncFSRFlag == false) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setRxFrameSyncPolarity(base, + (McBSP_RxFrameSyncPolarity)ptrFsyncParams->syncFSRPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableRxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureTxDataFormat +// +//***************************************************************************** +void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - a TX must at least has a single phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseTx(base); + + // + // Check if second phase is being used. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseTx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the Tx companding mode. + // + McBSP_setTxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set Tx data delay in bits. + // + McBSP_setTxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set DX pin delay. + // + if(ptrDataParams->pinDelayEnableFlag) + { + McBSP_enableDxPinDelay(base); + } + else + { + McBSP_disableDxPinDelay(base); + } + + // + // Set the transmitter interrupt source. + // + McBSP_setTxInterruptSource(base, + (McBSP_TxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureRxDataFormat +// +//***************************************************************************** +void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP mode. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - an RX must at least have a single phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseRx(base); + + // + // Check if second phase is to be enabled. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseRx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the receiver companding mode. + // + McBSP_setRxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set receiver data delay in bits. + // + McBSP_setRxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set receiver sign-extension and justification mode. + // + McBSP_setRxSignExtension(base, + (McBSP_RxSignExtensionMode)ptrDataParams->signExtMode); + + // + // Set the receiver interrupt source. + // + McBSP_setRxInterruptSource(base, + (McBSP_RxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureTxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorTx; + + errorTx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setTxChannelMode(base, + (McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx); + + // + // Configuration for multichannel selections that is for + // MCBSP_TX_CHANNEL_SELECTION_ENABLED, + // MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or + // MCBSP_SYMMERTIC_RX_TX_SELECTION. + // + if(((McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx) != + MCBSP_ALL_TX_CHANNELS_ENABLED) + { + // + // Select 2 partition or 8 partition. + // + McBSP_setTxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionTx); + + // + // Disable dual phase transmission mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionTx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if(((uint16_t)ptrMchnParams->channelCountTx) > 32U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*(ptrMchnParams->ptrChannelsListTx) + + index)); + } + else + { + errorTx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition B. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + else + { + errorTx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if((uint16_t)ptrMchnParams->channelCountTx > 128U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Enable the Tx channels. + // + McBSP_enableTxChannel(base, MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + } + } + return(errorTx); +} + +//***************************************************************************** +// +// McBSP_configureRxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorRx; + + errorRx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setRxChannelMode(base, + (McBSP_RxChannelMode)ptrMchnParams->multichannelModeRx); + + // + // Select 2 partition or 8 partition. + // + McBSP_setRxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionRx); + + // + // Configuration for multichannel selections that is for + // MCBSP_RX_CHANNEL_SELECTION_ENABLED. + // + if((ptrMchnParams->multichannelModeRx) == + MCBSP_RX_CHANNEL_SELECTION_ENABLED) + { + // + // Disable dual phase reception mode. + // + McBSP_disableTwoPhaseRx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionRx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if((uint16_t)ptrMchnParams->channelCountRx > 32U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (*((ptrMchnParams->ptrChannelsListRx) + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the Rx channel belonging to the block + // assigned to partition B. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if(ptrMchnParams->channelCountRx > 128U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Enable the Rx channels. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + index))); + } + } + } + return(errorRx); +} + +//***************************************************************************** +// +// McBSP_configureSPIMasterMode +// +//***************************************************************************** +void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams *ptrSPIMasterMode) +{ + // + // Configure clock stop mode. + // + if(((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPIMasterMode->clockStopMode); + + // + // Set loop back mode. + // + if(ptrSPIMasterMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as master. Use SRG as clock source for driving + // master clock. MCLKX pin will be the master clock out pin. + // + McBSP_setTxClockSource(base, MCBSP_INTERNAL_TX_CLOCK_SOURCE); + + // + // Set internal clock (LSPCLK) as SRG clock source. + // + McBSP_setTxSRGClockSource(base, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK); + + // + // Set SRG clock divider for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrSPIMasterMode->clockSRGDivider); + + // + // Set the output master clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPIMasterMode->spiMode); + + // + // Set FSX as an output driven by SRG. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE); + + // + // FSX is triggered when data is written to DXR registers. + // + McBSP_setTxInternalFrameSyncSource(base, + MCBSP_TX_INTERNAL_FRAME_SYNC_DATA); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + + // + // Set one bit data delay for transmission & reception to set correct + // setup time on FSX signal. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + } +} + +//***************************************************************************** +// +// McBSP_configureSPISlaveMode +// +//***************************************************************************** +void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams *ptrSPISlaveMode) +{ + + // + // Configure clock stop mode. + // + if(((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPISlaveMode->clockStopMode); + // + // Set loop back mode. + // + if(ptrSPISlaveMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as Slave. MCLKX pin acts as input slave + // clock and is driven externally by SPI master. + // + McBSP_setTxClockSource(base, MCBSP_EXTERNAL_TX_CLOCK_SOURCE); + + // + // Set the input slave clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPISlaveMode->spiMode); + + // + // Set internal clock (LSPCLK) as SRG clock source. SRG is used to + // synchronize McBSP logic with externally generated master clock. + // + McBSP_setRxSRGClockSource(base, MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK); + + // + // Assign a clock divider value of 1 for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, 1U); + + // + // Set FSX as an input which is driven by slave-enable signal + // from SPI master. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception.. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + + // + // Set zero bit data delay for transmission & reception. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + } +} diff --git a/gpio_driverlib_cpu2/device/driverlib/mcbsp.h b/gpio_driverlib_cpu2/device/driverlib/mcbsp.h new file mode 100644 index 0000000..949987d --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/mcbsp.h @@ -0,0 +1,3340 @@ +//########################################################################### +// +// FILE: mcbsp.h +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MCBSP_H +#define MCBSP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup mcbsp_api McBSP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "inc/hw_mcbsp.h" +#include "inc/hw_memmap.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Define to specify mask for setting the word and frame length in +// McBSP_setTxDataSize() anf McBSP_setRxDataSize(). +// +//***************************************************************************** +#define MCBSP_XCR1_M (MCBSP_XCR1_XWDLEN1_M | \ + MCBSP_XCR1_XFRLEN1_M) +#define MCBSP_RCR1_M (MCBSP_RCR1_RWDLEN1_M | \ + MCBSP_RCR1_RFRLEN1_M) +#define MCBSP_XCR2_M (MCBSP_XCR2_XWDLEN2_M | \ + MCBSP_XCR2_XFRLEN2_M) +#define MCBSP_RCR2_M (MCBSP_RCR2_RWDLEN2_M | \ + MCBSP_RCR2_RFRLEN2_M) + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getRxErrorStatus() when +// there is an error in Rx. +// +//***************************************************************************** +#define MCBSP_RX_NO_ERROR 0x0U //!< No error. +#define MCBSP_RX_BUFFER_ERROR 0x4U //!< Buffer Full. +#define MCBSP_RX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_RX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getTxErrorStatus() when +// there is an error in Tx. +// +//***************************************************************************** +#define MCBSP_TX_NO_ERROR 0x0U //!< No error. +#define MCBSP_TX_BUFFER_ERROR 0x4U //!< Buffer overrun. +#define MCBSP_TX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_TX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Values that can be returned by McBSP_configureTxMultichannel() and +// McBSP_configureRxMultichannel(). +// +//***************************************************************************** +#define MCBSP_ERROR_EXCEEDED_CHANNELS 0x1U //!< Exceeded number of channels. +#define MCBSP_ERROR_2_PARTITION_A 0x2U //!< Error in 2 partition A setup. +#define MCBSP_ERROR_2_PARTITION_B 0x4U //!< Error in 2 partition B setup. +#define MCBSP_ERROR_INVALID_MODE 0x8U //!< Invalid mode. + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxSignExtension() as the \e +//! mode parameters. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RIGHT_JUSTIFY_FILL_ZERO = 0x0000U, //!< Right justify and + //!< zero fill MSB. + MCBSP_RIGHT_JUSTIFY_FILL_SIGN = 0x2000U, //!< Right justified sign + //!< extended into MSBs. + MCBSP_LEFT_JUSTIFY_FILL_ZER0 = 0x4000U //!< Left justifies LBS + //!< filled with zero. +}McBSP_RxSignExtensionMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setClockStopMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_CLOCK_MCBSP_MODE = 0x0000U, //!< Disables clock stop mode. + MCBSP_CLOCK_SPI_MODE_NO_DELAY = 0x1000U, //!< Enables clock stop mode. + MCBSP_CLOCK_SPI_MODE_DELAY = 0x1800U //!< Enables clock stop mode + //!< with half cycle delay. +}McBSP_ClockStopMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxInterruptSource() as the +//! \e interruptSource parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RX_ISR_SOURCE_SERIAL_WORD = 0x0000U, //!> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Configures transmitter input clock source for sample generator. +//! +//! \param base is the base address of the McBSP module. +//! \param srgClockSource is clock source for the sample generator. +//! +//! This functions sets the clock source for the sample rate generator. +//! Valid values for \e clockSource are +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK for LSPCLK. +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN for external clock at MCLKR pin. +//! MCLKX pin will be an output driven by sample rate generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxSRGClockSource(uint32_t base, + const McBSP_SRGTxClockSource srgClockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKSM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_CLKSM) | + ((uint16_t)((uint16_t)srgClockSource & 0x1U) << 13U)); + // + // Set or clear SCLKME bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_SCLKME) | + (uint16_t)(((uint16_t)srgClockSource >> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Sets the mode for transmitter internal frame sync signal. +//! +//! \param base is the base address of the McBSP module. +//! \param syncMode is the frame sync mode. +//! +//! This function sets the frame sync signal generation mode. The signal can be +//! generated based on clock divider as set in McBSP_setFrameSyncPulsePeriod() +//! function or when data is transferred from DXR registers to XSR registers. +//! Valid input for syncMode are: +//! +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_DATA - frame sync signal is +//! generated when data is transferred from +//! DXR registers to XSR registers. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SRG - frame sync signal is +//! generated based on the clock counter +//! value as defined in +//! McBSP_setFrameSyncPulsePeriod() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxInternalFrameSyncSource(uint32_t base, + const McBSP_TxInternalFrameSyncSource syncMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSGM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_FSGM) | (uint16_t)syncMode); +} + +//***************************************************************************** +// +//! Set Multichannel receiver partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel receiver. Valid values +//! for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or Clear RMCME bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to receiver in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! receiver partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Check the block value if it is 0,2,4,6 or 1,3,5,7. + // + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to RPABLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPABLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to RPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPBBLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active receiver block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active receiver block involved in McBSP +//! reception. +//! +//! \return Active block in McBSP reception. Returned values range from 0 to 7 +//! representing the respective active block number . +// +//***************************************************************************** +static inline uint16_t +McBSP_getRxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return RCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR1) & MCBSP_MCR1_RCBLK_M) >> + MCBSP_MCR1_RCBLK_S); +} + +//***************************************************************************** +// +//! Configure channel selection mode for receiver. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_RX_CHANNELS_ENABLED - enables all channels. +//! - \b MCBSP_RX_CHANNEL_SELECTION_ENABLED - lets the user enable desired +//! channels by using McBSP_enableRxChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxChannelMode(uint32_t base, const McBSP_RxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear RMCM bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCM) | (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Set Multichannel transmitter partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel transmitter. Valid +//! values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear XMCME bit. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to transmitter in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! transmitter partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to XPABLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPABLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to XPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPBBLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active transmitter block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active transmitter block involved in +//! McBSP transmission. +//! +//! \return Active block in McBSP transmission. Returned values range from +//! 0 to 7 representing the respective active block number. +// +//***************************************************************************** +static inline uint16_t +McBSP_getTxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return XCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR2) & MCBSP_MCR2_XCBLK_M) >> + MCBSP_MCR2_XCBLK_S); + +} + +//***************************************************************************** +// +//! Configure channel selection mode for transmitter. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_TX_CHANNELS_ENABLED - enables and unmasks all channels +//! - \b MCBSP_TX_CHANNEL_SELECTION_ENABLED - lets the user enable and unmask +//! desired channels by using McBSP_enableTxChannel() +//! - \b MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION - All channels enables but +//! until enabled by McBSP_enableTxChannel() +//! - \b MCBSP_SYMMERTIC_RX_TX_SELECTION - Symmetric transmission and +//! reception. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxChannelMode(uint32_t base, const McBSP_TxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set values to the XMCM bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCM_M) | + (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Select the transmitter frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the transmitter frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSX. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! internally. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncSource(uint32_t base, + const McBSP_TxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Set or Clear the FSXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Select receiver frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the receiver frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSR. +//! - \b MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! by SRG. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncSource(uint32_t base, + const McBSP_RxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Configures the Transmit clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the transmission pin. +//! +//! This function configures the clock source for the transmitter. Valid input +//! for rxClockSource are: +//! - \b MCBSP_INTERNAL_TX_CLOCK_SOURCE - internal clock source. SRG is the +//! source. +//! - \b MCBSP_EXTERNAL_TX_CLOCK_SOURCE - external clock source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockSource(uint32_t base, const McBSP_TxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXM ) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Configures the Receive clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the reception pin. +//! +//! This function configures the clock source for the receiver. Valid input +//! for base are: +//! - \b MCBSP_INTERNAL_RX_CLOCK_SOURCE - internal clock source. Sample Rate +//! Generator will be used. +//! - \b MCBSP_EXTERNAL_RX_CLOCK_SOURCE - external clock will drive the data. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockSource(uint32_t base, const McBSP_RxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRM) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Sets transmitter frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSX pin. Use \b MCBSP_TX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_TX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncPolarity(uint32_t base, + const McBSP_TxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets receiver frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSR pin. Use \b MCBSP_RX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_RX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncPolarity(uint32_t base, + const McBSP_RxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets transmitter clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the transmitter +//! clock on MCLKX pin. +//! Valid values for clockPolarity are: +//! - \b MCBSP_TX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_TX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockPolarity(uint32_t base, + const McBSP_TxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKXP bit first , then set or clear CLKXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +//! Sets receiver clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the receiver +//! clock on MCLKR pin. If external clock is used, the polarity will affect +//! CLKG signal. +//! Valid values for clockPolarity are: +//! - \b MCBSP_RX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_RX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockPolarity(uint32_t base, + const McBSP_RxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKRP bit first , then set or clear CLKRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data value in data receive register. +//! +//! \return received data. +// +//***************************************************************************** +static inline +uint16_t McBSP_read16bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DRR1 register. + // + return(HWREGH(base + MCBSP_O_DRR1)); +} + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data values in data receive registers. +//! +//! \return received data. +// +//***************************************************************************** +static inline uint32_t +McBSP_read32bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DDR1 register and return DDR2:DDR1. + // + return((((uint32_t)HWREGH(base + MCBSP_O_DRR2) << 16U) | + HWREGH(base + MCBSP_O_DRR1))); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 8,12 or 16 bit data to data transmit register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write16bitData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data; +} + +//***************************************************************************** +// +//! Write 20, 24 or 32 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 20, 24 or 32 bit data to data transmit registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write32bitData(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR2 register first. + // + HWREGH(base + MCBSP_O_DXR2) = data >> 16U; + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data & 0xFFFFU; +} + +//***************************************************************************** +// +//! Return left justified for data for U Law or A Law companding. +//! +//! \param data is the 14 bit word. +//! \param compandingType specifies the type comapnding desired. +//! +//! This functions returns U law or A law adjusted word. +//! +//! \return U law or A law left justified word. +// +//***************************************************************************** +static inline uint16_t +McBSP_getLeftJustifyData(uint16_t data, + const McBSP_CompandingType compandingType) +{ + return(data << (uint16_t)compandingType); +} + + +//***************************************************************************** +// +//! Enable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_RINT; +} + +//***************************************************************************** +// +//! Disable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_RINT); +} + +//***************************************************************************** +// +//! Enable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_XINT; +} + +//***************************************************************************** +// +//! Disable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_XINT); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. +//! +//! \return None. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written to +//! the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! the transmitter buffer is empty the data will be written to the data +//! registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written +//! to the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData); + + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Reception. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing the first or second frame phase +//! respectively. Valid value for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Transmission. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing single or dual phase respectively. +//! Valid values for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setTxDataSize(uint32_t base, + const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Disables a channel in an eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function disables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function enables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Disables a channel in an eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function disables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function enables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Configures transmitter clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the transmitter clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFSR - true to sync with signal on FSR pin, +//! false to ignore signal on FSR pin. +//! the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_TX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_TX_CLOCK_SOURCE +//! - \b clockTxSRGSource - MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN +//! - \b clockMCLKXPolarity - Output polarity on MCLKX pin. +//! - MCBSP_TX_POLARITY_RISING_EDGE +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockMCLKRPolarity - Input polarity on MCLKR pin (if SRG is +//! sourced from MCLKR pin). +//! - MCBSP_RX_POLARITY_FALLING_EDGE +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures receiver clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the receiver clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_RX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_RX_CLOCK_SOURCE +//! - \b clockRxSRGSource - MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN +//! - \b clockMCLKRPolarity- output polarity on MCLKR pin. +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! - \b clockMCLKXPolarity- Input polarity on MCLKX pin (if SRG is sourced +//! from MCLKX pin). +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures transmitter frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSPTxFsyncParams. +//! This function sets up the transmitter frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin.This value has to +//! be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. false +//! to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceTx - MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncIntSource - MCBSP_TX_INTERNAL_FRAME_SYNC_DATA or +//! MCBSP_TX_INTERNAL_FRAME_SYNC_SRG +//! - \b syncFSXPolarity - MCBSP_TX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_TX_FRAME_SYNC_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures receiver frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSP_RxFsyncParams. +//! This function sets up the receiver frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, +//! false to ignore the pulse on FSR pin. +//! This value has to be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. +//! false to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceRx - MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncFSRPolarity - MCBSP_RX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_RX_FRAME_SYNC_POLARITY_HIGH +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures transmitter data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing \e data format +//! parameters McBSPTxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSPTxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for no loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b pinDelayEnableFlag - true to enable DX pin delay. +//! false to disable DX pin delay. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b interruptMode - MCBSP_TX_ISR_SOURCE_TX_READY, +//! MCBSP_TX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_TX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_TX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures receiver data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing data format +//! parameters McBSP_RxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSP_RxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for non loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b signExtMode - MCBSP_RIGHT_JUSTIFY_FILL_ZERO, +//! MCBSP_RIGHT_JUSTIFY_FILL_SIGN or +//! MCBSP_LEFT_JUSTIFY_FILL_ZER0 +//! - \b interruptMode - MCBSP_RX_ISR_SOURCE_SERIAL_WORD, +//! MCBSP_RX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_RX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_RX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures transmitter multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_TxMultichannelParams. +//! +//! This function sets up the transmitter multichannel mode. The following are +//! valid values and ranges for the parameters of the +//! McBSP_TxMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_TX_CHANNELS_ENABLED, +//! MCBSP_TX_CHANNEL_SELECTION_ENABLED, +//! MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or +//! MCBSP_SYMMERTIC_RX_TX_SELECTION +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even and +//! odd channels. For example you can have channels [48 -63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63] and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures receiver multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_RxMultiChannelParams. +//! +//! This function sets up the receiver multichannel mode. The following are +//! valid values and ranges for the parameters of the McBSPMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_RX_CHANNELS_ENABLED, +//! MCBSP_RX_CHANNEL_SELECTION_ENABLED, +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even +//! and odd channels. For example you can have channels [48 - 63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63]and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures McBSP in SPI master mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPIMasterMode is a pointer to a structure containing SPI +//! parameters McBSP_SPIMasterModeParams. +//! This function sets up the McBSP module in SPI master mode.The following are +//! valid values and ranges for the parameters of the +//! McBSP_SPIMasterModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity can take values: +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockSRGDivider - Maximum valid value is 255. +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams * ptrSPIMasterMode); + +//***************************************************************************** +// +//! Configures McBSP in SPI slave mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPISlaveMode is a pointer to a structure containing SPI +//! parameters McBSP_SPISlaveModeParams. +//! This function sets up the McBSP module in SPI slave mode.The following are +//! valid values and ranges for the parameters of the McBSP_SPISlaveModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity and can take +//! values: +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams * ptrSPISlaveMode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MCBSP_H diff --git a/gpio_driverlib_cpu2/device/driverlib/memcfg.c b/gpio_driverlib_cpu2/device/driverlib/memcfg.c new file mode 100644 index 0000000..c9a4dc7 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/memcfg.c @@ -0,0 +1,701 @@ +//########################################################################### +// +// FILE: memcfg.c +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "memcfg.h" + + +//***************************************************************************** +// +// MemCfg_lockConfig +// +//***************************************************************************** +void +MemCfg_lockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that blocks writes to the sections' configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Lock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_unlockConfig +// +//***************************************************************************** +void +MemCfg_unlockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Clear the bit that blocks writes to the sections' configuration + // registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Unlock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL)); + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_commitConfig +// +//***************************************************************************** +void +MemCfg_commitConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that permanently blocks writes to the sections' + // configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Commit configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setProtection +// +//***************************************************************************** +void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + uint32_t regOffset; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 8 bits in the corresponding ACCPROT register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 8U; + } + + // + // Calculate register offset. Also, make sure the shift value is no greater + // than 31. + // + regOffset = (shiftVal & ~(0x1FU)) >> 4U; + shiftVal &= 0x0001FU; + maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal; + regVal = protectMode << shiftVal; + + // + // Write the access protection mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal; + break; + + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setLSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel) +{ + uint32_t shiftVal; + uint32_t temp; + + // + // Check the arguments. + // + ASSERT((ramSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Calculate how far the controller select value needs to be shifted. Each + // section number is represented by a bit in the lower word of ramSection + // and 2 bits in the corresponding MSEL register. + // + shiftVal = 0U; + temp = MEMCFG_SECT_NUM_MASK & ramSection; + + while(temp != 1U) + { + temp = temp >> 1U; + shiftVal += 2U; + } + + // + // Write the controller select setting into the appropriate field + // + EALLOW; + + HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) = + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) & + ~((uint32_t)MEMCFG_LSXMSEL_MSEL_LS0_M << shiftVal)) | + ((uint32_t)controllerSel << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setGSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel) +{ + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS); + + // + // We only need the section number bits for this function. + // + sectionNum = ramSections & MEMCFG_SECT_NUM_MASK; + + // + // Write the controller select setting into the appropriate field. + // + EALLOW; + if(controllerSel == MEMCFG_GSRAMCONTROLLER_CPU1) + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &= ~sectionNum; + } + else + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) |= sectionNum; + } + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setTestMode +// +//***************************************************************************** +void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 2 bits in the corresponding TEST register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 2U; + } + + maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal; + regVal = (uint32_t)testMode << shiftVal; + + // + // Write the test mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal; + break; + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_initSections +// +//***************************************************************************** +void +MemCfg_initSections(uint32_t ramSections) +{ + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Set the bit in the various initialization registers that starts + // initialization. + // + EALLOW; + + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Initialize all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_MSGX_ALL; + break; + + default: + // + // Do nothing. Invalid ramSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_getInitStatus +// +//***************************************************************************** +bool +MemCfg_getInitStatus(uint32_t ramSections) +{ + uint32_t status; + + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Read registers containing the initialization complete status. + // + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE); + break; + + case MEMCFG_SECT_TYPE_LS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_GS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MSG: + status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Return the overall status. + // + if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) == + (MEMCFG_SECT_DX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) == + (MEMCFG_SECT_LSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) == + (MEMCFG_SECT_GSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) == + (MEMCFG_SECT_MSGX_ALL & MEMCFG_SECT_NUM_MASK))) + { + status = MEMCFG_SECT_NUM_MASK; + } + else + { + status = 0U; + } + break; + + default: + // + // Invalid ramSections. Make sure you aren't OR-ing values for two + // different types of RAM. + // + status = 0U; + break; + } + + return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK)); +} + +//***************************************************************************** +// +// MemCfg_getViolationAddress +// +//***************************************************************************** +uint32_t +MemCfg_getViolationAddress(uint32_t intFlag) +{ + uint32_t address; + uint32_t stsNumber; + + // + // Calculate the the address of the desired violation address register. + // + if((intFlag & MEMCFG_MVIOL_MASK) != 0U) + { + stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT; + address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR; + } + else + { + stsNumber = intFlag; + address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR; + } + + while(stsNumber > 1U) + { + stsNumber = stsNumber >> 1U; + address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR); + } + + // + // Read and return the access violation address at the calculated location. + // + return(HWREG(address)); +} + +//***************************************************************************** +// +// MemCfg_getCorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag) +{ + // + // Check the arguments. + // + if(stsFlag != MEMCFG_CERR_CPUREAD) + { + // + // Currently, the only correctable error address that can be read + // from a register is one for a CPU read error (MEMCFG_CERR_CPUREAD). + // For the sake of keeping this function portable to possible future + // devices with other error types, it still takes a stsFlag parameter. + // + ASSERT((bool)false); + } + + // + // Read and return the error address. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CCPUREADDR)); +} + +//***************************************************************************** +// +// MemCfg_getUncorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag) +{ + uint32_t address; + uint32_t temp; + + // + // Calculate the the address of the desired error address register. + // + address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR; + + temp = stsFlag; + + while(temp > 1U) + { + temp = temp >> 1U; + address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR); + } + + // + // Read and return the error address at the calculated location. + // + return(HWREG(address)); +} + + diff --git a/gpio_driverlib_cpu2/device/driverlib/memcfg.h b/gpio_driverlib_cpu2/device/driverlib/memcfg.h new file mode 100644 index 0000000..8a9b6fc --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/memcfg.h @@ -0,0 +1,1266 @@ +//########################################################################### +// +// FILE: memcfg.h +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MEMCFG_H +#define MEMCFG_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup memcfg_api MemCfg +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +// +// Masks to decode memory section defines. +// +#define MEMCFG_SECT_TYPE_MASK 0xFF000000U +#define MEMCFG_SECT_TYPE_D 0x00000000U +#define MEMCFG_SECT_TYPE_LS 0x01000000U +#define MEMCFG_SECT_TYPE_GS 0x02000000U +#define MEMCFG_SECT_TYPE_MSG 0x03000000U +#define MEMCFG_SECT_NUM_MASK 0x00FFFFFFU +#define MEMCFG_XACCPROTX_M ((uint32_t)MEMCFG_GSXACCPROT0_FETCHPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_DMAWRPROT_GS0) +#define MEMCFG_XTEST_M MEMCFG_DXTEST_TEST_M0_M + +// +// Used for access violation functions. +// +#define MEMCFG_NMVIOL_MASK 0x0000FFFFU +#define MEMCFG_MVIOL_MASK 0x000F0000U +#define MEMCFG_MVIOL_SHIFT 16U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(), +// MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(), +// MemCfg_setCLAMemType(), MemCfg_setLSRAMControllerSel(), +// MemCfg_getInitStatus() as the memSection(s) or ramSection(s) parameter. +// +//***************************************************************************** +// +// DxRAM - Dedicated RAM config +// +#define MEMCFG_SECT_M0 0x00000001U //!< M0 RAM +#define MEMCFG_SECT_M1 0x00000002U //!< M1 RAM +#define MEMCFG_SECT_D0 0x00000004U //!< D0 RAM +#define MEMCFG_SECT_D1 0x00000008U //!< D1 RAM +#define MEMCFG_SECT_DX_ALL 0x0000000FU //!< All M and D RAM + +// +// LSxRAM - Local shared RAM config +// +#define MEMCFG_SECT_LS0 0x01000001U //!< LS0 RAM +#define MEMCFG_SECT_LS1 0x01000002U //!< LS1 RAM +#define MEMCFG_SECT_LS2 0x01000004U //!< LS2 RAM +#define MEMCFG_SECT_LS3 0x01000008U //!< LS3 RAM +#define MEMCFG_SECT_LS4 0x01000010U //!< LS4 RAM +#define MEMCFG_SECT_LS5 0x01000020U //!< LS5 RAM +#define MEMCFG_SECT_LSX_ALL 0x0100003FU //!< All LS RAM + +// +// GSxRAM - Global shared RAM config +// +#define MEMCFG_SECT_GS0 0x02000001U //!< GS0 RAM +#define MEMCFG_SECT_GS1 0x02000002U //!< GS1 RAM +#define MEMCFG_SECT_GS2 0x02000004U //!< GS2 RAM +#define MEMCFG_SECT_GS3 0x02000008U //!< GS3 RAM +#define MEMCFG_SECT_GS4 0x02000010U //!< GS4 RAM +#define MEMCFG_SECT_GS5 0x02000020U //!< GS5 RAM +#define MEMCFG_SECT_GS6 0x02000040U //!< GS6 RAM +#define MEMCFG_SECT_GS7 0x02000080U //!< GS7 RAM +#define MEMCFG_SECT_GS8 0x02000100U //!< GS8 RAM +#define MEMCFG_SECT_GS9 0x02000200U //!< GS9 RAM +#define MEMCFG_SECT_GS10 0x02000400U //!< GS10 RAM +#define MEMCFG_SECT_GS11 0x02000800U //!< GS11 RAM +#define MEMCFG_SECT_GS12 0x02001000U //!< GS12 RAM +#define MEMCFG_SECT_GS13 0x02002000U //!< GS13 RAM +#define MEMCFG_SECT_GS14 0x02004000U //!< GS14 RAM +#define MEMCFG_SECT_GS15 0x02008000U //!< GS15 RAM +#define MEMCFG_SECT_GSX_ALL 0x0200FFFFU //!< All GS RAM + +// +// MSGxRAM - Message RAM config +// +#define MEMCFG_SECT_MSGCPUTOCPU 0x03000001U //!< CPU-to-CPU message RAM +#define MEMCFG_SECT_MSGCPUTOCLA1 0x03000002U //!< CPU-to-CLA1 message RAM +#define MEMCFG_SECT_MSGCLA1TOCPU 0x03000004U //!< CLA1-to-CPU message RAM +#define MEMCFG_SECT_MSGX_ALL 0x03000007U //!< All message RAM + + +// +// All sections +// +#define MEMCFG_SECT_ALL 0xFFFFFFFFU //!< All configurable RAM + +//***************************************************************************** +// +// Values that can be passed to MemCfg_setProtection() as the protectMode +// parameter. +// +//***************************************************************************** +#define MEMCFG_PROT_ALLOWCPUFETCH 0x00000000U //!< CPU fetch allowed +#define MEMCFG_PROT_BLOCKCPUFETCH 0x00000001U //!< CPU fetch blocked + +#define MEMCFG_PROT_ALLOWCPUWRITE 0x00000000U //!< CPU write allowed +#define MEMCFG_PROT_BLOCKCPUWRITE 0x00000002U //!< CPU write blocked + +#define MEMCFG_PROT_ALLOWDMAWRITE 0x00000000U //!< DMA write allowed (GSxRAM) +#define MEMCFG_PROT_BLOCKDMAWRITE 0x00000004U //!< DMA write blocked (GSxRAM) + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_NMVIOL_CPUREAD 0x00000001U //!< Non-controller CPU read access +#define MEMCFG_NMVIOL_CPUWRITE 0x00000002U //!< Non-controller CPU write access +#define MEMCFG_NMVIOL_CPUFETCH 0x00000004U //!< Non-controller CPU fetch access +#define MEMCFG_NMVIOL_DMAWRITE 0x00000008U //!< Non-controller DMA write access +#define MEMCFG_NMVIOL_CLA1READ 0x00000010U //!< Non-controller CLA1 read access +#define MEMCFG_NMVIOL_CLA1WRITE 0x00000020U //!< Non-controller CLA1 write access +#define MEMCFG_NMVIOL_CLA1FETCH 0x00000040U //!< Non-controller CLA1 fetch access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_MVIOL_CPUFETCH 0x00010000U //!< Controller CPU fetch access +#define MEMCFG_MVIOL_CPUWRITE 0x00020000U //!< Controller CPU write access +#define MEMCFG_MVIOL_DMAWRITE 0x00040000U //!< Controller DMA write access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceCorrErrorStatus(), +// MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus(). +// +// Note that MEMCFG_CERR_CPUREAD is the only value below that has a +// corresponding interrupt and may be used with the error functions that take +// an intFlag(s) parameter. +// +//***************************************************************************** +#define MEMCFG_CERR_CPUREAD 0x0001U //!< Correctable CPU read error +#define MEMCFG_CERR_DMAREAD 0x0002U //!< Correctable DMA read error +#define MEMCFG_CERR_CLA1READ 0x0004U //!< Correctable CLA1 read error +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceUncorrErrorStatus(), +// MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus(). +// +//***************************************************************************** +#define MEMCFG_UCERR_CPUREAD 0x0001U //!< Uncorrectable CPU read error +#define MEMCFG_UCERR_DMAREAD 0x0002U //!< Uncorrectable DMA read error +#define MEMCFG_UCERR_CLA1READ 0x0004U //!< Uncorrectable CLA1 read error + +#endif + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_CLA_MEM_DATA, //!< Section is CLA data memory + MEMCFG_CLA_MEM_PROGRAM //!< Section is CLA program memory +} MemCfg_CLAMemoryType; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setLSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_LSRAMCONTROLLER_CPU_ONLY, //!< CPU is the owner of the section + MEMCFG_LSRAMCONTROLLER_CPU_CLA1 //!< CPU and CLA1 share this section +} MemCfg_LSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setGSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_GSRAMCONTROLLER_CPU1, //!< CPU1 is controller of the section + MEMCFG_GSRAMCONTROLLER_CPU2 //!< CPU2 is controller of the section +} MemCfg_GSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setTestMode() as the \e testMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Functional mode. Test mode is disabled. + MEMCFG_TEST_FUNCTIONAL = 0, + //! Writes allowed to data only + MEMCFG_TEST_WRITE_DATA = 1, + //! Writes allowed to ECC only (for DxRAM/MxRAM) + MEMCFG_TEST_WRITE_ECC = 2, + //! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM) + MEMCFG_TEST_WRITE_PARITY = 2 +} MemCfg_TestMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sets the CLA memory type of the specified RAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param claMemType indicates data memory or program memory. +//! +//! This function sets the CLA memory type configuration of the RAM section. If +//! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will +//! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM +//! section will be configured as CLA program memory. +//! +//! The \e ramSections parameter is an OR of the following indicators: +//! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx. +//! +//! \note This API only applies to LSx RAM and has no effect if the CLA isn't +//! controller of the memory section. +//! +//! \sa MemCfg_setLSRAControllerSel() +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType) +{ + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Write the CLA memory configuration to the appropriate register. Either + // set or clear the bit that determines the function of the RAM section as + // it relates to the CLA. + // + EALLOW; + + if(claMemType == MEMCFG_CLA_MEM_PROGRAM) + { + // + // Program memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) |= ramSections; + } + else + { + // + // Data memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) &= ~ramSections; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! This function enables the indicated RAM access violation interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableViolationInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function disables the indicated RAM access violation interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only non-controller violations may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableViolationInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) &= + ~(intFlags & MEMCFG_NMVIOL_MASK); + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) &= + ~((intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM access violation status. +//! +//! This function returns the RAM access violation status. This function will +//! return flags for both controller and non-controller access violations +//! although only the non-controller flags have the ability to cause the +//! generation of an interrupt. +//! +//! \return Returns the current violation status, enumerated as a bit field of +//! the values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//***************************************************************************** +static inline uint32_t +MemCfg_getViolationInterruptStatus(void) +{ + uint32_t status; + + // + // Read and return RAM access status flags. + // + status = (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVFLG)) | + (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVFLG) << + MEMCFG_MVIOL_SHIFT); + + return(status); +} + +//***************************************************************************** +// +//! Sets the RAM access violation status. +//! +//! \param intFlags is a bit mask of the access violation flags to be set. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function sets the RAM access violation status. This function will +//! set flags for both controller and non-controller access violations, and an +//! interrupt will be generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceViolationInterrupt(uint32_t intFlags) +{ + // + // Shift and mask the flags appropriately and write them to the + // corresponding SET register. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVSET) = + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVSET) = + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Clears RAM access violation flags. +//! +//! \param intFlags is a bit mask of the access violation flags to be cleared. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearViolationInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested access violation flags. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVCLR) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVCLR) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the correctable error threshold value. +//! +//! \param threshold is the correctable error threshold. +//! +//! This value sets the error-count threshold at which a correctable error +//! interrupt is generated. That is when the error count register reaches the +//! value specified by the \e threshold parameter, an interrupt is +//! generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCorrErrorThreshold(uint32_t threshold) +{ + // + // Write the threshold value to the appropriate register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRTHRES) = threshold; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the correctable error count. +//! +//! \return Returns the number of correctable error have occurred. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorCount(void) +{ + // + // Read and return the number of errors that have occurred. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCNT)); +} + +//***************************************************************************** +// +//! Enables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function enables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function disables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) &= ~(intFlags); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM correctable error interrupt status. +//! +//! \return Returns the current error interrupt status. Will return a value of +//! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the +//! function will return 0. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorInterruptStatus(void) +{ + // + // Read and return correctable error interrupt flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTFLG)); +} + +//***************************************************************************** +// +//! Sets the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be set. Can take +//! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function sets the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTSET) = intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function clears the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTCLR) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current correctable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRFLG)); +} + +//***************************************************************************** +// +//! Gets the current uncorrectable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getUncorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRFLG)); +} + +//***************************************************************************** +// +//! Sets the specified correctable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function sets the specified correctable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the specified uncorrectable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function sets the specified uncorrectable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears correctable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function clears the specified correctable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears uncorrectable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function clears the specified uncorrectable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 1-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMWaitState(void) +{ + // + // Clear the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) &= + ~((uint32_t)MEMCFG_ROMWAITSTATE_WSDISABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 0-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMWaitState(void) +{ + // + // Set the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) |= + MEMCFG_ROMWAITSTATE_WSDISABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMPrefetch(void) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) |= + MEMCFG_ROMPREFETCH_PFENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMPrefetch(void) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) &= + ~((uint32_t)MEMCFG_ROMPREFETCH_PFENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the writes to the configuration of specified memory sections. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function locks writes to the access protection and controller select +//! configuration of a memory section.That means calling MemCfg_setProtection() +//! or MemCfg_setLSRAMControllerSel() for a locked memory section will have no +//! effect until MemCfg_unlockConfig() is called. +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_lockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Unlocks the writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function unlocks writes to the access protection and controller select +//! configuration of a memory section that has been locked using +//! MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_unlockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Permanently locks writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function permanently locks writes to the access protection and +//! controller select configuration of a memory section. That means calling +//! MemCfg_setProtection() or MemCfg_setLSRAMControllerSel() for a locked memory +//! section will have no effect. To lock the configuration in a nonpermanent +//! way, use MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_commitConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Sets the access protection mode of a single memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param protectMode is the logical OR of the settings to be applied. +//! +//! This function sets the access protection mode of a specified memory section. +//! The mode is passed into the \e protectMode parameter as the logical OR of +//! the following values: +//! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch +//! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write +//! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_D0 or \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory +//! is configured as CLA program memory. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode); + +//***************************************************************************** +// +//! Sets the controller of the specified LSxRAM section. +//! +//! \param ramSection is the LSxRAM section to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the LSxRAM +//! section. +//! If the \e controllerSel parameter is \b MEMCFG_LSRAMCONTROLLER_CPU_ONLY, +//! the LSxRAM section passed into the \e ramSection parameter will be dedicated +//! to the CPU. If \b MEMCFG_LSRAMCONTROLLER_CPU_CLA1, the memory section will +//! be shared between the CPU and the CLA. +//! +//! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0 +//! through \b MEMCFG_SECT_LSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to LSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the controller of the specified GSxRAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the GSxRAM +//! section.If the \e controllerSel parameter is \b MEMCFG_GSRAMCONTROLLER_CPU1, +//! the GSRAM sections passed into the \e ramSections parameter will be +//! dedicated to CPU1. If \b MEMCFG_GSRAMCONTROLLER_CPU2, the memory section +//! will be dedicated to CPU2. +//! +//! The \e ramSections parameter should be a logical OR of values from +//! \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to GSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the test mode of the specified memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param testMode is the test mode selected. +//! +//! This function sets the test mode configuration of the RAM section. The +//! \e testMode parameter can take one of the following values: +//! - \b MEMCFG_TEST_FUNCTIONAL +//! - \b MEMCFG_TEST_WRITE_DATA +//! - \b MEMCFG_TEST_WRITE_ECC +//! - \b MEMCFG_TEST_WRITE_PARITY +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1 +//! - \b MEMCFG_SECT_D0, \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode); + +//***************************************************************************** +// +//! Starts the initialization the specified RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be initialized. +//! +//! This function starts the initialization of the specified RAM sections. Use +//! MemCfg_getInitStatus() to check if the initialization is done. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_initSections(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the status of initialized RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be checked. +//! +//! This function gets the initialization status of the RAM sections specified +//! by the \e ramSections parameter. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections. +//! +//! \note Use MemCfg_initSections() to start the initialization. +//! +//! \return Returns \b true if all the sections specified by \e ramSections +//! have been initialized and \b false if not. +// +//***************************************************************************** +extern bool +MemCfg_getInitStatus(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the violation address associated with a intFlag. +//! +//! \param intFlag is the type of access violation as indicated by ONE of +//! these values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return Returns the violation address associated with the \e intFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getViolationAddress(uint32_t intFlag); + +//***************************************************************************** +// +//! Get the correctable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. Can currently take the value \b MEMCFG_CERR_CPUREAD only. +//! Other values are reserved. +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag); + +//***************************************************************************** +// +//! Get the uncorrectable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. It may be passed one of these values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or +//! \b MEMCFG_UCERR_CLA1READ values +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MEMCFG_H diff --git a/gpio_driverlib_cpu2/device/driverlib/pin_map.h b/gpio_driverlib_cpu2/device/driverlib/pin_map.h new file mode 100644 index 0000000..95c6fa3 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/pin_map.h @@ -0,0 +1,894 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// 0x00000003 = MUX register value +// 0x0000000C = GMUX register value +// 0x0000FF00 = Shift amount within mux registers +// 0xFFFF0000 = Offset of MUX register +//***************************************************************************** + + +#define GPIO_0_GPIO0 0x00060000U +#define GPIO_0_EPWM1A 0x00060001U +#define GPIO_0_SDAA 0x00060006U + +#define GPIO_1_GPIO1 0x00060200U +#define GPIO_1_EPWM1B 0x00060201U +#define GPIO_1_MFSRB 0x00060203U +#define GPIO_1_SCLA 0x00060206U + +#define GPIO_2_GPIO2 0x00060400U +#define GPIO_2_EPWM2A 0x00060401U +#define GPIO_2_OUTPUTXBAR1 0x00060405U +#define GPIO_2_SDAB 0x00060406U + +#define GPIO_3_GPIO3 0x00060600U +#define GPIO_3_EPWM2B 0x00060601U +#define GPIO_3_OUTPUTXBAR2 0x00060602U +#define GPIO_3_MCLKRB 0x00060603U +#define GPIO_3_SCLB 0x00060606U + +#define GPIO_4_GPIO4 0x00060800U +#define GPIO_4_EPWM3A 0x00060801U +#define GPIO_4_OUTPUTXBAR3 0x00060805U +#define GPIO_4_CANTXA 0x00060806U + +#define GPIO_5_GPIO5 0x00060A00U +#define GPIO_5_EPWM3B 0x00060A01U +#define GPIO_5_MFSRA 0x00060A02U +#define GPIO_5_OUTPUTXBAR3 0x00060A03U +#define GPIO_5_CANRXA 0x00060A06U + +#define GPIO_6_GPIO6 0x00060C00U +#define GPIO_6_EPWM4A 0x00060C01U +#define GPIO_6_OUTPUTXBAR4 0x00060C02U +#define GPIO_6_EPWMSYNCO 0x00060C03U +#define GPIO_6_EQEP3A 0x00060C05U +#define GPIO_6_CANTXB 0x00060C06U + +#define GPIO_7_GPIO7 0x00060E00U +#define GPIO_7_EPWM4B 0x00060E01U +#define GPIO_7_MCLKRA 0x00060E02U +#define GPIO_7_OUTPUTXBAR5 0x00060E03U +#define GPIO_7_EQEP3B 0x00060E05U +#define GPIO_7_CANRXB 0x00060E06U + +#define GPIO_8_GPIO8 0x00061000U +#define GPIO_8_EPWM5A 0x00061001U +#define GPIO_8_CANTXB 0x00061002U +#define GPIO_8_ADCSOCAO 0x00061003U +#define GPIO_8_EQEP3S 0x00061005U +#define GPIO_8_SCITXDA 0x00061006U + +#define GPIO_9_GPIO9 0x00061200U +#define GPIO_9_EPWM5B 0x00061201U +#define GPIO_9_SCITXDB 0x00061202U +#define GPIO_9_OUTPUTXBAR6 0x00061203U +#define GPIO_9_EQEP3I 0x00061205U +#define GPIO_9_SCIRXDA 0x00061206U + +#define GPIO_10_GPIO10 0x00061400U +#define GPIO_10_EPWM6A 0x00061401U +#define GPIO_10_CANRXB 0x00061402U +#define GPIO_10_ADCSOCBO 0x00061403U +#define GPIO_10_EQEP1A 0x00061405U +#define GPIO_10_SCITXDB 0x00061406U +#define GPIO_10_UPP_WAIT 0x0006140FU + +#define GPIO_11_GPIO11 0x00061600U +#define GPIO_11_EPWM6B 0x00061601U +#define GPIO_11_SCIRXDB 0x00061602U +#define GPIO_11_OUTPUTXBAR7 0x00061603U +#define GPIO_11_EQEP1B 0x00061605U +#define GPIO_11_UPP_STRT 0x0006160FU + +#define GPIO_12_GPIO12 0x00061800U +#define GPIO_12_EPWM7A 0x00061801U +#define GPIO_12_CANTXB 0x00061802U +#define GPIO_12_MDXB 0x00061803U +#define GPIO_12_EQEP1S 0x00061805U +#define GPIO_12_SCITXDC 0x00061806U +#define GPIO_12_UPP_ENA 0x0006180FU + +#define GPIO_13_GPIO13 0x00061A00U +#define GPIO_13_EPWM7B 0x00061A01U +#define GPIO_13_CANRXB 0x00061A02U +#define GPIO_13_MDRB 0x00061A03U +#define GPIO_13_EQEP1I 0x00061A05U +#define GPIO_13_SCIRXDC 0x00061A06U +#define GPIO_13_UPP_D7 0x00061A0FU + +#define GPIO_14_GPIO14 0x00061C00U +#define GPIO_14_EPWM8A 0x00061C01U +#define GPIO_14_SCITXDB 0x00061C02U +#define GPIO_14_MCLKXB 0x00061C03U +#define GPIO_14_OUTPUTXBAR3 0x00061C06U +#define GPIO_14_UPP_D6 0x00061C0FU + +#define GPIO_15_GPIO15 0x00061E00U +#define GPIO_15_EPWM8B 0x00061E01U +#define GPIO_15_SCIRXDB 0x00061E02U +#define GPIO_15_MFSXB 0x00061E03U +#define GPIO_15_OUTPUTXBAR4 0x00061E06U +#define GPIO_15_UPP_D5 0x00061E0FU + +#define GPIO_16_GPIO16 0x00080000U +#define GPIO_16_SPISIMOA 0x00080001U +#define GPIO_16_CANTXB 0x00080002U +#define GPIO_16_OUTPUTXBAR7 0x00080003U +#define GPIO_16_EPWM9A 0x00080005U +#define GPIO_16_SD1_D1 0x00080007U +#define GPIO_16_UPP_D4 0x0008000FU + +#define GPIO_17_GPIO17 0x00080200U +#define GPIO_17_SPISOMIA 0x00080201U +#define GPIO_17_CANRXB 0x00080202U +#define GPIO_17_OUTPUTXBAR8 0x00080203U +#define GPIO_17_EPWM9B 0x00080205U +#define GPIO_17_SD1_C1 0x00080207U +#define GPIO_17_UPP_D3 0x0008020FU + +#define GPIO_18_GPIO18 0x00080400U +#define GPIO_18_SPICLKA 0x00080401U +#define GPIO_18_SCITXDB 0x00080402U +#define GPIO_18_CANRXA 0x00080403U +#define GPIO_18_EPWM10A 0x00080405U +#define GPIO_18_SD1_D2 0x00080407U +#define GPIO_18_UPP_D2 0x0008040FU + +#define GPIO_19_GPIO19 0x00080600U +#define GPIO_19_SPISTEA 0x00080601U +#define GPIO_19_SCIRXDB 0x00080602U +#define GPIO_19_CANTXA 0x00080603U +#define GPIO_19_EPWM10B 0x00080605U +#define GPIO_19_SD1_C2 0x00080607U +#define GPIO_19_UPP_D1 0x0008060FU + +#define GPIO_20_GPIO20 0x00080800U +#define GPIO_20_EQEP1A 0x00080801U +#define GPIO_20_MDXA 0x00080802U +#define GPIO_20_CANTXB 0x00080803U +#define GPIO_20_EPWM11A 0x00080805U +#define GPIO_20_SD1_D3 0x00080807U +#define GPIO_20_UPP_D0 0x0008080FU + +#define GPIO_21_GPIO21 0x00080A00U +#define GPIO_21_EQEP1B 0x00080A01U +#define GPIO_21_MDRA 0x00080A02U +#define GPIO_21_CANRXB 0x00080A03U +#define GPIO_21_EPWM11B 0x00080A05U +#define GPIO_21_SD1_C3 0x00080A07U +#define GPIO_21_UPP_CLK 0x00080A0FU + +#define GPIO_22_GPIO22 0x00080C00U +#define GPIO_22_EQEP1S 0x00080C01U +#define GPIO_22_MCLKXA 0x00080C02U +#define GPIO_22_SCITXDB 0x00080C03U +#define GPIO_22_EPWM12A 0x00080C05U +#define GPIO_22_SPICLKB 0x00080C06U +#define GPIO_22_SD1_D4 0x00080C07U + +#define GPIO_23_GPIO23 0x00080E00U +#define GPIO_23_EQEP1I 0x00080E01U +#define GPIO_23_MFSXA 0x00080E02U +#define GPIO_23_SCIRXDB 0x00080E03U +#define GPIO_23_EPWM12B 0x00080E05U +#define GPIO_23_SPISTEB 0x00080E06U +#define GPIO_23_SD1_C4 0x00080E07U + +#define GPIO_24_GPIO24 0x00081000U +#define GPIO_24_OUTPUTXBAR1 0x00081001U +#define GPIO_24_EQEP2A 0x00081002U +#define GPIO_24_MDXB 0x00081003U +#define GPIO_24_SPISIMOB 0x00081006U +#define GPIO_24_SD2_D1 0x00081007U + +#define GPIO_25_GPIO25 0x00081200U +#define GPIO_25_OUTPUTXBAR2 0x00081201U +#define GPIO_25_EQEP2B 0x00081202U +#define GPIO_25_MDRB 0x00081203U +#define GPIO_25_SPISOMIB 0x00081206U +#define GPIO_25_SD2_C1 0x00081207U + +#define GPIO_26_GPIO26 0x00081400U +#define GPIO_26_OUTPUTXBAR3 0x00081401U +#define GPIO_26_EQEP2I 0x00081402U +#define GPIO_26_MCLKXB 0x00081403U +#define GPIO_26_SPICLKB 0x00081406U +#define GPIO_26_SD2_D2 0x00081407U + +#define GPIO_27_GPIO27 0x00081600U +#define GPIO_27_OUTPUTXBAR4 0x00081601U +#define GPIO_27_EQEP2S 0x00081602U +#define GPIO_27_MFSXB 0x00081603U +#define GPIO_27_SPISTEB 0x00081606U +#define GPIO_27_SD2_C2 0x00081607U + +#define GPIO_28_GPIO28 0x00081800U +#define GPIO_28_SCIRXDA 0x00081801U +#define GPIO_28_EM1CS4N 0x00081802U +#define GPIO_28_OUTPUTXBAR5 0x00081805U +#define GPIO_28_EQEP3A 0x00081806U +#define GPIO_28_SD2_D3 0x00081807U + +#define GPIO_29_GPIO29 0x00081A00U +#define GPIO_29_SCITXDA 0x00081A01U +#define GPIO_29_EM1SDCKE 0x00081A02U +#define GPIO_29_OUTPUTXBAR6 0x00081A05U +#define GPIO_29_EQEP3B 0x00081A06U +#define GPIO_29_SD2_C3 0x00081A07U + +#define GPIO_30_GPIO30 0x00081C00U +#define GPIO_30_CANRXA 0x00081C01U +#define GPIO_30_EM1CLK 0x00081C02U +#define GPIO_30_OUTPUTXBAR7 0x00081C05U +#define GPIO_30_EQEP3S 0x00081C06U +#define GPIO_30_SD2_D4 0x00081C07U + +#define GPIO_31_GPIO31 0x00081E00U +#define GPIO_31_CANTXA 0x00081E01U +#define GPIO_31_EM1WEN 0x00081E02U +#define GPIO_31_OUTPUTXBAR8 0x00081E05U +#define GPIO_31_EQEP3I 0x00081E06U +#define GPIO_31_SD2_C4 0x00081E07U + +#define GPIO_32_GPIO32 0x00460000U +#define GPIO_32_SDAA 0x00460001U +#define GPIO_32_EM1CS0N 0x00460002U + +#define GPIO_33_GPIO33 0x00460200U +#define GPIO_33_SCLA 0x00460201U +#define GPIO_33_EM1RNW 0x00460202U + +#define GPIO_34_GPIO34 0x00460400U +#define GPIO_34_OUTPUTXBAR1 0x00460401U +#define GPIO_34_EM1CS2N 0x00460402U +#define GPIO_34_SDAB 0x00460406U +#define GPIO_34_OFSD_2_N 0x0046040FU + +#define GPIO_35_GPIO35 0x00460600U +#define GPIO_35_SCIRXDA 0x00460601U +#define GPIO_35_EM1CS3N 0x00460602U +#define GPIO_35_SCLB 0x00460606U +#define GPIO_35_IID 0x0046060FU + +#define GPIO_36_GPIO36 0x00460800U +#define GPIO_36_SCITXDA 0x00460801U +#define GPIO_36_EM1WAIT 0x00460802U +#define GPIO_36_CANRXA 0x00460806U +#define GPIO_36_ISESSEND 0x0046080FU + +#define GPIO_37_GPIO37 0x00460A00U +#define GPIO_37_OUTPUTXBAR2 0x00460A01U +#define GPIO_37_EM1OEN 0x00460A02U +#define GPIO_37_CANTXA 0x00460A06U +#define GPIO_37_IAVALID 0x00460A0FU + +#define GPIO_38_GPIO38 0x00460C00U +#define GPIO_38_EM1A0 0x00460C02U +#define GPIO_38_SCITXDC 0x00460C05U +#define GPIO_38_CANTXB 0x00460C06U + +#define GPIO_39_GPIO39 0x00460E00U +#define GPIO_39_EM1A1 0x00460E02U +#define GPIO_39_SCIRXDC 0x00460E05U +#define GPIO_39_CANRXB 0x00460E06U + +#define GPIO_40_GPIO40 0x00461000U +#define GPIO_40_EM1A2 0x00461002U +#define GPIO_40_SDAB 0x00461006U + +#define GPIO_41_GPIO41 0x00461200U +#define GPIO_41_EM1A3 0x00461202U +#define GPIO_41_EMU1 0x00461203U +#define GPIO_41_SCLB 0x00461206U + +#define GPIO_42_GPIO42 0x00461400U +#define GPIO_42_SDAA 0x00461406U +#define GPIO_42_SCITXDA 0x0046140FU + +#define GPIO_43_GPIO43 0x00461600U +#define GPIO_43_SCLA 0x00461606U +#define GPIO_43_SCIRXDA 0x0046160FU + +#define GPIO_44_GPIO44 0x00461800U +#define GPIO_44_EM1A4 0x00461802U +#define GPIO_44_IXRCV 0x0046180FU + +#define GPIO_45_GPIO45 0x00461A00U +#define GPIO_45_EM1A5 0x00461A02U +#define GPIO_45_IDM 0x00461A0FU + +#define GPIO_46_GPIO46 0x00461C00U +#define GPIO_46_EM1A6 0x00461C02U +#define GPIO_46_SCIRXDD 0x00461C06U +#define GPIO_46_IDP 0x00461C0FU + +#define GPIO_47_GPIO47 0x00461E00U +#define GPIO_47_EM1A7 0x00461E02U +#define GPIO_47_SCITXDD 0x00461E06U +#define GPIO_47_OFSD_1_N 0x00461E0FU + +#define GPIO_48_GPIO48 0x00480000U +#define GPIO_48_OUTPUTXBAR3 0x00480001U +#define GPIO_48_EM1A8 0x00480002U +#define GPIO_48_SCITXDA 0x00480006U +#define GPIO_48_SD1_D1 0x00480007U + +#define GPIO_49_GPIO49 0x00480200U +#define GPIO_49_OUTPUTXBAR4 0x00480201U +#define GPIO_49_EM1A9 0x00480202U +#define GPIO_49_SCIRXDA 0x00480206U +#define GPIO_49_SD1_C1 0x00480207U + +#define GPIO_50_GPIO50 0x00480400U +#define GPIO_50_EQEP1A 0x00480401U +#define GPIO_50_EM1A10 0x00480402U +#define GPIO_50_SPISIMOC 0x00480406U +#define GPIO_50_SD1_D2 0x00480407U + +#define GPIO_51_GPIO51 0x00480600U +#define GPIO_51_EQEP1B 0x00480601U +#define GPIO_51_EM1A11 0x00480602U +#define GPIO_51_SPISOMIC 0x00480606U +#define GPIO_51_SD1_C2 0x00480607U + +#define GPIO_52_GPIO52 0x00480800U +#define GPIO_52_EQEP1S 0x00480801U +#define GPIO_52_EM1A12 0x00480802U +#define GPIO_52_SPICLKC 0x00480806U +#define GPIO_52_SD1_D3 0x00480807U + +#define GPIO_53_GPIO53 0x00480A00U +#define GPIO_53_EQEP1I 0x00480A01U +#define GPIO_53_EM1D31 0x00480A02U +#define GPIO_53_EM2D15 0x00480A03U +#define GPIO_53_SPISTEC 0x00480A06U +#define GPIO_53_SD1_C3 0x00480A07U + +#define GPIO_54_GPIO54 0x00480C00U +#define GPIO_54_SPISIMOA 0x00480C01U +#define GPIO_54_EM1D30 0x00480C02U +#define GPIO_54_EM2D14 0x00480C03U +#define GPIO_54_EQEP2A 0x00480C05U +#define GPIO_54_SCITXDB 0x00480C06U +#define GPIO_54_SD1_D4 0x00480C07U + +#define GPIO_55_GPIO55 0x00480E00U +#define GPIO_55_SPISOMIA 0x00480E01U +#define GPIO_55_EM1D29 0x00480E02U +#define GPIO_55_EM2D13 0x00480E03U +#define GPIO_55_EQEP2B 0x00480E05U +#define GPIO_55_SCIRXDB 0x00480E06U +#define GPIO_55_SD1_C4 0x00480E07U + +#define GPIO_56_GPIO56 0x00481000U +#define GPIO_56_SPICLKA 0x00481001U +#define GPIO_56_EM1D28 0x00481002U +#define GPIO_56_EM2D12 0x00481003U +#define GPIO_56_EQEP2S 0x00481005U +#define GPIO_56_SCITXDC 0x00481006U +#define GPIO_56_SD2_D1 0x00481007U + +#define GPIO_57_GPIO57 0x00481200U +#define GPIO_57_SPISTEA 0x00481201U +#define GPIO_57_EM1D27 0x00481202U +#define GPIO_57_EM2D11 0x00481203U +#define GPIO_57_EQEP2I 0x00481205U +#define GPIO_57_SCIRXDC 0x00481206U +#define GPIO_57_SD2_C1 0x00481207U + +#define GPIO_58_GPIO58 0x00481400U +#define GPIO_58_MCLKRA 0x00481401U +#define GPIO_58_EM1D26 0x00481402U +#define GPIO_58_EM2D10 0x00481403U +#define GPIO_58_OUTPUTXBAR1 0x00481405U +#define GPIO_58_SPICLKB 0x00481406U +#define GPIO_58_SD2_D2 0x00481407U +#define GPIO_58_SPISIMOA 0x0048140FU + +#define GPIO_59_GPIO59 0x00481600U +#define GPIO_59_MFSRA 0x00481601U +#define GPIO_59_EM1D25 0x00481602U +#define GPIO_59_EM2D9 0x00481603U +#define GPIO_59_OUTPUTXBAR2 0x00481605U +#define GPIO_59_SPISTEB 0x00481606U +#define GPIO_59_SD2_C2 0x00481607U +#define GPIO_59_SPISOMIA 0x0048160FU + +#define GPIO_60_GPIO60 0x00481800U +#define GPIO_60_MCLKRB 0x00481801U +#define GPIO_60_EM1D24 0x00481802U +#define GPIO_60_EM2D8 0x00481803U +#define GPIO_60_OUTPUTXBAR3 0x00481805U +#define GPIO_60_SPISIMOB 0x00481806U +#define GPIO_60_SD2_D3 0x00481807U +#define GPIO_60_SPICLKA 0x0048180FU + +#define GPIO_61_GPIO61 0x00481A00U +#define GPIO_61_MFSRB 0x00481A01U +#define GPIO_61_EM1D23 0x00481A02U +#define GPIO_61_EM2D7 0x00481A03U +#define GPIO_61_OUTPUTXBAR4 0x00481A05U +#define GPIO_61_SPISOMIB 0x00481A06U +#define GPIO_61_SD2_C3 0x00481A07U +#define GPIO_61_SPISTEA 0x00481A0FU + +#define GPIO_62_GPIO62 0x00481C00U +#define GPIO_62_SCIRXDC 0x00481C01U +#define GPIO_62_EM1D22 0x00481C02U +#define GPIO_62_EM2D6 0x00481C03U +#define GPIO_62_EQEP3A 0x00481C05U +#define GPIO_62_CANRXA 0x00481C06U +#define GPIO_62_SD2_D4 0x00481C07U + +#define GPIO_63_GPIO63 0x00481E00U +#define GPIO_63_SCITXDC 0x00481E01U +#define GPIO_63_EM1D21 0x00481E02U +#define GPIO_63_EM2D5 0x00481E03U +#define GPIO_63_EQEP3B 0x00481E05U +#define GPIO_63_CANTXA 0x00481E06U +#define GPIO_63_SD2_C4 0x00481E07U +#define GPIO_63_SPISIMOB 0x00481E0FU + +#define GPIO_64_GPIO64 0x00860000U +#define GPIO_64_EM1D20 0x00860002U +#define GPIO_64_EM2D4 0x00860003U +#define GPIO_64_EQEP3S 0x00860005U +#define GPIO_64_SCIRXDA 0x00860006U +#define GPIO_64_SPISOMIB 0x0086000FU + +#define GPIO_65_GPIO65 0x00860200U +#define GPIO_65_EM1D19 0x00860202U +#define GPIO_65_EM2D3 0x00860203U +#define GPIO_65_EQEP3I 0x00860205U +#define GPIO_65_SCITXDA 0x00860206U +#define GPIO_65_SPICLKB 0x0086020FU + +#define GPIO_66_GPIO66 0x00860400U +#define GPIO_66_EM1D18 0x00860402U +#define GPIO_66_EM2D2 0x00860403U +#define GPIO_66_SDAB 0x00860406U +#define GPIO_66_SPISTEB 0x0086040FU + +#define GPIO_67_GPIO67 0x00860600U +#define GPIO_67_EM1D17 0x00860602U +#define GPIO_67_EM2D1 0x00860603U + +#define GPIO_68_GPIO68 0x00860800U +#define GPIO_68_EM1D16 0x00860802U +#define GPIO_68_EM2D0 0x00860803U + +#define GPIO_69_GPIO69 0x00860A00U +#define GPIO_69_EM1D15 0x00860A02U +#define GPIO_69_EMU0 0x00860A03U +#define GPIO_69_SCLB 0x00860A06U +#define GPIO_69_SPISIMOC 0x00860A0FU + +#define GPIO_70_GPIO70 0x00860C00U +#define GPIO_70_EM1D14 0x00860C02U +#define GPIO_70_EMU0 0x00860C03U +#define GPIO_70_CANRXA 0x00860C05U +#define GPIO_70_SCITXDB 0x00860C06U +#define GPIO_70_SPISOMIC 0x00860C0FU + +#define GPIO_71_GPIO71 0x00860E00U +#define GPIO_71_EM1D13 0x00860E02U +#define GPIO_71_EMU1 0x00860E03U +#define GPIO_71_CANTXA 0x00860E05U +#define GPIO_71_SCIRXDB 0x00860E06U +#define GPIO_71_SPICLKC 0x00860E0FU + +#define GPIO_72_GPIO72 0x00861000U +#define GPIO_72_EM1D12 0x00861002U +#define GPIO_72_CANTXB 0x00861005U +#define GPIO_72_SCITXDC 0x00861006U +#define GPIO_72_SPISTEC 0x0086100FU + +#define GPIO_73_GPIO73 0x00861200U +#define GPIO_73_EM1D11 0x00861202U +#define GPIO_73_XCLKOUT 0x00861203U +#define GPIO_73_CANRXB 0x00861205U +#define GPIO_73_SCIRXDC 0x00861206U + +#define GPIO_74_GPIO74 0x00861400U +#define GPIO_74_EM1D10 0x00861402U + +#define GPIO_75_GPIO75 0x00861600U +#define GPIO_75_EM1D9 0x00861602U + +#define GPIO_76_GPIO76 0x00861800U +#define GPIO_76_EM1D8 0x00861802U +#define GPIO_76_SCITXDD 0x00861806U + +#define GPIO_77_GPIO77 0x00861A00U +#define GPIO_77_EM1D7 0x00861A02U +#define GPIO_77_SCIRXDD 0x00861A06U + +#define GPIO_78_GPIO78 0x00861C00U +#define GPIO_78_EM1D6 0x00861C02U +#define GPIO_78_EQEP2A 0x00861C06U + +#define GPIO_79_GPIO79 0x00861E00U +#define GPIO_79_EM1D5 0x00861E02U +#define GPIO_79_EQEP2B 0x00861E06U + +#define GPIO_80_GPIO80 0x00880000U +#define GPIO_80_EM1D4 0x00880002U +#define GPIO_80_EQEP2S 0x00880006U + +#define GPIO_81_GPIO81 0x00880200U +#define GPIO_81_EM1D3 0x00880202U +#define GPIO_81_EQEP2I 0x00880206U + +#define GPIO_82_GPIO82 0x00880400U +#define GPIO_82_EM1D2 0x00880402U + +#define GPIO_83_GPIO83 0x00880600U +#define GPIO_83_EM1D1 0x00880602U + +#define GPIO_84_GPIO84 0x00880800U +#define GPIO_84_SCITXDA 0x00880805U +#define GPIO_84_MDXB 0x00880806U +#define GPIO_84_MDXA 0x0088080FU + +#define GPIO_85_GPIO85 0x00880A00U +#define GPIO_85_EM1D0 0x00880A02U +#define GPIO_85_SCIRXDA 0x00880A05U +#define GPIO_85_MDRB 0x00880A06U +#define GPIO_85_MDRA 0x00880A0FU + +#define GPIO_86_GPIO86 0x00880C00U +#define GPIO_86_EM1A13 0x00880C02U +#define GPIO_86_EM1CAS 0x00880C03U +#define GPIO_86_SCITXDB 0x00880C05U +#define GPIO_86_MCLKXB 0x00880C06U +#define GPIO_86_MCLKXA 0x00880C0FU + +#define GPIO_87_GPIO87 0x00880E00U +#define GPIO_87_EM1A14 0x00880E02U +#define GPIO_87_EM1RAS 0x00880E03U +#define GPIO_87_SCIRXDB 0x00880E05U +#define GPIO_87_MFSXB 0x00880E06U +#define GPIO_87_MFSXA 0x00880E0FU + +#define GPIO_88_GPIO88 0x00881000U +#define GPIO_88_EM1A15 0x00881002U +#define GPIO_88_EM1DQM0 0x00881003U + +#define GPIO_89_GPIO89 0x00881200U +#define GPIO_89_EM1A16 0x00881202U +#define GPIO_89_EM1DQM1 0x00881203U +#define GPIO_89_SCITXDC 0x00881206U + +#define GPIO_90_GPIO90 0x00881400U +#define GPIO_90_EM1A17 0x00881402U +#define GPIO_90_EM1DQM2 0x00881403U +#define GPIO_90_SCIRXDC 0x00881406U + +#define GPIO_91_GPIO91 0x00881600U +#define GPIO_91_EM1A18 0x00881602U +#define GPIO_91_EM1DQM3 0x00881603U +#define GPIO_91_SDAA 0x00881606U + +#define GPIO_92_GPIO92 0x00881800U +#define GPIO_92_EM1A19 0x00881802U +#define GPIO_92_EM1BA1 0x00881803U +#define GPIO_92_SCLA 0x00881806U + +#define GPIO_93_GPIO93 0x00881A00U +#define GPIO_93_EM1A20 0x00881A02U +#define GPIO_93_EM1BA0 0x00881A03U +#define GPIO_93_SCITXDD 0x00881A06U + +#define GPIO_94_GPIO94 0x00881C00U +#define GPIO_94_EM1A21 0x00881C02U +#define GPIO_94_SCIRXDD 0x00881C06U + +#define GPIO_95_GPIO95 0x00881E00U + +#define GPIO_96_GPIO96 0x00C60000U +#define GPIO_96_EM2DQM1 0x00C60003U +#define GPIO_96_EQEP1A 0x00C60005U + +#define GPIO_97_GPIO97 0x00C60200U +#define GPIO_97_EM2DQM0 0x00C60203U +#define GPIO_97_EQEP1B 0x00C60205U + +#define GPIO_98_GPIO98 0x00C60400U +#define GPIO_98_EM2A0 0x00C60403U +#define GPIO_98_EQEP1S 0x00C60405U + +#define GPIO_99_GPIO99 0x00C60600U +#define GPIO_99_EM2A1 0x00C60603U +#define GPIO_99_EQEP1I 0x00C60605U + +#define GPIO_100_GPIO100 0x00C60800U +#define GPIO_100_EM2A2 0x00C60803U +#define GPIO_100_EQEP2A 0x00C60805U +#define GPIO_100_SPISIMOC 0x00C60806U + +#define GPIO_101_GPIO101 0x00C60A00U +#define GPIO_101_EM2A3 0x00C60A03U +#define GPIO_101_EQEP2B 0x00C60A05U +#define GPIO_101_SPISOMIC 0x00C60A06U + +#define GPIO_102_GPIO102 0x00C60C00U +#define GPIO_102_EM2A4 0x00C60C03U +#define GPIO_102_EQEP2S 0x00C60C05U +#define GPIO_102_SPICLKC 0x00C60C06U + +#define GPIO_103_GPIO103 0x00C60E00U +#define GPIO_103_EM2A5 0x00C60E03U +#define GPIO_103_EQEP2I 0x00C60E05U +#define GPIO_103_SPISTEC 0x00C60E06U + +#define GPIO_104_GPIO104 0x00C61000U +#define GPIO_104_SDAA 0x00C61001U +#define GPIO_104_EM2A6 0x00C61003U +#define GPIO_104_EQEP3A 0x00C61005U +#define GPIO_104_SCITXDD 0x00C61006U + +#define GPIO_105_GPIO105 0x00C61200U +#define GPIO_105_SCLA 0x00C61201U +#define GPIO_105_EM2A7 0x00C61203U +#define GPIO_105_EQEP3B 0x00C61205U +#define GPIO_105_SCIRXDD 0x00C61206U + +#define GPIO_106_GPIO106 0x00C61400U +#define GPIO_106_EM2A8 0x00C61403U +#define GPIO_106_EQEP3S 0x00C61405U +#define GPIO_106_SCITXDC 0x00C61406U + +#define GPIO_107_GPIO107 0x00C61600U +#define GPIO_107_EM2A9 0x00C61603U +#define GPIO_107_EQEP3I 0x00C61605U +#define GPIO_107_SCIRXDC 0x00C61606U + +#define GPIO_108_GPIO108 0x00C61800U +#define GPIO_108_EM2A10 0x00C61803U + +#define GPIO_109_GPIO109 0x00C61A00U +#define GPIO_109_EM2A11 0x00C61A03U + +#define GPIO_110_GPIO110 0x00C61C00U +#define GPIO_110_EM2WAIT 0x00C61C03U + +#define GPIO_111_GPIO111 0x00C61E00U +#define GPIO_111_EM2BA0 0x00C61E03U + +#define GPIO_112_GPIO112 0x00C80000U +#define GPIO_112_EM2BA1 0x00C80003U + +#define GPIO_113_GPIO113 0x00C80200U +#define GPIO_113_EM2CAS 0x00C80203U + +#define GPIO_114_GPIO114 0x00C80400U +#define GPIO_114_EM2RAS 0x00C80403U + +#define GPIO_115_GPIO115 0x00C80600U +#define GPIO_115_EM2CS0N 0x00C80603U + +#define GPIO_116_GPIO116 0x00C80800U +#define GPIO_116_EM2CS2N 0x00C80803U + +#define GPIO_117_GPIO117 0x00C80A00U +#define GPIO_117_EM2SDCKE 0x00C80A03U + +#define GPIO_118_GPIO118 0x00C80C00U +#define GPIO_118_EM2CLK 0x00C80C03U + +#define GPIO_119_GPIO119 0x00C80E00U +#define GPIO_119_EM2RNW 0x00C80E03U + +#define GPIO_120_GPIO120 0x00C81000U +#define GPIO_120_EM2WEN 0x00C81003U +#define GPIO_120_USB0PFLT 0x00C8100FU + +#define GPIO_121_GPIO121 0x00C81200U +#define GPIO_121_EM2OEN 0x00C81203U +#define GPIO_121_USB0EPEN 0x00C8120FU + +#define GPIO_122_GPIO122 0x00C81400U +#define GPIO_122_SPISIMOC 0x00C81406U +#define GPIO_122_SD1_D1 0x00C81407U +#define GPIO_122_ODISCHRGVBUS 0x00C8140FU + +#define GPIO_123_GPIO123 0x00C81600U +#define GPIO_123_SPISOMIC 0x00C81606U +#define GPIO_123_SD1_C1 0x00C81607U +#define GPIO_123_OCHRGVBUS 0x00C8160FU + +#define GPIO_124_GPIO124 0x00C81800U +#define GPIO_124_SPICLKC 0x00C81806U +#define GPIO_124_SD1_D2 0x00C81807U +#define GPIO_124_ODMPULLDN 0x00C8180FU + +#define GPIO_125_GPIO125 0x00C81A00U +#define GPIO_125_SPISTEC 0x00C81A06U +#define GPIO_125_SD1_C2 0x00C81A07U +#define GPIO_125_ODPPULLDN 0x00C81A0FU + +#define GPIO_126_GPIO126 0x00C81C00U +#define GPIO_126_SD1_D3 0x00C81C07U +#define GPIO_126_OLSD_2_N 0x00C81C0FU + +#define GPIO_127_GPIO127 0x00C81E00U +#define GPIO_127_SD1_C3 0x00C81E07U +#define GPIO_127_OLSD_1_N 0x00C81E0FU + +#define GPIO_128_GPIO128 0x01060000U +#define GPIO_128_SD1_D4 0x01060007U +#define GPIO_128_OIDPULLUP 0x0106000FU + +#define GPIO_129_GPIO129 0x01060200U +#define GPIO_129_SD1_C4 0x01060207U +#define GPIO_129_OSPEED 0x0106020FU + +#define GPIO_130_GPIO130 0x01060400U +#define GPIO_130_SD2_D1 0x01060407U +#define GPIO_130_OSUSPEND 0x0106040FU + +#define GPIO_131_GPIO131 0x01060600U +#define GPIO_131_SD2_C1 0x01060607U +#define GPIO_131_OOE 0x0106060FU + +#define GPIO_132_GPIO132 0x01060800U +#define GPIO_132_SD2_D2 0x01060807U +#define GPIO_132_ODMSE1 0x0106080FU + +#define GPIO_133_GPIO133 0x01060A00U +#define GPIO_133_SD2_C2 0x01060A07U +#define GPIO_133_ODPDAT 0x01060A0FU + +#define GPIO_134_GPIO134 0x01060C00U +#define GPIO_134_SD2_D3 0x01060C07U +#define GPIO_134_IVBUSVALID 0x01060C0FU + +#define GPIO_135_GPIO135 0x01060E00U +#define GPIO_135_SCITXDA 0x01060E06U +#define GPIO_135_SD2_C3 0x01060E07U + +#define GPIO_136_GPIO136 0x01061000U +#define GPIO_136_SCIRXDA 0x01061006U +#define GPIO_136_SD2_D4 0x01061007U + +#define GPIO_137_GPIO137 0x01061200U +#define GPIO_137_SCITXDB 0x01061206U +#define GPIO_137_SD2_C4 0x01061207U + +#define GPIO_138_GPIO138 0x01061400U +#define GPIO_138_SCIRXDB 0x01061406U + +#define GPIO_139_GPIO139 0x01061600U +#define GPIO_139_SCIRXDC 0x01061606U + +#define GPIO_140_GPIO140 0x01061800U +#define GPIO_140_SCITXDC 0x01061806U + +#define GPIO_141_GPIO141 0x01061A00U +#define GPIO_141_SCIRXDD 0x01061A06U + +#define GPIO_142_GPIO142 0x01061C00U +#define GPIO_142_SCITXDD 0x01061C06U + +#define GPIO_143_GPIO143 0x01061E00U + +#define GPIO_144_GPIO144 0x01080000U + +#define GPIO_145_GPIO145 0x01080200U +#define GPIO_145_EPWM1A 0x01080201U + +#define GPIO_146_GPIO146 0x01080400U +#define GPIO_146_EPWM1B 0x01080401U + +#define GPIO_147_GPIO147 0x01080600U +#define GPIO_147_EPWM2A 0x01080601U + +#define GPIO_148_GPIO148 0x01080800U +#define GPIO_148_EPWM2B 0x01080801U + +#define GPIO_149_GPIO149 0x01080A00U +#define GPIO_149_EPWM3A 0x01080A01U + +#define GPIO_150_GPIO150 0x01080C00U +#define GPIO_150_EPWM3B 0x01080C01U + +#define GPIO_151_GPIO151 0x01080E00U +#define GPIO_151_EPWM4A 0x01080E01U + +#define GPIO_152_GPIO152 0x01081000U +#define GPIO_152_EPWM4B 0x01081001U + +#define GPIO_153_GPIO153 0x01081200U +#define GPIO_153_EPWM5A 0x01081201U + +#define GPIO_154_GPIO154 0x01081400U +#define GPIO_154_EPWM5B 0x01081401U + +#define GPIO_155_GPIO155 0x01081600U +#define GPIO_155_EPWM6A 0x01081601U + +#define GPIO_156_GPIO156 0x01081800U +#define GPIO_156_EPWM6B 0x01081801U + +#define GPIO_157_GPIO157 0x01081A00U +#define GPIO_157_EPWM7A 0x01081A01U + +#define GPIO_158_GPIO158 0x01081C00U +#define GPIO_158_EPWM7B 0x01081C01U + +#define GPIO_159_GPIO159 0x01081E00U +#define GPIO_159_EPWM8A 0x01081E01U + +#define GPIO_160_GPIO160 0x01460000U +#define GPIO_160_EPWM8B 0x01460001U + +#define GPIO_161_GPIO161 0x01460200U +#define GPIO_161_EPWM9A 0x01460201U + +#define GPIO_162_GPIO162 0x01460400U +#define GPIO_162_EPWM9B 0x01460401U + +#define GPIO_163_GPIO163 0x01460600U +#define GPIO_163_EPWM10A 0x01460601U + +#define GPIO_164_GPIO164 0x01460800U +#define GPIO_164_EPWM10B 0x01460801U + +#define GPIO_165_GPIO165 0x01460A00U +#define GPIO_165_EPWM11A 0x01460A01U + +#define GPIO_166_GPIO166 0x01460C00U +#define GPIO_166_EPWM11B 0x01460C01U + +#define GPIO_167_GPIO167 0x01460E00U +#define GPIO_167_EPWM12A 0x01460E01U + +#define GPIO_168_GPIO168 0x01461000U +#define GPIO_168_EPWM12B 0x01461001U + +#endif // PIN_MAP_H diff --git a/gpio_driverlib_cpu2/device/driverlib/pin_map_legacy.h b/gpio_driverlib_cpu2/device/driverlib/pin_map_legacy.h new file mode 100644 index 0000000..c503ad4 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/pin_map_legacy.h @@ -0,0 +1,95 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Legacy definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_LEGACY_H__ +#define __PIN_MAP_LEGACY_H__ + + +#include "pin_map.h" + +//***************************************************************************** +// Legacy pinmuxing MACROS - Retained for portability across devices ONLY +// Not recommended for new users +//***************************************************************************** +#define GPIO_16_SD_D1 GPIO_16_SD1_D1 + +#define GPIO_17_SD_C1 GPIO_17_SD1_C1 + +#define GPIO_18_SD_D2 GPIO_18_SD1_D2 + +#define GPIO_19_SD_C2 GPIO_19_SD1_C2 + +#define GPIO_20_SD_D3 GPIO_20_SD1_D3 + +#define GPIO_21_SD_C3 GPIO_21_SD1_C3 + +#define GPIO_22_SD_D4 GPIO_22_SD1_D4 + +#define GPIO_23_SD_C4 GPIO_23_SD1_C4 + +#define GPIO_24_SD_D5 GPIO_24_SD2_D1 + +#define GPIO_25_SD_C5 GPIO_25_SD2_C1 + +#define GPIO_26_SD_D6 GPIO_26_SD2_D2 + +#define GPIO_27_SD_C6 GPIO_27_SD2_C2 + +#define GPIO_28_SD_D7 GPIO_28_SD2_D3 + +#define GPIO_29_SD_C7 GPIO_29_SD2_C3 + +#define GPIO_30_SD_D8 GPIO_30_SD2_D4 + +#define GPIO_31_SD_C8 GPIO_31_SD2_C4 + +#define GPIO_36_EM1WAIT1 GPIO_36_EM1WAIT + +#define GPIO_110_EM2WAIT1 GPIO_110_EM2WAIT + +#define GPIO_115_EM2CS0 GPIO_115_EM2CS0N + +#define GPIO_116_EM2CS2 GPIO_116_EM2CS2N + +#define GPIO_132_ODMSE0 GPIO_132_ODMSE1 + +#endif // __PIN_MAP_LEGACY_H__ diff --git a/gpio_driverlib_cpu2/device/driverlib/sci.c b/gpio_driverlib_cpu2/device/driverlib/sci.c new file mode 100644 index 0000000..dfd8e30 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/sci.c @@ -0,0 +1,421 @@ +//########################################################################### +// +// FILE: sci.c +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sci.h" + +//***************************************************************************** +// +// SCI_setConfig +// +//***************************************************************************** +void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, uint32_t config) +{ + uint32_t divider; + + // + // Check the arguments. + // Is the required baud rate greater than the maximum rate supported? + // + ASSERT(SCI_isBaseValid(base)); + ASSERT(baud != 0U); + ASSERT((baud * 16U) <= lspclkHz); + + // + // Stop the SCI. + // + SCI_disableModule(base); + + // + // Compute the baud rate divider. + // + divider = ((lspclkHz / (baud * 8U)) - 1U); + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; + + // + // Set parity, data length, and number of stop bits. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK)) | config); + + // + // Start the SCI. + // + SCI_enableModule(base); +} + +//***************************************************************************** +// +// SCI_writeCharArray +// +//***************************************************************************** +void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } + else + { + // + // FIFO is not enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } +} + +//***************************************************************************** +// +// SCI_readCharArray +// +//***************************************************************************** +void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } + else + { + // + // FIFO is not enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive buffer. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } +} + +//***************************************************************************** +// +// SCI_enableInterrupt +// +//***************************************************************************** +void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_disableInterrupt +// +//***************************************************************************** +void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SCI_getInterruptStatus(uint32_t base) +{ + uint32_t interruptStatus = 0; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the interrupt status. + // + if((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == SCI_CTL2_TXRDY) + { + interruptStatus |= SCI_INT_TXRDY; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXERROR) == SCI_RXST_RXERROR) + { + interruptStatus |= SCI_INT_RXERR; + } + if(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == SCI_RXST_RXRDY) || + ((HWREGH(base + SCI_O_RXST) & SCI_RXST_BRKDT) == SCI_RXST_BRKDT)) + { + interruptStatus |= SCI_INT_RXRDY_BRKDT; + } + if((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFINT) == SCI_FFTX_TXFFINT) + { + interruptStatus |= SCI_INT_TXFF; + } + if((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFINT) == SCI_FFRX_RXFFINT) + { + interruptStatus |= SCI_INT_RXFF; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_FE) == SCI_RXST_FE) + { + interruptStatus |= SCI_INT_FE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_OE) == SCI_RXST_OE) + { + interruptStatus |= SCI_INT_OE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_PE) == SCI_RXST_PE) + { + interruptStatus |= SCI_INT_PE; + } + + return(interruptStatus); +} + +//***************************************************************************** +// +// SCI_clearInterruptStatus +// +//***************************************************************************** +void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + if(((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) || + ((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) || + ((intFlags & SCI_INT_FE) == SCI_INT_FE) || + ((intFlags & SCI_INT_OE) == SCI_INT_OE) || + ((intFlags & SCI_INT_PE) == SCI_INT_PE)) + { + SCI_performSoftwareReset(base); + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFINTCLR; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR; + } +} + +//***************************************************************************** +// +// SCI_setBaud +// +//***************************************************************************** +void SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud) +{ + uint32_t divider; + + // + // Compute the baud rate divider {ROUND TO NEAREST INTEGER} + // + divider = ((float)((float)lspclkHz / ((float)baud * 8.0F)) - 1.0F) + 0.5F; + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; +} + +//***************************************************************************** +// +// SCI_setWakeFlag +// +//***************************************************************************** +void SCI_setWakeFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the TX wake flag bit to indicate + // that the next frame is an address frame. + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_TXWAKE; +} diff --git a/gpio_driverlib_cpu2/device/driverlib/sci.h b/gpio_driverlib_cpu2/device/driverlib/sci.h new file mode 100644 index 0000000..454ee12 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/sci.h @@ -0,0 +1,1646 @@ +//########################################################################### +// +// FILE: sci.h +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SCI_H +#define SCI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sci_api SCI +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_sci.h" +#include "inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and +// SCI_clearInterruptStatus as the intFlags parameter, and returned from +// SCI_getInterruptStatus. +// +//***************************************************************************** +#define SCI_INT_RXERR 0x01U //!< RXERR interrupt +#define SCI_INT_RXRDY_BRKDT 0x02U //!< RXRDY interrupt +#define SCI_INT_TXRDY 0x04U //!< TXRDY interrupt +#define SCI_INT_TXFF 0x08U //!< TX FIFO level interrupt +#define SCI_INT_RXFF 0x10U //!< RX FIFO level interrupt +#define SCI_INT_FE 0x20U //!< Frame Error +#define SCI_INT_OE 0x40U //!< Overrun Error +#define SCI_INT_PE 0x80U //!< Parity Error + +//***************************************************************************** +// +// Values that can be passed to SCI_setConfig as the config parameter +// and returned by SCI_getConfig in the config parameter. +// Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to +// SCI_setParityMode as the parity parameter, and are returned by +// SCI_getParityMode. +// +//***************************************************************************** +#define SCI_CONFIG_WLEN_MASK 0x0007U //!< Mask for extracting word length +#define SCI_CONFIG_WLEN_8 0x0007U //!< 8 bit data +#define SCI_CONFIG_WLEN_7 0x0006U //!< 7 bit data +#define SCI_CONFIG_WLEN_6 0x0005U //!< 6 bit data +#define SCI_CONFIG_WLEN_5 0x0004U //!< 5 bit data +#define SCI_CONFIG_WLEN_4 0x0003U //!< 4 bit data +#define SCI_CONFIG_WLEN_3 0x0002U //!< 3 bit data +#define SCI_CONFIG_WLEN_2 0x0001U //!< 2 bit data +#define SCI_CONFIG_WLEN_1 0x0000U //!< 1 bit data +#define SCI_CONFIG_STOP_MASK 0x0080U //!< Mask for extracting stop bits +#define SCI_CONFIG_STOP_ONE 0x0000U //!< One stop bit +#define SCI_CONFIG_STOP_TWO 0x0080U //!< Two stop bits +#define SCI_CONFIG_PAR_MASK 0x0060U //!< Parity Mask + +//***************************************************************************** +// +//! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to +//! describe the parity of the SCI communication. +// +//***************************************************************************** +typedef enum +{ + SCI_CONFIG_PAR_NONE = 0x0000U, //!< No parity + SCI_CONFIG_PAR_EVEN = 0x0060U, //!< Even parity + SCI_CONFIG_PAR_ODD = 0x0020U //!< Odd parity +} SCI_ParityType; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel +//! parameter and returned by SCI_getFIFOInteruptLevel() and +//! SCI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_TX0 = 0x0000U, //!< Transmit interrupt empty + SCI_FIFO_TX1 = 0x0001U, //!< Transmit interrupt 1/16 full + SCI_FIFO_TX2 = 0x0002U, //!< Transmit interrupt 2/16 full + SCI_FIFO_TX3 = 0x0003U, //!< Transmit interrupt 3/16 full + SCI_FIFO_TX4 = 0x0004U, //!< Transmit interrupt 4/16 full + SCI_FIFO_TX5 = 0x0005U, //!< Transmit interrupt 5/16 full + SCI_FIFO_TX6 = 0x0006U, //!< Transmit interrupt 6/16 full + SCI_FIFO_TX7 = 0x0007U, //!< Transmit interrupt 7/16 full + SCI_FIFO_TX8 = 0x0008U, //!< Transmit interrupt 8/16 full + SCI_FIFO_TX9 = 0x0009U, //!< Transmit interrupt 9/16 full + SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full + SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full + SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full + SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full + SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full + SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full + SCI_FIFO_TX16 = 0x0010U //!< Transmit interrupt full +} SCI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel +//! parameter and returned by SCI_getFIFOInterruptLevel() and +//! SCI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_RX0 = 0x0000U, //!< Receive interrupt empty + SCI_FIFO_RX1 = 0x0001U, //!< Receive interrupt 1/16 full + SCI_FIFO_RX2 = 0x0002U, //!< Receive interrupt 2/16 full + SCI_FIFO_RX3 = 0x0003U, //!< Receive interrupt 3/16 full + SCI_FIFO_RX4 = 0x0004U, //!< Receive interrupt 4/16 full + SCI_FIFO_RX5 = 0x0005U, //!< Receive interrupt 5/16 full + SCI_FIFO_RX6 = 0x0006U, //!< Receive interrupt 6/16 full + SCI_FIFO_RX7 = 0x0007U, //!< Receive interrupt 7/16 full + SCI_FIFO_RX8 = 0x0008U, //!< Receive interrupt 8/16 full + SCI_FIFO_RX9 = 0x0009U, //!< Receive interrupt 9/16 full + SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full + SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full + SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full + SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full + SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full + SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full + SCI_FIFO_RX16 = 0x0010U //!< Receive interrupt full +} SCI_RxFIFOLevel; + +//***************************************************************************** +// +// Values returned from SCI_getRxStatus(). These correspond to the different +// bits and flags of the SCIRXST register. +// +//***************************************************************************** +#define SCI_RXSTATUS_WAKE 0x0002U //!< Receiver wake up detect +#define SCI_RXSTATUS_PARITY 0x0004U //!< Parity error +#define SCI_RXSTATUS_OVERRUN 0x0008U //!< Overrun error +#define SCI_RXSTATUS_FRAMING 0x0010U //!< Framing error +#define SCI_RXSTATUS_BREAK 0x0020U //!< Break detect +#define SCI_RXSTATUS_READY 0x0040U //!< Receiver ready +#define SCI_RXSTATUS_ERROR 0x0080U //!< Receiver error + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a SCI base address. +//! +//! \param base is the base address of the SCI port. +//! +//! This function determines if a SCI port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SCI_isBaseValid(uint32_t base) +{ + return( + (base == SCIA_BASE) || + (base == SCIB_BASE) || + (base == SCIC_BASE) || + (base == SCID_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param base is the base address of the SCI port. +//! \param parity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e parity parameter must be one of the following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setParityMode(uint32_t base, SCI_ParityType parity) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the parity mode. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK)) | (uint16_t)parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param base is the base address of the SCI port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of the +//! following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +// +//***************************************************************************** +static inline SCI_ParityType +SCI_getParityMode(uint32_t base) +{ + uint16_t parity; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current parity setting. + // + parity = (HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK)); + + return((SCI_ParityType)parity); +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to address-bit mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to address-bit mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setAddrMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to idle-line mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to idle-line protocol. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setIdleMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Locks Autobaud. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs an autobaud lock for the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_lockAutobaud(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Prime the baud register + // + HWREGH(base + SCI_O_HBAUD) = 0x0U; + HWREGH(base + SCI_O_LBAUD) = 0x1U; + + // + // Prepare for autobaud detection. + // Set the CDC bit to enable autobaud detection and clear the ABD bit. + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_CDC; + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + + // + // Wait until we correctly read an 'A' or 'a' and lock + // + while((HWREGH(base + SCI_O_FFCT) & SCI_FFCT_ABD) != SCI_FFCT_ABD) + { + } + + // + // After autobaud lock, clear the ABD and CDC bits + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + HWREGH(base + SCI_O_FFCT) &= ~SCI_FFCT_CDC; +} + +//***************************************************************************** +// +//! Sets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as one of +//! the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or +//! \b SCI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as one of +//! the following +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel, + SCI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SCI_O_FFTX) = (HWREGH(base + SCI_O_FFTX) & + (~SCI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SCI_O_FFRX) = (HWREGH(base + SCI_O_FFRX) & + (~SCI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is a pointer to storage for the transmit FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel, + SCI_RxFIFOLevel *rxLevel) +{ + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SCI_TxFIFOLevel)(HWREGH(base + SCI_O_FFTX) & + SCI_FFTX_TXFFIL_M); + *rxLevel = (SCI_RxFIFOLevel)(HWREGH(base + SCI_O_FFRX) & + SCI_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Gets the current configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is a pointer to storage for the baud rate. +//! \param config is a pointer to storage for the data format. +//! +//! The baud rate and data format for the SCI is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e config is enumerated the same as the \e config parameter of +//! SCI_setConfig(). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud, + uint32_t *config) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Compute the baud rate. + // + *baud = lspclkHz / + ((1U + (((uint32_t)HWREGH(base + SCI_O_HBAUD) << 8U) | + HWREGH(base + SCI_O_LBAUD))) * 8U); + + // + // Get the parity, data length, and number of stop bits. + // + *config = (uint32_t)HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and +//! RXENA bits which enables transmit and receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX, TX, and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_RXENA | + SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the +//! data has been sent before disable the module during transmission. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~(SCI_FFTX_SCIFFENA); + + // + // Disable the SCI. + // + HWREGH(base + SCI_O_CTL1) &= ~(SCI_CTL1_TXENA | SCI_CTL1_RXENA); +} + +//***************************************************************************** +// +//! Enables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA bit +//! which enables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable TX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the TXENA bit +//! which disables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable TX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_TXENA; +} + +//***************************************************************************** +// +//! Enables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the RXENA bit +//! which enables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_RXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the RXENA bit +//! which disables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable RX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXENA; +} + +//***************************************************************************** +// +//! Enables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the sleep mode in SCI by setting the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set sleep bit + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Disables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the sleep mode in SCI by clearing the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear sleep bit + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions enables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIFFENA | SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions disables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Determines if the FIFO enhancement is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not the FIFO enhancement +//! is enabled. +//! +//! \return Returns \b true if the FIFO enhancement is enabled or \b false +//! if the FIFO enhancement is disabled. +// +//***************************************************************************** +static inline bool +SCI_isFIFOEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return true if the FIFO is enabled and false if it is disabled. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_SCIFFENA) == + SCI_FFTX_SCIFFENA) ? true : false); +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the receive FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the transmit FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the SCI Transmit and Receive Channels +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets transmit and receive channels in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetChannels(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the Tx and Rx Channels + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive buffer when the +//! FIFO enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive buffer. +//! +//! \return Returns \b true if there is data in the receive buffer or \b false +//! if there is no data in the receive buffer. +// +//***************************************************************************** +static inline bool +SCI_isDataAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of characters with FIFO disabled. + // + return(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == + SCI_RXST_RXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit buffer when the FIFO +//! enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit buffer when not using the FIFO enhancement. +//! +//! \return Returns \b true if there is space available in the transmit buffer +//! or \b false if there is no space available in the transmit buffer. +// +//***************************************************************************** +static inline bool +SCI_isSpaceAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of space. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == + SCI_CTL2_TXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3 +//! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16 +// +//***************************************************************************** +static inline SCI_TxFIFOLevel +SCI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_TxFIFOLevel)((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) >> + SCI_FFTX_TXFFST_S)); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3 +//! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16 +// +//***************************************************************************** +static inline SCI_RxFIFOLevel +SCI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_RxFIFOLevel)((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFST_M) >> + SCI_FFRX_RXFFST_S)); +} + +//***************************************************************************** +// +//! Determines whether the SCI transmitter is busy or not. +//! +//! \param base is the base address of the SCI port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware when the FIFO is not enabled. When the FIFO is +//! enabled, this function allows the caller to determine whether there is any +//! data in the FIFO. +//! +//! Without the FIFO enabled, if \b false is returned, the transmit buffer and +//! shift registers are empty and the transmitter is not busy. With the FIFO +//! enabled, if \b false is returned, the FIFO is empty. This does not +//! necessarily mean that the transmitter is not busy. The empty FIFO does not +//! reflect the status of the transmitter shift register. The FIFO may be empty +//! while the transmitter is still transmitting data. +//! +//! \return Returns \b true if the SCI is transmitting or \b false if +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SCI_isTransmitterBusy(uint32_t base) +{ + // + // Check the argument. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // With FIFO enhancement, determine if the SCI is busy. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) != + 0U) ? true : false); + } + else + { + // + // Without FIFO enhancement, determine if the SCI is busy. + // Check if the transmit buffer and shift register empty. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXEMPTY) == + SCI_CTL2_TXEMPTY) ? false : true); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. \e data is a uint16_t but +//! only 8 bits are written to the SCI port. SCI only transmits 8 bit +//! characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! before returning. \e data is a uint16_t but only 8 bits are written to the +//! SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Writes the character \e data to the transmit buffer for the specified port. +//! This function does not block and only writes to the transmit buffer. +//! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus() +//! to determine if the transmit buffer or FIFO have space available. +//! \e data is a uint16_t but only 8 bits are written to the SCI port. SCI +//! only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets current receiver status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns the current receiver status flags. The returned +//! error flags are equivalent to the error bits returned via the previous +//! reading or receiving of a character with the exception that the overrun +//! error is set immediately the overrun occurs rather than when a character +//! is next read. +//! +//! \return Returns a bitwise OR combination of the receiver status flags, +//! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN, +//! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY, +//! and \b SCI_RXSTATUS_ERROR. +// +//***************************************************************************** +static inline uint16_t +SCI_getRxStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current value of the receive status register. + // + return(HWREGH(base + SCI_O_RXST)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. Returns immediately in case of Error. +//! +//! \return Returns the character read from the specified port as \e uint16_t +//! or 0x0 in case of Error. The application must use +//! SCI_getRxStatus() API to check if some error occurred before +//! consuming the data +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + // + //If there is any error return + // + if((SCI_getRxStatus(base) & SCI_RXSTATUS_ERROR) != 0U) + { + return(0U); + } + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. If there +//! is no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port as \e uint16_t. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. This +//! function does not block and only reads the receive buffer. The user should +//! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if +//! the receive buffer or FIFO have data available. +//! +//! \return Returns \e uin16_t which is read from the receive buffer. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Performs a software reset of the SCI and Clears all reported receiver +//! status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs a software reset of the SCI port. It affects the +//! operating flags of the SCI, but it neither affects the configuration bits +//! nor restores the reset values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_performSoftwareReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // To clear all errors a sw reset of the module is required + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SWRESET; + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SWRESET; +} + +//***************************************************************************** +// +//! Enables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the loop back test mode where the Tx pin is internally connected +//! to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the loop back mode. + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Disables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the loop back test mode where the Tx pin is no longer internally +//! connected to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the loop back mode. + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Get the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the receive FIFO overflow flag status. +//! +//! \return Returns \b true if overflow has occurred, else returned \b false if +//! an overflow hasn't occurred. +// +//***************************************************************************** +static inline bool +SCI_getOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current FIFO overflow status + // + return((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFOVF) == SCI_FFRX_RXFFOVF); +} + +//***************************************************************************** +// +//! Clear the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions clears the receive FIFO overflow flag status. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_clearOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the current FIFO overflow status + // + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFOVRCLR; +} + +//***************************************************************************** +// +//! Sets the configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! \param config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the SCI for operation in the specified data +//! format. The baud rate is provided in the \e baud parameter and the data +//! format in the \e config parameter. +//! +//! The \e config parameter is the bitwise OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b SCI_CONFIG_WLEN_8, +//! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5, +//! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and +//! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte +//! (respectively). +//! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, +//! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity +//! bit, odd parity bit respectively). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! A baud rate divider (BRR) is used in this function to calculate the +//! baud rate. The value of BRR is calculated in float and type casted as int +//! to be fed in the \b SCIHBAUD and \b SCILBAUD registers. This conversion +//! brings an error in the calculated baud rate and the requested. Error will +//! be significant when operating at higher baud rates. The error is due to +//! lower BRR integer value granularity at higher baud rates. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, + uint32_t config); + +//***************************************************************************** +// +//! Waits to send an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be transmitted. +//! It is pointer to the array of characters to be transmitted. +//! \param length is the length of the array, or number of characters in the +//! array to be transmitted. +//! +//! Sends the number of characters specified by \e length, starting at the +//! address \e array, out of the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! and \e length number of characters are transmitted before returning. +//! \e array is a pointer to uint16_ts but only the least significant 8 bits +//! are written to the SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length); + +//***************************************************************************** +// +//! Waits to receive an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be received. +//! It is a pointer to the array of characters to be received. +//! \param length is the length of the array, or number of characters in the +//! array to be received. +//! +//! Receives an array of characters from the receive buffer for the specified +//! port, and stores them as an array of characters starting at address +//! \e array. This function waits until the \e length number of characters are +//! received before returning. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length); + +//***************************************************************************** +// +//! Enables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter is the bitwise OR of any of the following: +//! +//! - \b SCI_INT_RXERR - RXERR Interrupt +//! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt +//! - \b SCI_INT_TXRDY - TXRDY Interrupt +//! - \b SCI_INT_TXFF - TX FIFO Level Interrupt +//! - \b SCI_INT_RXFF - RX FIFO Level Interrupt +//! - \b SCI_INT_FE - Frame Error +//! - \b SCI_INT_OE - Overrun Error +//! - \b SCI_INT_PE - Parity Error +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the SCI port. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SCI_enableInterrupt(). +// +//***************************************************************************** +extern uint32_t +SCI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SCI interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Sets SCI Baud rate. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! +//! This function configures the SCI for operation in the specified baud rate +//! The baud rate is provided in the \e baud parameter. +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock() +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud); + +//***************************************************************************** +// +//! Sets the SCI TXWAKE flag +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the TXWAKE flag bit to indicate that the next frame +//! is an address frame. +//! TXWAKE bit controls selection of data-transmit feature based on +//! which mode is selected from idle-line and address-bit. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setWakeFlag(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SCI_H diff --git a/gpio_driverlib_cpu2/device/driverlib/sdfm.c b/gpio_driverlib_cpu2/device/driverlib/sdfm.c new file mode 100644 index 0000000..41bc605 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/sdfm.c @@ -0,0 +1,188 @@ +//########################################################################### +// +// FILE: sdfm.c +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sdfm.h" + +//***************************************************************************** +// +// Defines for filter configurations. Not intended for use by application code. +// +//***************************************************************************** +// +// Get filter oversampling ratio +// +#define SDFM_GET_OSR(C) ((C) >> 8U) + +// +// Maximum acceptable comparator filter oversampling ratio +// +#define SDFM_MAX_COMP_FILTER_OSR 31U + +// +// Maximum acceptable data filter oversampling ratio +// +#define SDFM_MAX_DATA_FILTER_OSR 255U + +// +// Get the filter type +// +#define SDFM_GET_FILTER_TYPE(C) ((C) & 0x30U) + +// +// Get the filter number +// +#define SDFM_GET_FILTER_NUMBER(C) ((C) & 0x3U) + + +// +// Get data shift value +// +#define SDFM_GET_SHIFT_VALUE(C) (((C) >> 2U) & 0x1FU) + +//***************************************************************************** +// +// SDFM_configComparator +// +//***************************************************************************** +void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_COMP_FILTER_OSR) + { + ratio = SDFM_MAX_COMP_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setComparatorFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setCompFilterOverSamplingRatio(base, filter, ratio); + + // + // Set the comparator high threshold value + // + SDFM_setCompFilterHighThreshold(base, filter, + SDFM_GET_HIGH_THRESHOLD(config2)); + + // + // Set the comparator low threshold value + // + SDFM_setCompFilterLowThreshold(base, filter, + SDFM_GET_LOW_THRESHOLD(config2)); + +} + +//***************************************************************************** +// +// SDFM_configDataFilter +// +//***************************************************************************** +void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_DATA_FILTER_OSR) + { + ratio = SDFM_MAX_DATA_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setFilterOverSamplingRatio(base, filter, ratio); + + // + // If filter switch on + // + if((config2 & SDFM_FILTER_ENABLE) == SDFM_FILTER_ENABLE) + { + SDFM_enableFilter(base, filter); + } + else + { + SDFM_disableFilter(base, filter); + } + + // + // Set output data format + // + SDFM_setOutputDataFormat(base, filter, + (SDFM_OutputDataFormat)(config2 & 0x1U)); + + // + // Set the shift value if data is in 16-bit 2's complement format + // + if((config2 & 0x1U) == (uint16_t)(SDFM_DATA_FORMAT_16_BIT)) + { + SDFM_setDataShiftValue(base, filter, SDFM_GET_SHIFT_VALUE(config2)); + } +} + + diff --git a/gpio_driverlib_cpu2/device/driverlib/sdfm.h b/gpio_driverlib_cpu2/device/driverlib/sdfm.h new file mode 100644 index 0000000..afbdfb7 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/sdfm.h @@ -0,0 +1,1178 @@ +//########################################################################### +// +// FILE: sdfm.h +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef SDFM_H +#define SDFM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sdfm_api SDFM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_types.h" +#include "inc/hw_sdfm.h" +#include "inc/hw_memmap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//! Macro to get the low threshold +//! +#define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C)) + +//! Macro to get the high threshold +//! +#define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U)) + + +//! Macro to convert comparator over sampling ratio to acceptable bit location +//! +#define SDFM_SET_OSR(X) (((X) - 1U) << 8U) +//! Macro to convert the data shift bit values to acceptable bit location +//! +#define SDFM_SHIFT_VALUE(X) ((X) << 2U) + +//! Macro to combine high threshold and low threshold values +//! +#define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L)) + +//! Macro to set the FIFO level to acceptable bit location +//! +#define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U) + +//! Macro to set and enable the zero cross threshold value. +//! +#define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X)) + +//! Macros to enable or disable filter. +//! +#define SDFM_FILTER_DISABLE 0x0U +#define SDFM_FILTER_ENABLE 0x2U + +//***************************************************************************** +// +//! Values that can be returned from SDFM_getThresholdStatus() +// +//***************************************************************************** +typedef enum +{ + SDFM_OUTPUT_WITHIN_THRESHOLD = 0, //!< SDFM output is within threshold + SDFM_OUTPUT_ABOVE_THRESHOLD = 1, //!< SDFM output is above threshold + SDFM_OUTPUT_BELOW_THRESHOLD = 2 //!< SDFM output is below threshold +} SDFM_OutputThresholdStatus; + +//***************************************************************************** +// +//! Values that can be passed to all functions as the \e filterNumber +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SDFM_FILTER_1 = 0, //!< Digital filter 1 + SDFM_FILTER_2 = 1, //!< Digital filter 2 + SDFM_FILTER_3 = 2, //!< Digital filter 3 + SDFM_FILTER_4 = 3 //!< Digital filter 4 +} SDFM_FilterNumber; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setFilterType(), +//! SDFM_setComparatorFilterType() as the \e filterType parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital filter with SincFast structure. + SDFM_FILTER_SINC_FAST = 0x00, + //! Digital filter with Sinc1 structure + SDFM_FILTER_SINC_1 = 0x10, + //! Digital filter with Sinc3 structure. + SDFM_FILTER_SINC_2 = 0x20, + //! Digital filter with Sinc4 structure. + SDFM_FILTER_SINC_3 = 0x30 +} SDFM_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setupModulatorClock(),as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Modulator clock is identical to the data rate + SDFM_MODULATOR_CLK_EQUAL_DATA_RATE = 0, + //! Modulator clock is half the data rate + SDFM_MODULATOR_CLK_HALF_DATA_RATE = 1, + //! Modulator clock is off. Data is Manchester coded. + SDFM_MODULATOR_CLK_OFF = 2, + //! Modulator clock is double the data rate. + SDFM_MODULATOR_CLK_DOUBLE_DATA_RATE = 3 +} SDFM_ModulatorClockMode; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setOutputDataFormat(),as the +//! \e dataFormat parameter. +// +//***************************************************************************** +typedef enum +{ + //! Filter output is in 16 bits 2's complement format. + SDFM_DATA_FORMAT_16_BIT = 0, + //! Filter output is in 32 bits 2's complement format. + SDFM_DATA_FORMAT_32_BIT = 1 +} SDFM_OutputDataFormat; + +//***************************************************************************** +// +// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt +// as intFlags parameter +// +//***************************************************************************** +//! Interrupt is generated if Modulator fails. +//! +#define SDFM_MODULATOR_FAILURE_INTERRUPT 0x200U +//! Interrupt on Comparator low-level threshold. +//! +#define SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT 0x40U +//! Interrupt on Comparator high-level threshold. +//! +#define SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT 0x20U +//! Interrupt on Acknowledge flag +//! +#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to SDFM_clearInterruptFlag flags parameter +// +//***************************************************************************** +//! Main interrupt flag +//! +#define SDFM_MAIN_INTERRUPT_FLAG 0x80000000U +//! Filter 1 high -level threshold flag +//! +#define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG 0x1U +//! Filter 1 low -level threshold flag +//! +#define SDFM_FILTER_1_LOW_THRESHOLD_FLAG 0x2U +//! Filter 2 high -level threshold flag +//! +#define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG 0x4U +//! Filter 2 low -level threshold flag +//! +#define SDFM_FILTER_2_LOW_THRESHOLD_FLAG 0x8U +//! Filter 3 high -level threshold flag +//! +#define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG 0x10U +//! Filter 3 low -level threshold flag +//! +#define SDFM_FILTER_3_LOW_THRESHOLD_FLAG 0x20U +//! Filter 4 high -level threshold flag +//! +#define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG 0x40U +//! Filter 4 low -level threshold flag +//! +#define SDFM_FILTER_4_LOW_THRESHOLD_FLAG 0x80U +//! Filter 1 modulator failed flag +//! +#define SDFM_FILTER_1_MOD_FAILED_FLAG 0x100U +//! Filter 2 modulator failed flag +//! +#define SDFM_FILTER_2_MOD_FAILED_FLAG 0x200U +//! Filter 3 modulator failed flag +//! +#define SDFM_FILTER_3_MOD_FAILED_FLAG 0x400U +//! Filter 4 modulator failed flag +//! +#define SDFM_FILTER_4_MOD_FAILED_FLAG 0x800U +//! Filter 1 new data flag +//! +#define SDFM_FILTER_1_NEW_DATA_FLAG 0x1000U +//! Filter 2 new data flag +//! +#define SDFM_FILTER_2_NEW_DATA_FLAG 0x2000U +//! Filter 3 new data flag +//! +#define SDFM_FILTER_3_NEW_DATA_FLAG 0x4000U +//! Filter 4 new data flag +//! +#define SDFM_FILTER_4_NEW_DATA_FLAG 0x8000U + +//***************************************************************************** +// +//! \internal +//! Checks SDFM base address. +//! +//! \param base specifies the SDFM module base address. +//! +//! This function determines if SDFM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SDFM_isBaseValid(uint32_t base) +{ + return( + (base == SDFM1_BASE) || + (base == SDFM2_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables data filter to be reset by an external source (PWM +//! compare output). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables data filter from being reset by an external source +//! (PWM compare output). +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Enable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables the filter specified by the \e filterNumber variable. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables the filter specified by the \e filterNumber +//! variable. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Set filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the filter type or structure. +//! +//! This function sets the filter type or structure to be used as specified by +//! filterType for the selected filter number as specified by filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SST bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_SST_M)) | + ((uint16_t)filterType << 6U); + EDIS; +} + +//***************************************************************************** +// +//! Set data filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the data filter over sampling ratio. +//! +//! This function sets the filter oversampling ratio for the filter specified +//! by the filterNumber variable.Valid values for the variable +//! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio +//! will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 256U); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DOSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_DOSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Set modulator clock mode. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param clockMode is the modulator clock mode. +//! +//! This function sets the modulator clock mode specified by clockMode +//! for the filter specified by filterNumber. +//! +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_ModulatorClockMode clockMode) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCTLPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to MOD bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCTLPARM1_MOD_M)) | + (uint16_t)clockMode; + + EDIS; +} + +//***************************************************************************** +// +//! Set the output data format +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param dataFormat is the output data format. +//! +//! This function sets the output data format for the filter specified by +//! filterNumber. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_OutputDataFormat dataFormat) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DR bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_DR)) | + ((uint16_t)dataFormat << 10U); + EDIS; +} + +//***************************************************************************** +// +//! Set data shift value. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param shiftValue is the data shift value. +//! +//! This function sets the shift value for the 16 bit 2's complement data +//! format. The valid maximum value for shiftValue is 31. +//! +//! \b Note: Use this function with 16 bit 2's complement data format only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t shiftValue) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(shiftValue < 32U); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SH bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_SH_M)) | + (shiftValue << SDFM_SDDPARM1_SH_S); + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output high-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param highThreshold is the high-level threshold. +//! +//! This function sets the unsigned high-level threshold value for the +//! Comparator filter output. If the output value of the filter exceeds +//! highThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t highThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(highThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPH1 + ((uint32_t)filterNumber * 16U); + + // + // Write to HLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPH1_HLT_M) | highThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output low-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param lowThreshold is the low-level threshold. +//! +//! This function sets the unsigned low-level threshold value for the +//! Comparator filter output. If the output value of the filter gets below +//! lowThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t lowThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(lowThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPL1 + ((uint32_t)filterNumber * 16U); + + // + // Write to LLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPL1_LLT_M) | lowThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Enable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function enables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter specified +//! by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, Modulator failure + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) |= + (intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) |= SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Disable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function disables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter +//! specified by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, modulator failure interrupts + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) &= + ~(intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) &= ~SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Set the comparator filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the comparator filter type or structure. +//! +//! This function sets the Comparator filter type or structure to be used as +//! specified by filterType for the selected filter number as specified by +//! filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to CS1_CS0 bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_CS1_CS0_M)) | + ((uint16_t)filterType << 3U); + EDIS; +} + +//***************************************************************************** +// +//! Set Comparator filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the comparator filter over sampling ration. +//! +//! This function sets the comparator filter oversampling ratio for the filter +//! specified by the filterNumber.Valid values for the variable +//! overSamplingRatio are 0 to 31 inclusive. +//! The actual oversampling ratio will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setCompFilterOverSamplingRatio(uint32_t base, + SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 32U); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to COSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_COSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Get the filter data output. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the latest data filter output. Depending on the +//! filter data output format selected, the valid value will be the lower 16 +//! bits or the whole 32 bits of the returned value. +//! +//! \return Returns the latest data filter output. +//***************************************************************************** +static inline uint32_t +SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDDATA bits + // + return(HWREG(base + SDFM_O_SDDATA1 + ((uint32_t)filterNumber * 16U))); +} + +//***************************************************************************** +// +//! Get the Comparator threshold status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Comparator output threshold status for the given +//! filterNumber. +//! +//! \return Returns the following status flags. +//! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the +//! specified threshold. +//! - \b SDFM_OUTPUT_ABOVE_THRESHOLD if the output is above the high +//! threshold +//! - \b SDFM_OUTPUT_BELOW_THRESHOLD if the output is below the low +//! threshold. +//! +//***************************************************************************** +static inline SDFM_OutputThresholdStatus +SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG high/low threshold bits + // + return((SDFM_OutputThresholdStatus)((HWREG(base + SDFM_O_SDIFLG) >> + (2U * (uint16_t)filterNumber)) & 0x3U)); +} + +//***************************************************************************** +// +//! Get the Modulator status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Modulator status. +//! +//! \return Returns true if the Modulator is operating normally +//! Returns false if the Modulator has failed +//! +//***************************************************************************** +static inline bool +SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MF1, MF2, MF3 OR MF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 8U)) & + 0x1U) != 0x1U); +} + +//***************************************************************************** +// +//! Check if new Filter data is available. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns new filter data status. +//! +//! \return Returns \b true if new filter data is available +//! Returns \b false if no new filter data is available +//! +//***************************************************************************** +static inline bool +SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG AF1, AF2, AF3 OR AF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 12U)) & + 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Get pending interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function returns any pending interrupt status. +//! +//! \return Returns \b true if there is a pending interrupt. +//! Returns \b false if no interrupt is pending. +//! +//***************************************************************************** +static inline bool +SDFM_getIsrStatus(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MIF + // + return((HWREG(base + SDFM_O_SDIFLG) >> 31U) == 0x1U); +} + +//***************************************************************************** +// +//! Clear pending flags. +//! +//! \param base is the base address of the SDFM module +//! \param flag is the SDFM status +//! +//! This function clears the specified pending interrupt flag. +//! Valid values are +//! SDFM_MAIN_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG, +//! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG, +//! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG, +//! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG, +//! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_4_LOW_THRESHOLD_FLAG or any combination of the above +//! flags. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_clearInterruptFlag(uint32_t base, uint32_t flag) +{ + ASSERT(SDFM_isBaseValid(base)); + ASSERT((flag & 0x8000FFFFU) == flag); + + // + // Write to SDIFLGCLR register + // + HWREG(base + SDFM_O_SDIFLGCLR) |= flag; +} + +//***************************************************************************** +// +//! Enable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) |= SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) &= ~SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Enable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) |= SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) &= ~SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Configures SDFM comparator for filter config & threshold values +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio. +//! \param config2 is high-level and low-level threshold values. +//! +//! This function configures the comparator filter for filter config and +//! threshold values based on provided inputs. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] filter number +//! - config1.[7:4] filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location. +//! For example the value +//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16)) +//! will select Filter 1, SINC 2 type with an oversampling ratio of 16. +//! +//! The config2 parameter is the logical OR of the filter high and low +//! threshold values. +//! The bit definitions for config2 are as follow: +//! - config2.[15:0] low threshold +//! - config2.[31:16] high threshold +//! The upper 16 bits define the high threshold and the lower +//! 16 bits define the low threshold. +//! SDFM_THRESHOLD(H,L) can be used to combine the high and low thresholds. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2); + +//***************************************************************************** +// +//! Configure SDFM data filter +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio +//! configuration. +//! \param config2 is filter switch, data representation and data shift values +//! configuration. +//! +//! This function configures the data filter based on configurations +//! config1 and config2. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] Filter number +//! - config1.[7:4] Filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio , which ranges [1,256] inclusive , in the appropriate bit location +//! for config1. For example the value +//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64)) +//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64. +//! +//! The config2 parameter is the logical OR of data representation, filter +//! switch, and data shift values +//! The bit definitions for config2 are as follow: +//! - config2.[0] Data representation +//! - config2.[1] Filter switch +//! - config2.[15:2] Shift values +//! Valid values for data representation are given in SDFM_OutputDataFormat +//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the +//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value +//! of the data shift value,which ranges [0,31] inclusive, in the appropriate +//! bit location for config2. +//! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data +//! representation format. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif +#endif // SDFM_H diff --git a/gpio_driverlib_cpu2/device/driverlib/spi.c b/gpio_driverlib_cpu2/device/driverlib/spi.c new file mode 100644 index 0000000..b077369 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/spi.c @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: spi.c +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "spi.h" + +//***************************************************************************** +// +// SPI_setConfig +// +//***************************************************************************** +void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth) +{ + uint16_t regValue; + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + ASSERT((dataWidth >= 1U) && (dataWidth <= 16U)); + ASSERT((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPISWRESET) == 0U); + + // + // Set polarity and data width. + // + regValue = (((uint16_t)protocol << 6U) & SPI_CCR_CLKPOLARITY) | + (dataWidth - 1U); + + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & + ~(SPI_CCR_CLKPOLARITY | SPI_CCR_SPICHAR_M)) | + regValue; + + // + // Set the mode and phase. + // + regValue = (uint16_t)mode | (((uint16_t)protocol << 2U) & + SPI_CTL_CLK_PHASE); + + HWREGH(base + SPI_O_CTL) = (HWREGH(base + SPI_O_CTL) & + ~(SPI_CTL_TALK | SPI_CTL_CONTROLLER_PERIPHERAL | + SPI_CTL_CLK_PHASE)) | regValue; + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_setBaudRate +// +//***************************************************************************** +void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate) +{ + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_enableInterrupt +// +//***************************************************************************** +void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_SPIINTENA; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_OVERRUNINTENA; + } + + // + // Enable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFIENA; + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SPI_disableInterrupt +// +//***************************************************************************** +void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_SPIINTENA); + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_OVERRUNINTENA); + } + + // + // Disable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_TXFFIENA); + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) &= ~(SPI_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// SPI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SPI_getInterruptStatus(uint32_t base) +{ + uint32_t temp = 0; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + if((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) != 0U) + { + temp |= SPI_INT_RX_DATA_TX_EMPTY; + } + + if((HWREGH(base + SPI_O_STS) & SPI_STS_OVERRUN_FLAG) != 0U) + { + temp |= SPI_INT_RX_OVERRUN; + } + + if((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFINT) != 0U) + { + temp |= SPI_INT_TXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFINT) != 0U) + { + temp |= SPI_INT_RXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFOVF) != 0U) + { + temp |= SPI_INT_RXFF_OVERFLOW; + } + + return(temp); +} + +//***************************************************************************** +// +// SPI_clearInterruptStatus +// +//***************************************************************************** +void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the specified non-FIFO interrupt sources. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_STS) |= SPI_STS_OVERRUN_FLAG; + } + + // + // Clear the specified FIFO-mode interrupt sources. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF_OVERFLOW) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFOVFCLR; + } +} +//***************************************************************************** +// +// SPI_pollingNonFIFOTransaction +// +//***************************************************************************** +uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, uint16_t data) +{ + uint16_t rxData; + + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + ASSERT(data < ((uint32_t)1U << charLength)); + + // + // Write to SPI Transmit buffer + // + SPI_writeDataBlockingNonFIFO(base, data << (16U - charLength)); + + // + // Read SPI Receive buffer + // + rxData = SPI_readDataBlockingNonFIFO(base); + + return(rxData); +} +//***************************************************************************** +// +// SPI_pollingFIFOTransaction +// +//***************************************************************************** + +void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay) +{ + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + + // + // Reset the TX / RX FIFO buffers to default state + // + SPI_disableFIFO(base); // Disable FIFO register + SPI_enableFIFO(base); // Enable FIFO register + + // + // Configure the FIFO Transmit Delay + // + SPI_setTxFifoTransmitDelay(base, txDelay); + + // + // Determine the number of 16-level words from number of words to be + // transmitted / received + // + uint16_t numOfSixteenWords = numOfWords / (uint16_t)SPI_FIFO_TXFULL; + + // + // Determine the number of remaining words from number of words to be + // transmitted / received + // + uint16_t remainingWords = numOfWords % (uint16_t)SPI_FIFO_TXFULL; + + uint16_t count = 0; + uint16_t i = 0; + uint16_t txBuffer_pos = 0; + uint16_t rxBuffer_pos = 0; + + // + // Number of transactions is based on numOfSixteenWords + // Each transaction will transmit and receive 16 words. + // + while(count < numOfSixteenWords) + { + // + // Fill-up the SPI Transmit FIFO buffers + // + for(i = 1; i <= (uint16_t)SPI_FIFO_TXFULL; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer is full + // + while(SPI_getRxFIFOStatus(base) < SPI_FIFO_RXFULL) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 1U; i <= (uint16_t)SPI_FIFO_RXFULL; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + count++; + } + + // + // Number of transactions is based on remainingWords + // + for(i = 0U; i < remainingWords; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer remaining words + // + while((uint16_t)SPI_getRxFIFOStatus(base) < remainingWords) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 0; i < remainingWords; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + // + // Disable SPI FIFO + // + SPI_disableFIFO(base); +} + +//***************************************************************************** +// +// SPI_transmit24Bits +// +//***************************************************************************** +void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t rxBuffer[3]; + uint16_t txBuffer[3]; + + ASSERT(data < ((uint32_t)1U << 24U)); + + // + // Empty Receive buffer + // + for(i = 0U; i < 3U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[23:16] + txBuffer[1] = (uint16_t)(data) >> 8U; // data[15:8] + txBuffer[2] = (uint16_t)(data) & 0x00FFU; // data[7:0] + + // + // Three 8-bits make a 24-bit + // Character length = 8 + // number of bytes = 3 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); +} +//***************************************************************************** +// +// SPI_receive16Bits +// +//***************************************************************************** + +uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + uint16_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 2U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 2U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = (rxBuffer[1] << 8) | rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = (rxBuffer[0] << 8) | rxBuffer[1]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_receive24Bits +// +//***************************************************************************** + +uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[3]; + uint16_t rxBuffer[3]; + uint32_t rxData = 0; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 3U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Two 8-bits make a 16-bit + // Character length = 8 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[2] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[2]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_transmit32Bits +// +//***************************************************************************** + +void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + + // + // Empty Receive buffer + // + for(i = 0U; i < 2U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[31:16] + txBuffer[1] = (uint16_t)(data); // data[15:0] + + // + // Two 16-bits make a 32-bit + // Character length = 16 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 16U, txBuffer, rxBuffer, 2U, txDelay); +} +//***************************************************************************** +// +// SPI_receive32Bits +// +//***************************************************************************** + +uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[4]; + uint16_t rxBuffer[4]; + uint32_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 4U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Four 8-bits make a 32-bit + // Character length = 8 + // number of bytes = 4 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 4U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[3] << 24U) | + ((uint32_t)rxBuffer[2] << 16U) | + ((uint32_t)rxBuffer[1] << 8U) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 24U) | + ((uint32_t)rxBuffer[1] << 16U) | + ((uint32_t)rxBuffer[2] << 8U) | + (uint32_t)rxBuffer[3]; + } + + return(rxData); +} diff --git a/gpio_driverlib_cpu2/device/driverlib/spi.h b/gpio_driverlib_cpu2/device/driverlib/spi.h new file mode 100644 index 0000000..b9e0d38 --- /dev/null +++ b/gpio_driverlib_cpu2/device/driverlib/spi.h @@ -0,0 +1,1743 @@ +//########################################################################### +// +// FILE: spi.h +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SPI_H +#define SPI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup spi_api SPI +//! \brief This module is used for SPI configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_spi.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(), +// and SPI_clearInterruptStatus() as the intFlags parameter, and returned by +// SPI_getInterruptStatus(). +// +//***************************************************************************** +#define SPI_INT_RX_OVERRUN 0x0001U //!< Receive overrun interrupt +#define SPI_INT_RX_DATA_TX_EMPTY 0x0002U //!< Data received, transmit empty +#define SPI_INT_RXFF 0x0004U //!< RX FIFO level interrupt +#define SPI_INT_TXFF 0x0008U //!< TX FIFO level interrupt +#define SPI_INT_RXFF_OVERFLOW 0x0010U //!< RX FIFO overflow +#endif + + +//***************************************************************************** +// +//! This macro definition is used to transmit a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitByte(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 8U, txData) + +//***************************************************************************** +// +//! This macro definition is used to transmit a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a 16-bit word of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmit16Bits(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 16U, txData) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of bytes to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' bytes of data. +//! This macro definition uses SPI_pollingFIFOTransaction function. +//! +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNBytes(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' 16-bit words of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit 'N' 16-bit words of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitN16BitWord(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' with previously +//! configured SPI character length +//! +//! \param base specifies the SPI module base address +//! \param charLength specifies the SPI character length +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' with configurable +//! SPI character length. +//! +//! This macro uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNWordsWithCharLength(base, charLength, txBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, txBuffer, NULL, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition is used to receive a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! +//! This macro definition is to receive a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received byte. +// +//***************************************************************************** +#define SPI_receiveByte(base, dummyData) \ + SPI_pollingNonFIFOTransaction(base, 8U, dummyData) + +//***************************************************************************** +// +//! This macro is used to receive 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of bytes to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' bytes of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNBytes(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' 16-bits words of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of 16-bit words to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' 16-bit words of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveN16BitWord(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' words with previously configured character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of words with specified character +//! length +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' words with specified character length +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNWordsWithcharLength(base, charLength, rxBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, NULL, rxBuffer, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e protocol parameter. +// +//***************************************************************************** +typedef enum +{ + //! Mode 0. Polarity 0, phase 0. Rising edge without delay. + SPI_PROT_POL0PHA0 = 0x0000U, + //! Mode 1. Polarity 0, phase 1. Rising edge with delay. + SPI_PROT_POL0PHA1 = 0x0002U, + //! Mode 2. Polarity 1, phase 0. Falling edge without delay. + SPI_PROT_POL1PHA0 = 0x0001U, + //! Mode 3. Polarity 1, phase 1. Falling edge with delay. + SPI_PROT_POL1PHA1 = 0x0003U +} SPI_TransferProtocol; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_MODE_PERIPHERAL = 0x0002U, //!< SPI peripheral + SPI_MODE_CONTROLLER = 0x0006U, //!< SPI controller + SPI_MODE_PERIPHERAL_OD = 0x0000U, //!< SPI peripheral w/ output disabled + SPI_MODE_CONTROLLER_OD = 0x0004U //!< SPI controller w/ output disabled +} SPI_Mode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by SPI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + SPI_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + SPI_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + SPI_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + SPI_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + SPI_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + SPI_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + SPI_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + SPI_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + SPI_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + SPI_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + SPI_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + SPI_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + SPI_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + SPI_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + SPI_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + SPI_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} SPI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by SPI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + SPI_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + SPI_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + SPI_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + SPI_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + SPI_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + SPI_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + SPI_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + SPI_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + SPI_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + SPI_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + SPI_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + SPI_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + SPI_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + SPI_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + SPI_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXFULL = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXDEFAULT = 0x001FU //!< To prevent interrupt at reset +} SPI_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after midway in the bit stream + SPI_EMULATION_STOP_MIDWAY = 0x0000U, + //! Continue SPI operation regardless + SPI_EMULATION_FREE_RUN = 0x0010U, + //! Transmission will stop after a started transmission completes + SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U +} SPI_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setPTESignalPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_PTE_ACTIVE_LOW = 0x0000U, //!< SPIPTE is active low (normal) + SPI_PTE_ACTIVE_HIGH = SPI_PRI_PTEINV //!< SPIPTE is active high (inverted) +} SPI_PTEPolarity; + +//***************************************************************************** +// +//! Values that can be passed to SPI_receive16Bits(), SPI_receive24Bits(), +//! SPI_receive32Bits() +// +//***************************************************************************** +typedef enum +{ + SPI_DATA_LITTLE_ENDIAN = 0U, //!< LITTLE ENDIAN + SPI_DATA_BIG_ENDIAN = 1U, //!< BIG ENDIAN +} SPI_endianess; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an SPI base address. +//! +//! \param base specifies the SPI module base address. +//! +//! This function determines if a SPI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SPI_isBaseValid(uint32_t base) +{ + return( + (base == SPIA_BASE) || + (base == SPIB_BASE) || + (base == SPIC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function enables operation of the serial peripheral interface. The +//! serial peripheral interface must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; +} + +//***************************************************************************** +// +//! Disables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function disables operation of the serial peripheral interface. Call +//! this function before doing any configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); +} + +//***************************************************************************** +// +//! Sets the character length of SPI transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the character length of SPI transaction +//! +//! This function configures the character length of SPI transaction. +//! SPI character length can be from anywhere between 1-bit word to 16 bit word +//! of character length +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setcharLength(uint32_t base, uint16_t charLength) +{ + // + // Check the arguments. + // + ASSERT((charLength >= 1U) && (charLength <= 16U)); + + bool originalStatus = ((HWREGH(base + SPI_O_CCR) & (SPI_CCR_SPISWRESET)) + == SPI_CCR_SPISWRESET ); + + SPI_disableModule(base); + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & ~SPI_CCR_SPICHAR_M) | + (charLength - 1U); + // + // Restore original status + // + if(originalStatus){ + SPI_enableModule(base); + } +} + + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions enables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions disables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO); + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the transmit FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFIFO; +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the receive FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the RX FIFO. + // + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or +//! \b SPI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or +//! \b SPI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel, + SPI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SPI_O_FFTX) = (HWREGH(base + SPI_O_FFTX) & + (~SPI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SPI_O_FFRX) = (HWREGH(base + SPI_O_FFRX) & + (~SPI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, +//! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, +//! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel, + SPI_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SPI_TxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFTX) & + SPI_FFTX_TXFFIL_M)); + *rxLevel = (SPI_RxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFRX) & + SPI_FFRX_RXFFIL_M)); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3, +//! ..., or \b SPI_FIFO_TX16 +// +//***************************************************************************** +static inline SPI_TxFIFOLevel +SPI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_TxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) >> + SPI_FFTX_TXFFST_S))); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3, +//! ..., or \b SPI_FIFO_RX16 +// +//***************************************************************************** +static inline SPI_RxFIFOLevel +SPI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_RxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFST_M) >> + SPI_FFRX_RXFFST_S))); +} + +//***************************************************************************** +// +//! Determines whether the SPI transmitter is busy or not. +//! +//! \param base is the base address of the SPI port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. This function is only valid when operating in +//! FIFO mode. +//! +//! \return Returns \b true if the SPI is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SPI_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Determine if the SPI is busy. + // + return((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) != 0U); +} + +//***************************************************************************** +// +//! Puts a data element into the SPI transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets a data element from the SPI receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function gets received data from the receive buffer of the specified +//! SPI module and returns it. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for space in the FIFO and then puts data into the transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once space is available in the transmit FIFO. This +//! function should only be used when the FIFO is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until space is available in the receive FIFO. + // + while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data in the FIFO and then reads it from the receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits until there is data in the receive FIFO and then reads +//! received data from the receive buffer. This function should only be used +//! when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data is available in the receive FIFO. + // + while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for the transmit buffer to empty and then writes data to it. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once it is empty. This function should not be used +//! when FIFO mode is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until the transmit buffer is not full. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_BUFFULL_FLAG) != 0U) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data to be received and then reads it from the buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits for data to be received and then reads it from the +//! receive buffer of the specified SPI module. This function should not be +//! used when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data has been received. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) == 0U) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Enables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables 3-wire mode. When in controller mode, this allows +//! SPIPICO to become SPICOCI and SPIPOCI to become free for non-SPI use. +//! When in peripheral mode, SPIPOCI because the SPIPIPO pin and SPIPICO is +//! free for non-SPI use. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the tri-wire bit to enable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) |= SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Disables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables 3-wire mode. SPI will operate in normal 4-wire mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the tri-wire bit to disable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) &= ~SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Enables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables loopback mode. This mode is only valid during +//! controller mode and is helpful during device testing as it internally +//! connects PICO and POCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Disables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Set the peripheral select (SPIPTE) signal polarity. +//! +//! \param base is the base address of the SPI port. +//! \param polarity is the SPIPTE signal polarity. +//! +//! This function sets the polarity of the peripheral select (SPIPTE) signal. +//! The two modes to choose from for the \e polarity parameter are +//! \b SPI_PTE_ACTIVE_LOW for active-low polarity (typical) and +//! \b SPI_PTE_ACTIVE_HIGH for active-high polarity (considered inverted). +//! +//! \note This has no effect on the PTE signal when in controller mode. It is +//! only applicable to peripheral mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setPTESignalPolarity(uint32_t base, SPI_PTEPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the polarity of the SPIPTE signal to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & ~SPI_PRI_PTEINV) | + (uint16_t)polarity; +} + +//***************************************************************************** +// +//! Enables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables high speed mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Disables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables high speed mode. High speed mode is disabled by +//! default after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Sets SPI emulation mode. +//! +//! \param base is the base address of the SPI port. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the SPI operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit +//! stream. The rest of the bits will be transmitting after the suspend is +//! deasserted. +//! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the +//! first SPICLK pulse, the transmission will not start. If it occurs later, +//! the transmission will be completed. +//! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & + ~(SPI_PRI_FREE | SPI_PRI_SOFT)) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Configures the FIFO Transmit Delay +//! +//! \param base is the base address of the SPI port. +//! \param delay Tx FIFO delay to be configured in cycles (0..0xFF) +//! +//! This function sets the delay between every transfer from FIFO +//! transmit buffer to transmit shift register. The delay is defined in +//! number SPI serial clock cycles. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_setTxFifoTransmitDelay(uint32_t base, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(delay <= 0xFFU); + + // + // Configure the FIFO Transmit Delay Bits + // + HWREGH(base + SPI_O_FFCT) = delay; +} + +//***************************************************************************** +// +//! Returns the Emulation Buffer Received Data +//! +//! \param base is the base address of the SPI port. +//! +//! This function returns the Emulation Buffer Received Data +//! +//! \return Rx emulation buffer data +// +//***************************************************************************** +static inline uint16_t +SPI_readRxEmulationBuffer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Return Emulation Buffer Received Data + // + return(HWREGH(base + SPI_O_RXEMU)); +} + +//***************************************************************************** +// +//! Enable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function sets the TALK bit enabling the data trasnmission. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_enableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) |= SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Disable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function clears the TALK bit disabling the data trasnmission. The +//! output pin will be put in high-impedance state. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_disableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) &= ~SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Reset SPI transmit and receive channels +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the SPI transmit and receive channels. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_reset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write to SPRST bit the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_SPIRST; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIRST; +} + +//***************************************************************************** +// +//! Configures the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param protocol specifies the data transfer protocol. +//! \param mode specifies the mode of operation. +//! \param bitRate specifies the clock rate in Hz. +//! \param dataWidth specifies number of bits transferred per frame. +//! +//! This function configures the serial peripheral interface. It sets the SPI +//! protocol, mode of operation, bit rate, and data width. +//! +//! The \e protocol parameter defines the data frame format. The \e protocol +//! parameter can be one of the following values: \b SPI_PROT_POL0PHA0, +//! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or +//! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity +//! and phase configurations: +//! +//!

    • h0IVYzESdR?7~ANT+Kr@Hk3c9 zII2|q5(OKu5!Q6LWbn$SmlZUe%t11i|8aRnL)f6$VFEXKxQWyAyQzlGw)Eu`mccS% zEp*;(kvjGI5)DUi5P=05g-vT-lX-`Nvk08=!Dp=XV3*Xb`F|6LXCWS!$;CItQK~Bz zSP-}*f=hV5yc$xZX_vW(LLvi+xW)DS8lE$u--f~-*dq*H%wn5a>wP)2s$wMYD>}0+&j~%RRT22t?VxS8f>+$)U#JSDhwgf6TsK7Jw$^eC> z{gszb64(M;gzcpDj}G%UykbWnl!Z`MsAKNmJMKu#y-T5nff{V=$5Krd$=}*3eB3M^jW((|wEfUZqT#);S9k+%s?2Qpchsh{B)k^Z3Ri!P4&9RY-jaqhImpDs z&wjscrlOAKIRd2|l;Rk@PV{}Vy5xjCfeHpHu%Uj3Bj#-Cp6Wor7>tE9uIb*sB}M<0 zBdvjfOicR|Qx}f$y3BCLa7E<`ez&Gso>DAQm@KqFgdFaLYzIkMun?!R5 zg(eP~a5p%5vnuvL>KJbV`(eK@t+^#N+3MblKwbMT%M_DtvLo7I$z3;YRqFyMhR(U|z6Tjmk@qDNk$S$Kytv1^cd*<=`zR%(nBA^@@=J9^nLb!7gDJpI(?NUw`!#4QqggFiK)(3qH$Fyc0pf z9wP9-ZRkzc&8!<84=E^tl5qX*$@-n`!*@iH@Cz1RU^Dd$zm=(UI8lh@AQqpeadWn4 zeGXU`O`wE@5efj^F_ z`KsgrZ|m_f1PXX4!1LTH1HZc&2l8VHRPj)SkfX55{LRYMHwmbLns6{otRJmhS8MhDs^(Qr5i;aIU*?4zWU{0|D99CYFuJ=bv9rv1_WTLcWjP$(!Uue$f3 zzXJ_lVBrFOT&e!2x!tY6}hgQI}}f#gohFw3cVs`>iRj$5(yOXP=pZOQr)3e{E&h> z3+|ZRb1FKMtM$hv5%|TzF9aV(z9%ANAen#x7zm$q&ktu(>0!GZ_YFit*oPtrKY2LyaL@WGjwn)y9nBD{&hU+|YO z;FS)(V~(_RKP2Hu1|qQr8>@n!&sOWD5lCbq5sy?O(rZ^}udz%g@QjCNI2@b4@7ghF z7*9bNl!Y%4$9FsoQ(W_ihBZM`SSSPk4HV5E{f377S?I^?KKe?&j{+K`^ z1BD3Z`$xa%`zG~-z&94YVXMwG8{`?Cd`jUZ121ulJ8f+h)Bfk|TmpV9_~DVKUU{8# zV2c%niz2v)I|rlC`G`>-o=3ok1s}ZQ{MHHc%)yDmT?X!A&&{g)wUl3dr4Y?PG&Z+l z^@H5Wi`G6PkikL*_MGz={?cCjF@;(dYOx;)Tgs)YCRS63<{%pLqhnNV*mm2)1q3$2 zMq!#%vz9M?t$MbQgg3)xAw099Mk{;1MG*-ffCEA{WyT(v-7v|Ph95ET2zzk5c&{yd zKUYj3m4{UPCi2t%yiLG)$r1u>9JJx2wtn5a*gbeUg&+=saKBu_I%qz5;Z9*WEEl%* z6Ya(yZrh~Oa4!eFSkQ?4FY^n^@0AirU?2h86xxul*<)~I275k@}3eo_0I`- ziog?R&TaSMhQH>{bH4y+LN>?d}QDwrdj_1y{SiD-Jswk0wutZZQRrcy2U}%Vp=y{VRrj8Ng9sdONVK;r$%WcatRdhk z0#}?rix!4*P%GQdJFJ@1hXHLku3F*RImZ^E$bqmcTyPC%n!qFMDy# zeBP)!5^m?99g}T}RR;trDN;z}AQ8Lw+T`h}rY}n=Jm%mrg4RBV-HIR0Dd>W(@Lj9@ zO~_=0|8CH54huQ>RrR>($tz3vSPCT^l;E>sg34ssE)KN;HZ`%y*VES#Ms_WwUW>SW_IO|LeRurCL`*jVqB;me0UaWaB+FP@jLNf!+m}dFox!R&cizWhY47lM*JhiU>+AQ_tW&-&P(@G$mfpEM-{q@S>Jz<^QgpL_T3UOmJ9 zt-$_Kwz;q?DS5YlMsDt-Mf2hl_U>Plkes$KXK6x~?3xwJmZd)uzAn?*?%KTLQnOGv z-0}UPH^eURb86ka$2W0+ z0e3H6y0?v;#m?^euXI!=4&V&r*fC(o%tOTgeB<4@%aRHaDmYNVnfw3E0|v}KvAaQ3 zG>*f98V}TX;vP|ca-l&@hY>Eq#X0}|{E?TZcIeN3h|TZ$@SZP*-a!i!?-nOCP{aMKSKB;6p!FMWpm!{PdNx340JFv|Ld_hqUx^IB@UN`Vt`^0LtxY= zt!ZcZ2n|AL5Qll|0wu74G>EShxyT#rr2a=}<^Wj5ap+ zaiNbMO-{bKM3DZ1xv{zev1E2~!)}`di!)+&JJyYw#)f zs;ttVf)LI?IL)YN%AU!sQbh<=JgA}^oO4%j-odX9!BPO00`Y#Ix;K2>qJ44$S1tNd}6D;=~Ap^p!Jl+ZqFx>NO@ z#vtg3K!?UyCOL0xhg>T{ArA^^x;qVnZ@rfoJeY-iF648?(@i&dHPIt-0)jq(KBZ1W zM|91>MZ<=$P|1NxD$C!)!bOz_-4F@^3aN+adY$jN_8~)A$QD61%}VC>!WEJI^AJ*m zkRlXstoH}k*V9}-Bjk%9pL(P{az6h3@_=D17z@CdqI)O4qO)h<0|X5LXb8lQ3bYvd zxzwN(;UD-%oC+6iJ)A$wZS-)q*;)kFl+H!z!i{4hcO(1-_)Dv}`}rS(Jt;~EWdbOp z5i+DcT}V~Gi=fJYDji_c1=*^Vy)g)JB8a0^v=}}+^DMChp&g)|&YjzDo+V`n%Md~U zLTGR~uXZm9PA7r|fCWKi*yG5eDdR@4pvMJ0Dgl|NTTZAx@jxixKmkV_5cB!xPM^3f z8p(o#5FF^-F_x&^-ekHCArByr#&~#BLfceI3!zm2t+euGMY6pK_Xdq(!G#Yld~xyw z{Eo5La2bv8je&2Jxr=6IY~>z~MW_d;r!hiG7Ojm;Y(#h~g159E5fTy$qb~hKNEJaU z1u=MjZOp3DX`@+aW}unISUle3;Lzwr2vz`AG{&^QQ5Mm9dl2Hd5XTjVB>YYO*~ZNK z2x<(d(GFgdO-=gc<%sYco{N_^)JUmuu|fhi|K`JQs=t#-X(v@LjUB^6HW#v~ns$V3 zC}~iiHoPD;=Rx2#s{Tf4TDZ zZT{{$1QP~KC<~1PN7i}GaGuOU1|Kr$PA)5%SZ0>*g0LD^i*xD&U$TAl;QdqBW=jA| z8hXc3gA-#iOb|+WP)fJJ4fSKvQM)Y>QW!}2pB>Lmo#Oq{386{=RaE-Et2e0$BRvt+ z0n};TU7K%b6n<8o%7PsS?C2`hoMHBezrqC}6d;slHR1Rwk2xm?PGg~f4+XTmxaV?< z>m_RtQ~^|JjDb6xZl7BsI~_p;sAepww+iHQn4W+QN*h;H#2 zKeXCC&3+;TF%U#2RkXya&(j-RoA6u%@gAgG5|6twl9JXyCkigIF|)& z9%xgKiPz@syZ3q$!WFn8F8yz}z9#^h$P7gvDKp4$wxzrOk+q6*&STJM2jLKLzX=A~ufV~S@ zXcj^<&Fb9Qr{Tw=ZXra9Ad>FBDtGO={7O@V5C%eMFHZSp#aK*CKqwSKA-y;atmmye zXe76Y1rH&3PzY_e4ZS+#stJNG7kp{uxgXBnclc?C(9MBvDw&8us{9h?7z8^W*ilYh z(5S!F=r?Hz3pD^Wv~tJsAC$`{&qUDSgATT&Sh}7&ShA@!>145lVPaLOE4?rk|-gZikQykV~_QJ!DxSyYd@C zga9JwLJ>Nxl2|4$vy25l2K*?x7vv;1joJGGp7e62L1uKUbS-s+W8*MaU392F*$~d(Eo#Hv5zpvnG!0Cu+gaif>Xg5|&4K#~>lZ4;~;6@d`*h%e3)If`sEL8KLns(!Kc>P0& zbwvmlK{%!KVYiH5ZkMYOyaeDy>(-SDeHW(EyNZQC0R$2(scGlDH($1zg@3-L($K0Pvvb-n%;MR_Q;A2qpj~G%M>ZjLLH1Jp^4o=u#eTI2q-( zWRn_#7YDp(<*S$W4%vG->0jW27nT1iqiOB$Hw>0!d-U+2hjvinkm8xlnUfG=co4%A zAFiI8zP$(^Ad6rs08@Gu(n+bclq=Im24AI?sBVs**5L_u%N-Muj?6}^9P{}|grRewegr=>vyEm}#jSJssff7=6 z_g~uHLhuoR4-KAgn3Ftlqa}hi7qsb!v2f+Oug{(>#lmj}e$yDSAs4+zy1hlX4%fxk zmi%OcDf`>^ZDgBYzzcDluKqJCtKq^MX|}mm0JT*5W8&2pY#P>skjsZ$%EH8}CGV2w zIc#RZkq3@+;!ZT#dZl^9sx2(Ii@=@Mz~5$`I`^*pRu+D7;TNqzSUGB^b&LW+vk00+ zlm7es5S?(m_2Ui$gr6MvN%wy7n^%=veFG8f_+Uo~J)(AQa#v>wLJb2o6pn@&uU`2T zY~99!4S)@$r-af26UobY2xP8MtdY-tr%!9SWdYU?3%^P!uH%vh<(!>3+x7YqIj_)~>HeDt2z{{mEf3z(eoMae6IGs=zMF-=0{BbI z^KP2#7TxeK6bqo3mUnrMQumxOCFK8S(8G}SX3s||zJ{zYhE zpoKPdo&7&%CmYmcSf~&}1+AgPCZPX>l^H_25ZdYOWt5wHv3FA%g0BF4>4_5Zws}Dju1MReq7Xu)0qh~%sKL`3Lbrv>WEnQvXzMlmh4(JdhRvDL_*G@rr1Mr5X zyU2I#jrlt+$g)r*gdz%wa_`TX_MNv8^Z@jzM@?hR{kZnW2sM1Dp$gB4cKsgm&J4jy z1Xgq{CMfr77OM?8z(OAf`e;_uBsTAy)N77#18#^@CwJaH$?X}z*qqCQTspRc8uuu1 z2E#!X$^pu0PA4BN%!-*AhmgUA3@U)RGllAPg-r;%VAs_D4vOP*-KIX|wPSOH2qI{z zPR5(FT-FK>vCzwdUK-l*Z*v#7V;w?15Aq3yO>bLNo4NzR7r>Y1bZ5PnvHr?y2#F#{ zr2Rg0rci45AsaasUh&`+J!;%y#q!@*2g|dN$Avsvh4!+s6>b0r1QQ{c&~+uP61dVgk$aeh4?Orl6+VB7?>(7X2B8z6lg5xbX}M-rVFH357yRfR z+h^phxFm^tgoRKMgwlRIHP)G+dOaQC9Ru(F=krGSiU%^Tx<^@X6@e>7w{iKkg9C4W zL`dO53PqP6u|j6S{v3qwLikRZUR5dz$(S(l7z;5B#88=S+xuB=y_PnD0~Z{qFpqq= za7XukAwm}ix@bS16omKuZmCAFX26=Jd+BxH>n@o`Cs;7zff3CrXy~Uo=Br#0EV*Dw zW8Cu%oH$JMqGlz=!9bA^3{GmqHSC_QmoYg((Q% z`S6`8wpjW3jUbn8r&w@gz>%i={JhtY0kaelF2N;nVb+aLa+GqBI?Xm)^TC?ZO+WI6 z>BaEP2wPx_xXk*V_k~~UJ&4V%0If7tL&=(5pZAYH!$KPu+Gy2xEzghoZZsF+w-A2Q zLHsNr?b0>rn+R20sG=U>d-iE7DXJqFiNJ_fT{d~pj!H#CgfCq9Ldmwcas2)H#UswL zpeF)7>fz+J*Fti@MTBG#BooNUF3dJce2kDOf=q%-#an!p-MtX3d06NvDU10Sg}hRp8t zUzWL5k%bBdDkva2c~)Qbb}A#}h#-ez`?2i4d}7tki!4L~L{k9_i+N~ne%%{EodI>q z+SXwvF1=g6|J#EH(XMwXiG?CQ6j2DF`#@6cl?@1P zB5#tazKtm4bUBXxgXm6|LpH`FrJcjv#rzz=#A zI?{aAZQ^2CgcL5M(3MiF7MAH|qKaU^2LqZ_o4nPZGvRIs={!iMlj_N-8|lZEZMw?B zUoQNmJnZ(iY0jOYjBp!ni?iy~&z?zl<&Cjf9^}Q%w|reCK89Oib16V6E$;K>wGvw1 zm#(o8&w+UQj&a$`#hZMO-a&XHgg3N%$JfaZHCp}_;U@z>DW_sv&L$uIy7@W_Rsyi1 zS4_*lOMJMS^brCW2%tFK`SMi9@K7j%2M;``kgu5DGKkg7LeS@cJ|*<%E9OcohgT!i zh@ggwYyk5nA++$Ig#wsaRV6p=)2b}w>f%lRb5-3Y1zP$lqC;%=Wd zOaY;W3pEt--eu+EqNNVpWWk>Y{*>uD8{^ss*IOf)3BinF6*1Ot_7;h$w^(T8K_kto zZ~Dotg^{|}xq35pMzYrvVAbRhf@qWnh(&pKB z*d9I{@S**X@^TxwXlf-wlnA2e72;#2AT8>#LLERImGPmQ+1H1*HI9G8 zg1rdrX|J=KL(UGEzZ}7a4>q(HWkJ^sQse$0lrT_2CxZNtc!Obwg~}|n2%&{y#ercB zbvg49lK7BBIqSUon3<%h20||fdTHgGvzuJ<4IB|FMNmmc#ZfbE{k}oI2peIeIMKke zLpoAR{xRG9N(8TH6{d4anx*;+5yJTpPD69ECY1R^6d@RL!I1WE<(A|VI+g>Tu#f_f zLOHwo{@%xj-`zp@D1whPM!k|->O+ndf+`18>1&MS=K-556>JgAIABK0TVofz_mr>> z;T;Fw5!}D2k#lbDil;0T@SuRsoMY?xxux$M5bU{NPtz?topv$6)DJ>&aVTE!Z(@y43Z|3T0bfF2#GEAIcZc0|EFgzr4~ zPIJ0?P_tOt!yUm%08W&J8QP&C<2P3!I5Xf(bE=aHe`+yQ@REfX4#ZHkzBvBKtJ_cl zp&Fo?(zE5}5xKUrwFvL{@Q$)jpkgh*a7!mb4i9o@R5gEOuzRbj!B50=zJZlp`< ziCqs7esJIi4Ss#hPPy-D4G4`4G*X%M%lwVZyt7S}g%W@gnw8a5JI}$7&mzPMAeL4> zqotuGYwC4`AU*_9x^4URz#?n0@D&TKTxg~Jb3MB3PV|dY2$CQv{!)IMLd}dT``=)5 zi2zDyHwGqM>FP+yL-@*ruT{3I8(y<-*`?V^Bh^@NhneT!htU|r<0G@t(j#yTZ;u74%iS#PuQw#t^W=o zmJ6}8yrSRZA1y5Xh!DVo018OM=y$g~X8%QKW1x+;HM`U&^=jN=Z5Dim;7cd8VrNZ& zsoENZQVx_-AurLmeWU5JGjR3tM5UxX8+bO|@KZAHn8w2FmH@ ztGzDkotKJ5(C33bC1-`iJdM8&Qo1Yz0t8Z|Zr+x8`EB}2Jr-0%phER}u4~e-U+13c zv+xSw6>XA%-4ows9O;vuy~S0_dbM29`1pr(|73$mBsLolakEebGv%cx;HFDb0L}vIV|DSGwYLD2U~e5S+V@st;ik(X)_BKZ(Wx!yC!RquKVW6pvR z14eW+&9RG693gXheIibr!46vFn*_0yG3Za%N(4yzN zww$^4TNaWSNTM-9s%wm+%|0SjbD)}v`P>M5?RiZCOBRedU`(+J^b9<#k=Bk7!h;Yx zKcyFQ3>9+v5Z1vu@vGLhap@m4e;u}Bo71_F{y(3O=W@p%6KNo1av_tTeL#=GiCKmS zD`18AK~{ICZyJ;H8k;}y;1hks8LT|=#JXB{1aBUA6F9fmPL1jdMTq1IBh1WoNXLzBZxB3r;7Nl| zlB!Tk&yPTeS=mPreyysTC zq0uYkXMSKol?$pgc(vkSzneD$5psl(LnYG}bwIICHw-}wK#TJHZt}1-8#XE0v9J?% zim$9ICO5}VS!ajMWqc^30P0PPSjg))w`aixz=a;9HCxHB?LZL11-KxNtnlyIH_sTJ z1KS)Xf-tJQ6JfK}ro{k)w+Or`KXz`~uGwFD(2<1*E=15NHFbZw#iQ&i2)kjoc&fsH zDKEFT+`#4>F62=14_46k{qe^V!B7B(^u>zt>bi(d!$yR!0AJ~J-s_omI-$B9!IS}0 z3b^Z$36c2|YCf{?9pF2yx_i&UtJyavIkDi*0e8xezadg}$7d}>FyVj+frM#Y-Qv-c zommKGAee5MBP9p-4V|zT!G{k%be`W_(0WuSLJc8;2N9G}TGQ9w$(W^y;3NVk3ZZ^$ zw6FYU7lZ(S09xRKIaUH?g=&O)0o2oN88g_-A;I3vg#}Lzc+zxR)&>0jHP{2;FCYF= z)=n4_JLl(iPlRwTgwr-Xn5p~hQfDhdHb6EFZjtc8BJkZG1Oo;PD7sggly_FmUgyff zJAil8W8>ERao&rh5MB%6H60b#oczx?m_0{m5I_U1<3eiw*=M6%5L6gYp)nLjPK!!> zU5^mOg(#XXe5flt9oFi`LMInGsg`0w3L|tvh3+iGG7w7#{mUSk-s+ia5!SRd1I<4V+|v;ZMPNw#SG8X`n>kd3(9VZ; z3i^VEpZ7iGH+ry;z=s4XO9@B)vWT`5o-BCr!Hbf|;uz;exuFI^8W+;2I(9Fx$Vjf< z>CJ)$4>aigC@stL*fmSeClSx!_Lgcy+vGxo8r5XRwzX2R>0f zt$U+A$#~BMgx@^)O$*fi@Zw&-^Lm7zT=+?YPp%kyCE}wKLLvi+G`RX{zbl(xkMw7u zi4RSbB_E3*FgtfTLJbFM=uPCSk;1e$vgZ(_L0bGeuqBHr4w?~-&7};K(vjr$uyyov z;0CZ@&IfZE;Z5b%=_ZX&5MB%5H65)}p4(s8{nHcSj{yDv`zS7$)AEik zKe@I_TJa0pBbx)+R2|d0UOqJ5bsM3U2elNb0?VY9d+VbRx_Hn8>%9R;rn#qZ7zNB|s$|FlNJs)vHd+MhN9XDD7YT;HX}YnB8AlxDWTmAGe=IE$x`- zvlp9B!)fs)_hLx-iU5TKY&PJ40qyq1>n$$T%~c5I0x+j=v~2Te>b^N7h=m-09GcMy zy|*=27s()$F;GT(F-2)nX3>I+2-*VBrX$aM{mn1u54=W*;X@3a3FTXV*5_6DAXETU z&=?o%b&vQA3`ST83rGL=3%9}%FO6(p#$t09AG&C_b8P4Kk8S1#vycXmMz`Oa+tQa5 zm0lp^av+!XPIt5YYv~)>2*n&IrVMod*3oz`ECaz1z>wx-Fz9rSwqrFyDg&vM<=V^k z*E-qm3t^#-19kMM=?;x?b2>T@w1uEeZ|EzMx6D@#Uhs{DI0oYAQN8nIA6&RNE|i64 z0W?zx%R>I_QXV`yjD?>9_(^d0%rc9%5=jIt2DIn^^ZR!5Z~gTn2u?h3qBG=XckQk5 zzfK_Bf?MJY+4Jzzi2Ka}*xbW~9!md~+iwr<>WV~o%fMS2;dP49F58{gB3ZC!z@Ff! z?)@_lDkBj-3*j?eio<5zEa5~eN3l@Bg9@sPvB}bhOXj~o&=GS;;`oMQiODX zblOSjZPbKHYvZ?{7MC z@!oQTLIw&cp$D!x9G|gP7omX*4HS~_dn!9GjQxmEC4?%PuHfpz0i6veVp&KMLK2N( z7CQFaQj2p4-vGW*R(V`)@0qz&5#bLP{?Hi1A_M;ZT<(PMO8~!U$8FQ!nKUSmk7L1B z0Jc=IzT5%F^<0-DlnbDodgOfVy4Ntk2EmF4R+I`~?>DYqGxIBgg#aw*QQXq8;j+6@ z5NZTaLys!%mhad5J|Uh3YYte`Ig)i$p;+G2CYZP2gs+Dr}tjH z_q}`PzmF1vHDyV;c}c+znG6IA9$3(H_wKh_@^MiQf(j2*D1A~>dYep!^&({PAd6s9 zpuMBbA-x0^!uSwI$uM!zYiakiCIoW^%qe%r`IK!q;iQttLL>u`RGKPgP0I#97bLOZ zF9d&@u5Cl^rK|~45Da->NP~CR&a7P;w+f+91cmfMz?)%sjyK8yA%g=MbSUjGuD@Kn z`&2Rup8-BotPYr)j9L5K2EkhZ-t@+k6RM!ylNp2X03L{Mfr##v3Vt#b*lZ^PI~w{_ zZcJjw(0+tfuu6Qt{x++vY>RlB!Zz12P)DmS{@qo!K2{Im3&0ne(a4{zMaCNjrLxcg z&_Vk>+q85R$^gn}R(XthcY*qHgpYjqNH3Xk^LmtLj@^XN$bm*Wqw8et z_Zl=@MDXN;C-qnpRUDOC0rQD$1Ypg&0+d~MRG%M?U#(kIVzar@KK%Wxf zSK=Vmnt&dJZUJ;tnRyKi&zS#nP6i8|Jm{nz55i7%8E&#b_$GpH^qw${v)^Eb-@l+K z1Wh`5gqzNeSA3U>JzfL6rjX1XKi5nB_^wPAthiuB2h83}pY)y%Rz~HB8{8wPBs{!W^8c@*cRBc$>nl`1yVB#=3fQipIHj*G7?3G+o+`u!ub*=7e3 zI8de^+U{R}(JB@pRS2n+htJ!>b$jk7A`}1=P^3P|1w1%{YC=$>*q*+aIX_|7 zE`&X>N8-P?k-;ewyH>v#oXa*Fh`@k`_C98iyJ4|3LK+{^XbmsMl-w?t^FXNMK^^UP zvX0V~$y`r_cRYAUN1m~x=OsbkFNA0jMAIfMU!!k%O8tBu3z~e;q>!Kdt!#Jg^}mqM zKtA1OefpY`O<6hEBbEcPbm~0N2&_*^szm5ypp%M!rG<^%IP>%QEQAAuQ>6OzIAOcI z!VzjkP)i?Nc3)FiF+MmCp+y8O^nV>V*{~37yUP)D7|@~p9=<)r;$Bw+LOcWUG`Q4B z=e<*8#}%+(Cj>i6ogaH|!@@UiH-1YH1KTKU7XgXSNv)<#GaLLz0=?qlu^G0GMQ z??mv9#`wo;L#Xm8l!^@BDQv(42) zsHSaN6H?rw7^jJlD}r1aLDux1<*QR|2vs7eqDZ}tD=M%G??BiDo5UmRtSesUJh~5? zfAQcKh2x>Wz-;+9g%TFb0L&<|t&2{1eJXH5*aq9g-_KR;kZV19Cl;Ig1kgw4bA5;O zk>$^am$G0X0t?#IdAtjTKlP_0L;yt42=c@2&6k>vD`PiKwdXxHoAJSn zsJLIR1JP74ii7ei)b-X}Z&DFUrV|i$ieZgBxAd4=(rD+hkNA=4b~hfOs)C65pV5Jk(g7C4=#skK2!7eYF1)1N|3i4jgi z>#+wPqUabNP&0Cj)2Y=6sXR!f*b3V}RWHpri4eqvAWDT(^Ud28uj?YzGEhso?v@%i z_wTGO1XC`U(#o?&tX=7}=xzfGVL}L_l@F7>oNaO-3?W?v=@j&T?#?@sFpt~FLaYd4 zsm5i>9DDYf-9|_SNTpa+`ud9nM-ezubbqZbFdNx#@|%TsLU>2}ktDbHjql-L1OosA zTDj!xA=ma^ncKvIt_XDLQ6WWU@tU)bB4}|zi=w;qbHGL zGYdLA(4mzp245MQqF08Hz<~rRw5ubV6?(s zKX1uq8-y?pgwdmZ9c`a{VM-Q4HXpL742mj(mcK13Y-Pbh2o@BQ2eOsQzN=ogv+#xs zZ)kzRD<&Er-{Op5#0Mh^d*>)ux9h)M5nKh}N_&1Wa?7Z!5u-X-NCHTr+-)rWEEFD_ zkI*E5Ci-A+yHe({q2?Wg6L3O&aqXISY-Q$xTx?DgKpKsZxM09Ewd0itAwmeDRb1Jq zWHwNAq?3g<0kqKwsj^PT170T}d}QDwh0tQ~IjN=lhjy{xDFRR0KON=o!?y5b5Q-Qm zqTSe7^C^AJg`wRn_=&)edh9>Yu|)OAbOZ%Z5U=9f_RJyq>*TQcivYgRD$2~(-J06! zhhQK81G@R;zbzDSWXAWf;Kl;y+eN>3>nhURKTW@R%Yp7AW+{c1551eTXP*BOaQ|^QCo&)cx{;UME=jd#H`iBJ< z23#nF)+>xX%nrUpu;+k1^*HEMP@H*K6QPt3rIdwgM<2XO>d;2eWI&T1^?R-1`GaP< z2wDQrqWv?s9w+%j!WY4p2fj4jwGJZ%W^ySAc^t^263Eor?=}0^f_@ev0U{|RgB<;j z#dXLd^z)&g68hE#*|VR591(Q6pi8lOzGn7=n#XPkiCjpe%ha%~V$O-hbN;f>BY+;- u!4(p%71Cja2<2QTr$^nrc;h^Ngu8e5!o5N4-&{`ccfL$$N$~Cg1O5-`eN5N@ literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_cmpss.h.1F121378400A79E1.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_cmpss.h.1F121378400A79E1.idx new file mode 100644 index 0000000000000000000000000000000000000000..e2b4a2062d50a773d074608145db58d3e772e76f GIT binary patch literal 2198 zcmYL~2T&AO7=ZUF2bNReWU zAjC4k2x#CG$V53Q0;0fxQKT8MVH6{p^510c?al1$%=f+f-(TMDdN|qJ=K;gmggFWM z2jfFz7=~GiS6sXxA^`8fcnK?cj@>;@O@qV3Nd{ZG#0Ojq#65TQA8Zp3x$fCvWYnJ| zS2&Sv*D!A%J})P?;#`f#NxxJ6CyUF^)r5zIL?G5z>MOlKkNTJ)>yt0@l66ZiMDjTS?8)J zb>X(ED4GZ~vGLnAzIt0xq`d}(FZj}YqTSZ!6)6--unpK~NW+ZsyVZ`Ija`R05fW*1 zzG3%hi=~kUVi$0sL3XNTr;eMM>meQ|Fi!NPVXR65H_2I5Z$n`L7OSNA{TW}`3;8A6 z5&MB3ZJB(GuF_KHlg5Z`!IpMDRwz>9G+i=5>d z+vL$Dy?TARnGPt95je&UU1fK&uXCh}GYTuPS}om}JEdbhY9eq!YzdYW-@9*hqN2Lh z74aZ}K{kF@Z{3K~c$O!MIs$cUqA%3TWo3$%aZs3pIXw+)8b1~I$1C_D-T^yko5Qr! zuTA9X`Xe?06S{47UbxecJFBxAdeOO-3hB>YC9uPWDv+;3yaYgt~ylmSR!1(l{Px#aM;oOM#pau zCqM$7*SqOTgXeAGk%;ZUj!w(o&X(k>;00hwd zO@bl@vah=(BAzBNP1Z{XFMjpf>;7a@5{iAWk7mT-B+AVF6_bpZ104Do-B&K=UT*&= z!93v6HrR%jKI4D-Aq#N_fe!XO3m)w%ZY^Gvh%N$MY$I%6V3@G5rvFS0eVn z9@+$t$-^cp71{%cYYEh{MO{~we{5b@HHg9={Aql~Zv6Io=QTr!t-+d3>RO=DXDJSX zQN&4*L`!TqXdo;9ch!>yB}t8#_A?en1U&N^E^0mwoH_)GKqMSz$E*m zbmsi{$CbRFXHldRNN3ZG)$vLfPk;XuMJ9nv_G~s<{d_=JucGI@uS3fdD^5-}KFK!v$myj&w MP78%#>qiXpA9u3t#{d8T literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_dac.h.8340D93FCBD6285D.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_dac.h.8340D93FCBD6285D.idx new file mode 100644 index 0000000000000000000000000000000000000000..5d8f16bfb80a7b17d936e461f5aa6acf6c056565 GIT binary patch literal 764 zcmWIYbaVT{#K7R3;#rZKT9U}Zz`!63#Kk2=nNdJG4u~t}Bzv4bdx;W<~}E7s}ZtKJ0W|`Oz)yBO9B*lKDYXBBw=7nLKmJ{IrzBoVbZi zDwAeTUo$^YZvLbhYo;G$V5m-)GcK;oO#&LuP?VZh90qj3I+?GG*Hr!qFmf^Ga^#AE zq(H#&TK~gZ)!Erz3Hrw3^0SYH^B*BGG-a2#SX1x-ius4S{+$BbT{;??D6>bI!2Xh3&&E9RhPNl&0T{loTlOq%E zovTZ_)DE1ro(B{*;V^+)8T!yzS}Eq}LZEOqM>gE-HyP~Rj-g(wfx^Zd#_*tWJvCeH zdzI&Ipl}pN6x_;d@%|y56@CYR!qFVjaABsq9W166suzI5UL0O4~d6@^1o#OF2sAV8UM~`sQ%{Y5@srb7%{|gu6ai&#bRM_Yf%T$>Avh z6K-jCTKGJ^`4Ldqfx`iA_NlYYr_|=I`~ws&;V6NdU6h)W2+~~S`vCCoy>IeR{$+%*lr7~~$fy{y6hah<7Ks+i*tLv?NK{%xXrZ*xzLON% z7nQVGT7*cMXbiGMY4E>y=JY)WboywCWbqb*1ADgqZYw2` zNQSXrr{5iSY+(Odv)=>Zo0nHr8)V&YYWid9l-rettEN^~*QqyZRMxMaHFL&{yMIWZ zeeSED^nU5K_tMhxu~8;L>(5yR1%}2(ZQEkId(&BW<$%!hsZnc`q5`bKQ_dGlBw-3l zS0zpd_t>%SC5~ISIr)#0NRlSsOjc@@NXTH4BtVidkt6>J$epfYGDndxI8Wd_QTZ<{ zk?7dW4LzUoFPszLoS@tf0j59a*Ih2-EvhI~Q4!AV8u!g#!CzodOQ9A)$=SQ=@bxe$ z1~C+3sF=g0IB-Y|spQ~I!JAI%&ylx8H?Y-o34Mf zm_r(YG=!ZUjunUe-f&m|3l#f1dg*l6ULm(`5DRxv=%QkVqS}rd*;2W(3|?5tNd9P` z%Al1(D}wGjKfk9=J{;!4+zI_-Qq_KEs%)Y?g@vyZxQ-bbeH#LYN{>=!uo_m6?SH-^ z<6uUnzsz(N4kr+fLyfLK8>pZbJA=U~0Z!pM-%gg6BRMiN8Qh_82bc3$W|M!N7tvzi zE`U3>P`+2ROl{daZ3d?WIE}FA*?arOsWWCX@TK63r|#)z$Hra8zj4TAZStGd>$=8#Gt6{jbyIZN+>o$NdY#$e3u z#{YhD^KPyyIw(J%g`L1jJnT!p9Ixn7*~Psp5_1ziTqVY#@CR~$DjR{dnJ$DbGADjr0o-%dryZcgRUPM{q( z<-P&?&nheKS;QcLKmtz9Vd<1(uJ7k9W?&BHWBRAI=F*47dPA(2uy7B79=xzRy`B$p z+BI6A1BD*?bAOBdg99A&sysM^5(vc%Qu@1{A`2cZWv~iXiPw*U%MhDJC(q?997G@p zpa0sRHgcodXaf!c1mW_`QR+@KTByn49D#G#BE-=2>1mrB4xSV|>G=LJd8=l2*0)5i zVsM4R6|C!DwPkM>d`{=kN1zWkeruq;+42!h9KtDtV~d`xYN6VCGgdPwrcjKFnjVuA zpi(uD!y^KZa8avdt@X*4ub^7R(Y4Z^lQXq&~H8 zJRB}SIM&tkYtVq*i9V(bA_zoa|1&jHch0CeY{oznG{yc+)K%_HUS7h(e^dAyUmT}b z$d5ba)@IHin?N>Jb+(GPj7&$o1%o64NtoeVbJgnL4SkjjDk)TARTbvyeD4f+wSmDg z0>_B>if!+H{;N~#v5gEmDRg4;K#5zDx?>QB8Ui)A4qX%SPrN&mWy>ImLJ}^idtl(k zK|L;Z4EzP~$AUC=s1L2|Dd%tmj)Y8Y1eUO2Fsg&z=jfEi?M_g~Ga=;lyHpbY12 zBgFTr4Y%6LAb>&u6_3|nUmT5h+VAF2L!k!eJ+<)U6HvUfjlnGnw-Az@^Oj~lUca5e zM%XyAe~0_UCTi5wsqSFm1OXE8CYWck+d4|P!{I1_qgcS<^|~bkueWn3B2a{bRZ9EY zZ`HQ(I~llvn>cF~A@F&+`Omvp*bofG^h4R_+pB+g*a9rX zaA#aY{rzUYJuI9^AraSLe$!xCDRaNQ46-O>AuRKq@YvU;oWm0ePw-VHIjuh+FYD1h z29GH`Mlh=j*)+?9Ixr|DP>K^*^v^>Mi)gD?tVn4@S^-LHm{J`NEAMBoOPdaqet zdbP9@gD3(~xL^GTziGE0qQl`9fm@j4z*NPT2^Z4$GdL^2S?p?hy=qx~%^qh4eH8le zzO?^1^=3(KDu+4(b-0^WM!zfeC|YoUK{kbK9Io(5uk@~5$Uz3nV3~M5%x(Ihx2YhX zhwZ^${IZ-oar-iFt7aD#P7xplcgFE?_dhL`YU7YbAr1T2m{l@;!elvD2EhUZ;~Z2! z8XVAc`;|k0009W2(hs@k-rCL~hCmF~$tz+>^pOv}91;?z#Q=svR;0$JAGsX4?iUE5X)y(RJJOpGR=)a zFNIz#_}VxBSi0_$_hjHf!GkLGpCMU8*9VL4DsjjXAPdJ79h#__dNG2-H44{o7N4p{ z&CzZ5JI>%Cg@?EYeWs}-ZEFqVkW3*NTXdh4sVK(zEPO?PEBHKh9;7QIjy%PnmOw3*JoDLW zpPuQ){tR*n0WG*W29wJ5thtSwHlnM0faahQB@+1{tA8vcO{ z*1#I^V?oD3H@j>5H6DIT;Vr&dR6Ng>S9z3h&<1U>uGaVKIy7u|1+lOn0Y4&s2^D6z zD#t&|;qZpS8|-L%Vn$@EO%I1^3e~uBiR0|24!k`fm_Z_eL_9~c7p4YGGx@>cD}}GP znbm3yZpmK@ImbX9)Q9$OW&H}(v3pJrJI})D0;J=dUlu8PNc5I-@DjiakFa0Z{Hys6 z+Mx_m1xUpfc2aw%tr=s-;Us~RM0|G*j<{$gCyWVWkRd<@w%BuSR$2TR*Kh{!3B1QY zm88w6wBKN<2nM>KD;99S;oG%FgEmL9@L39Hsd%FiyJ+8(;7d^q{v_}xe#I{G+&VCM z^Dh?}yr%FPD|^AELQnanCWl3^NPO*--LLumnwn`e3(tdjV&bl;-5E!EPV(?fm?>`j z0h)31iqrMuSvZeC9_~Gd(@~}C?jPWAlfX>`C5123Z1>JcU{FG#1Q+y!hT}xHg(@iw z0tp1-g4T_T%{LDz;E+xs9XI~t#vf)5r|xj@CE!cMVx$+l{V468lFs0~0OxV#f)+T` zysJ9K!BYTF1VQVR=|8sYbGpL9#RQ6R za_PHTe<^4-$Y794Ar*&u{qT}q-v&P8U;-xMK-F?Ab;CRV4c{ej7q17iwuKGF3kt5X z=PM{wV3kTv-W}4i;5mn<6rSSIwT!l@x^C~B$smV74vuL_tE54;#+yT!0AV=ifjT!| z6&8D6WAK&0S8TCLZqY-zNz<|zyddxb_fn3VQ1a0J8;5nUPMpO_hcRuTI+AP_{)@t2 zxWz2Y2Fgwh(%|3#4&rNe(t8c}ch2p?4YS3)XGz+sN=w^v zSojfzM>yxnC2=W_xB2HWs3%a5<+Gjf#aJ%EJ)eOA7>LJE*jG5;vhOwzhYApirD!3F zx9(5x;h+b4`1!AUM@i+oQ2`74Q1HPw(91%)!`iNiLozS1MIFu#mw80WM&M zvF+!Jw*DB-A(B8O?ru5DK84rWWgIS2xQJUOVB?1DukFiA7~CLm1D9uQM{3MNo4is6 z^I^U?*u@@R@$qN>4QCO^!sqL+KX~)xUE?kGd^Ck<%rGK2!J@^jxtu{0g(j?P_4;wA zZ7=FoGOz+G@lWXP;m1;~9uK&~!f_Phu%iuQHM%}t`o!U~0GIK4o4l>^V{GBZY6j0K zJjV>ty`9>@Nt$&G+6c7a78_&$v1(z_9D)f1W1U=k7rEM*KfB8ymO?BhHz?0-ESA_j zU=T?m65+#|Nwt533H1yP!6ETX2Yr@3c&NdchdT&#VCujut@I8H>jnn5Dcr_0*Qa%E z+c*K!BPCr440X$76q`OiG_ zB0vZ}f8*umHkH;S4r^hpcyw)+DcWiW?Rw0@?iAed18?9nx=G*pmnRHbD74_p9h}yp zbll9J!zBWjuo#3kLBN;;|g9n{Iok*I(e^Cx9R3=zWkUw_;jp2ZIv?PT-rjJ?C~=L%QrM z2FC?BjxCJWj(zbx+L*%$0Zt&84cAj%QQh6iz*_)sgwLneEhCFm|6<@FfCoZ`i@8y{ zxgm%3uwGn?;;t`ttsV_LoGd^xo{I0zxo27qYQ1K#9kz>a75AY-hgth{@o*!7M!Zzw zejGX)Z9VlZ15+>+*Dl-YBEd} z2GInfaV2EFk0ci1%^a4(QZd86343<64wn1O!e=O)q2fn^&p~Q?G_8okJp%V|sCuC{ zJ~e8*;Lt#z0U>7j&?|4VjlM8wBG7~o9b;7etXsZ^K_P)cytXuYYJEP*j^U6(AO#0& z>M(Qq3)2O?3?e8*;PmckC2B4SvHQy49ff!J9;!c@r~ZHHGJOnu1@Og{)6r?@k*nFv z!4+J^&)T2b@+Oyr&i{vnQz)chhPN4J=6~DNePi&9!ZR#+=O~4ih=oc&7+fH50SD{2 db+;}5(sXj%>?Fhfr6e!<)Wp#X<6IeS!NI=7VHFp2@_YxjL8JU#APF6X6|d2d)nlt$?t#rzxRCS-X=zg z#X=6lgi527`LdGCZ4ATM;-M%hem@PrC3q;pcu zCZbZa67G;p)I9x}<5oxq@pKogBEsAFf3I~L@SZ&3Dlc5Fg0BB_8Hfh4=^Z&Qd$%1b@7Pg z>9YppPza@4A`hRx*}Uf3jw}SB9lNZ~u9HvGe{$$VZXwWO8gbD>C*k_?nQjb%Ac!tX ztNqmGv^2dJIT(Uzd#K}J!jERQ=aFR~b7k9~$9~Tj*a?P^10aCjqQ|$E83&WhN02oH zG^QoFCyK%r8g_n#!C3-lO>b1n%*N2|mj;Z17kJUjK9RQU&>rge8d*y~OX!n!v;M)n z#D(__1~CvrACRe;wR=%!J!8mfP}7>!Bj1UxJmz0T7J-OzRe<7nva9O^auh_-l4B~4 zRrV{q8_0*@Fn!7@ZCY|XlpaQwfP`-MNq6rq?wi3n;b2YGag4BzsF#wE#sTn1(I4Y~98KVuX2 zRS%F;Acf0zOOLhn&XT}ikUhbZz8_iBB_AaX3>!HN!su`}R?ULr4(a|vE`S1hgZK}f ZmuYNN6lW`}@Y{??i&U5N&ehQj^B>~kV|D-l literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ecap.h.AA1FA7CD26AE7175.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_ecap.h.AA1FA7CD26AE7175.idx new file mode 100644 index 0000000000000000000000000000000000000000..1b9a09d8381a121e11abd8e576c2fe3d9ab2f812 GIT binary patch literal 1740 zcmYM#2~1OW7y$71HrIVsFtSc3$2u7(w=(1ghlWt79ECC&6a>m;Dijz+jsha192GJI z%H;(JQ;-R|DTs)Gpre_aj-f2uTmo_#f($o=WpnO(Tl#O4mzVs$f4=MelM4Af-Uy4L zJmdIT()e`oI*Ot=_{h@JB;oju!YAu=tj{<1_}9iJCNizfN7a4-*6Mrrtsd=Cj|&{_ zY;7N8vMMK)UhT`ggk=_MQ){D86;>-!RX4OYCd7%8A}c>Nt!k+IqA`fuc=B{;Q{50n zo&1*DO3AXNF_@l8i%*c5U=OcWt3){W)H*2wl?&&>GW?-eI|p>wB> z4RQoTysP2T@1BaDDQ`L=`+*-RDtHlTqmGfeAggFl(ImTN=BdX+zg}SihvBfkCJig< z4fa&mpgVFhBy%+!Apd%{uow0sOF%+S>kKt5xr7ul8~_32wCl*`-*umw`6Guy=zE$Z zmgOP6O`RY>b^r%5ka*)_Qug?K5VALTlg_;|>J?kqA|Y}q4W-)7Lxk;icfa)b2m>jQ zLW&yC$#2|lK6U_ENrRFmO=b<=T`Rp+8G?Z*h$7uwTsvhpUU5Q%EC2yXGo16;!!d4m z5^@a0kZydGY~IGca4B*L4JF!cM#prGOrBUKV?YEVlHJ-FQg0Hf>6}IdB?DLUb!Ihl0pH(+c^er=7PeZ-7$*UG~`T;G^6c`AE zKr)o{q4%WoF3)0Q7jPkIy0&$)hL6-Jk#ixJ6s=ue4eQq{E=SIR9P&9Xoj26^(O6x9 z>;z8a7VuXl_}!F6Epj$wlWWR-EA9Er_U?1YKHx*f-_+cHby_m?IdTvLkp@o$8*i*E zJ==y{M?;-VGu_0 z=lM$NcNq6FECnfrpTq36Z3i+_JKLeNfbod=L&AX*xF_kL(=2v*SLp zKlqcP@_F}?=cdgJyMY^-v*7(R_5=L9?~(byC#S8QkID90F8+dS1y*{R+(rXO8(I=p zpCH%JP@~y zCvc9;BWFOy7ERHVSr@U5Fn<9#5faH(fXMU!iVu?4JZh7~j@ uXwqbizi#WJ?U$H96%AF|MEGBkBxXjDrNzoN;QKZD?4bznR?%Q4Mg0qO{)boq literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_emif.h.7360F5A77CD3542C.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_emif.h.7360F5A77CD3542C.idx new file mode 100644 index 0000000000000000000000000000000000000000..73674250d4467f76f07edd40d0aa833ecbd09070 GIT binary patch literal 3224 zcmYM02{hH~7QoMzr=6El8lEOzN_9^+=Ms|fU70dP zw~KdqDGCGvHTneZ3fR1k{(I0T__()idxu^1joY__7S3;#IXEqpb#w`PbYwT34Rl4K z>p@D%596$g2CaPum6TLZ=dMh1JGwS4RdPDl*T-wyhUBO@DUytm+@EIU9?O!P$*30y zvc}9R5d?;8-$>yF0b<|4w|^H1zPRK*?~GR#fHK4Y#()+lxxd8V9}6n_)i|*UH%#uo%UBm_3^7MfC|q z9Bu_{Wnt8kA`RWcLPnEl25g3z@<7flS4Wq)r;Z^JfB|#m*x=^r#wdGhWx_*%Loi1! z2Au1gf1Bw&oF4=|4%i?-pfN%Nd8%_mU}Sk3Yo@!w^8#_5QV#7^AF z*GD?u_4XN!CmfCfjADUQbH+@tR&QHK;sxLf(3CIzuc{DL=S6G2C*h3FljJz!(~I^t z8`LAb1efspoo@ouwf2h*3G1RR*Tw()dz0Yv@yu_bMuZ~)BiXWF^K+&`Re)8j6gj<>w^Cfn%t_dzJzpVF>pn^9k~sNU0BzzF?AY1z16T3sA%Ii4M2H3`S5#+b`a#Zc1dCioI`qc|3`4 zfZteE`yW&p6vzw{NgMz?z;0ZbhNpf|)lyDGU<5x=TRf7?PWbQOa2;SBOZ1Lo*|)8I*A;>944fi zU74rGo;^z9DBw|+s_T*2t0z_F93znqn9hVzt*7q~rT)iBY{4!3IDZ>ETOv)^ouNVrPjJEnP56Nu_we3^ zE}3>AVNdkrPx-Eo=#s2kt%z_gU@q&sIzJ6@y8l#87^AU2T?JtYpoBfY$41(hqt#hS zq7<-{6(Vs;VR!Y~KRFQ#7|Y(65-!}*vT|At2}3mG_d5)euO_ynTqf*?etevup^eJPmFeQ8*bHy$H8U7YDqq zkthNzVxb!B(wBaF62}0K zv156=s#bkl@|8Xkp%}`KzxB;d1Lx-0JS6-M@EyBI{aTHB=GGG*lZXS1V^g9q+jWL{ z?(h>58Gsq=4Y9tu?hl6Fo{~5TbanWjl?cXH^<0@lsJS z^?pYp3owhFvi&3YB3qQjiF1JG*dB^Ks$WkYJNFL~Cjd{dJq-Q)`)GAD|IZ}CFpO_7 zWxZj5BdXsB9|t_nR`4`!9{coiL8J%*elz>M=KeXyv*+9&PbM>S=guS#yIMy}YtwW&xdl6Pjv4Pfyj>B{(W;L8o7NPjwQLZ;4n-$)@tgbZ=S z{}0Q_G55C%OY1Zl0v2G=?@xHvJoB~r5r#C}BtjGZe)G(6KJy~fSppY0xWEnh^NEbb zt|h%$OA5{`IJ5o#fVbM2+oR=UI0CIAwBn^keJ>nPcXW`9z%w46@qhjKL~_7f_uH}K zDEwmJ7c=+|94uRIJ%|mU5W_$WBQ-v9%&vI_)3Yg90a(GvKc5Kg7SNSR8N?H~FTj0a zz#nj1-SAOJ)26Th7AXA*D=)R!H{sejfrR5^5GRvp?@0RZM0M6;=Bvp z2z+MYGdt`LRLy%;-$U;bg&+ok@KQSFN*~@8U!f4eLIf+_ZtwC(>L22oC{zhhB}mhn zG4tKtWm8hS6G&ws6&wFIW%M3yeyckQR(asN*<&s}c%s47g!(-Wh7L zyJE~D1p?m%_%4k4Gayad`<*lBD4-A}LX|@3c5d`Q`5C^O6$v;3IAX7lS{_O=>{~?PB?m9@Qhp0`blkRX>_gxy z2VXfU)lRGQ;p4o1P?!(%rF$~4JER{g-(87>%Xuir46G|k^W0csOW~0Sk3=a6HffGI zzpp#rmq3XON^rRtUR|cS*;SvyR}sF7(xNvzlv$AdWgUgRuvbcg7QI47`)@NE4&Wew zljb4MKH=r&c%bdiiIYD8z9P z$4PU&b>q1$f5}@>cq@aqSct}k^j|Q@V$EL!+F5AFr0KQqpU&SIwbK!eDL0V7V*wsx)pS3wBjI&CP^b~12K&9Le4xpBMQaLrpeN1t z;t=(w>DzK>IGcfNM(W-_gL>X_+uLIhfeaaBU@z`3E-mE_8&bHzzzwV(%h%d3ySnw> zU;>v}xQyMqUUb+=rkFKf50^+%7^p_WJFp zmB*UxrVJ(UON3tt<9{eDtuoM}5X(X=E9J*RAI*_lGImn%;=l{HTcsg-S;3*_DMZL1 zLMCm7qaF9|T$uWd!W$9ZU>n=(tDk58(jP`(4$P5mR%^g1<6jR=Y1okgM@G8PLkpjj z`sQE?c`W3y(#USw9~IR2poT)K0I7nMvmSrPB^JJI7)~IbgLurSWzTa4hTb1Mf-Y3m7aNLW3H%n}H>Q7-Lf#-FZZ3ry8Pwo>?^e9sEo6WRg&Y~=APk+(>(s8v zq41i6*Er}mnTc|YnesRS`k*iE^`6JM=NO@&zw-M?nuTaqg8NQQt7j}up>UOhtGJBy=C$1N&f_N$sN$gt4_L-gIoDM> zGbogaP=?ERmH&YS!hmj*2^@u^(xBHWb(*P#AEjXr4m>!if}|Rx?-+Bxgn|JWNNe?} zU*WB%r#fiZhXWtHBL(GsrK`-`R0-q@kS|CVQjnjlz2;#og=ik4aV}O&YWiz(z#9tZ zIXI77Pw87&e`lY@zXTir9B{Ait$x~Y!1G%aG8o9f6OQZ0Q)^AnCsSzUpp}ybPi@B0R<|H!jbn@^HdUH3C;S zxPm>;YJRXVE#{><0c#PgMQIDQowxqGH#=rJffOE6u;*7}-X6BBRHKk4gEW~mx`lK0 z&)$3d1BG3%OA0TN3y5Q9HOwI4JRb6Jwo^8nE1&8=b|!%`9?E#BI;)P@rQhwC5rqN{ z3b1@l_Ly$>bwvt=?XX=+gCEE2w!Jx7N5ijqc#XIEeO+nq=&OpeXbS?A;R!gn(7NOL z)F~9Ez!a$(q&8Y0h)x7e-@Z)qEmRUwyv`&$e>9k zozq4i5o_WnE~fCFhxd3-`o~?fYO8Kih~yy>d%ZU7Q_ z;cEh16Qo0>nZku7F`U(00+|eC;!3qQ_EfNnKTp9?1V`*e*OR$Z`(GV4kHB34?qabE zyQ#X>bJ{8jZ49(wYOd}Yd7gRpRD-}X4xZsm5q74o@JBgUV`O&D>5QRtB;7Y{;l4_(Vh;qTtMcGb24jn0K{n z+*}q%p`3wo+{NbY9WY-dsgQyxm`Xz!bKBr|m|GW368_D@Z=8$vQE{D*d+AZw2HT`G zxI0kK@$*S<8qQ@Q7x%n&G1*xo?j40l5hC$0?Ot-^vBlO-3SkU{;mQAj=}f!+@~0OP zZ~}0`YTz?+#r0XL>RJQ}1t`Rd^T=O+=(%}D6yEUg25&Zc#`upFwD}bh(ZSs9oUA0tGj;g86|B38(|}T z-SXd0*PUEVU-$pQnH*%|Hj>lajg~XHxe6K-l0-76PYl3b#hZz9Rgcmi!>K*8oaO8`hhh3iicNtt0U@M&z(=^78597p@5a1 zB+uP(*>Sep6bdOaNWuDaMET9uUb9axA>b>3FE%~(`YM}n%K=LXtcA5w(?44_^%=O= zjD{09NWkRJdZF7eWvPi?2|4Oe8D%&_V6tl4(B19mkPYs zfyDQfeMc-O5XwU+Laf}roY|vRQ8)=FrQcUB9=J0y=@boL5#fp`?elsOw>r5-M+#XS zWZ?wG1ciE<-YTMSmxa4{o_)1LSK*Ooz)AuiWbgrxCF=t-ELxZRq!21VC{F3>BmU!~ z?jBf0zy`nuQ`snYpU;h@mK6Lr@WZ|3hWuF7Z|SF26EFiasTXe>Ztp#|!gLJ@Z-PzI zDxJA%SI_lRENM8Ng?M}t3D~4-EdR)lLb(9tSjF3NqH|`PzoJVZP=G)zjl11~j65$W ztR?VXg!fpTTGOhFuT-s}5W+wRuG1V|OsYF?MZtps4?NvOX3a@^H!g%i6bDh51pgNJ z*93E)DO8A1foGM=Mg4!>J?x-I+mJyBo=t1DqK|3%nds9`uuy@o@|LO{zvP~vaaNxlKKXJm{ZpV;rmK1&n@I#PRY0s!*vsvYR8wvai|4O%N(+2tLraqzJ zW)7OM$X$w04&d_YDbzAh%Saa*U>;Z|I5bmu$-qn8y9yLMl|2`(*+hYdmw4`w-@UAJ z$=!Mi)&SP{R6hcc>`V!ek1sICzCK zv3%hnXO)Gj6h8Ct85@80J2vp~gvAs*MexKWyt?9%xv}bQ3idqM;}H6{6n4%&ux2ZP z?=tv~M~tYy8H@YfJ1Nu)P>+Warf&OArHKC92!sg`hD*5fL0)sGst$#DFi)yay-bah zO>MnsxQc};eCMbl-n#fc?9_GwjRG`c3xh_ccA5tHQn2H|4o|-`D#sa=>y0!Z&>=zx zuDtxyU!Q*bIiErf3pqHpQ;ZYUFXj9G_X!3%aQ>!r@7AYr`AI|aiBCLy!pc8abF!YM z-nN|tia998C7BgoFy{MS>snUp%UO3caFA3+fkdNDfb>avv()R&{ zS`lio-~B7f&IFmgrf`vki#UJ&8g{qV>b|28AV2`_svg~i$$Be0_Yv@yfj{PL+Xw%N zZ6gQoC-6jsCwPjgv1pjx=&;L}Ks^ifIDZzebhb`3&Ua4zMvj z>Sjr|uM~=8P=q^WmQHMF)3rMX2*e2xhpz~(jajNSu&>@h0#Q6fVdi%8Rc^I+-%sHX z9Fhw0r<^Xl>62?T{8NOVxRu-sG<}lLtCfN;55739EA(Q=?#!RF^0#T0B=u*F2svnm{7WT}3bz+pHny-_>!cT%H9##$P-mVq@6U$J7g>#(rR z6rPIk6yM(;vdEj3I@*xJB@r%R4(=`8{BM9-dEZzW*%n7)%;ELTV*D_QN5ndl7a8HDL_!Y>ldCBYaJmy;v zaA&|B^P{bINk6&d{~(x!U|dVOj;5xnrLOc7MI01iog&{!9#e!y3YK6gjnw=V@i&C} zO_n6=Cx9QWB%cAc2lsp)cAP*S19@1b6o=%jReag)1cBc&_>JA0Z!%cE-dvG_od|X~ zgtns$*d3~#6e@YB#MCUY$RF>J7e>K}0Vm9lu8HTZHDl|e0@zEZ7>Kb+{5PvL<8 z4{*t}A3hP0tJME2ftfH36{kSUfeo!ifa{`?v1NWh8#E1aH- z^GduO-sDh-U?2kDOz>;E%vN1}!ihk=4C-;FhkYw_IkMmkh36tX#|OY0xfV%h)|69t z&%k?JsgbSv6Ib;3{NE>7c#bJB`CDZ5*Pvc5)xxVqyE7Mkpl}J`5*uA$6apCt#If3M9#mqQbeuw#2w6Dn1&=4@h#Ge& zv@+0&8TC-Okh$V;>tzCW1h|8z)E`Vz)RPCK#CBz-!*nU96yA6CKCar0hP@f^#tW(Y zhp(S+JlTW5Ssu<}@@#y&eXRV8E}jG;1c<;T-)0bY&7}Wv3hfNE{bUh2I+F7s4{x!J1BYU)do>NG5X(R;4#>2urL}HOCKQ?(XvQ`|bOTzl zXU_B{&?tjO%&K3*CN+MXZ9*YJgb19!)#_^dq!kPp36DX*Iy0l`;6g|G}(wpK- z!f70&;fgI8VzIFF;t>jgECk}NXH+~i<@U2aegv#}u*MdiCkQY4lSVw6+3gsGG#1kED~j4rekK>^%LNcH1VgE+ovJ_ z2fiIG3stlTA`r?#C@XzqUv3+6x&Eg!g;)V%@w}P1=ZglL8Bf850T-+~_T9fM3I6(> zLLCcrc%WW-G&{F=`n2l=4!{9v0Oyxg>re9eNW*6YID<>_>-mS%yBzL+gFqw$k$AIP z=WK3MYnx0VgoO}%bPQSWGksd2C52)c6ywf4{Iv3>uoaFJ*1=MR(QT91BXa%k8`1RuQF0@;^W%lf~k5X3_e-mIqwqch#RfP$3( zR+u;=2Y>N77(6hPK!^Y#2wDk6{;J026gmay#OE;Kil0ha_myE3Sm?xRaI?xJS+VjA zg^wJ3#A*=FZS68~$$)SIZUAohcBZGn<<0lxhfpvEV=2}8=WB*W*Ok%m4;lQx;h5-j z=178m!aV|BGVsF0DL&%2X=!K$g=8L*u^#xXKYcAryN1FHm?0%j)wW=$;}osY;TYB;FDZw+^HBNTeX={zCuS_ZFi zx4*Pj=KXZT5eg+dl;C$&7Ykaw-ah>&l0drv?f5`mYAx^Z-MoN8wG689Qcr75G;3zm zQ#c3*rI8A;-y7OD>QWR57qU=@SzfDh|DDM{Zi~;Ok%$dv8Ul$4r;Lv z7p*^7En0pejXH!Ki9N2KutyYh}_o#4V zAO&w3cw@>`7R-9_4I(Ib3gC%*s)~ZHUoX$DF9~GHAPbjQmq+efU&arjP{%+WBfT~g zcd0b{9@s+RBLg2X^+yaV+}-!Z<_rSa9Ask$_xI_DO#bTgaqo>jj$d7nQ!{Ho+<2d!-VjKw7?x9b^P}b$V@$S{564m5%O`I^!0koc6@P`g0l>q@i4ZyapV3& zIq4J{1ZcoNu8m)zF!1oPMQ;eSu+YLvN8>rax{qj+OQG;m1~2ih_5?1KW3HckOCX(x zbo|D{|9St_v%1cBN8ptRuP|>1?X~sudB2dt2G}5N&r^;SSNxj(_P^hk!7H4*@(Uw! zb&LDHC%=D@gNyh#@&!w3Odq@IQ1~i?ulR|DUasMuNfi{HFz^JAt=03qL!vV$$w z!&9tjs+WwGC-x7gU@w3@9^jUJd-(gx6pwrYr3{o}p4i67#v~ur40&Og`VFCWQ%Tax@feVFl5z27@ zH~H?^vg~*O1y=x9OwL<}-XEG_8BF1k0FQ8ef2!)=pt*m_2Le_yu);*RnXe@KefAKA z%M4t`%GvI)e{`ooJcUmze8T5Ed&iL8F^c&VVt9zbe*FBk=;4z&BZ>$#@zC^t65-{` zvX-K&6h1NV2@8GM_P#5u+!;WYQpG5eCEgZWV)z;Oz zjlxv{uHwsB?b3nCW-)I{X&W*Kz|&)4*HIZAmV3(xr1Fr81F|+vj3{^fx17Kg0j}U% zxQB|x+2`l$QdkHJrCyv$nRI>X^kf)O$Ohv-|-KUzi4&@RS{^HK|9v-)@SNH%%9w*a7%<+_*G}+12>(cF$+Hv z@DacV2c+Oe)o0g)#}poN@DQhIy?aQ@EG~hB4@C%pmnZkV&w>TwzCGb#yhqx$@ybB$a=Qp&5 zK(-9Bv3w~ky7#STlJYkK(F{c6bNy5}wrs(VG74K^t5jO#f4=fKuiin!)(lwV8_weJ zImYcP_&NepVX8D7BPS`1uz59rhC_G=!N0?=Ec0K#^SEt2fwKaf#R+=l4x6Vqrc!8O zpasi>LA+=1UcF)pA7$_n3(Jpny}~RzH-0A&&O$gY$!U{A?8ffs*+3vngfM(YN_;-j zPM!UiLMacWSeqA^PInt)m_Q+lfhZgft7Gp6Wmncx2p1t7FXa#tKR~f%!VdzAVX>4p zj}|J;jTw7`hU<8!!&Q;^V8h9}GXF*bULttmh4hXyT>?!XG!ckoArfC8wcdFh`^i(W znLvyHF_<6c7XR!%{ZT&(KRNh`4|FN1YX|mA%5EXx&wxK}Bo(QpLHdO&e-g0ez!r~j z^5(*PYR=t%#FbBc7T;!h5+_hn+A%$!Kvhl9WsxBKT|GYwB zJ*=0uTo13$D`d9MXt-2_QcVBY+2QwH(qwG}>Nu#wqei=ppK1?-0~8WPNW_s+c~R?Z zy~Xkufl2`?v9KIHcs4pF$CiQ{3vReBVydSr#^n`I$do}Qt|U)CxwwcyJK70cW8oUU zI@8u$TXSs42?|eHc#4aM@tZeFdoA2o2R#$JI;Ub|4PA807qQ-XRa6jtA2>- zAn-zj7ub*CW*2o5oflB3WT6rpAFdrHo>H=>;4Of+Af2|KCtMA1mJg>8Btj6DyZO^^ ztnxAG-AUj!2e)yW&Q|1oS$Ert!WAB_;4?$pw6}tI9hICTeQP$^Ac^4f^Z= literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_epwmxbar.h.1DB61B86D667E2D6.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_epwmxbar.h.1DB61B86D667E2D6.idx new file mode 100644 index 0000000000000000000000000000000000000000..dc7dd95f56229e800c556edddddb018ff2f5a444 GIT binary patch literal 20194 zcmYk@1yoj9_b_muyqmE_$Hq?Vz(B?B7#mv=yTMLEknR$tkq`kv5Gesc0SToW1f)Ae zkowMkzvZ+4vzBYtIzR3`XYaF5aL3uRW#h)&oqhVOQ{Hm-%9)#|gnjz-k!F8XZ>n54 z!Tx=k{ki+{^yY-bErF?7S$AelkBi^Fb5?xfH`&a&@#(wd7R;OX{f^kQSa*YG)5fz+ zV(}nXhdmaDtPWe4KX-LFt9)gea32yztKna z-W4U*MIV(jXI16cIHU_k4V9WTun+GaUa|<1Mbi-RpV>=~IT$9cL5LPWv|#f8Z)PLB zb2#ez%fkps0!Sk0elz0Igm62AgK$vt^V64Qt<$pg!sbXZM2aOnTwdwtQ8ULE!I=-v z{3(BX;H<|LpWai35X*;H{?xy4#`oKVWAafv25))rmM7_>uGDgoT5UCgKM(u~7JR?9 zKS*XApMgCe?D>)>w$v^w>Al{8P$_~+ihFd&^}wdPg9Qw_1kfdrbZ&34ICEbAAqeSW zNT)bXbZw3c9XJ=^G@O?7FeLAkPD|YpY|a!wCgtf?f&SLfwVDXsBIp)L;=Xxf&bmg` zV1)Z{U(&Iqeaq%qmU2SYY{LT^o&=OPSWJx?bp~N6EFJeZOB3A#(^WJRu{lWyNkYlb z>zYKE_Fp+i#6U{`S^`PO2UpqFs)Wo#umP}v34dSZ(SADPeS$7RmKd@q<^>0oj_4_t zAn0?T&yD~4M8cg2<4H9NVg~5|=`isxG_H-b+*rIHp;iR7l<<%X&7x(dt_Yt*@QL7Y z(X}0e;#D~Y0b&TC&cC~L!tLlLgs%W!X}Bg;o`Lqu1^|Ny4k9>79AC^W4`r)tL9pb3 zC8h9e;0F6r|5FHO;jCote9IE5H{I>T=AQsRDT?Y}C$#Tq>q#*%;=qXF?mckf)_)nM z2xdGmqaGF;>js6E2P5PQAzvsd|Iy(}a@j^Q|1i+zfi^vn{&uR?b%QMk`aIAlc(fdT@)4}~U`5be z^yf@Ji#~m^2LS|7@h>&mx4KeU3!#G#9rQ$B|DJQ_2ZtcM7Qt(gq}b+!_U~0W7K>0K zgc6F|z*HE1A+iAB9S83yg*N|iH#JvB^BJ<#1p(RoumLO377DTVv$4MLKgWCt*a=RrJA z^29%lFE;Xrm?5l!Rgya2Yw=a~!{K!US#uW;x@eNdDfFM!6K#axApj4GV&IgDzHVpj z5Wb4wE7iG-jnez%+Sdrrgz${k>)x`OpC@O2L&z0CF0I!S-O{FUn@SKG#Lys?)cK_K z%fLp>d=LXaKKN01+vi+yicDNJm_f1_l4&h%@O2J8{%jpWC?7)U2_31p@{7SI5v=)O zO*8Ji$44)E*7U7Ef?QJTRA4n9y-omv}n zykedm!e;?|rW%>5z3{`Tta5~R0Pm>t`B!2BG{P$p$~h>fUF5M{)*1`06``6B)fC{# z2&uUhcWs6;SOQBVHFCn;ND#Op0-J+)5Jabvw;d2ZNq{ntgH@gHnJ}8tmsCcN){LTtxUOhM!_d=dDvW&+mJy0pXhfzERv|S+3Fr zF2a8qWQrh@I@eBLxXdblJVK=yD(O|0ZQ9DuRF5Du@t}!jqu-IzS>aIum~1OE*)jVhZT5U&&B38fHpdlH`G?u9vWMUP$+;xD(MXsmrf^F zh{iB*5`hz4gJg4mjoZ9R9zjnCdNf#2{J9?Xo7BWw_jipU)6_0D34(dxnI0=`4Sa5G{si+HZf0_T8zxn}G054BrSu2A1#I z-lZU<@*$PVz~Z)>yT+j$ghoCzQmKtv9$KO`qY9xz3>|a|*bRDNwSUBj2@EQEP)Y0c zK!E3AwO8X1-t*u+)wzGy4Gp{h_9OTU!Cxpj{XWYZox1O+gy6;lH+t3i33E<_WIaIe z6M`Q-5wQD|#+VV-2<`yxR0vBKe=n+E5Q~s5fOOiBo_F+zL%lGOL9hsd=?bATCdFu> z?l6Qp9@J6iCq(vR_8z&4&?|smnh)92$1Sh4-a-fvLI8~_Wm!&m-L7baNIpbTcGrfk ztcX0^fnX~DTYA;Y{o4G}doq(4IP$@fitS*n#S9lmS%h#ggwqU8O=;BJa?BB-LkJyI zKDw^D&jz)(BSZ@!nhN^UqZ@0gd@fFA5WqnI9a?co9nS~$YeMK0KqrkVyL#`qBaXwT zFmU376OHO_=)KYzYNHTBc@Rod8!Yt7%m1o?;3fn&O35u%oA1KbScLVke(c|Sy5~;E zOI4=2Q(1Ga2y$s#&Gi|v@`#<)x{&*xVaIT?*8tB)1JwJzMAtZ2+Kyf^K5D@9x)u&?|&qg5?*Es@I-#mt~L(kV|oh+=o~E*DXDZfrS)UNJ(mB z$*0v1+iXT4=!rp(uGb?{Rv9KJh9MY>!I&WUP))UTVl{%H5DaMv+Lp?cT@4{S!HZio(t0L+xB2LUJMzG+41-x&LD$hWCJ06XFruYg5wxy4W_m9|D-T-fiFbk1cbh8@T*Tlbz(*<`{g9@? zRkvgix;f~k$aQ|cyDxuoCW5sPtZ6=$jq6FdQ=+(-L8t&isq@<^Ma$0?JVJ;OK@8<; zRm+>r5iWKJ?i{$&vdPoyl(nr2L)Z&@CB>6jpd94)v5y>UUJQ#RS7oj8fhR3CC}ZlwxlEazaE6Guyy3$9mH#hsm`YZqn5DdC?P~qVEW!& zmr8CaBZP4fM#Efq|MQp5yXpu%V(6g?yyASqP-tL+P%4H}x{5D5s^nm^I|AVt9Fqh# z_*dhr#a-FhT+cy0^-%OwdDyfM#Ry#hT{J!OG++0qw9j42z*-8dX>Dr`8jd_~|($8=}okG{zd$`JfG@S~YNy|Z%Hv9;w09RMBls*rhhuTOj) zzKnqb2M#n`JI&X@8`Jk9SP8(2N?^05j-Pz4Cc*~TAlZnt`pUd~(jJP|6yP^++3`^0N`297*%q*ryF_+FD#(QgHV z3=T3Vym!Yg#GNQ@L}=$jJFV1BqfTuY`0CI~1~=e_q@KPT^?gnGyyabls~%Pkl+}GP|t&U3eW0`u}=5b9|%c2NTQE77u+9~ReLX3%ixU=-q6;l z|HxwShCO=_UUKk~;&>TlpJJAC7hw&ok<7)!G2J7^|M0-(Zh&qo<-oHccV@qzy^cY) z7_#X$7&4)EP~+~W2)~8!n>JsAErxga=iL!HIq0N%TJ>&OTawqF^$bcxP(s_>ftAl> zjYeuA)bgR0a;q?ZYLj93<_!!&co0HILiLjFl6U8KBk1rzhccy|e{5T7pv5UbM9(TW44X@DqsfW!)LMWojbvYsv@>L-oAzuLbR6Mm8r_Nn> zW!7#6&pCKbU4PjU(56@a&t3-aMDUJkUH#^ghuZan5ZpL$qbFXrratSam)^&~P5^dP zJf1Mly?fy>1brdsQ}GnUxqeAmI~t)FpqQ4;zUmU^x4YyK{_x-r#r>b@u2og?`Uv$x zsHXt+E)9`?Xw~+=Cxq~aASc*p)zi^a_OmCHKuMCRy0!KLs)ruI<{S=kXoKM!X6U7z zzlPw?2Y;Hqq%*@})$ar$IC0=aarZY`_j+Ez_yY_og-}UdZ=15nPGN%vf|n4yXl>jT z7spJ9P&&xq7axAn`a3r-GUDH9@dyS022|)vFMC1kgjdJ<_5)Q?|Sb;Uynl z(yK;a(q7xIWvC*80AA7);~&;dYCa`{kRXBtTA0euwIVMqUW)LI58o*Ah+EGRP90Z4 zP!oU}70*p66|W7io*?9LkVi?BvvA#N&UqpH5yKz4vxRTJ+BW@W9)gV&*htCzy%$b# z*f~B(YQP}|ABFIdYQ%K&fh4N~NeBsINT9Q$$uCX8AiNvFfDZ-~d96eDhUEi?9cJ)C z1TSbGi5oqj$vfaALOeh`Wp|QhYSSQtdkC&PaHVq7lUm+R6g6i z)q~%h2|?)OLnnR4cQ_2<$aeuvT)z-D#cfZM$jxDb`%Xha#$6#cQMfbx_%c@RbK&X^%dyI;Y&v>6zC15pV#*O|@V-RA65KDFYqcF{C z>dFL!S7LZY=f=$$tTkI>lZX4eCFUYWmYFHbFO8}veOI}zyitF zWW5cw*(-;HVzVEBA63+~<7@67%NTox!Ami`q^?c3{z|ydJC2~s16`VJwd;wu@@9QT zu#^Hz`bB4`d*{UDgCz(rICw#0D%??+P`QwQmO;D_;wkQNKIdnigQW=S9H`S1`;&@@XAoM2&`N91`N<-u#rG60 zFbD$(qukE9cY5OFM+Xo-@ZkfMT9v)JuKby!2z3IeqXi@0V-Xb4b{;`P3N)ygwS9wZ zZ#2gtlmV1cAIlDW_~oGg<01n$05@7N_4nE*%BYXO#K0QBnjl|(u4$=R4MHA39=&S1 zlGcdSoxc$_!bZu0X}#(3_}ssDF0I$PV)H)OCyAhT$L_&T8qBcSk^@UhMULE=k5{ET5t0CsXdc?S2X*u+&q?9=nW2jiTtwhPbDiM4>0x%wegtz4%;^bT^{nIj4O9^l z#gIr@diMv?P_AdYtFpsX~YpLL`l9O#HxWPv*8GT!AZ+bU028T($G6 z_zr6}6N4Guoja2IwJ&VChqY&98*;icX_swX+Qqwg%m0V8?+S z#c*&`O16U6#(NA*#9%@_T)i50Eu{P%LIVd4^h6wAop*5K%KHp@_|QX(#r}QPE!&$4 z2wnp4qS_Frq%?P1?m}?kg9|+|vpDb;W6diisIQix669hsyNK zObaM#LU8ASJJnNyb4_wySQml@fCina+b??y<1CXNFtC*ZTe^GgZ!oV)y14rxgQo&` zO1r^>l5+(yn=T^60mM;Ftq(6&&iB(n&=i0sJyE8vej-~x5}^~Ilj3lVoEx9zpNHTq z1ZSF$=++{=m@AQw7-aAugW|a0)$2K-Sm7}P69Je|5|e{MKjw6fe8Qj|pq=_id2BlW zjNV0r-+cH@x13#%`AdV_gAwAz5KrYfX!*$-6LZ55+62%>eJop$T$efTBSHZO1+*1a zs7hB$6;&amiXoL=HPmk5f#8|d2pK}ipoz+F8{k?#SER-u6d;s_yD?j%_TIGJ2=4*j z6F5#krQq{;4}v;?I?dn+bLrdL*34IDP{~0hRbp!FR=u%O6;&uG8sIZ ztlNDd@Yit!Qw~gNK0fU)nJ{)m7J{xAbZOQ0T${LOVtF}283$$5`H60iKH1*iw6G5$ zn9$Bs?|E6hq@e?$h=U?}VrBO#IXMkSZ3fYNh^AaAUmcoM5VYtSgB(8O5M*^$Oe#54 zjF1SBNDIer_|w>}wxe_ybn~H`Hh?3t9DJ!>j*tzIO-X!ie=qRX?rR9aVhH}f1*ZV> z7hTe2peF@-bg#Ii_q;?_whiGrT$k*i)^AJnR^M5n$C~{F;77GSMW#N%DDSmC14}Vj z(sglh>4mVdpS~d!3!s=*xp1RhY0~-Q1`JvOS}D9Q!qm(S&aV-^^Wi%s;9He!E{+H$n{uH3V+|o(S13ea@Icn-JP)&DNjZGp%lEF@ipTJ_UGd zsNVDmlg5}ZsNkT2UR9-%yt-wsEJ6k!GAMG}lLOWdb=`+hFNS)$?%&&0AHHIh4MHRj zBIz3YT_gH;@@;if1`Yynpov=itwl!8bEP?h4BBy3kJym$rQKybo1f|3JM6#0L=tx zDyuRU9Xo*VUJUQ4JU?Gp?p8F+1z{bmliWO&Rw);5Q`~9EnmvW!N$0>ElhNJzyZ0j` z3L%jOJNKAJ*3D662#!KN*;V%!M(p3!WXuxXp-W7%~M!^ zvI}7|Y?gd`=yA|nyFh8QHEVt*hG$fqx)ZlF7|xYJ=oCRG<*6yMY|gzoa}n}IkWbf| z=gNg)X97JDG6ax8#W^`tYr}xfe{C3;0hmz&9lNx0m-oMkV9f(-+6(!k*)0&2s!{dG^*yx<~P;nC)zVm6M-5%arN%E zi;K40K(G*j1yxmbN$ZY3e%}ycco0KhE8JpgSH`-gA$SPEgO)%eEY1->pLU!NCujkEra!g`?z+5nTD;N+;8-V6z+2o8l1O zh~N$FI`<~m`26Rdf>6naN;<3~vZTkwSsry{;1A$Wo$syLY+ik>pA!RLA^1`pmG+%V z$3|>Is1QR1eKj+9p{|kj@HWB+A$*`GY?XzjmygYLW>CX}8mh#eVVY}0Yc3;L0a(#| z3`iIhmGa;!LJkjd=!vFh(fv>MeTtwd0!>O{v~SAUf^Gk~Ft`X8CEIG6{meI^*~-|Q zD~4REs?gw6L3nK!f*~IaDIw)=G+*gmkaJ}a0T4k6Nn2ZSZ$eQRg1Ho!(|4DHz3bMe zY)MCm=0P--!o1mDrvs<8AgBvLowmtlhoXkZ&6{5_(3JvRx(@iSuox z|5UT(BR;=Ccq)dcwC$ak@Vz4B7U#y`7r-w{;qmUu(X%JEA-Djz5a`YpF3r9x@6O;i z4}Mc_i_!*edolMhf+-J72?7IWrqygtM9||vk4DvRX8o0^-o*$#BIu#jadvHP^6agA z4+hyBWYZJj_Os?|nQcL66+q2&n+6^hChgt)F-YhrVX;kp~~? za92%epLpTPWQ5mzcumVJimAQW>@OxuN7>e$fohm{D493&E4n%`&t=3fKeFz^w84~;5r;ELQf`80%A0Iw*C zk(zO3=0`ISjQC(gouB_O!*`v03BqAGEcpat@!j#kzOTo;S#vBvEWPOH$~RM%?mLH& z&xd@9`|Dz-SJI$?PykRsDa@by&C9L11)-G>t<<&FW`*P^pL8Dv@qCD&Ae2%V zv1*g6R%AIsHV?9C(WvcQRjOtCzz;zP*;LRGbxGYbbzBj?2;d79&)$B+XUV8lBWMUg zgSHFXJC`2s@SEe$;42@#Qh;0TidPh6ZA9qeLl+h3!Tu|=6lD|<8UY$9?N+ajDPEJg zgpkQWCN0cUr@PI0t&b2~IdG)_Zw!49w0M#=f&(8Ms1FSThs>G{_6U|Du%yMWb1p3C z({?|E&tmvYd+xjCog0j$ixKQOu%|wze@>ZZG3NR^2Hya_(QtzU_c|H(GeEEwfi?9p zWc=on9-EE+2OL<_tIkU+-Jh)g6`_@bR)Pn!%?~<{9~!`*L;xl93sS*q`LXHiRwE?x zA(65h@Ta)4NO%z;mV;P&RsMs*XK4yv2rXi0p-n7dj^Pxq+Rq4Td{CoTIbAvic~2V= z!gvry1$U`2RrmewBgljN_`m7sav0~i zdDL5MHWz?7rQ^7dx6M_B|3MN5NmS>vN^6(O&1=9Xf;k8#Xdj}Qpr+S^kidfkD$Xl! zHmxXdVaF)@0xy6R8q=9ugPYrz{DY9oK`!k(!}sv-kDhTF!A}f+v{_6IStwg$bqygx z3=srBZ*C2*v@$}l5`qtCk`J3Luc+$Hwh0 za>HDr7`SlYLa!2*&-a5)DI6LrAC$yt7dQOy`0yJ+ zTMD%4wjO=C;_-j0N5(Vg6+h_=dGc6$up-v2S)b;1Uv&VVO>%KDhA%GvW z*_XG5YpJczLwE#_rvBX(EVah3-K7?gz?xUWO37ajJZU-bdVTgsY;NO08;$7d3b!ZE zu;WD_7-l9V$2wPx_R5g`yDkX|KQx?g%!`V0h308RSNA00JpkIIKm9IV**W#)k;R574BiOf4aM=TR&$Hf;5P^{e2Ae# z^hx)OH%n5Nr!qJRCnaU$rMNgjby^5E`*Yw=T_3qFN*}m!U>bu)Av98Wp}AShlm8q+ z&=7zI<@WLQ#?+6C(-Bs~YRQ=q{3dHd(X4|1y+{m=RA$PT`nziPmLfQcz>#J1yWPJL48>qb`{p=5-NpLK9$5^6gb+m6{Yh`sEIiZ05DYjlpggtP4_XjBybz&? z2SrqxJDh*_`TlNMHUn=Fc+=eN4{PioRzb-TPA3il7Y2l9czBr<&b)GAWNW*NCBpws_02GVA8uIe?HR zf;75}y69d@>05CZ!G#Ad)WcBerRQeW8X?$=!Jh7F71>(94jDTj1oI%64uy5o4PKm` zIX|DlF9H0b;@>}Kq?^+t9RyDRPs;55qjI^67cVYg5GRH>I(Xc3ezwlrBZsgM7D{S% z=F*Zr25aXQvSxc8*wbKF{m|EJ^IM8w!+{MQBB%QdRb7;F6(O7l;WSuP?&$b2Q}qx^ zIVhzk2BbL8by(|x@JtGx(Z-T7r?GkOvp|GE5d=~hJpYy$F~?q9#2`xqS(IDPD?7`~ z4sr+!5Mnrpq1mu~woOelSD}!^)_LFVz^ly5j}cr&;7XnE z?X}TYUG@{9ObBI^#I}s=HQSu6e=d644OG;rWB6& zJ}d2t`a*2WJn&2U>K11BkP zk{b2*qH(oqe#iX92N7yHsHG=FC)6%YIe861O$yX#Ev+#XD!!N#h2YKycdEjdw#w=D zyF;oN^zxvW=0ahzUeKW6UW6JE)KF&oxN9D$vD#V9;Hv<>Qic3;T7J>Hh-?INKA2Oc zs-i!b40vf!!{DhDJf%@>4qa?`F#iQY5+9Q2khXn(<ggB7g}JA++!#%PbJV_+--W18_9?XI>5 zS1v-R;zJe1G2q)0FQo&=5xxU_r}8}Wer2JPi2;Hp4>T!>;>q)l{wXO(&=-L|^>OFo z{TUM`$ka3N7K1k}{;rqHd{+o&Aoz0NOT}Y;Rx@#@zCJ=R4~nUe$1gN^);m8VSPQ_K z_9}a~FA8H9q#;D{A&Rp5rL*ekm}zp23|<4grZ}o1^`rPI76`FCh@}-fCu-f zF}Mf!rv9zNKXZ57KJ2>}oAsqYpC(r3pZ5iWmtRGA&%t|&B1e9~jDBy85TbYxMaM(K zFu!XvT>CdO_`-)TG}zVNZ#80lULt6VL7T2930nV+?WeP}g@GP`9z~JwQ1WKj+S3R@ z90XD4i}$o-T#dSn@LUR>(_aL#4;-)JxWgLZofzKHY@|EgZ{Jv7-^!o}poq4MN-66@ zgC|V>g&=|=S{-p4wkYtdrXsWppq*wz#bU5r%<_G04898CD;21?WAwDo$7~To079q_ z)wD5{*4dc|&Qjn^|2J~Q#K-?^b2#@K`w&Ar-6TIsJzV)|y+1;j7{Vxyu({vEdv&uA zbfiFsCTdcl+#=0}UkD#~@PXz-XYtI!fwKm-GsxpX9+g|+hBKFxswW}*5y2lS>5C(s z-Csw_BRm6mM)NUC<4K>#ryLRD1rSdgMqP{ed0*en9Skb?P(cfAQuM`1)AlPNd=bMJ ziX&2b+ueKTOb~p8;6v9^*+J7^$6mGk!@x!aHZ-aqr~fJZx4{v?9Kf7LHGX*1cSaQhAM<%^9ooYxhW`##}?R>%5<^jG9HvsIt-phyd82~1L3m>K2sq~ zp8f8;Sk(?8Q2>b)^+v_tUP&^t-3(j-Txmoen{N9Jzp@FTSO~>*kj~_9FIR0j-@~9t z07Z1KkJ1^sZHtpSLL&!_v>W;vo&0!35Qoq#hGwde!eddNiZ@gv6o{aJhC67)zqZGB z8TT^Kk^(KNkVV$oNzc?Q5ZXo1PMKXhQ#kVRv|xnKJorqTh02-Br*MZ*RXMHNm;Ia1 Q8*gz#X0xGAQJ+5l5A#|!Gynhq literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_eqep.h.4B417234E5F1F8A7.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_eqep.h.4B417234E5F1F8A7.idx new file mode 100644 index 0000000000000000000000000000000000000000..397c45d4706befbc1776ba93e3c27bc3a36f14dd GIT binary patch literal 2980 zcmYM03pADK8i4mVQ+h{cYNF7DGjlpKL+dd&q&bVt%xn{dH zgc71Dmnep55Xq&~CS;nL7M-+W7?sML_n)(T-(Krqd#&er|M&gA_j~_;Z+lB~^TL%p zo~f5*WRSPWV;PUflf^4s6z1oO-(TYuS?FoebKA21?$A(#hH6*0m5oOC?S6HMX7@eY zZCkXo1|p;~eo5U^F=H;Ak&;?nR%D;;oa2(6l~-0I^zsOF%ZS^UnJ2zjWT#x@lIv0| z{*lKk&{b~Wg+~PmFg-8KTNwUUn#a5Gvyv$I+2}GNO?<&uo>SbXqIXrnK_$cGhZItWi>Yf6M?utQOKDn-`xZy5pK;h3 zoE4XF(PHqoc}?xIh@&BzM%z0M?0;t?kwaWZppF$yI<~yhtYlsRMGAowLhpFuvqGSp zxLXm$5P=~=*S}~ubwcS^M`aY|U@o^**uyfiSY9SZ6>%|vVpc)tVC=v86c#q2*a}o1m(o=l_4dea_dr;&O$YmAw zW!fgbJM6X(MIV7amTH-?^aZzBLpu}>;6M}gOqU8gv>Q2`O(2^ka@%1fUZySPqev!@ z%$hye+aP$dsfrUuU_>XVu*Ya^lWp7q#M@yz#p4nG6y$H+Dea)&pFQUb5laY2*jODE zD{AOSggz)L2vo4L`gt~`*G^P$!W+D4{$RdbiFkb%hf4{RviM)#{9{2gUCSSZC0NpJ zRSPzE!F*CMVtvr3V{-YpTjxn(O$g$HaFAxds{D3g`D|t=;OD49w_TWi(9lMS}0jT*S8t z+-C77`eic>+}Cj;2!iO=DgqW}Jq!l&5g&tNba-3!QanR8yyCDYc+$~I(d+zJ$w|5Z zu^#AAY|&xzV(yzy3K3@#$YgEs)m|N8ohQ$U76L77HRG3LZY1a`aUup{=rEQ{Ci{k3 z_LL&-CD6;_b?vY*_$dCgb7!JKFy(7=SOz2pAh)+E%TFa=ZEM>VCnAasuT{Y;#XFw(d-+N6|!}iHV7t<|d_`{2x$QfCcU7BWnlOB{5fZUWsb&DXylX)AtM#R(HIp}&yh zjvqc9a(>u{_!fa%EZ)s2S<<35e+NY*MAB(f(U=oWq&>ci_zHn5EPldbRjAt$yCD?y z1nQY+`CF}Ear`bP&Jj4r#A#1nOzz-@2Pm!)xWn0u`WRwIaHJEI|7JLBBEI7x;v@n|>=!kuR_2t~p!*{f4+uP9@5Jza zt^Yc$)qH}&01Rk{oIjU8tZf|jE8-FYC2W~j&8!1dCfg=ZxPS}okc;!Qc4E8VB;o)F zpz9g5t%>+%)OZSUErD8=<}V-HCUuwJ;e?ogm_3mN86{_)CN@u_NFxp6&Wm96cvjYu!H)-K{!cDv+pQCo^U zdPu~!(Il7NS*vB`(H7CBT19QOD4Letw(NIi=lsu|Idf-zzwdni@BjTDC%{{wcsx!b zS-Rd^wRJ;GsIEjJnM_Y~OjP(9`VXN;btKHIsoA^gc4udtt<^7$zMt4OHs7@Auxo7h zcbso;|7+aX%tvV+rv?=p2gi;zC@u)d3Op2)buh2EVB`AGEy0RwB7{%k-n@?OWGTdP&rVjnQ(dp;RZUv*&`f9*l=94zswqyySl~<;{N?$kvP} z;fub~|Di;pzG5eFe{KB%;UvH$FcL&}>2A#`mGuM?b%1qXEr{uj!#{r6Z~P$%8Om6q zHmhq>y$&8WB%H%x4reOF+s7ELYZ^E$C9w%NSqL~}m3jO1dXpK1M*v4)h9Fk@{khr7 zcCHDDWw?yxw@=Cs&G})c8DTecGZCUw-dtEXaJ0jma0*}wOc%tR$j7Mz@h%o5RH!l* z@T}7A^1CCWvk7ZB)Nr!|5s|s$z_CX#heSGu>711yq<7DrpOVsPO=2@{X7#J?Kes%6 zXOPD~1O5!G(f3NmH@Nmz%qQ^@@FkcDiI&g%=jhf;gAOEI(RG@D>-KdTOM5IA5k3ic z63hkR-+M3U4}EKA5>Ei1h$D=NGYWrh3NjK4aUttazH3)c>P>4`!Zm<3V!SF?8d?>y z!i~fdT*C6lZVx;?A?lPT;SRtKun`76*=*J@@w2{VB#HowfX#Wswf+QegJr%X{L!Cn zm1CEaHAdR!{)9^aOT>89n5MI_>%0RJvw&y8Oo%_`JK-OXbgw3#H7Xc`%jyCB0SjqrS&&rVkSlhKUW<9R%GKnK=< zQhEQlYqIwJg!2LO#fD8$zB~WTU~v|SWWZ$cF6nvnjnN)%S2l@Ez)bNj-1l};vm$8T zArcjU6=Ev&C&@?NIqW@3A_PNN(|i;9Ex)j^Jw|vjE@mzMyU4@x{#984;XNGg;n;yQ zuIVASaCR`aO<6GWlxE54?`aOgY< z7j$7GOwKRStvDQUk+2p}3#^4@j&si_^<_0AA~BLRT(QzM=26ee2Eq$)!4#p;i*1Wn zc3l~2A}mKa+c1Ig!>_IztZOB#0n`8!iY+^~8N4XtMJ-^hII&n=W6$EMt8FA&0b7B6 z^>V#_k)^cP^5QDsRq>6CQ#)+^_C9GRq2^F6u61AO+>-T?E*&KD0Q1Bpgi@zp2Xit><8R0Zkw5UyRcAydN+x3z;bbnY5tMVGu-C&kQe|Q5LZIuG#LDWyW|fN z?&!{Tlh(^>qVvt=&j|aV54#v{yIi^Ap^p2La0_6I*uYnNBdQ$~?R_L306q}EX06Jy z-b%x^mn4b-i^Yn19cxtS`SBwpJkgWgF%z0~dhhw`y(Rn#@ReBTgW)`zV56C%Bo^T! fcE?0**b>U`ljx|hXnp$U;Qoka{k^U>M~UP=6+}VE literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_gpio.h.25BC6F0CEA046CD8.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_gpio.h.25BC6F0CEA046CD8.idx new file mode 100644 index 0000000000000000000000000000000000000000..c5ee698b6eac63a20e723e473359c6d23c4c5a72 GIT binary patch literal 80286 zcmYh^1yohr_Aqejz@+ogU^m!-o!EVCv9Sxgl}3<8q(P;T4(aX`m6DV$>6Y+2lW)8; z|8I;t-WdCL*I9e7m}{=Jx8B3Mwr~Hinv-Lz=B}r=FF(A%!@z}92mv-jn?TYwOTKYs~ZdUf*{VLgc-xicC$}T#va_Qp5g->{`YK_%>d$wQc;pG+c za6A0|li>yM2-M^Bngt zUwJT~#>p{jR#VXOBt8yK0nS)Ch?SE^#Q#<0{~Y?HD~GTRw#oeeiyR!Y4$e7jZ!jG% zw~9ln_>}*_&aD4Tc{eUV@MC}ihBjZFK+n7&8}hg9~*|7-)e+je(2?A zmsojUDNgmzCWLf8NatghP(K~_S%7OZ!drQGE3fpwI<)0)Up=ca3B%$rOm~(4+pK^g zejZEs%YeTO`=>r!G|W9P{{liDFXZvEf6D4hxjn!iKheQ_QtO5)fjfAV!J}_P(2DPG9mDAx{?aWZC_(Z_9k$;JFhBKP2IY zBpV)DCG=Rvh;g!@m;uEMx&J-jS=*)8ZaiO!U@8u#;_NzhaWHsfFK6AHSSf;)qT>JR5ImS1bw@-Gp;QV=={el?A8k!)`if91 z4Yktj+s$>2^*$^fkKif^uJjz$@i&&uf1HhwDhsJp`SOU*d$nR)5Za`mjq3P3i}$~{ zJN#TM=of;1A$Hfkm{;AZeq0j4MG9P`*f8;TUwOcMHG~Nvn4l8B3J@g0(-#a4qQlBIqM2SI}_TO><2uxUnAPz;T3|nB6usZTX*)5(NE(G zRtSCa&?nDs#G5t?poAHV&?y3)BJ7_EocGK8{6GRilRPw03F&jiw!e>LBX|jbmjJuO zCg16HSBonqK^VM**-!pAVfy1ty;g+pV(?vzJs1RbF`v4AVsNt{SrL-ycJp^BNUs$F z1P?**5M)2cf~2QMYfo*OEFl2N0_-|!6E!R^l&K?x@Iwec8|F0>*oGh8j!+~IMe^)M z6nC+(>D4=jV8aDATg0{QMl3 z(z13%gjf-X6=6>`VS&uOp3T!IfeT`}*llII%kjXUi0ufD%HXKXZgzLAvh5LfE+E)* zfj!-oyKJG`x|&IF;{!JemLUVPpE{^(Vu^Zjs26A7Zbg#+Seb$@!h|SHh_YLk;SjfA z_8J2OFD~$+yZU^qQu59wH-r&E7!hQb=w2>pnVuMhpv?=~yzDyuzK+!SWs;6yE(_+e z?C0ocfpcfp6d+XdLN&$REv0(9^!zFjzR1HD>htfys_FOljUxo{LJ-w)@~_<6Cz(nN z1VspfI2KD|Jjc)H>M-giIp_Z1S<%_L;_~_JM!2 ze?KE+N5x<(6+lC!CxNysoA+^dplos8bdIY21Ba+ z!(v#X*T>1rfQ7{%|H%UK-slv6M{Rk!UP(pRA-lwrIlk*Nj z3j=NIuWvu7tc!uCB2ENo$QB!ON6y8`MeB_0X)K>e^a!XIiTg({}I7Q34D~;bCBz)>G0r03__R`gwguJC^&FtS4293nH-o= zuJpUv?9b&rSqMhTU_`T4^Y>nnOI9Ta!xAto!S3^f(_a_<{W^hQBLOxve3o14ten@S z#K!_(N${oRZj)9|?c$Wx2ti5^M7KM*!c>Bhz8=9)1`K7`ecln?YFan{HbMk1L{O7B zbGEJ8C3_FSS`4hIb=@0g$4yDO9=bDJPzp-;EKXMIo97++b_@bQSeLgjgoT zGTHN-ujW?t{lobP1wv3jquqaGi_#U(1_TRUu%Nr@TKiTi(4rq9o)h9Z*@K~Gjbv$? zF*mT_2|SVhUn=2r>bcJIa8bPM!VNBzSH2K#_isCW7`{q5l$H4 zWY2PEgQ3%poeU6O!7FwRAA07>$Ly@Z%XyrT$H{(f)vp|U4?Vf~Szsy%rnE9A$?B}$ zv|=VgH$XQvi1z8>OaC6OK?oCtFj4kTNf|eDYvmn8$Ps`XTFW=QG#~k4e-`P}_PubNh8#F$|$V9119(Zr3v2JE!w2LIWo>&~tk|9Qu7QC>dc~ z4#wr!cV%QSy+qnP2jQzMe5F+I*~86gBY!60CA?&})Eq8@%kMmT@ZbL|0G}xxio9jL zul#*4LIwje7_$HCy(HbyjS(L>1X$230lhSl1KRX%1Q@X{v$8ii@Rnl_giQ>UJ(AI@ z5h6t)lBP_xsll?O(X|Mbd{9a8vmi-0`0{}*2%!oPN+aa-jKa2%ZD$ZZGT-f77 zbhto=i#?z(Ea155v6o+v1=>u|rYO?J;C>NJ{&D_vTlV8-I zUpD!V2$skcflNxd3iq!FYPl_k&?*G2l*%VOveH=)p@ zP6(v{r8EQGo>|)qOGF`93V1Ro*rp-_BlQGxaWy-@^jPVnYrZ}J1&7}|e^xrJEZA`346CwqInYjt#!BEp0+ zOwdACnt0#nK=e$6HYI4IJ+MI130L8zOAtnxFiQFNw0d2G*z3y?0;C{-nuNK#_vnX1 zs}Niy!G#u~rLP<}a~MBD80LauF7`A?T=e94sL<$S9ilKw3GJcBw|;D|n}l)&D5n{f zKVBsx`JP{x^;1UDU_?R5=8{!lfZR3&cL8vx$Z%xE`8md0_8^RL!Wadmu3cLEKSvKC z6i7k=-L6K|kg7?>QG`q`$fRugyvy0VHR0D0?!sMmqgz*-3s=X!#LJG{;7CJy#p!2U z3jMDT+!erGfgSd`(?na&m-!-?F~E!l=&@Yk?CXwS5Gt5ZL5=RGrZG+YOdNuR0$9*b zU5Zu|YconhD3*p|YLIgly3elsX-8nKwc)f9)YpaBaiw-4{FQ>g)PJ6mv3nI(trTIw zFGcu8kwoEC?5go=>k-@}!Hrrf|A_XrM30RKWztYam46U7Og{E^H^PV%j8Gkk%=K~` zn;s*yNJ5Jwduk33yww?2(naV|gdRoq7~#;;KV9zs4&k#De5NhFkg8{q(kgR=k9_cv zLd>nv9l82S9}uc}pqjROIiKdOx~k`f5GV_QwA#FJj&LkZ{e<8m0xooV!_iP9;d>|& z!A=tF=*jOLdaED&A_}1%pq{3`l!HgWM(t>XVICN!$~E=EuSC5oK=2djymwg z2@N9@i9it@3M{)cEA@6Wk0=YW#375;*%U}yIcy|~U?&H5l+G5|`TM-in2S&=1+~=d zn~G~vf`-;1{8WUW)V0AMx2K(N+KBK^9R5)q&x}Lv7Ab8;$d`nCdUE%TXJoD99wF$7 zfgXi1-V%QA;?&0o-ICBvUCX%k?98k9CkWcYpiS}3KlWvYuf{WkG=MZ}L`j#!vkts; zL}(I(CfdBc5(wRKVYVAWp&S&-v9ng^OzQ%k`p*ar;?O{QX1n1(^~w4H2x91 z?N$4mVF(3$P(Z_{Y|g=N`{tG)bV)!LEx}4v^QMPPt4A0Xgkid?In6tKl;3nAWQjr+ zEh`7*{tH@MF@Vs-15Gp-hJ&0Vmz)$8V?ntXlv5*eb2zQIv4M#YEez4rR#7YbGQF(l zA?Waf4sDG)gd4?LkE$ZP=Y{u_mS=S4ZMT!$h0q}n9dxF2Yx)JN&3Ug82IOIYU|00~ z#*cH&5n8yRg#wxCe|CGEnkFGY5&~#2{65FwS$W+SOIXN(1&zdFnMTEVr6mX^048*r zR-<_CyQ<%B1YL2^rL)RyH$!>v?rKNq7KQHr(}=;#xmW+;6K8?b6mXitj-u-t7RpO) zR7E%nN7>tp$0uBmd9|*@%hn2DO`&r7#n0DbGgl*+2!RPLr*H4wJ2LuXJwhQb6w=W~ z)vqhfMwxpMDx{%;;@d)vp@k)nZy^lvzz}t;_P^B8Bic_8@?Ysg`KhmWN)ukrm4IA2y{KOkc_d0~6rq6!8mOHHkE&KJH5fzqAqPKb zA{U2sj30^OkYK@pEDXr9*MWR%>s0?4G6;2|P)99W82CVx|AZn!tPsRfx4M0*yH~Sj zI)Wt=EGaqVnWvj=tFs!xQvy6`53g><*x>u}EP@3eSWrw@fBKiz;nmPn-RWtD_mEX@5U*K#Xitt_n-c!d)FBl51Ta<#}Ck}qJ%&ECr_qndk zK}h0)B+B(-+IR4q{jEkQm4s62!Q-uwrhX5UrC89!1x<7;b;U_*$9Ux|1ak(MQ&P7@ z$aXwt^DcxME~udrO@AxbUElTy!Bz=umDmSBOX8-o-t)aesE~mQ8TQ0nSr^+OcA zjuhn30)OxBot$%n<_Kn-U`AWFy_d4CUN&??NEL=uiaU$fhi_92O+e6-1U-7dzVP*y z(QTOsb#hQA$G)pj`_1jG@f8TBieO6bhEDQ$xZJx~iQp*)p48|5OPoX2540g@bAdJu z>gwf155sud5n5!Rg&t5=xg<)=^bdjyFSyWZc28||#kyae2-TcWO=ag=7jC;|-=3y;8FgoRq*lZLU0r8 z&-NW#gO{BJ!I?6**{Puf|N&~`rSkK6El5KQI4l-@8m*X2F9Xvryq zKcxg_w833;sV4fHr7(gaHyCoWk3nksi*nUg1!(wYyFA>uME zlaQ$ZnUq^pyxa8QaJeOxaFPcn8lFyluj{uDg&~AVLl`~a^7I+IK3T^g*eQb@&84H4 zrd3^O&q7G$g;c6Mc{uB|{G|qjVnryXt;kd@;hoPlxn)`4$_=iReOA}yPSw*9Kp$CDS{b=u<)3kS86w} zA>@ifE-esqr}Zw`b@lq>PYHn?_25d57CDvMj}Rg`A(BqL=l1A|Ep19e2v&k%T1+o^ z?g?9LnS-Ds06KIsG%NLJTKw^1gf1cIq7yFuS%Y@rPX-VMxM6^so%%8(7JZueV;rGV z96ITC*ZR$TndPb|$AVODNTo*Ps&*e!o4yWVKpF<5*-?GRl@(l<`8Ff`m4?3r9`V+% zlDFJIh~8>A{YpQ0WA?0KXz|DWw8PwTM4q2 z*h{>=%0TKNUUdY0A<(A>e7EoB@6q*_5%L8fpHA>CxBM#>8k+1#W_}zVkB4sF|oN~zw^`92Ox(E@%5J64CWu6_e{y+voy(HAr=6?I% z-G>s?zai*|fetMbnD-$fe57zje(#d;2NEh&YT;TXn7OvfXR+8X;ByVyW31g2wDxTAUCZgu#LC%5lgq z*PuTbVNd`Dsf5}iwMMr!RR|x2;Ukq;@~*u~Dn~_;1&zYcNHA|Gx}xyvLWCYJ=%JI- zfkQ%_e#Ytu7K&g&fz0XE!2#ck`w{wNpihRKG>?3&k-c*K;A9>A&`5bw+%^?Q!|`Z@ zP#y@SiBoxV->u|=Y6N>uu&2rS##GsN_UB%NG$BZ%A^O1ND!=p<2_+U7DuN;1m0qL& zlDh@U2;U{)J0+VB`8(b@ADWF&C8U4=IG@i|WF_`18ERH3Vx;u;yf^b~CScdZ)d9j1bEW zu@v+p=4t95o0Wv{i2?Wlt~bWAeuODZl(WOy<`_cHXmeDCZpX}>0#`>2cb*=%4mKZ z`nqh3f!r;GKsgAcS90HS8XgKfe2riy3U>5?LJ`l`B^jK$2zgSFNAp~B`{>QrZtoDP zm{3JI+7pzegz!ZY zzEGqNHBWu9ZcZ#h8!xm`6n*PW%x)xs6LNj3Q*oLKbDB^~{@gC98R7 zvfwxzXSdXa01MtmVF|o!Bm_qEc%0W~sKj(EM5yD2Ituv9_~UPmm@h-Sv?&QuD|xbahaZAJ5BO8Ea@odzNsLA~!ee+W^}n;5Eo;)cwu+_Wry<#Ss z9^Vqo{~a%X6N7J*cEH)un4|f{2&E!WN~h~fPD>7C{_Q{r5`iE(rQFdV+1(x4i7>1L z!!!))xB6TRY37*4f_O2Ar#iSemYU6KIe`$x4N=riU*ZoOFCBe};4TX8w9Nf@*SP+u zy*+|A7kE>g%D=VD`P{#91Vbe-q{@e0YVfCNR3P}tfgdfUM)J+>p5j#q{ff{}Geh%z z=L}2UE`+c0@Rj!dak{tC7MXP;1d2f*JqH+>iX15DLnxJlQaVvOD0kw_qtIc52qr|( z1dysoOnY*>g;ECt2%Q|lC^ zbH=zYAfyOD3Z*GGtP1RtcWWW!h(Zn>Ec!-9$M!6LjZh*4B{W}KyAI!s8_`FIlY=;# zeM=t?Nqa7`K`@#EMs&ojHdJw2u+?$0gfhg@?n$R=OU%fUIE1$hcuS|uzN=r}tZm6g z&=mk(S}*@CjG}p*!o+-?7N_)01_`fh|3`Z~pS0Df7-FG)O`N z#hv@+KTqsBeq*u@F$kdH_R;61i|>MO2!nhuNKxcYxwP(j(|UxD0`QSO{aCo=ne=uO zj=3!OE)L%*rq@c}FYBG5gwP-d4K#AC9_=?@wfiJOtT@C{i305nKjTaKBs5r_aIbqLnX~8Md_N0C1U>& zf@C3xmLStx@9Yfr3(sRg1{Y*dh>_Sd|D^7G34|eG7^2MWz^uQItgEIWK84zimP*V+Xq13PTCQaW1&?^uE=G6&57_r4Dxk2?Sl|*~4pD>< zN`%~}cSq^1H9&9_1V`GJKCI5Nf3@EfAzB2YY1wl0QoAGVYJ(6U1OXJQlD_OdpgYqQ zpBEcDZBWM$uyzUBgTgfVFtqs*fH_UkLpQuiWQ@qraRh4gN#bP2I1 z2u%XeM6*vwZ{?t*{Uo%?K`TX(HA(|Q%&}lB;lltQ%7{yUJTg?e9FLG84H>kFR&5&tw5R&*HiJp7=ioiu$uXZAI2tWrt_vX7}UktR* zBh)BD4W$q{%{Pzl-f|1!qbPi&{6+ZQe$H1f%@KT<;6p9_BG?$P%7jG!+G`V@|K9DDu-rgbem|m0^_52>SdNY>FA3gh3e?q;ooc4F$EThF&c3l?T33h8ug* z&8+6?D8fG}_(wgs_W`GuuFDEl7MLi232lglLga70T(ljbR1ivODz|pru5TAUjF2x6 z`IPIeJa_KgtM?ZXDtMrRDxV$fcq`@2bA%#pD58}=UHs_VW#ifi#++bGr&ZH*__(`U zKOz)!K`|{TEjH3k@7f{|GK3(5CiCGFvzDK_n2(So2uaknZ7H?>b!$rzcEfJ=Co%)G zk8p9nufoe=+z>`{Bfp$~5$i3(LKakULlwcrDmUA2vC|N|c)*Ju?{~CiswLkIgboSl zpg{a;P5+Jqxz7=7m|#OAciw#MhumtG2=NjSPiKd7b)1>+{T&dT7~n()8opA0SEwCy zLI{+HKx*`&mrZxFo0AY)B%p;V|Fj@O?utSRLNEh@DUJw#cl@~MOd~=&FSOINxhv9o z-J-MuL5~acXjyz4wr%=ep)rI&E(oOFh`)5YUcXIX5eu65pou1d%5h%4@K3@Bts>A$ z=V4p-{TndlSdQSx2aZ%C*CXvgc;01%dSR%iIV(0-q}y%HHH0o@=%Ow3+m3?|I2pDG z6ACav)2853>Uh|IE5ZOD3{V|6-W|K-BL5lTJvY3kuGKNtS5$uEjgYJW$+WfjanUHx zT`vG3RtjQi+AQwt>2dN8LI~%EaQdmb)ixJ@7$+c%Ghv(#f4=B1TPHV~ijXb?>Gbm1 zr(#)d^!;)KXGw6T*mKm%>hh9$&c!S!Re(~utDqYGiB4NC1XD3ErAV@1I=6(qgybYl z0aMx$?Aq{s%gNxG2!paPNGqDxgMSD2zBr6v%L}%2##42yB|+2b2tv64lv4nYUNZko zyund~b`fZ&O|C*=*P#PDP9jY3!UT=01*gh3&kNKh7$An{~v=MRua_Br| z;A=|y+`l>q7Q$dbgW&}{&$m(6N3azGTYB=%{@&|)GT$P6l7~+;KhopdA3qcbL@=KM z=F}v@T0$~+Cc+USl_8SSUzI!I>$_J(BgBY84CRxVL7A1SM@Nyd#=<2m$P|K1ifIp1afTyhtdsE~sSO4AmN+*t7a`vrtSMHr;6joZ90`N=sgglZ;KQvhgc&p%xs z=7HcN2|hH>w++Ru+#5X!I&z>x$1T_H>pT?luf!7W%HU4xf6B%w*F&AF5PmV>7wyUg zRzt%D)kXv_CV0_`6T@xzc5yFb83F^ms7ca~3|jl25k;uuggR>78Q$&@QK~BtN)(`k zqR%S%;$}_1JqRC#;3EyuV!Q67#Qu{A?c&f*yC*SFpfB7A$Dz`1`I_^Y`o(2$l+9Ng14R(S6RHe=Z>y$bbR;5z)`9 zC8x^GevObP4SCd7d%R|>Jg|8Zp20KrzJTx7Y^UIdM)>a=3VPhZJ`0bv-R)nj+mnkxt6&LHH7L5>*v z^WX^i#ldd7FCv5rLnxI^SjvGVMfMNfedhz;B_h;FKn?wAQ-klk zFT}NeAhdErDoQicAWt0fXa-&kmsaIgnlcH(kVg-w5UOiyoU#^SLJ1~l zYU+)@`MPB7K7>&@7^T1`k?7LUdg?y}GXXH8!En1nyF~w;34#wV_|ST@bL+LQTRj~S z^yNXHzOIv>GyA}YNI!%YL1>{ZhOCTT>E+501V<@wq~S9z=izWrHWpz(5e8_$S=kyb zY~GrLP{x2Viim4@{1ulT%SUKahBitc*FJae_j4&lcrOC)>1FlO`O)iJ*Zx8XmxXXT z7BCyS;$*jV5~7qLiZX^>-Ze?(DwS9wfgcj+pvkdrU1Tb6Gr|Elz@AT=uC*7IN_61m zae#4(ZpSzt2I)snRbxT1C=^rbkt9)?spho^AyWV{DI4=&ecJPq>UM-aKIo%d*Z1m{ zt$rLQ5Db}MNCPyMYe?>Vqy|C~KP1u3rj2l-G||y$Se@&@Tu5G!AFJ)X7kbXhsMVgD^@3bs9ZWkMpRmW094Z`ne{N`(^^+Y1S1(RqLtukpuh^R z9w&qvKB%GL<5#yw@<)|BLK8p}4bcPYJPEM^9tdGf2&1-&o>Gx6yVVoHn-{!k`kPMs z$;o9Nf-uO0L5l3+(c1-2<%c2s6^FkxN=jR=bYJ5xLa0-OI-2EYAHBb##aD+AC=P*C z;qo(?j^p55K8vzvu72E%v|+p;Qb?X(V!tuDm~UhB?9yPWVCRX-nm$qkV- zuI}AjA{Hq(j*!NHH2OpBp%JUO6}x!WvcQl5hV&8$<_N2aZ52dlkcS5PTtrLs((bY8 zYY6{nHqZzA)X83=_sLD zQ}@`RhgJx|au7_bpiNX^=MobKgcxy%p+4^vH2FAtV=lr!Cj6su^{lwuI{HBuLboz> z)2zK%qV}O8c@QC10%9p+c(|@fBIqH5dSf7c^See14gOYM>4nSie&CU7-Pa1J;&yW z9WvSH?jU6GLKbbPSN8a9sF`*bAwm=)=uhX0_9m~Yaes`EAPEVy#fbgaqxwMW4T2vR z_))Weyzn;moX}eY`zc^gd#G1I(HqJ)njm}-f)6wj>yw^6Sh&k#vJL@ApdjPnQKYSv z>x=MB2EI{h_jhG*$d1c?2qpqxLK(yUAf0TNm0uBZ1tFIr-1dkA#~jMy5bOlOj^@WQ z`S{U~`?C@B1VN8r_+rUH4x17Lb51a)Kf+RVS>tq_5a)UpxblK4MTXw`>%#w?+kp_k z2LTlNa>d2fJ?3a33`)ZwEky>&U%i^fA0c!BbkQ7a5M7|zapws_mK0=BGQVw4#r7*( zEfB&LA)NNKAA|c#p0rOwjR4e8BkC^m;$)P+#}eOo;T!dN@G|ksF0%pL`l$ zbPor~7?wBCBTUG{1jRS|u%iO=3t|zHxgnWi=e} zmY&<<+J%)7C;Abp0IFyx{4k6TENPbA$b$E>@Sb*QZQmcfsZ~)zu$2Z|+H=+Y-sV0e zxg24L7lx?E&+t3B*aT=I=qZ67J>UkvR&P6(R|w+*FfPFUuwQZ3tY?)`MhM1YU`(-R zX-94C!i&ZThWubinNQ`2e+w9|cDsWC=hP4bYH!&*x%B6$t$T z&`;o8B6g3ImV$e<7vGLV&&K+4T zj3t~D!HGTyNODPbJXF34!A=6~XfIzrWoxzB<~0bJe2__#*|tgZ!L^W02t6{;L%GuM zuc_1Pn;s#ADL@!?Z8T?n?V8^v2-!T4O_BZi({CRbDsBje;1GKpW|qCpSUJ}VFMA7t zH$C2t{?rjKnFxeI5g4RARGb;+I6poL!BQD4X-BJKC8heXF%`i=6fEc!*kyHiJZ_tg z@QDeZDCsJkmn458CJUjH4?5|&zn$CkXsLM-LOegjQ;(z+g{JQwM z_KqC6Ei6b9fFv606&maM9%;=%C>DcanrKOu!{2%bwj)?efHe)!Aic9CZxi<;)bc_t z&GLt_-QA@+#}N8?pr3X`u?_D${5s4KLZl&tTDNb;l{4ezwg~Qm;7-qRr%R;X{*D(y zw={Iq!Zj}U=I>JzUxYsl_(OmCtC_h^{cxop!gmSyP6<(*-`Q?%i9m!-Y3QV%GRp~F z&2_#E!Al;zXi*6}^w#o>W;sF#6GCW+Mt*CVIojERP|pSRw7+TXlCx~;oInWWhfo?< zqSMv(YxeSQWr3~&=+cXwXDN%W_3{ZLBq>1>EnFFgG#cmsU5b#U3|X`@zudR^*8anr z5iDfDg1WXyO|&#y;6DUY9x$b54;Q>;^*s9;LWBTBP@jJpN;jL*aTg&*0%9cCe>TF2 z?*{jjCVd1wCg{Q)3yYJ_k8f4=6RaKC4QBkSqOnV5J=Clj<4{^?DBksG-XJmCRyzncgDr` z8^Vwh4AHW}TF&P5n(}O8K^8z3t!d|uus)s{l0?Ymfn17+oenc~`G=(teEGna?rM;y zs_F1qX@o=}NTis^={snA#%mIM1;CfSwhCOOW}?hg#1dh05Jr)~``!Dg<)7vtbn!qJ zJ)jS-`fF*oH3(6n5JhJt$D^ww9$nak&>#X0^zQL%tn7Wg-S-eOL?DBb`PIWlc6Y?@ zBYfb45A+;6BCa$hZGVN}FAn~c-fR`|v3X+Zj$q6HV~V084~KKVP7Okc=7wkrOU#XS z7fRcr5z=@djT&+8s}TOE!7PM)KFFuak4Kz7eWEN6Ax|FiXsUH-{wHr_^BuuQ4t!{b zDjVgwGXHD|f{P5e&}iSMb?xZR_4No{^3X*i@q1}{&I;oJgjPOirOI>uycb`1bQr-_ z9Be6sn=9G$eaIi3{3$NzqVI1G^kr!mNio$~C31x!m-4sMx*>IK;KT<`)FiJ?sKi#Bi9z@& z4?n3t{EZS4rZ;pV=*odE^@rLkQ3;3AL4-sJNTl$3>(_zI1>ro~S3C$sWds*#aG^$wjDNrt@t-e(wG>#>AbKoXVkN}BKY^YaKoy8^TmXndMd$SXFE zkRT5U)a*x&3ZEHCo4SJqx)PvEYwfA$3Y-he79osF!8mP|W}a|+{i$z1LYpMCQEIR{ z=0ncBq5}vo;060b?_*HaRB`7WUba^Tdm6dZIzn}26wMHROTlldA!QBBzV_4!;WHn6 zrsrO1zf*6+EH?xTCRosr-gmc8=ZwckghqL2q^VioKFz|RAsNAk3w)@@w*|}pT9R0X zkR<|H6vmz$8=5a8-i+WO4jvS(?mV5-SveuHlLf|7U`+kzvhh@8hw4g%acLN*W&X{J z+4FL@uR}1C0y8RM4bN}f+qey318iU?!AlCCw5qr6!^?485Jxw=q4wKz*+b_MqNE^- zT1xBMn*tdNO@wu@j{QSUHnUH8mFrLbkSxT};rq^@CwV8OT@l7bV4Sk)pq+l!=81`u zH83HHT2}PgSjPO8d;}9NFrm*`{;X`H{_7wKNBF0_jUP5@4H0)Emn z=*4;4l?XM0P($hI@TGi(@L5|CYz4uVa4NtXFC zsI~^7UJ2@{1Xt>{rMYU`5KJpTR(g1->>Q)(lm z-Dt8U`YA#H4+K!6@`-a@_vVn72+>jyO;f<3&S8__n|BBe3eZ56b2&(d8_GB%SP6p_ z#dJ;O!GE``CLux&A}C9;tQ>h=+Vc@hgz!QLopLR3edpP(;)ReS137dkXCi#i`!HWQ zLX!eCQRUKctBU^99YGjZhH(md?Y(F12U-R8u%L?H)*1$ zwlqvRc^)B?0hx3JefCwu+jA|q5o(m7h8ACDxCGDdclQyzWx$(yuxyz@`0%Jcf)yuN z(U*en>t`KVVe|#ToCnOQ*=GjTKe^8ri;w}3LG$Tr@tQL;n=2dd=s<$}YT|Di5i&0G&Ge_+Z%3IKo4C$o}_J3Z}iCSuDPnb-7I%+9;^j zrs_qXvSa=C5m=jCUid`~7&u(!^>?NwLaP9@(zHx=V%$<0c#NPY0D5#-wxIZczH+T0 zLbyDH(>>LMySzKsW{Th@0B)3Ezp^T8nm@}7p-u|wXcT^brDbyVr8z7j8KVXR*1<0YHv!ZU%hj2A}gc3<8q2uQ*=auZnemEc$%0nUD z?kuKFrNvBFgaQF5peLX8H}O?NWF$hO93;|6FI#PyGNx65;4BNybiihob-y&WwFkjf z7F-GXH(n4{H`i=`dn@yIEsKHO*7Y=H7~O!d=Z>^z?r5%z)>w{o!_|#MG{a% z`KO`&)2V`Pc?fM>&_=mohL&i0l1(u}BoiWOF|GBE?)cB35#c=-yr=&VL4bp*QkjwD zein2pLMQEIEly}zOMX;9FlB%#ZIPBZRGc*XI31x@0cvUZh(CSKyWVIv!UVts&Dd}8 z#;qc~DhQT>U`dPV`kI{T+fAwnHoRa%V>jBuZpOZry$FR8P)JW6f7Gz}mF*D(cV2L( z5+aK#OWNn3nXE$;EGa9#UUpPUv;7i+o;2vuO3=lyd|};SgJ3EQrZhjsPE70J%MV2O zzzZL!j_$FQO&6tt5Q+t%n9_*v2gMtmjD8`MNI(hQ?k#aQi!ZYU4zS?282qN~OZ!}n zCUtiq1Y=1srr~3`%zX=|j}$_mAoNikOFh#MJ#b|rgb6?xO||!S4Z?XD%HH;UJ+o=()e?jT zK4_pt{wnWAkDv?d5E8i|k@m|OE4$5_%y%N(hTH7Vw%=5X5K7ChaZIe? zoLAZiZ@J+u9i1HX=3bSu-xQ&d8ycyGqNE!=4riPYJo&(r?rE-c)}@cToe@3)e55pR zm84~*YCr%&n+UYg$-*T@^i9r&AcTA_$fxwzV2h00lE)DU223!Z`7~GSzTl>~WQ1>$ z@Qs=<;nB`mg|bP=gepA?g zzrm`Gc0(t-I|w7nFhap~YtY)kD=Kdga%CWw5)UWG(e68sbP$Y~U_?#wY31v(#magJ z-lE`5Gq7lN29x)aEy5pZ_(Kco#nA1;D>-5iY{bEa4k<#P%{M6PO-BglgmC&RIKoX< z$~;KPL(u02eHtZNJ3x%jyBZ-_2!d%`b=FUCxnKG_S%MezX)xE59yAjf5A)ThpK#i~QCaY5j zdUBvgCkr=SUnG>YPQnNSMku)Qx$39KY`B0W+6ADUW_iaqkAv!N4-kF}z;A*V?YtrP zrWhl1h(HHzta5pul!u9#AlN8?4dqD-HWtk2+-`yJSrR_e*gZElf%Vr`ALl#BE zjppVDO@B;+vphJ{lkZuz=f5>a)38K~0<_Rt5Vj=4+pnbx!I=x3X}wt%{!puRQ$Iou z19Irgo3p1i>@B7YBe;r!D-EAb#tJRIRbvQ6Vo*deH2cPYOzb9^!z>7ugiv}8leU=7 zUk_Cfs>Gm*N>r(9<*#dai{Q@*{`9wCXek~k*d`c^Ff0ed^p#T9`D=$x&r3$Ik_IbU zJr0@9b}7D8gW$vkPV|7*ZK`#NPihey_`rd}Ql9no=92Y|2!-NMNZb1b^Q|>h7BT;0 z!Gr)z(EGrr&tIFZZyFrc@lp&;^jC|h@%W6;)aoG*oHj_Rh&>oBUd$& zcUFY{Z3GWK@SuCrYcyFN7B>l@0HL&G&&i&7MPbfsEaA-q-jtJ6uDFwYHAoL(SPX`# zZOvuN{f5_?A*3omDh-99Y3|4Uep?_kN zXA{{Fws^A#!Vo76QGZlcs_gbo_D2|Jz&K6+Z*No*oJR=#GSE-&e-CP1+Atz*fRH2! zNi_Kz@2mGY2Du>=NkI|))amqGb<0zW7ix4b?WdhySyV^~4~qG;s8 zP3;XeyVfEMNx%>#X*}-(TDSG=LvWV|cZ#`osqbPAlpI7b5(XoR(n3`?W~_X213`xg zIRDXY|-01T!I+e(Ld$r)wX? zyho@7sHL{rR~fPMu|_(Al@wUfiR02ManFuy%|RIDfl+Gq(4#d6H>Z6^sA51BtppCG z^`p-#N)g6*VT|_K+rMewt@u`kP|1W!`qHX$u87s!^AiXT^58&imCsuh{Q8jiaTZi7 zKs7b{^9ThI&MVRge;M$XX5i9)#;HQZvIt$G&_%&DXOrWXN9Wccbjm{~MUuHoGyfC5 zzY(FB6N>38LB>?qX)&*kBa|sY86D&CdZj-5!MKWGrVM73bU8g5oZ-{{3L#zu;weXL zns;WZ9rG)~J2`kq(?6E?@$P=(6ofB|@P$HUnS8`Tk1cHoRlHC|jmT$UG4gwQ4??#h zbkm0KSt94h(1XG!SkTLaUTR&<{M{V|zoig9iNYred}=diWEO0fK``P1BRZk=2{ZZR8xb^k$Tm(;E@T8=x`_y#CF`vZJPo-Q-CyT@Ha zaN-6h3QM=4N!#O}DZ-E(3{hI(_aw{KveXm7j|qM>KO*kTJM#5VFhafrObeuvc*RhaGhj9mIP!`37f9Ik!`=HA^a19fAoO%r=ycKmGuz{C83Z) z-{;V}7X}|<5M21dg+lnuqpAVdDl-s#8Q@FtYV~#BGyC~|B4mp|HVrtFLg%V`)9VmY z#36-l_m!#nvl9vJ2!-5GNb9CS^TG>8r^HUNpojrQG@Y9(eB5$;nFzf~&`Vuw6Z}G5 zE_^dWG$%w;mOnP^sG+>^7(%l=G}Bc3p$M~HIUk?=DS7B682&4s(NK8{;VN8ZuY!xx zv#&&M{(_f7cp!vgPifh^%KdM?BJ_wr55?(MTs_s|JE9SCgdvB5D_`I<%>$vS2rFO( z`xTRGjD1EeXFgswlm$aNwc6vSqAEXs)@c^liGdxhv&XsLY;hl$jnFO$?UWAf+jZjf z?fS(CVUiF=-TH`&yW$0N8G^YSnA7C<-l_HP>8VMG5Q7M+~@!XKJus=0gJMtlMg3Ybtputfgb%o+Ep5Oe`_ zX_p;P-f>{8rxziZ3xa7g{kLI8f2!|4gmO+Or*vo_ZR^YnH+VEypsxt}v_9P%TKC1P zniru_4jO6xsce#{J{YzVp_B(oY2i|``+rQ`by!u;(*SVkp}Wf#y9>L!J23d#frVX2 zcZYO$gQRo`(jncAbO_S#9iHcPe*fN&%Q#`Y$LU7_fr@C78?mY<}75 zT|?;OhCbR?S?y(*DfmJ!RGlr%>HTZ$ijXJ=iS&^7 zaMbEXHR)Ug8+ovymvNP3k5A5O=22omjU?32b>zRkbJ=2v5JIOAbW-*2Jd)PmSvDJC zm%q7W)&ppp{h-B1C;Cvra!ie;ggD%z5_NAB<+&O-=chY;%a zz%TY&RJN5OS_bnIG+n)?IJ8w{uufjXL) zk1tlyKD0vy;S+rNw^ev&ejHRhlEaU$z?FX=zl*X-IDh&QejLsU;S|nsPgs<1iC#r0 zV1)w837eY~Tt8YXAsDfO5w#GF?Dmg~RYhpvhX%R^tH+V0^S5auWC%e9)#S!(i-x~P zyb#7%VT}IN>-vd{n!9}wA~_(E!XW!(Uy|_RID|qLD5QERl^J`0TR#_JP!#V(1w5=fz_0YE&SYae^5QfQfIX>Te`; zAS4Mv67`k%=bzitySos62*VGmXUcs~BXiY7l^NhA2wrrI+_rmr#P%LTaFYc$8UQ6) zcEfh}Pa}kiKq!UI18J=#FW28ihyjS9|H27B5rJ0rVIb^kF#1a&b`r)BPBk?;k#x5fz5EHF*Kg~;39`(UYs z34$&==u$R3m(Er4R>J|IT?*PMy`=BgKmq}g2B%V%GXkj4UOG|P>(Hq~INuRur^gJe3m z?m+m^#>^pvE+*)rg8k&6Y(p*6I6?#mL{PNP`LMC+0n`5f7!W4}aTE*>%>xr^EOilT z#h{js(UJC}KdZ+Q!B-x9X=l1|$D6m3V^#=(LJ&wf+TqPpv#UB@2ousUK?Ne1+ikbE zbPz(hG?ddlx0p2)cATXMA)O1-Y43D}wC*>x<~D>MtnhOwWi*5DZ(H#4ARp*ug_7}@(=Dts1bo08V07zr$m+%?nn5>1>fibw|cT| zy>F|8;3@*Hv?|Y;`fv2~yJrXo;o!gI+S1Nb_Brn@emuzolQivsIo5efY9A211;Cr8 zn(wY2z0L7a6QNrcx+#sldRr6Y9;k&dC;)@hBDlFc^+2~bf}RxUQ8oMI_c+?fJsTmA z9Rg|CaK-93pZVK?FfIn;^Z;R&si{oQ8SdK*_#p^CD3ffxwPMe#W2+I8#2|?}eZgBx z@fX>r5NhP0hVI|4HUB;K(^5t#V}deT#S5Dbo3C5=8DWYKrYID;-TTjJYa1X~ih?Dr z0XdiM)7Eh|LKqc*QM&SHK9?Hb=Q<$N3qd{Yi>Ve`ES(GZPQf_FC`-CI( z^Fu#XsA|X8euZ=)xA!#1t648cfq;bNzHQ=2>DWwPpkOZDK~o~nd=bZ0OBa?+QxA0wpciUP$>+RbR9p= z+K9htpL>S^U!>s+joCG0{oCGlE%Y7;u9DjX*==C!95#jS&7w!XKJ_*M75qJG90X!A}VMD8(#s=WA>! z@IffzfFe4EB+~)2ImW&S1w2qdS@*}><98m{MkBb&fh$e8d@NLb7X7S7aFGBPO5hnI zt9PsjZALH<0RtMEMq?d*Lmyia5@aEPCfVChxEpLZ*NzY`3GuWJoV$?KSmS&#cWVaTOsWS;)mrV?;(^+LODg^wbr6j?xqhBTDYKv68QcD zwYBVpo+SEmqVoD=zbFfelYdb1#;3qv|(hWz4hcNcleBSdgQ1kEd7C_YrE-nIb2QyM%eM6X%e zy_RfVhTy~jPBb`;6b__a*m`EBg)Df|^zm=mk1u7tR}j7k!WX*o@MS8p98>oZ4Ee#3 zCW9^cjNb_Da7Oql314Zb$^2?^VzK>+kShbZv@~9#T&L2XoQDuD1>qDW^Pk^WOZmm~ zfB~gUP)Y$OJfZxo_MR|;i5!?v$|#m7-7#7E7NMUN`e~6-Ts>#{keMGst}NtIW;oom zJ!;Y<2%(G($|&GoZ+`4~!#ETnTN<)yN;JQ(v%(_22%(n)dZ`n6%YL)5|L#K25&$h4 zQ9UF5?a5_*2!BN353MCW=yO*-)cAw&TM&Lz5#AK8v#+h0>mdU&q#%R3WXCeekN2nK z5xix=n{L$o)yeWd>gFTVu|OR~dxp6}eTl*%gkdQdrit^l(p=U<&o>|#2!H{d?&MJB zJ@%eW2t%SUM5p_Er&jXDD+dw$nZTdkL`=ObF)LK=G=d*1_))hXv}Wr`RXu~y2GB<3 zF0R7sd`kBPgm_tqr|Woj+-@+=!~(&J39RVb%nd9;rMb`T5Ilv!lZL@|mKAM5r#uie zxj~bPm!rgk>XwcfaODG6dbpSymVH>{WB|4p2N0X!<6;~3|362VXu3@MB91!p$y8Bs;BWCcq)-FDf`Thgr`5!CrXo&MC> zua8H%FKZ%X2tx+la{=Qm%d-dl5DeJBfSy6E7QM#G6~Uy!fD&0Kp>b||v(w)`-GFcnuKnBAd3AK|o|cW*@MASuP@`#=Y?rdQ z_i;^xejezjl)tm#jQjIZBZL4x2%skguWW3xvt=w0{5ZhxfBN>u*5Hd7P6+X$5KmoL zz&X;byu=xyT>{#vddL|~7SH}$h45Df{!((?6~#KhesHr7jOldO(;480K?=~3OQS_!Kd2)70{BIDv`cjHp7%|UL~DdlUI?XFchmOVcjlHiLIE!n5D3~b#qHDcM~IV# zIO?m}wpqtvIuk*c6Le`Xb9dg(d@ovppeF}H>>;3Nx9RB1o-N&Z>- z)BxcxAN-}k`A*nqacSHPv@=6HZK8ZUKDk1^&;(ml%Rn_HnTUqvp7$N?5&D^+pLV+x zR>(}1d*mYAfjj>m{kiSQQ~HxygCCo-fH`$x=CS)@g{ch)KPBKNy$)Dc{9O39MGu0V zB-l}%6)TTP-|_~YGr&RsEGT&LdtA1}q=+Nbu|gg7?ex|&jyaJ#5Hgq`gJzXx`}C6{ z^4=i?i9!(Faow~lUGI}VBBXOdIt_nmA)f&`7h?o}aqy>6F0AuhZS8mfLMk()(j%Hi zH$knEt5FDp0E09FA84G+J@_OAp_~uO>27?tT=86!qYxoQ98#z{!eZOPFufbMq(Ju`Bw6d$_Iji>VT0cS-7i3Y&w_g2WV?^U0 zga8%@pyVoJpQPV+cLbr87g}jN2^TRvbXzuxpv?i=^y{bR*4}?Dy;9-@11te7>7i%v z_3nbfg!KrH0FDHuoXc1_f9*sF=7C_^G2p&o`SE1hAp{3`aG-~UyG%na%JDoy@Z$kL zYOy%4%78>>NTgtRS#Tmtx$`1|y8yV;bn{%C zi}TT=b_k|S!1zyi|Np<`378gB)$?^gFyaLx>h=|^)n}`oIL@@-1yh27hUtOjMXm^` z;*d(=!vm*Rs_czHn3RS|+E?PzU8U+US&9(G1z{8nHf=|Ow0X)AG}%Ct(%AiUCA(kh zzY#h_po5CU(Cf!b*XQ;kWO`Gw#j3oevg^~&V@mM)cg z#eiroh^9`A`7_abLS-(3u?QGby~%udY;MZBQwTPKU_)I|y-~39_Psg;Gk!3mskyse)Q|F~lL+}TkWaN>?danitH>>{8Q{qep438Rwdc~d z+XoRQWnq$vcK@YPeW3@12w%D3E8UN~oVi^QrN0nN zx%~OW5MY19fEGDup*?EzO+&}C=j=j=m4#TkQESU>wwXwrLWt*vcse+9*XQ@W(1<$v_aj z&GsxoJ=&mb62Vj)OsPi2)lE5nU&!>90li$%OChT1wfIWGV$K;5fL=;VEjPSMlgDQu zMgU@{)~>N)UE#85KDKaR0tb3Ie7?2#}ha&O0mc!bU7LO5bz>R$G;*_0K&Eq=Ux`=hrA zR^nhqfpBAa{C4G4h6rW=W>kRfvN^MsC>bFH$wCkf8kGl?H%d0dAPlg=0L`to-1j;c zDc6Qjzyt+UH6`tZBC7Jb5GFZcl6qI_@6m5DC;uQch(iNCfd9MHaNCsHG=d#J*ijzo zZsjfP4-tLO0Cx^>r(C6=B&K>|xi~_%D0I{0zenQHJlT{v2H^X-e$~bplXF3)!HM#*=1asrmB|FN9b*h^0XwIcH&l-zQ&$X?~dI|M#OoUK%1# z+1QvrA^=R&6u57`%f8kR90;8NodnA3e^_2QqJS_V3lmg1ZtZpNGF!YEVFPUVcd}cB z?#!hM8Juvvfh{h`=_th5jv!x zgLY39inC-qXFo@X6o5#&7iK9(4u9uVMKF*90}8f5z3UQ7H|Zfbh=T)-KfVJo&oq+! z5YjjxjRN|T>ZR&u+(ig|9MDJL@!=O6M_4gJ3lFr=R#S`DvK13&OAz`+p`V68LwX~3 zZdM0Er5sdJVGOeTkh4*`AHhu!+$fJck@uR{G9vwn0rjj)YJWzax;`R=-7pj z%LBPIjgMWY9@f13972^eRMFf7 zUq`Pabnrt5UB$BvTgCpKQAYS941Z{mq>^z_`|G#62rbOeLi4cx6(>$CIQ$f$nhmOH zZ1BjREuDAz140`Yw9&z99yRZO-aG>pQcyuJYxL!xu_n zR&V#&ZdlTcP{svi)Fmoh84+()`PCQ@!~sDR>sGu6gg0CkLHH#Mzi2fp+`RA0GbcHO z4hiU>z0lI?0gmZU3lK`gpoA7;`%{liD3#8DwH#PeCuRtKh+Ukr9b4o{LLU9^A1XIl zl>)DxLiolB-)R1_b9C?98`f75zHq}Ax=~tt=I?B_x`EKZ0}a%>f4y>CJ3?&{vcw^a z7Gk~9mFv!H{y_M{4u7Z!$=_bjEn`)Q5Gw$&bZZSh+Gz7_`HkQ&0shqO2I--aMW6c- zrkG%g_F>lMt#v;#dko>L0DPrC1x9-!rLKy9VL+M$q|u*}VeNQmDXxHEEeqDN|9*mG z^sbi4Nt4Y8NrI3>31e>=&(zqGeF(N9U`shvET(AXm5Vc=B?DUYj9h?L_c`CM!Q2#~PYU`dPb)R~etxxXnT2*FkmY-u6pasTc~r)}v77EEA4KkVA_ zMu^q+RW3rcI8@UdW_;T0{X&mw1U*^MqrxTRU}&)znh|cp?SH=zTk-rrv&X?+{CG?f z#^@pUE3v4b&I<+*z6-;58U+4p5}nl_$g1NJWI&Jl_P|0rZVA?12z{K;NAEPRPQJp~ z^6V7C8d&qMX7&v-m-6Q?cca}9yv4wqMpHj$^b4`&AqW}LkU_~< zX^U=0cx@s=EgRHQJ`9%{Kbta{g3u}ht+Zx5`O5l)zjq}<3J0Xn;GdgRDWbZs6QMyE z8YmfG(+U+B2$(_$;)Wm^e^H-OtPFEyH5jl7HvOwL24%k-?*}i&kNZWSpJv5B0*oIq zC$2!yl>}Y-p7Gd?Wa*9TRw0D*K{!3N`R~6CQZbX;5GuK$l6KdZ{#h5C615khT^8Eu zZrAg^H-EqO;0*9XJLS(wfej&<)@lgjEHF;5LDnZ%PcJM9KxmVJHtMM%?o~o9MJWhw z(%?o5o_b4p=Jh(M2)bbQR{8zOd&=M+oMI zUS!Bdl8)Yz=>L1 z|7x`D>9$h{^(;_NllVOMgXN^xOLa-bJ(-fPnZ=zOTwhEz21ga>iroU|BJak zhz|bhQ!_?L5`iS@#P0KzqS~u%5K4rhght?zXPvDH5q1a$d|*J~_UD$w!V|1n2$3uh zN#V9zls^KTY7o@KK#fMA_3DX*A#zg)fpQQ?xAyyc=7OlWSvm}8l!Hc^eb4*uuELTi zgwVqSJv12#YTKv!n{5%oFfR;K*)-wW^Q$ylyYe_fDGQX+)+NkZ zx=?ZVD};O@$fx(F|C_VhTd?Ij!k{D!QZX&)tl6|bBMV`a14e21Z@G3XLVjZ-!Za65 z)2|5xHZy+`vS>k2;|Dd`ix|3Y+tQcZhR`kv?R1Qi{5{^SBQxM730{=n;`d!oI_<=- z%V=RB0|sB40 zK@XsG2FAEyj9T2StSnfdl zGcCBGkxti$+n8t3e>)Mn_@Rrk&z_p4AF3ALMo4CbWZG#B3w$?~(f=MnR}OS(h9A27 zK%mw^HH11&sH0K)O!rz>ZeS=vJQu{%f+X{7)w5miGZCDbz?q)GtczdY)API>!9xH% zXm=r&xxW7O^*)4BF({>hqxa@r_47}I2nI}GK<_lMX|2!hjb_znKpr#XQIhc(lAP}{ zTL2-B3F7GcovMZvueW<#LU7;*2a3cTjm+H#8s8zM;I1@VY(lU z%U}8pn_D3`i-0qwS6BDX^D0yV5PJBbhq`^|$LfMzFA@;SxuKkHl)}Wvi1=G62ps?& zw30uXG4~KROFe=)E11(JLac6PQ+9VN!e-d~uR^U_bv(BHgRlYPV{0a`rk*mJV|}Ri zr948t4AfHsKXQ42%6#V#1br6Jr@YYrVC_jIyKn?kHZY~9Rkt>$e|&W<3L%RLvS^Po zx#;+(XzLk>0EnQg$oeqGa>}d@TV!xT1|_AmhfS$D!MuhHaF7KD+92&6zRJ07)fxmB z#+Os*A>ox}_c;!}+>GGQ1OBwNAvI@>Cd@jI(8dgHRJx4zuUSz0^D@Gy7>v?Dd%0P; zH>zp|w1q*NQoeRT{01S(&)8y66b5OaaYyf*Q~%ck!B7qiX>=@$%DMMD&J&?S8aim2 zR<~H6i}9r`geX>sqWkymWB%m$k~oCZaQfeV{Gp1xxZYFM_;HCOl+Z$2(VnU3^2;^^ zBPlSVTs8l}#hm$H#EcjaCIVqp(H3)Db1AqjiBKyEwUk;NQnQ#AoL-7BCIe#>3PVTF z@amo3g5b^u?zGf17fjb@E1!WsT=0j+c!wVU=TEP8Vv9&Qh@^_Zn$+MY#ypoM26HSa5Rs&&{el1PczZpo-?J zZ{1umC}hllDK?m*K`@~-@(UhsNBAubzv+$#48_iQb^jJZB0wTt`D}J0xi3QY2))A4 zOG~l8hazM45BVUBbHX@n?K@e2-*ugBjtK*jIU$)&*LUmFlde+aFD&`N9a(^kUmqoa=z8U&z$b_%ju9d*akUL(|sLoKam z?O9lk%vQEUaFhi{8nc_W)|$8f@j>A&TNKFK|`O)eEf%iNcUbnWs?v{wME6T?qA} zP*0gh-_GgVr8_fVD*(21R(ySDd@}bje$|xmq7yfS(lMA#Rn-)1_z{M=VVFk8rDvN9 z8$U@Q#EL>J&0!RND^JJmT!GLn2Hlh>dG+^yj%wb3;Kc!6bYr(IJbv?7+cAV5fF6qV z&?|jn^1Cb$TG*h4e#loz`Axz6$r-2Yd(8FKa)kv85Ym_-jb;mzU14>W zA>8J83{L2#$&FfmLAh8fFM^XaIMHsw73Ub^&r5_6YPg|>diUZ773u5)q6iLR;6QVj z6jt@OX4>-*x}>0sHrNcG>3KPhElauTNqx!25nwX%8QYF)|cK1zxHX@Ak zz&Nc6gb(@O^J6)TV8IO*6b!n)3uQ`bZz7a%LkXSkrF84@PXjs#(R>h1D?!K7HMx8d z?g*|N;7a%W^N7|elPi7*)%;LR_hW(bR}WK2L$GEBYbx2hx62e}vt=R-@xc&nBfQfr zZgp&}LTD9-Rtkp13(1d;b`Bz#F@qWXshVqg{Yw5r2w^M`Mw69?va4>EejG>8k_0VU zE_C@WIQPD4qXh%pS;3tOFwB#&b2+>n!9W%aC^M{&PJGn-W)DI-E2Puhc!{y3^~lca z2zdZ`6zw}i){Jot%s{0iR8pli7&JQ->G=j*yo8tkwhBM5Jyate?|>gyib5rg@;$D5 zo$bH+Bg9HVEX_f;8Qk{mUKffmCIDkJ{0sDaZk~Me10h-xqN&C1f*n2A{*)uw34{CS$kc~4FwcuRvf4gZH%6cv)%6|5Lw!wEK2nOV<&-)5Y* z3PDpAG%2d4l8fGIE1#GF3DBgizr)P6lb>guL}*}z2I}?|qnkJF<}^dF|K^MvEp382z={@_qD(^m!r%0eJb1yfhrM%*6|K^PTJf~Hc0q^{f*5+0v+wAbnWshxf*lXoQNXR$Sh#sZc0a;^1PsuRwfKJfkhLh}4?-0i zRMDd*{k{AKd&K72GN7LW`l;OWk2$WJH zvq|8-a=iW|LLV#i(H;D1q93;>?)1zt*ddCRm6MlpW3Ns>LGa}PU%HL}pP|zi{of!s zN`oUM{dkS}n>RexLnz{gBDzsEtWFUX?9m7fT+l$vm}T?4pL?}rBj^F>(NH@n{I0yr zyb2*z5K?KcavtN^RL}@P`-*dBXLJTuMr`i8}cc9UbO5K*l*Z@pvDPmR8o^~&$4>u z(uq(e3T2eYD%sta4}|hKFknakhNyB@J*`Y;ZxurD7X*KbtFe+(XV~_L%(M`KA=aAe?4o)k}02E^>Q>(8&*-v;fdM?G=4e`VE3M zGicMpzw~7a(FT(m2sX@ML(}=py0ad3T}B9fLeNKNm0IJra)HPmG`*y!Mj8Mo2g|sYT zyE7G6kb46mO&ZcD;2yn*vRfMS2qBCc!f1IF?^&@@LF@ygcQvy=s-v_XiLfM{xQRO{U_jk2 zCcpk_@{U{tT>xFm?W^UC>I#*r5Q3#3n7W;1#k0@v;(8H=q+p1402DVJ&db&H zPUxZ}^JxEmCRdYn2t{mAMAf;JD=0|M=nz7^G}Kdwb}Nf2z3DiN;K&1x6b#9?1UaS83u7VSVt;)5ibu*6SZ&`Bucbzwk`5aiGf z=kBK}e93Zi5RzmdiDLJ6l)~w@h5HZ;`M{9U663%9UjL%yC_*_alvCw=chGX|2HSlE zH4#vws&=Pkdx@i<3qq45G|_VDjjH)c`5|8f7fx`Y!XkOv6YiA+BJ_wr4^5*QWd`bx z7N;OMOMx@R?yUXOoM#?1BZLV+7~S*!b8~K6oo_?XkpvxDu@ncMi7HecLhzIVPx?~> zr420tWBjfR2o{E5T3Skex&PsWgE&H~2(;2!Dfa7kTrQb`XaR_(gWr1f^UXrpgV@4I z8jNVFRuXyb#XRNX2)|h17fquATpl}X_*_Eh5QYxggfE89bbnUH4`wlHtss<9>f3$! zt|LT9Lj(=A-8&oMlIbIaAz>JzKP6$vm3nmI4MK%1RM2GNp4)eOyZ_!H&EwgY;riW_D+Q2P=5cTr_rQ+tVq>*$CQFpiK|koMrc)mh4=EU?vS_6mUNL zr6zj<&Lgx*LK}@iOT+cc+Se)}=nH~AZMSJ2z51s>{suxY3j|Y$u6DQx({8U28UY$< z24K3}V^58u7eW>rWKlJ6>`Z*K_ErLdJ1@A?{Yc6fmh3c2M6h838+rt<>60|n70d6z zfN3e1rcxAO#5wS3bOC}bAJ|e_T0e1q_KUcs2o56PK-uTu%`ax3->yfflz>VK(dW7R z;-_l2%(P$u2dW=K^D7Utu^vTG1jT=kuIoG1Y?G=~@MAwt@S|+CZlvMf-$zCWIs%|W z!~a^^&S_Ua6NC;n=%D>aEwitkC8eGSPGaChMM6*$7TyktLMY^hLMkgT*tpDe3BM-; z^o2p6lG2t-4d*gCn;o z{#uDp#}0KgW4O(?!F#;D79mRrvZ$c${lq`8b8M$K1KI)FX>@p{%`)3wc>%#t8VqS@ zo`_+o_r3iVp^*z3DY^Ow-OKRRb3xFR2VMGhq~+JWoU^tCAn0&|4$bp5+~V`)df9v! zkSqwvR3ruzG*+*iBZH7709o`(OO0Sx!R~$Q5PF%QmsXrkNpUOIU)+Q+B?D8mfz;D} z`Rp9c8OY&+96DVNJ@*)$vg6pIToB6X;2fhLba?##Lzv`-Neb%x?fsRjV?QCZh(HS! z)RIRsV=H`g5Jp&Fgm&T1wpFNf&2~ai=K*yJQL~ta#q)&S5aOjFo~q#5=4F0eq?%ySs1~T4@{}WrWn3JnuCUxJ{|2KqE`@?@p<-~PK4A&?gWDMY=tG^J$muR>541$C+g ztMA8Wk8ABk$Yp|DS^(G>vYBo;bqc|c9sFoGpV_?P{q6X(2oroTLFKXUg5`?V-YW<{ zIp8Nn`+CW_UBUl7Md)LKJ_?44e2+Ce>>m++bHZ=RC9F^67Mg$7MtBGh|E0>3-(1FK zipKbHryO+B`+}7cnQlo>qY+}*A%;%&gbG*PZ1Z#kT|v;LGPEN|X^w+zK7tt^m{F%M zco{SCVPyw`IuocI zi#WK@E)n1Ur=@q4#1O0jtZ5A;zf?E)#>zPe-+15~#i3zN%W)O2H3(V&TGZmonaMMU z#@5dqg9ThDBkH~_+mh;i5W$%loM}QdUttqd{T*clV^J`sP`Gs?K)qk(Ho{*q_)Fo| z?^dy9>rWGeWGP6dNtc9-LtybEYlILv2%$BtSzzS5Ua262N?xd>IJ~^z*i%r*N5~U` zJj!poA{z}iwiP2d@`EESUBy!^)oSCK5K{Rem9||Hj|oZY{pdsRlL0^K_GjDXjj}2Z zBaF$x7_Eq+ubw;P^jyfF0mgh_O!qu>+Y-r}%%TXByf8_pyEAM|b@sYt2zhLfM^ld? z%}u*wqE{m{%R)2FDwSO09uytFf{?-uDU?I|WA-2G`l*9ZE)3;VZ@k=Nr8hXZA?OH# z4uxoZ*F(*ZT0RIB0#HHq|GvCu{qy7ygl<;orh2nyG;y>;BLSg=8A@np@Kx6x&P|S4 z2;;IaPN%!+;~&Qt+4%^8oDfKp56>rjVUI2pAl!tT|K2N^yYZCBiUZU5@lRR!`9E{~ zg&BV5R&5MmK$a9_QH*R;IAYvAcnzUZ02=8k{^-5dS-w^UL5&I2XrQ%KajdTStd0=O z3Bhzu!beYSe6!pGp^zC0>GFCKgV&pzmLT{_gD=&<|2}L9UwOO_!I1+TDJ2ElcIc;+ zaR)MBNDPK3)=yal*93_PAy`O)1wDM&&uMC&GO!pSm>GiU;P)+mRX4D$M5tzkYPuWS zwy^D9-L(c`f)yqR_Fm!&yx_MUA%Ybm2!>95DOt|80ii+!DyT%TyV|eJO}~K9B?n!U z_>`-1l$I(gA(*g%2~`5;P_^sB=dUC5b3#9*)^YDriwr%DnHDTyLJ6a|@6Mqm_8tg{ zQjkb@(6H#8LyfOLf;Bf-Q%Glprf zO@duHS&H}MLl7+Z!Gf~YWZj98J5i+wWwKC4<0JO3ruD(T0fYuoXrNhTw$_z2)w#n6 zy}Zy%xhL)8;rV`9GQkX(;D-tN#fClVhu#LjMua>8$fL93P%GI z|D0yO7eR{|v}lL=$)et!YkLkL=&*neEyk|-C+*SMcMhRW6zb@7TZF%4dKS$^ut;GBtmMFo((zB_U5i(qy^Sq8C83knjw?jc-1UMQTd7{UNA8StX;`StmX?1kFuXr3J>AEJkP47W!&zjl{^O0uBoK6DK!^4{KC)a`d@E=V!Y?WK zMY-gxh&gxe$Abv591u&lcJzCAxtrlJ1S3%}q6_r<)VS=omkL4{JA~0Vzn*qa@avH$ z2rf+ELcbky^mg?}C9`OR3|`2f5hbhU8Q=FS9wCke;wbfnWvVXe%xFQV6@gmHyZWEm z{mqY0B82ck2<^t`-Cymlx}PJA0fszaNE5ZXiiNum<*!BfBMpCOe3bKS*}9B*H$o-{ zWYU%U=4O8^h}}2Sf*JnMGoM>Wntk@~IgF6c0{JvJcZNLg&R=^Ep->VE>CKY8fnjc% zGDZmDoDfcx6RMI&A73y*2oQw;>fLQMN|U04t}}m13JU2)71TTJZ;pkabga82up!C|kZA%Ex!}AE!d@xN5pHmyn z2J3QeBiQqUJynCoFl{m3Y8!+fobZG0M{4+(_h;o0gb87opgmM0+b^dtTel;8<%O>l zyJ-p=CL?rMzcIjH4E*WJ*`7T8`l(O^;V%#TrDqJ%#YvxUv80ot_i~b&80fbN<2&L;_n^ZLqS+o+t zgBLug+cjUWHlDR>9fF+{*wOg7+{^Q>d)_{T5pEcv&4&<=RQofG?}IVGT^QV{;@sSR z`P1RC%Lr~V;70XhPG_EvTJ$4?OjgLGCm&KAk_Sqy-Xn}k!YCEU09W?bjNcjv&2rF8 z(?P#+GuP?ung|Y(;6Ov|b;9_#ysPodpW=m4y1BB(Z?`Lkr6E{ygC$k9?CXY0_H@)CWQs#3-6)^%fmO3AI}wcJ!H71ThE2r> zvUdwcGC-FPbSY(+kNtG`Tr7uBECR)pkk_=DKn@?I(#@A>W*N|57q?3>1hk@ zmUtkf@<1wu=n5yHLlg6h5b6Nxs0ce+O&_|rvJoLg1XAd9_iqn>b@YvJ6a$+0potzV zU)#E9(P-WZgl-P#rcz}0-`dZyUF#4^WucU2uMIo-7ezmQh!DvHk@U5)Xwyp$%fG)y zXyk!L%05r*G;R&XeL+YDNT$=3w&Wer=T}E)l7=QKkiUy`OD69+Bj|I2KIM`Xzm@hz zg+?Ky2|*g|8AQHYd#%PR8$pW+v}gq>eD84eIsR6JbWupBd(NMEJsO_Rj%I*6Gq}^H z$oj=LBi9X%BlOBbFNIHz{HiPK6W=4au!0Ls?mlGlrWS^NMko@3B08&t63M!Ujj0F~ z!caj8VB{_TvWa6=2v&SxMbTc)l^CQjzYC#B2AU}KDf`X7`l0RW*Qj1j)Tm`|EYHh3k zT+T_J*9gvH;7kc1=!~&O-P{?dKXj?1eC7WH7%P_(>cKAlKzFGEW-{qzFV;L|Z0~6F&i}+NI+{+Y4 zu;K?R8c~1qtTl^%N+68#!6=n&j?ld!5-)Bd^zlI-fw$sE6^__j2(H55N_Q~T{YB>L zlDi1qOwdhh10@@WrtXbT5dwrEfLdt(FuWtFYlbk%0+Y1kyw`UXyWeCY!c%zqZ-3?D zaiOcqCw}9{!MqSm_wVlc`ir)m!w5#~U_>3Fs8o1Ree(oDg&b5+EjYetfBEY2X@mqB zNT7N%61{7p^)>%@23U%NC2dQxtM-4HwQeE8C_9YOQwhJELB)*P6$l1AU_ePpfai4y z8_!;Z0Rb4G96F@P_3g#`3kV)E;6VrfHTUS9qj8TBf&qdl6f%yC2rpXw1fiP+x@mHL z;&3gC?c7%gQ@k)mU9u(rWMy5mA%eCXXwyO_kL9NGS}A9Q@7(a6Vtu}oQKz)CH^L85 z_(6FgS}?koZ*L%i5kDAF@Vsbm^fa1IM9`N4eG2J>#kWp3JEkF2160#>)Y1$|P}GJQ9bOh{iF%o)zpV_e7OD z{Hf-VL8umkY8skT5f5~C_^m~-j<}+0LBLNeI8W;5R+NS+Q{8`iI^# z@KXwY(jeFEiUXnuMz)@* zY2_V4(2@czx>55Jv@0~VIO7?>_^)h>C}CKBSRtwsHy1%y7IZ1)gU*K&msyu0xQl>0 zO;KyyJ6*n+?LgQCyZ(Kx<-ikJmzZw{@#6$RNT3WFe5f_wYxyCBWI0Ht?Q#3N)odxn z=Me09z@Em_=An0w?-BCd*nkix z2yt|QQLYbSRQmTIg!4i;9Yf3GlEH<*y$H5UU`t=ec0F;bOuv2xa@ir5QjE;F(fhHE z8OY{`Y})2;SdjnF@{bDssX-waqzlwn=ll8~TnC{+5*lcBEcjN7rRYOAg0Cp}(z;+G zkU4h8pBjX}67ZMa1`lulqN97J6(N`ng6Rvut26{XcOUCRu;m0>8c($*H+Q9-ADRJi zu%#Tz9W7^(P&_M<(PE4T#%Mw$cVl2O`kDwrBp*c5g8K6b_W(PuiwFrUkU)t~vusbP z{L1SH<03Fl6FXCr>W3=J?jqQTgAE=0DtCfjoTmmt4-@oIeM*-6`FriQ1cWqxNTc38 z9HHYdXW=A58$YxW__7bg&r_Y6X~73+bh_CUiA#mAOC&K`81RDurOH{$Z@;})G#|l- zAAATd_l%wt6M2e|BMUh+tK>KZDF-9oAWX5q6ctCm#%GUn_-zon<)E8tTG2KM-d%Px zU?~Qcl&#hZMDol_cEJ`SGB84;oMY4U@tTvt2;KnR^s?J+pWHohouLS+T#!oHDp6V9 z*yLOcf<6=I(|;J@d5L@Ks#PgMl?+tTF}yZzYt>O`K&TXhN;<28=fC34GxZ=?^MW;v zk1>tS`5lU52pSTgL0fI=HmX;04^1Grh=L2nZk4fj@6CM@$qdM3f=qf&+iyMR%zSTo zgkEXrrBTbq^7oo~l>$N_8w65N&)F5qDQmYF!Iv3)Dak0WOt3n#U>8CsGjviq-qf+% zEb8(BgrD5-lNP%wl1z>!YmXv)hR^?=(`xqAs4m$36hHRi0v|5<|NrW`Pglr^!UA)I zW@c!npF-RlFZT6glm$YB2t-h5(3$dQq{Z#B{2i-^`-AGEefYKoi(jAI~q%^bMDLl<8)PpS5-#)Qnw(Cioz(Bj?S}Oq&oX|BINQzF3nG^4`%6Q zivELOB?DH}<8D1eHE&Dgl^E> z`q4?3O+OKSNy0BGZ)|vX6fU^Pm&yhsVKAck#@c*Il=lNbm=K2vs^8{cEZ>!7CWc@o z1Xff+>HjwS?KGu;P%jVl6mHz1Ln)R@GZCVcAc`itl2neJHH8Zh4Ee#3egf-Sh>`iy z`n?F&5@1d9Z1}_UA~3&)U?u}*)K+yX6O-$k-ywAHLkBg9^LnjIYNu@xMtER^f}!My z?%*SFe}r;gDF2@axXG)AD#aoYszjlRdQfA@d&aM?kqF~lFirty`-7Kn30EURtpL>0 zvgdeM8uw%8L4;OCXr)3zF>fSdN<=t~4LzdJL+6lBca7-0uo@wU1v#`_$O`2-y1i@- zLN)`kDMS|=*8iT7a{%F!1bm`MT+=j7MaZJ8%ls!P z(w!BHU;$u3Yp&%E8omPNpAlN6p_OVx)vHVD->VKH*hzvNB_$QpdGgXT7o@WxK?D*g z5_4BSQ~B^{8G<<Sggjg8jmm$0TX(wsgJ*zIlHH! zSrD2jPaF3fa4uT31&;^?2&D?#aoNkVoLeUlf`uTMV)t^tOx^a8Y3LDx9vbHl*5w#* zi(J4X>=*=p3VZ=6CM2zei|Lf(9xKjJhvAYYlLpek*S1 zrXniyA0JkgUOIw}JlN1)@Cq-9*9M#G5!`sdjhZBWL@^^;hclB6>0*#h9i@3))GN1N z4#AKI3~8vH`u;^Nw|5_cxgeO+w?1t%`THB!Jwb@%g-Du$0~wR=UBq4@*olK3<=xm< zKx&FU5DVM0A94t{uRQgOY&_;Xk$Vf zmCY3;$F+r4@n*3hMi64C(d#6*bbO?R5ZZ;Iow~`|@mK@LD{+Jj24qlD`lK+iY3D}? zgk&*Drj}A2lkGl}vk{>VppJ&7OXz{^4>dL+xCww8)zdC7OlKApTtLv_0Uc`FyAiFC zfe&;MT4kV>zW=wq+afJwLkL2rAav4w1TZ*snlBF_H1I19T`aJW1LRtx&xO z!I~SaDGrl(KfaOEI*bq^0Ua2ihkDWSf-?R@c-@d#hGlLb4v*nsNC z8Xq)`5Nd>=hLYG(w_TMSF;)n=0-#H6+aH)F-Q(to;3fucRG2q9>^Wdj5`a)73`I2f z%~I~~F<%~sFvx&G>hbv;rNV0==Sqp{-9AAcV<57|jG*pPnhT)>wrw#RpS#4#A3eDaV0L2r+UHLr3_1&}^!k zaRVV*7NV)Ge1H714N|#-kSqnz@b#t&0X!x0*p&`5bC zD|Ozv+$Y5d>7tNM3&abz6mwR*o(2m+u%K+Xg;(g_Yu{cx!jls`X;YxLer0RMBHlbU z^eaF=Ev%Xx<=3w9V;9yBst6^*P(mSXTXu8e zQs6X1N>np!6R~6kW0j=NAI}AZW@%`qa>&c#^!O0#5rTsRI8fc% z{-RGtedUYklQW@&Hu5ec-Mh_L_7b6y8yYDqX!Irx#W$KGj0(Ug{RGz4>bVJLPP!os zaKZqsxH|hdLMkt$(s#|= z_vJMhcicg+mIiCOs?WjpLr=4wAo$6F9}VU=_BqBizAq8Nl^~qf5qW7>53Etoo_;F; zYYOU@En<^Z9C-*Ce2_tx%g@8>)~Hm5@J0yUP$8(zv)SXt;TD8Fu;)+C{W*I1Kh4T+ zeA!SE45`jt7NT7t{A2>5ix0Z!4BaA^+c?$v^VyKX3n_Hpy@7|nJ+T);sF#I$+MH@_ zGgEH25k}DE0bQEtF4lkUuGuPu&@Tx6)Uit2dDJ$Zn1fI#1BEm@@m=Y0ycs+fVM+?7 z=rfGb3%nj(>pq51DG!yDVz#Vta$X*D0%1}bCg~TVViJ-n75y|3^!P!K)@X0fM+Uw- zaAW!$(lA9wXf_(pZ5c2}nBap6YLd0@Ta)X1Y!E)k!v`u=UZ45#qj9}2!XPIMQb=e0 z=kcjvjz2=70u<8lZ@dBLjVFQ-x&XQ;>)zGAw`GWtf-t23Q*^`%_xa}=ic=AEbRhec0DeMe4lxFPzJ$D0j%irQ;`v~ z(id7QBIt{QKGlbV_Q$U)ZB;_(WP1+beZ-J2*u)1O!rY_H}kcDk0*j36a1*c|HXZD(XkDm5I%~-M>^sk0k=hR zOU4k=8IVpl$Zrr+$y?1+$OZ=maG*xyJ!dJq@s~J)9SiK}s>VIuX>;6Nh2SazuC&(d z)!SgVFmMOLC<{iZbmN6@Q#-e;vVE5Ugp|EP8eAn~KzPgia=O(gggxA|YU> ztu8_i7v#`3-pm1+n%Yc%ghFX3q^gI@C*C=WHyWXf1zmJ|hL$BehYT|i!dMVSEv57- zzF@aqAwoST)YF)~I2E(ny|4(OS`?~jYvT^zquQDG+Yw5npoHdGff*~m53Q3bVuJ$< z9OxY40sm;;lU5GH2X`qm0G@1VgDIR_U@?^{G@ceUY6^U=8PiIb5P%TVCSOF{kte4lTUpcy5B_CfdmxOZKg=rqw zddo4p6v0CVJZMFCCS$|VsM=oZtq8t~;7c)ezQQ{2Af>gx$IJAjbO2f1|ev^@XMR_hNT^h!Z5Md5o_)rlv2?jh6&Kn-Q}LBDM_ zUgw`7lygBj<&l$d2jA~pV~G$g2+=hDxD`$EX6E@Km;jj2_>;2~eW`ss0HIGB`lwoX z+&B`E8WMs~rv!C$A20aBduxxzB53o0HpTjhky(!?eX|hKc_Ezw^uvsYJ$c znBFSM`tHTQo(>~8Fu;K}@e+Egxp!zvma!q95Avz4Ol3qPA1z#jkRk>t6zlqO8xm9E zwj)eRz$A^Q8?!GI-(Ibb5Gn_uRJDFeX^I%*)I>;=g*58(6|p-{GvPdf1Aqgy)q=at zdT!N*2p;m_L3I*qfo+m}{Q;IB@ABwDLeJCCcnzfmU%dhbBy6`1}w=j59Th(g1zITq%M#vI|EP^WY3-c3BSRt5lf+;PH>y?)E zs&8^aD3FH&D&>tAU%Pm0Lm|SXBur9GJ5ZYv*jkY|e);&z>Tdj}rJq<0b0>nk1h~^MaE;k`*Qiv{D>k#~TzXgK50@zbwZvA@6(}^$B5Ul{w zRF!BvOjkMEV~t0&i$FWY)gj+nw@!6O1VaTdq_;ZEh-fiTibm+;hdx?!oiwd;khq+R z&;rmx>pI=*tL8W_sY7TJfHoSnDIfRoDlM2m2$Y3D+5%f9oGAF^^06v5REt41O%oM2 z5*iafKSOxO4ew}YWwp=5TAQ0j2zv&3jFx>DpS#uf~@S8g7fp}?%fWZTVDq*OiNIdoRh^Dej z9)hkE=u#rnEz0;Yd-it(M+I=C*0nSg4G3B_f?z8Qw)9q8{#8BCG+tc8hGZ#7rngc% z+3@A_n%xMwf{;roWAUWS-;3K{A^hZrpVU#hRVsXsk}VKoWFdyK&y43HckFgMA()GS zIc-~SeBPN-lb?uCCJAMf`gZO}7dvmCg%HOBaWoap9o?g4xy%?r`=9OjzEA}?MM zv066dNkbkjm28CEca})cM6lumE2>KZi(mTja?MB376NTb09QUZo%-Cp7@i@?lPI@)#WjQ$L1>|7uaHf;XHxMmg1!*w)8&>~&0TVQoHv8 zp+O89DB2h9Gk9K5@e09@1%5OMzgz!g+3g=D2-QMRO~v`9&EqF!uUjJgmVw{2xPqim zhGuyHLK6#`Xd$XRL#if?Cjvo-4|J&6y)KA$zkw(OPZ{u}y4`r2&iVU7u?XY5Fiu%? zcfkRfhX>;j4#L4dD}$F@y^kx`q)h*RCXCZ^x+<~kYpHZ8!bdUqNNxMLde*Ss#}CUhX8L%kCrR2)KS%)a9P_E-JC0|@Ws;XT!S^?ucB zp9TI#=;VS<%G0lJ^=L=09YL@Mu&3GM&8`&-7Jph^$A)MTh^GE?cyw8JXm};UxHyc{ z$J zobZ#j1=e1WYg@A?3qe~PwCSyk8>99=+3*#?p8@`qtvc56_Dy=XO#=`3Q>?RU#cbMz zIuLHc%|9Qu%vewreWwQJsW&@!G{L_ z4vjBnGxC)XrW9d{X0+s8{B3Yi1Hps`Oz4{G^|Xw$w9g;}$wClK5vT46{9F`t7QsdW zY-l?DQf74Cg!vL7P#glOK|W44KHYoXAHjnO9<=MBZ#d)q-{0~PT4bPwX8#Drl`WEP zd<|@96@^y%I*00N71`Py0tkA-phsESLrFJFVI32}K>!@6gj&`xm+P>K6hgB&G}Bcv zT~91AsgyOv_M?CqZ(Cv4#k4^58~eymZE*o}grZgf(@I) z2;b!38?8@|ACG^#(0mXfm;u2wY6JL{^Pf~1_~OMB7Bm9PgE4#UAE$aYQz?VW-(}{DdkM$x8(iIqX=ny zkVb1Rha<86Dyr8JO8B9KI%>#6rDxHrX~+?P913X;^*4KBmi~)JR0=~S4T9gNID)2@ z+9H^-z>KCX*V`&r$}6J~!Wj@wP2w^f`eOgG&j?1MU_{@#$%~irZb>Uf$W($%dNkE- zJxj&rMk&G+FHF%S)Z(O4LLfH;(yo%*_|Dznci3gy9q2;A4&hhy1K{5FEt7f$F67F9b*I1xyfZSzt?dE^z9{ z-|4N^2n7r%pgT7W@tJtc$U$(I2X~6y8MbE}JWR?E28Cdd2IuIeCNHhA-aH)WC){h?O7pRGsmV}Ku>T9mgD7KAXS0AuugXs>Ko|Jgq7RyKt5LO9I@e9K~w zGEVP87-Pa1l?6HGZJQcL_9FZgfSUqO17a{h=Ll8PZ{ORiJ$(*k2&5gK za^;*)nL<_weJtpsoVad%uWvk9BN(v2fMVAo;^^S^%m{=aDF~t@16umZX>*bh97Mr^ zBC%F$7c*^M0m3Ob^{0?%6B`@3{kjETE|P&F>ZW?2YYA(eJ%L-v||vQ}J%;KT_|w6k(%!zF5eE2Sfb!eP zgvfbuCjJOgMx7*$mzJ=hy z4IZ>QReE9{YUp8&5GM(7l=7Q?-CLtE5`fSN&`E1%nVyCyrSfEiDJ7VqP%xP3qm>nv zg`f|hPvzS}P$>YF zG???mIMeSc=pfVyK^?u7#fDoJt7iI4zm+`LQAX_W&|I?7ItD>U8g%H_z}g=F(q}zN zL+F)d`~P&`3=#41Is_{zu%gR-D4A3+!F#2H4VFx>q&kM9 z;{XqT+cf8fXBWxI8Lwn%=s7p3IyqkiMBMLdRi1|14%2TyM-k)r! z1gNAwue`U@>fxvmf~68zQlH0u=t^-rE`iV_15H$*Mg|tS&99V4un`9vs>fOtT#xC5 z&P8yO0XJH_-PQl(Tb;EK!H5ft=yz!rjx3El6ZrrkPZIJdvp=}-OyExbe+bzC*>t%F zAHkSqwv|5Nkzu|KxC^aetoEcDT0Y=3l>{&%}+&{hO(TE^tI zNe6`a8RHRc!q7%T?V7@|n%lir2>H^GPrDw9GH*6H+;T$b=7nzhVbT8eW8U|d`60ZO zhPTut+84*g)*kzS;HnI+%8LL0O^-(d1D_7RPD2P~KqyV~D%;nW?cn~3V9O1*l$J*M z?`%6NP=-(}0>#vW98)^oIj?&V^28yJ;>y^0w~3t(vx^ON0#HZ8xi$R9wT9oj5cH%# zk4BWEn`ptJN2d|a!MQ(c54G&qWBiw|bZ7>A?b?%()1TT;NFGZ{5l5wQ%L~ z^$4EQ;7O0CwrV{aUZ?yTAy^rLY4*=^Sj96-)CWPEAGGOHM+dK6O|~_NL>Lx3PLaSpx1e6MMLg62qWAuLK{IfwLF)K z%Jv|vfi-^~@L$Y=8ywp;@nvsb@TMyCRBZpm{Lp6zDRPiPDd}t!M_J~776?^*P({V& z5zT|fRa({v+47K0vrVe8mx0IEX~-0ZOxjSs|8-sOCiMh7;*%15qD4&V;b*Elc9kMH zFu{RZ>JoSG$d8N;gh+r$%DL9LHn~NCqQBTsECa<^j+dI3DGXOKHNx08=tbJLckB|F^lr3hC1U`2(ULdKrZ3#;xT?1%k-GEcMV>Cjk9 zQ+zo<3IgcVMHT6rPyL#PM1Dx5H#(K?w&o0{4Ia^`1dSBwu{+=Fd2zxGp+y*4XlyJm z$;jw_Ie-u^5AhTu!;FV>dvA{;^hiSwJ+24#&#(CU3iPp|nF-Cb8uAfa0>|4C?3BTdW+%=i zjI+=0a`v;~yC{68y|g`5U%j*%RS}YeA&H93^jYrPV@r1T^+bO}QjHR8hB@?&yIml2}mAc`_cY)n$JyL>1@5?BP6(LXn0%>S=99p{ZKh=B$7ZGrwWPBsbi`RMS5JIFlMAE#xLulKtfP`@bdl9gw zBc2DUaGSYIAQVVK0nM6nJnP>s?GhVggDDG4sZKiT4Y`NktU#z2gL;|+tz6EpU!%JX zVNe_f>EsS`c^AIpIe^e72z`{LZ~HF}uX(JF5G@4J6r$H&v@N$)K7}wO4ny=-_rslc zo1M`_uoeMpx{ou}VrCUc6K zywBn|E{hi-yyt@Vl;6(WbK*RH{~JQD9Q4xuo6_npcO0U-5QddtmvN5F1(*pp|BS?!^BDjYfG9Vwey^e^6~EBSxTU>o$b9GVqpe@aK_5 z*Prt2L-11uKbp(u>kH+cD>{vk$p@J5^59Ktv{NEG_gyOS zM+i`a0NP9I&@0GdEZhE@4LaPQL+7|u`fib)?hb@B2}q;ull8AoT+V*rh!D#Uu{3Pj zHeAqow;>cEQ3MhxMqX@em5DQnLkO0GU>bqp^KH(KI_4wv$wME7!hxBEmmc{wB9sU~ z36-;qFx4ABga#0X`CypZc3)~jVdgiEVK%rjz?GUr<#6hLwdcYJJ(AEv1MS|~ZC7&_ zEu21r2V7}C`~C{;;dQr;}}E+xKITf)Bh+&qgAt_b1Ohz^^=57s}sgwQGkt+Zyo z-?!+{+msIo*-DU26~@k1^UVtyBN6PSz@8>Mqk~*sy|+^l`naHv9)Gol*;>^PD9qAI?r(EdUAa|ACL z@S=g)XeDuLn^P`AJU7HsIh(xr_4t$jiV%z?!I-Y8_t(L<>i#_lvC@HgudVM zz@pXrrb7WjtvuAyAh=N^vT?Iy1;P|3Owod*KydH3s1M%}JVd~Qnq*mx+QY(mKM>rc z!Hw1(wmu1Ysmq1N*kBG|PKDry)t@q*u1+-XUH?|C@ThB6wn$AUdKRG$e! z=mY4ZN_X@GQ~s<|B*Gg(ctd+oky;L+3d;)+QY9dj5?|iS4$q>)^$2?0phv;*o@;iP z|3RT~HpGZS42{5hIqIB^KhzK=1z?iyyyd&)CXY{>5c1_ApZa{hJM-w!(Y*+Tl2Az5 zDr4CBCgblX2({8sOJBjVGtyXSHq#uTTpY^jD5V$)ir-hKu3HkJZrYMYg z(RsHILIWQ((8MLx%Ut_oS1dxZA|%sz(y#jEt)G~VU?>8HG|HQe&kMcd&p_~30Dt<- z*!%;<>9;?1Ab9eEC;i;FO_|ccj(@umiiM$=E;mPBd`_>T>=YY(rNNgHhDD0h&!JCi z5XNO;oc{hm9S8aNxdMaqs2nWai0hB(D-2eap literal 0 HcmV?d00001 diff --git a/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_hrpwm.h.5207EFB2BD1D4354.idx b/gpio_driverlib_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/hw_hrpwm.h.5207EFB2BD1D4354.idx new file mode 100644 index 0000000000000000000000000000000000000000..9294bb95fc5381f5a898b03d336aff1d93798b62 GIT binary patch literal 14692 zcmYM*2Uw5Y|2XjO&;9w__d7FtJP)!ZvxFY9S01ZmMMg?iR#HTXCecpOUT6_%PqZfw zl{96xk#_l?^Zoza@2;!Mb-iDodz^FL=Y7t7f1<9sZrwg*DXG;us>b@d=MRacq@;$C zUxV}Kj_o7=9wfiUo`*N&=BYk=T~cB+YerV~rY*Cw^9tpQ=Vrgzx=>->ydopcvBq}o z!|&^keCIfsKp%CNJ#LyV&K`k2M|2LI-0yg8ij&8kFdwz?K5815MyHQByA()Su5=8qUy^8T5*V+ZkwQgwOkL z(ouhJy-q?;B!*=1-+zu6)6w}-s@|7^3kNQoaH5%h_KBUDRP9lC3>vLAs? z4m!DMe~wU^d~Bm^|IZY<8R*7#oZVt{B-eIGe**Rl*fV4P95KjwieviPhZOuo;3pEg z@ap%e*N2?_OyQ#lK8l1RN=sfvCwyocNT8X6W={6csr03Xi>J4S4IX%a}22z^zic&;O~HJri@*fHYI72;+-{CK9LmxgOO zsKpG4jEoqdGaqCKtbi55=Ra)x#90kKO~W2y@W52F8>zQy@8C=dR~fj<2p7I_TH|I^ z^}rzndKu`&4xIYc>AZc3D}`JJauM8IJ~-+8TRoJ3y#(yB)pPqD4sT6qq0q)a8y?}} zl`_OXZ`3dX?ILIwjsDZT;v#-ht?Fh9W?&}V({=l!N}}CoX}Ft%ZcdnzU7dHfJ#=@c z5Ga8_ymVisPR_iEUKA=AsK5^Yknu#PMJ1R*A_Ixc_&=9!c#~(WIl6c_fe;o#*s*`$ z=Q6KR@*7JjM2R5^yU=!gZNz7O><9w39N2Qg?Y6-C#?8gW6yEXh4lBrVb(e*g3kHm& z*APPpo~rM?&0h};^C?*JV95)KV{>JBGb8pIMNcJxcbFel3(j}R8pcwv7J;=$n6K+u z?ap})$43)*DuJgGVZNr{&_9`FYfhnng94nd6Wv|j{e54341ruRQ0Npvr%1@#*$d51Jf7V`p->EkVxdaK z+}t?tM3?Gh0!b_+u|j$(-CpT^o!d{Lj)yu-&zPNVHF_(LP;lnJ88bwDV^mif*GJ(d z2RAw4;uGI)9=jw&cM5@S5p-jHe(oPwoZ#b2A)0|`91Tt_)$E1i_-O>H7^uQdZ0v9f zjJ9}5;R6F75UOJ*MVQCg&mi!Xg|9eJEfd={mMT1_5H5yrY`NXW&x@a&86`(x6KoQe z-Pf0#YBLW`rePNbTyQiRS6}D#KBiCz;UNUq%5dYcWpgJCn@PZp2R9tp8`pkp>L+`f z!baFATp>))n;8%vLc`fCWMd7vYyIhgPvj7J0?rIL&&CVk5N(8TP8rRfK z`Z+%65``}!_#zUvCo}lVxxE>V6qC8P_at!rQpJY z3$`NQq{>cH$2bb1A_&EmPu4L)JI+#J4uPi}JjL|v{OiJyebatY*af?URVMe|18N1CR;ZQMzV*U7*bkC&g_r>`H3OOjm zHWbfk8#+hBn}RO`zL*^chGd_!UeH6~Ee~(8JEpu`uP=R4S%JWDI4*RCgGWvEi!yf_ zE?}SlPjvW%hCi1{I3+g^6(Ww>hxHf zDVs(tARrI&L;sYn;;xXT-D>k__!SGUFgxNhs`Yh;FQV{W4Bv5Il=Zs*mU-VYDSTq! z6K*Vhd$#6Pe`}%OA_5njcj<2)PMhvCM2UbBC z+F$uT;#PHD&@uu!EaYGUd<%0jt}QL3@DKbW+|doqg74py2Q4SzL=F-;;Y2N-H6vzQ z@1*d6g9rFHa5PWdLM_{a!VMN~utL?i9UxkE?oc&_9uf3l!VGS)jk#GWwSqu61L3$W zK4q=GY53Hu6l}y`gGo>%KIZ8+%Y}k32flb$HU1-S7EiQVNuY&;7F;-MWzOGDOKG6+ zhKDyeq)Cr6zf^u+y^6p?79L`U^hIy)Tb-Lu!BGN^I2M*OrDYagE75bcf2T4iH3W4=)p^WlY4&kO+Yb)Xbz$=m1WajMD!+qp%BAC3^uPL zq4tHIg4`MccNnBWV zfy;1NSh0_;&zUlBW;qR)a8QEluhB=nxz*UJ3L{gk?D> zKD)?3y^}(@2+Bpmez^kXJCBx@T2G)s3=KGkEFbE9=sVwU1A)D;S11rlaD9D|zbOr; zNFW8bpT|L>vu&jn1%D3waYryXX+yipgd7S#dH9KoP4M>4`I~!cR0$k_1HvqQU$IVW z{Z8qPB%I1ZD(+I!(`>^-rTSC&kA?p*Hxw$h-UXa!r(nT=1tXm5acP-fR^Q@(3Ah5d zg3#*27XF{S?j51v#(^7-^_h~k-#T0FQK;ad0&n)k@w>az?XxKaG7yN{7o|08<@l7t zn+W_ThX1ew%dH|!Q(cZx@a4f5_px{V%f6O(-=mNyfkcULyK?*lL-FQl3btaf#R+z% z_O+qU0JY5ok{L+Gi!YDa)Mf1uM&YvvKI3|Qr7`R0VCirQ-Yj_Iv|nh`W*KO0w}pTk zfE#v6z$5YP%ci*$DkM;W1AFbVtK~D9P6|(1c#7R_q~$eozDmkg0yP}e;FIU!l$Uz# z$5w13pbW}Fa<-=aN}qY6mxdcTXvAu;Fu*T%;`9tP0#z(j;fR|~+Geb)*i50Eg>nSh z$w&A>LvE=PNEAUL7B5E=&!N7HA5ds!pqUZM-FFY^hE1(f+X*zX(1@*gs2=)lq3bXT zzs2wyJKb1p<2l$;or13fe6ixBy1lg>x9$=JXAwB##eHAuS?V3PrO?Jg8!J?2*^W-l znREImJd(g8iBOCx!%rA!uQ1mj@JkH8aGhWNYRw(J6sa8q5?DyUmd}=7BxzkVhQfOh zyvK>mY^$sE{54}If!hq+#rS&wxLUxaHmYf2S=u zNg-SW;Ub|6^=BWL=0D$(LLm!<*g(&#cVc2Qswnh`p$F&ea@)fCTP}wV5xC95ZB}?8 z>)%=OcUUo-+ zgK=3DEC4L9Zx3u<<~BOE&#=M(+eY0>BFgHD=&H zH^6;KgA|2WEDQ|o;?4ey8jLNE0`@im#0`rtGP_b||d32?sJ#Z@tE z%ozgD7$zJ`<{W__4ubG0=GU8n>)(l98xTn1 zAqk5LBu;(T^nKBJ0#O`9VYWv46}CS)u!=%52g!JiYnu~Z7%TKquo8h4?#)|WIuy=X z*BKJ1W}q6=M&IF@!B@L$7YJDJV1ch<7w9Y-QJi?mh(Lr0BCv4%t@7Yn*p?y+2^=Kg z#SOGIr#;Q>q!7YE2q!!-$Y}V^Hu_LvOuz}i3H!=u^MGNaTgxb1lfX61St*^;!j<;t$9i9CoU7n z=OG^p>X;|#&v#yyxV$ME4}-@Tu8l|X?63UFo3*u{lCGT%$#jTqiwJxD)Xso*Kw zO~Dz!8ArTIVNzAOJD3yj6N4Yt%@cvj=VTftQb?6RDz>Ans;8!9$QxB98rl5n#Knz3Z3Mfs>nlq@I|^H7XS;fk9h zvMm)$DO_XV8g6CYukf5+_#om20dEO-W6pMs9j&u0sEEQrI4ESGvdRe~&C?|`Y{P;L zD?F{A&X%lO+i&Vk0={DK#gQ{Nb9O#xZ9^f2g%q4%i~brDB$4MNKQwaCNCfgA(00ZIC<3Vc1>tjoo((o-7ZsCq- zQv8Y{)#d9bq_L2O_hf7`&m(_~IfZqwPFRIc$ww9?sjA*0;aUc2@y+8**$I)eo3~TQ zXCWVJLDG`6Oq;f|6v|jA!z<|Z8?EFvm%B~inHZkooX~rx7Zg@9jzS>=g;;_=rti#I zGgXh$B2(Z_y4?eWd(&221;i!Smt#^+k54rr5y-Za$t!$ zZnI?WplwMqjszkl5Q+P8wY(D9=~tIf&;l)Cw97XRl)j&Tl!o`f9w9MvR@$5WUYe z1#>Z&<1Q^=wRu->r_4P9_c^$aD|f5Yi3WSI7KJPpvM~Kaw3n^4)fRga=#oGePGRMd z$+LDmT|^ox;tgJ099 z_>d!lIS9s0*`<9ePVI84^Ce)1ynvORiEMZ0T<9)%V$ zwBVYdKWj!=SK(UWhueC&_%OgA6q zs7IlKg$f+n#x$CKlFzOsz+o zD!4{a=;NUek65`!CcAT*UI+nyG5F)k

    • FisRHSH=k&j3*FJAv8!SUjz+O$`?a}l=4zx08)N#(#&PgUo>s*r${;IF%}qai7dU$ zl%*Tl-?s1=08+m5=nH@5etiBh3=DaLom5j<%2xs@UnM+HrF=C+nUt@AD3kKF0OeA? z4x&uT*F%&^`38tGDK8VKNy;}ugOu`eXpmA~0S!{hH$j7x^3Bj7rF;u8C{n%^8l;rJ zBMd;wo4xr{_Qc3%j)Trqq#Sl03z8ioNOqcnq_O>73y%jN<%64C>Av`0i|U{rMaoG% zCMo|^mGZM9^C?pP8337-e-1z<<>vs%r2ISpnUr4uAd~Wo0Ay1B1pt|pe+fV)}{GP_g9YW)gc&gSjxXIA3dmX$4DhYZO zA7DIrC9kB5H!|%yeMOzVp>Frl`GaS^4?_UHv+fY6ch|%o{PlaguYkep_dm?^`Rvi0 zlAAwa`Cz8K0_VGcXnjtq-WDFF!7Nu{xL6o zEq*@Y%|Eb9X5hKg zw(7a>V?sdT!Gnb#WXmeyMxo&b-NuT14U11dJ~|wV7yUU1wp)4a=;n|<3$ot@718Zh z3@>O!%!z^A3GoW1;e^v?FmEr|{;%$?8g(v}KbQ{64nBsRh>uOrkIQD8a9Qn+(T+HG zCJM1xd>vy3e01hS|C2q=IkLLspw@Bkm^6K4c6E zCEm0a-lQakBPW5{2q-Hh5pRWtp|%1_#84dqwG)uRO>F|U7hpoH8-)<4gMi}W6HzS! zJtv^-=SPo0!366lu#|)>6hxp-0*Z~xKs5;zBcRN*1XPVsA1ffz4%~6%xHti3<+<^` zDHw_uP)d4Ac0ycd)PleXoLomrVgzy#C{aM9#3=ME0h0h2jhYj%GXPtnW&}(IU@O#w zL{bU>TcgJ0$SweEgBlUAD*)S~FcQV790Z~C+{9-8c(mDwfH<}MJN_x8ql;A%)jB>zan0c;a?rc z2<{3(PsyS3%;*towoLm1eyx0PO*T{#*+w?lyKD#kHb_*L^k9x?c=ouAp~e`<6_}e~ zbO_`LEHSfi^k`!cbeCXW;i%!pFz6w`xQu}VjbYGJV43*4uIMo6B_M+_IuLpTFcQ@u zq0Zxp>8S3I@H|eqv6BwYO#L|B{dqA4-64(v zoLPic%5tkNy%qS--<1Z+4PL{_?ToiP#e41N<8Rh6Bnb0<&ViBeeEh{u1U53&dEp4Q zMF<;BSr>%O;3&`^dwvmsI4P4*`+_$aY@tj~m=H7oS`rq*VxNwH|z2W&M0#`gg0YK*Y zN#0b@?~CqEuiB;V%(b9pmHM5ujJbY>hyJI$Jl^kTxtI9sg|TO>-#aGldUx8L7}IXe zbC~NXNfEJbwrw%)^A;ALlmyhEE)LUh3oqX%VaO;{pA7E^iFF?{0M#Q{q{Pxj56UeZ zhQbIOC17xkvgQ3NKcs%vXC`o$UZaqXV69=Ewqkcf{2Z-CVeA^k(Z<64!o|z9T2_7B zFH5`p59W`czAUZc;^WiU{`A;cvJ^F|bAEbGnxP&67T#^_8mt--zCegFd9NzbxR*x1 zY$!`L2`0p5$L7Zw0{@g~y$^+B4Uw-d;q312Zduue%-4``{IF3e!^dO}A7E&GO~q0) ze9Wk#VTRlXNj!E`KlBWtKUiXEg`He#)@; zBovM*%nvtuFH<3(z!4~rc+$-TN1`SKc8fL{g)qOf1Ps#CGQax)S6+V93pC8h(-RIW z+A!vLu5dh0lx8>{>gaCaJ_5%hyIvbywC8v(DBt9`9HhONGQo|9-|Q5>7sODubwdnBIj8*_UJ zyI&lWIGj!I6?7cF(4e!LSP5nmusRtyaT3g-L+mMn#!Hk9-D(6*kT6b?skjaFA|X-2 z>CcbF(QM?ABncDWn0|B?q=GKmz5A*)e(PR%HK%qFrI5vD7tuvsMQOZ?QZ2kU5PA~{ z{pkL0n_kcUFY-CqMf30hEMuo-v3puLr8dAR6=xeNAPq$gES*vbd0L`rL|3SWG*Un! zEL1@n3lQX>x&Bk$PaE=HbI=|&2a)zLcb^gNHWP*M9Ms&xJp*!iX6xnnfMaJ4fZ~Is zTt=#LIYY|jOi_W9%UKc=ayeUKs$9M)VBl<{Pc!bVX?xiPTBA5iTf>~4C!C!x3ggZ$ zuyDVCTn_o_`K7m<*S3P<6}gO5<#LcoE(gOXjX+c`hd`9cg$l9G&uv9R4H9N#WV<0)x}h5HB`@3!OMwr(eOj{)T?a!JaU za*4lnht3n2T)t=Wkjdq46U^jtk7yH+%e?{yj#pXqZrzp}|F(gKnH(2#xnDT`fhdhT ze!#+g1ag_#-)~iJ;Qlv2`HEad0=ZnI$mL?`o+6i}5*2c}L}IF3E|st%mv1SkkjrHf zlydpD1QoelE>Tr3S4dcu%asyV<#LsT6}en3NCjP#-g<#2G4abE0flN8sdBkabkTZI z8tWRd~*SmA0*{6QkBaIid?=bYEb2JqC}-!PEtT2my-nua!{OQ zQ%qEWYZYjZnu8R%d`-AJO%%p+(CZfN8Ia2zXE%l8eedAc3@LIMrOM@1DVNto1yU}r zOH9b+j}lYm@+ScUXGd!{SG4`|=79flmbQlFou7rXw?tvw*cJF7V* zD3EY}Qxfj)FeybKdVO+7q9Wnmm6)1v|B$efaPKLoNVxx#piH=bN>E9-_a&+(+`lBO zCfo-SRuk^u5>^uKKVlexE~@E&%0J`mxlaLwY8R;q_mLQsk40&`i#!(I8zA9cfB*1< zyT=RQ15zd7MyUz+3nk%xDQZv??pG3(3HNIS6bbi|06`AgJ9~=v&DJB%LVx=re!WE7 z!-nE_!rjZFFvDG^<9iGD451h06?5FefoolVdzFLYgGPue=BSJ~`S9Qnc9-1!p?7aT zlD$Uez4X5AVTr|$88ys!)OJLIG*iVIj~b4e;5g%H!!ZdPGmBtyA^x#MQ<9>x(u`~F z;}DHCuDL&fXuNUJeFCBhvBqWhNfR80pQ_;cPD$7Z$*SZz>uHJNR^*HrU|e6HkuW(J z=T>rG{!`Hfpg-?-i#s%;-oY(^a792V;jBMD7yWro6vq4WyoGli_`<5QE1&(jR@q1k zD4u>{6}`O1PbK&r>8bRNG`>9>NLu?ER}+FpV3gk7nZ{LvJtwC(^Iqp5cyw1QDLVI7 zzaHyA#p2N&E|gzH&)_$lXYz848_u;Ivv}iySlnDas>P%FQ}%;`gT-Y@CVs@wT{v|g zKL{pwINi?=ia<`%XMah@xFr(RA(jWiVgy`Ca(bv6Ftrv#{6bm6Ztv*;6?EszsLPUXfEzh_FU!Co}E#BBKIByWd|?72aq1e z&rapD#FY;4oMDx4ATPt6K%YO3J2nkJK24FCYLf%6 zRtq;&XR~NO#_$j)$$E>5MH-^BRmGwV#d$|ygi>COAv@cIjpO+V8R?0}!|v_E$e48C zT6X}DF}afy0KU`Z!h>7!zI%7TfTrJQrZ$8p$oF`z*v$(w*bH;*;lv^Ig_nq&4J9o$ zMZ|5p3)rmjH9mlrp4d4H4Y1f9AzBsk8Q%a$7MG*8#@AZ-5;QT3d@Z`w<*1|aXXXZu zS4I$v-Q}pO@#PEDf>$RIgP+Uc)c6V@YQU+U7y@06P>qWMHDo8^XHwWw-Q@_=?)7N( z{IC1ked%j3is4|Fqn_4NyLd5e|MXMz1QKH8ggP!qeT_#WJt307VJ=4l&A&&>8>L^R z{ye4sEs_q%kNH%)3C9b_SOEc-}5;b6C#axhe>RmfvwHusf5gy1fPZRXQ7`) zdLqW9*yz%DGNVOOqfz8?Y;6IHY(>smiSck)WD3$wfc0&d1j0H2$bivC@(kVQWW?KTk785&mKe+_~7$ zNh|oh%Bwy1hU{ghksI&CxEdQ{G=3kM8<{8Tu`yQTH+Z;_c~XvzaTVCKE!Y~b z@q1z1%01bRtqB^xi>p|vC%dpUQRBBd4Nqun@5P2BvnOPFOguS+jh!_d6IcP1X241j7@Y zsq_Y4VMAIaPjWJ8pZtK0=^`W%Y9@8^cJ$Er=RQim&=f;rjZGBK_jL6M`dJ=+^g#U} zpRR|G03iq_x=T_#Nxx#AJcmu_=|Zr%LdmjH@b}zh8)`XEps8`O@m&p>oG-xa?x+@- zMK2JDySwp#v_v3@-BXPVwS@w5;|njk-fNM7NYaW#fn;&SVgRxWsZuV3V0OX<1UM^Z zC)8OsJ9&%i=`vmrpPjtT83WT#+nSQqF9*Ld9+WJmpGIaDL|%3nH(BKL^Lycgu(0Xp z55mHx5#)m73IN$O;wo<`n0|5*01XqpLkJx`gw!YUpCMVh_&qO&IgA5w1WbLOW(B*g#j!V@3ho; z@agcAgMoL>-f9boZ<@Dum@j+Rj+mCc*U^sZ+!KT*NcY;IA6JcEo@u(PGl>_@m#Jaz z&N1)sbbx%{qjp}jR(0-zKuykF6b8_B-M`zjX4TSVJ)v{Gl=_)(UkTs7Hu+XtyQFhB z5F$-yUAJ}Yxhk(Ve;VFV2%5^v7OT*(b32%GNvW}&4fl46_Nwl^D^QbryMzJsU5}lY z?VEDD?S$@$zT?ZyaNq3_{_QpSS4Z2Yb5}rUc6cr=xkmFE+d$zmH1T&o8>12Xcbxf$ zF~hx2M0-{DP6*WG-brBq?rnYVq1VM%&YP}xg?pq0tozOg_dc!U-dUY{g3!mZ`x1u- zC6A2w%nQ1A0v`}hRs{1kq}aQ4*t^UecLJFf)7V@un(LF07Hb&DS5aykq#-^vHo~xw zFK5@vq{T==`0K&^w2csrM0iViKdoG#lqUS5rSW~8T7@uxARiePxawBds=>e$rxE0a zCyb>nf~Bn{mTGJ7=$sJ1Qt9GJAw5>V(G`>(#92~fe7c#X8KSi&mS#$WiKSW6qOdd@ zqKu_C1!`hxjxYe0w82xWOg+&EK6Di@S?C|v;jMM*lGE3@6 zS!`yhRJ7K_(h_Mfv9wfL6qeqCC}U}vKus*YEewFA_cBIrF8=NK)4&tKk}~2}3YJz? zVrjL`2|?&O5(%^F_n~tmxI{Ei3}#+ z6ai)>xU;*bq{h;(V({%E@PtHs=@Co5YR}KNt3U}`m>2x&ly52r?FsH!GOEdU-1(*n zlpKmLT>T9^9pKS?r+wcHjw6&M{hXUx`q`CNYJCVe3?=U)7=9X~(bsKE6{`4V!A-Pl z`DSybz|QR%uf+MyI(mN;C^oo1EjA?~F)Lntb+Yewj<|R{pTv2?&-XHKqdk>j)K#&; zI+)#^c=g@F7NetI26Y&-yJS`eYyDN;`fITDb$qY$hJqKV@Aa><>cSW2P50Rb$<{}5 zHSxXSNXT&c#z+IWyt=!=V6ek9z-(D@cos0aNF#`Z@jSx zkq16Z?|=P6YyPP8Mh4&}xX|z*3%^LfHq`UItFZsali9z=Ver~SjW3^Wb1~Wn?gkY~ zUzO18w&0#H(D|oW$R^QZ1HZCTQ4I-TxD!) z!z~{qJc@^F+MGRQn;92Y3wr|=zhKDOFz$1Q_}VPobFlBjKjW?kt{AX=Ul=Y-T;2r@ zq(ygw1IfqYBS(@$Y!ToMhLW$q!R*BzzGQEHh0iOX8e?Le%&K8N_zNEbOg_}{4Ycs) zg7-=9yLP_w#?a$CLE%BX7|iV{65bg@Oout@9xZdXJ_~9&d#b4 z6{qwlS45BU9u%3}=N@ot#Kp6NyRIjd$MzC>I0scFXHV#C$h0S_IC{ciOZ|s;8E(AX zVFYPJ+7blpt8rCb$sg~MzkE~;4~l9S?}2#IOsmvO7~Fa6>^Df&v0G4n-3zrm0X4Q9 znO61Sa%5U{jIMi?MgbgN_h}LncnV zieQrHLG=xzj89=Qzva@CyMLS9pI{Of2L)2nnG4HFF!4Zu}wQLbkj#;QeWx0qJJ=z?aL5$2|MtjV&~^3W#zR_%Pr*Bm*K~j9TaZP9uZ?otNY!`Qfmc-39Q3p{g-NNY09|@g zYIXrbKH3h9Mfc2QckxTvfmaDX8S8*ilhG-S)lu3Gj3Z@u9hzU(4vbfP-n&?bmLtv% zOdw@ka+J3N6A8Z>GB9H2F=qi^i}^`; z?Et;Jv`n>>FiZObj11|LU=B6Q__2>TRg8SItfKl^Sx5yE0boJ#SjvE9t7OC}23cTs z9Gv%P-L6}siFlRy0@Ed)n77OdemVD=75%8Nn0w>RN`BOqLU8^}rAM0j`;az@fj~J< zv#NlgfqWa!CfYcCD(|F2gtRSeN7zBbdm&W~BdtmcqB3>~NpnEiH zDF|v8f#4qh6sfIYtb@D&rW3`c4b)2EOz zUC7ilOZX84!?@>_1+tHL?4WupE68d5 zd=kj&sVqU}Cy-t{s9wqvWPU#AvxDlPEJ22YJT_AVPav{_42N;v_!4&TYf6R#H8wQ_ zzoBF}6!XUW?cleHEZ_%fgdO~D_LjE~MlQOY85HLq%s&QCW*ZycuQ=+x?LjfEL(!6U z@YJtuCPnw^;olW(pV68hbXK*4-`BgkdeT$l`z!!rcBj^?t!j4ghm0$kFGh~*wuTqw z=f~CU;Ey${{`>R4&7Y_bRC!byZwF7md-?8TapR)v39785h8;Zf^_HZ_wHrt700vwf zhnnxUgJ)MiIovyEXy7mqb35__+nRRpTu!geU(C(j)rAYpL9S&7)!SLY!uB~_h}w2g zy`9C2a^UZ=gBKJyg|LkV$7tU8d+nh5-h&E~a-o~O@%Pz5^|i-q;C)ob4qo~;W73ur zXFuHlW%Kem5Vjq>eC7N7c~{RbX$n+PZCyL~%lU79dw;<3gpRxd-kXVb@QR}X(N=vs zc$F08J>1X^{^~5sEv>N~yhe)hUTUEYQp)MN=&byVV-d2D0sbyDTbX8o$F2n8jEiN?}?jI7P$H@KEgHLS`ZqVXPm>#KA zd88OwB_6%y2YsjyPNU+~C_dB|^)`$Z8jS08#yxiR^JA{9h}EP4w!AK^tI)`CqR|1x zcA}9>h!TxFMRcH%k3<(59g$AL$sD)K1#R*3$%I$C&(kWPk*zenc>wxxaEg2?I`DneFi8xJBFEh!lBp;oB3VT?DF z-*~ZCY~RUElj&wpnb)8I^BXL{pfIg-N_tXOn>4Y)i10*&HbBf4aJfVD*rAPHBehIw z%++ayBDjD}NfCBvllQv;w};f&W)6)KrNPre)B%L8gx*!ZAkIFa)A)N^ZM+qv&K^Y+ z&VCYnCrh9A;LZ3Mshf6GB;drp2?e<9$!!WDFPR$Q{k+nzvoorYet{>zonu{?O!HIH z#j-H;v~uFe?V6UGZLr<-Q2!!4{>ucu#~#wp@dR4uwXa*42M(6~O25V<={$*HFr**j z5%kQC`5?3rV87At@dSWezb;b;zEOaqALNmHh<--Zuki?}6Hq6MarKit$mKefV7$RD zo#Zb?PRY;)=4nOp1T?4w0)AjQmj1JSVr0W+v7(LN|PUGeEBOZ(nIe;Zy zzvIE^^;viE^7A8Kd(|x~ye%9%}hY+H4-$NDA;l5u)qRV}&tuMpqsRiEr^U9?^mv2yl2wbK2 ze+ev+8Hql86!qb?L!%J^0?V;}UjFsJ3U^g-8K zpCPTpF>`WQOKuV|l_#8-Jc+_PG0~YO+45OpqB2d&V_5Fcp2nZMFzJtU!zk3!Hvb@M zZTHSohY)G2Fk31rt+bP85s-n@PVNp3Lfr`<^KbV5t>L`oS)_?#0ntV>*$K!Ll-vo( zR6>-1OjAUMk-UXO7a-G-P5{X}va?Q3^1%WkZLxqT3y~ppq0lThAhS_-a!OSHz{NGk zt>I6TCV19S#2j3AVe6~}$A`k<$kthP`N?ZY?XE;X5!@pRsm&FlO{Z1&oiTggdWbYd zw9!q;?mdCs`?Xt}Z%}ZeP1~&v#$|q9|5wsPG1{oT!_Z04g$o`Gox(ogeWSHe$KzyK zS}-8feCx!Hk4aN%S;`!-&<6JbL#I)fGgO!O&{-7QFdj41*!^J7=A<{C?68zH5ceb$ zz@EthR}TjlN%_vNxZ9DiHesjYA@yi(M4nbg9omwk_wQT$^3iNh>;TeM6@K(CXBEGN^RNbN%! zioGBKg!>tpEP%g|O#`~OT6hD5laU2mECD}Q8fWTARWZ09~_eMO~59-#(`LGD`CoPFc(!{;OG zQ!O8+%}ZC=SZUY9rCsGvQ!grF82hw#t+x%I{o<9&b4m5F`(^d%nJIEJlMOx@R}`A< z3Gf|G_~=f{6x*6}bSwa8!M7{0_~zzZ7Yjc7fW@~s=ebz*I4j6@Ki^T#1C1dl#+H6- zgsgPC44(Qy#S(G-i5`{l1Ayuw(ZXyjq0nO0n6QPrLrXjejA88eC|mfq)#n#KDf=m% z!D2sy0&E0lWaY3`OhzVr8Y!?&djhTD8;M5|hR$e(fe0VQUQqQcA&QrELgxrkysQ&C zPl)1WozPE&C|=eHT_8m9vQFqCA;L!{YyD?M^yhWSO5q9i`KRh7%HT=%IpZ>A@I?EZ z@e5_}Wc!?Pg)(@;ea^T_89eDeXZ%VTJn=qfT%!!0e4jIZ(+s&17Dun4-xY%d{CqNZ z(ukkF?=zhmOfPBpq${PpTvs#OUoLy85xU_)(;%y>vFG0CS$6z+4{0P8S66VaBDXL< ziKk)}_5xde1ztE%Zev7R&^MixOF$123Dho%N)-ArBVqDK&vlC?ZSfZ=gl#(7VhVZu zp>E1ubXQf10Z=3Kuoq=FjP`l}bg3I#rqZq_`jJLrbJPG(6SdwHxDCq>a2{=PV0^$7 z%{K-AR(;~&iDw)_{}jg)uQ`PNR~%0~>Ja+3IG%XhA#|rWo_OLRWGLMovWS-+LZ0Gy z;=zZISM!v?1w%eXb-8y_F-WgH+oI>3iSpR4lJFaia(i;;;f0{<8q=8nOZv|Fb|Nfnp`4mX!t? zk24;w^4p1r45DALD5~XDHHBhz)fl1}??u4KZKV^Z3YV4Le`X$OMch_mwwRriDnhn! zu>mP|SXh&Ah$r+omSc`N#IF_AHRiri407^y^6n1*^zAj2?rv7@VaVa2M34jSr1JZx zTzsymA&gpu~n1cXl#tvI2+Q z>j{0XIeGcnIpUn;pe9OCLQwPzMI}4Ozh3WrZNx+6HxS9x&ao7OEos>Vf%#`bp~I>+ z(Y;kdM?9#cVY~o}$<^|*>_J;RmtXpT)E~>1)7;fK9xMv=fUyC8iy5J(vPqok;0|Hv zQAKq=SQP4|$Rt2G>eiyjXFL4rn$o*D+m>D0SJ~}jF1xK5dfbaTz?(Rrl~io^>}?nQ zNB*5a6-xuIP^?Wx3Y`9Dwa(zvd7klLL}&MI!Cc zS`TiJI*X{iepV`Iht_#;$Gx~xT;i}DTJOOPXlE(j94``Whc@lCf+Qp_xr3boLv6f(s1tS**0P4tGh-n?(O8lB;$=Q3rC-x3LP^hoblfOxRc9+ zVB+l1d!C-B_cogOM8Br|D3$-Hyd8R|*HPIHZSml) zoo<+KZL$ig+M%tUHR(OJz4+XqZoCdws~+f zt+-Mgpqh4QyJwEvn<}mpZ?U!=+Tp>S9$u<_Mjp3hjDWt^4(;?jbnIgIrS2EL=Oy5T zihby?oktEz9XqtkvuoLF)BpZpBBZteH|{9GWwGthZqLZ09X7NWa#eJeqXd_ut{vLr z+4|2uGpADIT6Z11(-Q5_UQgTc%ZAoETYiYU1drsZZ-+kgOkZ?uyl?3bMI_~sS`F>c zKF@_^TdU>7|2ETI2M@(+Y==JboT^l7X5sC)dhQZD0;{PV`q)!qK&`8PUFlH3OOUTi z)+7%qAWv6blxv};UZw#!q#0hECpBB-L10mdp|_Re z-Pu?(L#O!@^q~U-P zBdr&VHaWe&796>3-3x2pAR{fVFBIU@JDZm1@zhWHcuIwjlH(~AK1$YK==w=J;$<4P z{MGHqmC9v2&-sO(=Tr|}L6ONB%cjEv>zw`JF_YBq)Ch@&L>2$EA|DoKoRA-nJuvwBGGkrx(Mk623(#HK`9JOP}!MF5r$=M7?z{P1cvxg zsSmxrW%Yxkb~g(y*D8Y z@48`l4>cw*3>bRw+}VjQTqm`=VbC_c#R&N(Lf@Lg$stNxr^kb zDoN9#XdTJnlw_J zb?AAty#tOcCAx+q+ewpfrfMEM+HYG)fU20;6cp^ z91{oT%sg_da}&}?ad7DQw5tP-hm`0Vj&4qxgrmErAsi1Y5nXT;sii76*r# zQ1RWgQ0P(B7Q)fXgPIdK#vW{S@lNFRIMPUQaMV|GDm>q$e8*!-bPdPjPMU<{2~9&d zo>U^b;OM8y5;$;she%o+9QAR1(O+4|Gpa3wV}J)WCvZG8yju4kKD<7RG*TQK4HO)M z9B@3RMAvXU@1#jM25TC^@q!Z31;-FomcW5~Swzy};Antw3{!9nS8X92BRr@%f#b#M zJIh7?Xr+-xii4w}f@8D;jxkDf4aZAPnuOzJO+z?dQ6jqF7^}(>IB?^RNLm~m4H1s< z3XTb?EresD2Q?>fJYX)#81(q>Pm)H8gQJmx<8=odZz$0<9B(>l5{}85hHy+#BD&z1 zs>%{LaF>!uS{xjW5RT~zjv1;ggyU@wYHk>R=sn7rJJUA&@ORDoNF%X-$vw)>$w|4a z@;sweL_~})l+>|vUPha`5YJaPKRcm8N^3Z1vLj0S?%sBE)#gi)TcUJT1X2szm5eCsJ9N4IxDhw66gtX~iYz-K*4O5%Wv`iYs%(>m z5?vKV*b#BQ{G?6|8r1D^%~6I_6lq74^BvwiB)vwhH=|{tdajCsc0_sKwwCL1KishF z2S*uFQP_^C;JZ|R_|a;QZLTg0)pu1CZAVn}ZN2`*prLCIS96ph6_v6hD*0~Ic;IHG zw9Uz~Py<&*rR|8yzSrMNeyZiAb1yr}kc!IM5mkI$7e-Y+b8Xj5S*W3_qBuLEs&D!O zKeQN8{Z!CVhE!DEj;Q7v*s#}cBUh|{T^4HOs;HtJQQdcV=k6oGXC_^f$Y)8cV z?tAU0{1J)w?w5s_5v64%C1>)a998Xz8ou{Go>MorW7!k31Tzp_qPiV%x9|Iy`m^`U z?R7<#U_Gx()UYFJ`dZHDRpI8o*DJ^ptV?x?ns!7j-^%k#w|v`ba06L_^_4DB+m5L1 zoA%YQ@*n;)YOgH8IzgAX*N(WyH|}ITJAABaUs-~ot4q|eBkuK`-aUWTs*b^)vIK)o zm$2=K`+S3*e}BQ5!eJliUH!UtL>-^nSr$VH*3%hTox~1o#Qna(e{F18BlJxpy&c`u zj<9_Lu77a&nc6S6ldbWCS-!s-@qq8g@qt7Co0PGh?61~;bIq_%; z9`$vyY1HWt3&z~;O})fTD3Frb4#qfZP_4wx3y_^KlO-X6bbKynp~naL|;IWNu2#jqgym$7~+hE>mqWUMQ0R{M^b;ufKKRkHwjY>QnZ zG=J4Bv8%$qz0GTsn#e!5&EGUtRKr_fpV{W`ng!YbLa7;@STH5~z&8KTO!%EHoQw*@|W9N zv28Btco}e@J6?SDntx+5NAn+7GRG?B|9ogel}6ooQci5`G7>PgAmtTK7%u33`sl93n5 zx}cQii7_9+s40aQ&fh?0X|+B9@s#k~fRf+~q$!e$Mn%RLu9Tz;5T zA3KuoF1IU$iApSH6C=$1CfvZjDX4UfcZCL?@_cYST79Gu5Qa zDw2~O{3OCQ512SKSbc&A-v#VQ-2B|cj@CSW`Wm#&gC^n=<(Ti_cVXN7!mJ(F_0FWU z+$DPMkG9P(wHV?je7=F7l(x-7=8jKaNIg1m>PA^zUVa{vqO5IxWzN3ScJSjf9;?Kb z3^>~XFU~d(n<-b`TJiYek|lXdT)6VKc|^D5nAzYbm2LB=dHiy0-6exR?F`2({I* z&F{>w%ap!na?VfdquQsWrsOi9Y}-6(F8ZTiZt$lmF;SfpSms+G*R{=4=DM;m8PAuh zkxrIXwYs-C{rfu`{-Db$v`Vq8>H$MedbsC0G^;ee^z5&xx%PqrDeZHTaE`F9!vP5V zou13@>{)-Q&qY5YqnEaBC^~uC?X@*+zbG-Q9-U$(epL`p1KU zlJC<|A1|u9W8KcF#Y!(90QE*#cewP)D7_BYX3{4s>2ieV-lwLgM z>GfMCMg&?VRIq`VUE(aui-H=EFG6AeN4qMc<4csCK`M?5LIDs9)|ql@@kCh9K_cO# z)D)g*l17$$2}U8xt+aE6yLhAU~rx{zHMu|^<~pzPT&d`r$Zk#`6f;`u)b z1~U_n-x@7XJ*_cVkGNc3!FmY+HH@Yj<$oshUpcB%#ZjcN(LGG;>4v_mOA}cMb;UM=_3|3kkxmk}XBCoqO%X-BY`_|)xk<1zF zc+Gl3F_@7g>2A@t;u#}ZcZzNJHRk*>1p!FYwQ2K**|&_sW1#E-pBAzfyU z^V#8lzA5q41B)LV(2}!Kli0T+tIf2-|MOVip8I8W=mbx(#v_bM*kP3*ItYc+;R!`P zm05Q9&R?O9adFAZ8%9Y6yuZYf=7kMUhc-ulJy5Q8W)wUvmeW3|b8cE|&Wy0(ED)j6 z(`mql;jPH}H@u}tJM7a;(RI*HlpQuTnf)d;Ed`|G?F8+xzKg79p^zQcmyx+_;y1jV zupRd63Rycm_VF$|9HGgq9SL)^9S&#)E6*b#OWNT`O$KB#5wcQtILcGwSPoEuHzkb+ zD1>zqEY4y(IV?CKtn*-T#M0R+o6R6$oePUIU;)l~?2{y{Qes7NH;<$5AK#B!+s5)>!B*^LPzGqR`NIu|1$3{VN`tU%-0VKe!@XzY-AVp>6ncrtP z@lJY9vGNL#!8=MXCfL}8EAH^^7}g7k*12hEdD*Su5d(&{T1SxAHqc)ZCB@590(+*U z1n@-!P%Rq-fR)3;5i4>{yWh=SlXsL|*Mrm@$8)wq-C`C{0Jaq)pi3VAWDL_MGZGBg z)C-2ylNm$>oIpr3N(I@BR3RHx$U#g|g$^jKVQe$hfdAn5yn!1>9(s|~9k&w-@S&kD zwRj@Jm$(AVH?jDl@MUZO^6t7a9GllUE_!j6&Q?4?2ZzA1p{p~9Ut)HyS7({39`1|u z>MT>&!*)@_dWpv1guNDs1r4j^88IqcVi5h5QAz!zQT0RY)JhDE>S=_@F!mbCsHzT{ z7k@M}&lS%15forX1$C=IkuRqO`1a=5sq~hD&h-}Hb;52#N6sKBP(*I6Y}V&qyfdYX zYB+XX6o(-Mw#BOHibUdfaeYP+;@^f+3kgqmgy&(bN5E4dT!=^*##}vXHaD{VX}xX8 zMN)Cxd_HUP?EDB%AS05c0%phr^us%BtCC|9&_0BDL2>1Z*;7FIkx1AYfc?H@tW}UO=Zil`X=PvaBltI_0S_ zN!AMin)0+hkF*QqE7>q-YHz=vYj3}@`IHY8F^mn`t`n9#^Tp1dZ=WaC$G*$#8q$2S zct})jp*N70Q_xMxDoRZd!KCJD7g+?5nrmES5j1M9)nsOm3EZH~b(EUO4cc5! zsrAGu)&@$2<0@t+8x@srI)k0dL#$1TLFR!LFQlG*w@t!6(rMx~GTCX;Al}DqBy+QC z8>xc1#fyD!7(2k4;iH26-?Ve+U_`fsIaT2gm6kYmH~b|GB0(RE*7Lz#=#)bKPFT>a zuk4polexPy8&GPBI0tP=sj0#u8fmJ47sx@gv7)+m41 z(&chToUerCREd2@N|n%eqEv}|0j0taWwzN_QT?!N79)X$ZJS*vgAWGI=t>!UJaEQC zn!(_2$c6-Gbfb($tYyyVt{9{Ts(txvh2I0d_x`g7Fci^zMD;+AB0bR4hhQ50bD>~&bdM~Xo_@)zZXpWNN^1s}o1;gOZk`9yi- zPm6fu&%6k)VQe>)&nY*u%gnPgE>0qK$L@jx!Xs;!a}Y4^kcOClp+x0WiTRh5DltE# zsRA(`lkyd%!pfT&{b5Dr*Z^X3wmPC11e>8#68}6@sZS3gzXKcP5soWtP87lBYcImU znp4;p4NU8P3(&aRzHV{jfGnCp;EM3l0DhzdIi{})TY*9rZn^yqulnh)PTveiSs$3lWN~v;j zaE(&s;@~$;75&3)@pnaaO;3L)2Epd_Y2OB(?mUL39&%uVamnUi3Y!~6u(|0)7z~3& zZ^)HX{Rt-qf8BNBRf^4TP(X}R6^?BF4cO!;Z2nQAa;n7Uf0Qb*`BzgNomjXofUZS`Uk`3M;C# z9z^Ia%BZIhilz*h7bHR@6@wtOAbIZ(r5g>ONVISugptl>X@yXkA_$fBAsA#V&K_~) zvw_2Uze?(MjK#)kE-nX4(WERKi{+K5oGKBjps5c3SCLYs|Eol)Faxl8p|YZKH1(WW zMKK6AZJ&8`*uysm9U}5OuxX6z^y&(m_#)WU@F5I_G0jk8@%QIG`C!3{#al_;u`{56 z7>i95Hnn_#_Kzm#m9Ua7@wrFS9Ts%2qPqOgeTqSJK2>i0+ubsMdWXp6(76ff zY%84~D57&+AF5{zqsj5 z#5eyHHyt(4*iGa=yRKQ8Iqe~22>OIG{?d##IT_i&WLrb5YdHHxacp>; zQL=Apwj4V08NyqNL1J`&{H5&Cyr=$HO$=GY=sFBpe#HNyg6jU~3aYDO{%hixAnztT zw69b7Z(i8uIzNGUayC%%Gup#lW2ih2(&paPKMa3Eu)tl<^!vSbk5h%ut_tSlrn2*R zuYK2mTjlHDzM7gaFqkjGt4#Z@XE!w+IO3}r4;*%$_1~pV*Mj*uJP^yW?;6zQtxtBJ zpVed!qos=@{=1&r@cR9$+75XAO>)AUHhcTDdpDeYpPuld8g&^?My9?3Q|jE<@H@XP z-p1&93n!ahfywDu2%bQwHzvZIVTByN0rWKAwh(=Oyw8IbAZBo;rGf*UUITEjY;%@{ z0kBcjZ2%jB2WMM@v(`U7``A6rqnv&Nm=HZU$BKD&)8z!aQ$HQH0D*&ZEn`r0$1Tq# zyci`01<%<6@pbd8A$3{}nzLi`&yv9(HG6U&QZ!@HUr;mxqA5MV1P*6Eg9* z1PG~HZ29v3JvH;yTHnfwcw#09s#{`x-S)k=hXqFNk_`S3UZQO-wSMnvk3G?D*t?R^ zgvnIjHkVlgQ~p@>Z|V0?Z}2O?X=t0vt+{{h`FH)b1CPj`Byi0e+vW=EOaVtj9ihHYs}I!ZOI=%0FnEtF7^n`^D3%O8pw-?wWI{sSJ|k!qXktSh^QtgZG|&;LcCn*l`z+2(pH z6ngjc#3O6BMhPbazDSj!liqZ=ajUe5i=U7-pOAS~u7D|9QK|(-XLGT;>tB`JUE>ZQ%3gslfQ( zx6U2CJpYY*H^RA?Bfz5W#U}=BdToeBhaZkIG5q?$Sd;Vc*gBtYt?Ox0f(*a7{!l=~ zMzC-YE~8k3z)|FnkwC~{k|e?HAqzs+!>93ZLZ0pLGp{p9B#$y+xCm*l$|J?J$6Thz zA3l#~Uq4}e;shilut9y&K-@~w0G@$>HbDgLIZ(csN{ntN81G;Br;FGe` z?arRvflbh!-KogVp53LWj-K7Eh@@xtAer4rf+f#Cua!-P-4@I)ee z0>BK!*N{k}K`^9|w85i6phD4x?9(@}Pv69fg!C1|lTlD2{kk_+op^Qd>Dr{`IEVB) zq+t}1el*sPBa}%$28l#^4AmrUIHl)nE#`DzLFvb0MJWBND5zn~H>Y7!~5(WDrYqe-uWlY6igao>9bh zXfC+WH~1^z>C?f8Bu zsTjMChj-$D49`P7x#8(-YhpBV!&BMTNY`OpC}{(`PP8EnZxMFgVgv@eZV3uXq<`RS z<=4OI@%SxLvr~F)c+-gVZ(;pT!<&voB0a{tk~W;uE5pObvBI;kB9wkM3QF>Bm+szh zd+M!cuaTPLdK=vExalDF(LJ>_aoc+oTR{0C+#$Lb5{di^mhBHt`S2U+a8Z8IinN`+ zXgexUO3EMoIEqRFCVpHHb>DphF8oR5e^|($o7PE5-!KyX;%}owH$oXvaM*W`Zj40Y zYsd61d#dGx?|PH!(bux-rP$3-Y!$dF#4aD*0wpwzAt05Ufx<_IP2AY==m}D9+%O?F ztX<^IQ5f$-BH=nDd#09Ah5Yn_1w7x$CJ=qWLQFPnEJUj)NivWJm5e(0YlA&yN#i(> zdE-(me4;RV6oMnPst`RI6(B?5HP7^06Q?YDmQ;*G!8w6MXUUO}#AlFb8pb4MkZ2Xg zM1=pU`D0g)+#WHEw1L9&Hl*-**d;1z35D;7auVTxcrxpe+ha$rClxz{SHn2EvlJde zpJ4inRuM{QP7L|t1J(wN&N>(QT(4@R4TtbJjH5ANE!rKh7F~#P8pcsW*;DnZpH10t zu3{}xaoh1QV6FZq!1Qr&65^tsd-E~4QoCsViWuMYAGmj#b2_(L2Ht#6ok$zNXp@X`PS=- zoSK%JEaYP!h}Ij50a2E%Q@W(UH#FN>wbVM%F!G?orK7Fd>%-J19(cbd!K_LrC?GJC zT`?8AVj5O2x}u!*7NTw#Z|G{rmKk<#W8Q8W_!2vXR}1Q;=c>*)=5d6kSjRnBzYI-@ zfH%x6*UJ+1_^!64UzP}@Ci6-SU<57a!xAjkRcbor+owhi9GuXlDv*@z^TP)DYdKe0 z>PZRfl#)i=HmqQM??KJTyOsxAFKAZ2?5A&%x?_7nOT2ESEW9_x35FLA+^jRIdIi0slUpC^K$@rw3sTvH?5LmAMNj?8ln}n0b8pnRxs7j>dXpYP%D#fSRbL%oeFX&3SB}R$^MTD30kAlkfTeVYL`)P zIZw6AYO2(coodG_s_RrcjxzMAwoW^XC%5ucTj!i5E3VSNwE8;o=@x5<3j7W;S3v?( z2|L@Y?7o3*R`DPVhOt#+`uhep$XFC$S3T*f} zr6a2=qssGaM=DoFmFL+ye=DLQJ&lceh&g* z7$0g>R{Fm`eCnOV?G%-d1u8oFtFDKhWG84`#0j@N$xhUChtX2`Q%{e#YI3QsIb}jVPUc6*ZNX zkgSRmO}83HDj)i{>1iSmYFdvwLvS2vO4HUwG;QNSrO5c`*>1?U@po#`Z(AH6I@YZ% zd!$N5#I#dFIs>yaDOJW7wWm}Wd*w*CDlLY^d+3C#(l9U%P-k5wsO0@R!D?8(*P>!k zQ9)^W3YGjKsC4uo0ESUcuYx~c`RMVn8<)^s?AVHI6`YcwBhotaybUTKyNgzp$7#zr zz^*Q`43KoBSmmW!=O7|TN80d*an z^@MW;Wj?8dlq)Dc>U45dPL+^9MaxRWpQh9XBKD}iqPhaHpP>xy0=bhKKp8p^`&rFk zuC#-LVp-fmqif;u+rHGv?{#vU{$Dd{LmJ)m*~ z9eGtV^XdbYBk0Jinwi%Cs2ss5x?Tr@IxuZWmsDxiDfLBSw3m^{KPtc@$<@ItNGBf^z1pRhebMZAKj{+rQK43e z%wKW$wY2qwq_EpgJC2>6#eX%HI2 z(@-uWMA-ahy|pt%!W^C8&;GqZnlHjq7o9 zz&$for;?tQgAY1IekQF~gKtBT!MD+a9cvh`8tM~rZq4@=KXW!bhEyCk0Sct1=@o?IIjd4W_KH;-GhUeC{rblgYPo3V^2^;4U%yrf)K%t1XkQLZZH z5~5ti%_Bs)hEqGU{O587r%o6-QLf(>ke|zYs0#@Zuc0oYRCxBNIQ)Z)$0Cnv0@>uuTR>g#3=_W4?O zpRdF2WvLF7P0#A_SNx=%Wj~^Q9>M!uf7xt|bX+Rigwk=M?DKaCQTF+Jged#`eL|Fd zzL^kZpKnn_0Xe@;wv`a&Z1Mpi!Y46XvTs8oM;9QM^TT$e6LcpWPCH!byAtyV5E5PW zm9z`d-R(wq4+06-ybXnJ{=)Vx&Q6bOM=Fhb7Yd}N=r5#wk&f$QDsqMsCAuG@$ebwA z-LHrO9zHdHLWuAo%|01FMIuK6;E_nEm?(n8z7kd6-4gjX-TISAs4o|MugP@1*A#1h ziApmYS4iwjDe=ee>#y~rNSNHt^bMWE5Vw^qUFQ)Ln$aWMm5b!%9!_W2@&QdW@FzWkt5qsA$t<(1X;`XVz&mqzIzD> z5?OU==LfX0AKf-~8bKt;KHJfF>hIxJBB?Y^AgjLz&qbA|c8vcs~=Oyn%O#5ak8D%Y-QJ-{~YctabRnW5`~?k{sE_3fZejC&;G$cr>T) z*CTrn5G1ndo9{P7_IEe3e;|lt^ftZy^V3%Mjr&NYa`fu&y}u$I7w&GLbet%6{%#VY z-150ah;qm0wjzpt;G_3%ByuERNXyat57Nmw+sv8|+T|ubavu>|oU^5ky zePUr1hiV(fB}0whzSBo%O+Pe;29CsDfdZ*1`peDqIB(eLoOR9{b~}N= zfz(#6AR!}NkAD3OPsofef?`Pz0>+M?6pCM#E*KEk_{80$-q=X)1>q20r4X}*`vPg5 z@)IECFGf6CBYfE3oCSGmFm923!&xIKJ1-kDrLkdbjdC#{*fEWN##y5^N0=K6fV9SF zDu|FMMPT1%)=QM-5P_wtv0m0}Rv%a@WDK%iQB;yRed5~Wt~DR-Oy^skI6XCmL%~pn zoRs76MwT^RRU|fQ%3BkB2&iG4(Pe! zET$f7hiXZ)gr~H27Q+$~k+rKBmY9#M-NmrP%E#JM3`?wkti8ps#LCzDuo#wD|62Qs zVTo0+^-(b_xfZrQE{-Qw#Mb`ecw${_eWH27h}go|`czXjxb^v$pY>UBJh;EWes@6g zqzN(V=ZZ=$ES)JCXtw2<&pMKR<`iY68H`md`-iuL+$P`38^Z@L)T>rd7k0W|meQ#94>^`}yn+v`u$YzZ~<`fn*J z@%mrYtP%0e&GWAiD5TftP)L;DRw&O@6`|LkUiEovE*oVJno`c za$)$>Ss7w^&2ma-^tOcpLvnXHSYCq71xp+t+$Kg$}@&;%}rs)8O@3dQvM^O}}(vI}YDEe2@j`Z6onkDThLW!Qu z6jcmM+EK6=mb9Z#F)Um?gp1=zuYXr@JZVRcXH|qV;&$YCP(>k_AnnNUpo->6J1X+5 z3fpC~^s_3&jw&C2b4RXkMibJ{Xh*7_r5(lMb!RJ1X@hoD&P0>p%Hpxi9)Q zkE2I5u`IqMH3c#>IsN`xmM9`e1W;M)l-UPZ2&af1WqPdF42cyad$l%bD%63A9j%Ro z%yL)q_0=Xq=5=$7-c@vx)avuGWtRWteV$&~=4r*04iccvYM^aVRSAG9T3daH1xaf4 zZ((|i6D6XqlMdiXtx{83JK>oNZ#Ib!A^vQ_Jk>xTIWsA%o&3&u$3M z{c~1+JD%Mu&Sz?ffb^0}JWcCf@18Yo!w)Q>J2FhW3${n0L@A&y3@Urva!%v04d+m~Y>^-mi(|h}$CmEOJ&{K z9P~rWb#)ofQ7h!%V2WFI$q#WCN#`7huuJa4hxgd;093fk#qW|w+a*6zKTs@wnYxr+ z^5dc`xQEML-zmAjD2rbwFKd_lM6txQ2|tLlORC*oE&-ReoL%y>t&4`Wdw0#~n~d5f zHz}EQBWISkOCGq`>4C1*wmkhXGNC6qucBS@^Gdz@>}VeISbxS#>ztOImDxr8wz6IF z;QV7|c zrCRtnP8hm){%*!B#v~r|yffr~1LnmZ>ES4V6@X1V?x}Y7_qWE432i1u(LT{X zq{dTei>Xmy-wUHy1{NTl+3v~-vrApD%21EaNL$xX3cZ;z1W#Mp?9Uk!7GoD;F7KEt1@H8E&C3yi4_E#6^m`ybQWX zb<<_sMVg|E#SU8&nyr!OI(KM;bh1=@u*tNc|GvCpCbf`m+(L9WG8=&y+_rcU(++1a zVIx({Of(0>DCJi}-RplQu(j^z38eBeWuO4qh<=aH_C%Odd?AP3fcH12`cO9Qo*}o+ zG+&?C^RHfRR&`udPEu}uMk=5AA#u)IzNb2Me(P$L%c~@VX9BGwnQ4lo9h@~Krj}L>BfG9n^ zIopRZ9zc{X-kjsZAOIlp)G_eR-drD^T>}xmguLnTJbVlV`!BcumeHgjTs9Y_``?Ji4k;{zA^@5~7%Y7JG%faSVK+2yL zPOuZWYLM?|r4NHaSruG2NcOYJhXIa^%9VpeKdXHhvwZKBHkRA4Knh$WFas= z^ci;#Z~W-(hbM|(aRC#t~rGfo2I6D^!*hU@b^a6a{6;#yf5*sL%9N8o(s!?dlE!?igBoC7{g zK`J@CbI$?ib04POlpNkoKLO{U4--#H4)2SL!1=<5=^2I4ydN$B<4d>DqF;Xj)*&C} zo0qjQ7vqb+3aqc7_e3&uQ61Ox8ZZtQsgARL2i6fErtcQN;TZf0jHAA?C93yY+j!qj z){cC3g0-{|W{_h(d?g|(7dBq_C$TSnF>sFi`rEBO{cX& zxl*i`C&L6R*UKZ1j{UXkx~U#AiN;QY0;!o@)P9RMBB~QyNX+b#njs#Vi7HSZ5RA;k z3c;1csLq-!7Y%R`J4#>g;3w@WS|Lhb@E{AzqbqjSee|=BXt;vd><~hU6+={aJZz8B zUt4msBdXAYsu>2mekAq1nfzCod$0F$9lK0r`nHE0H)2ak-)^hp52U0+_CywZa=#zf zI6wm(7|m8Re@c2iR*qk2c)&@n&x&$#T}39TrKZ1HqW(*rx5kq`sQidqCb>+i=f?rIu|56@#R)X#f7|hmsP@ z(OayQA1y{w+1qz1G@@N-#G57ksJLN_)M%V~CA-$>NoQRVyJKV<&hNfABh!;|Q(+w; zAIS-*xZ=p1Tu2|8k>5oySujap3Yx$CT4dMp0#lJlqOBvF{Jx;`zB;q2LZj-_R%FtE zQN~1I>UsQu>G)kZ1M3lM{tAJ&Q4R2J`n#}M#T9@0TXyMADvq_;cVYV^c443pMsOkf z$cF~Hag9#{F4)VDn_|?l~F0Br^PJ zeMf8)epJ>r+xpQ>L^-(px3JuA=f^=tCWF7@#(i*ar%E0=86b#aGAPjK-Z}8iOB1s{ zd5xeO*Hxm+5&bbDur164;G3d$U^{koP<`_=Ej@N%2W}7OolvhG*oo*u?p9%8tR@bf zX$N)<`1Gy(Pujhe&40s{D`5wAqiv|);D)kg2lhlpe4F&@s*gY8KjBM%f3?8g3kT-x zs1vMRHOSmI2voI3;KTVXm!91H+vNU0<5jn+5!mOT@!vjDBk+-f#uo#lJT(FzJBWNC zFdvBf9Yj87?*`&0NF+Vc^;C^<)h|R=pgnJp7P&y)V>7O3_>c%Ditzt#iD7ST> z+zx978j7qQxFaH;-qXBhXj=_>a|uOODB}~ErBn(i6uARRXBamPWy^ODm^eRX)Bt+s z8TU67NPPj48|CC?=c`*$-W;4$F1hL zvO~L!e6hjnjqs*ORM}Cf*RkIxN&%!SDAcPr{N&H!jTUxT>Qx?qR|895xIf@+g9;-M zA_Cc)j&zcgq)qilr`~n0=@KHW$T9bVY)!(@4q?coFjVxmM~w~RkcQ!E_St9VKe(tW zsX6Wlhk>Q2P0h|qQ$V~JsYva`Zn1Y5%Ijc>9b>P)>ZpE&Sn1o2nkCWFcOKN%tpYLqS$|QBi z?NWFtte)b46e3PKZ6%YS5FQ_7t3q#oR6vwQe00VaUK%Y)<$S?m&ahDlUtHJ>#HvXc z_6w;^+kJFzW>+G=$lvt>Z%g9xJmNB#;!@uG0zzOIi$HB0PEQ^Gd}GsN+ep1}>?biBb<{xA|1tK^cRgSJsV@;z zs?Xb!>OY9;w{)xDsz7Q=%;K}^AF{HP+!Ap@V8-d;#_nMH4;6I{mCezpERbD!Hz%mPhjPq6{fv||=JiF{FN*)fZpM7}DGuwxcGiLfkX8T(_FD5Ag(s6jhsDIPHg z(^&36-d1TlX4!>`dj>pvrpD`n%v&pC$1KlD_-xbOAFlra@`5Um__*gq;<$@XA-nudF#%fjviyvaa1u?4{cCJwAYQ4)RSy^~07pUdznANlI zzbpD!^R+$5LU{Xy@HaEt-bkejVMJLhgnu{GsGK+M=7)uq&(kp6xa&}W3m~l06A?2U z+>dzaHAcJU6n0&LyQvuMlo?SR{lzG!9Lb2{;4embWKI;velcUv<|3g_vpb0=*<)UE zQVZE*6f8_A=4C>Lq$99v0_0Z|SsQuGSR|7BI*2DRI(}bAXw7Wd&bbVHuL+dzD<)y_n zycoxUYEn*SDr8h{r_PZGM4MkiFjvE3ScP$b& z*&V6a9cm#Zx}$tdYee2KSW*_*9sSq5zN_KHE(N6CxOnUiwVIE~fY-dU@(W=hlb0@y zysc6JUIxl3EXak_jBE!sMz8kay`bFod;u4umiv+1OR=8_^!0nz?A}mDAt1*xUc_YS z>Vclkc2u~hj>*=H0`?ODwE7ZYy;Yb5x4wCffEcxak7P8~i!9_nMlIZN6~H=0E!PS5 z=$r^f8hiXGiRpyct93YH-x*;xjG>0Ye#4)2{U5eJ{UfP2Za5TxJ_Q((k|BYed~Uh) z;z&W@AtI%hC@hBZv-rAVZcRq16&C+oX1|L#h?bUFPl(mG$?Ia(JJR_T>ev(l^3 z*~`y@(yLJk!(d-i(yH!cpLo3bxtCq*yMMW6%)hHa{*XkUrKE}JhH`SRCkJ?ULX=MP zVM3Hnvyc#_)6`1?r_;)odgGlYM>^O`o!XC%NdE7hH8{mHn75V4ui%MpxBL8|Frm6hdjf&8> z!<9rtyUNYiO#Z6v(c7eb9>uBKm)ea|+KpCq$tX_m7%wV9?u&%RuDDpGju}I0=l4Z; z?GT)w)jET_;XETU!aKzq;&j%L@G0t@>P7IQI9(VN`#$s9-f3PmKf&bB4+6`yy>EF@ zEfJ8weqq_(>0Ug&5x+pk!q^eEcZL^-F8ShHd-krLZ8lffOuzV0Gx5c@68cNd4S(Oa z_VRr@o*zY3UIPV~3W?aJ>eTgaXC_j_c{k`jq|Qtn=z2G5zI0Y_p6T7Bs4nAvS22jQ zI+$|!_et^JK1-xk&Pq!wO<=P!fh{f*sOH`3Mb(M3x^dm!o-}w{K50QYt3;QxT0)$a zgkq_Z-8qhzDXL4=<%&U^)x5Q{hNNZBdyojCoD~Wp69uM8xRSr6y;Fzk zRT&DfHpM1c?Fe{nE(AyLY?I7yc`n5Mey!xN6LC>V>^risAVs{}>9zfS&wIDdwP-p1 zLW8KhRJb8fh%b8jBRtKc-{`m@au9NI1q~CX_6I$`Tr6|ySo)hIG_YaYAMz+? zD5Mk@XQFL?*kkqxE}66EuPXX{zm)C2%cEk8^Rx4lG7H7elH@L$UndNSB79iVv(74S z`%CJJ9?WI&t-*@6zZ8)K?q0xiH0`rshsYaW+4jeHVlU*+{UY&|r=r-`Uv5$XV^p>M zkk$P1zi&EB{W7BS*|76{{ zYKkd00&Cj-SWlIE+I2ng)E8%nHGTeC;kPr}=FOqjghnH*sg*}r(<3F)-#As*@A^7O zfdXk+pn~3uj)DiLa?&#RCRNlsxOR=~m<=?xV2zruXu`#_Rch1%MNG>s$lx0!Q41Zk z%nZIa617Ot*pDHp7+lYbTC9lBatFTq5v4Z-pydvH=Oaq(2kS_Rs=~DF%nm#^Vw6e&$A1j*W31(sSdi~9G{B&%s8vWO5jf*6j$HgsQ{PWyMDhq6 z#87y#sI~H2BWfMpUZ@bY9{a&Cu7QV=({uH@8=KddH=!n}IQ9=Hz>@uSW_O`*YPJeJ zf&66H7G*?ny~dG88NQ#AID_A<(W#VK-sNP@;1_FjDrLq<;S7GO=1~tS?gxfygB`|N z`g#-h`fxEqMBrJy^^e+Q!i}KJM68hiu8(4qN#XBBU--*+sPHDyS*-Dt&H_&BaSTbc zo=}5TuJNoVJqVs*)Cwv@qetEI=DDeDMw8mh+zSO5qQZF^o(QX=8Omqr5Wsy}mCO@W z+TPQt*OKW`oR-LjF3>BR6=v^g`pevdx3sVF+Ex`)`6^bN`xDc)s+tHP)WU8FLnS3_ ztC~5i)k&k>&ExNA|7F=$bzKST2_^_z_F3`f#m3{K_g1pbL1R<%9rEQ3VQ8SFZQW}c5p6H#?an#JE8=1JrEKdyT~Q7`wN%=+>X`j% z{jbH6@0xGrr6Ih>8(+q@?l&)-j=OWa)3`UII>BD2Y&gz_r_e?bjP`+g4+9#l&YSd{yF|L|)7PqwC7!bgKUFJM+HY!Myf&<}!AoQeI|^v1J)% z?914fglwfOrA1Uop_De2vX-J$vV;-|p~$Y37L^t$p^bLGbI$#q^S$3^`u*ec@jUlE zbI-ZwIp61=d%oxRc^~x>(I#AsuP=Rlb|Ts|((TO1va9k&-IuCyzqSn%(PokM!+x9h z)}RrW`{kH#RXK_175q@#u%e4JcH66m7jnygztWUJof1q_Dnj85%{kPH2d0a5Ohnsp)$I8->Q)O9(e@F0R*lk(J}pMU-4oFc5qk!V zg8j3J6wxCQ?HIA=5c!0@zGouZDPqs}@&B&r?7b4v&JnjFQH|sNm&_rFXqU**Zw}3Q zXxOg4YS>W2d;1=`oS}(mSFV^LG(0R3?Z&VP!$tzb6VU>$mKr$B^SUk(?H+kxMaO+b z<~3-khZFNqMkk^@B9S>s?MB{}x8A=+BY?4qXiqL%4?g-Yj!Q&)F>3yz>E$;hqP-bc zSDWU#F%j*a1q)sL&53Bg$jqawf35aiJR^X{);_c?&AMMb+>TMyA?4w_!A>-lNb~o5=k2H zV9DH$-bdUR70rA?Lh`-IAb)s#vYiVlrjwx`PYjOj~;T1q{k zaLt*D8W!39)!~kRzH)Ym|M$%@NtH+x9nOP7uL1ri=5Wo~iWm`TxV-mMmD<(m=>Nj3 zp;W0t(UHMln6J;_nsXF>O=R>}OG@5y?E7;1uebI;Oq)!g=(Ukm-JiW`a{T;JMRn`h zi+=UE`qik&<#&GEWK#B&PX3=Ui76^eD0-b}82vdrTyw6%uaD%mcqp1QZ^}ddpD_m4 z3`(TQV;>;r|(v<)ZS6qGN-9#taYPn)4Mt zF7nIOA5Qw?%B`jRADHA9m1`8efjdRM*?mIYm&yx@-WaLZYVIXlT7BuiSTrzcMoSej zp8rC=+Rs4OW0`_)ihNzK!mr;=D?7&gfd;CdhHE~rh?|4gQ%k*|@LM9^k1KLp`4;!o z@_%4@#BxR48vFs(`9+0Kh^*b-rvC0W{a5%uFx~VeMcfwr0oD0sg-?u}oYm}>k^>K& z_J3eH=?XVN!BH|AQ! z-4$8$Ua4J;H?IE1|B-p_>l869vVQl}7e9Ql*JzbJsQ0BIv2Ib^-4UDq?f=L;`>l$& zhsO{lJG!^G6)`#Zdb?d9S_Z0WQe{l5E zJ&K;qv>t)8O-J3UhzEmJPebX&$cL&q#`-+_tv71b3Hu&2Q6#H1jZXM)51S15Mu@`+jlJju)Dqc25y+7Tz9pfqAp&*E+X{|9a7?Xj-{&3Ef4ryY%i?zgM@+hQ^~M(&FKk1=q*U zRW31I`9Gh|%<0vwK_+>)bfgLA!QS3mBSCk>n!bE^T7wrC7Jc1lz1YoO1Sw=<$8_kw|5p_B8o{*q*V>tB-z#gtE^RSTc~VM5(yT^29nOGGgliL~nBycN63UNx-GN&lKGD5g>(twy-t zovEvL44IL^mxyAjB+_bz-{^Lt(y~OovgR7yRcKv=@;KEJX%~g_t{$}L({59$8D4h; z=4&L16{k`sv8(*rEZ3@WL&B+&Bo=B?` z{xP%1>27Oon(tqr8;UPTB+@Pm?|glBpGCip8Ej;3j9>jk+T~$(aY`lXtW>?xlxmg6 ziL|=m=&QT-7ZmwptNDo7NRsOKv}nM-u6u30zrfjYkvd#{}M?v%fD?(M0;^g6K&^@kF}Y z*WCPR!efc_FZl<(d->ZBl}w}`51@M4o%*Y#6X{xBy7$eatIH+Q zzhOAftmD$9#1rY?u7AHpVq(^cu`$(7CTQvx|MU}$@92_$^Yi20i*>gVQ?HXu|8DmF zJNwjo{jxFU#_4)5k$!UigPUL4`gghSR58lV=)%h<(!X#2a{KQ22R_;o>uzk9o*_v8 zA!Gm7W9C(FRaq77uc^#Pq@N1y&v?22k40vyEBz&v6%*+{PXB3V`+=w4`b*y%P1saQ zq@OO9`rBpg{ z;$PUmZl*mm?X+k7ON)zX&!r`=`t?k`dV9p5@uxlM&-n9n@vrTws&8zk@t0UsjDKry zH57V2aR2*OfBMhv-)xYa6pfd&6Pv(h9vB_6fYmGKmq zuB;L-nlzItE!N5Bo*JET@|unFMe$~xJQc4xwrh!B>{+nP`7QCQeSF0O4WT7r8say{ z2HN4A1!0NZd5eoBcAd7*sPM_-&o>aa=`XSKADF&P>I{F{&hVG)3{~QP+uDXgf2szg zIq(Htx4qZ7|B+l#cKLtQ1-hDQ=ydge%XDUqsO<&S7P#>(_GW2ilV1KF-|9g9`(FJE z^3~;f1#5hpW6aEiIkq_dwgrpYKi6Itu4l00+a0HWpfb|^1483F9Pa)^d;KTOk9Imz z|44mrNb&J^EG{&b*YVK!e!tHa^Zo1ltpg5XfI-!+5Ee(vEn#Q|HiYYM{|WgT>!z17Z!)L+Kpha4Gb zlEW5sO=AC&so(pOR?TAnn4v##wEcTNZ=2_c<7M-FXmPOwA$jteUz*KqKS4B4)xoL@ z1$u~X9_oP~+aBngjX%oQh<|EZS_~S+-u-4kg*Vz)ljZBNHBdg4{e~@jqwL*P;+t$o z4u!_4pHlDcJ-Tf8v%jj`D9SEBp33gkUS-<1@79@408cI&KWT;zhx^gcou2~H&>f*7 zBEfYN!qc}NIQXyllT~dba7EkJI&EuoM%Ji${H(qCP-r37XvSU3yWTVNJ(-m2J*{iR z;ZS|JsueD#9gvo3w077&SX!l_du8-uM%6q{uE`^aULwHO=0k1tQU{ zhjwmC)Zd(1@86()lIk>xx^8#9ge%AYW>+CvFKlZW3h9rW^f33`oz%M4!shphlD%_& z)!np`9|lwl^a)dKqw46*XkYhNbh~JqtsS1(48I>!x*;s5kI{?v7hG%0naz<0Fh@nI zmHf&2S64D)OH`EE_jjP6Oo56rTmN3=D6x}=ogEX^t}+CxP3=0wwd>WcINGTsIy7vX zFcg}reoyWCX0Il=V%v*}tx^blYBgJe@Lq+xei`NLk)H7th zEnmw74S4$UQ4SR!f$bz;HFYy?PYeGeaIZH0V>Cii9cr|z_!w7~{RliZZ0jhrv}s0o z&xO}sYb8o2EjdG_dQ$m-mMXZygIda9l(ke*fTX2L3Id2{I{w;QDRo83w(7hXJen1#dIMK@udjm^w(3`eZ7s#dJRKUo_<51JH^^j8voTM;8W+?Yxa;gK zP36^lnaZZpowSwv6M76${ZFk=(ReQ7)TPzp{%C85ig0J=)n&y@xT8N$O3rsxYwJq# zt5z}EE^KR|_ndG_zPd-9ty4CB3mrODU7){ExO%17dYNp}Xi--@Rm)_PMvDo!pr@Wl z*V$vy;!LO~?h`tJDVoZJ-wxVnM`MiY4x-6w%k06uAD@8A{f8DT(Xr zb^chiw8MpCwqIdnJNFAwTTmmb8Cd`5sA$|3<2Q2oXj<5|XDDt3>Wpv=_w7MMqCdZc>>9o2^Q zexD-=cXEHj5UkYTjx^hlCtlui}z6pn0Y;WncaEfZLIC3_kO*RT0GB! zFr$%gaj`qg(|`XlY15K>j*35Qc4skvm}=DCn)nXV#FvkEw0AB-Q1LICPp{YG!d;@& z@{>(<+U9odtm@@IH@7u%A{f~2&D8(8*UF9-Fp;850DLwL$eo~8`eC@M$ zPfZtp-b~Z9ZSDR%RjsG3S}$3(D)HX77NO9CT=wKvGk-Z=x}KSfbdIh3Bc^IfRQ-Kv zs%O=&cx!cJghKrH=l=Fi=~*S|YPtP+iWl_mqJM3Sa{NkrE!5WKQ;OuoS@Rzlm7VtF zFTSKCU3LL0cIQ`eoy=u>abPoi9JlP*^$l&X))B&`RYdaL?D=&70FxLAo zJU#Vz?}jgln>WUqZ=Twvj+5(UAlJ(A%ad#?ghB_oY5LUrVPdHF5~&*RecLoJt5i>& zRoS6yJC*yZUikgCsqgOE&e{46lgW5qZm(Q3nX4whLTa0#SUihKJ#(O^^!y3E224&=F!DZys3;GRI9ShG{aY6g667*Jw?k(W=IqCfW88+0j!zxwHS$ z+O>ZZkHovvHkugQJ=353QLenZU9#n7n5*DWs9lC5M2ARglzYXUWzJL(f1Nu-U^kC= zWmmTI>OidoE{>}W32PTQq(`%^<+IG(Esb;5Wd%~WfX-P%nb4#}E zk=LfHS#=wKvho+%*X$g3esXY2yZBRMp51&rG3(xxm>!4qhn^~l_&hsWE6|Q(nyQwF z&$nZqqRc>|;2Mee0y{Xw+7{&c+kjt`h%fwmb={OX#cIss9r0=>;*0FJ!&qB)xJsQw zeDV0_Chn{L?%Gql7vANG_|sqfIQGF$AADhWOjSjHs%UHKsMj@24JYEy)ZKJufNU<@EcW+8>&0@3|&$* z-aM&<{;&P6nuxbZvib0-EWW|UMRe9nNc1PjcuV(u3tiN{Lp!q@dn6HW#aG$+#$Y+o zL_GKZTwx0-nuxdNOL*E(-$wC7yiJmwBTUtt7Q7;2iFjU;ofkI*Nl?$pD!ybQo}XkV zFAcA{lqO0i;%$@cM=L|PSvgIYO~l(J*;zb8>&K_Qk|-{oh__F&UpXvCe=j`|?~r7_ z1Esdr<5PPx;_DxlPsBTN4Gr1Zkr|12rvPahPYX`}uu>x4Imx=KR5Q|8O7-|INmjQ$ zrFEo#rFwkVBs<2ZwpHK8`Bqf7?-uxLisL&`oxdQ!=`Q0psxDM%pnH-X1x3ewt=N;z zW|S>cPIg?|KmCq7Pz_|{KOU%Ax^3d6*NV!Ht7nw`j;n*c%6{pRThP8+k9@xmE5|T6 zsf4is`Q3Y)#!1A7B(-_G%le!buURi{C*JbKOHa3LoshR<|EhmGv-o!Im|MQzFOj?# zuMsJF~G?|jgwn>xTt@4~I$apO0;i`y7b zzum@faiChYp|oPQK#AY#(1Lbd%o}Zdf`jsVs6elOdz*t=_wL!>kMV931at3MCLt(3 z$z7P=$ISJ{Z+D1x0u9XjZk%_cD`?lpWCO){7dm~Nf8t%7H#yRvS`w*mhBrCVV2 zw;z+3sZIUYj1}hXmeZ77P6id<1KBKLZQW~8Z^*OU-j#)@5q1Hkv(>V zkL-mJzG7rwlC7B7mtphIbr0Ql=CZIT+w9BGPI(ypjh1#-O6`Sq7GU$@lmwr;6Cux_b6lWaA_>rwc%WyMAn ze7sVWZC;Ob+4)^v)f)O$qYj*!<8C!rvqlbunl*NWI2~cr+s6*pS-9+s`0M6$1p4b# zv1YDfS3t!wQky5)I*5n1YG#wn$s;G{ilW^^bKjxVaS*NinrSbpwV9gh?loAo)((ZL zwQ+=aXw?(5*6t{MthM<2?xESwOvx#!ZC%~kLES2*wokIv2!+P8<;d&b_UM863;qyg zd$*_y{ERgJp{Y-7sy~|SrNK72Nmno$=#^@QTkSQk{!xif=JPf8O_RK;xz>u)P9)0R z)8w!EQ|;Yc^);C1PqG&)M~zZZJ`hB7R-4`@THWugCJ)dIrs}() zI--$2eq8B__dR4rbYPNwcA?P3kc%kwsz>fSd(oHWMbX|J>H^Bva!<5aay(6w-u3lFt5!y;Mcg?0Ta|ms!{$|jEaoq-nFdeET6Ml6~ zM{32WDn?CDgrfR$OF-Vban;LfSi`Juqk3hbG#V7Qp4%h`U^75PwOm(FZ+?2*QeDAm zJKE0OjO_~TlWgOJLRY9f1}Zw`<#H`vtv{odDB5eOE@-FRVrR7xq8*aG*{Q|a6?Ew4 zZ~p8(m}(t@LH&L2yoV&}?<(d!EKz@3G4BzH`umD`k4n@(CD5BAQU8!Y?=gw`X9RkW zOVmFi(0f9n{t1EJT#3>Ff!>n<`{x6CPXX*759rMU*gqZ6n-6fddDZY10Ic>SP(zBh z(7`FXl{0g+;`Hl-w+NU1m<;nQ zFj@Mg&M?mbqn1q)vlN(YyJpf`224Z!nrBLT9+({cx@VXdfN7-P`3$ohn8y0m&oD0n z(?l=pG0aPn(b<5+ybO$T!^Es`j5t*wt;DHy$)jKWUg*ah>FxC6n+k80I(K>W=ulD# zZ*{7*y}mdrd23Rw4nv_PEY5b5+fF!rNtq`^;ht8nE}WJ5u^P=-nV&fA2bKA$L`j*S zNtBd%OroUB&m~IA{6eCn%r7NM$~-PnQs!3@C1rjsQLD^v048OA3ot431i+-s?*Jxc zo&=bb`MrZtnLhx-$~*-OEAvNSSed6K6Hw+EU|5-FfnjC-1Pm+lXJA;FzW~F^{1q5h z=5N5TGS30S$~+GYEAw~B1eEy)Fs#f!9V4dTwp3gFS7`S$Q-pZT6r3*}lI1_vK6(Fw zAFkkCNU{nP8=96Lv$py9j+gWoC40Yxd|9ebfNqk-8*i1VmmYaHxjQ9g>V-$%%@Xxj zEGT;|;;Wi{(AVDTP}3K)^^zttq)m{7I)jXe+a!^r=R3?VCQ71_{sV@XjHfvaKghI{9_(-cuJZx-dZ$?)}A0n&oWBG`~q3 zo7G(2-R@>hlQuDHxx9NMss;}|%i~Q4SoI+d&v39WaI?z9G{sC{l!&O2?gb{>wd;Mr zs8NJ|Gs`ieVZR<0eX~v3o%f5n2OHMksyR8uo9!C*!9orDP?Bv!k#MoBO7o@Tnm)Bb z6z=`Q4covq?4y3eD(7K3>l}BterHu+5KF!LNEn)c0Vhg!_NH61>X>yH?E3{ZWx0ZmDH3tiJLD%7-# zlWZ%Brkzv!vi<*d+kDyoZQ5+tv`hS^%`$q8dC$7LHBFmk)Ee`i1K4Oa<}C%-C^hCS zbFkmEMi8bko(IN=!Z0sLMh&laG*}Ldk%sxri;fXZ`@+5PgA)eqYb9zQ?6ujpX;-+W zeWg&-u1vD67z*jN%Jf!pU|+cL&)c)wh{DS+R2S&y7Fd(v0Nm)CHds@SIV`gW~SHP9Swwbrq{!n zUazICVJOs;{a(tsjoyZbONCPtDxA{?uH&inVaol){RBDfe1Rlnh@hiIU;V zl_(j$))FPd*G8gb`0^x5hA&^DWcb=jlnh@xiCV+g9$+$j9RMc7*AZYce4PL$!`B&L zGJIVe?8gIs73&HN8@_J9u;D8Jh7DhL$pj2v4`A5v^#q0uUoT+T@bw0U4PPH%*zolQ zh7DgoVA$~W2Zjyb0ASegT`8G>;Ts4H8@{U?BPPtcr3{_6E93i*gnIm0l7d{V9#Z8H z_ab&RyohCZLsP8=L!k;R%+Z&g8&&y84>=`Yz7h$u1HXwaDIRzcd)7KQ1JVr1a{?q) zE)^h&k~c!sWs)X&BSa07BzY%94U!^xD?|;FAl+7o=9Wm0FNwcSa(r2UR*fqpN@9FP zqNK%@5+x~ewxPZ)eGs@FtT@-upd>_>Xjs&stV2#VGz80#Qw3Yjg4Oq?Bv^c#CBfQzOA;(Smr!de z7*O6;@e8&0k(~qCW(n~j`}hqdf1X_M9&DJYr!Q4F%v0hZ-R+>Se%?+y{o$t+W_a&d zeT716`Ln}Cf0lc=;=p}h3q5CX-Yx$V^c68xIg+P-G#WgQ;RqEbB6JCl2P&d2zs z%N(oa{AjlZ7wj9NND41YrL8MRn~82)_X zGfJDp@TU{u3~PMZiY#LgSC)M!C}=Q_uT?oq4RTV*fm*|~*yg2C?LUU$d1?lHDd_ZXLCdqOC5 zIS1;o4OVwARqf;DqVV$d{6MYNC^-lHb1+c$p#D{W6sUg_AO-4k0;E8FUVs#+ ze-|JH>OTZXf%;DYQlS1zfE1|z7N8B(|45Vq^}iCOKz+fYz5*yvhuq`yVT#mA08^+= zcCbH6aI6jk!@)WN3`grCz;L*ZN+uAmQ-I-sT@)CO*u{Y1kX;-Yj@hZeaL|qc!%@2g zFdVi^0>g2;6fhjPOG_pYxyt~E zGPgMxmH9R>tjz7eurhZ5!^+$#nSe6i0fv?NE-h*KEYO+mkpa{Vkdoje+8Y1+rnPd_qn&0nPlcH$*vRxx9D3y-gn_1I=qo zO?AmX^P*CNl6`ioN=*sYJ-aofK1$~KVe!|p$U8qGQL@gDTGTv?fODQB2{z7;NrHXz zlz;zIZr&VKu2(fd7gs$jDtYCz$BvFdcl_g3Mx{5?8LRXb2 zMd)f0r3hVJq7o^!A z^ku+sguWaYj?i_1;Rv0OOdvwn1BN4XePB33X9B|!Itv(%&<%j$2%QZKN9cyYaD>hQ zh9h(%U^qfImP{Z*HvxttbW_I&@7({<(@R$!Dc?}2$9iY29vYsTy8zt+0(6GgGRbOC z%s2OcW%y;|7i51RinjC31-;!?SKe+jWYUtn_w4B5kI%kw-XlO#aVv}*i7q9n#65+yBuC{dE)M-n9^9+fBw z@nehnA)Vi0Kam8>@KZ^!3O|zsi}08r0vh~W5-huF80Gq#vFs4!N?x5aLQ z3g6TCw%F}XVL-CQZEfuhXs4P5XlI%QXeXKlXy=(NXdWlq;!Xl*TijXT0bATf5^RgR zN`h^1H%YK9cDq>k;$mCeUH*b?aSuy~bzRkK+_S6Wl2e1kW2)LeWIhY{kBK@!Z`%R- z$PQ4+>uaBND71n*z_j&qo*s718u|IX{3`AMY>Wq(hozRv_*2XFMt#)IEKAf*EKAhR zD+|;bA;G(`oB@hI`f^_M3*muv~q6}C>=b++&NlxF|8D>!F7#&(6V*cHavr!JiF7n#q5 zk5BrvyC~T@V|ApTbH*dYN{o@I_CABo_!@~)48B&P6of}fl%nu;5~VPFy+kPvkCrF} z;xQ7XNIX`e6pF`5)W+f)0H$DkBfu1m#{*2^_$GiU9^VWw1>{>CjL!I0U^paC0ET1o zZNP9)o+z0>RGtJ3hvnOW;kbMUFdUfg1coE?WMDWnPXUHw^Hg9sINt>fN9Sq4aCp93 zGJ*Jf4=@~{r#nVC<8hDNGd;IxBe^f3b;epfG(g|$R$|;&XeGw1RI9;INUwmRm0=(J z^i0LG4gZqKiC!yzR=HQVc6tLE`_{TnXmh>0*Pu3ElPGEPb%~NTH%OGU`G!PEn;Ruc z+T0{j(&n2IC2ek&C~5O8iCS%L0hqM86=2flHh@W+Zv#x)+zv2lbBBXbn>&GFZN38x zYx7-TSev^f6VT>vU|5^)0mItd0}N|(FEFgleZa6b_XES)JOB)9^B^#+%|pPjHV;cC zpw0JzVQqfk7_mjr+k4A)POEu`bkAmsAmyG(KqSwPoIH<$JS%%2r&=WndCsgdb=tqR z(>KYu>C3ZqZtzHXucY1C*L?K}>im<&J>C`4WXUx!iJ@MZu#2+#TD7QFe>W;C z(S{~9)GH@ZWoPuYyiKGjw~^VT!b_9aHa4lCUb;k^n4Ky-PohePDv2rPm1kIcp6o2M zVTBjiZ`Q#6mK9!L!&#F^m}$1H@B&-T8dy0zT{dhwo2d>;(lGBj>*o(=`}t&5+?|*N zVl~@r^U10Lqf9L2I8_6tk;^CJEouGI)M8`$O%3=>6PHg`Q!+}pb_LZ%z+}37vRc5X zRl4+dc>8NVA-aLfC*v)!eMY@P(QkMkY@cc9^2vBJY@bm}t?4(sA-2yna`|MJ!M!!s zkHxIDxEvUDBpESvC8LCE*HZC@*)e$5hQfH>!dD6=YTT^TE z$r^;M5Y>hR96TG%_~z|e4@O@Qg?k-L@N6xUJ?q9ylx*N15$`2pPI9^fH)!BbF4Y4# z+ZSkkfYsZD?x~po=lBxM0=SW{(FOoF_C=ZvuzG>gWjB_w9de&w`XFyI7Z0y@2fueE|LG?GNB|ZQ(s9W(}I{y`|KV= znf8cTMTSCcSfh~a8K*FT|w(W+ULHo(CB_Q*7z`K^Z>x5(Srb!Mh^i@ z8a)g!Y4m-7NuwVCOd35RVXM&(0Va)p1TbmzD8QuAj{zo)egZIQ^izOIqn`mx8a?J< z)ad8HutvX-OhBVw0>c_T4h(DbD_~foUjxG${RSA;=(oVIMo$348vPC!*62xKSfk%d zCZN$DfMJcE0){pEBQUJd(~c3dLyx^2{%BYKU$caaC;?QTCLA1Cy|4jL7xCs25C1sv8ZAN!v5O83T;T+%wEr$B40S{mpwe&2QU!pKMn@ zsg7z-O?#tj+VRk|mAsq6wiTgi`)%8N{_qc?@L<#O9PF)r)2d;_H0=a;x2CbwNvNi2 zZv&XpYbOG%dXsM2Ne=d<&Iz`+1H&1%cL2jFws!)f#uIuRlN}?PHtW0TSH{2Sbx73S zg%#DY+=S*`u4$(gYTCP1)B3F_ns(}law*4Nxa1j8c(7?X6?6tQEhX8`ba(4Fts2jD zW8EuZHO84N+xq}kucZ3wSq?T$+mN$t?*~S`lT$N201Ri@&IZOv!}Qt*9V42y>bghI z&iZV^E28$nrgf>HkGQ6Nv{2K|3ENf_P5a&YOJl`m4~4z#{VZD}2~Gul!f)D!lw~{D z-K}ZbhDNb5?@53u%l0XNDa&@AgH6+_f!1c(&IiVb!ZgzYU^vTmAuvW7<~NHRBbxTI z7Y{u(YRyGk{%_N|RM2N!(=I90w9kfZD~jFkepof(uckd0v=oJVOG3UG3Z{Z4Cl`~s zpkcRdkR?=C)XAU`N2CFX44wp-%;5I` zlNtO0U^0WJ046i|ql5hj!7ps5fnhUvMlu02corBogFgYoX7FcV*bM#x44c7UfnhWF z8!&7J&jG_`@H{YV27d>J&EOxB37Ek@fnhWF7cguF{{}{BlwR2Wag6vRapLIw)jcnK zRbS|cK1s9=B!`CF>sk`Lu4Q=1F{?%)(Tmqk`DOEm-<%Xhdsd=>STL?3jFkZ8NHpLFVX=9i;FM^2)gNBW41 zqK`rp&G6H$uMo8G_zXCFnPe3B}<0M2SzEE?v0O06CQKiiN>Q} zJu@szJV9&UMN(-8=P^4L@|c~%wkL@0k!ZMMz(1E&IV1`Xb`O5(?CRc(O!w&K>S4M^ zwpmgY^9m%aMiZ515c9eNY?f2SJU%(f6r$dYOj2o2xLS>zx{zJ~n}t*{uQ$Nzg-BoB z$HC^Ysn-s5-{ukY1;(seGE6^U%*rLh^an--3My@YWYpMUbB?bB#;js8r40netYk9G zRlumRgZ|DS$B6FH;K56x3%h?kMm)h__i!)HSG(>pv{3gL7PdV>1o-find|Pl{hrmL za2w!*Nu`@*fPc%4b9U@78?$Tym;(G(fGNOl1DFE*+W=F5-wrSZ_#FUKfZr)$8{ppo zm;(H}08@b91uzBp-2hX7e-B^^@OuEJ0KXSt3h?_J?2kq4!S@5h0seqw0s;OYFdX0y z0mA|QFfbh8-v@>R{0G2rfIk8Z2lx+x;Q;>;FdX2I0>c6RW61;p{3pP0fd3R24)C7= z!vX%7V?=;o^yRVF%ZwiNU)ygNsIz5VvgwyDz#lIZ;J-??YE(x+@@w+g#p6~EcqW=J zCEDJ9O%}kgiGN=t}^TMqdV)G`a#{(&#G^wi;at zFllrZz@*XD0Fy@708AQv6=2fnT7XHT>i{N=u6HnM^fh2uqpwRQpwSJ$utwhihBdko z7}n?}U|6GX0>c{J3=C`ZEnrxqTYzDWZUu%lx=k_xjlK;GYjis>tkE67uts+}M$Bb> z)M07A-CLT@5kj(aS;4f^T`rF9hB#W$doOJD7z(|~>#JXS=dO*#`pt3M&j*-Hcv}biot;g1J7Cy^ zw+Dtzcn4tEgm(mnO?W3@*o1cmhD~@EVAzCrb&Tj7rApPgw(Zo1w*P162xg>qcO!TY z7{M!gJ(F!e5S`=dMVs=TKc1Q_%J#T(um$hqcMi2w!gP+l?p{sjuok?Zgslbd4=`Eq z0RWQ)zY<`w-~$0B3w{;AWWfhH7%liRhi_Wv)68DEgqm9IaKFx4t$jB9M=`<9M>n?ejpt9o{m3t+I;z8`Gvtc z@L;0qw{GAt(fx$GRXcDP2mT$v6x~k(Ows*&fGN8F05C=OQvg$R{}Et{?x!Veqx%_v zDY~Bpn42g)h3zvO-T5eNUkAKwiBH1z z8IJCJ61LB9bm!BseTJhupNH);9NqayY@gxi&WB?A3`h41t^s_8qkG6jP@m!Go&*d> z_hiWgqI(z^j_wg)IJy@BhNFAbF~WgYJAQO@&$P^9QlkSx=3`nQWwn?K?!_UvXLzY$ zt41NwGxOhm>dsyl(nZl$qQR8aC!|E@y7m7Cajm zw%`qcVGEw)7|}hlMjzfCe&?@B;t2-3hx6b~T=!^NsCzU^wmm@v_($XSzTRg=ODZrNnm;!t`fGNPo0j2<-=3or)>A-M+_aqYt@a2Kw0AB$Z4)7Vk zaDcA}3?Lj`%B6)?qST35H7e(>Cb=m&w$cNuudn^pn6sj2ucNv^ zB@RGxY;UR3KJI3PO8Wv#D(wd_skA@9q|yNZlS;1ym{d9tU{dK-61FNG1Td*|FuF6Hw{3z_3b30mCZ24j5MH^}w)7 zM+3tu9Rm!jbSyBe(s97BN^by$ReGaj0xBI346F1eU|6L$1H&r4#W5mHw!-cod)&03 z#3CUjN|UuxqE(%@IiXGjp;q=L#jGYpB3{>at3NEc?^q8}Iwj(@k%@SFeVyiHn-e&_ zeeQORPIDUiiFo?~&hZoR4gjp&jZQi{2ykOR5$_PdP5eZ>!xC;(-%rGQA7EwUblD#O zoaHCt9Raw3pNRJ%z}bGj>_-4AGp)-$3UH2}i1#tTjnrZRb@e9zH`eK1G4E4=)fb5egJC`g#_S$om@j}aI|vx&OJK|{0){ybjM+)RFkb;Cv&(>CegMX7 zG+>xhz$pJt>pFjQjIg{vcJG>dGP7%6p(L`rZA2p8Strw<|5q|wCylSZGGu+``@0Fy?S z08AQv7GTooa{!Y@mjX;0T?Q~|^m%|uqb~qV8eI-BY4k-0qefo>hBf*!Fs#uPz_3PN z0fsfY5*XI#DqvWntASySt^tNM`YJH2(Y2BZXmlMgtkLzrutr}4hBf*+Fs#uHz_3Q& zaEwUATRi#Mr}Hnac$<(BCE{rrQ5=1Lk5avW^>V-6p|)(9A7VkxDmv1F7| z?GbEEfKkaR^qZ!R5o6!|PfTmy^zU=KMeW_#XVMU zDt4-Nof&d>&tTJXB3=)_X_Xr>y|$;jThp|S)p)KOs~5nOk{$CxTYOjsAoe!ZzQI4rM&=zD8O?wU5i#Hs#EiFkiH zPAoxKJmaCBe-CeZySPPKg5cjGjfelZ@02NGX8=rQ za3;WH2JZ!!%;0?hlNp=^Fqy&o0VXr}0KjAhXFJ#*#`uNpL15SnJ_HP#!H0oiGx!KF zYz7|%hRxs{VAu>k1`M0Q$AMup_yjO)2Iop9U)fuLGDQ zdOg4-(a`{tM8^P35*-ULNpu{*B+(lHCW+n%FiCX0gHfV40mBl#85ox6Ex@ouZv}=W zIsq7#=xxBTL?;5n5}gDLOZ0YNSfY1GCLqx}fnkYG28Ja%1sIm-RA5-5cLBo^o#q%J z(a=9PJ~Ak;kKAF|Nt6@urbp}x+l+{OVaxDlMywjeH|86z{C!3Kw7oe({q&8wjZDN# zb}wvZ2}0Oe9ver^5`+lAX20T?R|H`740SeC6kxMgam-5rSj|G~tBXoliPR+G6$4m# z8GUte2b<2W-iFkD8@HAUjOw_=#DFmiD9mq40Ator7^WmJW*LQHN&#b5QW&N*FlI4@ zVafobluP$k)-l3kPC0yitm@P?=fo4V9#bUZr8$q8UdUs5MQl$H-D6wX%c~x~YPfti z2zC#C>CA9%My7jIba(69ceBhx?U@L$S>vJhOa$00@Q8U;05+>TVqR5%)ySzIcr}1& zL-y(bs}~}DbqxpmVzx@!)F#rU1VVU<&Z-0j2=|8o(6bUze~A@EZW80RINS6yP@k zOaXoqz!c!$1egN+W`HTczXdP__$>fafZqx*1^8_a#sL2|FdX2w1H%D+2QVDqcLKu! z{vBXAz`qL&2l!pUaDd+p32r`zZVz|@cV$_0KXp?4)6zn;Q)US7!L4< z93uk!4Yj`Av+%@2tAvhhfDa_%ec%H8kwO9f!-!R*NW@z>Y{c1{Z@RZY6z%zmcx^-? z-gp<^%~JiF+;}21dNaVJ(OUo}jou0{X>q|w_XY&AL&VAAL$fJvjb156sd17OnV zodAYkSflp4 zdRhp{&SeD?@g8?^^a+Tg6}`DdtR6+KRk@o-Jw0oCJy;0r=UTN9iFjEqkQ$fOz>OzX zq{f721575oA;4t9a{wk2-Uwha;f*D1O?VT4$%Hp`Fq-gYz_1Cw0vI;o&4FPP-U1jl z;Vpq-6W$6KHsQIzunBMN7|}V#p6;?EyH$^j|Lh#WM7(@Ag13bcyrS1GV*7#U9Erc~ z>3vc6P%Tk5CF1GM!4|xu-#OIB3DY?`xqB5ByfeUL!MgxV7Q8FKWWl=uOcuNVV6x!d z0VWIH!@+35dji82yq9DG7Q8nwY{B~g!xp?RFl@p50mBx&KQL^;2RKG_4)6Yro6ont zd$M?dcH{^q;$7uB$Dl%;V{pXw1L44L%znSl*?~PT7G+xp9!$jh*bN*ex_{zs)eaoS zfqx1xMfcADrs#eQV2bXa15DBV3klok{w2T^-H!uI(fuocDY}0RFh%!o0H)~vEx;7r zPXJ8O{X2jux}OA?qWkv_#_0Y7FdW@a0mIS#M_@R*p9Y4b`x#(3x}ODxqx(<5aCH9} z7>@400K?J!SIGpT`)|N-bUz0SNB8r@3L0K?J!Psa!cUgE(1MsFu|2aWoP zcx?iSc>g$w{tFV#@GeBG8ihnBT>E+GhRY)l|EENQiFmW5MDKTZDkS;EV@B+$CRa~8B8s-toH7wF*@@J6tgyRRD^h)xLz_0-?4GbIbGQh9_FY6dF%{ecB&&NlG_W1Ah zK_U?^&2^7-=pL0kFJgOw=pJuOJoaA2Nm;A@Z}(seo*^xGMR&Ktf>#3A&VmDMXTbrs zv)}-e1+NCModpNj&VoA_EqF~}*n(dqnScea1q@s8+Q6^{zZe*{;Fkcy7W`6R*n-z_ zjOZRK^Q(%r*8)rdew~9cz^?~}1N>{iaDaau7!L3ofZ+iD1~44p zHv+=}eiJYp;NJv>1N>%SIKaOpnLvQw0t^TEt-x@A-v$f^__u-K0KXj=4)8l1BLe)~ zw7;*}ygk-i=*R~6KqB6|ZY9dDLMu^r$E+GfBHsGUwe8Dx{}U1i{6xGqkcju2ROvZ) zvqGik0Vb9H4lt?o4}eLfe*#P@{Y%1DrGEoVD*XpwQt7_{lS(fDOezhP5KC?vkxG*Q zCY2@wOezfnOe&24Oe!tnU{q-o7*=TtFs#y|z_3b-0mCXS4h*X_6&O}&3>a2v31C>I zC4pg;mXb_BrKN#km6id9RazDpR%tn4Sfz1bSfy!>5s7#=Cx3VC>&K7OmMXm}q;p!W zlqi;#FJafCR45_Wqg3`XN?1*XLPI%Y_LUo(r0lM>L#{^iMwpD*Jei0$ri2k>lN>)0 zZ>+mrA2x@a#=LO=n-flB-VFdNccYWeZj^9l{rY|;-gv~#(WWu)CdAFbrZMkk#FdrP z<==w1In*@f-HNz5(lq8xK-?T?8uM;LT$yTJ{zSyhVW#RB9mLI1rZMk!z}2ytCMWL> z#MRq`F8@x48_i~BnyvHAnuWK>#_CbOZY1EtQ!RL2z>Y6em!quEe1kuq7$hPoFili6&j`;ao(&4!wVl*w>5 z)cr`AEN4SKfRys~bn~+vCG7CxH}B0^nLGX^sbT-bC{h_o_+cmEM?k`ryhlq|wT422 zS;BuF{%7i(tcCZ9!ac3=b_IEXB)yR-LciCfhzQh#^m{G9q~B2hlYXz0u+#7Lh?9Ot zBTo7qgE;ATEaIf!afp+CZ$O;%dn4kc-|>i(es4mY^m{YlR=>9(PWrvo;f3@&0V&q+ zZAh_xCnClAorDzY_jaUMzjq+T`n?k=*6(DX0{WeT6zg{?Qmo&*kYfE#LyGl#H&U$M zdyr!NPDhIMJHt^Tfv@@(zg&@C=B2$tVwAwAB}U@CFU7{+St&C9R`Bjmu{sTf{#C)7 zcC4sdZPuY;o4ed2O7@b>maus;f$!g_)vrl~x)4SEnpCKetAT$t9h{W}u=0dD6)M@m ze*aYQ*PfgeMoQUVN`{Ic#b;*~LCWM@nPD^PC^0tXbV~f*y{I=`v;a*NPzzA=7IV#8 z9GbV1mzrW*QZLYR&AT(V#dBxhSO{t8^2WbvQLKCrOq=inAo+K&gSorb(tDrN$b1FzJpGOYa*rIAE>b|LW%KOYlQYJGIr<}{4`?eLaIee7d_qJQV zWCMEN+pOHTbtkCpic}TH*^O0itwgoC6-*!l`eA^?%^6h{W%eNy^EZ^x0K5+ZZmSw z*w5uYCf;8EEkz~;?sEb*%OUo=d$sY`EQdG%u-Up*ZF>f=dX_pf>yU)CfX(@9hY?qE z;`;jc5jQ)ws-4deSC&R!f5hRw0Mr|nx_M*uK151&WuiVp%B<-yzdDMPS=V8xkC8HK zI}G&+Qf7UJp*{slNm^w(8tOBol&Xn3<|yG)_b&P6_7|hotICc-uL2@L@JrWKjzd?e zo$q^qjHjD<|CTy0^S(!%_Obo}aW%f`$A1cO+R6Gy#MMidzW%hs=~aXGvOa?pZ)SZKDc;TcC!|zh zp-1>LQoNt_FG!j79;Q$HiWKi?{TothT%o^p&QYSf#QyAa&Db9=Z6=E`Z4x zOp~xP26rP)#^4^r$rwyWoQ%N?#K{=UM4XJly@-=BxDRnM2D1<+V{kv>WDFhv+!}+~ zh?6mR(BXxQ!9z%~F?bj$HU^I%#m3-Kq}UkDL5hvRV@R9-x?q~G?4lYToOPWtVLIO(?&;-ufsfLr}`L7ep4)!~Ko z+YKq!Zvj%Q-|k4UetRIr`t6An>$ewDtl!>9v3~mi70_>Aq*%ZGkYfGzM~d}304dh* zl}NFE2O`D#y$UJT?;uBsd9^366NM9C4`ifq;sO=M>kbc9X?|={Q>NI0tzai&j zM>*g+3fua0u=Sq1S<@vl)khT5Rmvkyw!Q-5Wa~2!CtF_;akBN55GPw-8F8}pRUBT( z)>lP}ZGAPQ*w$A^ifw%jq}bNiM2c0kz!Y{4Jmd7ZzIL7U^`Om3U(mHu3)F5gsb0o`C~&${!r&5p)u>~0||<|oP2kK zd^5cFqE@LwzHd)l|7pV!mu(Y8TloeP6#Gc|_H}nEP6w7x!QY_z_kYf4X zj1nD5cfs}N+YD)Vu!hi>m2V(!IH1+%c+teQb*v{4iOs4*jgq^8BjJTbxN8HZVBW`Ew9bU-Pe~1*D`j3!e zQ-2gGHuWDP#isrfq}bGd3RJ+ z)+0`~{uJVNwjOaiTkr5fw*CxKZ0pY=#kT$@q}bN~j1=4YUyx#3|0_~#>wiOvZT&e% ziSBagT~EK)ap)$PETE4&BC+ug*IoWB)Ls56Vta-#27{)r>9w;;v;Us04<X1dgJDRqF&K^%8-o#!62{=xv<bp`e{4jir9PLN?v-Obl__$Q?6Yge( zg69HE3Vsq`Qt(p}b_$+{I4O8O;-ugOh?9aBB2Efkgg7a9G2*1)rx7OwKZ7_acnRX9 z;Aa813Vsf8Qt(oT7gF#tq*%evBgG1S0V!7Sa->+nFCxVXehDd7@XJWCf>!_)Q1B~A zv4U43#R^`96f1Z&Qmo)LNU?%nMT!-?7AaQnI!B3w$c&eByB#^RVS1bkbiL#LZEbDw6T;yi z`vFzCuA_vNo;vyEhfmKd^03sgZ>33TB;)!e?UK68l5$C1B`>R_Rji1`z4uJ`c-nWp zAg|ev#rc7x$gE;g!wri4w}!I;w;FDUIB7Tsanf)j#7V=A5ho2dL7X()6mimUGsH>5 zS0GLrZjLxE)MrPa?z95F23e-F*;DrQ@%`$ z++EaZ*yKFDSG16ZO(tT0?somAZ(!2u)Y-y_Q~K#=h^wBZoA{W+X&B)A)6bFO z{L?Rx;{4Muky7IgJ(%N;5>1@)XYq+euPr@Rv_i0n-Iv;LToZp=sEJP$wXG?dxWT>8 zt+^?$nbb$Hi8(p)dun3kW=t>s!QHOk#Mx@(*G+Z`amqja5piXt_4TJ6PEE}Dr)Q8- z?-bNnXMs|qpUpr02`M8N(~Ez0lxX6OW#M`KSLn+;8HBoPT-& zDI*lqSRps0(yuuGGzlpq7xSxRM~Nn$*04##QU&F+L@NY)u}h9D;>O}AjK!6_lw!6u zMRMfw9|qPL{CV%yqHs!%%ooX#52n~0NJ@@;$gR1ugz7CiIr3pg6i$wOq!6c6OeY^c z>Nv67;;CNMZd@^b`7v>ewA{kKMH(j`cZ;~5D71)cZi=mGD5Muz(ktOV7ycdE>HPEp zQMPxD|4JB4j(pRf)XB6jgqz(9ECncfA$$vPYbLiKPG)i|;$$YbAx>uUZN$k;ZbzKV z8VPOn&AlF*Wel(8K2IzbI-{xC{6K=_7j9PPOPJNk@Q#MVusj0dbOW$i)r+?=~O_Cm~J} zPDY$097dcZ96_8UTm*5Fa1?MW;S|J4!bK4$2^T}0BwXC#g(RGc6iYaU6ic`SQY_(; zNU?-VA;l6d4OBqFWsqVCmqm&tTn;Iga2zR?a2ir9;dG=}!X8pA;qpkagexG$63%dx zkZ_me9!KlMHr(*v66Pey%FgFi0iT!QRV`}OD!!$6t@G)ioqs;^uqc|orRU2e$$9)j zXckk?cQ@-qY?jC_09=V!oi7*j79y^mr^Xi{Zg$m;d5aNO^X2;brx7c+fh5LZ4@ zU%$lRz6jLYmQ9p=7Ae)8DX;7~q|EveV-}YpW!8`wY8g;U&?@QEP|qV}R+1R%1*FVk z5<@LVN-3KPe9=+DvzBc){O&hby)s`sQR`VnqT~wKU0#9iQpsCc)bN2{DK)mx-`eIV(Onjvc=oZ9Jhqrj$xiNO-PmFlRd)v58iX#0lR@Z;I2nX)h?7AmK%5Lhcf`pc^gx^p zLQllWAoN0<3_@?j$sqIr+!}3k!qtCfZpAuzzejZ%DNSNHsZ|cUi zy$5g7YW0P2ZF>N>CVwyDWb*eRP9}dp;$-p`P$$v=z~oBa2YVw3*? zQf%^%02MI#A0ovj|0AT>mLW(W^&yEtE zrSDIho*VGdfsNvU20Dv#_`kW%a;{KkIiF(tg>d+1zsMN4vf9$kqHOE%gGrO)!QtQJ zoQ!k_Hv?|n!7YfBJGd2bat9L-CwFig;^Yn{B2MmL65`|zZbzKl!5xT`JGc{ZatD(E zx9(sH;^YpdB2Mn$F2u<;chirv9k9z=@W!9z%~J9ro=b_b6j#qQuyM+t}j!{cvNz2vcn zMhl%;haX6seB3$wCki?Ixkas7g@i|J{9{Yj$lUXyXe;4h;$#hwa7}lsQo&1aXq^rHGS+>mW`Nz6^1a@a2e;gzF+s5>5baC0q}2l5l;*Ny3?k zlZ3MzUP!_XkYWjEBgGPKh!jgW2Pu|tBcxcuje!bCxCv4$;igEjgqtD7621Z{mT+^V zSi&ukVhOiIiY43%DVA_9QY_)tjuH}XRL~;6q3h;qLT6UOf#k`2C*ih*B;2m3RjZhm zU2?8!$4cuO?G#1ZX<3;(IS&l}eCHXQi2Yf7z^%bwh&UPiMTpy3e8lZ6KH_#3A8|X2 z@9;tf|5>Ei;6H~H8~mk6vB6&kRKVarj}#mH7m#9uzZ@wx_%Aw2Ov`p!S*iT%vqu$( zCu(Q$MFQmtXWCu?)23$eQ*6%=-R0<U}_-`V`7JoBRZ1LYhiY@*Yq}bwb zMT#x{Hb;r>va0vC3%6We@@nx!gWbh>{2i{l>@3t>-bt}NLl}gXT}DoLZ2i~2i^8oz z2qsW|11ojDbt@9w*kWe!PXKNW!gq+1K{$yx8HDcoJO1s z!WqQLAe=><48l) z5Q;cT7=(e-ivM`u#Utc~#nvDMk|>M1#EoK*xRK!%FKN{p3h9M7G>d=FwjqDK8=g~3 zO87c|79Wx*8$tqBj=Ni_;zod56*oqlRNMq{QgKtnNyW_&Clz0TIH|Zf;-umhh?9z2 zB2Fr9g*d4=7jUcM)`*je+aOLV&O@A3obT{LDsGDutGFFftm5`av5Gq&#VYQI6sx!s zPyrQpMv7J31u0f>SEN|Q-H>7x7a+wd?v50zxCc_K;+{ycihCi&D(>wlkx03I=)fOe zott$|NR1LH^JOAsKPTk=Amqy4fRa|Tp-@{Ea-(m{9Da1j@A9}7uY(bCTbW3?f^?iy z-%q4`#oe#3;~aA!Y0O)RxH*nA=B+|p`6QhvxEgVD6lu&`gSa_}H0HgExH*P2=B-6s zSwmg^I>gNpq-x;@)Qg189dEzwgO{@Ps3~j z#tfi_c^eorgc@c$FlG=n%no48Flv~cz?gy5Fz*0khEl`43yc{|4YNx!D!*Fgvl?bM zFlInC%zMC?A=NN@fH8xrVfH#kSmr?$>X$0_@SGQj>UCekuqfbkeH2RE0Nux_7N*aAuqNLI1BuW}xDpAttGKYdj zpO*w{^aV)-G`buZ*654Cutr}3hBf*!Fs#uPz_3PN0fsfY5*XI#DqvWntASySu8~YY zqpt$P8eIzvYjhnjtkLz35s8rF?{9Vfz|(!;n|S|_l@SSaLvfp>_eODyEgpwoW1I;c(yY zItqA;pKk^+w9%s+lpckE6sG*!PB`6}N8f`q+Puf$Ds{Oq*-k-!<_7 zXyQuVmBnpqhC;upXG8BC#aG|FZD*Km>NPS!xgz@k+0Xq(UH#By=P+5tXV)v4Nn7A}XjTDvG{XQ9%^2pi*ogq9THd zqJnh6h6P3Vrkt5GXO`~|`I+aLojdo;IrB`rGg;)lVJ=3vmY$2bQXBQE1fyOZRQ7Y6 z#c0%FulssWy>^RrY2l+_)T)Z&YIXG4pfvSu7<@D~SnoSg1e+`4AB_#sgs>Isxx-gs zmrIfSLNgZk9AgQBl93=H} z8wW`pjkqDHS5Oorbqqy8Qm>>aNa|G-1xdY{q9CbbDGHK0PNSBjj;91l>I6y{k~-01 zP*NvZ3`*)X7K4&{t;L|EPPQ17)axt;C3T9$prlT<7?jj$7K4&Hoic``UT-ldsW(^* zO6rXkgOYlaX2>MdrAl73^u{8yYN}`?A=)c@^2W7| zC*Dc2)*)(q4z>t(imH+6gSt7PA^MPwt6r~-t6r~-t6r~-t6r~-t6r~-t6r~-t6neS zMu;w@sOt4nRP}l(s(QT?RlQz{s$MTeAw-|ns1>5mPy$2rSxOio`kcjJh(2#I7^2H9 z21E1(i@^|m(PA(}U$Phs(G?bhA-d9HFhpOr7!1)>lrci|6^p?Tebr(xL|0o3hUgm2 zkPsbo{P}6UXDzV~xgR8DG#@|rdR?pN8=*$4eN7h|7sri;BVBEr&Fb;= z7u&cvXfzzT#KxJ+^Yq;`4&CZb`g5;Kk&P0gW%cm?r`TuR`Psd>X6TK-%z< zlcihAi-Ojjr_jwZzt}lowc!V~FKhP@-K;}44sG~h8;3Uhh>b%Ve$>XH4gbl;p$$J~ z^J0#V)RCeLX6%-QHar-HEPA^ z3`$^(&ZLA9qqkTL#^@}I!5E!wF&Lw_S`5bMZ5D$uI>%x#MsK$mjM2FkgE4xC#bAuy zNf{$X=UEKK=v@|rF*@I3Fh=jz44JN|?$Bs)qrzJokwAid@rC9WHw$!-F0_I)D{@~@ z#iQfAgB`6)vl?s*zp=&Q?(z4}Z-@K6vSRRA-NXFGW`XX9FSPpM%stYSCy;K|y3a=a+-LH}e@NbH zsBC^VQPXO|)3qyW?-1RrS~d<%cx@YpCOpH&p$R|7#-RzXW8=_-*R^qI!t2>MG~p4% zjV3%wQE0+5DGE(^jH1wlXHgWI@Hj=G39nC4Xu=z4)M~;TQUaUsMwBp`@WvK{O?VTF z!6rQ0Vz3EsYBAV^pKCGLgg3JoY{Hvc3^w8CSqwJe=UWUm;Vmd*G~pLm3^w5{Ee4zL z3oQnla8EO&o3*^()$dir9z6SOmho9cYu$pkv0Ct0q-{_|BMH$Tx*qy2_18fKXAM#F zvxv8`0T;cjcXV??Lv+23Lx^s$aR||kHVz@W$;Kf>-?ecF(f4c|LiBwbhYQ^p9<-4=r(`i;e4h<$h2phI91diFOas&AQ#jp$(sF zo0cO!1J;rCD!+VFcR3T^lTib5N{kfP9r z-$zks!|$gkwBZkE)M~>QQ3BiW2Pt8+;SX61w&9B{2HWt5Ee6~0M=S>0@JB5M+wdh8 zgKhX@7K3g0;}(N$_)?3(Hv9?77;X5I7K3g0|11XE@MRW*ZTM4~A#M1hgId3K>+tVA z5=W{HH+H5!s}~KQOIS2~zNU&sw%CBPS;_NKpD7Hdb|+a!ddb-=YiIfwR+R44rKM52 z%f=x}zqE0P(yweBqV#JUhbY}`;}E6a*f>P#w>Az@x(9J1O24BhMCtbwg(&@jq7bEf zDGE`#kD?HzKT;H;biYQeC_O+4jM9UYFrxI3#bA^kwit}kBNl^EdemYtN`JB#jM8Hk zgHd|iVlYa7wit}kUn~Zr^jFFlQTm(3V3huDF&L#MEC!?W56zIB=Y^m7Q(lgY=tM#Z zcAgi~o#%h+Ks{*%YW>JRHC0SH&ZQWrca7zi49$Q? zQ5l$lizwRJN#^BkMN#JBNgQr%!R(7r4!5!3HsZRTKwArL%N8wJ>UI{~j$QM@;Pw{G zK8EFR2Mt57kniy4YleZ27SoZNS}>g~M%;QPn9dd>EL3H*3DwX6=>o&ms*Ut1WhpAEk;~}CYT(H5f`BeCf8!bRcM0Avlww1 znqcxN!@hE2H6xe;i(%X8fGO0Bph(@J z8|Y=-q1!OfJ6T1eJ`{tZ5D5h&AT7BSjZ z+|?Eilv}X4r!5@lW5ME%ws4@rg2nx8;XtJYi@Vvvfhr3Y_p*fpeJz-Mn9U2=kHYNp zs}v4f_jk9G--QIM`@7po84XzXcej%|8nEu~W(OMayR`z=_1)~qQW31y?cMF9lm@KJ zyW2@E4dC6~B3Rq$&qD%ud$(k?ng;OxZo#k*t>F8R0N&s&8Lg%Pyu({ET1^9Zi??L7 zng;M5Z^>vi4d6}QlF@1!umF~m zSq#1p30T*7vyUWLwTKc}w|IBZY8tRE@$R72G=O(_lVH7c$C(?}!MgO=4=um(O=w5*uRD(=;Eh4GxB!AR1(nWBUuxv-V2vK- zIUI9*UgVwNia%4_!_N%9BE(QJNOsu!yIy2{uyK=HH}`t-r=f~r7I3ozUSvaX!}Xhg z>AxnWD`)uf1t*fd$j0DuXG5J+*S>lV5aJi9USv~n#pJTpojx7?Feli)BmRS+7kM|h zcVf-oZZ7}m0LR%34#&e@a>L@OiV?qQ;zd3Rp4;`EjHZ>v-9%Px`45_Uk*&c=f4s4M z;(53B=06ad{W)`<7x_4N_lK9}9j)&0o?=8+ExgFK;EyAd-^$B)f1YAQZY{mYC&9NG zZSVHrlzPh*!?fGY_Pofa!Dr{z`E2T-ZQaG=1>DMud`8}cuQT%W7kiQI!H*;BKDhL~ zQFn@*gh9G_kFmv*n2y49=B4;AVICB0GXN2j&i0<)j#hAjG_q+>)_(e}I@?~&kZFj`{ zS6|QN1h_#jFY;Be$N1g72mJi|R~!d7DE1;>2glSqG<P2>&ZjcLZ zQ0_&(2|o72p4V!Rz4B+C4Y)yt7x^~WXzy2JE9M(d>@=}u+!LAejeFIG2-1uc#$81ZSOuW zc}bri$BC>u@~lRAk-esaPw0do-p2v90*?U{Px9Hu4=koJf3}Z>Sj;$A_q+e$yE+= zqZc_8{Ick&0bAC0xliO&!PDRDMGgn=f5HFd=7A^p`{hXo@n_Fu4aJe*<8$t*JT1zW$~IilinMX@*WXWz=GpMon28cnGCRZAZDdD2Jx*>f0kEI9sn z$$Ra(SHyr3znROJWEf|{LkGDv9!cF|ycQN9Z zV83hLZ1-;VsOjS6JM*XC&G27MN68b8;?KU95x)f|o_k>Hl7siG5NKB^AG7p5f1aiBbOsKd!8|?DB)(ej*DYO1F{` zr^q`==kRB*W6XcS$GSdM^4!#WmWtdecvf#S{B-c~oBy}8pn29bhUY8ySkIUT0U?H(H$<%DvcD6PM9OgpX$f)XWomr=fux~`p5%01p^j2r5c`qd3Jca(=$p`=Vlo2VRHkE1PD$ASm*vtq2*v^R5(6*NM536~!#g{TGVdNc*NDCR7 zlCS;adqxFAA3yo~4bLYxZpbs!{;`))p-}jrepie?c79ix9c$tI**`KO95QqzU;D=) zM%4&)=!-y?H{ukRX3zgC{mQD>suLBFQiVR;gs@^IgE*f z)VZa=h~La*Of;kpspO1mJ{XZ1QkP$FLNyh^;%=ZDl6U!2kYv5`?NLTX`0 zK3_DV?=s>7vw8}Zcf8M-mLav{M*c)N$A^r#ko-h79*popYO6edzG^%eaZyOEI?AkM z1wwd zk7%)DjhEmQV>*Y_<~EU=sLRs~?-Ej<)H==uY~BGT4j$>ypy#3)+r#HGsLlM^j&n2n zpSEg*(uxmJoQ1AV-u~qNsq+F;p69qu9(jNz5JMOC6;TfVZnV;Al^Xf4CLg&l$YD** z>6&FJBW7)m9r=t3@dP)Uja%IGgI_)Ja^;zQtvC)3VdEBm`qXv%T3=WZ zE8@6*2phQs(obFX#UZa?*VCNAhp^F0QhMf=V-?pvTH`TB<-tSP=p{M*k=IULz3p&8 z3y#A>*ytrC{lU7Yu6X<1a9@t=hp+)mYWlH0r8$RNm-7B;9zLWV)1maq?x8WS?cLdo zQTgzYC=;Rd{kI>f)#|Zt&gVEhB*qjdeM;TetI{98xH-r5L*h(=(jR|oZif{)*YLpz zT-(mg)qqJ*y1L?>QT*aBjmY2x-Re^4h@zABx#HahW~QL92TzFM3_owyEn;>u|`d3og(WmS4U+r7eyw+lx+8vK9e;)gomp^ZUMpMk^i8(<&qvB4)1m+{zr8siR#hru+ z%%_Uke38R7n1DZ+&H5%Wr(juMi-h^?wrW1fos0?0XX`_P-0Lub`Rum*jm0CTU;_T^ zcKoFUF;x>}(r3w;?{7Z$xmQmSr;w9AhEvEHTK9S%96R9N;G@S5G<0wDDgSaD!|8^< z(c+zZYOLE#@{drb(=)X04C-{^{>896Qx`qWv z?WNP*imdrOF%utlZ$s96UVG_ubC5Nh?skn5r|Y0rG2FSBzF&Y==Ck!&raK=Kn9uI0o$hW-K%MR$O%SKMru#X){~OYgI)&wQ zYNpX$sGaV<1gE>-r~J!tBG}TUe)H+KU;fy36Lq>6Y3cM?4DN%}>Ew-#?nAoh#Oc_# zb=>I|BWs#OEHQ=Mhmkd$?h!=Iis&qz?onjTT97Mo?h<6p=XI7&_ZYH<(><m`K9{9{>3R1_OhNtbe@K|G+gh~jqDfkYDahkR>n>6}g(=A6 zMGG%dJdG)+>pi0h;(C{zIQ02TPc|4pT*GobbzFt}ymr0i39k2oPkEW+)JNBISA_ob zKXpzS$v@JFxSqbO+g(9jueDs6a#!lI6W?RBaK4w3CRUN_$?hto4exseQBoa3e8TRl zNRzq{(i3)9BTXJDgeUB-LE3P@wHl=ksIS#^U&9pSsiJ8Y_4_)eAP*MJyGZc{rl1b^ zCKBY0MJq3Ux(-v2$Llp$_bp689xqyZk;mJZf;!+knjj81V*aDIZP-(H2XPR~0o6U` z?ndo^n-U!GU7zwbhh4d-hbl+YSGS(C=FWj6|45p2z`U}OlA5U)j(PIcH``3vF?%TS1i3q=avIb-bnJ?>pY^i*tiIdZr(DW$&O<*d zZE^I*Cyo?%Cb>s0kbYKFT2z%^R$8Dv?QdV2#N`k-rdsY%W?$lXH z@VWoaN`lv&J}U`+cjl}lc%I|xagp(!;CsHalHh&rSxM!8{;FjYgC`9}`&Zx1V{@%*(Pekc792ejYQT4e3AXo ze)O|uEI;~16XXNMw90;i|L(Qw8dA^l`&FoC@S)#zdv?NV&$8So`)JpqM>jWQa<5TWJd?+-mUxT@g&p$}=RzAcR^tBI_`qIST z+K0+?X%zuJRGvV95A{hPz=tXl2=JlG1Oj}hDuDnW>YG4-5A{nRz=!%L5a2@t5(wo( z0}~nWp+SiZ_|V`)27G8pA_G2jSt0{IG*mN|4^?Y|_|U=!-aY@s=GKQuJu4p)^$I>T zLi^Cj1RomZQ|{t8`%ufKcX}=Kz%42LNZyeHQp>6eDpAWm@TG~rxexJAyxb3UX%)ft z%5h?I0wF*0a$3!oc~VdwY~*fFB*lF_;+LN%lH$@HLGDN-*x*eIkIw^FbBBM*V=`4C%DizKIJWr^O2*6fG2%_|M|xD z+pT738%xl$BCoWt2TXnWQj_cX(hAsGe_4J(ey;GL{Nm*wO;A#RzUG|D8PtZ!AW6Xc1HX*j2ERassc+bEdE@#7k= z?4MJflPfj@C;zNbC`c|F^|RE!XdFtCD@Lx#ziM0-CD-xu{!QFBl&NYO-)e~vE-A==8iKG^Sy4t z9nqFmKU9%?BcnyWC6!eL<+>)qzO2HHU&_!qDPKCrr%LNMoADJEUDA2U9Wx*Op5z_bDqexDe}eckUuw$V zpu9lrLQgh2UFH2tDhHPGy%1uaFWKmJRpplVtdtd5AYIMqdC8jOR}~~1y)MjcfRpBD zoYC*%zhKpz#!&2Ykq_XSci7nE((}G~ki3le0FD)%zYN&vLTx9{vQsSiBA+sep`=y=wSLlj96_hW=wJrHSU^Z1WhSTjl&Q#QI&yA)XjlKs_EY=uecDBB^71RR0i#z0 z*?M%2h?3|SRY))@50dDW3M3)EBV*I*;eB`2BKeCDhx}#Hqhle&qvKRI5aQACs)(fA z&-#az^}l8{jgP1*_W&&S4Mw?dRC$}_zDa?k-1oG2^!?>UMWtsiH_IQ&JyVtY7L|=E z_bgRJ$Kgs0dqui*t#Nhz$1kR#5FIM*T~Lyb1%D=(n zl%N$1=AW2EKhv;`dagmy?Fu9oTk*r`=^GcUe)+5x6E6l9`$Ac4r^-iJY?m^Q&0E&o3;jLW{i_tTHUNPGv7qZLzl~ZdmMXn~@fKhrr5W>j|nY zwn4+9bOoiNZx!9BVK5}O?j{8iL*Ci^n_FAm_Ss+LeH()7iT4FVzOM}Vfyzf2@ zh4Mx7G*-beu6xmZjSb)!`)Ds5EznqH9_yoWs8B;WIhE3PduRyE#Y8dMQ-P#`x#STq z5b3;;er~E7M*db{t=`I7#VQ-sz?3M%IL^Ijtw-*i>N`2)rs<>_qW6KdDl77Ipgs~T zVot=m>rM@(=+Q@2{?N+s4K>jv8th+DR8>$tsGy>((g`qSi$10){;sS8z`@5ANL=IS zlm*`n{N@y$YE!OJ#LEOP`=ol=|EYYGYb;am0&^H~Ds8fIg9 z8*fa-YtB(Q2MhBHWqseSp-R@B7S%mhLq!#pvbyikP=0Z)tnNECR8b;hZk|R4_>igxB6SbVD1Wh_ zchMx0uadg59E{rzLH3uE9Axj;QDv>9E}4Oy6iABw>6Ggy=C=Ld8$HqRc4-BlI) zVwH_5_9d!>q-QZ}<(KvMH1gbxI6cyBn#UYVO`55=CMiak|jql!IEmC$j9V+c=rV&=)`PqgSm@{Nv? zAzWF7UQ%wf?tN6=M(bXoF>Ku{HHNKwmBz4j@2fH0y7$wN3_pJQcC^0+bMoZ}w9x?w zF%{rnx1yrP#sElMdAw zG{79JRv@Xohcn;LZrrlg-^9qe@|cmK@zBUl{ZS&ljA&zmG@@nt!=8a?<^qs zMxT9Sc*5_;mY7|lpJ!H)jEe=FZ!)2IEV9!dy9|Q z{9bgADjwiHdHR4C{f^+wcnnVRqTib^8`N+(*^B<51}Ea7ynJqUiWl9hT%E)D0|cDv zMfa&80f$+$$Wy0z(H~Xw$ziT#91nWY{YvyW&O7!T4|&l8s*BEX-hMDR>_rc%W+5!y zjiEKX=%FQfA18lt{h@X|G4Dh1)Q!C8Vb$4^I1?6zH};}ORBx7S?OpKJ%oobKy}OKV z?NxOrxAxA(O8qrD<<0j-+%lS0>O5Ylg?WWNWdFfU4fPLJR^?Pwm6sLgh(1>cLxFW# z1XnLXATh6g&qxf(T(qV1R}&CYZP67xl{# zeU*@oiXem8cMCZp*h0gUUj(ZviYj?en~xqs!!-(cLV>9qWZ!@%Gm|r1M~cAP z@l*N*K8mDgpT0x-%L(2=P3?w8E8KA^9o_dm?>GP9C8zq)Z5Ivuu>`U%c-*=vp(`P7 zLs#9ge*2Kk<9B*8ZZktytJ-v&$(U{N^x1o3iwkpU6;Bn}GNb9GrO@~w`-}BtSU)y2 zL6uO6MG6BaDp0&W>jlbfB%w(PC+*PHH~Q;UOfP?sJXf|uh2pvJK9kk^Tu0w07Mh}p z?l@Vvf23CP#ms{Sm&29ttBP=HxoM_f@=dD zcj8Rl2a&&P3mkXk%+BgvCD#r(K9+9@lIxDSITt&jt?#}b!SE9*%3HCr<-{R z{aq*E_%RQe-6+=?IDXbc=B1Qt-3mx9TAAG~Qdx%YT*}1Jl(d>M4L_aD5^kq=FJ7O} zMa80h&4_z69L5retfd)@<=V_%;D4FDssCkX7Asd{d*RXl4kv%Vy!yp==^{xqRrz1_ zfLz%@s&pEqW|q~IF9g>2d70(P_F=&&>+*)g%hY`xNh<3y()BWRr$>^?x{UODnY#BQ zNo`#&m6^I5BuQmm_RAzMQ}>4?sl1Po$zG=J8A(#PA0tz|Ox;70r1C#Trh1uLAS9_B zkg;iArq&5yl?O65=w)iP0M;;4$jj8K0jy!Au$QUz16adMHM~qMBq+T#z09HN<1qOf z^bsz#4ZO^1TQnx+P)O`Y8Z0R5UnB(jQ^N@VZxuh zLxCc?+iOwzLg8d`eC?Tlx9Rr#=}{vM`Q$j8-;hQGS@}}Q%2zb32))$@u`J+G=_8r8E}V@CC?(I8gOS_4zn^P0wt>Umv*SUqoO46El& zjTzOmPJ`^pP(5!Mn5v$)HD*-LI|{U_M^7!1>KRpV?RVGjX>cC#ajYJ0M5vxks(RkF ztLHsc6OQu`t5;~&7ytdxf}U4QwWhirkriK7nb(^2>Pl1%C3WCknZlyd0**R?urHj1 zf-ftDPhll#rH393T<4giRbJq1m04c%n4}e+9L(A#aNpGZHF~{B-2 zCGg@&-RO%qOuAIPBYE*}2Tt!^vF#Myq8P;&Z$n-@H}S<$m5mqIYHYo@7GmqgwFZ+H zf96c%%G0%$UHbpMxGWpIc#(SXUiORkR`2LIFEFD)jX%?SR;$ps^dQMRxEGeFj%Y!-f*Vq!C{asq`@zO%n?$4P;RdJyKI6gWv>Fk zNYLL+*{5*FS%c-hXM4as(f7|gX?b5a%4;<7DSxXnSM$XXQRN zt~)kNaec}NWJ-AZ<=fhQ^6^6rNd9t481jd_4}goL98@{Wp-ooGA>|Fk;L90a zdW>WoHBD|b+bKu2$@y2c!sI_GduWq$N|^kZrj*G!B}|U{EDV$XtkPR1|3%>>a^@8L zv;V^tKQ<;MZwO6>FgY(dnB{k6mJ`%04O9M57I2&g9UVCXw|>~bckW(#9Y^$GmVno1 zMNWU!PNsauOd>6TdR+_#K(+2)A>Ug|wHYK@r>*zaD`&(N(vF^fV8MjjGU6FY8zjWb^I9NPr};c>$cD|O)XtH{*f=vzqk>D^jG~2h9^8szDpoE2|^~2 zq8}tfrg0!ONtN7jPU0YAO!%HJcV5$IA$dad6dz=i=dsB`Rf91$wk^+--&n^`;ut1( zfyT7L@pN+cLrkk1$K>XRm{vB9$-NITW6WBfCwD%?jInBYp4{viGsdXpd2*j;%ov-N z=gBReF=I?xo+o#A#*CpTE3^D~CT0vl87TL3#*CpS1Lbzk7>XNzWx10xrp1lFOKZ7_ zGp3bIfUKX%^dP2XEtRL#U)9F+&{E*~WYCyi-V?Y!7c^F++(h8|RM1#26UQ?_W4#Hk zPXvwWbw8d@8+{&Vtc0Z3r-8;w39ioqjg=8xf0Y)~gHMsaJ_j_W$DIP#r+~)vkW=9L z4A7V!Z3HpEt%7zEYJ zCI&&Z%ETb3UNJEUDjYAT*5x89sIY$*`%DGZb~~s(SMfuFYF_PQubsDKsI`IsN>x~_ zmk?q*jiB14OlAbtmnH^5^_7W1PRBv%oQ^be~z^7*yD8X7AMogGzUsMS2XXUrBi|sD2|j z2G#Eb$Dlf4;zm&YL2wMJKNU`b>d)haXSPkL{}fRa6;#~$L8(rvp!&xSs()4dkf7Q> z@6H)D+uT$@@>NR3M+Uh?Rh5pL8k=JT)$OW?Mo<}hTXgsD4l^AD)tx2=K{e0BAgJy# zF$k*pCI&%uw~0Ye-D6@9RQH;g3aSMJgrHhTKnSY)2na!SKLJ6h9v~nD)glFQCo_WT zL4spYJw$K}s>KAypnBNEji7pj;22bo5*&kS3BfU_9wRsg)#C)mpjt|B45}vxjzRS# z!7-@*M{o?PWhQO})l&q=pn6*2B&bGLJz3K2v%n1E{3@t$SR8v!1=aI*P%T&SLxSq2 z292s;m>vCxolh6;u-ljzKk%;22bs z2#!H@jfopUbuGa$s3sE}gX%hhV^B>YI0n^Jf@4rkBRB@tbb@10T~BZfsv8K7L3N{v z8$opw!7-?ARyYZ&uYDVKkGUfID&qV)sF?GEQr)70YL*>TvsL^!4qt4CsgT^91v74R zCk-I^MjOkC3Z7|YH9H}twbL{;cDg2OW%&kOpBFo$#&{uyRWdDO^DV9yb9}0t0+**A z2E3Thry2#0^BGf?KG}=8KGm(|I1^lsr+P8JPbsrF2T~m19`s@XpFR+mXH(Xftr_ui z;`y$eSdyO36wi>P*lbkOizO41Z6C>J=V0(3*79O037nW&Vq}IFOHClfrxlE>!JrUObTJT+fRIEk3UwJT>aYLJ6FDYRrp;6G-*cxEHHINVXK7Q>-7_z>C!+ zbZ%K$71U27FP5Ib@eloYX`6VlTAC!wq~E>x!JEN5`(IC&NtNHU;*R6=Mu!@>KYVoX zjfdZ(4pqt$n0q>s2EZI7pT}2 z=*p%#=`sS!wmNAj0cB&Igd)Lz&c0G*TWFHBN{ES3)~@-PnHa8>Lg2bxOVVl~aMo2tsR(B*d*Dg3x*+33iYxJVR@aB$%;*(7NL| z70jieefm3R+P*6uz3~^~P7V9A1jZhaq)E`~C0#>Xy=c<4${!u)Cd~E4`?hWB(co_S zg-m3o$hDH4-LAS4f&T^4iWwmGr-?o3fn@>ZLF%i+8f>EZDUFI5XuY>8@U$k#S9V|4 zt#kf@@&hXyu}9(z^dKyNY|aDE1=Q5@^8xj0a_Tu2SRPQX;W*#1UxLM&ys_-~$jk3} zj$|F#%d;*o$tr&AdVc*s0~|(l0mI+2qITW zV+rSts&3Ln4n^78zO*e)EGc-!RNR2$%^O6fT_NDbCzDR{U zg{1pZ0<-+e2WIP>qz_~TZuP4YJI);37Frsdb@J8RtjCFgqIa+a#m3>DFbH)w2l1G+ z;z~I1b&GnHAfAxMNxrz|exynHp4?U3tr|45gY#TJ)})yo9Ot@ClhQRxP++Q= z9Uj;Espicb@wC>@G|w|-{X@B_)7`FdGhaN4^>fXe`Qk~eJ2cPpWxHS?-!BwS77ClZ z;_XQ~)R(S;i-kh7CZxlYQ$DZz6iHz*lxNj#ivTx(Q zqZwIU>|3a?yIz69zFL^v4GJf^)Fi!p&uyj0j}Q|y6uQKYj+1W;&ibyh?t9d__1*WC zA&GS#t2yPBanDV)mq-6s@ItXuy#-;fWNVc?t#zR>or$%wK|`(|zi7O%iNf>#QW0yY^X0 zus9yTpt@Szq0iAjp=Cs)#*OOH5bTa| zGkwa)j`OFZ`&*Z;4W!jxeM4iCfAl0v0QsxVqcdv zmBiD)P48E&!vo5ku+hq0qzp%_`O3Uei>EbjMo&nHf;GwcWX}b~pWK?_XsPFw&nX;E zmRfG(aIn-1HqJU;?2{b#MH`1>rCzdeI8|ze#=)9wm!G>*ftEF2RyeWd&}V0k-qPu! zXNe0bYnq33y{fFa+P3BzWjJEZ%y(=2`NOM+?j{*4Ym$??ehP{|wKb2af+`%WdECaq znm^k(So0Sf2W$Rn<6up_x~6u1acknz8aFZa4D`|(v1Z4nZM$DQanyM7(#o3VxmD@_ zAop+EnkSXv9Ooq#$Pnq%j?P_wZ;Rh!B;&}-EI~<5KVw&id!ZO{iB6~3^X7VbI3!QY zW*@!F;mJivh{KyX!S~p^t&jk>VuN?LwMMOWuZ<>%jCcHfQ^~P~DW8%Oiz9NN#1N(J z)xgc|;8(VQ!Moehuil#&maH=D1W7WPtKe|GYi<*9|QvWp2PX zhUzkdcjRh=)d{eFwcqx!p!Y1(eBsiaJ4y@2Kasuaz5qwS~u#)0sg@vNc2)v9q z`xb!1{A0nuDuls4>??)9D;lNt3B0NaGL!Yc-^W&j4=g-~yo8v^k}n~BC9qac1HNWW z17-$Z4=77G&U(m4vt-}| zK}B9}ac?KYKKjYPiGd1sP8~zjn8s(|%s@qXE=Sph@^HovI#>Rr0zMTT&N$mtK*m0m zlFR_--|_v=InP~7N9AG$n9XL&vA!=QLv20J&>L!Gk0_dPNLhlkEl&)ZIP#;LiiQxw zM@8F`SJ6f~4>QlU-~etO-WAHw6H>teXbC+F6&zq#LeD)h6fL1=oGAm28f$74GUC^7!&>OOpCB9NG?Ktz%QMQ!SDGeQXVLr(< z%1@~&G0v_FcL?@mXEm^`*s%9L+)>q5u(FJ;PzZv1Ot_OKir8wQRNioB4Pt8&?xH~Q znq|(*YvMCkuOkJ5*VO0Fh1GXB;chAuc+K#o>Wv(y2Chr>n?GgM1zR`%Kyr=LVhKvv zx?RP<>Vk@jGVzr}rPC$V{nlTjZytlhnxyCM@vpfyBUX88^@fmuxfR&-wd=Xx`S)Ml zXUO&$)BlwWEN%uo_j`Y%6&d%Pb4T5B#<1xyxr3emEZK8^(9IkpS<8!Ls^{)CNjB@! z8rh)d?n74ElI0lo+#mhdlufDCaQC-&g>=FB0R--TzdL4Djai$U%@G6?y@}@@@UJer zcKMX!ADk-)D0x%QJ?Nj*sMh00de@GIXu+F#?jibgHjmG*J#!EH^?iT*>3Q-z2hVel zV0une^<(a`h34Wt60ex14V1+xySsMKGfjtb6ag0 zBN=#`4xW45|KjRXNnhOX`DDrPW3k-qPM-U-f55kEpLqPChuJjN1O^=yl7+aa<>lY+?zR|5Wp{7Fb(d=}bv=ySX*; z#b}K!l)IO@-$y>(J>u2_SA_E6?gd^f<~ZHm9!*Bxm;Pgyr*Ms%c}mD4a31A_>gB4TnfQ&ERpb=&uHLSif#j6Bn~syr$BJDwn{JR| zZ$JyrEpgS{uqZg&;o@eu^xRT3C(DqJQ#iq#ugp~=8lIW54)eWoSIuiELYarTUmsUZ zCyA$sE5DiVRiJs;#RGh#&Y#lVb1PkS?0AR~Xr5fpt#Z{p9h_3;$@kp8t~zE~JVV_2 zUFf;}T)p{$r8iB}({uZ~>OMD~8IZy>y*zh-tM1)0ND;Wjo;%Q0HzOIOsP>s5H}5LcbmuLxzmD$l*lRTn~tHxrkT_w(GL?(;3G>%REI z4gOF`We@$BiJn{S#?HCw{d!~n_)0M9IoEjZFn9gs$sd1K^P`=bQ4gBzxx?MQxBtBS z*wG^_xQ&n>SN&46nIn3Rr6I2(TZa6dEWV+I7#)2rJ@Zs2`srqbOJ@l?G?9IZC8kqZ zFTwGp4PbxEUX(HEW^|*B8Mg|aln+NUaKcSYaIzsd8;)j}vu*vcG*4xmciD-PO=dS@ zkZyovS6Y^a_Z5998G5oU!#-FvmXYRD@8mc~FzY{>T=e-*k1SkIvW^~O2}+7s(_7ZB zP`zrHZCEX>YAxP0Y;0I9t&+Po!p4Tx(ki)WBW!F~Ev;%Ny3b*prDOTE7hkrAafXgz z9mGj)VVs>~SVwV`TNr2N7}iM~<`%|TIp|-oL%qU!N{;lozkDqx_|mEwZ;`hZA35u{ zm8J|YgsxQhKHA5KhwoP=bDV={$L)757~S@qr(PjBN4cRz&f19A8AjCG)i?%5)LYd! z21eA|)Hnu4)LYaz21dMI6_sOPM7=eQV_-zREsbMf#GCYQ4I|#HKyuj4t4GiMB09HL zTk@*nup9ZRU_rGVEj&x*B713>;n~Vqj&lGlSiHUaOSk2}+M8q>JuEDUr$>e#(jQAHit9<0|V+^L>vPHUS;M72E5wDz<^^lW_aK@1riTz*68%% z(-&XWj=U;(Ab(Zxz=_I&lTw%~zw{RDYa z@IdyaV82pjzcQ7H^1yOsD&m3TN6!1=_&)=SNv`05rjS$`2CPz98wTuaVqn02CI$xV zZ(?A;0VW0p#65QT#QM&$pTnDb{;FWXYGuJ; zDi`H}!wxnM!PN~2~pcq3>m(Nr=6K@Y2Z)Y@%JD&84LUKL`PzbaTz zEzpEltH&t|u2IHvoQrTV{Jld%-ZRcf$Oc=LJvWm;c}r&G5p=z5Qu=vP0Nb?(I*zRHx*-ge!{%$&+Q%x@%mN zr9f=bOUqFxX$-1;81=CgS0|rbH^#i`rZH4uWKgl zY~7dU${nCY9Y_)WxaO5@*^j2Vc2~e<$Xo>)otY}OV}ycjEh`IYJIjOjFq{F zC8ai)L^=(h9d_GNw2kQCy6q_1)?skiZLd)=XUuk#!4{|vnjj~nsi6%qK!ah-Lc{>P z%G?yUv%XcYi*>7BBe$!ojOjSMw+~VI)|}ZB4Oqs^fg@PT?A zLktp=A`GqRt6lq|FMMmJogZT7#){bx*UL!v{jlNUW;NbyT7#n^t>4S2<-581^>f}k zu;5^bZ3dT#171dL-~awQ-1m!N-;ENmNS)+mWcbEiv7>rJ%QbI=Dj;#PmvN4-<-b2q z-uG?m07pgI6fdKW@97aY{C>~L%(p@VAZ@CbQP+3xs$ExIbaDAfj*7HtUPe9Ny$dJT zoiI7%hAJz1$WjEojEL|0#U*X;yX?eB0gKcjFC*$(d{N(SH$OFhQHZURi1!P78JRw{ zh`>>iwuYAx^QlD^RH)UOJ}teIg5jJ&+#(w_9g-6^VD^`47>tSR!rJ_boarMKVQvEJF=L|V{yde#zfh<9(wfo|z%U6#1LWES$ zpLFnBE6T?RA-8J?r96&=UTPL%`7;t~u|w+RFO(418i;8j_gBiur|<(;-QSRb_Ku^! zQ?!lfthpyB3Rj;0K~bj1ycPUYqoNgLA4`Ht|D_4Cz5j`t4_z=TXX3-evSM?bvMdPn zKe`e8*J=c_+*7WqAU1=AwRU5xi7$*gd~gcMJECgM+$OTgswe}$;j9S}F8Kc&=AY;_pM-+ux+e%TWwT~$ZwYE*8R;_)a2~uk{R^FAfYSwSV zh-G!H8QWR5>stFfq1JY|s)AVFSZn>~wVd$o=UqP~c}E6AtnrZr?q@k;)tjTYS6KDt zBZN_JE)ulf{7BGx3sAzSw}g?dY+DAZdTMWNn;8nx;zqzQ86`J_*e zELsqlPG@bzmFGO#q-`PIYU-^f>3aQ9?#g0a4!^1-5^pu4f(`!qq~tyXsWh~BGUUcT(LX)#_ zek_l#K^Eq)o4xp!j4YfatH>$oTgn&W#R^mw&Xg4v1I{Hm3unui=(q0KKevco#mIid z&qB|_X){K)L6RSao`v&g>J9eCIm|_Iev_BmY!YH{9IK5?;(*C!jF^7@>r@*wq@oR`_E%>@f@B}O;u6PF0G zu2=PWgUU(O=Z&iBNPV{Jw5Z?owau<0SsV4Kqq94SPCfC)OhckGS3Ndp)n=Y1Xl>%+ z!dYrlPtEbFwrdlY8|>P|MF$jwEL?RkqZ8L1tlGrI2Tsu1)N2snEqsnMt60CFQJ*CW zB(3elHy7<*{P1ThiP2SSt2$<^wJleb*+*rgTH6X$Z=^Ec?EK}q_k1_pIsgNLv$AJC z&l=YGvu2pVIaB3tSLZF7u&Q&GCTMle*7#Yf^H!6ztMfKZ+SNHnGqU9qjV&(No7IU+ z_EvS?q4P+r&O0@y8{2srGAi>f1(M)AbY1zrA9CjeXl3%x44Kn_(V?-uN7d)ODkl}3 z3slvyYt-2v1;c7Z3Zt=o(C}OMRUEZ2bE?3!q9R)oD&h3-G*>y{t!+vB)^TM|FpcXR|K7kdE`!%gb^85|p4C9~|#ry5z5is8yD- z1ngRBez!_V-vOK~fo}ua1xFWe^Utb2;R}1980y z!eMqS2V58**UhoO^4e@c^7zqTGzb`&$v@p2WJ0_-Gig^%mzSAdB+Q=Prj6rr5Z8n`$mE}cy3@<;+=hL*4tCakUV*pQ{-C?O0%vQR zkY0Cr1T95nIC8o*BxDfcjmo~*F zAHJV@eBT4xFYHh1s^KW&4_H^=5W}IZjE~SuY2xnn=JAoL?j5Hon=1#WyX*R*KQ0@W z+MGNj(wrqgr(-v5I1CfA5cP{wif@868gBc_-0DzbBW?x z2!RK##Xq8iK9?xIl@j_~qWH&@V9mQcrzO6P68g}!_$QRmr>@06rG!3qE&drL^to&C z?Uc|5uf;#7gg$vKzJm}f6yXe__!pF5u?X+6QxhZ@uY2u@*IM?E(amlRXfQ&YKqP+U zgEL#=Ut3>1H;wQ1skn0-L!uv@`&GYPm4h!L!5Bq}Zo}iwmgv#Ebp?sW{aGRy`Ql(4 z_h&H-B>GAfwEVXq(N~!mNHmTO5GUomaRvF^mn15sNWLSsRqXP8yVj_DSD zfP)pD0Z8;MBqc~R4pLZ3CDAxS;UGvfj!ZZR5{)Ag4uVAM!3ejrA<=p~B5;&wJt7e} zO0*u32plC^4@Lxz60Juh0!N9~gA$G#5E^tL85=6C`j}% zih@KR*Qh1YKT`rF`WH%|ME^<&l<40GVMz4vlt76-K?#)TKPZ6`{U;?*qW_`I5z5`9_|BpBN)ed|;(V_Ff36GNhnIDts?sTGB| zYpp0Wjr&~{cSNEeJ{^2}SV7V(@(@F!+p=IxkmyB*L_eq+7|~$MruiWg1Buqt1cpTG z83K-hL_cEw79{#n69b7}VqzfCk132db|}%0n=nfBQWG{L`U!%gL_bMzl<5Bv93^@g z!BL{0A~;I)(+VdNeeYkjo^JHqEz?K^84^t@2>d`DLmjt{p>7smuIigev~SnAH!63o zSWTW`NHl*&qC~$WY8)gQcg^y&Akiz;8;O)4(JvDaBzlzzDv5rDfFRMY5)dR>Z=&T7 zQWCvJr4&+$qv*8+M~Qxo;3(0r6C5S_4T7UYze#YE=yfJ;Nc39-M~Qx0;iOeqv-P71 zZ{KyQoYa*e(X_6>AvP$9-e^noCRO)DqPLxx-8Q&+(EmG%<`1zXI@vWw(J8JfyCKo3 z1O$mrBOpk0kbof3Ap(L#hY1K0U4wui(KQJO5}i&!kmy-UAkoJD zMUH|*8`~B+3KDH>TjVH6G;Uk8B-+@y$djW)cw-HyFO zf<(X1TS6E`f1rX|iGf6KH8GIrk4+3DdYi(iM1Nw! zDAAvqup!Z(5ga9YJHb(+KPNa!^bUffM1MhWl<1ubClY<@6}OFDGG_0&q=F2ICKUvJ zpe_@PTbBtoi|Fp5cmaY$e@{S==pP6O z61~?1l|=6&AV~C&1O$oRPe2$&A5fqr(FX~R5`Bo^DA9)rjuL%@;3&~Y362u|lZhJ= zeT?8J(Z>}|T7}}d&-R(!zNjy$D?_4bU4cXVswDb1TcUqgbx$OE@QsZ-EvkIA3wek! zislcoB-%42`Xb%V8WL@MKf--LLFTS*$}r z`t`rDo}WA<`ix$NY|lI-L8AXOB>FGakQfsEw~2v7pENO$=zmNMB>Ghk#)o!62-cvnB-K;(#8SAym1{J zf`DH}KoIbu1Ox%ECLjp-Fajz8A5Kva@DUUR0Ut?G5b#kH1p&XDq9EX-HOd{s5b!G~ zfdW2;5-8wTQUV41Dnb|nel;afz{gSo1$-POP{7Ai0tI{mB~ZX8QUV2h5+zW;ub~7A z__dTk0iR3=L%^@21Pb^RO%MU!T_^JKQ;$XH`6-5g8*u``I9&_)^$7xggRA0>9YcyO zcHs6M1*;m~Y_-@g>lV8M^N<7qZw9MUVjB^DM<>HktWn}ubfN*3+lcTRIu3$};}>)s z1Qo~c=Qs#5-cmP>90VP|kbofMo(8#t<9zr<1V<@vMQ~%d-I@|8s*s*fTE zZzGQ}q?|tn)j+LYcOz1MseS`qV@k@qQxv2;hoT_mxdc^Go<~s_edkjYq`ZKlAmxP` z4c@IjUl=q|rN_i0_P|ABz0;Rk+B~Z$X31LWi2_;aP76O8l&mtg5`D_A$l;27~kn-CI2vR%bcxSV|8SjG&ZvWWksq<^4=4@2^`E8ID5A2M`d3 z;{yo@Qa*@)AmxJz2vRFwEDIZP=l=2ajKq((d36%0t zlt3xJoDwMIqcuUKy#DzW%er@+)SkKpN;#=9aEvQ;D}9yKN;ivN?NdHLr2Myd?H0b$|q42r2HC!Dk;B~q9EmyDGE}49YsOPr)boY z@~MrTi^Qpp?H&36%18D1lPG zo)ReK8z_NNzL63r<(nvhQvNO>3@Lw)5-8>GYl2Amj&b)E^shcWn#LoaMw2tCMw~z} zZq`!1B|*wRa#h?BDX+8Sj;h0JXVxPRF{HfH*`$1qDdo58*2IwVxda3$zk`4v<#!Sg zqr#N zKPFMiA0tx!xPAju%9m0Ur2Gkrf|Nf=P$lL6qbNxEGKzwfKSfcH@~1UwN%=FBKq-Hg z5-8=*Q39p>c}k#^FQ)`b`3r#2|9VPDLrT9siOZY9eDm4U}w(aONntpJD02-7t}~y zT_g3Z8fg-b_?7V;hZ`K$o7YTyxpUXWpR6K}h_t3PV(C;%t5Po1r3Yg|r5M*q%JM>l z7`I7E94f`QOj6=dDR`YE+6RL4mhhwAvp#-Td?wQ;D9Q#KCO@t=)Db(}`rsE#ul zwWC4l_daZtJ{%Kd5L0x5n1SiBFqC%hj!k1k%J(Ujf=1GPq0YS?iGw@8{9g}wL)zuNR} zq#+sA^x`A^Y9}-#GPl?9SF7d4NBPyBJR=RsD8q|i?pK?#AQ4|EGD}p)i;woJ9RWrf zl2JV`euZBx2}2@2O=V^j_2OgvYCXb8Lo$ka@hkmmLK+hBPO_O%+>2l3SF<5T8j?{1 zFMhRO4Tm8ScOt1>+(M1K_*lO>s{vBrcb_~(6E8l_uRaxp6!_T*PtnwikN2xDRUifK zdgUpadGQH;wNVyQ;IBX<{t9e66 zfny7v!t>(S`qgj*Qiw*KldZh?WWQ?GOcGA7YU9PP^Q-=v$-@~|?Y#IDzfviaM{9TR z;#2*qcL7OQcbh-GlNX=nS6y>))tfkJyo(o~?$@VTW7Eff(#?xs?^i7qIq7QItfx+X zK6B|xdeW6@by_uI?U?g0`wyC<3+K%FVn)V?YdNm3NsBIFf0gG{R2Aj-R1IxlB%J1! z$_5^RQEGG)EX*k>DrSu;M=w`sD*th5nZwfZ!+ZjxHIZM?uPCpeIbThv?L^~Zxp2RomW(urHtRq13y9JmU;a0pyYzi`M3j8$()j;P&t@RFa0j%m1= zWE|y3Ld%Sc^=p^GYu8{G`3CUlCN3}RQU!KsNC1y+;$T}bz6;>dO?~?26pQ1W0(f#$ zc~NO~URhsu5NQ(67Ef>DIkXdpaR%`8CJwfD{7m2i`t&AtaZM$=yo6=M+<_7L_$E=@ z4&uC=0G{1c$n4#-THJM_>I4sP;`y`Lf`F_EJitksqPnoGq9li(0oSjnvZ$<-xsFVz zPjn(xHm=`*2aY#9x|~?nsIp=hUsSSe&e^EDSA8(FRM|f}GMO{{b=8DZ*ftL`K{>ZNj2&|xJ8(DiR zDasZB__gaVYxMv4y6(Uzi>LkGl5e2?kIURIq@8 zprTTwND%}C6%iE?u_Gd)fE|0sUJ(4LC@P>Lwr_TKX7-);^!p=!?a+?DANuK)5uyP4i4raVTIVsg&L)p_+6NwQLWXdh7oqTIonwa1 z?$NaM*F8nzSub1b;Op!DrhzR@Qq8j^XrCuJyNIKOwp!d+2n?4Nc#6@KhIomwv37~4 ztw5>k`3)`DCIw)<=EjM(vq0EsM!UJ6Z~mq%DvIK^lX-vLpAvYM?etuNot|$(CUKk_ zt(_)KJE!i-@(xFd#ItU)cEV@a!A>tVNxiJDj=X3mXV%>cyev_uqsm6FFseNRN{pWI zDhou3bBp{p^}Oc7??tBECGJGc{Tp23Hxo+yRud|ms5cw?AM9S3e@PpWxVzqT=4S8R zCaJ|`rBvegII|i>uXtagx+O^q?2>4isW%^36g^1Qn-3Y41LeR+ED+Wiv*ps_mh;wR zhyu8+)0wREDO=~W1nYd>gbd+0IW{I7GqY-Om&`QTVr4}*CKPmG>+FVBrKT<($FT4f z=hnbxLNBn#1Dm;uz+Mk*rYZtodtftD5%`}6HWL+rZ#=M>rwDxOfz32U;5!SW^;Pe3 zAEO@Yf6oG8{m)K$wxROd%gg`M`d!HSKeF|IO0fRVO~}xWlV`2JYx$cmE`H*nMI!O6 zW32TH+4_f?V7*g4lE5#VS$xD;-8dikRibG6-z18bKP*vL5L3SSJEJLO#aI(`BX&dz zbY;+jKcv7$)<3O4nZHm~3H^(|qyRP@U{L*=1%iQh*PR)fbKcOA!booaFC+$h$rM%n z$ug?84tB6hp4xx zVM0A_5onO8c?}^jP@>TLQ0@L8MzzgtZ*?#Wgv~FCG;9CM{)zIDE|<+Y=$^?oAC_SA z;Z4ZAj1ujjwm^N8>nmu)yCj%C}NpJ1B{nvfZk`?GCI zZeG^5A)*|47)xWp56E zQ`z2ECfNI`CS+RSi-#w!>Q-K`G*hIVWqq+52f%B<-lbL4JHD2)s!{A6Unf!Q9Z#1i z_Ks&*)bOKyaVDeMHsGPyHqK&!u+0a3AG`U=)M?v9{#~}|MxBE>Y@4|Wwwc$2%-}ft z9rne!x9(}3f7Z#PMcP?EgMz82MQob|V4FI&%|gzqM$tBlB#O4V(W0(;x>%xEPnR%? z^%VMox=VGF6u?b#C|D{55NUAixr_zEng@nPXYJ~D^fPxiqP*m++I$s0?80e{J zkp3f0?BVRRdT1*BCjpwdxb&X|*jYDu=?55$!^dmP8{O##8CBV=(cQ81LvC3rYQ@?;9o(kzK zWK>rOFdjCii&!AuxjtvmzVFXXX?vb1Yj}jWtT<7(BtQeMn*wsc6$va2kloZO$?{uOqf?lGU4jcL^Hx$9x?Cf=`Wreusrk9{APqEaK$A%C+J zl^K!l4?ST;*ovtB&=y9`9A9HyByAp=-l5sn z{bPkCOiO~6Kr3&joyCD2o}I<*0?+u!ppJ78Si*YHZ0ocSYW^9}PNbdvD<~){*R!*R z3WKn4VV>a&bt5MY#%n9;byE^5Vk}l)Uelo4l2CUBAvIVeQKk%?#-RFjEMBksP@&Tq zHU>@w&kvo!AgmpLrs^w&dN640s=7*{o&+{kAlTHnZ>SgH;=QW(_dc^Aw13yTqS*Sq zDlE3KXs85RfKVxUExuP3DkIA|&gs@^cl~ox67LZQx+9w`lLA}Zp`%5b4uNq85`x4xiK>`$|-kaW?Yn0;l|7`Ij4^sGlS%uN;hVP z$T?MR3hQ)eIV9RjZs+L!hAL$(J8}bbaQe2Zi|zEyjF`7GFvZ zJtLOGi=jwMPK+23*BaiqKC@}tiJj%-WwyFa31}&;kD;3bFNMMK{($M2nPdGNAMkPj zPs?Ff7b}s+h5ENGY&&AG%==*1H!$<`;$#jxx5<3FoF0@dPix_U(brmfVDz?D9=Nk!$<9glz;G@Inv$HOJaAV%8{ zzpG%skiXz&znesn{UV7X``smq?4Kr4WdC%DBKv1Z6xr_~QDncTM2Y=g9vIp0?SYZ~ zVh@b$mv~@gztjUG`(+*&*)L~Uus=3=;FUjCp6%)9yVy6gu+VB%GW%7W6tUmePecp$ zum7!YkBMJST=k#q<1{R=KU%PVE`Pzz{&^Bb_QyyR*&i!WWdD4LBKsFe6xqK}qR9R@ zi6Z;sB}(jHi#;&1e~AZ1_Am9o$o>QmjO5*^56uE9WK5UL(UbjvI5vV6QP} zETuyc{(PcT@Z9k9(vu_CJ4619XIsf`Q?B~dDP9+A8BpH?52%@zr}>N75(Kz)A9 zn96iRH&N;uM4lfPAo9FffXMR`0z{s-2oQOGQh>M2e$hEy~R-;I^y=qpY$hN&_ zR-;I_y<}FS$hW;=R-;I`y2d5r%>AxTXTC!p+=E=dqbf{k$ZbRp+=E=dpDs*k$ZbFp+=E=dn=(vk$Zb3 zp+=E=dmo`jiThf%xPh^{*Lh&%et-u??qePpxsQ8bRDg#!1N3GVI1R@!LDy}i{+ zqsYCz(n_Pqy}i#$qsYCz%u1uky}ijwqsYCz#!92ey}iRqqsYCzz)GXU{WP|?fsy-b zJTP*9tp`T#uk*mj{d5nE+|Tg9$o)))1^3wx4O{=I|J#v*9~bv#sTa7P&D`5NbBO!7 zKB8H0Klr%&*Zr`rnM~WoJudYE_je2K?M*1!Xvn?221TRDy}biPqsYCz07aw7y}kWJ zqsYCz`b4A1y}kEDqsYCz^hBe`y}j{7qs0A#Y;gl4_YZksRD zOau4t3GUzLtZJhn_q!yD+e(I;v=*E96t3!x#Z5X@D=V^_#8147v|X>H~F~|Me-vOMe_3`isTYWxJ8mr^RSvAoQ3bmGjRo+lwrSpPA5MRE!e+$)4UrWdoFjNNZif7orSLv?Dyv{ zxY@6jD6(HCQDlFBM3McNM3MctM3Mb^i6Z+A5=Hh0N|e|i!5$ddAL4f=B2lD!szj0PDfw~7d^c{WGUfzA9iG@ElRr9-nh*Abm-Ui-z!n% zdA&rD=ldjzJa3RF@_av`g6Esoo>+CldtaX+=y37ORr(>~`C&?jcz%Q^6+B1oTb{CE zM$RQ7VHeMK7XCFi&#zPJZl2!|AoBdC0Fmdn1c*GpEkNY?9RVWG?+OrkeouhN^ZNoM zo_9$UdHz76$n%F1MV>#BDDwQVM3LuDB#JzLN~qwu@7w#AZ9ne4u%N@mGta_*K|Fs+ z=@8GmiBiW|VP|KzubNcf>8iX5BH?T`eXF)*RK)Bo{9kUK|EAR4JpV(Wj^oI)!(#`H zBGEpHBGZ0}BGpL}MXm!9MY5Yn6xmLeDAAqbfsyZ~9vBHv^}xt@&;ujoArFk4r+Hu` zy&1z|sP=SdV*a#ILAjR7Lp4PXw&E>$sMd;8qM=&4k2n^?^bVJOT=#@;+mnKL9;R2s z?6mx;VwfJ~54d}49VCj}ca$h{Um#KBzLP|e`_2+Y?z>17x$i1b`sbxtUmtT^OTmwe zd!ClRn7O}%QzGs!^%2d2`xkizDduO>uk^5!xYsCF>4~*R3?17Q{6&@J5U+IC7 z`&&FPa(}A_M(%H8Sa3h=l$RP_I`pvTc3yQCo(af2Ex($%zk^dE?$`K;X2E^0>uA%E&r6@{%QVzwlEIUwn-GZ-!4()euqSn`)4GI+&?Q(0?qBi1$o;Dx7`cCqVZnXBmz$NwPfnAaZdbkMY56yq z`?okH;{I(P(JZ)sy5-KV{_c6lWBJ8KG;2b=eaC$d=~0(Hy00KQP`+}j z?;&-6N_AV|#+{aYsIL`&#<+2AAiW9Y8jd~sxhQw%TzAr2?YBN4i}E}uK>CgPlma9k zciJ}1S?X^Fn1UQ%G-sKg&K`sSg)=1T%09rC`{_J|!qrIuCGbacZuZkwMlFCj6D3HB z=B)73>??oZI{~ z;=^CS#ryvJrqP^Le%h#mztDozXwL0^8ZF>2zzhBP!D!BEKke|qUuZ!nnsbMr`k45O zLiLNZXwDix?F+zPXhE}R&Ygbhncy$Fsb4gY=G^6{)nxpI7PN@w-0i1$hQBCMzi1iF zS?i}YNc@Esw2J23_zNvKDw=bzpXv_&0_r^cq;)iBy`N4U z;7^PsBbsxcpH@QXH=5ndXwC*d?Nz7WXh~Ky=YBuUpVMzNzuD282mG|dnSP@sZK633 z`f1ixTnM?~hG9pJJ@c#P@}=|A}3NXEU}-j|cBnX^GbIsHKJ@y7b% zlIn72yRT`us5yXYelK1g8(3b}2wT4#UntzY_V}yE>_~YyJq^TaTF5O1hYy8Mb8Dyx z1*s7Tg->^DsKKYyNDhV1aBHX`iqvQt3iohpsE(}E2!_Hv-5RR9BQ?@O;a+YH6%?gL z^H8|ATSGOSQln)kT(?MR9^ia4&sCZ2Z9u^9h3YA2&W`@FLLM73z*`aVbtLR() z3Jhod{I;QRg%ounQTtH14~xo*>x-*v`;aUg3Rki$R$mL3dMY1)+hs%HDi*-`L&A>^ zh5Itzzov@tV?yD6j8|1xm-i{ICfRYJa5c*sz`UI66GGt{A>mA)6bknjlFpRcDWPz! zkaQtQG!(8AlCC7_7zz&%l0uSn3WZ}r(v2itLgBcO6p^Gb6s{MN?j$J+g&Twfyaf$< zS|~hFir5Nggu;WQh|SP56dueXxFW5Xf7Ck^9^#giu%sju9_p5qvZO2&K9ePbA!975 z2!)3U3Fn|P6dukJ$UzzZrf(>G7E8>XlT_I1P`HsrgNpl=lc0YnJc0%KmZQe{p(Lye zg+~fuCzmi53Xc-P&MsknD15dMc5w*@hQj9vVON)Ma40-l2n$`pp`q}(LfFkE92N?n zCxk^V;aQ>Z7$Ibu*;tx z3Xc~OcKHiK;fsWXU4DEhe6f|N%ZP}yi$mc{goMj;X()WDkZ^e>hQbqsgv)bzC_GU} zxIB|X;md@C%QGbuzMLg0pe2TzD?{N)LM1WYTpbEeW)*$)k11hN{xuL1uMi?EVp9Hf zAetgXSjMFM86cX9d8Uv%AXB7R|y?&6idpV3p!T|9d8^<%D(}0 zrnz-Gc>`He{sPdshIQaxmEy+OU^2rZ5MC>V^(%=k(9pybQTI7 zZ$~33{{hfh#5!=_OEFRW5J+y6l8UN|S`t43;>B)p2}w4BWQmlxf4B+6H?bJ*GAea> z$7T>Nl|swV77#9T3(H);+zP_wQfPnqGzf2Y3*BC|9fT{S(Ejon5Uz9!-5&KE2yc-> z`^y(Vcqrn?sAJt+@JdZq<0G`f9@j?tra5v+$SKqM~L`y zpMhu{i%Q{2>_#s67a+S=%J^%$LAGAX_;Y(ecAu2-_r3<%1}Wo8`3=bKmol!C-+}A_ zDZ^-*l>a@*9+WbSr%CzyLG}>KR9B3%`4fm979!5&0T4YRM4ZV(AbONVs&ViRACmHa z1)YsT#~Ue=@(+W~W2`fe&Jxw{?arOWr2Iu7-65nfY@lv&QvPBPKO@BjF7ZtuepZTY zzd0#?8Hk@_u`+pL-{5A@dETwlIk9iB5_Db=I*HNeR?vA-=p;s;RiN_{>ljn$AreGf z5bYEq8a^fEuL0T1QpSwj1+rJ9j5%2gvR7FK#qXS0FV=z1YeFZnUaSY5*M&}^=WYO< zH-t{2=RN>BZwj46&wU7V-V!>Ap8E*sye)JRY264q@3?ikB+|MGblw#@iL`D8o%e)J zBCT6M=Y64*Xy>hGV>DXd@6JjnRyv>J`*~L%)AOZpSyLsCNlFn=zPIC&>44kn%)HAmr`iE zA#a0lHw(ccT@yKd7j(W7I*FXV4?25C(+K|fzE!R zlW6DfLFY%IlW6Dtp!1W^Nwo7%p!2iPNwo6;&^aJ<6775lbPfugL_7ZqI){W#qMZ+e z&M$7AZi#k20y@94PD33G5HVu>36jGs0Z;FiXx+a-=Xar#Xx(d)LgBxKPNH?M1D$_J zM@`;$OSJ9`&~bc1Dbc*MK*=YS674%1l>AaD(ZF*-Dak6qvlwid8$i^=iXgj1iH2PO zN~u-}1`(z1Ui~5v2c?)>-NhgaNg4NcZUR}FlyMh!8OWLmS(*EjH-osj6!Rxnf~iQcph zlrp7KqBpGvr7WqG=uI0yDO)NfdeZ}-)W#~QdoCMc!M8R>we2BLXloT>#WnB>RxAc< zN@_((>OKOx?X0eO!0JD>H-dJ1tF2NlE-fvGH^v55)xtAx@NN}lViTz5Sk?HDcw=34 zbz{7`s*Y4PgG$({6gLb`P}u@1xmE=Rmb;#=|=tEwNO*3;uH@mlwt704lKLRrELmSQusmKLcht*rsSlCe@j_p9F=s08pSRkL@yg<|+CfgL z`q3leN1gP&v8j&|C|>>!HvOph`ukpZS>!KwxHo@T`b|`NzSPE)K9ahb3JQzH@MA3f zhGSZs(EZ!4o((^w%2AA8&0vh+(lMq;zS`ro#2-Z4$*aTS8nJF%H{$DD7-&eWvGj*4);^d{idK znPCgs=iDn^8gNdL+%1`XJtz!-H4VO=)z>t0SP=RdaVHJ#*37h*ZIzY+rnt+rcWoKh z^}(H~nf9u!Qn;K|y*QD{_iTwh`t#qoYG8-WCyx{5)O++PABM@yvysV6zE{gI*)DT5 zmBn#RvU~JfOxb(X#&wmmM8espg2DiPxgAP(yV{Gd>tLomL{nEfJ~@Mt24RAV^vhwqh|6!8OMoPcW~Zl zyJ5%=P38-0{dzJKuT!R1Pp@S5vS2N^wz}&xvo~V{;;~W(z_iR_!i2kTdbelv zica^B7Zx$@jut^vmyxNC~wAw>*O0+S1z7fmn{;`?x;*%4jxYJb>?Mg zXmyu$rahp?9&bg^7!ir6c1chZm1kk{^keUg~9X#m&Rbo!%X5~7Nuf%Xp?z8 zncRVffq58n#)U7Bd}iBpk!-elTm;@waW|_~!9iu_GT_XU>KKCkdrq?Y;Q)r>00k5jV+iP~ zar_F4Gp4TXZq)a5Ymcudfw*|N=*pV%iT7OeiZF=2co_|Xh8{$Q9!$v?L$}QwLN;}r zZyh#tdds%cdmZl7Mx>klJt#oB&>LZo-wA$IUSXQ}mnrRFMO96OG4(5qm6m~?x~@I* zRg2XErcM1CV*|>nD@-$QPwovUt1vB$KJ+{|SS3VHpjk;_+)1KSIKA#Gl zd~Qz|F*Wqd$$fsm@^4XCGNLLh8u2|cA|KTwBkm%5i6FV`ueatLeSF4WB3%Smc5*NZ#mzFi0+TK^P>LFvLy9O$>39 z!M8F(O~W9$jJ1#j)nqIuPz1@gZ|oVjGOu@zu$Bpu%38?5O5)%aO2lxGop~#n+i^~@ zEylyYRu1nz{!Bd%vg4f&s>OguxtW8F?uPp@N?Q50apO%EA{MyM8)OzXvlg@P1VhZi z78ispJn4dvg{>|KS$K*eX5ndun1yW&F$>!nay8sL2ox;L{P~5-Vc&22jpUic%~t9ETyiA z&>e*HT~J+Zwdo;T-~y{_i_7$7;F%Y?(0FATjAvE5Fpf~sbGT)})A#N8^Qdn`22IZa zGl(U>m`Z*LrDICoF7r|h=j98fdWiE)Rk2aDJCCmzAji+ zUR^xINowXxYi|3XSaD!5(42dr@JPA+#G}3Eo^#_vue>Hck*mi1{0Wo!=J#Xfn?E2k z-@f^SluwcQH5-e__J1+fID?bzZGJInRYMB<; z(`4eD$oj3*A5MO{i989e&xw$wmH+uuTCJjybgSDvBk6XnR{MxB$59U=Vg2dzTgBfW zWe)pPu$Wz@SsVmiZ#!QQniDLmgRYh8dxz$dvjrP!0aLxckPWV;N~yj`$cESQTIjv$ zhfZvKEw8PvGOwK20Bf31^$>i>hFJLW06ioM*%%979-v1=Asb}Xk2~ujQOJf_`0@Zf zCJNa&3tt|fheRP8Xw{FqIDn>wIMnJ_Q@Zl2DI9M_CHpCL&#!M4c9|rMh%E#f(J&NR zft4(@Qcljb58XmcIL;i0=_&oZ__q@$XPzQb&b|Q@Vx{(imGm231JHC^@YtZT>hk^t zjxuJtEqkmYreR+Sz_R!-=m6Hzx%luMo0+wvrXF1Qdz+_3W^@liXT~&w>2&#X`U>(9 zj9uv~sWgtW*`}IxCs9KDzl$7MdZ6h(x(Swu;(2bblrZW&!EJEv5Klby5E~V z(_*EyHFd@P%bXCj8RX7yv`1FPaNv+gv7E_jNaeyAz#>y|>dJuRh(iqRC_gld4v{;D#^Z(dnS;VFrx z6)_dzRg;v$lM+o!v?Vmi(-OiM|I0e?Q>!a?$w5522V~pSfRvtSjFeuo24tu7rgA&Z zWZOWkzIs{9RgsHF31ehURSi^m96Ols*7|kHsdcq6-8coNCsQd?2gl;$b?X$EVZlLV z3e_)L&9o>Sf-nNrMg?YBfoaY3qhi-vv~o~MRlI(@9ySGLyYQ+Kb*=;?`cbhtR)P(i zN`0HT^ef<6a6Ku!<-qZX^ zj8a%NPhI%~ED)2_4@Ng_oq23WIoY8nsoj|{g@luf_)r`88aXbWTlA*}s637{-4^n* zKQ9kk6!RArhzIGO zfBELm-)=ra-ue+9;mrn?^KcTC^YlW#q3Ul@TUF<>c=qvX;n6u&nXzY={N7!^Ivi=w@E{(S2P8$=0Aj}uFv+{Kp?m`v^xxPnu{Q|W;z zNn{Ae`NUf1{l(pXDQy)SDbmjV92C@sa(HC21ZsxkYnodaR6u2MOfSvl+Q6ocDpx_z z#y&%s%W*AOU0YjM(hph--LK5$pcbqvR%@9`5CnVVa$rM&Zmx4VvIXPykdDfUn(fN9 zbM9z72&TC_=`O0nl%^{xPicKcohYB4?ZWaI)8+QYK$y#O?WR}IHn)UKV7={eQVlaGA*-&vXx0*#N8R%xh+nTvG1d6CL z`tVmXqIn-?iGu360%br|P_!Vuc9%PV(lHinmm4EviIOyXI(^~FihQ=oC)2E#y>3b?=lQ^ICC#0*P1}-kYOg04aBPXyEW%sGJo2F9U@`9 zY7Q2!sDQJ^R3~2wR#emvR=sf5+05NZ>Erk#2^PR|UuLir))>_iQ|>Da6_=F30;cMm zq~*TqMs+tk_cekrhwIdo3qPNG z?T6JDiG;HcgMuzN9GaqnZ-zQmQBhUxgj5mjtfNM`QL$5x8t-4P%Bua}&OoBXuy1D} z6$}q~Y75$lNI>D>j;UhWl6FE;{h)RrJfDl!wDXciQeiC0bCbfN4a-VKOx*R2XT+*{ zc2sb*=(A+e=e!nuo{Z->2dqVp{c3OHZ_`q4kQP-Y*9pVsR0SEs^Fh3aP-?|hJd0=RmO72veohX@tsEIX>^=&9q^ z?GUB54hp44b3RJuoM(8tJfj-z(NV55Iu{DS5sO=lh}63!k83XrMFlHvy3Qv~6% zA*lW}^>QHPk|qdMWgSGIn7hcy{p-Gp!FQ|^U(js0IR^}C-&m^FqdlgQ11JbxPB8@uPv$xh}>O_ zo8YIWA96nsAUw>gIQo!4(WRLATE|@{KM~6jxuGtF$_n5Hj zl1$~Q&~pfBx&Jfv?n+tE_PMuEnZ!i<)X9}s-Z1dn zD@DqBq8)MzeHFMDftsb+!SdMPGFaqPbnvW?+ZX53H-#@&{_|_B*=-Z#kk)2ieF8H- zpIG8KPx8fuluyUm2PB{`p7Pb$d7%SU9c1SBgM!XH&Co&z=j`SO-35dx8Qp)j8z8Xz zr>x6cAVgbw>#uj5GAli@*+)k;xePA_#!Uw)AKI`NW`=@>(zCb=;zJPhZlk$ESB}6`OH)Ydt zZt}4Ylt1-B@9uZ48zWNAUJeT21Ii$Ar)AUJFPp=EFoc4kZ0>FvhomVCdd=!K5Wv5p z?zO^o1W^KiGWC3Q^P&VP(cEvT=BJq!1<B%&=`rs(OFR?opdX!r5x|HeOa*QwL}CvDJ+{7_6)Y zT3{M4!aXdiZ&04d!{iGhj5?ukxi6G5ihd; ze7M<|2fF+u63$Yq$|mDHQj7$Asho4yO~hz)m34a)v6y0ce0u2l_2s{KjDDu;6PWi@ zTGWf!dxvp~B@*&cPDS>QY}xvS^Zwc||10}^lXql@EBixzWMta-tFnJ4qaypsPks?^ zmHd6W_=KJzG8R(jDbx&64xKf*^j71`g{Juj`MO@GgQrPlgg*liwgW#9Dz zlgs+{0Va|CSk4zM_rEi~|9@p)o%GPzf0VPokqtrFf6PZY6<+^+tG{M<81SZC2eDpn zCu$;31gpvG?a0xUc^)(huYaS{8-Lw8>zvgh@7C*iekAfVc|8ve$?LaM9);cC__5>R zvpVhAC=#|_Uv0gWitXN-QzE-( z_$a3$`-cXe)owuV%3np=uIyW{Kiidk*X6=4%iGI^MfM*%^QvhVA6a&@_=GF_?Db9&|XgUDf=;4~{=(^$d~y>_$v%%8Zcudcv zM0i>Owt!aZer1IBJn3Dbs#h6#fm)_uX}qAZG~UrkfpJyjMTToCs?6@_$V-eNoiI9y z@I001uD#X#%qK5-^{O95mQ8n!vW(vND%B*OpTh21|%3NIQ!OgS5A}wMdQyT_y=LDqf7~SGD_|iJMP7 zAabr>j6oW?hUT%49L-4?A88-S_mKsJS$0kS;(zD18Qn`H?lz09qT}3V8P6ZEX1U0X zp;<1rm@vyF7Pn@()PgRvOkh-)W%rGJ+MIBmBad~t&B8VRayH8(PKwMj*+&)-X6f@thJFj<)8m!;1n z=U?u7Oyt~c7H&~qVYAr#k;yEt`N#r}v&!L06byI1W>(6KIU@1wJ3s+kvA$ZiDYJsG zp+RpAiP(J|rU0r#9I?AP6xd0xZA9eozOx?dMtFFy`=78MCAkElY13k&kWZKcSpr_gR;o z=YuqerTGx1lRQkPCP{+B;a=-oi z!ck+-@76@5opq0!d)roY^rbTS1zhPc9_sRUk|-LWvqaGXT_lPo=*p-#&bTJ))&0j_ zc!J!j6IK(r?4#T=6mb>k&WV{S5RRPYqY?`<99ikVcXCm_r)3akux-Okml3>$WYU(CPhrQZcz(hS@Z%x5#$_XWrd3w=~#aoq3g!aI76 zex_!Z*ZbFseCSg*CLdVUFCk~YR62W`$OI~hFP`^ATF-Dexjh zFb;E<>cm)NIaQlryevMXzdHS^PDMm+X54fs)E?o;3IZKxki%8s)`fSDIHRJiXAwhf zLxReTS;ltaR;p#UQA(zkbUQ>XWNuEousEemdIa2Mfcvc>^QiL7yu3NCuhv-|G; zCjGX5t`^q7!Gtli?IH94FK6fI$$p&5_UL6XGDvR=u|@22OR3U9O02TWCZ&vuO8~}y zv*z1hzIs*8Z-s}uT!i}!6JyRkqWYl`y>U`8}|tc;VQ1<6E3^hgA>9o@BIAO_P>sl?iV>1cHvIMEo>M2)DGF@ zHXoV5aqb7BVvKsL?U?&VE!ynqP(Ng>E}N1&upf~Mdv7E5$h;~6>>XDP!ky%!TC=lh zVt6e_gK+RfY2MA6@VcOZ$k=N9A^$jX*p4#WR;~ zJLa-W+Uyi*XFU!I&|oVw+h(Mn4|~(vF{=3s8bx!|NEGeSU!rJ`T8olJ>MTSi8NiSj zdvD4e^T+4W=~sz-gVaE1dsYbay0U}Z(P;5otMGdul|8v$4rSvzVLNyve~zAUl}H^TMYG+meI(UKAO6K z#IRSQM6IHc-9GBUC=vfCJsSDSM=g@duUfuSKRGHI+2f;yI3qA?&8?%6y*^s2Py$XX zBO3YIN0YDWD{73R(#niR{^z4XiY|o!$*}^Wep0W1*Or*pFUc(GlFU@D2qn^^3lSE5^!4O(a7IEnxRx*fx_sYR74~H z_-NQ7mh(G~ob^uI{p%}Egw~&rGIXYTZt=2O z23mE&stTwvYHLn}_bUSil|^mLiNq-IDZNg56+aSpVc>^qAAh9Yg#piMdrqXmg#pEC zcTU7^0fh9r=uM~*-T|n-+r{)`2J>%gDhfwAfG5aNTU?$T05$V;E^tO>2 z;@5FLcDTN;Kku&B-);A}obAp23=}9N^Hk*J*l$)Bk3}X?nXuoiZXSzF79ezq)C9y8 z0>mEC6ajWMqll>t*1#@3b>mayN`_R&q0m&os|46hA8(HEE>xL4}us71FAAi%7fp8wDPkFqm58U4b zW=gSbmgx*{rl;w+)`|_Wd~|0w&8-UMvVmpjolloYvCn8b=We+HesdJ zPC$LlwqPm^^9E#!ZNn63UVu!otyupW-H4^wMog)7)y-InY{m*z`>z_T6x)m`0^aCs>Jc=@C^(mYQCBu7rkZ4((0MLc zl}CeP7=)QMY->}-5-6PKjFt-<9u7|IDk#R$DpIVR$DfjNAv#aWI9co3r;H~*ah&Dg zbr@yak6SWf&jM$(NI82YD8$QD%5eCcTHBOMf^c{gj!RU+RTFRrAA=X&hDqni)%6Mz{zt^LEX9{OgAE?-g0Y07F^BQctE*Um;7KlQM-0 z2wf3dWoE5Tdu2&=X`M(qJIYn2-WK{%S6h>^kun;rZ;ZvtOx56RZ`c5-IgFG|Zp~6B z04-I@<8G`NmOd1?nZTy?jo>k4swWsWb%k7Y3*(T3Qk?_sOiwaysu5&D<69XAeYnpK znRv<#SCp!m60QC;;llj_Bh&7_b;qx{!dx!*19Kq}JBWy9BoXaXo+X<*&J^%2biY5Z z{%UpZ!+qWqDQ8~=3gCW?<%8iN#+v?k+Z424FM!<#$Mxoxlou(hxL86KkNQU$E6$R>EBy~w>ASIcK25=_@tD9Q_O)acAF3@+j1X3jm z6D3MFDACUPo|ZsJqR_!mx@i*as_$kAG?OT-iYeXZjOz2z5b=zG11(q}=9Zc@+xX?Y zcOG~`*ubn`pbd<11L?d0_9)Le_jZBS$z)3SoS)fi-T9dXNlOp45ou=~1qxta*HK`& zBxf>TlA}b$+RUx4;6Xp#preE(=9-)-|0*ms_vB3dS0Nk^0u!~et5xn~VOc~8?Q)e{ zSYfWpx%yv|g=Ss-a@xNNVUAM?uVEqGiKB`FSI6MpH`o5Fyss*%svfPb`&W5CRaz~d z{;%?CRbVZj@vrh4Rc0-p`LFW+s@Pg?SJbsz+1q^VqB@<&$6wfWbumSCTE}08_n-an z=fWq<6czb|aky6VXo{-U4W0$F_O0go$hREl1&19jzqatqH;?^kph!GxCn%`XNN^TE z-jS>HTd>ACH>cH84Zu|^hV)o*n zV{y~^0h|^X&1ec->~GRg9u+v(3XJu@+FEd)6o3KE4K0B&ED*adhW|Bt@Cl2zZ54$v zyD!jGP#Cn;1@x47;6gve2s7;&4vh1YSsX{5ibh+V*LCoL`@5X)*@W_p+g7|T9=O;K zFNv3ur7qzNYZUEtsYFZ7k%b8oEz{E-fr%DHo9b%|7^OOg&U85ogoU2ial(eO0WTE& zKNh0p_P`Zvp(zO#n(8NGI8Lq&qua)w)1sKajbLG zIL8L=WPIrw58T-p=~@rm#aQV&58PGH3k9Zo;6gn$6qw?d1W#GIkyFc~j zxi88Cep$!487SoXyvUEun{M=OLi~OBBt&M51W@n$6i%*_K~yZ2}hMIsFx|! zFfDK!v#=_Gh1>mPaK~{SZyJ8sJj{UxZYPR5Rs(i&RdSU^QdjI11};8w~k+PB>7)LB>Bci#e>VbtmnPd;myN4 zMlHHimU)xQ^Kda00?9roGrSpxW&WPCt5GcT4-!Sk+b>acydNcswf-lGVx|9CqFCn- zNEEC5L5X(Pvn7E;5>;~zs(bK@2QJX_Q-NPSa3?)S75L4%>~DSGv}V?eXzn?4b=38yei%1{yhVW)6B6(J|!^ArD$ zlWCnIwzzTX(f4=`Y-hD`Ifadw0e@<_dWhL{!J2Tz)hIeevP97-QY4B_(Nv=76sZzL zrwCfqu%S*{1VR!u3)_J-i9)YL#erswYP;KRU2_%)ySFa?VAS#LKa?F*VRsJ1t+)Y7 zPq6z@eloG+Jne8-W#xpD5gWpDJ`${E?EnP|#5N9Rg5BY=ZM1t9XIG5y zSWV4I2HHxrlZgWD7}fRxtD#@EXMwQK#fyX2?#}KtMwCFpFBUA!g12A zUyi$E(w#3YctBb|E5qfNHcB4jhdoYcontw(fT3-UvzW1h9ugccQ5+JSAW^ey6*y6% zT}n?{M$g->?lpjZethx6Px&gjP3)hPC!izJG@=k5~4-t%b| zH5}=l$?1%0`+%pSPoBX7VV^g8EnZUkR>32p1i~lPOI5nl(2MQUJHbB1elmsQ{N!+* z?Qzfk$4_hb@?|3Rtb?FHb+(A@QwH{_WBZhIb~TFjsgNkzr;kNlb+%HXSZAvk#X5_V z_JO`q&_#9Cbw8}16hQRB5nDA2ghk`Ubq8;$I`iLlx?x92J?o_{TFVx#OR(qwKN-() zp0gIcWy`0TNB^Gx?zJDMK2;N4VHq= zY^5Pm0I>qCG?WFxO4nECOn-0N(_KV4gx{%m2(^`lvz5+Duu`L+4B|K{1mm#ws*>M( zR(yKw7Lj^(d({@ga}j)6G5z9TOx^yY#tP||(7+!sxWG$|6w>YTLad^px>}FZ(s_9y z7}NWRV=>idPfO?Jg`m0}twzt)rSsYXP7|vjoPIffs!ZS8rl#!Ey$gvjSDuz`7ZOXW z`^D?)oFtfUOSdbDvAzxZZUzADN@7`ciC&;e=XFFVH+TpdXWV)3HtslOlQfPw>7b3H z%nmo(UX63<>C-5;W*x9i`ZZ);HT%cOewz2Vv*+wCGo{U&pv`&LVftA?xXl!8ZkN^c zEhF0Iys8$&`_)wJNgqj>2o4rTA7ycCbY4&k_EDeGHs{4OxW5N5ZE{{m3##Tw_k`2W zqWk%d5uBUh^qBay-21uGv--~Vikw``SRGHVs-t# z{1)@~6kk*=vp>jw$2dnG-MN&Yp7D2F3qqzcGwOx6<*CME|CTUQYkf^VyEl7D)oFbYCmb&u#5-3dc z?4;sHPuYCKr=loqA}9))sD@0`pOPUH)si*D{XU0RU01&6&5>y$U30%row&s?Z;ra& z2k$V6c9Y>Xrfzvum{y3X9|A$PDL!F3N|9v$|~^BneUm$!&=DefVR zcOH9p)#Sl{%d8)!gzY_qc~`jaA!T^8lm+5CbmYL6AFACN`)T%l41i>mDxX?c9zr>eX53c|dL zIWvH(hy+_O((fX%#B5PH`&bB!y|43P0O>CQPWPSW#c@15=+NZ-JmRI zMICpwTi?u>`f(@IY_AX?46s$?T1lX2c~1VW^`H};XuUxcg<2j}6m+)R$V96s8EScM zCu@lF6kF<37Jk=ZX|_n$oTq?DVqf#hi(%(LT_T!icXz@~SgPyT2(Rn*F%`I;KCIrZ zGPvrY^9_Cnpi<7>+D)-(rqHrJHp-AMs6O<`seyf2z}7X=9g zLx$8IWPdd8Zpyg5C@d+Ox0W)el%b=elmpScd#IygulH&a&0FVI)>r>2_2g*Yy;8up zljW^<3-}(grqMh;ZKJ*myNgvqsnNU*Zhd<_S>F9rMU}d0+mwDNn)d)Tf(EDS$?_hg zaHI1Nv!DL_X3@Nd?Db@I_Ik3shsn3ae&)qzUbf@*Z7ZU3KQpn^QPJcKgFkFE4?Q?O zK6C!n_bQyXKbxD2VtrggqUTiCpikLAeb_Snc`9$PVh}thq1-P01;RwfcSVPWo>$*J zf0;<%bbNLCruwDt#Ojy+GNod?u1)$Yltb8yYqOnw^>ME~@a^8EBH8R)K_L#w+EK;h zLAaL^UdM#hnRMRM6s(B%snJ^{(|JRaDqb8O41^k&zJ>CDRafm-PJfcYK5C?4MpC?w zNtAiYiki+#h95dxWRAZ`)vVx8%Oi{uCE}@#YMw!|^8Hh<4 zebA?5aVx_vB3Lp|&nV6!Gzo#9gP_3*)E8{z^ED)8u z+p1XB(4rGQ5ZTnvUAVJ}W|+-pnBy@+ZeVT-mDq9STQeMdapS_b4}G{tq@T42%>XZL z>eub!PIA-0{FG)c8~CDu1u4W)$ZG-c27ffLFs1g!KFiO3`RC(9uH337F%S(bN};le z#_zGBLHBn4@RbW?<44&vjo&Pr|CB|($8O6SD*NDBb9DaW&>)mm4Fpn{#|iK#Np&?m zTW>^85XSp~i2<%u$W#!}%NX@AbvX;fiye2=?cVy!of8X$CBq}UIYFwfpqEJkQ#>z| zL;_O-R4T{05`K>!+x3%A0~P09D;MLlrkM|vmGpr)%;mg3DOJrBbTqCyJIPx>xUw-Y zhfz-f=dwUd>|M38cJuBFUOp}YU*tGrCiaHJ@%vc1`TW4d0?&ISIe~>qR1n8mW=pql z-`3BsJ@(h%MCw^8UI1Ib8I;cM?Kx4?2xsZkSUGSK6QalkWh~ z$^y|4osd2BpZVpnyG72hA>y22!8>YB>#7Zcfg+14Tfn5ba{ca%YFj{~jEf4V zu|U}3shyL{-kq@I5s_J!Ep%ql7CqP&JriuvD?r5-TM_Q-K4wI6#q4z=d9xKkI|28~ zVOhQ;kgA$!e1oNw^P3v4u7Y>swF8t{)a3x>jCvfPf(63yZ~3S1q_NA#nU?ipkIKB=Qtk#y;!Y>^#6132lL;Q{AYg*3iT!6^xP3j?&BJUB-?2n z!=@T(CEMwo+IVHXYI5O*rE)#sO72TdK#*j5rZl-9<0_%fdP8|~HG?XVT4+HB>&>Fc zH7ux$l~wCY1N27GWS;F2BbIiz>^SZF+g|%!SWb^vux!dzd@0ETupgDo=jm|7k__KB z<^g-yepK@xXS}n#ZI4Suy4h+6v`*JFgTAK8g~8JLn6`o1|D0^+9P29M&`7BH=VUwO zsEed${FCj3BN;$X`X{?)8wXV=kuk2FYOI812px6Qk&d)vo^Di~Q;0?CJV#n`4{OCr zIC!RybEGBrWK=$Ko!pBAqKmpKx9^Dq&$;_wy5+_OXxb7oZ7HRKUDV_0MPF<%)O>pjThHs` zaL@sY+``uK`dEpc!DwOYw`o?A)la!@o5d7$9Y%{<%BX%cLGKc3QOB5RO4Ro97WUL^ zJzVIe#$heEk_YR}VbHV|JgWk4AKPL+dfJ4m-&)?`ZBfizm{8NjG!EWkAlj}4GiYp= z)nYK2$#K57iS}4E_?`Q|J*JmPH2X)DXk}>y9|;M;oNZaWYN&cA70MBsA_@nub3*tG zxn^v&F1&22bnSGlv7!pKA)c&lT0dB&s}BpPK~sn)Z1MCGB&~6tt<^XjD>Ngi5YN?W z9G0z7-!)kqx8>c{`nk~`Z+Kt!@Qn-V@|ubkqN&=@Od3F;3x;Nq#l(jA7p|RHFnxOQ zIns=3TB5$HhFXahg~94LtT90Y(SjS_rZomqWo*H%uOR-y11F69wDHpWMB;{cNZjPO z#py)+88XLNEqYMq9OrIph>O!3pRT>Q!+4Qs);g8rnph`jpWPkk%acgjJxVS(sm9lk&1&znb%m(%OIljX{&F+$)f zKHhS*=XgsvFfEyiEV?tV|Mb#LpA7qawXj3>aAk+O7{1>Kt;gtKJ-pafsb`B?oJ-{n z*2POJ^=wg#^9X|%^5DnV`aZni)cg8gvS5)&UB4%)Q^!hsK5@r0^v2t=TU{>)X0pYtijx}?Vt?!e? z$)19BbCY4O*i)c+Vmrg$t*1cqwsyveJ}Q<1&7;~GCkaqD9cdXS3(!2HopFi)&HLFI zrwXu}?&4)c8BBo>710@>j1B_tPG^5IItm;%p5mdOi~=cuw$wCi8TP_Y^@RdB&5iy;5ehef6#4vOgO53?BLftb#62$Bobz-UPgE7 znq-{j>6#pyak`H@0A5YDZV|tt^}e<{&-+KZ#glHgC@8G2?OfpYi=Nsq3JQ&5xb8et zHtMENm1VfDJyU3r?yY9HEy$Ci0L(Ix3m1u!JIhIi-QP|?Ebju~$ z+4x5Vql$}8u+IujZZAR8g0Ac#mGT#`y%m2^B?aBsL;6ZV5qn5KDd^4~V()uWAMf0e zJ;Yx5qy+`+A@Q_cjzJm*hOL<7db8??jvu2GZ9Jb zh+Q8a_VE>4{*-;5tm8m|9TAo{OW++%Jm{1GM^m6=W~wK{budLyu7|-Hu45^R8QqJ` za2-lfhSB4m4A+qq0K4dZVutHL3V>a8Pcg%F90kBaJr2rn9Yz5VXoK!vhU+K_fJJ&U zPKG^+qB7qdx-g(=PoXFfS`5|I%$URb%rpv~snEF+?W7k2GUiFNvtA9zxIvq6A%(+4V16=T(%Tt1`V7xX!C6L7}p~ z7P!uhcSVC1+$sc68}ZJ9jN7CDY9sz)6$>0^gsqK( z4xjq`CHI}wMb<`DUA@%=tKuEB*Dzy^XRl#?#+`nubs~s6HS<5L8h6<};u|)I7l1Jm zg7`pp5Ff;ilJ;EFR1X#)2Js;R#2`LYfEdK>%PuNS4C2FtCI<200>mJG7K4g18^rB1 zFABFoe1y<<1@VzmV1xK5DX>BOY$>oo{2VE;L433n*dTr`3q%m#zi-m1Yin*_D+mj7 z5Eq1@Ta4uv`g~6deQd@BKJowo<@r54?mESxRAlEpz>eZ>X>YNW@DAntkwL1|+U zcRhrlPz>Uia9OnzVGzGmpwNWqAU;8&7{n(^6odF>62%~XIitEt+aNwk3TzOcECn`* z+hg!LDI3J?5qK@ILEIjH*8&^F?a_B7a0PLD>|G0N5VuF(MG!B$e`osevj=`FxU)fA za)&N*ExX8d9v3+-W4e#LK?LywQz};^_dfrS_>2wW>NB1ozSbSY@8LGjv>R$JJ7b*y zF^JzQKn&vR1&BfXJ^^A7-ylE?;`a*>gZKji#325l05OO^BtQz{4@(q-_#+a9&vlQ4M{)80RAihNiTtWOvDX>9&s}$HE{*)Bh zApW!z*dV@53TzPHE(JD-?~no;#GjD@8^oWL0vp7i69QKde_je~5PyLMB8dM`5Zhn- z$b?%&H3@SNcU2RtiaR-oznl=nU-46|6G8m>cH!jiZ{65Ne8UFuPT(I2L41}wh})YY zTtVF45}`m0;;zRR0K_0}-(FCf7{upso2fty;x`BogZO*_Vh~@zpmJ{;#1{(O2JuA# zcLnhqrN9R9#Zq8{_!23wLHs5uut9vO6xblXj0GZy556k&@be>PwH1WfAT9_)w^+d~ z^h!?)eQd@pKJow{XqV_y29{E^}-Hi)aQBnI(SB8cD4`PYttL437DF^JzGQ4Hd1 z1WG~tPKja=ze}PR#P60U2621MuJRApNcJ;fQ-B!6-x44O@wWwtLHr#7Vi12AdiyFbv>!)gLg7 z-*&|xFbv;zxgRi$-gc!QFbv*yogXla-Mq@*6fhgQd5vGeHgfYhBL%wxcQMWRYuv`| z5`o*W&5Qq9-$v~+p>KmWA3xIiHfC3lzBt3vtL}odUvrwx6!hedbj)Oopa*@R3fEII z`pUJtV>0>?*N(H+IzZn?7WSJub)wuzl6|ks0TQEif6X>do7?qjWk`(GcEMVK7^>}p zwE{6x+a+rNDNysGwRRzl)AkI2(!?-r4*)0-qcrdQS2lJ9XXU^ZZWEu#Iu;b@6P~!d3H$SEqesT$ z+^KNI<;?=bxcr0wF)nWrAjah<1&DEZs{k=BKP5nn%TEgsr}X=g z;u9Q}yFvaF!tyfJ0%BNRP7R1|eoa`u*^S|7d4(Ipu)NZZVOYM!jbT{6)s10TzRitc zSYAb#YK(1IzTFMmu)Nw0yTbAv0=Hp#jlgYKzEj{fEZ-$?86ZCLc7WAMG+)FL-df5^mlW`w$EyD7QMYUi5Q1b3{@dXac>I;cs`2o!~hUEt- z;~K=U{D17dcU+W5*DyTSHp(KnAc7rTjC~OVYmCwqjD-L;EQk~(A|S=yVtO^nZF(>E zJBewgnI6-7@4ffl6W?>DpIyA4yubH(zTfx9v%1T5%AA=wQ_h@o%{A9Pf|O?YMuL>y z@=Z2UndO@aQkvyk2vVBmTM1Hn%lj2F%q-tV@Ww3PPVmMo-$C%kEZ<4+#w_1O@Ww13 zu<@2zzMJ5US-wZ%$!u`U{NJuU^I)H!NK0w6Oj}BJhWk}#cz||>{>cxjb|+@J_ukgr zx{DrJO|sD5GG-BGmVI^>j2vY#NOS&kz}X_h+?q%_O% z1S!pO0zpc%+?gPiSq@OFG|Pz;E6s8e#Y(f>g<_>yPNrCCmb+>!8V)Opok9u5ET>X} zG0WX3!I_%G|Nvb95u_&*l1&xpS97JS$>Y-jah!4;Eh>+f#8iJ&jahzK;fYzk zDEp?G?oS<#^`+U#tZ6pV6mNAD&v-~!1 zZE2R@Q3dBnX_nt5NNJYeBS>kM-?x#SkkTxFM3B-ff2@#UX899>H)i=$ zf;VRQGlDl}`E!CdX88+(H)i=u8*iEAuL$0l<*yZ<%m%-0zpKBeXzdH6rLG|M>zDb4aof|O=?6hTU}JenYtSsp{N(kzdqSZS8WQLHq}M^dab z%i}3ln&qQ3Hq0zfpaf%6$I=kZCw(*Tvfs`-@*$FoHrkj=n9-hP8|~S8jjdmqLN~67qAeGUsqF8CP7gMY>+SL>*jdl&iN~2v%vC?SQX>6F$ zUP1}RXfLG%W3=lj!5Hmh3BfYj%P7GZ?FLFPMteCW7^B@t3C3tQQGzkr&6Hq__6kZc zM!SU)jL~kT1Y@+@2*EPi?UZ1Q_DW44Mtk*9U0y!e`L`d*DAB&OHA>__)bH*}4u5x7 zzvOi;HRc#w4YR%60y2L^Ue2*ebtjT6Qq}!AQ5LECHpm+oP5wN>D_0W#@-*cL7AU?pz@X#i&w{BB`1U(gVi&+vs=}H zvF^qM4Y=lu#^h6y=xIPHy`%|(Bj(^tR{iAX&#oB0<3-f%7u^~hn1FzC3n$t;JyuvL-fg^Q zXPj&p7!h8*Gme~AoOtYGWl~9gYY80ynOM78{b2^{~%Jl;>LH7AjR8% zd=C?(cA>Nx~!IJ&m~By+J6zGRP8o`l&U?CAf;;0H%Ow|3v9fl+6xWd zQtd?=OH{k>m}?en?DETNr1t!^t-NDl?WJlj)vCQri&Cn++@-Y0*x%48r4c%5-szY3 zzUsDfiSQH$=jsZ(%iaWUYk>pC`7u*BYvHI?K1KU(F}N9UTsS|K>{f#lT7hlL*s=D9 z=- z*}J9tiB~TsWmdzld@4v*!*8MPBF6hr!*7vG)txA0$>j;o+h;v{1`%#6Bu^`(8WqAv zg;a>;bx49#h~;<)f>Ma_J*22CsSx9PDD#gBF^&gO$U`5zFy;5_zgdogAO3)qwg9{eR=%01{y3&c@Y?R57F8f!-ouiG{QGlcRw5lJbdLF zXK=E&@O_v*E50iG1V2#5XGK`0GWpZ!J`-bAD&vRB_$CvA#@nRC@lZ_Rvmz_$?H&(#jQiO@vlQ-TEuX*Q^J*EGq_ow(9@5?Jh zapl~StyN*-^gRM9x?E8nmyMn6uJobm-%1-u19o<9qkfEPuJl5%5a zoKIuSjNcifjhS&d)x0E(nejL!UK%swaLSG&jhXQ`b%(grf;MAbx3xX5E@luB;+IVY0a8fv4E(lIGc-a?Gho@*P z8I%nlTpi#3_UB2YqSEeLYbyOpXx|xHjvAC_x|FsU`^2bl=d=TJ@B8zC-9&QA=R$?0 z`Falfh;+n{wRoe%PYg~g@l%5%O8hJwFO~SYjklEeML1q6@k@iZI^tIvOO*IS)hla% zn|FT#sj5;UR8{uFZ*@QXPRmhB{NAPXMb`Y=rhK?%)|BccM6z7-gD&i~>5DELrqZ2y zNoRma=}x^&kaErc3PH*>|EmNk*Zi*$q+IjAZjh=S_&|Qc#tVIOcj`@pmz@)$2fnv7 zme|;5Q%6?bmpSkgQhRA*W$mSE-_@#pPm2<&?df~prL;&?n{eI@2~nFD(G`tRtv$-G zvQ>Mv&cIUbH3TVDdo4jq)ov$9soEU`DOJ1EAc<;s*?3E}yA9q_?H-LKsvWxF^)YL+ zHywQ#)mlUUI<4C4wJ4?98(d0@jGYJGl3c!wy{WMN(k&m*&`8RK+?}$maTnW7P1e$J z>Jz4%yMFs{(3*e-_ zP`@0twJFXJG8vrg=L+>3*#RvJX`WEOQ613uo3VVMexo~}!A(F{Fgnz4Ob4_aq{W8% zjU_aAt>rN@;dpUZFfP<@93kZw6~bF0W==z5e5jv3ESkJ^rZE5U$JZyEn?8tH?=~5s z)HEFR#74Qb{w_+I{b=iu68boL%2;5SSyCeOR}}4E>~w-RjDh0()%pgrAKqmJZYvhX z74p|OFMssFS^lqIdC@OA5THFFf336Pr#qi-9(cmh{`?}z9Ub!5IcH5h|JnD}b-UMJ zJPA&S6`JrbaRz?x{_L_pXDtMD@vK}fJTBy4>MUFD?pnI0lXTtl` z5g~tzqh7a$3ChZO76U{6R+0rSdm-z=A%B~b{7V1PFJ;HX3VtqrXvp90xEh@U1%KsV z$Hnt*84CGV+TxGVbr>G7hdLvx3kLLIw|De;=H)~p5fJx9~?qP+IRI+@0*?AJ(7+z zHK4>udmTobTohhe*X!fu+n&D`N1!?Q`z?TG!E4Mg0K}gwh0w&4v4|0`vGkcu%ZMy1 z&n+z%v39+48DD!j84q^%W8_BfT$Zm)h=F5{eR|(=?5u*qskw9U{T=+R9(v<)Y+=FV z!b!zb%c15d3(u?d>Fvv07EJ$mJ5cXkCO6bR99H&_- z-qJ|T4X>{dZ;*N0qRlAbf;<=kHM^B@ZiD`ag3NB^vU0(Ua`@`=Jtc>zC~rcixBr-$ zw1?D0sz}sCs^~+dBE3&psp#V?r8dZpvKQ|?zE{)f?g}C}r3O?qyC8phxxVA*Ip~WK z7=Ez4=V6~Jr;7K2FY0+jV@a^-g6vQJ%0JYrz{fwxGC- z-^lm8X|TdJp(pNni(;X7W9{G8SkiVY&VKFg+ywu3wDxmU5oO)q({+DeixG8C^?cw{ z)g<@2@BjPfs27t4&~d|W)Xy$}9UN*-@H~T+$1NSvSjuO$c)R7E(^%s46pxxWz5l-5 zXVS8x(<8Ewg?~{O{v|C(Iz673eX5*{t%QWK;YQs1=eZ9Szr31APFcex&o-}b@qFxy znFjBDJfCSSsnZJo%f3e^{qzXQnMa&v7huk^ zPG9OeeWm57I(_X^#b@k8Q>Wc|cQt(U=OyQ-=%?^5vjd(Oj$l4~U&!5_ z@EHbQ)pn1@(!DaCdo_VH_6=Q=idQD47m>VqV~f18vEhwn59l|RJs9@JvTmM-JgNeW z78buxO)(hoH`n)bMkW0Y1c363+{-`pH@;4);qUB1E#3CN^37V&AIdP;)iA#u}d8*bX7V!vB@Ftq)D3uZpUylo# zr)+sjNi5>=prCo$mJ>&-lo%8Wnx}4UViC8^LG$!2C(8DO4OhHL@o4v;c@Q^@g*Pl` zG0)_37TLC33N$ZgF^}hlvG7LbEapjF&LZ2HOOfa32hBsfVJy7CxfJvKE@zQ#&ZR)J za~AU`Zx{=2e9oeu>W$_svWdAAdES2TUe#RTEW9IdDfdwp*%!DJc?N&*{=>2GPQj%- zKv`tdb1Cv%{@{a$W8ocyOL>U0$UefQ$g}!`2M@=>I}4Zcuwo%o(w2ws-qQ1~fwz;1 zqYv6tJ#mOxDX3m19eiB*@?tU9Gx&s>eHg1Z4*B~Fo(XvWoOX~%PHg}NDLG5cwZW(1 zk(S@?6T2p|W|%AaFJ1UYDy{TwSo$U(E*=U5R#4(j#3$ZeFEX!MhcvEqff zxik1$E2y7Tl=!?EVtUa}D#qqd&C9HWR^WSu7KAwVA4A_bp9jF+GYV&isDy9m*R`0{B?f~J6X740T) z8ZRfQLfSRD3Pww^E)KU zHF^Oh(lvTvheWwXpQMOlq1n+Iee&U0%o@FjvUIdYFFqWLS))&(EFG=Uk3JlWS))&- zEFG=UryY*PtkI`amX6lw`WcABuhI1r5rUcA>%h>B?jXwSF18XO3*&8;D-;!%|7{+Feep1*P{bW^Cg_mpe zQ^N6bjee?)x7O&Vh2!NK{q%6WT%(^6j+blnGd12`hRZejSsfDP8hvXRQ7u^c8vX1J ziE@d4P8d-wRQU@1+zyFyf&Q;BqFSKx_4&3AiE?>ZmcUDEvl;Clu`F6v!e>zU>AkG?KF%o(eSD2Tjka=E^1az)r(lfIrSJ*rlWoocEYw`1F>QJ>YmORAcB z2G2p=F>#_3_sZMue%LjT_-|FU*g3NcrWQ_zh!fn#O}x&aCzW!v19$xruh(eo>2PZn zobSXN6q3B9{p@qwlAGH6G|lryv)%Oz;Lw)B`bg&ZOeWJUWwjg~~8?4hA7$0~+(g zmW;$J4W26mHrt{?t}_6m zP#W2(geZ;dQk7>6+f;_iuDSQhxh?)b22+h}MUBAjnoM)IH+`i2PO?A9F!udhV=mlGx4`R)j<7099_rPsP_9*MQ5uzk%}&v z@YF>Kf4>_RK~gQ6ZB?{_wCFtDcvg$f*GSr;3pCzp(S-_0Dw=!wuA0XWPP($=7RB<& zimKPiq-(EFRkT{wiBvRZ|FZ0Z2NO>rf_01LSQV`!6*c~yRZ-*H(TW<^&Z?+(>qtdE zSUdH{`AeSpnv_R(T`Z5R=yKJf+I3SEZBlh&5K`8Y(FG4SA3E)V(1k>BYAi5dS3#*| z%paZJ5-;ZhSbwCqsu?2=kuYv>e+1y$)Bxjn=w^s_h0@zqf8=;*6~wzk=_^(9aXeH4 z@t#onDplJ!p+vxXL+Pv4P7ThT37ZFyJvx-GeJ)POl7yI0y7ss@VT2^ahSIgaMV2W~ zK6UnxY3a|W&}E8JkXWXi&$Q<9n|oYd`oUKENKxuVz)%5k)EP6%AwRhj(G?w-7OS=# z1*WU69Gf?7MgbTg*oPF*Q$aK)Eh(Np95?yk4VQqP5ELmBlW>xr6G#wwXduw`&V(Cy ziOmi|JUhZJ8Fm;~RG?gTn7~ZBWbG4}rE1972d3Hw{u=#8&rPdY8lbfB)Q^R5GcE#i z<(!6l%mNj<%DGdgRuq=b;JY&dW?BIBjOm5^*n)tW7iPk);{2JVh5W8cz|0G|rPB%v z_$`%yo)_e-h__M#COCv02v(aK`kh zb4zol$*p?OZ?21#*h)YT=eM;2W=&_&GWo5ofL_|!>BI?Qfql9ataRcavA~TT(ZqRT zftxy_iDShAdKGBrCr%d&+|p4xamZNUR!tLQoDYKi3K=aYL~-a+;5LP4412L$N4@#u zwkz4iv+2~;r&2VLtxMU{?^JDd7wzf&0tZyHFxJHcH9oJnJ7rd7+GN^RDZpUb3VM;+ z6$*{DO)CNMxuUgF@#P*#zv#x&5--l$7IzvnnlS^~+$P95@ zETY8p5D)%PV2diXCWzNt29A#)h;v8-Cqxj$VWfc*BM9O|(!fa(1aT~Bz=ZQusl?f& z0Ta(t1aUxVKnL`=^5L|=IAPm#Krfmnz{jkZ%Oz+!sHY|hiPu3rVh?-O*4=$%($XfP z&py%~qHwNH*;rduW1USKt54t@)h_UGx@oMR?prtV`Um>b^FdQTH;qN7hnH&+pw6LgPhEET%O8;(l>xP6bKe4LG)~n>KQAX1JN*LV zRpH5DDmTns)KXdXr$gkY;$bSFFIeP)y6jUK0~6(vF%F&-3FN9Ki!CXGu+EJ9qggcK z^E5smwiP29A1n#bm;uDO5UFDZVe`6<889{vN+X*$bpMHe)*krrO;X%G3nPjvCyFAa zjbhrqeFIZe#Tm2wg=gNH^U%k0-rPaN3x5H^VB!A4r^a9SOxM`*7d}@=FZchD<%HBoy`RN#=@v=cCUw&YV30mo6Q0!PHym+jZ|Tl2-h z+0@NUnT7Txt3!{W$ca&lA>%R>JF3(+QThy1IwVS`;ph&D(rcL7AyK*w(>f$dzhQcZ zMCmxp=#VHqhY~{+lR0-Cj?q{e+Ygj#0(n}fZ~wP{J7r6!+emxy^Jv4=D!ctmwcRQ( zD{Q+}zrbuqH46=$)iG825Y{QBs>`5c=|q^*N=d%bi^%C%vUDRxc1)Fi#Hfy`(vdKyo05E` zCo!huw9=Ir+c8!865~3iN@wE8j;Yd{7;mVe+uUa>tGxNx$$DLOGBR6g7N0@*GSwWut|`*3FsH9;iu5b`=;~^UbS%;$Dblm(8%dF_MZZXj z^euvs6zN=~YYJ}(<6ZPO1YS|%UL0YFbX_<=6Uaj9jmdGRt-bcj`-pCP^GHM%Ul`gB z#$ercL&DmwPhhB{nu)PrP21g@J@JoCmv7roRcMC$4BDBuO{J?7=l8>1UYTw}vDg4YTjokff(!cHA10bT!OgTSJn*hPBI97v4A< z))re$HQt8VXB(xd#@#TlW-wIaZ2sJD zH;`zT1g$(mM z-c@+wcf54`2fux><;8kZT;X?+;!16NpcddCQf>4Ne55K4%MdepB(3>6`tAKU{)>oD z9Rv)O)5^*xsfQ=x?ueZ_YZ4Dx#@(sP89R06Bp#@YyGx^{PvX(ZxC0tfF^PvH3g}Wa;#RNh8D|SaJ7jEV7C-u;L!j$Z3Um-(WTm z6vjQM(Uqko`OMQ9q&}on#2X?Ty+ZVd;|?lb67&D+?MKSK{%HGHqNzR@^B0;D4G{OJ zY=F4Olyn*Mk9%C{nz10Hl78h!{f@uwx`9vA6@2E(rurJjdKUjvrltnC&Blfr#@pIo-FoZH`SkFGU~B!7#@d>+>ZMgJ%<iS%%>( zKk(F;H>O`zO*wTrWRfVBZjxN|)9LOZ75iq>B=wD4^l-y>^T90zCobMi1B^X^4_@t= z*}t!&6lz zPSJ;?P-pik7%7Dilq2v@|m4$s-o_VOp%~d#FG?ntoVIR`dyy2ktuY1qu(zi#lF@xQxEvF z=`_ac5vTL;lN7A2^UT}ZGuK7t(N(8NCMmwUcg^*E&s$7;FVADRP61=jYLCg=XMA;M z(XS^*=5d5h0n?F{V&S)wew#gE^b3(G5_O6INm2da1O3iAbhSG&MV3whec#HXtG8dx z^`jrUCo)Ayr+`6grTFBDOYa^UH!v+SMK_%ym8Osl6?au<~fSYxmU+nY%_s zrts<%U|g&e`yb!D=aoI>4UsAQIz=o=G4kv#fB93}zKu*VK&OCt*2-h~HTS$9I_;FG z$P_(wiXMzv^WwW-HJ=_ttgLPrBj%bW2-8;Zv&XL9c}=g;r%@#-*%3;*{LfDlwzi(! zn`D4WfNl=JV%6mdEQwQRS3vS8DjV;7zunIc`M2$23hXUM3Pe?H{%N2chkQ&3yD z=$lR(DsJz7dt{1eodOzvFw-rQz1Ck-U4M5sl7e^NG~OdUUWStkOpW;aVe;J%4JpWo zNdrLdwV{1jCX2FHlzUIiD|zJWUClIET|-k9tUW#Udi>Po53I~Q_cZ#{OR%P?eQ`rA z+?BEy&EvPe|IooVzx;&?#X_eUeyf`wdgr2zi&~=UcsI|1`EDarVuTtKqMKWu!GNXh zr{B=(P2%DedqSF$Vh^C>UP``n?Z&5famnjpUgVP1lq4iugW=AYWuH#|^Q%}c`FmId zAbYRo`o{XU%DP4v44s`}+MTc}aB?qp@`h8{6+9c2ZiJGSj^b?noc+eXhkR1t6?Ry$ zyK(id1VM@%0A<^*Se+g`?cOaL0L!uze~-}sdHbHe@<;a^{|nwhV~YJJ^8gT zs{QLOdiU9TNy3CQC6A2+5i*Z2Cd}wtdUM59gtgbws>Ygz+7?myF3uPw(AM!K-yHMm zXE%TS7p=UK7g71bd%6yPY|d-KOsdN8$}2%o1glNXD0=(38<(C~Ned<>sLYW#L3wkP zw_{IG7xma0eDc=hmuNbipm?feU#^mDSLTxg_r~3I<+?LzWt6OluBfz5GD%2NUZXAf z$<~!8&%NxUlc;1RK&Z*;Xin3~F}ni_DR1Fnf`3XE%MZ!M+FHJ2HsH!rNHR!5 z-R}S3r(InGq?o<(XOzr^JNo%EN()$&t4I~lwn;aw8U9P`UvEB05^@XUQ!@KO4OYTe zj+Hkr&dNX7-94V9NL>RAyqaxQI3-4Rc1??i8dr*vcXG{8y(q4+eL3o)73<@4a+PR; zLb{S%$EaeF!EpBCn7=-5*nAPmSyZw-H*abobGu4a>Fg$7`}W0^dtMpzENyZnEnRM~DL!>xI>Qq)0uk3pH_(!kU`v^@XEDtXyUmtgIZO|)StBMW2 z*Y+LU`}$IvSXYrJ?d~3@@~}&rcvVvMn#wZ^Xwrt-#wBe_d1*_Oa9c4CeY(Hr(5pYF z;;Ck;1}P~ooiuZLKI`lnsuwO+cysdFv@r>1EH5O9df-aLtHXHqKwmX_-@>!T^tyuZ zC!{GccJD20=>6k?A%8o(_p0)YP*O$jwT#l=^Lnki^82&vIr~aAFQ_sL_UTYAIR$?- zuE&?}u3YgkFUSRwz1uO!(Amk0uWDIR&77`Ip2{x{Fe`Dsb@g-dV(xA~okd>+-i+mn zFZl5BY4e^qdoGdKE4LIL2^r?(sr>8|N(@QC4Tnpabu=8-JlS+(=B_64Dg6 z&HC)M@H|}Ec(I;;L{=~%O@-HOP0u{<#jD;PdBewCb&7R_5)h&3@y^pP+_xpYnzAdw zg54@}>IHwixT$&fXS~cxdP16#VizRuyCWX_>+2nNP|0fc5R$EBZ5QzL_y-~be5LIS z^SaZSm%Rq?5ND^W%Y;3HzMhm9LfBpp^MnO}vlB+gG4?Is`Z$$N;Ux#Q4ZiV%{Rl@S zJS8k)XGr)rPq;)UL^vYhlVJ(j8hlX(l)`!5^~cK>X1#OdH<<`WB*fPW*hOXEdifiV zdpj36w_kI{_%U^R|HL;SMkD|Tn`gaj8Be&&Sv6($nDO@<`wPMm35SD!P7{-)>S5N5GHJx>LW2Sghryz3Um4(*5S#9G3TWx$GW|3T6p@QroG zBZw)Mde>&SPS|)kTqTuBZxwFdz(E@$-{7^ z(s-O>o+IG=mn^V@9M``GbgKkwKcetz-1=?NSJ}CNyp?u#0Jn$b*Y*v~zx5{yx8Sx9 zRr;Khpnh!7W@tYKU#x8p&}gjlAc9!qOvhUnS>VUj@yFNMHK_P5Ff9P-p zAO_V_z*TglgD~o7q2q0f)R8TuBc+r3ONVFVgaY~ zLRLEn^ZxI6*M}7nO0~&WMb0!X9Dr0PVJnw%hJ!Fl+2(jR=A6aZo&&b`0gWuTaJHQe!pL?bvfa$tx_jX%OwbXs zJkHr}a}Y+hXP`{jIN0fw_mhn>?gPeb%<~{zq8CfUbsl&bye~fKD(G&j2*$gp;q&`Pe}ibNShER)^&R z)8hh52#$lWOxK6?^L1f`SZk-x`5OztVxx>Tr~&aefeP@o#yIV}`oc9gL_;>f)fylp zDGk0pXCZ=^;&x|a_KA{|jcWG*J^O69=!_RT;UX0-M)pMLCV+auMNS|1VS}!LA4H+Z zYvJp2?ne;C_H>+$IoBZ9fXCtI5kMiw0nXLeK^WOaBHLY@?K@z52T;iJ1ZTU`K^WN{ zL$=2`TPmpcYd|5(OPuW)2VrD;5!qhkY!iU(5TKCd1J3q_gD|o|AJ~}lK4(LdinT|U z?>O7X4#LRxo#XJn7Yp53#d>qT<;flgGHM2se0vjC-0MOZlWlZ6CD8T>kV^F!X#1W7 zoZpXt3kO;tcDD?Gt!aBL9uIH9tH)7znp7l~K554ux0Pg#-R(yL13I*~J66 zF|2&c=Yu>|IiNRGQFvJ$g^z8ZaQ#XOFI`XJC0i(5cPfQzw^F#~JPKD|O5w#uWT=c_>H{hZ_T=>>QdmaTBi{K0OT=W?bRJ~a?_NRX#{}+I+hHk(w zPE{A@;KlDix&$v`U}RpcFxM%}EpUNqEPc?a*#{b7Y zwK1#@Z3ycF>%;oMy0AX5HmnbwZ(JP0G(jmS2Fv;6>USP^77inHzaAdGAWkZn9?>kftotBEXAINSXmgputLWGm)u zxxj`>K$ddO_M``4WP1+T$~fCnU~2+2vMk_iFMAM1wl|S&K4;qsY;Ax>mZhBSJrBaj z_6f2r;cWYXZ9Sloj(B$tIx91Qxwn8P;U-wWRyfVm|fS_53C0i-B+{V({k?91WzD&Wn&0WP-V#XWGb z6E7Zvi`{Sm&ql*nW%4v&XG11zGu#@6ugPQvAaTA@6ujn{4 zAoo@%_q*^latEIVYzaVCB%kwd1Tn=8T;A#oXI2Oxb@wg9nLippbqg%RDaiv+-6|XT zB8bnP4w%>BBIh0WfgxcPr3y$b@uE**U96&P1Gd#b#_onBpR)`>OtDT>4P4bT0a7<0 zJkG*@A-}wrkl`#us=8?b1x2d5WsrR_055>poR{E-oWd8l3P_JZp|Jf?5muo-0@mAs ztVllRBm^GA=g(?LM2?W)Rg`9^V z5gYs#{H%a9SQHeMV`o!8oxV1cFqC#fo$NbvcCfO{($UpuEVnk zt?cgu49*0K6y*$1w*?T5DJSVl?*d3sVY1l^po;xN7u^S-isZw{MP_y10Y)xTRrDXm z=1l;qn;I|)?6<(2Lwu-OMlNsw$fW^c1YX;0S70#q4xC@nJ|M~GOh6D*pwPb)nPX^}5G* z^2QvIHmd+WM|j$Uyp|0}_UYfpmr&iV>f7#;jRu zc}ZMCi5L+E>P|sjdPX=ML%~454d{J?-kANUi}*tL^}*(9-V7My^*ZiXfy0~gz>Quf z-sh6SF(3=1kC8O_fh)W*BPM$tNQvZ$VCuwnQtUlb58Hdn*0kogwKSLxgppGa`ZhGX zH}G)f&)yhUY-g``SG_AL^;fU60}js-1;bbo*1W7ukIS3rO#(6QW~>9Cz3yJ$d1HTo({vyuhzDiusi=TIkQDw`>=l3a{OR?h zR8NAplPfB5&z>DhR3~8AzyeUneEEfPw$6o8a^m+Oi1R6K z5a&&R?(T|C;HX5%4jbAP9q)<~0{6NS;$5i;uB1e--~IhYSAS>?_cjM=goX71QvxLT z#T&EJ>s=&%_kcLA(kRitFgyqb=AddnMMIxW z=6&h=AFxM#|NT6>%VA6o*v^i@u8lQ<%!M2|0bn!^7%r6zqA|mnFct?)du%4)u`|Lr z9I))yEF>2UzXA1rO$|$paW|kpDd}`rVYCg1FYCk=cE%WF1L}J^DWPI)4X9rtHGuV> z=k>!Sj3;acXc}jpo-r`M2E1Eh1ur%^=Z)$7eIzqR*MRv_&Wxh49pfu1*79pT$<600 z)@*5kheynzOThA0F0OB@tFLXSsa#%F-&k4Q+@5LX(z4BvPv@atZ$i_AryHC3|7V}} zI?bZkB8oR2F6&fTS-G!Ll=x^aykEz{;lbawtkHI{wxI;DB)3#o zR#x3!xo=VRzRD{17Uzb2Lfir_F1=%Mbv2dM%bTe{h61-cofhq@+_w+QwXY6-7Q?p+ zpvp>s@Uy52%8O=7gclB%L2G4A{Yshv2JYN9J6Pw+nyS0-59V|1&GMqM77)!m??sjS z{)O~Km5Xj%RC(i#aE0H>%4Lggys5GZz9Ma9y6^_bKnNbk1!J>y(9xP( zYAf;C4AX5flIC>^VbT%Fn|bo#@QYn)EbUTN?QO6*SS8ocQs9P<*M-3`7;FD_I(b}P zkNY(?8K&u&uHL?`xP;@qF;l$p?lrC`2hFwn>5VS0u}DfV_<;PuQGlkfSqST^fFi)~ojs{L25 z3&VLJ_9R&Eq;&Si*Ljnwy}h=36TvotvEEb-SMGRmmEbOLxgBqu%RSAT1m;5kV3_-T z;7zCjHej!*7YP#X6%`)9OV(RdINZgqU9A+1`dCa@!#o3<)$77w78LqrSj~9`h}MKQ z87i<@fSl`%`poN@H{aVW)9YF8?E$~Ag7iQx*bhCd5By@Qhxz=K4NcX{l*<3_c;^wh zVG|UQ>vdru$m`^Ly>h~UvSYZ(>l|gHFp%YSvPJboOe6@IV6l7C7KZ(+t$dP?N*ShgDx&{qoxX$v#n2-MajLum)u0 zU{CACCz&oCPcr|1VHnB_spk5ynJ{9m{|A)*&Lt_zFyMMp(PN5@3R zM*E|CMvsf05S<@A8C8QHw6HKXS<5*L6yn#gc zlx>FlP4E}#weVNr(HH9BnRU}X^VWMT;78%QtGt#W;tv?))O4}JK)l2!$O6`pUTk@yk|kG?wcpsaEWkM4Qr z4*1b0@2LLhjmJrTTi*l zKpe}Eo3yshmdST$Yud&lY=0$_Z;U<+jc<2842^GMJ`9a-O%9`V0T@3R6YfZd7!9_^ zyec0?fxALFQLl~VcG)rho1$qOX4*6i0Hens(ygD5G*t$4S3;832!C;|#1HyoL*TE> z>tqLdJ|7FGyB8;IctVc>B?p(ZX_9{t{Dnn`ljQdn0}h-?xb)+t8!zz!&Qoxuy5sTE z>t*=I=Lb^2Nrdqi)rq;ILM_j zBRL7Q;g0ruMKPe=2?BCUkqE!yNF@m1=!OWtpaa+)Z`<}r1|00k=n9%JHSDE9Uaj6K zB6BUe4?%#eG@R1<_GKAf*dYpk02NFJk$(SCaG8DtD~3$^hd?{14W5yILbt~FlP1QW zJkfv3ME}-_@!KZCzM&&Rn3du3PUu#gCi%R;$C(C1GKI4Y3}b=Zv>ZFXL6Lmnq6Qz9 z#TGQ=KXUP64>c@U_cJDTT7 z*Xf+nA1v93&Br->0A-&77pTh9Cc>nWgHXUZ6|YB%Yrvn0;HXn2W1_PS`z>VsU)-7} zK2pP~>Wo!QEz96oyXIEm6OO6LXsB8|taf$P^5%xx){M+y=$o_-t7)%l7zUIK8Un@W zXGVU>OnCES?le|joK`-qY(&;@?t`XHt#4db+mbf3v3_;h%B-AFW@c!3T0Wd;&{Dr- zXOpClW5$demNh(cbXqxN*_u`ikD9l%FRyKE!)rM90KCt+^fUpYh9r+Lek8ljA)#j<;I?-MVU448byFVW_*js@B?E zJino(cF7F>BsH5{Qaq!wtQP$LlKRGJ?W;N8^!DY8Yg-s7m@RK#UDDKA-&Wt$h}Uch z{#3WtHZVA11Vktm)!v_$KVPZaUaRd#>GvIHMKRx zGfLVU8rqv%CpEQXjv5K-5heK#T*HU|S6rwmIMkrMu}ugog%}8?SpuyiI{~uHQmUBU zQr}jK44_9uS`7?+LEcNnHkJ@8sBh()VVah(d>%w;Z>cSxHb-=(@|ODLyhi|cNkap_ zEU9g&Z(ds4Qq_=;+HO@6BJgFka4dly3aqrYp%%K6L6p_D;0=TV$hoa{c{8gjp3<nyOY zt*OQW;g&)T*K#flBTzVRc^FwdHmmr?C8v~V{+2jKja=W zYHa54(do>(cOz{=^~%lxkk->&JaAw9}eA0hv5O;>S2N}rXe@>lT$N`Ft&pWfV2{Z@h- zDax1>CKGfOKcVy}2>l59tDC8OQO?<#uF_#$ zML)`cD~!15g&uW+FhLr8#bl_MscU3-aAFMS5zdg|!AVl_P&W#BuqZIGSUi?~U`96ZB-bFN~r+&*Lwg~iENF<@b}Gl(n=P)soo;{hi}00x}}WMj(! zFm4q180h^i0Dgj0e%xlr#So^VU)JAkql|BcheQ}w9~o z@YV3J1&;p@o|y30@IZzCic|P(c&5UC;)LBDl0kWFcq#%h2q~{hvdmLzCzSnnvitxYi34Y55!zcAEXAqyr$EJs(pd*4$+9L># z1%mjHwDBzPpf9cNP)3n@? z!RKX_GlLJsa)$;Vdqt-PpKCpgHw&8J1`E0;7_nmjIs(4j(LvHg__`R{$Ki0*AHM(4 zRgsPjBw)GlbuqM||Cch9yMsb{a3N@DtKbR?qMa1DW_{u7VrXaaE(<4X7n3`Yh6#;r zUIY{OLk$yJ+(;(wogz~ZzAlDlw;ZleV-fBV;P_E>FjazeJz25+XQu`ep?P#MG|A`K zi7dYZH&7v`WJT-z{$W_TFM_Q2mQxo)LtPJ7cpDg3GWE%s%=9+mac^i_<02 z4LL$@(H}Q+bA8@-2=xYcdtmK?<3lcC0QRzh2+NO~`S^QF3>?KhGXqDnLI7fS35*-= zP@)>}DN+2m;Z7!Y6!mdK>9D)0j~niQ9;*QO>t>zU3IfOT19cV34R@GNPypxe%&;e^ zkDCS9#R`DGZm9isgnxxe89r{7#BRU~4R>L85jdGWjPSGggZy3DD|qoP{ve#fKE;b~ z@dx2l_8Y$v3U|X2C>AgAj63+CwtI_93HM+b1nvpXS#px3_hN+v?hUU?u<3nRErHWm zJAwPMvk2UeT|(d>+eP4Xeq5T$!42K{0YX25;TdJ>E?Za5j63 zz&Y%D0*~YeJ(>EAV!cIIlJy(SvI#tfO(F1DR)H`a|A!wp8^`Ji{YbW&z~kA;1U`zL zPv8k`JAo&%TL_%X9wcxcd!E4g>^%Y(upa=%lN&_&3YizyYj_BxfG4pOfbldz0Z(Q} zAS^#_R>VdSxR^~O@Dw(Uz(=!12*b&Z_;JH*(F8D_z# zqCRd`!mcOqF>vmPqN4m#_Besd*sBCCXCD)ICi{`Vv+(5@`r~G^SyuwjVS@=gmyITH z1)D_Rd90kk^VwnoFJR3CUdV8Ps6K91$<83~B6cx>tJp3AFJ}7*T+JRLaE)qOo`oBB zFuhOcb?iF=!^=W^sx+wIrK~f7>sfCCAIpXkco~~O;0AUKzl&|BHV1a4!m6S$pyM&Om~R|2nMQQ&>3j~lF0 zcLJ|r!w9^VjVJIrb_{{nvpNEAV66n+$Tkyr6T@>Z)W^*>^C#L3d>q?F=v&x+0w2#F zB=8CBSpuKP-Xicx>?;DF%zi_-S>))3h?FN<<&N!lD(g(((^xM8pUwso_zads;4|3- z0-wc>Ch%4^o4{wY8iY5i@|?pO5ZDOlMU z1*k!)aPyBEOn27!RPd`SB248y+rgtdfsM z-YPoj@2)f1Ibr?tN`POxMew^^=dv9Dzh}Y!2KXZjz6s#3E%~06${E&jS3U1-}gNOBVbVz^_~IhX8+K!CwIUg#}~8=6ehN4d7oa7&kShKx`X7 zSl=js$60VZz!NPv8Q=#kxF^7mT5u5HKP-4Kz<*hACct>l1V3)b59gcr(K+L=m~Zf8 zIRT6Iuh9KJZ2obb&F8Os4oUk3?KukMs}IgM*q(`UK2q&@j|F3UK48Jvo~btq3CNG_ ziHH5+2VrbaJo8V%*q(UwpMtSH2U;+;XUKxFJ@JG<#gFYd&4RH#=U6bdAD$+t__2L$ z7~At$i;nHtWWm^;7h5p4=k*qh?YZBAu{}SuU~JDXEEwDKdkZcG_%{nK0r-#w&j$F2 zn@sr^0vxj7T7cUuxB=kR7TgN(9TvP6-~$$X9KiQm@F@VlVZmDge%pf22lz7!z6@YI z2vF(wT7dC9Kn3pw7>@;1@J#^svfw)a4qEVi0MEAIM*yy~;HLpzW5F*0yv2gw1o$Ki z{s7?9EckPPw_5Ob0AFaqzXE)*1s?);DM1@9^>z3{d%t^~I`z21fmC z@2p@^zTYkQUt#%Q8V2tQgKr6g?*(}0W+7jdcbkND33zgZZDj zSzwetPPbqz&lwhsc9+oJ~f@!mLols=EoP_WQvqm@67hxaWQ%hMcI zp2^nyaB5h2E)Iil1o-LADnBtlWMwK?ALU&HVI8Sbn%(!F&1m z!TRI+^E3;_^~zQY#`Vet7L4nai!2z|D_2=Cu2*ib;I|=vm7mh@YgrqiU5{`Ip3t8XrfESLGMu ze`1P)h5j$FVAS`Vu=+iZTNdDh>x06u@?(CumjypcpN}1-V3FVLmVDIb4;GC1T^N?1 zNGi8{MnY$L$ga#4ct)-d=AfQMT2+rrX63$R+$bO!tO zF2Zs=b%x;XHvr>vqF6?x{~iXz!$pK141-4jjPd;%_!EG5P9DM#&o1EbR5lG@jHlz0 zC;;)Kc}U0jCal>45WiW9FvQnAP=^4-ds+d;c)Z{*WXB;L;^Ffl#t?w`&lvz?ycDPO z0K~7ZL3%Ts^335=*dBx-Ub=|GP3$&=As#xB!!7I}z!+~A<(tNy1sLzwV37h4e|isK zwU;mv=Kt>jR(lB%cEDFwdkGOv23YMKM0gy)YL6kpGXPe52N7NXu-cP|@Cty{UPFY> z0$A-iMEDYb)m}w}Zva^BaYXnbfYqKwgg*yZ?P)~#Z-CL?$ND22l^|a105@Ve+y`K_ zXAtQF09Jb#5k3-NwHFcLDFCazhzQRCSnX*<7?0Uidl(U34zSv@i10dq)m}t|&jlF$ zku+JJ%K=tvBK!=%YVRb% zZvm|KU?Th}z-rGW!aoD7_HH5^1szlE=|s3Iz-61ojqpUUhdlsRpG5EChEOt;J{W*X=yF`%#U_ajl*k!@r0gUz^(<40q zYyE?e9;YNs-xXlAzhb<`vYr5={Z()}!1n_`!pJ`YV6@)~E&zBhz=@JR17Nim5$ih( zV4Sa2e)u>1gJlD}3-+nk)bb74EF?C*hgw(Fw^c7?A$WSDwvB~=2>Z`Mi(#KS{*0Ad z%R{(JzOt&NrD_eN#5aes5IikK?0Ka9PV*s+KQl9WMT4vQT+( z2rzZ+jn%AVW_jMsNs|go@oIKyad}~J!5lWZu)MS|w?JM>20&^CU{(wwFL*XhWhM|= z;fN98h-`x>sIRN5ZK-Xnt~I!l`r28w)otbYln<{&;qvyQYuCUjrwp$0rh)F%HJp$I z+xl7&>gXT1%3?7B4Z(M?KZgn-BZG`7zfN*$nOBXx0rkX#R#`6MTu}!JA z0sc6fVuLiT@bHdJhm_$cNFR;@DHIj<7#zujiSI0-~f`5 z_P_yFJ3Zq~vZponY}U%G$7`>5H#smnV~;lm&$=^SlXXt3h$HX=5L}QrM2bR$ls|wF zCxk#k;=%!O$_c?O-1xrt>Qzqz12z)Zn&} zY8=Gi(H5$zIj>Gnv$I80R^z7JUOH{e?bprKx_Ps1zFs%qNM;~T-dIY>DibhSed6j^ zsousU>z6Q67l4uaB^Up$izG}eEG-yTMn^o#~_h$2x#ktTJqc5c8qsG1c>1mZp5;M8q znjc{;?c%ITgXl=ew6#-(+d-}MJ16t)#q4l~+hr^kX^$pY`U~cjFqfsSyZc9}Xc(zr z7^xXB(zw2RaG3QeTIss%R=K|__gCfq&Y$h?o+ST!RTb;0>+q#^ds(Tq_C5wRD;{vY zst)A-elVM!Jspd%6K?rp96dWcu{dsWGm9VM77ye3?8WozxaZ4nSzIcS9W$|P9{jOu z>(_=|*_X2K$-Xc9RoUN^{p+%SL-udVzI#J|^ysc0-qqu~>Y%G0z^RsE)JIpHbk$3# zUNF5zNLgwlViT}Vn>`{_v{dhZPY% zdg`U8UV7@KuU`7Sa~Etg4q)^|C5n?&t-% zGfY?V>~v#xJUJKf%BQ$+?TlEvv~6mq9~^+)D{SgQ39~q*4>r5=!|k{4_O{<){Mk-* z|K6j;!<^Cj-FLRvc6Y~Xdk;qA&8^J`btdWh-NE|XNWW9;3?A(5Y!zFh@z&t2VzfOT z+}~Rp7B#BrXuCUpcd#=G;PJz?;ohJaJsj-Z8IB$mds`bJHrg%~=p?5~zrQ6*s3Qe- ziJ~fe(+_70WyqrS7Z6a@Sz6$IOBQ%H!GUeM1ePViBJc2GOS9^Fg2T@l} zk|sdeaIW^<2?(orm5|5q?7(_@<^bFVT=(70cL(Y~?ZMUt%zeDGKq+#pISo>*6fZnk z4s~OFFKQ-&nO|fqr1XRnMJi;VF7n$QvoKb0FpVg=MHlH2=pxovn{-9(c35Pjt0nf6 z&}MSYiIgD3qGTrWkfi-j!cYCkOada3bn1w%FrhB|b*=(Sk{2ncIl3q_omY zF|9ONLF;OwC3GG>d0kDkq=}IKlZh648=FoSvme^a7k_yzw4_ai6n zr%oI>>Yn!gD#r!RI+9|r^Y?3{M1Pmy$aVMNeh-}aF8&mYixJEFYmWPS%#IPmeUan- z6|-Z+aR141sRm0pa_sFG#d=HMiIuDKaCQ9H(iqo#}p$Eg7i?jKIvznwU0)_BUL zmW>BTjT;Y++BY5?HE}#RYL^hlagy^qGTz&uhF=@ksG(yxKA6fpgAA?;HXOBeA`bIX z#64;8N6j5i{iwy`!BL|pmW%l`mV3LUTx$1t{87`#gQM1u2S*Jc502VE9vn4;JUD6z zd2rMi^5CdFkH4Qeanwli_@j1`2S-gM4~|+(9vn58 zJUD7Id2rNhB2I>YO8;-1-?m_njIRLX@kfm(502VT9vn5HJh&1dt1Iiy@$d7m;7=HW z<&m>$ac2Gb8=a#1nxRr2xr;e&?PjO=B5*~CwmfngEzb0B-|G}Bxc6AV0W{ElJ4qQ^PzGh7c2$k_wF;iz3@arzkUbc#>1aoqfV)WChY*D3yjv}X881NVpT zb&4;o@)`K&4czbcJH=}){>WuTb=GEw@++_HE#fz=O&I-IB}C)3p*ZKK@0g_$SixK-_-; DRmOEl literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1_linkInfo.xml b/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1_linkInfo.xml new file mode 100644 index 0000000..e4b6fa2 --- /dev/null +++ b/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1_linkInfo.xml @@ -0,0 +1,6138 @@ + + + TMS320C2000 Linker Unix v25.11.0.LTS + Copyright (c) 1996-2018 Texas Instruments Incorporated + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/lnk2000 --tm_feedback=/var/tmp/TI0JbBTGQsv --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --buffer_diagnostics --ecc=off --map_file=gpio_bitfield_cpu1.map --stack_size=0x100 --warn_sections --search_path=/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib --search_path=/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include --reread_libs --diag_wrap=off --display_error_number --xml_link_info=gpio_bitfield_cpu1_linkInfo.xml --entry_point=code_start --rom_model --output_file=gpio_bitfield_cpu1.out ./F2837xD_GlobalVariableDefs.obj ./F2837xD_Gpio.obj ./F2837xD_SysCtrl.obj ./F2837xD_usDelay.obj ./gpio_bitfield_main_cpu1.obj ./device/F2837xD_CodeStartBranch.obj ./device/device.obj ../2837xD_RAM_lnk_cpu1.cmd ../F2837xD_Headers_nonBIOS_cpu1.cmd /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib --library=libc.a + 0x6a590eee + 0x0 + /Users/gmarx/lwc/workshops/f28379d/lab-examples/1-gpios-dual-lab/gpio_bitfield_cpu1/CPU1_RAM/gpio_bitfield_cpu1.out + + code_start +